diff --git a/.gitignore b/.gitignore index c248b611b..3d5660b7d 100644 --- a/.gitignore +++ b/.gitignore @@ -13,7 +13,6 @@ core-v-mini-mcu.upf tb/tb_util.svh hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv hw/core-v-mini-mcu/system_bus.sv -hw/system/x_heep_system.sv hw/system/pad_ring.sv tb/tb_util.svh hw/ip/power_manager/data/power_manager.hjson diff --git a/Makefile b/Makefile index 20f04ecbb..b8a68b9d0 100644 --- a/Makefile +++ b/Makefile @@ -14,9 +14,7 @@ mcu-gen: python util/mcu_gen.py --cfg mcu_cfg.hjson --outdir hw/core-v-mini-mcu/include --cpu $(CPU) --bus $(BUS) --memorybanks $(MEMORY_BANKS) --external_domains $(EXTERNAL_DOMAINS) --pkg-sv hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv.tpl python util/mcu_gen.py --cfg mcu_cfg.hjson --outdir hw/core-v-mini-mcu/ --memorybanks $(MEMORY_BANKS) --tpl-sv hw/core-v-mini-mcu/system_bus.sv.tpl python util/mcu_gen.py --cfg mcu_cfg.hjson --outdir tb/ --memorybanks $(MEMORY_BANKS) --tpl-sv tb/tb_util.svh.tpl - python util/mcu_gen.py --cfg mcu_cfg.hjson --outdir hw/system/ --tpl-sv hw/system/pad_ring.sv.tpl python util/mcu_gen.py --cfg mcu_cfg.hjson --outdir hw/core-v-mini-mcu/ --tpl-sv hw/core-v-mini-mcu/core_v_mini_mcu.sv.tpl - python util/mcu_gen.py --cfg mcu_cfg.hjson --outdir hw/system/ --tpl-sv hw/system/x_heep_system.sv.tpl python util/mcu_gen.py --cfg mcu_cfg.hjson --outdir sw/device/lib/runtime --cpu $(CPU) --memorybanks $(MEMORY_BANKS) --header-c sw/device/lib/runtime/core_v_mini_mcu.h.tpl python util/mcu_gen.py --cfg mcu_cfg.hjson --outdir sw/linker --memorybanks $(MEMORY_BANKS) --linker_script sw/linker/link.ld.tpl python util/mcu_gen.py --cfg mcu_cfg.hjson --outdir . --memorybanks $(MEMORY_BANKS) --pkg-sv ./core-v-mini-mcu.upf.tpl diff --git a/README.md b/README.md index cc122b364..6ff7aa583 100644 --- a/README.md +++ b/README.md @@ -115,6 +115,41 @@ If you want to see the vcd waveforms generated by the Verilator simulation, inst sudo apt install libcanberra-gtk-module libcanberra-gtk3-module sudo apt-get install -y gtkwave ``` +## Generate padframe + +First, to generate the padframe, you should have padrick, you can install the padrick by: + +``` +curl https://api.github.com/repos/pulp-platform/padrick/releases/latest \ + | grep "Padrick-x86_64.AppImage" \ + | cut -d : -f 2,3 \ + | tr -d \" \ + | wget -qi - +mv Padrick-x86_64.AppImage padrick +chmod a+x padrick +``` + +Then, go to the hw/system/padframe folder, here you can see a padframe.yml file, in which you can modify the configurations of the padframe, after that, you can generate the padframe by: + +``` +padrick generate rtl padframe.yml +``` + +This command will generate all the files of the new padframe. Now that your padframe IP is generated you can instantiate it within your design. The toplevel module for user instantiation is called .sv. The structs that make up the interface of this SystemVerilog module are defined in pkg_.sv. + +Correspondingly, you can also generate the driver by: + +``` +padrick generate driver -o ../../../sw/device/lib/drivers/padframe/ padframe.yml +``` +'-o' here defines the output folder. + +You can also use the following command to show the built-in helo +``` +padrick --help +``` + +To further know how to intergrate the generated padframe, please refer to https://padrick.readthedocs.io/en/latest/ ## Files are formatted with Verible diff --git a/core-v-mini-mcu.core b/core-v-mini-mcu.core index 1c0d6c818..b47ccaa20 100644 --- a/core-v-mini-mcu.core +++ b/core-v-mini-mcu.core @@ -14,6 +14,7 @@ filesets: - openhwgroup.org:ip:cv32e40p - openhwgroup.org:ip:cve2 - pulp-platform.org:ip:fpnew + - pulp-platform.org:ip:gpio - pulp-platform.org::common_cells - pulp-platform.org::cluster_interconnect - pulp-platform.org::riscv_dbg @@ -22,7 +23,6 @@ filesets: - lowrisc:ip:uart:0.1 - lowrisc:ip:rv_plic_example:0.1 - lowrisc:ip:rv_timer:0.1 - - lowrisc:ip:gpio:0.1 - lowrisc:ip:spi_host:1.0 - lowrisc:ip:i2c:0.1 - yosyshq:picorv32_spimemio:0-r1 @@ -58,10 +58,9 @@ filesets: x_heep_system: depend: - x-heep::packages - - x-heep:ip:pad_control + - x-heep:ip:padframe files: - hw/system/x_heep_system.sv - - hw/system/pad_ring.sv file_type: systemVerilogSource tb-utils: diff --git a/hw/core-v-mini-mcu/ao_peripheral_subsystem.sv b/hw/core-v-mini-mcu/ao_peripheral_subsystem.sv index 1ba744a35..05bc9f81b 100644 --- a/hw/core-v-mini-mcu/ao_peripheral_subsystem.sv +++ b/hw/core-v-mini-mcu/ao_peripheral_subsystem.sv @@ -337,8 +337,8 @@ module ao_peripheral_subsystem .dma_intr_o ); - assign pad_req_o = ao_peripheral_slv_req[core_v_mini_mcu_pkg::PAD_CONTROL_IDX]; - assign ao_peripheral_slv_rsp[core_v_mini_mcu_pkg::PAD_CONTROL_IDX] = pad_resp_i; + assign pad_req_o = ao_peripheral_slv_req[core_v_mini_mcu_pkg::PADFRAME_IDX]; + assign ao_peripheral_slv_rsp[core_v_mini_mcu_pkg::PADFRAME_IDX] = pad_resp_i; fast_intr_ctrl #( .reg_req_t(reg_pkg::reg_req_t), @@ -352,32 +352,19 @@ module ao_peripheral_subsystem .fast_intr_o ); - reg_to_tlul #( - .req_t(reg_pkg::reg_req_t), - .rsp_t(reg_pkg::reg_rsp_t), - .tl_h2d_t(tlul_pkg::tl_h2d_t), - .tl_d2h_t(tlul_pkg::tl_d2h_t), - .tl_a_user_t(tlul_pkg::tl_a_user_t), - .tl_a_op_e(tlul_pkg::tl_a_op_e), - .TL_A_USER_DEFAULT(tlul_pkg::TL_A_USER_DEFAULT), - .PutFullData(tlul_pkg::PutFullData), - .Get(tlul_pkg::Get) - ) reg_to_tlul_gpio_ao_i ( - .tl_o(gpio_tl_h2d), - .tl_i(gpio_tl_d2h), - .reg_req_i(ao_peripheral_slv_req[core_v_mini_mcu_pkg::GPIO_AO_IDX]), - .reg_rsp_o(ao_peripheral_slv_rsp[core_v_mini_mcu_pkg::GPIO_AO_IDX]) - ); - - gpio gpio_ao_i ( + gpio #( + .reg_req_t(reg_pkg::reg_req_t), + .reg_rsp_t(reg_pkg::reg_rsp_t) + ) gpio_ao_i ( .clk_i, .rst_ni, - .tl_i(gpio_tl_h2d), - .tl_o(gpio_tl_d2h), - .cio_gpio_i({24'b0, cio_gpio_i}), - .cio_gpio_o({cio_gpio_unused, cio_gpio_o}), - .cio_gpio_en_o({cio_gpio_en_unused, cio_gpio_en_o}), - .intr_gpio_o({intr_gpio_unused, intr_gpio_o}) + .reg_req_i(ao_peripheral_slv_req[core_v_mini_mcu_pkg::GPIO_AO_IDX]), + .reg_rsp_o(ao_peripheral_slv_rsp[core_v_mini_mcu_pkg::GPIO_AO_IDX]), + .gpio_in({24'b0, cio_gpio_i}), + .gpio_out({cio_gpio_unused, cio_gpio_o}), + .gpio_tx_en_o({cio_gpio_en_unused, cio_gpio_en_o}), + .gpio_in_sync_o(), + .interrupt_o({intr_gpio_unused, intr_gpio_o}) ); reg_to_tlul #( diff --git a/hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv.tpl b/hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv.tpl index 6ea2b842f..ad57038ec 100644 --- a/hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv.tpl +++ b/hw/core-v-mini-mcu/include/core_v_mini_mcu_pkg.sv.tpl @@ -154,10 +154,10 @@ package core_v_mini_mcu_pkg; localparam logic[31:0] EXT_PERIPH_END_ADDRESS = EXT_PERIPH_START_ADDRESS + EXT_PERIPH_SIZE; localparam logic[31:0] EXT_PERIPH_IDX = 32'd9; - localparam logic[31:0] PAD_CONTROL_START_ADDRESS = AO_PERIPHERAL_START_ADDRESS + 32'h${pad_control_start_offset}; - localparam logic[31:0] PAD_CONTROL_SIZE = 32'h${pad_control_size_address}; - localparam logic[31:0] PAD_CONTROL_END_ADDRESS = PAD_CONTROL_START_ADDRESS + PAD_CONTROL_SIZE; - localparam logic[31:0] PAD_CONTROL_IDX = 32'd10; + localparam logic[31:0] PADFRAME_START_ADDRESS = AO_PERIPHERAL_START_ADDRESS + 32'h${padframe_start_offset}; + localparam logic[31:0] PADFRAME_SIZE = 32'h${padframe_size_address}; + localparam logic[31:0] PADFRAME_END_ADDRESS = PADFRAME_START_ADDRESS + PADFRAME_SIZE; + localparam logic[31:0] PADFRAME_IDX = 32'd10; localparam logic[31:0] GPIO_AO_START_ADDRESS = AO_PERIPHERAL_START_ADDRESS + 32'h${gpio_ao_start_offset}; localparam logic[31:0] GPIO_AO_SIZE = 32'h${gpio_ao_size_address}; @@ -180,7 +180,7 @@ package core_v_mini_mcu_pkg; '{ idx: DMA_IDX, start_addr: DMA_START_ADDRESS, end_addr: DMA_END_ADDRESS }, '{ idx: FAST_INTR_CTRL_IDX, start_addr: FAST_INTR_CTRL_START_ADDRESS, end_addr: FAST_INTR_CTRL_END_ADDRESS }, '{ idx: EXT_PERIPH_IDX, start_addr: EXT_PERIPH_START_ADDRESS, end_addr: EXT_PERIPH_END_ADDRESS }, - '{ idx: PAD_CONTROL_IDX, start_addr: PAD_CONTROL_START_ADDRESS, end_addr: PAD_CONTROL_END_ADDRESS }, + '{ idx: PADFRAME_IDX, start_addr: PADFRAME_START_ADDRESS, end_addr: PADFRAME_END_ADDRESS }, '{ idx: GPIO_AO_IDX, start_addr: GPIO_AO_START_ADDRESS, end_addr: GPIO_AO_END_ADDRESS }, '{ idx: UART_IDX, start_addr: UART_START_ADDRESS, end_addr: UART_END_ADDRESS } }; diff --git a/hw/core-v-mini-mcu/peripheral_subsystem.sv b/hw/core-v-mini-mcu/peripheral_subsystem.sv index 9aa321754..14a8904c0 100644 --- a/hw/core-v-mini-mcu/peripheral_subsystem.sv +++ b/hw/core-v-mini-mcu/peripheral_subsystem.sv @@ -225,32 +225,19 @@ module peripheral_subsystem .msip_o(msip_o) ); - reg_to_tlul #( - .req_t(reg_pkg::reg_req_t), - .rsp_t(reg_pkg::reg_rsp_t), - .tl_h2d_t(tlul_pkg::tl_h2d_t), - .tl_d2h_t(tlul_pkg::tl_d2h_t), - .tl_a_user_t(tlul_pkg::tl_a_user_t), - .tl_a_op_e(tlul_pkg::tl_a_op_e), - .TL_A_USER_DEFAULT(tlul_pkg::TL_A_USER_DEFAULT), - .PutFullData(tlul_pkg::PutFullData), - .Get(tlul_pkg::Get) - ) reg_to_tlul_gpio_i ( - .tl_o(gpio_tl_h2d), - .tl_i(gpio_tl_d2h), - .reg_req_i(peripheral_slv_req[core_v_mini_mcu_pkg::GPIO_IDX]), - .reg_rsp_o(peripheral_slv_rsp[core_v_mini_mcu_pkg::GPIO_IDX]) - ); - - gpio gpio_i ( + gpio #( + .reg_req_t(reg_pkg::reg_req_t), + .reg_rsp_t(reg_pkg::reg_rsp_t) + ) gpio_i ( .clk_i, .rst_ni, - .tl_i(gpio_tl_h2d), - .tl_o(gpio_tl_d2h), - .cio_gpio_i({cio_gpio_i, 8'b0}), - .cio_gpio_o({cio_gpio_o, cio_gpio_unused}), - .cio_gpio_en_o({cio_gpio_en_o, cio_gpio_en_unused}), - .intr_gpio_o({gpio_intr, gpio_int_unused}) + .reg_req_i(peripheral_slv_req[core_v_mini_mcu_pkg::GPIO_IDX]), + .reg_rsp_o(peripheral_slv_rsp[core_v_mini_mcu_pkg::GPIO_IDX]), + .gpio_in({cio_gpio_i, 8'b0}), + .gpio_out({cio_gpio_o, cio_gpio_unused}), + .gpio_tx_en_o({cio_gpio_en_o, cio_gpio_en_unused}), + .gpio_in_sync_o(), + .interrupt_o({gpio_intr, gpio_int_unused}) ); reg_to_tlul #( diff --git a/hw/simulation/pad_cell_inout.sv b/hw/simulation/pad_cell_inout.sv index c98e3c269..5b621433d 100644 --- a/hw/simulation/pad_cell_inout.sv +++ b/hw/simulation/pad_cell_inout.sv @@ -9,8 +9,7 @@ module pad_cell_inout #( input logic pad_in_i, input logic pad_oe_i, output logic pad_out_o, - inout logic pad_io, - input logic [PADATTR-1:0] pad_attributes_i + inout logic pad_io ); logic pad; diff --git a/hw/simulation/pad_cell_input.sv b/hw/simulation/pad_cell_input.sv index 68d5ddb3c..045f43dbe 100644 --- a/hw/simulation/pad_cell_input.sv +++ b/hw/simulation/pad_cell_input.sv @@ -9,8 +9,7 @@ module pad_cell_input #( input logic pad_in_i, input logic pad_oe_i, output logic pad_out_o, - inout logic pad_io, - input logic [PADATTR-1:0] pad_attributes_i + inout logic pad_io ); logic pad; diff --git a/hw/simulation/pad_cell_output.sv b/hw/simulation/pad_cell_output.sv index 8c3d916cc..5bc3758e3 100644 --- a/hw/simulation/pad_cell_output.sv +++ b/hw/simulation/pad_cell_output.sv @@ -9,8 +9,7 @@ module pad_cell_output #( input logic pad_in_i, input logic pad_oe_i, output logic pad_out_o, - inout logic pad_io, - input logic [PADATTR-1:0] pad_attributes_i + inout logic pad_io ); logic pad; diff --git a/hw/system/pad_ring.sv.tpl b/hw/system/pad_ring.sv.tpl deleted file mode 100644 index 90792cc17..000000000 --- a/hw/system/pad_ring.sv.tpl +++ /dev/null @@ -1,27 +0,0 @@ -// Copyright 2022 EPFL -// Solderpad Hardware License, Version 2.1, see LICENSE.md for details. -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 - -module pad_ring ( -% for pad in pad_list: -${pad.pad_ring_io_interface} -${pad.pad_ring_ctrl_interface} -% endfor - -% for external_pad in external_pad_list: -${external_pad.pad_ring_io_interface} -${external_pad.pad_ring_ctrl_interface} -% endfor - - input logic [core_v_mini_mcu_pkg::NUM_PAD-1:0][7:0] pad_attributes_i -); - -% for pad in pad_list: -${pad.pad_ring_instance} -% endfor - -% for external_pad in external_pad_list: -${external_pad.pad_ring_instance} -% endfor - -endmodule // pad_ring diff --git a/hw/system/padframe/include/padframe/assign.svh b/hw/system/padframe/include/padframe/assign.svh new file mode 100644 index 000000000..75c0d33e7 --- /dev/null +++ b/hw/system/padframe/include/padframe/assign.svh @@ -0,0 +1,51 @@ +// File auto-generated by Padrick 0.3.1.post0.dev2+ge09286c + +// Assignment Macros +// Assigns all members of port struct to another struct with same names but potentially different order + +`define ASSIGN_XHEEP_I2C_PAD2SOC(load, driver) \ + assign load.i2c_scl_o = driver.i2c_scl_o; \ + assign load.i2c_sda_o = driver.i2c_sda_o; \ + +`define ASSIGN_XHEEP_I2C_SOC2PAD(load, driver) \ + assign load.i2c_scl_i = driver.i2c_scl_i; \ + assign load.i2c_scl_oe_i = driver.i2c_scl_oe_i; \ + assign load.i2c_sda_i = driver.i2c_sda_i; \ + assign load.i2c_sda_oe_i = driver.i2c_sda_oe_i; \ + +`define ASSIGN_XHEEP_GPIO_PAD2SOC(load, driver) \ + assign load.gpio_30_o = driver.gpio_30_o; \ + assign load.gpio_31_o = driver.gpio_31_o; \ + +`define ASSIGN_XHEEP_GPIO_SOC2PAD(load, driver) \ + assign load.gpio_30_i = driver.gpio_30_i; \ + assign load.gpio_30_oe_i = driver.gpio_30_oe_i; \ + assign load.gpio_31_i = driver.gpio_31_i; \ + assign load.gpio_31_oe_i = driver.gpio_31_oe_i; \ + +`define ASSIGN_XHEEP_SPI2_PAD2SOC(load, driver) \ + assign load.spi2_cs_00_o = driver.spi2_cs_00_o; \ + assign load.spi2_cs_01_o = driver.spi2_cs_01_o; \ + assign load.spi2_sck_o = driver.spi2_sck_o; \ + assign load.spi2_sd_00_o = driver.spi2_sd_00_o; \ + assign load.spi2_sd_01_o = driver.spi2_sd_01_o; \ + assign load.spi2_sd_02_o = driver.spi2_sd_02_o; \ + assign load.spi2_sd_03_o = driver.spi2_sd_03_o; \ + +`define ASSIGN_XHEEP_SPI2_SOC2PAD(load, driver) \ + assign load.spi2_cs_00_i = driver.spi2_cs_00_i; \ + assign load.spi2_cs_00_oe_i = driver.spi2_cs_00_oe_i; \ + assign load.spi2_cs_01_i = driver.spi2_cs_01_i; \ + assign load.spi2_cs_01_oe_i = driver.spi2_cs_01_oe_i; \ + assign load.spi2_sck_i = driver.spi2_sck_i; \ + assign load.spi2_sck_oe_i = driver.spi2_sck_oe_i; \ + assign load.spi2_sd_00_i = driver.spi2_sd_00_i; \ + assign load.spi2_sd_00_oe_i = driver.spi2_sd_00_oe_i; \ + assign load.spi2_sd_01_i = driver.spi2_sd_01_i; \ + assign load.spi2_sd_01_oe_i = driver.spi2_sd_01_oe_i; \ + assign load.spi2_sd_02_i = driver.spi2_sd_02_i; \ + assign load.spi2_sd_02_oe_i = driver.spi2_sd_02_oe_i; \ + assign load.spi2_sd_03_i = driver.spi2_sd_03_i; \ + assign load.spi2_sd_03_oe_i = driver.spi2_sd_03_oe_i; \ + + diff --git a/hw/system/padframe/ips_list.yml b/hw/system/padframe/ips_list.yml new file mode 100644 index 000000000..33816352e --- /dev/null +++ b/hw/system/padframe/ips_list.yml @@ -0,0 +1,17 @@ +# File auto-generated by Padrick 0.3.1.post0.dev2+ge09286c +# IPApprox dependencies for padframe +common_cells: + commit: v1.21.0 + domain: [cluster, soc] + server: https://github.com + group: pulp-platform +register_interface: + commit: v0.2.1 + domain: [soc] + server: https://github.com + group: pulp-platform +axi/axi: + commit: v0.27.0 + domain: [cluster, soc] + server: https://github.com + group: pulp-platform diff --git a/hw/system/padframe/padframe.core b/hw/system/padframe/padframe.core new file mode 100644 index 000000000..405bef3e2 --- /dev/null +++ b/hw/system/padframe/padframe.core @@ -0,0 +1,30 @@ +CAPI=2: + +name: "x-heep:ip:padframe" +description: "core-v-mini-mcu dma peripheral" + +# Copyright 2022 EPFL +# Solderpad Hardware License, Version 2.1, see LICENSE.md for details. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +filesets: + files_rtl: + depend: + - pulp-platform.org::common_cells + - pulp-platform.org::register_interface + files: + - include/padframe/assign.svh: {is_include_file: true} + - src/pkg_padframe.sv + - src/pkg_internal_padframe_xheep.sv + - src/padframe_xheep_config_reg_pkg.sv + - src/padframe_xheep_config_reg_top.sv + - src/padframe_xheep_pads.sv + - src/padframe_xheep_muxer.sv + - src/padframe_xheep.sv + - src/padframe.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/hw/system/padframe/padframe.yaml b/hw/system/padframe/padframe.yaml new file mode 100644 index 000000000..e409ad54d --- /dev/null +++ b/hw/system/padframe/padframe.yaml @@ -0,0 +1,373 @@ +manifest_version: 2 +name: padframe +pad_domains: + - name: xheep + pad_types: + - name: generic_pad_cell_input + + template: | + pad_cell_input ${instance_name} ( + .pad_in_i(${conn["chip2pad"]}), + .pad_oe_i(${conn["output_en"]}), + .pad_out_o(${conn["pad2chip"]}), + .pad_io(${conn["pad"]}) + ); + pad_signals: &DEFAULT_SIGNALS + - name: chip2pad + size: 1 + kind: input + conn_type: dynamic + default_reset_value: 0 + default_static_value: 1'b0 + - name: pad2chip + size: 1 + kind: output + conn_type: dynamic + - name: output_en + size: 1 + kind: input + conn_type: dynamic + default_reset_value: 0 + default_static_value: 1'b0 + - name: pad + size: 1 + kind: pad + - name: generic_pad_cell_output + template: | + pad_cell_output ${instance_name} ( + .pad_in_i(${conn["chip2pad"]}), + .pad_oe_i(${conn["output_en"]}), + .pad_out_o(${conn["pad2chip"]}), + .pad_io(${conn["pad"]}) + ); + pad_signals: *DEFAULT_SIGNALS + + - name: generic_pad_cell_inout + template: | + pad_cell_inout ${instance_name} ( + .pad_in_i(${conn["chip2pad"]}), + .pad_oe_i(${conn["output_en"]}), + .pad_out_o(${conn["pad2chip"]}), + .pad_io(${conn["pad"]}) + ); + pad_signals: *DEFAULT_SIGNALS + + pad_list: + +# +# Static Connection +# + - name: pad_clk + pad_type: generic_pad_cell_input + is_static: true + connections: + chip2pad: 1'b0 + output_en: 1'b0 + pad2chip: clk_o + + - name: pad_rst + pad_type: generic_pad_cell_input + is_static: true + connections: + chip2pad: 1'b0 + output_en: 1'b0 + pad2chip: rst_o + + - name: pad_boot_select + pad_type: generic_pad_cell_input + is_static: true + connections: + chip2pad: 1'b0 + output_en: 1'b0 + pad2chip: boot_select_o + + - name: pad_execute_from_flash + pad_type: generic_pad_cell_input + is_static: true + connections: + chip2pad: 1'b0 + output_en: 1'b0 + pad2chip: execute_from_flash_o + + - name: pad_jtag_tck + pad_type: generic_pad_cell_input + is_static: true + connections: + chip2pad: 1'b0 + output_en: 1'b0 + pad2chip: jtag_tck_o + + - name: pad_jtag_tms + pad_type: generic_pad_cell_input + is_static: true + connections: + chip2pad: 1'b0 + output_en: 1'b0 + pad2chip: jtag_tms_o + + - name: pad_jtag_trst + pad_type: generic_pad_cell_input + is_static: true + connections: + chip2pad: 1'b0 + output_en: 1'b0 + pad2chip: jtag_trst_o + + - name: pad_jtag_tdi + pad_type: generic_pad_cell_input + is_static: true + connections: + chip2pad: 1'b0 + output_en: 1'b0 + pad2chip: jtag_tdi_o + + - name: pad_jtag_tdo + pad_type: generic_pad_cell_output + is_static: true + connections: + chip2pad: jtag_tdo_i + output_en: 1'b1 + + - name: pad_exit_valid + pad_type: generic_pad_cell_output + is_static: true + connections: + chip2pad: exit_valid_i + output_en: 1'b1 + + - name: pad_uart_rx + pad_type: generic_pad_cell_input + is_static: true + connections: + chip2pad: 1'b0 + output_en: 1'b0 + pad2chip: uart_rx_o + + - name: pad_uart_tx + pad_type: generic_pad_cell_output + is_static: true + connections: + chip2pad: uart_tx_i + output_en: 1'b1 + + - name: pad_gpio_{i:2d}_i + multiple: 23 + pad_type: generic_pad_cell_inout + is_static: true + connections: + chip2pad: gpio_{i:2d}_i + output_en: gpio_{i:2d}_oe_i + pad2chip: gpio_{i:2d}_o + + - name: pad_spi_flash_sck + pad_type: generic_pad_cell_inout + is_static: true + connections: + chip2pad: spi_flash_sck_i + output_en: spi_flash_sck_oe_i + pad2chip: spi_flash_sck_o + + - name: pad_spi_flash_cs_{i:2d} + multiple: 2 + pad_type: generic_pad_cell_inout + is_static: true + connections: + chip2pad: spi_flash_cs_{i:2d}_i + output_en: spi_flash_cs_{i:2d}_oe_i + pad2chip: spi_flash_cs_{i:2d}_o + + - name: pad_spi_flash_sd_{i:2d} + multiple: 4 + pad_type: generic_pad_cell_inout + is_static: true + connections: + chip2pad: spi_flash_sd_{i:2d}_i + output_en: spi_flash_sd_{i:2d}_oe_i + pad2chip: spi_flash_sd_{i:2d}_o + + - name: pad_spi_sck + pad_type: generic_pad_cell_inout + is_static: true + connections: + chip2pad: spi_sck_i + output_en: spi_sck_oe_i + pad2chip: spi_sck_o + + - name: pad_spi_cs_{i:2d} + multiple: 2 + pad_type: generic_pad_cell_inout + is_static: true + connections: + chip2pad: spi_cs_{i:2d}_i + output_en: spi_cs_{i:2d}_oe_i + pad2chip: spi_cs_{i:2d}_o + + - name: pad_spi_sd_{i:2d} + multiple: 4 + pad_type: generic_pad_cell_inout + is_static: true + connections: + chip2pad: spi_sd_{i:2d}_i + output_en: spi_sd_{i:2d}_oe_i + pad2chip: spi_sd_{i:2d}_o + + +# +# Dynamic Connection +# + + # - name: pad_io_{i+23:2d} + # multiple: 9 + # mux_groups: ["pad{i+23:2d}"] + # pad_type: generic_pad_cell_inout + # is_static: false + # default_port: + # pad_io_23: spi2.spi2_cs_00 + # pad_io_24: spi2.spi2_cs_01 + # pad_io_25: spi2.spi2_sck + # pad_io_{i%4+26:2d}: spi2.sd_{i%4:2d} + # pad_io_30: i2c.i2c_sda + # pad_io_31: i2c.i2c_scl + + - name: pad_io_23 + default_port: spi2.spi2_cs_00 + mux_groups: [pad23] + pad_type: generic_pad_cell_inout + is_static: false + + - name: pad_io_24 + default_port: spi2.spi2_cs_01 + mux_groups: [pad24] + pad_type: generic_pad_cell_inout + is_static: false + + - name: pad_io_25 + default_port: spi2.spi2_sck + mux_groups: [pad25] + pad_type: generic_pad_cell_inout + is_static: false + + - name: pad_io_26 + default_port: spi2.spi2_sd_00 + mux_groups: [pad26] + pad_type: generic_pad_cell_inout + is_static: false + + - name: pad_io_27 + default_port: spi2.spi2_sd_01 + mux_groups: [pad27] + pad_type: generic_pad_cell_inout + is_static: false + + - name: pad_io_28 + default_port: spi2.spi2_sd_02 + mux_groups: [pad28] + pad_type: generic_pad_cell_inout + is_static: false + + - name: pad_io_29 + default_port: spi2.spi2_sd_03 + mux_groups: [pad29] + pad_type: generic_pad_cell_inout + is_static: false + + - name: pad_io_30 + default_port: i2c.i2c_sda + mux_groups: [pad30] + pad_type: generic_pad_cell_inout + is_static: false + + - name: pad_io_31 + default_port: i2c.i2c_scl + mux_groups: [pad31] + pad_type: generic_pad_cell_inout + is_static: false + + port_groups: + + - name: i2c + output_defaults: 1'b0 + ports: + - name: i2c_scl + mux_groups: [pad31] + connections: + chip2pad: i2c_scl_i + i2c_scl_o: pad2chip + output_en: i2c_scl_oe_i + + - name: i2c_sda + mux_groups: [pad30] + connections: + chip2pad: i2c_sda_i + i2c_sda_o: pad2chip + output_en: i2c_sda_oe_i + + - name: gpio + output_defaults: 1'b0 + ports: + - name: gpio_30 + mux_groups: [pad30] + connections: + chip2pad: gpio_30_i + gpio_30_o: pad2chip + output_en: gpio_30_oe_i + + - name: gpio_31 + mux_groups: [pad31] + connections: + chip2pad: gpio_31_i + gpio_31_o: pad2chip + output_en: gpio_31_oe_i + + - name: spi2 + output_defaults: 1'b0 + ports: + - name: spi2_cs_00 + mux_groups: [pad23] + connections: + chip2pad: spi2_cs_00_i + spi2_cs_00_o: pad2chip + output_en: spi2_cs_00_oe_i + + - name: spi2_cs_01 + mux_groups: [pad24] + connections: + chip2pad: spi2_cs_01_i + spi2_cs_01_o: pad2chip + output_en: spi2_cs_01_oe_i + + - name: spi2_sck + mux_groups: [pad25] + connections: + chip2pad: spi2_sck_i + spi2_sck_o: pad2chip + output_en: spi2_sck_oe_i + + - name: spi2_sd_00 + mux_groups: [pad26] + connections: + chip2pad: spi2_sd_00_i + spi2_sd_00_o: pad2chip + output_en: spi2_sd_00_oe_i + + - name: spi2_sd_01 + mux_groups: [pad27] + connections: + chip2pad: spi2_sd_01_i + spi2_sd_01_o: pad2chip + output_en: spi2_sd_01_oe_i + + - name: spi2_sd_02 + mux_groups: [pad28] + connections: + chip2pad: spi2_sd_02_i + spi2_sd_02_o: pad2chip + output_en: spi2_sd_02_oe_i + + - name: spi2_sd_03 + mux_groups: [pad29] + connections: + chip2pad: spi2_sd_03_i + spi2_sd_03_o: pad2chip + output_en: spi2_sd_03_oe_i + diff --git a/hw/system/padframe/src/padframe.sv b/hw/system/padframe/src/padframe.sv new file mode 100644 index 000000000..adfcf21ff --- /dev/null +++ b/hw/system/padframe/src/padframe.sv @@ -0,0 +1,206 @@ +// File auto-generated by Padrick 0.3.1.post0.dev2+ge09286c +module padframe + import pkg_padframe::*; +#( + parameter int unsigned AW = 32, + parameter int unsigned DW = 32, + parameter type req_t = logic, // reg_interface request type + parameter type resp_t = logic, // reg_interface response type + parameter logic [DW-1:0] DecodeErrRespData = 32'hdeadda7a +)( + input logic clk_i, + input logic rst_ni, + output static_connection_signals_pad2soc_t static_connection_signals_pad2soc, + input static_connection_signals_soc2pad_t static_connection_signals_soc2pad, + output port_signals_pad2soc_t port_signals_pad2soc, + input port_signals_soc2pad_t port_signals_soc2pad, + // Landing Pads + inout wire logic pad_xheep_pad_clk_pad, + inout wire logic pad_xheep_pad_rst_pad, + inout wire logic pad_xheep_pad_boot_select_pad, + inout wire logic pad_xheep_pad_execute_from_flash_pad, + inout wire logic pad_xheep_pad_jtag_tck_pad, + inout wire logic pad_xheep_pad_jtag_tms_pad, + inout wire logic pad_xheep_pad_jtag_trst_pad, + inout wire logic pad_xheep_pad_jtag_tdi_pad, + inout wire logic pad_xheep_pad_jtag_tdo_pad, + inout wire logic pad_xheep_pad_exit_valid_pad, + inout wire logic pad_xheep_pad_uart_rx_pad, + inout wire logic pad_xheep_pad_uart_tx_pad, + inout wire logic pad_xheep_pad_gpio_00_i_pad, + inout wire logic pad_xheep_pad_gpio_01_i_pad, + inout wire logic pad_xheep_pad_gpio_02_i_pad, + inout wire logic pad_xheep_pad_gpio_03_i_pad, + inout wire logic pad_xheep_pad_gpio_04_i_pad, + inout wire logic pad_xheep_pad_gpio_05_i_pad, + inout wire logic pad_xheep_pad_gpio_06_i_pad, + inout wire logic pad_xheep_pad_gpio_07_i_pad, + inout wire logic pad_xheep_pad_gpio_08_i_pad, + inout wire logic pad_xheep_pad_gpio_09_i_pad, + inout wire logic pad_xheep_pad_gpio_10_i_pad, + inout wire logic pad_xheep_pad_gpio_11_i_pad, + inout wire logic pad_xheep_pad_gpio_12_i_pad, + inout wire logic pad_xheep_pad_gpio_13_i_pad, + inout wire logic pad_xheep_pad_gpio_14_i_pad, + inout wire logic pad_xheep_pad_gpio_15_i_pad, + inout wire logic pad_xheep_pad_gpio_16_i_pad, + inout wire logic pad_xheep_pad_gpio_17_i_pad, + inout wire logic pad_xheep_pad_gpio_18_i_pad, + inout wire logic pad_xheep_pad_gpio_19_i_pad, + inout wire logic pad_xheep_pad_gpio_20_i_pad, + inout wire logic pad_xheep_pad_gpio_21_i_pad, + inout wire logic pad_xheep_pad_gpio_22_i_pad, + inout wire logic pad_xheep_pad_spi_flash_sck_pad, + inout wire logic pad_xheep_pad_spi_flash_cs_00_pad, + inout wire logic pad_xheep_pad_spi_flash_cs_01_pad, + inout wire logic pad_xheep_pad_spi_flash_sd_00_pad, + inout wire logic pad_xheep_pad_spi_flash_sd_01_pad, + inout wire logic pad_xheep_pad_spi_flash_sd_02_pad, + inout wire logic pad_xheep_pad_spi_flash_sd_03_pad, + inout wire logic pad_xheep_pad_spi_sck_pad, + inout wire logic pad_xheep_pad_spi_cs_00_pad, + inout wire logic pad_xheep_pad_spi_cs_01_pad, + inout wire logic pad_xheep_pad_spi_sd_00_pad, + inout wire logic pad_xheep_pad_spi_sd_01_pad, + inout wire logic pad_xheep_pad_spi_sd_02_pad, + inout wire logic pad_xheep_pad_spi_sd_03_pad, + inout wire logic pad_xheep_pad_io_23_pad, + inout wire logic pad_xheep_pad_io_24_pad, + inout wire logic pad_xheep_pad_io_25_pad, + inout wire logic pad_xheep_pad_io_26_pad, + inout wire logic pad_xheep_pad_io_27_pad, + inout wire logic pad_xheep_pad_io_28_pad, + inout wire logic pad_xheep_pad_io_29_pad, + inout wire logic pad_xheep_pad_io_30_pad, + inout wire logic pad_xheep_pad_io_31_pad, + // Config Interface + input req_t config_req_i, + output resp_t config_rsp_o + ); + + + req_t xheep_config_req; + resp_t xheep_config_resp; + padframe_xheep #( + .req_t(req_t), + .resp_t(resp_t) + ) i_xheep ( + .clk_i, + .rst_ni, + .static_connection_signals_pad2soc(static_connection_signals_pad2soc.xheep), + .static_connection_signals_soc2pad(static_connection_signals_soc2pad.xheep), + .port_signals_pad2soc_o(port_signals_pad2soc.xheep), + .port_signals_soc2pad_i(port_signals_soc2pad.xheep), + .pad_pad_clk_pad(pad_xheep_pad_clk_pad), + .pad_pad_rst_pad(pad_xheep_pad_rst_pad), + .pad_pad_boot_select_pad(pad_xheep_pad_boot_select_pad), + .pad_pad_execute_from_flash_pad(pad_xheep_pad_execute_from_flash_pad), + .pad_pad_jtag_tck_pad(pad_xheep_pad_jtag_tck_pad), + .pad_pad_jtag_tms_pad(pad_xheep_pad_jtag_tms_pad), + .pad_pad_jtag_trst_pad(pad_xheep_pad_jtag_trst_pad), + .pad_pad_jtag_tdi_pad(pad_xheep_pad_jtag_tdi_pad), + .pad_pad_jtag_tdo_pad(pad_xheep_pad_jtag_tdo_pad), + .pad_pad_exit_valid_pad(pad_xheep_pad_exit_valid_pad), + .pad_pad_uart_rx_pad(pad_xheep_pad_uart_rx_pad), + .pad_pad_uart_tx_pad(pad_xheep_pad_uart_tx_pad), + .pad_pad_gpio_00_i_pad(pad_xheep_pad_gpio_00_i_pad), + .pad_pad_gpio_01_i_pad(pad_xheep_pad_gpio_01_i_pad), + .pad_pad_gpio_02_i_pad(pad_xheep_pad_gpio_02_i_pad), + .pad_pad_gpio_03_i_pad(pad_xheep_pad_gpio_03_i_pad), + .pad_pad_gpio_04_i_pad(pad_xheep_pad_gpio_04_i_pad), + .pad_pad_gpio_05_i_pad(pad_xheep_pad_gpio_05_i_pad), + .pad_pad_gpio_06_i_pad(pad_xheep_pad_gpio_06_i_pad), + .pad_pad_gpio_07_i_pad(pad_xheep_pad_gpio_07_i_pad), + .pad_pad_gpio_08_i_pad(pad_xheep_pad_gpio_08_i_pad), + .pad_pad_gpio_09_i_pad(pad_xheep_pad_gpio_09_i_pad), + .pad_pad_gpio_10_i_pad(pad_xheep_pad_gpio_10_i_pad), + .pad_pad_gpio_11_i_pad(pad_xheep_pad_gpio_11_i_pad), + .pad_pad_gpio_12_i_pad(pad_xheep_pad_gpio_12_i_pad), + .pad_pad_gpio_13_i_pad(pad_xheep_pad_gpio_13_i_pad), + .pad_pad_gpio_14_i_pad(pad_xheep_pad_gpio_14_i_pad), + .pad_pad_gpio_15_i_pad(pad_xheep_pad_gpio_15_i_pad), + .pad_pad_gpio_16_i_pad(pad_xheep_pad_gpio_16_i_pad), + .pad_pad_gpio_17_i_pad(pad_xheep_pad_gpio_17_i_pad), + .pad_pad_gpio_18_i_pad(pad_xheep_pad_gpio_18_i_pad), + .pad_pad_gpio_19_i_pad(pad_xheep_pad_gpio_19_i_pad), + .pad_pad_gpio_20_i_pad(pad_xheep_pad_gpio_20_i_pad), + .pad_pad_gpio_21_i_pad(pad_xheep_pad_gpio_21_i_pad), + .pad_pad_gpio_22_i_pad(pad_xheep_pad_gpio_22_i_pad), + .pad_pad_spi_flash_sck_pad(pad_xheep_pad_spi_flash_sck_pad), + .pad_pad_spi_flash_cs_00_pad(pad_xheep_pad_spi_flash_cs_00_pad), + .pad_pad_spi_flash_cs_01_pad(pad_xheep_pad_spi_flash_cs_01_pad), + .pad_pad_spi_flash_sd_00_pad(pad_xheep_pad_spi_flash_sd_00_pad), + .pad_pad_spi_flash_sd_01_pad(pad_xheep_pad_spi_flash_sd_01_pad), + .pad_pad_spi_flash_sd_02_pad(pad_xheep_pad_spi_flash_sd_02_pad), + .pad_pad_spi_flash_sd_03_pad(pad_xheep_pad_spi_flash_sd_03_pad), + .pad_pad_spi_sck_pad(pad_xheep_pad_spi_sck_pad), + .pad_pad_spi_cs_00_pad(pad_xheep_pad_spi_cs_00_pad), + .pad_pad_spi_cs_01_pad(pad_xheep_pad_spi_cs_01_pad), + .pad_pad_spi_sd_00_pad(pad_xheep_pad_spi_sd_00_pad), + .pad_pad_spi_sd_01_pad(pad_xheep_pad_spi_sd_01_pad), + .pad_pad_spi_sd_02_pad(pad_xheep_pad_spi_sd_02_pad), + .pad_pad_spi_sd_03_pad(pad_xheep_pad_spi_sd_03_pad), + .pad_pad_io_23_pad(pad_xheep_pad_io_23_pad), + .pad_pad_io_24_pad(pad_xheep_pad_io_24_pad), + .pad_pad_io_25_pad(pad_xheep_pad_io_25_pad), + .pad_pad_io_26_pad(pad_xheep_pad_io_26_pad), + .pad_pad_io_27_pad(pad_xheep_pad_io_27_pad), + .pad_pad_io_28_pad(pad_xheep_pad_io_28_pad), + .pad_pad_io_29_pad(pad_xheep_pad_io_29_pad), + .pad_pad_io_30_pad(pad_xheep_pad_io_30_pad), + .pad_pad_io_31_pad(pad_xheep_pad_io_31_pad), + .config_req_i(xheep_config_req), + .config_rsp_o(xheep_config_resp) + ); + + + localparam int unsigned NUM_PAD_DOMAINS = 1; + localparam int unsigned REG_ADDR_WIDTH = 7; + typedef struct packed { + int unsigned idx; + logic [REG_ADDR_WIDTH-1:0] start_addr; + logic [REG_ADDR_WIDTH-1:0] end_addr; + } addr_rule_t; + + localparam addr_rule_t[NUM_PAD_DOMAINS-1:0] ADDR_DEMUX_RULES = '{ + '{ idx: 0, start_addr: 7'd0, end_addr: 7'd76} + }; + logic[$clog2(NUM_PAD_DOMAINS+1)-1:0] pad_domain_sel; // +1 since there is an additional error slave + addr_decode #( + .NoIndices(NUM_PAD_DOMAINS+1), + .NoRules(NUM_PAD_DOMAINS), + .addr_t(logic[REG_ADDR_WIDTH-1:0]), + .rule_t(addr_rule_t) + ) i_addr_decode( + .addr_i(config_req_i.addr[REG_ADDR_WIDTH-1:0]), + .addr_map_i(ADDR_DEMUX_RULES), + .dec_valid_o(), + .dec_error_o(), + .idx_o(pad_domain_sel), + .en_default_idx_i(1'b1), + .default_idx_i(1'd1) // The last entry is the error slave + ); + + req_t error_slave_req; + resp_t error_slave_rsp; + + // Config Interface demultiplexing + reg_demux #( + .NoPorts(NUM_PAD_DOMAINS+1), //+1 for the error slave + .req_t(req_t), + .rsp_t(resp_t) + ) i_config_demuxer ( + .clk_i, + .rst_ni, + .in_select_i(pad_domain_sel), + .in_req_i(config_req_i), + .in_rsp_o(config_rsp_o), + .out_req_o({error_slave_req, xheep_config_req}), + .out_rsp_i({error_slave_rsp, xheep_config_resp}) + ); + + assign error_slave_rsp.error = 1'b1; + assign error_slave_rsp.rdata = DecodeErrRespData; + assign error_slave_rsp.ready = 1'b1; + +endmodule diff --git a/hw/system/padframe/src/padframe_xheep.sv b/hw/system/padframe/src/padframe_xheep.sv new file mode 100644 index 000000000..f3fe82032 --- /dev/null +++ b/hw/system/padframe/src/padframe_xheep.sv @@ -0,0 +1,161 @@ +// File auto-generated by Padrick 0.3.1.post0.dev2+ge09286c +module padframe_xheep + import pkg_padframe::*; + import pkg_internal_padframe_xheep::*; +#( + parameter type req_t = logic, // reg_interface request type + parameter type resp_t = logic // reg_interface response type +) ( + input logic clk_i, + input logic rst_ni, + output pad_domain_xheep_static_connection_signals_pad2soc_t static_connection_signals_pad2soc, + input pad_domain_xheep_static_connection_signals_soc2pad_t static_connection_signals_soc2pad, + output pad_domain_xheep_ports_pad2soc_t port_signals_pad2soc_o, + input pad_domain_xheep_ports_soc2pad_t port_signals_soc2pad_i, + inout wire logic pad_pad_clk_pad, + inout wire logic pad_pad_rst_pad, + inout wire logic pad_pad_boot_select_pad, + inout wire logic pad_pad_execute_from_flash_pad, + inout wire logic pad_pad_jtag_tck_pad, + inout wire logic pad_pad_jtag_tms_pad, + inout wire logic pad_pad_jtag_trst_pad, + inout wire logic pad_pad_jtag_tdi_pad, + inout wire logic pad_pad_jtag_tdo_pad, + inout wire logic pad_pad_exit_valid_pad, + inout wire logic pad_pad_uart_rx_pad, + inout wire logic pad_pad_uart_tx_pad, + inout wire logic pad_pad_gpio_00_i_pad, + inout wire logic pad_pad_gpio_01_i_pad, + inout wire logic pad_pad_gpio_02_i_pad, + inout wire logic pad_pad_gpio_03_i_pad, + inout wire logic pad_pad_gpio_04_i_pad, + inout wire logic pad_pad_gpio_05_i_pad, + inout wire logic pad_pad_gpio_06_i_pad, + inout wire logic pad_pad_gpio_07_i_pad, + inout wire logic pad_pad_gpio_08_i_pad, + inout wire logic pad_pad_gpio_09_i_pad, + inout wire logic pad_pad_gpio_10_i_pad, + inout wire logic pad_pad_gpio_11_i_pad, + inout wire logic pad_pad_gpio_12_i_pad, + inout wire logic pad_pad_gpio_13_i_pad, + inout wire logic pad_pad_gpio_14_i_pad, + inout wire logic pad_pad_gpio_15_i_pad, + inout wire logic pad_pad_gpio_16_i_pad, + inout wire logic pad_pad_gpio_17_i_pad, + inout wire logic pad_pad_gpio_18_i_pad, + inout wire logic pad_pad_gpio_19_i_pad, + inout wire logic pad_pad_gpio_20_i_pad, + inout wire logic pad_pad_gpio_21_i_pad, + inout wire logic pad_pad_gpio_22_i_pad, + inout wire logic pad_pad_spi_flash_sck_pad, + inout wire logic pad_pad_spi_flash_cs_00_pad, + inout wire logic pad_pad_spi_flash_cs_01_pad, + inout wire logic pad_pad_spi_flash_sd_00_pad, + inout wire logic pad_pad_spi_flash_sd_01_pad, + inout wire logic pad_pad_spi_flash_sd_02_pad, + inout wire logic pad_pad_spi_flash_sd_03_pad, + inout wire logic pad_pad_spi_sck_pad, + inout wire logic pad_pad_spi_cs_00_pad, + inout wire logic pad_pad_spi_cs_01_pad, + inout wire logic pad_pad_spi_sd_00_pad, + inout wire logic pad_pad_spi_sd_01_pad, + inout wire logic pad_pad_spi_sd_02_pad, + inout wire logic pad_pad_spi_sd_03_pad, + inout wire logic pad_pad_io_23_pad, + inout wire logic pad_pad_io_24_pad, + inout wire logic pad_pad_io_25_pad, + inout wire logic pad_pad_io_26_pad, + inout wire logic pad_pad_io_27_pad, + inout wire logic pad_pad_io_28_pad, + inout wire logic pad_pad_io_29_pad, + inout wire logic pad_pad_io_30_pad, + inout wire logic pad_pad_io_31_pad, + input req_t config_req_i, + output resp_t config_rsp_o +); + + mux_to_pads_t s_mux_to_pads; + pads_to_mux_t s_pads_to_mux; + + padframe_xheep_pads i_xheep_pads ( + .static_connection_signals_pad2soc, + .static_connection_signals_soc2pad, + .mux_to_pads_i(s_mux_to_pads), + .pads_to_mux_o(s_pads_to_mux), + .pad_pad_clk_pad, + .pad_pad_rst_pad, + .pad_pad_boot_select_pad, + .pad_pad_execute_from_flash_pad, + .pad_pad_jtag_tck_pad, + .pad_pad_jtag_tms_pad, + .pad_pad_jtag_trst_pad, + .pad_pad_jtag_tdi_pad, + .pad_pad_jtag_tdo_pad, + .pad_pad_exit_valid_pad, + .pad_pad_uart_rx_pad, + .pad_pad_uart_tx_pad, + .pad_pad_gpio_00_i_pad, + .pad_pad_gpio_01_i_pad, + .pad_pad_gpio_02_i_pad, + .pad_pad_gpio_03_i_pad, + .pad_pad_gpio_04_i_pad, + .pad_pad_gpio_05_i_pad, + .pad_pad_gpio_06_i_pad, + .pad_pad_gpio_07_i_pad, + .pad_pad_gpio_08_i_pad, + .pad_pad_gpio_09_i_pad, + .pad_pad_gpio_10_i_pad, + .pad_pad_gpio_11_i_pad, + .pad_pad_gpio_12_i_pad, + .pad_pad_gpio_13_i_pad, + .pad_pad_gpio_14_i_pad, + .pad_pad_gpio_15_i_pad, + .pad_pad_gpio_16_i_pad, + .pad_pad_gpio_17_i_pad, + .pad_pad_gpio_18_i_pad, + .pad_pad_gpio_19_i_pad, + .pad_pad_gpio_20_i_pad, + .pad_pad_gpio_21_i_pad, + .pad_pad_gpio_22_i_pad, + .pad_pad_spi_flash_sck_pad, + .pad_pad_spi_flash_cs_00_pad, + .pad_pad_spi_flash_cs_01_pad, + .pad_pad_spi_flash_sd_00_pad, + .pad_pad_spi_flash_sd_01_pad, + .pad_pad_spi_flash_sd_02_pad, + .pad_pad_spi_flash_sd_03_pad, + .pad_pad_spi_sck_pad, + .pad_pad_spi_cs_00_pad, + .pad_pad_spi_cs_01_pad, + .pad_pad_spi_sd_00_pad, + .pad_pad_spi_sd_01_pad, + .pad_pad_spi_sd_02_pad, + .pad_pad_spi_sd_03_pad, + .pad_pad_io_23_pad, + .pad_pad_io_24_pad, + .pad_pad_io_25_pad, + .pad_pad_io_26_pad, + .pad_pad_io_27_pad, + .pad_pad_io_28_pad, + .pad_pad_io_29_pad, + .pad_pad_io_30_pad, + .pad_pad_io_31_pad + + ); + + padframe_xheep_muxer #( + .req_t(req_t), + .resp_t(resp_t) + )i_xheep_muxer ( + .clk_i, + .rst_ni, + .port_signals_soc2pad_i, + .port_signals_pad2soc_o, + .mux_to_pads_o(s_mux_to_pads), + .pads_to_mux_i(s_pads_to_mux), + // Configuration interface using register_interface protocol + .config_req_i, + .config_rsp_o + ); + +endmodule : padframe_xheep diff --git a/hw/system/padframe/src/padframe_xheep_config_reg_pkg.sv b/hw/system/padframe/src/padframe_xheep_config_reg_pkg.sv new file mode 100644 index 000000000..4763cb5c4 --- /dev/null +++ b/hw/system/padframe/src/padframe_xheep_config_reg_pkg.sv @@ -0,0 +1,233 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package padframe_xheep_config_reg_pkg; + + // Address widths within the block + parameter int BlockAw = 7; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + struct packed { + logic [15:0] q; + } hw_version; + struct packed { + logic [15:0] q; + } padcount; + } padframe_xheep_config_reg2hw_info_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } output_en; + } padframe_xheep_config_reg2hw_pad_io_23_cfg_reg_t; + + typedef struct packed { + logic q; + } padframe_xheep_config_reg2hw_pad_io_23_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } output_en; + } padframe_xheep_config_reg2hw_pad_io_24_cfg_reg_t; + + typedef struct packed { + logic q; + } padframe_xheep_config_reg2hw_pad_io_24_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } output_en; + } padframe_xheep_config_reg2hw_pad_io_25_cfg_reg_t; + + typedef struct packed { + logic q; + } padframe_xheep_config_reg2hw_pad_io_25_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } output_en; + } padframe_xheep_config_reg2hw_pad_io_26_cfg_reg_t; + + typedef struct packed { + logic q; + } padframe_xheep_config_reg2hw_pad_io_26_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } output_en; + } padframe_xheep_config_reg2hw_pad_io_27_cfg_reg_t; + + typedef struct packed { + logic q; + } padframe_xheep_config_reg2hw_pad_io_27_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } output_en; + } padframe_xheep_config_reg2hw_pad_io_28_cfg_reg_t; + + typedef struct packed { + logic q; + } padframe_xheep_config_reg2hw_pad_io_28_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } output_en; + } padframe_xheep_config_reg2hw_pad_io_29_cfg_reg_t; + + typedef struct packed { + logic q; + } padframe_xheep_config_reg2hw_pad_io_29_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } output_en; + } padframe_xheep_config_reg2hw_pad_io_30_cfg_reg_t; + + typedef struct packed { + logic [1:0] q; + } padframe_xheep_config_reg2hw_pad_io_30_mux_sel_reg_t; + + typedef struct packed { + struct packed { + logic q; + } chip2pad; + struct packed { + logic q; + } output_en; + } padframe_xheep_config_reg2hw_pad_io_31_cfg_reg_t; + + typedef struct packed { + logic [1:0] q; + } padframe_xheep_config_reg2hw_pad_io_31_mux_sel_reg_t; + + // Register -> HW type + typedef struct packed { + padframe_xheep_config_reg2hw_info_reg_t info; // [60:29] + padframe_xheep_config_reg2hw_pad_io_23_cfg_reg_t pad_io_23_cfg; // [28:27] + padframe_xheep_config_reg2hw_pad_io_23_mux_sel_reg_t pad_io_23_mux_sel; // [26:26] + padframe_xheep_config_reg2hw_pad_io_24_cfg_reg_t pad_io_24_cfg; // [25:24] + padframe_xheep_config_reg2hw_pad_io_24_mux_sel_reg_t pad_io_24_mux_sel; // [23:23] + padframe_xheep_config_reg2hw_pad_io_25_cfg_reg_t pad_io_25_cfg; // [22:21] + padframe_xheep_config_reg2hw_pad_io_25_mux_sel_reg_t pad_io_25_mux_sel; // [20:20] + padframe_xheep_config_reg2hw_pad_io_26_cfg_reg_t pad_io_26_cfg; // [19:18] + padframe_xheep_config_reg2hw_pad_io_26_mux_sel_reg_t pad_io_26_mux_sel; // [17:17] + padframe_xheep_config_reg2hw_pad_io_27_cfg_reg_t pad_io_27_cfg; // [16:15] + padframe_xheep_config_reg2hw_pad_io_27_mux_sel_reg_t pad_io_27_mux_sel; // [14:14] + padframe_xheep_config_reg2hw_pad_io_28_cfg_reg_t pad_io_28_cfg; // [13:12] + padframe_xheep_config_reg2hw_pad_io_28_mux_sel_reg_t pad_io_28_mux_sel; // [11:11] + padframe_xheep_config_reg2hw_pad_io_29_cfg_reg_t pad_io_29_cfg; // [10:9] + padframe_xheep_config_reg2hw_pad_io_29_mux_sel_reg_t pad_io_29_mux_sel; // [8:8] + padframe_xheep_config_reg2hw_pad_io_30_cfg_reg_t pad_io_30_cfg; // [7:6] + padframe_xheep_config_reg2hw_pad_io_30_mux_sel_reg_t pad_io_30_mux_sel; // [5:4] + padframe_xheep_config_reg2hw_pad_io_31_cfg_reg_t pad_io_31_cfg; // [3:2] + padframe_xheep_config_reg2hw_pad_io_31_mux_sel_reg_t pad_io_31_mux_sel; // [1:0] + } padframe_xheep_config_reg2hw_t; + + // Register offsets + parameter logic [BlockAw-1:0] PADFRAME_XHEEP_CONFIG_INFO_OFFSET = 7'h 0; + parameter logic [BlockAw-1:0] PADFRAME_XHEEP_CONFIG_PAD_IO_23_CFG_OFFSET = 7'h 4; + parameter logic [BlockAw-1:0] PADFRAME_XHEEP_CONFIG_PAD_IO_23_MUX_SEL_OFFSET = 7'h 8; + parameter logic [BlockAw-1:0] PADFRAME_XHEEP_CONFIG_PAD_IO_24_CFG_OFFSET = 7'h c; + parameter logic [BlockAw-1:0] PADFRAME_XHEEP_CONFIG_PAD_IO_24_MUX_SEL_OFFSET = 7'h 10; + parameter logic [BlockAw-1:0] PADFRAME_XHEEP_CONFIG_PAD_IO_25_CFG_OFFSET = 7'h 14; + parameter logic [BlockAw-1:0] PADFRAME_XHEEP_CONFIG_PAD_IO_25_MUX_SEL_OFFSET = 7'h 18; + parameter logic [BlockAw-1:0] PADFRAME_XHEEP_CONFIG_PAD_IO_26_CFG_OFFSET = 7'h 1c; + parameter logic [BlockAw-1:0] PADFRAME_XHEEP_CONFIG_PAD_IO_26_MUX_SEL_OFFSET = 7'h 20; + parameter logic [BlockAw-1:0] PADFRAME_XHEEP_CONFIG_PAD_IO_27_CFG_OFFSET = 7'h 24; + parameter logic [BlockAw-1:0] PADFRAME_XHEEP_CONFIG_PAD_IO_27_MUX_SEL_OFFSET = 7'h 28; + parameter logic [BlockAw-1:0] PADFRAME_XHEEP_CONFIG_PAD_IO_28_CFG_OFFSET = 7'h 2c; + parameter logic [BlockAw-1:0] PADFRAME_XHEEP_CONFIG_PAD_IO_28_MUX_SEL_OFFSET = 7'h 30; + parameter logic [BlockAw-1:0] PADFRAME_XHEEP_CONFIG_PAD_IO_29_CFG_OFFSET = 7'h 34; + parameter logic [BlockAw-1:0] PADFRAME_XHEEP_CONFIG_PAD_IO_29_MUX_SEL_OFFSET = 7'h 38; + parameter logic [BlockAw-1:0] PADFRAME_XHEEP_CONFIG_PAD_IO_30_CFG_OFFSET = 7'h 3c; + parameter logic [BlockAw-1:0] PADFRAME_XHEEP_CONFIG_PAD_IO_30_MUX_SEL_OFFSET = 7'h 40; + parameter logic [BlockAw-1:0] PADFRAME_XHEEP_CONFIG_PAD_IO_31_CFG_OFFSET = 7'h 44; + parameter logic [BlockAw-1:0] PADFRAME_XHEEP_CONFIG_PAD_IO_31_MUX_SEL_OFFSET = 7'h 48; + + // Register index + typedef enum int { + PADFRAME_XHEEP_CONFIG_INFO, + PADFRAME_XHEEP_CONFIG_PAD_IO_23_CFG, + PADFRAME_XHEEP_CONFIG_PAD_IO_23_MUX_SEL, + PADFRAME_XHEEP_CONFIG_PAD_IO_24_CFG, + PADFRAME_XHEEP_CONFIG_PAD_IO_24_MUX_SEL, + PADFRAME_XHEEP_CONFIG_PAD_IO_25_CFG, + PADFRAME_XHEEP_CONFIG_PAD_IO_25_MUX_SEL, + PADFRAME_XHEEP_CONFIG_PAD_IO_26_CFG, + PADFRAME_XHEEP_CONFIG_PAD_IO_26_MUX_SEL, + PADFRAME_XHEEP_CONFIG_PAD_IO_27_CFG, + PADFRAME_XHEEP_CONFIG_PAD_IO_27_MUX_SEL, + PADFRAME_XHEEP_CONFIG_PAD_IO_28_CFG, + PADFRAME_XHEEP_CONFIG_PAD_IO_28_MUX_SEL, + PADFRAME_XHEEP_CONFIG_PAD_IO_29_CFG, + PADFRAME_XHEEP_CONFIG_PAD_IO_29_MUX_SEL, + PADFRAME_XHEEP_CONFIG_PAD_IO_30_CFG, + PADFRAME_XHEEP_CONFIG_PAD_IO_30_MUX_SEL, + PADFRAME_XHEEP_CONFIG_PAD_IO_31_CFG, + PADFRAME_XHEEP_CONFIG_PAD_IO_31_MUX_SEL + } padframe_xheep_config_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] PADFRAME_XHEEP_CONFIG_PERMIT [19] = '{ + 4'b 1111, // index[ 0] PADFRAME_XHEEP_CONFIG_INFO + 4'b 0001, // index[ 1] PADFRAME_XHEEP_CONFIG_PAD_IO_23_CFG + 4'b 0001, // index[ 2] PADFRAME_XHEEP_CONFIG_PAD_IO_23_MUX_SEL + 4'b 0001, // index[ 3] PADFRAME_XHEEP_CONFIG_PAD_IO_24_CFG + 4'b 0001, // index[ 4] PADFRAME_XHEEP_CONFIG_PAD_IO_24_MUX_SEL + 4'b 0001, // index[ 5] PADFRAME_XHEEP_CONFIG_PAD_IO_25_CFG + 4'b 0001, // index[ 6] PADFRAME_XHEEP_CONFIG_PAD_IO_25_MUX_SEL + 4'b 0001, // index[ 7] PADFRAME_XHEEP_CONFIG_PAD_IO_26_CFG + 4'b 0001, // index[ 8] PADFRAME_XHEEP_CONFIG_PAD_IO_26_MUX_SEL + 4'b 0001, // index[ 9] PADFRAME_XHEEP_CONFIG_PAD_IO_27_CFG + 4'b 0001, // index[10] PADFRAME_XHEEP_CONFIG_PAD_IO_27_MUX_SEL + 4'b 0001, // index[11] PADFRAME_XHEEP_CONFIG_PAD_IO_28_CFG + 4'b 0001, // index[12] PADFRAME_XHEEP_CONFIG_PAD_IO_28_MUX_SEL + 4'b 0001, // index[13] PADFRAME_XHEEP_CONFIG_PAD_IO_29_CFG + 4'b 0001, // index[14] PADFRAME_XHEEP_CONFIG_PAD_IO_29_MUX_SEL + 4'b 0001, // index[15] PADFRAME_XHEEP_CONFIG_PAD_IO_30_CFG + 4'b 0001, // index[16] PADFRAME_XHEEP_CONFIG_PAD_IO_30_MUX_SEL + 4'b 0001, // index[17] PADFRAME_XHEEP_CONFIG_PAD_IO_31_CFG + 4'b 0001 // index[18] PADFRAME_XHEEP_CONFIG_PAD_IO_31_MUX_SEL + }; + +endpackage + diff --git a/hw/system/padframe/src/padframe_xheep_config_reg_top.sv b/hw/system/padframe/src/padframe_xheep_config_reg_top.sv new file mode 100644 index 000000000..942e2e0ce --- /dev/null +++ b/hw/system/padframe/src/padframe_xheep_config_reg_top.sv @@ -0,0 +1,1177 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + + +`include "common_cells/assertions.svh" + +module padframe_xheep_config_reg_top #( + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic, + parameter int AW = 7 +) ( + input clk_i, + input rst_ni, + input reg_req_t reg_req_i, + output reg_rsp_t reg_rsp_o, + // To HW + output padframe_xheep_config_reg_pkg::padframe_xheep_config_reg2hw_t reg2hw, // Write + + + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + + import padframe_xheep_config_reg_pkg::* ; + + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + + // Below register interface can be changed + reg_req_t reg_intf_req; + reg_rsp_t reg_intf_rsp; + + + assign reg_intf_req = reg_req_i; + assign reg_rsp_o = reg_intf_rsp; + + + assign reg_we = reg_intf_req.valid & reg_intf_req.write; + assign reg_re = reg_intf_req.valid & ~reg_intf_req.write; + assign reg_addr = reg_intf_req.addr; + assign reg_wdata = reg_intf_req.wdata; + assign reg_be = reg_intf_req.wstrb; + assign reg_intf_rsp.rdata = reg_rdata; + assign reg_intf_rsp.error = reg_error; + assign reg_intf_rsp.ready = 1'b1; + + assign reg_rdata = reg_rdata_next ; + assign reg_error = (devmode_i & addrmiss) | wr_err; + + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic [15:0] info_hw_version_qs; + logic [15:0] info_padcount_qs; + logic pad_io_23_cfg_chip2pad_qs; + logic pad_io_23_cfg_chip2pad_wd; + logic pad_io_23_cfg_chip2pad_we; + logic pad_io_23_cfg_output_en_qs; + logic pad_io_23_cfg_output_en_wd; + logic pad_io_23_cfg_output_en_we; + logic pad_io_23_mux_sel_qs; + logic pad_io_23_mux_sel_wd; + logic pad_io_23_mux_sel_we; + logic pad_io_24_cfg_chip2pad_qs; + logic pad_io_24_cfg_chip2pad_wd; + logic pad_io_24_cfg_chip2pad_we; + logic pad_io_24_cfg_output_en_qs; + logic pad_io_24_cfg_output_en_wd; + logic pad_io_24_cfg_output_en_we; + logic pad_io_24_mux_sel_qs; + logic pad_io_24_mux_sel_wd; + logic pad_io_24_mux_sel_we; + logic pad_io_25_cfg_chip2pad_qs; + logic pad_io_25_cfg_chip2pad_wd; + logic pad_io_25_cfg_chip2pad_we; + logic pad_io_25_cfg_output_en_qs; + logic pad_io_25_cfg_output_en_wd; + logic pad_io_25_cfg_output_en_we; + logic pad_io_25_mux_sel_qs; + logic pad_io_25_mux_sel_wd; + logic pad_io_25_mux_sel_we; + logic pad_io_26_cfg_chip2pad_qs; + logic pad_io_26_cfg_chip2pad_wd; + logic pad_io_26_cfg_chip2pad_we; + logic pad_io_26_cfg_output_en_qs; + logic pad_io_26_cfg_output_en_wd; + logic pad_io_26_cfg_output_en_we; + logic pad_io_26_mux_sel_qs; + logic pad_io_26_mux_sel_wd; + logic pad_io_26_mux_sel_we; + logic pad_io_27_cfg_chip2pad_qs; + logic pad_io_27_cfg_chip2pad_wd; + logic pad_io_27_cfg_chip2pad_we; + logic pad_io_27_cfg_output_en_qs; + logic pad_io_27_cfg_output_en_wd; + logic pad_io_27_cfg_output_en_we; + logic pad_io_27_mux_sel_qs; + logic pad_io_27_mux_sel_wd; + logic pad_io_27_mux_sel_we; + logic pad_io_28_cfg_chip2pad_qs; + logic pad_io_28_cfg_chip2pad_wd; + logic pad_io_28_cfg_chip2pad_we; + logic pad_io_28_cfg_output_en_qs; + logic pad_io_28_cfg_output_en_wd; + logic pad_io_28_cfg_output_en_we; + logic pad_io_28_mux_sel_qs; + logic pad_io_28_mux_sel_wd; + logic pad_io_28_mux_sel_we; + logic pad_io_29_cfg_chip2pad_qs; + logic pad_io_29_cfg_chip2pad_wd; + logic pad_io_29_cfg_chip2pad_we; + logic pad_io_29_cfg_output_en_qs; + logic pad_io_29_cfg_output_en_wd; + logic pad_io_29_cfg_output_en_we; + logic pad_io_29_mux_sel_qs; + logic pad_io_29_mux_sel_wd; + logic pad_io_29_mux_sel_we; + logic pad_io_30_cfg_chip2pad_qs; + logic pad_io_30_cfg_chip2pad_wd; + logic pad_io_30_cfg_chip2pad_we; + logic pad_io_30_cfg_output_en_qs; + logic pad_io_30_cfg_output_en_wd; + logic pad_io_30_cfg_output_en_we; + logic [1:0] pad_io_30_mux_sel_qs; + logic [1:0] pad_io_30_mux_sel_wd; + logic pad_io_30_mux_sel_we; + logic pad_io_31_cfg_chip2pad_qs; + logic pad_io_31_cfg_chip2pad_wd; + logic pad_io_31_cfg_chip2pad_we; + logic pad_io_31_cfg_output_en_qs; + logic pad_io_31_cfg_output_en_wd; + logic pad_io_31_cfg_output_en_we; + logic [1:0] pad_io_31_mux_sel_qs; + logic [1:0] pad_io_31_mux_sel_wd; + logic pad_io_31_mux_sel_we; + + // Register instances + // R[info]: V(False) + + // F[hw_version]: 15:0 + prim_subreg #( + .DW (16), + .SWACCESS("RO"), + .RESVAL (16'h2) + ) u_info_hw_version ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.info.hw_version.q ), + + // to register interface (read) + .qs (info_hw_version_qs) + ); + + + // F[padcount]: 31:16 + prim_subreg #( + .DW (16), + .SWACCESS("RO"), + .RESVAL (16'h9) + ) u_info_padcount ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + .we (1'b0), + .wd ('0 ), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.info.padcount.q ), + + // to register interface (read) + .qs (info_padcount_qs) + ); + + + // R[pad_io_23_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io_23_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_23_cfg_chip2pad_we), + .wd (pad_io_23_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_23_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io_23_cfg_chip2pad_qs) + ); + + + // F[output_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io_23_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_23_cfg_output_en_we), + .wd (pad_io_23_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_23_cfg.output_en.q ), + + // to register interface (read) + .qs (pad_io_23_cfg_output_en_qs) + ); + + + // R[pad_io_23_mux_sel]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io_23_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_23_mux_sel_we), + .wd (pad_io_23_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_23_mux_sel.q ), + + // to register interface (read) + .qs (pad_io_23_mux_sel_qs) + ); + + + // R[pad_io_24_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io_24_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_24_cfg_chip2pad_we), + .wd (pad_io_24_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_24_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io_24_cfg_chip2pad_qs) + ); + + + // F[output_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io_24_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_24_cfg_output_en_we), + .wd (pad_io_24_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_24_cfg.output_en.q ), + + // to register interface (read) + .qs (pad_io_24_cfg_output_en_qs) + ); + + + // R[pad_io_24_mux_sel]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io_24_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_24_mux_sel_we), + .wd (pad_io_24_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_24_mux_sel.q ), + + // to register interface (read) + .qs (pad_io_24_mux_sel_qs) + ); + + + // R[pad_io_25_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io_25_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_25_cfg_chip2pad_we), + .wd (pad_io_25_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_25_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io_25_cfg_chip2pad_qs) + ); + + + // F[output_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io_25_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_25_cfg_output_en_we), + .wd (pad_io_25_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_25_cfg.output_en.q ), + + // to register interface (read) + .qs (pad_io_25_cfg_output_en_qs) + ); + + + // R[pad_io_25_mux_sel]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io_25_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_25_mux_sel_we), + .wd (pad_io_25_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_25_mux_sel.q ), + + // to register interface (read) + .qs (pad_io_25_mux_sel_qs) + ); + + + // R[pad_io_26_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io_26_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_26_cfg_chip2pad_we), + .wd (pad_io_26_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_26_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io_26_cfg_chip2pad_qs) + ); + + + // F[output_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io_26_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_26_cfg_output_en_we), + .wd (pad_io_26_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_26_cfg.output_en.q ), + + // to register interface (read) + .qs (pad_io_26_cfg_output_en_qs) + ); + + + // R[pad_io_26_mux_sel]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io_26_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_26_mux_sel_we), + .wd (pad_io_26_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_26_mux_sel.q ), + + // to register interface (read) + .qs (pad_io_26_mux_sel_qs) + ); + + + // R[pad_io_27_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io_27_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_27_cfg_chip2pad_we), + .wd (pad_io_27_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_27_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io_27_cfg_chip2pad_qs) + ); + + + // F[output_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io_27_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_27_cfg_output_en_we), + .wd (pad_io_27_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_27_cfg.output_en.q ), + + // to register interface (read) + .qs (pad_io_27_cfg_output_en_qs) + ); + + + // R[pad_io_27_mux_sel]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io_27_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_27_mux_sel_we), + .wd (pad_io_27_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_27_mux_sel.q ), + + // to register interface (read) + .qs (pad_io_27_mux_sel_qs) + ); + + + // R[pad_io_28_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io_28_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_28_cfg_chip2pad_we), + .wd (pad_io_28_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_28_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io_28_cfg_chip2pad_qs) + ); + + + // F[output_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io_28_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_28_cfg_output_en_we), + .wd (pad_io_28_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_28_cfg.output_en.q ), + + // to register interface (read) + .qs (pad_io_28_cfg_output_en_qs) + ); + + + // R[pad_io_28_mux_sel]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io_28_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_28_mux_sel_we), + .wd (pad_io_28_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_28_mux_sel.q ), + + // to register interface (read) + .qs (pad_io_28_mux_sel_qs) + ); + + + // R[pad_io_29_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io_29_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_29_cfg_chip2pad_we), + .wd (pad_io_29_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_29_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io_29_cfg_chip2pad_qs) + ); + + + // F[output_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io_29_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_29_cfg_output_en_we), + .wd (pad_io_29_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_29_cfg.output_en.q ), + + // to register interface (read) + .qs (pad_io_29_cfg_output_en_qs) + ); + + + // R[pad_io_29_mux_sel]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_pad_io_29_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_29_mux_sel_we), + .wd (pad_io_29_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_29_mux_sel.q ), + + // to register interface (read) + .qs (pad_io_29_mux_sel_qs) + ); + + + // R[pad_io_30_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io_30_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_30_cfg_chip2pad_we), + .wd (pad_io_30_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_30_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io_30_cfg_chip2pad_qs) + ); + + + // F[output_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io_30_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_30_cfg_output_en_we), + .wd (pad_io_30_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_30_cfg.output_en.q ), + + // to register interface (read) + .qs (pad_io_30_cfg_output_en_qs) + ); + + + // R[pad_io_30_mux_sel]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_pad_io_30_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_30_mux_sel_we), + .wd (pad_io_30_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_30_mux_sel.q ), + + // to register interface (read) + .qs (pad_io_30_mux_sel_qs) + ); + + + // R[pad_io_31_cfg]: V(False) + + // F[chip2pad]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io_31_cfg_chip2pad ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_31_cfg_chip2pad_we), + .wd (pad_io_31_cfg_chip2pad_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_31_cfg.chip2pad.q ), + + // to register interface (read) + .qs (pad_io_31_cfg_chip2pad_qs) + ); + + + // F[output_en]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_pad_io_31_cfg_output_en ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_31_cfg_output_en_we), + .wd (pad_io_31_cfg_output_en_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_31_cfg.output_en.q ), + + // to register interface (read) + .qs (pad_io_31_cfg_output_en_qs) + ); + + + // R[pad_io_31_mux_sel]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h2) + ) u_pad_io_31_mux_sel ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (pad_io_31_mux_sel_we), + .wd (pad_io_31_mux_sel_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.pad_io_31_mux_sel.q ), + + // to register interface (read) + .qs (pad_io_31_mux_sel_qs) + ); + + + + + logic [18:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == PADFRAME_XHEEP_CONFIG_INFO_OFFSET); + addr_hit[ 1] = (reg_addr == PADFRAME_XHEEP_CONFIG_PAD_IO_23_CFG_OFFSET); + addr_hit[ 2] = (reg_addr == PADFRAME_XHEEP_CONFIG_PAD_IO_23_MUX_SEL_OFFSET); + addr_hit[ 3] = (reg_addr == PADFRAME_XHEEP_CONFIG_PAD_IO_24_CFG_OFFSET); + addr_hit[ 4] = (reg_addr == PADFRAME_XHEEP_CONFIG_PAD_IO_24_MUX_SEL_OFFSET); + addr_hit[ 5] = (reg_addr == PADFRAME_XHEEP_CONFIG_PAD_IO_25_CFG_OFFSET); + addr_hit[ 6] = (reg_addr == PADFRAME_XHEEP_CONFIG_PAD_IO_25_MUX_SEL_OFFSET); + addr_hit[ 7] = (reg_addr == PADFRAME_XHEEP_CONFIG_PAD_IO_26_CFG_OFFSET); + addr_hit[ 8] = (reg_addr == PADFRAME_XHEEP_CONFIG_PAD_IO_26_MUX_SEL_OFFSET); + addr_hit[ 9] = (reg_addr == PADFRAME_XHEEP_CONFIG_PAD_IO_27_CFG_OFFSET); + addr_hit[10] = (reg_addr == PADFRAME_XHEEP_CONFIG_PAD_IO_27_MUX_SEL_OFFSET); + addr_hit[11] = (reg_addr == PADFRAME_XHEEP_CONFIG_PAD_IO_28_CFG_OFFSET); + addr_hit[12] = (reg_addr == PADFRAME_XHEEP_CONFIG_PAD_IO_28_MUX_SEL_OFFSET); + addr_hit[13] = (reg_addr == PADFRAME_XHEEP_CONFIG_PAD_IO_29_CFG_OFFSET); + addr_hit[14] = (reg_addr == PADFRAME_XHEEP_CONFIG_PAD_IO_29_MUX_SEL_OFFSET); + addr_hit[15] = (reg_addr == PADFRAME_XHEEP_CONFIG_PAD_IO_30_CFG_OFFSET); + addr_hit[16] = (reg_addr == PADFRAME_XHEEP_CONFIG_PAD_IO_30_MUX_SEL_OFFSET); + addr_hit[17] = (reg_addr == PADFRAME_XHEEP_CONFIG_PAD_IO_31_CFG_OFFSET); + addr_hit[18] = (reg_addr == PADFRAME_XHEEP_CONFIG_PAD_IO_31_MUX_SEL_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(PADFRAME_XHEEP_CONFIG_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(PADFRAME_XHEEP_CONFIG_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(PADFRAME_XHEEP_CONFIG_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(PADFRAME_XHEEP_CONFIG_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(PADFRAME_XHEEP_CONFIG_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(PADFRAME_XHEEP_CONFIG_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(PADFRAME_XHEEP_CONFIG_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(PADFRAME_XHEEP_CONFIG_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(PADFRAME_XHEEP_CONFIG_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(PADFRAME_XHEEP_CONFIG_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(PADFRAME_XHEEP_CONFIG_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(PADFRAME_XHEEP_CONFIG_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(PADFRAME_XHEEP_CONFIG_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(PADFRAME_XHEEP_CONFIG_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(PADFRAME_XHEEP_CONFIG_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(PADFRAME_XHEEP_CONFIG_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(PADFRAME_XHEEP_CONFIG_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(PADFRAME_XHEEP_CONFIG_PERMIT[17] & ~reg_be))) | + (addr_hit[18] & (|(PADFRAME_XHEEP_CONFIG_PERMIT[18] & ~reg_be))))); + end + + assign pad_io_23_cfg_chip2pad_we = addr_hit[1] & reg_we & !reg_error; + assign pad_io_23_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io_23_cfg_output_en_we = addr_hit[1] & reg_we & !reg_error; + assign pad_io_23_cfg_output_en_wd = reg_wdata[1]; + + assign pad_io_23_mux_sel_we = addr_hit[2] & reg_we & !reg_error; + assign pad_io_23_mux_sel_wd = reg_wdata[0]; + + assign pad_io_24_cfg_chip2pad_we = addr_hit[3] & reg_we & !reg_error; + assign pad_io_24_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io_24_cfg_output_en_we = addr_hit[3] & reg_we & !reg_error; + assign pad_io_24_cfg_output_en_wd = reg_wdata[1]; + + assign pad_io_24_mux_sel_we = addr_hit[4] & reg_we & !reg_error; + assign pad_io_24_mux_sel_wd = reg_wdata[0]; + + assign pad_io_25_cfg_chip2pad_we = addr_hit[5] & reg_we & !reg_error; + assign pad_io_25_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io_25_cfg_output_en_we = addr_hit[5] & reg_we & !reg_error; + assign pad_io_25_cfg_output_en_wd = reg_wdata[1]; + + assign pad_io_25_mux_sel_we = addr_hit[6] & reg_we & !reg_error; + assign pad_io_25_mux_sel_wd = reg_wdata[0]; + + assign pad_io_26_cfg_chip2pad_we = addr_hit[7] & reg_we & !reg_error; + assign pad_io_26_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io_26_cfg_output_en_we = addr_hit[7] & reg_we & !reg_error; + assign pad_io_26_cfg_output_en_wd = reg_wdata[1]; + + assign pad_io_26_mux_sel_we = addr_hit[8] & reg_we & !reg_error; + assign pad_io_26_mux_sel_wd = reg_wdata[0]; + + assign pad_io_27_cfg_chip2pad_we = addr_hit[9] & reg_we & !reg_error; + assign pad_io_27_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io_27_cfg_output_en_we = addr_hit[9] & reg_we & !reg_error; + assign pad_io_27_cfg_output_en_wd = reg_wdata[1]; + + assign pad_io_27_mux_sel_we = addr_hit[10] & reg_we & !reg_error; + assign pad_io_27_mux_sel_wd = reg_wdata[0]; + + assign pad_io_28_cfg_chip2pad_we = addr_hit[11] & reg_we & !reg_error; + assign pad_io_28_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io_28_cfg_output_en_we = addr_hit[11] & reg_we & !reg_error; + assign pad_io_28_cfg_output_en_wd = reg_wdata[1]; + + assign pad_io_28_mux_sel_we = addr_hit[12] & reg_we & !reg_error; + assign pad_io_28_mux_sel_wd = reg_wdata[0]; + + assign pad_io_29_cfg_chip2pad_we = addr_hit[13] & reg_we & !reg_error; + assign pad_io_29_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io_29_cfg_output_en_we = addr_hit[13] & reg_we & !reg_error; + assign pad_io_29_cfg_output_en_wd = reg_wdata[1]; + + assign pad_io_29_mux_sel_we = addr_hit[14] & reg_we & !reg_error; + assign pad_io_29_mux_sel_wd = reg_wdata[0]; + + assign pad_io_30_cfg_chip2pad_we = addr_hit[15] & reg_we & !reg_error; + assign pad_io_30_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io_30_cfg_output_en_we = addr_hit[15] & reg_we & !reg_error; + assign pad_io_30_cfg_output_en_wd = reg_wdata[1]; + + assign pad_io_30_mux_sel_we = addr_hit[16] & reg_we & !reg_error; + assign pad_io_30_mux_sel_wd = reg_wdata[1:0]; + + assign pad_io_31_cfg_chip2pad_we = addr_hit[17] & reg_we & !reg_error; + assign pad_io_31_cfg_chip2pad_wd = reg_wdata[0]; + + assign pad_io_31_cfg_output_en_we = addr_hit[17] & reg_we & !reg_error; + assign pad_io_31_cfg_output_en_wd = reg_wdata[1]; + + assign pad_io_31_mux_sel_we = addr_hit[18] & reg_we & !reg_error; + assign pad_io_31_mux_sel_wd = reg_wdata[1:0]; + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[15:0] = info_hw_version_qs; + reg_rdata_next[31:16] = info_padcount_qs; + end + + addr_hit[1]: begin + reg_rdata_next[0] = pad_io_23_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io_23_cfg_output_en_qs; + end + + addr_hit[2]: begin + reg_rdata_next[0] = pad_io_23_mux_sel_qs; + end + + addr_hit[3]: begin + reg_rdata_next[0] = pad_io_24_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io_24_cfg_output_en_qs; + end + + addr_hit[4]: begin + reg_rdata_next[0] = pad_io_24_mux_sel_qs; + end + + addr_hit[5]: begin + reg_rdata_next[0] = pad_io_25_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io_25_cfg_output_en_qs; + end + + addr_hit[6]: begin + reg_rdata_next[0] = pad_io_25_mux_sel_qs; + end + + addr_hit[7]: begin + reg_rdata_next[0] = pad_io_26_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io_26_cfg_output_en_qs; + end + + addr_hit[8]: begin + reg_rdata_next[0] = pad_io_26_mux_sel_qs; + end + + addr_hit[9]: begin + reg_rdata_next[0] = pad_io_27_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io_27_cfg_output_en_qs; + end + + addr_hit[10]: begin + reg_rdata_next[0] = pad_io_27_mux_sel_qs; + end + + addr_hit[11]: begin + reg_rdata_next[0] = pad_io_28_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io_28_cfg_output_en_qs; + end + + addr_hit[12]: begin + reg_rdata_next[0] = pad_io_28_mux_sel_qs; + end + + addr_hit[13]: begin + reg_rdata_next[0] = pad_io_29_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io_29_cfg_output_en_qs; + end + + addr_hit[14]: begin + reg_rdata_next[0] = pad_io_29_mux_sel_qs; + end + + addr_hit[15]: begin + reg_rdata_next[0] = pad_io_30_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io_30_cfg_output_en_qs; + end + + addr_hit[16]: begin + reg_rdata_next[1:0] = pad_io_30_mux_sel_qs; + end + + addr_hit[17]: begin + reg_rdata_next[0] = pad_io_31_cfg_chip2pad_qs; + reg_rdata_next[1] = pad_io_31_cfg_output_en_qs; + end + + addr_hit[18]: begin + reg_rdata_next[1:0] = pad_io_31_mux_sel_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) + +endmodule diff --git a/hw/system/padframe/src/padframe_xheep_muxer.sv b/hw/system/padframe/src/padframe_xheep_muxer.sv new file mode 100644 index 000000000..614188df7 --- /dev/null +++ b/hw/system/padframe/src/padframe_xheep_muxer.sv @@ -0,0 +1,565 @@ +// File auto-generated by Padrick 0.3.1.post0.dev2+ge09286c +module padframe_xheep_muxer + import pkg_internal_padframe_xheep::*; + import pkg_padframe::*; + import padframe_xheep_config_reg_pkg::*; +#( + parameter type req_t = logic, // reg_interface request type + parameter type resp_t = logic // reg_interface response type +) ( + input logic clk_i, + input logic rst_ni, + input pad_domain_xheep_ports_soc2pad_t port_signals_soc2pad_i, + output pad_domain_xheep_ports_pad2soc_t port_signals_pad2soc_o, + output mux_to_pads_t mux_to_pads_o, + input pads_to_mux_t pads_to_mux_i, + // Configuration interface using register_interface protocol + input req_t config_req_i, + output resp_t config_rsp_o +); + // Connections between register file and pads + padframe_xheep_config_reg2hw_t s_reg2hw; + + // Register File Instantiation + padframe_xheep_config_reg_top #( + .reg_req_t(req_t), + .reg_rsp_t(resp_t) + ) i_regfile ( + .clk_i, + .rst_ni, + .reg2hw(s_reg2hw), + .reg_req_i(config_req_i), + .reg_rsp_o(config_rsp_o), + .devmode_i(1'b1) + ); + + + // SoC -> Pad Multiplex Logic + // Pad pad_io_23 + always_comb begin + unique case (s_reg2hw.pad_io_23_mux_sel.q) + PAD_MUX_GROUP_PAD23_SEL_DEFAULT: begin + mux_to_pads_o.pad_io_23.chip2pad = s_reg2hw.pad_io_23_cfg.chip2pad.q; + mux_to_pads_o.pad_io_23.output_en = s_reg2hw.pad_io_23_cfg.output_en.q; + end + PAD_MUX_GROUP_PAD23_SEL_SPI2_SPI2_CS_00: begin + mux_to_pads_o.pad_io_23.chip2pad = port_signals_soc2pad_i.spi2.spi2_cs_00_i; + mux_to_pads_o.pad_io_23.output_en = port_signals_soc2pad_i.spi2.spi2_cs_00_oe_i; + end + default: begin + mux_to_pads_o.pad_io_23.chip2pad = s_reg2hw.pad_io_23_cfg.chip2pad.q; + mux_to_pads_o.pad_io_23.output_en = s_reg2hw.pad_io_23_cfg.output_en.q; + end + endcase + end // always_comb + + // Pad pad_io_24 + always_comb begin + unique case (s_reg2hw.pad_io_24_mux_sel.q) + PAD_MUX_GROUP_PAD24_SEL_DEFAULT: begin + mux_to_pads_o.pad_io_24.chip2pad = s_reg2hw.pad_io_24_cfg.chip2pad.q; + mux_to_pads_o.pad_io_24.output_en = s_reg2hw.pad_io_24_cfg.output_en.q; + end + PAD_MUX_GROUP_PAD24_SEL_SPI2_SPI2_CS_01: begin + mux_to_pads_o.pad_io_24.chip2pad = port_signals_soc2pad_i.spi2.spi2_cs_01_i; + mux_to_pads_o.pad_io_24.output_en = port_signals_soc2pad_i.spi2.spi2_cs_01_oe_i; + end + default: begin + mux_to_pads_o.pad_io_24.chip2pad = s_reg2hw.pad_io_24_cfg.chip2pad.q; + mux_to_pads_o.pad_io_24.output_en = s_reg2hw.pad_io_24_cfg.output_en.q; + end + endcase + end // always_comb + + // Pad pad_io_25 + always_comb begin + unique case (s_reg2hw.pad_io_25_mux_sel.q) + PAD_MUX_GROUP_PAD25_SEL_DEFAULT: begin + mux_to_pads_o.pad_io_25.chip2pad = s_reg2hw.pad_io_25_cfg.chip2pad.q; + mux_to_pads_o.pad_io_25.output_en = s_reg2hw.pad_io_25_cfg.output_en.q; + end + PAD_MUX_GROUP_PAD25_SEL_SPI2_SPI2_SCK: begin + mux_to_pads_o.pad_io_25.chip2pad = port_signals_soc2pad_i.spi2.spi2_sck_i; + mux_to_pads_o.pad_io_25.output_en = port_signals_soc2pad_i.spi2.spi2_sck_oe_i; + end + default: begin + mux_to_pads_o.pad_io_25.chip2pad = s_reg2hw.pad_io_25_cfg.chip2pad.q; + mux_to_pads_o.pad_io_25.output_en = s_reg2hw.pad_io_25_cfg.output_en.q; + end + endcase + end // always_comb + + // Pad pad_io_26 + always_comb begin + unique case (s_reg2hw.pad_io_26_mux_sel.q) + PAD_MUX_GROUP_PAD26_SEL_DEFAULT: begin + mux_to_pads_o.pad_io_26.chip2pad = s_reg2hw.pad_io_26_cfg.chip2pad.q; + mux_to_pads_o.pad_io_26.output_en = s_reg2hw.pad_io_26_cfg.output_en.q; + end + PAD_MUX_GROUP_PAD26_SEL_SPI2_SPI2_SD_00: begin + mux_to_pads_o.pad_io_26.chip2pad = port_signals_soc2pad_i.spi2.spi2_sd_00_i; + mux_to_pads_o.pad_io_26.output_en = port_signals_soc2pad_i.spi2.spi2_sd_00_oe_i; + end + default: begin + mux_to_pads_o.pad_io_26.chip2pad = s_reg2hw.pad_io_26_cfg.chip2pad.q; + mux_to_pads_o.pad_io_26.output_en = s_reg2hw.pad_io_26_cfg.output_en.q; + end + endcase + end // always_comb + + // Pad pad_io_27 + always_comb begin + unique case (s_reg2hw.pad_io_27_mux_sel.q) + PAD_MUX_GROUP_PAD27_SEL_DEFAULT: begin + mux_to_pads_o.pad_io_27.chip2pad = s_reg2hw.pad_io_27_cfg.chip2pad.q; + mux_to_pads_o.pad_io_27.output_en = s_reg2hw.pad_io_27_cfg.output_en.q; + end + PAD_MUX_GROUP_PAD27_SEL_SPI2_SPI2_SD_01: begin + mux_to_pads_o.pad_io_27.chip2pad = port_signals_soc2pad_i.spi2.spi2_sd_01_i; + mux_to_pads_o.pad_io_27.output_en = port_signals_soc2pad_i.spi2.spi2_sd_01_oe_i; + end + default: begin + mux_to_pads_o.pad_io_27.chip2pad = s_reg2hw.pad_io_27_cfg.chip2pad.q; + mux_to_pads_o.pad_io_27.output_en = s_reg2hw.pad_io_27_cfg.output_en.q; + end + endcase + end // always_comb + + // Pad pad_io_28 + always_comb begin + unique case (s_reg2hw.pad_io_28_mux_sel.q) + PAD_MUX_GROUP_PAD28_SEL_DEFAULT: begin + mux_to_pads_o.pad_io_28.chip2pad = s_reg2hw.pad_io_28_cfg.chip2pad.q; + mux_to_pads_o.pad_io_28.output_en = s_reg2hw.pad_io_28_cfg.output_en.q; + end + PAD_MUX_GROUP_PAD28_SEL_SPI2_SPI2_SD_02: begin + mux_to_pads_o.pad_io_28.chip2pad = port_signals_soc2pad_i.spi2.spi2_sd_02_i; + mux_to_pads_o.pad_io_28.output_en = port_signals_soc2pad_i.spi2.spi2_sd_02_oe_i; + end + default: begin + mux_to_pads_o.pad_io_28.chip2pad = s_reg2hw.pad_io_28_cfg.chip2pad.q; + mux_to_pads_o.pad_io_28.output_en = s_reg2hw.pad_io_28_cfg.output_en.q; + end + endcase + end // always_comb + + // Pad pad_io_29 + always_comb begin + unique case (s_reg2hw.pad_io_29_mux_sel.q) + PAD_MUX_GROUP_PAD29_SEL_DEFAULT: begin + mux_to_pads_o.pad_io_29.chip2pad = s_reg2hw.pad_io_29_cfg.chip2pad.q; + mux_to_pads_o.pad_io_29.output_en = s_reg2hw.pad_io_29_cfg.output_en.q; + end + PAD_MUX_GROUP_PAD29_SEL_SPI2_SPI2_SD_03: begin + mux_to_pads_o.pad_io_29.chip2pad = port_signals_soc2pad_i.spi2.spi2_sd_03_i; + mux_to_pads_o.pad_io_29.output_en = port_signals_soc2pad_i.spi2.spi2_sd_03_oe_i; + end + default: begin + mux_to_pads_o.pad_io_29.chip2pad = s_reg2hw.pad_io_29_cfg.chip2pad.q; + mux_to_pads_o.pad_io_29.output_en = s_reg2hw.pad_io_29_cfg.output_en.q; + end + endcase + end // always_comb + + // Pad pad_io_30 + always_comb begin + unique case (s_reg2hw.pad_io_30_mux_sel.q) + PAD_MUX_GROUP_PAD30_SEL_DEFAULT: begin + mux_to_pads_o.pad_io_30.chip2pad = s_reg2hw.pad_io_30_cfg.chip2pad.q; + mux_to_pads_o.pad_io_30.output_en = s_reg2hw.pad_io_30_cfg.output_en.q; + end + PAD_MUX_GROUP_PAD30_SEL_I2C_I2C_SDA: begin + mux_to_pads_o.pad_io_30.chip2pad = port_signals_soc2pad_i.i2c.i2c_sda_i; + mux_to_pads_o.pad_io_30.output_en = port_signals_soc2pad_i.i2c.i2c_sda_oe_i; + end + PAD_MUX_GROUP_PAD30_SEL_GPIO_GPIO_30: begin + mux_to_pads_o.pad_io_30.chip2pad = port_signals_soc2pad_i.gpio.gpio_30_i; + mux_to_pads_o.pad_io_30.output_en = port_signals_soc2pad_i.gpio.gpio_30_oe_i; + end + default: begin + mux_to_pads_o.pad_io_30.chip2pad = s_reg2hw.pad_io_30_cfg.chip2pad.q; + mux_to_pads_o.pad_io_30.output_en = s_reg2hw.pad_io_30_cfg.output_en.q; + end + endcase + end // always_comb + + // Pad pad_io_31 + always_comb begin + unique case (s_reg2hw.pad_io_31_mux_sel.q) + PAD_MUX_GROUP_PAD31_SEL_DEFAULT: begin + mux_to_pads_o.pad_io_31.chip2pad = s_reg2hw.pad_io_31_cfg.chip2pad.q; + mux_to_pads_o.pad_io_31.output_en = s_reg2hw.pad_io_31_cfg.output_en.q; + end + PAD_MUX_GROUP_PAD31_SEL_I2C_I2C_SCL: begin + mux_to_pads_o.pad_io_31.chip2pad = port_signals_soc2pad_i.i2c.i2c_scl_i; + mux_to_pads_o.pad_io_31.output_en = port_signals_soc2pad_i.i2c.i2c_scl_oe_i; + end + PAD_MUX_GROUP_PAD31_SEL_GPIO_GPIO_31: begin + mux_to_pads_o.pad_io_31.chip2pad = port_signals_soc2pad_i.gpio.gpio_31_i; + mux_to_pads_o.pad_io_31.output_en = port_signals_soc2pad_i.gpio.gpio_31_oe_i; + end + default: begin + mux_to_pads_o.pad_io_31.chip2pad = s_reg2hw.pad_io_31_cfg.chip2pad.q; + mux_to_pads_o.pad_io_31.output_en = s_reg2hw.pad_io_31_cfg.output_en.q; + end + endcase + end // always_comb + + + // Pad -> SoC Multiplex Logic + // Port Group i2c + + // Port Signal i2c_scl_o + logic [0:0] port_mux_sel_i2c_i2c_scl_o_req; + logic [PORT_MUX_GROUP_PAD31_SEL_WIDTH-1:0] port_mux_sel_i2c_i2c_scl_o_arbitrated; + logic port_mux_sel_i2c_i2c_scl_o_no_connection; + + assign port_mux_sel_i2c_i2c_scl_o_req[PORT_MUX_GROUP_PAD31_SEL_PAD_IO_31] = s_reg2hw.pad_io_31_mux_sel.q == PAD_MUX_GROUP_PAD31_SEL_I2C_I2C_SCL ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_i2c_i2c_scl_o_arbiter ( + .in_i(port_mux_sel_i2c_i2c_scl_o_req), + .cnt_o(port_mux_sel_i2c_i2c_scl_o_arbitrated), + .empty_o(port_mux_sel_i2c_i2c_scl_o_no_connection) + ); + + always_comb begin + if (port_mux_sel_i2c_i2c_scl_o_no_connection) begin + port_signals_pad2soc_o.i2c.i2c_scl_o = 1'b0; + end else begin + unique case (port_mux_sel_i2c_i2c_scl_o_arbitrated) + PORT_MUX_GROUP_PAD31_SEL_PAD_IO_31: begin + port_signals_pad2soc_o.i2c.i2c_scl_o = pads_to_mux_i.pad_io_31.pad2chip; + end + default: begin + port_signals_pad2soc_o.i2c.i2c_scl_o = 1'b0; + end + endcase + end + end + + + // Port Signal i2c_sda_o + logic [0:0] port_mux_sel_i2c_i2c_sda_o_req; + logic [PORT_MUX_GROUP_PAD30_SEL_WIDTH-1:0] port_mux_sel_i2c_i2c_sda_o_arbitrated; + logic port_mux_sel_i2c_i2c_sda_o_no_connection; + + assign port_mux_sel_i2c_i2c_sda_o_req[PORT_MUX_GROUP_PAD30_SEL_PAD_IO_30] = s_reg2hw.pad_io_30_mux_sel.q == PAD_MUX_GROUP_PAD30_SEL_I2C_I2C_SDA ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_i2c_i2c_sda_o_arbiter ( + .in_i(port_mux_sel_i2c_i2c_sda_o_req), + .cnt_o(port_mux_sel_i2c_i2c_sda_o_arbitrated), + .empty_o(port_mux_sel_i2c_i2c_sda_o_no_connection) + ); + + always_comb begin + if (port_mux_sel_i2c_i2c_sda_o_no_connection) begin + port_signals_pad2soc_o.i2c.i2c_sda_o = 1'b0; + end else begin + unique case (port_mux_sel_i2c_i2c_sda_o_arbitrated) + PORT_MUX_GROUP_PAD30_SEL_PAD_IO_30: begin + port_signals_pad2soc_o.i2c.i2c_sda_o = pads_to_mux_i.pad_io_30.pad2chip; + end + default: begin + port_signals_pad2soc_o.i2c.i2c_sda_o = 1'b0; + end + endcase + end + end + + // Port Group gpio + + // Port Signal gpio_30_o + logic [0:0] port_mux_sel_gpio_gpio_30_o_req; + logic [PORT_MUX_GROUP_PAD30_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_30_o_arbitrated; + logic port_mux_sel_gpio_gpio_30_o_no_connection; + + assign port_mux_sel_gpio_gpio_30_o_req[PORT_MUX_GROUP_PAD30_SEL_PAD_IO_30] = s_reg2hw.pad_io_30_mux_sel.q == PAD_MUX_GROUP_PAD30_SEL_GPIO_GPIO_30 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_30_o_arbiter ( + .in_i(port_mux_sel_gpio_gpio_30_o_req), + .cnt_o(port_mux_sel_gpio_gpio_30_o_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_30_o_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_30_o_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_30_o = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_30_o_arbitrated) + PORT_MUX_GROUP_PAD30_SEL_PAD_IO_30: begin + port_signals_pad2soc_o.gpio.gpio_30_o = pads_to_mux_i.pad_io_30.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_30_o = 1'b0; + end + endcase + end + end + + + // Port Signal gpio_31_o + logic [0:0] port_mux_sel_gpio_gpio_31_o_req; + logic [PORT_MUX_GROUP_PAD31_SEL_WIDTH-1:0] port_mux_sel_gpio_gpio_31_o_arbitrated; + logic port_mux_sel_gpio_gpio_31_o_no_connection; + + assign port_mux_sel_gpio_gpio_31_o_req[PORT_MUX_GROUP_PAD31_SEL_PAD_IO_31] = s_reg2hw.pad_io_31_mux_sel.q == PAD_MUX_GROUP_PAD31_SEL_GPIO_GPIO_31 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_gpio_gpio_31_o_arbiter ( + .in_i(port_mux_sel_gpio_gpio_31_o_req), + .cnt_o(port_mux_sel_gpio_gpio_31_o_arbitrated), + .empty_o(port_mux_sel_gpio_gpio_31_o_no_connection) + ); + + always_comb begin + if (port_mux_sel_gpio_gpio_31_o_no_connection) begin + port_signals_pad2soc_o.gpio.gpio_31_o = 1'b0; + end else begin + unique case (port_mux_sel_gpio_gpio_31_o_arbitrated) + PORT_MUX_GROUP_PAD31_SEL_PAD_IO_31: begin + port_signals_pad2soc_o.gpio.gpio_31_o = pads_to_mux_i.pad_io_31.pad2chip; + end + default: begin + port_signals_pad2soc_o.gpio.gpio_31_o = 1'b0; + end + endcase + end + end + + // Port Group spi2 + + // Port Signal spi2_cs_00_o + logic [0:0] port_mux_sel_spi2_spi2_cs_00_o_req; + logic [PORT_MUX_GROUP_PAD23_SEL_WIDTH-1:0] port_mux_sel_spi2_spi2_cs_00_o_arbitrated; + logic port_mux_sel_spi2_spi2_cs_00_o_no_connection; + + assign port_mux_sel_spi2_spi2_cs_00_o_req[PORT_MUX_GROUP_PAD23_SEL_PAD_IO_23] = s_reg2hw.pad_io_23_mux_sel.q == PAD_MUX_GROUP_PAD23_SEL_SPI2_SPI2_CS_00 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_spi2_spi2_cs_00_o_arbiter ( + .in_i(port_mux_sel_spi2_spi2_cs_00_o_req), + .cnt_o(port_mux_sel_spi2_spi2_cs_00_o_arbitrated), + .empty_o(port_mux_sel_spi2_spi2_cs_00_o_no_connection) + ); + + always_comb begin + if (port_mux_sel_spi2_spi2_cs_00_o_no_connection) begin + port_signals_pad2soc_o.spi2.spi2_cs_00_o = 1'b0; + end else begin + unique case (port_mux_sel_spi2_spi2_cs_00_o_arbitrated) + PORT_MUX_GROUP_PAD23_SEL_PAD_IO_23: begin + port_signals_pad2soc_o.spi2.spi2_cs_00_o = pads_to_mux_i.pad_io_23.pad2chip; + end + default: begin + port_signals_pad2soc_o.spi2.spi2_cs_00_o = 1'b0; + end + endcase + end + end + + + // Port Signal spi2_cs_01_o + logic [0:0] port_mux_sel_spi2_spi2_cs_01_o_req; + logic [PORT_MUX_GROUP_PAD24_SEL_WIDTH-1:0] port_mux_sel_spi2_spi2_cs_01_o_arbitrated; + logic port_mux_sel_spi2_spi2_cs_01_o_no_connection; + + assign port_mux_sel_spi2_spi2_cs_01_o_req[PORT_MUX_GROUP_PAD24_SEL_PAD_IO_24] = s_reg2hw.pad_io_24_mux_sel.q == PAD_MUX_GROUP_PAD24_SEL_SPI2_SPI2_CS_01 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_spi2_spi2_cs_01_o_arbiter ( + .in_i(port_mux_sel_spi2_spi2_cs_01_o_req), + .cnt_o(port_mux_sel_spi2_spi2_cs_01_o_arbitrated), + .empty_o(port_mux_sel_spi2_spi2_cs_01_o_no_connection) + ); + + always_comb begin + if (port_mux_sel_spi2_spi2_cs_01_o_no_connection) begin + port_signals_pad2soc_o.spi2.spi2_cs_01_o = 1'b0; + end else begin + unique case (port_mux_sel_spi2_spi2_cs_01_o_arbitrated) + PORT_MUX_GROUP_PAD24_SEL_PAD_IO_24: begin + port_signals_pad2soc_o.spi2.spi2_cs_01_o = pads_to_mux_i.pad_io_24.pad2chip; + end + default: begin + port_signals_pad2soc_o.spi2.spi2_cs_01_o = 1'b0; + end + endcase + end + end + + + // Port Signal spi2_sck_o + logic [0:0] port_mux_sel_spi2_spi2_sck_o_req; + logic [PORT_MUX_GROUP_PAD25_SEL_WIDTH-1:0] port_mux_sel_spi2_spi2_sck_o_arbitrated; + logic port_mux_sel_spi2_spi2_sck_o_no_connection; + + assign port_mux_sel_spi2_spi2_sck_o_req[PORT_MUX_GROUP_PAD25_SEL_PAD_IO_25] = s_reg2hw.pad_io_25_mux_sel.q == PAD_MUX_GROUP_PAD25_SEL_SPI2_SPI2_SCK ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_spi2_spi2_sck_o_arbiter ( + .in_i(port_mux_sel_spi2_spi2_sck_o_req), + .cnt_o(port_mux_sel_spi2_spi2_sck_o_arbitrated), + .empty_o(port_mux_sel_spi2_spi2_sck_o_no_connection) + ); + + always_comb begin + if (port_mux_sel_spi2_spi2_sck_o_no_connection) begin + port_signals_pad2soc_o.spi2.spi2_sck_o = 1'b0; + end else begin + unique case (port_mux_sel_spi2_spi2_sck_o_arbitrated) + PORT_MUX_GROUP_PAD25_SEL_PAD_IO_25: begin + port_signals_pad2soc_o.spi2.spi2_sck_o = pads_to_mux_i.pad_io_25.pad2chip; + end + default: begin + port_signals_pad2soc_o.spi2.spi2_sck_o = 1'b0; + end + endcase + end + end + + + // Port Signal spi2_sd_00_o + logic [0:0] port_mux_sel_spi2_spi2_sd_00_o_req; + logic [PORT_MUX_GROUP_PAD26_SEL_WIDTH-1:0] port_mux_sel_spi2_spi2_sd_00_o_arbitrated; + logic port_mux_sel_spi2_spi2_sd_00_o_no_connection; + + assign port_mux_sel_spi2_spi2_sd_00_o_req[PORT_MUX_GROUP_PAD26_SEL_PAD_IO_26] = s_reg2hw.pad_io_26_mux_sel.q == PAD_MUX_GROUP_PAD26_SEL_SPI2_SPI2_SD_00 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_spi2_spi2_sd_00_o_arbiter ( + .in_i(port_mux_sel_spi2_spi2_sd_00_o_req), + .cnt_o(port_mux_sel_spi2_spi2_sd_00_o_arbitrated), + .empty_o(port_mux_sel_spi2_spi2_sd_00_o_no_connection) + ); + + always_comb begin + if (port_mux_sel_spi2_spi2_sd_00_o_no_connection) begin + port_signals_pad2soc_o.spi2.spi2_sd_00_o = 1'b0; + end else begin + unique case (port_mux_sel_spi2_spi2_sd_00_o_arbitrated) + PORT_MUX_GROUP_PAD26_SEL_PAD_IO_26: begin + port_signals_pad2soc_o.spi2.spi2_sd_00_o = pads_to_mux_i.pad_io_26.pad2chip; + end + default: begin + port_signals_pad2soc_o.spi2.spi2_sd_00_o = 1'b0; + end + endcase + end + end + + + // Port Signal spi2_sd_01_o + logic [0:0] port_mux_sel_spi2_spi2_sd_01_o_req; + logic [PORT_MUX_GROUP_PAD27_SEL_WIDTH-1:0] port_mux_sel_spi2_spi2_sd_01_o_arbitrated; + logic port_mux_sel_spi2_spi2_sd_01_o_no_connection; + + assign port_mux_sel_spi2_spi2_sd_01_o_req[PORT_MUX_GROUP_PAD27_SEL_PAD_IO_27] = s_reg2hw.pad_io_27_mux_sel.q == PAD_MUX_GROUP_PAD27_SEL_SPI2_SPI2_SD_01 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_spi2_spi2_sd_01_o_arbiter ( + .in_i(port_mux_sel_spi2_spi2_sd_01_o_req), + .cnt_o(port_mux_sel_spi2_spi2_sd_01_o_arbitrated), + .empty_o(port_mux_sel_spi2_spi2_sd_01_o_no_connection) + ); + + always_comb begin + if (port_mux_sel_spi2_spi2_sd_01_o_no_connection) begin + port_signals_pad2soc_o.spi2.spi2_sd_01_o = 1'b0; + end else begin + unique case (port_mux_sel_spi2_spi2_sd_01_o_arbitrated) + PORT_MUX_GROUP_PAD27_SEL_PAD_IO_27: begin + port_signals_pad2soc_o.spi2.spi2_sd_01_o = pads_to_mux_i.pad_io_27.pad2chip; + end + default: begin + port_signals_pad2soc_o.spi2.spi2_sd_01_o = 1'b0; + end + endcase + end + end + + + // Port Signal spi2_sd_02_o + logic [0:0] port_mux_sel_spi2_spi2_sd_02_o_req; + logic [PORT_MUX_GROUP_PAD28_SEL_WIDTH-1:0] port_mux_sel_spi2_spi2_sd_02_o_arbitrated; + logic port_mux_sel_spi2_spi2_sd_02_o_no_connection; + + assign port_mux_sel_spi2_spi2_sd_02_o_req[PORT_MUX_GROUP_PAD28_SEL_PAD_IO_28] = s_reg2hw.pad_io_28_mux_sel.q == PAD_MUX_GROUP_PAD28_SEL_SPI2_SPI2_SD_02 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_spi2_spi2_sd_02_o_arbiter ( + .in_i(port_mux_sel_spi2_spi2_sd_02_o_req), + .cnt_o(port_mux_sel_spi2_spi2_sd_02_o_arbitrated), + .empty_o(port_mux_sel_spi2_spi2_sd_02_o_no_connection) + ); + + always_comb begin + if (port_mux_sel_spi2_spi2_sd_02_o_no_connection) begin + port_signals_pad2soc_o.spi2.spi2_sd_02_o = 1'b0; + end else begin + unique case (port_mux_sel_spi2_spi2_sd_02_o_arbitrated) + PORT_MUX_GROUP_PAD28_SEL_PAD_IO_28: begin + port_signals_pad2soc_o.spi2.spi2_sd_02_o = pads_to_mux_i.pad_io_28.pad2chip; + end + default: begin + port_signals_pad2soc_o.spi2.spi2_sd_02_o = 1'b0; + end + endcase + end + end + + + // Port Signal spi2_sd_03_o + logic [0:0] port_mux_sel_spi2_spi2_sd_03_o_req; + logic [PORT_MUX_GROUP_PAD29_SEL_WIDTH-1:0] port_mux_sel_spi2_spi2_sd_03_o_arbitrated; + logic port_mux_sel_spi2_spi2_sd_03_o_no_connection; + + assign port_mux_sel_spi2_spi2_sd_03_o_req[PORT_MUX_GROUP_PAD29_SEL_PAD_IO_29] = s_reg2hw.pad_io_29_mux_sel.q == PAD_MUX_GROUP_PAD29_SEL_SPI2_SPI2_SD_03 ? 1'b1 : 1'b0; + + lzc #( + .WIDTH(1), + .MODE(1'b0) + ) i_port_muxsel_spi2_spi2_sd_03_o_arbiter ( + .in_i(port_mux_sel_spi2_spi2_sd_03_o_req), + .cnt_o(port_mux_sel_spi2_spi2_sd_03_o_arbitrated), + .empty_o(port_mux_sel_spi2_spi2_sd_03_o_no_connection) + ); + + always_comb begin + if (port_mux_sel_spi2_spi2_sd_03_o_no_connection) begin + port_signals_pad2soc_o.spi2.spi2_sd_03_o = 1'b0; + end else begin + unique case (port_mux_sel_spi2_spi2_sd_03_o_arbitrated) + PORT_MUX_GROUP_PAD29_SEL_PAD_IO_29: begin + port_signals_pad2soc_o.spi2.spi2_sd_03_o = pads_to_mux_i.pad_io_29.pad2chip; + end + default: begin + port_signals_pad2soc_o.spi2.spi2_sd_03_o = 1'b0; + end + endcase + end + end + +endmodule : padframe_xheep_muxer diff --git a/hw/system/padframe/src/padframe_xheep_pads.sv b/hw/system/padframe/src/padframe_xheep_pads.sv new file mode 100644 index 000000000..b4c99666a --- /dev/null +++ b/hw/system/padframe/src/padframe_xheep_pads.sv @@ -0,0 +1,422 @@ +// File auto-generated by Padrick 0.3.1.post0.dev2+ge09286c +module padframe_xheep_pads + import pkg_padframe::*; + import pkg_internal_padframe_xheep::*; +( + output pad_domain_xheep_static_connection_signals_pad2soc_t static_connection_signals_pad2soc, + input pad_domain_xheep_static_connection_signals_soc2pad_t static_connection_signals_soc2pad, + // Dynamic Pad control signals, these signals are controlled by the multiplexer in the correpsongin pad_controller module + input mux_to_pads_t mux_to_pads_i, + output pads_to_mux_t pads_to_mux_o, + // Landing Pads + inout wire logic pad_pad_clk_pad, + inout wire logic pad_pad_rst_pad, + inout wire logic pad_pad_boot_select_pad, + inout wire logic pad_pad_execute_from_flash_pad, + inout wire logic pad_pad_jtag_tck_pad, + inout wire logic pad_pad_jtag_tms_pad, + inout wire logic pad_pad_jtag_trst_pad, + inout wire logic pad_pad_jtag_tdi_pad, + inout wire logic pad_pad_jtag_tdo_pad, + inout wire logic pad_pad_exit_valid_pad, + inout wire logic pad_pad_uart_rx_pad, + inout wire logic pad_pad_uart_tx_pad, + inout wire logic pad_pad_gpio_00_i_pad, + inout wire logic pad_pad_gpio_01_i_pad, + inout wire logic pad_pad_gpio_02_i_pad, + inout wire logic pad_pad_gpio_03_i_pad, + inout wire logic pad_pad_gpio_04_i_pad, + inout wire logic pad_pad_gpio_05_i_pad, + inout wire logic pad_pad_gpio_06_i_pad, + inout wire logic pad_pad_gpio_07_i_pad, + inout wire logic pad_pad_gpio_08_i_pad, + inout wire logic pad_pad_gpio_09_i_pad, + inout wire logic pad_pad_gpio_10_i_pad, + inout wire logic pad_pad_gpio_11_i_pad, + inout wire logic pad_pad_gpio_12_i_pad, + inout wire logic pad_pad_gpio_13_i_pad, + inout wire logic pad_pad_gpio_14_i_pad, + inout wire logic pad_pad_gpio_15_i_pad, + inout wire logic pad_pad_gpio_16_i_pad, + inout wire logic pad_pad_gpio_17_i_pad, + inout wire logic pad_pad_gpio_18_i_pad, + inout wire logic pad_pad_gpio_19_i_pad, + inout wire logic pad_pad_gpio_20_i_pad, + inout wire logic pad_pad_gpio_21_i_pad, + inout wire logic pad_pad_gpio_22_i_pad, + inout wire logic pad_pad_spi_flash_sck_pad, + inout wire logic pad_pad_spi_flash_cs_00_pad, + inout wire logic pad_pad_spi_flash_cs_01_pad, + inout wire logic pad_pad_spi_flash_sd_00_pad, + inout wire logic pad_pad_spi_flash_sd_01_pad, + inout wire logic pad_pad_spi_flash_sd_02_pad, + inout wire logic pad_pad_spi_flash_sd_03_pad, + inout wire logic pad_pad_spi_sck_pad, + inout wire logic pad_pad_spi_cs_00_pad, + inout wire logic pad_pad_spi_cs_01_pad, + inout wire logic pad_pad_spi_sd_00_pad, + inout wire logic pad_pad_spi_sd_01_pad, + inout wire logic pad_pad_spi_sd_02_pad, + inout wire logic pad_pad_spi_sd_03_pad, + inout wire logic pad_pad_io_23_pad, + inout wire logic pad_pad_io_24_pad, + inout wire logic pad_pad_io_25_pad, + inout wire logic pad_pad_io_26_pad, + inout wire logic pad_pad_io_27_pad, + inout wire logic pad_pad_io_28_pad, + inout wire logic pad_pad_io_29_pad, + inout wire logic pad_pad_io_30_pad, + inout wire logic pad_pad_io_31_pad + ); + + // Pad instantiations + pad_cell_input i_pad_clk ( + .pad_in_i(1'b0), + .pad_oe_i(1'b0), + .pad_out_o(static_connection_signals_pad2soc.clk_o), + .pad_io(pad_pad_clk_pad) + ); + pad_cell_input i_pad_rst ( + .pad_in_i(1'b0), + .pad_oe_i(1'b0), + .pad_out_o(static_connection_signals_pad2soc.rst_o), + .pad_io(pad_pad_rst_pad) + ); + pad_cell_input i_pad_boot_select ( + .pad_in_i(1'b0), + .pad_oe_i(1'b0), + .pad_out_o(static_connection_signals_pad2soc.boot_select_o), + .pad_io(pad_pad_boot_select_pad) + ); + pad_cell_input i_pad_execute_from_flash ( + .pad_in_i(1'b0), + .pad_oe_i(1'b0), + .pad_out_o(static_connection_signals_pad2soc.execute_from_flash_o), + .pad_io(pad_pad_execute_from_flash_pad) + ); + pad_cell_input i_pad_jtag_tck ( + .pad_in_i(1'b0), + .pad_oe_i(1'b0), + .pad_out_o(static_connection_signals_pad2soc.jtag_tck_o), + .pad_io(pad_pad_jtag_tck_pad) + ); + pad_cell_input i_pad_jtag_tms ( + .pad_in_i(1'b0), + .pad_oe_i(1'b0), + .pad_out_o(static_connection_signals_pad2soc.jtag_tms_o), + .pad_io(pad_pad_jtag_tms_pad) + ); + pad_cell_input i_pad_jtag_trst ( + .pad_in_i(1'b0), + .pad_oe_i(1'b0), + .pad_out_o(static_connection_signals_pad2soc.jtag_trst_o), + .pad_io(pad_pad_jtag_trst_pad) + ); + pad_cell_input i_pad_jtag_tdi ( + .pad_in_i(1'b0), + .pad_oe_i(1'b0), + .pad_out_o(static_connection_signals_pad2soc.jtag_tdi_o), + .pad_io(pad_pad_jtag_tdi_pad) + ); + pad_cell_output i_pad_jtag_tdo ( + .pad_in_i(static_connection_signals_soc2pad.jtag_tdo_i), + .pad_oe_i(1'b1), + .pad_out_o(), + .pad_io(pad_pad_jtag_tdo_pad) + ); + pad_cell_output i_pad_exit_valid ( + .pad_in_i(static_connection_signals_soc2pad.exit_valid_i), + .pad_oe_i(1'b1), + .pad_out_o(), + .pad_io(pad_pad_exit_valid_pad) + ); + pad_cell_input i_pad_uart_rx ( + .pad_in_i(1'b0), + .pad_oe_i(1'b0), + .pad_out_o(static_connection_signals_pad2soc.uart_rx_o), + .pad_io(pad_pad_uart_rx_pad) + ); + pad_cell_output i_pad_uart_tx ( + .pad_in_i(static_connection_signals_soc2pad.uart_tx_i), + .pad_oe_i(1'b1), + .pad_out_o(), + .pad_io(pad_pad_uart_tx_pad) + ); + pad_cell_inout i_pad_gpio_00_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_00_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_00_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_00_o), + .pad_io(pad_pad_gpio_00_i_pad) + ); + pad_cell_inout i_pad_gpio_01_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_01_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_01_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_01_o), + .pad_io(pad_pad_gpio_01_i_pad) + ); + pad_cell_inout i_pad_gpio_02_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_02_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_02_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_02_o), + .pad_io(pad_pad_gpio_02_i_pad) + ); + pad_cell_inout i_pad_gpio_03_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_03_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_03_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_03_o), + .pad_io(pad_pad_gpio_03_i_pad) + ); + pad_cell_inout i_pad_gpio_04_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_04_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_04_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_04_o), + .pad_io(pad_pad_gpio_04_i_pad) + ); + pad_cell_inout i_pad_gpio_05_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_05_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_05_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_05_o), + .pad_io(pad_pad_gpio_05_i_pad) + ); + pad_cell_inout i_pad_gpio_06_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_06_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_06_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_06_o), + .pad_io(pad_pad_gpio_06_i_pad) + ); + pad_cell_inout i_pad_gpio_07_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_07_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_07_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_07_o), + .pad_io(pad_pad_gpio_07_i_pad) + ); + pad_cell_inout i_pad_gpio_08_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_08_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_08_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_08_o), + .pad_io(pad_pad_gpio_08_i_pad) + ); + pad_cell_inout i_pad_gpio_09_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_09_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_09_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_09_o), + .pad_io(pad_pad_gpio_09_i_pad) + ); + pad_cell_inout i_pad_gpio_10_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_10_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_10_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_10_o), + .pad_io(pad_pad_gpio_10_i_pad) + ); + pad_cell_inout i_pad_gpio_11_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_11_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_11_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_11_o), + .pad_io(pad_pad_gpio_11_i_pad) + ); + pad_cell_inout i_pad_gpio_12_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_12_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_12_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_12_o), + .pad_io(pad_pad_gpio_12_i_pad) + ); + pad_cell_inout i_pad_gpio_13_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_13_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_13_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_13_o), + .pad_io(pad_pad_gpio_13_i_pad) + ); + pad_cell_inout i_pad_gpio_14_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_14_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_14_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_14_o), + .pad_io(pad_pad_gpio_14_i_pad) + ); + pad_cell_inout i_pad_gpio_15_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_15_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_15_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_15_o), + .pad_io(pad_pad_gpio_15_i_pad) + ); + pad_cell_inout i_pad_gpio_16_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_16_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_16_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_16_o), + .pad_io(pad_pad_gpio_16_i_pad) + ); + pad_cell_inout i_pad_gpio_17_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_17_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_17_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_17_o), + .pad_io(pad_pad_gpio_17_i_pad) + ); + pad_cell_inout i_pad_gpio_18_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_18_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_18_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_18_o), + .pad_io(pad_pad_gpio_18_i_pad) + ); + pad_cell_inout i_pad_gpio_19_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_19_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_19_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_19_o), + .pad_io(pad_pad_gpio_19_i_pad) + ); + pad_cell_inout i_pad_gpio_20_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_20_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_20_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_20_o), + .pad_io(pad_pad_gpio_20_i_pad) + ); + pad_cell_inout i_pad_gpio_21_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_21_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_21_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_21_o), + .pad_io(pad_pad_gpio_21_i_pad) + ); + pad_cell_inout i_pad_gpio_22_i ( + .pad_in_i(static_connection_signals_soc2pad.gpio_22_i), + .pad_oe_i(static_connection_signals_soc2pad.gpio_22_oe_i), + .pad_out_o(static_connection_signals_pad2soc.gpio_22_o), + .pad_io(pad_pad_gpio_22_i_pad) + ); + pad_cell_inout i_pad_spi_flash_sck ( + .pad_in_i(static_connection_signals_soc2pad.spi_flash_sck_i), + .pad_oe_i(static_connection_signals_soc2pad.spi_flash_sck_oe_i), + .pad_out_o(static_connection_signals_pad2soc.spi_flash_sck_o), + .pad_io(pad_pad_spi_flash_sck_pad) + ); + pad_cell_inout i_pad_spi_flash_cs_00 ( + .pad_in_i(static_connection_signals_soc2pad.spi_flash_cs_00_i), + .pad_oe_i(static_connection_signals_soc2pad.spi_flash_cs_00_oe_i), + .pad_out_o(static_connection_signals_pad2soc.spi_flash_cs_00_o), + .pad_io(pad_pad_spi_flash_cs_00_pad) + ); + pad_cell_inout i_pad_spi_flash_cs_01 ( + .pad_in_i(static_connection_signals_soc2pad.spi_flash_cs_01_i), + .pad_oe_i(static_connection_signals_soc2pad.spi_flash_cs_01_oe_i), + .pad_out_o(static_connection_signals_pad2soc.spi_flash_cs_01_o), + .pad_io(pad_pad_spi_flash_cs_01_pad) + ); + pad_cell_inout i_pad_spi_flash_sd_00 ( + .pad_in_i(static_connection_signals_soc2pad.spi_flash_sd_00_i), + .pad_oe_i(static_connection_signals_soc2pad.spi_flash_sd_00_oe_i), + .pad_out_o(static_connection_signals_pad2soc.spi_flash_sd_00_o), + .pad_io(pad_pad_spi_flash_sd_00_pad) + ); + pad_cell_inout i_pad_spi_flash_sd_01 ( + .pad_in_i(static_connection_signals_soc2pad.spi_flash_sd_01_i), + .pad_oe_i(static_connection_signals_soc2pad.spi_flash_sd_01_oe_i), + .pad_out_o(static_connection_signals_pad2soc.spi_flash_sd_01_o), + .pad_io(pad_pad_spi_flash_sd_01_pad) + ); + pad_cell_inout i_pad_spi_flash_sd_02 ( + .pad_in_i(static_connection_signals_soc2pad.spi_flash_sd_02_i), + .pad_oe_i(static_connection_signals_soc2pad.spi_flash_sd_02_oe_i), + .pad_out_o(static_connection_signals_pad2soc.spi_flash_sd_02_o), + .pad_io(pad_pad_spi_flash_sd_02_pad) + ); + pad_cell_inout i_pad_spi_flash_sd_03 ( + .pad_in_i(static_connection_signals_soc2pad.spi_flash_sd_03_i), + .pad_oe_i(static_connection_signals_soc2pad.spi_flash_sd_03_oe_i), + .pad_out_o(static_connection_signals_pad2soc.spi_flash_sd_03_o), + .pad_io(pad_pad_spi_flash_sd_03_pad) + ); + pad_cell_inout i_pad_spi_sck ( + .pad_in_i(static_connection_signals_soc2pad.spi_sck_i), + .pad_oe_i(static_connection_signals_soc2pad.spi_sck_oe_i), + .pad_out_o(static_connection_signals_pad2soc.spi_sck_o), + .pad_io(pad_pad_spi_sck_pad) + ); + pad_cell_inout i_pad_spi_cs_00 ( + .pad_in_i(static_connection_signals_soc2pad.spi_cs_00_i), + .pad_oe_i(static_connection_signals_soc2pad.spi_cs_00_oe_i), + .pad_out_o(static_connection_signals_pad2soc.spi_cs_00_o), + .pad_io(pad_pad_spi_cs_00_pad) + ); + pad_cell_inout i_pad_spi_cs_01 ( + .pad_in_i(static_connection_signals_soc2pad.spi_cs_01_i), + .pad_oe_i(static_connection_signals_soc2pad.spi_cs_01_oe_i), + .pad_out_o(static_connection_signals_pad2soc.spi_cs_01_o), + .pad_io(pad_pad_spi_cs_01_pad) + ); + pad_cell_inout i_pad_spi_sd_00 ( + .pad_in_i(static_connection_signals_soc2pad.spi_sd_00_i), + .pad_oe_i(static_connection_signals_soc2pad.spi_sd_00_oe_i), + .pad_out_o(static_connection_signals_pad2soc.spi_sd_00_o), + .pad_io(pad_pad_spi_sd_00_pad) + ); + pad_cell_inout i_pad_spi_sd_01 ( + .pad_in_i(static_connection_signals_soc2pad.spi_sd_01_i), + .pad_oe_i(static_connection_signals_soc2pad.spi_sd_01_oe_i), + .pad_out_o(static_connection_signals_pad2soc.spi_sd_01_o), + .pad_io(pad_pad_spi_sd_01_pad) + ); + pad_cell_inout i_pad_spi_sd_02 ( + .pad_in_i(static_connection_signals_soc2pad.spi_sd_02_i), + .pad_oe_i(static_connection_signals_soc2pad.spi_sd_02_oe_i), + .pad_out_o(static_connection_signals_pad2soc.spi_sd_02_o), + .pad_io(pad_pad_spi_sd_02_pad) + ); + pad_cell_inout i_pad_spi_sd_03 ( + .pad_in_i(static_connection_signals_soc2pad.spi_sd_03_i), + .pad_oe_i(static_connection_signals_soc2pad.spi_sd_03_oe_i), + .pad_out_o(static_connection_signals_pad2soc.spi_sd_03_o), + .pad_io(pad_pad_spi_sd_03_pad) + ); + pad_cell_inout i_pad_io_23 ( + .pad_in_i(mux_to_pads_i.pad_io_23.chip2pad), + .pad_oe_i(mux_to_pads_i.pad_io_23.output_en), + .pad_out_o(pads_to_mux_o.pad_io_23.pad2chip), + .pad_io(pad_pad_io_23_pad) + ); + pad_cell_inout i_pad_io_24 ( + .pad_in_i(mux_to_pads_i.pad_io_24.chip2pad), + .pad_oe_i(mux_to_pads_i.pad_io_24.output_en), + .pad_out_o(pads_to_mux_o.pad_io_24.pad2chip), + .pad_io(pad_pad_io_24_pad) + ); + pad_cell_inout i_pad_io_25 ( + .pad_in_i(mux_to_pads_i.pad_io_25.chip2pad), + .pad_oe_i(mux_to_pads_i.pad_io_25.output_en), + .pad_out_o(pads_to_mux_o.pad_io_25.pad2chip), + .pad_io(pad_pad_io_25_pad) + ); + pad_cell_inout i_pad_io_26 ( + .pad_in_i(mux_to_pads_i.pad_io_26.chip2pad), + .pad_oe_i(mux_to_pads_i.pad_io_26.output_en), + .pad_out_o(pads_to_mux_o.pad_io_26.pad2chip), + .pad_io(pad_pad_io_26_pad) + ); + pad_cell_inout i_pad_io_27 ( + .pad_in_i(mux_to_pads_i.pad_io_27.chip2pad), + .pad_oe_i(mux_to_pads_i.pad_io_27.output_en), + .pad_out_o(pads_to_mux_o.pad_io_27.pad2chip), + .pad_io(pad_pad_io_27_pad) + ); + pad_cell_inout i_pad_io_28 ( + .pad_in_i(mux_to_pads_i.pad_io_28.chip2pad), + .pad_oe_i(mux_to_pads_i.pad_io_28.output_en), + .pad_out_o(pads_to_mux_o.pad_io_28.pad2chip), + .pad_io(pad_pad_io_28_pad) + ); + pad_cell_inout i_pad_io_29 ( + .pad_in_i(mux_to_pads_i.pad_io_29.chip2pad), + .pad_oe_i(mux_to_pads_i.pad_io_29.output_en), + .pad_out_o(pads_to_mux_o.pad_io_29.pad2chip), + .pad_io(pad_pad_io_29_pad) + ); + pad_cell_inout i_pad_io_30 ( + .pad_in_i(mux_to_pads_i.pad_io_30.chip2pad), + .pad_oe_i(mux_to_pads_i.pad_io_30.output_en), + .pad_out_o(pads_to_mux_o.pad_io_30.pad2chip), + .pad_io(pad_pad_io_30_pad) + ); + pad_cell_inout i_pad_io_31 ( + .pad_in_i(mux_to_pads_i.pad_io_31.chip2pad), + .pad_oe_i(mux_to_pads_i.pad_io_31.output_en), + .pad_out_o(pads_to_mux_o.pad_io_31.pad2chip), + .pad_io(pad_pad_io_31_pad) + ); + +endmodule : padframe_xheep_pads diff --git a/hw/system/padframe/src/padframe_xheep_regs.hjson b/hw/system/padframe/src/padframe_xheep_regs.hjson new file mode 100644 index 000000000..8491c7a08 --- /dev/null +++ b/hw/system/padframe/src/padframe_xheep_regs.hjson @@ -0,0 +1,535 @@ + +{ + # File auto-generated by Padrick 0.3.1.post0.dev2+ge09286c + name: "padframe_xheep_config" + clock_primary: "clk_i" + reset_primary: "rst_ni" + bus_interfaces: [ + { protocol: "reg_iface", direction: "device"} + ] + regwidth: 32, + registers: [ + {skipto: "0x0"}, + { + name: INFO + desc: "Read-only IP Information register" + swaccess: "ro" + hwaccess: "hro" + fields: [ + { + bits: "15:0" + name: HW_VERSION + desc: "Hardware version ID." + resval: 2 + }, + { + bits:"31:16" + name: PADCOUNT + desc: "The number of muxable pads in this IP." + resval: "9" + } + ] + } + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + { + name: PAD_IO_23_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: output_en + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO_23_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io_23. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 1 + fields: [ + { + bits: "0:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_spi2_spi2_cs_00", desc: "Connect port spi2_cs_00 from port group spi2 to this pad." } + ] + } + ] + } + + { + name: PAD_IO_24_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: output_en + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO_24_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io_24. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 1 + fields: [ + { + bits: "0:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_spi2_spi2_cs_01", desc: "Connect port spi2_cs_01 from port group spi2 to this pad." } + ] + } + ] + } + + { + name: PAD_IO_25_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: output_en + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO_25_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io_25. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 1 + fields: [ + { + bits: "0:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_spi2_spi2_sck", desc: "Connect port spi2_sck from port group spi2 to this pad." } + ] + } + ] + } + + { + name: PAD_IO_26_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: output_en + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO_26_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io_26. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 1 + fields: [ + { + bits: "0:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_spi2_spi2_sd_00", desc: "Connect port spi2_sd_00 from port group spi2 to this pad." } + ] + } + ] + } + + { + name: PAD_IO_27_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: output_en + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO_27_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io_27. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 1 + fields: [ + { + bits: "0:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_spi2_spi2_sd_01", desc: "Connect port spi2_sd_01 from port group spi2 to this pad." } + ] + } + ] + } + + { + name: PAD_IO_28_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: output_en + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO_28_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io_28. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 1 + fields: [ + { + bits: "0:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_spi2_spi2_sd_02", desc: "Connect port spi2_sd_02 from port group spi2 to this pad." } + ] + } + ] + } + + { + name: PAD_IO_29_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: output_en + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO_29_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io_29. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 1 + fields: [ + { + bits: "0:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_spi2_spi2_sd_03", desc: "Connect port spi2_sd_03 from port group spi2 to this pad." } + ] + } + ] + } + + { + name: PAD_IO_30_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: output_en + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO_30_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io_30. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 2 + fields: [ + { + bits: "1:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_gpio_gpio_30", desc: "Connect port gpio_30 from port group gpio to this pad." } + { value: "2", name: "port_i2c_i2c_sda", desc: "Connect port i2c_sda from port group i2c to this pad." } + ] + } + ] + } + + { + name: PAD_IO_31_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: output_en + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO_31_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io_31. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 2 + fields: [ + { + bits: "1:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_gpio_gpio_31", desc: "Connect port gpio_31 from port group gpio to this pad." } + { value: "2", name: "port_i2c_i2c_scl", desc: "Connect port i2c_scl from port group i2c to this pad." } + ] + } + ] + } + + ] +} diff --git a/hw/system/padframe/src/pkg_internal_padframe_xheep.sv b/hw/system/padframe/src/pkg_internal_padframe_xheep.sv new file mode 100644 index 000000000..62bb52a1c --- /dev/null +++ b/hw/system/padframe/src/pkg_internal_padframe_xheep.sv @@ -0,0 +1,178 @@ +// File auto-generated by Padrick 0.3.1.post0.dev2+ge09286c +package pkg_internal_padframe_xheep; + typedef struct packed{ + logic chip2pad; + logic output_en; + } mux_to_pad_pad_io_23_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io_23_t; + + typedef struct packed{ + logic chip2pad; + logic output_en; + } mux_to_pad_pad_io_24_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io_24_t; + + typedef struct packed{ + logic chip2pad; + logic output_en; + } mux_to_pad_pad_io_25_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io_25_t; + + typedef struct packed{ + logic chip2pad; + logic output_en; + } mux_to_pad_pad_io_26_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io_26_t; + + typedef struct packed{ + logic chip2pad; + logic output_en; + } mux_to_pad_pad_io_27_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io_27_t; + + typedef struct packed{ + logic chip2pad; + logic output_en; + } mux_to_pad_pad_io_28_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io_28_t; + + typedef struct packed{ + logic chip2pad; + logic output_en; + } mux_to_pad_pad_io_29_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io_29_t; + + typedef struct packed{ + logic chip2pad; + logic output_en; + } mux_to_pad_pad_io_30_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io_30_t; + + typedef struct packed{ + logic chip2pad; + logic output_en; + } mux_to_pad_pad_io_31_t; + + typedef struct packed{ + logic pad2chip; + } pad_to_mux_pad_io_31_t; + + typedef struct packed{ + mux_to_pad_pad_io_23_t pad_io_23; + mux_to_pad_pad_io_24_t pad_io_24; + mux_to_pad_pad_io_25_t pad_io_25; + mux_to_pad_pad_io_26_t pad_io_26; + mux_to_pad_pad_io_27_t pad_io_27; + mux_to_pad_pad_io_28_t pad_io_28; + mux_to_pad_pad_io_29_t pad_io_29; + mux_to_pad_pad_io_30_t pad_io_30; + mux_to_pad_pad_io_31_t pad_io_31; + } mux_to_pads_t; + + typedef struct packed{ + pad_to_mux_pad_io_23_t pad_io_23; + pad_to_mux_pad_io_24_t pad_io_24; + pad_to_mux_pad_io_25_t pad_io_25; + pad_to_mux_pad_io_26_t pad_io_26; + pad_to_mux_pad_io_27_t pad_io_27; + pad_to_mux_pad_io_28_t pad_io_28; + pad_to_mux_pad_io_29_t pad_io_29; + pad_to_mux_pad_io_30_t pad_io_30; + pad_to_mux_pad_io_31_t pad_io_31; + } pads_to_mux_t; + + + + // Indices definitions + + parameter PAD_MUX_GROUP_PAD23_SEL_WIDTH = 1; + parameter logic[0:0] PAD_MUX_GROUP_PAD23_SEL_DEFAULT = 1'd0; + parameter logic[0:0] PAD_MUX_GROUP_PAD23_SEL_SPI2_SPI2_CS_00 = 1'd1; + + parameter PAD_MUX_GROUP_PAD24_SEL_WIDTH = 1; + parameter logic[0:0] PAD_MUX_GROUP_PAD24_SEL_DEFAULT = 1'd0; + parameter logic[0:0] PAD_MUX_GROUP_PAD24_SEL_SPI2_SPI2_CS_01 = 1'd1; + + parameter PAD_MUX_GROUP_PAD25_SEL_WIDTH = 1; + parameter logic[0:0] PAD_MUX_GROUP_PAD25_SEL_DEFAULT = 1'd0; + parameter logic[0:0] PAD_MUX_GROUP_PAD25_SEL_SPI2_SPI2_SCK = 1'd1; + + parameter PAD_MUX_GROUP_PAD26_SEL_WIDTH = 1; + parameter logic[0:0] PAD_MUX_GROUP_PAD26_SEL_DEFAULT = 1'd0; + parameter logic[0:0] PAD_MUX_GROUP_PAD26_SEL_SPI2_SPI2_SD_00 = 1'd1; + + parameter PAD_MUX_GROUP_PAD27_SEL_WIDTH = 1; + parameter logic[0:0] PAD_MUX_GROUP_PAD27_SEL_DEFAULT = 1'd0; + parameter logic[0:0] PAD_MUX_GROUP_PAD27_SEL_SPI2_SPI2_SD_01 = 1'd1; + + parameter PAD_MUX_GROUP_PAD28_SEL_WIDTH = 1; + parameter logic[0:0] PAD_MUX_GROUP_PAD28_SEL_DEFAULT = 1'd0; + parameter logic[0:0] PAD_MUX_GROUP_PAD28_SEL_SPI2_SPI2_SD_02 = 1'd1; + + parameter PAD_MUX_GROUP_PAD29_SEL_WIDTH = 1; + parameter logic[0:0] PAD_MUX_GROUP_PAD29_SEL_DEFAULT = 1'd0; + parameter logic[0:0] PAD_MUX_GROUP_PAD29_SEL_SPI2_SPI2_SD_03 = 1'd1; + + parameter PAD_MUX_GROUP_PAD30_SEL_WIDTH = 2; + parameter logic[1:0] PAD_MUX_GROUP_PAD30_SEL_DEFAULT = 2'd0; + parameter logic[1:0] PAD_MUX_GROUP_PAD30_SEL_GPIO_GPIO_30 = 2'd1; + parameter logic[1:0] PAD_MUX_GROUP_PAD30_SEL_I2C_I2C_SDA = 2'd2; + + parameter PAD_MUX_GROUP_PAD31_SEL_WIDTH = 2; + parameter logic[1:0] PAD_MUX_GROUP_PAD31_SEL_DEFAULT = 2'd0; + parameter logic[1:0] PAD_MUX_GROUP_PAD31_SEL_GPIO_GPIO_31 = 2'd1; + parameter logic[1:0] PAD_MUX_GROUP_PAD31_SEL_I2C_I2C_SCL = 2'd2; + + // Dynamic Pad instance index + + parameter PORT_MUX_GROUP_PAD23_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD23_SEL_PAD_IO_23 = 1'd0; + + parameter PORT_MUX_GROUP_PAD24_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD24_SEL_PAD_IO_24 = 1'd0; + + parameter PORT_MUX_GROUP_PAD25_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD25_SEL_PAD_IO_25 = 1'd0; + + parameter PORT_MUX_GROUP_PAD26_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD26_SEL_PAD_IO_26 = 1'd0; + + parameter PORT_MUX_GROUP_PAD27_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD27_SEL_PAD_IO_27 = 1'd0; + + parameter PORT_MUX_GROUP_PAD28_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD28_SEL_PAD_IO_28 = 1'd0; + + parameter PORT_MUX_GROUP_PAD29_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD29_SEL_PAD_IO_29 = 1'd0; + + parameter PORT_MUX_GROUP_PAD30_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD30_SEL_PAD_IO_30 = 1'd0; + + parameter PORT_MUX_GROUP_PAD31_SEL_WIDTH = 1; + parameter logic[0:0] PORT_MUX_GROUP_PAD31_SEL_PAD_IO_31 = 1'd0; +endpackage : pkg_internal_padframe_xheep diff --git a/hw/system/padframe/src/pkg_padframe.sv b/hw/system/padframe/src/pkg_padframe.sv new file mode 100644 index 000000000..b05d3c1e2 --- /dev/null +++ b/hw/system/padframe/src/pkg_padframe.sv @@ -0,0 +1,220 @@ +// File auto-generated by Padrick 0.3.1.post0.dev2+ge09286c +package pkg_padframe; + + //Structs for xheep + + //Static connections signals + typedef struct packed { + logic exit_valid_i; + logic gpio_00_i; + logic gpio_00_oe_i; + logic gpio_01_i; + logic gpio_01_oe_i; + logic gpio_02_i; + logic gpio_02_oe_i; + logic gpio_03_i; + logic gpio_03_oe_i; + logic gpio_04_i; + logic gpio_04_oe_i; + logic gpio_05_i; + logic gpio_05_oe_i; + logic gpio_06_i; + logic gpio_06_oe_i; + logic gpio_07_i; + logic gpio_07_oe_i; + logic gpio_08_i; + logic gpio_08_oe_i; + logic gpio_09_i; + logic gpio_09_oe_i; + logic gpio_10_i; + logic gpio_10_oe_i; + logic gpio_11_i; + logic gpio_11_oe_i; + logic gpio_12_i; + logic gpio_12_oe_i; + logic gpio_13_i; + logic gpio_13_oe_i; + logic gpio_14_i; + logic gpio_14_oe_i; + logic gpio_15_i; + logic gpio_15_oe_i; + logic gpio_16_i; + logic gpio_16_oe_i; + logic gpio_17_i; + logic gpio_17_oe_i; + logic gpio_18_i; + logic gpio_18_oe_i; + logic gpio_19_i; + logic gpio_19_oe_i; + logic gpio_20_i; + logic gpio_20_oe_i; + logic gpio_21_i; + logic gpio_21_oe_i; + logic gpio_22_i; + logic gpio_22_oe_i; + logic jtag_tdo_i; + logic spi_cs_00_i; + logic spi_cs_00_oe_i; + logic spi_cs_01_i; + logic spi_cs_01_oe_i; + logic spi_flash_cs_00_i; + logic spi_flash_cs_00_oe_i; + logic spi_flash_cs_01_i; + logic spi_flash_cs_01_oe_i; + logic spi_flash_sck_i; + logic spi_flash_sck_oe_i; + logic spi_flash_sd_00_i; + logic spi_flash_sd_00_oe_i; + logic spi_flash_sd_01_i; + logic spi_flash_sd_01_oe_i; + logic spi_flash_sd_02_i; + logic spi_flash_sd_02_oe_i; + logic spi_flash_sd_03_i; + logic spi_flash_sd_03_oe_i; + logic spi_sck_i; + logic spi_sck_oe_i; + logic spi_sd_00_i; + logic spi_sd_00_oe_i; + logic spi_sd_01_i; + logic spi_sd_01_oe_i; + logic spi_sd_02_i; + logic spi_sd_02_oe_i; + logic spi_sd_03_i; + logic spi_sd_03_oe_i; + logic uart_tx_i; + } pad_domain_xheep_static_connection_signals_soc2pad_t; + + typedef struct packed { + logic boot_select_o; + logic clk_o; + logic execute_from_flash_o; + logic gpio_00_o; + logic gpio_01_o; + logic gpio_02_o; + logic gpio_03_o; + logic gpio_04_o; + logic gpio_05_o; + logic gpio_06_o; + logic gpio_07_o; + logic gpio_08_o; + logic gpio_09_o; + logic gpio_10_o; + logic gpio_11_o; + logic gpio_12_o; + logic gpio_13_o; + logic gpio_14_o; + logic gpio_15_o; + logic gpio_16_o; + logic gpio_17_o; + logic gpio_18_o; + logic gpio_19_o; + logic gpio_20_o; + logic gpio_21_o; + logic gpio_22_o; + logic jtag_tck_o; + logic jtag_tdi_o; + logic jtag_tms_o; + logic jtag_trst_o; + logic rst_o; + logic spi_cs_00_o; + logic spi_cs_01_o; + logic spi_flash_cs_00_o; + logic spi_flash_cs_01_o; + logic spi_flash_sck_o; + logic spi_flash_sd_00_o; + logic spi_flash_sd_01_o; + logic spi_flash_sd_02_o; + logic spi_flash_sd_03_o; + logic spi_sck_o; + logic spi_sd_00_o; + logic spi_sd_01_o; + logic spi_sd_02_o; + logic spi_sd_03_o; + logic uart_rx_o; + } pad_domain_xheep_static_connection_signals_pad2soc_t; + + // Port Group signals + typedef struct packed { + logic i2c_scl_i; + logic i2c_scl_oe_i; + logic i2c_sda_i; + logic i2c_sda_oe_i; + } pad_domain_xheep_port_group_i2c_soc2pad_t; + + typedef struct packed { + logic i2c_scl_o; + logic i2c_sda_o; + } pad_domain_xheep_port_group_i2c_pad2soc_t; + + typedef struct packed { + logic gpio_30_i; + logic gpio_30_oe_i; + logic gpio_31_i; + logic gpio_31_oe_i; + } pad_domain_xheep_port_group_gpio_soc2pad_t; + + typedef struct packed { + logic gpio_30_o; + logic gpio_31_o; + } pad_domain_xheep_port_group_gpio_pad2soc_t; + + typedef struct packed { + logic spi2_cs_00_i; + logic spi2_cs_00_oe_i; + logic spi2_cs_01_i; + logic spi2_cs_01_oe_i; + logic spi2_sck_i; + logic spi2_sck_oe_i; + logic spi2_sd_00_i; + logic spi2_sd_00_oe_i; + logic spi2_sd_01_i; + logic spi2_sd_01_oe_i; + logic spi2_sd_02_i; + logic spi2_sd_02_oe_i; + logic spi2_sd_03_i; + logic spi2_sd_03_oe_i; + } pad_domain_xheep_port_group_spi2_soc2pad_t; + + typedef struct packed { + logic spi2_cs_00_o; + logic spi2_cs_01_o; + logic spi2_sck_o; + logic spi2_sd_00_o; + logic spi2_sd_01_o; + logic spi2_sd_02_o; + logic spi2_sd_03_o; + } pad_domain_xheep_port_group_spi2_pad2soc_t; + + typedef struct packed { + pad_domain_xheep_port_group_i2c_soc2pad_t i2c; + pad_domain_xheep_port_group_gpio_soc2pad_t gpio; + pad_domain_xheep_port_group_spi2_soc2pad_t spi2; + } pad_domain_xheep_ports_soc2pad_t; + + typedef struct packed { + pad_domain_xheep_port_group_i2c_pad2soc_t i2c; + pad_domain_xheep_port_group_gpio_pad2soc_t gpio; + pad_domain_xheep_port_group_spi2_pad2soc_t spi2; + } pad_domain_xheep_ports_pad2soc_t; + + + //Toplevel structs + + typedef struct packed { + pad_domain_xheep_static_connection_signals_pad2soc_t xheep; + } static_connection_signals_pad2soc_t; + + typedef struct packed { + pad_domain_xheep_static_connection_signals_soc2pad_t xheep; + } static_connection_signals_soc2pad_t; + + typedef struct packed { + pad_domain_xheep_ports_pad2soc_t xheep; + } port_signals_pad2soc_t; + + typedef struct packed { + pad_domain_xheep_ports_soc2pad_t xheep; + } port_signals_soc2pad_t; + + +endpackage : pkg_padframe diff --git a/hw/system/padframe/src_files.yml b/hw/system/padframe/src_files.yml new file mode 100644 index 000000000..5545d8450 --- /dev/null +++ b/hw/system/padframe/src_files.yml @@ -0,0 +1,12 @@ +# File auto-generated by Padrick 0.3.1.post0.dev2+ge09286c +padframe: + files: + - src/pkg_padframe.sv + - src/pkg_internal_padframe_xheep.sv + - src/padframe_xheep_config_reg_pkg.sv + - src/padframe_xheep_config_reg_top.sv + - src/padframe_xheep_pads.sv + - src/padframe_xheep.sv + - src/padframe.sv + vlog_opts: + - -L axi_lib \ No newline at end of file diff --git a/hw/system/x_heep_system.sv b/hw/system/x_heep_system.sv new file mode 100644 index 000000000..6adecb519 --- /dev/null +++ b/hw/system/x_heep_system.sv @@ -0,0 +1,797 @@ +// Copyright 2022 OpenHW Group +// Solderpad Hardware License, Version 2.1, see LICENSE.md for details. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +module x_heep_system + import obi_pkg::*; + import reg_pkg::*; +#( + parameter PULP_XPULP = 0, + parameter FPU = 0, + parameter PULP_ZFINX = 0, + parameter EXT_XBAR_NMASTER = 0 +) ( + input logic [core_v_mini_mcu_pkg::NEXT_INT-1:0] intr_vector_ext_i, + + input obi_req_t [EXT_XBAR_NMASTER-1:0] ext_xbar_master_req_i, + output obi_resp_t [EXT_XBAR_NMASTER-1:0] ext_xbar_master_resp_o, + + output obi_req_t ext_xbar_slave_req_o, + input obi_resp_t ext_xbar_slave_resp_i, + + output reg_req_t ext_peripheral_slave_req_o, + input reg_rsp_t ext_peripheral_slave_resp_i, + + output logic [core_v_mini_mcu_pkg::EXTERNAL_DOMAINS-1:0] external_subsystem_powergate_switch_o, + input logic [core_v_mini_mcu_pkg::EXTERNAL_DOMAINS-1:0] external_subsystem_powergate_switch_ack_i, + output logic [core_v_mini_mcu_pkg::EXTERNAL_DOMAINS-1:0] external_subsystem_powergate_iso_o, + output logic [core_v_mini_mcu_pkg::EXTERNAL_DOMAINS-1:0] external_subsystem_rst_no, + output logic [core_v_mini_mcu_pkg::EXTERNAL_DOMAINS-1:0] external_ram_banks_set_retentive_o, + + output logic [31:0] exit_value_o, + + inout logic clk_i, + inout logic rst_ni, + inout logic boot_select_i, + inout logic execute_from_flash_i, + inout logic jtag_tck_i, + inout logic jtag_tms_i, + inout logic jtag_trst_ni, + inout logic jtag_tdi_i, + inout logic jtag_tdo_o, + inout logic uart_rx_i, + inout logic uart_tx_o, + inout logic exit_valid_o, + inout logic gpio_0_io, + inout logic gpio_1_io, + inout logic gpio_2_io, + inout logic gpio_3_io, + inout logic gpio_4_io, + inout logic gpio_5_io, + inout logic gpio_6_io, + inout logic gpio_7_io, + inout logic gpio_8_io, + inout logic gpio_9_io, + inout logic gpio_10_io, + inout logic gpio_11_io, + inout logic gpio_12_io, + inout logic gpio_13_io, + inout logic gpio_14_io, + inout logic gpio_15_io, + inout logic gpio_16_io, + inout logic gpio_17_io, + inout logic gpio_18_io, + inout logic gpio_19_io, + inout logic gpio_20_io, + inout logic gpio_21_io, + inout logic gpio_22_io, + inout logic spi_flash_sck_io, + inout logic spi_flash_cs_0_io, + inout logic spi_flash_cs_1_io, + inout logic spi_flash_sd_0_io, + inout logic spi_flash_sd_1_io, + inout logic spi_flash_sd_2_io, + inout logic spi_flash_sd_3_io, + inout logic spi_sck_io, + inout logic spi_cs_0_io, + inout logic spi_cs_1_io, + inout logic spi_sd_0_io, + inout logic spi_sd_1_io, + inout logic spi_sd_2_io, + inout logic spi_sd_3_io, + inout logic spi2_cs_0_io, + inout logic spi2_cs_1_io, + inout logic spi2_sck_io, + inout logic spi2_sd_0_io, + inout logic spi2_sd_1_io, + inout logic spi2_sd_2_io, + inout logic spi2_sd_3_io, + inout logic i2c_scl_io, + inout logic i2c_sda_io +); + + import core_v_mini_mcu_pkg::*; + + // PM signals + logic cpu_subsystem_powergate_switch; + logic cpu_subsystem_powergate_switch_ack; + logic cpu_subsystem_powergate_iso; + logic cpu_subsystem_rst_n; + logic peripheral_subsystem_powergate_switch; + logic peripheral_subsystem_powergate_switch_ack; + logic peripheral_subsystem_powergate_iso; + logic peripheral_subsystem_rst_n; + logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_switch; + logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_switch_ack; + logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_powergate_iso; + logic [core_v_mini_mcu_pkg::NUM_BANKS-1:0] memory_subsystem_banks_set_retentive; + + // PAD controller + reg_req_t pad_req; + reg_rsp_t pad_resp; + logic [core_v_mini_mcu_pkg::NUM_PAD-1:0][7:0] pad_attributes; + logic [core_v_mini_mcu_pkg::NUM_PAD-1:0][3:0] pad_muxes; + + logic rst_ngen; + + //input, output pins from core_v_mini_mcu + logic clk_in_x, clk_out_x, clk_oe_x; + + logic rst_nin_x, rst_nout_x, rst_noe_x; + + logic boot_select_in_x, boot_select_out_x, boot_select_oe_x; + + logic execute_from_flash_in_x, execute_from_flash_out_x, execute_from_flash_oe_x; + + logic jtag_tck_in_x, jtag_tck_out_x, jtag_tck_oe_x; + + logic jtag_tms_in_x, jtag_tms_out_x, jtag_tms_oe_x; + + logic jtag_trst_nin_x, jtag_trst_nout_x, jtag_trst_noe_x; + + logic jtag_tdi_in_x, jtag_tdi_out_x, jtag_tdi_oe_x; + + logic jtag_tdo_in_x, jtag_tdo_out_x, jtag_tdo_oe_x; + + logic uart_rx_in_x, uart_rx_out_x, uart_rx_oe_x; + + logic uart_tx_in_x, uart_tx_out_x, uart_tx_oe_x; + + logic exit_valid_in_x, exit_valid_out_x, exit_valid_oe_x; + + logic gpio_0_in_x, gpio_0_out_x, gpio_0_oe_x; + + logic gpio_1_in_x, gpio_1_out_x, gpio_1_oe_x; + + logic gpio_2_in_x, gpio_2_out_x, gpio_2_oe_x; + + logic gpio_3_in_x, gpio_3_out_x, gpio_3_oe_x; + + logic gpio_4_in_x, gpio_4_out_x, gpio_4_oe_x; + + logic gpio_5_in_x, gpio_5_out_x, gpio_5_oe_x; + + logic gpio_6_in_x, gpio_6_out_x, gpio_6_oe_x; + + logic gpio_7_in_x, gpio_7_out_x, gpio_7_oe_x; + + logic gpio_8_in_x, gpio_8_out_x, gpio_8_oe_x; + + logic gpio_9_in_x, gpio_9_out_x, gpio_9_oe_x; + + logic gpio_10_in_x, gpio_10_out_x, gpio_10_oe_x; + + logic gpio_11_in_x, gpio_11_out_x, gpio_11_oe_x; + + logic gpio_12_in_x, gpio_12_out_x, gpio_12_oe_x; + + logic gpio_13_in_x, gpio_13_out_x, gpio_13_oe_x; + + logic gpio_14_in_x, gpio_14_out_x, gpio_14_oe_x; + + logic gpio_15_in_x, gpio_15_out_x, gpio_15_oe_x; + + logic gpio_16_in_x, gpio_16_out_x, gpio_16_oe_x; + + logic gpio_17_in_x, gpio_17_out_x, gpio_17_oe_x; + + logic gpio_18_in_x, gpio_18_out_x, gpio_18_oe_x; + + logic gpio_19_in_x, gpio_19_out_x, gpio_19_oe_x; + + logic gpio_20_in_x, gpio_20_out_x, gpio_20_oe_x; + + logic gpio_21_in_x, gpio_21_out_x, gpio_21_oe_x; + + logic gpio_22_in_x, gpio_22_out_x, gpio_22_oe_x; + + logic spi_flash_sck_in_x, spi_flash_sck_out_x, spi_flash_sck_oe_x; + + logic spi_flash_cs_0_in_x, spi_flash_cs_0_out_x, spi_flash_cs_0_oe_x; + + logic spi_flash_cs_1_in_x, spi_flash_cs_1_out_x, spi_flash_cs_1_oe_x; + + logic spi_flash_sd_0_in_x, spi_flash_sd_0_out_x, spi_flash_sd_0_oe_x; + + logic spi_flash_sd_1_in_x, spi_flash_sd_1_out_x, spi_flash_sd_1_oe_x; + + logic spi_flash_sd_2_in_x, spi_flash_sd_2_out_x, spi_flash_sd_2_oe_x; + + logic spi_flash_sd_3_in_x, spi_flash_sd_3_out_x, spi_flash_sd_3_oe_x; + + logic spi_sck_in_x, spi_sck_out_x, spi_sck_oe_x; + + logic spi_cs_0_in_x, spi_cs_0_out_x, spi_cs_0_oe_x; + + logic spi_cs_1_in_x, spi_cs_1_out_x, spi_cs_1_oe_x; + + logic spi_sd_0_in_x, spi_sd_0_out_x, spi_sd_0_oe_x; + + logic spi_sd_1_in_x, spi_sd_1_out_x, spi_sd_1_oe_x; + + logic spi_sd_2_in_x, spi_sd_2_out_x, spi_sd_2_oe_x; + + logic spi_sd_3_in_x, spi_sd_3_out_x, spi_sd_3_oe_x; + + logic spi2_cs_0_in_x, spi2_cs_0_out_x, spi2_cs_0_oe_x; + logic gpio_23_in_x, gpio_23_out_x, gpio_23_oe_x; + logic spi2_cs_0_in_x_muxed, spi2_cs_0_out_x_muxed, spi2_cs_0_oe_x_muxed; + + logic spi2_cs_1_in_x, spi2_cs_1_out_x, spi2_cs_1_oe_x; + logic gpio_24_in_x, gpio_24_out_x, gpio_24_oe_x; + logic spi2_cs_1_in_x_muxed, spi2_cs_1_out_x_muxed, spi2_cs_1_oe_x_muxed; + + logic spi2_sck_in_x, spi2_sck_out_x, spi2_sck_oe_x; + logic gpio_25_in_x, gpio_25_out_x, gpio_25_oe_x; + logic spi2_sck_in_x_muxed, spi2_sck_out_x_muxed, spi2_sck_oe_x_muxed; + + logic spi2_sd_0_in_x, spi2_sd_0_out_x, spi2_sd_0_oe_x; + logic gpio_26_in_x, gpio_26_out_x, gpio_26_oe_x; + logic spi2_sd_0_in_x_muxed, spi2_sd_0_out_x_muxed, spi2_sd_0_oe_x_muxed; + + logic spi2_sd_1_in_x, spi2_sd_1_out_x, spi2_sd_1_oe_x; + logic gpio_27_in_x, gpio_27_out_x, gpio_27_oe_x; + logic spi2_sd_1_in_x_muxed, spi2_sd_1_out_x_muxed, spi2_sd_1_oe_x_muxed; + + logic spi2_sd_2_in_x, spi2_sd_2_out_x, spi2_sd_2_oe_x; + logic gpio_28_in_x, gpio_28_out_x, gpio_28_oe_x; + logic spi2_sd_2_in_x_muxed, spi2_sd_2_out_x_muxed, spi2_sd_2_oe_x_muxed; + + logic spi2_sd_3_in_x, spi2_sd_3_out_x, spi2_sd_3_oe_x; + logic gpio_29_in_x, gpio_29_out_x, gpio_29_oe_x; + logic spi2_sd_3_in_x_muxed, spi2_sd_3_out_x_muxed, spi2_sd_3_oe_x_muxed; + + logic i2c_scl_in_x, i2c_scl_out_x, i2c_scl_oe_x; + logic gpio_31_in_x, gpio_31_out_x, gpio_31_oe_x; + logic i2c_scl_in_x_muxed, i2c_scl_out_x_muxed, i2c_scl_oe_x_muxed; + + logic i2c_sda_in_x, i2c_sda_out_x, i2c_sda_oe_x; + logic gpio_30_in_x, gpio_30_out_x, gpio_30_oe_x; + logic i2c_sda_in_x_muxed, i2c_sda_out_x_muxed, i2c_sda_oe_x_muxed; + + + core_v_mini_mcu #( + .PULP_XPULP(PULP_XPULP), + .FPU(FPU), + .PULP_ZFINX(PULP_ZFINX), + .EXT_XBAR_NMASTER(EXT_XBAR_NMASTER) + ) core_v_mini_mcu_i ( + + .rst_ni(rst_ngen), + .clk_i (clk_in_x), + + + .boot_select_i(boot_select_in_x), + + .execute_from_flash_i(execute_from_flash_in_x), + + .jtag_tck_i(jtag_tck_in_x), + + .jtag_tms_i(jtag_tms_in_x), + + .jtag_trst_ni(jtag_trst_nin_x), + + .jtag_tdi_i(jtag_tdi_in_x), + + .jtag_tdo_o(jtag_tdo_out_x), + + .uart_rx_i(uart_rx_in_x), + + .uart_tx_o(uart_tx_out_x), + + .exit_valid_o(exit_valid_out_x), + + .gpio_0_i(gpio_0_in_x), + .gpio_0_o(gpio_0_out_x), + .gpio_0_oe_o(gpio_0_oe_x), + + .gpio_1_i(gpio_1_in_x), + .gpio_1_o(gpio_1_out_x), + .gpio_1_oe_o(gpio_1_oe_x), + + .gpio_2_i(gpio_2_in_x), + .gpio_2_o(gpio_2_out_x), + .gpio_2_oe_o(gpio_2_oe_x), + + .gpio_3_i(gpio_3_in_x), + .gpio_3_o(gpio_3_out_x), + .gpio_3_oe_o(gpio_3_oe_x), + + .gpio_4_i(gpio_4_in_x), + .gpio_4_o(gpio_4_out_x), + .gpio_4_oe_o(gpio_4_oe_x), + + .gpio_5_i(gpio_5_in_x), + .gpio_5_o(gpio_5_out_x), + .gpio_5_oe_o(gpio_5_oe_x), + + .gpio_6_i(gpio_6_in_x), + .gpio_6_o(gpio_6_out_x), + .gpio_6_oe_o(gpio_6_oe_x), + + .gpio_7_i(gpio_7_in_x), + .gpio_7_o(gpio_7_out_x), + .gpio_7_oe_o(gpio_7_oe_x), + + .gpio_8_i(gpio_8_in_x), + .gpio_8_o(gpio_8_out_x), + .gpio_8_oe_o(gpio_8_oe_x), + + .gpio_9_i(gpio_9_in_x), + .gpio_9_o(gpio_9_out_x), + .gpio_9_oe_o(gpio_9_oe_x), + + .gpio_10_i(gpio_10_in_x), + .gpio_10_o(gpio_10_out_x), + .gpio_10_oe_o(gpio_10_oe_x), + + .gpio_11_i(gpio_11_in_x), + .gpio_11_o(gpio_11_out_x), + .gpio_11_oe_o(gpio_11_oe_x), + + .gpio_12_i(gpio_12_in_x), + .gpio_12_o(gpio_12_out_x), + .gpio_12_oe_o(gpio_12_oe_x), + + .gpio_13_i(gpio_13_in_x), + .gpio_13_o(gpio_13_out_x), + .gpio_13_oe_o(gpio_13_oe_x), + + .gpio_14_i(gpio_14_in_x), + .gpio_14_o(gpio_14_out_x), + .gpio_14_oe_o(gpio_14_oe_x), + + .gpio_15_i(gpio_15_in_x), + .gpio_15_o(gpio_15_out_x), + .gpio_15_oe_o(gpio_15_oe_x), + + .gpio_16_i(gpio_16_in_x), + .gpio_16_o(gpio_16_out_x), + .gpio_16_oe_o(gpio_16_oe_x), + + .gpio_17_i(gpio_17_in_x), + .gpio_17_o(gpio_17_out_x), + .gpio_17_oe_o(gpio_17_oe_x), + + .gpio_18_i(gpio_18_in_x), + .gpio_18_o(gpio_18_out_x), + .gpio_18_oe_o(gpio_18_oe_x), + + .gpio_19_i(gpio_19_in_x), + .gpio_19_o(gpio_19_out_x), + .gpio_19_oe_o(gpio_19_oe_x), + + .gpio_20_i(gpio_20_in_x), + .gpio_20_o(gpio_20_out_x), + .gpio_20_oe_o(gpio_20_oe_x), + + .gpio_21_i(gpio_21_in_x), + .gpio_21_o(gpio_21_out_x), + .gpio_21_oe_o(gpio_21_oe_x), + + .gpio_22_i(gpio_22_in_x), + .gpio_22_o(gpio_22_out_x), + .gpio_22_oe_o(gpio_22_oe_x), + + .spi_flash_sck_i(spi_flash_sck_in_x), + .spi_flash_sck_o(spi_flash_sck_out_x), + .spi_flash_sck_oe_o(spi_flash_sck_oe_x), + + .spi_flash_cs_0_i(spi_flash_cs_0_in_x), + .spi_flash_cs_0_o(spi_flash_cs_0_out_x), + .spi_flash_cs_0_oe_o(spi_flash_cs_0_oe_x), + + .spi_flash_cs_1_i(spi_flash_cs_1_in_x), + .spi_flash_cs_1_o(spi_flash_cs_1_out_x), + .spi_flash_cs_1_oe_o(spi_flash_cs_1_oe_x), + + .spi_flash_sd_0_i(spi_flash_sd_0_in_x), + .spi_flash_sd_0_o(spi_flash_sd_0_out_x), + .spi_flash_sd_0_oe_o(spi_flash_sd_0_oe_x), + + .spi_flash_sd_1_i(spi_flash_sd_1_in_x), + .spi_flash_sd_1_o(spi_flash_sd_1_out_x), + .spi_flash_sd_1_oe_o(spi_flash_sd_1_oe_x), + + .spi_flash_sd_2_i(spi_flash_sd_2_in_x), + .spi_flash_sd_2_o(spi_flash_sd_2_out_x), + .spi_flash_sd_2_oe_o(spi_flash_sd_2_oe_x), + + .spi_flash_sd_3_i(spi_flash_sd_3_in_x), + .spi_flash_sd_3_o(spi_flash_sd_3_out_x), + .spi_flash_sd_3_oe_o(spi_flash_sd_3_oe_x), + + .spi_sck_i(spi_sck_in_x), + .spi_sck_o(spi_sck_out_x), + .spi_sck_oe_o(spi_sck_oe_x), + + .spi_cs_0_i(spi_cs_0_in_x), + .spi_cs_0_o(spi_cs_0_out_x), + .spi_cs_0_oe_o(spi_cs_0_oe_x), + + .spi_cs_1_i(spi_cs_1_in_x), + .spi_cs_1_o(spi_cs_1_out_x), + .spi_cs_1_oe_o(spi_cs_1_oe_x), + + .spi_sd_0_i(spi_sd_0_in_x), + .spi_sd_0_o(spi_sd_0_out_x), + .spi_sd_0_oe_o(spi_sd_0_oe_x), + + .spi_sd_1_i(spi_sd_1_in_x), + .spi_sd_1_o(spi_sd_1_out_x), + .spi_sd_1_oe_o(spi_sd_1_oe_x), + + .spi_sd_2_i(spi_sd_2_in_x), + .spi_sd_2_o(spi_sd_2_out_x), + .spi_sd_2_oe_o(spi_sd_2_oe_x), + + .spi_sd_3_i(spi_sd_3_in_x), + .spi_sd_3_o(spi_sd_3_out_x), + .spi_sd_3_oe_o(spi_sd_3_oe_x), + + .spi2_cs_0_i(spi2_cs_0_in_x), + .spi2_cs_0_o(spi2_cs_0_out_x), + .spi2_cs_0_oe_o(spi2_cs_0_oe_x), + .gpio_23_i(gpio_23_in_x), + .gpio_23_o(gpio_23_out_x), + .gpio_23_oe_o(gpio_23_oe_x), + + .spi2_cs_1_i(spi2_cs_1_in_x), + .spi2_cs_1_o(spi2_cs_1_out_x), + .spi2_cs_1_oe_o(spi2_cs_1_oe_x), + .gpio_24_i(gpio_24_in_x), + .gpio_24_o(gpio_24_out_x), + .gpio_24_oe_o(gpio_24_oe_x), + + .spi2_sck_i(spi2_sck_in_x), + .spi2_sck_o(spi2_sck_out_x), + .spi2_sck_oe_o(spi2_sck_oe_x), + .gpio_25_i(gpio_25_in_x), + .gpio_25_o(gpio_25_out_x), + .gpio_25_oe_o(gpio_25_oe_x), + + .spi2_sd_0_i(spi2_sd_0_in_x), + .spi2_sd_0_o(spi2_sd_0_out_x), + .spi2_sd_0_oe_o(spi2_sd_0_oe_x), + .gpio_26_i(gpio_26_in_x), + .gpio_26_o(gpio_26_out_x), + .gpio_26_oe_o(gpio_26_oe_x), + + .spi2_sd_1_i(spi2_sd_1_in_x), + .spi2_sd_1_o(spi2_sd_1_out_x), + .spi2_sd_1_oe_o(spi2_sd_1_oe_x), + .gpio_27_i(gpio_27_in_x), + .gpio_27_o(gpio_27_out_x), + .gpio_27_oe_o(gpio_27_oe_x), + + .spi2_sd_2_i(spi2_sd_2_in_x), + .spi2_sd_2_o(spi2_sd_2_out_x), + .spi2_sd_2_oe_o(spi2_sd_2_oe_x), + .gpio_28_i(gpio_28_in_x), + .gpio_28_o(gpio_28_out_x), + .gpio_28_oe_o(gpio_28_oe_x), + + .spi2_sd_3_i(spi2_sd_3_in_x), + .spi2_sd_3_o(spi2_sd_3_out_x), + .spi2_sd_3_oe_o(spi2_sd_3_oe_x), + .gpio_29_i(gpio_29_in_x), + .gpio_29_o(gpio_29_out_x), + .gpio_29_oe_o(gpio_29_oe_x), + + .i2c_scl_i(i2c_scl_in_x), + .i2c_scl_o(i2c_scl_out_x), + .i2c_scl_oe_o(i2c_scl_oe_x), + .gpio_31_i(gpio_31_in_x), + .gpio_31_o(gpio_31_out_x), + .gpio_31_oe_o(gpio_31_oe_x), + + .i2c_sda_i(i2c_sda_in_x), + .i2c_sda_o(i2c_sda_out_x), + .i2c_sda_oe_o(i2c_sda_oe_x), + .gpio_30_i(gpio_30_in_x), + .gpio_30_o(gpio_30_out_x), + .gpio_30_oe_o(gpio_30_oe_x), + + .intr_vector_ext_i, + .pad_req_o(pad_req), + .pad_resp_i(pad_resp), + .ext_xbar_master_req_i, + .ext_xbar_master_resp_o, + .ext_xbar_slave_req_o, + .ext_xbar_slave_resp_i, + .ext_peripheral_slave_req_o, + .ext_peripheral_slave_resp_i, + .cpu_subsystem_powergate_switch_o(cpu_subsystem_powergate_switch), + .cpu_subsystem_powergate_switch_ack_i(cpu_subsystem_powergate_switch_ack), + .peripheral_subsystem_powergate_switch_o(peripheral_subsystem_powergate_switch), + .peripheral_subsystem_powergate_switch_ack_i(peripheral_subsystem_powergate_switch_ack), + .memory_subsystem_banks_powergate_switch_o(memory_subsystem_banks_powergate_switch), + .memory_subsystem_banks_powergate_switch_ack_i(memory_subsystem_banks_powergate_switch_ack), + .external_subsystem_powergate_switch_o, + .external_subsystem_powergate_switch_ack_i, + .external_subsystem_powergate_iso_o, + .external_subsystem_rst_no, + .external_ram_banks_set_retentive_o, + .exit_value_o + ); + + + import pkg_padframe::port_signals_soc2pad_t; + import pkg_padframe::port_signals_pad2soc_t; + import pkg_padframe::static_connection_signals_soc2pad_t; + import pkg_padframe::static_connection_signals_pad2soc_t; + + port_signals_soc2pad_t port_signals_soc2pad; + port_signals_pad2soc_t port_signals_pad2soc; + static_connection_signals_soc2pad_t static_connection_signals_soc2pad; + static_connection_signals_pad2soc_t static_connection_signals_pad2soc; + + assign static_connection_signals_soc2pad.xheep.exit_valid_i = exit_valid_out_x; + assign static_connection_signals_soc2pad.xheep.jtag_tdo_i = jtag_tdo_out_x; + assign static_connection_signals_soc2pad.xheep.uart_tx_i = uart_tx_out_x; + assign static_connection_signals_soc2pad.xheep.spi_sck_i = spi_sck_out_x; + assign static_connection_signals_soc2pad.xheep.spi_cs_00_i = spi_cs_0_out_x; + assign static_connection_signals_soc2pad.xheep.spi_cs_01_i = spi_cs_1_out_x; + assign static_connection_signals_soc2pad.xheep.spi_cs_00_oe_i = spi_cs_0_oe_x; + assign static_connection_signals_soc2pad.xheep.spi_cs_01_oe_i = spi_cs_1_oe_x; + assign static_connection_signals_soc2pad.xheep.spi_sd_00_i = spi_sd_0_out_x; + assign static_connection_signals_soc2pad.xheep.spi_sd_01_i = spi_sd_1_out_x; + assign static_connection_signals_soc2pad.xheep.spi_sd_02_i = spi_sd_2_out_x; + assign static_connection_signals_soc2pad.xheep.spi_sd_03_i = spi_sd_3_out_x; + assign static_connection_signals_soc2pad.xheep.spi_sd_00_oe_i = spi_sd_0_oe_x; + assign static_connection_signals_soc2pad.xheep.spi_sd_01_oe_i = spi_sd_1_oe_x; + assign static_connection_signals_soc2pad.xheep.spi_sd_02_oe_i = spi_sd_2_oe_x; + assign static_connection_signals_soc2pad.xheep.spi_sd_03_oe_i = spi_sd_3_oe_x; + + assign static_connection_signals_soc2pad.xheep.spi_flash_sck_i = spi_flash_sck_out_x; + assign static_connection_signals_soc2pad.xheep.spi_flash_cs_00_i = spi_flash_cs_0_out_x; + assign static_connection_signals_soc2pad.xheep.spi_flash_cs_01_i = spi_flash_cs_1_out_x; + assign static_connection_signals_soc2pad.xheep.spi_flash_cs_00_oe_i = spi_flash_cs_0_oe_x; + assign static_connection_signals_soc2pad.xheep.spi_flash_cs_01_oe_i = spi_flash_cs_1_oe_x; + assign static_connection_signals_soc2pad.xheep.spi_flash_sd_00_i = spi_flash_sd_0_out_x; + assign static_connection_signals_soc2pad.xheep.spi_flash_sd_01_i = spi_flash_sd_1_out_x; + assign static_connection_signals_soc2pad.xheep.spi_flash_sd_02_i = spi_flash_sd_2_out_x; + assign static_connection_signals_soc2pad.xheep.spi_flash_sd_03_i = spi_flash_sd_3_out_x; + assign static_connection_signals_soc2pad.xheep.spi_flash_sd_00_oe_i = spi_flash_sd_0_oe_x; + assign static_connection_signals_soc2pad.xheep.spi_flash_sd_01_oe_i = spi_flash_sd_1_oe_x; + assign static_connection_signals_soc2pad.xheep.spi_flash_sd_02_oe_i = spi_flash_sd_2_oe_x; + assign static_connection_signals_soc2pad.xheep.spi_flash_sd_03_oe_i = spi_flash_sd_3_oe_x; + + assign static_connection_signals_soc2pad.xheep.gpio_00_i = gpio_0_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_01_i = gpio_1_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_02_i = gpio_2_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_03_i = gpio_3_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_04_i = gpio_4_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_05_i = gpio_5_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_06_i = gpio_6_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_07_i = gpio_7_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_08_i = gpio_8_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_09_i = gpio_9_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_10_i = gpio_10_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_11_i = gpio_11_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_12_i = gpio_12_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_13_i = gpio_13_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_14_i = gpio_14_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_15_i = gpio_15_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_16_i = gpio_16_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_17_i = gpio_17_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_18_i = gpio_18_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_19_i = gpio_19_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_20_i = gpio_20_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_21_i = gpio_21_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_22_i = gpio_22_out_x; + assign static_connection_signals_soc2pad.xheep.gpio_00_oe_i = gpio_0_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_01_oe_i = gpio_1_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_02_oe_i = gpio_2_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_03_oe_i = gpio_3_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_04_oe_i = gpio_4_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_05_oe_i = gpio_5_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_06_oe_i = gpio_6_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_07_oe_i = gpio_7_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_08_oe_i = gpio_8_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_09_oe_i = gpio_9_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_10_oe_i = gpio_10_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_11_oe_i = gpio_11_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_12_oe_i = gpio_12_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_13_oe_i = gpio_13_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_14_oe_i = gpio_14_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_15_oe_i = gpio_15_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_16_oe_i = gpio_16_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_17_oe_i = gpio_17_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_18_oe_i = gpio_18_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_19_oe_i = gpio_19_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_20_oe_i = gpio_20_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_21_oe_i = gpio_21_oe_x; + assign static_connection_signals_soc2pad.xheep.gpio_22_oe_i = gpio_22_oe_x; + + assign clk_in_x = static_connection_signals_pad2soc.xheep.clk_o; + assign rst_nin_x = static_connection_signals_pad2soc.xheep.rst_o; + assign boot_select_in_x = static_connection_signals_pad2soc.xheep.boot_select_o; + assign execute_from_flash_in_x = static_connection_signals_pad2soc.xheep.execute_from_flash_o; + assign uart_rx_in_x = static_connection_signals_pad2soc.xheep.uart_rx_o; + + assign jtag_tck_in_x = static_connection_signals_pad2soc.xheep.jtag_tck_o; + assign jtag_tdi_in_x = static_connection_signals_pad2soc.xheep.jtag_tdi_o; + assign jtag_tms_in_x = static_connection_signals_pad2soc.xheep.jtag_tms_o; + assign jtag_trst_in_x = static_connection_signals_pad2soc.xheep.jtag_trst_o; + assign spi_sck_in_x = static_connection_signals_pad2soc.xheep.spi_sck_o; + assign spi_cs_0_in_x = static_connection_signals_pad2soc.xheep.spi_cs_00_o; + assign spi_cs_1_in_x = static_connection_signals_pad2soc.xheep.spi_cs_01_o; + assign spi_sd_0_in_x = static_connection_signals_pad2soc.xheep.spi_sd_00_o; + assign spi_sd_1_in_x = static_connection_signals_pad2soc.xheep.spi_sd_01_o; + assign spi_sd_2_in_x = static_connection_signals_pad2soc.xheep.spi_sd_02_o; + assign spi_sd_3_in_x = static_connection_signals_pad2soc.xheep.spi_sd_03_o; + + assign spi_flash_sck_in_x = static_connection_signals_pad2soc.xheep.spi_flash_sck_o; + assign spi_flash_cs_0_in_x = static_connection_signals_pad2soc.xheep.spi_flash_cs_00_o; + assign spi_flash_cs_1_in_x = static_connection_signals_pad2soc.xheep.spi_flash_cs_01_o; + assign spi_flash_sd_0_in_x = static_connection_signals_pad2soc.xheep.spi_flash_sd_00_o; + assign spi_flash_sd_1_in_x = static_connection_signals_pad2soc.xheep.spi_flash_sd_01_o; + assign spi_flash_sd_2_in_x = static_connection_signals_pad2soc.xheep.spi_flash_sd_02_o; + assign spi_flash_sd_3_in_x = static_connection_signals_pad2soc.xheep.spi_flash_sd_03_o; + + assign gpio_0_in_x = static_connection_signals_pad2soc.xheep.gpio_00_o; + assign gpio_1_in_x = static_connection_signals_pad2soc.xheep.gpio_01_o; + assign gpio_2_in_x = static_connection_signals_pad2soc.xheep.gpio_02_o; + assign gpio_3_in_x = static_connection_signals_pad2soc.xheep.gpio_03_o; + assign gpio_4_in_x = static_connection_signals_pad2soc.xheep.gpio_04_o; + assign gpio_5_in_x = static_connection_signals_pad2soc.xheep.gpio_05_o; + assign gpio_6_in_x = static_connection_signals_pad2soc.xheep.gpio_06_o; + assign gpio_7_in_x = static_connection_signals_pad2soc.xheep.gpio_07_o; + assign gpio_8_in_x = static_connection_signals_pad2soc.xheep.gpio_08_o; + assign gpio_9_in_x = static_connection_signals_pad2soc.xheep.gpio_09_o; + assign gpio_10_in_x = static_connection_signals_pad2soc.xheep.gpio_10_o; + assign gpio_11_in_x = static_connection_signals_pad2soc.xheep.gpio_11_o; + assign gpio_12_in_x = static_connection_signals_pad2soc.xheep.gpio_12_o; + assign gpio_13_in_x = static_connection_signals_pad2soc.xheep.gpio_13_o; + assign gpio_14_in_x = static_connection_signals_pad2soc.xheep.gpio_14_o; + assign gpio_15_in_x = static_connection_signals_pad2soc.xheep.gpio_15_o; + assign gpio_16_in_x = static_connection_signals_pad2soc.xheep.gpio_16_o; + assign gpio_17_in_x = static_connection_signals_pad2soc.xheep.gpio_17_o; + assign gpio_18_in_x = static_connection_signals_pad2soc.xheep.gpio_18_o; + assign gpio_19_in_x = static_connection_signals_pad2soc.xheep.gpio_19_o; + assign gpio_20_in_x = static_connection_signals_pad2soc.xheep.gpio_20_o; + assign gpio_21_in_x = static_connection_signals_pad2soc.xheep.gpio_21_o; + assign gpio_22_in_x = static_connection_signals_pad2soc.xheep.gpio_22_o; + + + assign port_signals_soc2pad.xheep.i2c.i2c_scl_i = i2c_scl_out_x; + assign port_signals_soc2pad.xheep.i2c.i2c_sda_i = i2c_sda_out_x; + assign port_signals_soc2pad.xheep.i2c.i2c_scl_oe_i = i2c_scl_oe_x; + assign port_signals_soc2pad.xheep.i2c.i2c_sda_oe_i = i2c_sda_oe_x; + assign port_signals_soc2pad.xheep.gpio.gpio_30_i = gpio_30_out_x; + assign port_signals_soc2pad.xheep.gpio.gpio_31_i = gpio_31_out_x; + assign port_signals_soc2pad.xheep.gpio.gpio_30_oe_i = gpio_30_oe_x; + assign port_signals_soc2pad.xheep.gpio.gpio_31_oe_i = gpio_31_oe_x; + assign port_signals_soc2pad.xheep.spi2.spi2_sck_i = spi2_sck_out_x; + assign port_signals_soc2pad.xheep.spi2.spi2_sck_oe_i = spi2_sck_oe_x; + assign port_signals_soc2pad.xheep.spi2.spi2_cs_00_i = spi2_cs_0_out_x; + assign port_signals_soc2pad.xheep.spi2.spi2_cs_01_i = spi2_cs_1_out_x; + assign port_signals_soc2pad.xheep.spi2.spi2_cs_00_oe_i = spi_cs_0_oe_x; + assign port_signals_soc2pad.xheep.spi2.spi2_cs_01_oe_i = spi_cs_1_oe_x; + assign port_signals_soc2pad.xheep.spi2.spi2_sd_00_i = spi2_sd_0_in_x; + assign port_signals_soc2pad.xheep.spi2.spi2_sd_01_i = spi2_sd_1_in_x; + assign port_signals_soc2pad.xheep.spi2.spi2_sd_02_i = spi2_sd_2_in_x; + assign port_signals_soc2pad.xheep.spi2.spi2_sd_03_i = spi2_sd_3_in_x; + assign port_signals_soc2pad.xheep.spi2.spi2_sd_00_oe_i = spi2_sd_0_oe_x; + assign port_signals_soc2pad.xheep.spi2.spi2_sd_01_oe_i = spi2_sd_1_oe_x; + assign port_signals_soc2pad.xheep.spi2.spi2_sd_02_oe_i = spi2_sd_2_oe_x; + assign port_signals_soc2pad.xheep.spi2.spi2_sd_03_oe_i = spi2_sd_3_oe_x; + + + assign i2c_scl_in_x = port_signals_pad2soc.xheep.i2c.i2c_scl_o; + assign i2c_sda_in_x = port_signals_pad2soc.xheep.i2c.i2c_sda_o; + assign gpio_30_in_x = port_signals_pad2soc.xheep.gpio.gpio_30_o; + assign gpio_31_in_x = port_signals_pad2soc.xheep.gpio.gpio_31_o; + assign spi2_sck_in_x = port_signals_pad2soc.xheep.spi2.spi2_sck_o; + assign spi2_cs_0_in_x = port_signals_pad2soc.xheep.spi2.spi2_cs_00_o; + assign spi2_cs_1_in_x = port_signals_pad2soc.xheep.spi2.spi2_cs_01_o; + assign spi2_sd_0_in_x = port_signals_pad2soc.xheep.spi2.spi2_sd_00_o; + assign spi2_sd_1_in_x = port_signals_pad2soc.xheep.spi2.spi2_sd_01_o; + assign spi2_sd_2_in_x = port_signals_pad2soc.xheep.spi2.spi2_sd_02_o; + assign spi2_sd_3_in_x = port_signals_pad2soc.xheep.spi2.spi2_sd_03_o; + + assign clk_out_x = 1'b0; + assign clk_oe_x = 1'b0; + assign rst_nout_x = 1'b0; + assign rst_noe_x = 1'b0; + assign boot_select_out_x = 1'b0; + assign boot_select_oe_x = 1'b0; + assign execute_from_flash_out_x = 1'b0; + assign execute_from_flash_oe_x = 1'b0; + assign jtag_tck_out_x = 1'b0; + assign jtag_tck_oe_x = 1'b0; + assign jtag_tms_out_x = 1'b0; + assign jtag_tms_oe_x = 1'b0; + assign jtag_trst_nout_x = 1'b0; + assign jtag_trst_noe_x = 1'b0; + assign jtag_tdi_out_x = 1'b0; + assign jtag_tdi_oe_x = 1'b0; + assign jtag_tdo_oe_x = 1'b1; + assign uart_rx_out_x = 1'b0; + assign uart_rx_oe_x = 1'b0; + assign uart_tx_oe_x = 1'b1; + assign exit_valid_oe_x = 1'b1; + + padframe #( + .req_t (reg_pkg::reg_req_t), + .resp_t(reg_pkg::reg_rsp_t) + ) xpadframe ( + .clk_i (clk_in_x), + .rst_ni (rst_nin_x), + .static_connection_signals_pad2soc (static_connection_signals_pad2soc), + .static_connection_signals_soc2pad (static_connection_signals_soc2pad), + .port_signals_pad2soc (port_signals_pad2soc), + .port_signals_soc2pad (port_signals_soc2pad), + .pad_xheep_pad_clk_pad (clk_i), + .pad_xheep_pad_rst_pad (rst_ni), + .pad_xheep_pad_boot_select_pad (boot_select_i), + .pad_xheep_pad_execute_from_flash_pad(execute_from_flash_i), + .pad_xheep_pad_jtag_tck_pad (jtag_tck_i), + .pad_xheep_pad_jtag_tms_pad (jtag_tms_i), + .pad_xheep_pad_jtag_trst_pad (jtag_trst_i), + .pad_xheep_pad_jtag_tdi_pad (jtag_tdi_i), + .pad_xheep_pad_jtag_tdo_pad (jtag_tdo_o), + .pad_xheep_pad_exit_valid_pad (exit_valid_o), + .pad_xheep_pad_uart_rx_pad (uart_rx_i), + .pad_xheep_pad_uart_tx_pad (uart_tx_o), + .pad_xheep_pad_gpio_00_i_pad (gpio_0_io), + .pad_xheep_pad_gpio_01_i_pad (gpio_1_io), + .pad_xheep_pad_gpio_02_i_pad (gpio_2_io), + .pad_xheep_pad_gpio_03_i_pad (gpio_3_io), + .pad_xheep_pad_gpio_04_i_pad (gpio_4_io), + .pad_xheep_pad_gpio_05_i_pad (gpio_5_io), + .pad_xheep_pad_gpio_06_i_pad (gpio_6_io), + .pad_xheep_pad_gpio_07_i_pad (gpio_7_io), + .pad_xheep_pad_gpio_08_i_pad (gpio_8_io), + .pad_xheep_pad_gpio_09_i_pad (gpio_9_io), + .pad_xheep_pad_gpio_10_i_pad (gpio_10_io), + .pad_xheep_pad_gpio_11_i_pad (gpio_11_io), + .pad_xheep_pad_gpio_12_i_pad (gpio_12_io), + .pad_xheep_pad_gpio_13_i_pad (gpio_13_io), + .pad_xheep_pad_gpio_14_i_pad (gpio_14_io), + .pad_xheep_pad_gpio_15_i_pad (gpio_15_io), + .pad_xheep_pad_gpio_16_i_pad (gpio_16_io), + .pad_xheep_pad_gpio_17_i_pad (gpio_17_io), + .pad_xheep_pad_gpio_18_i_pad (gpio_18_io), + .pad_xheep_pad_gpio_19_i_pad (gpio_19_io), + .pad_xheep_pad_gpio_20_i_pad (gpio_20_io), + .pad_xheep_pad_gpio_21_i_pad (gpio_21_io), + .pad_xheep_pad_gpio_22_i_pad (gpio_22_io), + .pad_xheep_pad_spi_flash_sck_pad (spi_flash_sck_io), + .pad_xheep_pad_spi_flash_cs_00_pad (spi_flash_cs_0_io), + .pad_xheep_pad_spi_flash_cs_01_pad (spi_flash_cs_1_io), + .pad_xheep_pad_spi_flash_sd_00_pad (spi_flash_sd_0_io), + .pad_xheep_pad_spi_flash_sd_01_pad (spi_flash_sd_1_io), + .pad_xheep_pad_spi_flash_sd_02_pad (spi_flash_sd_2_io), + .pad_xheep_pad_spi_flash_sd_03_pad (spi_flash_sd_3_io), + .pad_xheep_pad_spi_sck_pad (spi_sck_io), + .pad_xheep_pad_spi_cs_00_pad (spi_cs_0_io), + .pad_xheep_pad_spi_cs_01_pad (spi_cs_1_io), + .pad_xheep_pad_spi_sd_00_pad (spi_sd_0_io), + .pad_xheep_pad_spi_sd_01_pad (spi_sd_1_io), + .pad_xheep_pad_spi_sd_02_pad (spi_sd_2_io), + .pad_xheep_pad_spi_sd_03_pad (spi_sd_3_io), + .pad_xheep_pad_io_23_pad (spi2_cs_0_io), + .pad_xheep_pad_io_24_pad (spi2_cs_1_io), + .pad_xheep_pad_io_25_pad (spi2_sck_io), + .pad_xheep_pad_io_26_pad (spi2_sd_0_io), + .pad_xheep_pad_io_27_pad (spi2_sd_1_io), + .pad_xheep_pad_io_28_pad (spi2_sd_2_io), + .pad_xheep_pad_io_29_pad (spi2_sd_3_io), + .pad_xheep_pad_io_30_pad (i2c_sda_io), + .pad_xheep_pad_io_31_pad (i2c_scl_io), + .config_req_i (pad_req), + .config_rsp_o (pad_resp) + ); + + rstgen rstgen_i ( + .clk_i(clk_in_x), + .rst_ni(rst_nin_x), + .test_mode_i(1'b0), + .rst_no(rst_ngen), + .init_no() + ); + + +endmodule // x_heep_system diff --git a/hw/vendor/pulp_platform_gpio.core b/hw/vendor/pulp_platform_gpio.core new file mode 100644 index 000000000..542140490 --- /dev/null +++ b/hw/vendor/pulp_platform_gpio.core @@ -0,0 +1,43 @@ +CAPI=2: + +# Copyright 2021 OpenHW Group +# Solderpad Hardware License, Version 2.1, see LICENSE.md for details. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +name: "pulp-platform.org:ip:gpio" + +filesets: + rtl: + depend: + - pulp-platform.org::common_cells + - pulp-platform.org::register_interface + - pulp-platform.org::tech_cells_generic + files: + - pulp_platform_gpio/src/gpio_reg_pkg.sv + - pulp_platform_gpio/src/gpio_reg_top.sv + - pulp_platform_gpio/src/gpio.sv + file_type: systemVerilogSource + + no-clock-gate: + files: + - pulp_platform_gpio/src/gpio_input_stage_no_clk_gates.sv + file_type: systemVerilogSource + + clock-gate: + files: + - pulp_platform_gpio/src/gpio_input_stage.sv + file_type: systemVerilogSource + + testbench: + files: + - pulp_platform_gpio/test/tb_gpio.sv + file_type: systemVerilogSource + +targets: + default: &default_target + filesets: + - rtl + - "gpio-test? (testbench)" + - target_sim? (clock-gate) + - target_nexys-a7-100t? (no-clock-gate) + - target_pynq-z2? (no-clock-gate) \ No newline at end of file diff --git a/hw/vendor/pulp_platform_gpio.lock.hjson b/hw/vendor/pulp_platform_gpio.lock.hjson new file mode 100644 index 000000000..92e2ae1fc --- /dev/null +++ b/hw/vendor/pulp_platform_gpio.lock.hjson @@ -0,0 +1,6 @@ +{ + upstream: { + url: "https://github.com/pulp-platform/gpio.git", + rev: "a6d5c08f4b16c2b9b30c81fc79bd7abda837d953", + } +} diff --git a/hw/vendor/pulp_platform_gpio.vendor.hjson b/hw/vendor/pulp_platform_gpio.vendor.hjson new file mode 100644 index 000000000..24e0801cf --- /dev/null +++ b/hw/vendor/pulp_platform_gpio.vendor.hjson @@ -0,0 +1,12 @@ +// Copyright 2020 OpenHW Group +// Solderpad Hardware License, Version 2.1, see LICENSE.md for details. +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +{ + name: "pulp_platform_gpio", + target_dir: "pulp_platform_gpio", + + upstream: { + url: "https://github.com/pulp-platform/gpio.git", + rev: "a6d5c08f4b16c2b9b30c81fc79bd7abda837d953", + }, +} diff --git a/hw/vendor/pulp_platform_gpio/Bender.lock b/hw/vendor/pulp_platform_gpio/Bender.lock new file mode 100644 index 000000000..0a670c932 --- /dev/null +++ b/hw/vendor/pulp_platform_gpio/Bender.lock @@ -0,0 +1,46 @@ +packages: + apb: + revision: 5c4fa53bfd650959d05afa517e921ea9001a6cf3 + version: null + source: + Git: https://github.com/pulp-platform/apb.git + dependencies: + - common_cells + axi: + revision: 2f395b176bee1c769c80f060a4345fda965bb04b + version: 0.38.0 + source: + Git: https://github.com/pulp-platform/axi.git + dependencies: + - common_cells + - common_verification + - tech_cells_generic + common_cells: + revision: 9c1a1bdbd1a0928340863cad90c6fc0503da43a7 + version: 1.27.1 + source: + Git: https://github.com/pulp-platform/common_cells.git + dependencies: + - common_verification + - tech_cells_generic + common_verification: + revision: 9c07fa860593b2caabd9b5681740c25fac04b878 + version: 0.2.3 + source: + Git: https://github.com/pulp-platform/common_verification.git + dependencies: [] + register_interface: + revision: ceb3f9791449f60558d17a9444613bdf0819e027 + version: 0.3.7 + source: + Git: https://github.com/pulp-platform/register_interface.git + dependencies: + - axi + - common_cells + tech_cells_generic: + revision: aef525b2dc7670525fc293dfc55f167e371b8c35 + version: 0.2.10 + source: + Git: https://github.com/pulp-platform/tech_cells_generic.git + dependencies: + - common_verification diff --git a/hw/vendor/pulp_platform_gpio/Bender.yml b/hw/vendor/pulp_platform_gpio/Bender.yml new file mode 100644 index 000000000..fc815532b --- /dev/null +++ b/hw/vendor/pulp_platform_gpio/Bender.yml @@ -0,0 +1,28 @@ +package: + name: gpio + authors: + - "Manuel Eggimann " + +dependencies: + tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.9 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.21.0 } + common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0} + register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.3.1} + apb: { git: "https://github.com/pulp-platform/apb.git", rev: "5c4fa53bfd650959d05afa517e921ea9001a6cf3" } # To be udpated once PR #6 got merged. + axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.35.3 } + +sources: + - src/gpio_reg_pkg.sv + - src/gpio_reg_top.sv + - src/gpio.sv + - src/gpio_axi_lite_wrap.sv + - src/gpio_apb_wrap.sv + - target: all(any(test, gpio_include_tb_files), not(gpio_exclude_tb_files)) + files: + - test/tb_gpio.sv + - target: all(any(asic, gpio_with_clk_gates), not(gpio_no_clk_gates)) + files: + - src/gpio_input_stage.sv + - target: all(any(fpga, gpio_no_clk_gates), not(gpio_with_clk_gates)) + files: + - src/gpio_input_stage_no_clk_gates.sv diff --git a/hw/vendor/pulp_platform_gpio/CHANGELOG.md b/hw/vendor/pulp_platform_gpio/CHANGELOG.md new file mode 100644 index 000000000..a9bd1f70d --- /dev/null +++ b/hw/vendor/pulp_platform_gpio/CHANGELOG.md @@ -0,0 +1,26 @@ +# Changelog +All notable changes to this project will be documented in this file. + +The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/) +and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html). + +## 0.1.2 - 2022-12-04 +### Changelog +- Added make dependencies to auto-setup python env for reconfiguration + +### Fixed +- Fix some small issues reported by linter + +## 0.1.1 - 2022-10-07 +### Changed +- Bumped AXI version to v0.35.3 +- Added NumRepetitions to tb_gpio to choose test duration +- Refactored TB + +### Fixed +- Fix tx_en inversion bug for open-drain mode 1 +- Fix bug in TB that caused open-drain misbehavior not to be catched + + +## 0.1.0 - 2022-04-14 +Initial release diff --git a/hw/vendor/pulp_platform_gpio/LICENSE b/hw/vendor/pulp_platform_gpio/LICENSE new file mode 100644 index 000000000..18e4f6769 --- /dev/null +++ b/hw/vendor/pulp_platform_gpio/LICENSE @@ -0,0 +1,176 @@ +SOLDERPAD HARDWARE LICENSE version 0.51 + +This license is based closely on the Apache License Version 2.0, but is not +approved or endorsed by the Apache Foundation. A copy of the non-modified +Apache License 2.0 can be found at http://www.apache.org/licenses/LICENSE-2.0. + +As this license is not currently OSI or FSF approved, the Licensor permits any +Work licensed under this License, at the option of the Licensee, to be treated +as licensed under the Apache License Version 2.0 (which is so approved). + +This License is licensed under the terms of this License and in particular +clause 7 below (Disclaimer of Warranties) applies in relation to its use. + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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While redistributing the Work or +Derivative Works thereof, You may choose to offer, and charge a fee for, +acceptance of support, warranty, indemnity, or other liability obligations +and/or rights consistent with this License. However, in accepting such +obligations, You may act only on Your own behalf and on Your sole +responsibility, not on behalf of any other Contributor, and only if You agree +to indemnify, defend, and hold each Contributor harmless for any liability +incurred by, or claims asserted against, such Contributor by reason of your +accepting any such warranty or additional liability. + +END OF TERMS AND CONDITIONS diff --git a/hw/vendor/pulp_platform_gpio/Makefile b/hw/vendor/pulp_platform_gpio/Makefile new file mode 100644 index 000000000..fde3357e1 --- /dev/null +++ b/hw/vendor/pulp_platform_gpio/Makefile @@ -0,0 +1,35 @@ +.DEFAULT_GOAL := help + +VENVDIR?=$(WORKDIR)/.venv +REQUIREMENTS_TXT?=$(wildcard requirements.txt) +include Makefile.venv + +## Regenerate the register file and HAL C-header for a different GPIO count. Usage: make reconfigure GPIOS=128 +reconfigure: .bender/git/checkouts | venv + @sed -i -r 's/default: "[0-9]+"/default: "${GPIOS}"/g' gpio_regs.hjson + $(VENV)/python $$(./bender path register_interface)/vendor/lowrisc_opentitan/util/regtool.py gpio_regs.hjson -r -t src -p GPIOCount=${GPIOS} + $(VENV)/python $$(./bender path register_interface)/vendor/lowrisc_opentitan/util/regtool.py gpio_regs.hjson --cdefines -o hal/gpio_hal.h -p GPIOCount=${GPIOS}; + @echo "Done" + +.bender/git/checkouts: bender + bender update + bender path register_interface + +bender: +ifeq (,$(wildcard ./bender)) +ifeq (,$(shell which curl)) +$(error 'curl' is not installed on your machine. Please make sure to install it so we can download the bender binary.) +else + curl --proto '=https' --tlsv1.2 -sSf https://fabianschuiki.github.io/bender/init \ + | bash -s -- 0.26.1 + touch bender +endif +endif + + +.PHONY: help +help: Makefile + @printf "GPIO Reconfiguration\n" + @printf "Use this Makefile to regenerate the register file and HAL C-header for a different number GPIOs than the default one.\n\n" + @printf "Usage: \n" + @printf "make reconfigure GPIOS=\n\n" diff --git a/hw/vendor/pulp_platform_gpio/Makefile.venv b/hw/vendor/pulp_platform_gpio/Makefile.venv new file mode 100644 index 000000000..c79b9bbcd --- /dev/null +++ b/hw/vendor/pulp_platform_gpio/Makefile.venv @@ -0,0 +1,274 @@ +# +# SEAMLESSLY MANAGE PYTHON VIRTUAL ENVIRONMENT WITH A MAKEFILE +# +# https://github.com/sio/Makefile.venv v2022.07.20 +# +# +# Insert `include Makefile.venv` at the bottom of your Makefile to enable these +# rules. +# +# When writing your Makefile use '$(VENV)/python' to refer to the Python +# interpreter within virtual environment and '$(VENV)/executablename' for any +# other executable in venv. +# +# This Makefile provides the following targets: +# venv +# Use this as a dependency for any target that requires virtual +# environment to be created and configured +# python, ipython +# Use these to launch interactive Python shell within virtual environment +# shell, bash, zsh +# Launch interactive command line shell. "shell" target launches the +# default shell Makefile executes its rules in (usually /bin/sh). +# "bash" and "zsh" can be used to refer to the specific desired shell. +# show-venv +# Show versions of Python and pip, and the path to the virtual environment +# clean-venv +# Remove virtual environment +# $(VENV)/executable_name +# Install `executable_name` with pip. Only packages with names matching +# the name of the corresponding executable are supported. +# Use this as a lightweight mechanism for development dependencies +# tracking. E.g. for one-off tools that are not required in every +# developer's environment, therefore are not included into +# requirements.txt or setup.py. +# Note: +# Rules using such target or dependency MUST be defined below +# `include` directive to make use of correct $(VENV) value. +# Example: +# codestyle: $(VENV)/pyflakes +# $(VENV)/pyflakes . +# See `ipython` target below for another example. +# +# This Makefile can be configured via following variables: +# PY +# Command name for system Python interpreter. It is used only initially to +# create the virtual environment +# Default: python3 +# REQUIREMENTS_TXT +# Space separated list of paths to requirements.txt files. +# Paths are resolved relative to current working directory. +# Default: requirements.txt +# +# Non-existent files are treated as hard dependencies, +# recipes for creating such files must be provided by the main Makefile. +# Providing empty value (REQUIREMENTS_TXT=) turns off processing of +# requirements.txt even when the file exists. +# SETUP_PY +# Space separated list of paths to setup.py files. +# Corresponding packages will be installed into venv in editable mode +# along with all their dependencies +# Default: setup.py +# +# Non-existent and empty values are treated in the same way as for REQUIREMENTS_TXT. +# WORKDIR +# Parent directory for the virtual environment. +# Default: current working directory. +# VENVDIR +# Python virtual environment directory. +# Default: $(WORKDIR)/.venv +# +# This Makefile was written for GNU Make and may not work with other make +# implementations. +# +# +# Copyright (c) 2019-2020 Vitaly Potyarkin +# +# Licensed under the Apache License, Version 2.0 +# +# + + +# +# Configuration variables +# + +WORKDIR?=. +VENVDIR?=$(WORKDIR)/.venv +REQUIREMENTS_TXT?=$(wildcard requirements.txt) # Multiple paths are supported (space separated) +SETUP_PY?=$(wildcard setup.py) # Multiple paths are supported (space separated) +SETUP_CFG?=$(foreach s,$(SETUP_PY),$(wildcard $(patsubst %setup.py,%setup.cfg,$(s)))) +MARKER=.initialized-with-Makefile.venv + + +# +# Python interpreter detection +# + +_PY_AUTODETECT_MSG=Detected Python interpreter: $(PY). Use PY environment variable to override + +ifeq (ok,$(shell test -e /dev/null 2>&1 && echo ok)) +NULL_STDERR=2>/dev/null +else +NULL_STDERR=2>NUL +endif + +ifndef PY +_PY_OPTION:=python3 +ifeq (ok,$(shell $(_PY_OPTION) -c "print('ok')" $(NULL_STDERR))) +PY=$(_PY_OPTION) +endif +endif + +ifndef PY +_PY_OPTION:=$(VENVDIR)/bin/python +ifeq (ok,$(shell $(_PY_OPTION) -c "print('ok')" $(NULL_STDERR))) +PY=$(_PY_OPTION) +$(info $(_PY_AUTODETECT_MSG)) +endif +endif + +ifndef PY +_PY_OPTION:=$(subst /,\,$(VENVDIR)/Scripts/python) +ifeq (ok,$(shell $(_PY_OPTION) -c "print('ok')" $(NULL_STDERR))) +PY=$(_PY_OPTION) +$(info $(_PY_AUTODETECT_MSG)) +endif +endif + +ifndef PY +_PY_OPTION:=py -3 +ifeq (ok,$(shell $(_PY_OPTION) -c "print('ok')" $(NULL_STDERR))) +PY=$(_PY_OPTION) +$(info $(_PY_AUTODETECT_MSG)) +endif +endif + +ifndef PY +_PY_OPTION:=python +ifeq (ok,$(shell $(_PY_OPTION) -c "print('ok')" $(NULL_STDERR))) +PY=$(_PY_OPTION) +$(info $(_PY_AUTODETECT_MSG)) +endif +endif + +ifndef PY +define _PY_AUTODETECT_ERR +Could not detect Python interpreter automatically. +Please specify path to interpreter via PY environment variable. +endef +$(error $(_PY_AUTODETECT_ERR)) +endif + + +# +# Internal variable resolution +# + +VENV=$(VENVDIR)/bin +EXE= +# Detect windows +ifeq (win32,$(shell $(PY) -c "import __future__, sys; print(sys.platform)")) +VENV=$(VENVDIR)/Scripts +EXE=.exe +endif + +touch=touch $(1) +ifeq (,$(shell command -v touch $(NULL_STDERR))) +# https://ss64.com/nt/touch.html +touch=type nul >> $(subst /,\,$(1)) && copy /y /b $(subst /,\,$(1))+,, $(subst /,\,$(1)) +endif + +RM?=rm -f +ifeq (,$(shell command -v $(firstword $(RM)) $(NULL_STDERR))) +RMDIR:=rd /s /q +else +RMDIR:=$(RM) -r +endif + + +# +# Virtual environment +# + +.PHONY: venv +venv: $(VENV)/$(MARKER) + +.PHONY: clean-venv +clean-venv: + -$(RMDIR) "$(VENVDIR)" + +.PHONY: show-venv +show-venv: venv + @$(VENV)/python -c "import sys; print('Python ' + sys.version.replace('\n',''))" + @$(VENV)/pip --version + @echo venv: $(VENVDIR) + +.PHONY: debug-venv +debug-venv: + @echo "PATH (Shell)=$$PATH" + @$(MAKE) --version + $(info PATH (GNU Make)="$(PATH)") + $(info SHELL="$(SHELL)") + $(info PY="$(PY)") + $(info REQUIREMENTS_TXT="$(REQUIREMENTS_TXT)") + $(info SETUP_PY="$(SETUP_PY)") + $(info SETUP_CFG="$(SETUP_CFG)") + $(info VENVDIR="$(VENVDIR)") + $(info VENVDEPENDS="$(VENVDEPENDS)") + $(info WORKDIR="$(WORKDIR)") + + +# +# Dependencies +# + +ifneq ($(strip $(REQUIREMENTS_TXT)),) +VENVDEPENDS+=$(REQUIREMENTS_TXT) +endif + +ifneq ($(strip $(SETUP_PY)),) +VENVDEPENDS+=$(SETUP_PY) +endif +ifneq ($(strip $(SETUP_CFG)),) +VENVDEPENDS+=$(SETUP_CFG) +endif + +$(VENV): + $(PY) -m venv $(VENVDIR) + $(VENV)/python -m pip install --upgrade pip setuptools wheel + +$(VENV)/$(MARKER): $(VENVDEPENDS) | $(VENV) +ifneq ($(strip $(REQUIREMENTS_TXT)),) + $(VENV)/pip install $(foreach path,$(REQUIREMENTS_TXT),-r $(path)) +endif +ifneq ($(strip $(SETUP_PY)),) + $(VENV)/pip install $(foreach path,$(SETUP_PY),-e $(dir $(path))) +endif + $(call touch,$(VENV)/$(MARKER)) + + +# +# Interactive shells +# + +.PHONY: python +python: venv + exec $(VENV)/python + +.PHONY: ipython +ipython: $(VENV)/ipython + exec $(VENV)/ipython + +.PHONY: shell +shell: venv + . $(VENV)/activate && exec $(notdir $(SHELL)) + +.PHONY: bash zsh +bash zsh: venv + . $(VENV)/activate && exec $@ + + +# +# Commandline tools (wildcard rule, executable name must match package name) +# + +ifneq ($(EXE),) +$(VENV)/%: $(VENV)/%$(EXE) ; +.PHONY: $(VENV)/% +.PRECIOUS: $(VENV)/%$(EXE) +endif + +$(VENV)/%$(EXE): $(VENV)/$(MARKER) + $(VENV)/pip install --upgrade $* + $(call touch,$@) diff --git a/hw/vendor/pulp_platform_gpio/README.md b/hw/vendor/pulp_platform_gpio/README.md new file mode 100644 index 000000000..cfc2eab34 --- /dev/null +++ b/hw/vendor/pulp_platform_gpio/README.md @@ -0,0 +1,270 @@ +# GPIO Peripheral + +This repository provides an simple GPIO peripheral with integrated register file +to control 64 GPIOs (by default). The peripheral performs two stage +synchronization of the inputs to resolve potential metastability. The outputs +can be driven in push-pull or open-drain mode. Each GPIO supports any +combination of rising-edge, falling-edge, low-level and high-level interrupts +with individual status registers to query the type of pending interrupts. + +The interface to the peripheral is the lightweight [register_interface protocol](https://github.com/pulp-platform/register_interface ). +However, the repository contains convenience wrappers to attach AXI-lite or APB +buses for control. Each module in the repository contains an additional wrapper +at the bottom of the respective source files for the users that prefer +SystemVerilog interfaces over hierarchical structs. + +# Changing Number of GPIOs + Changing the number of GPIOs requires regeneration of the register file to + include the right number of config registers. The `gpio.sv` will automatically + adapt accordingly. + + The repo contains a Makefile that simplifies the process of invoking the reggen tool for this regeneration. + E.g. the following comand will reconfigure the project for 48 GPIOs. + + ``` + make reconfigure GPIOS=48 + ``` + +# Ports +| **Signal Name** | **Direction** | **Description** | +| --------------- | ------------- | --------------- | +| `clk_i` | *input* | Primary input clock. The control interface is suposed to be synchronous to this clock. | +| `rst_ni` | *input* | Asynchronous active-low reset | +| `gpio_in` | *input* | GPIO input signals from IO Pads (Pad -> SoC) signal. | +| `gpio_out` | *output* | GPIO output signals to IO Pads (SoC -> Pad) signal. | +| `gpio_tx_en_o` | *output* | GPIO TX Buffer enable signal. This signal is supposed to control the output buffer enable of the IO Pad. 0 -> TX disabled (High-Z or Pull-low/high), 1 -> TX. | +| `gpio_in_sync_o` | *input* | Synchronized GPIO input signals. This port provides the `gpio_in` signal synchronized to `clk_i`. | +| `interrupt_o` | *output* | Global interrupt line. The interrupt line is asserted for one `clk_i` whenever an unmasked interrupt on one of the GPIOs arrives. | +| `reg_req_i` | *input* | Control interface request side using register interface protocol. | +| `reg_rsp_o` | *output* | Control interface request side using register_interface protocol. | + +# Clock Gates +The GPIO IP manually instantiates a clock gate for each input to reduce power +consumption when the corresponding GPIO is disabled. However, some target +technologies (e.g. FPGA) don't behave that well when the clock path contains to +many clock gating resources. Therefore, the IP is available in two flavors, one +with the manual clock gates and one without them. You can (*and have to*) select +between the two by either supplying the /Bender Target/ `-t gpio_with_clk_gates` +or `-t gpio_no_clk_gates`. + +# Register Map +The registers of this module are all defined in the `gpio_regs.hjson` file which +is used to auto-generate the actual SV register file using [lowRISCs reggen tool](https://docs.opentitan.org/doc/rm/register_tool/ ). + +Here is a summary of the registers: +## `INFO` Register (offset 0x00, read-only) + Contains read-only registers with the number of GPIOs this instance of the + GPIO peripheral was parametrized for and an IP version number. + + | 31 - 20 | 19 - 10 | 9 - 0 | + |------------|------------|-----------------| + | *reserved* | IP_VERSION | Number of GPIOs | + + +## `CFG` Register (offset 0x04, rw) + Controls the interrupt mode of the gpios. If 1, keep the interrupt line + asserted until all interrupts for all GPIOs are cleared. If 0, generate one + cycle wide pulses for every new interrupt. + + | 31 - 1 | 0 | + |------------|------------------| + | *reserved* | `interrupt_mode` | + +## `GPIO_MODE<0-XX>` Registers (offset 0x08+*4, rw) + The GPIO_MODE registers control the operating mode of the individual GPIOs. + Each register controls 16 GPIOs. + + | 31 - 30 | ... | 3 - 2 | 1 - 0 | + |----------|-----|---------|---------| + | `GPIO15` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + + The values for `GPIO0_MODE` are: + + | Value | Description | + |-------|-------------------------------------------------------------------------------| + | 0 | Configures GPIO as an input. | + | 1 | Configures GPIO as a push-pull output. | + | 2 | Configures the GPIO to be in open_drain0 (0 -> High-Z, 1 -> Drive High) mode. | + | 3 | Configures the GPIO to be in open_drain1 (0 -> Drive Low, 1 -> High-Z) mode. | + +## `GPIO_EN<0-XX>` Registers (offset 0x80+*4, rw) + Each bit of these registers control the sampling of one GPIO. This register + enables sampling of the inputs. If disables (0) the corresponding GPIO will + not sample the inputs (saves power) and will not generate any interrupts. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `GPIO_IN<0-XX>` Registers (offset 0x100+*4, read-only) + The bits of these registers contain the input values of the corresponding + gpios. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `GPIO_OUT<0-XX>` Registers (offset 0x180+*4, rw) + Change the value of the corresponding GPIO. In `GPIO_MODE 1` writing 1 drives + high, writing 0 drives low. In `GPIO_MODE 2` (drive 1) writing a 1 will drive + the gpio to high while writing a 0 will put the gpio in high-z. In `GPIO_MODE + 3` writing 0 drives low and writing 1 puts the gpio into high-z. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `GPIO_SET<0-XX>` Registers (offset 0x200+*4, rw) + For each asserted bit in the register, set the corresponding bit in the + GPIO_OUT register (masked set). This simplifys setting a single gpio without + altering the state of the other ones. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `GPIO_CLEAR<0-XX>` Registers (offset 0x280+*4, rw) + For each asserted bit in the register, clear the corresponding bit in the + GPIO_OUT register (masked clear). This simplifys clearing a single gpio without + altering the state of the other ones. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `GPIO_TOGGLE<0-XX>` Registers (offset 0x300+*4, rw) + For each asserted bit in the register, toggle the corresponding bit in the + GPIO_OUT register (masked toggle). This simplifys toggling a single gpio without + altering the state of the other ones. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `INTRPT_RISE_EN<0-xx>` Registers (offset 0x380+*4, rw) + Enable interrupts on rising edges for the corresponding GPIO. + + The corresponding gpio needs to be enabled `GPIO_EN`. Once an interrupt + condition is detected, the global interrupt line `interrupt_o` is asserted + (according to the interrupt mode in `CFG`) and the corresponding bit in the + interrupt status registers is set. To clear the interrupt, write a `1` to the + corresponding bit in the status register. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `INTRPT_FALL_EN<0-xx>` Registers (offset 0x400+*4, rw) + Enable interrupts on falling edges for the corresponding GPIO. + + The corresponding gpio needs to be enabled `GPIO_EN`. Once an interrupt + condition is detected, the global interrupt line `interrupt_o` is asserted + (according to the interrupt mode in `CFG`) and the corresponding bit in the + interrupt status registers is set. To clear the interrupt, write a `1` to the + corresponding bit in the status register. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `INTRPT_LVL_HIGH_EN<0-xx>` Registers (offset 0x480+*4, rw) + Enable logic-high level-sensitive interrupts for the corresponding GPIO + (interrupt keeps getting triggered while GPIO is high). + + The corresponding gpio needs to be enabled `GPIO_EN`. Once an interrupt + condition is detected, the global interrupt line `interrupt_o` is asserted + (according to the interrupt mode in `CFG`) and the corresponding bit in the + interrupt status registers is set. To clear the interrupt, write a `1` to the + corresponding bit in the status register. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `INTRPT_LVL_LOW_EN<0-xx>` Registers (offset 0x500+*4, rw) + Enable logic-low level-sensitive interrupts for the corresponding GPIO + (interrupt keeps getting triggered while GPIO is low). + + The corresponding gpio needs to be enabled `GPIO_EN`. Once an interrupt + condition is detected, the global interrupt line `interrupt_o` is asserted + (according to the interrupt mode in `CFG`) and the corresponding bit in the + interrupt status registers is set. To clear the interrupt, write a `1` to the + corresponding bit in the status register. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `INTRPT_STATUS<0-xx>` Registers (offset 0x580+*4, rw) + Each bit indicates if there are any pending interrupts on the corresponding + GPIO. Writing a 1 to a specific bit clears **all** pending interrupts (rise, + fall, low, high) for the corresponding GPIO. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `INTRPT_RISE_STATUS<0-xx>` Registers (offset 0x600+*4, rw) + Each bit indicates if there is a pending rising-edge interrupt on the corresponding + GPIO. Writing a 1 to a specific bit clears the interrupt for the corresponding GPIO. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `INTRPT_FALL_STATUS<0-xx>` Registers (offset 0x680+*4, rw) + Each bit indicates if there is a pending falling-edge interrupt on the corresponding + GPIO. Writing a 1 to a specific bit clears the interrupt for the corresponding GPIO. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `INTRPT_LVL_LOW_STATUS<0-xx>` Registers (offset 0x700+*4, rw) + Each bit indicates if there is a pending low-level sensitive interrupt on the corresponding + GPIO. Writing a 1 to a specific bit clears the interrupt for the corresponding GPIO. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + +## `INTRPT_LVL_HIGH_STATUS<0-xx>` Registers (offset 0x780+*4, rw) + Each bit indicates if there is a pending low-level sensitive interrupt on the corresponding + GPIO. Writing a 1 to a specific bit clears the interrupt for the corresponding GPIO. + + | 31 | ... | 1 | 0 | + |----------|-----|---------|---------| + | `GPIO31` | ... | `GPIO1` | `GPIO0` | + + *Continues in next register* + diff --git a/hw/vendor/pulp_platform_gpio/bender b/hw/vendor/pulp_platform_gpio/bender new file mode 100755 index 000000000..328536cec Binary files /dev/null and b/hw/vendor/pulp_platform_gpio/bender differ diff --git a/hw/vendor/pulp_platform_gpio/gpio_regs.hjson b/hw/vendor/pulp_platform_gpio/gpio_regs.hjson new file mode 100644 index 000000000..6f9bd89ea --- /dev/null +++ b/hw/vendor/pulp_platform_gpio/gpio_regs.hjson @@ -0,0 +1,350 @@ +{ + name: "gpio" + clock_primary: "clk_i" + reset_primary: "rst_ni" + param_list: [ + { + name: GPIOCount + default: "32" + } + ] + bus_interfaces: [ + { protocol: "reg_iface", direction: "device"} + ] + regwidth: 32, + registers: [ + { + name: "INFO" + desc: "Info register that contains information about this peripheral." + swaccess: "ro", + hwaccess: "hwo", + hwext: true + fields: [ + { + name: "GPIO_CNT" + bits: "9:0" + desc: "Contains the number of GPIOs controlled by this peripheral." + } + { + name: "VERSION" + bits: "19:10" + desc: "The version number of the IPs." + resval: 2 + } + ] + } + { + name: "CFG" + desc: "Global configuration register for the peripheral" + swaccess: "rw" + hwaccess: "hro" + fields: [ + { + name: "INTRPT_MODE" + bits: "0" + desc: ''' + If 1, keep the interrupt line asserted until all + interrupts are cleared. If 0, generate one cycle wide pulse for every interrupt. + ''' + resval: 0 + } + { + name: "reserved" + bits: "1" + desc: " Reserved for future use" + + } + ] + } + { multireg: + { name: "GPIO_MODE", + cname: "GPIO_MODE", + count: "GPIOCount", + desc: "Set the IO Mode of the GPIO." + swaccess: "rw", + hwaccess: "hro", + compact: true + fields: [ + { + bits: "1:0" + name: "MODE", + desc: "Change the IO mode of the GPIO." + resval: "0" + enum: [ + { value: 0, name: "INPUT_ONLY", desc: "The correspondin GPIO acts as an input only." } + { value: 1, name: "OUTPUT_ACTIVE", desc: "Actively drive output to 0 or 1" } + { value: 2, name: "OPEN_DRAIN0", desc: "Value 1 drives, value 0 enables tristate. "} + { value: 3, name: "OPEN_DRAIN1", desc: "Value 0 drives, value 1 enables tristate. "} + ] + } + ] + } + } + {skipto: "0x080"} + { multireg: + { name: "GPIO_EN", + cname: "GPIO_EN", + count: "GPIOCount", + compact: true, + desc: "Enable sampling on the corresponding GPIO", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x100"} + { multireg: + { name: "GPIO_IN", + cname: "GPIO_IN", + count: "GPIOCount", + compact: true, + desc: "Read the current input values of all GPIOs." + swaccess: "ro", + hwaccess: "hwo", + hwext: true + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x180"} + { multireg: + { name: "GPIO_OUT", + cname: "GPIO_OUT", + count: "GPIOCount", + compact: true, + desc: "Set the output value of the corresponding GPIOs." + swaccess: "rw", + hwaccess: "hrw", + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x200"} + { multireg: + { name: "GPIO_SET", + cname: "GPIO_SET", + count: "GPIOCount", + compact: true, + desc: "For each asserted bit in this register, set the corresponding bit in the padout register." + swaccess: "wo", + hwaccess: "hro", + hwqe: true, + hwext: true, + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x280"} + { multireg: + { name: "GPIO_CLEAR", + cname: "GPIO_CLEAR", + count: "GPIOCount", + compact: true, + desc: "For each asserted bit in this register, clear the corresponding bit in the padout register." + swaccess: "wo", + hwaccess: "hro", + hwqe: true, + hwext: true, + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x300"} + { multireg: + { name: "GPIO_TOGGLE", + cname: "GPIO_TOGGLE", + count: "GPIOCount", + compact: true + desc: "For each asserted bit in this register, toggle the corresponding bit in the padout register." + swaccess: "wo", + hwaccess: "hro", + hwqe: true, + hwext: true, + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x380"} + { multireg: + { name: "INTRPT_RISE_EN", + cname: "INTRPT_RISE_EN", + count: "GPIOCount", + compact: true + desc: "Enable Interrupts on rising edges for the corresponding GPIO" + swaccess: "rw", + hwaccess: "hro", + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x400"} + { multireg: + { name: "INTRPT_FALL_EN", + cname: "INTRPT_FALL_EN", + count: "GPIOCount", + compact: true + desc: "Enable Interrupts on falling edges for the corresponding GPIO" + swaccess: "rw", + hwaccess: "hro", + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x480"} + { multireg: + { name: "INTRPT_LVL_HIGH_EN", + cname: "INTRPT_LVL_HIGH_EN", + count: "GPIOCount", + compact: true + desc: "Enable logic high level-sensitive Interrupts on the corresponding GPIO" + swaccess: "rw", + hwaccess: "hro", + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x500"} + { multireg: + { name: "INTRPT_LVL_LOW_EN", + cname: "INTRPT_LVL_LOW_EN", + count: "GPIOCount", + compact: true + desc: "Enable logic low level-sensitive Interrupts on the corresponding GPIO" + swaccess: "rw", + hwaccess: "hro", + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x580"} + { multireg: + { name: "INTRPT_STATUS", + cname: "INTRPT_STATUS", + count: "GPIOCount", + compact: true + desc: ''' + Asserted if there is any pending interrupts on corresponding GPIOs. + Writing 1 to a specific bit clears all pending interrupts (rise, fall, low, high) of the corresponding GPIO. + ''' + swaccess: "rw1c", + hwaccess: "hrw", + hwqe: true, + hwext: true, + fields: [ + { + bits: "0" + } + ] + } + } + {skipto: "0x600"} + { multireg: + { name: "INTRPT_RISE_STATUS", + cname: "INTRPT_RISE_STATUS", + count: "GPIOCount", + compact: true + desc: ''' + Asserted if there is a pending rise interrupts on corresponding GPIOs. + Writing 1 to a specific bit clears the pending interrupt of the corresponding GPIO. + ''' + fields: [ + { + bits: "0" + swaccess: "rw1c", + hwaccess: "hrw", + } + ] + } + } + {skipto: "0x680"} + { multireg: + { name: "INTRPT_FALL_STATUS", + cname: "INTRPT_FALL_STATUS", + count: "GPIOCount", + compact: true + desc: ''' + Asserted if there is any pending fall interrupts on corresponding GPIOs. + Writing 1 to a specific bit clears the pending interrupt of the corresponding GPIO. + ''' + fields: [ + { + bits: "0" + swaccess: "rw1c", + hwaccess: "hrw", + } + ] + } + } + {skipto: "0x700"} + { multireg: + { name: "INTRPT_LVL_HIGH_STATUS", + cname: "INTRPT_LVL_HIGH_STATUS", + count: "GPIOCount", + compact: true + desc: ''' + Asserted if there is any pending high-level interrupts on corresponding GPIOs. + Writing 1 to a specific bit clears the pending interrupt of the corresponding GPIO. + ''' + swaccess: "rw1c", + hwaccess: "hrw", + fields: [ + { + bits: "0" + swaccess: "rw1c", + hwaccess: "hrw", + } + ] + } + } + {skipto: "0x780"} + { multireg: + { name: "INTRPT_LVL_LOW_STATUS", + cname: "INTRPT_LVL_LOW_STATUS", + count: "GPIOCount", + compact: true + desc: ''' + Asserted if there is any pending low-level interrupts on corresponding GPIOs. + Writing 1 to a specific bit clears the pending interrupt of the corresponding GPIO. + ''' + fields: [ + { + bits: "0" + swaccess: "rw1c", + hwaccess: "hrw", + } + ] + } + } + ] +} diff --git a/hw/vendor/pulp_platform_gpio/hal/gpio_hal.h b/hw/vendor/pulp_platform_gpio/hal/gpio_hal.h new file mode 100644 index 000000000..91e3c55fc --- /dev/null +++ b/hw/vendor/pulp_platform_gpio/hal/gpio_hal.h @@ -0,0 +1,851 @@ +// Generated register defines for gpio + +#ifndef _GPIO_REG_DEFS_ +#define _GPIO_REG_DEFS_ + +#ifdef __cplusplus +extern "C" { +#endif +#define GPIO_PARAM_G_P_I_O_COUNT 32 + +// Register width +#define GPIO_PARAM_REG_WIDTH 32 + +// Info register that contains information about this peripheral. +#define GPIO_INFO_REG_OFFSET 0x0 +#define GPIO_INFO_GPIO_CNT_MASK 0x3ff +#define GPIO_INFO_GPIO_CNT_OFFSET 0 +#define GPIO_INFO_GPIO_CNT_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_INFO_GPIO_CNT_MASK, .index = GPIO_INFO_GPIO_CNT_OFFSET }) +#define GPIO_INFO_VERSION_MASK 0x3ff +#define GPIO_INFO_VERSION_OFFSET 10 +#define GPIO_INFO_VERSION_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_INFO_VERSION_MASK, .index = GPIO_INFO_VERSION_OFFSET }) + +// Global configuration register for the peripheral +#define GPIO_CFG_REG_OFFSET 0x4 +#define GPIO_CFG_INTRPT_MODE_BIT 0 +#define GPIO_CFG_RESERVED_BIT 1 + +// Set the IO Mode of the GPIO. (common parameters) +#define GPIO_GPIO_MODE_MODE_FIELD_WIDTH 2 +#define GPIO_GPIO_MODE_MODE_FIELDS_PER_REG 16 +#define GPIO_GPIO_MODE_MULTIREG_COUNT 2 + +// Set the IO Mode of the GPIO. +#define GPIO_GPIO_MODE_0_REG_OFFSET 0x8 +#define GPIO_GPIO_MODE_0_MODE_0_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_0_OFFSET 0 +#define GPIO_GPIO_MODE_0_MODE_0_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_0_MASK, .index = GPIO_GPIO_MODE_0_MODE_0_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_0_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_0_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_0_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_0_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_1_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_1_OFFSET 2 +#define GPIO_GPIO_MODE_0_MODE_1_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_1_MASK, .index = GPIO_GPIO_MODE_0_MODE_1_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_1_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_1_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_1_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_1_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_2_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_2_OFFSET 4 +#define GPIO_GPIO_MODE_0_MODE_2_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_2_MASK, .index = GPIO_GPIO_MODE_0_MODE_2_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_2_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_2_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_2_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_2_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_3_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_3_OFFSET 6 +#define GPIO_GPIO_MODE_0_MODE_3_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_3_MASK, .index = GPIO_GPIO_MODE_0_MODE_3_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_3_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_3_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_3_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_3_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_4_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_4_OFFSET 8 +#define GPIO_GPIO_MODE_0_MODE_4_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_4_MASK, .index = GPIO_GPIO_MODE_0_MODE_4_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_4_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_4_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_4_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_4_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_5_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_5_OFFSET 10 +#define GPIO_GPIO_MODE_0_MODE_5_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_5_MASK, .index = GPIO_GPIO_MODE_0_MODE_5_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_5_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_5_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_5_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_5_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_6_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_6_OFFSET 12 +#define GPIO_GPIO_MODE_0_MODE_6_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_6_MASK, .index = GPIO_GPIO_MODE_0_MODE_6_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_6_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_6_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_6_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_6_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_7_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_7_OFFSET 14 +#define GPIO_GPIO_MODE_0_MODE_7_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_7_MASK, .index = GPIO_GPIO_MODE_0_MODE_7_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_7_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_7_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_7_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_7_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_8_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_8_OFFSET 16 +#define GPIO_GPIO_MODE_0_MODE_8_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_8_MASK, .index = GPIO_GPIO_MODE_0_MODE_8_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_8_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_8_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_8_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_8_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_9_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_9_OFFSET 18 +#define GPIO_GPIO_MODE_0_MODE_9_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_9_MASK, .index = GPIO_GPIO_MODE_0_MODE_9_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_9_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_9_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_9_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_9_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_10_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_10_OFFSET 20 +#define GPIO_GPIO_MODE_0_MODE_10_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_10_MASK, .index = GPIO_GPIO_MODE_0_MODE_10_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_10_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_10_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_10_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_10_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_11_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_11_OFFSET 22 +#define GPIO_GPIO_MODE_0_MODE_11_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_11_MASK, .index = GPIO_GPIO_MODE_0_MODE_11_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_11_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_11_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_11_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_11_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_12_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_12_OFFSET 24 +#define GPIO_GPIO_MODE_0_MODE_12_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_12_MASK, .index = GPIO_GPIO_MODE_0_MODE_12_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_12_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_12_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_12_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_12_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_13_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_13_OFFSET 26 +#define GPIO_GPIO_MODE_0_MODE_13_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_13_MASK, .index = GPIO_GPIO_MODE_0_MODE_13_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_13_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_13_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_13_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_13_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_14_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_14_OFFSET 28 +#define GPIO_GPIO_MODE_0_MODE_14_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_14_MASK, .index = GPIO_GPIO_MODE_0_MODE_14_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_14_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_14_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_14_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_14_VALUE_OPEN_DRAIN1 0x3 +#define GPIO_GPIO_MODE_0_MODE_15_MASK 0x3 +#define GPIO_GPIO_MODE_0_MODE_15_OFFSET 30 +#define GPIO_GPIO_MODE_0_MODE_15_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_0_MODE_15_MASK, .index = GPIO_GPIO_MODE_0_MODE_15_OFFSET }) +#define GPIO_GPIO_MODE_0_MODE_15_VALUE_INPUT_ONLY 0x0 +#define GPIO_GPIO_MODE_0_MODE_15_VALUE_OUTPUT_ACTIVE 0x1 +#define GPIO_GPIO_MODE_0_MODE_15_VALUE_OPEN_DRAIN0 0x2 +#define GPIO_GPIO_MODE_0_MODE_15_VALUE_OPEN_DRAIN1 0x3 + +// Set the IO Mode of the GPIO. +#define GPIO_GPIO_MODE_1_REG_OFFSET 0xc +#define GPIO_GPIO_MODE_1_MODE_16_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_16_OFFSET 0 +#define GPIO_GPIO_MODE_1_MODE_16_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_16_MASK, .index = GPIO_GPIO_MODE_1_MODE_16_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_17_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_17_OFFSET 2 +#define GPIO_GPIO_MODE_1_MODE_17_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_17_MASK, .index = GPIO_GPIO_MODE_1_MODE_17_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_18_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_18_OFFSET 4 +#define GPIO_GPIO_MODE_1_MODE_18_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_18_MASK, .index = GPIO_GPIO_MODE_1_MODE_18_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_19_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_19_OFFSET 6 +#define GPIO_GPIO_MODE_1_MODE_19_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_19_MASK, .index = GPIO_GPIO_MODE_1_MODE_19_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_20_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_20_OFFSET 8 +#define GPIO_GPIO_MODE_1_MODE_20_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_20_MASK, .index = GPIO_GPIO_MODE_1_MODE_20_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_21_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_21_OFFSET 10 +#define GPIO_GPIO_MODE_1_MODE_21_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_21_MASK, .index = GPIO_GPIO_MODE_1_MODE_21_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_22_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_22_OFFSET 12 +#define GPIO_GPIO_MODE_1_MODE_22_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_22_MASK, .index = GPIO_GPIO_MODE_1_MODE_22_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_23_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_23_OFFSET 14 +#define GPIO_GPIO_MODE_1_MODE_23_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_23_MASK, .index = GPIO_GPIO_MODE_1_MODE_23_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_24_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_24_OFFSET 16 +#define GPIO_GPIO_MODE_1_MODE_24_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_24_MASK, .index = GPIO_GPIO_MODE_1_MODE_24_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_25_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_25_OFFSET 18 +#define GPIO_GPIO_MODE_1_MODE_25_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_25_MASK, .index = GPIO_GPIO_MODE_1_MODE_25_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_26_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_26_OFFSET 20 +#define GPIO_GPIO_MODE_1_MODE_26_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_26_MASK, .index = GPIO_GPIO_MODE_1_MODE_26_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_27_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_27_OFFSET 22 +#define GPIO_GPIO_MODE_1_MODE_27_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_27_MASK, .index = GPIO_GPIO_MODE_1_MODE_27_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_28_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_28_OFFSET 24 +#define GPIO_GPIO_MODE_1_MODE_28_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_28_MASK, .index = GPIO_GPIO_MODE_1_MODE_28_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_29_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_29_OFFSET 26 +#define GPIO_GPIO_MODE_1_MODE_29_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_29_MASK, .index = GPIO_GPIO_MODE_1_MODE_29_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_30_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_30_OFFSET 28 +#define GPIO_GPIO_MODE_1_MODE_30_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_30_MASK, .index = GPIO_GPIO_MODE_1_MODE_30_OFFSET }) +#define GPIO_GPIO_MODE_1_MODE_31_MASK 0x3 +#define GPIO_GPIO_MODE_1_MODE_31_OFFSET 30 +#define GPIO_GPIO_MODE_1_MODE_31_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_GPIO_MODE_1_MODE_31_MASK, .index = GPIO_GPIO_MODE_1_MODE_31_OFFSET }) + +// Enable sampling on the corresponding GPIO (common parameters) +#define GPIO_GPIO_EN_GPIO_EN_FIELD_WIDTH 1 +#define GPIO_GPIO_EN_GPIO_EN_FIELDS_PER_REG 32 +#define GPIO_GPIO_EN_MULTIREG_COUNT 1 + +// Enable sampling on the corresponding GPIO +#define GPIO_GPIO_EN_REG_OFFSET 0x80 +#define GPIO_GPIO_EN_GPIO_EN_0_BIT 0 +#define GPIO_GPIO_EN_GPIO_EN_1_BIT 1 +#define GPIO_GPIO_EN_GPIO_EN_2_BIT 2 +#define GPIO_GPIO_EN_GPIO_EN_3_BIT 3 +#define GPIO_GPIO_EN_GPIO_EN_4_BIT 4 +#define GPIO_GPIO_EN_GPIO_EN_5_BIT 5 +#define GPIO_GPIO_EN_GPIO_EN_6_BIT 6 +#define GPIO_GPIO_EN_GPIO_EN_7_BIT 7 +#define GPIO_GPIO_EN_GPIO_EN_8_BIT 8 +#define GPIO_GPIO_EN_GPIO_EN_9_BIT 9 +#define GPIO_GPIO_EN_GPIO_EN_10_BIT 10 +#define GPIO_GPIO_EN_GPIO_EN_11_BIT 11 +#define GPIO_GPIO_EN_GPIO_EN_12_BIT 12 +#define GPIO_GPIO_EN_GPIO_EN_13_BIT 13 +#define GPIO_GPIO_EN_GPIO_EN_14_BIT 14 +#define GPIO_GPIO_EN_GPIO_EN_15_BIT 15 +#define GPIO_GPIO_EN_GPIO_EN_16_BIT 16 +#define GPIO_GPIO_EN_GPIO_EN_17_BIT 17 +#define GPIO_GPIO_EN_GPIO_EN_18_BIT 18 +#define GPIO_GPIO_EN_GPIO_EN_19_BIT 19 +#define GPIO_GPIO_EN_GPIO_EN_20_BIT 20 +#define GPIO_GPIO_EN_GPIO_EN_21_BIT 21 +#define GPIO_GPIO_EN_GPIO_EN_22_BIT 22 +#define GPIO_GPIO_EN_GPIO_EN_23_BIT 23 +#define GPIO_GPIO_EN_GPIO_EN_24_BIT 24 +#define GPIO_GPIO_EN_GPIO_EN_25_BIT 25 +#define GPIO_GPIO_EN_GPIO_EN_26_BIT 26 +#define GPIO_GPIO_EN_GPIO_EN_27_BIT 27 +#define GPIO_GPIO_EN_GPIO_EN_28_BIT 28 +#define GPIO_GPIO_EN_GPIO_EN_29_BIT 29 +#define GPIO_GPIO_EN_GPIO_EN_30_BIT 30 +#define GPIO_GPIO_EN_GPIO_EN_31_BIT 31 + +// Read the current input values of all GPIOs. (common parameters) +#define GPIO_GPIO_IN_GPIO_IN_FIELD_WIDTH 1 +#define GPIO_GPIO_IN_GPIO_IN_FIELDS_PER_REG 32 +#define GPIO_GPIO_IN_MULTIREG_COUNT 1 + +// Read the current input values of all GPIOs. +#define GPIO_GPIO_IN_REG_OFFSET 0x100 +#define GPIO_GPIO_IN_GPIO_IN_0_BIT 0 +#define GPIO_GPIO_IN_GPIO_IN_1_BIT 1 +#define GPIO_GPIO_IN_GPIO_IN_2_BIT 2 +#define GPIO_GPIO_IN_GPIO_IN_3_BIT 3 +#define GPIO_GPIO_IN_GPIO_IN_4_BIT 4 +#define GPIO_GPIO_IN_GPIO_IN_5_BIT 5 +#define GPIO_GPIO_IN_GPIO_IN_6_BIT 6 +#define GPIO_GPIO_IN_GPIO_IN_7_BIT 7 +#define GPIO_GPIO_IN_GPIO_IN_8_BIT 8 +#define GPIO_GPIO_IN_GPIO_IN_9_BIT 9 +#define GPIO_GPIO_IN_GPIO_IN_10_BIT 10 +#define GPIO_GPIO_IN_GPIO_IN_11_BIT 11 +#define GPIO_GPIO_IN_GPIO_IN_12_BIT 12 +#define GPIO_GPIO_IN_GPIO_IN_13_BIT 13 +#define GPIO_GPIO_IN_GPIO_IN_14_BIT 14 +#define GPIO_GPIO_IN_GPIO_IN_15_BIT 15 +#define GPIO_GPIO_IN_GPIO_IN_16_BIT 16 +#define GPIO_GPIO_IN_GPIO_IN_17_BIT 17 +#define GPIO_GPIO_IN_GPIO_IN_18_BIT 18 +#define GPIO_GPIO_IN_GPIO_IN_19_BIT 19 +#define GPIO_GPIO_IN_GPIO_IN_20_BIT 20 +#define GPIO_GPIO_IN_GPIO_IN_21_BIT 21 +#define GPIO_GPIO_IN_GPIO_IN_22_BIT 22 +#define GPIO_GPIO_IN_GPIO_IN_23_BIT 23 +#define GPIO_GPIO_IN_GPIO_IN_24_BIT 24 +#define GPIO_GPIO_IN_GPIO_IN_25_BIT 25 +#define GPIO_GPIO_IN_GPIO_IN_26_BIT 26 +#define GPIO_GPIO_IN_GPIO_IN_27_BIT 27 +#define GPIO_GPIO_IN_GPIO_IN_28_BIT 28 +#define GPIO_GPIO_IN_GPIO_IN_29_BIT 29 +#define GPIO_GPIO_IN_GPIO_IN_30_BIT 30 +#define GPIO_GPIO_IN_GPIO_IN_31_BIT 31 + +// Set the output value of the corresponding GPIOs. (common parameters) +#define GPIO_GPIO_OUT_GPIO_OUT_FIELD_WIDTH 1 +#define GPIO_GPIO_OUT_GPIO_OUT_FIELDS_PER_REG 32 +#define GPIO_GPIO_OUT_MULTIREG_COUNT 1 + +// Set the output value of the corresponding GPIOs. +#define GPIO_GPIO_OUT_REG_OFFSET 0x180 +#define GPIO_GPIO_OUT_GPIO_OUT_0_BIT 0 +#define GPIO_GPIO_OUT_GPIO_OUT_1_BIT 1 +#define GPIO_GPIO_OUT_GPIO_OUT_2_BIT 2 +#define GPIO_GPIO_OUT_GPIO_OUT_3_BIT 3 +#define GPIO_GPIO_OUT_GPIO_OUT_4_BIT 4 +#define GPIO_GPIO_OUT_GPIO_OUT_5_BIT 5 +#define GPIO_GPIO_OUT_GPIO_OUT_6_BIT 6 +#define GPIO_GPIO_OUT_GPIO_OUT_7_BIT 7 +#define GPIO_GPIO_OUT_GPIO_OUT_8_BIT 8 +#define GPIO_GPIO_OUT_GPIO_OUT_9_BIT 9 +#define GPIO_GPIO_OUT_GPIO_OUT_10_BIT 10 +#define GPIO_GPIO_OUT_GPIO_OUT_11_BIT 11 +#define GPIO_GPIO_OUT_GPIO_OUT_12_BIT 12 +#define GPIO_GPIO_OUT_GPIO_OUT_13_BIT 13 +#define GPIO_GPIO_OUT_GPIO_OUT_14_BIT 14 +#define GPIO_GPIO_OUT_GPIO_OUT_15_BIT 15 +#define GPIO_GPIO_OUT_GPIO_OUT_16_BIT 16 +#define GPIO_GPIO_OUT_GPIO_OUT_17_BIT 17 +#define GPIO_GPIO_OUT_GPIO_OUT_18_BIT 18 +#define GPIO_GPIO_OUT_GPIO_OUT_19_BIT 19 +#define GPIO_GPIO_OUT_GPIO_OUT_20_BIT 20 +#define GPIO_GPIO_OUT_GPIO_OUT_21_BIT 21 +#define GPIO_GPIO_OUT_GPIO_OUT_22_BIT 22 +#define GPIO_GPIO_OUT_GPIO_OUT_23_BIT 23 +#define GPIO_GPIO_OUT_GPIO_OUT_24_BIT 24 +#define GPIO_GPIO_OUT_GPIO_OUT_25_BIT 25 +#define GPIO_GPIO_OUT_GPIO_OUT_26_BIT 26 +#define GPIO_GPIO_OUT_GPIO_OUT_27_BIT 27 +#define GPIO_GPIO_OUT_GPIO_OUT_28_BIT 28 +#define GPIO_GPIO_OUT_GPIO_OUT_29_BIT 29 +#define GPIO_GPIO_OUT_GPIO_OUT_30_BIT 30 +#define GPIO_GPIO_OUT_GPIO_OUT_31_BIT 31 + +// For each asserted bit in this register, set the corresponding bit in the +// padout register. (common parameters) +#define GPIO_GPIO_SET_GPIO_SET_FIELD_WIDTH 1 +#define GPIO_GPIO_SET_GPIO_SET_FIELDS_PER_REG 32 +#define GPIO_GPIO_SET_MULTIREG_COUNT 1 + +// For each asserted bit in this register, set the corresponding bit in the +// padout register. +#define GPIO_GPIO_SET_REG_OFFSET 0x200 +#define GPIO_GPIO_SET_GPIO_SET_0_BIT 0 +#define GPIO_GPIO_SET_GPIO_SET_1_BIT 1 +#define GPIO_GPIO_SET_GPIO_SET_2_BIT 2 +#define GPIO_GPIO_SET_GPIO_SET_3_BIT 3 +#define GPIO_GPIO_SET_GPIO_SET_4_BIT 4 +#define GPIO_GPIO_SET_GPIO_SET_5_BIT 5 +#define GPIO_GPIO_SET_GPIO_SET_6_BIT 6 +#define GPIO_GPIO_SET_GPIO_SET_7_BIT 7 +#define GPIO_GPIO_SET_GPIO_SET_8_BIT 8 +#define GPIO_GPIO_SET_GPIO_SET_9_BIT 9 +#define GPIO_GPIO_SET_GPIO_SET_10_BIT 10 +#define GPIO_GPIO_SET_GPIO_SET_11_BIT 11 +#define GPIO_GPIO_SET_GPIO_SET_12_BIT 12 +#define GPIO_GPIO_SET_GPIO_SET_13_BIT 13 +#define GPIO_GPIO_SET_GPIO_SET_14_BIT 14 +#define GPIO_GPIO_SET_GPIO_SET_15_BIT 15 +#define GPIO_GPIO_SET_GPIO_SET_16_BIT 16 +#define GPIO_GPIO_SET_GPIO_SET_17_BIT 17 +#define GPIO_GPIO_SET_GPIO_SET_18_BIT 18 +#define GPIO_GPIO_SET_GPIO_SET_19_BIT 19 +#define GPIO_GPIO_SET_GPIO_SET_20_BIT 20 +#define GPIO_GPIO_SET_GPIO_SET_21_BIT 21 +#define GPIO_GPIO_SET_GPIO_SET_22_BIT 22 +#define GPIO_GPIO_SET_GPIO_SET_23_BIT 23 +#define GPIO_GPIO_SET_GPIO_SET_24_BIT 24 +#define GPIO_GPIO_SET_GPIO_SET_25_BIT 25 +#define GPIO_GPIO_SET_GPIO_SET_26_BIT 26 +#define GPIO_GPIO_SET_GPIO_SET_27_BIT 27 +#define GPIO_GPIO_SET_GPIO_SET_28_BIT 28 +#define GPIO_GPIO_SET_GPIO_SET_29_BIT 29 +#define GPIO_GPIO_SET_GPIO_SET_30_BIT 30 +#define GPIO_GPIO_SET_GPIO_SET_31_BIT 31 + +// For each asserted bit in this register, clear the corresponding bit in the +// padout register. (common parameters) +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_FIELD_WIDTH 1 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_FIELDS_PER_REG 32 +#define GPIO_GPIO_CLEAR_MULTIREG_COUNT 1 + +// For each asserted bit in this register, clear the corresponding bit in the +// padout register. +#define GPIO_GPIO_CLEAR_REG_OFFSET 0x280 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_0_BIT 0 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_1_BIT 1 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_2_BIT 2 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_3_BIT 3 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_4_BIT 4 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_5_BIT 5 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_6_BIT 6 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_7_BIT 7 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_8_BIT 8 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_9_BIT 9 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_10_BIT 10 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_11_BIT 11 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_12_BIT 12 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_13_BIT 13 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_14_BIT 14 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_15_BIT 15 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_16_BIT 16 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_17_BIT 17 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_18_BIT 18 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_19_BIT 19 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_20_BIT 20 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_21_BIT 21 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_22_BIT 22 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_23_BIT 23 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_24_BIT 24 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_25_BIT 25 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_26_BIT 26 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_27_BIT 27 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_28_BIT 28 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_29_BIT 29 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_30_BIT 30 +#define GPIO_GPIO_CLEAR_GPIO_CLEAR_31_BIT 31 + +// For each asserted bit in this register, toggle the corresponding bit in +// the padout register. (common parameters) +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_FIELD_WIDTH 1 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_FIELDS_PER_REG 32 +#define GPIO_GPIO_TOGGLE_MULTIREG_COUNT 1 + +// For each asserted bit in this register, toggle the corresponding bit in +// the padout register. +#define GPIO_GPIO_TOGGLE_REG_OFFSET 0x300 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_0_BIT 0 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_1_BIT 1 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_2_BIT 2 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_3_BIT 3 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_4_BIT 4 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_5_BIT 5 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_6_BIT 6 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_7_BIT 7 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_8_BIT 8 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_9_BIT 9 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_10_BIT 10 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_11_BIT 11 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_12_BIT 12 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_13_BIT 13 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_14_BIT 14 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_15_BIT 15 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_16_BIT 16 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_17_BIT 17 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_18_BIT 18 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_19_BIT 19 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_20_BIT 20 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_21_BIT 21 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_22_BIT 22 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_23_BIT 23 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_24_BIT 24 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_25_BIT 25 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_26_BIT 26 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_27_BIT 27 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_28_BIT 28 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_29_BIT 29 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_30_BIT 30 +#define GPIO_GPIO_TOGGLE_GPIO_TOGGLE_31_BIT 31 + +// Enable Interrupts on rising edges for the corresponding GPIO (common +// parameters) +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_FIELD_WIDTH 1 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_FIELDS_PER_REG 32 +#define GPIO_INTRPT_RISE_EN_MULTIREG_COUNT 1 + +// Enable Interrupts on rising edges for the corresponding GPIO +#define GPIO_INTRPT_RISE_EN_REG_OFFSET 0x380 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_0_BIT 0 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_1_BIT 1 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_2_BIT 2 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_3_BIT 3 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_4_BIT 4 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_5_BIT 5 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_6_BIT 6 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_7_BIT 7 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_8_BIT 8 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_9_BIT 9 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_10_BIT 10 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_11_BIT 11 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_12_BIT 12 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_13_BIT 13 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_14_BIT 14 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_15_BIT 15 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_16_BIT 16 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_17_BIT 17 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_18_BIT 18 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_19_BIT 19 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_20_BIT 20 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_21_BIT 21 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_22_BIT 22 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_23_BIT 23 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_24_BIT 24 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_25_BIT 25 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_26_BIT 26 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_27_BIT 27 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_28_BIT 28 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_29_BIT 29 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_30_BIT 30 +#define GPIO_INTRPT_RISE_EN_INTRPT_RISE_EN_31_BIT 31 + +// Enable Interrupts on falling edges for the corresponding GPIO (common +// parameters) +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_FIELD_WIDTH 1 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_FIELDS_PER_REG 32 +#define GPIO_INTRPT_FALL_EN_MULTIREG_COUNT 1 + +// Enable Interrupts on falling edges for the corresponding GPIO +#define GPIO_INTRPT_FALL_EN_REG_OFFSET 0x400 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_0_BIT 0 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_1_BIT 1 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_2_BIT 2 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_3_BIT 3 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_4_BIT 4 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_5_BIT 5 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_6_BIT 6 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_7_BIT 7 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_8_BIT 8 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_9_BIT 9 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_10_BIT 10 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_11_BIT 11 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_12_BIT 12 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_13_BIT 13 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_14_BIT 14 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_15_BIT 15 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_16_BIT 16 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_17_BIT 17 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_18_BIT 18 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_19_BIT 19 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_20_BIT 20 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_21_BIT 21 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_22_BIT 22 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_23_BIT 23 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_24_BIT 24 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_25_BIT 25 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_26_BIT 26 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_27_BIT 27 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_28_BIT 28 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_29_BIT 29 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_30_BIT 30 +#define GPIO_INTRPT_FALL_EN_INTRPT_FALL_EN_31_BIT 31 + +// Enable logic high level-sensitive Interrupts on the corresponding GPIO +// (common parameters) +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_FIELD_WIDTH 1 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_FIELDS_PER_REG 32 +#define GPIO_INTRPT_LVL_HIGH_EN_MULTIREG_COUNT 1 + +// Enable logic high level-sensitive Interrupts on the corresponding GPIO +#define GPIO_INTRPT_LVL_HIGH_EN_REG_OFFSET 0x480 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_0_BIT 0 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_1_BIT 1 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_2_BIT 2 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_3_BIT 3 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_4_BIT 4 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_5_BIT 5 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_6_BIT 6 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_7_BIT 7 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_8_BIT 8 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_9_BIT 9 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_10_BIT 10 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_11_BIT 11 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_12_BIT 12 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_13_BIT 13 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_14_BIT 14 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_15_BIT 15 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_16_BIT 16 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_17_BIT 17 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_18_BIT 18 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_19_BIT 19 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_20_BIT 20 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_21_BIT 21 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_22_BIT 22 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_23_BIT 23 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_24_BIT 24 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_25_BIT 25 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_26_BIT 26 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_27_BIT 27 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_28_BIT 28 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_29_BIT 29 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_30_BIT 30 +#define GPIO_INTRPT_LVL_HIGH_EN_INTRPT_LVL_HIGH_EN_31_BIT 31 + +// Enable logic low level-sensitive Interrupts on the corresponding GPIO +// (common parameters) +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_FIELD_WIDTH 1 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_FIELDS_PER_REG 32 +#define GPIO_INTRPT_LVL_LOW_EN_MULTIREG_COUNT 1 + +// Enable logic low level-sensitive Interrupts on the corresponding GPIO +#define GPIO_INTRPT_LVL_LOW_EN_REG_OFFSET 0x500 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_0_BIT 0 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_1_BIT 1 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_2_BIT 2 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_3_BIT 3 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_4_BIT 4 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_5_BIT 5 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_6_BIT 6 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_7_BIT 7 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_8_BIT 8 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_9_BIT 9 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_10_BIT 10 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_11_BIT 11 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_12_BIT 12 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_13_BIT 13 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_14_BIT 14 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_15_BIT 15 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_16_BIT 16 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_17_BIT 17 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_18_BIT 18 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_19_BIT 19 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_20_BIT 20 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_21_BIT 21 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_22_BIT 22 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_23_BIT 23 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_24_BIT 24 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_25_BIT 25 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_26_BIT 26 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_27_BIT 27 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_28_BIT 28 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_29_BIT 29 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_30_BIT 30 +#define GPIO_INTRPT_LVL_LOW_EN_INTRPT_LVL_LOW_EN_31_BIT 31 + +// Asserted if there is any pending interrupts on corresponding GPIOs. +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_FIELD_WIDTH 1 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_FIELDS_PER_REG 32 +#define GPIO_INTRPT_STATUS_MULTIREG_COUNT 1 + +// Asserted if there is any pending interrupts on corresponding GPIOs. +#define GPIO_INTRPT_STATUS_REG_OFFSET 0x580 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_0_BIT 0 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_1_BIT 1 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_2_BIT 2 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_3_BIT 3 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_4_BIT 4 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_5_BIT 5 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_6_BIT 6 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_7_BIT 7 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_8_BIT 8 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_9_BIT 9 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_10_BIT 10 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_11_BIT 11 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_12_BIT 12 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_13_BIT 13 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_14_BIT 14 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_15_BIT 15 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_16_BIT 16 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_17_BIT 17 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_18_BIT 18 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_19_BIT 19 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_20_BIT 20 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_21_BIT 21 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_22_BIT 22 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_23_BIT 23 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_24_BIT 24 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_25_BIT 25 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_26_BIT 26 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_27_BIT 27 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_28_BIT 28 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_29_BIT 29 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_30_BIT 30 +#define GPIO_INTRPT_STATUS_INTRPT_STATUS_31_BIT 31 + +// Asserted if there is a pending rise interrupts on corresponding GPIOs. +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_FIELD_WIDTH 1 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_FIELDS_PER_REG 32 +#define GPIO_INTRPT_RISE_STATUS_MULTIREG_COUNT 1 + +// Asserted if there is a pending rise interrupts on corresponding GPIOs. +#define GPIO_INTRPT_RISE_STATUS_REG_OFFSET 0x600 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_0_BIT 0 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_1_BIT 1 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_2_BIT 2 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_3_BIT 3 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_4_BIT 4 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_5_BIT 5 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_6_BIT 6 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_7_BIT 7 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_8_BIT 8 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_9_BIT 9 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_10_BIT 10 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_11_BIT 11 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_12_BIT 12 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_13_BIT 13 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_14_BIT 14 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_15_BIT 15 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_16_BIT 16 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_17_BIT 17 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_18_BIT 18 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_19_BIT 19 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_20_BIT 20 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_21_BIT 21 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_22_BIT 22 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_23_BIT 23 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_24_BIT 24 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_25_BIT 25 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_26_BIT 26 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_27_BIT 27 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_28_BIT 28 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_29_BIT 29 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_30_BIT 30 +#define GPIO_INTRPT_RISE_STATUS_INTRPT_RISE_STATUS_31_BIT 31 + +// Asserted if there is any pending fall interrupts on corresponding GPIOs. +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_FIELD_WIDTH 1 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_FIELDS_PER_REG 32 +#define GPIO_INTRPT_FALL_STATUS_MULTIREG_COUNT 1 + +// Asserted if there is any pending fall interrupts on corresponding GPIOs. +#define GPIO_INTRPT_FALL_STATUS_REG_OFFSET 0x680 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_0_BIT 0 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_1_BIT 1 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_2_BIT 2 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_3_BIT 3 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_4_BIT 4 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_5_BIT 5 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_6_BIT 6 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_7_BIT 7 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_8_BIT 8 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_9_BIT 9 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_10_BIT 10 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_11_BIT 11 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_12_BIT 12 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_13_BIT 13 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_14_BIT 14 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_15_BIT 15 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_16_BIT 16 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_17_BIT 17 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_18_BIT 18 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_19_BIT 19 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_20_BIT 20 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_21_BIT 21 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_22_BIT 22 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_23_BIT 23 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_24_BIT 24 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_25_BIT 25 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_26_BIT 26 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_27_BIT 27 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_28_BIT 28 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_29_BIT 29 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_30_BIT 30 +#define GPIO_INTRPT_FALL_STATUS_INTRPT_FALL_STATUS_31_BIT 31 + +// Asserted if there is any pending high-level interrupts on corresponding +// GPIOs. +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_FIELD_WIDTH 1 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_FIELDS_PER_REG 32 +#define GPIO_INTRPT_LVL_HIGH_STATUS_MULTIREG_COUNT 1 + +// Asserted if there is any pending high-level interrupts on corresponding +// GPIOs. +#define GPIO_INTRPT_LVL_HIGH_STATUS_REG_OFFSET 0x700 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_0_BIT 0 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_1_BIT 1 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_2_BIT 2 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_3_BIT 3 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_4_BIT 4 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_5_BIT 5 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_6_BIT 6 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_7_BIT 7 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_8_BIT 8 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_9_BIT 9 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_10_BIT 10 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_11_BIT 11 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_12_BIT 12 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_13_BIT 13 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_14_BIT 14 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_15_BIT 15 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_16_BIT 16 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_17_BIT 17 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_18_BIT 18 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_19_BIT 19 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_20_BIT 20 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_21_BIT 21 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_22_BIT 22 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_23_BIT 23 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_24_BIT 24 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_25_BIT 25 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_26_BIT 26 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_27_BIT 27 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_28_BIT 28 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_29_BIT 29 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_30_BIT 30 +#define GPIO_INTRPT_LVL_HIGH_STATUS_INTRPT_LVL_HIGH_STATUS_31_BIT 31 + +// Asserted if there is any pending low-level interrupts on corresponding +// GPIOs. +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_FIELD_WIDTH 1 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_FIELDS_PER_REG 32 +#define GPIO_INTRPT_LVL_LOW_STATUS_MULTIREG_COUNT 1 + +// Asserted if there is any pending low-level interrupts on corresponding +// GPIOs. +#define GPIO_INTRPT_LVL_LOW_STATUS_REG_OFFSET 0x780 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_0_BIT 0 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_1_BIT 1 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_2_BIT 2 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_3_BIT 3 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_4_BIT 4 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_5_BIT 5 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_6_BIT 6 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_7_BIT 7 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_8_BIT 8 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_9_BIT 9 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_10_BIT 10 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_11_BIT 11 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_12_BIT 12 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_13_BIT 13 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_14_BIT 14 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_15_BIT 15 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_16_BIT 16 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_17_BIT 17 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_18_BIT 18 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_19_BIT 19 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_20_BIT 20 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_21_BIT 21 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_22_BIT 22 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_23_BIT 23 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_24_BIT 24 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_25_BIT 25 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_26_BIT 26 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_27_BIT 27 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_28_BIT 28 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_29_BIT 29 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_30_BIT 30 +#define GPIO_INTRPT_LVL_LOW_STATUS_INTRPT_LVL_LOW_STATUS_31_BIT 31 + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _GPIO_REG_DEFS_ +// End generated register defines for gpio \ No newline at end of file diff --git a/hw/vendor/pulp_platform_gpio/requirements.txt b/hw/vendor/pulp_platform_gpio/requirements.txt new file mode 100644 index 000000000..1f824cb05 --- /dev/null +++ b/hw/vendor/pulp_platform_gpio/requirements.txt @@ -0,0 +1,4 @@ +hjson==3.1.0 +Mako==1.2.4 +MarkupSafe==2.1.1 +PyYAML==6.0 diff --git a/hw/vendor/pulp_platform_gpio/src/gpio.sv b/hw/vendor/pulp_platform_gpio/src/gpio.sv new file mode 100644 index 000000000..e88071d13 --- /dev/null +++ b/hw/vendor/pulp_platform_gpio/src/gpio.sv @@ -0,0 +1,284 @@ +//----------------------------------------------------------------------------- +// Title : GPIO Peripheral +//----------------------------------------------------------------------------- +// File : gpio.sv +// Author : Manuel Eggimann +// Created : 06.05.2021 +//----------------------------------------------------------------------------- +// Description : +// This Module contains a very simple but clean implementation of a GPIO +// peripheral. The is controlled through a lightweight reg_bus interface. At the +// bottom of this file there is a SV interface wrapper for the module. +//----------------------------------------------------------------------------- +// Copyright (C) 2013-2021 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//----------------------------------------------------------------------------- + + +`include "typedef.svh" +`include "assign.svh" + +`define assert_condition(cond, rst_ni) \ +assert(^cond !== 1'bx | rst_ni !== 1'b1) \ + else $error("Condition: %s = X in instance %m.", `"cond`") + +module gpio #( + /// Data width of the reg_bus + parameter int unsigned DATA_WIDTH = 32, + /// Regbus request struct type. + parameter type reg_req_t = logic, + /// Regbus response struct type. + parameter type reg_rsp_t = logic, + /// The number of GPIOs in this module. This parameter can only be changed if + /// the corresponding register file is regenerated with the same number of + /// GPIOs. The module will error out during elaboration if the given parameter + /// does not match the number of defined GPIOs in the register file. + localparam int unsigned NrGPIOs = gpio_reg_pkg::GPIOCount +) ( + /// Primary input clock. The control interface is suposed to be synchronous to + /// this clock. + input logic clk_i, + /// Asynchronous active-low reset + input logic rst_ni, + /// GPIO input signals from IO Pads (Pad -> SoC) signal. + input logic [NrGPIOs-1:0] gpio_in, + /// GPIO output signals to IO Pads (SoC -> Pad) signal. + output logic [NrGPIOs-1:0] gpio_out, + /// GPIO tx enable signals. This signal is supposed to control the output + /// buffer enable of the corresponding IO Pad. 0 -> RX (input), 1 -> TX (output). + output logic [NrGPIOs-1:0] gpio_tx_en_o, // 0 -> input, 1 -> output + /// Synchronized GPIO input signals. This port provides the `gpio_in` signal + /// synchronized to `clk_i`. + output logic [NrGPIOs-1:0] gpio_in_sync_o, + /// Global interrupt line. The interrupt line is asserted for one `clk_i` + /// whenever an unmasked interrupt on one of the GPIOs arrives. + output logic interrupt_o, + /// Control interface request side using register_interface protocol. + input reg_req_t reg_req_i, + /// Control interface request side using register_interface protocol. + output reg_rsp_t reg_rsp_o +); + // The version number exposed via the INFO register + localparam logic [9:0] HW_VERSION = 1; + + import gpio_reg_pkg::*; + + // Internal Signals + gpio_reg2hw_t s_reg2hw; + gpio_hw2reg_t s_hw2reg; + + // Synchronized inputs + logic [NrGPIOs-1:0] s_gpio_in_sync; + + + // Individual interrupt signals + logic [NrGPIOs-1:0] s_gpio_rise_edge; + logic [NrGPIOs-1:0] s_gpio_rise_intrpt_mask; + logic [NrGPIOs-1:0] s_gpio_fall_edge; + logic [NrGPIOs-1:0] s_gpio_fall_intrpt_mask; + // for the level sensitive interrupts we can use the synchronized signal + // directly, no need for an additional signal + logic [NrGPIOs-1:0] s_gpio_high_intrpt_mask; + logic [NrGPIOs-1:0] s_gpio_low_intrpt_mask; + + logic [NrGPIOs-1:0] s_gpio_rise_intrpt; + logic [NrGPIOs-1:0] s_gpio_fall_intrpt; + logic [NrGPIOs-1:0] s_gpio_high_intrpt; + logic [NrGPIOs-1:0] s_gpio_low_intrpt; + + // Aggregated interrupts per GPIO + logic [NrGPIOs-1:0] interrupts_edges; // Aggregates new interrupts + logic [NrGPIOs-1:0] interrupts_pending; // Aggregates pending interrupts + + // Instantiate auto-generated register file + gpio_reg_top #( + .reg_req_t(reg_req_t), + .reg_rsp_t(reg_rsp_t) + ) i_reg_file ( + .clk_i, + .rst_ni, + .reg_req_i, + .reg_rsp_o, + .reg2hw(s_reg2hw), + .hw2reg(s_hw2reg), + .devmode_i(1'b1) + ); + + // Asign value to info register + assign s_hw2reg.info.version.d = HW_VERSION; + assign s_hw2reg.info.gpio_cnt.d = NrGPIOs[9:0]; + + // Mask interrupts + assign s_gpio_rise_intrpt = s_gpio_rise_edge & s_gpio_rise_intrpt_mask; + assign s_gpio_fall_intrpt = s_gpio_fall_edge & s_gpio_fall_intrpt_mask; + assign s_gpio_high_intrpt = s_gpio_in_sync & s_gpio_high_intrpt_mask; + assign s_gpio_low_intrpt = ~s_gpio_in_sync & s_gpio_low_intrpt_mask; + + // Generate combined interrupt signal that combines all enabled interrupts for + // each GPIO + assign interrupts_edges = s_gpio_rise_intrpt | s_gpio_fall_intrpt | s_gpio_high_intrpt | s_gpio_low_intrpt; + + // Aggregate all pending interrupts. Aggregation of all sticky interrupts. + assign interrupts_pending = s_reg2hw.intrpt_rise_status | s_reg2hw.intrpt_fall_status | s_reg2hw.intrpt_lvl_high_status | s_reg2hw.intrpt_lvl_low_status; + + // Assign interrupt output signal depending on inerrupt mode + assign interrupt_o = (s_reg2hw.cfg.intrpt_mode.q)? |interrupts_pending : |interrupts_edges; + + // Assign synchronized gpio inputs to external port + assign gpio_in_sync_o = s_gpio_in_sync; + + // Instantiate logic for individual gpios in blocks of DATA_WIDTH + for (genvar gpio_idx = 0; gpio_idx < NrGPIOs; gpio_idx++) begin : gen_gpios + // Instantiate synchronizer to synchronize input to sampling clock + gpio_input_stage #( + .NrSyncStages(2) + ) i_sync_gpio_input( + .clk_i, + .rst_ni, + .en_i(s_reg2hw.gpio_en[gpio_idx].q && s_reg2hw.gpio_mode[gpio_idx].q == 0), + .serial_i(gpio_in[gpio_idx]), + .r_edge_o(s_gpio_rise_edge[gpio_idx]), + .f_edge_o(s_gpio_fall_edge[gpio_idx]), + .serial_o(s_gpio_in_sync[gpio_idx]) + ); + + // Assign GPIO_IN register + assign s_hw2reg.gpio_in[gpio_idx].d= s_gpio_in_sync[gpio_idx]; + + // Control output with GPIO_OUT register + assign gpio_out[gpio_idx] = s_reg2hw.gpio_out[gpio_idx].q; + // Control gpio_tx_en_o depending on GPIO_MODE register value + always_comb begin + `assert_condition(s_reg2hw.gpio_mode[gpio_idx], rst_ni); + case (s_reg2hw.gpio_mode[gpio_idx]) + 2'b00: begin //INPUT_ONLY + gpio_tx_en_o[gpio_idx] = 1'b0; + end + 2'b01: begin //OUTPUT_ACTIVE + gpio_tx_en_o[gpio_idx] = 1'b1; + end + 2'b10: begin // OPEN_DRAIN0 + gpio_tx_en_o[gpio_idx] = s_reg2hw.gpio_out[gpio_idx].q; + end + 2'b11: begin // OPEN_DRAIN1 + gpio_tx_en_o[gpio_idx] = ~s_reg2hw.gpio_out[gpio_idx].q; + end + default: begin + gpio_tx_en_o[gpio_idx] = 1'b0; + end + endcase + end + + // Wire individual masks + assign s_gpio_rise_intrpt_mask[gpio_idx] = s_reg2hw.intrpt_rise_en[gpio_idx].q; + assign s_gpio_fall_intrpt_mask[gpio_idx] = s_reg2hw.intrpt_fall_en[gpio_idx].q; + assign s_gpio_high_intrpt_mask[gpio_idx] = s_reg2hw.intrpt_lvl_high_en[gpio_idx].q; + assign s_gpio_low_intrpt_mask[gpio_idx] = s_reg2hw.intrpt_lvl_low_en[gpio_idx].q; + + // GPIO set, clear and toggle logic + always_comb begin + unique if (s_reg2hw.gpio_set[gpio_idx].qe && s_reg2hw.gpio_set[gpio_idx].q) begin + `assert_condition(s_reg2hw.gpio_set[gpio_idx].qe && s_reg2hw.gpio_set[gpio_idx].q, rst_ni); + s_hw2reg.gpio_out[gpio_idx].d = 1'b1; + s_hw2reg.gpio_out[gpio_idx].de = 1'b1; + end else if (s_reg2hw.gpio_clear[gpio_idx].qe && s_reg2hw.gpio_clear[gpio_idx].q) begin + `assert_condition(s_reg2hw.gpio_clear[gpio_idx].qe && s_reg2hw.gpio_clear[gpio_idx].q, rst_ni); + s_hw2reg.gpio_out[gpio_idx].d = 1'b0; + s_hw2reg.gpio_out[gpio_idx].de = 1'b1; + end else if (s_reg2hw.gpio_toggle[gpio_idx].qe && s_reg2hw.gpio_toggle[gpio_idx].q) begin + `assert_condition(s_reg2hw.gpio_toggle[gpio_idx].qe && s_reg2hw.gpio_toggle[gpio_idx].q, rst_ni); + s_hw2reg.gpio_out[gpio_idx].d = ~s_reg2hw.gpio_out[gpio_idx].q; + s_hw2reg.gpio_out[gpio_idx].de = 1'b1; + end else begin + s_hw2reg.gpio_out[gpio_idx].d = s_reg2hw.gpio_out[gpio_idx].q; + s_hw2reg.gpio_out[gpio_idx].de = 1'b0; + end + end + + //Wire interrupt status registers + always_comb begin + `assert_condition({s_reg2hw.intrpt_status[gpio_idx].qe, s_reg2hw.intrpt_status[gpio_idx].q}, rst_ni); + //If we clear the aggregated, clear all individual interrupt status registers for the corresponding block of + //GPIOs + if (s_reg2hw.intrpt_status[gpio_idx].qe & (s_reg2hw.intrpt_status[gpio_idx].q == 1)) begin + s_hw2reg.intrpt_rise_status[gpio_idx].d = '0; + s_hw2reg.intrpt_rise_status[gpio_idx].de = 1'b1; + s_hw2reg.intrpt_fall_status[gpio_idx].d = '0; + s_hw2reg.intrpt_fall_status[gpio_idx].de = 1'b1; + s_hw2reg.intrpt_lvl_high_status[gpio_idx].d = '0; + s_hw2reg.intrpt_lvl_high_status[gpio_idx].de = 1'b1; + s_hw2reg.intrpt_lvl_low_status[gpio_idx].d = '0; + s_hw2reg.intrpt_lvl_low_status[gpio_idx].de = 1'b1; + end else begin + // Set new bits of the the individual status registers when an interrupt + // arrives. Only update the registers (de) if there are any new + // interrupts of the given type. + s_hw2reg.intrpt_rise_status[gpio_idx].d = s_gpio_rise_intrpt[gpio_idx] | s_reg2hw.intrpt_rise_status[gpio_idx].q; + s_hw2reg.intrpt_rise_status[gpio_idx].de = |s_gpio_rise_intrpt[gpio_idx]; + s_hw2reg.intrpt_fall_status[gpio_idx].d = s_gpio_fall_intrpt[gpio_idx] | s_reg2hw.intrpt_fall_status[gpio_idx].q; + s_hw2reg.intrpt_fall_status[gpio_idx].de = |s_gpio_fall_intrpt[gpio_idx]; + s_hw2reg.intrpt_lvl_high_status[gpio_idx].d = s_gpio_high_intrpt[gpio_idx] | s_reg2hw.intrpt_lvl_high_status[gpio_idx].q; + s_hw2reg.intrpt_lvl_high_status[gpio_idx].de = |s_gpio_high_intrpt[gpio_idx]; + s_hw2reg.intrpt_lvl_low_status[gpio_idx].d = s_gpio_low_intrpt[gpio_idx] | s_reg2hw.intrpt_lvl_low_status[gpio_idx].q; + s_hw2reg.intrpt_lvl_low_status[gpio_idx].de = |s_gpio_low_intrpt[gpio_idx]; + end + end // always_comb + assign s_hw2reg.intrpt_status[gpio_idx].d = interrupts_pending[gpio_idx]; + end +endmodule : gpio + +module gpio_intf #( + /// ADDR_WIDTH of the reg_bus interface + parameter int unsigned ADDR_WIDTH = 32, + /// DATA_WIDTH of the reg_bus interface + parameter int unsigned DATA_WIDTH = 32, + localparam int unsigned NrGPIOs = gpio_reg_pkg::GPIOCount, + localparam int unsigned STRB_WIDTH = DATA_WIDTH/8 +) ( + input logic clk_i, + input logic rst_ni, + input logic [NrGPIOs-1:0] gpio_in, + output logic [NrGPIOs-1:0] gpio_out, + output logic [NrGPIOs-1:0] gpio_tx_en_o, // 0 -> input, 1 -> output + output logic [NrGPIOs-1:0] gpio_in_sync_o, // sampled and synchronized GPIO + // input. + output logic interrupt_o, + REG_BUS.in reg_bus +); + + // Define structs for reg_bus + typedef logic [ADDR_WIDTH-1:0] addr_t; + typedef logic [DATA_WIDTH-1:0] data_t; + typedef logic [STRB_WIDTH-1:0] strb_t; + `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t) + + reg_bus_req_t s_reg_req; + reg_bus_rsp_t s_reg_rsp; + + // Assign SV interface to structs + `REG_BUS_ASSIGN_TO_REQ(s_reg_req, reg_bus) + `REG_BUS_ASSIGN_FROM_RSP(reg_bus, s_reg_rsp) + + gpio #( + .reg_req_t(reg_bus_req_t), + .reg_rsp_t(reg_bus_rsp_t) + ) i_gpio ( + .clk_i, + .rst_ni, + .gpio_in, + .gpio_out, + .gpio_tx_en_o, // 0 -> input, 1 -> output + .gpio_in_sync_o, // sampled and synchronized GPIO + .interrupt_o, + .reg_req_i(s_reg_req), + .reg_rsp_o(s_reg_rsp) + ); + +endmodule : gpio_intf diff --git a/hw/vendor/pulp_platform_gpio/src/gpio_apb_wrap.sv b/hw/vendor/pulp_platform_gpio/src/gpio_apb_wrap.sv new file mode 100644 index 000000000..fcfa2a34f --- /dev/null +++ b/hw/vendor/pulp_platform_gpio/src/gpio_apb_wrap.sv @@ -0,0 +1,133 @@ +//----------------------------------------------------------------------------- +// Title : GPIO APB Wrapper +//----------------------------------------------------------------------------- +// File : gpio_apb_wrap.sv +// Author : Manuel Eggimann +// Created : 06.05.2021 +//----------------------------------------------------------------------------- +// Description : +// This file provides wrappers around the GPIO peripheral with an APB +// interface. The file contains two versions of the module, one structs for the +// APB interface and one using SystemVerilog Interfaces. +//----------------------------------------------------------------------------- +// Copyright (C) 2013-2021 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//----------------------------------------------------------------------------- +`include "apb/typedef.svh" +`include "apb/assign.svh" + +module gpio_apb_wrap # ( + /// ADDR_WIDTH of the APB interface + parameter int unsigned ADDR_WIDTH = 32, + /// DATA_WIDTH of the APB interface + parameter int unsigned DATA_WIDTH = 32, + /// APB request struct type. + parameter type apb_req_t = logic, + /// APB response struct type. + parameter type apb_rsp_t = logic, + localparam int unsigned NrGPIOs = gpio_reg_pkg::GPIOCount, + localparam int unsigned STRB_WIDTH = DATA_WIDTH/8 +)( + input logic clk_i, + input logic rst_ni, + input logic [NrGPIOs-1:0] gpio_in, + output logic [NrGPIOs-1:0] gpio_out, + output logic [NrGPIOs-1:0] gpio_tx_en_o, // 0 -> input, 1 -> output + output logic [NrGPIOs-1:0] gpio_in_sync_o, // sampled and synchronized GPIO + // input. + output logic interrupt_o, + input apb_req_t apb_req_i, + output apb_rsp_t apb_rsp_o +); + + // Convert APB to reg_bus + REG_BUS #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH)) s_reg_bus(); + apb_to_reg i_abp_to_reg ( + .clk_i, + .rst_ni, + .penable_i ( apb_req_i.penable ), + .pwrite_i ( apb_req_i.pwrite ), + .paddr_i ( apb_req_i.paddr ), + .psel_i ( apb_req_i.psel ), + .pwdata_i ( apb_req_i.pwdata ), + .prdata_o ( apb_rsp_o.prdata ), + .pready_o ( apb_rsp_o.pready ), + .pslverr_o ( apb_rsp_o.pslverr ), + .reg_o ( s_reg_bus ) + ); + + gpio_intf #( + .ADDR_WIDTH ( ADDR_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ) + ) i_gpio ( + .clk_i, + .rst_ni, + .gpio_in, + .gpio_out, + .gpio_tx_en_o, + .gpio_in_sync_o, + .interrupt_o, + .reg_bus(s_reg_bus) + ); +endmodule // gpio_apb_wrap + + +module gpio_apb_wrap_intf # ( + /// ADDR_WIDTH of the APB interface + parameter int unsigned ADDR_WIDTH = 32, + /// DATA_WIDTH of the APB interface + parameter int unsigned DATA_WIDTH = 32, + localparam int unsigned NrGPIOs = gpio_reg_pkg::GPIOCount, + localparam int unsigned STRB_WIDTH = DATA_WIDTH/8 +)( + input logic clk_i, + input logic rst_ni, + input logic [NrGPIOs-1:0] gpio_in, + output logic [NrGPIOs-1:0] gpio_out, + output logic [NrGPIOs-1:0] gpio_tx_en_o, // 0 -> input, 1 -> output + output logic [NrGPIOs-1:0] gpio_in_sync_o, // sampled and synchronized GPIO + // input. + output logic interrupt_o, + APB.Slave apb_slave +); + + // Convert SV Interface to structs + typedef logic [ADDR_WIDTH-1:0] addr_t; + typedef logic [DATA_WIDTH-1:0] data_t; + typedef logic [DATA_WIDTH/8-1:0] strb_t; // The APB bus interface only + // supports 8-bit strobe so we don't need to + // check the strobe width of the intput bus. + `APB_TYPEDEF_REQ_T(apb_req_t, addr_t, data_t, strb_t) + `APB_TYPEDEF_RESP_T(apb_rsp_t, data_t) + + apb_req_t s_apb_req; + apb_rsp_t s_apb_rsp; + + `APB_ASSIGN_TO_REQ(s_apb_req, apb_slave) + `APB_ASSIGN_FROM_RESP(apb_slave, s_apb_rsp) + + gpio_apb_wrap #( + .ADDR_WIDTH ( ADDR_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ), + .apb_req_t ( apb_req_t ), + .apb_rsp_t ( apb_rsp_t ) + ) i_gpio_apb_wrap ( + .clk_i, + .rst_ni, + .gpio_in, + .gpio_out, + .gpio_tx_en_o, + .gpio_in_sync_o, + .interrupt_o, + .apb_req_i ( s_apb_req ), + .apb_rsp_o ( s_apb_rsp ) + ); + +endmodule diff --git a/hw/vendor/pulp_platform_gpio/src/gpio_axi_lite_wrap.sv b/hw/vendor/pulp_platform_gpio/src/gpio_axi_lite_wrap.sv new file mode 100644 index 000000000..99416748c --- /dev/null +++ b/hw/vendor/pulp_platform_gpio/src/gpio_axi_lite_wrap.sv @@ -0,0 +1,158 @@ +//----------------------------------------------------------------------------- +// Title : GPIO AXI Lite Wrapper +//----------------------------------------------------------------------------- +// File : gpio_axi_lite_wrap.sv +// Author : Manuel Eggimann +// Created : 06.05.2021 +//----------------------------------------------------------------------------- +// Description : +// This file provides a wrapper around the GPIO peripheral with an AXI4-lite +// interface. The file contains two versions of the module, one structs for the +// AXI-lite interface and one using SystemVerilog Interfaces. +//----------------------------------------------------------------------------- +// Copyright (C) 2013-2021 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//----------------------------------------------------------------------------- + + +`include "register_interface/typedef.svh" +`include "register_interface/assign.svh" +`include "axi/typedef.svh" +`include "axi/assign.svh" + +module gpio_axi_lite_wrap # ( + /// ADDR_WIDTH of the AXI lite interface + parameter int unsigned ADDR_WIDTH = 32, + /// DATA_WIDTH of the AXI lite interface + parameter int unsigned DATA_WIDTH = 32, + /// Whether the AXI-Lite W channel should be decoupled with a register. This + /// can help break long paths at the expense of registers. + parameter bit DECOUPLE_W = 1, + /// AXI-Lite request struct type. + parameter type axi_lite_req_t = logic, + /// AXI-Lite response struct type. + parameter type axi_lite_rsp_t = logic, + localparam int unsigned NrGPIOs = gpio_reg_pkg::GPIOCount, + localparam int unsigned STRB_WIDTH = DATA_WIDTH/8 +)( + input logic clk_i, + input logic rst_ni, + input logic [NrGPIOs-1:0] gpio_in, + output logic [NrGPIOs-1:0] gpio_out, + output logic [NrGPIOs-1:0] gpio_tx_en_o, // 0 -> input, 1 -> output + output logic [NrGPIOs-1:0] gpio_in_sync_o, // sampled and synchronized GPIO + // input. + output logic interrupt_o, + input axi_lite_req_t axi_lite_req_i, + output axi_lite_rsp_t axi_lite_rsp_o +); + + if (STRB_WIDTH != DATA_WIDTH/8) + $error("Unsupported AXI strobe width (%d) The underlying register bus protocol does not support strobe widths other than 8-bit.", STRB_WIDTH); + + typedef logic [ADDR_WIDTH-1:0] addr_t; + typedef logic [DATA_WIDTH-1:0] data_t; + typedef logic [STRB_WIDTH-1:0] strb_t; + `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t) + + reg_bus_req_t s_reg_req; + reg_bus_rsp_t s_reg_rsp; + + axi_lite_to_reg #( + .ADDR_WIDTH(ADDR_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .BUFFER_DEPTH(1), + .DECOUPLE_W(0), + .axi_lite_req_t(axi_lite_req_t), + .axi_lite_rsp_t(axi_lite_rsp_t), + .reg_req_t(reg_bus_req_t), + .reg_rsp_t(reg_bus_rsp_t) + ) i_axi_lite_to_reg ( + .clk_i, + .rst_ni, + .axi_lite_req_i, + .axi_lite_rsp_o, + .reg_req_o(s_reg_req), + .reg_rsp_i(s_reg_rsp) + ); + + + gpio #( + .DATA_WIDTH ( DATA_WIDTH ), + .reg_req_t ( reg_bus_req_t ), + .reg_rsp_t ( reg_bus_rsp_t ) + ) i_gpio ( + .clk_i, + .rst_ni, + .gpio_in, + .gpio_out, + .gpio_tx_en_o, + .gpio_in_sync_o, + .interrupt_o, + .reg_req_i ( s_reg_req ), + .reg_rsp_o ( s_reg_rsp ) + ); + +endmodule + +module gpio_axi_lite_wrap_intf # ( + /// ADDR_WIDTH of the AXI lite interface + parameter int unsigned ADDR_WIDTH = 32, + /// DATA_WIDTH of the AXI lite interface + parameter int unsigned DATA_WIDTH = 32, + /// Whether the AXI-Lite W channel should be decoupled with a register. This + /// can help break long paths at the expense of registers. + parameter bit DECOUPLE_W = 1, + localparam int unsigned NrGPIOs = gpio_reg_pkg::GPIOCount, + localparam int unsigned STRB_WIDTH = DATA_WIDTH/8 +)( + input logic clk_i, + input logic rst_ni, + input logic [NrGPIOs-1:0] gpio_in, + output logic [NrGPIOs-1:0] gpio_out, + output logic [NrGPIOs-1:0] gpio_tx_en_o, // 0 -> input, 1 -> output + output logic [NrGPIOs-1:0] gpio_in_sync_o, // sampled and synchronized GPIO + // input. + output logic interrupt_o, + AXI_LITE.Slave axi_i +); + + // Convert SV interface to structs + // Declare axi_lite structs + typedef logic [ADDR_WIDTH-1:0] addr_t; + typedef logic [DATA_WIDTH-1:0] data_t; + typedef logic [STRB_WIDTH-1:0] strb_t; + `AXI_LITE_TYPEDEF_ALL(axi_lite, addr_t, data_t, strb_t) + // Declare axi_lit struct signals + axi_lite_req_t s_axi_lite_req; + axi_lite_resp_t s_axi_lite_rsp; + // Connect SV interface to structs + `AXI_LITE_ASSIGN_TO_REQ(s_axi_lite_req, axi_i) + `AXI_LITE_ASSIGN_FROM_RESP(axi_i, s_axi_lite_rsp) + + gpio_axi_lite_wrap #( + .ADDR_WIDTH ( ADDR_WIDTH ), + .DATA_WIDTH ( DATA_WIDTH ), + .DECOUPLE_W ( DECOUPLE_W ), + .axi_lite_req_t ( axi_lite_req_t ), + .axi_lite_rsp_t ( axi_lite_resp_t ) + ) i_gpio_axi_lite_wrap ( + .clk_i, + .rst_ni, + .gpio_in, + .gpio_out, + .gpio_tx_en_o, + .gpio_in_sync_o, + .interrupt_o, + .axi_lite_req_i ( s_axi_lite_req ), + .axi_lite_rsp_o ( s_axi_lite_rsp ) + ); + +endmodule diff --git a/hw/vendor/pulp_platform_gpio/src/gpio_input_stage.sv b/hw/vendor/pulp_platform_gpio/src/gpio_input_stage.sv new file mode 100644 index 000000000..e79143db0 --- /dev/null +++ b/hw/vendor/pulp_platform_gpio/src/gpio_input_stage.sv @@ -0,0 +1,81 @@ +//----------------------------------------------------------------------------- +// Title : GPIO Input Stage +//----------------------------------------------------------------------------- +// File : gpio_input_stage.sv +// Author : Manuel Eggimann +// Created : 14.04.2022 +//----------------------------------------------------------------------------- +// Description : +// +// This module implements the input synchronization stage for a single GPIO. It +// uses a two-stage synchronizer for meta-stability resolution. This version of +// the input stage instantiates a clock gate to disable input sampling when the +// corresponding GPIO is disabled. This clock gate instance (tc_clk_gating) is +// behavioraly implemented in the `pulp-plaform/common_cells` (on GitHub) +// repository. In case you want to tape-out this GPIO, you either have to map +// this behavioral clock gate cell to a dedicated ICG of your std cell library +// or use the alternative version (`gpio_input_stage_no_clk_gates.sv`) of the +// input stage that does not include any clock gates. +// +//----------------------------------------------------------------------------- +// Copyright (C) 2022 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// SPDX-License-Identifier: SHL-0.51 +//----------------------------------------------------------------------------- + + +module gpio_input_stage #( + parameter NrSyncStages=2 +) ( + input logic clk_i, + input logic rst_ni, + input logic en_i, + input logic serial_i, + output logic r_edge_o, + output logic f_edge_o, + output logic serial_o +); + + logic clk; + logic serial, serial_q; + + assign serial_o = serial_q; + assign f_edge_o = (~serial) & serial_q; + assign r_edge_o = serial & (~serial_q); + + tc_clk_gating #( + .IS_FUNCTIONAL(0) // The clock gate is not required for proper + // functionality. Just for power saving. + ) i_clk_gate ( + .clk_i, + .en_i, + .test_en_i ( 1'b0 ), + .clk_o ( clk ) + ); + + sync #( + .STAGES (NrSyncStages) + ) i_sync ( + .clk_i(clk), + .rst_ni, + .serial_i, + .serial_o ( serial ) + ); + + always_ff @(posedge clk, negedge rst_ni) begin + if (!rst_ni) begin + serial_q <= 1'b0; + end else begin + serial_q <= serial; + end + end + + +endmodule : gpio_input_stage diff --git a/hw/vendor/pulp_platform_gpio/src/gpio_input_stage_no_clk_gates.sv b/hw/vendor/pulp_platform_gpio/src/gpio_input_stage_no_clk_gates.sv new file mode 100644 index 000000000..b73f5ab88 --- /dev/null +++ b/hw/vendor/pulp_platform_gpio/src/gpio_input_stage_no_clk_gates.sv @@ -0,0 +1,39 @@ +module gpio_input_stage #( + parameter NrSyncStages=2 +) ( + input logic clk_i, + input logic rst_ni, + input logic en_i, + input logic serial_i, + output logic r_edge_o, + output logic f_edge_o, + output logic serial_o +); + + logic serial, serial_q; + + assign serial_o = serial_q; + assign f_edge_o = (~serial) & serial_q; + assign r_edge_o = serial & (~serial_q); + + sync #( + .STAGES (NrSyncStages) + ) i_sync ( + .clk_i(clk_i), + .rst_ni, + .serial_i, + .serial_o ( serial ) + ); + + always_ff @(posedge clk_i, negedge rst_ni) begin + if (!rst_ni) begin + serial_q <= 1'b0; + end else begin + if (en_i) begin + serial_q <= serial; + end + end + end + + +endmodule : gpio_input_stage diff --git a/hw/vendor/pulp_platform_gpio/src/gpio_reg_pkg.sv b/hw/vendor/pulp_platform_gpio/src/gpio_reg_pkg.sv new file mode 100644 index 000000000..7b327e7f9 --- /dev/null +++ b/hw/vendor/pulp_platform_gpio/src/gpio_reg_pkg.sv @@ -0,0 +1,243 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package gpio_reg_pkg; + + // Param list + parameter int GPIOCount = 32; + + // Address widths within the block + parameter int BlockAw = 11; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + struct packed { + logic q; + } intrpt_mode; + struct packed { + logic q; + } reserved; + } gpio_reg2hw_cfg_reg_t; + + typedef struct packed { + logic [1:0] q; + } gpio_reg2hw_gpio_mode_mreg_t; + + typedef struct packed { + logic q; + } gpio_reg2hw_gpio_en_mreg_t; + + typedef struct packed { + logic q; + } gpio_reg2hw_gpio_out_mreg_t; + + typedef struct packed { + logic q; + logic qe; + } gpio_reg2hw_gpio_set_mreg_t; + + typedef struct packed { + logic q; + logic qe; + } gpio_reg2hw_gpio_clear_mreg_t; + + typedef struct packed { + logic q; + logic qe; + } gpio_reg2hw_gpio_toggle_mreg_t; + + typedef struct packed { + logic q; + } gpio_reg2hw_intrpt_rise_en_mreg_t; + + typedef struct packed { + logic q; + } gpio_reg2hw_intrpt_fall_en_mreg_t; + + typedef struct packed { + logic q; + } gpio_reg2hw_intrpt_lvl_high_en_mreg_t; + + typedef struct packed { + logic q; + } gpio_reg2hw_intrpt_lvl_low_en_mreg_t; + + typedef struct packed { + logic q; + logic qe; + } gpio_reg2hw_intrpt_status_mreg_t; + + typedef struct packed { + logic q; + } gpio_reg2hw_intrpt_rise_status_mreg_t; + + typedef struct packed { + logic q; + } gpio_reg2hw_intrpt_fall_status_mreg_t; + + typedef struct packed { + logic q; + } gpio_reg2hw_intrpt_lvl_high_status_mreg_t; + + typedef struct packed { + logic q; + } gpio_reg2hw_intrpt_lvl_low_status_mreg_t; + + typedef struct packed { + struct packed { + logic [9:0] d; + } gpio_cnt; + struct packed { + logic [9:0] d; + } version; + } gpio_hw2reg_info_reg_t; + + typedef struct packed { + logic d; + } gpio_hw2reg_gpio_in_mreg_t; + + typedef struct packed { + logic d; + logic de; + } gpio_hw2reg_gpio_out_mreg_t; + + typedef struct packed { + logic d; + } gpio_hw2reg_intrpt_status_mreg_t; + + typedef struct packed { + logic d; + logic de; + } gpio_hw2reg_intrpt_rise_status_mreg_t; + + typedef struct packed { + logic d; + logic de; + } gpio_hw2reg_intrpt_fall_status_mreg_t; + + typedef struct packed { + logic d; + logic de; + } gpio_hw2reg_intrpt_lvl_high_status_mreg_t; + + typedef struct packed { + logic d; + logic de; + } gpio_hw2reg_intrpt_lvl_low_status_mreg_t; + + // Register -> HW type + typedef struct packed { + gpio_reg2hw_cfg_reg_t cfg; // [641:640] + gpio_reg2hw_gpio_mode_mreg_t [31:0] gpio_mode; // [639:576] + gpio_reg2hw_gpio_en_mreg_t [31:0] gpio_en; // [575:544] + gpio_reg2hw_gpio_out_mreg_t [31:0] gpio_out; // [543:512] + gpio_reg2hw_gpio_set_mreg_t [31:0] gpio_set; // [511:448] + gpio_reg2hw_gpio_clear_mreg_t [31:0] gpio_clear; // [447:384] + gpio_reg2hw_gpio_toggle_mreg_t [31:0] gpio_toggle; // [383:320] + gpio_reg2hw_intrpt_rise_en_mreg_t [31:0] intrpt_rise_en; // [319:288] + gpio_reg2hw_intrpt_fall_en_mreg_t [31:0] intrpt_fall_en; // [287:256] + gpio_reg2hw_intrpt_lvl_high_en_mreg_t [31:0] intrpt_lvl_high_en; // [255:224] + gpio_reg2hw_intrpt_lvl_low_en_mreg_t [31:0] intrpt_lvl_low_en; // [223:192] + gpio_reg2hw_intrpt_status_mreg_t [31:0] intrpt_status; // [191:128] + gpio_reg2hw_intrpt_rise_status_mreg_t [31:0] intrpt_rise_status; // [127:96] + gpio_reg2hw_intrpt_fall_status_mreg_t [31:0] intrpt_fall_status; // [95:64] + gpio_reg2hw_intrpt_lvl_high_status_mreg_t [31:0] intrpt_lvl_high_status; // [63:32] + gpio_reg2hw_intrpt_lvl_low_status_mreg_t [31:0] intrpt_lvl_low_status; // [31:0] + } gpio_reg2hw_t; + + // HW -> register type + typedef struct packed { + gpio_hw2reg_info_reg_t info; // [403:384] + gpio_hw2reg_gpio_in_mreg_t [31:0] gpio_in; // [383:352] + gpio_hw2reg_gpio_out_mreg_t [31:0] gpio_out; // [351:288] + gpio_hw2reg_intrpt_status_mreg_t [31:0] intrpt_status; // [287:256] + gpio_hw2reg_intrpt_rise_status_mreg_t [31:0] intrpt_rise_status; // [255:192] + gpio_hw2reg_intrpt_fall_status_mreg_t [31:0] intrpt_fall_status; // [191:128] + gpio_hw2reg_intrpt_lvl_high_status_mreg_t [31:0] intrpt_lvl_high_status; // [127:64] + gpio_hw2reg_intrpt_lvl_low_status_mreg_t [31:0] intrpt_lvl_low_status; // [63:0] + } gpio_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] GPIO_INFO_OFFSET = 11'h 0; + parameter logic [BlockAw-1:0] GPIO_CFG_OFFSET = 11'h 4; + parameter logic [BlockAw-1:0] GPIO_GPIO_MODE_0_OFFSET = 11'h 8; + parameter logic [BlockAw-1:0] GPIO_GPIO_MODE_1_OFFSET = 11'h c; + parameter logic [BlockAw-1:0] GPIO_GPIO_EN_OFFSET = 11'h 80; + parameter logic [BlockAw-1:0] GPIO_GPIO_IN_OFFSET = 11'h 100; + parameter logic [BlockAw-1:0] GPIO_GPIO_OUT_OFFSET = 11'h 180; + parameter logic [BlockAw-1:0] GPIO_GPIO_SET_OFFSET = 11'h 200; + parameter logic [BlockAw-1:0] GPIO_GPIO_CLEAR_OFFSET = 11'h 280; + parameter logic [BlockAw-1:0] GPIO_GPIO_TOGGLE_OFFSET = 11'h 300; + parameter logic [BlockAw-1:0] GPIO_INTRPT_RISE_EN_OFFSET = 11'h 380; + parameter logic [BlockAw-1:0] GPIO_INTRPT_FALL_EN_OFFSET = 11'h 400; + parameter logic [BlockAw-1:0] GPIO_INTRPT_LVL_HIGH_EN_OFFSET = 11'h 480; + parameter logic [BlockAw-1:0] GPIO_INTRPT_LVL_LOW_EN_OFFSET = 11'h 500; + parameter logic [BlockAw-1:0] GPIO_INTRPT_STATUS_OFFSET = 11'h 580; + parameter logic [BlockAw-1:0] GPIO_INTRPT_RISE_STATUS_OFFSET = 11'h 600; + parameter logic [BlockAw-1:0] GPIO_INTRPT_FALL_STATUS_OFFSET = 11'h 680; + parameter logic [BlockAw-1:0] GPIO_INTRPT_LVL_HIGH_STATUS_OFFSET = 11'h 700; + parameter logic [BlockAw-1:0] GPIO_INTRPT_LVL_LOW_STATUS_OFFSET = 11'h 780; + + // Reset values for hwext registers and their fields + parameter logic [19:0] GPIO_INFO_RESVAL = 20'h 800; + parameter logic [9:0] GPIO_INFO_VERSION_RESVAL = 10'h 2; + parameter logic [31:0] GPIO_GPIO_IN_RESVAL = 32'h 0; + parameter logic [31:0] GPIO_GPIO_SET_RESVAL = 32'h 0; + parameter logic [31:0] GPIO_GPIO_CLEAR_RESVAL = 32'h 0; + parameter logic [31:0] GPIO_GPIO_TOGGLE_RESVAL = 32'h 0; + parameter logic [31:0] GPIO_INTRPT_STATUS_RESVAL = 32'h 0; + + // Register index + typedef enum int { + GPIO_INFO, + GPIO_CFG, + GPIO_GPIO_MODE_0, + GPIO_GPIO_MODE_1, + GPIO_GPIO_EN, + GPIO_GPIO_IN, + GPIO_GPIO_OUT, + GPIO_GPIO_SET, + GPIO_GPIO_CLEAR, + GPIO_GPIO_TOGGLE, + GPIO_INTRPT_RISE_EN, + GPIO_INTRPT_FALL_EN, + GPIO_INTRPT_LVL_HIGH_EN, + GPIO_INTRPT_LVL_LOW_EN, + GPIO_INTRPT_STATUS, + GPIO_INTRPT_RISE_STATUS, + GPIO_INTRPT_FALL_STATUS, + GPIO_INTRPT_LVL_HIGH_STATUS, + GPIO_INTRPT_LVL_LOW_STATUS + } gpio_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] GPIO_PERMIT [19] = '{ + 4'b 0111, // index[ 0] GPIO_INFO + 4'b 0001, // index[ 1] GPIO_CFG + 4'b 1111, // index[ 2] GPIO_GPIO_MODE_0 + 4'b 1111, // index[ 3] GPIO_GPIO_MODE_1 + 4'b 1111, // index[ 4] GPIO_GPIO_EN + 4'b 1111, // index[ 5] GPIO_GPIO_IN + 4'b 1111, // index[ 6] GPIO_GPIO_OUT + 4'b 1111, // index[ 7] GPIO_GPIO_SET + 4'b 1111, // index[ 8] GPIO_GPIO_CLEAR + 4'b 1111, // index[ 9] GPIO_GPIO_TOGGLE + 4'b 1111, // index[10] GPIO_INTRPT_RISE_EN + 4'b 1111, // index[11] GPIO_INTRPT_FALL_EN + 4'b 1111, // index[12] GPIO_INTRPT_LVL_HIGH_EN + 4'b 1111, // index[13] GPIO_INTRPT_LVL_LOW_EN + 4'b 1111, // index[14] GPIO_INTRPT_STATUS + 4'b 1111, // index[15] GPIO_INTRPT_RISE_STATUS + 4'b 1111, // index[16] GPIO_INTRPT_FALL_STATUS + 4'b 1111, // index[17] GPIO_INTRPT_LVL_HIGH_STATUS + 4'b 1111 // index[18] GPIO_INTRPT_LVL_LOW_STATUS + }; + +endpackage + diff --git a/hw/vendor/pulp_platform_gpio/src/gpio_reg_top.sv b/hw/vendor/pulp_platform_gpio/src/gpio_reg_top.sv new file mode 100644 index 000000000..f5e65a239 --- /dev/null +++ b/hw/vendor/pulp_platform_gpio/src/gpio_reg_top.sv @@ -0,0 +1,15437 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + + +`include "common_cells/assertions.svh" + +module gpio_reg_top #( + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic, + parameter int AW = 11 +) ( + input clk_i, + input rst_ni, + input reg_req_t reg_req_i, + output reg_rsp_t reg_rsp_o, + // To HW + output gpio_reg_pkg::gpio_reg2hw_t reg2hw, // Write + input gpio_reg_pkg::gpio_hw2reg_t hw2reg, // Read + + + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + + import gpio_reg_pkg::* ; + + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [AW-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + + // Below register interface can be changed + reg_req_t reg_intf_req; + reg_rsp_t reg_intf_rsp; + + + assign reg_intf_req = reg_req_i; + assign reg_rsp_o = reg_intf_rsp; + + + assign reg_we = reg_intf_req.valid & reg_intf_req.write; + assign reg_re = reg_intf_req.valid & ~reg_intf_req.write; + assign reg_addr = reg_intf_req.addr; + assign reg_wdata = reg_intf_req.wdata; + assign reg_be = reg_intf_req.wstrb; + assign reg_intf_rsp.rdata = reg_rdata; + assign reg_intf_rsp.error = reg_error; + assign reg_intf_rsp.ready = 1'b1; + + assign reg_rdata = reg_rdata_next ; + assign reg_error = (devmode_i & addrmiss) | wr_err; + + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic [9:0] info_gpio_cnt_qs; + logic info_gpio_cnt_re; + logic [9:0] info_version_qs; + logic info_version_re; + logic cfg_intrpt_mode_qs; + logic cfg_intrpt_mode_wd; + logic cfg_intrpt_mode_we; + logic cfg_reserved_qs; + logic cfg_reserved_wd; + logic cfg_reserved_we; + logic [1:0] gpio_mode_0_mode_0_qs; + logic [1:0] gpio_mode_0_mode_0_wd; + logic gpio_mode_0_mode_0_we; + logic [1:0] gpio_mode_0_mode_1_qs; + logic [1:0] gpio_mode_0_mode_1_wd; + logic gpio_mode_0_mode_1_we; + logic [1:0] gpio_mode_0_mode_2_qs; + logic [1:0] gpio_mode_0_mode_2_wd; + logic gpio_mode_0_mode_2_we; + logic [1:0] gpio_mode_0_mode_3_qs; + logic [1:0] gpio_mode_0_mode_3_wd; + logic gpio_mode_0_mode_3_we; + logic [1:0] gpio_mode_0_mode_4_qs; + logic [1:0] gpio_mode_0_mode_4_wd; + logic gpio_mode_0_mode_4_we; + logic [1:0] gpio_mode_0_mode_5_qs; + logic [1:0] gpio_mode_0_mode_5_wd; + logic gpio_mode_0_mode_5_we; + logic [1:0] gpio_mode_0_mode_6_qs; + logic [1:0] gpio_mode_0_mode_6_wd; + logic gpio_mode_0_mode_6_we; + logic [1:0] gpio_mode_0_mode_7_qs; + logic [1:0] gpio_mode_0_mode_7_wd; + logic gpio_mode_0_mode_7_we; + logic [1:0] gpio_mode_0_mode_8_qs; + logic [1:0] gpio_mode_0_mode_8_wd; + logic gpio_mode_0_mode_8_we; + logic [1:0] gpio_mode_0_mode_9_qs; + logic [1:0] gpio_mode_0_mode_9_wd; + logic gpio_mode_0_mode_9_we; + logic [1:0] gpio_mode_0_mode_10_qs; + logic [1:0] gpio_mode_0_mode_10_wd; + logic gpio_mode_0_mode_10_we; + logic [1:0] gpio_mode_0_mode_11_qs; + logic [1:0] gpio_mode_0_mode_11_wd; + logic gpio_mode_0_mode_11_we; + logic [1:0] gpio_mode_0_mode_12_qs; + logic [1:0] gpio_mode_0_mode_12_wd; + logic gpio_mode_0_mode_12_we; + logic [1:0] gpio_mode_0_mode_13_qs; + logic [1:0] gpio_mode_0_mode_13_wd; + logic gpio_mode_0_mode_13_we; + logic [1:0] gpio_mode_0_mode_14_qs; + logic [1:0] gpio_mode_0_mode_14_wd; + logic gpio_mode_0_mode_14_we; + logic [1:0] gpio_mode_0_mode_15_qs; + logic [1:0] gpio_mode_0_mode_15_wd; + logic gpio_mode_0_mode_15_we; + logic [1:0] gpio_mode_1_mode_16_qs; + logic [1:0] gpio_mode_1_mode_16_wd; + logic gpio_mode_1_mode_16_we; + logic [1:0] gpio_mode_1_mode_17_qs; + logic [1:0] gpio_mode_1_mode_17_wd; + logic gpio_mode_1_mode_17_we; + logic [1:0] gpio_mode_1_mode_18_qs; + logic [1:0] gpio_mode_1_mode_18_wd; + logic gpio_mode_1_mode_18_we; + logic [1:0] gpio_mode_1_mode_19_qs; + logic [1:0] gpio_mode_1_mode_19_wd; + logic gpio_mode_1_mode_19_we; + logic [1:0] gpio_mode_1_mode_20_qs; + logic [1:0] gpio_mode_1_mode_20_wd; + logic gpio_mode_1_mode_20_we; + logic [1:0] gpio_mode_1_mode_21_qs; + logic [1:0] gpio_mode_1_mode_21_wd; + logic gpio_mode_1_mode_21_we; + logic [1:0] gpio_mode_1_mode_22_qs; + logic [1:0] gpio_mode_1_mode_22_wd; + logic gpio_mode_1_mode_22_we; + logic [1:0] gpio_mode_1_mode_23_qs; + logic [1:0] gpio_mode_1_mode_23_wd; + logic gpio_mode_1_mode_23_we; + logic [1:0] gpio_mode_1_mode_24_qs; + logic [1:0] gpio_mode_1_mode_24_wd; + logic gpio_mode_1_mode_24_we; + logic [1:0] gpio_mode_1_mode_25_qs; + logic [1:0] gpio_mode_1_mode_25_wd; + logic gpio_mode_1_mode_25_we; + logic [1:0] gpio_mode_1_mode_26_qs; + logic [1:0] gpio_mode_1_mode_26_wd; + logic gpio_mode_1_mode_26_we; + logic [1:0] gpio_mode_1_mode_27_qs; + logic [1:0] gpio_mode_1_mode_27_wd; + logic gpio_mode_1_mode_27_we; + logic [1:0] gpio_mode_1_mode_28_qs; + logic [1:0] gpio_mode_1_mode_28_wd; + logic gpio_mode_1_mode_28_we; + logic [1:0] gpio_mode_1_mode_29_qs; + logic [1:0] gpio_mode_1_mode_29_wd; + logic gpio_mode_1_mode_29_we; + logic [1:0] gpio_mode_1_mode_30_qs; + logic [1:0] gpio_mode_1_mode_30_wd; + logic gpio_mode_1_mode_30_we; + logic [1:0] gpio_mode_1_mode_31_qs; + logic [1:0] gpio_mode_1_mode_31_wd; + logic gpio_mode_1_mode_31_we; + logic gpio_en_gpio_en_0_qs; + logic gpio_en_gpio_en_0_wd; + logic gpio_en_gpio_en_0_we; + logic gpio_en_gpio_en_1_qs; + logic gpio_en_gpio_en_1_wd; + logic gpio_en_gpio_en_1_we; + logic gpio_en_gpio_en_2_qs; + logic gpio_en_gpio_en_2_wd; + logic gpio_en_gpio_en_2_we; + logic gpio_en_gpio_en_3_qs; + logic gpio_en_gpio_en_3_wd; + logic gpio_en_gpio_en_3_we; + logic gpio_en_gpio_en_4_qs; + logic gpio_en_gpio_en_4_wd; + logic gpio_en_gpio_en_4_we; + logic gpio_en_gpio_en_5_qs; + logic gpio_en_gpio_en_5_wd; + logic gpio_en_gpio_en_5_we; + logic gpio_en_gpio_en_6_qs; + logic gpio_en_gpio_en_6_wd; + logic gpio_en_gpio_en_6_we; + logic gpio_en_gpio_en_7_qs; + logic gpio_en_gpio_en_7_wd; + logic gpio_en_gpio_en_7_we; + logic gpio_en_gpio_en_8_qs; + logic gpio_en_gpio_en_8_wd; + logic gpio_en_gpio_en_8_we; + logic gpio_en_gpio_en_9_qs; + logic gpio_en_gpio_en_9_wd; + logic gpio_en_gpio_en_9_we; + logic gpio_en_gpio_en_10_qs; + logic gpio_en_gpio_en_10_wd; + logic gpio_en_gpio_en_10_we; + logic gpio_en_gpio_en_11_qs; + logic gpio_en_gpio_en_11_wd; + logic gpio_en_gpio_en_11_we; + logic gpio_en_gpio_en_12_qs; + logic gpio_en_gpio_en_12_wd; + logic gpio_en_gpio_en_12_we; + logic gpio_en_gpio_en_13_qs; + logic gpio_en_gpio_en_13_wd; + logic gpio_en_gpio_en_13_we; + logic gpio_en_gpio_en_14_qs; + logic gpio_en_gpio_en_14_wd; + logic gpio_en_gpio_en_14_we; + logic gpio_en_gpio_en_15_qs; + logic gpio_en_gpio_en_15_wd; + logic gpio_en_gpio_en_15_we; + logic gpio_en_gpio_en_16_qs; + logic gpio_en_gpio_en_16_wd; + logic gpio_en_gpio_en_16_we; + logic gpio_en_gpio_en_17_qs; + logic gpio_en_gpio_en_17_wd; + logic gpio_en_gpio_en_17_we; + logic gpio_en_gpio_en_18_qs; + logic gpio_en_gpio_en_18_wd; + logic gpio_en_gpio_en_18_we; + logic gpio_en_gpio_en_19_qs; + logic gpio_en_gpio_en_19_wd; + logic gpio_en_gpio_en_19_we; + logic gpio_en_gpio_en_20_qs; + logic gpio_en_gpio_en_20_wd; + logic gpio_en_gpio_en_20_we; + logic gpio_en_gpio_en_21_qs; + logic gpio_en_gpio_en_21_wd; + logic gpio_en_gpio_en_21_we; + logic gpio_en_gpio_en_22_qs; + logic gpio_en_gpio_en_22_wd; + logic gpio_en_gpio_en_22_we; + logic gpio_en_gpio_en_23_qs; + logic gpio_en_gpio_en_23_wd; + logic gpio_en_gpio_en_23_we; + logic gpio_en_gpio_en_24_qs; + logic gpio_en_gpio_en_24_wd; + logic gpio_en_gpio_en_24_we; + logic gpio_en_gpio_en_25_qs; + logic gpio_en_gpio_en_25_wd; + logic gpio_en_gpio_en_25_we; + logic gpio_en_gpio_en_26_qs; + logic gpio_en_gpio_en_26_wd; + logic gpio_en_gpio_en_26_we; + logic gpio_en_gpio_en_27_qs; + logic gpio_en_gpio_en_27_wd; + logic gpio_en_gpio_en_27_we; + logic gpio_en_gpio_en_28_qs; + logic gpio_en_gpio_en_28_wd; + logic gpio_en_gpio_en_28_we; + logic gpio_en_gpio_en_29_qs; + logic gpio_en_gpio_en_29_wd; + logic gpio_en_gpio_en_29_we; + logic gpio_en_gpio_en_30_qs; + logic gpio_en_gpio_en_30_wd; + logic gpio_en_gpio_en_30_we; + logic gpio_en_gpio_en_31_qs; + logic gpio_en_gpio_en_31_wd; + logic gpio_en_gpio_en_31_we; + logic gpio_in_gpio_in_0_qs; + logic gpio_in_gpio_in_0_re; + logic gpio_in_gpio_in_1_qs; + logic gpio_in_gpio_in_1_re; + logic gpio_in_gpio_in_2_qs; + logic gpio_in_gpio_in_2_re; + logic gpio_in_gpio_in_3_qs; + logic gpio_in_gpio_in_3_re; + logic gpio_in_gpio_in_4_qs; + logic gpio_in_gpio_in_4_re; + logic gpio_in_gpio_in_5_qs; + logic gpio_in_gpio_in_5_re; + logic gpio_in_gpio_in_6_qs; + logic gpio_in_gpio_in_6_re; + logic gpio_in_gpio_in_7_qs; + logic gpio_in_gpio_in_7_re; + logic gpio_in_gpio_in_8_qs; + logic gpio_in_gpio_in_8_re; + logic gpio_in_gpio_in_9_qs; + logic gpio_in_gpio_in_9_re; + logic gpio_in_gpio_in_10_qs; + logic gpio_in_gpio_in_10_re; + logic gpio_in_gpio_in_11_qs; + logic gpio_in_gpio_in_11_re; + logic gpio_in_gpio_in_12_qs; + logic gpio_in_gpio_in_12_re; + logic gpio_in_gpio_in_13_qs; + logic gpio_in_gpio_in_13_re; + logic gpio_in_gpio_in_14_qs; + logic gpio_in_gpio_in_14_re; + logic gpio_in_gpio_in_15_qs; + logic gpio_in_gpio_in_15_re; + logic gpio_in_gpio_in_16_qs; + logic gpio_in_gpio_in_16_re; + logic gpio_in_gpio_in_17_qs; + logic gpio_in_gpio_in_17_re; + logic gpio_in_gpio_in_18_qs; + logic gpio_in_gpio_in_18_re; + logic gpio_in_gpio_in_19_qs; + logic gpio_in_gpio_in_19_re; + logic gpio_in_gpio_in_20_qs; + logic gpio_in_gpio_in_20_re; + logic gpio_in_gpio_in_21_qs; + logic gpio_in_gpio_in_21_re; + logic gpio_in_gpio_in_22_qs; + logic gpio_in_gpio_in_22_re; + logic gpio_in_gpio_in_23_qs; + logic gpio_in_gpio_in_23_re; + logic gpio_in_gpio_in_24_qs; + logic gpio_in_gpio_in_24_re; + logic gpio_in_gpio_in_25_qs; + logic gpio_in_gpio_in_25_re; + logic gpio_in_gpio_in_26_qs; + logic gpio_in_gpio_in_26_re; + logic gpio_in_gpio_in_27_qs; + logic gpio_in_gpio_in_27_re; + logic gpio_in_gpio_in_28_qs; + logic gpio_in_gpio_in_28_re; + logic gpio_in_gpio_in_29_qs; + logic gpio_in_gpio_in_29_re; + logic gpio_in_gpio_in_30_qs; + logic gpio_in_gpio_in_30_re; + logic gpio_in_gpio_in_31_qs; + logic gpio_in_gpio_in_31_re; + logic gpio_out_gpio_out_0_qs; + logic gpio_out_gpio_out_0_wd; + logic gpio_out_gpio_out_0_we; + logic gpio_out_gpio_out_1_qs; + logic gpio_out_gpio_out_1_wd; + logic gpio_out_gpio_out_1_we; + logic gpio_out_gpio_out_2_qs; + logic gpio_out_gpio_out_2_wd; + logic gpio_out_gpio_out_2_we; + logic gpio_out_gpio_out_3_qs; + logic gpio_out_gpio_out_3_wd; + logic gpio_out_gpio_out_3_we; + logic gpio_out_gpio_out_4_qs; + logic gpio_out_gpio_out_4_wd; + logic gpio_out_gpio_out_4_we; + logic gpio_out_gpio_out_5_qs; + logic gpio_out_gpio_out_5_wd; + logic gpio_out_gpio_out_5_we; + logic gpio_out_gpio_out_6_qs; + logic gpio_out_gpio_out_6_wd; + logic gpio_out_gpio_out_6_we; + logic gpio_out_gpio_out_7_qs; + logic gpio_out_gpio_out_7_wd; + logic gpio_out_gpio_out_7_we; + logic gpio_out_gpio_out_8_qs; + logic gpio_out_gpio_out_8_wd; + logic gpio_out_gpio_out_8_we; + logic gpio_out_gpio_out_9_qs; + logic gpio_out_gpio_out_9_wd; + logic gpio_out_gpio_out_9_we; + logic gpio_out_gpio_out_10_qs; + logic gpio_out_gpio_out_10_wd; + logic gpio_out_gpio_out_10_we; + logic gpio_out_gpio_out_11_qs; + logic gpio_out_gpio_out_11_wd; + logic gpio_out_gpio_out_11_we; + logic gpio_out_gpio_out_12_qs; + logic gpio_out_gpio_out_12_wd; + logic gpio_out_gpio_out_12_we; + logic gpio_out_gpio_out_13_qs; + logic gpio_out_gpio_out_13_wd; + logic gpio_out_gpio_out_13_we; + logic gpio_out_gpio_out_14_qs; + logic gpio_out_gpio_out_14_wd; + logic gpio_out_gpio_out_14_we; + logic gpio_out_gpio_out_15_qs; + logic gpio_out_gpio_out_15_wd; + logic gpio_out_gpio_out_15_we; + logic gpio_out_gpio_out_16_qs; + logic gpio_out_gpio_out_16_wd; + logic gpio_out_gpio_out_16_we; + logic gpio_out_gpio_out_17_qs; + logic gpio_out_gpio_out_17_wd; + logic gpio_out_gpio_out_17_we; + logic gpio_out_gpio_out_18_qs; + logic gpio_out_gpio_out_18_wd; + logic gpio_out_gpio_out_18_we; + logic gpio_out_gpio_out_19_qs; + logic gpio_out_gpio_out_19_wd; + logic gpio_out_gpio_out_19_we; + logic gpio_out_gpio_out_20_qs; + logic gpio_out_gpio_out_20_wd; + logic gpio_out_gpio_out_20_we; + logic gpio_out_gpio_out_21_qs; + logic gpio_out_gpio_out_21_wd; + logic gpio_out_gpio_out_21_we; + logic gpio_out_gpio_out_22_qs; + logic gpio_out_gpio_out_22_wd; + logic gpio_out_gpio_out_22_we; + logic gpio_out_gpio_out_23_qs; + logic gpio_out_gpio_out_23_wd; + logic gpio_out_gpio_out_23_we; + logic gpio_out_gpio_out_24_qs; + logic gpio_out_gpio_out_24_wd; + logic gpio_out_gpio_out_24_we; + logic gpio_out_gpio_out_25_qs; + logic gpio_out_gpio_out_25_wd; + logic gpio_out_gpio_out_25_we; + logic gpio_out_gpio_out_26_qs; + logic gpio_out_gpio_out_26_wd; + logic gpio_out_gpio_out_26_we; + logic gpio_out_gpio_out_27_qs; + logic gpio_out_gpio_out_27_wd; + logic gpio_out_gpio_out_27_we; + logic gpio_out_gpio_out_28_qs; + logic gpio_out_gpio_out_28_wd; + logic gpio_out_gpio_out_28_we; + logic gpio_out_gpio_out_29_qs; + logic gpio_out_gpio_out_29_wd; + logic gpio_out_gpio_out_29_we; + logic gpio_out_gpio_out_30_qs; + logic gpio_out_gpio_out_30_wd; + logic gpio_out_gpio_out_30_we; + logic gpio_out_gpio_out_31_qs; + logic gpio_out_gpio_out_31_wd; + logic gpio_out_gpio_out_31_we; + logic gpio_set_gpio_set_0_wd; + logic gpio_set_gpio_set_0_we; + logic gpio_set_gpio_set_1_wd; + logic gpio_set_gpio_set_1_we; + logic gpio_set_gpio_set_2_wd; + logic gpio_set_gpio_set_2_we; + logic gpio_set_gpio_set_3_wd; + logic gpio_set_gpio_set_3_we; + logic gpio_set_gpio_set_4_wd; + logic gpio_set_gpio_set_4_we; + logic gpio_set_gpio_set_5_wd; + logic gpio_set_gpio_set_5_we; + logic gpio_set_gpio_set_6_wd; + logic gpio_set_gpio_set_6_we; + logic gpio_set_gpio_set_7_wd; + logic gpio_set_gpio_set_7_we; + logic gpio_set_gpio_set_8_wd; + logic gpio_set_gpio_set_8_we; + logic gpio_set_gpio_set_9_wd; + logic gpio_set_gpio_set_9_we; + logic gpio_set_gpio_set_10_wd; + logic gpio_set_gpio_set_10_we; + logic gpio_set_gpio_set_11_wd; + logic gpio_set_gpio_set_11_we; + logic gpio_set_gpio_set_12_wd; + logic gpio_set_gpio_set_12_we; + logic gpio_set_gpio_set_13_wd; + logic gpio_set_gpio_set_13_we; + logic gpio_set_gpio_set_14_wd; + logic gpio_set_gpio_set_14_we; + logic gpio_set_gpio_set_15_wd; + logic gpio_set_gpio_set_15_we; + logic gpio_set_gpio_set_16_wd; + logic gpio_set_gpio_set_16_we; + logic gpio_set_gpio_set_17_wd; + logic gpio_set_gpio_set_17_we; + logic gpio_set_gpio_set_18_wd; + logic gpio_set_gpio_set_18_we; + logic gpio_set_gpio_set_19_wd; + logic gpio_set_gpio_set_19_we; + logic gpio_set_gpio_set_20_wd; + logic gpio_set_gpio_set_20_we; + logic gpio_set_gpio_set_21_wd; + logic gpio_set_gpio_set_21_we; + logic gpio_set_gpio_set_22_wd; + logic gpio_set_gpio_set_22_we; + logic gpio_set_gpio_set_23_wd; + logic gpio_set_gpio_set_23_we; + logic gpio_set_gpio_set_24_wd; + logic gpio_set_gpio_set_24_we; + logic gpio_set_gpio_set_25_wd; + logic gpio_set_gpio_set_25_we; + logic gpio_set_gpio_set_26_wd; + logic gpio_set_gpio_set_26_we; + logic gpio_set_gpio_set_27_wd; + logic gpio_set_gpio_set_27_we; + logic gpio_set_gpio_set_28_wd; + logic gpio_set_gpio_set_28_we; + logic gpio_set_gpio_set_29_wd; + logic gpio_set_gpio_set_29_we; + logic gpio_set_gpio_set_30_wd; + logic gpio_set_gpio_set_30_we; + logic gpio_set_gpio_set_31_wd; + logic gpio_set_gpio_set_31_we; + logic gpio_clear_gpio_clear_0_wd; + logic gpio_clear_gpio_clear_0_we; + logic gpio_clear_gpio_clear_1_wd; + logic gpio_clear_gpio_clear_1_we; + logic gpio_clear_gpio_clear_2_wd; + logic gpio_clear_gpio_clear_2_we; + logic gpio_clear_gpio_clear_3_wd; + logic gpio_clear_gpio_clear_3_we; + logic gpio_clear_gpio_clear_4_wd; + logic gpio_clear_gpio_clear_4_we; + logic gpio_clear_gpio_clear_5_wd; + logic gpio_clear_gpio_clear_5_we; + logic gpio_clear_gpio_clear_6_wd; + logic gpio_clear_gpio_clear_6_we; + logic gpio_clear_gpio_clear_7_wd; + logic gpio_clear_gpio_clear_7_we; + logic gpio_clear_gpio_clear_8_wd; + logic gpio_clear_gpio_clear_8_we; + logic gpio_clear_gpio_clear_9_wd; + logic gpio_clear_gpio_clear_9_we; + logic gpio_clear_gpio_clear_10_wd; + logic gpio_clear_gpio_clear_10_we; + logic gpio_clear_gpio_clear_11_wd; + logic gpio_clear_gpio_clear_11_we; + logic gpio_clear_gpio_clear_12_wd; + logic gpio_clear_gpio_clear_12_we; + logic gpio_clear_gpio_clear_13_wd; + logic gpio_clear_gpio_clear_13_we; + logic gpio_clear_gpio_clear_14_wd; + logic gpio_clear_gpio_clear_14_we; + logic gpio_clear_gpio_clear_15_wd; + logic gpio_clear_gpio_clear_15_we; + logic gpio_clear_gpio_clear_16_wd; + logic gpio_clear_gpio_clear_16_we; + logic gpio_clear_gpio_clear_17_wd; + logic gpio_clear_gpio_clear_17_we; + logic gpio_clear_gpio_clear_18_wd; + logic gpio_clear_gpio_clear_18_we; + logic gpio_clear_gpio_clear_19_wd; + logic gpio_clear_gpio_clear_19_we; + logic gpio_clear_gpio_clear_20_wd; + logic gpio_clear_gpio_clear_20_we; + logic gpio_clear_gpio_clear_21_wd; + logic gpio_clear_gpio_clear_21_we; + logic gpio_clear_gpio_clear_22_wd; + logic gpio_clear_gpio_clear_22_we; + logic gpio_clear_gpio_clear_23_wd; + logic gpio_clear_gpio_clear_23_we; + logic gpio_clear_gpio_clear_24_wd; + logic gpio_clear_gpio_clear_24_we; + logic gpio_clear_gpio_clear_25_wd; + logic gpio_clear_gpio_clear_25_we; + logic gpio_clear_gpio_clear_26_wd; + logic gpio_clear_gpio_clear_26_we; + logic gpio_clear_gpio_clear_27_wd; + logic gpio_clear_gpio_clear_27_we; + logic gpio_clear_gpio_clear_28_wd; + logic gpio_clear_gpio_clear_28_we; + logic gpio_clear_gpio_clear_29_wd; + logic gpio_clear_gpio_clear_29_we; + logic gpio_clear_gpio_clear_30_wd; + logic gpio_clear_gpio_clear_30_we; + logic gpio_clear_gpio_clear_31_wd; + logic gpio_clear_gpio_clear_31_we; + logic gpio_toggle_gpio_toggle_0_wd; + logic gpio_toggle_gpio_toggle_0_we; + logic gpio_toggle_gpio_toggle_1_wd; + logic gpio_toggle_gpio_toggle_1_we; + logic gpio_toggle_gpio_toggle_2_wd; + logic gpio_toggle_gpio_toggle_2_we; + logic gpio_toggle_gpio_toggle_3_wd; + logic gpio_toggle_gpio_toggle_3_we; + logic gpio_toggle_gpio_toggle_4_wd; + logic gpio_toggle_gpio_toggle_4_we; + logic gpio_toggle_gpio_toggle_5_wd; + logic gpio_toggle_gpio_toggle_5_we; + logic gpio_toggle_gpio_toggle_6_wd; + logic gpio_toggle_gpio_toggle_6_we; + logic gpio_toggle_gpio_toggle_7_wd; + logic gpio_toggle_gpio_toggle_7_we; + logic gpio_toggle_gpio_toggle_8_wd; + logic gpio_toggle_gpio_toggle_8_we; + logic gpio_toggle_gpio_toggle_9_wd; + logic gpio_toggle_gpio_toggle_9_we; + logic gpio_toggle_gpio_toggle_10_wd; + logic gpio_toggle_gpio_toggle_10_we; + logic gpio_toggle_gpio_toggle_11_wd; + logic gpio_toggle_gpio_toggle_11_we; + logic gpio_toggle_gpio_toggle_12_wd; + logic gpio_toggle_gpio_toggle_12_we; + logic gpio_toggle_gpio_toggle_13_wd; + logic gpio_toggle_gpio_toggle_13_we; + logic gpio_toggle_gpio_toggle_14_wd; + logic gpio_toggle_gpio_toggle_14_we; + logic gpio_toggle_gpio_toggle_15_wd; + logic gpio_toggle_gpio_toggle_15_we; + logic gpio_toggle_gpio_toggle_16_wd; + logic gpio_toggle_gpio_toggle_16_we; + logic gpio_toggle_gpio_toggle_17_wd; + logic gpio_toggle_gpio_toggle_17_we; + logic gpio_toggle_gpio_toggle_18_wd; + logic gpio_toggle_gpio_toggle_18_we; + logic gpio_toggle_gpio_toggle_19_wd; + logic gpio_toggle_gpio_toggle_19_we; + logic gpio_toggle_gpio_toggle_20_wd; + logic gpio_toggle_gpio_toggle_20_we; + logic gpio_toggle_gpio_toggle_21_wd; + logic gpio_toggle_gpio_toggle_21_we; + logic gpio_toggle_gpio_toggle_22_wd; + logic gpio_toggle_gpio_toggle_22_we; + logic gpio_toggle_gpio_toggle_23_wd; + logic gpio_toggle_gpio_toggle_23_we; + logic gpio_toggle_gpio_toggle_24_wd; + logic gpio_toggle_gpio_toggle_24_we; + logic gpio_toggle_gpio_toggle_25_wd; + logic gpio_toggle_gpio_toggle_25_we; + logic gpio_toggle_gpio_toggle_26_wd; + logic gpio_toggle_gpio_toggle_26_we; + logic gpio_toggle_gpio_toggle_27_wd; + logic gpio_toggle_gpio_toggle_27_we; + logic gpio_toggle_gpio_toggle_28_wd; + logic gpio_toggle_gpio_toggle_28_we; + logic gpio_toggle_gpio_toggle_29_wd; + logic gpio_toggle_gpio_toggle_29_we; + logic gpio_toggle_gpio_toggle_30_wd; + logic gpio_toggle_gpio_toggle_30_we; + logic gpio_toggle_gpio_toggle_31_wd; + logic gpio_toggle_gpio_toggle_31_we; + logic intrpt_rise_en_intrpt_rise_en_0_qs; + logic intrpt_rise_en_intrpt_rise_en_0_wd; + logic intrpt_rise_en_intrpt_rise_en_0_we; + logic intrpt_rise_en_intrpt_rise_en_1_qs; + logic intrpt_rise_en_intrpt_rise_en_1_wd; + logic intrpt_rise_en_intrpt_rise_en_1_we; + logic intrpt_rise_en_intrpt_rise_en_2_qs; + logic intrpt_rise_en_intrpt_rise_en_2_wd; + logic intrpt_rise_en_intrpt_rise_en_2_we; + logic intrpt_rise_en_intrpt_rise_en_3_qs; + logic intrpt_rise_en_intrpt_rise_en_3_wd; + logic intrpt_rise_en_intrpt_rise_en_3_we; + logic intrpt_rise_en_intrpt_rise_en_4_qs; + logic intrpt_rise_en_intrpt_rise_en_4_wd; + logic intrpt_rise_en_intrpt_rise_en_4_we; + logic intrpt_rise_en_intrpt_rise_en_5_qs; + logic intrpt_rise_en_intrpt_rise_en_5_wd; + logic intrpt_rise_en_intrpt_rise_en_5_we; + logic intrpt_rise_en_intrpt_rise_en_6_qs; + logic intrpt_rise_en_intrpt_rise_en_6_wd; + logic intrpt_rise_en_intrpt_rise_en_6_we; + logic intrpt_rise_en_intrpt_rise_en_7_qs; + logic intrpt_rise_en_intrpt_rise_en_7_wd; + logic intrpt_rise_en_intrpt_rise_en_7_we; + logic intrpt_rise_en_intrpt_rise_en_8_qs; + logic intrpt_rise_en_intrpt_rise_en_8_wd; + logic intrpt_rise_en_intrpt_rise_en_8_we; + logic intrpt_rise_en_intrpt_rise_en_9_qs; + logic intrpt_rise_en_intrpt_rise_en_9_wd; + logic intrpt_rise_en_intrpt_rise_en_9_we; + logic intrpt_rise_en_intrpt_rise_en_10_qs; + logic intrpt_rise_en_intrpt_rise_en_10_wd; + logic intrpt_rise_en_intrpt_rise_en_10_we; + logic intrpt_rise_en_intrpt_rise_en_11_qs; + logic intrpt_rise_en_intrpt_rise_en_11_wd; + logic intrpt_rise_en_intrpt_rise_en_11_we; + logic intrpt_rise_en_intrpt_rise_en_12_qs; + logic intrpt_rise_en_intrpt_rise_en_12_wd; + logic intrpt_rise_en_intrpt_rise_en_12_we; + logic intrpt_rise_en_intrpt_rise_en_13_qs; + logic intrpt_rise_en_intrpt_rise_en_13_wd; + logic intrpt_rise_en_intrpt_rise_en_13_we; + logic intrpt_rise_en_intrpt_rise_en_14_qs; + logic intrpt_rise_en_intrpt_rise_en_14_wd; + logic intrpt_rise_en_intrpt_rise_en_14_we; + logic intrpt_rise_en_intrpt_rise_en_15_qs; + logic intrpt_rise_en_intrpt_rise_en_15_wd; + logic intrpt_rise_en_intrpt_rise_en_15_we; + logic intrpt_rise_en_intrpt_rise_en_16_qs; + logic intrpt_rise_en_intrpt_rise_en_16_wd; + logic intrpt_rise_en_intrpt_rise_en_16_we; + logic intrpt_rise_en_intrpt_rise_en_17_qs; + logic intrpt_rise_en_intrpt_rise_en_17_wd; + logic intrpt_rise_en_intrpt_rise_en_17_we; + logic intrpt_rise_en_intrpt_rise_en_18_qs; + logic intrpt_rise_en_intrpt_rise_en_18_wd; + logic intrpt_rise_en_intrpt_rise_en_18_we; + logic intrpt_rise_en_intrpt_rise_en_19_qs; + logic intrpt_rise_en_intrpt_rise_en_19_wd; + logic intrpt_rise_en_intrpt_rise_en_19_we; + logic intrpt_rise_en_intrpt_rise_en_20_qs; + logic intrpt_rise_en_intrpt_rise_en_20_wd; + logic intrpt_rise_en_intrpt_rise_en_20_we; + logic intrpt_rise_en_intrpt_rise_en_21_qs; + logic intrpt_rise_en_intrpt_rise_en_21_wd; + logic intrpt_rise_en_intrpt_rise_en_21_we; + logic intrpt_rise_en_intrpt_rise_en_22_qs; + logic intrpt_rise_en_intrpt_rise_en_22_wd; + logic intrpt_rise_en_intrpt_rise_en_22_we; + logic intrpt_rise_en_intrpt_rise_en_23_qs; + logic intrpt_rise_en_intrpt_rise_en_23_wd; + logic intrpt_rise_en_intrpt_rise_en_23_we; + logic intrpt_rise_en_intrpt_rise_en_24_qs; + logic intrpt_rise_en_intrpt_rise_en_24_wd; + logic intrpt_rise_en_intrpt_rise_en_24_we; + logic intrpt_rise_en_intrpt_rise_en_25_qs; + logic intrpt_rise_en_intrpt_rise_en_25_wd; + logic intrpt_rise_en_intrpt_rise_en_25_we; + logic intrpt_rise_en_intrpt_rise_en_26_qs; + logic intrpt_rise_en_intrpt_rise_en_26_wd; + logic intrpt_rise_en_intrpt_rise_en_26_we; + logic intrpt_rise_en_intrpt_rise_en_27_qs; + logic intrpt_rise_en_intrpt_rise_en_27_wd; + logic intrpt_rise_en_intrpt_rise_en_27_we; + logic intrpt_rise_en_intrpt_rise_en_28_qs; + logic intrpt_rise_en_intrpt_rise_en_28_wd; + logic intrpt_rise_en_intrpt_rise_en_28_we; + logic intrpt_rise_en_intrpt_rise_en_29_qs; + logic intrpt_rise_en_intrpt_rise_en_29_wd; + logic intrpt_rise_en_intrpt_rise_en_29_we; + logic intrpt_rise_en_intrpt_rise_en_30_qs; + logic intrpt_rise_en_intrpt_rise_en_30_wd; + logic intrpt_rise_en_intrpt_rise_en_30_we; + logic intrpt_rise_en_intrpt_rise_en_31_qs; + logic intrpt_rise_en_intrpt_rise_en_31_wd; + logic intrpt_rise_en_intrpt_rise_en_31_we; + logic intrpt_fall_en_intrpt_fall_en_0_qs; + logic intrpt_fall_en_intrpt_fall_en_0_wd; + logic intrpt_fall_en_intrpt_fall_en_0_we; + logic intrpt_fall_en_intrpt_fall_en_1_qs; + logic intrpt_fall_en_intrpt_fall_en_1_wd; + logic intrpt_fall_en_intrpt_fall_en_1_we; + logic intrpt_fall_en_intrpt_fall_en_2_qs; + logic intrpt_fall_en_intrpt_fall_en_2_wd; + logic intrpt_fall_en_intrpt_fall_en_2_we; + logic intrpt_fall_en_intrpt_fall_en_3_qs; + logic intrpt_fall_en_intrpt_fall_en_3_wd; + logic intrpt_fall_en_intrpt_fall_en_3_we; + logic intrpt_fall_en_intrpt_fall_en_4_qs; + logic intrpt_fall_en_intrpt_fall_en_4_wd; + logic intrpt_fall_en_intrpt_fall_en_4_we; + logic intrpt_fall_en_intrpt_fall_en_5_qs; + logic intrpt_fall_en_intrpt_fall_en_5_wd; + logic intrpt_fall_en_intrpt_fall_en_5_we; + logic intrpt_fall_en_intrpt_fall_en_6_qs; + logic intrpt_fall_en_intrpt_fall_en_6_wd; + logic intrpt_fall_en_intrpt_fall_en_6_we; + logic intrpt_fall_en_intrpt_fall_en_7_qs; + logic intrpt_fall_en_intrpt_fall_en_7_wd; + logic intrpt_fall_en_intrpt_fall_en_7_we; + logic intrpt_fall_en_intrpt_fall_en_8_qs; + logic intrpt_fall_en_intrpt_fall_en_8_wd; + logic intrpt_fall_en_intrpt_fall_en_8_we; + logic intrpt_fall_en_intrpt_fall_en_9_qs; + logic intrpt_fall_en_intrpt_fall_en_9_wd; + logic intrpt_fall_en_intrpt_fall_en_9_we; + logic intrpt_fall_en_intrpt_fall_en_10_qs; + logic intrpt_fall_en_intrpt_fall_en_10_wd; + logic intrpt_fall_en_intrpt_fall_en_10_we; + logic intrpt_fall_en_intrpt_fall_en_11_qs; + logic intrpt_fall_en_intrpt_fall_en_11_wd; + logic intrpt_fall_en_intrpt_fall_en_11_we; + logic intrpt_fall_en_intrpt_fall_en_12_qs; + logic intrpt_fall_en_intrpt_fall_en_12_wd; + logic intrpt_fall_en_intrpt_fall_en_12_we; + logic intrpt_fall_en_intrpt_fall_en_13_qs; + logic intrpt_fall_en_intrpt_fall_en_13_wd; + logic intrpt_fall_en_intrpt_fall_en_13_we; + logic intrpt_fall_en_intrpt_fall_en_14_qs; + logic intrpt_fall_en_intrpt_fall_en_14_wd; + logic intrpt_fall_en_intrpt_fall_en_14_we; + logic intrpt_fall_en_intrpt_fall_en_15_qs; + logic intrpt_fall_en_intrpt_fall_en_15_wd; + logic intrpt_fall_en_intrpt_fall_en_15_we; + logic intrpt_fall_en_intrpt_fall_en_16_qs; + logic intrpt_fall_en_intrpt_fall_en_16_wd; + logic intrpt_fall_en_intrpt_fall_en_16_we; + logic intrpt_fall_en_intrpt_fall_en_17_qs; + logic intrpt_fall_en_intrpt_fall_en_17_wd; + logic intrpt_fall_en_intrpt_fall_en_17_we; + logic intrpt_fall_en_intrpt_fall_en_18_qs; + logic intrpt_fall_en_intrpt_fall_en_18_wd; + logic intrpt_fall_en_intrpt_fall_en_18_we; + logic intrpt_fall_en_intrpt_fall_en_19_qs; + logic intrpt_fall_en_intrpt_fall_en_19_wd; + logic intrpt_fall_en_intrpt_fall_en_19_we; + logic intrpt_fall_en_intrpt_fall_en_20_qs; + logic intrpt_fall_en_intrpt_fall_en_20_wd; + logic intrpt_fall_en_intrpt_fall_en_20_we; + logic intrpt_fall_en_intrpt_fall_en_21_qs; + logic intrpt_fall_en_intrpt_fall_en_21_wd; + logic intrpt_fall_en_intrpt_fall_en_21_we; + logic intrpt_fall_en_intrpt_fall_en_22_qs; + logic intrpt_fall_en_intrpt_fall_en_22_wd; + logic intrpt_fall_en_intrpt_fall_en_22_we; + logic intrpt_fall_en_intrpt_fall_en_23_qs; + logic intrpt_fall_en_intrpt_fall_en_23_wd; + logic intrpt_fall_en_intrpt_fall_en_23_we; + logic intrpt_fall_en_intrpt_fall_en_24_qs; + logic intrpt_fall_en_intrpt_fall_en_24_wd; + logic intrpt_fall_en_intrpt_fall_en_24_we; + logic intrpt_fall_en_intrpt_fall_en_25_qs; + logic intrpt_fall_en_intrpt_fall_en_25_wd; + logic intrpt_fall_en_intrpt_fall_en_25_we; + logic intrpt_fall_en_intrpt_fall_en_26_qs; + logic intrpt_fall_en_intrpt_fall_en_26_wd; + logic intrpt_fall_en_intrpt_fall_en_26_we; + logic intrpt_fall_en_intrpt_fall_en_27_qs; + logic intrpt_fall_en_intrpt_fall_en_27_wd; + logic intrpt_fall_en_intrpt_fall_en_27_we; + logic intrpt_fall_en_intrpt_fall_en_28_qs; + logic intrpt_fall_en_intrpt_fall_en_28_wd; + logic intrpt_fall_en_intrpt_fall_en_28_we; + logic intrpt_fall_en_intrpt_fall_en_29_qs; + logic intrpt_fall_en_intrpt_fall_en_29_wd; + logic intrpt_fall_en_intrpt_fall_en_29_we; + logic intrpt_fall_en_intrpt_fall_en_30_qs; + logic intrpt_fall_en_intrpt_fall_en_30_wd; + logic intrpt_fall_en_intrpt_fall_en_30_we; + logic intrpt_fall_en_intrpt_fall_en_31_qs; + logic intrpt_fall_en_intrpt_fall_en_31_wd; + logic intrpt_fall_en_intrpt_fall_en_31_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_0_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_0_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_0_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_1_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_1_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_1_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_2_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_2_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_2_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_3_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_3_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_3_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_4_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_4_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_4_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_5_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_5_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_5_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_6_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_6_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_6_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_7_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_7_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_7_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_8_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_8_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_8_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_9_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_9_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_9_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_10_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_10_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_10_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_11_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_11_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_11_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_12_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_12_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_12_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_13_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_13_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_13_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_14_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_14_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_14_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_15_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_15_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_15_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_16_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_16_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_16_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_17_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_17_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_17_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_18_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_18_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_18_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_19_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_19_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_19_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_20_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_20_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_20_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_21_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_21_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_21_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_22_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_22_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_22_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_23_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_23_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_23_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_24_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_24_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_24_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_25_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_25_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_25_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_26_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_26_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_26_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_27_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_27_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_27_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_28_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_28_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_28_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_29_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_29_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_29_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_30_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_30_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_30_we; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_31_qs; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_31_wd; + logic intrpt_lvl_high_en_intrpt_lvl_high_en_31_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_0_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_0_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_0_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_1_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_1_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_1_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_2_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_2_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_2_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_3_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_3_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_3_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_4_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_4_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_4_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_5_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_5_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_5_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_6_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_6_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_6_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_7_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_7_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_7_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_8_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_8_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_8_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_9_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_9_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_9_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_10_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_10_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_10_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_11_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_11_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_11_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_12_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_12_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_12_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_13_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_13_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_13_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_14_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_14_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_14_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_15_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_15_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_15_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_16_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_16_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_16_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_17_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_17_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_17_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_18_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_18_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_18_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_19_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_19_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_19_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_20_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_20_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_20_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_21_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_21_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_21_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_22_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_22_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_22_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_23_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_23_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_23_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_24_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_24_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_24_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_25_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_25_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_25_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_26_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_26_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_26_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_27_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_27_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_27_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_28_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_28_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_28_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_29_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_29_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_29_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_30_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_30_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_30_we; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_31_qs; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_31_wd; + logic intrpt_lvl_low_en_intrpt_lvl_low_en_31_we; + logic intrpt_status_intrpt_status_0_qs; + logic intrpt_status_intrpt_status_0_wd; + logic intrpt_status_intrpt_status_0_we; + logic intrpt_status_intrpt_status_0_re; + logic intrpt_status_intrpt_status_1_qs; + logic intrpt_status_intrpt_status_1_wd; + logic intrpt_status_intrpt_status_1_we; + logic intrpt_status_intrpt_status_1_re; + logic intrpt_status_intrpt_status_2_qs; + logic intrpt_status_intrpt_status_2_wd; + logic intrpt_status_intrpt_status_2_we; + logic intrpt_status_intrpt_status_2_re; + logic intrpt_status_intrpt_status_3_qs; + logic intrpt_status_intrpt_status_3_wd; + logic intrpt_status_intrpt_status_3_we; + logic intrpt_status_intrpt_status_3_re; + logic intrpt_status_intrpt_status_4_qs; + logic intrpt_status_intrpt_status_4_wd; + logic intrpt_status_intrpt_status_4_we; + logic intrpt_status_intrpt_status_4_re; + logic intrpt_status_intrpt_status_5_qs; + logic intrpt_status_intrpt_status_5_wd; + logic intrpt_status_intrpt_status_5_we; + logic intrpt_status_intrpt_status_5_re; + logic intrpt_status_intrpt_status_6_qs; + logic intrpt_status_intrpt_status_6_wd; + logic intrpt_status_intrpt_status_6_we; + logic intrpt_status_intrpt_status_6_re; + logic intrpt_status_intrpt_status_7_qs; + logic intrpt_status_intrpt_status_7_wd; + logic intrpt_status_intrpt_status_7_we; + logic intrpt_status_intrpt_status_7_re; + logic intrpt_status_intrpt_status_8_qs; + logic intrpt_status_intrpt_status_8_wd; + logic intrpt_status_intrpt_status_8_we; + logic intrpt_status_intrpt_status_8_re; + logic intrpt_status_intrpt_status_9_qs; + logic intrpt_status_intrpt_status_9_wd; + logic intrpt_status_intrpt_status_9_we; + logic intrpt_status_intrpt_status_9_re; + logic intrpt_status_intrpt_status_10_qs; + logic intrpt_status_intrpt_status_10_wd; + logic intrpt_status_intrpt_status_10_we; + logic intrpt_status_intrpt_status_10_re; + logic intrpt_status_intrpt_status_11_qs; + logic intrpt_status_intrpt_status_11_wd; + logic intrpt_status_intrpt_status_11_we; + logic intrpt_status_intrpt_status_11_re; + logic intrpt_status_intrpt_status_12_qs; + logic intrpt_status_intrpt_status_12_wd; + logic intrpt_status_intrpt_status_12_we; + logic intrpt_status_intrpt_status_12_re; + logic intrpt_status_intrpt_status_13_qs; + logic intrpt_status_intrpt_status_13_wd; + logic intrpt_status_intrpt_status_13_we; + logic intrpt_status_intrpt_status_13_re; + logic intrpt_status_intrpt_status_14_qs; + logic intrpt_status_intrpt_status_14_wd; + logic intrpt_status_intrpt_status_14_we; + logic intrpt_status_intrpt_status_14_re; + logic intrpt_status_intrpt_status_15_qs; + logic intrpt_status_intrpt_status_15_wd; + logic intrpt_status_intrpt_status_15_we; + logic intrpt_status_intrpt_status_15_re; + logic intrpt_status_intrpt_status_16_qs; + logic intrpt_status_intrpt_status_16_wd; + logic intrpt_status_intrpt_status_16_we; + logic intrpt_status_intrpt_status_16_re; + logic intrpt_status_intrpt_status_17_qs; + logic intrpt_status_intrpt_status_17_wd; + logic intrpt_status_intrpt_status_17_we; + logic intrpt_status_intrpt_status_17_re; + logic intrpt_status_intrpt_status_18_qs; + logic intrpt_status_intrpt_status_18_wd; + logic intrpt_status_intrpt_status_18_we; + logic intrpt_status_intrpt_status_18_re; + logic intrpt_status_intrpt_status_19_qs; + logic intrpt_status_intrpt_status_19_wd; + logic intrpt_status_intrpt_status_19_we; + logic intrpt_status_intrpt_status_19_re; + logic intrpt_status_intrpt_status_20_qs; + logic intrpt_status_intrpt_status_20_wd; + logic intrpt_status_intrpt_status_20_we; + logic intrpt_status_intrpt_status_20_re; + logic intrpt_status_intrpt_status_21_qs; + logic intrpt_status_intrpt_status_21_wd; + logic intrpt_status_intrpt_status_21_we; + logic intrpt_status_intrpt_status_21_re; + logic intrpt_status_intrpt_status_22_qs; + logic intrpt_status_intrpt_status_22_wd; + logic intrpt_status_intrpt_status_22_we; + logic intrpt_status_intrpt_status_22_re; + logic intrpt_status_intrpt_status_23_qs; + logic intrpt_status_intrpt_status_23_wd; + logic intrpt_status_intrpt_status_23_we; + logic intrpt_status_intrpt_status_23_re; + logic intrpt_status_intrpt_status_24_qs; + logic intrpt_status_intrpt_status_24_wd; + logic intrpt_status_intrpt_status_24_we; + logic intrpt_status_intrpt_status_24_re; + logic intrpt_status_intrpt_status_25_qs; + logic intrpt_status_intrpt_status_25_wd; + logic intrpt_status_intrpt_status_25_we; + logic intrpt_status_intrpt_status_25_re; + logic intrpt_status_intrpt_status_26_qs; + logic intrpt_status_intrpt_status_26_wd; + logic intrpt_status_intrpt_status_26_we; + logic intrpt_status_intrpt_status_26_re; + logic intrpt_status_intrpt_status_27_qs; + logic intrpt_status_intrpt_status_27_wd; + logic intrpt_status_intrpt_status_27_we; + logic intrpt_status_intrpt_status_27_re; + logic intrpt_status_intrpt_status_28_qs; + logic intrpt_status_intrpt_status_28_wd; + logic intrpt_status_intrpt_status_28_we; + logic intrpt_status_intrpt_status_28_re; + logic intrpt_status_intrpt_status_29_qs; + logic intrpt_status_intrpt_status_29_wd; + logic intrpt_status_intrpt_status_29_we; + logic intrpt_status_intrpt_status_29_re; + logic intrpt_status_intrpt_status_30_qs; + logic intrpt_status_intrpt_status_30_wd; + logic intrpt_status_intrpt_status_30_we; + logic intrpt_status_intrpt_status_30_re; + logic intrpt_status_intrpt_status_31_qs; + logic intrpt_status_intrpt_status_31_wd; + logic intrpt_status_intrpt_status_31_we; + logic intrpt_status_intrpt_status_31_re; + logic intrpt_rise_status_intrpt_rise_status_0_qs; + logic intrpt_rise_status_intrpt_rise_status_0_wd; + logic intrpt_rise_status_intrpt_rise_status_0_we; + logic intrpt_rise_status_intrpt_rise_status_1_qs; + logic intrpt_rise_status_intrpt_rise_status_1_wd; + logic intrpt_rise_status_intrpt_rise_status_1_we; + logic intrpt_rise_status_intrpt_rise_status_2_qs; + logic intrpt_rise_status_intrpt_rise_status_2_wd; + logic intrpt_rise_status_intrpt_rise_status_2_we; + logic intrpt_rise_status_intrpt_rise_status_3_qs; + logic intrpt_rise_status_intrpt_rise_status_3_wd; + logic intrpt_rise_status_intrpt_rise_status_3_we; + logic intrpt_rise_status_intrpt_rise_status_4_qs; + logic intrpt_rise_status_intrpt_rise_status_4_wd; + logic intrpt_rise_status_intrpt_rise_status_4_we; + logic intrpt_rise_status_intrpt_rise_status_5_qs; + logic intrpt_rise_status_intrpt_rise_status_5_wd; + logic intrpt_rise_status_intrpt_rise_status_5_we; + logic intrpt_rise_status_intrpt_rise_status_6_qs; + logic intrpt_rise_status_intrpt_rise_status_6_wd; + logic intrpt_rise_status_intrpt_rise_status_6_we; + logic intrpt_rise_status_intrpt_rise_status_7_qs; + logic intrpt_rise_status_intrpt_rise_status_7_wd; + logic intrpt_rise_status_intrpt_rise_status_7_we; + logic intrpt_rise_status_intrpt_rise_status_8_qs; + logic intrpt_rise_status_intrpt_rise_status_8_wd; + logic intrpt_rise_status_intrpt_rise_status_8_we; + logic intrpt_rise_status_intrpt_rise_status_9_qs; + logic intrpt_rise_status_intrpt_rise_status_9_wd; + logic intrpt_rise_status_intrpt_rise_status_9_we; + logic intrpt_rise_status_intrpt_rise_status_10_qs; + logic intrpt_rise_status_intrpt_rise_status_10_wd; + logic intrpt_rise_status_intrpt_rise_status_10_we; + logic intrpt_rise_status_intrpt_rise_status_11_qs; + logic intrpt_rise_status_intrpt_rise_status_11_wd; + logic intrpt_rise_status_intrpt_rise_status_11_we; + logic intrpt_rise_status_intrpt_rise_status_12_qs; + logic intrpt_rise_status_intrpt_rise_status_12_wd; + logic intrpt_rise_status_intrpt_rise_status_12_we; + logic intrpt_rise_status_intrpt_rise_status_13_qs; + logic intrpt_rise_status_intrpt_rise_status_13_wd; + logic intrpt_rise_status_intrpt_rise_status_13_we; + logic intrpt_rise_status_intrpt_rise_status_14_qs; + logic intrpt_rise_status_intrpt_rise_status_14_wd; + logic intrpt_rise_status_intrpt_rise_status_14_we; + logic intrpt_rise_status_intrpt_rise_status_15_qs; + logic intrpt_rise_status_intrpt_rise_status_15_wd; + logic intrpt_rise_status_intrpt_rise_status_15_we; + logic intrpt_rise_status_intrpt_rise_status_16_qs; + logic intrpt_rise_status_intrpt_rise_status_16_wd; + logic intrpt_rise_status_intrpt_rise_status_16_we; + logic intrpt_rise_status_intrpt_rise_status_17_qs; + logic intrpt_rise_status_intrpt_rise_status_17_wd; + logic intrpt_rise_status_intrpt_rise_status_17_we; + logic intrpt_rise_status_intrpt_rise_status_18_qs; + logic intrpt_rise_status_intrpt_rise_status_18_wd; + logic intrpt_rise_status_intrpt_rise_status_18_we; + logic intrpt_rise_status_intrpt_rise_status_19_qs; + logic intrpt_rise_status_intrpt_rise_status_19_wd; + logic intrpt_rise_status_intrpt_rise_status_19_we; + logic intrpt_rise_status_intrpt_rise_status_20_qs; + logic intrpt_rise_status_intrpt_rise_status_20_wd; + logic intrpt_rise_status_intrpt_rise_status_20_we; + logic intrpt_rise_status_intrpt_rise_status_21_qs; + logic intrpt_rise_status_intrpt_rise_status_21_wd; + logic intrpt_rise_status_intrpt_rise_status_21_we; + logic intrpt_rise_status_intrpt_rise_status_22_qs; + logic intrpt_rise_status_intrpt_rise_status_22_wd; + logic intrpt_rise_status_intrpt_rise_status_22_we; + logic intrpt_rise_status_intrpt_rise_status_23_qs; + logic intrpt_rise_status_intrpt_rise_status_23_wd; + logic intrpt_rise_status_intrpt_rise_status_23_we; + logic intrpt_rise_status_intrpt_rise_status_24_qs; + logic intrpt_rise_status_intrpt_rise_status_24_wd; + logic intrpt_rise_status_intrpt_rise_status_24_we; + logic intrpt_rise_status_intrpt_rise_status_25_qs; + logic intrpt_rise_status_intrpt_rise_status_25_wd; + logic intrpt_rise_status_intrpt_rise_status_25_we; + logic intrpt_rise_status_intrpt_rise_status_26_qs; + logic intrpt_rise_status_intrpt_rise_status_26_wd; + logic intrpt_rise_status_intrpt_rise_status_26_we; + logic intrpt_rise_status_intrpt_rise_status_27_qs; + logic intrpt_rise_status_intrpt_rise_status_27_wd; + logic intrpt_rise_status_intrpt_rise_status_27_we; + logic intrpt_rise_status_intrpt_rise_status_28_qs; + logic intrpt_rise_status_intrpt_rise_status_28_wd; + logic intrpt_rise_status_intrpt_rise_status_28_we; + logic intrpt_rise_status_intrpt_rise_status_29_qs; + logic intrpt_rise_status_intrpt_rise_status_29_wd; + logic intrpt_rise_status_intrpt_rise_status_29_we; + logic intrpt_rise_status_intrpt_rise_status_30_qs; + logic intrpt_rise_status_intrpt_rise_status_30_wd; + logic intrpt_rise_status_intrpt_rise_status_30_we; + logic intrpt_rise_status_intrpt_rise_status_31_qs; + logic intrpt_rise_status_intrpt_rise_status_31_wd; + logic intrpt_rise_status_intrpt_rise_status_31_we; + logic intrpt_fall_status_intrpt_fall_status_0_qs; + logic intrpt_fall_status_intrpt_fall_status_0_wd; + logic intrpt_fall_status_intrpt_fall_status_0_we; + logic intrpt_fall_status_intrpt_fall_status_1_qs; + logic intrpt_fall_status_intrpt_fall_status_1_wd; + logic intrpt_fall_status_intrpt_fall_status_1_we; + logic intrpt_fall_status_intrpt_fall_status_2_qs; + logic intrpt_fall_status_intrpt_fall_status_2_wd; + logic intrpt_fall_status_intrpt_fall_status_2_we; + logic intrpt_fall_status_intrpt_fall_status_3_qs; + logic intrpt_fall_status_intrpt_fall_status_3_wd; + logic intrpt_fall_status_intrpt_fall_status_3_we; + logic intrpt_fall_status_intrpt_fall_status_4_qs; + logic intrpt_fall_status_intrpt_fall_status_4_wd; + logic intrpt_fall_status_intrpt_fall_status_4_we; + logic intrpt_fall_status_intrpt_fall_status_5_qs; + logic intrpt_fall_status_intrpt_fall_status_5_wd; + logic intrpt_fall_status_intrpt_fall_status_5_we; + logic intrpt_fall_status_intrpt_fall_status_6_qs; + logic intrpt_fall_status_intrpt_fall_status_6_wd; + logic intrpt_fall_status_intrpt_fall_status_6_we; + logic intrpt_fall_status_intrpt_fall_status_7_qs; + logic intrpt_fall_status_intrpt_fall_status_7_wd; + logic intrpt_fall_status_intrpt_fall_status_7_we; + logic intrpt_fall_status_intrpt_fall_status_8_qs; + logic intrpt_fall_status_intrpt_fall_status_8_wd; + logic intrpt_fall_status_intrpt_fall_status_8_we; + logic intrpt_fall_status_intrpt_fall_status_9_qs; + logic intrpt_fall_status_intrpt_fall_status_9_wd; + logic intrpt_fall_status_intrpt_fall_status_9_we; + logic intrpt_fall_status_intrpt_fall_status_10_qs; + logic intrpt_fall_status_intrpt_fall_status_10_wd; + logic intrpt_fall_status_intrpt_fall_status_10_we; + logic intrpt_fall_status_intrpt_fall_status_11_qs; + logic intrpt_fall_status_intrpt_fall_status_11_wd; + logic intrpt_fall_status_intrpt_fall_status_11_we; + logic intrpt_fall_status_intrpt_fall_status_12_qs; + logic intrpt_fall_status_intrpt_fall_status_12_wd; + logic intrpt_fall_status_intrpt_fall_status_12_we; + logic intrpt_fall_status_intrpt_fall_status_13_qs; + logic intrpt_fall_status_intrpt_fall_status_13_wd; + logic intrpt_fall_status_intrpt_fall_status_13_we; + logic intrpt_fall_status_intrpt_fall_status_14_qs; + logic intrpt_fall_status_intrpt_fall_status_14_wd; + logic intrpt_fall_status_intrpt_fall_status_14_we; + logic intrpt_fall_status_intrpt_fall_status_15_qs; + logic intrpt_fall_status_intrpt_fall_status_15_wd; + logic intrpt_fall_status_intrpt_fall_status_15_we; + logic intrpt_fall_status_intrpt_fall_status_16_qs; + logic intrpt_fall_status_intrpt_fall_status_16_wd; + logic intrpt_fall_status_intrpt_fall_status_16_we; + logic intrpt_fall_status_intrpt_fall_status_17_qs; + logic intrpt_fall_status_intrpt_fall_status_17_wd; + logic intrpt_fall_status_intrpt_fall_status_17_we; + logic intrpt_fall_status_intrpt_fall_status_18_qs; + logic intrpt_fall_status_intrpt_fall_status_18_wd; + logic intrpt_fall_status_intrpt_fall_status_18_we; + logic intrpt_fall_status_intrpt_fall_status_19_qs; + logic intrpt_fall_status_intrpt_fall_status_19_wd; + logic intrpt_fall_status_intrpt_fall_status_19_we; + logic intrpt_fall_status_intrpt_fall_status_20_qs; + logic intrpt_fall_status_intrpt_fall_status_20_wd; + logic intrpt_fall_status_intrpt_fall_status_20_we; + logic intrpt_fall_status_intrpt_fall_status_21_qs; + logic intrpt_fall_status_intrpt_fall_status_21_wd; + logic intrpt_fall_status_intrpt_fall_status_21_we; + logic intrpt_fall_status_intrpt_fall_status_22_qs; + logic intrpt_fall_status_intrpt_fall_status_22_wd; + logic intrpt_fall_status_intrpt_fall_status_22_we; + logic intrpt_fall_status_intrpt_fall_status_23_qs; + logic intrpt_fall_status_intrpt_fall_status_23_wd; + logic intrpt_fall_status_intrpt_fall_status_23_we; + logic intrpt_fall_status_intrpt_fall_status_24_qs; + logic intrpt_fall_status_intrpt_fall_status_24_wd; + logic intrpt_fall_status_intrpt_fall_status_24_we; + logic intrpt_fall_status_intrpt_fall_status_25_qs; + logic intrpt_fall_status_intrpt_fall_status_25_wd; + logic intrpt_fall_status_intrpt_fall_status_25_we; + logic intrpt_fall_status_intrpt_fall_status_26_qs; + logic intrpt_fall_status_intrpt_fall_status_26_wd; + logic intrpt_fall_status_intrpt_fall_status_26_we; + logic intrpt_fall_status_intrpt_fall_status_27_qs; + logic intrpt_fall_status_intrpt_fall_status_27_wd; + logic intrpt_fall_status_intrpt_fall_status_27_we; + logic intrpt_fall_status_intrpt_fall_status_28_qs; + logic intrpt_fall_status_intrpt_fall_status_28_wd; + logic intrpt_fall_status_intrpt_fall_status_28_we; + logic intrpt_fall_status_intrpt_fall_status_29_qs; + logic intrpt_fall_status_intrpt_fall_status_29_wd; + logic intrpt_fall_status_intrpt_fall_status_29_we; + logic intrpt_fall_status_intrpt_fall_status_30_qs; + logic intrpt_fall_status_intrpt_fall_status_30_wd; + logic intrpt_fall_status_intrpt_fall_status_30_we; + logic intrpt_fall_status_intrpt_fall_status_31_qs; + logic intrpt_fall_status_intrpt_fall_status_31_wd; + logic intrpt_fall_status_intrpt_fall_status_31_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_0_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_0_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_0_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_1_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_1_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_1_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_2_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_2_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_2_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_3_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_3_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_3_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_4_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_4_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_4_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_5_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_5_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_5_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_6_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_6_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_6_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_7_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_7_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_7_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_8_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_8_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_8_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_9_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_9_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_9_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_10_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_10_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_10_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_11_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_11_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_11_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_12_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_12_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_12_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_13_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_13_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_13_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_14_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_14_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_14_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_15_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_15_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_15_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_16_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_16_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_16_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_17_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_17_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_17_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_18_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_18_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_18_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_19_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_19_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_19_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_20_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_20_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_20_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_21_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_21_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_21_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_22_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_22_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_22_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_23_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_23_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_23_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_24_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_24_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_24_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_25_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_25_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_25_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_26_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_26_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_26_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_27_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_27_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_27_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_28_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_28_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_28_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_29_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_29_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_29_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_30_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_30_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_30_we; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_31_qs; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_31_wd; + logic intrpt_lvl_high_status_intrpt_lvl_high_status_31_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_0_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_0_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_0_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_1_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_1_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_1_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_2_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_2_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_2_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_3_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_3_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_3_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_4_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_4_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_4_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_5_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_5_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_5_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_6_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_6_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_6_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_7_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_7_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_7_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_8_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_8_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_8_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_9_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_9_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_9_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_10_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_10_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_10_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_11_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_11_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_11_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_12_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_12_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_12_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_13_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_13_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_13_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_14_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_14_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_14_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_15_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_15_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_15_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_16_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_16_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_16_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_17_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_17_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_17_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_18_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_18_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_18_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_19_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_19_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_19_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_20_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_20_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_20_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_21_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_21_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_21_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_22_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_22_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_22_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_23_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_23_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_23_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_24_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_24_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_24_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_25_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_25_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_25_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_26_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_26_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_26_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_27_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_27_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_27_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_28_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_28_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_28_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_29_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_29_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_29_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_30_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_30_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_30_we; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_31_qs; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_31_wd; + logic intrpt_lvl_low_status_intrpt_lvl_low_status_31_we; + + // Register instances + // R[info]: V(True) + + // F[gpio_cnt]: 9:0 + prim_subreg_ext #( + .DW (10) + ) u_info_gpio_cnt ( + .re (info_gpio_cnt_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.info.gpio_cnt.d), + .qre (), + .qe (), + .q (), + .qs (info_gpio_cnt_qs) + ); + + + // F[version]: 19:10 + prim_subreg_ext #( + .DW (10) + ) u_info_version ( + .re (info_version_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.info.version.d), + .qre (), + .qe (), + .q (), + .qs (info_version_qs) + ); + + + // R[cfg]: V(False) + + // F[intrpt_mode]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_cfg_intrpt_mode ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_intrpt_mode_we), + .wd (cfg_intrpt_mode_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg.intrpt_mode.q ), + + // to register interface (read) + .qs (cfg_intrpt_mode_qs) + ); + + + // F[reserved]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_cfg_reserved ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (cfg_reserved_we), + .wd (cfg_reserved_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.cfg.reserved.q ), + + // to register interface (read) + .qs (cfg_reserved_qs) + ); + + + + // Subregister 0 of Multireg gpio_mode + // R[gpio_mode_0]: V(False) + + // F[mode_0]: 1:0 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_0_we), + .wd (gpio_mode_0_mode_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[0].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_0_qs) + ); + + + // F[mode_1]: 3:2 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_1_we), + .wd (gpio_mode_0_mode_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[1].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_1_qs) + ); + + + // F[mode_2]: 5:4 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_2_we), + .wd (gpio_mode_0_mode_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[2].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_2_qs) + ); + + + // F[mode_3]: 7:6 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_3_we), + .wd (gpio_mode_0_mode_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[3].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_3_qs) + ); + + + // F[mode_4]: 9:8 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_4_we), + .wd (gpio_mode_0_mode_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[4].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_4_qs) + ); + + + // F[mode_5]: 11:10 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_5_we), + .wd (gpio_mode_0_mode_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[5].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_5_qs) + ); + + + // F[mode_6]: 13:12 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_6_we), + .wd (gpio_mode_0_mode_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[6].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_6_qs) + ); + + + // F[mode_7]: 15:14 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_7_we), + .wd (gpio_mode_0_mode_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[7].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_7_qs) + ); + + + // F[mode_8]: 17:16 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_8_we), + .wd (gpio_mode_0_mode_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[8].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_8_qs) + ); + + + // F[mode_9]: 19:18 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_9_we), + .wd (gpio_mode_0_mode_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[9].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_9_qs) + ); + + + // F[mode_10]: 21:20 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_10_we), + .wd (gpio_mode_0_mode_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[10].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_10_qs) + ); + + + // F[mode_11]: 23:22 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_11_we), + .wd (gpio_mode_0_mode_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[11].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_11_qs) + ); + + + // F[mode_12]: 25:24 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_12_we), + .wd (gpio_mode_0_mode_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[12].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_12_qs) + ); + + + // F[mode_13]: 27:26 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_13_we), + .wd (gpio_mode_0_mode_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[13].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_13_qs) + ); + + + // F[mode_14]: 29:28 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_14_we), + .wd (gpio_mode_0_mode_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[14].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_14_qs) + ); + + + // F[mode_15]: 31:30 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_0_mode_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_0_mode_15_we), + .wd (gpio_mode_0_mode_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[15].q ), + + // to register interface (read) + .qs (gpio_mode_0_mode_15_qs) + ); + + + // Subregister 16 of Multireg gpio_mode + // R[gpio_mode_1]: V(False) + + // F[mode_16]: 1:0 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_16_we), + .wd (gpio_mode_1_mode_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[16].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_16_qs) + ); + + + // F[mode_17]: 3:2 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_17_we), + .wd (gpio_mode_1_mode_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[17].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_17_qs) + ); + + + // F[mode_18]: 5:4 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_18_we), + .wd (gpio_mode_1_mode_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[18].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_18_qs) + ); + + + // F[mode_19]: 7:6 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_19_we), + .wd (gpio_mode_1_mode_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[19].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_19_qs) + ); + + + // F[mode_20]: 9:8 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_20_we), + .wd (gpio_mode_1_mode_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[20].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_20_qs) + ); + + + // F[mode_21]: 11:10 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_21_we), + .wd (gpio_mode_1_mode_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[21].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_21_qs) + ); + + + // F[mode_22]: 13:12 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_22_we), + .wd (gpio_mode_1_mode_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[22].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_22_qs) + ); + + + // F[mode_23]: 15:14 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_23_we), + .wd (gpio_mode_1_mode_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[23].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_23_qs) + ); + + + // F[mode_24]: 17:16 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_24_we), + .wd (gpio_mode_1_mode_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[24].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_24_qs) + ); + + + // F[mode_25]: 19:18 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_25_we), + .wd (gpio_mode_1_mode_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[25].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_25_qs) + ); + + + // F[mode_26]: 21:20 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_26_we), + .wd (gpio_mode_1_mode_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[26].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_26_qs) + ); + + + // F[mode_27]: 23:22 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_27_we), + .wd (gpio_mode_1_mode_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[27].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_27_qs) + ); + + + // F[mode_28]: 25:24 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_28_we), + .wd (gpio_mode_1_mode_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[28].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_28_qs) + ); + + + // F[mode_29]: 27:26 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_29_we), + .wd (gpio_mode_1_mode_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[29].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_29_qs) + ); + + + // F[mode_30]: 29:28 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_30_we), + .wd (gpio_mode_1_mode_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[30].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_30_qs) + ); + + + // F[mode_31]: 31:30 + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_gpio_mode_1_mode_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_mode_1_mode_31_we), + .wd (gpio_mode_1_mode_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_mode[31].q ), + + // to register interface (read) + .qs (gpio_mode_1_mode_31_qs) + ); + + + + + // Subregister 0 of Multireg gpio_en + // R[gpio_en]: V(False) + + // F[gpio_en_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_0_we), + .wd (gpio_en_gpio_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[0].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_0_qs) + ); + + + // F[gpio_en_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_1_we), + .wd (gpio_en_gpio_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[1].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_1_qs) + ); + + + // F[gpio_en_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_2_we), + .wd (gpio_en_gpio_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[2].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_2_qs) + ); + + + // F[gpio_en_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_3_we), + .wd (gpio_en_gpio_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[3].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_3_qs) + ); + + + // F[gpio_en_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_4_we), + .wd (gpio_en_gpio_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[4].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_4_qs) + ); + + + // F[gpio_en_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_5_we), + .wd (gpio_en_gpio_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[5].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_5_qs) + ); + + + // F[gpio_en_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_6_we), + .wd (gpio_en_gpio_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[6].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_6_qs) + ); + + + // F[gpio_en_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_7_we), + .wd (gpio_en_gpio_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[7].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_7_qs) + ); + + + // F[gpio_en_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_8_we), + .wd (gpio_en_gpio_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[8].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_8_qs) + ); + + + // F[gpio_en_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_9_we), + .wd (gpio_en_gpio_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[9].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_9_qs) + ); + + + // F[gpio_en_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_10_we), + .wd (gpio_en_gpio_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[10].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_10_qs) + ); + + + // F[gpio_en_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_11_we), + .wd (gpio_en_gpio_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[11].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_11_qs) + ); + + + // F[gpio_en_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_12_we), + .wd (gpio_en_gpio_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[12].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_12_qs) + ); + + + // F[gpio_en_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_13_we), + .wd (gpio_en_gpio_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[13].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_13_qs) + ); + + + // F[gpio_en_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_14_we), + .wd (gpio_en_gpio_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[14].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_14_qs) + ); + + + // F[gpio_en_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_15_we), + .wd (gpio_en_gpio_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[15].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_15_qs) + ); + + + // F[gpio_en_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_16_we), + .wd (gpio_en_gpio_en_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[16].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_16_qs) + ); + + + // F[gpio_en_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_17_we), + .wd (gpio_en_gpio_en_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[17].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_17_qs) + ); + + + // F[gpio_en_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_18_we), + .wd (gpio_en_gpio_en_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[18].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_18_qs) + ); + + + // F[gpio_en_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_19_we), + .wd (gpio_en_gpio_en_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[19].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_19_qs) + ); + + + // F[gpio_en_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_20_we), + .wd (gpio_en_gpio_en_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[20].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_20_qs) + ); + + + // F[gpio_en_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_21_we), + .wd (gpio_en_gpio_en_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[21].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_21_qs) + ); + + + // F[gpio_en_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_22_we), + .wd (gpio_en_gpio_en_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[22].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_22_qs) + ); + + + // F[gpio_en_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_23_we), + .wd (gpio_en_gpio_en_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[23].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_23_qs) + ); + + + // F[gpio_en_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_24_we), + .wd (gpio_en_gpio_en_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[24].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_24_qs) + ); + + + // F[gpio_en_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_25_we), + .wd (gpio_en_gpio_en_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[25].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_25_qs) + ); + + + // F[gpio_en_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_26_we), + .wd (gpio_en_gpio_en_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[26].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_26_qs) + ); + + + // F[gpio_en_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_27_we), + .wd (gpio_en_gpio_en_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[27].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_27_qs) + ); + + + // F[gpio_en_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_28_we), + .wd (gpio_en_gpio_en_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[28].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_28_qs) + ); + + + // F[gpio_en_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_29_we), + .wd (gpio_en_gpio_en_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[29].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_29_qs) + ); + + + // F[gpio_en_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_30_we), + .wd (gpio_en_gpio_en_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[30].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_30_qs) + ); + + + // F[gpio_en_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_en_gpio_en_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_en_gpio_en_31_we), + .wd (gpio_en_gpio_en_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_en[31].q ), + + // to register interface (read) + .qs (gpio_en_gpio_en_31_qs) + ); + + + + + // Subregister 0 of Multireg gpio_in + // R[gpio_in]: V(True) + + // F[gpio_in_0]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_0 ( + .re (gpio_in_gpio_in_0_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[0].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_0_qs) + ); + + + // F[gpio_in_1]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_1 ( + .re (gpio_in_gpio_in_1_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[1].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_1_qs) + ); + + + // F[gpio_in_2]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_2 ( + .re (gpio_in_gpio_in_2_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[2].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_2_qs) + ); + + + // F[gpio_in_3]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_3 ( + .re (gpio_in_gpio_in_3_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[3].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_3_qs) + ); + + + // F[gpio_in_4]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_4 ( + .re (gpio_in_gpio_in_4_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[4].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_4_qs) + ); + + + // F[gpio_in_5]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_5 ( + .re (gpio_in_gpio_in_5_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[5].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_5_qs) + ); + + + // F[gpio_in_6]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_6 ( + .re (gpio_in_gpio_in_6_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[6].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_6_qs) + ); + + + // F[gpio_in_7]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_7 ( + .re (gpio_in_gpio_in_7_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[7].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_7_qs) + ); + + + // F[gpio_in_8]: 8:8 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_8 ( + .re (gpio_in_gpio_in_8_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[8].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_8_qs) + ); + + + // F[gpio_in_9]: 9:9 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_9 ( + .re (gpio_in_gpio_in_9_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[9].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_9_qs) + ); + + + // F[gpio_in_10]: 10:10 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_10 ( + .re (gpio_in_gpio_in_10_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[10].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_10_qs) + ); + + + // F[gpio_in_11]: 11:11 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_11 ( + .re (gpio_in_gpio_in_11_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[11].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_11_qs) + ); + + + // F[gpio_in_12]: 12:12 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_12 ( + .re (gpio_in_gpio_in_12_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[12].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_12_qs) + ); + + + // F[gpio_in_13]: 13:13 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_13 ( + .re (gpio_in_gpio_in_13_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[13].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_13_qs) + ); + + + // F[gpio_in_14]: 14:14 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_14 ( + .re (gpio_in_gpio_in_14_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[14].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_14_qs) + ); + + + // F[gpio_in_15]: 15:15 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_15 ( + .re (gpio_in_gpio_in_15_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[15].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_15_qs) + ); + + + // F[gpio_in_16]: 16:16 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_16 ( + .re (gpio_in_gpio_in_16_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[16].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_16_qs) + ); + + + // F[gpio_in_17]: 17:17 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_17 ( + .re (gpio_in_gpio_in_17_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[17].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_17_qs) + ); + + + // F[gpio_in_18]: 18:18 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_18 ( + .re (gpio_in_gpio_in_18_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[18].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_18_qs) + ); + + + // F[gpio_in_19]: 19:19 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_19 ( + .re (gpio_in_gpio_in_19_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[19].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_19_qs) + ); + + + // F[gpio_in_20]: 20:20 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_20 ( + .re (gpio_in_gpio_in_20_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[20].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_20_qs) + ); + + + // F[gpio_in_21]: 21:21 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_21 ( + .re (gpio_in_gpio_in_21_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[21].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_21_qs) + ); + + + // F[gpio_in_22]: 22:22 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_22 ( + .re (gpio_in_gpio_in_22_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[22].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_22_qs) + ); + + + // F[gpio_in_23]: 23:23 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_23 ( + .re (gpio_in_gpio_in_23_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[23].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_23_qs) + ); + + + // F[gpio_in_24]: 24:24 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_24 ( + .re (gpio_in_gpio_in_24_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[24].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_24_qs) + ); + + + // F[gpio_in_25]: 25:25 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_25 ( + .re (gpio_in_gpio_in_25_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[25].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_25_qs) + ); + + + // F[gpio_in_26]: 26:26 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_26 ( + .re (gpio_in_gpio_in_26_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[26].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_26_qs) + ); + + + // F[gpio_in_27]: 27:27 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_27 ( + .re (gpio_in_gpio_in_27_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[27].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_27_qs) + ); + + + // F[gpio_in_28]: 28:28 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_28 ( + .re (gpio_in_gpio_in_28_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[28].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_28_qs) + ); + + + // F[gpio_in_29]: 29:29 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_29 ( + .re (gpio_in_gpio_in_29_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[29].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_29_qs) + ); + + + // F[gpio_in_30]: 30:30 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_30 ( + .re (gpio_in_gpio_in_30_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[30].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_30_qs) + ); + + + // F[gpio_in_31]: 31:31 + prim_subreg_ext #( + .DW (1) + ) u_gpio_in_gpio_in_31 ( + .re (gpio_in_gpio_in_31_re), + .we (1'b0), + .wd ('0), + .d (hw2reg.gpio_in[31].d), + .qre (), + .qe (), + .q (), + .qs (gpio_in_gpio_in_31_qs) + ); + + + + + // Subregister 0 of Multireg gpio_out + // R[gpio_out]: V(False) + + // F[gpio_out_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_0_we), + .wd (gpio_out_gpio_out_0_wd), + + // from internal hardware + .de (hw2reg.gpio_out[0].de), + .d (hw2reg.gpio_out[0].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[0].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_0_qs) + ); + + + // F[gpio_out_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_1_we), + .wd (gpio_out_gpio_out_1_wd), + + // from internal hardware + .de (hw2reg.gpio_out[1].de), + .d (hw2reg.gpio_out[1].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[1].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_1_qs) + ); + + + // F[gpio_out_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_2_we), + .wd (gpio_out_gpio_out_2_wd), + + // from internal hardware + .de (hw2reg.gpio_out[2].de), + .d (hw2reg.gpio_out[2].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[2].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_2_qs) + ); + + + // F[gpio_out_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_3_we), + .wd (gpio_out_gpio_out_3_wd), + + // from internal hardware + .de (hw2reg.gpio_out[3].de), + .d (hw2reg.gpio_out[3].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[3].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_3_qs) + ); + + + // F[gpio_out_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_4_we), + .wd (gpio_out_gpio_out_4_wd), + + // from internal hardware + .de (hw2reg.gpio_out[4].de), + .d (hw2reg.gpio_out[4].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[4].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_4_qs) + ); + + + // F[gpio_out_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_5_we), + .wd (gpio_out_gpio_out_5_wd), + + // from internal hardware + .de (hw2reg.gpio_out[5].de), + .d (hw2reg.gpio_out[5].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[5].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_5_qs) + ); + + + // F[gpio_out_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_6_we), + .wd (gpio_out_gpio_out_6_wd), + + // from internal hardware + .de (hw2reg.gpio_out[6].de), + .d (hw2reg.gpio_out[6].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[6].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_6_qs) + ); + + + // F[gpio_out_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_7_we), + .wd (gpio_out_gpio_out_7_wd), + + // from internal hardware + .de (hw2reg.gpio_out[7].de), + .d (hw2reg.gpio_out[7].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[7].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_7_qs) + ); + + + // F[gpio_out_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_8_we), + .wd (gpio_out_gpio_out_8_wd), + + // from internal hardware + .de (hw2reg.gpio_out[8].de), + .d (hw2reg.gpio_out[8].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[8].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_8_qs) + ); + + + // F[gpio_out_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_9_we), + .wd (gpio_out_gpio_out_9_wd), + + // from internal hardware + .de (hw2reg.gpio_out[9].de), + .d (hw2reg.gpio_out[9].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[9].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_9_qs) + ); + + + // F[gpio_out_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_10_we), + .wd (gpio_out_gpio_out_10_wd), + + // from internal hardware + .de (hw2reg.gpio_out[10].de), + .d (hw2reg.gpio_out[10].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[10].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_10_qs) + ); + + + // F[gpio_out_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_11_we), + .wd (gpio_out_gpio_out_11_wd), + + // from internal hardware + .de (hw2reg.gpio_out[11].de), + .d (hw2reg.gpio_out[11].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[11].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_11_qs) + ); + + + // F[gpio_out_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_12_we), + .wd (gpio_out_gpio_out_12_wd), + + // from internal hardware + .de (hw2reg.gpio_out[12].de), + .d (hw2reg.gpio_out[12].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[12].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_12_qs) + ); + + + // F[gpio_out_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_13_we), + .wd (gpio_out_gpio_out_13_wd), + + // from internal hardware + .de (hw2reg.gpio_out[13].de), + .d (hw2reg.gpio_out[13].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[13].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_13_qs) + ); + + + // F[gpio_out_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_14_we), + .wd (gpio_out_gpio_out_14_wd), + + // from internal hardware + .de (hw2reg.gpio_out[14].de), + .d (hw2reg.gpio_out[14].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[14].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_14_qs) + ); + + + // F[gpio_out_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_15_we), + .wd (gpio_out_gpio_out_15_wd), + + // from internal hardware + .de (hw2reg.gpio_out[15].de), + .d (hw2reg.gpio_out[15].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[15].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_15_qs) + ); + + + // F[gpio_out_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_16_we), + .wd (gpio_out_gpio_out_16_wd), + + // from internal hardware + .de (hw2reg.gpio_out[16].de), + .d (hw2reg.gpio_out[16].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[16].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_16_qs) + ); + + + // F[gpio_out_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_17_we), + .wd (gpio_out_gpio_out_17_wd), + + // from internal hardware + .de (hw2reg.gpio_out[17].de), + .d (hw2reg.gpio_out[17].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[17].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_17_qs) + ); + + + // F[gpio_out_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_18_we), + .wd (gpio_out_gpio_out_18_wd), + + // from internal hardware + .de (hw2reg.gpio_out[18].de), + .d (hw2reg.gpio_out[18].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[18].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_18_qs) + ); + + + // F[gpio_out_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_19_we), + .wd (gpio_out_gpio_out_19_wd), + + // from internal hardware + .de (hw2reg.gpio_out[19].de), + .d (hw2reg.gpio_out[19].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[19].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_19_qs) + ); + + + // F[gpio_out_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_20_we), + .wd (gpio_out_gpio_out_20_wd), + + // from internal hardware + .de (hw2reg.gpio_out[20].de), + .d (hw2reg.gpio_out[20].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[20].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_20_qs) + ); + + + // F[gpio_out_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_21_we), + .wd (gpio_out_gpio_out_21_wd), + + // from internal hardware + .de (hw2reg.gpio_out[21].de), + .d (hw2reg.gpio_out[21].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[21].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_21_qs) + ); + + + // F[gpio_out_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_22_we), + .wd (gpio_out_gpio_out_22_wd), + + // from internal hardware + .de (hw2reg.gpio_out[22].de), + .d (hw2reg.gpio_out[22].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[22].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_22_qs) + ); + + + // F[gpio_out_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_23_we), + .wd (gpio_out_gpio_out_23_wd), + + // from internal hardware + .de (hw2reg.gpio_out[23].de), + .d (hw2reg.gpio_out[23].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[23].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_23_qs) + ); + + + // F[gpio_out_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_24_we), + .wd (gpio_out_gpio_out_24_wd), + + // from internal hardware + .de (hw2reg.gpio_out[24].de), + .d (hw2reg.gpio_out[24].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[24].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_24_qs) + ); + + + // F[gpio_out_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_25_we), + .wd (gpio_out_gpio_out_25_wd), + + // from internal hardware + .de (hw2reg.gpio_out[25].de), + .d (hw2reg.gpio_out[25].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[25].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_25_qs) + ); + + + // F[gpio_out_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_26_we), + .wd (gpio_out_gpio_out_26_wd), + + // from internal hardware + .de (hw2reg.gpio_out[26].de), + .d (hw2reg.gpio_out[26].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[26].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_26_qs) + ); + + + // F[gpio_out_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_27_we), + .wd (gpio_out_gpio_out_27_wd), + + // from internal hardware + .de (hw2reg.gpio_out[27].de), + .d (hw2reg.gpio_out[27].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[27].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_27_qs) + ); + + + // F[gpio_out_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_28_we), + .wd (gpio_out_gpio_out_28_wd), + + // from internal hardware + .de (hw2reg.gpio_out[28].de), + .d (hw2reg.gpio_out[28].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[28].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_28_qs) + ); + + + // F[gpio_out_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_29_we), + .wd (gpio_out_gpio_out_29_wd), + + // from internal hardware + .de (hw2reg.gpio_out[29].de), + .d (hw2reg.gpio_out[29].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[29].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_29_qs) + ); + + + // F[gpio_out_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_30_we), + .wd (gpio_out_gpio_out_30_wd), + + // from internal hardware + .de (hw2reg.gpio_out[30].de), + .d (hw2reg.gpio_out[30].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[30].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_30_qs) + ); + + + // F[gpio_out_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_gpio_out_gpio_out_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (gpio_out_gpio_out_31_we), + .wd (gpio_out_gpio_out_31_wd), + + // from internal hardware + .de (hw2reg.gpio_out[31].de), + .d (hw2reg.gpio_out[31].d ), + + // to internal hardware + .qe (), + .q (reg2hw.gpio_out[31].q ), + + // to register interface (read) + .qs (gpio_out_gpio_out_31_qs) + ); + + + + + // Subregister 0 of Multireg gpio_set + // R[gpio_set]: V(True) + + // F[gpio_set_0]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_0 ( + .re (1'b0), + .we (gpio_set_gpio_set_0_we), + .wd (gpio_set_gpio_set_0_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[0].qe), + .q (reg2hw.gpio_set[0].q ), + .qs () + ); + + + // F[gpio_set_1]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_1 ( + .re (1'b0), + .we (gpio_set_gpio_set_1_we), + .wd (gpio_set_gpio_set_1_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[1].qe), + .q (reg2hw.gpio_set[1].q ), + .qs () + ); + + + // F[gpio_set_2]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_2 ( + .re (1'b0), + .we (gpio_set_gpio_set_2_we), + .wd (gpio_set_gpio_set_2_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[2].qe), + .q (reg2hw.gpio_set[2].q ), + .qs () + ); + + + // F[gpio_set_3]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_3 ( + .re (1'b0), + .we (gpio_set_gpio_set_3_we), + .wd (gpio_set_gpio_set_3_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[3].qe), + .q (reg2hw.gpio_set[3].q ), + .qs () + ); + + + // F[gpio_set_4]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_4 ( + .re (1'b0), + .we (gpio_set_gpio_set_4_we), + .wd (gpio_set_gpio_set_4_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[4].qe), + .q (reg2hw.gpio_set[4].q ), + .qs () + ); + + + // F[gpio_set_5]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_5 ( + .re (1'b0), + .we (gpio_set_gpio_set_5_we), + .wd (gpio_set_gpio_set_5_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[5].qe), + .q (reg2hw.gpio_set[5].q ), + .qs () + ); + + + // F[gpio_set_6]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_6 ( + .re (1'b0), + .we (gpio_set_gpio_set_6_we), + .wd (gpio_set_gpio_set_6_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[6].qe), + .q (reg2hw.gpio_set[6].q ), + .qs () + ); + + + // F[gpio_set_7]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_7 ( + .re (1'b0), + .we (gpio_set_gpio_set_7_we), + .wd (gpio_set_gpio_set_7_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[7].qe), + .q (reg2hw.gpio_set[7].q ), + .qs () + ); + + + // F[gpio_set_8]: 8:8 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_8 ( + .re (1'b0), + .we (gpio_set_gpio_set_8_we), + .wd (gpio_set_gpio_set_8_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[8].qe), + .q (reg2hw.gpio_set[8].q ), + .qs () + ); + + + // F[gpio_set_9]: 9:9 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_9 ( + .re (1'b0), + .we (gpio_set_gpio_set_9_we), + .wd (gpio_set_gpio_set_9_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[9].qe), + .q (reg2hw.gpio_set[9].q ), + .qs () + ); + + + // F[gpio_set_10]: 10:10 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_10 ( + .re (1'b0), + .we (gpio_set_gpio_set_10_we), + .wd (gpio_set_gpio_set_10_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[10].qe), + .q (reg2hw.gpio_set[10].q ), + .qs () + ); + + + // F[gpio_set_11]: 11:11 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_11 ( + .re (1'b0), + .we (gpio_set_gpio_set_11_we), + .wd (gpio_set_gpio_set_11_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[11].qe), + .q (reg2hw.gpio_set[11].q ), + .qs () + ); + + + // F[gpio_set_12]: 12:12 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_12 ( + .re (1'b0), + .we (gpio_set_gpio_set_12_we), + .wd (gpio_set_gpio_set_12_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[12].qe), + .q (reg2hw.gpio_set[12].q ), + .qs () + ); + + + // F[gpio_set_13]: 13:13 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_13 ( + .re (1'b0), + .we (gpio_set_gpio_set_13_we), + .wd (gpio_set_gpio_set_13_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[13].qe), + .q (reg2hw.gpio_set[13].q ), + .qs () + ); + + + // F[gpio_set_14]: 14:14 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_14 ( + .re (1'b0), + .we (gpio_set_gpio_set_14_we), + .wd (gpio_set_gpio_set_14_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[14].qe), + .q (reg2hw.gpio_set[14].q ), + .qs () + ); + + + // F[gpio_set_15]: 15:15 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_15 ( + .re (1'b0), + .we (gpio_set_gpio_set_15_we), + .wd (gpio_set_gpio_set_15_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[15].qe), + .q (reg2hw.gpio_set[15].q ), + .qs () + ); + + + // F[gpio_set_16]: 16:16 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_16 ( + .re (1'b0), + .we (gpio_set_gpio_set_16_we), + .wd (gpio_set_gpio_set_16_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[16].qe), + .q (reg2hw.gpio_set[16].q ), + .qs () + ); + + + // F[gpio_set_17]: 17:17 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_17 ( + .re (1'b0), + .we (gpio_set_gpio_set_17_we), + .wd (gpio_set_gpio_set_17_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[17].qe), + .q (reg2hw.gpio_set[17].q ), + .qs () + ); + + + // F[gpio_set_18]: 18:18 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_18 ( + .re (1'b0), + .we (gpio_set_gpio_set_18_we), + .wd (gpio_set_gpio_set_18_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[18].qe), + .q (reg2hw.gpio_set[18].q ), + .qs () + ); + + + // F[gpio_set_19]: 19:19 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_19 ( + .re (1'b0), + .we (gpio_set_gpio_set_19_we), + .wd (gpio_set_gpio_set_19_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[19].qe), + .q (reg2hw.gpio_set[19].q ), + .qs () + ); + + + // F[gpio_set_20]: 20:20 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_20 ( + .re (1'b0), + .we (gpio_set_gpio_set_20_we), + .wd (gpio_set_gpio_set_20_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[20].qe), + .q (reg2hw.gpio_set[20].q ), + .qs () + ); + + + // F[gpio_set_21]: 21:21 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_21 ( + .re (1'b0), + .we (gpio_set_gpio_set_21_we), + .wd (gpio_set_gpio_set_21_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[21].qe), + .q (reg2hw.gpio_set[21].q ), + .qs () + ); + + + // F[gpio_set_22]: 22:22 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_22 ( + .re (1'b0), + .we (gpio_set_gpio_set_22_we), + .wd (gpio_set_gpio_set_22_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[22].qe), + .q (reg2hw.gpio_set[22].q ), + .qs () + ); + + + // F[gpio_set_23]: 23:23 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_23 ( + .re (1'b0), + .we (gpio_set_gpio_set_23_we), + .wd (gpio_set_gpio_set_23_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[23].qe), + .q (reg2hw.gpio_set[23].q ), + .qs () + ); + + + // F[gpio_set_24]: 24:24 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_24 ( + .re (1'b0), + .we (gpio_set_gpio_set_24_we), + .wd (gpio_set_gpio_set_24_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[24].qe), + .q (reg2hw.gpio_set[24].q ), + .qs () + ); + + + // F[gpio_set_25]: 25:25 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_25 ( + .re (1'b0), + .we (gpio_set_gpio_set_25_we), + .wd (gpio_set_gpio_set_25_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[25].qe), + .q (reg2hw.gpio_set[25].q ), + .qs () + ); + + + // F[gpio_set_26]: 26:26 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_26 ( + .re (1'b0), + .we (gpio_set_gpio_set_26_we), + .wd (gpio_set_gpio_set_26_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[26].qe), + .q (reg2hw.gpio_set[26].q ), + .qs () + ); + + + // F[gpio_set_27]: 27:27 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_27 ( + .re (1'b0), + .we (gpio_set_gpio_set_27_we), + .wd (gpio_set_gpio_set_27_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[27].qe), + .q (reg2hw.gpio_set[27].q ), + .qs () + ); + + + // F[gpio_set_28]: 28:28 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_28 ( + .re (1'b0), + .we (gpio_set_gpio_set_28_we), + .wd (gpio_set_gpio_set_28_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[28].qe), + .q (reg2hw.gpio_set[28].q ), + .qs () + ); + + + // F[gpio_set_29]: 29:29 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_29 ( + .re (1'b0), + .we (gpio_set_gpio_set_29_we), + .wd (gpio_set_gpio_set_29_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[29].qe), + .q (reg2hw.gpio_set[29].q ), + .qs () + ); + + + // F[gpio_set_30]: 30:30 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_30 ( + .re (1'b0), + .we (gpio_set_gpio_set_30_we), + .wd (gpio_set_gpio_set_30_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[30].qe), + .q (reg2hw.gpio_set[30].q ), + .qs () + ); + + + // F[gpio_set_31]: 31:31 + prim_subreg_ext #( + .DW (1) + ) u_gpio_set_gpio_set_31 ( + .re (1'b0), + .we (gpio_set_gpio_set_31_we), + .wd (gpio_set_gpio_set_31_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_set[31].qe), + .q (reg2hw.gpio_set[31].q ), + .qs () + ); + + + + + // Subregister 0 of Multireg gpio_clear + // R[gpio_clear]: V(True) + + // F[gpio_clear_0]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_0 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_0_we), + .wd (gpio_clear_gpio_clear_0_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[0].qe), + .q (reg2hw.gpio_clear[0].q ), + .qs () + ); + + + // F[gpio_clear_1]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_1 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_1_we), + .wd (gpio_clear_gpio_clear_1_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[1].qe), + .q (reg2hw.gpio_clear[1].q ), + .qs () + ); + + + // F[gpio_clear_2]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_2 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_2_we), + .wd (gpio_clear_gpio_clear_2_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[2].qe), + .q (reg2hw.gpio_clear[2].q ), + .qs () + ); + + + // F[gpio_clear_3]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_3 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_3_we), + .wd (gpio_clear_gpio_clear_3_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[3].qe), + .q (reg2hw.gpio_clear[3].q ), + .qs () + ); + + + // F[gpio_clear_4]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_4 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_4_we), + .wd (gpio_clear_gpio_clear_4_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[4].qe), + .q (reg2hw.gpio_clear[4].q ), + .qs () + ); + + + // F[gpio_clear_5]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_5 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_5_we), + .wd (gpio_clear_gpio_clear_5_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[5].qe), + .q (reg2hw.gpio_clear[5].q ), + .qs () + ); + + + // F[gpio_clear_6]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_6 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_6_we), + .wd (gpio_clear_gpio_clear_6_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[6].qe), + .q (reg2hw.gpio_clear[6].q ), + .qs () + ); + + + // F[gpio_clear_7]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_7 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_7_we), + .wd (gpio_clear_gpio_clear_7_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[7].qe), + .q (reg2hw.gpio_clear[7].q ), + .qs () + ); + + + // F[gpio_clear_8]: 8:8 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_8 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_8_we), + .wd (gpio_clear_gpio_clear_8_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[8].qe), + .q (reg2hw.gpio_clear[8].q ), + .qs () + ); + + + // F[gpio_clear_9]: 9:9 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_9 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_9_we), + .wd (gpio_clear_gpio_clear_9_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[9].qe), + .q (reg2hw.gpio_clear[9].q ), + .qs () + ); + + + // F[gpio_clear_10]: 10:10 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_10 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_10_we), + .wd (gpio_clear_gpio_clear_10_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[10].qe), + .q (reg2hw.gpio_clear[10].q ), + .qs () + ); + + + // F[gpio_clear_11]: 11:11 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_11 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_11_we), + .wd (gpio_clear_gpio_clear_11_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[11].qe), + .q (reg2hw.gpio_clear[11].q ), + .qs () + ); + + + // F[gpio_clear_12]: 12:12 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_12 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_12_we), + .wd (gpio_clear_gpio_clear_12_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[12].qe), + .q (reg2hw.gpio_clear[12].q ), + .qs () + ); + + + // F[gpio_clear_13]: 13:13 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_13 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_13_we), + .wd (gpio_clear_gpio_clear_13_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[13].qe), + .q (reg2hw.gpio_clear[13].q ), + .qs () + ); + + + // F[gpio_clear_14]: 14:14 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_14 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_14_we), + .wd (gpio_clear_gpio_clear_14_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[14].qe), + .q (reg2hw.gpio_clear[14].q ), + .qs () + ); + + + // F[gpio_clear_15]: 15:15 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_15 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_15_we), + .wd (gpio_clear_gpio_clear_15_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[15].qe), + .q (reg2hw.gpio_clear[15].q ), + .qs () + ); + + + // F[gpio_clear_16]: 16:16 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_16 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_16_we), + .wd (gpio_clear_gpio_clear_16_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[16].qe), + .q (reg2hw.gpio_clear[16].q ), + .qs () + ); + + + // F[gpio_clear_17]: 17:17 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_17 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_17_we), + .wd (gpio_clear_gpio_clear_17_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[17].qe), + .q (reg2hw.gpio_clear[17].q ), + .qs () + ); + + + // F[gpio_clear_18]: 18:18 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_18 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_18_we), + .wd (gpio_clear_gpio_clear_18_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[18].qe), + .q (reg2hw.gpio_clear[18].q ), + .qs () + ); + + + // F[gpio_clear_19]: 19:19 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_19 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_19_we), + .wd (gpio_clear_gpio_clear_19_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[19].qe), + .q (reg2hw.gpio_clear[19].q ), + .qs () + ); + + + // F[gpio_clear_20]: 20:20 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_20 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_20_we), + .wd (gpio_clear_gpio_clear_20_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[20].qe), + .q (reg2hw.gpio_clear[20].q ), + .qs () + ); + + + // F[gpio_clear_21]: 21:21 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_21 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_21_we), + .wd (gpio_clear_gpio_clear_21_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[21].qe), + .q (reg2hw.gpio_clear[21].q ), + .qs () + ); + + + // F[gpio_clear_22]: 22:22 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_22 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_22_we), + .wd (gpio_clear_gpio_clear_22_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[22].qe), + .q (reg2hw.gpio_clear[22].q ), + .qs () + ); + + + // F[gpio_clear_23]: 23:23 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_23 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_23_we), + .wd (gpio_clear_gpio_clear_23_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[23].qe), + .q (reg2hw.gpio_clear[23].q ), + .qs () + ); + + + // F[gpio_clear_24]: 24:24 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_24 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_24_we), + .wd (gpio_clear_gpio_clear_24_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[24].qe), + .q (reg2hw.gpio_clear[24].q ), + .qs () + ); + + + // F[gpio_clear_25]: 25:25 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_25 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_25_we), + .wd (gpio_clear_gpio_clear_25_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[25].qe), + .q (reg2hw.gpio_clear[25].q ), + .qs () + ); + + + // F[gpio_clear_26]: 26:26 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_26 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_26_we), + .wd (gpio_clear_gpio_clear_26_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[26].qe), + .q (reg2hw.gpio_clear[26].q ), + .qs () + ); + + + // F[gpio_clear_27]: 27:27 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_27 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_27_we), + .wd (gpio_clear_gpio_clear_27_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[27].qe), + .q (reg2hw.gpio_clear[27].q ), + .qs () + ); + + + // F[gpio_clear_28]: 28:28 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_28 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_28_we), + .wd (gpio_clear_gpio_clear_28_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[28].qe), + .q (reg2hw.gpio_clear[28].q ), + .qs () + ); + + + // F[gpio_clear_29]: 29:29 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_29 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_29_we), + .wd (gpio_clear_gpio_clear_29_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[29].qe), + .q (reg2hw.gpio_clear[29].q ), + .qs () + ); + + + // F[gpio_clear_30]: 30:30 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_30 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_30_we), + .wd (gpio_clear_gpio_clear_30_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[30].qe), + .q (reg2hw.gpio_clear[30].q ), + .qs () + ); + + + // F[gpio_clear_31]: 31:31 + prim_subreg_ext #( + .DW (1) + ) u_gpio_clear_gpio_clear_31 ( + .re (1'b0), + .we (gpio_clear_gpio_clear_31_we), + .wd (gpio_clear_gpio_clear_31_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_clear[31].qe), + .q (reg2hw.gpio_clear[31].q ), + .qs () + ); + + + + + // Subregister 0 of Multireg gpio_toggle + // R[gpio_toggle]: V(True) + + // F[gpio_toggle_0]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_0 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_0_we), + .wd (gpio_toggle_gpio_toggle_0_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[0].qe), + .q (reg2hw.gpio_toggle[0].q ), + .qs () + ); + + + // F[gpio_toggle_1]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_1 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_1_we), + .wd (gpio_toggle_gpio_toggle_1_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[1].qe), + .q (reg2hw.gpio_toggle[1].q ), + .qs () + ); + + + // F[gpio_toggle_2]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_2 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_2_we), + .wd (gpio_toggle_gpio_toggle_2_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[2].qe), + .q (reg2hw.gpio_toggle[2].q ), + .qs () + ); + + + // F[gpio_toggle_3]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_3 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_3_we), + .wd (gpio_toggle_gpio_toggle_3_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[3].qe), + .q (reg2hw.gpio_toggle[3].q ), + .qs () + ); + + + // F[gpio_toggle_4]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_4 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_4_we), + .wd (gpio_toggle_gpio_toggle_4_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[4].qe), + .q (reg2hw.gpio_toggle[4].q ), + .qs () + ); + + + // F[gpio_toggle_5]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_5 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_5_we), + .wd (gpio_toggle_gpio_toggle_5_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[5].qe), + .q (reg2hw.gpio_toggle[5].q ), + .qs () + ); + + + // F[gpio_toggle_6]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_6 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_6_we), + .wd (gpio_toggle_gpio_toggle_6_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[6].qe), + .q (reg2hw.gpio_toggle[6].q ), + .qs () + ); + + + // F[gpio_toggle_7]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_7 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_7_we), + .wd (gpio_toggle_gpio_toggle_7_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[7].qe), + .q (reg2hw.gpio_toggle[7].q ), + .qs () + ); + + + // F[gpio_toggle_8]: 8:8 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_8 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_8_we), + .wd (gpio_toggle_gpio_toggle_8_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[8].qe), + .q (reg2hw.gpio_toggle[8].q ), + .qs () + ); + + + // F[gpio_toggle_9]: 9:9 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_9 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_9_we), + .wd (gpio_toggle_gpio_toggle_9_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[9].qe), + .q (reg2hw.gpio_toggle[9].q ), + .qs () + ); + + + // F[gpio_toggle_10]: 10:10 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_10 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_10_we), + .wd (gpio_toggle_gpio_toggle_10_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[10].qe), + .q (reg2hw.gpio_toggle[10].q ), + .qs () + ); + + + // F[gpio_toggle_11]: 11:11 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_11 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_11_we), + .wd (gpio_toggle_gpio_toggle_11_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[11].qe), + .q (reg2hw.gpio_toggle[11].q ), + .qs () + ); + + + // F[gpio_toggle_12]: 12:12 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_12 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_12_we), + .wd (gpio_toggle_gpio_toggle_12_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[12].qe), + .q (reg2hw.gpio_toggle[12].q ), + .qs () + ); + + + // F[gpio_toggle_13]: 13:13 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_13 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_13_we), + .wd (gpio_toggle_gpio_toggle_13_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[13].qe), + .q (reg2hw.gpio_toggle[13].q ), + .qs () + ); + + + // F[gpio_toggle_14]: 14:14 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_14 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_14_we), + .wd (gpio_toggle_gpio_toggle_14_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[14].qe), + .q (reg2hw.gpio_toggle[14].q ), + .qs () + ); + + + // F[gpio_toggle_15]: 15:15 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_15 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_15_we), + .wd (gpio_toggle_gpio_toggle_15_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[15].qe), + .q (reg2hw.gpio_toggle[15].q ), + .qs () + ); + + + // F[gpio_toggle_16]: 16:16 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_16 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_16_we), + .wd (gpio_toggle_gpio_toggle_16_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[16].qe), + .q (reg2hw.gpio_toggle[16].q ), + .qs () + ); + + + // F[gpio_toggle_17]: 17:17 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_17 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_17_we), + .wd (gpio_toggle_gpio_toggle_17_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[17].qe), + .q (reg2hw.gpio_toggle[17].q ), + .qs () + ); + + + // F[gpio_toggle_18]: 18:18 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_18 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_18_we), + .wd (gpio_toggle_gpio_toggle_18_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[18].qe), + .q (reg2hw.gpio_toggle[18].q ), + .qs () + ); + + + // F[gpio_toggle_19]: 19:19 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_19 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_19_we), + .wd (gpio_toggle_gpio_toggle_19_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[19].qe), + .q (reg2hw.gpio_toggle[19].q ), + .qs () + ); + + + // F[gpio_toggle_20]: 20:20 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_20 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_20_we), + .wd (gpio_toggle_gpio_toggle_20_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[20].qe), + .q (reg2hw.gpio_toggle[20].q ), + .qs () + ); + + + // F[gpio_toggle_21]: 21:21 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_21 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_21_we), + .wd (gpio_toggle_gpio_toggle_21_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[21].qe), + .q (reg2hw.gpio_toggle[21].q ), + .qs () + ); + + + // F[gpio_toggle_22]: 22:22 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_22 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_22_we), + .wd (gpio_toggle_gpio_toggle_22_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[22].qe), + .q (reg2hw.gpio_toggle[22].q ), + .qs () + ); + + + // F[gpio_toggle_23]: 23:23 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_23 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_23_we), + .wd (gpio_toggle_gpio_toggle_23_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[23].qe), + .q (reg2hw.gpio_toggle[23].q ), + .qs () + ); + + + // F[gpio_toggle_24]: 24:24 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_24 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_24_we), + .wd (gpio_toggle_gpio_toggle_24_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[24].qe), + .q (reg2hw.gpio_toggle[24].q ), + .qs () + ); + + + // F[gpio_toggle_25]: 25:25 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_25 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_25_we), + .wd (gpio_toggle_gpio_toggle_25_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[25].qe), + .q (reg2hw.gpio_toggle[25].q ), + .qs () + ); + + + // F[gpio_toggle_26]: 26:26 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_26 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_26_we), + .wd (gpio_toggle_gpio_toggle_26_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[26].qe), + .q (reg2hw.gpio_toggle[26].q ), + .qs () + ); + + + // F[gpio_toggle_27]: 27:27 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_27 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_27_we), + .wd (gpio_toggle_gpio_toggle_27_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[27].qe), + .q (reg2hw.gpio_toggle[27].q ), + .qs () + ); + + + // F[gpio_toggle_28]: 28:28 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_28 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_28_we), + .wd (gpio_toggle_gpio_toggle_28_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[28].qe), + .q (reg2hw.gpio_toggle[28].q ), + .qs () + ); + + + // F[gpio_toggle_29]: 29:29 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_29 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_29_we), + .wd (gpio_toggle_gpio_toggle_29_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[29].qe), + .q (reg2hw.gpio_toggle[29].q ), + .qs () + ); + + + // F[gpio_toggle_30]: 30:30 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_30 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_30_we), + .wd (gpio_toggle_gpio_toggle_30_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[30].qe), + .q (reg2hw.gpio_toggle[30].q ), + .qs () + ); + + + // F[gpio_toggle_31]: 31:31 + prim_subreg_ext #( + .DW (1) + ) u_gpio_toggle_gpio_toggle_31 ( + .re (1'b0), + .we (gpio_toggle_gpio_toggle_31_we), + .wd (gpio_toggle_gpio_toggle_31_wd), + .d ('0), + .qre (), + .qe (reg2hw.gpio_toggle[31].qe), + .q (reg2hw.gpio_toggle[31].q ), + .qs () + ); + + + + + // Subregister 0 of Multireg intrpt_rise_en + // R[intrpt_rise_en]: V(False) + + // F[intrpt_rise_en_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_0_we), + .wd (intrpt_rise_en_intrpt_rise_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[0].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_0_qs) + ); + + + // F[intrpt_rise_en_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_1_we), + .wd (intrpt_rise_en_intrpt_rise_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[1].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_1_qs) + ); + + + // F[intrpt_rise_en_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_2_we), + .wd (intrpt_rise_en_intrpt_rise_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[2].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_2_qs) + ); + + + // F[intrpt_rise_en_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_3_we), + .wd (intrpt_rise_en_intrpt_rise_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[3].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_3_qs) + ); + + + // F[intrpt_rise_en_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_4_we), + .wd (intrpt_rise_en_intrpt_rise_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[4].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_4_qs) + ); + + + // F[intrpt_rise_en_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_5_we), + .wd (intrpt_rise_en_intrpt_rise_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[5].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_5_qs) + ); + + + // F[intrpt_rise_en_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_6_we), + .wd (intrpt_rise_en_intrpt_rise_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[6].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_6_qs) + ); + + + // F[intrpt_rise_en_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_7_we), + .wd (intrpt_rise_en_intrpt_rise_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[7].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_7_qs) + ); + + + // F[intrpt_rise_en_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_8_we), + .wd (intrpt_rise_en_intrpt_rise_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[8].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_8_qs) + ); + + + // F[intrpt_rise_en_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_9_we), + .wd (intrpt_rise_en_intrpt_rise_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[9].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_9_qs) + ); + + + // F[intrpt_rise_en_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_10_we), + .wd (intrpt_rise_en_intrpt_rise_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[10].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_10_qs) + ); + + + // F[intrpt_rise_en_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_11_we), + .wd (intrpt_rise_en_intrpt_rise_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[11].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_11_qs) + ); + + + // F[intrpt_rise_en_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_12_we), + .wd (intrpt_rise_en_intrpt_rise_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[12].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_12_qs) + ); + + + // F[intrpt_rise_en_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_13_we), + .wd (intrpt_rise_en_intrpt_rise_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[13].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_13_qs) + ); + + + // F[intrpt_rise_en_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_14_we), + .wd (intrpt_rise_en_intrpt_rise_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[14].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_14_qs) + ); + + + // F[intrpt_rise_en_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_15_we), + .wd (intrpt_rise_en_intrpt_rise_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[15].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_15_qs) + ); + + + // F[intrpt_rise_en_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_16_we), + .wd (intrpt_rise_en_intrpt_rise_en_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[16].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_16_qs) + ); + + + // F[intrpt_rise_en_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_17_we), + .wd (intrpt_rise_en_intrpt_rise_en_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[17].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_17_qs) + ); + + + // F[intrpt_rise_en_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_18_we), + .wd (intrpt_rise_en_intrpt_rise_en_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[18].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_18_qs) + ); + + + // F[intrpt_rise_en_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_19_we), + .wd (intrpt_rise_en_intrpt_rise_en_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[19].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_19_qs) + ); + + + // F[intrpt_rise_en_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_20_we), + .wd (intrpt_rise_en_intrpt_rise_en_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[20].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_20_qs) + ); + + + // F[intrpt_rise_en_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_21_we), + .wd (intrpt_rise_en_intrpt_rise_en_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[21].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_21_qs) + ); + + + // F[intrpt_rise_en_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_22_we), + .wd (intrpt_rise_en_intrpt_rise_en_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[22].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_22_qs) + ); + + + // F[intrpt_rise_en_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_23_we), + .wd (intrpt_rise_en_intrpt_rise_en_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[23].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_23_qs) + ); + + + // F[intrpt_rise_en_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_24_we), + .wd (intrpt_rise_en_intrpt_rise_en_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[24].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_24_qs) + ); + + + // F[intrpt_rise_en_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_25_we), + .wd (intrpt_rise_en_intrpt_rise_en_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[25].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_25_qs) + ); + + + // F[intrpt_rise_en_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_26_we), + .wd (intrpt_rise_en_intrpt_rise_en_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[26].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_26_qs) + ); + + + // F[intrpt_rise_en_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_27_we), + .wd (intrpt_rise_en_intrpt_rise_en_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[27].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_27_qs) + ); + + + // F[intrpt_rise_en_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_28_we), + .wd (intrpt_rise_en_intrpt_rise_en_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[28].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_28_qs) + ); + + + // F[intrpt_rise_en_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_29_we), + .wd (intrpt_rise_en_intrpt_rise_en_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[29].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_29_qs) + ); + + + // F[intrpt_rise_en_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_30_we), + .wd (intrpt_rise_en_intrpt_rise_en_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[30].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_30_qs) + ); + + + // F[intrpt_rise_en_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_rise_en_intrpt_rise_en_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_en_intrpt_rise_en_31_we), + .wd (intrpt_rise_en_intrpt_rise_en_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_en[31].q ), + + // to register interface (read) + .qs (intrpt_rise_en_intrpt_rise_en_31_qs) + ); + + + + + // Subregister 0 of Multireg intrpt_fall_en + // R[intrpt_fall_en]: V(False) + + // F[intrpt_fall_en_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_0_we), + .wd (intrpt_fall_en_intrpt_fall_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[0].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_0_qs) + ); + + + // F[intrpt_fall_en_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_1_we), + .wd (intrpt_fall_en_intrpt_fall_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[1].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_1_qs) + ); + + + // F[intrpt_fall_en_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_2_we), + .wd (intrpt_fall_en_intrpt_fall_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[2].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_2_qs) + ); + + + // F[intrpt_fall_en_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_3_we), + .wd (intrpt_fall_en_intrpt_fall_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[3].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_3_qs) + ); + + + // F[intrpt_fall_en_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_4_we), + .wd (intrpt_fall_en_intrpt_fall_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[4].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_4_qs) + ); + + + // F[intrpt_fall_en_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_5_we), + .wd (intrpt_fall_en_intrpt_fall_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[5].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_5_qs) + ); + + + // F[intrpt_fall_en_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_6_we), + .wd (intrpt_fall_en_intrpt_fall_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[6].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_6_qs) + ); + + + // F[intrpt_fall_en_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_7_we), + .wd (intrpt_fall_en_intrpt_fall_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[7].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_7_qs) + ); + + + // F[intrpt_fall_en_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_8_we), + .wd (intrpt_fall_en_intrpt_fall_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[8].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_8_qs) + ); + + + // F[intrpt_fall_en_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_9_we), + .wd (intrpt_fall_en_intrpt_fall_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[9].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_9_qs) + ); + + + // F[intrpt_fall_en_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_10_we), + .wd (intrpt_fall_en_intrpt_fall_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[10].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_10_qs) + ); + + + // F[intrpt_fall_en_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_11_we), + .wd (intrpt_fall_en_intrpt_fall_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[11].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_11_qs) + ); + + + // F[intrpt_fall_en_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_12_we), + .wd (intrpt_fall_en_intrpt_fall_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[12].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_12_qs) + ); + + + // F[intrpt_fall_en_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_13_we), + .wd (intrpt_fall_en_intrpt_fall_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[13].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_13_qs) + ); + + + // F[intrpt_fall_en_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_14_we), + .wd (intrpt_fall_en_intrpt_fall_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[14].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_14_qs) + ); + + + // F[intrpt_fall_en_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_15_we), + .wd (intrpt_fall_en_intrpt_fall_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[15].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_15_qs) + ); + + + // F[intrpt_fall_en_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_16_we), + .wd (intrpt_fall_en_intrpt_fall_en_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[16].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_16_qs) + ); + + + // F[intrpt_fall_en_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_17_we), + .wd (intrpt_fall_en_intrpt_fall_en_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[17].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_17_qs) + ); + + + // F[intrpt_fall_en_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_18_we), + .wd (intrpt_fall_en_intrpt_fall_en_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[18].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_18_qs) + ); + + + // F[intrpt_fall_en_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_19_we), + .wd (intrpt_fall_en_intrpt_fall_en_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[19].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_19_qs) + ); + + + // F[intrpt_fall_en_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_20_we), + .wd (intrpt_fall_en_intrpt_fall_en_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[20].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_20_qs) + ); + + + // F[intrpt_fall_en_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_21_we), + .wd (intrpt_fall_en_intrpt_fall_en_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[21].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_21_qs) + ); + + + // F[intrpt_fall_en_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_22_we), + .wd (intrpt_fall_en_intrpt_fall_en_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[22].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_22_qs) + ); + + + // F[intrpt_fall_en_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_23_we), + .wd (intrpt_fall_en_intrpt_fall_en_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[23].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_23_qs) + ); + + + // F[intrpt_fall_en_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_24_we), + .wd (intrpt_fall_en_intrpt_fall_en_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[24].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_24_qs) + ); + + + // F[intrpt_fall_en_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_25_we), + .wd (intrpt_fall_en_intrpt_fall_en_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[25].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_25_qs) + ); + + + // F[intrpt_fall_en_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_26_we), + .wd (intrpt_fall_en_intrpt_fall_en_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[26].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_26_qs) + ); + + + // F[intrpt_fall_en_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_27_we), + .wd (intrpt_fall_en_intrpt_fall_en_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[27].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_27_qs) + ); + + + // F[intrpt_fall_en_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_28_we), + .wd (intrpt_fall_en_intrpt_fall_en_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[28].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_28_qs) + ); + + + // F[intrpt_fall_en_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_29_we), + .wd (intrpt_fall_en_intrpt_fall_en_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[29].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_29_qs) + ); + + + // F[intrpt_fall_en_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_30_we), + .wd (intrpt_fall_en_intrpt_fall_en_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[30].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_30_qs) + ); + + + // F[intrpt_fall_en_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_fall_en_intrpt_fall_en_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_en_intrpt_fall_en_31_we), + .wd (intrpt_fall_en_intrpt_fall_en_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_en[31].q ), + + // to register interface (read) + .qs (intrpt_fall_en_intrpt_fall_en_31_qs) + ); + + + + + // Subregister 0 of Multireg intrpt_lvl_high_en + // R[intrpt_lvl_high_en]: V(False) + + // F[intrpt_lvl_high_en_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_0_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[0].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_0_qs) + ); + + + // F[intrpt_lvl_high_en_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_1_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[1].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_1_qs) + ); + + + // F[intrpt_lvl_high_en_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_2_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[2].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_2_qs) + ); + + + // F[intrpt_lvl_high_en_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_3_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[3].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_3_qs) + ); + + + // F[intrpt_lvl_high_en_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_4_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[4].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_4_qs) + ); + + + // F[intrpt_lvl_high_en_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_5_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[5].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_5_qs) + ); + + + // F[intrpt_lvl_high_en_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_6_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[6].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_6_qs) + ); + + + // F[intrpt_lvl_high_en_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_7_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[7].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_7_qs) + ); + + + // F[intrpt_lvl_high_en_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_8_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[8].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_8_qs) + ); + + + // F[intrpt_lvl_high_en_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_9_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[9].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_9_qs) + ); + + + // F[intrpt_lvl_high_en_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_10_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[10].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_10_qs) + ); + + + // F[intrpt_lvl_high_en_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_11_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[11].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_11_qs) + ); + + + // F[intrpt_lvl_high_en_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_12_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[12].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_12_qs) + ); + + + // F[intrpt_lvl_high_en_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_13_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[13].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_13_qs) + ); + + + // F[intrpt_lvl_high_en_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_14_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[14].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_14_qs) + ); + + + // F[intrpt_lvl_high_en_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_15_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[15].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_15_qs) + ); + + + // F[intrpt_lvl_high_en_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_16_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[16].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_16_qs) + ); + + + // F[intrpt_lvl_high_en_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_17_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[17].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_17_qs) + ); + + + // F[intrpt_lvl_high_en_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_18_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[18].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_18_qs) + ); + + + // F[intrpt_lvl_high_en_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_19_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[19].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_19_qs) + ); + + + // F[intrpt_lvl_high_en_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_20_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[20].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_20_qs) + ); + + + // F[intrpt_lvl_high_en_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_21_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[21].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_21_qs) + ); + + + // F[intrpt_lvl_high_en_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_22_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[22].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_22_qs) + ); + + + // F[intrpt_lvl_high_en_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_23_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[23].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_23_qs) + ); + + + // F[intrpt_lvl_high_en_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_24_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[24].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_24_qs) + ); + + + // F[intrpt_lvl_high_en_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_25_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[25].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_25_qs) + ); + + + // F[intrpt_lvl_high_en_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_26_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[26].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_26_qs) + ); + + + // F[intrpt_lvl_high_en_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_27_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[27].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_27_qs) + ); + + + // F[intrpt_lvl_high_en_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_28_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[28].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_28_qs) + ); + + + // F[intrpt_lvl_high_en_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_29_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[29].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_29_qs) + ); + + + // F[intrpt_lvl_high_en_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_30_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[30].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_30_qs) + ); + + + // F[intrpt_lvl_high_en_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_en_intrpt_lvl_high_en_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_en_intrpt_lvl_high_en_31_we), + .wd (intrpt_lvl_high_en_intrpt_lvl_high_en_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_en[31].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_en_intrpt_lvl_high_en_31_qs) + ); + + + + + // Subregister 0 of Multireg intrpt_lvl_low_en + // R[intrpt_lvl_low_en]: V(False) + + // F[intrpt_lvl_low_en_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_0_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_0_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[0].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_0_qs) + ); + + + // F[intrpt_lvl_low_en_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_1_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_1_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[1].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_1_qs) + ); + + + // F[intrpt_lvl_low_en_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_2_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_2_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[2].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_2_qs) + ); + + + // F[intrpt_lvl_low_en_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_3_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_3_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[3].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_3_qs) + ); + + + // F[intrpt_lvl_low_en_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_4_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_4_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[4].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_4_qs) + ); + + + // F[intrpt_lvl_low_en_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_5_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_5_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[5].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_5_qs) + ); + + + // F[intrpt_lvl_low_en_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_6_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_6_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[6].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_6_qs) + ); + + + // F[intrpt_lvl_low_en_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_7_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_7_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[7].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_7_qs) + ); + + + // F[intrpt_lvl_low_en_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_8_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_8_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[8].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_8_qs) + ); + + + // F[intrpt_lvl_low_en_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_9_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_9_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[9].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_9_qs) + ); + + + // F[intrpt_lvl_low_en_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_10_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_10_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[10].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_10_qs) + ); + + + // F[intrpt_lvl_low_en_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_11_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_11_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[11].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_11_qs) + ); + + + // F[intrpt_lvl_low_en_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_12_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_12_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[12].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_12_qs) + ); + + + // F[intrpt_lvl_low_en_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_13_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_13_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[13].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_13_qs) + ); + + + // F[intrpt_lvl_low_en_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_14_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_14_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[14].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_14_qs) + ); + + + // F[intrpt_lvl_low_en_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_15_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_15_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[15].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_15_qs) + ); + + + // F[intrpt_lvl_low_en_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_16_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_16_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[16].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_16_qs) + ); + + + // F[intrpt_lvl_low_en_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_17_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_17_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[17].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_17_qs) + ); + + + // F[intrpt_lvl_low_en_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_18_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_18_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[18].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_18_qs) + ); + + + // F[intrpt_lvl_low_en_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_19_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_19_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[19].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_19_qs) + ); + + + // F[intrpt_lvl_low_en_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_20_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_20_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[20].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_20_qs) + ); + + + // F[intrpt_lvl_low_en_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_21_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_21_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[21].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_21_qs) + ); + + + // F[intrpt_lvl_low_en_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_22_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_22_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[22].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_22_qs) + ); + + + // F[intrpt_lvl_low_en_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_23_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_23_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[23].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_23_qs) + ); + + + // F[intrpt_lvl_low_en_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_24_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_24_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[24].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_24_qs) + ); + + + // F[intrpt_lvl_low_en_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_25_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_25_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[25].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_25_qs) + ); + + + // F[intrpt_lvl_low_en_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_26_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_26_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[26].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_26_qs) + ); + + + // F[intrpt_lvl_low_en_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_27_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_27_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[27].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_27_qs) + ); + + + // F[intrpt_lvl_low_en_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_28_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_28_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[28].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_28_qs) + ); + + + // F[intrpt_lvl_low_en_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_29_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_29_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[29].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_29_qs) + ); + + + // F[intrpt_lvl_low_en_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_30_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_30_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[30].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_30_qs) + ); + + + // F[intrpt_lvl_low_en_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_en_intrpt_lvl_low_en_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_en_intrpt_lvl_low_en_31_we), + .wd (intrpt_lvl_low_en_intrpt_lvl_low_en_31_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_en[31].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_en_intrpt_lvl_low_en_31_qs) + ); + + + + + // Subregister 0 of Multireg intrpt_status + // R[intrpt_status]: V(True) + + // F[intrpt_status_0]: 0:0 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_0 ( + .re (intrpt_status_intrpt_status_0_re), + .we (intrpt_status_intrpt_status_0_we), + .wd (intrpt_status_intrpt_status_0_wd), + .d (hw2reg.intrpt_status[0].d), + .qre (), + .qe (reg2hw.intrpt_status[0].qe), + .q (reg2hw.intrpt_status[0].q ), + .qs (intrpt_status_intrpt_status_0_qs) + ); + + + // F[intrpt_status_1]: 1:1 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_1 ( + .re (intrpt_status_intrpt_status_1_re), + .we (intrpt_status_intrpt_status_1_we), + .wd (intrpt_status_intrpt_status_1_wd), + .d (hw2reg.intrpt_status[1].d), + .qre (), + .qe (reg2hw.intrpt_status[1].qe), + .q (reg2hw.intrpt_status[1].q ), + .qs (intrpt_status_intrpt_status_1_qs) + ); + + + // F[intrpt_status_2]: 2:2 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_2 ( + .re (intrpt_status_intrpt_status_2_re), + .we (intrpt_status_intrpt_status_2_we), + .wd (intrpt_status_intrpt_status_2_wd), + .d (hw2reg.intrpt_status[2].d), + .qre (), + .qe (reg2hw.intrpt_status[2].qe), + .q (reg2hw.intrpt_status[2].q ), + .qs (intrpt_status_intrpt_status_2_qs) + ); + + + // F[intrpt_status_3]: 3:3 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_3 ( + .re (intrpt_status_intrpt_status_3_re), + .we (intrpt_status_intrpt_status_3_we), + .wd (intrpt_status_intrpt_status_3_wd), + .d (hw2reg.intrpt_status[3].d), + .qre (), + .qe (reg2hw.intrpt_status[3].qe), + .q (reg2hw.intrpt_status[3].q ), + .qs (intrpt_status_intrpt_status_3_qs) + ); + + + // F[intrpt_status_4]: 4:4 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_4 ( + .re (intrpt_status_intrpt_status_4_re), + .we (intrpt_status_intrpt_status_4_we), + .wd (intrpt_status_intrpt_status_4_wd), + .d (hw2reg.intrpt_status[4].d), + .qre (), + .qe (reg2hw.intrpt_status[4].qe), + .q (reg2hw.intrpt_status[4].q ), + .qs (intrpt_status_intrpt_status_4_qs) + ); + + + // F[intrpt_status_5]: 5:5 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_5 ( + .re (intrpt_status_intrpt_status_5_re), + .we (intrpt_status_intrpt_status_5_we), + .wd (intrpt_status_intrpt_status_5_wd), + .d (hw2reg.intrpt_status[5].d), + .qre (), + .qe (reg2hw.intrpt_status[5].qe), + .q (reg2hw.intrpt_status[5].q ), + .qs (intrpt_status_intrpt_status_5_qs) + ); + + + // F[intrpt_status_6]: 6:6 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_6 ( + .re (intrpt_status_intrpt_status_6_re), + .we (intrpt_status_intrpt_status_6_we), + .wd (intrpt_status_intrpt_status_6_wd), + .d (hw2reg.intrpt_status[6].d), + .qre (), + .qe (reg2hw.intrpt_status[6].qe), + .q (reg2hw.intrpt_status[6].q ), + .qs (intrpt_status_intrpt_status_6_qs) + ); + + + // F[intrpt_status_7]: 7:7 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_7 ( + .re (intrpt_status_intrpt_status_7_re), + .we (intrpt_status_intrpt_status_7_we), + .wd (intrpt_status_intrpt_status_7_wd), + .d (hw2reg.intrpt_status[7].d), + .qre (), + .qe (reg2hw.intrpt_status[7].qe), + .q (reg2hw.intrpt_status[7].q ), + .qs (intrpt_status_intrpt_status_7_qs) + ); + + + // F[intrpt_status_8]: 8:8 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_8 ( + .re (intrpt_status_intrpt_status_8_re), + .we (intrpt_status_intrpt_status_8_we), + .wd (intrpt_status_intrpt_status_8_wd), + .d (hw2reg.intrpt_status[8].d), + .qre (), + .qe (reg2hw.intrpt_status[8].qe), + .q (reg2hw.intrpt_status[8].q ), + .qs (intrpt_status_intrpt_status_8_qs) + ); + + + // F[intrpt_status_9]: 9:9 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_9 ( + .re (intrpt_status_intrpt_status_9_re), + .we (intrpt_status_intrpt_status_9_we), + .wd (intrpt_status_intrpt_status_9_wd), + .d (hw2reg.intrpt_status[9].d), + .qre (), + .qe (reg2hw.intrpt_status[9].qe), + .q (reg2hw.intrpt_status[9].q ), + .qs (intrpt_status_intrpt_status_9_qs) + ); + + + // F[intrpt_status_10]: 10:10 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_10 ( + .re (intrpt_status_intrpt_status_10_re), + .we (intrpt_status_intrpt_status_10_we), + .wd (intrpt_status_intrpt_status_10_wd), + .d (hw2reg.intrpt_status[10].d), + .qre (), + .qe (reg2hw.intrpt_status[10].qe), + .q (reg2hw.intrpt_status[10].q ), + .qs (intrpt_status_intrpt_status_10_qs) + ); + + + // F[intrpt_status_11]: 11:11 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_11 ( + .re (intrpt_status_intrpt_status_11_re), + .we (intrpt_status_intrpt_status_11_we), + .wd (intrpt_status_intrpt_status_11_wd), + .d (hw2reg.intrpt_status[11].d), + .qre (), + .qe (reg2hw.intrpt_status[11].qe), + .q (reg2hw.intrpt_status[11].q ), + .qs (intrpt_status_intrpt_status_11_qs) + ); + + + // F[intrpt_status_12]: 12:12 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_12 ( + .re (intrpt_status_intrpt_status_12_re), + .we (intrpt_status_intrpt_status_12_we), + .wd (intrpt_status_intrpt_status_12_wd), + .d (hw2reg.intrpt_status[12].d), + .qre (), + .qe (reg2hw.intrpt_status[12].qe), + .q (reg2hw.intrpt_status[12].q ), + .qs (intrpt_status_intrpt_status_12_qs) + ); + + + // F[intrpt_status_13]: 13:13 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_13 ( + .re (intrpt_status_intrpt_status_13_re), + .we (intrpt_status_intrpt_status_13_we), + .wd (intrpt_status_intrpt_status_13_wd), + .d (hw2reg.intrpt_status[13].d), + .qre (), + .qe (reg2hw.intrpt_status[13].qe), + .q (reg2hw.intrpt_status[13].q ), + .qs (intrpt_status_intrpt_status_13_qs) + ); + + + // F[intrpt_status_14]: 14:14 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_14 ( + .re (intrpt_status_intrpt_status_14_re), + .we (intrpt_status_intrpt_status_14_we), + .wd (intrpt_status_intrpt_status_14_wd), + .d (hw2reg.intrpt_status[14].d), + .qre (), + .qe (reg2hw.intrpt_status[14].qe), + .q (reg2hw.intrpt_status[14].q ), + .qs (intrpt_status_intrpt_status_14_qs) + ); + + + // F[intrpt_status_15]: 15:15 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_15 ( + .re (intrpt_status_intrpt_status_15_re), + .we (intrpt_status_intrpt_status_15_we), + .wd (intrpt_status_intrpt_status_15_wd), + .d (hw2reg.intrpt_status[15].d), + .qre (), + .qe (reg2hw.intrpt_status[15].qe), + .q (reg2hw.intrpt_status[15].q ), + .qs (intrpt_status_intrpt_status_15_qs) + ); + + + // F[intrpt_status_16]: 16:16 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_16 ( + .re (intrpt_status_intrpt_status_16_re), + .we (intrpt_status_intrpt_status_16_we), + .wd (intrpt_status_intrpt_status_16_wd), + .d (hw2reg.intrpt_status[16].d), + .qre (), + .qe (reg2hw.intrpt_status[16].qe), + .q (reg2hw.intrpt_status[16].q ), + .qs (intrpt_status_intrpt_status_16_qs) + ); + + + // F[intrpt_status_17]: 17:17 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_17 ( + .re (intrpt_status_intrpt_status_17_re), + .we (intrpt_status_intrpt_status_17_we), + .wd (intrpt_status_intrpt_status_17_wd), + .d (hw2reg.intrpt_status[17].d), + .qre (), + .qe (reg2hw.intrpt_status[17].qe), + .q (reg2hw.intrpt_status[17].q ), + .qs (intrpt_status_intrpt_status_17_qs) + ); + + + // F[intrpt_status_18]: 18:18 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_18 ( + .re (intrpt_status_intrpt_status_18_re), + .we (intrpt_status_intrpt_status_18_we), + .wd (intrpt_status_intrpt_status_18_wd), + .d (hw2reg.intrpt_status[18].d), + .qre (), + .qe (reg2hw.intrpt_status[18].qe), + .q (reg2hw.intrpt_status[18].q ), + .qs (intrpt_status_intrpt_status_18_qs) + ); + + + // F[intrpt_status_19]: 19:19 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_19 ( + .re (intrpt_status_intrpt_status_19_re), + .we (intrpt_status_intrpt_status_19_we), + .wd (intrpt_status_intrpt_status_19_wd), + .d (hw2reg.intrpt_status[19].d), + .qre (), + .qe (reg2hw.intrpt_status[19].qe), + .q (reg2hw.intrpt_status[19].q ), + .qs (intrpt_status_intrpt_status_19_qs) + ); + + + // F[intrpt_status_20]: 20:20 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_20 ( + .re (intrpt_status_intrpt_status_20_re), + .we (intrpt_status_intrpt_status_20_we), + .wd (intrpt_status_intrpt_status_20_wd), + .d (hw2reg.intrpt_status[20].d), + .qre (), + .qe (reg2hw.intrpt_status[20].qe), + .q (reg2hw.intrpt_status[20].q ), + .qs (intrpt_status_intrpt_status_20_qs) + ); + + + // F[intrpt_status_21]: 21:21 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_21 ( + .re (intrpt_status_intrpt_status_21_re), + .we (intrpt_status_intrpt_status_21_we), + .wd (intrpt_status_intrpt_status_21_wd), + .d (hw2reg.intrpt_status[21].d), + .qre (), + .qe (reg2hw.intrpt_status[21].qe), + .q (reg2hw.intrpt_status[21].q ), + .qs (intrpt_status_intrpt_status_21_qs) + ); + + + // F[intrpt_status_22]: 22:22 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_22 ( + .re (intrpt_status_intrpt_status_22_re), + .we (intrpt_status_intrpt_status_22_we), + .wd (intrpt_status_intrpt_status_22_wd), + .d (hw2reg.intrpt_status[22].d), + .qre (), + .qe (reg2hw.intrpt_status[22].qe), + .q (reg2hw.intrpt_status[22].q ), + .qs (intrpt_status_intrpt_status_22_qs) + ); + + + // F[intrpt_status_23]: 23:23 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_23 ( + .re (intrpt_status_intrpt_status_23_re), + .we (intrpt_status_intrpt_status_23_we), + .wd (intrpt_status_intrpt_status_23_wd), + .d (hw2reg.intrpt_status[23].d), + .qre (), + .qe (reg2hw.intrpt_status[23].qe), + .q (reg2hw.intrpt_status[23].q ), + .qs (intrpt_status_intrpt_status_23_qs) + ); + + + // F[intrpt_status_24]: 24:24 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_24 ( + .re (intrpt_status_intrpt_status_24_re), + .we (intrpt_status_intrpt_status_24_we), + .wd (intrpt_status_intrpt_status_24_wd), + .d (hw2reg.intrpt_status[24].d), + .qre (), + .qe (reg2hw.intrpt_status[24].qe), + .q (reg2hw.intrpt_status[24].q ), + .qs (intrpt_status_intrpt_status_24_qs) + ); + + + // F[intrpt_status_25]: 25:25 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_25 ( + .re (intrpt_status_intrpt_status_25_re), + .we (intrpt_status_intrpt_status_25_we), + .wd (intrpt_status_intrpt_status_25_wd), + .d (hw2reg.intrpt_status[25].d), + .qre (), + .qe (reg2hw.intrpt_status[25].qe), + .q (reg2hw.intrpt_status[25].q ), + .qs (intrpt_status_intrpt_status_25_qs) + ); + + + // F[intrpt_status_26]: 26:26 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_26 ( + .re (intrpt_status_intrpt_status_26_re), + .we (intrpt_status_intrpt_status_26_we), + .wd (intrpt_status_intrpt_status_26_wd), + .d (hw2reg.intrpt_status[26].d), + .qre (), + .qe (reg2hw.intrpt_status[26].qe), + .q (reg2hw.intrpt_status[26].q ), + .qs (intrpt_status_intrpt_status_26_qs) + ); + + + // F[intrpt_status_27]: 27:27 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_27 ( + .re (intrpt_status_intrpt_status_27_re), + .we (intrpt_status_intrpt_status_27_we), + .wd (intrpt_status_intrpt_status_27_wd), + .d (hw2reg.intrpt_status[27].d), + .qre (), + .qe (reg2hw.intrpt_status[27].qe), + .q (reg2hw.intrpt_status[27].q ), + .qs (intrpt_status_intrpt_status_27_qs) + ); + + + // F[intrpt_status_28]: 28:28 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_28 ( + .re (intrpt_status_intrpt_status_28_re), + .we (intrpt_status_intrpt_status_28_we), + .wd (intrpt_status_intrpt_status_28_wd), + .d (hw2reg.intrpt_status[28].d), + .qre (), + .qe (reg2hw.intrpt_status[28].qe), + .q (reg2hw.intrpt_status[28].q ), + .qs (intrpt_status_intrpt_status_28_qs) + ); + + + // F[intrpt_status_29]: 29:29 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_29 ( + .re (intrpt_status_intrpt_status_29_re), + .we (intrpt_status_intrpt_status_29_we), + .wd (intrpt_status_intrpt_status_29_wd), + .d (hw2reg.intrpt_status[29].d), + .qre (), + .qe (reg2hw.intrpt_status[29].qe), + .q (reg2hw.intrpt_status[29].q ), + .qs (intrpt_status_intrpt_status_29_qs) + ); + + + // F[intrpt_status_30]: 30:30 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_30 ( + .re (intrpt_status_intrpt_status_30_re), + .we (intrpt_status_intrpt_status_30_we), + .wd (intrpt_status_intrpt_status_30_wd), + .d (hw2reg.intrpt_status[30].d), + .qre (), + .qe (reg2hw.intrpt_status[30].qe), + .q (reg2hw.intrpt_status[30].q ), + .qs (intrpt_status_intrpt_status_30_qs) + ); + + + // F[intrpt_status_31]: 31:31 + prim_subreg_ext #( + .DW (1) + ) u_intrpt_status_intrpt_status_31 ( + .re (intrpt_status_intrpt_status_31_re), + .we (intrpt_status_intrpt_status_31_we), + .wd (intrpt_status_intrpt_status_31_wd), + .d (hw2reg.intrpt_status[31].d), + .qre (), + .qe (reg2hw.intrpt_status[31].qe), + .q (reg2hw.intrpt_status[31].q ), + .qs (intrpt_status_intrpt_status_31_qs) + ); + + + + + // Subregister 0 of Multireg intrpt_rise_status + // R[intrpt_rise_status]: V(False) + + // F[intrpt_rise_status_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_0_we), + .wd (intrpt_rise_status_intrpt_rise_status_0_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[0].de), + .d (hw2reg.intrpt_rise_status[0].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[0].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_0_qs) + ); + + + // F[intrpt_rise_status_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_1_we), + .wd (intrpt_rise_status_intrpt_rise_status_1_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[1].de), + .d (hw2reg.intrpt_rise_status[1].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[1].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_1_qs) + ); + + + // F[intrpt_rise_status_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_2_we), + .wd (intrpt_rise_status_intrpt_rise_status_2_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[2].de), + .d (hw2reg.intrpt_rise_status[2].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[2].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_2_qs) + ); + + + // F[intrpt_rise_status_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_3_we), + .wd (intrpt_rise_status_intrpt_rise_status_3_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[3].de), + .d (hw2reg.intrpt_rise_status[3].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[3].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_3_qs) + ); + + + // F[intrpt_rise_status_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_4_we), + .wd (intrpt_rise_status_intrpt_rise_status_4_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[4].de), + .d (hw2reg.intrpt_rise_status[4].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[4].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_4_qs) + ); + + + // F[intrpt_rise_status_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_5_we), + .wd (intrpt_rise_status_intrpt_rise_status_5_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[5].de), + .d (hw2reg.intrpt_rise_status[5].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[5].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_5_qs) + ); + + + // F[intrpt_rise_status_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_6_we), + .wd (intrpt_rise_status_intrpt_rise_status_6_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[6].de), + .d (hw2reg.intrpt_rise_status[6].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[6].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_6_qs) + ); + + + // F[intrpt_rise_status_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_7_we), + .wd (intrpt_rise_status_intrpt_rise_status_7_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[7].de), + .d (hw2reg.intrpt_rise_status[7].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[7].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_7_qs) + ); + + + // F[intrpt_rise_status_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_8_we), + .wd (intrpt_rise_status_intrpt_rise_status_8_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[8].de), + .d (hw2reg.intrpt_rise_status[8].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[8].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_8_qs) + ); + + + // F[intrpt_rise_status_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_9_we), + .wd (intrpt_rise_status_intrpt_rise_status_9_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[9].de), + .d (hw2reg.intrpt_rise_status[9].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[9].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_9_qs) + ); + + + // F[intrpt_rise_status_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_10_we), + .wd (intrpt_rise_status_intrpt_rise_status_10_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[10].de), + .d (hw2reg.intrpt_rise_status[10].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[10].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_10_qs) + ); + + + // F[intrpt_rise_status_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_11_we), + .wd (intrpt_rise_status_intrpt_rise_status_11_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[11].de), + .d (hw2reg.intrpt_rise_status[11].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[11].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_11_qs) + ); + + + // F[intrpt_rise_status_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_12_we), + .wd (intrpt_rise_status_intrpt_rise_status_12_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[12].de), + .d (hw2reg.intrpt_rise_status[12].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[12].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_12_qs) + ); + + + // F[intrpt_rise_status_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_13_we), + .wd (intrpt_rise_status_intrpt_rise_status_13_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[13].de), + .d (hw2reg.intrpt_rise_status[13].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[13].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_13_qs) + ); + + + // F[intrpt_rise_status_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_14_we), + .wd (intrpt_rise_status_intrpt_rise_status_14_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[14].de), + .d (hw2reg.intrpt_rise_status[14].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[14].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_14_qs) + ); + + + // F[intrpt_rise_status_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_15_we), + .wd (intrpt_rise_status_intrpt_rise_status_15_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[15].de), + .d (hw2reg.intrpt_rise_status[15].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[15].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_15_qs) + ); + + + // F[intrpt_rise_status_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_16_we), + .wd (intrpt_rise_status_intrpt_rise_status_16_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[16].de), + .d (hw2reg.intrpt_rise_status[16].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[16].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_16_qs) + ); + + + // F[intrpt_rise_status_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_17_we), + .wd (intrpt_rise_status_intrpt_rise_status_17_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[17].de), + .d (hw2reg.intrpt_rise_status[17].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[17].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_17_qs) + ); + + + // F[intrpt_rise_status_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_18_we), + .wd (intrpt_rise_status_intrpt_rise_status_18_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[18].de), + .d (hw2reg.intrpt_rise_status[18].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[18].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_18_qs) + ); + + + // F[intrpt_rise_status_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_19_we), + .wd (intrpt_rise_status_intrpt_rise_status_19_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[19].de), + .d (hw2reg.intrpt_rise_status[19].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[19].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_19_qs) + ); + + + // F[intrpt_rise_status_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_20_we), + .wd (intrpt_rise_status_intrpt_rise_status_20_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[20].de), + .d (hw2reg.intrpt_rise_status[20].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[20].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_20_qs) + ); + + + // F[intrpt_rise_status_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_21_we), + .wd (intrpt_rise_status_intrpt_rise_status_21_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[21].de), + .d (hw2reg.intrpt_rise_status[21].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[21].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_21_qs) + ); + + + // F[intrpt_rise_status_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_22_we), + .wd (intrpt_rise_status_intrpt_rise_status_22_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[22].de), + .d (hw2reg.intrpt_rise_status[22].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[22].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_22_qs) + ); + + + // F[intrpt_rise_status_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_23_we), + .wd (intrpt_rise_status_intrpt_rise_status_23_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[23].de), + .d (hw2reg.intrpt_rise_status[23].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[23].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_23_qs) + ); + + + // F[intrpt_rise_status_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_24_we), + .wd (intrpt_rise_status_intrpt_rise_status_24_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[24].de), + .d (hw2reg.intrpt_rise_status[24].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[24].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_24_qs) + ); + + + // F[intrpt_rise_status_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_25_we), + .wd (intrpt_rise_status_intrpt_rise_status_25_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[25].de), + .d (hw2reg.intrpt_rise_status[25].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[25].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_25_qs) + ); + + + // F[intrpt_rise_status_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_26_we), + .wd (intrpt_rise_status_intrpt_rise_status_26_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[26].de), + .d (hw2reg.intrpt_rise_status[26].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[26].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_26_qs) + ); + + + // F[intrpt_rise_status_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_27_we), + .wd (intrpt_rise_status_intrpt_rise_status_27_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[27].de), + .d (hw2reg.intrpt_rise_status[27].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[27].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_27_qs) + ); + + + // F[intrpt_rise_status_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_28_we), + .wd (intrpt_rise_status_intrpt_rise_status_28_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[28].de), + .d (hw2reg.intrpt_rise_status[28].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[28].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_28_qs) + ); + + + // F[intrpt_rise_status_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_29_we), + .wd (intrpt_rise_status_intrpt_rise_status_29_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[29].de), + .d (hw2reg.intrpt_rise_status[29].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[29].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_29_qs) + ); + + + // F[intrpt_rise_status_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_30_we), + .wd (intrpt_rise_status_intrpt_rise_status_30_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[30].de), + .d (hw2reg.intrpt_rise_status[30].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[30].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_30_qs) + ); + + + // F[intrpt_rise_status_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_rise_status_intrpt_rise_status_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_rise_status_intrpt_rise_status_31_we), + .wd (intrpt_rise_status_intrpt_rise_status_31_wd), + + // from internal hardware + .de (hw2reg.intrpt_rise_status[31].de), + .d (hw2reg.intrpt_rise_status[31].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_rise_status[31].q ), + + // to register interface (read) + .qs (intrpt_rise_status_intrpt_rise_status_31_qs) + ); + + + + + // Subregister 0 of Multireg intrpt_fall_status + // R[intrpt_fall_status]: V(False) + + // F[intrpt_fall_status_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_0_we), + .wd (intrpt_fall_status_intrpt_fall_status_0_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[0].de), + .d (hw2reg.intrpt_fall_status[0].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[0].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_0_qs) + ); + + + // F[intrpt_fall_status_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_1_we), + .wd (intrpt_fall_status_intrpt_fall_status_1_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[1].de), + .d (hw2reg.intrpt_fall_status[1].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[1].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_1_qs) + ); + + + // F[intrpt_fall_status_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_2_we), + .wd (intrpt_fall_status_intrpt_fall_status_2_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[2].de), + .d (hw2reg.intrpt_fall_status[2].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[2].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_2_qs) + ); + + + // F[intrpt_fall_status_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_3_we), + .wd (intrpt_fall_status_intrpt_fall_status_3_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[3].de), + .d (hw2reg.intrpt_fall_status[3].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[3].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_3_qs) + ); + + + // F[intrpt_fall_status_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_4_we), + .wd (intrpt_fall_status_intrpt_fall_status_4_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[4].de), + .d (hw2reg.intrpt_fall_status[4].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[4].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_4_qs) + ); + + + // F[intrpt_fall_status_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_5_we), + .wd (intrpt_fall_status_intrpt_fall_status_5_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[5].de), + .d (hw2reg.intrpt_fall_status[5].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[5].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_5_qs) + ); + + + // F[intrpt_fall_status_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_6_we), + .wd (intrpt_fall_status_intrpt_fall_status_6_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[6].de), + .d (hw2reg.intrpt_fall_status[6].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[6].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_6_qs) + ); + + + // F[intrpt_fall_status_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_7_we), + .wd (intrpt_fall_status_intrpt_fall_status_7_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[7].de), + .d (hw2reg.intrpt_fall_status[7].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[7].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_7_qs) + ); + + + // F[intrpt_fall_status_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_8_we), + .wd (intrpt_fall_status_intrpt_fall_status_8_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[8].de), + .d (hw2reg.intrpt_fall_status[8].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[8].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_8_qs) + ); + + + // F[intrpt_fall_status_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_9_we), + .wd (intrpt_fall_status_intrpt_fall_status_9_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[9].de), + .d (hw2reg.intrpt_fall_status[9].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[9].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_9_qs) + ); + + + // F[intrpt_fall_status_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_10_we), + .wd (intrpt_fall_status_intrpt_fall_status_10_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[10].de), + .d (hw2reg.intrpt_fall_status[10].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[10].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_10_qs) + ); + + + // F[intrpt_fall_status_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_11_we), + .wd (intrpt_fall_status_intrpt_fall_status_11_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[11].de), + .d (hw2reg.intrpt_fall_status[11].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[11].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_11_qs) + ); + + + // F[intrpt_fall_status_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_12_we), + .wd (intrpt_fall_status_intrpt_fall_status_12_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[12].de), + .d (hw2reg.intrpt_fall_status[12].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[12].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_12_qs) + ); + + + // F[intrpt_fall_status_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_13_we), + .wd (intrpt_fall_status_intrpt_fall_status_13_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[13].de), + .d (hw2reg.intrpt_fall_status[13].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[13].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_13_qs) + ); + + + // F[intrpt_fall_status_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_14_we), + .wd (intrpt_fall_status_intrpt_fall_status_14_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[14].de), + .d (hw2reg.intrpt_fall_status[14].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[14].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_14_qs) + ); + + + // F[intrpt_fall_status_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_15_we), + .wd (intrpt_fall_status_intrpt_fall_status_15_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[15].de), + .d (hw2reg.intrpt_fall_status[15].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[15].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_15_qs) + ); + + + // F[intrpt_fall_status_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_16_we), + .wd (intrpt_fall_status_intrpt_fall_status_16_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[16].de), + .d (hw2reg.intrpt_fall_status[16].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[16].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_16_qs) + ); + + + // F[intrpt_fall_status_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_17_we), + .wd (intrpt_fall_status_intrpt_fall_status_17_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[17].de), + .d (hw2reg.intrpt_fall_status[17].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[17].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_17_qs) + ); + + + // F[intrpt_fall_status_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_18_we), + .wd (intrpt_fall_status_intrpt_fall_status_18_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[18].de), + .d (hw2reg.intrpt_fall_status[18].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[18].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_18_qs) + ); + + + // F[intrpt_fall_status_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_19_we), + .wd (intrpt_fall_status_intrpt_fall_status_19_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[19].de), + .d (hw2reg.intrpt_fall_status[19].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[19].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_19_qs) + ); + + + // F[intrpt_fall_status_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_20_we), + .wd (intrpt_fall_status_intrpt_fall_status_20_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[20].de), + .d (hw2reg.intrpt_fall_status[20].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[20].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_20_qs) + ); + + + // F[intrpt_fall_status_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_21_we), + .wd (intrpt_fall_status_intrpt_fall_status_21_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[21].de), + .d (hw2reg.intrpt_fall_status[21].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[21].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_21_qs) + ); + + + // F[intrpt_fall_status_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_22_we), + .wd (intrpt_fall_status_intrpt_fall_status_22_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[22].de), + .d (hw2reg.intrpt_fall_status[22].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[22].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_22_qs) + ); + + + // F[intrpt_fall_status_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_23_we), + .wd (intrpt_fall_status_intrpt_fall_status_23_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[23].de), + .d (hw2reg.intrpt_fall_status[23].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[23].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_23_qs) + ); + + + // F[intrpt_fall_status_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_24_we), + .wd (intrpt_fall_status_intrpt_fall_status_24_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[24].de), + .d (hw2reg.intrpt_fall_status[24].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[24].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_24_qs) + ); + + + // F[intrpt_fall_status_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_25_we), + .wd (intrpt_fall_status_intrpt_fall_status_25_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[25].de), + .d (hw2reg.intrpt_fall_status[25].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[25].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_25_qs) + ); + + + // F[intrpt_fall_status_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_26_we), + .wd (intrpt_fall_status_intrpt_fall_status_26_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[26].de), + .d (hw2reg.intrpt_fall_status[26].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[26].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_26_qs) + ); + + + // F[intrpt_fall_status_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_27_we), + .wd (intrpt_fall_status_intrpt_fall_status_27_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[27].de), + .d (hw2reg.intrpt_fall_status[27].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[27].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_27_qs) + ); + + + // F[intrpt_fall_status_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_28_we), + .wd (intrpt_fall_status_intrpt_fall_status_28_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[28].de), + .d (hw2reg.intrpt_fall_status[28].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[28].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_28_qs) + ); + + + // F[intrpt_fall_status_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_29_we), + .wd (intrpt_fall_status_intrpt_fall_status_29_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[29].de), + .d (hw2reg.intrpt_fall_status[29].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[29].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_29_qs) + ); + + + // F[intrpt_fall_status_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_30_we), + .wd (intrpt_fall_status_intrpt_fall_status_30_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[30].de), + .d (hw2reg.intrpt_fall_status[30].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[30].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_30_qs) + ); + + + // F[intrpt_fall_status_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_fall_status_intrpt_fall_status_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_fall_status_intrpt_fall_status_31_we), + .wd (intrpt_fall_status_intrpt_fall_status_31_wd), + + // from internal hardware + .de (hw2reg.intrpt_fall_status[31].de), + .d (hw2reg.intrpt_fall_status[31].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_fall_status[31].q ), + + // to register interface (read) + .qs (intrpt_fall_status_intrpt_fall_status_31_qs) + ); + + + + + // Subregister 0 of Multireg intrpt_lvl_high_status + // R[intrpt_lvl_high_status]: V(False) + + // F[intrpt_lvl_high_status_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_0_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_0_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[0].de), + .d (hw2reg.intrpt_lvl_high_status[0].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[0].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_0_qs) + ); + + + // F[intrpt_lvl_high_status_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_1_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_1_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[1].de), + .d (hw2reg.intrpt_lvl_high_status[1].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[1].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_1_qs) + ); + + + // F[intrpt_lvl_high_status_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_2_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_2_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[2].de), + .d (hw2reg.intrpt_lvl_high_status[2].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[2].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_2_qs) + ); + + + // F[intrpt_lvl_high_status_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_3_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_3_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[3].de), + .d (hw2reg.intrpt_lvl_high_status[3].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[3].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_3_qs) + ); + + + // F[intrpt_lvl_high_status_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_4_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_4_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[4].de), + .d (hw2reg.intrpt_lvl_high_status[4].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[4].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_4_qs) + ); + + + // F[intrpt_lvl_high_status_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_5_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_5_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[5].de), + .d (hw2reg.intrpt_lvl_high_status[5].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[5].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_5_qs) + ); + + + // F[intrpt_lvl_high_status_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_6_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_6_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[6].de), + .d (hw2reg.intrpt_lvl_high_status[6].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[6].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_6_qs) + ); + + + // F[intrpt_lvl_high_status_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_7_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_7_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[7].de), + .d (hw2reg.intrpt_lvl_high_status[7].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[7].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_7_qs) + ); + + + // F[intrpt_lvl_high_status_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_8_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_8_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[8].de), + .d (hw2reg.intrpt_lvl_high_status[8].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[8].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_8_qs) + ); + + + // F[intrpt_lvl_high_status_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_9_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_9_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[9].de), + .d (hw2reg.intrpt_lvl_high_status[9].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[9].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_9_qs) + ); + + + // F[intrpt_lvl_high_status_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_10_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_10_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[10].de), + .d (hw2reg.intrpt_lvl_high_status[10].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[10].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_10_qs) + ); + + + // F[intrpt_lvl_high_status_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_11_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_11_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[11].de), + .d (hw2reg.intrpt_lvl_high_status[11].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[11].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_11_qs) + ); + + + // F[intrpt_lvl_high_status_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_12_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_12_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[12].de), + .d (hw2reg.intrpt_lvl_high_status[12].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[12].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_12_qs) + ); + + + // F[intrpt_lvl_high_status_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_13_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_13_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[13].de), + .d (hw2reg.intrpt_lvl_high_status[13].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[13].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_13_qs) + ); + + + // F[intrpt_lvl_high_status_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_14_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_14_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[14].de), + .d (hw2reg.intrpt_lvl_high_status[14].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[14].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_14_qs) + ); + + + // F[intrpt_lvl_high_status_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_15_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_15_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[15].de), + .d (hw2reg.intrpt_lvl_high_status[15].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[15].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_15_qs) + ); + + + // F[intrpt_lvl_high_status_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_16_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_16_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[16].de), + .d (hw2reg.intrpt_lvl_high_status[16].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[16].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_16_qs) + ); + + + // F[intrpt_lvl_high_status_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_17_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_17_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[17].de), + .d (hw2reg.intrpt_lvl_high_status[17].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[17].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_17_qs) + ); + + + // F[intrpt_lvl_high_status_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_18_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_18_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[18].de), + .d (hw2reg.intrpt_lvl_high_status[18].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[18].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_18_qs) + ); + + + // F[intrpt_lvl_high_status_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_19_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_19_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[19].de), + .d (hw2reg.intrpt_lvl_high_status[19].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[19].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_19_qs) + ); + + + // F[intrpt_lvl_high_status_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_20_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_20_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[20].de), + .d (hw2reg.intrpt_lvl_high_status[20].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[20].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_20_qs) + ); + + + // F[intrpt_lvl_high_status_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_21_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_21_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[21].de), + .d (hw2reg.intrpt_lvl_high_status[21].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[21].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_21_qs) + ); + + + // F[intrpt_lvl_high_status_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_22_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_22_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[22].de), + .d (hw2reg.intrpt_lvl_high_status[22].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[22].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_22_qs) + ); + + + // F[intrpt_lvl_high_status_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_23_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_23_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[23].de), + .d (hw2reg.intrpt_lvl_high_status[23].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[23].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_23_qs) + ); + + + // F[intrpt_lvl_high_status_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_24_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_24_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[24].de), + .d (hw2reg.intrpt_lvl_high_status[24].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[24].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_24_qs) + ); + + + // F[intrpt_lvl_high_status_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_25_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_25_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[25].de), + .d (hw2reg.intrpt_lvl_high_status[25].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[25].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_25_qs) + ); + + + // F[intrpt_lvl_high_status_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_26_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_26_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[26].de), + .d (hw2reg.intrpt_lvl_high_status[26].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[26].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_26_qs) + ); + + + // F[intrpt_lvl_high_status_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_27_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_27_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[27].de), + .d (hw2reg.intrpt_lvl_high_status[27].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[27].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_27_qs) + ); + + + // F[intrpt_lvl_high_status_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_28_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_28_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[28].de), + .d (hw2reg.intrpt_lvl_high_status[28].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[28].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_28_qs) + ); + + + // F[intrpt_lvl_high_status_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_29_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_29_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[29].de), + .d (hw2reg.intrpt_lvl_high_status[29].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[29].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_29_qs) + ); + + + // F[intrpt_lvl_high_status_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_30_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_30_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[30].de), + .d (hw2reg.intrpt_lvl_high_status[30].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[30].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_30_qs) + ); + + + // F[intrpt_lvl_high_status_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_high_status_intrpt_lvl_high_status_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_high_status_intrpt_lvl_high_status_31_we), + .wd (intrpt_lvl_high_status_intrpt_lvl_high_status_31_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_high_status[31].de), + .d (hw2reg.intrpt_lvl_high_status[31].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_high_status[31].q ), + + // to register interface (read) + .qs (intrpt_lvl_high_status_intrpt_lvl_high_status_31_qs) + ); + + + + + // Subregister 0 of Multireg intrpt_lvl_low_status + // R[intrpt_lvl_low_status]: V(False) + + // F[intrpt_lvl_low_status_0]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_0_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_0_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[0].de), + .d (hw2reg.intrpt_lvl_low_status[0].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[0].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_0_qs) + ); + + + // F[intrpt_lvl_low_status_1]: 1:1 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_1_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_1_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[1].de), + .d (hw2reg.intrpt_lvl_low_status[1].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[1].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_1_qs) + ); + + + // F[intrpt_lvl_low_status_2]: 2:2 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_2_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_2_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[2].de), + .d (hw2reg.intrpt_lvl_low_status[2].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[2].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_2_qs) + ); + + + // F[intrpt_lvl_low_status_3]: 3:3 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_3_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_3_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[3].de), + .d (hw2reg.intrpt_lvl_low_status[3].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[3].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_3_qs) + ); + + + // F[intrpt_lvl_low_status_4]: 4:4 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_4_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_4_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[4].de), + .d (hw2reg.intrpt_lvl_low_status[4].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[4].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_4_qs) + ); + + + // F[intrpt_lvl_low_status_5]: 5:5 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_5_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_5_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[5].de), + .d (hw2reg.intrpt_lvl_low_status[5].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[5].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_5_qs) + ); + + + // F[intrpt_lvl_low_status_6]: 6:6 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_6_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_6_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[6].de), + .d (hw2reg.intrpt_lvl_low_status[6].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[6].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_6_qs) + ); + + + // F[intrpt_lvl_low_status_7]: 7:7 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_7_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_7_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[7].de), + .d (hw2reg.intrpt_lvl_low_status[7].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[7].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_7_qs) + ); + + + // F[intrpt_lvl_low_status_8]: 8:8 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_8_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_8_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[8].de), + .d (hw2reg.intrpt_lvl_low_status[8].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[8].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_8_qs) + ); + + + // F[intrpt_lvl_low_status_9]: 9:9 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_9 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_9_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_9_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[9].de), + .d (hw2reg.intrpt_lvl_low_status[9].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[9].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_9_qs) + ); + + + // F[intrpt_lvl_low_status_10]: 10:10 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_10 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_10_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_10_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[10].de), + .d (hw2reg.intrpt_lvl_low_status[10].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[10].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_10_qs) + ); + + + // F[intrpt_lvl_low_status_11]: 11:11 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_11 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_11_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_11_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[11].de), + .d (hw2reg.intrpt_lvl_low_status[11].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[11].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_11_qs) + ); + + + // F[intrpt_lvl_low_status_12]: 12:12 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_12 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_12_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_12_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[12].de), + .d (hw2reg.intrpt_lvl_low_status[12].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[12].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_12_qs) + ); + + + // F[intrpt_lvl_low_status_13]: 13:13 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_13 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_13_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_13_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[13].de), + .d (hw2reg.intrpt_lvl_low_status[13].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[13].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_13_qs) + ); + + + // F[intrpt_lvl_low_status_14]: 14:14 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_14 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_14_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_14_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[14].de), + .d (hw2reg.intrpt_lvl_low_status[14].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[14].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_14_qs) + ); + + + // F[intrpt_lvl_low_status_15]: 15:15 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_15 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_15_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_15_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[15].de), + .d (hw2reg.intrpt_lvl_low_status[15].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[15].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_15_qs) + ); + + + // F[intrpt_lvl_low_status_16]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_16 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_16_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_16_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[16].de), + .d (hw2reg.intrpt_lvl_low_status[16].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[16].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_16_qs) + ); + + + // F[intrpt_lvl_low_status_17]: 17:17 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_17 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_17_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_17_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[17].de), + .d (hw2reg.intrpt_lvl_low_status[17].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[17].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_17_qs) + ); + + + // F[intrpt_lvl_low_status_18]: 18:18 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_18 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_18_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_18_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[18].de), + .d (hw2reg.intrpt_lvl_low_status[18].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[18].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_18_qs) + ); + + + // F[intrpt_lvl_low_status_19]: 19:19 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_19 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_19_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_19_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[19].de), + .d (hw2reg.intrpt_lvl_low_status[19].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[19].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_19_qs) + ); + + + // F[intrpt_lvl_low_status_20]: 20:20 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_20 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_20_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_20_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[20].de), + .d (hw2reg.intrpt_lvl_low_status[20].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[20].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_20_qs) + ); + + + // F[intrpt_lvl_low_status_21]: 21:21 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_21 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_21_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_21_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[21].de), + .d (hw2reg.intrpt_lvl_low_status[21].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[21].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_21_qs) + ); + + + // F[intrpt_lvl_low_status_22]: 22:22 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_22 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_22_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_22_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[22].de), + .d (hw2reg.intrpt_lvl_low_status[22].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[22].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_22_qs) + ); + + + // F[intrpt_lvl_low_status_23]: 23:23 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_23 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_23_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_23_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[23].de), + .d (hw2reg.intrpt_lvl_low_status[23].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[23].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_23_qs) + ); + + + // F[intrpt_lvl_low_status_24]: 24:24 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_24 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_24_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_24_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[24].de), + .d (hw2reg.intrpt_lvl_low_status[24].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[24].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_24_qs) + ); + + + // F[intrpt_lvl_low_status_25]: 25:25 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_25 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_25_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_25_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[25].de), + .d (hw2reg.intrpt_lvl_low_status[25].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[25].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_25_qs) + ); + + + // F[intrpt_lvl_low_status_26]: 26:26 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_26 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_26_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_26_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[26].de), + .d (hw2reg.intrpt_lvl_low_status[26].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[26].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_26_qs) + ); + + + // F[intrpt_lvl_low_status_27]: 27:27 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_27 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_27_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_27_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[27].de), + .d (hw2reg.intrpt_lvl_low_status[27].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[27].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_27_qs) + ); + + + // F[intrpt_lvl_low_status_28]: 28:28 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_28 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_28_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_28_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[28].de), + .d (hw2reg.intrpt_lvl_low_status[28].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[28].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_28_qs) + ); + + + // F[intrpt_lvl_low_status_29]: 29:29 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_29 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_29_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_29_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[29].de), + .d (hw2reg.intrpt_lvl_low_status[29].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[29].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_29_qs) + ); + + + // F[intrpt_lvl_low_status_30]: 30:30 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_30 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_30_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_30_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[30].de), + .d (hw2reg.intrpt_lvl_low_status[30].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[30].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_30_qs) + ); + + + // F[intrpt_lvl_low_status_31]: 31:31 + prim_subreg #( + .DW (1), + .SWACCESS("W1C"), + .RESVAL (1'h0) + ) u_intrpt_lvl_low_status_intrpt_lvl_low_status_31 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (intrpt_lvl_low_status_intrpt_lvl_low_status_31_we), + .wd (intrpt_lvl_low_status_intrpt_lvl_low_status_31_wd), + + // from internal hardware + .de (hw2reg.intrpt_lvl_low_status[31].de), + .d (hw2reg.intrpt_lvl_low_status[31].d ), + + // to internal hardware + .qe (), + .q (reg2hw.intrpt_lvl_low_status[31].q ), + + // to register interface (read) + .qs (intrpt_lvl_low_status_intrpt_lvl_low_status_31_qs) + ); + + + + + + logic [18:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == GPIO_INFO_OFFSET); + addr_hit[ 1] = (reg_addr == GPIO_CFG_OFFSET); + addr_hit[ 2] = (reg_addr == GPIO_GPIO_MODE_0_OFFSET); + addr_hit[ 3] = (reg_addr == GPIO_GPIO_MODE_1_OFFSET); + addr_hit[ 4] = (reg_addr == GPIO_GPIO_EN_OFFSET); + addr_hit[ 5] = (reg_addr == GPIO_GPIO_IN_OFFSET); + addr_hit[ 6] = (reg_addr == GPIO_GPIO_OUT_OFFSET); + addr_hit[ 7] = (reg_addr == GPIO_GPIO_SET_OFFSET); + addr_hit[ 8] = (reg_addr == GPIO_GPIO_CLEAR_OFFSET); + addr_hit[ 9] = (reg_addr == GPIO_GPIO_TOGGLE_OFFSET); + addr_hit[10] = (reg_addr == GPIO_INTRPT_RISE_EN_OFFSET); + addr_hit[11] = (reg_addr == GPIO_INTRPT_FALL_EN_OFFSET); + addr_hit[12] = (reg_addr == GPIO_INTRPT_LVL_HIGH_EN_OFFSET); + addr_hit[13] = (reg_addr == GPIO_INTRPT_LVL_LOW_EN_OFFSET); + addr_hit[14] = (reg_addr == GPIO_INTRPT_STATUS_OFFSET); + addr_hit[15] = (reg_addr == GPIO_INTRPT_RISE_STATUS_OFFSET); + addr_hit[16] = (reg_addr == GPIO_INTRPT_FALL_STATUS_OFFSET); + addr_hit[17] = (reg_addr == GPIO_INTRPT_LVL_HIGH_STATUS_OFFSET); + addr_hit[18] = (reg_addr == GPIO_INTRPT_LVL_LOW_STATUS_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(GPIO_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(GPIO_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(GPIO_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(GPIO_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(GPIO_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(GPIO_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(GPIO_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(GPIO_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(GPIO_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(GPIO_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(GPIO_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(GPIO_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(GPIO_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(GPIO_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(GPIO_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(GPIO_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(GPIO_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(GPIO_PERMIT[17] & ~reg_be))) | + (addr_hit[18] & (|(GPIO_PERMIT[18] & ~reg_be))))); + end + + assign info_gpio_cnt_re = addr_hit[0] & reg_re & !reg_error; + + assign info_version_re = addr_hit[0] & reg_re & !reg_error; + + assign cfg_intrpt_mode_we = addr_hit[1] & reg_we & !reg_error; + assign cfg_intrpt_mode_wd = reg_wdata[0]; + + assign cfg_reserved_we = addr_hit[1] & reg_we & !reg_error; + assign cfg_reserved_wd = reg_wdata[1]; + + assign gpio_mode_0_mode_0_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_0_wd = reg_wdata[1:0]; + + assign gpio_mode_0_mode_1_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_1_wd = reg_wdata[3:2]; + + assign gpio_mode_0_mode_2_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_2_wd = reg_wdata[5:4]; + + assign gpio_mode_0_mode_3_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_3_wd = reg_wdata[7:6]; + + assign gpio_mode_0_mode_4_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_4_wd = reg_wdata[9:8]; + + assign gpio_mode_0_mode_5_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_5_wd = reg_wdata[11:10]; + + assign gpio_mode_0_mode_6_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_6_wd = reg_wdata[13:12]; + + assign gpio_mode_0_mode_7_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_7_wd = reg_wdata[15:14]; + + assign gpio_mode_0_mode_8_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_8_wd = reg_wdata[17:16]; + + assign gpio_mode_0_mode_9_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_9_wd = reg_wdata[19:18]; + + assign gpio_mode_0_mode_10_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_10_wd = reg_wdata[21:20]; + + assign gpio_mode_0_mode_11_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_11_wd = reg_wdata[23:22]; + + assign gpio_mode_0_mode_12_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_12_wd = reg_wdata[25:24]; + + assign gpio_mode_0_mode_13_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_13_wd = reg_wdata[27:26]; + + assign gpio_mode_0_mode_14_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_14_wd = reg_wdata[29:28]; + + assign gpio_mode_0_mode_15_we = addr_hit[2] & reg_we & !reg_error; + assign gpio_mode_0_mode_15_wd = reg_wdata[31:30]; + + assign gpio_mode_1_mode_16_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_16_wd = reg_wdata[1:0]; + + assign gpio_mode_1_mode_17_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_17_wd = reg_wdata[3:2]; + + assign gpio_mode_1_mode_18_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_18_wd = reg_wdata[5:4]; + + assign gpio_mode_1_mode_19_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_19_wd = reg_wdata[7:6]; + + assign gpio_mode_1_mode_20_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_20_wd = reg_wdata[9:8]; + + assign gpio_mode_1_mode_21_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_21_wd = reg_wdata[11:10]; + + assign gpio_mode_1_mode_22_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_22_wd = reg_wdata[13:12]; + + assign gpio_mode_1_mode_23_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_23_wd = reg_wdata[15:14]; + + assign gpio_mode_1_mode_24_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_24_wd = reg_wdata[17:16]; + + assign gpio_mode_1_mode_25_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_25_wd = reg_wdata[19:18]; + + assign gpio_mode_1_mode_26_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_26_wd = reg_wdata[21:20]; + + assign gpio_mode_1_mode_27_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_27_wd = reg_wdata[23:22]; + + assign gpio_mode_1_mode_28_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_28_wd = reg_wdata[25:24]; + + assign gpio_mode_1_mode_29_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_29_wd = reg_wdata[27:26]; + + assign gpio_mode_1_mode_30_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_30_wd = reg_wdata[29:28]; + + assign gpio_mode_1_mode_31_we = addr_hit[3] & reg_we & !reg_error; + assign gpio_mode_1_mode_31_wd = reg_wdata[31:30]; + + assign gpio_en_gpio_en_0_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_0_wd = reg_wdata[0]; + + assign gpio_en_gpio_en_1_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_1_wd = reg_wdata[1]; + + assign gpio_en_gpio_en_2_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_2_wd = reg_wdata[2]; + + assign gpio_en_gpio_en_3_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_3_wd = reg_wdata[3]; + + assign gpio_en_gpio_en_4_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_4_wd = reg_wdata[4]; + + assign gpio_en_gpio_en_5_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_5_wd = reg_wdata[5]; + + assign gpio_en_gpio_en_6_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_6_wd = reg_wdata[6]; + + assign gpio_en_gpio_en_7_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_7_wd = reg_wdata[7]; + + assign gpio_en_gpio_en_8_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_8_wd = reg_wdata[8]; + + assign gpio_en_gpio_en_9_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_9_wd = reg_wdata[9]; + + assign gpio_en_gpio_en_10_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_10_wd = reg_wdata[10]; + + assign gpio_en_gpio_en_11_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_11_wd = reg_wdata[11]; + + assign gpio_en_gpio_en_12_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_12_wd = reg_wdata[12]; + + assign gpio_en_gpio_en_13_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_13_wd = reg_wdata[13]; + + assign gpio_en_gpio_en_14_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_14_wd = reg_wdata[14]; + + assign gpio_en_gpio_en_15_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_15_wd = reg_wdata[15]; + + assign gpio_en_gpio_en_16_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_16_wd = reg_wdata[16]; + + assign gpio_en_gpio_en_17_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_17_wd = reg_wdata[17]; + + assign gpio_en_gpio_en_18_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_18_wd = reg_wdata[18]; + + assign gpio_en_gpio_en_19_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_19_wd = reg_wdata[19]; + + assign gpio_en_gpio_en_20_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_20_wd = reg_wdata[20]; + + assign gpio_en_gpio_en_21_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_21_wd = reg_wdata[21]; + + assign gpio_en_gpio_en_22_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_22_wd = reg_wdata[22]; + + assign gpio_en_gpio_en_23_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_23_wd = reg_wdata[23]; + + assign gpio_en_gpio_en_24_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_24_wd = reg_wdata[24]; + + assign gpio_en_gpio_en_25_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_25_wd = reg_wdata[25]; + + assign gpio_en_gpio_en_26_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_26_wd = reg_wdata[26]; + + assign gpio_en_gpio_en_27_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_27_wd = reg_wdata[27]; + + assign gpio_en_gpio_en_28_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_28_wd = reg_wdata[28]; + + assign gpio_en_gpio_en_29_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_29_wd = reg_wdata[29]; + + assign gpio_en_gpio_en_30_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_30_wd = reg_wdata[30]; + + assign gpio_en_gpio_en_31_we = addr_hit[4] & reg_we & !reg_error; + assign gpio_en_gpio_en_31_wd = reg_wdata[31]; + + assign gpio_in_gpio_in_0_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_1_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_2_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_3_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_4_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_5_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_6_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_7_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_8_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_9_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_10_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_11_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_12_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_13_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_14_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_15_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_16_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_17_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_18_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_19_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_20_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_21_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_22_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_23_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_24_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_25_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_26_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_27_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_28_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_29_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_30_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_in_gpio_in_31_re = addr_hit[5] & reg_re & !reg_error; + + assign gpio_out_gpio_out_0_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_0_wd = reg_wdata[0]; + + assign gpio_out_gpio_out_1_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_1_wd = reg_wdata[1]; + + assign gpio_out_gpio_out_2_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_2_wd = reg_wdata[2]; + + assign gpio_out_gpio_out_3_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_3_wd = reg_wdata[3]; + + assign gpio_out_gpio_out_4_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_4_wd = reg_wdata[4]; + + assign gpio_out_gpio_out_5_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_5_wd = reg_wdata[5]; + + assign gpio_out_gpio_out_6_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_6_wd = reg_wdata[6]; + + assign gpio_out_gpio_out_7_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_7_wd = reg_wdata[7]; + + assign gpio_out_gpio_out_8_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_8_wd = reg_wdata[8]; + + assign gpio_out_gpio_out_9_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_9_wd = reg_wdata[9]; + + assign gpio_out_gpio_out_10_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_10_wd = reg_wdata[10]; + + assign gpio_out_gpio_out_11_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_11_wd = reg_wdata[11]; + + assign gpio_out_gpio_out_12_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_12_wd = reg_wdata[12]; + + assign gpio_out_gpio_out_13_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_13_wd = reg_wdata[13]; + + assign gpio_out_gpio_out_14_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_14_wd = reg_wdata[14]; + + assign gpio_out_gpio_out_15_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_15_wd = reg_wdata[15]; + + assign gpio_out_gpio_out_16_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_16_wd = reg_wdata[16]; + + assign gpio_out_gpio_out_17_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_17_wd = reg_wdata[17]; + + assign gpio_out_gpio_out_18_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_18_wd = reg_wdata[18]; + + assign gpio_out_gpio_out_19_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_19_wd = reg_wdata[19]; + + assign gpio_out_gpio_out_20_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_20_wd = reg_wdata[20]; + + assign gpio_out_gpio_out_21_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_21_wd = reg_wdata[21]; + + assign gpio_out_gpio_out_22_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_22_wd = reg_wdata[22]; + + assign gpio_out_gpio_out_23_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_23_wd = reg_wdata[23]; + + assign gpio_out_gpio_out_24_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_24_wd = reg_wdata[24]; + + assign gpio_out_gpio_out_25_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_25_wd = reg_wdata[25]; + + assign gpio_out_gpio_out_26_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_26_wd = reg_wdata[26]; + + assign gpio_out_gpio_out_27_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_27_wd = reg_wdata[27]; + + assign gpio_out_gpio_out_28_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_28_wd = reg_wdata[28]; + + assign gpio_out_gpio_out_29_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_29_wd = reg_wdata[29]; + + assign gpio_out_gpio_out_30_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_30_wd = reg_wdata[30]; + + assign gpio_out_gpio_out_31_we = addr_hit[6] & reg_we & !reg_error; + assign gpio_out_gpio_out_31_wd = reg_wdata[31]; + + assign gpio_set_gpio_set_0_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_0_wd = reg_wdata[0]; + + assign gpio_set_gpio_set_1_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_1_wd = reg_wdata[1]; + + assign gpio_set_gpio_set_2_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_2_wd = reg_wdata[2]; + + assign gpio_set_gpio_set_3_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_3_wd = reg_wdata[3]; + + assign gpio_set_gpio_set_4_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_4_wd = reg_wdata[4]; + + assign gpio_set_gpio_set_5_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_5_wd = reg_wdata[5]; + + assign gpio_set_gpio_set_6_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_6_wd = reg_wdata[6]; + + assign gpio_set_gpio_set_7_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_7_wd = reg_wdata[7]; + + assign gpio_set_gpio_set_8_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_8_wd = reg_wdata[8]; + + assign gpio_set_gpio_set_9_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_9_wd = reg_wdata[9]; + + assign gpio_set_gpio_set_10_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_10_wd = reg_wdata[10]; + + assign gpio_set_gpio_set_11_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_11_wd = reg_wdata[11]; + + assign gpio_set_gpio_set_12_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_12_wd = reg_wdata[12]; + + assign gpio_set_gpio_set_13_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_13_wd = reg_wdata[13]; + + assign gpio_set_gpio_set_14_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_14_wd = reg_wdata[14]; + + assign gpio_set_gpio_set_15_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_15_wd = reg_wdata[15]; + + assign gpio_set_gpio_set_16_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_16_wd = reg_wdata[16]; + + assign gpio_set_gpio_set_17_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_17_wd = reg_wdata[17]; + + assign gpio_set_gpio_set_18_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_18_wd = reg_wdata[18]; + + assign gpio_set_gpio_set_19_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_19_wd = reg_wdata[19]; + + assign gpio_set_gpio_set_20_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_20_wd = reg_wdata[20]; + + assign gpio_set_gpio_set_21_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_21_wd = reg_wdata[21]; + + assign gpio_set_gpio_set_22_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_22_wd = reg_wdata[22]; + + assign gpio_set_gpio_set_23_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_23_wd = reg_wdata[23]; + + assign gpio_set_gpio_set_24_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_24_wd = reg_wdata[24]; + + assign gpio_set_gpio_set_25_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_25_wd = reg_wdata[25]; + + assign gpio_set_gpio_set_26_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_26_wd = reg_wdata[26]; + + assign gpio_set_gpio_set_27_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_27_wd = reg_wdata[27]; + + assign gpio_set_gpio_set_28_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_28_wd = reg_wdata[28]; + + assign gpio_set_gpio_set_29_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_29_wd = reg_wdata[29]; + + assign gpio_set_gpio_set_30_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_30_wd = reg_wdata[30]; + + assign gpio_set_gpio_set_31_we = addr_hit[7] & reg_we & !reg_error; + assign gpio_set_gpio_set_31_wd = reg_wdata[31]; + + assign gpio_clear_gpio_clear_0_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_0_wd = reg_wdata[0]; + + assign gpio_clear_gpio_clear_1_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_1_wd = reg_wdata[1]; + + assign gpio_clear_gpio_clear_2_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_2_wd = reg_wdata[2]; + + assign gpio_clear_gpio_clear_3_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_3_wd = reg_wdata[3]; + + assign gpio_clear_gpio_clear_4_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_4_wd = reg_wdata[4]; + + assign gpio_clear_gpio_clear_5_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_5_wd = reg_wdata[5]; + + assign gpio_clear_gpio_clear_6_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_6_wd = reg_wdata[6]; + + assign gpio_clear_gpio_clear_7_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_7_wd = reg_wdata[7]; + + assign gpio_clear_gpio_clear_8_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_8_wd = reg_wdata[8]; + + assign gpio_clear_gpio_clear_9_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_9_wd = reg_wdata[9]; + + assign gpio_clear_gpio_clear_10_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_10_wd = reg_wdata[10]; + + assign gpio_clear_gpio_clear_11_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_11_wd = reg_wdata[11]; + + assign gpio_clear_gpio_clear_12_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_12_wd = reg_wdata[12]; + + assign gpio_clear_gpio_clear_13_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_13_wd = reg_wdata[13]; + + assign gpio_clear_gpio_clear_14_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_14_wd = reg_wdata[14]; + + assign gpio_clear_gpio_clear_15_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_15_wd = reg_wdata[15]; + + assign gpio_clear_gpio_clear_16_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_16_wd = reg_wdata[16]; + + assign gpio_clear_gpio_clear_17_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_17_wd = reg_wdata[17]; + + assign gpio_clear_gpio_clear_18_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_18_wd = reg_wdata[18]; + + assign gpio_clear_gpio_clear_19_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_19_wd = reg_wdata[19]; + + assign gpio_clear_gpio_clear_20_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_20_wd = reg_wdata[20]; + + assign gpio_clear_gpio_clear_21_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_21_wd = reg_wdata[21]; + + assign gpio_clear_gpio_clear_22_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_22_wd = reg_wdata[22]; + + assign gpio_clear_gpio_clear_23_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_23_wd = reg_wdata[23]; + + assign gpio_clear_gpio_clear_24_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_24_wd = reg_wdata[24]; + + assign gpio_clear_gpio_clear_25_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_25_wd = reg_wdata[25]; + + assign gpio_clear_gpio_clear_26_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_26_wd = reg_wdata[26]; + + assign gpio_clear_gpio_clear_27_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_27_wd = reg_wdata[27]; + + assign gpio_clear_gpio_clear_28_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_28_wd = reg_wdata[28]; + + assign gpio_clear_gpio_clear_29_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_29_wd = reg_wdata[29]; + + assign gpio_clear_gpio_clear_30_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_30_wd = reg_wdata[30]; + + assign gpio_clear_gpio_clear_31_we = addr_hit[8] & reg_we & !reg_error; + assign gpio_clear_gpio_clear_31_wd = reg_wdata[31]; + + assign gpio_toggle_gpio_toggle_0_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_0_wd = reg_wdata[0]; + + assign gpio_toggle_gpio_toggle_1_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_1_wd = reg_wdata[1]; + + assign gpio_toggle_gpio_toggle_2_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_2_wd = reg_wdata[2]; + + assign gpio_toggle_gpio_toggle_3_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_3_wd = reg_wdata[3]; + + assign gpio_toggle_gpio_toggle_4_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_4_wd = reg_wdata[4]; + + assign gpio_toggle_gpio_toggle_5_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_5_wd = reg_wdata[5]; + + assign gpio_toggle_gpio_toggle_6_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_6_wd = reg_wdata[6]; + + assign gpio_toggle_gpio_toggle_7_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_7_wd = reg_wdata[7]; + + assign gpio_toggle_gpio_toggle_8_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_8_wd = reg_wdata[8]; + + assign gpio_toggle_gpio_toggle_9_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_9_wd = reg_wdata[9]; + + assign gpio_toggle_gpio_toggle_10_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_10_wd = reg_wdata[10]; + + assign gpio_toggle_gpio_toggle_11_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_11_wd = reg_wdata[11]; + + assign gpio_toggle_gpio_toggle_12_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_12_wd = reg_wdata[12]; + + assign gpio_toggle_gpio_toggle_13_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_13_wd = reg_wdata[13]; + + assign gpio_toggle_gpio_toggle_14_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_14_wd = reg_wdata[14]; + + assign gpio_toggle_gpio_toggle_15_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_15_wd = reg_wdata[15]; + + assign gpio_toggle_gpio_toggle_16_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_16_wd = reg_wdata[16]; + + assign gpio_toggle_gpio_toggle_17_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_17_wd = reg_wdata[17]; + + assign gpio_toggle_gpio_toggle_18_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_18_wd = reg_wdata[18]; + + assign gpio_toggle_gpio_toggle_19_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_19_wd = reg_wdata[19]; + + assign gpio_toggle_gpio_toggle_20_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_20_wd = reg_wdata[20]; + + assign gpio_toggle_gpio_toggle_21_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_21_wd = reg_wdata[21]; + + assign gpio_toggle_gpio_toggle_22_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_22_wd = reg_wdata[22]; + + assign gpio_toggle_gpio_toggle_23_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_23_wd = reg_wdata[23]; + + assign gpio_toggle_gpio_toggle_24_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_24_wd = reg_wdata[24]; + + assign gpio_toggle_gpio_toggle_25_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_25_wd = reg_wdata[25]; + + assign gpio_toggle_gpio_toggle_26_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_26_wd = reg_wdata[26]; + + assign gpio_toggle_gpio_toggle_27_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_27_wd = reg_wdata[27]; + + assign gpio_toggle_gpio_toggle_28_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_28_wd = reg_wdata[28]; + + assign gpio_toggle_gpio_toggle_29_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_29_wd = reg_wdata[29]; + + assign gpio_toggle_gpio_toggle_30_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_30_wd = reg_wdata[30]; + + assign gpio_toggle_gpio_toggle_31_we = addr_hit[9] & reg_we & !reg_error; + assign gpio_toggle_gpio_toggle_31_wd = reg_wdata[31]; + + assign intrpt_rise_en_intrpt_rise_en_0_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_0_wd = reg_wdata[0]; + + assign intrpt_rise_en_intrpt_rise_en_1_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_1_wd = reg_wdata[1]; + + assign intrpt_rise_en_intrpt_rise_en_2_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_2_wd = reg_wdata[2]; + + assign intrpt_rise_en_intrpt_rise_en_3_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_3_wd = reg_wdata[3]; + + assign intrpt_rise_en_intrpt_rise_en_4_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_4_wd = reg_wdata[4]; + + assign intrpt_rise_en_intrpt_rise_en_5_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_5_wd = reg_wdata[5]; + + assign intrpt_rise_en_intrpt_rise_en_6_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_6_wd = reg_wdata[6]; + + assign intrpt_rise_en_intrpt_rise_en_7_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_7_wd = reg_wdata[7]; + + assign intrpt_rise_en_intrpt_rise_en_8_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_8_wd = reg_wdata[8]; + + assign intrpt_rise_en_intrpt_rise_en_9_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_9_wd = reg_wdata[9]; + + assign intrpt_rise_en_intrpt_rise_en_10_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_10_wd = reg_wdata[10]; + + assign intrpt_rise_en_intrpt_rise_en_11_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_11_wd = reg_wdata[11]; + + assign intrpt_rise_en_intrpt_rise_en_12_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_12_wd = reg_wdata[12]; + + assign intrpt_rise_en_intrpt_rise_en_13_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_13_wd = reg_wdata[13]; + + assign intrpt_rise_en_intrpt_rise_en_14_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_14_wd = reg_wdata[14]; + + assign intrpt_rise_en_intrpt_rise_en_15_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_15_wd = reg_wdata[15]; + + assign intrpt_rise_en_intrpt_rise_en_16_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_16_wd = reg_wdata[16]; + + assign intrpt_rise_en_intrpt_rise_en_17_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_17_wd = reg_wdata[17]; + + assign intrpt_rise_en_intrpt_rise_en_18_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_18_wd = reg_wdata[18]; + + assign intrpt_rise_en_intrpt_rise_en_19_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_19_wd = reg_wdata[19]; + + assign intrpt_rise_en_intrpt_rise_en_20_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_20_wd = reg_wdata[20]; + + assign intrpt_rise_en_intrpt_rise_en_21_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_21_wd = reg_wdata[21]; + + assign intrpt_rise_en_intrpt_rise_en_22_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_22_wd = reg_wdata[22]; + + assign intrpt_rise_en_intrpt_rise_en_23_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_23_wd = reg_wdata[23]; + + assign intrpt_rise_en_intrpt_rise_en_24_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_24_wd = reg_wdata[24]; + + assign intrpt_rise_en_intrpt_rise_en_25_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_25_wd = reg_wdata[25]; + + assign intrpt_rise_en_intrpt_rise_en_26_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_26_wd = reg_wdata[26]; + + assign intrpt_rise_en_intrpt_rise_en_27_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_27_wd = reg_wdata[27]; + + assign intrpt_rise_en_intrpt_rise_en_28_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_28_wd = reg_wdata[28]; + + assign intrpt_rise_en_intrpt_rise_en_29_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_29_wd = reg_wdata[29]; + + assign intrpt_rise_en_intrpt_rise_en_30_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_30_wd = reg_wdata[30]; + + assign intrpt_rise_en_intrpt_rise_en_31_we = addr_hit[10] & reg_we & !reg_error; + assign intrpt_rise_en_intrpt_rise_en_31_wd = reg_wdata[31]; + + assign intrpt_fall_en_intrpt_fall_en_0_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_0_wd = reg_wdata[0]; + + assign intrpt_fall_en_intrpt_fall_en_1_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_1_wd = reg_wdata[1]; + + assign intrpt_fall_en_intrpt_fall_en_2_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_2_wd = reg_wdata[2]; + + assign intrpt_fall_en_intrpt_fall_en_3_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_3_wd = reg_wdata[3]; + + assign intrpt_fall_en_intrpt_fall_en_4_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_4_wd = reg_wdata[4]; + + assign intrpt_fall_en_intrpt_fall_en_5_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_5_wd = reg_wdata[5]; + + assign intrpt_fall_en_intrpt_fall_en_6_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_6_wd = reg_wdata[6]; + + assign intrpt_fall_en_intrpt_fall_en_7_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_7_wd = reg_wdata[7]; + + assign intrpt_fall_en_intrpt_fall_en_8_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_8_wd = reg_wdata[8]; + + assign intrpt_fall_en_intrpt_fall_en_9_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_9_wd = reg_wdata[9]; + + assign intrpt_fall_en_intrpt_fall_en_10_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_10_wd = reg_wdata[10]; + + assign intrpt_fall_en_intrpt_fall_en_11_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_11_wd = reg_wdata[11]; + + assign intrpt_fall_en_intrpt_fall_en_12_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_12_wd = reg_wdata[12]; + + assign intrpt_fall_en_intrpt_fall_en_13_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_13_wd = reg_wdata[13]; + + assign intrpt_fall_en_intrpt_fall_en_14_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_14_wd = reg_wdata[14]; + + assign intrpt_fall_en_intrpt_fall_en_15_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_15_wd = reg_wdata[15]; + + assign intrpt_fall_en_intrpt_fall_en_16_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_16_wd = reg_wdata[16]; + + assign intrpt_fall_en_intrpt_fall_en_17_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_17_wd = reg_wdata[17]; + + assign intrpt_fall_en_intrpt_fall_en_18_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_18_wd = reg_wdata[18]; + + assign intrpt_fall_en_intrpt_fall_en_19_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_19_wd = reg_wdata[19]; + + assign intrpt_fall_en_intrpt_fall_en_20_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_20_wd = reg_wdata[20]; + + assign intrpt_fall_en_intrpt_fall_en_21_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_21_wd = reg_wdata[21]; + + assign intrpt_fall_en_intrpt_fall_en_22_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_22_wd = reg_wdata[22]; + + assign intrpt_fall_en_intrpt_fall_en_23_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_23_wd = reg_wdata[23]; + + assign intrpt_fall_en_intrpt_fall_en_24_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_24_wd = reg_wdata[24]; + + assign intrpt_fall_en_intrpt_fall_en_25_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_25_wd = reg_wdata[25]; + + assign intrpt_fall_en_intrpt_fall_en_26_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_26_wd = reg_wdata[26]; + + assign intrpt_fall_en_intrpt_fall_en_27_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_27_wd = reg_wdata[27]; + + assign intrpt_fall_en_intrpt_fall_en_28_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_28_wd = reg_wdata[28]; + + assign intrpt_fall_en_intrpt_fall_en_29_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_29_wd = reg_wdata[29]; + + assign intrpt_fall_en_intrpt_fall_en_30_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_30_wd = reg_wdata[30]; + + assign intrpt_fall_en_intrpt_fall_en_31_we = addr_hit[11] & reg_we & !reg_error; + assign intrpt_fall_en_intrpt_fall_en_31_wd = reg_wdata[31]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_0_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_0_wd = reg_wdata[0]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_1_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_1_wd = reg_wdata[1]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_2_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_2_wd = reg_wdata[2]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_3_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_3_wd = reg_wdata[3]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_4_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_4_wd = reg_wdata[4]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_5_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_5_wd = reg_wdata[5]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_6_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_6_wd = reg_wdata[6]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_7_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_7_wd = reg_wdata[7]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_8_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_8_wd = reg_wdata[8]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_9_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_9_wd = reg_wdata[9]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_10_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_10_wd = reg_wdata[10]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_11_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_11_wd = reg_wdata[11]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_12_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_12_wd = reg_wdata[12]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_13_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_13_wd = reg_wdata[13]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_14_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_14_wd = reg_wdata[14]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_15_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_15_wd = reg_wdata[15]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_16_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_16_wd = reg_wdata[16]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_17_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_17_wd = reg_wdata[17]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_18_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_18_wd = reg_wdata[18]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_19_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_19_wd = reg_wdata[19]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_20_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_20_wd = reg_wdata[20]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_21_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_21_wd = reg_wdata[21]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_22_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_22_wd = reg_wdata[22]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_23_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_23_wd = reg_wdata[23]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_24_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_24_wd = reg_wdata[24]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_25_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_25_wd = reg_wdata[25]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_26_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_26_wd = reg_wdata[26]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_27_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_27_wd = reg_wdata[27]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_28_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_28_wd = reg_wdata[28]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_29_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_29_wd = reg_wdata[29]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_30_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_30_wd = reg_wdata[30]; + + assign intrpt_lvl_high_en_intrpt_lvl_high_en_31_we = addr_hit[12] & reg_we & !reg_error; + assign intrpt_lvl_high_en_intrpt_lvl_high_en_31_wd = reg_wdata[31]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_0_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_0_wd = reg_wdata[0]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_1_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_1_wd = reg_wdata[1]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_2_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_2_wd = reg_wdata[2]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_3_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_3_wd = reg_wdata[3]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_4_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_4_wd = reg_wdata[4]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_5_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_5_wd = reg_wdata[5]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_6_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_6_wd = reg_wdata[6]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_7_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_7_wd = reg_wdata[7]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_8_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_8_wd = reg_wdata[8]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_9_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_9_wd = reg_wdata[9]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_10_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_10_wd = reg_wdata[10]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_11_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_11_wd = reg_wdata[11]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_12_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_12_wd = reg_wdata[12]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_13_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_13_wd = reg_wdata[13]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_14_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_14_wd = reg_wdata[14]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_15_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_15_wd = reg_wdata[15]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_16_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_16_wd = reg_wdata[16]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_17_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_17_wd = reg_wdata[17]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_18_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_18_wd = reg_wdata[18]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_19_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_19_wd = reg_wdata[19]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_20_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_20_wd = reg_wdata[20]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_21_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_21_wd = reg_wdata[21]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_22_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_22_wd = reg_wdata[22]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_23_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_23_wd = reg_wdata[23]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_24_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_24_wd = reg_wdata[24]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_25_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_25_wd = reg_wdata[25]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_26_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_26_wd = reg_wdata[26]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_27_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_27_wd = reg_wdata[27]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_28_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_28_wd = reg_wdata[28]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_29_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_29_wd = reg_wdata[29]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_30_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_30_wd = reg_wdata[30]; + + assign intrpt_lvl_low_en_intrpt_lvl_low_en_31_we = addr_hit[13] & reg_we & !reg_error; + assign intrpt_lvl_low_en_intrpt_lvl_low_en_31_wd = reg_wdata[31]; + + assign intrpt_status_intrpt_status_0_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_0_wd = reg_wdata[0]; + assign intrpt_status_intrpt_status_0_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_1_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_1_wd = reg_wdata[1]; + assign intrpt_status_intrpt_status_1_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_2_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_2_wd = reg_wdata[2]; + assign intrpt_status_intrpt_status_2_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_3_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_3_wd = reg_wdata[3]; + assign intrpt_status_intrpt_status_3_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_4_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_4_wd = reg_wdata[4]; + assign intrpt_status_intrpt_status_4_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_5_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_5_wd = reg_wdata[5]; + assign intrpt_status_intrpt_status_5_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_6_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_6_wd = reg_wdata[6]; + assign intrpt_status_intrpt_status_6_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_7_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_7_wd = reg_wdata[7]; + assign intrpt_status_intrpt_status_7_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_8_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_8_wd = reg_wdata[8]; + assign intrpt_status_intrpt_status_8_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_9_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_9_wd = reg_wdata[9]; + assign intrpt_status_intrpt_status_9_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_10_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_10_wd = reg_wdata[10]; + assign intrpt_status_intrpt_status_10_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_11_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_11_wd = reg_wdata[11]; + assign intrpt_status_intrpt_status_11_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_12_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_12_wd = reg_wdata[12]; + assign intrpt_status_intrpt_status_12_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_13_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_13_wd = reg_wdata[13]; + assign intrpt_status_intrpt_status_13_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_14_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_14_wd = reg_wdata[14]; + assign intrpt_status_intrpt_status_14_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_15_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_15_wd = reg_wdata[15]; + assign intrpt_status_intrpt_status_15_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_16_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_16_wd = reg_wdata[16]; + assign intrpt_status_intrpt_status_16_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_17_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_17_wd = reg_wdata[17]; + assign intrpt_status_intrpt_status_17_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_18_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_18_wd = reg_wdata[18]; + assign intrpt_status_intrpt_status_18_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_19_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_19_wd = reg_wdata[19]; + assign intrpt_status_intrpt_status_19_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_20_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_20_wd = reg_wdata[20]; + assign intrpt_status_intrpt_status_20_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_21_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_21_wd = reg_wdata[21]; + assign intrpt_status_intrpt_status_21_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_22_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_22_wd = reg_wdata[22]; + assign intrpt_status_intrpt_status_22_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_23_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_23_wd = reg_wdata[23]; + assign intrpt_status_intrpt_status_23_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_24_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_24_wd = reg_wdata[24]; + assign intrpt_status_intrpt_status_24_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_25_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_25_wd = reg_wdata[25]; + assign intrpt_status_intrpt_status_25_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_26_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_26_wd = reg_wdata[26]; + assign intrpt_status_intrpt_status_26_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_27_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_27_wd = reg_wdata[27]; + assign intrpt_status_intrpt_status_27_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_28_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_28_wd = reg_wdata[28]; + assign intrpt_status_intrpt_status_28_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_29_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_29_wd = reg_wdata[29]; + assign intrpt_status_intrpt_status_29_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_30_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_30_wd = reg_wdata[30]; + assign intrpt_status_intrpt_status_30_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_status_intrpt_status_31_we = addr_hit[14] & reg_we & !reg_error; + assign intrpt_status_intrpt_status_31_wd = reg_wdata[31]; + assign intrpt_status_intrpt_status_31_re = addr_hit[14] & reg_re & !reg_error; + + assign intrpt_rise_status_intrpt_rise_status_0_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_0_wd = reg_wdata[0]; + + assign intrpt_rise_status_intrpt_rise_status_1_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_1_wd = reg_wdata[1]; + + assign intrpt_rise_status_intrpt_rise_status_2_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_2_wd = reg_wdata[2]; + + assign intrpt_rise_status_intrpt_rise_status_3_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_3_wd = reg_wdata[3]; + + assign intrpt_rise_status_intrpt_rise_status_4_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_4_wd = reg_wdata[4]; + + assign intrpt_rise_status_intrpt_rise_status_5_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_5_wd = reg_wdata[5]; + + assign intrpt_rise_status_intrpt_rise_status_6_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_6_wd = reg_wdata[6]; + + assign intrpt_rise_status_intrpt_rise_status_7_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_7_wd = reg_wdata[7]; + + assign intrpt_rise_status_intrpt_rise_status_8_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_8_wd = reg_wdata[8]; + + assign intrpt_rise_status_intrpt_rise_status_9_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_9_wd = reg_wdata[9]; + + assign intrpt_rise_status_intrpt_rise_status_10_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_10_wd = reg_wdata[10]; + + assign intrpt_rise_status_intrpt_rise_status_11_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_11_wd = reg_wdata[11]; + + assign intrpt_rise_status_intrpt_rise_status_12_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_12_wd = reg_wdata[12]; + + assign intrpt_rise_status_intrpt_rise_status_13_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_13_wd = reg_wdata[13]; + + assign intrpt_rise_status_intrpt_rise_status_14_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_14_wd = reg_wdata[14]; + + assign intrpt_rise_status_intrpt_rise_status_15_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_15_wd = reg_wdata[15]; + + assign intrpt_rise_status_intrpt_rise_status_16_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_16_wd = reg_wdata[16]; + + assign intrpt_rise_status_intrpt_rise_status_17_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_17_wd = reg_wdata[17]; + + assign intrpt_rise_status_intrpt_rise_status_18_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_18_wd = reg_wdata[18]; + + assign intrpt_rise_status_intrpt_rise_status_19_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_19_wd = reg_wdata[19]; + + assign intrpt_rise_status_intrpt_rise_status_20_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_20_wd = reg_wdata[20]; + + assign intrpt_rise_status_intrpt_rise_status_21_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_21_wd = reg_wdata[21]; + + assign intrpt_rise_status_intrpt_rise_status_22_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_22_wd = reg_wdata[22]; + + assign intrpt_rise_status_intrpt_rise_status_23_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_23_wd = reg_wdata[23]; + + assign intrpt_rise_status_intrpt_rise_status_24_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_24_wd = reg_wdata[24]; + + assign intrpt_rise_status_intrpt_rise_status_25_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_25_wd = reg_wdata[25]; + + assign intrpt_rise_status_intrpt_rise_status_26_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_26_wd = reg_wdata[26]; + + assign intrpt_rise_status_intrpt_rise_status_27_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_27_wd = reg_wdata[27]; + + assign intrpt_rise_status_intrpt_rise_status_28_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_28_wd = reg_wdata[28]; + + assign intrpt_rise_status_intrpt_rise_status_29_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_29_wd = reg_wdata[29]; + + assign intrpt_rise_status_intrpt_rise_status_30_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_30_wd = reg_wdata[30]; + + assign intrpt_rise_status_intrpt_rise_status_31_we = addr_hit[15] & reg_we & !reg_error; + assign intrpt_rise_status_intrpt_rise_status_31_wd = reg_wdata[31]; + + assign intrpt_fall_status_intrpt_fall_status_0_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_0_wd = reg_wdata[0]; + + assign intrpt_fall_status_intrpt_fall_status_1_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_1_wd = reg_wdata[1]; + + assign intrpt_fall_status_intrpt_fall_status_2_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_2_wd = reg_wdata[2]; + + assign intrpt_fall_status_intrpt_fall_status_3_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_3_wd = reg_wdata[3]; + + assign intrpt_fall_status_intrpt_fall_status_4_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_4_wd = reg_wdata[4]; + + assign intrpt_fall_status_intrpt_fall_status_5_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_5_wd = reg_wdata[5]; + + assign intrpt_fall_status_intrpt_fall_status_6_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_6_wd = reg_wdata[6]; + + assign intrpt_fall_status_intrpt_fall_status_7_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_7_wd = reg_wdata[7]; + + assign intrpt_fall_status_intrpt_fall_status_8_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_8_wd = reg_wdata[8]; + + assign intrpt_fall_status_intrpt_fall_status_9_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_9_wd = reg_wdata[9]; + + assign intrpt_fall_status_intrpt_fall_status_10_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_10_wd = reg_wdata[10]; + + assign intrpt_fall_status_intrpt_fall_status_11_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_11_wd = reg_wdata[11]; + + assign intrpt_fall_status_intrpt_fall_status_12_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_12_wd = reg_wdata[12]; + + assign intrpt_fall_status_intrpt_fall_status_13_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_13_wd = reg_wdata[13]; + + assign intrpt_fall_status_intrpt_fall_status_14_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_14_wd = reg_wdata[14]; + + assign intrpt_fall_status_intrpt_fall_status_15_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_15_wd = reg_wdata[15]; + + assign intrpt_fall_status_intrpt_fall_status_16_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_16_wd = reg_wdata[16]; + + assign intrpt_fall_status_intrpt_fall_status_17_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_17_wd = reg_wdata[17]; + + assign intrpt_fall_status_intrpt_fall_status_18_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_18_wd = reg_wdata[18]; + + assign intrpt_fall_status_intrpt_fall_status_19_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_19_wd = reg_wdata[19]; + + assign intrpt_fall_status_intrpt_fall_status_20_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_20_wd = reg_wdata[20]; + + assign intrpt_fall_status_intrpt_fall_status_21_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_21_wd = reg_wdata[21]; + + assign intrpt_fall_status_intrpt_fall_status_22_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_22_wd = reg_wdata[22]; + + assign intrpt_fall_status_intrpt_fall_status_23_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_23_wd = reg_wdata[23]; + + assign intrpt_fall_status_intrpt_fall_status_24_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_24_wd = reg_wdata[24]; + + assign intrpt_fall_status_intrpt_fall_status_25_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_25_wd = reg_wdata[25]; + + assign intrpt_fall_status_intrpt_fall_status_26_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_26_wd = reg_wdata[26]; + + assign intrpt_fall_status_intrpt_fall_status_27_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_27_wd = reg_wdata[27]; + + assign intrpt_fall_status_intrpt_fall_status_28_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_28_wd = reg_wdata[28]; + + assign intrpt_fall_status_intrpt_fall_status_29_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_29_wd = reg_wdata[29]; + + assign intrpt_fall_status_intrpt_fall_status_30_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_30_wd = reg_wdata[30]; + + assign intrpt_fall_status_intrpt_fall_status_31_we = addr_hit[16] & reg_we & !reg_error; + assign intrpt_fall_status_intrpt_fall_status_31_wd = reg_wdata[31]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_0_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_0_wd = reg_wdata[0]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_1_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_1_wd = reg_wdata[1]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_2_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_2_wd = reg_wdata[2]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_3_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_3_wd = reg_wdata[3]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_4_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_4_wd = reg_wdata[4]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_5_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_5_wd = reg_wdata[5]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_6_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_6_wd = reg_wdata[6]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_7_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_7_wd = reg_wdata[7]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_8_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_8_wd = reg_wdata[8]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_9_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_9_wd = reg_wdata[9]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_10_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_10_wd = reg_wdata[10]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_11_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_11_wd = reg_wdata[11]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_12_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_12_wd = reg_wdata[12]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_13_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_13_wd = reg_wdata[13]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_14_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_14_wd = reg_wdata[14]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_15_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_15_wd = reg_wdata[15]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_16_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_16_wd = reg_wdata[16]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_17_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_17_wd = reg_wdata[17]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_18_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_18_wd = reg_wdata[18]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_19_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_19_wd = reg_wdata[19]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_20_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_20_wd = reg_wdata[20]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_21_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_21_wd = reg_wdata[21]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_22_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_22_wd = reg_wdata[22]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_23_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_23_wd = reg_wdata[23]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_24_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_24_wd = reg_wdata[24]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_25_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_25_wd = reg_wdata[25]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_26_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_26_wd = reg_wdata[26]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_27_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_27_wd = reg_wdata[27]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_28_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_28_wd = reg_wdata[28]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_29_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_29_wd = reg_wdata[29]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_30_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_30_wd = reg_wdata[30]; + + assign intrpt_lvl_high_status_intrpt_lvl_high_status_31_we = addr_hit[17] & reg_we & !reg_error; + assign intrpt_lvl_high_status_intrpt_lvl_high_status_31_wd = reg_wdata[31]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_0_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_0_wd = reg_wdata[0]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_1_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_1_wd = reg_wdata[1]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_2_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_2_wd = reg_wdata[2]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_3_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_3_wd = reg_wdata[3]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_4_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_4_wd = reg_wdata[4]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_5_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_5_wd = reg_wdata[5]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_6_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_6_wd = reg_wdata[6]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_7_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_7_wd = reg_wdata[7]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_8_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_8_wd = reg_wdata[8]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_9_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_9_wd = reg_wdata[9]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_10_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_10_wd = reg_wdata[10]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_11_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_11_wd = reg_wdata[11]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_12_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_12_wd = reg_wdata[12]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_13_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_13_wd = reg_wdata[13]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_14_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_14_wd = reg_wdata[14]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_15_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_15_wd = reg_wdata[15]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_16_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_16_wd = reg_wdata[16]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_17_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_17_wd = reg_wdata[17]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_18_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_18_wd = reg_wdata[18]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_19_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_19_wd = reg_wdata[19]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_20_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_20_wd = reg_wdata[20]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_21_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_21_wd = reg_wdata[21]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_22_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_22_wd = reg_wdata[22]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_23_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_23_wd = reg_wdata[23]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_24_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_24_wd = reg_wdata[24]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_25_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_25_wd = reg_wdata[25]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_26_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_26_wd = reg_wdata[26]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_27_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_27_wd = reg_wdata[27]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_28_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_28_wd = reg_wdata[28]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_29_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_29_wd = reg_wdata[29]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_30_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_30_wd = reg_wdata[30]; + + assign intrpt_lvl_low_status_intrpt_lvl_low_status_31_we = addr_hit[18] & reg_we & !reg_error; + assign intrpt_lvl_low_status_intrpt_lvl_low_status_31_wd = reg_wdata[31]; + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[9:0] = info_gpio_cnt_qs; + reg_rdata_next[19:10] = info_version_qs; + end + + addr_hit[1]: begin + reg_rdata_next[0] = cfg_intrpt_mode_qs; + reg_rdata_next[1] = cfg_reserved_qs; + end + + addr_hit[2]: begin + reg_rdata_next[1:0] = gpio_mode_0_mode_0_qs; + reg_rdata_next[3:2] = gpio_mode_0_mode_1_qs; + reg_rdata_next[5:4] = gpio_mode_0_mode_2_qs; + reg_rdata_next[7:6] = gpio_mode_0_mode_3_qs; + reg_rdata_next[9:8] = gpio_mode_0_mode_4_qs; + reg_rdata_next[11:10] = gpio_mode_0_mode_5_qs; + reg_rdata_next[13:12] = gpio_mode_0_mode_6_qs; + reg_rdata_next[15:14] = gpio_mode_0_mode_7_qs; + reg_rdata_next[17:16] = gpio_mode_0_mode_8_qs; + reg_rdata_next[19:18] = gpio_mode_0_mode_9_qs; + reg_rdata_next[21:20] = gpio_mode_0_mode_10_qs; + reg_rdata_next[23:22] = gpio_mode_0_mode_11_qs; + reg_rdata_next[25:24] = gpio_mode_0_mode_12_qs; + reg_rdata_next[27:26] = gpio_mode_0_mode_13_qs; + reg_rdata_next[29:28] = gpio_mode_0_mode_14_qs; + reg_rdata_next[31:30] = gpio_mode_0_mode_15_qs; + end + + addr_hit[3]: begin + reg_rdata_next[1:0] = gpio_mode_1_mode_16_qs; + reg_rdata_next[3:2] = gpio_mode_1_mode_17_qs; + reg_rdata_next[5:4] = gpio_mode_1_mode_18_qs; + reg_rdata_next[7:6] = gpio_mode_1_mode_19_qs; + reg_rdata_next[9:8] = gpio_mode_1_mode_20_qs; + reg_rdata_next[11:10] = gpio_mode_1_mode_21_qs; + reg_rdata_next[13:12] = gpio_mode_1_mode_22_qs; + reg_rdata_next[15:14] = gpio_mode_1_mode_23_qs; + reg_rdata_next[17:16] = gpio_mode_1_mode_24_qs; + reg_rdata_next[19:18] = gpio_mode_1_mode_25_qs; + reg_rdata_next[21:20] = gpio_mode_1_mode_26_qs; + reg_rdata_next[23:22] = gpio_mode_1_mode_27_qs; + reg_rdata_next[25:24] = gpio_mode_1_mode_28_qs; + reg_rdata_next[27:26] = gpio_mode_1_mode_29_qs; + reg_rdata_next[29:28] = gpio_mode_1_mode_30_qs; + reg_rdata_next[31:30] = gpio_mode_1_mode_31_qs; + end + + addr_hit[4]: begin + reg_rdata_next[0] = gpio_en_gpio_en_0_qs; + reg_rdata_next[1] = gpio_en_gpio_en_1_qs; + reg_rdata_next[2] = gpio_en_gpio_en_2_qs; + reg_rdata_next[3] = gpio_en_gpio_en_3_qs; + reg_rdata_next[4] = gpio_en_gpio_en_4_qs; + reg_rdata_next[5] = gpio_en_gpio_en_5_qs; + reg_rdata_next[6] = gpio_en_gpio_en_6_qs; + reg_rdata_next[7] = gpio_en_gpio_en_7_qs; + reg_rdata_next[8] = gpio_en_gpio_en_8_qs; + reg_rdata_next[9] = gpio_en_gpio_en_9_qs; + reg_rdata_next[10] = gpio_en_gpio_en_10_qs; + reg_rdata_next[11] = gpio_en_gpio_en_11_qs; + reg_rdata_next[12] = gpio_en_gpio_en_12_qs; + reg_rdata_next[13] = gpio_en_gpio_en_13_qs; + reg_rdata_next[14] = gpio_en_gpio_en_14_qs; + reg_rdata_next[15] = gpio_en_gpio_en_15_qs; + reg_rdata_next[16] = gpio_en_gpio_en_16_qs; + reg_rdata_next[17] = gpio_en_gpio_en_17_qs; + reg_rdata_next[18] = gpio_en_gpio_en_18_qs; + reg_rdata_next[19] = gpio_en_gpio_en_19_qs; + reg_rdata_next[20] = gpio_en_gpio_en_20_qs; + reg_rdata_next[21] = gpio_en_gpio_en_21_qs; + reg_rdata_next[22] = gpio_en_gpio_en_22_qs; + reg_rdata_next[23] = gpio_en_gpio_en_23_qs; + reg_rdata_next[24] = gpio_en_gpio_en_24_qs; + reg_rdata_next[25] = gpio_en_gpio_en_25_qs; + reg_rdata_next[26] = gpio_en_gpio_en_26_qs; + reg_rdata_next[27] = gpio_en_gpio_en_27_qs; + reg_rdata_next[28] = gpio_en_gpio_en_28_qs; + reg_rdata_next[29] = gpio_en_gpio_en_29_qs; + reg_rdata_next[30] = gpio_en_gpio_en_30_qs; + reg_rdata_next[31] = gpio_en_gpio_en_31_qs; + end + + addr_hit[5]: begin + reg_rdata_next[0] = gpio_in_gpio_in_0_qs; + reg_rdata_next[1] = gpio_in_gpio_in_1_qs; + reg_rdata_next[2] = gpio_in_gpio_in_2_qs; + reg_rdata_next[3] = gpio_in_gpio_in_3_qs; + reg_rdata_next[4] = gpio_in_gpio_in_4_qs; + reg_rdata_next[5] = gpio_in_gpio_in_5_qs; + reg_rdata_next[6] = gpio_in_gpio_in_6_qs; + reg_rdata_next[7] = gpio_in_gpio_in_7_qs; + reg_rdata_next[8] = gpio_in_gpio_in_8_qs; + reg_rdata_next[9] = gpio_in_gpio_in_9_qs; + reg_rdata_next[10] = gpio_in_gpio_in_10_qs; + reg_rdata_next[11] = gpio_in_gpio_in_11_qs; + reg_rdata_next[12] = gpio_in_gpio_in_12_qs; + reg_rdata_next[13] = gpio_in_gpio_in_13_qs; + reg_rdata_next[14] = gpio_in_gpio_in_14_qs; + reg_rdata_next[15] = gpio_in_gpio_in_15_qs; + reg_rdata_next[16] = gpio_in_gpio_in_16_qs; + reg_rdata_next[17] = gpio_in_gpio_in_17_qs; + reg_rdata_next[18] = gpio_in_gpio_in_18_qs; + reg_rdata_next[19] = gpio_in_gpio_in_19_qs; + reg_rdata_next[20] = gpio_in_gpio_in_20_qs; + reg_rdata_next[21] = gpio_in_gpio_in_21_qs; + reg_rdata_next[22] = gpio_in_gpio_in_22_qs; + reg_rdata_next[23] = gpio_in_gpio_in_23_qs; + reg_rdata_next[24] = gpio_in_gpio_in_24_qs; + reg_rdata_next[25] = gpio_in_gpio_in_25_qs; + reg_rdata_next[26] = gpio_in_gpio_in_26_qs; + reg_rdata_next[27] = gpio_in_gpio_in_27_qs; + reg_rdata_next[28] = gpio_in_gpio_in_28_qs; + reg_rdata_next[29] = gpio_in_gpio_in_29_qs; + reg_rdata_next[30] = gpio_in_gpio_in_30_qs; + reg_rdata_next[31] = gpio_in_gpio_in_31_qs; + end + + addr_hit[6]: begin + reg_rdata_next[0] = gpio_out_gpio_out_0_qs; + reg_rdata_next[1] = gpio_out_gpio_out_1_qs; + reg_rdata_next[2] = gpio_out_gpio_out_2_qs; + reg_rdata_next[3] = gpio_out_gpio_out_3_qs; + reg_rdata_next[4] = gpio_out_gpio_out_4_qs; + reg_rdata_next[5] = gpio_out_gpio_out_5_qs; + reg_rdata_next[6] = gpio_out_gpio_out_6_qs; + reg_rdata_next[7] = gpio_out_gpio_out_7_qs; + reg_rdata_next[8] = gpio_out_gpio_out_8_qs; + reg_rdata_next[9] = gpio_out_gpio_out_9_qs; + reg_rdata_next[10] = gpio_out_gpio_out_10_qs; + reg_rdata_next[11] = gpio_out_gpio_out_11_qs; + reg_rdata_next[12] = gpio_out_gpio_out_12_qs; + reg_rdata_next[13] = gpio_out_gpio_out_13_qs; + reg_rdata_next[14] = gpio_out_gpio_out_14_qs; + reg_rdata_next[15] = gpio_out_gpio_out_15_qs; + reg_rdata_next[16] = gpio_out_gpio_out_16_qs; + reg_rdata_next[17] = gpio_out_gpio_out_17_qs; + reg_rdata_next[18] = gpio_out_gpio_out_18_qs; + reg_rdata_next[19] = gpio_out_gpio_out_19_qs; + reg_rdata_next[20] = gpio_out_gpio_out_20_qs; + reg_rdata_next[21] = gpio_out_gpio_out_21_qs; + reg_rdata_next[22] = gpio_out_gpio_out_22_qs; + reg_rdata_next[23] = gpio_out_gpio_out_23_qs; + reg_rdata_next[24] = gpio_out_gpio_out_24_qs; + reg_rdata_next[25] = gpio_out_gpio_out_25_qs; + reg_rdata_next[26] = gpio_out_gpio_out_26_qs; + reg_rdata_next[27] = gpio_out_gpio_out_27_qs; + reg_rdata_next[28] = gpio_out_gpio_out_28_qs; + reg_rdata_next[29] = gpio_out_gpio_out_29_qs; + reg_rdata_next[30] = gpio_out_gpio_out_30_qs; + reg_rdata_next[31] = gpio_out_gpio_out_31_qs; + end + + addr_hit[7]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + reg_rdata_next[2] = '0; + reg_rdata_next[3] = '0; + reg_rdata_next[4] = '0; + reg_rdata_next[5] = '0; + reg_rdata_next[6] = '0; + reg_rdata_next[7] = '0; + reg_rdata_next[8] = '0; + reg_rdata_next[9] = '0; + reg_rdata_next[10] = '0; + reg_rdata_next[11] = '0; + reg_rdata_next[12] = '0; + reg_rdata_next[13] = '0; + reg_rdata_next[14] = '0; + reg_rdata_next[15] = '0; + reg_rdata_next[16] = '0; + reg_rdata_next[17] = '0; + reg_rdata_next[18] = '0; + reg_rdata_next[19] = '0; + reg_rdata_next[20] = '0; + reg_rdata_next[21] = '0; + reg_rdata_next[22] = '0; + reg_rdata_next[23] = '0; + reg_rdata_next[24] = '0; + reg_rdata_next[25] = '0; + reg_rdata_next[26] = '0; + reg_rdata_next[27] = '0; + reg_rdata_next[28] = '0; + reg_rdata_next[29] = '0; + reg_rdata_next[30] = '0; + reg_rdata_next[31] = '0; + end + + addr_hit[8]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + reg_rdata_next[2] = '0; + reg_rdata_next[3] = '0; + reg_rdata_next[4] = '0; + reg_rdata_next[5] = '0; + reg_rdata_next[6] = '0; + reg_rdata_next[7] = '0; + reg_rdata_next[8] = '0; + reg_rdata_next[9] = '0; + reg_rdata_next[10] = '0; + reg_rdata_next[11] = '0; + reg_rdata_next[12] = '0; + reg_rdata_next[13] = '0; + reg_rdata_next[14] = '0; + reg_rdata_next[15] = '0; + reg_rdata_next[16] = '0; + reg_rdata_next[17] = '0; + reg_rdata_next[18] = '0; + reg_rdata_next[19] = '0; + reg_rdata_next[20] = '0; + reg_rdata_next[21] = '0; + reg_rdata_next[22] = '0; + reg_rdata_next[23] = '0; + reg_rdata_next[24] = '0; + reg_rdata_next[25] = '0; + reg_rdata_next[26] = '0; + reg_rdata_next[27] = '0; + reg_rdata_next[28] = '0; + reg_rdata_next[29] = '0; + reg_rdata_next[30] = '0; + reg_rdata_next[31] = '0; + end + + addr_hit[9]: begin + reg_rdata_next[0] = '0; + reg_rdata_next[1] = '0; + reg_rdata_next[2] = '0; + reg_rdata_next[3] = '0; + reg_rdata_next[4] = '0; + reg_rdata_next[5] = '0; + reg_rdata_next[6] = '0; + reg_rdata_next[7] = '0; + reg_rdata_next[8] = '0; + reg_rdata_next[9] = '0; + reg_rdata_next[10] = '0; + reg_rdata_next[11] = '0; + reg_rdata_next[12] = '0; + reg_rdata_next[13] = '0; + reg_rdata_next[14] = '0; + reg_rdata_next[15] = '0; + reg_rdata_next[16] = '0; + reg_rdata_next[17] = '0; + reg_rdata_next[18] = '0; + reg_rdata_next[19] = '0; + reg_rdata_next[20] = '0; + reg_rdata_next[21] = '0; + reg_rdata_next[22] = '0; + reg_rdata_next[23] = '0; + reg_rdata_next[24] = '0; + reg_rdata_next[25] = '0; + reg_rdata_next[26] = '0; + reg_rdata_next[27] = '0; + reg_rdata_next[28] = '0; + reg_rdata_next[29] = '0; + reg_rdata_next[30] = '0; + reg_rdata_next[31] = '0; + end + + addr_hit[10]: begin + reg_rdata_next[0] = intrpt_rise_en_intrpt_rise_en_0_qs; + reg_rdata_next[1] = intrpt_rise_en_intrpt_rise_en_1_qs; + reg_rdata_next[2] = intrpt_rise_en_intrpt_rise_en_2_qs; + reg_rdata_next[3] = intrpt_rise_en_intrpt_rise_en_3_qs; + reg_rdata_next[4] = intrpt_rise_en_intrpt_rise_en_4_qs; + reg_rdata_next[5] = intrpt_rise_en_intrpt_rise_en_5_qs; + reg_rdata_next[6] = intrpt_rise_en_intrpt_rise_en_6_qs; + reg_rdata_next[7] = intrpt_rise_en_intrpt_rise_en_7_qs; + reg_rdata_next[8] = intrpt_rise_en_intrpt_rise_en_8_qs; + reg_rdata_next[9] = intrpt_rise_en_intrpt_rise_en_9_qs; + reg_rdata_next[10] = intrpt_rise_en_intrpt_rise_en_10_qs; + reg_rdata_next[11] = intrpt_rise_en_intrpt_rise_en_11_qs; + reg_rdata_next[12] = intrpt_rise_en_intrpt_rise_en_12_qs; + reg_rdata_next[13] = intrpt_rise_en_intrpt_rise_en_13_qs; + reg_rdata_next[14] = intrpt_rise_en_intrpt_rise_en_14_qs; + reg_rdata_next[15] = intrpt_rise_en_intrpt_rise_en_15_qs; + reg_rdata_next[16] = intrpt_rise_en_intrpt_rise_en_16_qs; + reg_rdata_next[17] = intrpt_rise_en_intrpt_rise_en_17_qs; + reg_rdata_next[18] = intrpt_rise_en_intrpt_rise_en_18_qs; + reg_rdata_next[19] = intrpt_rise_en_intrpt_rise_en_19_qs; + reg_rdata_next[20] = intrpt_rise_en_intrpt_rise_en_20_qs; + reg_rdata_next[21] = intrpt_rise_en_intrpt_rise_en_21_qs; + reg_rdata_next[22] = intrpt_rise_en_intrpt_rise_en_22_qs; + reg_rdata_next[23] = intrpt_rise_en_intrpt_rise_en_23_qs; + reg_rdata_next[24] = intrpt_rise_en_intrpt_rise_en_24_qs; + reg_rdata_next[25] = intrpt_rise_en_intrpt_rise_en_25_qs; + reg_rdata_next[26] = intrpt_rise_en_intrpt_rise_en_26_qs; + reg_rdata_next[27] = intrpt_rise_en_intrpt_rise_en_27_qs; + reg_rdata_next[28] = intrpt_rise_en_intrpt_rise_en_28_qs; + reg_rdata_next[29] = intrpt_rise_en_intrpt_rise_en_29_qs; + reg_rdata_next[30] = intrpt_rise_en_intrpt_rise_en_30_qs; + reg_rdata_next[31] = intrpt_rise_en_intrpt_rise_en_31_qs; + end + + addr_hit[11]: begin + reg_rdata_next[0] = intrpt_fall_en_intrpt_fall_en_0_qs; + reg_rdata_next[1] = intrpt_fall_en_intrpt_fall_en_1_qs; + reg_rdata_next[2] = intrpt_fall_en_intrpt_fall_en_2_qs; + reg_rdata_next[3] = intrpt_fall_en_intrpt_fall_en_3_qs; + reg_rdata_next[4] = intrpt_fall_en_intrpt_fall_en_4_qs; + reg_rdata_next[5] = intrpt_fall_en_intrpt_fall_en_5_qs; + reg_rdata_next[6] = intrpt_fall_en_intrpt_fall_en_6_qs; + reg_rdata_next[7] = intrpt_fall_en_intrpt_fall_en_7_qs; + reg_rdata_next[8] = intrpt_fall_en_intrpt_fall_en_8_qs; + reg_rdata_next[9] = intrpt_fall_en_intrpt_fall_en_9_qs; + reg_rdata_next[10] = intrpt_fall_en_intrpt_fall_en_10_qs; + reg_rdata_next[11] = intrpt_fall_en_intrpt_fall_en_11_qs; + reg_rdata_next[12] = intrpt_fall_en_intrpt_fall_en_12_qs; + reg_rdata_next[13] = intrpt_fall_en_intrpt_fall_en_13_qs; + reg_rdata_next[14] = intrpt_fall_en_intrpt_fall_en_14_qs; + reg_rdata_next[15] = intrpt_fall_en_intrpt_fall_en_15_qs; + reg_rdata_next[16] = intrpt_fall_en_intrpt_fall_en_16_qs; + reg_rdata_next[17] = intrpt_fall_en_intrpt_fall_en_17_qs; + reg_rdata_next[18] = intrpt_fall_en_intrpt_fall_en_18_qs; + reg_rdata_next[19] = intrpt_fall_en_intrpt_fall_en_19_qs; + reg_rdata_next[20] = intrpt_fall_en_intrpt_fall_en_20_qs; + reg_rdata_next[21] = intrpt_fall_en_intrpt_fall_en_21_qs; + reg_rdata_next[22] = intrpt_fall_en_intrpt_fall_en_22_qs; + reg_rdata_next[23] = intrpt_fall_en_intrpt_fall_en_23_qs; + reg_rdata_next[24] = intrpt_fall_en_intrpt_fall_en_24_qs; + reg_rdata_next[25] = intrpt_fall_en_intrpt_fall_en_25_qs; + reg_rdata_next[26] = intrpt_fall_en_intrpt_fall_en_26_qs; + reg_rdata_next[27] = intrpt_fall_en_intrpt_fall_en_27_qs; + reg_rdata_next[28] = intrpt_fall_en_intrpt_fall_en_28_qs; + reg_rdata_next[29] = intrpt_fall_en_intrpt_fall_en_29_qs; + reg_rdata_next[30] = intrpt_fall_en_intrpt_fall_en_30_qs; + reg_rdata_next[31] = intrpt_fall_en_intrpt_fall_en_31_qs; + end + + addr_hit[12]: begin + reg_rdata_next[0] = intrpt_lvl_high_en_intrpt_lvl_high_en_0_qs; + reg_rdata_next[1] = intrpt_lvl_high_en_intrpt_lvl_high_en_1_qs; + reg_rdata_next[2] = intrpt_lvl_high_en_intrpt_lvl_high_en_2_qs; + reg_rdata_next[3] = intrpt_lvl_high_en_intrpt_lvl_high_en_3_qs; + reg_rdata_next[4] = intrpt_lvl_high_en_intrpt_lvl_high_en_4_qs; + reg_rdata_next[5] = intrpt_lvl_high_en_intrpt_lvl_high_en_5_qs; + reg_rdata_next[6] = intrpt_lvl_high_en_intrpt_lvl_high_en_6_qs; + reg_rdata_next[7] = intrpt_lvl_high_en_intrpt_lvl_high_en_7_qs; + reg_rdata_next[8] = intrpt_lvl_high_en_intrpt_lvl_high_en_8_qs; + reg_rdata_next[9] = intrpt_lvl_high_en_intrpt_lvl_high_en_9_qs; + reg_rdata_next[10] = intrpt_lvl_high_en_intrpt_lvl_high_en_10_qs; + reg_rdata_next[11] = intrpt_lvl_high_en_intrpt_lvl_high_en_11_qs; + reg_rdata_next[12] = intrpt_lvl_high_en_intrpt_lvl_high_en_12_qs; + reg_rdata_next[13] = intrpt_lvl_high_en_intrpt_lvl_high_en_13_qs; + reg_rdata_next[14] = intrpt_lvl_high_en_intrpt_lvl_high_en_14_qs; + reg_rdata_next[15] = intrpt_lvl_high_en_intrpt_lvl_high_en_15_qs; + reg_rdata_next[16] = intrpt_lvl_high_en_intrpt_lvl_high_en_16_qs; + reg_rdata_next[17] = intrpt_lvl_high_en_intrpt_lvl_high_en_17_qs; + reg_rdata_next[18] = intrpt_lvl_high_en_intrpt_lvl_high_en_18_qs; + reg_rdata_next[19] = intrpt_lvl_high_en_intrpt_lvl_high_en_19_qs; + reg_rdata_next[20] = intrpt_lvl_high_en_intrpt_lvl_high_en_20_qs; + reg_rdata_next[21] = intrpt_lvl_high_en_intrpt_lvl_high_en_21_qs; + reg_rdata_next[22] = intrpt_lvl_high_en_intrpt_lvl_high_en_22_qs; + reg_rdata_next[23] = intrpt_lvl_high_en_intrpt_lvl_high_en_23_qs; + reg_rdata_next[24] = intrpt_lvl_high_en_intrpt_lvl_high_en_24_qs; + reg_rdata_next[25] = intrpt_lvl_high_en_intrpt_lvl_high_en_25_qs; + reg_rdata_next[26] = intrpt_lvl_high_en_intrpt_lvl_high_en_26_qs; + reg_rdata_next[27] = intrpt_lvl_high_en_intrpt_lvl_high_en_27_qs; + reg_rdata_next[28] = intrpt_lvl_high_en_intrpt_lvl_high_en_28_qs; + reg_rdata_next[29] = intrpt_lvl_high_en_intrpt_lvl_high_en_29_qs; + reg_rdata_next[30] = intrpt_lvl_high_en_intrpt_lvl_high_en_30_qs; + reg_rdata_next[31] = intrpt_lvl_high_en_intrpt_lvl_high_en_31_qs; + end + + addr_hit[13]: begin + reg_rdata_next[0] = intrpt_lvl_low_en_intrpt_lvl_low_en_0_qs; + reg_rdata_next[1] = intrpt_lvl_low_en_intrpt_lvl_low_en_1_qs; + reg_rdata_next[2] = intrpt_lvl_low_en_intrpt_lvl_low_en_2_qs; + reg_rdata_next[3] = intrpt_lvl_low_en_intrpt_lvl_low_en_3_qs; + reg_rdata_next[4] = intrpt_lvl_low_en_intrpt_lvl_low_en_4_qs; + reg_rdata_next[5] = intrpt_lvl_low_en_intrpt_lvl_low_en_5_qs; + reg_rdata_next[6] = intrpt_lvl_low_en_intrpt_lvl_low_en_6_qs; + reg_rdata_next[7] = intrpt_lvl_low_en_intrpt_lvl_low_en_7_qs; + reg_rdata_next[8] = intrpt_lvl_low_en_intrpt_lvl_low_en_8_qs; + reg_rdata_next[9] = intrpt_lvl_low_en_intrpt_lvl_low_en_9_qs; + reg_rdata_next[10] = intrpt_lvl_low_en_intrpt_lvl_low_en_10_qs; + reg_rdata_next[11] = intrpt_lvl_low_en_intrpt_lvl_low_en_11_qs; + reg_rdata_next[12] = intrpt_lvl_low_en_intrpt_lvl_low_en_12_qs; + reg_rdata_next[13] = intrpt_lvl_low_en_intrpt_lvl_low_en_13_qs; + reg_rdata_next[14] = intrpt_lvl_low_en_intrpt_lvl_low_en_14_qs; + reg_rdata_next[15] = intrpt_lvl_low_en_intrpt_lvl_low_en_15_qs; + reg_rdata_next[16] = intrpt_lvl_low_en_intrpt_lvl_low_en_16_qs; + reg_rdata_next[17] = intrpt_lvl_low_en_intrpt_lvl_low_en_17_qs; + reg_rdata_next[18] = intrpt_lvl_low_en_intrpt_lvl_low_en_18_qs; + reg_rdata_next[19] = intrpt_lvl_low_en_intrpt_lvl_low_en_19_qs; + reg_rdata_next[20] = intrpt_lvl_low_en_intrpt_lvl_low_en_20_qs; + reg_rdata_next[21] = intrpt_lvl_low_en_intrpt_lvl_low_en_21_qs; + reg_rdata_next[22] = intrpt_lvl_low_en_intrpt_lvl_low_en_22_qs; + reg_rdata_next[23] = intrpt_lvl_low_en_intrpt_lvl_low_en_23_qs; + reg_rdata_next[24] = intrpt_lvl_low_en_intrpt_lvl_low_en_24_qs; + reg_rdata_next[25] = intrpt_lvl_low_en_intrpt_lvl_low_en_25_qs; + reg_rdata_next[26] = intrpt_lvl_low_en_intrpt_lvl_low_en_26_qs; + reg_rdata_next[27] = intrpt_lvl_low_en_intrpt_lvl_low_en_27_qs; + reg_rdata_next[28] = intrpt_lvl_low_en_intrpt_lvl_low_en_28_qs; + reg_rdata_next[29] = intrpt_lvl_low_en_intrpt_lvl_low_en_29_qs; + reg_rdata_next[30] = intrpt_lvl_low_en_intrpt_lvl_low_en_30_qs; + reg_rdata_next[31] = intrpt_lvl_low_en_intrpt_lvl_low_en_31_qs; + end + + addr_hit[14]: begin + reg_rdata_next[0] = intrpt_status_intrpt_status_0_qs; + reg_rdata_next[1] = intrpt_status_intrpt_status_1_qs; + reg_rdata_next[2] = intrpt_status_intrpt_status_2_qs; + reg_rdata_next[3] = intrpt_status_intrpt_status_3_qs; + reg_rdata_next[4] = intrpt_status_intrpt_status_4_qs; + reg_rdata_next[5] = intrpt_status_intrpt_status_5_qs; + reg_rdata_next[6] = intrpt_status_intrpt_status_6_qs; + reg_rdata_next[7] = intrpt_status_intrpt_status_7_qs; + reg_rdata_next[8] = intrpt_status_intrpt_status_8_qs; + reg_rdata_next[9] = intrpt_status_intrpt_status_9_qs; + reg_rdata_next[10] = intrpt_status_intrpt_status_10_qs; + reg_rdata_next[11] = intrpt_status_intrpt_status_11_qs; + reg_rdata_next[12] = intrpt_status_intrpt_status_12_qs; + reg_rdata_next[13] = intrpt_status_intrpt_status_13_qs; + reg_rdata_next[14] = intrpt_status_intrpt_status_14_qs; + reg_rdata_next[15] = intrpt_status_intrpt_status_15_qs; + reg_rdata_next[16] = intrpt_status_intrpt_status_16_qs; + reg_rdata_next[17] = intrpt_status_intrpt_status_17_qs; + reg_rdata_next[18] = intrpt_status_intrpt_status_18_qs; + reg_rdata_next[19] = intrpt_status_intrpt_status_19_qs; + reg_rdata_next[20] = intrpt_status_intrpt_status_20_qs; + reg_rdata_next[21] = intrpt_status_intrpt_status_21_qs; + reg_rdata_next[22] = intrpt_status_intrpt_status_22_qs; + reg_rdata_next[23] = intrpt_status_intrpt_status_23_qs; + reg_rdata_next[24] = intrpt_status_intrpt_status_24_qs; + reg_rdata_next[25] = intrpt_status_intrpt_status_25_qs; + reg_rdata_next[26] = intrpt_status_intrpt_status_26_qs; + reg_rdata_next[27] = intrpt_status_intrpt_status_27_qs; + reg_rdata_next[28] = intrpt_status_intrpt_status_28_qs; + reg_rdata_next[29] = intrpt_status_intrpt_status_29_qs; + reg_rdata_next[30] = intrpt_status_intrpt_status_30_qs; + reg_rdata_next[31] = intrpt_status_intrpt_status_31_qs; + end + + addr_hit[15]: begin + reg_rdata_next[0] = intrpt_rise_status_intrpt_rise_status_0_qs; + reg_rdata_next[1] = intrpt_rise_status_intrpt_rise_status_1_qs; + reg_rdata_next[2] = intrpt_rise_status_intrpt_rise_status_2_qs; + reg_rdata_next[3] = intrpt_rise_status_intrpt_rise_status_3_qs; + reg_rdata_next[4] = intrpt_rise_status_intrpt_rise_status_4_qs; + reg_rdata_next[5] = intrpt_rise_status_intrpt_rise_status_5_qs; + reg_rdata_next[6] = intrpt_rise_status_intrpt_rise_status_6_qs; + reg_rdata_next[7] = intrpt_rise_status_intrpt_rise_status_7_qs; + reg_rdata_next[8] = intrpt_rise_status_intrpt_rise_status_8_qs; + reg_rdata_next[9] = intrpt_rise_status_intrpt_rise_status_9_qs; + reg_rdata_next[10] = intrpt_rise_status_intrpt_rise_status_10_qs; + reg_rdata_next[11] = intrpt_rise_status_intrpt_rise_status_11_qs; + reg_rdata_next[12] = intrpt_rise_status_intrpt_rise_status_12_qs; + reg_rdata_next[13] = intrpt_rise_status_intrpt_rise_status_13_qs; + reg_rdata_next[14] = intrpt_rise_status_intrpt_rise_status_14_qs; + reg_rdata_next[15] = intrpt_rise_status_intrpt_rise_status_15_qs; + reg_rdata_next[16] = intrpt_rise_status_intrpt_rise_status_16_qs; + reg_rdata_next[17] = intrpt_rise_status_intrpt_rise_status_17_qs; + reg_rdata_next[18] = intrpt_rise_status_intrpt_rise_status_18_qs; + reg_rdata_next[19] = intrpt_rise_status_intrpt_rise_status_19_qs; + reg_rdata_next[20] = intrpt_rise_status_intrpt_rise_status_20_qs; + reg_rdata_next[21] = intrpt_rise_status_intrpt_rise_status_21_qs; + reg_rdata_next[22] = intrpt_rise_status_intrpt_rise_status_22_qs; + reg_rdata_next[23] = intrpt_rise_status_intrpt_rise_status_23_qs; + reg_rdata_next[24] = intrpt_rise_status_intrpt_rise_status_24_qs; + reg_rdata_next[25] = intrpt_rise_status_intrpt_rise_status_25_qs; + reg_rdata_next[26] = intrpt_rise_status_intrpt_rise_status_26_qs; + reg_rdata_next[27] = intrpt_rise_status_intrpt_rise_status_27_qs; + reg_rdata_next[28] = intrpt_rise_status_intrpt_rise_status_28_qs; + reg_rdata_next[29] = intrpt_rise_status_intrpt_rise_status_29_qs; + reg_rdata_next[30] = intrpt_rise_status_intrpt_rise_status_30_qs; + reg_rdata_next[31] = intrpt_rise_status_intrpt_rise_status_31_qs; + end + + addr_hit[16]: begin + reg_rdata_next[0] = intrpt_fall_status_intrpt_fall_status_0_qs; + reg_rdata_next[1] = intrpt_fall_status_intrpt_fall_status_1_qs; + reg_rdata_next[2] = intrpt_fall_status_intrpt_fall_status_2_qs; + reg_rdata_next[3] = intrpt_fall_status_intrpt_fall_status_3_qs; + reg_rdata_next[4] = intrpt_fall_status_intrpt_fall_status_4_qs; + reg_rdata_next[5] = intrpt_fall_status_intrpt_fall_status_5_qs; + reg_rdata_next[6] = intrpt_fall_status_intrpt_fall_status_6_qs; + reg_rdata_next[7] = intrpt_fall_status_intrpt_fall_status_7_qs; + reg_rdata_next[8] = intrpt_fall_status_intrpt_fall_status_8_qs; + reg_rdata_next[9] = intrpt_fall_status_intrpt_fall_status_9_qs; + reg_rdata_next[10] = intrpt_fall_status_intrpt_fall_status_10_qs; + reg_rdata_next[11] = intrpt_fall_status_intrpt_fall_status_11_qs; + reg_rdata_next[12] = intrpt_fall_status_intrpt_fall_status_12_qs; + reg_rdata_next[13] = intrpt_fall_status_intrpt_fall_status_13_qs; + reg_rdata_next[14] = intrpt_fall_status_intrpt_fall_status_14_qs; + reg_rdata_next[15] = intrpt_fall_status_intrpt_fall_status_15_qs; + reg_rdata_next[16] = intrpt_fall_status_intrpt_fall_status_16_qs; + reg_rdata_next[17] = intrpt_fall_status_intrpt_fall_status_17_qs; + reg_rdata_next[18] = intrpt_fall_status_intrpt_fall_status_18_qs; + reg_rdata_next[19] = intrpt_fall_status_intrpt_fall_status_19_qs; + reg_rdata_next[20] = intrpt_fall_status_intrpt_fall_status_20_qs; + reg_rdata_next[21] = intrpt_fall_status_intrpt_fall_status_21_qs; + reg_rdata_next[22] = intrpt_fall_status_intrpt_fall_status_22_qs; + reg_rdata_next[23] = intrpt_fall_status_intrpt_fall_status_23_qs; + reg_rdata_next[24] = intrpt_fall_status_intrpt_fall_status_24_qs; + reg_rdata_next[25] = intrpt_fall_status_intrpt_fall_status_25_qs; + reg_rdata_next[26] = intrpt_fall_status_intrpt_fall_status_26_qs; + reg_rdata_next[27] = intrpt_fall_status_intrpt_fall_status_27_qs; + reg_rdata_next[28] = intrpt_fall_status_intrpt_fall_status_28_qs; + reg_rdata_next[29] = intrpt_fall_status_intrpt_fall_status_29_qs; + reg_rdata_next[30] = intrpt_fall_status_intrpt_fall_status_30_qs; + reg_rdata_next[31] = intrpt_fall_status_intrpt_fall_status_31_qs; + end + + addr_hit[17]: begin + reg_rdata_next[0] = intrpt_lvl_high_status_intrpt_lvl_high_status_0_qs; + reg_rdata_next[1] = intrpt_lvl_high_status_intrpt_lvl_high_status_1_qs; + reg_rdata_next[2] = intrpt_lvl_high_status_intrpt_lvl_high_status_2_qs; + reg_rdata_next[3] = intrpt_lvl_high_status_intrpt_lvl_high_status_3_qs; + reg_rdata_next[4] = intrpt_lvl_high_status_intrpt_lvl_high_status_4_qs; + reg_rdata_next[5] = intrpt_lvl_high_status_intrpt_lvl_high_status_5_qs; + reg_rdata_next[6] = intrpt_lvl_high_status_intrpt_lvl_high_status_6_qs; + reg_rdata_next[7] = intrpt_lvl_high_status_intrpt_lvl_high_status_7_qs; + reg_rdata_next[8] = intrpt_lvl_high_status_intrpt_lvl_high_status_8_qs; + reg_rdata_next[9] = intrpt_lvl_high_status_intrpt_lvl_high_status_9_qs; + reg_rdata_next[10] = intrpt_lvl_high_status_intrpt_lvl_high_status_10_qs; + reg_rdata_next[11] = intrpt_lvl_high_status_intrpt_lvl_high_status_11_qs; + reg_rdata_next[12] = intrpt_lvl_high_status_intrpt_lvl_high_status_12_qs; + reg_rdata_next[13] = intrpt_lvl_high_status_intrpt_lvl_high_status_13_qs; + reg_rdata_next[14] = intrpt_lvl_high_status_intrpt_lvl_high_status_14_qs; + reg_rdata_next[15] = intrpt_lvl_high_status_intrpt_lvl_high_status_15_qs; + reg_rdata_next[16] = intrpt_lvl_high_status_intrpt_lvl_high_status_16_qs; + reg_rdata_next[17] = intrpt_lvl_high_status_intrpt_lvl_high_status_17_qs; + reg_rdata_next[18] = intrpt_lvl_high_status_intrpt_lvl_high_status_18_qs; + reg_rdata_next[19] = intrpt_lvl_high_status_intrpt_lvl_high_status_19_qs; + reg_rdata_next[20] = intrpt_lvl_high_status_intrpt_lvl_high_status_20_qs; + reg_rdata_next[21] = intrpt_lvl_high_status_intrpt_lvl_high_status_21_qs; + reg_rdata_next[22] = intrpt_lvl_high_status_intrpt_lvl_high_status_22_qs; + reg_rdata_next[23] = intrpt_lvl_high_status_intrpt_lvl_high_status_23_qs; + reg_rdata_next[24] = intrpt_lvl_high_status_intrpt_lvl_high_status_24_qs; + reg_rdata_next[25] = intrpt_lvl_high_status_intrpt_lvl_high_status_25_qs; + reg_rdata_next[26] = intrpt_lvl_high_status_intrpt_lvl_high_status_26_qs; + reg_rdata_next[27] = intrpt_lvl_high_status_intrpt_lvl_high_status_27_qs; + reg_rdata_next[28] = intrpt_lvl_high_status_intrpt_lvl_high_status_28_qs; + reg_rdata_next[29] = intrpt_lvl_high_status_intrpt_lvl_high_status_29_qs; + reg_rdata_next[30] = intrpt_lvl_high_status_intrpt_lvl_high_status_30_qs; + reg_rdata_next[31] = intrpt_lvl_high_status_intrpt_lvl_high_status_31_qs; + end + + addr_hit[18]: begin + reg_rdata_next[0] = intrpt_lvl_low_status_intrpt_lvl_low_status_0_qs; + reg_rdata_next[1] = intrpt_lvl_low_status_intrpt_lvl_low_status_1_qs; + reg_rdata_next[2] = intrpt_lvl_low_status_intrpt_lvl_low_status_2_qs; + reg_rdata_next[3] = intrpt_lvl_low_status_intrpt_lvl_low_status_3_qs; + reg_rdata_next[4] = intrpt_lvl_low_status_intrpt_lvl_low_status_4_qs; + reg_rdata_next[5] = intrpt_lvl_low_status_intrpt_lvl_low_status_5_qs; + reg_rdata_next[6] = intrpt_lvl_low_status_intrpt_lvl_low_status_6_qs; + reg_rdata_next[7] = intrpt_lvl_low_status_intrpt_lvl_low_status_7_qs; + reg_rdata_next[8] = intrpt_lvl_low_status_intrpt_lvl_low_status_8_qs; + reg_rdata_next[9] = intrpt_lvl_low_status_intrpt_lvl_low_status_9_qs; + reg_rdata_next[10] = intrpt_lvl_low_status_intrpt_lvl_low_status_10_qs; + reg_rdata_next[11] = intrpt_lvl_low_status_intrpt_lvl_low_status_11_qs; + reg_rdata_next[12] = intrpt_lvl_low_status_intrpt_lvl_low_status_12_qs; + reg_rdata_next[13] = intrpt_lvl_low_status_intrpt_lvl_low_status_13_qs; + reg_rdata_next[14] = intrpt_lvl_low_status_intrpt_lvl_low_status_14_qs; + reg_rdata_next[15] = intrpt_lvl_low_status_intrpt_lvl_low_status_15_qs; + reg_rdata_next[16] = intrpt_lvl_low_status_intrpt_lvl_low_status_16_qs; + reg_rdata_next[17] = intrpt_lvl_low_status_intrpt_lvl_low_status_17_qs; + reg_rdata_next[18] = intrpt_lvl_low_status_intrpt_lvl_low_status_18_qs; + reg_rdata_next[19] = intrpt_lvl_low_status_intrpt_lvl_low_status_19_qs; + reg_rdata_next[20] = intrpt_lvl_low_status_intrpt_lvl_low_status_20_qs; + reg_rdata_next[21] = intrpt_lvl_low_status_intrpt_lvl_low_status_21_qs; + reg_rdata_next[22] = intrpt_lvl_low_status_intrpt_lvl_low_status_22_qs; + reg_rdata_next[23] = intrpt_lvl_low_status_intrpt_lvl_low_status_23_qs; + reg_rdata_next[24] = intrpt_lvl_low_status_intrpt_lvl_low_status_24_qs; + reg_rdata_next[25] = intrpt_lvl_low_status_intrpt_lvl_low_status_25_qs; + reg_rdata_next[26] = intrpt_lvl_low_status_intrpt_lvl_low_status_26_qs; + reg_rdata_next[27] = intrpt_lvl_low_status_intrpt_lvl_low_status_27_qs; + reg_rdata_next[28] = intrpt_lvl_low_status_intrpt_lvl_low_status_28_qs; + reg_rdata_next[29] = intrpt_lvl_low_status_intrpt_lvl_low_status_29_qs; + reg_rdata_next[30] = intrpt_lvl_low_status_intrpt_lvl_low_status_30_qs; + reg_rdata_next[31] = intrpt_lvl_low_status_intrpt_lvl_low_status_31_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) + +endmodule diff --git a/hw/vendor/pulp_platform_gpio/test/tb_gpio.sv b/hw/vendor/pulp_platform_gpio/test/tb_gpio.sv new file mode 100644 index 000000000..7f870f8cf --- /dev/null +++ b/hw/vendor/pulp_platform_gpio/test/tb_gpio.sv @@ -0,0 +1,820 @@ +//----------------------------------------------------------------------------- +// Title : GPIO Testbench +//----------------------------------------------------------------------------- +// File : tb_gpio.sv +// Author : Manuel Eggimann +// Created : 07.05.2021 +//----------------------------------------------------------------------------- +// Description : +// Test the functionality of the GPIO Peripheral +//----------------------------------------------------------------------------- +// Copyright (C) 2013-2021 ETH Zurich, University of Bologna +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +//----------------------------------------------------------------------------- + + +`define SV_RAND_CHECK(r) \ +do begin \ + if (!(r)) begin \ + $display("%s:%0d: Randomization failed \"%s\"", `__FILE__, `__LINE__, `"r`"); \ + $stop;\ + end\ + end while (0) + + +module tb_gpio; + localparam ClkPeriod = 10ns; + localparam RstCycles = 6; + localparam ApplTime = 1ns; + localparam TestTime = 8ns; + localparam DataWidth = 32; + localparam AddrWidth = 32; + parameter NumRepetitions = 20; + localparam SimTimeoutCycles = 5000*NumRepetitions; // Timeout the simulation after 5000 cycles + localparam NrGPIOs = gpio_reg_pkg::GPIOCount; + + // Testbench control signals + logic clk; + logic rst_n; + logic end_of_sim; + + // Generate clock and reset + clk_rst_gen #( + .ClkPeriod ( ClkPeriod ), + .RstClkCycles ( RstCycles ) + ) i_clk_rst_gen ( + .clk_o ( clk ), + .rst_no( rst_n ) + ); + + // Test Timeout Module + sim_timeout #( + .Cycles(SimTimeoutCycles) + ) i_sim_timeout( + .clk_i ( clk ), + .rst_ni ( rst_n ) + ); + + // End of test procedure + initial begin : proc_end_of_test + wait (end_of_sim); + repeat (100) @(posedge clk); + $info("Simulation ended."); + $stop(); + end + + // Interface Signals + REG_BUS #( + .ADDR_WIDTH (AddrWidth), + .DATA_WIDTH (DataWidth)) s_reg_bus (.clk_i(clk)); + + logic [NrGPIOs-1:0] gpio_in; + logic [NrGPIOs-1:0] gpio_in_sync; + logic [NrGPIOs-1:0] gpio_out; + logic [NrGPIOs-1:0] gpio_tx_en; + logic interrupt; + + + // Instantiate DUT + gpio_intf #( + .ADDR_WIDTH ( AddrWidth ), + .DATA_WIDTH ( DataWidth ) + ) i_dut ( + .reg_bus ( s_reg_bus.in ), + // Outputs + .gpio_out ( gpio_out[NrGPIOs-1:0] ), + .gpio_tx_en_o ( gpio_tx_en[NrGPIOs-1:0] ), + .gpio_in_sync_o ( gpio_in_sync[NrGPIOs-1:0] ), + .interrupt_o ( interrupt ), + // Inputs + .clk_i ( clk ), + .rst_ni ( rst_n ), + .gpio_in ( gpio_in[NrGPIOs-1:0] ) + ); + + // Connect test programm + test #( + .NrGPIOs ( NrGPIOs ), + .DataWidth ( DataWidth ), + .AddrWidth ( AddrWidth ), + .ApplTime ( ApplTime ), + .TestTime ( TestTime ), + .NumRepetitions ( NumRepetitions ) + ) i_test ( + .end_of_sim_o ( end_of_sim ), + .clk_i ( clk ), + .rst_ni ( rst_n ), + .gpio_in_o ( gpio_in ), + .gpio_out_i ( gpio_out ), + .gpio_tx_en_i ( gpio_tx_en ), + .gpio_in_sync_i ( gpio_in_sync ), + .interrupt_i ( interrupt ), + .reg_bus ( s_reg_bus ) + ); +endmodule + + +program automatic test #( + parameter int unsigned NrGPIOs = 64, + localparam int unsigned NrGPIOs_rounded = ((NrGPIOs+32-1)/32)*32, + parameter DataWidth = 32, + parameter AddrWidth = 32, + parameter ApplTime, + parameter TestTime, + parameter int unsigned NumRepetitions +) ( + output logic end_of_sim_o, + input logic clk_i, + input logic rst_ni, + output logic [NrGPIOs-1:0] gpio_in_o, + input logic [NrGPIOs-1:0] gpio_out_i, + input logic [NrGPIOs-1:0] gpio_tx_en_i, // 0 -> input, 1 -> output + input logic [NrGPIOs-1:0] gpio_in_sync_i, // sampled and synchronized GPIO + // input. + input logic interrupt_i, + REG_BUS.out reg_bus +); + default clocking cb @(posedge clk_i); + endclocking + + import reg_test::reg_driver; + import gpio_reg_pkg::*; + + localparam type gpio_reg_driver_t = reg_driver #(.AW(AddrWidth), .DW(DataWidth), .TA(ApplTime), .TT(TestTime)); + gpio_reg_driver_t gpio_reg_driver; + // reg_driver #(.AW(AddrWidth), .DW(DataWidth), .TA(ApplTime), .TT(TestTime)) gpio_reg_driver; + + // Debug Signals + logic [NrGPIOs_rounded-1:0][1:0] gpio_modes; + logic [NrGPIOs_rounded-1:0] gpio_values; + int error_count = 0; + + task automatic test_toggle_set_clear(gpio_reg_driver_t gpio_reg_driver, int unsigned NumRepetitions); + logic [DataWidth-1:0] data = 0; + logic [AddrWidth-1:0] addr; + logic [DataWidth/8-1:0] strb = '1; + logic error = 0; + + $info("Verifying toggle, set and clear functionality of the outputs"); + for (int i = 0; i < (NrGPIOs+DataWidth-1)/DataWidth*2; i++) begin : cfg_gpio_modes + addr = GPIO_GPIO_MODE_0_OFFSET + i*4; + data = {16{2'b01}}; // Put all gpios in push-pull mode + gpio_reg_driver.send_write(addr, data, strb, error); + assert(error == 0) else begin + $error("Interface write error while writing GPIO mode."); + error_count++; + end + end + + // Set random gpio out values + `SV_RAND_CHECK(randomize(gpio_values)); + for (int i = 0; i < (NrGPIOs+DataWidth-1)/DataWidth; i++) begin + addr = GPIO_GPIO_OUT_0_OFFSET + i*4; + data = gpio_values[i*DataWidth+:DataWidth]; + gpio_reg_driver.send_write(addr, data, strb, error); + assert(error == 0) else begin + $error("Interface write error while writing GPIO out values."); + error_count++; + end + end + + assert (gpio_tx_en_i == '1) else begin + $error("GPIO TX driver not enabled although all GPIOs should be configured as outputs in push-pull mode."); + error_count++; + end + assert (gpio_out_i == gpio_values[NrGPIOs-1:0]) else begin + $error("Missmatch in GPIO outputs. Expected output pattern %0b but was %0b.", gpio_values, gpio_out_i); + error_count++; + end + + // Sequentially toggle, set and clear all GPIOs and verify only the ones set are modified + for (int i= 0; i < NrGPIOs; i++) begin + data = 1<<(i%32); + // Toggle the GPIO + addr = GPIO_GPIO_TOGGLE_0_OFFSET + i/32*4; + gpio_reg_driver.send_write(addr, data, strb, error); + for (int j = 0; j < NrGPIOs; j++) begin + if (i == j) begin + assert(gpio_out_i[j] == ~gpio_values[j]) else begin + $error("GPIO %0d has not toggled.", j); + error_count++; + end + end else begin + assert(gpio_out_i[j] == gpio_values[j]) else begin + $error("GPIO %0d was %0b instead of %0b although it should not have beend altered during modification of GPIO %0d.", j, gpio_out_i[j], gpio_values[j], i); + error_count++; + end + end + end + + + //Set the GPIO + addr = GPIO_GPIO_SET_0_OFFSET + i/32*4; + gpio_reg_driver.send_write(addr, data, strb, error); + for (int j = 0; j < NrGPIOs; j++) begin + if (i == j) begin + assert(gpio_out_i[j] == 1'b1) else begin + $error("GPIO %0d is not set.", j); + error_count++; + end + end else begin + assert(gpio_out_i[j] == gpio_values[j]) else begin + $error("GPIO %0d was %0b instead of %0b although it should not have beend altered during modification of GPIO %0d.", j, gpio_out_i[j], gpio_values[j], i); + error_count++; + end + end + end + + // Now clear the GPIO + addr = GPIO_GPIO_CLEAR_0_OFFSET + i/32*4; + gpio_reg_driver.send_write(addr, data, strb, error); + for (int j = 0; j < NrGPIOs; j++) begin + if (i == j) begin + assert(gpio_out_i[j] == 1'b0) else begin + $error("GPIO %0d is not cleared.", j); + error_count++; + end + end else begin + assert(gpio_out_i[j] == gpio_values[j]) else begin + $error("GPIO %0d was %0b instead of %0b although it should not have beend altered during modification of GPIO %0d.", j, gpio_out_i[j], gpio_values[j], i); + error_count++; + end + end + end + gpio_values[i] = 1'b0; + end + + endtask + + task automatic test_inputs(gpio_reg_driver_t reg_driver, int unsigned NumRepetitions); + logic [DataWidth-1:0] data = 0; + logic [AddrWidth-1:0] addr; + logic [DataWidth/8-1:0] strb = '1; + logic error = 0; + logic [NrGPIOs_rounded-1:0] enabled_gpios; + logic [NrGPIOs-1:0] gpio_values; + logic [NrGPIOs-1:0] data_queue[$]; + + gpio_in_o = '0; + + $info("Test GPIOs in input mode with random data."); + for (int i = 0; i < (NrGPIOs+DataWidth-1)/DataWidth*2; i++) begin : cfg_gpio_modes + addr = GPIO_GPIO_MODE_0_OFFSET + i*4; + data = {16{2'b00}}; // Put all gpios in input mode + gpio_reg_driver.send_write(addr, data, strb, error); + assert(error == 0) else begin + $error("Interface write error while writing GPIO mode."); + error_count++; + end + end + $info("Enabling input sampling on random GPIOs"); + `SV_RAND_CHECK(randomize(enabled_gpios)); + for (int i = 0; i < (NrGPIOs+DataWidth-1)/DataWidth; i++) begin : cfg_gpio_enable + addr = GPIO_GPIO_EN_0_OFFSET + i*4; + data = enabled_gpios[i*32+:32]; + gpio_reg_driver.send_write(addr, data, strb, error); + assert(error == 0) else begin + $error("Interface write error while writing GPIO mode."); + error_count++; + end + end + + $info("Apply and verify random inputs"); + for (int i = 0; i < NumRepetitions; i++) begin + `SV_RAND_CHECK(randomize(gpio_in_o)); + ##3; //Wait three cycles + #TestTime; + for (int i = 0; i < (NrGPIOs+DataWidth-1)/DataWidth; i++) begin + addr = GPIO_GPIO_IN_0_OFFSET + i*4; + gpio_reg_driver.send_read(addr, data, error); + assert(error == 0) else begin + $error("Interface write error while writing GPIO mode."); + error_count++; + end + for (int j = i*32; j < (i+1)*32; j++) begin + if (j < NrGPIOs && enabled_gpios[j]) begin + assert(gpio_in_o[j] == data[j%32]) else begin + $error("Got wrong gpio value for GPIO%0d. Was %0b instead of %0b", j, gpio_in_o[j], data[j%32]); + error_count++; + end + end + end + end + end + + $info("Test fast data sampling"); + for (int k = 0; k < NumRepetitions; k++) begin + `SV_RAND_CHECK(randomize(gpio_values)); + data_queue.push_back(gpio_values); + end + fork + begin + $info("Aplying inputs..."); + foreach(data_queue[i]) begin + #ApplTime; + gpio_in_o = data_queue[i]; + ##1; + end + end + begin + ##3; // Delay sampling by 3 cycles for + $info("Start reading sampled values on GPIO0..."); + addr = GPIO_GPIO_IN_0_OFFSET; + foreach(data_queue[i]) begin + gpio_reg_driver.send_read(addr, data, error); + for (int j = 0; j < NrGPIOs && j < 32; j++) begin + if (enabled_gpios[j]) + assert(data[j] == data_queue[i][j]) else begin + $error("On GPIO %0d. Was %0b instead of %0b.", j, data[j], data_queue[i][j]); + error_count++; + end + end + end + end + join + endtask + + typedef enum logic[2:0] {None, Rising, Falling, EitherEdge, Low, High} interrupt_mode_e; + interrupt_mode_e [NrGPIOs_rounded-1:0] interrupt_modes; + + task automatic test_interrupts(gpio_reg_driver_t gpio_reg_driver, int unsigned NumRepetitions); + logic [DataWidth-1:0] data = 0; + logic [AddrWidth-1:0] addr; + logic [DataWidth/8-1:0] strb = '1; + logic error = 0; + logic [NrGPIOs_rounded-1:0] enabled_gpios; + logic [NrGPIOs-1:0] gpio_values; + logic [NrGPIOs-1:0] toggle_mask; + logic [NrGPIOs_rounded-1:0] pending_intrpt, pending_rise_intrpt, pending_fall_intrpt, pending_low_intrpt, pending_high_intrpt; + logic clear_interrupt; + + + int unsigned delay; + + $info("Test GPIO interrupts."); + for (int i = 0; i < (NrGPIOs+DataWidth-1)/DataWidth*2; i++) begin : cfg_gpio_modes + addr = GPIO_GPIO_MODE_0_OFFSET + i*4; + data = {16{2'b00}}; // Put all gpios in input mode + gpio_reg_driver.send_write(addr, data, strb, error); + assert(error == 0) else begin + $error("Interface write error while writing GPIO mode."); + error_count++; + end + end + $info("Enabling input sampling on all GPIOs"); + `SV_RAND_CHECK(randomize(enabled_gpios)); + for (int i = 0; i < (NrGPIOs+DataWidth-1)/DataWidth; i++) begin : cfg_gpio_enable + addr = GPIO_GPIO_EN_0_OFFSET + i*4; + data = '1; + gpio_reg_driver.send_write(addr, data, strb, error); + assert(error == 0) else begin + $error("Interface write error while writing GPIO mode."); + error_count++; + end + end + + $info("Put GPIOs into random interrupt modes..."); + // We randomize the modes such that there are not to many enabled + // interrupts. Otherwise the interrupt line will probably stay high all the + // time due to the level sensitive interrupts. + std::randomize(interrupt_modes) with { + foreach (interrupt_modes[i]) { + interrupt_modes[i] dist { + None := 20, + Rising := 2, + Falling := 2, + EitherEdge := 1, + Low := 1, + High := 1 + }; + } + }; + // Before enabling level low sensitive interrupts, put gpio inputs in a state + // that doesn't immediately trigger them. + foreach(gpio_in_o[i]) begin + gpio_in_o[i] = interrupt_modes[i] == Low; + end + ##3; + + for (int i = 0; i < (NrGPIOs+DataWidth-1)/DataWidth; i++) begin : cfg_gpio_enable + // Enable rising edge interrupts + addr = GPIO_INTRPT_RISE_EN_0_OFFSET + i*4; + foreach(data[j]) begin + data[j] = interrupt_modes[i*32+j] == Rising || interrupt_modes[i*32+j] == EitherEdge; + end + gpio_reg_driver.send_write(addr, data, strb, error); + // Enable falling edge interrupts + addr = GPIO_INTRPT_FALL_EN_0_OFFSET + i*4; + foreach(data[j]) begin + data[j] = interrupt_modes[i*32+j] == Falling || interrupt_modes[i*32+j] == EitherEdge; + end + gpio_reg_driver.send_write(addr, data, strb, error); + + // Enable low level-sensitive interrupts + foreach(data[j]) begin + data[j] = interrupt_modes[i*32+j] == Low; + end + addr = GPIO_INTRPT_LVL_LOW_EN_0_OFFSET + i*4; + gpio_reg_driver.send_write(addr, data, strb, error); + // Enable high level-sensitive interrupts + addr = GPIO_INTRPT_LVL_HIGH_EN_0_OFFSET + i*4; + foreach(data[j]) begin + data[j] = interrupt_modes[i*32+j] == High; + end + gpio_reg_driver.send_write(addr, data, strb, error); + assert(error == 0) else begin + $error("Interface write error while writing GPIO mode."); + error_count++; + end + end + ##10; + + $info("Inserting random interrupts..."); + pending_rise_intrpt = '0; + pending_fall_intrpt = '0; + pending_high_intrpt = '0; + pending_low_intrpt = '0; + for (int i = 0; i < NumRepetitions; i++) begin + ## 1; + // Toggle some random GPIOs + `SV_RAND_CHECK(randomize(toggle_mask) with { + $countones(toggle_mask) < 3; + }); + $info("Toggling GPIOs..."); + gpio_in_o ^= toggle_mask; + #ApplTime; + //Check which interrups this change should trigger... + foreach(toggle_mask[j]) begin + case (interrupt_modes[j]) + Falling: begin + if (gpio_in_o[j] == 1'b0 && toggle_mask[j]) + pending_fall_intrpt[j] = 1'b1; + end + + Rising: begin + if (gpio_in_o[j] == 1'b1 && toggle_mask[j]) + pending_rise_intrpt[j] = 1'b1; + end + + EitherEdge: begin + if (toggle_mask[j]) begin + if (gpio_in_o[j] == 1'b1) + pending_rise_intrpt[j] = 1'b1; + else + pending_fall_intrpt[j] = 1'b1; + end + end + + Low: begin + if (gpio_in_o[j] == 1'b0) + pending_low_intrpt[j] = 1'b1; + end + + High: begin + if (gpio_in_o[j] == 1'b1) + pending_high_intrpt[j] = 1'b1; + end + endcase + end + $info("Checking interrupt status regs..."); + pending_intrpt = pending_high_intrpt | pending_low_intrpt | pending_rise_intrpt | pending_fall_intrpt; + if (pending_intrpt) begin + if (pending_rise_intrpt | pending_fall_intrpt) begin + // Wait 2 cycles (rising and falling edge interrupts arrive 1 cycle + // earlier than level sensitive interrupts) + ##2; + end else begin + ##3; + end + + #TestTime; + assert(interrupt_i == 1'b1) else begin + $error("Interrupt was not asserted."); + error_count++; + end + ##2; // Wait another 2 cycles for the interrupt status register to be + // updated + //Read interrupt status registers + for (int i = 0; i < (NrGPIOs+DataWidth-1)/DataWidth; i++) begin + addr = GPIO_INTRPT_STATUS_0_OFFSET + i*4; + gpio_reg_driver.send_read(addr, data, error); + assert(data == pending_intrpt[i*32+:32]) else begin + $error("Interrupt status missmatch. Was %0x instead of %0x", data, pending_intrpt[i*32+:32]); + error_count++; + end + addr = GPIO_INTRPT_RISE_STATUS_0_OFFSET + i*4; + gpio_reg_driver.send_read(addr, data, error); + assert(data == pending_rise_intrpt[i*32+:32]) else begin + $error("Interrupt rise status missmatch. Was %0x instead of %0x", data, pending_rise_intrpt[i*32+:32]); + error_count++; + end + addr = GPIO_INTRPT_FALL_STATUS_0_OFFSET + i*4; + gpio_reg_driver.send_read(addr, data, error); + assert(data == pending_fall_intrpt[i*32+:32]) else begin + $error("Interrupt fall status missmatch. Was %0x instead of %0x", data, pending_fall_intrpt[i*32+:32]); + error_count++; + end + addr = GPIO_INTRPT_LVL_LOW_STATUS_0_OFFSET + i*4; + gpio_reg_driver.send_read(addr, data, error); + assert(data == pending_low_intrpt[i*32+:32]) else begin + $error("Interrupt low status missmatch. Was %0x instead of %0x", data, pending_low_intrpt[i*32+:32]); + error_count++; + end + addr = GPIO_INTRPT_LVL_HIGH_STATUS_0_OFFSET + i*4; + gpio_reg_driver.send_read(addr, data, error); + assert(data == pending_high_intrpt[i*32+:32]) else begin + $error("Interrupt high status missmatch. Was %0x instead of %0x", data, pending_high_intrpt[i*32+:32]); + error_count++; + end + end + + //Now clear some of the pending interrupts + $info("Start interrupt clearing..."); + foreach(pending_intrpt[j]) begin + if (pending_intrpt[j]) begin + randcase + 2: begin + $info("Clearing all interrupts on GPIO %0d.", j); + addr = GPIO_INTRPT_STATUS_0_OFFSET + j/32*4; + data = 1<params.base_addr, reg_lower_offset, - (mask_lower_half << 16) | (val & 0x0000FFFFu)); - } - if (mask_upper_half != 0) { - mmio_region_write32(gpio->params.base_addr, reg_upper_offset, - mask_upper_half | ((val & 0xFFFF0000u) >> 16)); - } - - return kGpioOk; -} - -/** - * Perform a masked write to a single bit of a GPIO register. + * Perform a masked write to a single bit of a GPIO register. (For the new GPIO) * * The GPIO device provides masked bit-level atomic writes to its DIRECT_OUT * and DIRECT_OE registers. This allows software to modify half of the bits @@ -81,21 +36,25 @@ static gpio_result_t gpio_masked_write(const gpio_t *gpio, * @param val Value to write. */ static gpio_result_t gpio_masked_bit_write(const gpio_t *gpio, - ptrdiff_t reg_lower_offset, - ptrdiff_t reg_upper_offset, + ptrdiff_t reg_offset, uint32_t index, bool val) { if (gpio == NULL) { return kGpioBadArg; } - - // Write to reg_lower_offset if the bit is in the lower half, write to - // reg_upper_offset otherwise. - const ptrdiff_t offset = (index < 16) ? reg_lower_offset : reg_upper_offset; - // Since masked access writes to half of a register, index mod 16 gives the - // index of the bit in the half-word mask. - const uint32_t mask = index_to_mask(index % 16); - mmio_region_write32(gpio->params.base_addr, offset, - (mask << 16) | (val ? mask : 0u)); + uint32_t temp = mmio_region_read32(gpio->params.base_addr, reg_offset); + if (val == true){ + uint32_t mask = index_to_mask(index); + uint32_t mask_val = mask | temp; + mmio_region_write32(gpio->params.base_addr, reg_offset, + mask_val); + + }else{ + uint32_t mask = index_to_mask(index); + mask = ~mask; + uint32_t mask_val = mask & temp; + mmio_region_write32(gpio->params.base_addr, reg_offset, + mask_val); + } return kGpioOk; } @@ -117,9 +76,10 @@ gpio_result_t gpio_reset(const gpio_t *gpio) { // We don't need to write to `GPIO_MASKED_OE_*` and `GPIO_MASKED_OUT_*` // since we directly reset `GPIO_DIRECT_OE` and `GPIO_DIRECT_OUT` below. - mmio_region_write32(gpio->params.base_addr, GPIO_INTR_ENABLE_REG_OFFSET, 0); - mmio_region_write32(gpio->params.base_addr, GPIO_DIRECT_OE_REG_OFFSET, 0); + mmio_region_write32(gpio->params.base_addr, GPIO_GPIO_EN_OFFSET, 0); + mmio_region_write32(gpio->params.base_addr, GPIO_DATA_IN_REG_OFFSET, 0); mmio_region_write32(gpio->params.base_addr, GPIO_DIRECT_OUT_REG_OFFSET, 0); + // Clear all the interrupt enable mmio_region_write32(gpio->params.base_addr, GPIO_INTR_CTRL_EN_RISING_REG_OFFSET, 0); mmio_region_write32(gpio->params.base_addr, @@ -128,10 +88,17 @@ gpio_result_t gpio_reset(const gpio_t *gpio) { GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET, 0); mmio_region_write32(gpio->params.base_addr, GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET, 0); + // Also clear all the interrupt + mmio_region_write32(gpio->params.base_addr, + GPIO_INTRPT_RISE_STATUS_OFFSET, 0); mmio_region_write32(gpio->params.base_addr, - GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, 0); + GPIO_INTRPT_FALL_STATUS_OFFSET, 0); + mmio_region_write32(gpio->params.base_addr, + GPIO_INTRPT_LVL_HIGH_STATUS_OFFSET, 0); + mmio_region_write32(gpio->params.base_addr, + GPIO_INTRPT_LVL_LOW_STATUS_OFFSET, 0); // Also clear all pending interrupts - mmio_region_write32(gpio->params.base_addr, GPIO_INTR_STATE_REG_OFFSET, + mmio_region_write32(gpio->params.base_addr, GPIO_INTRPT_STATUS_OFFSET, 0xFFFFFFFFu); return kGpioOk; @@ -145,7 +112,7 @@ gpio_result_t gpio_irq_is_pending(const gpio_t *gpio, } *is_pending = mmio_region_get_bit32(gpio->params.base_addr, - GPIO_INTR_STATE_REG_OFFSET, pin); + GPIO_INTRPT_STATUS_OFFSET, pin); return kGpioOk; } @@ -157,7 +124,7 @@ gpio_result_t gpio_irq_is_pending_all(const gpio_t *gpio, } *is_pending = - mmio_region_read32(gpio->params.base_addr, GPIO_INTR_STATE_REG_OFFSET); + mmio_region_read32(gpio->params.base_addr, GPIO_INTRPT_STATUS_OFFSET); return kGpioOk; } @@ -168,111 +135,12 @@ gpio_result_t gpio_irq_acknowledge(const gpio_t *gpio, return kGpioBadArg; } - mmio_region_write32(gpio->params.base_addr, GPIO_INTR_STATE_REG_OFFSET, + mmio_region_write32(gpio->params.base_addr, GPIO_INTRPT_STATUS_OFFSET, index_to_mask(pin)); return kGpioOk; } -gpio_result_t gpio_irq_get_enabled(const gpio_t *gpio, - gpio_pin_t pin, - gpio_toggle_t *state) { - if (gpio == NULL || state == NULL) { - return kGpioBadArg; - } - - bool is_enabled = mmio_region_get_bit32(gpio->params.base_addr, - GPIO_INTR_ENABLE_REG_OFFSET, pin); - *state = is_enabled ? kGpioToggleEnabled : kGpioToggleDisabled; - - return kGpioOk; -} - -gpio_result_t gpio_irq_set_enabled(const gpio_t *gpio, - gpio_pin_t pin, - gpio_toggle_t state) { - if (gpio == NULL) { - return kGpioBadArg; - } - - switch (state) { - case kGpioToggleEnabled: - mmio_region_nonatomic_set_bit32(gpio->params.base_addr, - GPIO_INTR_ENABLE_REG_OFFSET, pin); - break; - case kGpioToggleDisabled: - mmio_region_nonatomic_clear_bit32(gpio->params.base_addr, - GPIO_INTR_ENABLE_REG_OFFSET, pin); - break; - default: - return kGpioBadArg; - } - - return kGpioOk; -} - -gpio_result_t gpio_irq_set_enabled_masked(const gpio_t *gpio, - gpio_mask_t mask, - gpio_toggle_t state) { - if (gpio == NULL) { - return kGpioBadArg; - } - - switch (state) { - case kGpioToggleEnabled: - mmio_region_nonatomic_set_mask32(gpio->params.base_addr, - GPIO_INTR_ENABLE_REG_OFFSET, mask, 0); - break; - case kGpioToggleDisabled: - mmio_region_nonatomic_clear_mask32(gpio->params.base_addr, - GPIO_INTR_ENABLE_REG_OFFSET, mask, 0); - break; - default: - return kGpioBadArg; - } - - return kGpioOk; -} - -gpio_result_t gpio_irq_force(const gpio_t *gpio, - gpio_pin_t pin) { - if (gpio == NULL) { - return kGpioBadArg; - } - - mmio_region_write32(gpio->params.base_addr, GPIO_INTR_TEST_REG_OFFSET, - index_to_mask(pin)); - - return kGpioOk; -} - -gpio_result_t gpio_irq_disable_all(const gpio_t *gpio, - gpio_state_t *snapshot) { - if (gpio == NULL) { - return kGpioBadArg; - } - - if (snapshot != NULL) { - *snapshot = - mmio_region_read32(gpio->params.base_addr, GPIO_INTR_ENABLE_REG_OFFSET); - } - mmio_region_write32(gpio->params.base_addr, GPIO_INTR_ENABLE_REG_OFFSET, 0); - - return kGpioOk; -} - -gpio_result_t gpio_irq_restore_all(const gpio_t *gpio, - const gpio_state_t *snapshot) { - if (gpio == NULL || snapshot == NULL) { - return kGpioBadArg; - } - - mmio_region_write32(gpio->params.base_addr, GPIO_INTR_ENABLE_REG_OFFSET, - *snapshot); - - return kGpioOk; -} - gpio_result_t gpio_irq_set_trigger(const gpio_t *gpio, gpio_mask_t mask, gpio_irq_trigger_t trigger) { @@ -374,68 +242,87 @@ gpio_result_t gpio_write_all(const gpio_t *gpio, gpio_result_t gpio_write(const gpio_t *gpio, gpio_pin_t pin, bool state) { - return gpio_masked_bit_write(gpio, GPIO_MASKED_OUT_LOWER_REG_OFFSET, - GPIO_MASKED_OUT_UPPER_REG_OFFSET, pin, state); + if (state == true){ + return gpio_masked_bit_write(gpio, GPIO_GPIO_SET_OFFSET, + pin, state); + }else{ + return gpio_masked_bit_write(gpio, GPIO_GPIO_CLEAR_OFFSET, + pin, state); + } } +gpio_result_t gpio_input_set_enabled_all(const gpio_t *gpio, + gpio_state_t state) { + if (gpio == NULL) { + return kGpioBadArg; + } -gpio_result_t gpio_write_masked(const gpio_t *gpio, - gpio_mask_t mask, - gpio_state_t state) { - return gpio_masked_write(gpio, GPIO_MASKED_OUT_LOWER_REG_OFFSET, - GPIO_MASKED_OUT_UPPER_REG_OFFSET, mask, state); + mmio_region_write32(gpio->params.base_addr, GPIO_GPIO_EN_OFFSET, state); + + return kGpioOk; } -gpio_result_t gpio_output_set_enabled_all(const gpio_t *gpio, +gpio_result_t gpio_input_set_enabled(const gpio_t *gpio, + gpio_pin_t pin, gpio_state_t state) { if (gpio == NULL) { return kGpioBadArg; } - - mmio_region_write32(gpio->params.base_addr, GPIO_DIRECT_OE_REG_OFFSET, state); + gpio_masked_bit_write(gpio, GPIO_GPIO_EN_OFFSET, + pin, state); return kGpioOk; } -gpio_result_t gpio_output_set_enabled(const gpio_t *gpio, - gpio_pin_t pin, - gpio_toggle_t state) { +gpio_result_t gpio_set(const gpio_t *gpio, gpio_state_t state) { if (gpio == NULL) { return kGpioBadArg; } - return gpio_masked_bit_write(gpio, GPIO_MASKED_OE_LOWER_REG_OFFSET, - GPIO_MASKED_OE_UPPER_REG_OFFSET, pin, state); + mmio_region_write32(gpio->params.base_addr, GPIO_GPIO_SET_OFFSET, + state); return kGpioOk; } -gpio_result_t gpio_output_set_enabled_masked(const gpio_t *gpio, - gpio_mask_t mask, - gpio_state_t state) { - return gpio_masked_write(gpio, GPIO_MASKED_OE_LOWER_REG_OFFSET, - GPIO_MASKED_OE_UPPER_REG_OFFSET, mask, state); +gpio_result_t gpio_clear(const gpio_t *gpio, gpio_state_t state) { + if (gpio == NULL) { + return kGpioBadArg; + } + + mmio_region_write32(gpio->params.base_addr, GPIO_GPIO_CLEAR_OFFSET, + state); + + return kGpioOk; } -gpio_result_t gpio_input_noise_filter_set_enabled( - const gpio_t *gpio, gpio_mask_t mask, gpio_toggle_t state) { +gpio_result_t gpio_toggle(const gpio_t *gpio, gpio_state_t state) { if (gpio == NULL) { return kGpioBadArg; } - switch (state) { - case kGpioToggleEnabled: - mmio_region_nonatomic_set_mask32(gpio->params.base_addr, - GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, - mask, 0); - break; - case kGpioToggleDisabled: - mmio_region_nonatomic_clear_mask32(gpio->params.base_addr, - GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET, - mask, 0); - break; - default: - return kGpioBadArg; - } + mmio_region_write32(gpio->params.base_addr, GPIO_GPIO_TOGGLE_OFFSET, + state); return kGpioOk; } + + +gpio_result_t gpio_set_mode(const gpio_t *gpio, gpio_pin_t pin, + bool state1, bool state2) { + if(pin < 16){ + gpio_masked_bit_write(gpio, GPIO_GPIO_MODE_0_OFFSET, 2*pin, state2); + return gpio_masked_bit_write(gpio, GPIO_GPIO_MODE_0_OFFSET, 2*pin+1, state1); + }else{ + gpio_masked_bit_write(gpio, GPIO_GPIO_MODE_1_OFFSET, 2*(pin-16), state2); + return gpio_masked_bit_write(gpio, GPIO_GPIO_MODE_1_OFFSET, 2*(pin-16)+1, state1); + } +} +gpio_result_t gpio_set_mode_all(const gpio_t *gpio, + bool state1, bool state2) { + mmio_region_write32(gpio->params.base_addr, GPIO_GPIO_MODE_1_OFFSET, + state1); + mmio_region_write32(gpio->params.base_addr, GPIO_GPIO_MODE_0_OFFSET, + state2); + return kGpioOk; + +} \ No newline at end of file diff --git a/sw/device/lib/drivers/gpio/gpio.h b/sw/device/lib/drivers/gpio/gpio.h index 2b2edce55..ecbe6122c 100644 --- a/sw/device/lib/drivers/gpio/gpio.h +++ b/sw/device/lib/drivers/gpio/gpio.h @@ -208,78 +208,6 @@ gpio_result_t gpio_irq_is_pending_all(const gpio_t *gpio, gpio_result_t gpio_irq_acknowledge(const gpio_t *gpio, gpio_pin_t pin); -/** - * Checks whether a particular pin's interrupt is currently enabled or disabled. - * - * @param gpio A GPIO handle. - * @param pin A GPIO pin. - * @param[out] state Out-param toggle state of the interrupt. - * @return The result of the operation. - */ -gpio_result_t gpio_irq_get_enabled(const gpio_t *gpio, - gpio_pin_t pin, - gpio_toggle_t *state); - -/** - * Sets whether a particular pin's interrupt is currently enabled or disabled. - * - * @param gpio A GPIO handle. - * @param pin A GPIO pin. - * @param state The new toggle state for the interrupt. - * @return The result of the operation. - */ -gpio_result_t gpio_irq_set_enabled(const gpio_t *gpio, - gpio_pin_t pin, - gpio_toggle_t state); - -/** - * Sets whether a particular pin's interrupt is currently enabled or disabled. - * - * @param gpio A GPIO handle. - * @param mask Mask that identifies the pins whose interrupt triggers will be - * configured. - * @param state The new toggle state for the interrupt. - * @return The result of the operation. - */ -gpio_result_t gpio_irq_set_enabled_masked(const gpio_t *gpio, - gpio_mask_t mask, - gpio_toggle_t state); - -/** - * Forces a particular pin's interrupt, causing it to be serviced as if hardware - * had asserted it. - * - * @param gpio A GPIO handle. - * @param pin A GPIO pin. - * @return The result of the operation. - */ -gpio_result_t gpio_irq_force(const gpio_t *gpio, - gpio_pin_t pin); - -/** - * Disables all interrupts, optionally snapshotting all toggle state for later - * restoration. - * - * @param gpio A GPIO handle. - * @param[out] snapshot Out-param for the snapshot; may be `NULL`. - * @return The result of the operation. - */ -gpio_result_t gpio_irq_disable_all(const gpio_t *gpio, - gpio_state_t *snapshot); - -/** - * Restores interrupts from the given snapshot. - * - * This function can be used with `gpio_irq_disable_all()` to temporary - * interrupt save-and-restore. - * - * @param gpio A GPIO handle. - * @param snapshot A snapshot to restore from. - * @return The result of the operation. - */ -gpio_result_t gpio_irq_restore_all(const gpio_t *gpio, - const gpio_state_t *snapshot); - /** * Configures interrupt triggers for a set of pins. * @@ -352,66 +280,79 @@ gpio_result_t gpio_write_all(const gpio_t *gpio, gpio_state_t state); /** - * Writes to the pins identified by a mask. - * - * The actual values on the pins depend on the output enable setting. + * Sets output modes of all pins. * * @param gpio A GPIO handle. - * @param mask Mask that identifies the pins to write to. - * @param state Value to write. + * @param state Output modes of the pins. * @return The result of the operation. */ -gpio_result_t gpio_write_masked(const gpio_t *gpio, - gpio_mask_t mask, - gpio_state_t state); +gpio_result_t gpio_input_set_enabled_all(const gpio_t *gpio, + gpio_state_t state); + /** - * Sets output enable mode of a pin. + * Sets output modes of all pins. * * @param gpio A GPIO handle. * @param pin A GPIO pin. - * @param state Output mode of the pin. + * @param state Output modes of the pins. * @return The result of the operation. */ -gpio_result_t gpio_output_set_enabled(const gpio_t *gpio, - gpio_pin_t pin, - gpio_toggle_t state); +gpio_result_t gpio_input_set_enabled(const gpio_t *gpio, + gpio_pin_t pin, + gpio_state_t state); +/** + * Set all GPIO to 1 + * + * When enabled, all GPIO will be set to 1 + * + * @param gpio A GPIO handle. + * @param state Value to write. + */ +gpio_result_t gpio_set(const gpio_t *gpio, gpio_state_t state); /** - * Sets output modes of all pins. + * Set all GPIO to 0 + * + * When enabled, all GPIO will be set to 0 * * @param gpio A GPIO handle. - * @param state Output modes of the pins. - * @return The result of the operation. + * @param state Value to write. */ -gpio_result_t gpio_output_set_enabled_all(const gpio_t *gpio, - gpio_state_t state); +gpio_result_t gpio_clear(const gpio_t *gpio, gpio_state_t state); + +/** + * Toggle all GPIO + * + * When enabled, all GPIO will be toggled + * + * @param gpio A GPIO handle. + * @param state Value to write. + */ +gpio_result_t gpio_toggle(const gpio_t *gpio, gpio_state_t state); /** - * Sets the output modes of the pins identified by a mask. + * Set the mode regs of a single GPIO * * @param gpio A GPIO handle. - * @param mask Mask that identifies the pins whose output modes will be set. - * @param state Output modes of the pins. + * @param pin A GPIO pin. + * @param state1 Set the higher bit of the mode reg of the pin. + * @param state1 Set the lower bit of the mode reg of the pin. * @return The result of the operation. */ -gpio_result_t gpio_output_set_enabled_masked(const gpio_t *gpio, - gpio_mask_t mask, - gpio_state_t state); +gpio_result_t gpio_set_mode(const gpio_t *gpio, gpio_pin_t pin, + bool state1, bool state2); /** - * Enable noise filter for GPIO inputs. - * - * When enabled, changes in the pin value will be ignored unless stable - * for 16 cycles. + * Set the mode regs of all GPIO * * @param gpio A GPIO handle. - * @param mask Mask that identifies pins to set the filter state of. - * @param state The new toggle state for the filter. + * @param state1 Set the higher 32bits of the mode regs. + * @param state1 Set the lower 32bits of the mode reg. * @return The result of the operation. */ -gpio_result_t gpio_input_noise_filter_set_enabled( - const gpio_t *gpio, gpio_mask_t mask, gpio_toggle_t state); +gpio_result_t gpio_set_mode_all(const gpio_t *gpio, + bool state1, bool state2); #ifdef __cplusplus } // extern "C" diff --git a/sw/device/lib/drivers/gpio/gpio_regs.h b/sw/device/lib/drivers/gpio/gpio_regs.h index 2c187c25d..d2580d78a 100644 --- a/sw/device/lib/drivers/gpio/gpio_regs.h +++ b/sw/device/lib/drivers/gpio/gpio_regs.h @@ -16,84 +16,56 @@ extern "C" { // Register width #define GPIO_PARAM_REG_WIDTH 32 -// Common Interrupt Offsets +// GPIO Mode +#define GPIO_GPIO_MODE_0_OFFSET 0x8 +#define GPIO_GPIO_MODE_1_OFFSET 0xc -// Interrupt State Register -#define GPIO_INTR_STATE_REG_OFFSET 0x0 - -// Interrupt Enable Register -#define GPIO_INTR_ENABLE_REG_OFFSET 0x4 - -// Interrupt Test Register -#define GPIO_INTR_TEST_REG_OFFSET 0x8 +// GPIO Enable +#define GPIO_GPIO_EN_OFFSET 0x80 // GPIO Input data read value -#define GPIO_DATA_IN_REG_OFFSET 0xc +#define GPIO_DATA_IN_REG_OFFSET 0x100 // GPIO direct output data write value -#define GPIO_DIRECT_OUT_REG_OFFSET 0x10 - -// GPIO write data lower with mask. -#define GPIO_MASKED_OUT_LOWER_REG_OFFSET 0x14 -#define GPIO_MASKED_OUT_LOWER_DATA_MASK 0xffff -#define GPIO_MASKED_OUT_LOWER_DATA_OFFSET 0 -#define GPIO_MASKED_OUT_LOWER_DATA_FIELD \ - ((bitfield_field32_t) { .mask = GPIO_MASKED_OUT_LOWER_DATA_MASK, .index = GPIO_MASKED_OUT_LOWER_DATA_OFFSET }) -#define GPIO_MASKED_OUT_LOWER_MASK_MASK 0xffff -#define GPIO_MASKED_OUT_LOWER_MASK_OFFSET 16 -#define GPIO_MASKED_OUT_LOWER_MASK_FIELD \ - ((bitfield_field32_t) { .mask = GPIO_MASKED_OUT_LOWER_MASK_MASK, .index = GPIO_MASKED_OUT_LOWER_MASK_OFFSET }) - -// GPIO write data upper with mask. -#define GPIO_MASKED_OUT_UPPER_REG_OFFSET 0x18 -#define GPIO_MASKED_OUT_UPPER_DATA_MASK 0xffff -#define GPIO_MASKED_OUT_UPPER_DATA_OFFSET 0 -#define GPIO_MASKED_OUT_UPPER_DATA_FIELD \ - ((bitfield_field32_t) { .mask = GPIO_MASKED_OUT_UPPER_DATA_MASK, .index = GPIO_MASKED_OUT_UPPER_DATA_OFFSET }) -#define GPIO_MASKED_OUT_UPPER_MASK_MASK 0xffff -#define GPIO_MASKED_OUT_UPPER_MASK_OFFSET 16 -#define GPIO_MASKED_OUT_UPPER_MASK_FIELD \ - ((bitfield_field32_t) { .mask = GPIO_MASKED_OUT_UPPER_MASK_MASK, .index = GPIO_MASKED_OUT_UPPER_MASK_OFFSET }) - -// GPIO Output Enable. -#define GPIO_DIRECT_OE_REG_OFFSET 0x1c - -// GPIO write Output Enable lower with mask. -#define GPIO_MASKED_OE_LOWER_REG_OFFSET 0x20 -#define GPIO_MASKED_OE_LOWER_DATA_MASK 0xffff -#define GPIO_MASKED_OE_LOWER_DATA_OFFSET 0 -#define GPIO_MASKED_OE_LOWER_DATA_FIELD \ - ((bitfield_field32_t) { .mask = GPIO_MASKED_OE_LOWER_DATA_MASK, .index = GPIO_MASKED_OE_LOWER_DATA_OFFSET }) -#define GPIO_MASKED_OE_LOWER_MASK_MASK 0xffff -#define GPIO_MASKED_OE_LOWER_MASK_OFFSET 16 -#define GPIO_MASKED_OE_LOWER_MASK_FIELD \ - ((bitfield_field32_t) { .mask = GPIO_MASKED_OE_LOWER_MASK_MASK, .index = GPIO_MASKED_OE_LOWER_MASK_OFFSET }) - -// GPIO write Output Enable upper with mask. -#define GPIO_MASKED_OE_UPPER_REG_OFFSET 0x24 -#define GPIO_MASKED_OE_UPPER_DATA_MASK 0xffff -#define GPIO_MASKED_OE_UPPER_DATA_OFFSET 0 -#define GPIO_MASKED_OE_UPPER_DATA_FIELD \ - ((bitfield_field32_t) { .mask = GPIO_MASKED_OE_UPPER_DATA_MASK, .index = GPIO_MASKED_OE_UPPER_DATA_OFFSET }) -#define GPIO_MASKED_OE_UPPER_MASK_MASK 0xffff -#define GPIO_MASKED_OE_UPPER_MASK_OFFSET 16 -#define GPIO_MASKED_OE_UPPER_MASK_FIELD \ - ((bitfield_field32_t) { .mask = GPIO_MASKED_OE_UPPER_MASK_MASK, .index = GPIO_MASKED_OE_UPPER_MASK_OFFSET }) +#define GPIO_DIRECT_OUT_REG_OFFSET 0x180 + +// GPIO Set +#define GPIO_GPIO_SET_OFFSET 0x200 + +// GPIO Clear +#define GPIO_GPIO_CLEAR_OFFSET 0x280 + +// GPIO Toggle +#define GPIO_GPIO_TOGGLE_OFFSET 0x300 // GPIO interrupt enable for GPIO, rising edge. -#define GPIO_INTR_CTRL_EN_RISING_REG_OFFSET 0x28 +#define GPIO_INTR_CTRL_EN_RISING_REG_OFFSET 0x380 // GPIO interrupt enable for GPIO, falling edge. -#define GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET 0x2c +#define GPIO_INTR_CTRL_EN_FALLING_REG_OFFSET 0x400 // GPIO interrupt enable for GPIO, level high. -#define GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET 0x30 +#define GPIO_INTR_CTRL_EN_LVLHIGH_REG_OFFSET 0x480 // GPIO interrupt enable for GPIO, level low. -#define GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET 0x34 +#define GPIO_INTR_CTRL_EN_LVLLOW_REG_OFFSET 0x500 + + +// GPIO interrupt status for GPIO +#define GPIO_INTRPT_STATUS_OFFSET 0x580 + +// GPIO interrupt status for GPIO, falling edge. +#define GPIO_INTRPT_RISE_STATUS_OFFSET 0x600 + +// GPIO interrupt status for GPIO, level high. +#define GPIO_INTRPT_FALL_STATUS_OFFSET 0x680 + +// GPIO interrupt status for GPIO, level low. +#define GPIO_INTRPT_LVL_HIGH_STATUS_OFFSET 0x700 + +// GPIO interrupt status for GPIO, level low. +#define GPIO_INTRPT_LVL_LOW_STATUS_OFFSET 0x780 -// filter enable for GPIO input bits. -#define GPIO_CTRL_EN_INPUT_FILTER_REG_OFFSET 0x38 #ifdef __cplusplus } // extern "C" diff --git a/sw/device/lib/drivers/padframe/include/bitfield.h b/sw/device/lib/drivers/padframe/include/bitfield.h new file mode 100644 index 000000000..3177f1491 --- /dev/null +++ b/sw/device/lib/drivers/padframe/include/bitfield.h @@ -0,0 +1,285 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef OPENTITAN_SW_DEVICE_LIB_BASE_BITFIELD_H_ +#define OPENTITAN_SW_DEVICE_LIB_BASE_BITFIELD_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif // __cplusplus + +/** + * @file + * @brief Bitfield Manipulation Functions + */ + +/** + * All the bitfield functions are pure (they do not modify their arguments), so + * the result must be used. We enable warnings to ensure this happens. + */ +#define BITFIELD_WARN_UNUSED_RESULT __attribute__((warn_unused_result)) + +/** + * A field of a 32-bit bitfield. + * + * The following field definition: `{ .mask = 0b11, .index = 12 }` + * + * Denotes the X-marked bits in the following 32-bit bitfield: + * + * field: 0b--------'--------'--XX----'-------- + * index: 31 0 + * + * Restrictions: The index plus the width of the mask must not be greater than + * 31. + */ +typedef struct bitfield_field32 { + /** The field mask. Usually all ones. */ + uint32_t mask; + /** The field position in the bitfield, counting from the zero-bit. */ + uint32_t index; +} bitfield_field32_t; + +/** + * Reads a value from `field` in `bitfield`. + * + * This function uses the `field` parameter to read the value from `bitfield`. + * The resulting value will be shifted right and zero-extended so the field's + * zero-bit is the return value's zero-bit. + * + * @param bitfield Bitfield to get the field from. + * @param field Field to read out from. + * @return Zero-extended `field` from `bitfield`. + */ +BITFIELD_WARN_UNUSED_RESULT +inline uint32_t bitfield_field32_read(uint32_t bitfield, + bitfield_field32_t field) { + return (bitfield >> field.index) & field.mask; +} + +/** + * Writes `value` to `field` in `bitfield`. + * + * This function uses the `field` parameter to set specific bits in `bitfield`. + * The relevant portion of `bitfield` is zeroed before the bits are set to + * `value`. + * + * @param bitfield Bitfield to set the field in. + * @param field Field within bitfield to be set. + * @param value Value for the new field. + * @return `bitfield` with `field` set to `value`. + */ +BITFIELD_WARN_UNUSED_RESULT +inline uint32_t bitfield_field32_write(uint32_t bitfield, + bitfield_field32_t field, + uint32_t value) { + bitfield &= ~(field.mask << field.index); + bitfield |= (value & field.mask) << field.index; + return bitfield; +} + +/** + * A single bit in a 32-bit bitfield. + * + * This denotes the position of a single bit, counting from the zero-bit. + * + * For instance, `(bitfield_bit_index_t)4` denotes the X-marked bit in the + * following 32-bit bitfield: + * + * field: 0b--------'--------'--------'---X---- + * index: 31 0 + * + * Restrictions: The value must not be greater than 31. + */ +typedef uint32_t bitfield_bit32_index_t; + +/** + * Turns a `bitfield_bit32_index_t` into a `bitfield_field32_t` (which is more + * general). + * + * @param bit_index The corresponding single bit to turn into a field. + * @return A 1-bit field that corresponds to `bit_index`. + */ +BITFIELD_WARN_UNUSED_RESULT +inline bitfield_field32_t bitfield_bit32_to_field32( + bitfield_bit32_index_t bit_index) { + return (bitfield_field32_t){ + .mask = 0x1, .index = bit_index, + }; +} + +/** + * Reads the `bit_index`th bit in `bitfield`. + * + * @param bitfield Bitfield to get the bit from. + * @param bit_index Bit to read. + * @return `true` if the bit was one, `false` otherwise. + */ +BITFIELD_WARN_UNUSED_RESULT +inline bool bitfield_bit32_read(uint32_t bitfield, + bitfield_bit32_index_t bit_index) { + return bitfield_field32_read(bitfield, + bitfield_bit32_to_field32(bit_index)) == 0x1u; +} + +/** + * Writes `value` to the `bit_index`th bit in `bitfield`. + * + * @param bitfield Bitfield to update the bit in. + * @param bit_index Bit to update. + * @param value Bit value to write to `bitfield`. + * @return `bitfield` with the `bit_index`th bit set to `value`. + */ +BITFIELD_WARN_UNUSED_RESULT +inline uint32_t bitfield_bit32_write(uint32_t bitfield, + bitfield_bit32_index_t bit_index, + bool value) { + return bitfield_field32_write(bitfield, bitfield_bit32_to_field32(bit_index), + value ? 0x1u : 0x0u); +} + +/** + * Find First Set Bit + * + * Returns one plus the index of the least-significant 1-bit of a 32-bit word. + * + * For instance, `bitfield_find_first_set32(field)` of the below 32-bit value + * returns `5`. + * + * field: 0b00000000'00000000'11111111'00010000 + * index: 31 0 + * + * This is the canonical definition for the GCC/Clang builtin `__builtin_ffs`, + * and hence takes and returns a signed integer. + * + * @param bitfield Bitfield to find the first set bit in. + * @return One plus the index of the least-significant 1-bit of `bitfield`. + */ +BITFIELD_WARN_UNUSED_RESULT +inline int32_t bitfield_find_first_set32(int32_t bitfield) { + return __builtin_ffs(bitfield); +} + +/** + * Count Leading Zeroes + * + * Returns the number of leading 0-bits in `bitfield`, starting at the most + * significant bit position. If `bitfield` is 0, the result is 32, to match the + * RISC-V B Extension. + * + * For instance, `bitfield_count_leading_zeroes32(field)` of the below 32-bit + * value returns `16`. + * + * field: 0b00000000'00000000'11111111'00010000 + * index: 31 0 + * + * This is the canonical definition for the GCC/Clang builtin `__builtin_clz`, + * and hence returns a signed integer. + * + * @param bitfield Bitfield to count leading 0-bits from. + * @return The number of leading 0-bits in `bitfield`. + */ +BITFIELD_WARN_UNUSED_RESULT +inline int32_t bitfield_count_leading_zeroes32(uint32_t bitfield) { + return (bitfield != 0) ? __builtin_clz(bitfield) : 32; +} + +/** + * Count Trailing Zeroes + * + * Returns the number of trailing 0-bits in `bitfield`, starting at the least + * significant bit position. If `bitfield` is 0, the result is 32, to match the + * RISC-V B Extension. + * + * For instance, `bitfield_count_trailing_zeroes32(field)` of the below 32-bit + * value returns `4`. + * + * field: 0b00000000'00000000'11111111'00010000 + * index: 31 0 + * + * This is the canonical definition for the GCC/Clang builtin `__builtin_ctz`, + * and hence returns a signed integer. + * + * @param bitfield Bitfield to count trailing 0-bits from. + * @return The number of trailing 0-bits in `bitfield`. + */ +BITFIELD_WARN_UNUSED_RESULT +inline int32_t bitfield_count_trailing_zeroes32(uint32_t bitfield) { + return (bitfield != 0) ? __builtin_ctz(bitfield) : 32; +} + +/** + * Count Set Bits + * + * Returns the number of 1-bits in `bitfield`. + * + * For instance, `bitfield_popcount32(field)` of the below 32-bit value returns + * `9`. + * + * field: 0b00000000'00000000'11111111'00010000 + * index: 31 0 + * + * This is the canonical definition for the GCC/Clang builtin + * `__builtin_popcount`, and hence returns a signed integer. + * + * @param bitfield Bitfield to count 1-bits from. + * @return The number of 1-bits in `bitfield`. + */ +BITFIELD_WARN_UNUSED_RESULT +inline int32_t bitfield_popcount32(uint32_t bitfield) { + return __builtin_popcount(bitfield); +} + +/** + * Parity + * + * Returns the number of 1-bits in `bitfield`, modulo 2. + * + * For instance, `bitfield_parity32(field)` of the below 32-bit value returns + * `1`. + * + * field: 0b00000000'00000000'11111111'00010000 + * index: 31 0 + * + * This is the canonical definition for the GCC/Clang builtin + * `__builtin_parity`, and hence returns a signed integer. + * + * @param bitfield Bitfield to count 1-bits from. + * @return The number of 1-bits in `bitfield`, modulo 2. + */ +BITFIELD_WARN_UNUSED_RESULT +inline int32_t bitfield_parity32(uint32_t bitfield) { + return __builtin_parity(bitfield); +} + +/** + * Byte Swap + * + * Returns `field` with the order of the bytes reversed. Bytes here always means + * exactly 8 bits. + * + * For instance, `byteswap(field)` of the below 32-bit value returns `1`. + * + * field: 0bAAAAAAAA'BBBBBBBB'CCCCCCCC'DDDDDDDD + * index: 31 0 + * returns: 0bDDDDDDDD'CCCCCCCC'BBBBBBBB'AAAAAAAA + * + * This is the canonical definition for the GCC/Clang builtin + * `__builtin_bswap32`. + * + * @param bitfield Bitfield to reverse bytes of. + * @return `bitfield` with the order of bytes reversed. + */ +BITFIELD_WARN_UNUSED_RESULT +inline uint32_t bitfield_byteswap32(uint32_t bitfield) { + return __builtin_bswap32(bitfield); +} + +#ifdef __cplusplus +} // extern "C" +#endif // __cplusplus + +#endif // OPENTITAN_SW_DEVICE_LIB_BASE_BITFIELD_H_ diff --git a/sw/device/lib/drivers/padframe/include/padframe.h b/sw/device/lib/drivers/padframe/include/padframe.h new file mode 100644 index 000000000..9e93cc99a --- /dev/null +++ b/sw/device/lib/drivers/padframe/include/padframe.h @@ -0,0 +1,113 @@ + +#ifndef PADFRAME_H +#define PADFRAME_H +#include + +#ifndef PADFRAME_BASE_ADDRESS +#error "PADFRAME_BASE_ADDRESS is not defined. Set this token to the configuration base address of your padframe before you include this header file." +#endif + + + +/** + * Sets the chip2pad pad signal for the pad: pad_io_30 + * + * @param value The value to program into the pad configuration register. A value smaller than 1. + */ +void padframe_xheep_pad_io_30_cfg_chip2pad_set(uint8_t value); + +/** + * Get the currently configured chip2pad value for the pad: pad_io_30 + * + * @return The value of the chip2pad field + */ +uint8_t padframe_xheep_pad_io_30_cfg_chip2pad_get(); + +/** + * Sets the output_en pad signal for the pad: pad_io_30 + * + * @param value The value to program into the pad configuration register. A value smaller than 1. + */ +void padframe_xheep_pad_io_30_cfg_output_en_set(uint8_t value); + +/** + * Get the currently configured output_en value for the pad: pad_io_30 + * + * @return The value of the output_en field + */ +uint8_t padframe_xheep_pad_io_30_cfg_output_en_get(); + +typedef enum { + PADFRAME_XHEEP_PAD_IO_30_REGISTER = 0, + PADFRAME_XHEEP_PAD_IO_30_group_GPIO_port_GPIO_30 = 1, + PADFRAME_XHEEP_PAD_IO_30_group_I2C_port_I2C_SDA = 2, +} padframe_xheep_pad_io_30_mux_sel_t; + +/** + * Choose the entity (a port or the dedicated configuration register) that controls pad_io_30. + * + * @param mux_sel Port or configuration register to connect to the pad. + */ +void padframe_xheep_pad_io_30_mux_set(padframe_xheep_pad_io_30_mux_sel_t mux_sel); + +/** + * Read the current multiplexer select value configured for pad_io_30. + * + * @return Port or configuration register currently connected to the pad. + */ + padframe_xheep_pad_io_30_mux_sel_t padframe_xheep_pad_io_30_mux_get(); + + + +/** + * Sets the chip2pad pad signal for the pad: pad_io_31 + * + * @param value The value to program into the pad configuration register. A value smaller than 1. + */ +void padframe_xheep_pad_io_31_cfg_chip2pad_set(uint8_t value); + +/** + * Get the currently configured chip2pad value for the pad: pad_io_31 + * + * @return The value of the chip2pad field + */ +uint8_t padframe_xheep_pad_io_31_cfg_chip2pad_get(); + +/** + * Sets the output_en pad signal for the pad: pad_io_31 + * + * @param value The value to program into the pad configuration register. A value smaller than 1. + */ +void padframe_xheep_pad_io_31_cfg_output_en_set(uint8_t value); + +/** + * Get the currently configured output_en value for the pad: pad_io_31 + * + * @return The value of the output_en field + */ +uint8_t padframe_xheep_pad_io_31_cfg_output_en_get(); + +typedef enum { + PADFRAME_XHEEP_PAD_IO_31_REGISTER = 0, + PADFRAME_XHEEP_PAD_IO_31_group_GPIO_port_GPIO_31 = 1, + PADFRAME_XHEEP_PAD_IO_31_group_I2C_port_I2C_SCL = 2, +} padframe_xheep_pad_io_31_mux_sel_t; + +/** + * Choose the entity (a port or the dedicated configuration register) that controls pad_io_31. + * + * @param mux_sel Port or configuration register to connect to the pad. + */ +void padframe_xheep_pad_io_31_mux_set(padframe_xheep_pad_io_31_mux_sel_t mux_sel); + +/** + * Read the current multiplexer select value configured for pad_io_31. + * + * @return Port or configuration register currently connected to the pad. + */ + padframe_xheep_pad_io_31_mux_sel_t padframe_xheep_pad_io_31_mux_get(); + + + + +#endif /* PADFRAME_H */ diff --git a/sw/device/lib/drivers/padframe/include/padframe_driver.h b/sw/device/lib/drivers/padframe/include/padframe_driver.h new file mode 100644 index 000000000..6f53e92e6 --- /dev/null +++ b/sw/device/lib/drivers/padframe/include/padframe_driver.h @@ -0,0 +1,5 @@ + +#include "core_v_mini_mcu.h" +#define PADFRAME_BASE_ADDRESS PADFRAME_START_ADDRESS + +#include "padframe.h" \ No newline at end of file diff --git a/sw/device/lib/drivers/padframe/include/padframe_xheep_regs.h b/sw/device/lib/drivers/padframe/include/padframe_xheep_regs.h new file mode 100644 index 000000000..df584c868 --- /dev/null +++ b/sw/device/lib/drivers/padframe/include/padframe_xheep_regs.h @@ -0,0 +1,67 @@ +// Generated register defines for padframe_xheep_config + +// Licensing information found in source file: + +#ifndef _PADFRAME_XHEEP_CONFIG_REG_DEFS_ +#define _PADFRAME_XHEEP_CONFIG_REG_DEFS_ + +#ifdef __cplusplus +extern "C" { +#endif +// Register width +#define PADFRAME_XHEEP_CONFIG_PARAM_REG_WIDTH 32 + +// Read-only IP Information register +#define PADFRAME_XHEEP_CONFIG_INFO_REG_OFFSET 0x0 +#define PADFRAME_XHEEP_CONFIG_INFO_HW_VERSION_MASK 0xffff +#define PADFRAME_XHEEP_CONFIG_INFO_HW_VERSION_OFFSET 0 +#define PADFRAME_XHEEP_CONFIG_INFO_HW_VERSION_FIELD \ + ((bitfield_field32_t) { .mask = PADFRAME_XHEEP_CONFIG_INFO_HW_VERSION_MASK, .index = PADFRAME_XHEEP_CONFIG_INFO_HW_VERSION_OFFSET }) +#define PADFRAME_XHEEP_CONFIG_INFO_PADCOUNT_MASK 0xffff +#define PADFRAME_XHEEP_CONFIG_INFO_PADCOUNT_OFFSET 16 +#define PADFRAME_XHEEP_CONFIG_INFO_PADCOUNT_FIELD \ + ((bitfield_field32_t) { .mask = PADFRAME_XHEEP_CONFIG_INFO_PADCOUNT_MASK, .index = PADFRAME_XHEEP_CONFIG_INFO_PADCOUNT_OFFSET }) + +// Pad signal configuration. +#define PADFRAME_XHEEP_CONFIG_PAD_IO_30_CFG_REG_OFFSET 0x4 +#define PADFRAME_XHEEP_CONFIG_PAD_IO_30_CFG_CHIP2PAD_BIT 0 +#define PADFRAME_XHEEP_CONFIG_PAD_IO_30_CFG_OUTPUT_EN_BIT 1 + +// Pad signal port multiplex selection for pad pad_io_30. The programmed +// value defines which port +#define PADFRAME_XHEEP_CONFIG_PAD_IO_30_MUX_SEL_REG_OFFSET 0x8 +#define PADFRAME_XHEEP_CONFIG_PAD_IO_30_MUX_SEL_PAD_IO_30_MUX_SEL_MASK 0x3 +#define PADFRAME_XHEEP_CONFIG_PAD_IO_30_MUX_SEL_PAD_IO_30_MUX_SEL_OFFSET 0 +#define PADFRAME_XHEEP_CONFIG_PAD_IO_30_MUX_SEL_PAD_IO_30_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PADFRAME_XHEEP_CONFIG_PAD_IO_30_MUX_SEL_PAD_IO_30_MUX_SEL_MASK, .index = PADFRAME_XHEEP_CONFIG_PAD_IO_30_MUX_SEL_PAD_IO_30_MUX_SEL_OFFSET }) +#define PADFRAME_XHEEP_CONFIG_PAD_IO_30_MUX_SEL_PAD_IO_30_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PADFRAME_XHEEP_CONFIG_PAD_IO_30_MUX_SEL_PAD_IO_30_MUX_SEL_VALUE_PORT_GPIO_GPIO_30 \ + 0x1 +#define PADFRAME_XHEEP_CONFIG_PAD_IO_30_MUX_SEL_PAD_IO_30_MUX_SEL_VALUE_PORT_I2C_I2C_SDA \ + 0x2 + +// Pad signal configuration. +#define PADFRAME_XHEEP_CONFIG_PAD_IO_31_CFG_REG_OFFSET 0xc +#define PADFRAME_XHEEP_CONFIG_PAD_IO_31_CFG_CHIP2PAD_BIT 0 +#define PADFRAME_XHEEP_CONFIG_PAD_IO_31_CFG_OUTPUT_EN_BIT 1 + +// Pad signal port multiplex selection for pad pad_io_31. The programmed +// value defines which port +#define PADFRAME_XHEEP_CONFIG_PAD_IO_31_MUX_SEL_REG_OFFSET 0x10 +#define PADFRAME_XHEEP_CONFIG_PAD_IO_31_MUX_SEL_PAD_IO_31_MUX_SEL_MASK 0x3 +#define PADFRAME_XHEEP_CONFIG_PAD_IO_31_MUX_SEL_PAD_IO_31_MUX_SEL_OFFSET 0 +#define PADFRAME_XHEEP_CONFIG_PAD_IO_31_MUX_SEL_PAD_IO_31_MUX_SEL_FIELD \ + ((bitfield_field32_t) { .mask = PADFRAME_XHEEP_CONFIG_PAD_IO_31_MUX_SEL_PAD_IO_31_MUX_SEL_MASK, .index = PADFRAME_XHEEP_CONFIG_PAD_IO_31_MUX_SEL_PAD_IO_31_MUX_SEL_OFFSET }) +#define PADFRAME_XHEEP_CONFIG_PAD_IO_31_MUX_SEL_PAD_IO_31_MUX_SEL_VALUE_REGISTER \ + 0x0 +#define PADFRAME_XHEEP_CONFIG_PAD_IO_31_MUX_SEL_PAD_IO_31_MUX_SEL_VALUE_PORT_GPIO_GPIO_31 \ + 0x1 +#define PADFRAME_XHEEP_CONFIG_PAD_IO_31_MUX_SEL_PAD_IO_31_MUX_SEL_VALUE_PORT_I2C_I2C_SCL \ + 0x2 + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _PADFRAME_XHEEP_CONFIG_REG_DEFS_ +// End generated register defines for padframe_xheep_config \ No newline at end of file diff --git a/sw/device/lib/drivers/padframe/padframe_xheep_regs.hjson b/sw/device/lib/drivers/padframe/padframe_xheep_regs.hjson new file mode 100644 index 000000000..ac80674d9 --- /dev/null +++ b/sw/device/lib/drivers/padframe/padframe_xheep_regs.hjson @@ -0,0 +1,192 @@ + +{ + # File auto-generated by Padrick 0.3.1.post0.dev2+ge09286c + name: "padframe_xheep_config" + clock_primary: "clk_i" + reset_primary: "rst_ni" + bus_interfaces: [ + { protocol: "reg_iface", direction: "device"} + ] + regwidth: 32, + registers: [ + {skipto: "0x0"}, + { + name: INFO + desc: "Read-only IP Information register" + swaccess: "ro" + hwaccess: "hro" + fields: [ + { + bits: "15:0" + name: HW_VERSION + desc: "Hardware version ID." + resval: 2 + }, + { + bits:"31:16" + name: PADCOUNT + desc: "The number of muxable pads in this IP." + resval: "2" + } + ] + } + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + { + name: PAD_IO_30_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: output_en + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO_30_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io_30. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 2 + fields: [ + { + bits: "1:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_gpio_gpio_30", desc: "Connect port gpio_30 from port group gpio to this pad." } + { value: "2", name: "port_i2c_i2c_sda", desc: "Connect port i2c_sda from port group i2c to this pad." } + ] + } + ] + } + + { + name: PAD_IO_31_CFG + desc: ''' + Pad signal configuration. + ''' + swaccess: "rw" + fields: [ + { + bits: "0" + name: chip2pad + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + { + bits: "1" + name: output_en + desc: ''' + + ''' + swaccess: "rw" + hwaccess: "hro" + resval: "0" + }, + ] + } + + { + name: PAD_IO_31_MUX_SEL + desc: ''' + Pad signal port multiplex selection for pad pad_io_31. The programmed value defines which port + is connected to the pad. + ''' + swaccess: "rw" + hwaccess: "hro" + resval: 2 + fields: [ + { + bits: "1:0" + enum: [ + { value: "0", name: "register", desc: "Connects the Pad to the internal configuration register."} + { value: "1", name: "port_gpio_gpio_31", desc: "Connect port gpio_31 from port group gpio to this pad." } + { value: "2", name: "port_i2c_i2c_scl", desc: "Connect port i2c_scl from port group i2c to this pad." } + ] + } + ] + } + + ] +} diff --git a/sw/device/lib/drivers/padframe/src/padframe.c b/sw/device/lib/drivers/padframe/src/padframe.c new file mode 100644 index 000000000..9cecc1a67 --- /dev/null +++ b/sw/device/lib/drivers/padframe/src/padframe.c @@ -0,0 +1,83 @@ + +#include "padframe.h" +#define PADFRAME_XHEEP_CONFIG0_BASE_ADDR PADFRAME_BASE_ADDRESS +#include "padframe_xheep_regs.h" +#include "bitfield.h" + +#define REG_WRITE32(addr, value) *((volatile uint32_t*) addr) = (uint32_t) value; +#define REG_READ32(addr) *((volatile uint32_t*) addr) + + +void padframe_xheep_pad_io_30_cfg_chip2pad_set(uint8_t value) { + uint32_t address = PADFRAME_BASE_ADDRESS + PADFRAME_XHEEP_CONFIG_PAD_IO_30_CFG_REG_OFFSET; + uint32_t reg = REG_READ32(address); + reg = bitfield_bit32_write(reg, PADFRAME_XHEEP_CONFIG_PAD_IO_30_CFG_CHIP2PAD_BIT, value); + REG_WRITE32(address, reg); +} + +uint8_t padframe_xheep_pad_io_30_cfg_chip2pad_get() { + uint32_t address = PADFRAME_BASE_ADDRESS + PADFRAME_XHEEP_CONFIG_PAD_IO_30_CFG_REG_OFFSET; + uint32_t reg = REG_READ32(address); + return bitfield_bit32_read(reg, PADFRAME_XHEEP_CONFIG_PAD_IO_30_CFG_CHIP2PAD_BIT); +} + +void padframe_xheep_pad_io_30_cfg_output_en_set(uint8_t value) { + uint32_t address = PADFRAME_BASE_ADDRESS + PADFRAME_XHEEP_CONFIG_PAD_IO_30_CFG_REG_OFFSET; + uint32_t reg = REG_READ32(address); + reg = bitfield_bit32_write(reg, PADFRAME_XHEEP_CONFIG_PAD_IO_30_CFG_OUTPUT_EN_BIT, value); + REG_WRITE32(address, reg); +} + +uint8_t padframe_xheep_pad_io_30_cfg_output_en_get() { + uint32_t address = PADFRAME_BASE_ADDRESS + PADFRAME_XHEEP_CONFIG_PAD_IO_30_CFG_REG_OFFSET; + uint32_t reg = REG_READ32(address); + return bitfield_bit32_read(reg, PADFRAME_XHEEP_CONFIG_PAD_IO_30_CFG_OUTPUT_EN_BIT); +} + +void padframe_xheep_pad_io_30_mux_set(padframe_xheep_pad_io_30_mux_sel_t mux_sel) { + const uint32_t address = PADFRAME_BASE_ADDRESS + PADFRAME_XHEEP_CONFIG_PAD_IO_30_MUX_SEL_REG_OFFSET; + REG_WRITE32(address, mux_sel & 3); +} + +padframe_xheep_pad_io_30_mux_sel_t padframe_xheep_pad_io_30_mux_get() { + const uint32_t address = PADFRAME_BASE_ADDRESS + PADFRAME_XHEEP_CONFIG_PAD_IO_30_MUX_SEL_REG_OFFSET; + + return REG_READ32(address) & 3; +} + +void padframe_xheep_pad_io_31_cfg_chip2pad_set(uint8_t value) { + uint32_t address = PADFRAME_BASE_ADDRESS + PADFRAME_XHEEP_CONFIG_PAD_IO_31_CFG_REG_OFFSET; + uint32_t reg = REG_READ32(address); + reg = bitfield_bit32_write(reg, PADFRAME_XHEEP_CONFIG_PAD_IO_31_CFG_CHIP2PAD_BIT, value); + REG_WRITE32(address, reg); +} + +uint8_t padframe_xheep_pad_io_31_cfg_chip2pad_get() { + uint32_t address = PADFRAME_BASE_ADDRESS + PADFRAME_XHEEP_CONFIG_PAD_IO_31_CFG_REG_OFFSET; + uint32_t reg = REG_READ32(address); + return bitfield_bit32_read(reg, PADFRAME_XHEEP_CONFIG_PAD_IO_31_CFG_CHIP2PAD_BIT); +} + +void padframe_xheep_pad_io_31_cfg_output_en_set(uint8_t value) { + uint32_t address = PADFRAME_BASE_ADDRESS + PADFRAME_XHEEP_CONFIG_PAD_IO_31_CFG_REG_OFFSET; + uint32_t reg = REG_READ32(address); + reg = bitfield_bit32_write(reg, PADFRAME_XHEEP_CONFIG_PAD_IO_31_CFG_OUTPUT_EN_BIT, value); + REG_WRITE32(address, reg); +} + +uint8_t padframe_xheep_pad_io_31_cfg_output_en_get() { + uint32_t address = PADFRAME_BASE_ADDRESS + PADFRAME_XHEEP_CONFIG_PAD_IO_31_CFG_REG_OFFSET; + uint32_t reg = REG_READ32(address); + return bitfield_bit32_read(reg, PADFRAME_XHEEP_CONFIG_PAD_IO_31_CFG_OUTPUT_EN_BIT); +} + +void padframe_xheep_pad_io_31_mux_set(padframe_xheep_pad_io_31_mux_sel_t mux_sel) { + const uint32_t address = PADFRAME_BASE_ADDRESS + PADFRAME_XHEEP_CONFIG_PAD_IO_31_MUX_SEL_REG_OFFSET; + REG_WRITE32(address, mux_sel & 3); +} + +padframe_xheep_pad_io_31_mux_sel_t padframe_xheep_pad_io_31_mux_get() { + const uint32_t address = PADFRAME_BASE_ADDRESS + PADFRAME_XHEEP_CONFIG_PAD_IO_31_MUX_SEL_REG_OFFSET; + + return REG_READ32(address) & 3; +} diff --git a/sw/device/lib/drivers/padframe/src/padframe_driver.c b/sw/device/lib/drivers/padframe/src/padframe_driver.c new file mode 100644 index 000000000..da79a2382 --- /dev/null +++ b/sw/device/lib/drivers/padframe/src/padframe_driver.c @@ -0,0 +1,5 @@ +#include "padframe_driver.h" + +#include "../src/padframe.c" + +//This is the glue-logic c file for other generated driver files \ No newline at end of file diff --git a/sw/device/lib/runtime/core_v_mini_mcu.h.tpl b/sw/device/lib/runtime/core_v_mini_mcu.h.tpl index 53f5e8a48..6baece6c0 100644 --- a/sw/device/lib/runtime/core_v_mini_mcu.h.tpl +++ b/sw/device/lib/runtime/core_v_mini_mcu.h.tpl @@ -60,9 +60,9 @@ extern "C" { #define EXT_PERIPHERAL_SIZE 0x${ext_periph_size_address} #define EXT_PERIPHERAL_END_ADDRESS (EXT_PERIPHERAL_START_ADDRESS + EXT_PERIPHERAL_SIZE) -#define PAD_CONTROL_START_ADDRESS (AO_PERIPHERAL_START_ADDRESS + 0x${pad_control_start_offset}) -#define PAD_CONTROL_SIZE 0x${pad_control_size_address} -#define PAD_CONTROL_END_ADDRESS (PAD_CONTROL_START_ADDRESS + PAD_CONTROL_SIZE) +#define PADFRAME_START_ADDRESS (AO_PERIPHERAL_START_ADDRESS + 0x${padframe_start_offset}) +#define PADFRAME_SIZE 0x${padframe_size_address} +#define PADFRAME_END_ADDRESS (PADFRAME_START_ADDRESS + PADFRAME_SIZE) #define GPIO_AO_START_ADDRESS (AO_PERIPHERAL_START_ADDRESS + 0x${gpio_ao_start_offset}) #define GPIO_AO_SIZE 0x${gpio_ao_size_address} diff --git a/util/mcu_gen.py b/util/mcu_gen.py index fb443f0fb..67afd6c00 100755 --- a/util/mcu_gen.py +++ b/util/mcu_gen.py @@ -437,8 +437,8 @@ def main(): ext_periph_start_offset = string2int(obj['ao_peripherals']['ext_periph']['offset']) ext_periph_size_address = string2int(obj['ao_peripherals']['ext_periph']['length']) - pad_control_start_offset = string2int(obj['ao_peripherals']['pad_control']['offset']) - pad_control_size_address = string2int(obj['ao_peripherals']['pad_control']['length']) + padframe_start_offset = string2int(obj['ao_peripherals']['padframe']['offset']) + padframe_size_address = string2int(obj['ao_peripherals']['padframe']['length']) gpio_ao_start_offset = string2int(obj['ao_peripherals']['gpio_ao']['offset']) gpio_ao_size_address = string2int(obj['ao_peripherals']['gpio_ao']['length']) @@ -822,8 +822,8 @@ def main(): "fast_intr_ctrl_size_address" : fast_intr_ctrl_size_address, "ext_periph_start_offset" : ext_periph_start_offset, "ext_periph_size_address" : ext_periph_size_address, - "pad_control_start_offset" : pad_control_start_offset, - "pad_control_size_address" : pad_control_size_address, + "padframe_start_offset" : padframe_start_offset, + "padframe_size_address" : padframe_size_address, "gpio_ao_start_offset" : gpio_ao_start_offset, "gpio_ao_size_address" : gpio_ao_size_address, "uart_start_offset" : uart_start_offset,