diff --git a/litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v b/litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v index 384334d..1861e7f 100644 --- a/litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v +++ b/litepcie/phy/xilinx_us/m_axis_cq_adapt_x4.v @@ -64,7 +64,7 @@ module m_axis_cq_adapt # ( else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0; else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a) begin - if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'b1; //read + if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'd1; //read else if (m_axis_cq_tlast_dly_en) m_axis_cq_tlast_lat <= 1'b1; end @@ -77,8 +77,8 @@ module m_axis_cq_adapt # ( ////keep address (low) or data (high), not header - reg [DATA_WIDTH-1:0] m_axis_cq_tdata_a1; - reg [DATA_WIDTH/8-1:0] m_axis_cq_tlast_be1; + reg [127:0] m_axis_cq_tdata_a1; + reg [15:0] m_axis_cq_tlast_be1; always @(posedge user_clk) if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) begin @@ -89,15 +89,15 @@ module m_axis_cq_adapt # ( //data processing wire [63:0] m_axis_cq_tdata_hdr = m_axis_cq_tdata_a[127:64]; - assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; - wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; - wire m_axis_cq_ep = 1'b0; - wire m_axis_cq_td = 1'b0; - wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; + assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; + wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; + wire m_axis_cq_ep = 1'b0; + wire m_axis_cq_td = 1'b0; + wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; wire [4:0] m_axis_cq_type; wire [2:0] m_axis_cq_fmt; - wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0]; - wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; + wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0]; + wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; wire [15:0] m_axis_cq_requesterid = m_axis_cq_tdata_hdr[31:16]; assign {m_axis_cq_fmt, m_axis_cq_type} = m_axis_cq_tdata_hdr[14:11] == 4'b0000 ? 8'b000_00000 : //Mem read Request @@ -125,15 +125,13 @@ module m_axis_cq_adapt # ( reg [63:0] m_axis_cq_header; always @(posedge user_clk) if (m_axis_cq_tvalid_a && m_axis_cq_sop) - m_axis_cq_header = { - m_axis_cq_requesterid, - m_axis_cq_tag, - m_axis_cq_be, - m_axis_cq_fmt, m_axis_cq_type, - 1'b0, m_axis_cq_tc, 4'b0, - m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, - 2'b0, m_axis_cq_dwlen - }; + m_axis_cq_header = {m_axis_cq_requesterid, + m_axis_cq_tag, + m_axis_cq_be, + m_axis_cq_fmt, m_axis_cq_type, + 1'b0, m_axis_cq_tc, 4'b0, + m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, + 2'b0, m_axis_cq_dwlen}; wire [31:0] m_axis_cq_hiaddr_mask = m_axis_cq_read_l ? 32'b0 : m_axis_cq_tdata_a[31:0]; assign m_axis_cq_tdata = (m_axis_cq_read_l | m_axis_cq_second) ? {m_axis_cq_hiaddr_mask, m_axis_cq_tdata_a1[31:0], m_axis_cq_header} : @@ -144,12 +142,12 @@ module m_axis_cq_adapt # ( assign m_axis_cq_tuser = { - 5'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - 5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F - m_axis_cq_tuser_barhit, - 1'b0, //rx_err_fwd -> no equivalent - m_axis_cq_ecrc //ECRC mapped to discontinue - }; + 5'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + 5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F + m_axis_cq_tuser_barhit, + 1'b0, //rx_err_fwd -> no equivalent + m_axis_cq_ecrc //ECRC mapped to discontinue + }; endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v b/litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v index df99038..f360de5 100644 --- a/litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v +++ b/litepcie/phy/xilinx_us/m_axis_cq_adapt_x8.v @@ -4,7 +4,7 @@ // SPDX-License-Identifier: BSD-2-Clause module m_axis_cq_adapt # ( - parameter DATA_WIDTH = 128, + parameter DATA_WIDTH = 256, parameter KEEP_WIDTH = DATA_WIDTH/8 )( @@ -60,7 +60,7 @@ module m_axis_cq_adapt # ( else if (m_axis_cq_tlast_lat && m_axis_cq_tready) m_axis_cq_tlast_lat <= 1'd0; else if (m_axis_cq_tvalid_a && m_axis_cq_tready_a && m_axis_cq_tlast_a) begin - if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'b1; //read + if (m_axis_cq_sop) m_axis_cq_tlast_lat <= 1'b1; else if (m_axis_cq_tlast_dly_en) m_axis_cq_tlast_lat <= 1'b1; end @@ -73,8 +73,8 @@ module m_axis_cq_adapt # ( ////keep address (low) or data (high), not header - reg [DATA_WIDTH-1:0] m_axis_cq_tdata_a1; - reg [DATA_WIDTH/8-1:0] m_axis_cq_tlast_be1; + reg [255:0] m_axis_cq_tdata_a1; + reg [31:0] m_axis_cq_tlast_be1; always @(posedge user_clk) if (m_axis_cq_tvalid_a && m_axis_cq_tready_a) begin @@ -85,15 +85,15 @@ module m_axis_cq_adapt # ( //data processing wire [63:0] m_axis_cq_tdata_hdr = m_axis_cq_tdata_a[127:64]; - assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; - wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; - wire m_axis_cq_ep = 1'b0; - wire m_axis_cq_td = 1'b0; - wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; + assign m_axis_cq_dwlen = m_axis_cq_tdata_hdr[9:0]; + wire [1:0] m_axis_cq_attr = m_axis_cq_tdata_hdr[61:60]; + wire m_axis_cq_ep = 1'b0; + wire m_axis_cq_td = 1'b0; + wire [2:0] m_axis_cq_tc = m_axis_cq_tdata_hdr[59:57]; wire [4:0] m_axis_cq_type; wire [2:0] m_axis_cq_fmt; - wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0]; - wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; + wire [7:0] m_axis_cq_be = m_axis_cq_tuser_a[7:0]; + wire [7:0] m_axis_cq_tag = m_axis_cq_tdata_hdr[39:32]; wire [15:0] m_axis_cq_requesterid = m_axis_cq_tdata_hdr[31:16]; assign {m_axis_cq_fmt, m_axis_cq_type} = m_axis_cq_tdata_hdr[14:11] == 4'b0000 ? 8'b000_00000 : //Mem read Request @@ -115,27 +115,25 @@ module m_axis_cq_adapt # ( reg [63:0] m_axis_cq_header; always @(posedge user_clk) if (m_axis_cq_tvalid_a && m_axis_cq_sop) - m_axis_cq_header = { - m_axis_cq_requesterid, - m_axis_cq_tag, - m_axis_cq_be, - m_axis_cq_fmt, m_axis_cq_type, - 1'b0, m_axis_cq_tc, 4'b0, - m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, - 2'b0, m_axis_cq_dwlen - }; + m_axis_cq_header = {m_axis_cq_requesterid, + m_axis_cq_tag, + m_axis_cq_be, + m_axis_cq_fmt, m_axis_cq_type, + 1'b0, m_axis_cq_tc, 4'b0, + m_axis_cq_td, m_axis_cq_ep, m_axis_cq_attr, + 2'b0, m_axis_cq_dwlen}; assign m_axis_cq_tdata = (m_axis_cq_rdwr_l | m_axis_cq_second) ? {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[255:128], m_axis_cq_tdata_a1[31:0], m_axis_cq_header} : {m_axis_cq_tdata_a[31:0], m_axis_cq_tdata_a1[255:32]}; assign m_axis_cq_tkeep = m_axis_cq_rdwr_l ? {4'b0, m_axis_cq_tlast_be1[31:16], 12'hFFF} : m_axis_cq_tlast_lat ? {4'b0, m_axis_cq_tlast_be1[31:4]} : 32'hFFFF_FFFF; assign m_axis_cq_tuser = { - 5'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - 5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F - m_axis_cq_tuser_barhit, - 1'b0, //rx_err_fwd -> no equivalent - m_axis_cq_tuser_a[41] //ECRC mapped to discontinue - }; + 5'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + 5'b0, //m_axis_cq_tuser_a[40],4'b0, //rx_is_sof only for 128-bit I/F + m_axis_cq_tuser_barhit, + 1'b0, //rx_err_fwd -> no equivalent + m_axis_cq_tuser_a[41] //ECRC mapped to discontinue + }; endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v b/litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v index f22a94c..fb857ef 100644 --- a/litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v +++ b/litepcie/phy/xilinx_us/m_axis_rc_adapt_x4.v @@ -47,20 +47,20 @@ module m_axis_rc_adapt # ( m_axis_rc_poisoning_l <= m_axis_rc_poisoning; end - wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; - wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; - wire m_axis_rc_ep = 1'b0; - wire m_axis_rc_td = 1'b0; - wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; + wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; + wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; + wire m_axis_rc_ep = 1'b0; + wire m_axis_rc_td = 1'b0; + wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; wire [4:0] m_axis_rc_type; wire [2:0] m_axis_rc_fmt; - wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; - wire m_axis_rc_bmc = 1'b0; - wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; + wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; + wire m_axis_rc_bmc = 1'b0; + wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; wire [15:0] m_axis_rc_completerid = m_axis_rc_tdata_a[87:72]; - wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; - wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; + wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; + wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; wire [15:0] m_axis_rc_requesterid = m_axis_rc_tdata_a[63:48]; assign {m_axis_rc_fmt, @@ -69,36 +69,31 @@ module m_axis_rc_adapt # ( ((m_axis_rc_bytecnt == 0) ? 8'b000_01010 : //Completion w/o data 8'b010_01010); //Completion w/ data - wire [63:0] m_axis_rc_header0 = { - m_axis_rc_completerid, - m_axis_rc_cmpstatus, - m_axis_rc_bmc, - m_axis_rc_bytecnt, - m_axis_rc_fmt[2:0], m_axis_rc_type, - 1'b0, m_axis_rc_tc, 4'b0, - m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, - 2'b0, m_axis_rc_dwlen - }; - wire [63:0] m_axis_rc_header1 = { - m_axis_rc_tdata_a[127:96], - m_axis_rc_requesterid, - m_axis_rc_tag, - 1'b0, m_axis_rc_lowaddr - }; - - assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; - assign m_axis_rc_tready_a = m_axis_rc_tready; - assign m_axis_rc_tlast = m_axis_rc_tlast_a; - assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; - assign m_axis_rc_tkeep = m_axis_rc_sop ? 16'hFFFF : m_axis_rc_tuser_a[15:0]; - assign m_axis_rc_tuser = { - 5'd0, //m_axis_rc_tlast_a, 4'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - m_axis_rc_sop, 4'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ?????? - 8'b0, //BAR hit no equivalent for RC - m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion - m_axis_rc_tuser_a[42] //ECRC mapped to discontinue - }; + wire [63:0] m_axis_rc_header0 = {m_axis_rc_completerid, + m_axis_rc_cmpstatus, + m_axis_rc_bmc, + m_axis_rc_bytecnt, + m_axis_rc_fmt[2:0], m_axis_rc_type, + 1'b0, m_axis_rc_tc, 4'b0, + m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, + 2'b0, m_axis_rc_dwlen}; + wire [63:0] m_axis_rc_header1 = {m_axis_rc_tdata_a[127:96], + m_axis_rc_requesterid, + m_axis_rc_tag, + 1'b0, m_axis_rc_lowaddr}; + assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; + assign m_axis_rc_tready_a = m_axis_rc_tready; + assign m_axis_rc_tlast = m_axis_rc_tlast_a; + assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; + assign m_axis_rc_tkeep = m_axis_rc_sop ? 16'hFFFF : m_axis_rc_tuser_a[15:0]; + assign m_axis_rc_tuser = { + 5'd0, //m_axis_rc_tlast_a, 4'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + m_axis_rc_sop, 4'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ????????????????????? + 8'b0, //BAR hit no equivalent for RC + m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion + m_axis_rc_tuser_a[42] //ECRC mapped to discontinue + }; endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v b/litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v index 0e5e04e..3811870 100644 --- a/litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v +++ b/litepcie/phy/xilinx_us/m_axis_rc_adapt_x8.v @@ -4,7 +4,7 @@ // SPDX-License-Identifier: BSD-2-Clause module m_axis_rc_adapt # ( - parameter DATA_WIDTH = 128, + parameter DATA_WIDTH = 256, parameter KEEP_WIDTH = DATA_WIDTH/8 )( @@ -47,20 +47,20 @@ module m_axis_rc_adapt # ( m_axis_rc_poisoning_l <= m_axis_rc_poisoning; end - wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; - wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; - wire m_axis_rc_ep = 1'b0; - wire m_axis_rc_td = 1'b0; - wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; + wire [9:0] m_axis_rc_dwlen = m_axis_rc_tdata_a[41:32]; + wire [1:0] m_axis_rc_attr = m_axis_rc_tdata_a[93:92]; + wire m_axis_rc_ep = 1'b0; + wire m_axis_rc_td = 1'b0; + wire [2:0] m_axis_rc_tc = m_axis_rc_tdata_a[91:89]; wire [4:0] m_axis_rc_type; wire [2:0] m_axis_rc_fmt; - wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; - wire m_axis_rc_bmc = 1'b0; - wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; + wire [11:0] m_axis_rc_bytecnt = m_axis_rc_tdata_a[27:16]; + wire m_axis_rc_bmc = 1'b0; + wire [2:0] m_axis_rc_cmpstatus = m_axis_rc_tdata_a[45:43]; wire [15:0] m_axis_rc_completerid = m_axis_rc_tdata_a[87:72]; - wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; - wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; + wire [6:0] m_axis_rc_lowaddr = m_axis_rc_tdata_a[6:0]; + wire [7:0] m_axis_rc_tag = m_axis_rc_tdata_a[71:64]; wire [15:0] m_axis_rc_requesterid = m_axis_rc_tdata_a[63:48]; assign {m_axis_rc_fmt, @@ -69,35 +69,32 @@ module m_axis_rc_adapt # ( ((m_axis_rc_bytecnt == 0) ? 8'b000_01010 : //Completion w/o data 8'b010_01010); //Completion w/ data - wire [63:0] m_axis_rc_header0 = { - m_axis_rc_completerid, - m_axis_rc_cmpstatus, - m_axis_rc_bmc, - m_axis_rc_bytecnt, - m_axis_rc_fmt[2:0], m_axis_rc_type, - 1'b0, m_axis_rc_tc, 4'b0, - m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, - 2'b0, m_axis_rc_dwlen - }; - wire [63:0] m_axis_rc_header1 = { - m_axis_rc_tdata_a[127:96], - m_axis_rc_requesterid, - m_axis_rc_tag, - 1'b0, m_axis_rc_lowaddr - }; + wire [63:0] m_axis_rc_header0 = {m_axis_rc_completerid, + m_axis_rc_cmpstatus, + m_axis_rc_bmc, + m_axis_rc_bytecnt, + m_axis_rc_fmt[2:0], m_axis_rc_type, + 1'b0, m_axis_rc_tc, 4'b0, + m_axis_rc_td, m_axis_rc_ep, m_axis_rc_attr, + 2'b0, m_axis_rc_dwlen}; + wire [63:0] m_axis_rc_header1 = {m_axis_rc_tdata_a[127:96], + m_axis_rc_requesterid, + m_axis_rc_tag, + 1'b0, m_axis_rc_lowaddr}; + + assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; + assign m_axis_rc_tready_a = m_axis_rc_tready; + assign m_axis_rc_tlast = m_axis_rc_tlast_a; + assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_tdata_a[255:128], m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; + assign m_axis_rc_tkeep = m_axis_rc_sop ? {m_axis_rc_tuser_a[31:12], 12'hFFF} : m_axis_rc_tuser_a[31:0]; + assign m_axis_rc_tuser = { + 5'b0, //rx_is_eof only for 128-bit I/F + 2'b0, //reserved + 5'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ????????????????????? + 8'b0, //BAR hit no equivalent for RC + m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion + m_axis_rc_tuser_a[42] //ECRC mapped to discontinue + }; - assign m_axis_rc_tvalid = m_axis_rc_tvalid_a; - assign m_axis_rc_tready_a = m_axis_rc_tready; - assign m_axis_rc_tlast = m_axis_rc_tlast_a; - assign m_axis_rc_tdata = m_axis_rc_sop ? {m_axis_rc_tdata_a[255:128], m_axis_rc_header1, m_axis_rc_header0} : m_axis_rc_tdata_a; - assign m_axis_rc_tkeep = m_axis_rc_sop ? {m_axis_rc_tuser_a[31:12], 12'hFFF} : m_axis_rc_tuser_a[31:0]; - assign m_axis_rc_tuser = { - 5'b0, //rx_is_eof only for 128-bit I/F - 2'b0, //reserved - 5'b0, //m_axis_rc_tuser_a[32],4'b0, //rx_is_sof, only for 128-bit I/F ????????????????????? - 8'b0, //BAR hit no equivalent for RC - m_axis_rc_sop ? m_axis_rc_poisoning : m_axis_rc_poisoning_l, //rx_err_fwd mapped to Poisoned completion - m_axis_rc_tuser_a[42] //ECRC mapped to discontinue - }; endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_us/pcie_us_support.v b/litepcie/phy/xilinx_us/pcie_us_support.v index 5bfe21b..e9b9072 100644 --- a/litepcie/phy/xilinx_us/pcie_us_support.v +++ b/litepcie/phy/xilinx_us/pcie_us_support.v @@ -314,6 +314,13 @@ module pcie_support # ( //----------------------------------------------------- RQ AXIS -------------------------------------------------// + wire s_axis_rq_tvalid_a; + wire s_axis_rq_tready_a; + wire [KEEP_WIDTH-1 :0] s_axis_rq_tkeep_a; + wire [C_DATA_WIDTH-1 :0] s_axis_rq_tdata_a; + wire [255 :0] s_axis_rq_tuser_a; + wire s_axis_rq_tlast_a; + s_axis_rq_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) @@ -342,7 +349,7 @@ module pcie_support # ( wire m_axis_rc_tready_a; wire [KEEP_WIDTH-1 :0] m_axis_rc_tkeep_a; wire [C_DATA_WIDTH-1 :0] m_axis_rc_tdata_a; - wire [74 :0] m_axis_rc_tuser_a; + wire [255 :0] m_axis_rc_tuser_a; wire m_axis_rc_tlast_a; m_axis_rc_adapt #( @@ -373,7 +380,7 @@ module pcie_support # ( wire m_axis_cq_tready_a; wire [KEEP_WIDTH-1 :0] m_axis_cq_tkeep_a; wire [C_DATA_WIDTH-1 :0] m_axis_cq_tdata_a; - wire [74 :0] m_axis_cq_tuser_a; + wire [255 :0] m_axis_cq_tuser_a; wire m_axis_cq_tlast_a; m_axis_cq_adapt #( @@ -390,16 +397,23 @@ module pcie_support # ( .m_axis_cq_tuser( m_axis_cq_tuser), .m_axis_cq_tvalid(m_axis_cq_tvalid), - .m_axis_cq_tdata_a( s_axis_cq_tdata_a), - .m_axis_cq_tkeep_a( s_axis_cq_tkeep_a), - .m_axis_cq_tlast_a( s_axis_cq_tlast_a), - .m_axis_cq_tready_a(s_axis_cq_tready_a), - .m_axis_cq_tuser_a( s_axis_cq_tuser_a), - .m_axis_cq_tvalid_a(s_axis_cq_tvalid_a) + .m_axis_cq_tdata_a( m_axis_cq_tdata_a), + .m_axis_cq_tkeep_a( m_axis_cq_tkeep_a), + .m_axis_cq_tlast_a( m_axis_cq_tlast_a), + .m_axis_cq_tready_a(m_axis_cq_tready_a), + .m_axis_cq_tuser_a( m_axis_cq_tuser_a), + .m_axis_cq_tvalid_a(m_axis_cq_tvalid_a) ); //----------------------------------------------------- CC AXIS --------------------------------------------------// + wire s_axis_cc_tvalid_a; + wire s_axis_cc_tready_a; + wire [KEEP_WIDTH-1 :0] s_axis_cc_tkeep_a; + wire [C_DATA_WIDTH-1 :0] s_axis_cc_tdata_a; + wire [255 :0] s_axis_cc_tuser_a; + wire s_axis_cc_tlast_a; + s_axis_cc_adapt #( .DATA_WIDTH(C_DATA_WIDTH), .KEEP_WIDTH(KEEP_WIDTH) @@ -436,7 +450,7 @@ module pcie_support # ( 3'd1 : cfg_interrupt_msi_int_enc <= 32'h0000_0002; 3'd2 : cfg_interrupt_msi_int_enc <= 32'h0000_0010; 3'd3 : cfg_interrupt_msi_int_enc <= 32'h0000_0100; - 3'd4: cfg_interrupt_msi_int_enc <= 32'h0001_0000; + 3'd4 : cfg_interrupt_msi_int_enc <= 32'h0001_0000; default: cfg_interrupt_msi_int_enc <= 32'h8000_0000; endcase diff --git a/litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v b/litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v index b04e728..c270cb3 100644 --- a/litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v +++ b/litepcie/phy/xilinx_us/s_axis_cc_adapt_x4.v @@ -11,36 +11,32 @@ module s_axis_cc_adapt # ( input user_clk, input user_reset, - output [DATA_WIDTH-1:0] s_axis_cc_tdata, - output [KEEP_WIDTH-1:0] s_axis_cc_tkeep, - output s_axis_cc_tlast, - input [3:0] s_axis_cc_tready, - output [3:0] s_axis_cc_tuser, - output s_axis_cc_tvalid, - - input [DATA_WIDTH-1:0] s_axis_cc_tdata_a, - input [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a, - input s_axis_cc_tlast_a, - output [3:0] s_axis_cc_tready_a, - input [3:0] s_axis_cc_tuser_a, - input s_axis_cc_tvalid_a + input [DATA_WIDTH-1:0] s_axis_cc_tdata, + input [KEEP_WIDTH-1:0] s_axis_cc_tkeep, + input s_axis_cc_tlast, + output s_axis_cc_tready, + input [3:0] s_axis_cc_tuser, + input s_axis_cc_tvalid, + + output [DATA_WIDTH-1:0] s_axis_cc_tdata_a, + output [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a, + output s_axis_cc_tlast_a, + input s_axis_cc_tready_a, + output [32:0] s_axis_cc_tuser_a, + output s_axis_cc_tvalid_a ); wire s_axis_cc_tready_ff, s_axis_cc_tvalid_ff, s_axis_cc_tlast_ff; - wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_or = { - |s_axis_cc_tkeep[15:12], - |s_axis_cc_tkeep[11:8], - |s_axis_cc_tkeep[7:4], - |s_axis_cc_tkeep[3:0] - }; + wire [3:0] s_axis_cc_tkeep_or = {|s_axis_cc_tkeep[15:12], |s_axis_cc_tkeep[11:8], + |s_axis_cc_tkeep[7:4], |s_axis_cc_tkeep[3:0]}; wire [3:0] s_axis_cc_tuser_ff; - wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_ff; - wire [DATA_WIDTH-1:0] s_axis_cc_tdata_ff; + wire [3:0] s_axis_cc_tkeep_ff; + wire [127:0] s_axis_cc_tdata_ff; - axis_iff #(.DAT_B(DATA_WIDTH+KEEP_WIDTH+4)) s_axis_cc_iff + axis_iff #(.DAT_B(128+4+4)) s_axis_cc_iff ( .clk (user_clk), .rst (user_reset), @@ -67,41 +63,36 @@ module s_axis_cc_adapt # ( else if (!s_axis_cc_cnt[1]) s_axis_cc_cnt <= s_axis_cc_cnt + 1; end - wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; + wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; wire s_axis_cc_tsecond = s_axis_cc_cnt == 1; - wire [3:0] s_axis_cc_tready_a; - - wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; - wire [1:0] s_axis_cc_at = 2'b0; //address translation - wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; + wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; + wire [1:0] s_axis_cc_at = 2'b0; //address translation + wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; wire s_axis_cc_lockedrdcmp = (s_axis_cc_tdata_ff[29:24] == 6'b0_01011); //Read-Locked Completion - wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; - wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; - wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; + wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; + wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; + wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; wire [15:0] s_axis_cc_requesterid = s_axis_cc_tdata_ff[95:80]; - wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; - wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; + wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; + wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; wire s_axis_cc_completerid_en = 1'b0; //must be 0 for End-point - wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; - wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; - wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop - - - wire [63:0] s_axis_cc_header0 = { - s_axis_cc_requesterid, - 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, - 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, - 6'b0, s_axis_cc_at, - 1'b0, s_axis_cc_lowaddr - }; - wire [63:0] s_axis_cc_header1 = { - s_axis_cc_tdata_ff[127:96], - s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, - s_axis_cc_completerid, - s_axis_cc_tag - }; + wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; + wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; + wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop + + + wire [63:0] s_axis_cc_header0 = {s_axis_cc_requesterid, + 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, + 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, + 6'b0, s_axis_cc_at, + 1'b0, s_axis_cc_lowaddr}; + wire [63:0] s_axis_cc_header1 = {s_axis_cc_tdata_ff[127:96], + s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, + s_axis_cc_completerid, + s_axis_cc_tag + }; reg [3:0] s_axis_cc_firstbe; reg [3:0] s_axis_cc_lastbe; @@ -115,11 +106,11 @@ module s_axis_cc_adapt # ( else if (s_axis_cc_tfirst) s_axis_cc_tvalid_ff_lat <= 1'd1; end - wire s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; - assign s_axis_cc_tready_ff = s_axis_cc_tready_a[0]; - wire [DATA_WIDTH-1:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; - wire s_axis_cc_tlast_a = s_axis_cc_tlast_ff; - wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; - wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} + assign s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; + assign s_axis_cc_tready_ff = s_axis_cc_tready_a; + assign s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; + assign s_axis_cc_tlast_a = s_axis_cc_tlast_ff; + assign s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; + assign s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v b/litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v index e401c10..a3f50cc 100644 --- a/litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v +++ b/litepcie/phy/xilinx_us/s_axis_cc_adapt_x8.v @@ -4,47 +4,41 @@ // SPDX-License-Identifier: BSD-2-Clause module s_axis_cc_adapt # ( - parameter DATA_WIDTH = 128, + parameter DATA_WIDTH = 256, parameter KEEP_WIDTH = DATA_WIDTH/8 )( input user_clk, input user_reset, - output [DATA_WIDTH-1:0] s_axis_cc_tdata, - output [KEEP_WIDTH-1:0] s_axis_cc_tkeep, - output s_axis_cc_tlast, - input [3:0] s_axis_cc_tready, - output [3:0] s_axis_cc_tuser, - output s_axis_cc_tvalid, - - input [DATA_WIDTH-1:0] s_axis_cc_tdata_a, - input [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a, - input s_axis_cc_tlast_a, - output [3:0] s_axis_cc_tready_a, - input [3:0] s_axis_cc_tuser_a, - input s_axis_cc_tvalid_a + input [DATA_WIDTH-1:0] s_axis_cc_tdata, + input [KEEP_WIDTH-1:0] s_axis_cc_tkeep, + input s_axis_cc_tlast, + output s_axis_cc_tready, + input [3:0] s_axis_cc_tuser, + input s_axis_cc_tvalid, + + output [DATA_WIDTH-1:0] s_axis_cc_tdata_a, + output [KEEP_WIDTH-1:0] s_axis_cc_tkeep_a, + output s_axis_cc_tlast_a, + input s_axis_cc_tready_a, + output [32:0] s_axis_cc_tuser_a, + output s_axis_cc_tvalid_a ); - wire s_axis_cc_tready_ff, - s_axis_cc_tvalid_ff, - s_axis_cc_tlast_ff; - wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_or = { - |s_axis_cc_tkeep[31:28], - |s_axis_cc_tkeep[27:24], - |s_axis_cc_tkeep[23:20], - |s_axis_cc_tkeep[19:16], - |s_axis_cc_tkeep[15:12], - |s_axis_cc_tkeep[11:8], - |s_axis_cc_tkeep[7:4], - |s_axis_cc_tkeep[3:0] - }; - - wire [3 :0] s_axis_cc_tuser_ff; - wire [KEEP_WIDTH-1:0] s_axis_cc_tkeep_ff; - wire [DATA_WIDTH-1:0] s_axis_cc_tdata_ff; - - axis_iff #(.DAT_B(DATA_WIDTH+KEEP_WIDTH+4)) s_axis_cc_iff + wire s_axis_cc_tready_ff, + s_axis_cc_tvalid_ff, + s_axis_cc_tlast_ff; + wire [7:0] s_axis_cc_tkeep_or = {|s_axis_cc_tkeep[31:28], |s_axis_cc_tkeep[27:24], + |s_axis_cc_tkeep[23:20], |s_axis_cc_tkeep[19:16], + |s_axis_cc_tkeep[15:12], |s_axis_cc_tkeep[11:8], + |s_axis_cc_tkeep[7:4], |s_axis_cc_tkeep[3:0]}; + + wire [3:0] s_axis_cc_tuser_ff; + wire [7:0] s_axis_cc_tkeep_ff; + wire [255:0] s_axis_cc_tdata_ff; + + axis_iff #(.DAT_B(256+8+4)) s_axis_cc_iff ( .clk (user_clk), .rst (user_reset), @@ -71,48 +65,43 @@ module s_axis_cc_adapt # ( else if (!s_axis_cc_cnt[1]) s_axis_cc_cnt <= s_axis_cc_cnt + 1; end - wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; + wire s_axis_cc_tfirst = s_axis_cc_cnt == 0; wire s_axis_cc_tsecond = s_axis_cc_cnt == 1; - wire [3:0] s_axis_cc_tready_a; - - wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; - wire [1:0] s_axis_cc_at = 2'b0; //address translation - wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; + wire [6:0] s_axis_cc_lowaddr = s_axis_cc_tdata_ff[70:64]; + wire [1:0] s_axis_cc_at = 2'b0; //address translation + wire [12:0] s_axis_cc_bytecnt = {1'b0, s_axis_cc_tdata_ff[43:32]}; wire s_axis_cc_lockedrdcmp = (s_axis_cc_tdata_ff[29:24] == 6'b0_01011); //Read-Locked Completion - wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; - wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; - wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; + wire [9:0] s_axis_cc_dwordcnt = s_axis_cc_tdata_ff[9:0]; + wire [2:0] s_axis_cc_cmpstatus = s_axis_cc_tdata_ff[47:45]; + wire s_axis_cc_poison = s_axis_cc_tdata_ff[14]; wire [15:0] s_axis_cc_requesterid = s_axis_cc_tdata_ff[95:80]; - wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; - wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; + wire [7:0] s_axis_cc_tag = s_axis_cc_tdata_ff[79:72]; + wire [15:0] s_axis_cc_completerid = s_axis_cc_tdata_ff[63:48]; wire s_axis_cc_completerid_en = 1'b0; //must be 0 for End-point - wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; - wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; - wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop - - - wire [63:0] s_axis_cc_header0 = { - s_axis_cc_requesterid, - 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, - 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, - 6'b0, s_axis_cc_at, - 1'b0, s_axis_cc_lowaddr - }; - wire [63:0] s_axis_cc_header1 = { - s_axis_cc_tdata_ff[127:96], - s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, - s_axis_cc_completerid, - s_axis_cc_tag - }; - - wire s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; - - assign s_axis_cc_tready_ff = s_axis_cc_tready_a[0]; - wire [DATA_WIDTH-1:0] s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_tdata_ff[255:128], s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; - wire s_axis_cc_tlast_a = s_axis_cc_tlast_ff; - wire [KEEP_WIDTH:0] s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; - wire [32:0] s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} + wire [2:0] s_axis_cc_tc = s_axis_cc_tdata_ff[22:20]; + wire [2:0] s_axis_cc_attr = {1'b0, s_axis_cc_tdata_ff[13:12]}; + wire s_axis_cc_td = s_axis_cc_tdata_ff[15] | s_axis_cc_tuser_ff[0]; //ECRC @sop + + + wire [63:0] s_axis_cc_header0 = {s_axis_cc_requesterid, + 2'b0, s_axis_cc_poison, s_axis_cc_cmpstatus, s_axis_cc_dwordcnt, + 2'b0, s_axis_cc_lockedrdcmp, s_axis_cc_bytecnt, + 6'b0, s_axis_cc_at, + 1'b0, s_axis_cc_lowaddr}; + wire [63:0] s_axis_cc_header1 = {s_axis_cc_tdata_ff[127:96], + s_axis_cc_td, s_axis_cc_attr, s_axis_cc_tc, s_axis_cc_completerid_en, + s_axis_cc_completerid, + s_axis_cc_tag + }; + + assign s_axis_cc_tvalid_a = s_axis_cc_tvalid_ff; + + assign s_axis_cc_tready_ff = s_axis_cc_tready_a; + assign s_axis_cc_tdata_a = s_axis_cc_tfirst ? {s_axis_cc_tdata_ff[255:128], s_axis_cc_header1, s_axis_cc_header0} : s_axis_cc_tdata_ff; + assign s_axis_cc_tlast_a = s_axis_cc_tlast_ff; + assign s_axis_cc_tkeep_a = s_axis_cc_tkeep_ff; + assign s_axis_cc_tuser_a = {32'b0, s_axis_cc_tuser_ff[3]}; //{parity, discontinue} endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v index d204a91..3a69917 100644 --- a/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v +++ b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x4.v @@ -11,36 +11,31 @@ module s_axis_rq_adapt # ( input user_clk, input user_reset, - output [DATA_WIDTH-1:0] s_axis_rq_tdata, - output [KEEP_WIDTH-1:0] s_axis_rq_tkeep, - output s_axis_rq_tlast, - input [3:0] s_axis_rq_tready, - output [3:0] s_axis_rq_tuser, - output s_axis_rq_tvalid, - - input [DATA_WIDTH-1:0] s_axis_rq_tdata_a, - input [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a, - input s_axis_rq_tlast_a, - output [3:0] s_axis_rq_tready_a, - input [3:0] s_axis_rq_tuser_a, - input s_axis_rq_tvalid_a + input [DATA_WIDTH-1:0] s_axis_rq_tdata, + input [KEEP_WIDTH-1:0] s_axis_rq_tkeep, + input s_axis_rq_tlast, + output s_axis_rq_tready, + input [3:0] s_axis_rq_tuser, + input s_axis_rq_tvalid, + + output [DATA_WIDTH-1:0] s_axis_rq_tdata_a, + output [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a, + output s_axis_rq_tlast_a, + input s_axis_rq_tready_a, + output [59:0] s_axis_rq_tuser_a, + output s_axis_rq_tvalid_a ); wire s_axis_rq_tready_ff, s_axis_rq_tvalid_ff, s_axis_rq_tlast_ff; - wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_or = { - |s_axis_rq_tkeep[15:12], - |s_axis_rq_tkeep[11:8], - |s_axis_rq_tkeep[7:4], - |s_axis_rq_tkeep[3:0] - }; + wire [3:0] s_axis_rq_tkeep_or = {|s_axis_rq_tkeep[15:12], |s_axis_rq_tkeep[11:8], |s_axis_rq_tkeep[7:4], |s_axis_rq_tkeep[3:0]}; - wire [3:0] s_axis_rq_tuser_ff; - wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_ff; - wire [DATA_WIDTH-1:0] s_axis_rq_tdata_ff; + wire [3:0] s_axis_rq_tuser_ff; + wire [3:0] s_axis_rq_tkeep_ff; + wire [127:0] s_axis_rq_tdata_ff; - axis_iff #(.DAT_B(DATA_WIDTH+KEEP_WIDTH+4)) s_axis_rq_iff + axis_iff #(.DAT_B(128+4+4)) s_axis_rq_iff ( .clk (user_clk), .rst (user_reset), @@ -61,58 +56,83 @@ module s_axis_rq_adapt # ( reg [1:0] s_axis_rq_cnt; //0-2 always @(posedge user_clk) - if (user_reset) s_axis_rq_cnt <= 2'd0; + if (user_reset) + s_axis_rq_cnt <= 2'd0; else if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) begin - if (s_axis_rq_tlast_ff) s_axis_rq_cnt <= 2'd0; - else if (!s_axis_rq_cnt[1]) s_axis_rq_cnt <= s_axis_rq_cnt + 1; + if (s_axis_rq_tlast_ff) + s_axis_rq_cnt <= 2'd0; + else if (!s_axis_rq_cnt[1]) + s_axis_rq_cnt <= s_axis_rq_cnt + 1; end - wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); - wire s_axis_rq_tsecond = s_axis_rq_cnt == 1; + wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); + wire s_axis_rq_tsecond = s_axis_rq_cnt == 1; - //processing for tlast: generate new last in case write & last num of dword = 5 + i*4 - wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request - wire s_axis_rq_write = !s_axis_rq_read; - reg s_axis_rq_tlast_dly_en; - reg s_axis_rq_tlast_lat; - wire [3:0] s_axis_rq_tready_a; + // processing for tlast: generate new last in case write & last num of dword = 5, 9, 13, ... + wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request + wire s_axis_rq_write = !s_axis_rq_read; + reg s_axis_rq_tlast_dly_en; + reg s_axis_rq_tlast_lat; always @(posedge user_clk) - if (user_reset) s_axis_rq_tlast_dly_en <= 1'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_tready_ff && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[1:0] == 2'd1); + if (user_reset) + s_axis_rq_tlast_dly_en <= 1'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_tready_ff && s_axis_rq_write) + s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[1:0] == 2'd1); always @(posedge user_clk) - if (user_reset) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; + if (user_reset) + s_axis_rq_tlast_lat <= 1'd0; + else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) + s_axis_rq_tlast_lat <= 1'd0; else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) begin - if (s_axis_rq_tfirst) s_axis_rq_tlast_lat <= s_axis_rq_write ? 1'b1 : 1'b0; //write 1-dword - else s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; + if (s_axis_rq_tfirst) + s_axis_rq_tlast_lat <= s_axis_rq_write ? 1'b1 : 1'b0; //write 1-dword + else + s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; end - wire s_axis_rq_tlast_a = s_axis_rq_tfirst ? s_axis_rq_read : - s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; - - //Generae ready for TLP - assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); - wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; - - wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; - wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request - {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000001 ? 4'b0111 : //Mem Read request-locked - {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0100000 ? 4'b0001 : //Mem write request - s_axis_rq_tdata_ff[31:24] == 8'b00000010 ? 4'b0010 : //I/O Read request - s_axis_rq_tdata_ff[31:24] == 8'b01000010 ? 4'b0011 : //I/O Write request - s_axis_rq_tdata_ff[31:24] == 8'b00000100 ? 4'b1000 : //Cfg Read Type 0 - s_axis_rq_tdata_ff[31:24] == 8'b01000100 ? 4'b1010 : //Cfg Write Type 0 - s_axis_rq_tdata_ff[31:24] == 8'b00000101 ? 4'b1001 : //Cfg Read Type 1 - s_axis_rq_tdata_ff[31:24] == 8'b01000101 ? 4'b1011 : //Cfg Write Type 1 - 4'b1111; + assign s_axis_rq_tlast_a = s_axis_rq_tfirst ? s_axis_rq_read : + s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; + + // Generate ready for TLP + assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); + + // Latch valid because it is uncontigous when coming from TLP request + reg s_axis_rq_tvalid_lat; + always @(posedge user_clk) + if (user_reset) + s_axis_rq_tvalid_lat <= 1'b0; + else if (s_axis_rq_tvalid_lat && s_axis_rq_tready_a[0]) + begin + if (s_axis_rq_tlast_dly_en) + s_axis_rq_tvalid_lat <= !s_axis_rq_tlast_lat; + else + s_axis_rq_tvalid_lat <= !(s_axis_rq_tlast_ff && s_axis_rq_tvalid_ff); + end + else if (s_axis_rq_tvalid_ff & s_axis_rq_tfirst & s_axis_rq_write) + s_axis_rq_tvalid_lat <= 1'b1; //latche input valid (required by PCIe IP) + + assign s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; + + wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; + wire [3:0] s_axis_rq_reqtype = + {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request + {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000001 ? 4'b0111 : //Mem Read request-locked + {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0100000 ? 4'b0001 : //Mem write request + s_axis_rq_tdata_ff[31:24] == 8'b00000010 ? 4'b0010 : //I/O Read request + s_axis_rq_tdata_ff[31:24] == 8'b01000010 ? 4'b0011 : //I/O Write request + s_axis_rq_tdata_ff[31:24] == 8'b00000100 ? 4'b1000 : //Cfg Read Type 0 + s_axis_rq_tdata_ff[31:24] == 8'b01000100 ? 4'b1010 : //Cfg Write Type 0 + s_axis_rq_tdata_ff[31:24] == 8'b00000101 ? 4'b1001 : //Cfg Read Type 1 + s_axis_rq_tdata_ff[31:24] == 8'b01000101 ? 4'b1011 : //Cfg Write Type 1 + 4'b1111; wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; - wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID - wire s_axis_rq_requester_en = 1'b0; //Must be 0 for Endpoint + wire [15:0] s_axis_rq_completerid = 16'b0; // Applicable only to Configuration requests and messages routed by ID. + wire s_axis_rq_requester_en = 1'b0; // Must be 0 for Endpoint. wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest @@ -138,7 +158,7 @@ module s_axis_rq_adapt # ( if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst) begin s_axis_rq_firstbe_l <= s_axis_rq_firstbe; - s_axis_rq_lastbe_l <= s_axis_rq_lastbe; + s_axis_rq_lastbe_l <= s_axis_rq_lastbe; end end @@ -147,10 +167,11 @@ module s_axis_rq_adapt # ( if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[127:96]; - wire [DATA_WIDTH-1:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : {s_axis_rq_tdata_ff[95:0], s_axis_rq_tdata_l[31:0]}; - wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 4'b0001 : 4'b1111; //{s_axis_rq_tkeep_ff[2:0], 1'b1}; - wire [59:0] s_axis_rq_tuser_a; - assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; - assign s_axis_rq_tuser_a[7:0] = s_axis_rq_tfirst ? {s_axis_rq_lastbe, s_axis_rq_firstbe} : {s_axis_rq_lastbe_l, s_axis_rq_firstbe_l}; + assign s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : {s_axis_rq_tdata_ff[95:0], s_axis_rq_tdata_l[31:0]}; + assign s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 4'b0001 : 4'b1111; + assign s_axis_rq_tuser_a; + assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; + assign s_axis_rq_tuser_a[7:0] = s_axis_rq_tfirst ? {s_axis_rq_lastbe, s_axis_rq_firstbe} : {s_axis_rq_lastbe_l, s_axis_rq_firstbe_l}; + endmodule \ No newline at end of file diff --git a/litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v index 900f23e..a21bda1 100644 --- a/litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v +++ b/litepcie/phy/xilinx_us/s_axis_rq_adapt_x8.v @@ -4,47 +4,39 @@ // SPDX-License-Identifier: BSD-2-Clause module s_axis_rq_adapt # ( - parameter DATA_WIDTH = 128, + parameter DATA_WIDTH = 256, parameter KEEP_WIDTH = DATA_WIDTH/8 )( input user_clk, input user_reset, - output [DATA_WIDTH-1:0] s_axis_rq_tdata, - output [KEEP_WIDTH-1:0] s_axis_rq_tkeep, - output s_axis_rq_tlast, - input [3:0] s_axis_rq_tready, - output [3:0] s_axis_rq_tuser, - output s_axis_rq_tvalid, - - input [DATA_WIDTH-1:0] s_axis_rq_tdata_a, - input [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a, - input s_axis_rq_tlast_a, - output [3:0] s_axis_rq_tready_a, - input [3:0] s_axis_rq_tuser_a, - input s_axis_rq_tvalid_a + input [DATA_WIDTH-1:0] s_axis_rq_tdata, + input [KEEP_WIDTH-1:0] s_axis_rq_tkeep, + input s_axis_rq_tlast, + output s_axis_rq_tready, + input [3:0] s_axis_rq_tuser, + input s_axis_rq_tvalid, + + output [DATA_WIDTH-1:0] s_axis_rq_tdata_a, + output [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a, + output s_axis_rq_tlast_a, + input s_axis_rq_tready_a, + output [59:0] s_axis_rq_tuser_a, + output s_axis_rq_tvalid_a ); - wire s_axis_rq_tready_ff, + wire s_axis_rq_tready_ff, s_axis_rq_tvalid_ff, s_axis_rq_tlast_ff; - wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_or = { - s_axis_rq_tkeep[28], - s_axis_rq_tkeep[24], - s_axis_rq_tkeep[20], - s_axis_rq_tkeep[16], - s_axis_rq_tkeep[12], - s_axis_rq_tkeep[8], - s_axis_rq_tkeep[4], - s_axis_rq_tkeep[0] - }; - - wire [3:0] s_axis_rq_tuser_ff; - wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_ff; - wire [DATA_WIDTH-1:0] s_axis_rq_tdata_ff; - - axis_iff #(.DAT_B(DATA_WIDTH+KEEP_WIDTH+4)) s_axis_rq_iff + wire [7:0] s_axis_rq_tkeep_or = {s_axis_rq_tkeep[28], s_axis_rq_tkeep[24], s_axis_rq_tkeep[20], s_axis_rq_tkeep[16], + s_axis_rq_tkeep[12], s_axis_rq_tkeep[8], s_axis_rq_tkeep[4], s_axis_rq_tkeep[0]}; + + wire [3:0] s_axis_rq_tuser_ff; + wire [7:0] s_axis_rq_tkeep_ff; + wire [255:0] s_axis_rq_tdata_ff; + + axis_iff #(.DAT_B(256+8+4)) s_axis_rq_iff ( .clk (user_clk), .rst (user_reset), @@ -72,34 +64,33 @@ module s_axis_rq_adapt # ( else if (!s_axis_rq_cnt[1]) s_axis_rq_cnt <= s_axis_rq_cnt + 1; end - wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); + wire s_axis_rq_tfirst = (s_axis_rq_cnt == 0) && (!s_axis_rq_tlast_lat); wire s_axis_rq_tsecond = s_axis_rq_cnt == 1; //processing for tlast: generate new last in case write & last num of dword = 5 + i*8 - wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request + wire s_axis_rq_read = (s_axis_rq_tdata_ff[31:30] == 2'b0); //Read request wire s_axis_rq_write = !s_axis_rq_read; reg s_axis_rq_tlast_dly_en; reg s_axis_rq_tlast_lat; - wire [3:0] s_axis_rq_tready_a; always @(posedge user_clk) if (user_reset) s_axis_rq_tlast_dly_en <= 1'd0; else if (s_axis_rq_tvalid_ff && s_axis_rq_tfirst && s_axis_rq_write) s_axis_rq_tlast_dly_en <= (s_axis_rq_tdata_ff[2:0] == 3'b101); always @(posedge user_clk) if (user_reset) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a[0]) s_axis_rq_tlast_lat <= 1'd0; - else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a[0]) + else if (s_axis_rq_tlast_lat && s_axis_rq_tready_a) s_axis_rq_tlast_lat <= 1'd0; + else if (s_axis_rq_tvalid_ff && s_axis_rq_tlast_ff && s_axis_rq_tready_a) begin if (s_axis_rq_tfirst) s_axis_rq_tlast_lat <= s_axis_rq_write ? (s_axis_rq_dwlen == 11'd5) : 1'b0; //write 5 dwords else s_axis_rq_tlast_lat <= s_axis_rq_tlast_dly_en; end - wire s_axis_rq_tlast_a = s_axis_rq_tfirst ? (s_axis_rq_read | (s_axis_rq_dwlen < 11'd5)) : - s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; + assign s_axis_rq_tlast_a = s_axis_rq_tfirst ? (s_axis_rq_read | (s_axis_rq_dwlen < 11'd5)) : + s_axis_rq_tlast_dly_en ? s_axis_rq_tlast_lat : s_axis_rq_tlast_ff; - //Generae ready for TLP - assign s_axis_rq_tready_ff = s_axis_rq_tready_a[0] && (!s_axis_rq_tlast_lat); - wire s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; + //Generate ready for TLP + assign s_axis_rq_tready_ff = s_axis_rq_tready_a && (!s_axis_rq_tlast_lat); + assign s_axis_rq_tvalid_a = s_axis_rq_tvalid_ff | s_axis_rq_tlast_lat; wire [10:0] s_axis_rq_dwlen = {1'b0, s_axis_rq_tdata_ff[9:0]}; wire [3:0] s_axis_rq_reqtype = {s_axis_rq_tdata_ff[31:30], s_axis_rq_tdata_ff[28:24]} == 7'b0000000 ? 4'b0000 : //Mem read Request @@ -112,30 +103,28 @@ module s_axis_rq_adapt # ( s_axis_rq_tdata_ff[31:24] == 8'b00000101 ? 4'b1001 : //Cfg Read Type 1 s_axis_rq_tdata_ff[31:24] == 8'b01000101 ? 4'b1011 : //Cfg Write Type 1 4'b1111; - wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request - wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; - wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; - wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID + wire s_axis_rq_poisoning = s_axis_rq_tdata_ff[14] | s_axis_rq_tuser_ff[1]; //EP must be 0 for request + wire [15:0] s_axis_rq_requesterid = s_axis_rq_tdata_ff[63:48]; + wire [7:0] s_axis_rq_tag = s_axis_rq_tdata_ff[47:40]; + wire [15:0] s_axis_rq_completerid = 16'b0; //applicable only to Configuration requests and messages routed by ID wire s_axis_rq_requester_en = 1'b0; //Must be 0 for Endpoint - wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; - wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; - wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest - - wire [63:0] s_axis_rq_tdata_header = { - s_axis_rq_ecrc, - s_axis_rq_attr, - s_axis_rq_tc, - s_axis_rq_requester_en, - s_axis_rq_completerid, - s_axis_rq_tag, - s_axis_rq_requesterid, - s_axis_rq_poisoning, s_axis_rq_reqtype, s_axis_rq_dwlen - }; - - wire [3:0] s_axis_rq_firstbe = s_axis_rq_tdata_ff[35:32]; - wire [3:0] s_axis_rq_lastbe = s_axis_rq_tdata_ff[39:36]; - reg [3:0] s_axis_rq_firstbe_l; - reg [3:0] s_axis_rq_lastbe_l; + wire [2:0] s_axis_rq_tc = s_axis_rq_tdata_ff[22:20]; + wire [2:0] s_axis_rq_attr = {1'b0, s_axis_rq_tdata_ff[13:12]}; + wire s_axis_rq_ecrc = s_axis_rq_tdata_ff[15] | s_axis_rq_tuser_ff[0]; //TLP Digest + + wire [63:0] s_axis_rq_tdata_header = {s_axis_rq_ecrc, + s_axis_rq_attr, + s_axis_rq_tc, + s_axis_rq_requester_en, + s_axis_rq_completerid, + s_axis_rq_tag, + s_axis_rq_requesterid, + s_axis_rq_poisoning, s_axis_rq_reqtype, s_axis_rq_dwlen}; + + wire [3:0] s_axis_rq_firstbe = s_axis_rq_tdata_ff[35:32]; + wire [3:0] s_axis_rq_lastbe = s_axis_rq_tdata_ff[39:36]; + reg [3:0] s_axis_rq_firstbe_l; + reg [3:0] s_axis_rq_lastbe_l; always @(posedge user_clk) begin @@ -151,11 +140,10 @@ module s_axis_rq_adapt # ( if (s_axis_rq_tvalid_ff && s_axis_rq_tready_ff) s_axis_rq_tdata_l <= s_axis_rq_tdata_ff[255:224]; - wire [DATA_WIDTH-1:0] s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_ff[223:96], s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : - {s_axis_rq_tdata_ff[223:0], s_axis_rq_tdata_l[31:0]}; - wire [KEEP_WIDTH-1:0] s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 8'h1 : {s_axis_rq_tkeep_ff[6:0], 1'b1}; - wire [59:0] s_axis_rq_tuser_a; - assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; - assign s_axis_rq_tuser_a[7:0] = {s_axis_rq_lastbe, s_axis_rq_firstbe}; + assign s_axis_rq_tdata_a = s_axis_rq_tfirst ? {s_axis_rq_tdata_ff[223:96], s_axis_rq_tdata_header, 32'b0, s_axis_rq_tdata_ff[95:64]} : + {s_axis_rq_tdata_ff[223:0], s_axis_rq_tdata_l[31:0]}; + assign s_axis_rq_tkeep_a = s_axis_rq_tlast_lat ? 8'h1 : {s_axis_rq_tkeep_ff[6:0], 1'b1}; + assign s_axis_rq_tuser_a[59:8] = {32'b0, 4'b0, 1'b0, 8'b0, 2'b0, 1'b0, s_axis_rq_tuser_ff[3], 3'b0}; + assign s_axis_rq_tuser_a[7:0] = {s_axis_rq_lastbe, s_axis_rq_firstbe}; endmodule \ No newline at end of file