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FinalProject.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2021 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
# Date created = 22:59:12 April 24, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# FinalProject_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C7G
set_global_assignment -name TOP_LEVEL_ENTITY FinalProject
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:59:12 APRIL 24, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name VHDL_FILE Experiment05PartA.vhd
set_global_assignment -name VHDL_FILE HEXtoBCD.vhd
set_global_assignment -name VHDL_FILE BCDto7Seg.vhd
set_global_assignment -name VHDL_FILE FinalProject.vhd
set_global_assignment -name VHDL_FILE Timer90.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_AA8 -to Sa
set_location_assignment PIN_AA2 -to Sd
set_location_assignment PIN_Y4 -to Se
set_location_assignment PIN_Y3 -to Sf
set_location_assignment PIN_P11 -to clk
set_location_assignment PIN_C10 -to Reset
set_location_assignment PIN_B17 -to O1[6]
set_location_assignment PIN_A18 -to O1[5]
set_location_assignment PIN_A17 -to O1[4]
set_location_assignment PIN_B16 -to O1[3]
set_location_assignment PIN_E18 -to O1[2]
set_location_assignment PIN_D18 -to O1[1]
set_location_assignment PIN_C18 -to O1[0]
set_location_assignment PIN_C17 -to O0[6]
set_location_assignment PIN_D17 -to O0[5]
set_location_assignment PIN_E16 -to O0[4]
set_location_assignment PIN_C16 -to O0[3]
set_location_assignment PIN_C15 -to O0[2]
set_location_assignment PIN_E15 -to O0[1]
set_location_assignment PIN_C14 -to O0[0]
set_location_assignment PIN_AB3 -to Dg
set_location_assignment PIN_AA5 -to Cg
set_location_assignment PIN_AA7 -to Cr
set_location_assignment PIN_AA6 -to Cy
set_location_assignment PIN_W5 -to Ar
set_location_assignment PIN_AA14 -to Ay
set_location_assignment PIN_W12 -to Ag
set_location_assignment PIN_W9 -to Br
set_location_assignment PIN_W13 -to By
set_location_assignment PIN_AB13 -to Bg
set_location_assignment PIN_V10 -to Er
set_location_assignment PIN_V9 -to Ey
set_location_assignment PIN_V8 -to Eg
set_location_assignment PIN_Y7 -to Fr
set_location_assignment PIN_Y8 -to Fy
set_location_assignment PIN_AA10 -to Fg
set_location_assignment PIN_C11 -to En
set_global_assignment -name VHDL_FILE FiniteStateMachine.vhd
set_global_assignment -name VHDL_FILE Counter60.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top