From a848e3a603c7d44ac692c707f7bf472441d8aee6 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Wed, 9 Aug 2023 18:41:29 +0300 Subject: [PATCH 1/2] Add cocotb flow to caravel_user_project_analog and port the mprj_por test to cocotb --- verilog/dv/cocotb/.gitignore | 4 ++ verilog/dv/cocotb/README.md | 43 +++++++++++++++++ verilog/dv/cocotb/cocotb_tests.py | 3 ++ verilog/dv/cocotb/design_info.yaml | 9 ++++ verilog/dv/cocotb/hello_world/hello_world.c | 4 ++ verilog/dv/cocotb/hello_world/hello_world.py | 9 ++++ .../dv/cocotb/hello_world/hello_world.yaml | 11 +++++ .../hello_world_uart/hello_world_uart.c | 13 ++++++ .../hello_world_uart/hello_world_uart.py | 21 +++++++++ .../hello_world_uart/hello_world_uart.yaml | 7 +++ verilog/dv/cocotb/mprj_por/mprj_por.c | 46 +++++++++++++++++++ verilog/dv/cocotb/mprj_por/mprj_por.py | 41 +++++++++++++++++ .../includes.gl+sdf.caravel_user_project | 18 ++++++++ .../includes/includes.gl.caravel_user_project | 18 ++++++++ .../includes.rtl.caravel_user_project | 22 +++++++++ verilog/rtl/user_analog_proj_example.v | 3 +- 16 files changed, 271 insertions(+), 1 deletion(-) create mode 100644 verilog/dv/cocotb/.gitignore create mode 100644 verilog/dv/cocotb/README.md create mode 100644 verilog/dv/cocotb/cocotb_tests.py create mode 100644 verilog/dv/cocotb/design_info.yaml create mode 100644 verilog/dv/cocotb/hello_world/hello_world.c create mode 100644 verilog/dv/cocotb/hello_world/hello_world.py create mode 100644 verilog/dv/cocotb/hello_world/hello_world.yaml create mode 100644 verilog/dv/cocotb/hello_world_uart/hello_world_uart.c create mode 100644 verilog/dv/cocotb/hello_world_uart/hello_world_uart.py create mode 100644 verilog/dv/cocotb/hello_world_uart/hello_world_uart.yaml create mode 100644 verilog/dv/cocotb/mprj_por/mprj_por.c create mode 100644 verilog/dv/cocotb/mprj_por/mprj_por.py create mode 100644 verilog/includes/includes.gl+sdf.caravel_user_project create mode 100644 verilog/includes/includes.gl.caravel_user_project create mode 100644 verilog/includes/includes.rtl.caravel_user_project diff --git a/verilog/dv/cocotb/.gitignore b/verilog/dv/cocotb/.gitignore new file mode 100644 index 00000000..fe104e16 --- /dev/null +++ b/verilog/dv/cocotb/.gitignore @@ -0,0 +1,4 @@ +sim/ +*.log +*.vcd +*.pyc \ No newline at end of file diff --git a/verilog/dv/cocotb/README.md b/verilog/dv/cocotb/README.md new file mode 100644 index 00000000..340e85d5 --- /dev/null +++ b/verilog/dv/cocotb/README.md @@ -0,0 +1,43 @@ +Overview +======== +This directory contain tests to verify the example user project 16 bit counter and 2 other simple tests as examples. + +directory hierarchy +===================== + +# counter_tests + +contain tests for 16 bit counter for more info refer to [counter_tests](counter_tests/README.md) + + # hello_world + + Example test with empty firmware that only power and reset caravel the print "Hello World" + + # hello_world_uart + + Example test That uses the firmware to send "Hello World" using UART TX + +# cocotb_tests.py + +Module that should import all the tests used to be seen for cocotb as a test + + +Run tests +=========== +# run hello_world_uart + ```bash + caravel_cocotb -t hello_world_uart -tag hello_world + ``` +# run all counter testlist + ```bash + caravel_cocotb -tl counter_tests/counter_tests.yaml -tag counter_tests + ``` +# run from different directory + ```bash + caravel_cocotb -t hello_world_uart -tag hello_world -design_info + ``` +# run with changing the results directory + ```bash + caravel_cocotb -t hello_world_uart -tag hello_world -sim + ``` + diff --git a/verilog/dv/cocotb/cocotb_tests.py b/verilog/dv/cocotb/cocotb_tests.py new file mode 100644 index 00000000..173de550 --- /dev/null +++ b/verilog/dv/cocotb/cocotb_tests.py @@ -0,0 +1,3 @@ +from hello_world.hello_world import hello_world +from hello_world_uart.hello_world_uart import hello_world_uart +from mprj_por.mprj_por import mprj_por \ No newline at end of file diff --git a/verilog/dv/cocotb/design_info.yaml b/verilog/dv/cocotb/design_info.yaml new file mode 100644 index 00000000..143e24b9 --- /dev/null +++ b/verilog/dv/cocotb/design_info.yaml @@ -0,0 +1,9 @@ +CARAVEL_ROOT: /caravel +MCW_ROOT: /litex +PDK: sky130A +PDK_ROOT: /pdk +USER_PROJECT_ROOT: /caravel_user_project_analog/ +caravan: true +clk: 25 +emailto: +- null diff --git a/verilog/dv/cocotb/hello_world/hello_world.c b/verilog/dv/cocotb/hello_world/hello_world.c new file mode 100644 index 00000000..c6526b82 --- /dev/null +++ b/verilog/dv/cocotb/hello_world/hello_world.c @@ -0,0 +1,4 @@ +#include +void main(){ + return; +} \ No newline at end of file diff --git a/verilog/dv/cocotb/hello_world/hello_world.py b/verilog/dv/cocotb/hello_world/hello_world.py new file mode 100644 index 00000000..3618d49c --- /dev/null +++ b/verilog/dv/cocotb/hello_world/hello_world.py @@ -0,0 +1,9 @@ +from caravel_cocotb.caravel_interfaces import test_configure +from caravel_cocotb.caravel_interfaces import report_test +import cocotb + +@cocotb.test() +@report_test +async def hello_world(dut): + caravelEnv = await test_configure(dut,timeout_cycles=9373) + cocotb.log.info("Hello World") \ No newline at end of file diff --git a/verilog/dv/cocotb/hello_world/hello_world.yaml b/verilog/dv/cocotb/hello_world/hello_world.yaml new file mode 100644 index 00000000..bd6165dc --- /dev/null +++ b/verilog/dv/cocotb/hello_world/hello_world.yaml @@ -0,0 +1,11 @@ +--- +# Yalm file contain general design information that would mostly need to be updated in the first run only +# example +## tests: [debug,clock_redirect] +## sim: [RTL,RTL] +Tests: + - {name: hello_world, sim: RTL} + + + + diff --git a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.c b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.c new file mode 100644 index 00000000..098a6d7d --- /dev/null +++ b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.c @@ -0,0 +1,13 @@ +#include + +void main(){ + ManagmentGpio_write(0); + ManagmentGpio_outputEnable(); + GPIOs_configure(6,GPIO_MODE_MGMT_STD_OUTPUT); + GPIOs_loadConfigs(); + UART_enableTX(1); + ManagmentGpio_write(1); // configuration finished + + print("Hello World\n"); + return; +} \ No newline at end of file diff --git a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.py b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.py new file mode 100644 index 00000000..66ab6d88 --- /dev/null +++ b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.py @@ -0,0 +1,21 @@ +from caravel_cocotb.caravel_interfaces import test_configure +from caravel_cocotb.caravel_interfaces import report_test +import cocotb +from caravel_cocotb.caravel_interfaces import UART + +@cocotb.test() +@report_test +async def hello_world_uart(dut): + caravelEnv = await test_configure(dut,timeout_cycles=3346140) + + cocotb.log.info(f"[TEST] Start uart test") + expected_msg = "Hello World" + uart = UART(caravelEnv) + # wait for start of sending + await caravelEnv.wait_mgmt_gpio(1) + # read the msg sent + msg = await uart.get_line() + if msg in expected_msg : + cocotb.log.info (f"[TEST] Pass recieve the full expected msg '{msg}'") + else: + cocotb.log.error (f"[TEST] recieved wrong msg from uart msg recieved:'{msg}' expected '{expected_msg}'") \ No newline at end of file diff --git a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.yaml b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.yaml new file mode 100644 index 00000000..37d5fd1c --- /dev/null +++ b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.yaml @@ -0,0 +1,7 @@ +--- +# Yalm file contain general design information that would mostly need to be updated in the first run only + +Tests: + - {name: hello_world_uart, sim: RTL} + + diff --git a/verilog/dv/cocotb/mprj_por/mprj_por.c b/verilog/dv/cocotb/mprj_por/mprj_por.c new file mode 100644 index 00000000..0613c1ce --- /dev/null +++ b/verilog/dv/cocotb/mprj_por/mprj_por.c @@ -0,0 +1,46 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +// -------------------------------------------------------- + +void main() +{ + ManagmentGpio_write(0); + ManagmentGpio_outputEnable(); + GPIOs_writeLow(0x00000000); + GPIOs_writeHigh(0x00000000); + + // Configure mprj_io 10 and 25 as analog (digital in/out = off) + // Configure mprj_io 11, 12, 26, and 27 as digital output + // mprj_io 14 to 24 are analog pads and cannot be configured + GPIOs_configure(27, GPIO_MODE_USER_STD_OUTPUT); + GPIOs_configure(26, GPIO_MODE_USER_STD_OUTPUT); + GPIOs_configure(25, GPIO_MODE_USER_STD_ANALOG); + + GPIOs_configure(12, GPIO_MODE_USER_STD_OUTPUT); + GPIOs_configure(11, GPIO_MODE_USER_STD_OUTPUT); + GPIOs_configure(10, GPIO_MODE_USER_STD_ANALOG); + + GPIOs_loadConfigs(); + ManagmentGpio_write(1); // finish configuration + + /* Block until end of test */ + while (1); +} + diff --git a/verilog/dv/cocotb/mprj_por/mprj_por.py b/verilog/dv/cocotb/mprj_por/mprj_por.py new file mode 100644 index 00000000..7f2a9107 --- /dev/null +++ b/verilog/dv/cocotb/mprj_por/mprj_por.py @@ -0,0 +1,41 @@ +from caravel_cocotb.caravel_interfaces import test_configure +from caravel_cocotb.caravel_interfaces import report_test +import cocotb +from cocotb.triggers import ClockCycles + + +@cocotb.test() +@report_test +async def mprj_por(dut): + caravelEnv = await test_configure(dut,timeout_cycles=3346140) + # Power supply for POR + caravelEnv.drive_gpio_in(18, 0) + await caravelEnv.reset() + await cocotb.start(power_por(caravelEnv)) + await wait_status(caravelEnv, "01") + check_bits = caravelEnv.monitor_discontinuous_gpios([27, 26, 12, 11]) + if check_bits != "1001": + cocotb.log.error(f"[TEST] POR test failed expected 1001 got {check_bits}") + else: + cocotb.log.info(f"[TEST] phase 1 passed seen 1001 at gpios 27 26 12 11") + await wait_status(caravelEnv, "11") + check_bits = caravelEnv.monitor_discontinuous_gpios([27, 26, 12, 11]) + if check_bits != "0101": + cocotb.log.error(f"[TEST] POR test failed expected 0101 got {check_bits}") + else: + cocotb.log.info(f"[TEST] phase 2 passed seen 0101 at gpios 27 26 12 11") + + +async def wait_status(caravelEnv, val_to_wait): + while True: + if caravelEnv.monitor_discontinuous_gpios([25, 10]) == val_to_wait: + break + await ClockCycles(caravelEnv.clk, 1) + await ClockCycles(caravelEnv.clk, 3) + + + +async def power_por(caravelEnv): + await caravelEnv.wait_mgmt_gpio(1) # wait configuration finished + await ClockCycles(caravelEnv.clk, 10) + caravelEnv.drive_gpio_in(18, 1) diff --git a/verilog/includes/includes.gl+sdf.caravel_user_project b/verilog/includes/includes.gl+sdf.caravel_user_project new file mode 100644 index 00000000..44fa5425 --- /dev/null +++ b/verilog/includes/includes.gl+sdf.caravel_user_project @@ -0,0 +1,18 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +// Caravel user project includes +$USER_PROJECT_VERILOG/gl/user_project_wrapper.v +$USER_PROJECT_VERILOG/gl/user_proj_example.v diff --git a/verilog/includes/includes.gl.caravel_user_project b/verilog/includes/includes.gl.caravel_user_project new file mode 100644 index 00000000..b62af99f --- /dev/null +++ b/verilog/includes/includes.gl.caravel_user_project @@ -0,0 +1,18 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +# Caravel user project includes +-v $(USER_PROJECT_VERILOG)/gl/user_project_wrapper.v +-v $(USER_PROJECT_VERILOG)/gl/user_proj_example.v diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project new file mode 100644 index 00000000..ea9391b4 --- /dev/null +++ b/verilog/includes/includes.rtl.caravel_user_project @@ -0,0 +1,22 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + +# Caravel user project includes +-v $(USER_PROJECT_VERILOG)/rtl/example_por.v +-v $(USER_PROJECT_VERILOG)/rtl/user_analog_proj_example.v +-v $(USER_PROJECT_VERILOG)/rtl/user_analog_project_wrapper.v +-v $(USER_PROJECT_VERILOG)/rtl/user_defines.v + + \ No newline at end of file diff --git a/verilog/rtl/user_analog_proj_example.v b/verilog/rtl/user_analog_proj_example.v index 94412daf..92a27d1a 100644 --- a/verilog/rtl/user_analog_proj_example.v +++ b/verilog/rtl/user_analog_proj_example.v @@ -15,8 +15,9 @@ `default_nettype none +`ifndef COCOTB_SIM `include "example_por.v" - +`endif /* * I/O mapping for analog * From f81d9f7d219fd0b89a5b438e9fed73ac6aaa1080 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Thu, 10 Aug 2023 13:15:36 +0300 Subject: [PATCH 2/2] Update how to run cocotb tests documention and add SPDX-FileCopyrightText to cocotb files --- verilog/dv/cocotb/README.md | 22 ++++++++++++------- verilog/dv/cocotb/cocotb_tests.py | 17 ++++++++++++++ verilog/dv/cocotb/design_info.yaml | 16 ++++++++++++++ verilog/dv/cocotb/hello_world/hello_world.c | 18 +++++++++++++++ verilog/dv/cocotb/hello_world/hello_world.py | 17 ++++++++++++++ .../dv/cocotb/hello_world/hello_world.yaml | 19 +++++++++++++++- .../hello_world_uart/hello_world_uart.c | 17 ++++++++++++++ .../hello_world_uart/hello_world_uart.py | 17 ++++++++++++++ .../hello_world_uart/hello_world_uart.yaml | 19 +++++++++++++++- verilog/dv/cocotb/mprj_por/mprj_por.c | 2 +- verilog/dv/cocotb/mprj_por/mprj_por.py | 15 +++++++++++++ verilog/dv/mprj_por/Makefile | 5 +++-- 12 files changed, 171 insertions(+), 13 deletions(-) diff --git a/verilog/dv/cocotb/README.md b/verilog/dv/cocotb/README.md index 340e85d5..53f1f85c 100644 --- a/verilog/dv/cocotb/README.md +++ b/verilog/dv/cocotb/README.md @@ -2,12 +2,18 @@ Overview ======== This directory contain tests to verify the example user project 16 bit counter and 2 other simple tests as examples. +Prerequisites +============== + +- ```bash pip install caravel-cocotb``` +- update design_info.yaml + directory hierarchy ===================== -# counter_tests - -contain tests for 16 bit counter for more info refer to [counter_tests](counter_tests/README.md) +# mprj_por + +Example test for the PoR user project example # hello_world @@ -24,14 +30,15 @@ Module that should import all the tests used to be seen for cocotb as a test Run tests =========== -# run hello_world_uart +# run mprj_por ```bash - caravel_cocotb -t hello_world_uart -tag hello_world + caravel_cocotb -t mprj_por -tag mprj_por_run ``` -# run all counter testlist +# run hello_world_uart ```bash - caravel_cocotb -tl counter_tests/counter_tests.yaml -tag counter_tests + caravel_cocotb -t hello_world_uart -tag hello_world ``` + # run from different directory ```bash caravel_cocotb -t hello_world_uart -tag hello_world -design_info @@ -40,4 +47,3 @@ Run tests ```bash caravel_cocotb -t hello_world_uart -tag hello_world -sim ``` - diff --git a/verilog/dv/cocotb/cocotb_tests.py b/verilog/dv/cocotb/cocotb_tests.py index 173de550..d324c61b 100644 --- a/verilog/dv/cocotb/cocotb_tests.py +++ b/verilog/dv/cocotb/cocotb_tests.py @@ -1,3 +1,20 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# SPDX-License-Identifier: Apache-2.0 + + from hello_world.hello_world import hello_world from hello_world_uart.hello_world_uart import hello_world_uart from mprj_por.mprj_por import mprj_por \ No newline at end of file diff --git a/verilog/dv/cocotb/design_info.yaml b/verilog/dv/cocotb/design_info.yaml index 143e24b9..eb8e2f3b 100644 --- a/verilog/dv/cocotb/design_info.yaml +++ b/verilog/dv/cocotb/design_info.yaml @@ -1,3 +1,19 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + + CARAVEL_ROOT: /caravel MCW_ROOT: /litex PDK: sky130A diff --git a/verilog/dv/cocotb/hello_world/hello_world.c b/verilog/dv/cocotb/hello_world/hello_world.c index c6526b82..e3a70642 100644 --- a/verilog/dv/cocotb/hello_world/hello_world.c +++ b/verilog/dv/cocotb/hello_world/hello_world.c @@ -1,3 +1,21 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation + +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 + +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// SPDX-License-Identifier: Apache-2.0 + + + #include void main(){ return; diff --git a/verilog/dv/cocotb/hello_world/hello_world.py b/verilog/dv/cocotb/hello_world/hello_world.py index 3618d49c..e9ef82f7 100644 --- a/verilog/dv/cocotb/hello_world/hello_world.py +++ b/verilog/dv/cocotb/hello_world/hello_world.py @@ -1,3 +1,20 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# SPDX-License-Identifier: Apache-2.0 + + from caravel_cocotb.caravel_interfaces import test_configure from caravel_cocotb.caravel_interfaces import report_test import cocotb diff --git a/verilog/dv/cocotb/hello_world/hello_world.yaml b/verilog/dv/cocotb/hello_world/hello_world.yaml index bd6165dc..f2ae160e 100644 --- a/verilog/dv/cocotb/hello_world/hello_world.yaml +++ b/verilog/dv/cocotb/hello_world/hello_world.yaml @@ -1,4 +1,21 @@ ---- +# SPDX-FileCopyrightText: 2020 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# SPDX-License-Identifier: Apache-2.0 + + + # Yalm file contain general design information that would mostly need to be updated in the first run only # example ## tests: [debug,clock_redirect] diff --git a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.c b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.c index 098a6d7d..811700b2 100644 --- a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.c +++ b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.c @@ -1,3 +1,20 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation + +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 + +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// SPDX-License-Identifier: Apache-2.0 + + #include void main(){ diff --git a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.py b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.py index 66ab6d88..edf85e8d 100644 --- a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.py +++ b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.py @@ -1,3 +1,20 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# SPDX-License-Identifier: Apache-2.0 + + from caravel_cocotb.caravel_interfaces import test_configure from caravel_cocotb.caravel_interfaces import report_test import cocotb diff --git a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.yaml b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.yaml index 37d5fd1c..4e785ebd 100644 --- a/verilog/dv/cocotb/hello_world_uart/hello_world_uart.yaml +++ b/verilog/dv/cocotb/hello_world_uart/hello_world_uart.yaml @@ -1,4 +1,21 @@ ---- +# SPDX-FileCopyrightText: 2020 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# SPDX-License-Identifier: Apache-2.0 + + + # Yalm file contain general design information that would mostly need to be updated in the first run only Tests: diff --git a/verilog/dv/cocotb/mprj_por/mprj_por.c b/verilog/dv/cocotb/mprj_por/mprj_por.c index 0613c1ce..0671df9f 100644 --- a/verilog/dv/cocotb/mprj_por/mprj_por.c +++ b/verilog/dv/cocotb/mprj_por/mprj_por.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020 Efabless Corporation + * SPDX-FileCopyrightText: 2023 Efabless Corporation * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/verilog/dv/cocotb/mprj_por/mprj_por.py b/verilog/dv/cocotb/mprj_por/mprj_por.py index 7f2a9107..27ee6d98 100644 --- a/verilog/dv/cocotb/mprj_por/mprj_por.py +++ b/verilog/dv/cocotb/mprj_por/mprj_por.py @@ -1,3 +1,18 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation + +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at + +# http://www.apache.org/licenses/LICENSE-2.0 + +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# SPDX-License-Identifier: Apache-2.0 + from caravel_cocotb.caravel_interfaces import test_configure from caravel_cocotb.caravel_interfaces import report_test import cocotb diff --git a/verilog/dv/mprj_por/Makefile b/verilog/dv/mprj_por/Makefile index 6d8e9c44..12547acc 100644 --- a/verilog/dv/mprj_por/Makefile +++ b/verilog/dv/mprj_por/Makefile @@ -19,6 +19,7 @@ PDK_PATH = $(PDK_ROOT)/$(PDK) ## Caravel Pointers CARAVEL_ROOT ?= ../../../caravel +MCW_ROOT ?= ../../../caravel_mgmt_soc_litex CARAVEL_PATH ?= $(CARAVEL_ROOT) CARAVEL_FIRMWARE_PATH = $(CARAVEL_PATH)/verilog/dv/caravel CARAVEL_VERILOG_PATH = $(CARAVEL_PATH)/verilog @@ -31,7 +32,7 @@ UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl UPRJ_BEHAVIOURAL_MODELS = ../ ## RISCV GCC -GCC_PATH?=/ef/apps/bin +GCC_PATH?=/opt/riscv/bin GCC_PREFIX?=riscv32-unknown-elf ## Simulation mode: RTL/GL @@ -50,7 +51,7 @@ hex: ${PATTERN:=.hex} ifeq ($(SIM),RTL) iverilog $(SIM_DEFINES) -I $(PDK_PATH) \ -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \ - -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \ + -I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) -I $(MCW_ROOT)/verilog/rtl \ $< -o $@ else iverilog $(SIM_DEFINES) -DGL -I $(PDK_PATH) \