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Commit 9b8472e

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add watchdog support
1 parent 8f0add9 commit 9b8472e

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+14
-3
lines changed

1 file changed

+14
-3
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board/pedal/main.c

+14-3
Original file line numberDiff line numberDiff line change
@@ -117,10 +117,11 @@ uint32_t timeout = 0;
117117
uint32_t current_index = 0;
118118

119119
#define STATE_GOOD 0
120-
#define STATE_FAULT_CHECKSUM 1
120+
#define STATE_FAULT_BAD_CHECKSUM 1
121121
#define STATE_FAULT_SEND 2
122122
#define STATE_FAULT_SCE 3
123-
uint8_t state = STATE_NONE;
123+
#define STATE_FAULT_STARTUP 4
124+
uint8_t state = STATE_FAULT_STARTUP;
124125

125126
void CAN1_RX0_IRQHandler() {
126127
while (CAN->RF0R & CAN_RF0R_FMP0) {
@@ -157,7 +158,7 @@ void CAN1_RX0_IRQHandler() {
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current_index = index;
158159
} else {
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// wrong checksum = fault
160-
state = STATE_FAULT_CHECKSUM;
161+
state = STATE_FAULT_BAD_CHECKSUM;
161162
}
162163
}
163164
// next
@@ -234,6 +235,9 @@ void pedal() {
234235
dac_set(0, pdl0);
235236
dac_set(1, pdl1);
236237
}
238+
239+
// feed the watchdog
240+
IWDG->KR = 0xAAAA;
237241
}
238242

239243
int main() {
@@ -267,6 +271,13 @@ int main() {
267271

268272
NVIC_EnableIRQ(TIM3_IRQn);
269273

274+
// setup watchdog
275+
IWDG->KR = 0x5555;
276+
IWDG->PR = 0; // divider /4
277+
// 0 = 0.125 ms, let's have a 50ms watchdog
278+
IWDG->RLR = 400 - 1;
279+
IWDG->KR = 0xCCCC;
280+
270281
puts("**** INTERRUPTS ON ****\n");
271282
__enable_irq();
272283

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