]9;8;"USERNAME"\@]9;8;"COMPUTERNAME"\ D:\Sergey\git\runtime\artifacts\tests\coreclr\windows.x64.Checked\JIT\Regression\JitBlue\Runtime_53189\Runtime_53189 $ ]9;12\set complus_JitEnregStructLocals=1b ]9;8;"USERNAME"\@]9;8;"COMPUTERNAME"\ D:\Sergey\git\runtime\artifacts\tests\coreclr\windows.x64.Checked\JIT\Regression\JitBlue\Runtime_53189\Runtime_53189 $ ]9;12\call Runtime_53189.cmd BEGIN EXECUTION "D:\Sergey\git\runtime\artifacts\tests\coreclr\windows.x64.Checked\Tests\Core_Root\corerun.exe" Runtime_53189.dll Compiling 0 System.Runtime.CompilerServices.CastHelpers::StelemRef, IL size = 86, hash=0x1b5e9e9c FullOpts Compiling 1 System.Runtime.CompilerServices.CastHelpers::LdelemaRef, IL size = 42, hash=0xd1234a96 FullOpts Compiling 2 System.AppContext::Setup, IL size = 86, hash=0xfd42e87f FullOpts Compiling 3 System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]::.ctor, IL size = 102, hash=0x08da6f5d FullOpts Compiling 4 System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]::Initialize, IL size = 56, hash=0xa68b9105 FullOpts Compiling 5 System.Collections.HashHelpers::GetPrime, IL size = 83, hash=0x5705a8d6 FullOpts Compiling 6 System.Collections.HashHelpers::.cctor, IL size = 24, hash=0xbccaa83e Tier-0 switched MinOpts Compiling 7 System.Collections.Generic.NonRandomizedStringEqualityComparer::GetStringComparer, IL size = 39, hash=0x0bbf74b8 FullOpts Compiling 8 System.Collections.Generic.NonRandomizedStringEqualityComparer::.cctor, IL size = 46, hash=0x89975f68 Tier-0 switched MinOpts Compiling 9 System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon]::get_Default, IL size = 6, hash=0x98394f86 FullOpts Compiling 10 System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon]::.cctor, IL size = 26, hash=0x8d4cfe41 Tier-0 switched MinOpts Compiling 11 System.Collections.Generic.ComparerHelpers::CreateDefaultEqualityComparer, IL size = 229, hash=0x6fa03044 FullOpts Compiling 12 System.Runtime.CompilerServices.CastHelpers::ChkCastClass, IL size = 22, hash=0x1e1a1b83 FullOpts Compiling 13 System.Runtime.CompilerServices.CastHelpers::ChkCastClassSpecial, IL size = 100, hash=0xac179d82 FullOpts Compiling 14 OrdinalComparer::.ctor, IL size = 8, hash=0xbc058f25 FullOpts Compiling 15 System.StringComparer::get_Ordinal, IL size = 6, hash=0xf311999e FullOpts Compiling 16 System.OrdinalCaseSensitiveComparer::.cctor, IL size = 11, hash=0x02f5faec Tier-0 switched MinOpts Compiling 17 System.OrdinalCaseSensitiveComparer::.ctor, IL size = 8, hash=0xad2a2b73 FullOpts Compiling 18 System.StringComparer::get_OrdinalIgnoreCase, IL size = 6, hash=0x466d39b2 FullOpts Compiling 19 System.OrdinalIgnoreCaseComparer::.cctor, IL size = 11, hash=0x61ecf558 Tier-0 switched MinOpts Compiling 20 System.OrdinalIgnoreCaseComparer::.ctor, IL size = 8, hash=0xae111bc7 FullOpts Compiling 21 OrdinalIgnoreCaseComparer::.ctor, IL size = 8, hash=0x92c0ba49 FullOpts Compiling 22 System.Runtime.CompilerServices.CastHelpers::ChkCastAny, IL size = 47, hash=0xff4e6e3b FullOpts Compiling 23 System.String::Ctor, IL size = 57, hash=0x3b3dacf8 FullOpts Compiling 24 System.SpanHelpers::IndexOf, IL size = 912, hash=0x576e6ccc FullOpts Compiling 25 System.Buffer::Memmove, IL size = 609, hash=0x8415318b FullOpts Compiling 26 System.Buffer::_Memmove, IL size = 25, hash=0x55b3bfb4 FullOpts ****** START compiling System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this (MethodHash=0b956994) Generating code for Windows x64 OPTIONS: compCodeOpt = BLENDED_CODE OPTIONS: compDbgCode = false OPTIONS: compDbgInfo = true OPTIONS: compDbgEnC = false OPTIONS: compProcedureSplitting = false OPTIONS: compProcedureSplittingEH = false OPTIONS: No PGO data IL to import: IL_0000 03 ldarg.1 IL_0001 8c 18 00 00 1b box 0x1B000018 IL_0006 2d 06 brtrue.s 6 (IL_000e) IL_0008 1a ldc.i4.4 IL_0009 28 3f 19 00 06 call 0x600193F IL_000e 02 ldarg.0 IL_000f 7b 21 0c 00 0a ldfld 0xA000C21 IL_0014 2d 08 brtrue.s 8 (IL_001e) IL_0016 02 ldarg.0 IL_0017 16 ldc.i4.0 IL_0018 28 ff 0b 00 0a call 0xA000BFF IL_001d 26 pop IL_001e 02 ldarg.0 IL_001f 7b 21 0c 00 0a ldfld 0xA000C21 IL_0024 14 ldnull IL_0025 fe 03 cgt.un IL_0027 28 f9 5c 00 06 call 0x6005CF9 IL_002c 02 ldarg.0 IL_002d 7b 06 0c 00 0a ldfld 0xA000C06 IL_0032 0a stloc.0 IL_0033 06 ldloc.0 IL_0034 14 ldnull IL_0035 fe 03 cgt.un IL_0037 72 09 48 03 70 ldstr 0x70034809 IL_003c 28 fa 5c 00 06 call 0x6005CFA IL_0041 02 ldarg.0 IL_0042 7b 00 0c 00 0a ldfld 0xA000C00 IL_0047 0b stloc.1 IL_0048 07 ldloc.1 IL_0049 2c 09 brfalse.s 9 (IL_0054) IL_004b 07 ldloc.1 IL_004c 03 ldarg.1 IL_004d 6f 29 0c 00 0a callvirt 0xA000C29 IL_0052 2b 0d br.s 13 (IL_0061) IL_0054 0f 01 ldarga.s 0x1 IL_0056 fe 16 18 00 00 1b constrained. 0x1B000018 IL_005c 6f e4 04 00 06 callvirt 0x60004E4 IL_0061 0c stloc.2 IL_0062 16 ldc.i4.0 IL_0063 0d stloc.3 IL_0064 02 ldarg.0 IL_0065 08 ldloc.2 IL_0066 28 27 0c 00 0a call 0xA000C27 IL_006b 13 04 stloc.s 0x4 IL_006d 11 04 ldloc.s 0x4 IL_006f 4a ldind.i4 IL_0070 17 ldc.i4.1 IL_0071 59 sub IL_0072 13 05 stloc.s 0x5 IL_0074 07 ldloc.1 IL_0075 3a fd 00 00 00 brtrue 253 (IL_0177) IL_007a d0 18 00 00 1b ldtoken 0x1B000018 IL_007f 28 d6 07 00 06 call 0x60007D6 IL_0084 28 1f 08 00 06 call 0x600081F IL_0089 2c 74 brfalse.s 116 (IL_00ff) IL_008b 11 05 ldloc.s 0x5 IL_008d 06 ldloc.0 IL_008e 8e ldlen IL_008f 69 conv.i4 IL_0090 41 4f 01 00 00 bge.un 335 (IL_01e4) IL_0095 06 ldloc.0 IL_0096 11 05 ldloc.s 0x5 IL_0098 8f 29 04 00 1b ldelema 0x1B000429 IL_009d 7b 28 0c 00 0a ldfld 0xA000C28 IL_00a2 08 ldloc.2 IL_00a3 33 3a bne.un.s 58 (IL_00df) IL_00a5 28 8d 04 00 0a call 0xA00048D IL_00aa 06 ldloc.0 IL_00ab 11 05 ldloc.s 0x5 IL_00ad 8f 29 04 00 1b ldelema 0x1B000429 IL_00b2 7b 0a 0c 00 0a ldfld 0xA000C0A IL_00b7 03 ldarg.1 IL_00b8 6f 8e 04 00 0a callvirt 0xA00048E IL_00bd 2c 20 brfalse.s 32 (IL_00df) IL_00bf 05 ldarg.3 IL_00c0 17 ldc.i4.1 IL_00c1 33 10 bne.un.s 16 (IL_00d3) IL_00c3 06 ldloc.0 IL_00c4 11 05 ldloc.s 0x5 IL_00c6 8f 29 04 00 1b ldelema 0x1B000429 IL_00cb 04 ldarg.2 IL_00cc 7d 0b 0c 00 0a stfld 0xA000C0B IL_00d1 17 ldc.i4.1 IL_00d2 2a ret IL_00d3 05 ldarg.3 IL_00d4 18 ldc.i4.2 IL_00d5 33 06 bne.un.s 6 (IL_00dd) IL_00d7 03 ldarg.1 IL_00d8 28 85 05 00 2b call 0x2B000585 IL_00dd 16 ldc.i4.0 IL_00de 2a ret IL_00df 06 ldloc.0 IL_00e0 11 05 ldloc.s 0x5 IL_00e2 8f 29 04 00 1b ldelema 0x1B000429 IL_00e7 7b 09 0c 00 0a ldfld 0xA000C09 IL_00ec 13 05 stloc.s 0x5 IL_00ee 09 ldloc.3 IL_00ef 17 ldc.i4.1 IL_00f0 58 add IL_00f1 0d stloc.3 IL_00f2 09 ldloc.3 IL_00f3 06 ldloc.0 IL_00f4 8e ldlen IL_00f5 69 conv.i4 IL_00f6 36 93 ble.un.s -109 (IL_008b) IL_00f8 28 5c 19 00 06 call 0x600195C IL_00fd 2b 8c br.s -116 (IL_008b) IL_00ff 28 8d 04 00 0a call 0xA00048D IL_0104 13 08 stloc.s 0x8 IL_0106 11 05 ldloc.s 0x5 IL_0108 06 ldloc.0 IL_0109 8e ldlen IL_010a 69 conv.i4 IL_010b 41 d4 00 00 00 bge.un 212 (IL_01e4) IL_0110 06 ldloc.0 IL_0111 11 05 ldloc.s 0x5 IL_0113 8f 29 04 00 1b ldelema 0x1B000429 IL_0118 7b 28 0c 00 0a ldfld 0xA000C28 IL_011d 08 ldloc.2 IL_011e 33 37 bne.un.s 55 (IL_0157) IL_0120 11 08 ldloc.s 0x8 IL_0122 06 ldloc.0 IL_0123 11 05 ldloc.s 0x5 IL_0125 8f 29 04 00 1b ldelema 0x1B000429 IL_012a 7b 0a 0c 00 0a ldfld 0xA000C0A IL_012f 03 ldarg.1 IL_0130 6f 8e 04 00 0a callvirt 0xA00048E IL_0135 2c 20 brfalse.s 32 (IL_0157) IL_0137 05 ldarg.3 IL_0138 17 ldc.i4.1 IL_0139 33 10 bne.un.s 16 (IL_014b) IL_013b 06 ldloc.0 IL_013c 11 05 ldloc.s 0x5 IL_013e 8f 29 04 00 1b ldelema 0x1B000429 IL_0143 04 ldarg.2 IL_0144 7d 0b 0c 00 0a stfld 0xA000C0B IL_0149 17 ldc.i4.1 IL_014a 2a ret IL_014b 05 ldarg.3 IL_014c 18 ldc.i4.2 IL_014d 33 06 bne.un.s 6 (IL_0155) IL_014f 03 ldarg.1 IL_0150 28 85 05 00 2b call 0x2B000585 IL_0155 16 ldc.i4.0 IL_0156 2a ret IL_0157 06 ldloc.0 IL_0158 11 05 ldloc.s 0x5 IL_015a 8f 29 04 00 1b ldelema 0x1B000429 IL_015f 7b 09 0c 00 0a ldfld 0xA000C09 IL_0164 13 05 stloc.s 0x5 IL_0166 09 ldloc.3 IL_0167 17 ldc.i4.1 IL_0168 58 add IL_0169 0d stloc.3 IL_016a 09 ldloc.3 IL_016b 06 ldloc.0 IL_016c 8e ldlen IL_016d 69 conv.i4 IL_016e 36 96 ble.un.s -106 (IL_0106) IL_0170 28 5c 19 00 06 call 0x600195C IL_0175 2b 8f br.s -113 (IL_0106) IL_0177 11 05 ldloc.s 0x5 IL_0179 06 ldloc.0 IL_017a 8e ldlen IL_017b 69 conv.i4 IL_017c 34 66 bge.un.s 102 (IL_01e4) IL_017e 06 ldloc.0 IL_017f 11 05 ldloc.s 0x5 IL_0181 8f 29 04 00 1b ldelema 0x1B000429 IL_0186 7b 28 0c 00 0a ldfld 0xA000C28 IL_018b 08 ldloc.2 IL_018c 33 36 bne.un.s 54 (IL_01c4) IL_018e 07 ldloc.1 IL_018f 06 ldloc.0 IL_0190 11 05 ldloc.s 0x5 IL_0192 8f 29 04 00 1b ldelema 0x1B000429 IL_0197 7b 0a 0c 00 0a ldfld 0xA000C0A IL_019c 03 ldarg.1 IL_019d 6f 2a 0c 00 0a callvirt 0xA000C2A IL_01a2 2c 20 brfalse.s 32 (IL_01c4) IL_01a4 05 ldarg.3 IL_01a5 17 ldc.i4.1 IL_01a6 33 10 bne.un.s 16 (IL_01b8) IL_01a8 06 ldloc.0 IL_01a9 11 05 ldloc.s 0x5 IL_01ab 8f 29 04 00 1b ldelema 0x1B000429 IL_01b0 04 ldarg.2 IL_01b1 7d 0b 0c 00 0a stfld 0xA000C0B IL_01b6 17 ldc.i4.1 IL_01b7 2a ret IL_01b8 05 ldarg.3 IL_01b9 18 ldc.i4.2 IL_01ba 33 06 bne.un.s 6 (IL_01c2) IL_01bc 03 ldarg.1 IL_01bd 28 85 05 00 2b call 0x2B000585 IL_01c2 16 ldc.i4.0 IL_01c3 2a ret IL_01c4 06 ldloc.0 IL_01c5 11 05 ldloc.s 0x5 IL_01c7 8f 29 04 00 1b ldelema 0x1B000429 IL_01cc 7b 09 0c 00 0a ldfld 0xA000C09 IL_01d1 13 05 stloc.s 0x5 IL_01d3 09 ldloc.3 IL_01d4 17 ldc.i4.1 IL_01d5 58 add IL_01d6 0d stloc.3 IL_01d7 09 ldloc.3 IL_01d8 06 ldloc.0 IL_01d9 8e ldlen IL_01da 69 conv.i4 IL_01db 36 9a ble.un.s -102 (IL_0177) IL_01dd 28 5c 19 00 06 call 0x600195C IL_01e2 2b 93 br.s -109 (IL_0177) IL_01e4 02 ldarg.0 IL_01e5 7b 10 0c 00 0a ldfld 0xA000C10 IL_01ea 16 ldc.i4.0 IL_01eb 31 56 ble.s 86 (IL_0243) IL_01ed 02 ldarg.0 IL_01ee 7b 22 0c 00 0a ldfld 0xA000C22 IL_01f3 13 06 stloc.s 0x6 IL_01f5 1f fd ldc.i4.s 0xFFFFFFFD IL_01f7 06 ldloc.0 IL_01f8 02 ldarg.0 IL_01f9 7b 22 0c 00 0a ldfld 0xA000C22 IL_01fe 8f 29 04 00 1b ldelema 0x1B000429 IL_0203 7b 09 0c 00 0a ldfld 0xA000C09 IL_0208 59 sub IL_0209 15 ldc.i4.m1 IL_020a fe 04 clt IL_020c 16 ldc.i4.0 IL_020d fe 01 ceq IL_020f 72 49 48 03 70 ldstr 0x70034849 IL_0214 28 fa 5c 00 06 call 0x6005CFA IL_0219 02 ldarg.0 IL_021a 1f fd ldc.i4.s 0xFFFFFFFD IL_021c 06 ldloc.0 IL_021d 02 ldarg.0 IL_021e 7b 22 0c 00 0a ldfld 0xA000C22 IL_0223 8f 29 04 00 1b ldelema 0x1B000429 IL_0228 7b 09 0c 00 0a ldfld 0xA000C09 IL_022d 59 sub IL_022e 7d 22 0c 00 0a stfld 0xA000C22 IL_0233 02 ldarg.0 IL_0234 02 ldarg.0 IL_0235 7b 10 0c 00 0a ldfld 0xA000C10 IL_023a 17 ldc.i4.1 IL_023b 59 sub IL_023c 7d 10 0c 00 0a stfld 0xA000C10 IL_0241 2b 33 br.s 51 (IL_0276) IL_0243 02 ldarg.0 IL_0244 7b 07 0c 00 0a ldfld 0xA000C07 IL_0249 13 09 stloc.s 0x9 IL_024b 11 09 ldloc.s 0x9 IL_024d 06 ldloc.0 IL_024e 8e ldlen IL_024f 69 conv.i4 IL_0250 33 0f bne.un.s 15 (IL_0261) IL_0252 02 ldarg.0 IL_0253 28 2c 0c 00 0a call 0xA000C2C IL_0258 02 ldarg.0 IL_0259 08 ldloc.2 IL_025a 28 27 0c 00 0a call 0xA000C27 IL_025f 13 04 stloc.s 0x4 IL_0261 11 09 ldloc.s 0x9 IL_0263 13 06 stloc.s 0x6 IL_0265 02 ldarg.0 IL_0266 11 09 ldloc.s 0x9 IL_0268 17 ldc.i4.1 IL_0269 58 add IL_026a 7d 07 0c 00 0a stfld 0xA000C07 IL_026f 02 ldarg.0 IL_0270 7b 06 0c 00 0a ldfld 0xA000C06 IL_0275 0a stloc.0 IL_0276 06 ldloc.0 IL_0277 11 06 ldloc.s 0x6 IL_0279 8f 29 04 00 1b ldelema 0x1B000429 IL_027e 13 07 stloc.s 0x7 IL_0280 11 07 ldloc.s 0x7 IL_0282 08 ldloc.2 IL_0283 7d 28 0c 00 0a stfld 0xA000C28 IL_0288 11 07 ldloc.s 0x7 IL_028a 11 04 ldloc.s 0x4 IL_028c 4a ldind.i4 IL_028d 17 ldc.i4.1 IL_028e 59 sub IL_028f 7d 09 0c 00 0a stfld 0xA000C09 IL_0294 11 07 ldloc.s 0x7 IL_0296 03 ldarg.1 IL_0297 7d 0a 0c 00 0a stfld 0xA000C0A IL_029c 11 07 ldloc.s 0x7 IL_029e 04 ldarg.2 IL_029f 7d 0b 0c 00 0a stfld 0xA000C0B IL_02a4 11 04 ldloc.s 0x4 IL_02a6 11 06 ldloc.s 0x6 IL_02a8 17 ldc.i4.1 IL_02a9 58 add IL_02aa 54 stind.i4 IL_02ab 02 ldarg.0 IL_02ac 02 ldarg.0 IL_02ad 7b 24 0c 00 0a ldfld 0xA000C24 IL_02b2 17 ldc.i4.1 IL_02b3 58 add IL_02b4 7d 24 0c 00 0a stfld 0xA000C24 IL_02b9 d0 18 00 00 1b ldtoken 0x1B000018 IL_02be 28 d6 07 00 06 call 0x60007D6 IL_02c3 28 1f 08 00 06 call 0x600081F IL_02c8 2d 17 brtrue.s 23 (IL_02e1) IL_02ca 09 ldloc.3 IL_02cb 1f 64 ldc.i4.s 0x64 IL_02cd 36 12 ble.un.s 18 (IL_02e1) IL_02cf 07 ldloc.1 IL_02d0 75 6b 08 00 02 isinst 0x200086B IL_02d5 2c 0a brfalse.s 10 (IL_02e1) IL_02d7 02 ldarg.0 IL_02d8 06 ldloc.0 IL_02d9 8e ldlen IL_02da 69 conv.i4 IL_02db 17 ldc.i4.1 IL_02dc 28 2d 0c 00 0a call 0xA000C2D IL_02e1 17 ldc.i4.1 IL_02e2 2a ret lvaSetClass: setting class for V00 to (00000000D1FFAB1E) System.Collections.Generic.Dictionary`2[__Canon,__Canon] 'this' passed in register rcx lvaSetClass: setting class for V01 to (00000000D1FFAB1E) System.__Canon Arg #1 passed in register(s) rdx lvaSetClass: setting class for V02 to (00000000D1FFAB1E) System.__Canon Arg #2 passed in register(s) r8 Arg #3 passed in register(s) r9 lvaSetClass: setting class for V04 to (00000000D1FFAB1E) System.Collections.Generic.Dictionary`2+Entry[System.__Canon,System.__Canon][] lvaSetClass: setting class for V05 to (00000000D1FFAB1E) System.Collections.Generic.IEqualityComparer`1[__Canon] lvaSetClass: setting class for V12 to (00000000D1FFAB1E) System.Collections.Generic.EqualityComparer`1[__Canon] lvaGrabTemp returning 14 (V14 tmp0) (a long lifetime temp) called for OutgoingArgSpace. ; Initial local variable assignments ; ; V00 this ref this class-hnd ; V01 arg1 ref class-hnd ; V02 arg2 ref class-hnd ; V03 arg3 ubyte ; V04 loc0 ref class-hnd ; V05 loc1 ref class-hnd ; V06 loc2 int ; V07 loc3 int ; V08 loc4 byref ; V09 loc5 int ; V10 loc6 int ; V11 loc7 byref ; V12 loc8 ref class-hnd ; V13 loc9 int ; V14 OutArgs lclBlk "OutgoingArgSpace" *************** In compInitDebuggingInfo() for System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this getVars() returned cVars = 0, extendOthers = true info.compVarScopesCount = 14 VarNum LVNum Name Beg End 0: 00h 00h V00 this 000h 2E3h 1: 01h 01h V01 arg1 000h 2E3h 2: 02h 02h V02 arg2 000h 2E3h 3: 03h 03h V03 arg3 000h 2E3h 4: 04h 04h V04 loc0 000h 2E3h 5: 05h 05h V05 loc1 000h 2E3h 6: 06h 06h V06 loc2 000h 2E3h 7: 07h 07h V07 loc3 000h 2E3h 8: 08h 08h V08 loc4 000h 2E3h 9: 09h 09h V09 loc5 000h 2E3h 10: 0Ah 0Ah V10 loc6 000h 2E3h 11: 0Bh 0Bh V11 loc7 000h 2E3h 12: 0Ch 0Ch V12 loc8 000h 2E3h 13: 0Dh 0Dh V13 loc9 000h 2E3h info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE ) *************** In fgFindBasicBlocks() for System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this Marked V05 as a single def local Marked V06 as a single def local Marked V11 as a single def local Marked V12 as a single def local Marked V13 as a single def local Jump targets: IL_000e IL_001e IL_0054 IL_0061 IL_008b IL_00d3 IL_00dd IL_00df IL_00ff IL_0106 IL_014b IL_0155 IL_0157 IL_0177 IL_01b8 IL_01c2 IL_01c4 IL_01e4 IL_0243 IL_0261 IL_0276 IL_02e1 New Basic Block BB01 [0000] created. BB01 [000..008) New Basic Block BB02 [0001] created. BB02 [008..00E) New Basic Block BB03 [0002] created. BB03 [00E..016) New Basic Block BB04 [0003] created. BB04 [016..01E) New Basic Block BB05 [0004] created. BB05 [01E..04B) New Basic Block BB06 [0005] created. BB06 [04B..054) New Basic Block BB07 [0006] created. BB07 [054..061) New Basic Block BB08 [0007] created. BB08 [061..07A) New Basic Block BB09 [0008] created. BB09 [07A..08B) New Basic Block BB10 [0009] created. BB10 [08B..095) New Basic Block BB11 [0010] created. BB11 [095..0A5) New Basic Block BB12 [0011] created. BB12 [0A5..0BF) New Basic Block BB13 [0012] created. BB13 [0BF..0C3) New Basic Block BB14 [0013] created. BB14 [0C3..0D3) New Basic Block BB15 [0014] created. BB15 [0D3..0D7) New Basic Block BB16 [0015] created. BB16 [0D7..0DD) New Basic Block BB17 [0016] created. BB17 [0DD..0DF) New Basic Block BB18 [0017] created. BB18 [0DF..0F8) New Basic Block BB19 [0018] created. BB19 [0F8..0FF) New Basic Block BB20 [0019] created. BB20 [0FF..106) New Basic Block BB21 [0020] created. BB21 [106..110) New Basic Block BB22 [0021] created. BB22 [110..120) New Basic Block BB23 [0022] created. BB23 [120..137) New Basic Block BB24 [0023] created. BB24 [137..13B) New Basic Block BB25 [0024] created. BB25 [13B..14B) New Basic Block BB26 [0025] created. BB26 [14B..14F) New Basic Block BB27 [0026] created. BB27 [14F..155) New Basic Block BB28 [0027] created. BB28 [155..157) New Basic Block BB29 [0028] created. BB29 [157..170) New Basic Block BB30 [0029] created. BB30 [170..177) New Basic Block BB31 [0030] created. BB31 [177..17E) New Basic Block BB32 [0031] created. BB32 [17E..18E) New Basic Block BB33 [0032] created. BB33 [18E..1A4) New Basic Block BB34 [0033] created. BB34 [1A4..1A8) New Basic Block BB35 [0034] created. BB35 [1A8..1B8) New Basic Block BB36 [0035] created. BB36 [1B8..1BC) New Basic Block BB37 [0036] created. BB37 [1BC..1C2) New Basic Block BB38 [0037] created. BB38 [1C2..1C4) New Basic Block BB39 [0038] created. BB39 [1C4..1DD) New Basic Block BB40 [0039] created. BB40 [1DD..1E4) New Basic Block BB41 [0040] created. BB41 [1E4..1ED) New Basic Block BB42 [0041] created. BB42 [1ED..243) New Basic Block BB43 [0042] created. BB43 [243..252) New Basic Block BB44 [0043] created. BB44 [252..261) New Basic Block BB45 [0044] created. BB45 [261..276) New Basic Block BB46 [0045] created. BB46 [276..2CA) New Basic Block BB47 [0046] created. BB47 [2CA..2CF) New Basic Block BB48 [0047] created. BB48 [2CF..2D7) New Basic Block BB49 [0048] created. BB49 [2D7..2E1) New Basic Block BB50 [0049] created. BB50 [2E1..2E3) IL Code Size,Instr 739, 320, Basic Block count 50, Local Variable Num,Ref count 15,130 for method System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this OPTIONS: opts.MinOpts() == false Basic block list for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) BB02 [0001] 1 1 [008..00E) BB03 [0002] 2 1 [00E..016)-> BB05 ( cond ) BB04 [0003] 1 1 [016..01E) BB05 [0004] 2 1 [01E..04B)-> BB07 ( cond ) BB06 [0005] 1 1 [04B..054)-> BB08 (always) BB07 [0006] 1 1 [054..061) BB08 [0007] 2 1 [061..07A)-> BB31 ( cond ) BB09 [0008] 1 1 [07A..08B)-> BB20 ( cond ) BB10 [0009] 3 1 [08B..095)-> BB41 ( cond ) bwd bwd-target BB11 [0010] 1 1 [095..0A5)-> BB18 ( cond ) bwd BB12 [0011] 1 1 [0A5..0BF)-> BB18 ( cond ) bwd BB13 [0012] 1 1 [0BF..0C3)-> BB15 ( cond ) bwd BB14 [0013] 1 1 [0C3..0D3) (return) BB15 [0014] 1 1 [0D3..0D7)-> BB17 ( cond ) bwd BB16 [0015] 1 1 [0D7..0DD) bwd BB17 [0016] 2 1 [0DD..0DF) (return) BB18 [0017] 2 1 [0DF..0F8)-> BB10 ( cond ) bwd BB19 [0018] 1 1 [0F8..0FF)-> BB10 (always) bwd BB20 [0019] 1 1 [0FF..106) BB21 [0020] 3 1 [106..110)-> BB41 ( cond ) bwd bwd-target BB22 [0021] 1 1 [110..120)-> BB29 ( cond ) bwd BB23 [0022] 1 1 [120..137)-> BB29 ( cond ) bwd BB24 [0023] 1 1 [137..13B)-> BB26 ( cond ) bwd BB25 [0024] 1 1 [13B..14B) (return) BB26 [0025] 1 1 [14B..14F)-> BB28 ( cond ) bwd BB27 [0026] 1 1 [14F..155) bwd BB28 [0027] 2 1 [155..157) (return) BB29 [0028] 2 1 [157..170)-> BB21 ( cond ) bwd BB30 [0029] 1 1 [170..177)-> BB21 (always) bwd BB31 [0030] 3 1 [177..17E)-> BB41 ( cond ) bwd bwd-target BB32 [0031] 1 1 [17E..18E)-> BB39 ( cond ) bwd BB33 [0032] 1 1 [18E..1A4)-> BB39 ( cond ) bwd BB34 [0033] 1 1 [1A4..1A8)-> BB36 ( cond ) bwd BB35 [0034] 1 1 [1A8..1B8) (return) BB36 [0035] 1 1 [1B8..1BC)-> BB38 ( cond ) bwd BB37 [0036] 1 1 [1BC..1C2) bwd BB38 [0037] 2 1 [1C2..1C4) (return) BB39 [0038] 2 1 [1C4..1DD)-> BB31 ( cond ) bwd BB40 [0039] 1 1 [1DD..1E4)-> BB31 (always) bwd BB41 [0040] 3 1 [1E4..1ED)-> BB43 ( cond ) BB42 [0041] 1 1 [1ED..243)-> BB46 (always) BB43 [0042] 1 1 [243..252)-> BB45 ( cond ) BB44 [0043] 1 1 [252..261) BB45 [0044] 2 1 [261..276) BB46 [0045] 2 1 [276..2CA)-> BB50 ( cond ) BB47 [0046] 1 1 [2CA..2CF)-> BB50 ( cond ) BB48 [0047] 1 1 [2CF..2D7)-> BB50 ( cond ) BB49 [0048] 1 1 [2D7..2E1) BB50 [0049] 4 1 [2E1..2E3) (return) ----------------------------------------------------------------------------------------------------------------------------------------- Compiling 27 System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]::TryInsert, IL size = 739, hash=0x0b956994 FullOpts *************** Starting PHASE Pre-import *************** Finishing PHASE Pre-import *************** Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) *************** Finishing PHASE Profile incorporation [no changes] *************** Starting PHASE Importation *************** In impImport() for System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this impImportBlockPending for BB01 Importing BB01 (PC=000) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 0 (0x000) ldarg.1 [ 1] 1 (0x001) box 1B000018 Importing BOX(refClass) as NOP [ 1] 6 (0x006) brtrue.s STMT00000 (IL 0x000... ???) [000003] ------------ * JTRUE void [000002] ------------ \--* NE int [000000] ------------ +--* LCL_VAR ref V01 arg1 [000001] ------------ \--* CNS_INT ref null impImportBlockPending for BB02 impImportBlockPending for BB03 Importing BB03 (PC=014) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 14 (0x00e) ldarg.0 [ 1] 15 (0x00f) ldfld 0A000C21 [ 1] 20 (0x014) brtrue.s STMT00001 (IL 0x00E... ???) [000008] ---XG------- * JTRUE void [000007] ---XG------- \--* NE int [000005] ---XG------- +--* FIELD ref _buckets [000004] ------------ | \--* LCL_VAR ref V00 this [000006] ------------ \--* CNS_INT ref null impImportBlockPending for BB04 impImportBlockPending for BB05 Importing BB05 (PC=030) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 30 (0x01e) ldarg.0 [ 1] 31 (0x01f) ldfld 0A000C21 [ 1] 36 (0x024) ldnull [ 2] 37 (0x025) cgt.un [ 1] 39 (0x027) call 06005CF9 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 STMT00002 (IL 0x01E... ???) [000013] I-CXG------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000014] ---XG------- arg0 \--* PUTARG_TYPE bool [000012] N--XG----U-- \--* GT int [000010] ---XG------- +--* FIELD ref _buckets [000009] ------------ | \--* LCL_VAR ref V00 this [000011] ------------ \--* CNS_INT ref null [ 0] 44 (0x02c) ldarg.0 [ 1] 45 (0x02d) ldfld 0A000C06 [ 1] 50 (0x032) stloc.0 STMT00003 (IL 0x02C... ???) [000018] -A-XG------- * ASG ref [000017] D------N---- +--* LCL_VAR ref V04 loc0 [000016] ---XG------- \--* FIELD ref _entries [000015] ------------ \--* LCL_VAR ref V00 this [ 0] 51 (0x033) ldloc.0 [ 1] 52 (0x034) ldnull [ 2] 53 (0x035) cgt.un [ 1] 55 (0x037) ldstr 70034809 [ 2] 60 (0x03c) call 06005CFA In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 STMT00004 (IL 0x033... ???) [000023] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000024] ------------ arg0 +--* PUTARG_TYPE bool [000021] N--------U-- | \--* GT int [000019] ------------ | +--* LCL_VAR ref V04 loc0 [000020] ------------ | \--* CNS_INT ref null [000022] ------------ arg1 \--* CNS_STR ref [ 0] 65 (0x041) ldarg.0 [ 1] 66 (0x042) ldfld 0A000C00 [ 1] 71 (0x047) stloc.1Querying runtime about current class of field System.Collections.Generic.Dictionary`2[System.__Canon,System.__Canon]._comparer (declared as System.Collections.Generic.IEqualityComparer`1[__Canon]) Field's current class not available STMT00005 (IL 0x041... ???) [000028] -A-XG------- * ASG ref [000027] D------N---- +--* LCL_VAR ref V05 loc1 [000026] ---XG------- \--* FIELD ref _comparer [000025] ------------ \--* LCL_VAR ref V00 this [ 0] 72 (0x048) ldloc.1 [ 1] 73 (0x049) brfalse.s STMT00006 (IL 0x048... ???) [000032] ------------ * JTRUE void [000031] ------------ \--* EQ int [000029] ------------ +--* LCL_VAR ref V05 loc1 [000030] ------------ \--* CNS_INT ref null impImportBlockPending for BB06 impImportBlockPending for BB07 Importing BB07 (PC=084) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 84 (0x054) ldarga.s 1 [ 1] 86 (0x056) constrained. (1B000018) callvirt 060004E4 In Compiler::impImportCall: opcode is callvirt, kind=4, callRetType is int, structSize is 0 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is System.__Canon (attrib 20020000) base method is System.Object::GetHashCode --- no derived method Class not final or exact, and method not final Considering guarded devirtualization at IL offset 92 (0x5c) Not guessing for class: no class profile pgo data, or pgo disabled INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Object:GetHashCode():int:this' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' *************** In impGetSpillTmpBase(BB07) lvaGrabTemps(1) returning 15..15 (long lifetime temps) called for IL Stack Entries *************** In fgComputeCheapPreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 1 [008..00E) BB03 [0002] 2 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 1 [016..01E) BB05 [0004] 2 1 [01E..04B)-> BB07 ( cond ) i BB06 [0005] 1 1 [04B..054)-> BB08 (always) BB07 [0006] 1 1 [054..061) BB08 [0007] 2 1 [061..07A)-> BB31 ( cond ) BB09 [0008] 1 1 [07A..08B)-> BB20 ( cond ) BB10 [0009] 3 1 [08B..095)-> BB41 ( cond ) bwd bwd-target BB11 [0010] 1 1 [095..0A5)-> BB18 ( cond ) bwd BB12 [0011] 1 1 [0A5..0BF)-> BB18 ( cond ) bwd BB13 [0012] 1 1 [0BF..0C3)-> BB15 ( cond ) bwd BB14 [0013] 1 1 [0C3..0D3) (return) BB15 [0014] 1 1 [0D3..0D7)-> BB17 ( cond ) bwd BB16 [0015] 1 1 [0D7..0DD) bwd BB17 [0016] 2 1 [0DD..0DF) (return) BB18 [0017] 2 1 [0DF..0F8)-> BB10 ( cond ) bwd BB19 [0018] 1 1 [0F8..0FF)-> BB10 (always) bwd BB20 [0019] 1 1 [0FF..106) BB21 [0020] 3 1 [106..110)-> BB41 ( cond ) bwd bwd-target BB22 [0021] 1 1 [110..120)-> BB29 ( cond ) bwd BB23 [0022] 1 1 [120..137)-> BB29 ( cond ) bwd BB24 [0023] 1 1 [137..13B)-> BB26 ( cond ) bwd BB25 [0024] 1 1 [13B..14B) (return) BB26 [0025] 1 1 [14B..14F)-> BB28 ( cond ) bwd BB27 [0026] 1 1 [14F..155) bwd BB28 [0027] 2 1 [155..157) (return) BB29 [0028] 2 1 [157..170)-> BB21 ( cond ) bwd BB30 [0029] 1 1 [170..177)-> BB21 (always) bwd BB31 [0030] 3 1 [177..17E)-> BB41 ( cond ) bwd bwd-target BB32 [0031] 1 1 [17E..18E)-> BB39 ( cond ) bwd BB33 [0032] 1 1 [18E..1A4)-> BB39 ( cond ) bwd BB34 [0033] 1 1 [1A4..1A8)-> BB36 ( cond ) bwd BB35 [0034] 1 1 [1A8..1B8) (return) BB36 [0035] 1 1 [1B8..1BC)-> BB38 ( cond ) bwd BB37 [0036] 1 1 [1BC..1C2) bwd BB38 [0037] 2 1 [1C2..1C4) (return) BB39 [0038] 2 1 [1C4..1DD)-> BB31 ( cond ) bwd BB40 [0039] 1 1 [1DD..1E4)-> BB31 (always) bwd BB41 [0040] 3 1 [1E4..1ED)-> BB43 ( cond ) BB42 [0041] 1 1 [1ED..243)-> BB46 (always) BB43 [0042] 1 1 [243..252)-> BB45 ( cond ) BB44 [0043] 1 1 [252..261) BB45 [0044] 2 1 [261..276) BB46 [0045] 2 1 [276..2CA)-> BB50 ( cond ) BB47 [0046] 1 1 [2CA..2CF)-> BB50 ( cond ) BB48 [0047] 1 1 [2CF..2D7)-> BB50 ( cond ) BB49 [0048] 1 1 [2D7..2E1) BB50 [0049] 4 1 [2E1..2E3) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** After fgComputeCheapPreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd cheap preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 BB01 1 [008..00E) BB03 [0002] 2 BB02,BB01 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) BB05 [0004] 2 BB04,BB03 1 [01E..04B)-> BB07 ( cond ) i BB06 [0005] 1 BB05 1 [04B..054)-> BB08 (always) BB07 [0006] 1 BB05 1 [054..061) BB08 [0007] 2 BB07,BB06 1 [061..07A)-> BB31 ( cond ) BB09 [0008] 1 BB08 1 [07A..08B)-> BB20 ( cond ) BB10 [0009] 3 BB19,BB18,BB09 1 [08B..095)-> BB41 ( cond ) bwd bwd-target BB11 [0010] 1 BB10 1 [095..0A5)-> BB18 ( cond ) bwd BB12 [0011] 1 BB11 1 [0A5..0BF)-> BB18 ( cond ) bwd BB13 [0012] 1 BB12 1 [0BF..0C3)-> BB15 ( cond ) bwd BB14 [0013] 1 BB13 1 [0C3..0D3) (return) BB15 [0014] 1 BB13 1 [0D3..0D7)-> BB17 ( cond ) bwd BB16 [0015] 1 BB15 1 [0D7..0DD) bwd BB17 [0016] 2 BB16,BB15 1 [0DD..0DF) (return) BB18 [0017] 2 BB12,BB11 1 [0DF..0F8)-> BB10 ( cond ) bwd BB19 [0018] 1 BB18 1 [0F8..0FF)-> BB10 (always) bwd BB20 [0019] 1 BB09 1 [0FF..106) BB21 [0020] 3 BB30,BB29,BB20 1 [106..110)-> BB41 ( cond ) bwd bwd-target BB22 [0021] 1 BB21 1 [110..120)-> BB29 ( cond ) bwd BB23 [0022] 1 BB22 1 [120..137)-> BB29 ( cond ) bwd BB24 [0023] 1 BB23 1 [137..13B)-> BB26 ( cond ) bwd BB25 [0024] 1 BB24 1 [13B..14B) (return) BB26 [0025] 1 BB24 1 [14B..14F)-> BB28 ( cond ) bwd BB27 [0026] 1 BB26 1 [14F..155) bwd BB28 [0027] 2 BB27,BB26 1 [155..157) (return) BB29 [0028] 2 BB23,BB22 1 [157..170)-> BB21 ( cond ) bwd BB30 [0029] 1 BB29 1 [170..177)-> BB21 (always) bwd BB31 [0030] 3 BB40,BB39,BB08 1 [177..17E)-> BB41 ( cond ) bwd bwd-target BB32 [0031] 1 BB31 1 [17E..18E)-> BB39 ( cond ) bwd BB33 [0032] 1 BB32 1 [18E..1A4)-> BB39 ( cond ) bwd BB34 [0033] 1 BB33 1 [1A4..1A8)-> BB36 ( cond ) bwd BB35 [0034] 1 BB34 1 [1A8..1B8) (return) BB36 [0035] 1 BB34 1 [1B8..1BC)-> BB38 ( cond ) bwd BB37 [0036] 1 BB36 1 [1BC..1C2) bwd BB38 [0037] 2 BB37,BB36 1 [1C2..1C4) (return) BB39 [0038] 2 BB33,BB32 1 [1C4..1DD)-> BB31 ( cond ) bwd BB40 [0039] 1 BB39 1 [1DD..1E4)-> BB31 (always) bwd BB41 [0040] 3 BB31,BB21,BB10 1 [1E4..1ED)-> BB43 ( cond ) BB42 [0041] 1 BB41 1 [1ED..243)-> BB46 (always) BB43 [0042] 1 BB41 1 [243..252)-> BB45 ( cond ) BB44 [0043] 1 BB43 1 [252..261) BB45 [0044] 2 BB44,BB43 1 [261..276) BB46 [0045] 2 BB45,BB42 1 [276..2CA)-> BB50 ( cond ) BB47 [0046] 1 BB46 1 [2CA..2CF)-> BB50 ( cond ) BB48 [0047] 1 BB47 1 [2CF..2D7)-> BB50 ( cond ) BB49 [0048] 1 BB48 1 [2D7..2E1) BB50 [0049] 4 BB49,BB48,BB47,BB46 1 [2E1..2E3) (return) ----------------------------------------------------------------------------------------------------------------------------------------- Spilling stack entries into temps STMT00007 (IL 0x054... ???) [000038] -ACXG------- * ASG int [000037] D------N---- +--* LCL_VAR int V15 tmp1 [000035] --CXG------- \--* CALLV vt-ind int System.Object.GetHashCode [000036] *--XG------- this in rcx \--* IND ref [000034] ------------ \--* ADDR long [000033] -------N---- \--* LCL_VAR ref V01 arg1 impImportBlockPending for BB08 Importing BB08 (PC=097) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 1] 97 (0x061) stloc.2 STMT00008 (IL ???... ???) [000042] -A---------- * ASG int [000041] D------N---- +--* LCL_VAR int V06 loc2 [000040] ------------ \--* LCL_VAR int V15 tmp1 [ 0] 98 (0x062) ldc.i4.0 0 [ 1] 99 (0x063) stloc.3 STMT00009 (IL 0x062... ???) [000045] -A---------- * ASG int [000044] D------N---- +--* LCL_VAR int V07 loc3 [000043] ------------ \--* CNS_INT int 0 [ 0] 100 (0x064) ldarg.0 [ 1] 101 (0x065) ldloc.2 [ 2] 102 (0x066) call 0A000C27 In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 STMT00010 (IL 0x064... ???) [000048] I-C-G------- * CALL byref System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].GetBucket (exactContextHnd=0x00000000D1FFAB1E) [000046] ------------ this in rcx +--* LCL_VAR ref V00 this [000047] ------------ arg1 \--* LCL_VAR int V06 loc2 [ 1] 107 (0x06b) stloc.s 4 STMT00011 (IL ???... ???) [000051] -AC--------- * ASG byref [000050] D------N---- +--* LCL_VAR byref V08 loc4 [000049] --C--------- \--* RET_EXPR byref (inl return expr [000048]) [ 0] 109 (0x06d) ldloc.s 4 [ 1] 111 (0x06f) ldind.i4 [ 1] 112 (0x070) ldc.i4.1 1 [ 2] 113 (0x071) sub [ 1] 114 (0x072) stloc.s 5 STMT00012 (IL 0x06D... ???) [000057] -A-XG------- * ASG int [000056] D------N---- +--* LCL_VAR int V09 loc5 [000055] ---XG------- \--* SUB int [000053] *--XG------- +--* IND int [000052] ------------ | \--* LCL_VAR byref V08 loc4 [000054] ------------ \--* CNS_INT int 1 [ 0] 116 (0x074) ldloc.1 [ 1] 117 (0x075) brtrue STMT00013 (IL 0x074... ???) [000061] ------------ * JTRUE void [000060] ------------ \--* NE int [000058] ------------ +--* LCL_VAR ref V05 loc1 [000059] ------------ \--* CNS_INT ref null impImportBlockPending for BB09 impImportBlockPending for BB31 Importing BB31 (PC=375) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 375 (0x177) ldloc.s 5 [ 1] 377 (0x179) ldloc.0 [ 2] 378 (0x17a) ldlen [ 2] 379 (0x17b) conv.i4 [ 2] 380 (0x17c) bge.un.s STMT00014 (IL 0x177... ???) [000066] ---X-------- * JTRUE void [000065] N--X-----U-- \--* GE int [000062] ------------ +--* LCL_VAR int V09 loc5 [000064] ---X-------- \--* ARR_LENGTH int [000063] ------------ \--* LCL_VAR ref V04 loc0 impImportBlockPending for BB32 impImportBlockPending for BB41 Importing BB41 (PC=484) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 484 (0x1e4) ldarg.0 [ 1] 485 (0x1e5) ldfld 0A000C10 [ 1] 490 (0x1ea) ldc.i4.0 0 [ 2] 491 (0x1eb) ble.s STMT00015 (IL 0x1E4... ???) [000071] ---XG------- * JTRUE void [000070] ---XG------- \--* LE int [000068] ---XG------- +--* FIELD int _freeCount [000067] ------------ | \--* LCL_VAR ref V00 this [000069] ------------ \--* CNS_INT int 0 impImportBlockPending for BB42 impImportBlockPending for BB43 Importing BB43 (PC=579) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 579 (0x243) ldarg.0 [ 1] 580 (0x244) ldfld 0A000C07 [ 1] 585 (0x249) stloc.s 9 STMT00016 (IL 0x243... ???) [000075] -A-XG------- * ASG int [000074] D------N---- +--* LCL_VAR int V13 loc9 [000073] ---XG------- \--* FIELD int _count [000072] ------------ \--* LCL_VAR ref V00 this [ 0] 587 (0x24b) ldloc.s 9 [ 1] 589 (0x24d) ldloc.0 [ 2] 590 (0x24e) ldlen [ 2] 591 (0x24f) conv.i4 [ 2] 592 (0x250) bne.un.s STMT00017 (IL 0x24B... ???) [000080] ---X-------- * JTRUE void [000079] N--X-----U-- \--* NE int [000076] ------------ +--* LCL_VAR int V13 loc9 [000078] ---X-------- \--* ARR_LENGTH int [000077] ------------ \--* LCL_VAR ref V04 loc0 impImportBlockPending for BB44 impImportBlockPending for BB45 Importing BB45 (PC=609) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 609 (0x261) ldloc.s 9 [ 1] 611 (0x263) stloc.s 6 STMT00018 (IL 0x261... ???) [000083] -A---------- * ASG int [000082] D------N---- +--* LCL_VAR int V10 loc6 [000081] ------------ \--* LCL_VAR int V13 loc9 [ 0] 613 (0x265) ldarg.0 [ 1] 614 (0x266) ldloc.s 9 [ 2] 616 (0x268) ldc.i4.1 1 [ 3] 617 (0x269) add [ 2] 618 (0x26a) stfld 0A000C07 STMT00019 (IL 0x265... ???) [000089] -A-XG------- * ASG int [000088] ---XG--N---- +--* FIELD int _count [000084] ------------ | \--* LCL_VAR ref V00 this [000087] ------------ \--* ADD int [000085] ------------ +--* LCL_VAR int V13 loc9 [000086] ------------ \--* CNS_INT int 1 [ 0] 623 (0x26f) ldarg.0 [ 1] 624 (0x270) ldfld 0A000C06 [ 1] 629 (0x275) stloc.0 STMT00020 (IL 0x26F... ???) [000093] -A-XG------- * ASG ref [000092] D------N---- +--* LCL_VAR ref V04 loc0 [000091] ---XG------- \--* FIELD ref _entries [000090] ------------ \--* LCL_VAR ref V00 this impImportBlockPending for BB46 Importing BB46 (PC=630) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 630 (0x276) ldloc.0 [ 1] 631 (0x277) ldloc.s 6 [ 2] 633 (0x279) ldelema 1B000429 [ 1] 638 (0x27e) stloc.s 7 STMT00021 (IL 0x276... ???) [000099] -A-XG------- * ASG byref [000098] D------N---- +--* LCL_VAR byref V11 loc7 [000097] ---XG------- \--* ADDR byref [000096] ---XG--N---- \--* INDEX struct [000094] ------------ +--* LCL_VAR ref V04 loc0 [000095] ------------ \--* LCL_VAR int V10 loc6 [ 0] 640 (0x280) ldloc.s 7 [ 1] 642 (0x282) ldloc.2 [ 2] 643 (0x283) stfld 0A000C28 STMT00022 (IL 0x280... ???) [000103] -A-XG------- * ASG int [000102] ---XG--N---- +--* FIELD int hashCode [000100] ------------ | \--* LCL_VAR byref V11 loc7 [000101] ------------ \--* LCL_VAR int V06 loc2 [ 0] 648 (0x288) ldloc.s 7 [ 1] 650 (0x28a) ldloc.s 4 [ 2] 652 (0x28c) ldind.i4 [ 2] 653 (0x28d) ldc.i4.1 1 [ 3] 654 (0x28e) sub [ 2] 655 (0x28f) stfld 0A000C09 STMT00023 (IL 0x288... ???) [000110] -A-XG------- * ASG int [000109] ---XG--N---- +--* FIELD int next [000104] ------------ | \--* LCL_VAR byref V11 loc7 [000108] ---XG------- \--* SUB int [000106] *--XG------- +--* IND int [000105] ------------ | \--* LCL_VAR byref V08 loc4 [000107] ------------ \--* CNS_INT int 1 [ 0] 660 (0x294) ldloc.s 7 [ 1] 662 (0x296) ldarg.1 [ 2] 663 (0x297) stfld 0A000C0A STMT00024 (IL 0x294... ???) [000114] -A-XG------- * ASG ref [000113] ---XG--N---- +--* FIELD ref key [000111] ------------ | \--* LCL_VAR byref V11 loc7 [000112] ------------ \--* LCL_VAR ref V01 arg1 [ 0] 668 (0x29c) ldloc.s 7 [ 1] 670 (0x29e) ldarg.2 [ 2] 671 (0x29f) stfld 0A000C0B STMT00025 (IL 0x29C... ???) [000118] -A-XG------- * ASG ref [000117] ---XG--N---- +--* FIELD ref value [000115] ------------ | \--* LCL_VAR byref V11 loc7 [000116] ------------ \--* LCL_VAR ref V02 arg2 [ 0] 676 (0x2a4) ldloc.s 4 [ 1] 678 (0x2a6) ldloc.s 6 [ 2] 680 (0x2a8) ldc.i4.1 1 [ 3] 681 (0x2a9) add [ 2] 682 (0x2aa) stind.i4 STMT00026 (IL 0x2A4... ???) [000124] -A-XG------- * ASG int [000123] *------N---- +--* IND int [000119] ------------ | \--* LCL_VAR byref V08 loc4 [000122] ------------ \--* ADD int [000120] ------------ +--* LCL_VAR int V10 loc6 [000121] ------------ \--* CNS_INT int 1 [ 0] 683 (0x2ab) ldarg.0 [ 1] 684 (0x2ac) ldarg.0 [ 2] 685 (0x2ad) ldfld 0A000C24 [ 2] 690 (0x2b2) ldc.i4.1 1 [ 3] 691 (0x2b3) add [ 2] 692 (0x2b4) stfld 0A000C24 STMT00027 (IL 0x2AB... ???) [000131] -A-XG------- * ASG int [000130] ---XG--N---- +--* FIELD int _version [000125] ------------ | \--* LCL_VAR ref V00 this [000129] ---XG------- \--* ADD int [000127] ---XG------- +--* FIELD int _version [000126] ------------ | \--* LCL_VAR ref V00 this [000128] ------------ \--* CNS_INT int 1 [ 0] 697 (0x2b9) ldtoken [ 1] 702 (0x2be) call 060007D6 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 Named Intrinsic System.Type.GetTypeFromHandle: Recognized [ 1] 707 (0x2c3) call 0600081F In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 Named Intrinsic System.Type.get_IsValueType: Recognized [ 1] 712 (0x2c8) brtrue.s Folding operator with constant nodes into a constant: [000144] ------------ * NE int [000142] ------------ +--* CNS_INT int 0 [000143] ------------ \--* CNS_INT int 0 Bashed to int constant: [000144] ------------ * CNS_INT int 0 The block falls through into the next BB47 impImportBlockPending for BB47 Importing BB47 (PC=714) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 714 (0x2ca) ldloc.3 [ 1] 715 (0x2cb) ldc.i4.s 100 [ 2] 717 (0x2cd) ble.un.s STMT00028 (IL 0x2CA... ???) [000148] ------------ * JTRUE void [000147] N--------U-- \--* LE int [000145] ------------ +--* LCL_VAR int V07 loc3 [000146] ------------ \--* CNS_INT int 100 impImportBlockPending for BB48 impImportBlockPending for BB50 Importing BB50 (PC=737) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 737 (0x2e1) ldc.i4.1 1 [ 1] 738 (0x2e2) ret STMT00029 (IL 0x2E1... ???) [000150] ------------ * RETURN int [000149] ------------ \--* CNS_INT int 1 Importing BB48 (PC=719) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 719 (0x2cf) ldloc.1 [ 1] 720 (0x2d0) isinst 0200086B Considering optimization of isinst from 00000000D1FFAB1E (System.Collections.Generic.IEqualityComparer`1[__Canon]) to 00000000D1FFAB1E (System.Collections.Generic.NonRandomizedStringEqualityComparer) Result of cast unknown, must generate runtime test Expanding isinst as call because inline expansion not legal [ 1] 725 (0x2d5) brfalse.s STMT00030 (IL 0x2CF... ???) [000156] --C-G------- * JTRUE void [000155] --C-G------- \--* EQ int [000153] --C-G------- +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS [000152] H------N---- arg0 | +--* CNS_INT(h) long 0xd1ffab1e class [000151] ------------ arg1 | \--* LCL_VAR ref V05 loc1 [000154] ------------ \--* CNS_INT ref null impImportBlockPending for BB49 impImportBlockPending for BB50 Importing BB49 (PC=727) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 727 (0x2d7) ldarg.0 [ 1] 728 (0x2d8) ldloc.0 [ 2] 729 (0x2d9) ldlen [ 2] 730 (0x2da) conv.i4 [ 2] 731 (0x2db) ldc.i4.1 1 [ 3] 732 (0x2dc) call 0A000C2D In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize(int,bool):this' INLINER: Marking System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize(int,bool):this as NOINLINE because of too many il bytes INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' STMT00031 (IL 0x2D7... ???) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [000157] ------------ this in rcx +--* LCL_VAR ref V00 this [000159] ---X-------- arg1 +--* ARR_LENGTH int [000158] ------------ | \--* LCL_VAR ref V04 loc0 [000162] ------------ arg2 \--* PUTARG_TYPE bool [000160] ------------ \--* CNS_INT int 1 impImportBlockPending for BB50 Importing BB44 (PC=594) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 594 (0x252) ldarg.0 [ 1] 595 (0x253) call 0A000C2C In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 STMT00032 (IL 0x252... ???) [000164] I-C-G------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize (exactContextHnd=0x00000000D1FFAB1E) [000163] ------------ this in rcx \--* LCL_VAR ref V00 this [ 0] 600 (0x258) ldarg.0 [ 1] 601 (0x259) ldloc.2 [ 2] 602 (0x25a) call 0A000C27 In Compiler::impImportCall: opcode is call, kind=0, callRetType is byref, structSize is 0 STMT00033 (IL 0x258... ???) [000167] I-C-G------- * CALL byref System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].GetBucket (exactContextHnd=0x00000000D1FFAB1E) [000165] ------------ this in rcx +--* LCL_VAR ref V00 this [000166] ------------ arg1 \--* LCL_VAR int V06 loc2 [ 1] 607 (0x25f) stloc.s 4 STMT00034 (IL ???... ???) [000170] -AC--------- * ASG byref [000169] D------N---- +--* LCL_VAR byref V08 loc4 [000168] --C--------- \--* RET_EXPR byref (inl return expr [000167]) impImportBlockPending for BB45 Importing BB42 (PC=493) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 493 (0x1ed) ldarg.0 [ 1] 494 (0x1ee) ldfld 0A000C22 [ 1] 499 (0x1f3) stloc.s 6 STMT00035 (IL 0x1ED... ???) [000174] -A-XG------- * ASG int [000173] D------N---- +--* LCL_VAR int V10 loc6 [000172] ---XG------- \--* FIELD int _freeList [000171] ------------ \--* LCL_VAR ref V00 this [ 0] 501 (0x1f5) ldc.i4.s -3 [ 1] 503 (0x1f7) ldloc.0 [ 2] 504 (0x1f8) ldarg.0 [ 3] 505 (0x1f9) ldfld 0A000C22 [ 3] 510 (0x1fe) ldelema 1B000429 [ 2] 515 (0x203) ldfld 0A000C09 [ 2] 520 (0x208) sub [ 1] 521 (0x209) ldc.i4.m1 -1 [ 2] 522 (0x20a) clt [ 1] 524 (0x20c) ldc.i4.0 0 [ 2] 525 (0x20d) ceq [ 1] 527 (0x20f) ldstr 70034849 [ 2] 532 (0x214) call 06005CFA In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 STMT00036 (IL 0x1F5... ???) [000188] I-CXG------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000189] ---XG------- arg0 +--* PUTARG_TYPE bool [000186] ---XG------- | \--* EQ int [000184] ---XG------- | +--* LT int [000182] ---XG------- | | +--* SUB int [000175] ------------ | | | +--* CNS_INT int -3 [000181] ---XG------- | | | \--* FIELD int next [000180] ---XG------- | | | \--* ADDR byref [000179] ---XG--N---- | | | \--* INDEX struct [000176] ------------ | | | +--* LCL_VAR ref V04 loc0 [000178] ---XG------- | | | \--* FIELD int _freeList [000177] ------------ | | | \--* LCL_VAR ref V00 this [000183] ------------ | | \--* CNS_INT int -1 [000185] ------------ | \--* CNS_INT int 0 [000187] ------------ arg1 \--* CNS_STR ref [ 0] 537 (0x219) ldarg.0 [ 1] 538 (0x21a) ldc.i4.s -3 [ 2] 540 (0x21c) ldloc.0 [ 3] 541 (0x21d) ldarg.0 [ 4] 542 (0x21e) ldfld 0A000C22 [ 4] 547 (0x223) ldelema 1B000429 [ 3] 552 (0x228) ldfld 0A000C09 [ 3] 557 (0x22d) sub [ 2] 558 (0x22e) stfld 0A000C22 STMT00037 (IL 0x219... ???) [000200] -A-XG------- * ASG int [000199] ---XG--N---- +--* FIELD int _freeList [000190] ------------ | \--* LCL_VAR ref V00 this [000198] ---XG------- \--* SUB int [000191] ------------ +--* CNS_INT int -3 [000197] ---XG------- \--* FIELD int next [000196] ---XG------- \--* ADDR byref [000195] ---XG--N---- \--* INDEX struct [000192] ------------ +--* LCL_VAR ref V04 loc0 [000194] ---XG------- \--* FIELD int _freeList [000193] ------------ \--* LCL_VAR ref V00 this [ 0] 563 (0x233) ldarg.0 [ 1] 564 (0x234) ldarg.0 [ 2] 565 (0x235) ldfld 0A000C10 [ 2] 570 (0x23a) ldc.i4.1 1 [ 3] 571 (0x23b) sub [ 2] 572 (0x23c) stfld 0A000C10 STMT00038 (IL 0x233... ???) [000207] -A-XG------- * ASG int [000206] ---XG--N---- +--* FIELD int _freeCount [000201] ------------ | \--* LCL_VAR ref V00 this [000205] ---XG------- \--* SUB int [000203] ---XG------- +--* FIELD int _freeCount [000202] ------------ | \--* LCL_VAR ref V00 this [000204] ------------ \--* CNS_INT int 1 [ 0] 577 (0x241) br.s impImportBlockPending for BB46 Importing BB32 (PC=382) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 382 (0x17e) ldloc.0 [ 1] 383 (0x17f) ldloc.s 5 [ 2] 385 (0x181) ldelema 1B000429 [ 1] 390 (0x186) ldfld 0A000C28 [ 1] 395 (0x18b) ldloc.2 [ 2] 396 (0x18c) bne.un.s STMT00039 (IL 0x17E... ???) [000215] ---XG------- * JTRUE void [000214] N--XG----U-- \--* NE int [000212] ---XG------- +--* FIELD int hashCode [000211] ---XG------- | \--* ADDR byref [000210] ---XG--N---- | \--* INDEX struct [000208] ------------ | +--* LCL_VAR ref V04 loc0 [000209] ------------ | \--* LCL_VAR int V09 loc5 [000213] ------------ \--* LCL_VAR int V06 loc2 impImportBlockPending for BB33 impImportBlockPending for BB39 Importing BB39 (PC=452) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 452 (0x1c4) ldloc.0 [ 1] 453 (0x1c5) ldloc.s 5 [ 2] 455 (0x1c7) ldelema 1B000429 [ 1] 460 (0x1cc) ldfld 0A000C09 [ 1] 465 (0x1d1) stloc.s 5 STMT00040 (IL 0x1C4... ???) [000222] -A-XG------- * ASG int [000221] D------N---- +--* LCL_VAR int V09 loc5 [000220] ---XG------- \--* FIELD int next [000219] ---XG------- \--* ADDR byref [000218] ---XG--N---- \--* INDEX struct [000216] ------------ +--* LCL_VAR ref V04 loc0 [000217] ------------ \--* LCL_VAR int V09 loc5 [ 0] 467 (0x1d3) ldloc.3 [ 1] 468 (0x1d4) ldc.i4.1 1 [ 2] 469 (0x1d5) add [ 1] 470 (0x1d6) stloc.3 STMT00041 (IL 0x1D3... ???) [000227] -A---------- * ASG int [000226] D------N---- +--* LCL_VAR int V07 loc3 [000225] ------------ \--* ADD int [000223] ------------ +--* LCL_VAR int V07 loc3 [000224] ------------ \--* CNS_INT int 1 [ 0] 471 (0x1d7) ldloc.3 [ 1] 472 (0x1d8) ldloc.0 [ 2] 473 (0x1d9) ldlen [ 2] 474 (0x1da) conv.i4 [ 2] 475 (0x1db) ble.un.s STMT00042 (IL 0x1D7... ???) [000232] ---X-------- * JTRUE void [000231] N--X-----U-- \--* LE int [000228] ------------ +--* LCL_VAR int V07 loc3 [000230] ---X-------- \--* ARR_LENGTH int [000229] ------------ \--* LCL_VAR ref V04 loc0 impImportBlockPending for BB40 impImportBlockPending for BB31 Importing BB40 (PC=477) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 477 (0x1dd) call 0600195C In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 STMT00043 (IL 0x1DD... ???) [000233] I-C-G------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported (exactContextHnd=0x00000000D1FFAB1E) [ 0] 482 (0x1e2) br.s impImportBlockPending for BB31 Importing BB33 (PC=398) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 398 (0x18e) ldloc.1 [ 1] 399 (0x18f) ldloc.0 [ 2] 400 (0x190) ldloc.s 5 [ 3] 402 (0x192) ldelema 1B000429 [ 2] 407 (0x197) ldfld 0A000C0A [ 2] 412 (0x19c) ldarg.1 [ 3] 413 (0x19d) callvirt 0A000C2A In Compiler::impImportCall: opcode is callvirt, kind=2, callRetType is bool, structSize is 0 lvaGrabTemp returning 16 (V16 tmp2) called for impRuntimeLookup slot. lvaGrabTemp returning 17 (V17 tmp3) called for impAppendStmt. STMT00045 (IL 0x18E... ???) [000246] -A-XG------- * ASG ref [000245] D------N---- +--* LCL_VAR ref V17 tmp3 [000239] ---XG------- \--* FIELD ref key [000238] ---XG------- \--* ADDR byref [000237] ---XG--N---- \--* INDEX struct [000235] ------------ +--* LCL_VAR ref V04 loc0 [000236] ------------ \--* LCL_VAR int V09 loc5 Marked V17 as a single def temp Querying runtime about current class of field Entry[System.__Canon,System.__Canon].key (declared as System.__Canon) Field's current class not available lvaSetClass: setting class for V17 to (00000000D1FFAB1E) System.__Canon STMT00044 (IL 0x18E... ???) [000244] -A-X-------- * ASG long [000243] D------N---- +--* LCL_VAR long V16 tmp2 [000242] #--X-------- \--* IND long [000241] !----------- \--* LCL_VAR ref V00 this lvaGrabTemp returning 18 (V18 tmp4) called for bubbling QMark1. STMT00046 (IL ???... ???) [000257] -A---------- * ASG ref [000256] D------N---- +--* LCL_VAR ref V18 tmp4 [000240] ------------ \--* LCL_VAR ref V01 arg1 Marked V18 as a single def temp lvaSetClass: setting class for V18 to (00000000D1FFAB1E) System.__Canon lvaGrabTemp returning 19 (V19 tmp5) called for spilling Runtime Lookup tree. STMT00047 (IL ???... ???) [000275] -AC-G------- * ASG long [000274] D------N---- +--* LCL_VAR long V19 tmp5 [000273] --C-G------- \--* QMARK long [000263] Q----------- if +--* NE int [000259] n----------- | +--* IND long [000255] ------------ | | \--* ADD long [000253] #----------- | | +--* IND long [000252] #----------- | | | \--* IND long [000251] ------------ | | | \--* ADD long [000249] ------------ | | | +--* LCL_VAR long V16 tmp2 [000250] ------------ | | | \--* CNS_INT long 56 [000254] ------------ | | \--* CNS_INT long 48 [000262] ------------ | \--* CNS_INT long 0 [000272] --C-G------- if \--* COLON long [000261] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000248] ------------ arg0 | +--* LCL_VAR long V16 tmp2 [000260] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000264] n----------- then \--* IND long [000265] ------------ \--* ADD long [000266] #----------- +--* IND long [000267] #----------- | \--* IND long [000268] ------------ | \--* ADD long [000269] ------------ | +--* LCL_VAR long V16 tmp2 [000270] ------------ | \--* CNS_INT long 56 [000271] ------------ \--* CNS_INT long 48 lvaGrabTemp returning 20 (V20 tmp6) called for VirtualCall with runtime lookup. STMT00048 (IL ???... ???) [000278] -A---------- * ASG long [000277] D------N---- +--* LCL_VAR long V20 tmp6 [000276] ------------ \--* LCL_VAR long V19 tmp5 impDevirtualizeCall: Trying to devirtualize interface call: class for 'this' is System.Collections.Generic.IEqualityComparer`1[__Canon] (attrib 10220400) base method is System.Collections.Generic.IEqualityComparer`1[__Canon]::Equals Considering guarded devirtualization at IL offset 413 (0x19d) Not guessing for class: no class profile pgo data, or pgo disabled INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'n/a' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' [ 1] 418 (0x1a2) brfalse.s STMT00049 (IL ???... ???) [000283] --CXG------- * JTRUE void [000282] --CXG------- \--* EQ int [000280] --CXG------- +--* CALL ind stub int [000234] ------------ this in rcx | +--* LCL_VAR ref V05 loc1 [000247] ------------ arg1 | +--* LCL_VAR ref V17 tmp3 [000258] ------------ arg2 | +--* LCL_VAR ref V18 tmp4 [000279] ------------ calli tgt | \--* LCL_VAR long V20 tmp6 [000281] ------------ \--* CNS_INT int 0 impImportBlockPending for BB34 impImportBlockPending for BB39 Importing BB34 (PC=420) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 420 (0x1a4) ldarg.3 [ 1] 421 (0x1a5) ldc.i4.1 1 [ 2] 422 (0x1a6) bne.un.s STMT00050 (IL 0x1A4... ???) [000287] ------------ * JTRUE void [000286] N--------U-- \--* NE int [000284] ------------ +--* LCL_VAR ubyte V03 arg3 [000285] ------------ \--* CNS_INT int 1 impImportBlockPending for BB35 impImportBlockPending for BB36 Importing BB36 (PC=440) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 440 (0x1b8) ldarg.3 [ 1] 441 (0x1b9) ldc.i4.2 2 [ 2] 442 (0x1ba) bne.un.s STMT00051 (IL 0x1B8... ???) [000291] ------------ * JTRUE void [000290] N--------U-- \--* NE int [000288] ------------ +--* LCL_VAR ubyte V03 arg3 [000289] ------------ \--* CNS_INT int 2 impImportBlockPending for BB37 impImportBlockPending for BB38 Importing BB38 (PC=450) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 450 (0x1c2) ldc.i4.0 0 [ 1] 451 (0x1c3) ret STMT00052 (IL 0x1C2... ???) [000293] ------------ * RETURN int [000292] ------------ \--* CNS_INT int 0 Importing BB37 (PC=444) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 444 (0x1bc) ldarg.1 [ 1] 445 (0x1bd) call 2B000585 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 lvaGrabTemp returning 21 (V21 tmp7) called for impRuntimeLookup slot. STMT00053 (IL 0x1BC... ???) [000299] -A-X-------- * ASG long [000298] D------N---- +--* LCL_VAR long V21 tmp7 [000297] #--X-------- \--* IND long [000296] !----------- \--* LCL_VAR ref V00 this lvaGrabTemp returning 22 (V22 tmp8) called for bubbling QMark1. STMT00054 (IL ???... ???) [000309] -A---------- * ASG ref [000308] D------N---- +--* LCL_VAR ref V22 tmp8 [000294] ------------ \--* LCL_VAR ref V01 arg1 Marked V22 as a single def temp lvaSetClass: setting class for V22 to (00000000D1FFAB1E) System.__Canon lvaGrabTemp returning 23 (V23 tmp9) called for spilling Runtime Lookup tree. STMT00055 (IL ???... ???) [000327] -AC-G------- * ASG long [000326] D------N---- +--* LCL_VAR long V23 tmp9 [000325] --C-G------- \--* QMARK long [000315] Q----------- if +--* NE int [000311] n----------- | +--* IND long [000307] ------------ | | \--* ADD long [000305] #----------- | | +--* IND long [000304] #----------- | | | \--* IND long [000303] ------------ | | | \--* ADD long [000301] ------------ | | | +--* LCL_VAR long V21 tmp7 [000302] ------------ | | | \--* CNS_INT long 56 [000306] ------------ | | \--* CNS_INT long 56 [000314] ------------ | \--* CNS_INT long 0 [000324] --C-G------- if \--* COLON long [000313] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000300] ------------ arg0 | +--* LCL_VAR long V21 tmp7 [000312] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000316] n----------- then \--* IND long [000317] ------------ \--* ADD long [000318] #----------- +--* IND long [000319] #----------- | \--* IND long [000320] ------------ | \--* ADD long [000321] ------------ | +--* LCL_VAR long V21 tmp7 [000322] ------------ | \--* CNS_INT long 56 [000323] ------------ \--* CNS_INT long 56 STMT00056 (IL ???... ???) [000295] I-C-G------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException (exactContextHnd=0x00000000D1FFAB1E) [000329] ------------ arg0 +--* RUNTIMELOOKUP long 0xd1ffab1e method [000328] ------------ | \--* LCL_VAR long V23 tmp9 [000310] ------------ arg1 \--* LCL_VAR ref V22 tmp8 impImportBlockPending for BB38 Importing BB35 (PC=424) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 424 (0x1a8) ldloc.0 [ 1] 425 (0x1a9) ldloc.s 5 [ 2] 427 (0x1ab) ldelema 1B000429 [ 1] 432 (0x1b0) ldarg.2 [ 2] 433 (0x1b1) stfld 0A000C0B STMT00057 (IL 0x1A8... ???) [000336] -A-XG------- * ASG ref [000335] ---XG--N---- +--* FIELD ref value [000333] ---XG------- | \--* ADDR byref [000332] ---XG--N---- | \--* INDEX struct [000330] ------------ | +--* LCL_VAR ref V04 loc0 [000331] ------------ | \--* LCL_VAR int V09 loc5 [000334] ------------ \--* LCL_VAR ref V02 arg2 [ 0] 438 (0x1b6) ldc.i4.1 1 [ 1] 439 (0x1b7) ret STMT00058 (IL 0x1B6... ???) [000338] ------------ * RETURN int [000337] ------------ \--* CNS_INT int 1 Importing BB09 (PC=122) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 122 (0x07a) ldtoken [ 1] 127 (0x07f) call 060007D6 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 Named Intrinsic System.Type.GetTypeFromHandle: Recognized [ 1] 132 (0x084) call 0600081F In Compiler::impImportCall: opcode is call, kind=0, callRetType is bool, structSize is 0 Named Intrinsic System.Type.get_IsValueType: Recognized [ 1] 137 (0x089) brfalse.s Folding operator with constant nodes into a constant: [000351] ------------ * EQ int [000349] ------------ +--* CNS_INT int 0 [000350] ------------ \--* CNS_INT int 0 Bashed to int constant: [000351] ------------ * CNS_INT int 1 The conditional jump becomes an unconditional jump to BB20 impImportBlockPending for BB20 Importing BB20 (PC=255) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 255 (0x0ff) call 0A00048D In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 Named Intrinsic System.Collections.Generic.EqualityComparer`1.get_Default: Recognized lvaGrabTemp returning 24 (V24 tmp10) called for impRuntimeLookup slot. STMT00059 (IL 0x0FF... ???) [000356] -A-X-------- * ASG long [000355] D------N---- +--* LCL_VAR long V24 tmp10 [000354] #--X-------- \--* IND long [000353] !----------- \--* LCL_VAR ref V00 this lvaGrabTemp returning 25 (V25 tmp11) called for spilling Runtime Lookup tree. STMT00060 (IL ???... ???) [000381] -AC-G------- * ASG long [000380] D------N---- +--* LCL_VAR long V25 tmp11 [000379] --C-G------- \--* QMARK long [000369] Q----------- if +--* NE int [000365] n----------- | +--* IND long [000364] ------------ | | \--* ADD long [000362] #----------- | | +--* IND long [000361] #----------- | | | \--* IND long [000360] ------------ | | | \--* ADD long [000358] ------------ | | | +--* LCL_VAR long V24 tmp10 [000359] ------------ | | | \--* CNS_INT long 56 [000363] ------------ | | \--* CNS_INT long 32 [000368] ------------ | \--* CNS_INT long 0 [000378] --C-G------- if \--* COLON long [000367] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000357] ------------ arg0 | +--* LCL_VAR long V24 tmp10 [000366] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000370] n----------- then \--* IND long [000371] ------------ \--* ADD long [000372] #----------- +--* IND long [000373] #----------- | \--* IND long [000374] ------------ | \--* ADD long [000375] ------------ | +--* LCL_VAR long V24 tmp10 [000376] ------------ | \--* CNS_INT long 56 [000377] ------------ \--* CNS_INT long 32 STMT00061 (IL ???... ???) [000352] I-C-G------- * CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default (exactContextHnd=0x00000000D1FFAB1E) [000383] ------------ arg0 \--* RUNTIMELOOKUP long 0xd1ffab1e class [000382] ------------ \--* LCL_VAR long V25 tmp11 [ 1] 260 (0x104) stloc.s 8Named Intrinsic System.Collections.Generic.EqualityComparer`1.get_Default: Recognized Special intrinsic: looking for exact type returned by System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon]:get_Default():System.Collections.Generic.EqualityComparer`1[__Canon] Named Intrinsic System.Collections.Generic.EqualityComparer`1.get_Default: Recognized Special intrinsic for type System.__Canon: type not final, so deferring opt STMT00062 (IL ???... ???) [000386] -AC--------- * ASG ref [000385] D------N---- +--* LCL_VAR ref V12 loc8 [000384] --C--------- \--* RET_EXPR ref (inl return expr [000352]) impImportBlockPending for BB21 Importing BB21 (PC=262) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 262 (0x106) ldloc.s 5 [ 1] 264 (0x108) ldloc.0 [ 2] 265 (0x109) ldlen [ 2] 266 (0x10a) conv.i4 [ 2] 267 (0x10b) bge.un STMT00063 (IL 0x106... ???) [000391] ---X-------- * JTRUE void [000390] N--X-----U-- \--* GE int [000387] ------------ +--* LCL_VAR int V09 loc5 [000389] ---X-------- \--* ARR_LENGTH int [000388] ------------ \--* LCL_VAR ref V04 loc0 impImportBlockPending for BB22 impImportBlockPending for BB41 Importing BB22 (PC=272) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 272 (0x110) ldloc.0 [ 1] 273 (0x111) ldloc.s 5 [ 2] 275 (0x113) ldelema 1B000429 [ 1] 280 (0x118) ldfld 0A000C28 [ 1] 285 (0x11d) ldloc.2 [ 2] 286 (0x11e) bne.un.s STMT00064 (IL 0x110... ???) [000399] ---XG------- * JTRUE void [000398] N--XG----U-- \--* NE int [000396] ---XG------- +--* FIELD int hashCode [000395] ---XG------- | \--* ADDR byref [000394] ---XG--N---- | \--* INDEX struct [000392] ------------ | +--* LCL_VAR ref V04 loc0 [000393] ------------ | \--* LCL_VAR int V09 loc5 [000397] ------------ \--* LCL_VAR int V06 loc2 impImportBlockPending for BB23 impImportBlockPending for BB29 Importing BB29 (PC=343) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 343 (0x157) ldloc.0 [ 1] 344 (0x158) ldloc.s 5 [ 2] 346 (0x15a) ldelema 1B000429 [ 1] 351 (0x15f) ldfld 0A000C09 [ 1] 356 (0x164) stloc.s 5 STMT00065 (IL 0x157... ???) [000406] -A-XG------- * ASG int [000405] D------N---- +--* LCL_VAR int V09 loc5 [000404] ---XG------- \--* FIELD int next [000403] ---XG------- \--* ADDR byref [000402] ---XG--N---- \--* INDEX struct [000400] ------------ +--* LCL_VAR ref V04 loc0 [000401] ------------ \--* LCL_VAR int V09 loc5 [ 0] 358 (0x166) ldloc.3 [ 1] 359 (0x167) ldc.i4.1 1 [ 2] 360 (0x168) add [ 1] 361 (0x169) stloc.3 STMT00066 (IL 0x166... ???) [000411] -A---------- * ASG int [000410] D------N---- +--* LCL_VAR int V07 loc3 [000409] ------------ \--* ADD int [000407] ------------ +--* LCL_VAR int V07 loc3 [000408] ------------ \--* CNS_INT int 1 [ 0] 362 (0x16a) ldloc.3 [ 1] 363 (0x16b) ldloc.0 [ 2] 364 (0x16c) ldlen [ 2] 365 (0x16d) conv.i4 [ 2] 366 (0x16e) ble.un.s STMT00067 (IL 0x16A... ???) [000416] ---X-------- * JTRUE void [000415] N--X-----U-- \--* LE int [000412] ------------ +--* LCL_VAR int V07 loc3 [000414] ---X-------- \--* ARR_LENGTH int [000413] ------------ \--* LCL_VAR ref V04 loc0 impImportBlockPending for BB30 impImportBlockPending for BB21 Importing BB30 (PC=368) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 368 (0x170) call 0600195C In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 STMT00068 (IL 0x170... ???) [000417] I-C-G------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported (exactContextHnd=0x00000000D1FFAB1E) [ 0] 373 (0x175) br.s impImportBlockPending for BB21 Importing BB23 (PC=288) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 288 (0x120) ldloc.s 8 [ 1] 290 (0x122) ldloc.0 [ 2] 291 (0x123) ldloc.s 5 [ 3] 293 (0x125) ldelema 1B000429 [ 2] 298 (0x12a) ldfld 0A000C0A [ 2] 303 (0x12f) ldarg.1 [ 3] 304 (0x130) callvirt 0A00048E In Compiler::impImportCall: opcode is callvirt, kind=4, callRetType is bool, structSize is 0 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is System.Collections.Generic.EqualityComparer`1[__Canon] (attrib 20020400) base method is System.Collections.Generic.EqualityComparer`1[__Canon]::Equals devirt to System.Collections.Generic.EqualityComparer`1[__Canon]::Equals -- inexact or not final [000425] --CXG------- * CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals [000418] ------------ this in rcx +--* LCL_VAR ref V12 loc8 [000423] ---XG------- arg1 +--* FIELD ref key [000422] ---XG------- | \--* ADDR byref [000421] ---XG--N---- | \--* INDEX struct [000419] ------------ | +--* LCL_VAR ref V04 loc0 [000420] ------------ | \--* LCL_VAR int V09 loc5 [000424] ------------ arg2 \--* LCL_VAR ref V01 arg1 Class not final or exact, and method not final Considering guarded devirtualization at IL offset 304 (0x130) Not guessing for class: no class profile pgo data, or pgo disabled INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon]:Equals(System.__Canon,System.__Canon):bool:this' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' [ 1] 309 (0x135) brfalse.s STMT00069 (IL 0x120... ???) [000428] --CXG------- * JTRUE void [000427] --CXG------- \--* EQ int [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 [000423] ---XG------- arg1 | +--* FIELD ref key [000422] ---XG------- | | \--* ADDR byref [000421] ---XG--N---- | | \--* INDEX struct [000419] ------------ | | +--* LCL_VAR ref V04 loc0 [000420] ------------ | | \--* LCL_VAR int V09 loc5 [000424] ------------ arg2 | \--* LCL_VAR ref V01 arg1 [000426] ------------ \--* CNS_INT int 0 impImportBlockPending for BB24 impImportBlockPending for BB29 Importing BB24 (PC=311) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 311 (0x137) ldarg.3 [ 1] 312 (0x138) ldc.i4.1 1 [ 2] 313 (0x139) bne.un.s STMT00070 (IL 0x137... ???) [000432] ------------ * JTRUE void [000431] N--------U-- \--* NE int [000429] ------------ +--* LCL_VAR ubyte V03 arg3 [000430] ------------ \--* CNS_INT int 1 impImportBlockPending for BB25 impImportBlockPending for BB26 Importing BB26 (PC=331) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 331 (0x14b) ldarg.3 [ 1] 332 (0x14c) ldc.i4.2 2 [ 2] 333 (0x14d) bne.un.s STMT00071 (IL 0x14B... ???) [000436] ------------ * JTRUE void [000435] N--------U-- \--* NE int [000433] ------------ +--* LCL_VAR ubyte V03 arg3 [000434] ------------ \--* CNS_INT int 2 impImportBlockPending for BB27 impImportBlockPending for BB28 Importing BB28 (PC=341) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 341 (0x155) ldc.i4.0 0 [ 1] 342 (0x156) ret STMT00072 (IL 0x155... ???) [000438] ------------ * RETURN int [000437] ------------ \--* CNS_INT int 0 Importing BB27 (PC=335) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 335 (0x14f) ldarg.1 [ 1] 336 (0x150) call 2B000585 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 lvaGrabTemp returning 26 (V26 tmp12) called for impRuntimeLookup slot. STMT00073 (IL 0x14F... ???) [000444] -A-X-------- * ASG long [000443] D------N---- +--* LCL_VAR long V26 tmp12 [000442] #--X-------- \--* IND long [000441] !----------- \--* LCL_VAR ref V00 this lvaGrabTemp returning 27 (V27 tmp13) called for bubbling QMark1. STMT00074 (IL ???... ???) [000454] -A---------- * ASG ref [000453] D------N---- +--* LCL_VAR ref V27 tmp13 [000439] ------------ \--* LCL_VAR ref V01 arg1 Marked V27 as a single def temp lvaSetClass: setting class for V27 to (00000000D1FFAB1E) System.__Canon lvaGrabTemp returning 28 (V28 tmp14) called for spilling Runtime Lookup tree. STMT00075 (IL ???... ???) [000472] -AC-G------- * ASG long [000471] D------N---- +--* LCL_VAR long V28 tmp14 [000470] --C-G------- \--* QMARK long [000460] Q----------- if +--* NE int [000456] n----------- | +--* IND long [000452] ------------ | | \--* ADD long [000450] #----------- | | +--* IND long [000449] #----------- | | | \--* IND long [000448] ------------ | | | \--* ADD long [000446] ------------ | | | +--* LCL_VAR long V26 tmp12 [000447] ------------ | | | \--* CNS_INT long 56 [000451] ------------ | | \--* CNS_INT long 56 [000459] ------------ | \--* CNS_INT long 0 [000469] --C-G------- if \--* COLON long [000458] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000445] ------------ arg0 | +--* LCL_VAR long V26 tmp12 [000457] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000461] n----------- then \--* IND long [000462] ------------ \--* ADD long [000463] #----------- +--* IND long [000464] #----------- | \--* IND long [000465] ------------ | \--* ADD long [000466] ------------ | +--* LCL_VAR long V26 tmp12 [000467] ------------ | \--* CNS_INT long 56 [000468] ------------ \--* CNS_INT long 56 STMT00076 (IL ???... ???) [000440] I-C-G------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException (exactContextHnd=0x00000000D1FFAB1E) [000474] ------------ arg0 +--* RUNTIMELOOKUP long 0xd1ffab1e method [000473] ------------ | \--* LCL_VAR long V28 tmp14 [000455] ------------ arg1 \--* LCL_VAR ref V27 tmp13 impImportBlockPending for BB28 Importing BB25 (PC=315) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 315 (0x13b) ldloc.0 [ 1] 316 (0x13c) ldloc.s 5 [ 2] 318 (0x13e) ldelema 1B000429 [ 1] 323 (0x143) ldarg.2 [ 2] 324 (0x144) stfld 0A000C0B STMT00077 (IL 0x13B... ???) [000481] -A-XG------- * ASG ref [000480] ---XG--N---- +--* FIELD ref value [000478] ---XG------- | \--* ADDR byref [000477] ---XG--N---- | \--* INDEX struct [000475] ------------ | +--* LCL_VAR ref V04 loc0 [000476] ------------ | \--* LCL_VAR int V09 loc5 [000479] ------------ \--* LCL_VAR ref V02 arg2 [ 0] 329 (0x149) ldc.i4.1 1 [ 1] 330 (0x14a) ret STMT00078 (IL 0x149... ???) [000483] ------------ * RETURN int [000482] ------------ \--* CNS_INT int 1 Importing BB06 (PC=075) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 75 (0x04b) ldloc.1 [ 1] 76 (0x04c) ldarg.1 [ 2] 77 (0x04d) callvirt 0A000C29 In Compiler::impImportCall: opcode is callvirt, kind=2, callRetType is int, structSize is 0 lvaGrabTemp returning 29 (V29 tmp15) called for impRuntimeLookup slot. STMT00079 (IL 0x04B... ???) [000489] -A-X-------- * ASG long [000488] D------N---- +--* LCL_VAR long V29 tmp15 [000487] #--X-------- \--* IND long [000486] !----------- \--* LCL_VAR ref V00 this lvaGrabTemp returning 30 (V30 tmp16) called for bubbling QMark1. STMT00080 (IL ???... ???) [000499] -A---------- * ASG ref [000498] D------N---- +--* LCL_VAR ref V30 tmp16 [000485] ------------ \--* LCL_VAR ref V01 arg1 Marked V30 as a single def temp lvaSetClass: setting class for V30 to (00000000D1FFAB1E) System.__Canon lvaGrabTemp returning 31 (V31 tmp17) called for spilling Runtime Lookup tree. STMT00081 (IL ???... ???) [000517] -AC-G------- * ASG long [000516] D------N---- +--* LCL_VAR long V31 tmp17 [000515] --C-G------- \--* QMARK long [000505] Q----------- if +--* NE int [000501] n----------- | +--* IND long [000497] ------------ | | \--* ADD long [000495] #----------- | | +--* IND long [000494] #----------- | | | \--* IND long [000493] ------------ | | | \--* ADD long [000491] ------------ | | | +--* LCL_VAR long V29 tmp15 [000492] ------------ | | | \--* CNS_INT long 56 [000496] ------------ | | \--* CNS_INT long 64 [000504] ------------ | \--* CNS_INT long 0 [000514] --C-G------- if \--* COLON long [000503] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000490] ------------ arg0 | +--* LCL_VAR long V29 tmp15 [000502] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000506] n----------- then \--* IND long [000507] ------------ \--* ADD long [000508] #----------- +--* IND long [000509] #----------- | \--* IND long [000510] ------------ | \--* ADD long [000511] ------------ | +--* LCL_VAR long V29 tmp15 [000512] ------------ | \--* CNS_INT long 56 [000513] ------------ \--* CNS_INT long 64 lvaGrabTemp returning 32 (V32 tmp18) called for VirtualCall with runtime lookup. STMT00082 (IL ???... ???) [000520] -A---------- * ASG long [000519] D------N---- +--* LCL_VAR long V32 tmp18 [000518] ------------ \--* LCL_VAR long V31 tmp17 impDevirtualizeCall: Trying to devirtualize interface call: class for 'this' is System.Collections.Generic.IEqualityComparer`1[__Canon] (attrib 10220400) base method is System.Collections.Generic.IEqualityComparer`1[__Canon]::GetHashCode Considering guarded devirtualization at IL offset 77 (0x4d) Not guessing for class: no class profile pgo data, or pgo disabled INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'n/a' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' [ 1] 82 (0x052) br.s Spilling stack entries into temps STMT00083 (IL ???... ???) [000524] -ACXG------- * ASG int [000523] D------N---- +--* LCL_VAR int V15 tmp1 [000522] --CXG------- \--* CALL ind stub int [000484] ------------ this in rcx +--* LCL_VAR ref V05 loc1 [000500] ------------ arg1 +--* LCL_VAR ref V30 tmp16 [000521] ------------ calli tgt \--* LCL_VAR long V32 tmp18 impImportBlockPending for BB08 Importing BB04 (PC=022) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 22 (0x016) ldarg.0 [ 1] 23 (0x017) ldc.i4.0 0 [ 2] 24 (0x018) call 0A000BFF In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 STMT00084 (IL 0x016... ???) [000528] I-C-G------- * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize (exactContextHnd=0x00000000D1FFAB1E) [000526] ------------ this in rcx +--* LCL_VAR ref V00 this [000527] ------------ arg1 \--* CNS_INT int 0 [ 1] 29 (0x01d) pop STMT00085 (IL ???... ???) [000531] --C--------- * COMMA void [000529] --C--------- +--* RET_EXPR int (inl return expr [000528]) [000530] ------------ \--* NOP void impImportBlockPending for BB05 Importing BB02 (PC=008) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' [ 0] 8 (0x008) ldc.i4.4 4 [ 1] 9 (0x009) call 0600193F In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 STMT00086 (IL 0x008... ???) [000533] I-C-G------- * CALL void System.ThrowHelper.ThrowArgumentNullException (exactContextHnd=0x00000000D1FFAB1E) [000532] ------------ arg0 \--* CNS_INT int 4 impImportBlockPending for BB03 ** Note: root method IL was partially imported -- imported 606 of 739 bytes of method IL *************** Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 1 [008..00E) i BB03 [0002] 2 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 1 [016..01E) i BB05 [0004] 2 1 [01E..04B)-> BB07 ( cond ) i BB06 [0005] 1 1 [04B..054)-> BB08 (always) i BB07 [0006] 1 1 [054..061) i BB08 [0007] 2 1 [061..07A)-> BB31 ( cond ) i BB09 [0008] 1 1 [07A..08B)-> BB20 (always) i BB10 [0009] 3 1 [08B..095)-> BB41 ( cond ) bwd bwd-target BB11 [0010] 1 1 [095..0A5)-> BB18 ( cond ) bwd BB12 [0011] 1 1 [0A5..0BF)-> BB18 ( cond ) bwd BB13 [0012] 1 1 [0BF..0C3)-> BB15 ( cond ) bwd BB14 [0013] 1 1 [0C3..0D3) (return) BB15 [0014] 1 1 [0D3..0D7)-> BB17 ( cond ) bwd BB16 [0015] 1 1 [0D7..0DD) bwd BB17 [0016] 2 1 [0DD..0DF) (return) BB18 [0017] 2 1 [0DF..0F8)-> BB10 ( cond ) bwd BB19 [0018] 1 1 [0F8..0FF)-> BB10 (always) bwd BB20 [0019] 1 1 [0FF..106) i BB21 [0020] 3 1 [106..110)-> BB41 ( cond ) i idxlen bwd bwd-target BB22 [0021] 1 1 [110..120)-> BB29 ( cond ) i idxlen bwd BB23 [0022] 1 1 [120..137)-> BB29 ( cond ) i idxlen bwd BB24 [0023] 1 1 [137..13B)-> BB26 ( cond ) i bwd BB25 [0024] 1 1 [13B..14B) (return) i idxlen BB26 [0025] 1 1 [14B..14F)-> BB28 ( cond ) i bwd BB27 [0026] 1 1 [14F..155) i bwd BB28 [0027] 2 1 [155..157) (return) i BB29 [0028] 2 1 [157..170)-> BB21 ( cond ) i idxlen bwd BB30 [0029] 1 1 [170..177)-> BB21 (always) i bwd BB31 [0030] 3 1 [177..17E)-> BB41 ( cond ) i idxlen bwd bwd-target BB32 [0031] 1 1 [17E..18E)-> BB39 ( cond ) i idxlen bwd BB33 [0032] 1 1 [18E..1A4)-> BB39 ( cond ) i idxlen bwd BB34 [0033] 1 1 [1A4..1A8)-> BB36 ( cond ) i bwd BB35 [0034] 1 1 [1A8..1B8) (return) i idxlen BB36 [0035] 1 1 [1B8..1BC)-> BB38 ( cond ) i bwd BB37 [0036] 1 1 [1BC..1C2) i bwd BB38 [0037] 2 1 [1C2..1C4) (return) i BB39 [0038] 2 1 [1C4..1DD)-> BB31 ( cond ) i idxlen bwd BB40 [0039] 1 1 [1DD..1E4)-> BB31 (always) i bwd BB41 [0040] 3 1 [1E4..1ED)-> BB43 ( cond ) i BB42 [0041] 1 1 [1ED..243)-> BB46 (always) i BB43 [0042] 1 1 [243..252)-> BB45 ( cond ) i idxlen BB44 [0043] 1 1 [252..261) i BB45 [0044] 2 1 [261..276) i BB46 [0045] 2 1 [276..2CA) i idxlen BB47 [0046] 1 1 [2CA..2CF)-> BB50 ( cond ) i BB48 [0047] 1 1 [2CF..2D7)-> BB50 ( cond ) i BB49 [0048] 1 1 [2D7..2E1) i idxlen BB50 [0049] 4 1 [2E1..2E3) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 (IL 0x000...0x006) [000003] ------------ * JTRUE void [000002] ------------ \--* NE int [000000] ------------ +--* LCL_VAR ref V01 arg1 [000001] ------------ \--* CNS_INT ref null ------------ BB02 [008..00E), preds={} succs={BB03} ***** BB02 STMT00086 (IL 0x008...0x009) [000533] I-C-G------- * CALL void System.ThrowHelper.ThrowArgumentNullException (exactContextHnd=0x00000000D1FFAB1E) [000532] ------------ arg0 \--* CNS_INT int 4 ------------ BB03 [00E..016) -> BB05 (cond), preds={} succs={BB04,BB05} ***** BB03 STMT00001 (IL 0x00E...0x014) [000008] ---XG------- * JTRUE void [000007] ---XG------- \--* NE int [000005] ---XG------- +--* FIELD ref _buckets [000004] ------------ | \--* LCL_VAR ref V00 this [000006] ------------ \--* CNS_INT ref null ------------ BB04 [016..01E), preds={} succs={BB05} ***** BB04 STMT00084 (IL 0x016...0x01D) [000528] I-C-G------- * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize (exactContextHnd=0x00000000D1FFAB1E) [000526] ------------ this in rcx +--* LCL_VAR ref V00 this [000527] ------------ arg1 \--* CNS_INT int 0 ***** BB04 STMT00085 (IL ???... ???) [000531] --C--------- * COMMA void [000529] --C--------- +--* RET_EXPR int (inl return expr [000528]) [000530] ------------ \--* NOP void ------------ BB05 [01E..04B) -> BB07 (cond), preds={} succs={BB06,BB07} ***** BB05 STMT00002 (IL 0x01E...0x032) [000013] I-CXG------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000014] ---XG------- arg0 \--* PUTARG_TYPE bool [000012] N--XG----U-- \--* GT int [000010] ---XG------- +--* FIELD ref _buckets [000009] ------------ | \--* LCL_VAR ref V00 this [000011] ------------ \--* CNS_INT ref null ***** BB05 STMT00003 (IL 0x02C... ???) [000018] -A-XG------- * ASG ref [000017] D------N---- +--* LCL_VAR ref V04 loc0 [000016] ---XG------- \--* FIELD ref _entries [000015] ------------ \--* LCL_VAR ref V00 this ***** BB05 STMT00004 (IL 0x033...0x047) [000023] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000024] ------------ arg0 +--* PUTARG_TYPE bool [000021] N--------U-- | \--* GT int [000019] ------------ | +--* LCL_VAR ref V04 loc0 [000020] ------------ | \--* CNS_INT ref null [000022] ------------ arg1 \--* CNS_STR ref ***** BB05 STMT00005 (IL 0x041... ???) [000028] -A-XG------- * ASG ref [000027] D------N---- +--* LCL_VAR ref V05 loc1 [000026] ---XG------- \--* FIELD ref _comparer [000025] ------------ \--* LCL_VAR ref V00 this ***** BB05 STMT00006 (IL 0x048...0x049) [000032] ------------ * JTRUE void [000031] ------------ \--* EQ int [000029] ------------ +--* LCL_VAR ref V05 loc1 [000030] ------------ \--* CNS_INT ref null ------------ BB06 [04B..054) -> BB08 (always), preds={} succs={BB08} ***** BB06 STMT00079 (IL 0x04B...0x052) [000489] -A-X-------- * ASG long [000488] D------N---- +--* LCL_VAR long V29 tmp15 [000487] #--X-------- \--* IND long [000486] !----------- \--* LCL_VAR ref V00 this ***** BB06 STMT00080 (IL ???... ???) [000499] -A---------- * ASG ref [000498] D------N---- +--* LCL_VAR ref V30 tmp16 [000485] ------------ \--* LCL_VAR ref V01 arg1 ***** BB06 STMT00081 (IL ???... ???) [000517] -AC-G------- * ASG long [000516] D------N---- +--* LCL_VAR long V31 tmp17 [000515] --C-G------- \--* QMARK long [000505] Q----------- if +--* NE int [000501] n----------- | +--* IND long [000497] ------------ | | \--* ADD long [000495] #----------- | | +--* IND long [000494] #----------- | | | \--* IND long [000493] ------------ | | | \--* ADD long [000491] ------------ | | | +--* LCL_VAR long V29 tmp15 [000492] ------------ | | | \--* CNS_INT long 56 [000496] ------------ | | \--* CNS_INT long 64 [000504] ------------ | \--* CNS_INT long 0 [000514] --C-G------- if \--* COLON long [000503] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000490] ------------ arg0 | +--* LCL_VAR long V29 tmp15 [000502] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000506] n----------- then \--* IND long [000507] ------------ \--* ADD long [000508] #----------- +--* IND long [000509] #----------- | \--* IND long [000510] ------------ | \--* ADD long [000511] ------------ | +--* LCL_VAR long V29 tmp15 [000512] ------------ | \--* CNS_INT long 56 [000513] ------------ \--* CNS_INT long 64 ***** BB06 STMT00082 (IL ???... ???) [000520] -A---------- * ASG long [000519] D------N---- +--* LCL_VAR long V32 tmp18 [000518] ------------ \--* LCL_VAR long V31 tmp17 ***** BB06 STMT00083 (IL ???... ???) [000524] -ACXG------- * ASG int [000523] D------N---- +--* LCL_VAR int V15 tmp1 [000522] --CXG------- \--* CALL ind stub int [000484] ------------ this in rcx +--* LCL_VAR ref V05 loc1 [000500] ------------ arg1 +--* LCL_VAR ref V30 tmp16 [000521] ------------ calli tgt \--* LCL_VAR long V32 tmp18 ------------ BB07 [054..061), preds={} succs={BB08} ***** BB07 STMT00007 (IL 0x054...0x05C) [000038] -ACXG------- * ASG int [000037] D------N---- +--* LCL_VAR int V15 tmp1 [000035] --CXG------- \--* CALLV vt-ind int System.Object.GetHashCode [000036] *--XG------- this in rcx \--* IND ref [000034] ------------ \--* ADDR long [000033] -------N---- \--* LCL_VAR ref V01 arg1 ------------ BB08 [061..07A) -> BB31 (cond), preds={} succs={BB09,BB31} ***** BB08 STMT00008 (IL ???...0x061) [000042] -A---------- * ASG int [000041] D------N---- +--* LCL_VAR int V06 loc2 [000040] ------------ \--* LCL_VAR int V15 tmp1 ***** BB08 STMT00009 (IL 0x062...0x063) [000045] -A---------- * ASG int [000044] D------N---- +--* LCL_VAR int V07 loc3 [000043] ------------ \--* CNS_INT int 0 ***** BB08 STMT00010 (IL 0x064...0x06B) [000048] I-C-G------- * CALL byref System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].GetBucket (exactContextHnd=0x00000000D1FFAB1E) [000046] ------------ this in rcx +--* LCL_VAR ref V00 this [000047] ------------ arg1 \--* LCL_VAR int V06 loc2 ***** BB08 STMT00011 (IL ???... ???) [000051] -AC--------- * ASG byref [000050] D------N---- +--* LCL_VAR byref V08 loc4 [000049] --C--------- \--* RET_EXPR byref (inl return expr [000048]) ***** BB08 STMT00012 (IL 0x06D...0x072) [000057] -A-XG------- * ASG int [000056] D------N---- +--* LCL_VAR int V09 loc5 [000055] ---XG------- \--* SUB int [000053] *--XG------- +--* IND int [000052] ------------ | \--* LCL_VAR byref V08 loc4 [000054] ------------ \--* CNS_INT int 1 ***** BB08 STMT00013 (IL 0x074...0x075) [000061] ------------ * JTRUE void [000060] ------------ \--* NE int [000058] ------------ +--* LCL_VAR ref V05 loc1 [000059] ------------ \--* CNS_INT ref null ------------ BB09 [07A..08B) -> BB20 (always), preds={} succs={BB20} ------------ BB10 [08B..095) -> BB41 (cond), preds={} succs={BB11,BB41} ------------ BB11 [095..0A5) -> BB18 (cond), preds={} succs={BB12,BB18} ------------ BB12 [0A5..0BF) -> BB18 (cond), preds={} succs={BB13,BB18} ------------ BB13 [0BF..0C3) -> BB15 (cond), preds={} succs={BB14,BB15} ------------ BB14 [0C3..0D3) (return), preds={} succs={} ------------ BB15 [0D3..0D7) -> BB17 (cond), preds={} succs={BB16,BB17} ------------ BB16 [0D7..0DD), preds={} succs={BB17} ------------ BB17 [0DD..0DF) (return), preds={} succs={} ------------ BB18 [0DF..0F8) -> BB10 (cond), preds={} succs={BB19,BB10} ------------ BB19 [0F8..0FF) -> BB10 (always), preds={} succs={BB10} ------------ BB20 [0FF..106), preds={} succs={BB21} ***** BB20 STMT00059 (IL 0x0FF...0x104) [000356] -A-X-------- * ASG long [000355] D------N---- +--* LCL_VAR long V24 tmp10 [000354] #--X-------- \--* IND long [000353] !----------- \--* LCL_VAR ref V00 this ***** BB20 STMT00060 (IL ???... ???) [000381] -AC-G------- * ASG long [000380] D------N---- +--* LCL_VAR long V25 tmp11 [000379] --C-G------- \--* QMARK long [000369] Q----------- if +--* NE int [000365] n----------- | +--* IND long [000364] ------------ | | \--* ADD long [000362] #----------- | | +--* IND long [000361] #----------- | | | \--* IND long [000360] ------------ | | | \--* ADD long [000358] ------------ | | | +--* LCL_VAR long V24 tmp10 [000359] ------------ | | | \--* CNS_INT long 56 [000363] ------------ | | \--* CNS_INT long 32 [000368] ------------ | \--* CNS_INT long 0 [000378] --C-G------- if \--* COLON long [000367] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000357] ------------ arg0 | +--* LCL_VAR long V24 tmp10 [000366] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000370] n----------- then \--* IND long [000371] ------------ \--* ADD long [000372] #----------- +--* IND long [000373] #----------- | \--* IND long [000374] ------------ | \--* ADD long [000375] ------------ | +--* LCL_VAR long V24 tmp10 [000376] ------------ | \--* CNS_INT long 56 [000377] ------------ \--* CNS_INT long 32 ***** BB20 STMT00061 (IL ???... ???) [000352] I-C-G------- * CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default (exactContextHnd=0x00000000D1FFAB1E) [000383] ------------ arg0 \--* RUNTIMELOOKUP long 0xd1ffab1e class [000382] ------------ \--* LCL_VAR long V25 tmp11 ***** BB20 STMT00062 (IL ???... ???) [000386] -AC--------- * ASG ref [000385] D------N---- +--* LCL_VAR ref V12 loc8 [000384] --C--------- \--* RET_EXPR ref (inl return expr [000352]) ------------ BB21 [106..110) -> BB41 (cond), preds={} succs={BB22,BB41} ***** BB21 STMT00063 (IL 0x106...0x10B) [000391] ---X-------- * JTRUE void [000390] N--X-----U-- \--* GE int [000387] ------------ +--* LCL_VAR int V09 loc5 [000389] ---X-------- \--* ARR_LENGTH int [000388] ------------ \--* LCL_VAR ref V04 loc0 ------------ BB22 [110..120) -> BB29 (cond), preds={} succs={BB23,BB29} ***** BB22 STMT00064 (IL 0x110...0x11E) [000399] ---XG------- * JTRUE void [000398] N--XG----U-- \--* NE int [000396] ---XG------- +--* FIELD int hashCode [000395] ---XG------- | \--* ADDR byref [000394] ---XG--N---- | \--* INDEX struct [000392] ------------ | +--* LCL_VAR ref V04 loc0 [000393] ------------ | \--* LCL_VAR int V09 loc5 [000397] ------------ \--* LCL_VAR int V06 loc2 ------------ BB23 [120..137) -> BB29 (cond), preds={} succs={BB24,BB29} ***** BB23 STMT00069 (IL 0x120...0x135) [000428] --CXG------- * JTRUE void [000427] --CXG------- \--* EQ int [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 [000423] ---XG------- arg1 | +--* FIELD ref key [000422] ---XG------- | | \--* ADDR byref [000421] ---XG--N---- | | \--* INDEX struct [000419] ------------ | | +--* LCL_VAR ref V04 loc0 [000420] ------------ | | \--* LCL_VAR int V09 loc5 [000424] ------------ arg2 | \--* LCL_VAR ref V01 arg1 [000426] ------------ \--* CNS_INT int 0 ------------ BB24 [137..13B) -> BB26 (cond), preds={} succs={BB25,BB26} ***** BB24 STMT00070 (IL 0x137...0x139) [000432] ------------ * JTRUE void [000431] N--------U-- \--* NE int [000429] ------------ +--* LCL_VAR ubyte V03 arg3 [000430] ------------ \--* CNS_INT int 1 ------------ BB25 [13B..14B) (return), preds={} succs={} ***** BB25 STMT00077 (IL 0x13B...0x144) [000481] -A-XG------- * ASG ref [000480] ---XG--N---- +--* FIELD ref value [000478] ---XG------- | \--* ADDR byref [000477] ---XG--N---- | \--* INDEX struct [000475] ------------ | +--* LCL_VAR ref V04 loc0 [000476] ------------ | \--* LCL_VAR int V09 loc5 [000479] ------------ \--* LCL_VAR ref V02 arg2 ***** BB25 STMT00078 (IL 0x149...0x14A) [000483] ------------ * RETURN int [000482] ------------ \--* CNS_INT int 1 ------------ BB26 [14B..14F) -> BB28 (cond), preds={} succs={BB27,BB28} ***** BB26 STMT00071 (IL 0x14B...0x14D) [000436] ------------ * JTRUE void [000435] N--------U-- \--* NE int [000433] ------------ +--* LCL_VAR ubyte V03 arg3 [000434] ------------ \--* CNS_INT int 2 ------------ BB27 [14F..155), preds={} succs={BB28} ***** BB27 STMT00073 (IL 0x14F...0x150) [000444] -A-X-------- * ASG long [000443] D------N---- +--* LCL_VAR long V26 tmp12 [000442] #--X-------- \--* IND long [000441] !----------- \--* LCL_VAR ref V00 this ***** BB27 STMT00074 (IL ???... ???) [000454] -A---------- * ASG ref [000453] D------N---- +--* LCL_VAR ref V27 tmp13 [000439] ------------ \--* LCL_VAR ref V01 arg1 ***** BB27 STMT00075 (IL ???... ???) [000472] -AC-G------- * ASG long [000471] D------N---- +--* LCL_VAR long V28 tmp14 [000470] --C-G------- \--* QMARK long [000460] Q----------- if +--* NE int [000456] n----------- | +--* IND long [000452] ------------ | | \--* ADD long [000450] #----------- | | +--* IND long [000449] #----------- | | | \--* IND long [000448] ------------ | | | \--* ADD long [000446] ------------ | | | +--* LCL_VAR long V26 tmp12 [000447] ------------ | | | \--* CNS_INT long 56 [000451] ------------ | | \--* CNS_INT long 56 [000459] ------------ | \--* CNS_INT long 0 [000469] --C-G------- if \--* COLON long [000458] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000445] ------------ arg0 | +--* LCL_VAR long V26 tmp12 [000457] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000461] n----------- then \--* IND long [000462] ------------ \--* ADD long [000463] #----------- +--* IND long [000464] #----------- | \--* IND long [000465] ------------ | \--* ADD long [000466] ------------ | +--* LCL_VAR long V26 tmp12 [000467] ------------ | \--* CNS_INT long 56 [000468] ------------ \--* CNS_INT long 56 ***** BB27 STMT00076 (IL ???... ???) [000440] I-C-G------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException (exactContextHnd=0x00000000D1FFAB1E) [000474] ------------ arg0 +--* RUNTIMELOOKUP long 0xd1ffab1e method [000473] ------------ | \--* LCL_VAR long V28 tmp14 [000455] ------------ arg1 \--* LCL_VAR ref V27 tmp13 ------------ BB28 [155..157) (return), preds={} succs={} ***** BB28 STMT00072 (IL 0x155...0x156) [000438] ------------ * RETURN int [000437] ------------ \--* CNS_INT int 0 ------------ BB29 [157..170) -> BB21 (cond), preds={} succs={BB30,BB21} ***** BB29 STMT00065 (IL 0x157...0x164) [000406] -A-XG------- * ASG int [000405] D------N---- +--* LCL_VAR int V09 loc5 [000404] ---XG------- \--* FIELD int next [000403] ---XG------- \--* ADDR byref [000402] ---XG--N---- \--* INDEX struct [000400] ------------ +--* LCL_VAR ref V04 loc0 [000401] ------------ \--* LCL_VAR int V09 loc5 ***** BB29 STMT00066 (IL 0x166...0x169) [000411] -A---------- * ASG int [000410] D------N---- +--* LCL_VAR int V07 loc3 [000409] ------------ \--* ADD int [000407] ------------ +--* LCL_VAR int V07 loc3 [000408] ------------ \--* CNS_INT int 1 ***** BB29 STMT00067 (IL 0x16A...0x16E) [000416] ---X-------- * JTRUE void [000415] N--X-----U-- \--* LE int [000412] ------------ +--* LCL_VAR int V07 loc3 [000414] ---X-------- \--* ARR_LENGTH int [000413] ------------ \--* LCL_VAR ref V04 loc0 ------------ BB30 [170..177) -> BB21 (always), preds={} succs={BB21} ***** BB30 STMT00068 (IL 0x170...0x175) [000417] I-C-G------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported (exactContextHnd=0x00000000D1FFAB1E) ------------ BB31 [177..17E) -> BB41 (cond), preds={} succs={BB32,BB41} ***** BB31 STMT00014 (IL 0x177...0x17C) [000066] ---X-------- * JTRUE void [000065] N--X-----U-- \--* GE int [000062] ------------ +--* LCL_VAR int V09 loc5 [000064] ---X-------- \--* ARR_LENGTH int [000063] ------------ \--* LCL_VAR ref V04 loc0 ------------ BB32 [17E..18E) -> BB39 (cond), preds={} succs={BB33,BB39} ***** BB32 STMT00039 (IL 0x17E...0x18C) [000215] ---XG------- * JTRUE void [000214] N--XG----U-- \--* NE int [000212] ---XG------- +--* FIELD int hashCode [000211] ---XG------- | \--* ADDR byref [000210] ---XG--N---- | \--* INDEX struct [000208] ------------ | +--* LCL_VAR ref V04 loc0 [000209] ------------ | \--* LCL_VAR int V09 loc5 [000213] ------------ \--* LCL_VAR int V06 loc2 ------------ BB33 [18E..1A4) -> BB39 (cond), preds={} succs={BB34,BB39} ***** BB33 STMT00045 (IL 0x18E...0x1A2) [000246] -A-XG------- * ASG ref [000245] D------N---- +--* LCL_VAR ref V17 tmp3 [000239] ---XG------- \--* FIELD ref key [000238] ---XG------- \--* ADDR byref [000237] ---XG--N---- \--* INDEX struct [000235] ------------ +--* LCL_VAR ref V04 loc0 [000236] ------------ \--* LCL_VAR int V09 loc5 ***** BB33 STMT00044 (IL 0x18E... ???) [000244] -A-X-------- * ASG long [000243] D------N---- +--* LCL_VAR long V16 tmp2 [000242] #--X-------- \--* IND long [000241] !----------- \--* LCL_VAR ref V00 this ***** BB33 STMT00046 (IL ???... ???) [000257] -A---------- * ASG ref [000256] D------N---- +--* LCL_VAR ref V18 tmp4 [000240] ------------ \--* LCL_VAR ref V01 arg1 ***** BB33 STMT00047 (IL ???... ???) [000275] -AC-G------- * ASG long [000274] D------N---- +--* LCL_VAR long V19 tmp5 [000273] --C-G------- \--* QMARK long [000263] Q----------- if +--* NE int [000259] n----------- | +--* IND long [000255] ------------ | | \--* ADD long [000253] #----------- | | +--* IND long [000252] #----------- | | | \--* IND long [000251] ------------ | | | \--* ADD long [000249] ------------ | | | +--* LCL_VAR long V16 tmp2 [000250] ------------ | | | \--* CNS_INT long 56 [000254] ------------ | | \--* CNS_INT long 48 [000262] ------------ | \--* CNS_INT long 0 [000272] --C-G------- if \--* COLON long [000261] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000248] ------------ arg0 | +--* LCL_VAR long V16 tmp2 [000260] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000264] n----------- then \--* IND long [000265] ------------ \--* ADD long [000266] #----------- +--* IND long [000267] #----------- | \--* IND long [000268] ------------ | \--* ADD long [000269] ------------ | +--* LCL_VAR long V16 tmp2 [000270] ------------ | \--* CNS_INT long 56 [000271] ------------ \--* CNS_INT long 48 ***** BB33 STMT00048 (IL ???... ???) [000278] -A---------- * ASG long [000277] D------N---- +--* LCL_VAR long V20 tmp6 [000276] ------------ \--* LCL_VAR long V19 tmp5 ***** BB33 STMT00049 (IL ???... ???) [000283] --CXG------- * JTRUE void [000282] --CXG------- \--* EQ int [000280] --CXG------- +--* CALL ind stub int [000234] ------------ this in rcx | +--* LCL_VAR ref V05 loc1 [000247] ------------ arg1 | +--* LCL_VAR ref V17 tmp3 [000258] ------------ arg2 | +--* LCL_VAR ref V18 tmp4 [000279] ------------ calli tgt | \--* LCL_VAR long V20 tmp6 [000281] ------------ \--* CNS_INT int 0 ------------ BB34 [1A4..1A8) -> BB36 (cond), preds={} succs={BB35,BB36} ***** BB34 STMT00050 (IL 0x1A4...0x1A6) [000287] ------------ * JTRUE void [000286] N--------U-- \--* NE int [000284] ------------ +--* LCL_VAR ubyte V03 arg3 [000285] ------------ \--* CNS_INT int 1 ------------ BB35 [1A8..1B8) (return), preds={} succs={} ***** BB35 STMT00057 (IL 0x1A8...0x1B1) [000336] -A-XG------- * ASG ref [000335] ---XG--N---- +--* FIELD ref value [000333] ---XG------- | \--* ADDR byref [000332] ---XG--N---- | \--* INDEX struct [000330] ------------ | +--* LCL_VAR ref V04 loc0 [000331] ------------ | \--* LCL_VAR int V09 loc5 [000334] ------------ \--* LCL_VAR ref V02 arg2 ***** BB35 STMT00058 (IL 0x1B6...0x1B7) [000338] ------------ * RETURN int [000337] ------------ \--* CNS_INT int 1 ------------ BB36 [1B8..1BC) -> BB38 (cond), preds={} succs={BB37,BB38} ***** BB36 STMT00051 (IL 0x1B8...0x1BA) [000291] ------------ * JTRUE void [000290] N--------U-- \--* NE int [000288] ------------ +--* LCL_VAR ubyte V03 arg3 [000289] ------------ \--* CNS_INT int 2 ------------ BB37 [1BC..1C2), preds={} succs={BB38} ***** BB37 STMT00053 (IL 0x1BC...0x1BD) [000299] -A-X-------- * ASG long [000298] D------N---- +--* LCL_VAR long V21 tmp7 [000297] #--X-------- \--* IND long [000296] !----------- \--* LCL_VAR ref V00 this ***** BB37 STMT00054 (IL ???... ???) [000309] -A---------- * ASG ref [000308] D------N---- +--* LCL_VAR ref V22 tmp8 [000294] ------------ \--* LCL_VAR ref V01 arg1 ***** BB37 STMT00055 (IL ???... ???) [000327] -AC-G------- * ASG long [000326] D------N---- +--* LCL_VAR long V23 tmp9 [000325] --C-G------- \--* QMARK long [000315] Q----------- if +--* NE int [000311] n----------- | +--* IND long [000307] ------------ | | \--* ADD long [000305] #----------- | | +--* IND long [000304] #----------- | | | \--* IND long [000303] ------------ | | | \--* ADD long [000301] ------------ | | | +--* LCL_VAR long V21 tmp7 [000302] ------------ | | | \--* CNS_INT long 56 [000306] ------------ | | \--* CNS_INT long 56 [000314] ------------ | \--* CNS_INT long 0 [000324] --C-G------- if \--* COLON long [000313] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000300] ------------ arg0 | +--* LCL_VAR long V21 tmp7 [000312] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000316] n----------- then \--* IND long [000317] ------------ \--* ADD long [000318] #----------- +--* IND long [000319] #----------- | \--* IND long [000320] ------------ | \--* ADD long [000321] ------------ | +--* LCL_VAR long V21 tmp7 [000322] ------------ | \--* CNS_INT long 56 [000323] ------------ \--* CNS_INT long 56 ***** BB37 STMT00056 (IL ???... ???) [000295] I-C-G------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException (exactContextHnd=0x00000000D1FFAB1E) [000329] ------------ arg0 +--* RUNTIMELOOKUP long 0xd1ffab1e method [000328] ------------ | \--* LCL_VAR long V23 tmp9 [000310] ------------ arg1 \--* LCL_VAR ref V22 tmp8 ------------ BB38 [1C2..1C4) (return), preds={} succs={} ***** BB38 STMT00052 (IL 0x1C2...0x1C3) [000293] ------------ * RETURN int [000292] ------------ \--* CNS_INT int 0 ------------ BB39 [1C4..1DD) -> BB31 (cond), preds={} succs={BB40,BB31} ***** BB39 STMT00040 (IL 0x1C4...0x1D1) [000222] -A-XG------- * ASG int [000221] D------N---- +--* LCL_VAR int V09 loc5 [000220] ---XG------- \--* FIELD int next [000219] ---XG------- \--* ADDR byref [000218] ---XG--N---- \--* INDEX struct [000216] ------------ +--* LCL_VAR ref V04 loc0 [000217] ------------ \--* LCL_VAR int V09 loc5 ***** BB39 STMT00041 (IL 0x1D3...0x1D6) [000227] -A---------- * ASG int [000226] D------N---- +--* LCL_VAR int V07 loc3 [000225] ------------ \--* ADD int [000223] ------------ +--* LCL_VAR int V07 loc3 [000224] ------------ \--* CNS_INT int 1 ***** BB39 STMT00042 (IL 0x1D7...0x1DB) [000232] ---X-------- * JTRUE void [000231] N--X-----U-- \--* LE int [000228] ------------ +--* LCL_VAR int V07 loc3 [000230] ---X-------- \--* ARR_LENGTH int [000229] ------------ \--* LCL_VAR ref V04 loc0 ------------ BB40 [1DD..1E4) -> BB31 (always), preds={} succs={BB31} ***** BB40 STMT00043 (IL 0x1DD...0x1E2) [000233] I-C-G------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported (exactContextHnd=0x00000000D1FFAB1E) ------------ BB41 [1E4..1ED) -> BB43 (cond), preds={} succs={BB42,BB43} ***** BB41 STMT00015 (IL 0x1E4...0x1EB) [000071] ---XG------- * JTRUE void [000070] ---XG------- \--* LE int [000068] ---XG------- +--* FIELD int _freeCount [000067] ------------ | \--* LCL_VAR ref V00 this [000069] ------------ \--* CNS_INT int 0 ------------ BB42 [1ED..243) -> BB46 (always), preds={} succs={BB46} ***** BB42 STMT00035 (IL 0x1ED...0x1F3) [000174] -A-XG------- * ASG int [000173] D------N---- +--* LCL_VAR int V10 loc6 [000172] ---XG------- \--* FIELD int _freeList [000171] ------------ \--* LCL_VAR ref V00 this ***** BB42 STMT00036 (IL 0x1F5...0x22E) [000188] I-CXG------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000189] ---XG------- arg0 +--* PUTARG_TYPE bool [000186] ---XG------- | \--* EQ int [000184] ---XG------- | +--* LT int [000182] ---XG------- | | +--* SUB int [000175] ------------ | | | +--* CNS_INT int -3 [000181] ---XG------- | | | \--* FIELD int next [000180] ---XG------- | | | \--* ADDR byref [000179] ---XG--N---- | | | \--* INDEX struct [000176] ------------ | | | +--* LCL_VAR ref V04 loc0 [000178] ---XG------- | | | \--* FIELD int _freeList [000177] ------------ | | | \--* LCL_VAR ref V00 this [000183] ------------ | | \--* CNS_INT int -1 [000185] ------------ | \--* CNS_INT int 0 [000187] ------------ arg1 \--* CNS_STR ref ***** BB42 STMT00037 (IL 0x219... ???) [000200] -A-XG------- * ASG int [000199] ---XG--N---- +--* FIELD int _freeList [000190] ------------ | \--* LCL_VAR ref V00 this [000198] ---XG------- \--* SUB int [000191] ------------ +--* CNS_INT int -3 [000197] ---XG------- \--* FIELD int next [000196] ---XG------- \--* ADDR byref [000195] ---XG--N---- \--* INDEX struct [000192] ------------ +--* LCL_VAR ref V04 loc0 [000194] ---XG------- \--* FIELD int _freeList [000193] ------------ \--* LCL_VAR ref V00 this ***** BB42 STMT00038 (IL 0x233...0x23C) [000207] -A-XG------- * ASG int [000206] ---XG--N---- +--* FIELD int _freeCount [000201] ------------ | \--* LCL_VAR ref V00 this [000205] ---XG------- \--* SUB int [000203] ---XG------- +--* FIELD int _freeCount [000202] ------------ | \--* LCL_VAR ref V00 this [000204] ------------ \--* CNS_INT int 1 ------------ BB43 [243..252) -> BB45 (cond), preds={} succs={BB44,BB45} ***** BB43 STMT00016 (IL 0x243...0x249) [000075] -A-XG------- * ASG int [000074] D------N---- +--* LCL_VAR int V13 loc9 [000073] ---XG------- \--* FIELD int _count [000072] ------------ \--* LCL_VAR ref V00 this ***** BB43 STMT00017 (IL 0x24B...0x250) [000080] ---X-------- * JTRUE void [000079] N--X-----U-- \--* NE int [000076] ------------ +--* LCL_VAR int V13 loc9 [000078] ---X-------- \--* ARR_LENGTH int [000077] ------------ \--* LCL_VAR ref V04 loc0 ------------ BB44 [252..261), preds={} succs={BB45} ***** BB44 STMT00032 (IL 0x252...0x25F) [000164] I-C-G------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize (exactContextHnd=0x00000000D1FFAB1E) [000163] ------------ this in rcx \--* LCL_VAR ref V00 this ***** BB44 STMT00033 (IL 0x258... ???) [000167] I-C-G------- * CALL byref System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].GetBucket (exactContextHnd=0x00000000D1FFAB1E) [000165] ------------ this in rcx +--* LCL_VAR ref V00 this [000166] ------------ arg1 \--* LCL_VAR int V06 loc2 ***** BB44 STMT00034 (IL ???... ???) [000170] -AC--------- * ASG byref [000169] D------N---- +--* LCL_VAR byref V08 loc4 [000168] --C--------- \--* RET_EXPR byref (inl return expr [000167]) ------------ BB45 [261..276), preds={} succs={BB46} ***** BB45 STMT00018 (IL 0x261...0x263) [000083] -A---------- * ASG int [000082] D------N---- +--* LCL_VAR int V10 loc6 [000081] ------------ \--* LCL_VAR int V13 loc9 ***** BB45 STMT00019 (IL 0x265...0x26A) [000089] -A-XG------- * ASG int [000088] ---XG--N---- +--* FIELD int _count [000084] ------------ | \--* LCL_VAR ref V00 this [000087] ------------ \--* ADD int [000085] ------------ +--* LCL_VAR int V13 loc9 [000086] ------------ \--* CNS_INT int 1 ***** BB45 STMT00020 (IL 0x26F...0x275) [000093] -A-XG------- * ASG ref [000092] D------N---- +--* LCL_VAR ref V04 loc0 [000091] ---XG------- \--* FIELD ref _entries [000090] ------------ \--* LCL_VAR ref V00 this ------------ BB46 [276..2CA), preds={} succs={BB47} ***** BB46 STMT00021 (IL 0x276...0x27E) [000099] -A-XG------- * ASG byref [000098] D------N---- +--* LCL_VAR byref V11 loc7 [000097] ---XG------- \--* ADDR byref [000096] ---XG--N---- \--* INDEX struct [000094] ------------ +--* LCL_VAR ref V04 loc0 [000095] ------------ \--* LCL_VAR int V10 loc6 ***** BB46 STMT00022 (IL 0x280...0x283) [000103] -A-XG------- * ASG int [000102] ---XG--N---- +--* FIELD int hashCode [000100] ------------ | \--* LCL_VAR byref V11 loc7 [000101] ------------ \--* LCL_VAR int V06 loc2 ***** BB46 STMT00023 (IL 0x288...0x28F) [000110] -A-XG------- * ASG int [000109] ---XG--N---- +--* FIELD int next [000104] ------------ | \--* LCL_VAR byref V11 loc7 [000108] ---XG------- \--* SUB int [000106] *--XG------- +--* IND int [000105] ------------ | \--* LCL_VAR byref V08 loc4 [000107] ------------ \--* CNS_INT int 1 ***** BB46 STMT00024 (IL 0x294...0x297) [000114] -A-XG------- * ASG ref [000113] ---XG--N---- +--* FIELD ref key [000111] ------------ | \--* LCL_VAR byref V11 loc7 [000112] ------------ \--* LCL_VAR ref V01 arg1 ***** BB46 STMT00025 (IL 0x29C...0x29F) [000118] -A-XG------- * ASG ref [000117] ---XG--N---- +--* FIELD ref value [000115] ------------ | \--* LCL_VAR byref V11 loc7 [000116] ------------ \--* LCL_VAR ref V02 arg2 ***** BB46 STMT00026 (IL 0x2A4...0x2AA) [000124] -A-XG------- * ASG int [000123] *------N---- +--* IND int [000119] ------------ | \--* LCL_VAR byref V08 loc4 [000122] ------------ \--* ADD int [000120] ------------ +--* LCL_VAR int V10 loc6 [000121] ------------ \--* CNS_INT int 1 ***** BB46 STMT00027 (IL 0x2AB...0x2B4) [000131] -A-XG------- * ASG int [000130] ---XG--N---- +--* FIELD int _version [000125] ------------ | \--* LCL_VAR ref V00 this [000129] ---XG------- \--* ADD int [000127] ---XG------- +--* FIELD int _version [000126] ------------ | \--* LCL_VAR ref V00 this [000128] ------------ \--* CNS_INT int 1 ------------ BB47 [2CA..2CF) -> BB50 (cond), preds={} succs={BB48,BB50} ***** BB47 STMT00028 (IL 0x2CA...0x2CD) [000148] ------------ * JTRUE void [000147] N--------U-- \--* LE int [000145] ------------ +--* LCL_VAR int V07 loc3 [000146] ------------ \--* CNS_INT int 100 ------------ BB48 [2CF..2D7) -> BB50 (cond), preds={} succs={BB49,BB50} ***** BB48 STMT00030 (IL 0x2CF...0x2D5) [000156] --C-G------- * JTRUE void [000155] --C-G------- \--* EQ int [000153] --C-G------- +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS [000152] H------N---- arg0 | +--* CNS_INT(h) long 0xd1ffab1e class [000151] ------------ arg1 | \--* LCL_VAR ref V05 loc1 [000154] ------------ \--* CNS_INT ref null ------------ BB49 [2D7..2E1), preds={} succs={BB50} ***** BB49 STMT00031 (IL 0x2D7...0x2DC) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [000157] ------------ this in rcx +--* LCL_VAR ref V00 this [000159] ---X-------- arg1 +--* ARR_LENGTH int [000158] ------------ | \--* LCL_VAR ref V04 loc0 [000162] ------------ arg2 \--* PUTARG_TYPE bool [000160] ------------ \--* CNS_INT int 1 ------------ BB50 [2E1..2E3) (return), preds={} succs={} ***** BB50 STMT00029 (IL 0x2E1...0x2E2) [000150] ------------ * RETURN int [000149] ------------ \--* CNS_INT int 1 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Indirect call transform -- no candidates to transform *************** Finishing PHASE Indirect call transform [no changes] *************** Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Finishing PHASE Expand patchpoints [no changes] *************** Starting PHASE Post-import *************** Finishing PHASE Post-import *************** Starting PHASE Morph - Init New BlockSet epoch 1, # of blocks (including unused BB00): 51, bitset array size: 1 (short) *************** In fgRemoveEmptyBlocks BB10 was not imported, marking as removed (0) BB11 was not imported, marking as removed (1) BB12 was not imported, marking as removed (2) BB13 was not imported, marking as removed (3) BB14 was not imported, marking as removed (4) BB15 was not imported, marking as removed (5) BB16 was not imported, marking as removed (6) BB17 was not imported, marking as removed (7) BB18 was not imported, marking as removed (8) BB19 was not imported, marking as removed (9) Renumbering the basic blocks for fgRemoveEmptyBlocks *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 1 [008..00E) i BB03 [0002] 2 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 1 [016..01E) i BB05 [0004] 2 1 [01E..04B)-> BB07 ( cond ) i BB06 [0005] 1 1 [04B..054)-> BB08 (always) i BB07 [0006] 1 1 [054..061) i BB08 [0007] 2 1 [061..07A)-> BB31 ( cond ) i BB09 [0008] 1 1 [07A..08B)-> BB20 (always) i BB20 [0019] 1 1 [0FF..106) i BB21 [0020] 3 1 [106..110)-> BB41 ( cond ) i idxlen bwd bwd-target BB22 [0021] 1 1 [110..120)-> BB29 ( cond ) i idxlen bwd BB23 [0022] 1 1 [120..137)-> BB29 ( cond ) i idxlen bwd BB24 [0023] 1 1 [137..13B)-> BB26 ( cond ) i bwd BB25 [0024] 1 1 [13B..14B) (return) i idxlen BB26 [0025] 1 1 [14B..14F)-> BB28 ( cond ) i bwd BB27 [0026] 1 1 [14F..155) i bwd BB28 [0027] 2 1 [155..157) (return) i BB29 [0028] 2 1 [157..170)-> BB21 ( cond ) i idxlen bwd BB30 [0029] 1 1 [170..177)-> BB21 (always) i bwd BB31 [0030] 3 1 [177..17E)-> BB41 ( cond ) i idxlen bwd bwd-target BB32 [0031] 1 1 [17E..18E)-> BB39 ( cond ) i idxlen bwd BB33 [0032] 1 1 [18E..1A4)-> BB39 ( cond ) i idxlen bwd BB34 [0033] 1 1 [1A4..1A8)-> BB36 ( cond ) i bwd BB35 [0034] 1 1 [1A8..1B8) (return) i idxlen BB36 [0035] 1 1 [1B8..1BC)-> BB38 ( cond ) i bwd BB37 [0036] 1 1 [1BC..1C2) i bwd BB38 [0037] 2 1 [1C2..1C4) (return) i BB39 [0038] 2 1 [1C4..1DD)-> BB31 ( cond ) i idxlen bwd BB40 [0039] 1 1 [1DD..1E4)-> BB31 (always) i bwd BB41 [0040] 3 1 [1E4..1ED)-> BB43 ( cond ) i BB42 [0041] 1 1 [1ED..243)-> BB46 (always) i BB43 [0042] 1 1 [243..252)-> BB45 ( cond ) i idxlen BB44 [0043] 1 1 [252..261) i BB45 [0044] 2 1 [261..276) i BB46 [0045] 2 1 [276..2CA) i idxlen BB47 [0046] 1 1 [2CA..2CF)-> BB50 ( cond ) i BB48 [0047] 1 1 [2CF..2D7)-> BB50 ( cond ) i BB49 [0048] 1 1 [2D7..2E1) i idxlen BB50 [0049] 4 1 [2E1..2E3) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB20 to BB10 Renumber BB21 to BB11 Renumber BB22 to BB12 Renumber BB23 to BB13 Renumber BB24 to BB14 Renumber BB25 to BB15 Renumber BB26 to BB16 Renumber BB27 to BB17 Renumber BB28 to BB18 Renumber BB29 to BB19 Renumber BB30 to BB20 Renumber BB31 to BB21 Renumber BB32 to BB22 Renumber BB33 to BB23 Renumber BB34 to BB24 Renumber BB35 to BB25 Renumber BB36 to BB26 Renumber BB37 to BB27 Renumber BB38 to BB28 Renumber BB39 to BB29 Renumber BB40 to BB30 Renumber BB41 to BB31 Renumber BB42 to BB32 Renumber BB43 to BB33 Renumber BB44 to BB34 Renumber BB45 to BB35 Renumber BB46 to BB36 Renumber BB47 to BB37 Renumber BB48 to BB38 Renumber BB49 to BB39 Renumber BB50 to BB40 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 1 [008..00E) i BB03 [0002] 2 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 1 [016..01E) i BB05 [0004] 2 1 [01E..04B)-> BB07 ( cond ) i BB06 [0005] 1 1 [04B..054)-> BB08 (always) i BB07 [0006] 1 1 [054..061) i BB08 [0007] 2 1 [061..07A)-> BB21 ( cond ) i BB09 [0008] 1 1 [07A..08B)-> BB10 (always) i BB10 [0019] 1 1 [0FF..106) i BB11 [0020] 3 1 [106..110)-> BB31 ( cond ) i idxlen bwd bwd-target BB12 [0021] 1 1 [110..120)-> BB19 ( cond ) i idxlen bwd BB13 [0022] 1 1 [120..137)-> BB19 ( cond ) i idxlen bwd BB14 [0023] 1 1 [137..13B)-> BB16 ( cond ) i bwd BB15 [0024] 1 1 [13B..14B) (return) i idxlen BB16 [0025] 1 1 [14B..14F)-> BB18 ( cond ) i bwd BB17 [0026] 1 1 [14F..155) i bwd BB18 [0027] 2 1 [155..157) (return) i BB19 [0028] 2 1 [157..170)-> BB11 ( cond ) i idxlen bwd BB20 [0029] 1 1 [170..177)-> BB11 (always) i bwd BB21 [0030] 3 1 [177..17E)-> BB31 ( cond ) i idxlen bwd bwd-target BB22 [0031] 1 1 [17E..18E)-> BB29 ( cond ) i idxlen bwd BB23 [0032] 1 1 [18E..1A4)-> BB29 ( cond ) i idxlen bwd BB24 [0033] 1 1 [1A4..1A8)-> BB26 ( cond ) i bwd BB25 [0034] 1 1 [1A8..1B8) (return) i idxlen BB26 [0035] 1 1 [1B8..1BC)-> BB28 ( cond ) i bwd BB27 [0036] 1 1 [1BC..1C2) i bwd BB28 [0037] 2 1 [1C2..1C4) (return) i BB29 [0038] 2 1 [1C4..1DD)-> BB21 ( cond ) i idxlen bwd BB30 [0039] 1 1 [1DD..1E4)-> BB21 (always) i bwd BB31 [0040] 3 1 [1E4..1ED)-> BB33 ( cond ) i BB32 [0041] 1 1 [1ED..243)-> BB36 (always) i BB33 [0042] 1 1 [243..252)-> BB35 ( cond ) i idxlen BB34 [0043] 1 1 [252..261) i BB35 [0044] 2 1 [261..276) i BB36 [0045] 2 1 [276..2CA) i idxlen BB37 [0046] 1 1 [2CA..2CF)-> BB40 ( cond ) i BB38 [0047] 1 1 [2CF..2D7)-> BB40 ( cond ) i BB39 [0048] 1 1 [2D7..2E1) i idxlen BB40 [0049] 4 1 [2E1..2E3) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 2, # of blocks (including unused BB00): 41, bitset array size: 1 (short) *************** Finishing PHASE Morph - Init *************** In fgDebugCheckBBlist *************** Starting PHASE Morph - Inlining Expanding INLINE_CANDIDATE in statement STMT00086 in BB02: STMT00086 (IL 0x008...0x009) [000533] I-C-G------- * CALL void System.ThrowHelper.ThrowArgumentNullException (exactContextHnd=0x00000000D1FFAB1E) [000532] ------------ arg0 \--* CNS_INT int 4 Argument #0: is a constant [000532] ------------ * CNS_INT int 4 INLINER: inlineInfo.tokenLookupContextHandle for System.ThrowHelper:ThrowArgumentNullException(int) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.ThrowHelper:ThrowArgumentNullException(int) : IL to import: IL_0000 02 ldarg.0 IL_0001 28 70 19 00 06 call 0x6001970 IL_0006 73 00 0a 00 06 newobj 0x6000A00 IL_000b 7a throw INLINER impTokenLookupContextHandle for System.ThrowHelper:ThrowArgumentNullException(int) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.ThrowHelper:ThrowArgumentNullException(int) Jump targets: none New Basic Block BB41 [0050] created. BB41 [000..00C) Basic block list for 'System.ThrowHelper:ThrowArgumentNullException(int)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB41 [0050] 1 0 [000..00C) (throw ) rare ----------------------------------------------------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.ThrowHelper:ThrowArgumentNullException(int)' INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' Expanding INLINE_CANDIDATE in statement STMT00084 in BB04: STMT00084 (IL 0x016...0x01D) [000528] I-C-G------- * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize (exactContextHnd=0x00000000D1FFAB1E) [000526] ------------ this in rcx +--* LCL_VAR ref V00 this [000527] ------------ arg1 \--* CNS_INT int 0 thisArg: is a local var [000526] ------------ * LCL_VAR ref V00 this Argument #1: is a constant [000527] ------------ * CNS_INT int 0 INLINER: inlineInfo.tokenLookupContextHandle for System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Initialize(int):int:this set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Initialize(int):int:this : IL to import: IL_0000 03 ldarg.1 IL_0001 28 a5 63 00 06 call 0x60063A5 IL_0006 0a stloc.0 IL_0007 06 ldloc.0 IL_0008 8d 41 01 00 02 newarr 0x2000141 IL_000d 0b stloc.1 IL_000e 06 ldloc.0 IL_000f 8d 29 04 00 1b newarr 0x1B000429 IL_0014 0c stloc.2 IL_0015 02 ldarg.0 IL_0016 15 ldc.i4.m1 IL_0017 7d 22 0c 00 0a stfld 0xA000C22 IL_001c 02 ldarg.0 IL_001d 06 ldloc.0 IL_001e 28 a7 63 00 06 call 0x60063A7 IL_0023 7d 2b 0c 00 0a stfld 0xA000C2B IL_0028 02 ldarg.0 IL_0029 07 ldloc.1 IL_002a 7d 21 0c 00 0a stfld 0xA000C21 IL_002f 02 ldarg.0 IL_0030 08 ldloc.2 IL_0031 7d 06 0c 00 0a stfld 0xA000C06 IL_0036 06 ldloc.0 IL_0037 2a ret INLINER impTokenLookupContextHandle for System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Initialize(int):int:this is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Initialize(int):int:this weight= 16 : state 4 [ ldarg.1 ] weight= 79 : state 40 [ call ] weight= 20 : state 199 [ stloc.0 -> ldloc.0 ] weight=152 : state 118 [ newarr ] weight= 34 : state 12 [ stloc.1 ] weight= 12 : state 7 [ ldloc.0 ] weight=152 : state 118 [ newarr ] weight= 4 : state 13 [ stloc.2 ] weight= 10 : state 3 [ ldarg.0 ] weight= 22 : state 22 [ ldc.i4.m1 ] weight= 31 : state 111 [ stfld ] weight= 10 : state 3 [ ldarg.0 ] weight= 12 : state 7 [ ldloc.0 ] weight= 79 : state 40 [ call ] weight= 31 : state 111 [ stfld ] weight= 10 : state 3 [ ldarg.0 ] weight= 9 : state 8 [ ldloc.1 ] weight= 31 : state 111 [ stfld ] weight= 10 : state 3 [ ldarg.0 ] weight= 22 : state 9 [ ldloc.2 ] weight= 31 : state 111 [ stfld ] weight= 12 : state 7 [ ldloc.0 ] weight= 19 : state 42 [ ret ] Inline candidate callsite is boring. Multiplier increased to 1.3. calleeNativeSizeEstimate=808 callsiteNativeSizeEstimate=115 benefit multiplier=1.3 threshold=149 Native estimate for function size exceeds threshold for inlining 80.8 > 14.9 (multiplier = 1.3) Inline expansion aborted, inline not profitable Inlining [000528] failed, so bashing STMT00084 to NOP INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Initialize(int):int:this' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Replacing the return expression placeholder [000529] with [000528] [000529] --C--------- * RET_EXPR int (inl return expr [000528]) Inserting the inline return expression [000528] --C-G------- * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize [000526] ------------ this in rcx +--* LCL_VAR ref V00 this [000527] ------------ arg1 \--* CNS_INT int 0 Expanding INLINE_CANDIDATE in statement STMT00002 in BB05: STMT00002 (IL 0x01E...0x032) [000013] I-CXG------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000014] ---XG------- arg0 \--* PUTARG_TYPE bool [000012] N--XG----U-- \--* GT int [000010] ---XG------- +--* FIELD ref _buckets [000009] ------------ | \--* LCL_VAR ref V00 this [000011] ------------ \--* CNS_INT ref null Argument #0: has global refs has side effects [000012] N--XG----U-- * GT int [000010] ---XG------- +--* FIELD ref _buckets [000009] ------------ | \--* LCL_VAR ref V00 this [000011] ------------ \--* CNS_INT ref null INLINER: inlineInfo.tokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Diagnostics.Debug:Assert(bool) : IL to import: IL_0000 02 ldarg.0 IL_0001 7e 68 02 00 04 ldsfld 0x4000268 IL_0006 7e 68 02 00 04 ldsfld 0x4000268 IL_000b 28 fb 5c 00 06 call 0x6005CFB IL_0010 2a ret INLINER impTokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Diagnostics.Debug:Assert(bool) weight= 10 : state 3 [ ldarg.0 ] weight=159 : state 112 [ ldsfld ] weight=159 : state 112 [ ldsfld ] weight= 79 : state 40 [ call ] weight= 19 : state 42 [ ret ] Inline candidate looks like a wrapper method. Multiplier increased to 1. Inline candidate is mostly loads and stores. Multiplier increased to 4. Inline candidate callsite is boring. Multiplier increased to 5.3. calleeNativeSizeEstimate=426 callsiteNativeSizeEstimate=85 benefit multiplier=5.3 threshold=450 Native estimate for function size is within threshold for inlining 42.6 <= 45 (multiplier = 5.3) Jump targets: none New Basic Block BB42 [0050] created. BB42 [000..011) Basic block list for 'System.Diagnostics.Debug:Assert(bool)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB42 [0050] 1 1 [000..011) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000013] Starting PHASE Pre-import *************** Inline @[000013] Finishing PHASE Pre-import *************** Inline @[000013] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000013] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB42 [0050] 1 1 [000..011) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB42 [000..011) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000013] Starting PHASE Importation *************** In impImport() for System.Diagnostics.Debug:Assert(bool) impImportBlockPending for BB42 Importing BB42 (PC=000) of 'System.Diagnostics.Debug:Assert(bool)' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 33 (V33 tmp19) called for Inlining Arg. [ 1] 1 (0x001) ldsfld 04000268 [ 2] 6 (0x006) ldsfld 04000268 [ 3] 11 (0x00b) call 06005CFB In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000541] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000542] ------------ arg0 +--* PUTARG_TYPE bool [000536] ------------ | \--* LCL_VAR int V33 tmp19 [000538] #---G------- arg1 +--* IND ref [000537] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [000540] #---G------- arg2 \--* IND ref [000539] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [ 0] 16 (0x010) ret *************** Inline @[000013] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB42 [0050] 1 1 [000..011) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB42 [000..011) (return), preds={} succs={} ***** BB42 [000541] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000542] ------------ arg0 +--* PUTARG_TYPE bool [000536] ------------ | \--* LCL_VAR int V33 tmp19 [000538] #---G------- arg1 +--* IND ref [000537] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [000540] #---G------- arg2 \--* IND ref [000539] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000013] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000013] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000013] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000013] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000013] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000013] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000013] ----------- Arguments setup: STMT00088 (IL 0x01E... ???) [000544] -A-XG------- * ASG bool [000543] D------N---- +--* LCL_VAR bool V33 tmp19 [000535] ---XG------- \--* CAST int <- bool <- int [000012] N--XG----U-- \--* GT int [000010] ---XG------- +--* FIELD ref _buckets [000009] ------------ | \--* LCL_VAR ref V00 this [000011] ------------ \--* CNS_INT ref null Inlinee method body: STMT00087 (IL 0x01E... ???) [000541] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000542] ------------ arg0 +--* PUTARG_TYPE bool [000536] ------------ | \--* LCL_VAR int V33 tmp19 [000538] #---G------- arg1 +--* IND ref [000537] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [000540] #---G------- arg2 \--* IND ref [000539] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Diagnostics.Debug:Assert(bool) (17 IL bytes) (depth 1) [profitable inline] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'profitable inline' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Diagnostics.Debug:Assert(bool)' INLINER: during 'fgInline' result 'success' reason 'profitable inline' Expanding INLINE_CANDIDATE in statement STMT00087 in BB05: STMT00087 (IL 0x01E... ???) [000541] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000542] ------------ arg0 +--* PUTARG_TYPE bool [000536] ------------ | \--* LCL_VAR int V33 tmp19 [000538] #---G------- arg1 +--* IND ref [000537] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [000540] #---G------- arg2 \--* IND ref [000539] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] Argument #0: is a local var [000536] ------------ * LCL_VAR int V33 tmp19 Argument #1: has global refs [000538] #---G------- * IND ref [000537] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] Argument #2: has global refs [000540] #---G------- * IND ref [000539] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] INLINER: inlineInfo.tokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool,System.String,System.String) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Diagnostics.Debug:Assert(bool,System.String,System.String) : IL to import: IL_0000 02 ldarg.0 IL_0001 2d 07 brtrue.s 7 (IL_000a) IL_0003 03 ldarg.1 IL_0004 04 ldarg.2 IL_0005 28 fe 5c 00 06 call 0x6005CFE IL_000a 2a ret INLINER impTokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool,System.String,System.String) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Diagnostics.Debug:Assert(bool,System.String,System.String) Jump targets: IL_000a New Basic Block BB43 [0051] created. BB43 [000..003) New Basic Block BB44 [0052] created. BB44 [003..00A) New Basic Block BB45 [0053] created. BB45 [00A..00B) Basic block list for 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB43 [0051] 1 1 [000..003)-> BB45 ( cond ) BB44 [0052] 1 1 [003..00A) BB45 [0053] 2 1 [00A..00B) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000541] Starting PHASE Pre-import *************** Inline @[000541] Finishing PHASE Pre-import *************** Inline @[000541] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000541] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB43 [0051] 1 1 [000..003)-> BB45 ( cond ) BB44 [0052] 1 1 [003..00A) BB45 [0053] 2 1 [00A..00B) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB43 [000..003) -> BB45 (cond), preds={} succs={BB44,BB45} ------------ BB44 [003..00A), preds={} succs={BB45} ------------ BB45 [00A..00B) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000541] Starting PHASE Importation *************** In impImport() for System.Diagnostics.Debug:Assert(bool,System.String,System.String) impImportBlockPending for BB43 Importing BB43 (PC=000) of 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) brtrue.s [000549] ------------ * JTRUE void [000548] ------------ \--* NE int [000546] ------------ +--* LCL_VAR int V33 tmp19 [000547] ------------ \--* CNS_INT int 0 impImportBlockPending for BB44 impImportBlockPending for BB45 Importing BB45 (PC=010) of 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' [ 0] 10 (0x00a) ret Importing BB44 (PC=003) of 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' [ 0] 3 (0x003) ldarg.1 lvaGrabTemp returning 34 (V34 tmp20) called for Inlining Arg. Marked V34 as a single def temp lvaSetClass: setting class for V34 to (00000000D1FFAB1E) System.String [ 1] 4 (0x004) ldarg.2 lvaGrabTemp returning 35 (V35 tmp21) called for Inlining Arg. Marked V35 as a single def temp lvaSetClass: setting class for V35 to (00000000D1FFAB1E) System.String [ 2] 5 (0x005) call 06005CFE In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' calling 'System.Diagnostics.Debug:Fail(System.String,System.String)' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' [000552] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000550] ------------ arg0 +--* LCL_VAR ref V34 tmp20 [000551] ------------ arg1 \--* LCL_VAR ref V35 tmp21 impImportBlockPending for BB45 ** Note: inlinee IL was partially imported -- imported 10 of 11 bytes of method IL *************** Inline @[000541] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB43 [0051] 1 1 [000..003)-> BB45 ( cond ) i BB44 [0052] 1 1 [003..00A) i BB45 [0053] 2 1 [00A..00B) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB43 [000..003) -> BB45 (cond), preds={} succs={BB44,BB45} ***** BB43 [000549] ------------ * JTRUE void [000548] ------------ \--* NE int [000546] ------------ +--* LCL_VAR int V33 tmp19 [000547] ------------ \--* CNS_INT int 0 ------------ BB44 [003..00A), preds={} succs={BB45} ***** BB44 [000552] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000550] ------------ arg0 +--* LCL_VAR ref V34 tmp20 [000551] ------------ arg1 \--* LCL_VAR ref V35 tmp21 ------------ BB45 [00A..00B) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000541] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000541] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000541] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000541] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000541] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000541] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000541] ----------- Arguments setup: STMT00091 (IL 0x01E... ???) [000554] -A--G------- * ASG ref [000553] D------N---- +--* LCL_VAR ref V34 tmp20 [000538] #---G------- \--* IND ref [000537] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] STMT00092 (IL 0x01E... ???) [000556] -A--G------- * ASG ref [000555] D------N---- +--* LCL_VAR ref V35 tmp21 [000540] #---G------- \--* IND ref [000539] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] Inlinee method body:New Basic Block BB46 [0054] created. Convert bbJumpKind of BB45 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB43 [0051] 1 1 [01E..01F)-> BB45 ( cond ) i BB44 [0052] 1 1 [01E..01F) i BB45 [0053] 2 1 [01E..01F) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB43 [01E..01F) -> BB45 (cond), preds={} succs={BB44,BB45} ***** BB43 STMT00089 (IL 0x01E... ???) [000549] ------------ * JTRUE void [000548] ------------ \--* NE int [000546] ------------ +--* LCL_VAR int V33 tmp19 [000547] ------------ \--* CNS_INT int 0 ------------ BB44 [01E..01F), preds={} succs={BB45} ***** BB44 STMT00090 (IL 0x01E... ???) [000552] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000550] ------------ arg0 +--* LCL_VAR ref V34 tmp20 [000551] ------------ arg1 \--* LCL_VAR ref V35 tmp21 ------------ BB45 [01E..01F), preds={} succs={BB46} ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Diagnostics.Debug:Assert(bool,System.String,System.String) (11 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement STMT00004 in BB46: STMT00004 (IL 0x033...0x047) [000023] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000024] ------------ arg0 +--* PUTARG_TYPE bool [000021] N--------U-- | \--* GT int [000019] ------------ | +--* LCL_VAR ref V04 loc0 [000020] ------------ | \--* CNS_INT ref null [000022] ------------ arg1 \--* CNS_STR ref Argument #0: [000021] N--------U-- * GT int [000019] ------------ +--* LCL_VAR ref V04 loc0 [000020] ------------ \--* CNS_INT ref null Argument #1: is a constant [000022] ------------ * CNS_STR ref INLINER: inlineInfo.tokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool,System.String) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Diagnostics.Debug:Assert(bool,System.String) : IL to import: IL_0000 02 ldarg.0 IL_0001 03 ldarg.1 IL_0002 7e 68 02 00 04 ldsfld 0x4000268 IL_0007 28 fb 5c 00 06 call 0x6005CFB IL_000c 2a ret INLINER impTokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool,System.String) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Diagnostics.Debug:Assert(bool,System.String) Jump targets: none New Basic Block BB47 [0055] created. BB47 [000..00D) Basic block list for 'System.Diagnostics.Debug:Assert(bool,System.String)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB47 [0055] 1 1 [000..00D) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000023] Starting PHASE Pre-import *************** Inline @[000023] Finishing PHASE Pre-import *************** Inline @[000023] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000023] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB47 [0055] 1 1 [000..00D) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB47 [000..00D) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000023] Starting PHASE Importation *************** In impImport() for System.Diagnostics.Debug:Assert(bool,System.String) impImportBlockPending for BB47 Importing BB47 (PC=000) of 'System.Diagnostics.Debug:Assert(bool,System.String)' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 36 (V36 tmp22) called for Inlining Arg. [ 1] 1 (0x001) ldarg.1 [ 2] 2 (0x002) ldsfld 04000268 [ 3] 7 (0x007) call 06005CFB In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000563] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000564] ------------ arg0 +--* PUTARG_TYPE bool [000559] ------------ | \--* LCL_VAR int V36 tmp22 [000560] ------------ arg1 +--* CNS_STR ref [000562] #---G------- arg2 \--* IND ref [000561] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [ 0] 12 (0x00c) ret *************** Inline @[000023] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB47 [0055] 1 1 [000..00D) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB47 [000..00D) (return), preds={} succs={} ***** BB47 [000563] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000564] ------------ arg0 +--* PUTARG_TYPE bool [000559] ------------ | \--* LCL_VAR int V36 tmp22 [000560] ------------ arg1 +--* CNS_STR ref [000562] #---G------- arg2 \--* IND ref [000561] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000023] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000023] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000023] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000023] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000023] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000023] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000023] ----------- Arguments setup: STMT00094 (IL 0x033... ???) [000566] -A---------- * ASG bool [000565] D------N---- +--* LCL_VAR bool V36 tmp22 [000558] ------------ \--* CAST int <- bool <- int [000021] N--------U-- \--* GT int [000019] ------------ +--* LCL_VAR ref V04 loc0 [000020] ------------ \--* CNS_INT ref null Inlinee method body: STMT00093 (IL 0x033... ???) [000563] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000564] ------------ arg0 +--* PUTARG_TYPE bool [000559] ------------ | \--* LCL_VAR int V36 tmp22 [000560] ------------ arg1 +--* CNS_STR ref [000562] #---G------- arg2 \--* IND ref [000561] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Diagnostics.Debug:Assert(bool,System.String) (13 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Diagnostics.Debug:Assert(bool,System.String)' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement STMT00093 in BB46: STMT00093 (IL 0x033... ???) [000563] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000564] ------------ arg0 +--* PUTARG_TYPE bool [000559] ------------ | \--* LCL_VAR int V36 tmp22 [000560] ------------ arg1 +--* CNS_STR ref [000562] #---G------- arg2 \--* IND ref [000561] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] Argument #0: is a local var [000559] ------------ * LCL_VAR int V36 tmp22 Argument #1: is a constant [000560] ------------ * CNS_STR ref Argument #2: has global refs [000562] #---G------- * IND ref [000561] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] INLINER: inlineInfo.tokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool,System.String,System.String) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Diagnostics.Debug:Assert(bool,System.String,System.String) : IL to import: IL_0000 02 ldarg.0 IL_0001 2d 07 brtrue.s 7 (IL_000a) IL_0003 03 ldarg.1 IL_0004 04 ldarg.2 IL_0005 28 fe 5c 00 06 call 0x6005CFE IL_000a 2a ret INLINER impTokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool,System.String,System.String) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Diagnostics.Debug:Assert(bool,System.String,System.String) Jump targets: IL_000a New Basic Block BB48 [0056] created. BB48 [000..003) New Basic Block BB49 [0057] created. BB49 [003..00A) New Basic Block BB50 [0058] created. BB50 [00A..00B) Basic block list for 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB48 [0056] 1 1 [000..003)-> BB50 ( cond ) BB49 [0057] 1 1 [003..00A) BB50 [0058] 2 1 [00A..00B) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000563] Starting PHASE Pre-import *************** Inline @[000563] Finishing PHASE Pre-import *************** Inline @[000563] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000563] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB48 [0056] 1 1 [000..003)-> BB50 ( cond ) BB49 [0057] 1 1 [003..00A) BB50 [0058] 2 1 [00A..00B) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB48 [000..003) -> BB50 (cond), preds={} succs={BB49,BB50} ------------ BB49 [003..00A), preds={} succs={BB50} ------------ BB50 [00A..00B) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000563] Starting PHASE Importation *************** In impImport() for System.Diagnostics.Debug:Assert(bool,System.String,System.String) impImportBlockPending for BB48 Importing BB48 (PC=000) of 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) brtrue.s [000571] ------------ * JTRUE void [000570] ------------ \--* NE int [000568] ------------ +--* LCL_VAR int V36 tmp22 [000569] ------------ \--* CNS_INT int 0 impImportBlockPending for BB49 impImportBlockPending for BB50 Importing BB50 (PC=010) of 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' [ 0] 10 (0x00a) ret Importing BB49 (PC=003) of 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' [ 0] 3 (0x003) ldarg.1 [ 1] 4 (0x004) ldarg.2 lvaGrabTemp returning 37 (V37 tmp23) called for Inlining Arg. Marked V37 as a single def temp lvaSetClass: setting class for V37 to (00000000D1FFAB1E) System.String [ 2] 5 (0x005) call 06005CFE In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' calling 'System.Diagnostics.Debug:Fail(System.String,System.String)' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' [000574] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000572] ------------ arg0 +--* CNS_STR ref [000573] ------------ arg1 \--* LCL_VAR ref V37 tmp23 impImportBlockPending for BB50 ** Note: inlinee IL was partially imported -- imported 10 of 11 bytes of method IL *************** Inline @[000563] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB48 [0056] 1 1 [000..003)-> BB50 ( cond ) i BB49 [0057] 1 1 [003..00A) i BB50 [0058] 2 1 [00A..00B) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB48 [000..003) -> BB50 (cond), preds={} succs={BB49,BB50} ***** BB48 [000571] ------------ * JTRUE void [000570] ------------ \--* NE int [000568] ------------ +--* LCL_VAR int V36 tmp22 [000569] ------------ \--* CNS_INT int 0 ------------ BB49 [003..00A), preds={} succs={BB50} ***** BB49 [000574] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000572] ------------ arg0 +--* CNS_STR ref [000573] ------------ arg1 \--* LCL_VAR ref V37 tmp23 ------------ BB50 [00A..00B) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000563] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000563] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000563] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000563] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000563] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000563] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000563] ----------- Arguments setup: STMT00097 (IL 0x033... ???) [000576] -A--G------- * ASG ref [000575] D------N---- +--* LCL_VAR ref V37 tmp23 [000562] #---G------- \--* IND ref [000561] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] Inlinee method body:New Basic Block BB51 [0059] created. Convert bbJumpKind of BB50 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB48 [0056] 1 1 [033..034)-> BB50 ( cond ) i BB49 [0057] 1 1 [033..034) i BB50 [0058] 2 1 [033..034) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB48 [033..034) -> BB50 (cond), preds={} succs={BB49,BB50} ***** BB48 STMT00095 (IL 0x033... ???) [000571] ------------ * JTRUE void [000570] ------------ \--* NE int [000568] ------------ +--* LCL_VAR int V36 tmp22 [000569] ------------ \--* CNS_INT int 0 ------------ BB49 [033..034), preds={} succs={BB50} ***** BB49 STMT00096 (IL 0x033... ???) [000574] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000572] ------------ arg0 +--* CNS_STR ref [000573] ------------ arg1 \--* LCL_VAR ref V37 tmp23 ------------ BB50 [033..034), preds={} succs={BB51} ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Diagnostics.Debug:Assert(bool,System.String,System.String) (11 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Querying runtime about current class of field System.Collections.Generic.Dictionary`2[System.__Canon,System.__Canon]._comparer (declared as System.Collections.Generic.IEqualityComparer`1[__Canon]) Field's current class not available **** Late devirt opportunity [000035] --CXG------- * CALLV vt-ind int System.Object.GetHashCode [000036] *--XG------- this in rcx \--* IND ref [000034] ------------ \--* ADDR long [000033] -------N---- \--* LCL_VAR ref V01 arg1 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is System.__Canon (attrib 20020000) base method is System.Object::GetHashCode --- no derived method Class not final or exact, and method not final No guarded devirt during late devirtualization Expanding INLINE_CANDIDATE in statement STMT00010 in BB08: STMT00010 (IL 0x064...0x06B) [000048] I-C-G------- * CALL byref System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].GetBucket (exactContextHnd=0x00000000D1FFAB1E) [000046] ------------ this in rcx +--* LCL_VAR ref V00 this [000047] ------------ arg1 \--* LCL_VAR int V06 loc2 thisArg: is a local var [000046] ------------ * LCL_VAR ref V00 this Argument #1: is a local var [000047] ------------ * LCL_VAR int V06 loc2 INLINER: inlineInfo.tokenLookupContextHandle for System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:GetBucket(int):byref:this set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:GetBucket(int):byref:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 21 0c 00 0a ldfld 0xA000C21 IL_0006 0a stloc.0 IL_0007 06 ldloc.0 IL_0008 03 ldarg.1 IL_0009 06 ldloc.0 IL_000a 8e ldlen IL_000b 69 conv.i4 IL_000c 02 ldarg.0 IL_000d 7b 2b 0c 00 0a ldfld 0xA000C2B IL_0012 28 a8 63 00 06 call 0x60063A8 IL_0017 8f 41 01 00 02 ldelema 0x2000141 IL_001c 2a ret INLINER impTokenLookupContextHandle for System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:GetBucket(int):byref:this is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:GetBucket(int):byref:this Jump targets: none New Basic Block BB52 [0060] created. BB52 [000..01D) lvaGrabTemp returning 38 (V38 tmp24) (a long lifetime temp) called for Inline return value spill temp. Basic block list for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:GetBucket(int):byref:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB52 [0060] 1 1 [000..01D) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000048] Starting PHASE Pre-import *************** Inline @[000048] Finishing PHASE Pre-import *************** Inline @[000048] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000048] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB52 [0060] 1 1 [000..01D) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB52 [000..01D) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000048] Starting PHASE Importation *************** In impImport() for System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:GetBucket(int):byref:this impImportBlockPending for BB52 Importing BB52 (PC=000) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:GetBucket(int):byref:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000C21 [ 1] 6 (0x006) stloc.0 lvaGrabTemp returning 39 (V39 tmp25) (a long lifetime temp) called for Inline stloc first use temp. Marked V39 as a single def temp lvaSetClass: setting class for V39 to (00000000D1FFAB1E) System.Int32[] Querying runtime about current class of field System.Collections.Generic.Dictionary`2[System.__Canon,System.__Canon]._buckets (declared as System.Int32[]) Field's current class not available [000580] -A-XG------- * ASG ref [000579] D------N---- +--* LCL_VAR ref V39 tmp25 [000578] ---XG------- \--* FIELD ref _buckets [000046] ------------ \--* LCL_VAR ref V00 this [ 0] 7 (0x007) ldloc.0 [ 1] 8 (0x008) ldarg.1 [ 2] 9 (0x009) ldloc.0 [ 3] 10 (0x00a) ldlen [ 3] 11 (0x00b) conv.i4 [ 3] 12 (0x00c) ldarg.0 [ 4] 13 (0x00d) ldfld 0A000C2B [ 4] 18 (0x012) call 060063A8 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 [000586] I-CXG------- * CALL int System.Collections.HashHelpers.FastMod (exactContextHnd=0x00000000D1FFAB1E) [000047] ------------ arg0 +--* LCL_VAR int V06 loc2 [000583] ---X-------- arg1 +--* ARR_LENGTH int [000582] ------------ | \--* LCL_VAR ref V39 tmp25 [000585] ---XG------- arg2 \--* FIELD long _fastModMultiplier [000584] ------------ \--* LCL_VAR ref V00 this [ 2] 23 (0x017) ldelema 02000141 [ 1] 28 (0x01c) ret Inlinee Return expression (before normalization) => [000589] --CXG------- * ADDR byref [000588] --CXG--N---- \--* INDEX int [000581] ------------ +--* LCL_VAR ref V39 tmp25 [000587] --C--------- \--* RET_EXPR int (inl return expr [000586]) [000591] -ACXG------- * ASG byref [000590] D------N---- +--* LCL_VAR byref V38 tmp24 [000589] --CXG------- \--* ADDR byref [000588] --CXG--N---- \--* INDEX int [000581] ------------ +--* LCL_VAR ref V39 tmp25 [000587] --C--------- \--* RET_EXPR int (inl return expr [000586]) Inlinee Return expression (after normalization) => [000592] ------------ * LCL_VAR byref V38 tmp24 *************** Inline @[000048] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB52 [0060] 1 1 [000..01D) (return) i idxlen ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB52 [000..01D) (return), preds={} succs={} ***** BB52 [000580] -A-XG------- * ASG ref [000579] D------N---- +--* LCL_VAR ref V39 tmp25 [000578] ---XG------- \--* FIELD ref _buckets [000046] ------------ \--* LCL_VAR ref V00 this ***** BB52 [000586] I-CXG------- * CALL int System.Collections.HashHelpers.FastMod (exactContextHnd=0x00000000D1FFAB1E) [000047] ------------ arg0 +--* LCL_VAR int V06 loc2 [000583] ---X-------- arg1 +--* ARR_LENGTH int [000582] ------------ | \--* LCL_VAR ref V39 tmp25 [000585] ---XG------- arg2 \--* FIELD long _fastModMultiplier [000584] ------------ \--* LCL_VAR ref V00 this ***** BB52 [000591] -ACXG------- * ASG byref [000590] D------N---- +--* LCL_VAR byref V38 tmp24 [000589] --CXG------- \--* ADDR byref [000588] --CXG--N---- \--* INDEX int [000581] ------------ +--* LCL_VAR ref V39 tmp25 [000587] --C--------- \--* RET_EXPR int (inl return expr [000586]) ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000048] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000048] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000048] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000048] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000048] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000048] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000048] ----------- Arguments setup: Inlinee method body: STMT00098 (IL 0x064... ???) [000580] -A-XG------- * ASG ref [000579] D------N---- +--* LCL_VAR ref V39 tmp25 [000578] ---XG------- \--* FIELD ref _buckets [000046] ------------ \--* LCL_VAR ref V00 this STMT00099 (IL 0x064... ???) [000586] I-CXG------- * CALL int System.Collections.HashHelpers.FastMod (exactContextHnd=0x00000000D1FFAB1E) [000047] ------------ arg0 +--* LCL_VAR int V06 loc2 [000583] ---X-------- arg1 +--* ARR_LENGTH int [000582] ------------ | \--* LCL_VAR ref V39 tmp25 [000585] ---XG------- arg2 \--* FIELD long _fastModMultiplier [000584] ------------ \--* LCL_VAR ref V00 this STMT00100 (IL 0x064... ???) [000591] -ACXG------- * ASG byref [000590] D------N---- +--* LCL_VAR byref V38 tmp24 [000589] --CXG------- \--* ADDR byref [000588] --CXG--N---- \--* INDEX int [000581] ------------ +--* LCL_VAR ref V39 tmp25 [000587] --C--------- \--* RET_EXPR int (inl return expr [000586]) fgInlineAppendStatements: nulling out gc ref inlinee locals. STMT00101 (IL 0x064... ???) [000595] -A---------- * ASG ref [000594] D------N---- +--* LCL_VAR ref V39 tmp25 [000593] ------------ \--* CNS_INT ref null Return expression for call at [000048] is [000592] ------------ * LCL_VAR byref V38 tmp24 Successfully inlined System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:GetBucket(int):byref:this (29 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:GetBucket(int):byref:this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Querying runtime about current class of field System.Collections.Generic.Dictionary`2[System.__Canon,System.__Canon]._buckets (declared as System.Int32[]) Field's current class not available Expanding INLINE_CANDIDATE in statement STMT00099 in BB08: STMT00099 (IL 0x064... ???) [000586] I-CXG------- * CALL int System.Collections.HashHelpers.FastMod (exactContextHnd=0x00000000D1FFAB1E) [000047] ------------ arg0 +--* LCL_VAR int V06 loc2 [000583] ---X-------- arg1 +--* ARR_LENGTH int [000582] ------------ | \--* LCL_VAR ref V39 tmp25 [000585] ---XG------- arg2 \--* FIELD long _fastModMultiplier [000584] ------------ \--* LCL_VAR ref V00 this Argument #0: is a local var [000047] ------------ * LCL_VAR int V06 loc2 Argument #1: has side effects [000583] ---X-------- * ARR_LENGTH int [000582] ------------ \--* LCL_VAR ref V39 tmp25 Argument #2: has global refs has side effects [000585] ---XG------- * FIELD long _fastModMultiplier [000584] ------------ \--* LCL_VAR ref V00 this INLINER: inlineInfo.tokenLookupContextHandle for System.Collections.HashHelpers:FastMod(int,int,long):int set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Collections.HashHelpers:FastMod(int,int,long):int : IL to import: IL_0000 03 ldarg.1 IL_0001 20 ff ff ff 7f ldc.i4 0x7FFFFFFF IL_0006 fe 03 cgt.un IL_0008 16 ldc.i4.0 IL_0009 fe 01 ceq IL_000b 28 f9 5c 00 06 call 0x6005CF9 IL_0010 04 ldarg.2 IL_0011 02 ldarg.0 IL_0012 6e conv.u8 IL_0013 5a mul IL_0014 1f 20 ldc.i4.s 0x20 IL_0016 64 shr.un IL_0017 17 ldc.i4.1 IL_0018 6a conv.i8 IL_0019 58 add IL_001a 03 ldarg.1 IL_001b 6e conv.u8 IL_001c 5a mul IL_001d 1f 20 ldc.i4.s 0x20 IL_001f 64 shr.un IL_0020 6d conv.u4 IL_0021 0a stloc.0 IL_0022 06 ldloc.0 IL_0023 02 ldarg.0 IL_0024 03 ldarg.1 IL_0025 5e rem.un IL_0026 fe 01 ceq IL_0028 28 f9 5c 00 06 call 0x6005CF9 IL_002d 06 ldloc.0 IL_002e 2a ret INLINER impTokenLookupContextHandle for System.Collections.HashHelpers:FastMod(int,int,long):int is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Collections.HashHelpers:FastMod(int,int,long):int Jump targets: none New Basic Block BB53 [0061] created. BB53 [000..02F) Basic block list for 'System.Collections.HashHelpers:FastMod(int,int,long):int' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB53 [0061] 1 1 [000..02F) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000586] Starting PHASE Pre-import *************** Inline @[000586] Finishing PHASE Pre-import *************** Inline @[000586] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000586] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB53 [0061] 1 1 [000..02F) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB53 [000..02F) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000586] Starting PHASE Importation *************** In impImport() for System.Collections.HashHelpers:FastMod(int,int,long):int impImportBlockPending for BB53 Importing BB53 (PC=000) of 'System.Collections.HashHelpers:FastMod(int,int,long):int' [ 0] 0 (0x000) ldarg.1 lvaGrabTemp returning 40 (V40 tmp26) called for Inlining Arg. [ 1] 1 (0x001) ldc.i4 2147483647 [ 2] 6 (0x006) cgt.un [ 1] 8 (0x008) ldc.i4.0 0 [ 2] 9 (0x009) ceq [ 1] 11 (0x00b) call 06005CF9 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000602] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000603] ------------ arg0 \--* PUTARG_TYPE bool [000601] ------------ \--* EQ int [000599] N--------U-- +--* GT int [000597] ------------ | +--* LCL_VAR int V40 tmp26 [000598] ------------ | \--* CNS_INT int 0x7FFFFFFF [000600] ------------ \--* CNS_INT int 0 [ 0] 16 (0x010) ldarg.2 lvaGrabTemp returning 41 (V41 tmp27) called for Inlining Arg. [ 1] 17 (0x011) ldarg.0 [ 2] 18 (0x012) conv.u8 [ 2] 19 (0x013) mul [ 1] 20 (0x014) ldc.i4.s 32 [ 2] 22 (0x016) shr.un [ 1] 23 (0x017) ldc.i4.1 1 [ 2] 24 (0x018) conv.i8 Folding long operator with constant nodes into a constant: [000610] ------------ * CAST long <- int [000609] ------------ \--* CNS_INT int 1 Bashed to long constant: [000610] ------------ * CNS_INT long 1 [ 2] 25 (0x019) add [ 1] 26 (0x01a) ldarg.1 [ 2] 27 (0x01b) conv.u8 [ 2] 28 (0x01c) mul [ 1] 29 (0x01d) ldc.i4.s 32 [ 2] 31 (0x01f) shr.un [ 1] 32 (0x020) conv.u4 [ 1] 33 (0x021) stloc.0 lvaGrabTemp returning 42 (V42 tmp28) (a long lifetime temp) called for Inline stloc first use temp. [000619] -A---------- * ASG int [000618] D------N---- +--* LCL_VAR int V42 tmp28 [000617] ------------ \--* CAST int <- uint <- long [000616] ------------ \--* RSZ long [000614] ------------ +--* MUL long [000611] ------------ | +--* ADD long [000608] ------------ | | +--* RSZ long [000606] ------------ | | | +--* MUL long [000604] ------------ | | | | +--* LCL_VAR long V41 tmp27 [000605] ---------U-- | | | | \--* CAST long <- ulong <- uint [000047] ------------ | | | | \--* LCL_VAR int V06 loc2 [000607] ------------ | | | \--* CNS_INT int 32 [000610] ------------ | | \--* CNS_INT long 1 [000613] ---------U-- | \--* CAST long <- ulong <- uint [000612] ------------ | \--* LCL_VAR int V40 tmp26 [000615] ------------ \--* CNS_INT int 32 [ 0] 34 (0x022) ldloc.0 [ 1] 35 (0x023) ldarg.0 [ 2] 36 (0x024) ldarg.1 [ 3] 37 (0x025) rem.un [ 2] 38 (0x026) ceq [ 1] 40 (0x028) call 06005CF9 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000625] I-CXG------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000626] ---X-------- arg0 \--* PUTARG_TYPE bool [000624] ---X-------- \--* EQ int [000620] ------------ +--* LCL_VAR int V42 tmp28 [000623] ---X-------- \--* UMOD int [000621] ------------ +--* LCL_VAR int V06 loc2 [000622] ------------ \--* LCL_VAR int V40 tmp26 [ 0] 45 (0x02d) ldloc.0 [ 1] 46 (0x02e) ret Inlinee Return expression (before normalization) => [000627] ------------ * LCL_VAR int V42 tmp28 Inlinee Return expression (after normalization) => [000627] ------------ * LCL_VAR int V42 tmp28 *************** Inline @[000586] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB53 [0061] 1 1 [000..02F) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB53 [000..02F) (return), preds={} succs={} ***** BB53 [000602] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000603] ------------ arg0 \--* PUTARG_TYPE bool [000601] ------------ \--* EQ int [000599] N--------U-- +--* GT int [000597] ------------ | +--* LCL_VAR int V40 tmp26 [000598] ------------ | \--* CNS_INT int 0x7FFFFFFF [000600] ------------ \--* CNS_INT int 0 ***** BB53 [000619] -A---------- * ASG int [000618] D------N---- +--* LCL_VAR int V42 tmp28 [000617] ------------ \--* CAST int <- uint <- long [000616] ------------ \--* RSZ long [000614] ------------ +--* MUL long [000611] ------------ | +--* ADD long [000608] ------------ | | +--* RSZ long [000606] ------------ | | | +--* MUL long [000604] ------------ | | | | +--* LCL_VAR long V41 tmp27 [000605] ---------U-- | | | | \--* CAST long <- ulong <- uint [000047] ------------ | | | | \--* LCL_VAR int V06 loc2 [000607] ------------ | | | \--* CNS_INT int 32 [000610] ------------ | | \--* CNS_INT long 1 [000613] ---------U-- | \--* CAST long <- ulong <- uint [000612] ------------ | \--* LCL_VAR int V40 tmp26 [000615] ------------ \--* CNS_INT int 32 ***** BB53 [000625] I-CXG------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000626] ---X-------- arg0 \--* PUTARG_TYPE bool [000624] ---X-------- \--* EQ int [000620] ------------ +--* LCL_VAR int V42 tmp28 [000623] ---X-------- \--* UMOD int [000621] ------------ +--* LCL_VAR int V06 loc2 [000622] ------------ \--* LCL_VAR int V40 tmp26 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000586] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000586] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000586] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000586] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000586] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000586] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000586] ----------- Arguments setup: STMT00105 (IL 0x064... ???) [000629] -A-X-------- * ASG int [000628] D------N---- +--* LCL_VAR int V40 tmp26 [000583] ---X-------- \--* ARR_LENGTH int [000582] ------------ \--* LCL_VAR ref V39 tmp25 STMT00106 (IL 0x064... ???) [000631] -A-XG------- * ASG long [000630] D------N---- +--* LCL_VAR long V41 tmp27 [000585] ---XG------- \--* FIELD long _fastModMultiplier [000584] ------------ \--* LCL_VAR ref V00 this Inlinee method body: STMT00102 (IL 0x064... ???) [000602] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000603] ------------ arg0 \--* PUTARG_TYPE bool [000601] ------------ \--* EQ int [000599] N--------U-- +--* GT int [000597] ------------ | +--* LCL_VAR int V40 tmp26 [000598] ------------ | \--* CNS_INT int 0x7FFFFFFF [000600] ------------ \--* CNS_INT int 0 STMT00103 (IL 0x064... ???) [000619] -A---------- * ASG int [000618] D------N---- +--* LCL_VAR int V42 tmp28 [000617] ------------ \--* CAST int <- uint <- long [000616] ------------ \--* RSZ long [000614] ------------ +--* MUL long [000611] ------------ | +--* ADD long [000608] ------------ | | +--* RSZ long [000606] ------------ | | | +--* MUL long [000604] ------------ | | | | +--* LCL_VAR long V41 tmp27 [000605] ---------U-- | | | | \--* CAST long <- ulong <- uint [000047] ------------ | | | | \--* LCL_VAR int V06 loc2 [000607] ------------ | | | \--* CNS_INT int 32 [000610] ------------ | | \--* CNS_INT long 1 [000613] ---------U-- | \--* CAST long <- ulong <- uint [000612] ------------ | \--* LCL_VAR int V40 tmp26 [000615] ------------ \--* CNS_INT int 32 STMT00104 (IL 0x064... ???) [000625] I-CXG------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000626] ---X-------- arg0 \--* PUTARG_TYPE bool [000624] ---X-------- \--* EQ int [000620] ------------ +--* LCL_VAR int V42 tmp28 [000623] ---X-------- \--* UMOD int [000621] ------------ +--* LCL_VAR int V06 loc2 [000622] ------------ \--* LCL_VAR int V40 tmp26 fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000586] is [000627] ------------ * LCL_VAR int V42 tmp28 Successfully inlined System.Collections.HashHelpers:FastMod(int,int,long):int (47 IL bytes) (depth 2) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Collections.HashHelpers:FastMod(int,int,long):int' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00102 in BB08: STMT00102 (IL 0x064... ???) [000602] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000603] ------------ arg0 \--* PUTARG_TYPE bool [000601] ------------ \--* EQ int [000599] N--------U-- +--* GT int [000597] ------------ | +--* LCL_VAR int V40 tmp26 [000598] ------------ | \--* CNS_INT int 0x7FFFFFFF [000600] ------------ \--* CNS_INT int 0 Argument #0: [000601] ------------ * EQ int [000599] N--------U-- +--* GT int [000597] ------------ | +--* LCL_VAR int V40 tmp26 [000598] ------------ | \--* CNS_INT int 0x7FFFFFFF [000600] ------------ \--* CNS_INT int 0 INLINER: inlineInfo.tokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Diagnostics.Debug:Assert(bool) : IL to import: IL_0000 02 ldarg.0 IL_0001 7e 68 02 00 04 ldsfld 0x4000268 IL_0006 7e 68 02 00 04 ldsfld 0x4000268 IL_000b 28 fb 5c 00 06 call 0x6005CFB IL_0010 2a ret INLINER impTokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Diagnostics.Debug:Assert(bool) weight= 10 : state 3 [ ldarg.0 ] weight=159 : state 112 [ ldsfld ] weight=159 : state 112 [ ldsfld ] weight= 79 : state 40 [ call ] weight= 19 : state 42 [ ret ] Inline candidate looks like a wrapper method. Multiplier increased to 1. Inline candidate is mostly loads and stores. Multiplier increased to 4. Inline candidate callsite is boring. Multiplier increased to 5.3. calleeNativeSizeEstimate=426 callsiteNativeSizeEstimate=85 benefit multiplier=5.3 threshold=450 Native estimate for function size is within threshold for inlining 42.6 <= 45 (multiplier = 5.3) Jump targets: none New Basic Block BB54 [0062] created. BB54 [000..011) Basic block list for 'System.Diagnostics.Debug:Assert(bool)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB54 [0062] 1 1 [000..011) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000602] Starting PHASE Pre-import *************** Inline @[000602] Finishing PHASE Pre-import *************** Inline @[000602] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000602] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB54 [0062] 1 1 [000..011) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB54 [000..011) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000602] Starting PHASE Importation *************** In impImport() for System.Diagnostics.Debug:Assert(bool) impImportBlockPending for BB54 Importing BB54 (PC=000) of 'System.Diagnostics.Debug:Assert(bool)' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 43 (V43 tmp29) called for Inlining Arg. [ 1] 1 (0x001) ldsfld 04000268 [ 2] 6 (0x006) ldsfld 04000268 [ 3] 11 (0x00b) call 06005CFB In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000639] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000640] ------------ arg0 +--* PUTARG_TYPE bool [000634] ------------ | \--* LCL_VAR int V43 tmp29 [000636] #---G------- arg1 +--* IND ref [000635] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [000638] #---G------- arg2 \--* IND ref [000637] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [ 0] 16 (0x010) ret *************** Inline @[000602] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB54 [0062] 1 1 [000..011) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB54 [000..011) (return), preds={} succs={} ***** BB54 [000639] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000640] ------------ arg0 +--* PUTARG_TYPE bool [000634] ------------ | \--* LCL_VAR int V43 tmp29 [000636] #---G------- arg1 +--* IND ref [000635] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [000638] #---G------- arg2 \--* IND ref [000637] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000602] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000602] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000602] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000602] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000602] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000602] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000602] ----------- Arguments setup: STMT00108 (IL 0x064... ???) [000642] -A---------- * ASG bool [000641] D------N---- +--* LCL_VAR bool V43 tmp29 [000633] ------------ \--* CAST int <- bool <- int [000601] ------------ \--* EQ int [000599] N--------U-- +--* GT int [000597] ------------ | +--* LCL_VAR int V40 tmp26 [000598] ------------ | \--* CNS_INT int 0x7FFFFFFF [000600] ------------ \--* CNS_INT int 0 Inlinee method body: STMT00107 (IL 0x064... ???) [000639] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000640] ------------ arg0 +--* PUTARG_TYPE bool [000634] ------------ | \--* LCL_VAR int V43 tmp29 [000636] #---G------- arg1 +--* IND ref [000635] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [000638] #---G------- arg2 \--* IND ref [000637] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Diagnostics.Debug:Assert(bool) (17 IL bytes) (depth 3) [profitable inline] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'profitable inline' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Diagnostics.Debug:Assert(bool)' INLINER: during 'fgInline' result 'success' reason 'profitable inline' Expanding INLINE_CANDIDATE in statement STMT00107 in BB08: STMT00107 (IL 0x064... ???) [000639] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000640] ------------ arg0 +--* PUTARG_TYPE bool [000634] ------------ | \--* LCL_VAR int V43 tmp29 [000636] #---G------- arg1 +--* IND ref [000635] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [000638] #---G------- arg2 \--* IND ref [000637] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] Argument #0: is a local var [000634] ------------ * LCL_VAR int V43 tmp29 Argument #1: has global refs [000636] #---G------- * IND ref [000635] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] Argument #2: has global refs [000638] #---G------- * IND ref [000637] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] INLINER: inlineInfo.tokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool,System.String,System.String) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Diagnostics.Debug:Assert(bool,System.String,System.String) : IL to import: IL_0000 02 ldarg.0 IL_0001 2d 07 brtrue.s 7 (IL_000a) IL_0003 03 ldarg.1 IL_0004 04 ldarg.2 IL_0005 28 fe 5c 00 06 call 0x6005CFE IL_000a 2a ret INLINER impTokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool,System.String,System.String) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Diagnostics.Debug:Assert(bool,System.String,System.String) Jump targets: IL_000a New Basic Block BB55 [0063] created. BB55 [000..003) New Basic Block BB56 [0064] created. BB56 [003..00A) New Basic Block BB57 [0065] created. BB57 [00A..00B) Basic block list for 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB55 [0063] 1 1 [000..003)-> BB57 ( cond ) BB56 [0064] 1 1 [003..00A) BB57 [0065] 2 1 [00A..00B) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000639] Starting PHASE Pre-import *************** Inline @[000639] Finishing PHASE Pre-import *************** Inline @[000639] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000639] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB55 [0063] 1 1 [000..003)-> BB57 ( cond ) BB56 [0064] 1 1 [003..00A) BB57 [0065] 2 1 [00A..00B) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB55 [000..003) -> BB57 (cond), preds={} succs={BB56,BB57} ------------ BB56 [003..00A), preds={} succs={BB57} ------------ BB57 [00A..00B) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000639] Starting PHASE Importation *************** In impImport() for System.Diagnostics.Debug:Assert(bool,System.String,System.String) impImportBlockPending for BB55 Importing BB55 (PC=000) of 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) brtrue.s [000647] ------------ * JTRUE void [000646] ------------ \--* NE int [000644] ------------ +--* LCL_VAR int V43 tmp29 [000645] ------------ \--* CNS_INT int 0 impImportBlockPending for BB56 impImportBlockPending for BB57 Importing BB57 (PC=010) of 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' [ 0] 10 (0x00a) ret Importing BB56 (PC=003) of 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' [ 0] 3 (0x003) ldarg.1 lvaGrabTemp returning 44 (V44 tmp30) called for Inlining Arg. Marked V44 as a single def temp lvaSetClass: setting class for V44 to (00000000D1FFAB1E) System.String [ 1] 4 (0x004) ldarg.2 lvaGrabTemp returning 45 (V45 tmp31) called for Inlining Arg. Marked V45 as a single def temp lvaSetClass: setting class for V45 to (00000000D1FFAB1E) System.String [ 2] 5 (0x005) call 06005CFE In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' calling 'System.Diagnostics.Debug:Fail(System.String,System.String)' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' [000650] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000648] ------------ arg0 +--* LCL_VAR ref V44 tmp30 [000649] ------------ arg1 \--* LCL_VAR ref V45 tmp31 impImportBlockPending for BB57 ** Note: inlinee IL was partially imported -- imported 10 of 11 bytes of method IL *************** Inline @[000639] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB55 [0063] 1 1 [000..003)-> BB57 ( cond ) i BB56 [0064] 1 1 [003..00A) i BB57 [0065] 2 1 [00A..00B) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB55 [000..003) -> BB57 (cond), preds={} succs={BB56,BB57} ***** BB55 [000647] ------------ * JTRUE void [000646] ------------ \--* NE int [000644] ------------ +--* LCL_VAR int V43 tmp29 [000645] ------------ \--* CNS_INT int 0 ------------ BB56 [003..00A), preds={} succs={BB57} ***** BB56 [000650] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000648] ------------ arg0 +--* LCL_VAR ref V44 tmp30 [000649] ------------ arg1 \--* LCL_VAR ref V45 tmp31 ------------ BB57 [00A..00B) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000639] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000639] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000639] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000639] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000639] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000639] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000639] ----------- Arguments setup: STMT00111 (IL 0x064... ???) [000652] -A--G------- * ASG ref [000651] D------N---- +--* LCL_VAR ref V44 tmp30 [000636] #---G------- \--* IND ref [000635] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] STMT00112 (IL 0x064... ???) [000654] -A--G------- * ASG ref [000653] D------N---- +--* LCL_VAR ref V45 tmp31 [000638] #---G------- \--* IND ref [000637] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] Inlinee method body:New Basic Block BB58 [0066] created. Convert bbJumpKind of BB57 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB55 [0063] 1 1 [064..065)-> BB57 ( cond ) i BB56 [0064] 1 1 [064..065) i BB57 [0065] 2 1 [064..065) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB55 [064..065) -> BB57 (cond), preds={} succs={BB56,BB57} ***** BB55 STMT00109 (IL 0x064... ???) [000647] ------------ * JTRUE void [000646] ------------ \--* NE int [000644] ------------ +--* LCL_VAR int V43 tmp29 [000645] ------------ \--* CNS_INT int 0 ------------ BB56 [064..065), preds={} succs={BB57} ***** BB56 STMT00110 (IL 0x064... ???) [000650] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000648] ------------ arg0 +--* LCL_VAR ref V44 tmp30 [000649] ------------ arg1 \--* LCL_VAR ref V45 tmp31 ------------ BB57 [064..065), preds={} succs={BB58} ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Diagnostics.Debug:Assert(bool,System.String,System.String) (11 IL bytes) (depth 4) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement STMT00104 in BB58: STMT00104 (IL 0x064... ???) [000625] I-CXG------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000626] ---X-------- arg0 \--* PUTARG_TYPE bool [000624] ---X-------- \--* EQ int [000620] ------------ +--* LCL_VAR int V42 tmp28 [000623] ---X-------- \--* UMOD int [000621] ------------ +--* LCL_VAR int V06 loc2 [000622] ------------ \--* LCL_VAR int V40 tmp26 Argument #0: has side effects [000624] ---X-------- * EQ int [000620] ------------ +--* LCL_VAR int V42 tmp28 [000623] ---X-------- \--* UMOD int [000621] ------------ +--* LCL_VAR int V06 loc2 [000622] ------------ \--* LCL_VAR int V40 tmp26 INLINER: inlineInfo.tokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Diagnostics.Debug:Assert(bool) : IL to import: IL_0000 02 ldarg.0 IL_0001 7e 68 02 00 04 ldsfld 0x4000268 IL_0006 7e 68 02 00 04 ldsfld 0x4000268 IL_000b 28 fb 5c 00 06 call 0x6005CFB IL_0010 2a ret INLINER impTokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Diagnostics.Debug:Assert(bool) weight= 10 : state 3 [ ldarg.0 ] weight=159 : state 112 [ ldsfld ] weight=159 : state 112 [ ldsfld ] weight= 79 : state 40 [ call ] weight= 19 : state 42 [ ret ] Inline candidate looks like a wrapper method. Multiplier increased to 1. Inline candidate is mostly loads and stores. Multiplier increased to 4. Inline candidate callsite is boring. Multiplier increased to 5.3. calleeNativeSizeEstimate=426 callsiteNativeSizeEstimate=85 benefit multiplier=5.3 threshold=450 Native estimate for function size is within threshold for inlining 42.6 <= 45 (multiplier = 5.3) Jump targets: none New Basic Block BB59 [0067] created. BB59 [000..011) Basic block list for 'System.Diagnostics.Debug:Assert(bool)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB59 [0067] 1 1 [000..011) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000625] Starting PHASE Pre-import *************** Inline @[000625] Finishing PHASE Pre-import *************** Inline @[000625] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000625] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB59 [0067] 1 1 [000..011) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB59 [000..011) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000625] Starting PHASE Importation *************** In impImport() for System.Diagnostics.Debug:Assert(bool) impImportBlockPending for BB59 Importing BB59 (PC=000) of 'System.Diagnostics.Debug:Assert(bool)' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 46 (V46 tmp32) called for Inlining Arg. [ 1] 1 (0x001) ldsfld 04000268 [ 2] 6 (0x006) ldsfld 04000268 [ 3] 11 (0x00b) call 06005CFB In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000662] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000663] ------------ arg0 +--* PUTARG_TYPE bool [000657] ------------ | \--* LCL_VAR int V46 tmp32 [000659] #---G------- arg1 +--* IND ref [000658] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [000661] #---G------- arg2 \--* IND ref [000660] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [ 0] 16 (0x010) ret *************** Inline @[000625] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB59 [0067] 1 1 [000..011) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB59 [000..011) (return), preds={} succs={} ***** BB59 [000662] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000663] ------------ arg0 +--* PUTARG_TYPE bool [000657] ------------ | \--* LCL_VAR int V46 tmp32 [000659] #---G------- arg1 +--* IND ref [000658] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [000661] #---G------- arg2 \--* IND ref [000660] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000625] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000625] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000625] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000625] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000625] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000625] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000625] ----------- Arguments setup: STMT00114 (IL 0x064... ???) [000665] -A-X-------- * ASG bool [000664] D------N---- +--* LCL_VAR bool V46 tmp32 [000656] ---X-------- \--* CAST int <- bool <- int [000624] ---X-------- \--* EQ int [000620] ------------ +--* LCL_VAR int V42 tmp28 [000623] ---X-------- \--* UMOD int [000621] ------------ +--* LCL_VAR int V06 loc2 [000622] ------------ \--* LCL_VAR int V40 tmp26 Inlinee method body: STMT00113 (IL 0x064... ???) [000662] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000663] ------------ arg0 +--* PUTARG_TYPE bool [000657] ------------ | \--* LCL_VAR int V46 tmp32 [000659] #---G------- arg1 +--* IND ref [000658] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [000661] #---G------- arg2 \--* IND ref [000660] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Diagnostics.Debug:Assert(bool) (17 IL bytes) (depth 3) [profitable inline] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'profitable inline' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Diagnostics.Debug:Assert(bool)' INLINER: during 'fgInline' result 'success' reason 'profitable inline' Expanding INLINE_CANDIDATE in statement STMT00113 in BB58: STMT00113 (IL 0x064... ???) [000662] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000663] ------------ arg0 +--* PUTARG_TYPE bool [000657] ------------ | \--* LCL_VAR int V46 tmp32 [000659] #---G------- arg1 +--* IND ref [000658] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [000661] #---G------- arg2 \--* IND ref [000660] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] Argument #0: is a local var [000657] ------------ * LCL_VAR int V46 tmp32 Argument #1: has global refs [000659] #---G------- * IND ref [000658] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] Argument #2: has global refs [000661] #---G------- * IND ref [000660] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] INLINER: inlineInfo.tokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool,System.String,System.String) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Diagnostics.Debug:Assert(bool,System.String,System.String) : IL to import: IL_0000 02 ldarg.0 IL_0001 2d 07 brtrue.s 7 (IL_000a) IL_0003 03 ldarg.1 IL_0004 04 ldarg.2 IL_0005 28 fe 5c 00 06 call 0x6005CFE IL_000a 2a ret INLINER impTokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool,System.String,System.String) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Diagnostics.Debug:Assert(bool,System.String,System.String) Jump targets: IL_000a New Basic Block BB60 [0068] created. BB60 [000..003) New Basic Block BB61 [0069] created. BB61 [003..00A) New Basic Block BB62 [0070] created. BB62 [00A..00B) Basic block list for 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB60 [0068] 1 1 [000..003)-> BB62 ( cond ) BB61 [0069] 1 1 [003..00A) BB62 [0070] 2 1 [00A..00B) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000662] Starting PHASE Pre-import *************** Inline @[000662] Finishing PHASE Pre-import *************** Inline @[000662] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000662] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB60 [0068] 1 1 [000..003)-> BB62 ( cond ) BB61 [0069] 1 1 [003..00A) BB62 [0070] 2 1 [00A..00B) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB60 [000..003) -> BB62 (cond), preds={} succs={BB61,BB62} ------------ BB61 [003..00A), preds={} succs={BB62} ------------ BB62 [00A..00B) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000662] Starting PHASE Importation *************** In impImport() for System.Diagnostics.Debug:Assert(bool,System.String,System.String) impImportBlockPending for BB60 Importing BB60 (PC=000) of 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) brtrue.s [000670] ------------ * JTRUE void [000669] ------------ \--* NE int [000667] ------------ +--* LCL_VAR int V46 tmp32 [000668] ------------ \--* CNS_INT int 0 impImportBlockPending for BB61 impImportBlockPending for BB62 Importing BB62 (PC=010) of 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' [ 0] 10 (0x00a) ret Importing BB61 (PC=003) of 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' [ 0] 3 (0x003) ldarg.1 lvaGrabTemp returning 47 (V47 tmp33) called for Inlining Arg. Marked V47 as a single def temp lvaSetClass: setting class for V47 to (00000000D1FFAB1E) System.String [ 1] 4 (0x004) ldarg.2 lvaGrabTemp returning 48 (V48 tmp34) called for Inlining Arg. Marked V48 as a single def temp lvaSetClass: setting class for V48 to (00000000D1FFAB1E) System.String [ 2] 5 (0x005) call 06005CFE In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' calling 'System.Diagnostics.Debug:Fail(System.String,System.String)' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' [000673] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000671] ------------ arg0 +--* LCL_VAR ref V47 tmp33 [000672] ------------ arg1 \--* LCL_VAR ref V48 tmp34 impImportBlockPending for BB62 ** Note: inlinee IL was partially imported -- imported 10 of 11 bytes of method IL *************** Inline @[000662] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB60 [0068] 1 1 [000..003)-> BB62 ( cond ) i BB61 [0069] 1 1 [003..00A) i BB62 [0070] 2 1 [00A..00B) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB60 [000..003) -> BB62 (cond), preds={} succs={BB61,BB62} ***** BB60 [000670] ------------ * JTRUE void [000669] ------------ \--* NE int [000667] ------------ +--* LCL_VAR int V46 tmp32 [000668] ------------ \--* CNS_INT int 0 ------------ BB61 [003..00A), preds={} succs={BB62} ***** BB61 [000673] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000671] ------------ arg0 +--* LCL_VAR ref V47 tmp33 [000672] ------------ arg1 \--* LCL_VAR ref V48 tmp34 ------------ BB62 [00A..00B) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000662] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000662] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000662] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000662] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000662] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000662] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000662] ----------- Arguments setup: STMT00117 (IL 0x064... ???) [000675] -A--G------- * ASG ref [000674] D------N---- +--* LCL_VAR ref V47 tmp33 [000659] #---G------- \--* IND ref [000658] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] STMT00118 (IL 0x064... ???) [000677] -A--G------- * ASG ref [000676] D------N---- +--* LCL_VAR ref V48 tmp34 [000661] #---G------- \--* IND ref [000660] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] Inlinee method body:New Basic Block BB63 [0071] created. Convert bbJumpKind of BB62 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB60 [0068] 1 1 [064..065)-> BB62 ( cond ) i BB61 [0069] 1 1 [064..065) i BB62 [0070] 2 1 [064..065) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB60 [064..065) -> BB62 (cond), preds={} succs={BB61,BB62} ***** BB60 STMT00115 (IL 0x064... ???) [000670] ------------ * JTRUE void [000669] ------------ \--* NE int [000667] ------------ +--* LCL_VAR int V46 tmp32 [000668] ------------ \--* CNS_INT int 0 ------------ BB61 [064..065), preds={} succs={BB62} ***** BB61 STMT00116 (IL 0x064... ???) [000673] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000671] ------------ arg0 +--* LCL_VAR ref V47 tmp33 [000672] ------------ arg1 \--* LCL_VAR ref V48 tmp34 ------------ BB62 [064..065), preds={} succs={BB63} ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Diagnostics.Debug:Assert(bool,System.String,System.String) (11 IL bytes) (depth 4) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000587] with [000627] [000587] --C--------- * RET_EXPR int (inl return expr [000627]) Inserting the inline return expression [000627] ------------ * LCL_VAR int V42 tmp28 Replacing the return expression placeholder [000049] with [000592] [000049] --C--------- * RET_EXPR byref (inl return expr [000592]) Inserting the inline return expression [000592] ------------ * LCL_VAR byref V38 tmp24 Expanding INLINE_CANDIDATE in statement STMT00061 in BB10: STMT00061 (IL ???... ???) [000352] I-C-G------- * CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default (exactContextHnd=0x00000000D1FFAB1E) [000383] ------------ arg0 \--* RUNTIMELOOKUP long 0xd1ffab1e class [000382] ------------ \--* LCL_VAR long V25 tmp11 INLINER: inlineInfo.tokenLookupContextHandle for System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon]:get_Default():System.Collections.Generic.EqualityComparer`1[__Canon] set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon]:get_Default():System.Collections.Generic.EqualityComparer`1[__Canon] : IL to import: IL_0000 7e f4 0b 00 0a ldsfld 0xA000BF4 IL_0005 2a ret INLINER impTokenLookupContextHandle for System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon]:get_Default():System.Collections.Generic.EqualityComparer`1[__Canon] is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon]:get_Default():System.Collections.Generic.EqualityComparer`1[__Canon] Jump targets: none New Basic Block BB64 [0072] created. BB64 [000..006) Basic block list for 'System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon]:get_Default():System.Collections.Generic.EqualityComparer`1[__Canon]' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB64 [0072] 1 1 [000..006) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000352] Starting PHASE Pre-import *************** Inline @[000352] Finishing PHASE Pre-import *************** Inline @[000352] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000352] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB64 [0072] 1 1 [000..006) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB64 [000..006) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000352] Starting PHASE Importation *************** In impImport() for System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon]:get_Default():System.Collections.Generic.EqualityComparer`1[__Canon] impImportBlockPending for BB64 Importing BB64 (PC=000) of 'System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon]:get_Default():System.Collections.Generic.EqualityComparer`1[__Canon]' [ 0] 0 (0x000) ldsfld 0A000BF4 ** Note: inlinee IL was partially imported -- imported 0 of 6 bytes of method IL *************** Inline @[000352] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB64 [0072] 1 1 [000..006) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB64 [000..006) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000352] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000352] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000352] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000352] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000352] Starting PHASE Post-import *************** Inline @[000352] Finishing PHASE Post-import Inlining [000352] failed, so bashing STMT00061 to NOP INLINER: during 'fgInline' result 'failed this call site' reason 'ldfld needs helper' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon]:get_Default():System.Collections.Generic.EqualityComparer`1[__Canon]' INLINER: during 'fgInline' result 'failed this call site' reason 'ldfld needs helper' Replacing the return expression placeholder [000384] with [000352] [000384] --C--------- * RET_EXPR ref (inl return expr [000352]) Inserting the inline return expression [000352] --C-G------- * CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default [000383] ------------ arg0 \--* RUNTIMELOOKUP long 0xd1ffab1e class [000382] ------------ \--* LCL_VAR long V25 tmp11 Named Intrinsic System.Collections.Generic.EqualityComparer`1.get_Default: Recognized Special intrinsic: looking for exact type returned by System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon]:get_Default():System.Collections.Generic.EqualityComparer`1[__Canon] Named Intrinsic System.Collections.Generic.EqualityComparer`1.get_Default: Recognized Special intrinsic for type System.__Canon: type not final, so deferring opt **** Late devirt opportunity [000425] --CXG------- * CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals [000418] ------------ this in rcx +--* LCL_VAR ref V12 loc8 [000423] ---XG------- arg1 +--* FIELD ref key [000422] ---XG------- | \--* ADDR byref [000421] ---XG--N---- | \--* INDEX struct [000419] ------------ | +--* LCL_VAR ref V04 loc0 [000420] ------------ | \--* LCL_VAR int V09 loc5 [000424] ------------ arg2 \--* LCL_VAR ref V01 arg1 impDevirtualizeCall: Trying to devirtualize virtual call: class for 'this' is System.Collections.Generic.EqualityComparer`1[__Canon] (attrib 20020400) base method is System.Collections.Generic.EqualityComparer`1[__Canon]::Equals devirt to System.Collections.Generic.EqualityComparer`1[__Canon]::Equals -- inexact or not final [000425] --CXG------- * CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals [000418] ------------ this in rcx +--* LCL_VAR ref V12 loc8 [000423] ---XG------- arg1 +--* FIELD ref key [000422] ---XG------- | \--* ADDR byref [000421] ---XG--N---- | \--* INDEX struct [000419] ------------ | +--* LCL_VAR ref V04 loc0 [000420] ------------ | \--* LCL_VAR int V09 loc5 [000424] ------------ arg2 \--* LCL_VAR ref V01 arg1 Class not final or exact, and method not final No guarded devirt during late devirtualization Expanding INLINE_CANDIDATE in statement STMT00076 in BB17: STMT00076 (IL ???... ???) [000440] I-C-G------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException (exactContextHnd=0x00000000D1FFAB1E) [000474] ------------ arg0 +--* RUNTIMELOOKUP long 0xd1ffab1e method [000473] ------------ | \--* LCL_VAR long V28 tmp14 [000455] ------------ arg1 \--* LCL_VAR ref V27 tmp13 Argument #0: is a local var [000455] ------------ * LCL_VAR ref V27 tmp13 INLINER: inlineInfo.tokenLookupContextHandle for System.ThrowHelper:ThrowAddingDuplicateWithKeyArgumentException(System.__Canon) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.ThrowHelper:ThrowAddingDuplicateWithKeyArgumentException(System.__Canon) : IL to import: IL_0000 02 ldarg.0 IL_0001 8c 08 00 00 1b box 0x1B000008 IL_0006 28 39 19 00 06 call 0x6001939 IL_000b 7a throw INLINER impTokenLookupContextHandle for System.ThrowHelper:ThrowAddingDuplicateWithKeyArgumentException(System.__Canon) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.ThrowHelper:ThrowAddingDuplicateWithKeyArgumentException(System.__Canon) Jump targets: none New Basic Block BB65 [0073] created. BB65 [000..00C) Basic block list for 'System.ThrowHelper:ThrowAddingDuplicateWithKeyArgumentException(System.__Canon)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB65 [0073] 1 0 [000..00C) (throw ) rare ----------------------------------------------------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.ThrowHelper:ThrowAddingDuplicateWithKeyArgumentException(System.__Canon)' INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' Expanding INLINE_CANDIDATE in statement STMT00068 in BB20: STMT00068 (IL 0x170...0x175) [000417] I-C-G------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported (exactContextHnd=0x00000000D1FFAB1E) INLINER: inlineInfo.tokenLookupContextHandle for System.ThrowHelper:ThrowInvalidOperationException_ConcurrentOperationsNotSupported() set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.ThrowHelper:ThrowInvalidOperationException_ConcurrentOperationsNotSupported() : IL to import: IL_0000 28 64 17 00 06 call 0x6001764 IL_0005 73 dc 10 00 06 newobj 0x60010DC IL_000a 7a throw INLINER impTokenLookupContextHandle for System.ThrowHelper:ThrowInvalidOperationException_ConcurrentOperationsNotSupported() is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.ThrowHelper:ThrowInvalidOperationException_ConcurrentOperationsNotSupported() Jump targets: none New Basic Block BB66 [0073] created. BB66 [000..00B) Basic block list for 'System.ThrowHelper:ThrowInvalidOperationException_ConcurrentOperationsNotSupported()' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB66 [0073] 1 0 [000..00B) (throw ) rare ----------------------------------------------------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.ThrowHelper:ThrowInvalidOperationException_ConcurrentOperationsNotSupported()' INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' Querying runtime about current class of field Entry[System.__Canon,System.__Canon].key (declared as System.__Canon) Field's current class not available Expanding INLINE_CANDIDATE in statement STMT00056 in BB27: STMT00056 (IL ???... ???) [000295] I-C-G------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException (exactContextHnd=0x00000000D1FFAB1E) [000329] ------------ arg0 +--* RUNTIMELOOKUP long 0xd1ffab1e method [000328] ------------ | \--* LCL_VAR long V23 tmp9 [000310] ------------ arg1 \--* LCL_VAR ref V22 tmp8 Argument #0: is a local var [000310] ------------ * LCL_VAR ref V22 tmp8 INLINER: inlineInfo.tokenLookupContextHandle for System.ThrowHelper:ThrowAddingDuplicateWithKeyArgumentException(System.__Canon) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.ThrowHelper:ThrowAddingDuplicateWithKeyArgumentException(System.__Canon) : IL to import: IL_0000 02 ldarg.0 IL_0001 8c 08 00 00 1b box 0x1B000008 IL_0006 28 39 19 00 06 call 0x6001939 IL_000b 7a throw INLINER impTokenLookupContextHandle for System.ThrowHelper:ThrowAddingDuplicateWithKeyArgumentException(System.__Canon) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.ThrowHelper:ThrowAddingDuplicateWithKeyArgumentException(System.__Canon) Jump targets: none New Basic Block BB67 [0073] created. BB67 [000..00C) Basic block list for 'System.ThrowHelper:ThrowAddingDuplicateWithKeyArgumentException(System.__Canon)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB67 [0073] 1 0 [000..00C) (throw ) rare ----------------------------------------------------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.ThrowHelper:ThrowAddingDuplicateWithKeyArgumentException(System.__Canon)' INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' Expanding INLINE_CANDIDATE in statement STMT00043 in BB30: STMT00043 (IL 0x1DD...0x1E2) [000233] I-C-G------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported (exactContextHnd=0x00000000D1FFAB1E) INLINER: inlineInfo.tokenLookupContextHandle for System.ThrowHelper:ThrowInvalidOperationException_ConcurrentOperationsNotSupported() set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.ThrowHelper:ThrowInvalidOperationException_ConcurrentOperationsNotSupported() : IL to import: IL_0000 28 64 17 00 06 call 0x6001764 IL_0005 73 dc 10 00 06 newobj 0x60010DC IL_000a 7a throw INLINER impTokenLookupContextHandle for System.ThrowHelper:ThrowInvalidOperationException_ConcurrentOperationsNotSupported() is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.ThrowHelper:ThrowInvalidOperationException_ConcurrentOperationsNotSupported() Jump targets: none New Basic Block BB68 [0073] created. BB68 [000..00B) Basic block list for 'System.ThrowHelper:ThrowInvalidOperationException_ConcurrentOperationsNotSupported()' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB68 [0073] 1 0 [000..00B) (throw ) rare ----------------------------------------------------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.ThrowHelper:ThrowInvalidOperationException_ConcurrentOperationsNotSupported()' INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' Expanding INLINE_CANDIDATE in statement STMT00036 in BB32: STMT00036 (IL 0x1F5...0x22E) [000188] I-CXG------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000189] ---XG------- arg0 +--* PUTARG_TYPE bool [000186] ---XG------- | \--* EQ int [000184] ---XG------- | +--* LT int [000182] ---XG------- | | +--* SUB int [000175] ------------ | | | +--* CNS_INT int -3 [000181] ---XG------- | | | \--* FIELD int next [000180] ---XG------- | | | \--* ADDR byref [000179] ---XG--N---- | | | \--* INDEX struct [000176] ------------ | | | +--* LCL_VAR ref V04 loc0 [000178] ---XG------- | | | \--* FIELD int _freeList [000177] ------------ | | | \--* LCL_VAR ref V00 this [000183] ------------ | | \--* CNS_INT int -1 [000185] ------------ | \--* CNS_INT int 0 [000187] ------------ arg1 \--* CNS_STR ref Argument #0: has global refs has side effects [000186] ---XG------- * EQ int [000184] ---XG------- +--* LT int [000182] ---XG------- | +--* SUB int [000175] ------------ | | +--* CNS_INT int -3 [000181] ---XG------- | | \--* FIELD int next [000180] ---XG------- | | \--* ADDR byref [000179] ---XG--N---- | | \--* INDEX struct [000176] ------------ | | +--* LCL_VAR ref V04 loc0 [000178] ---XG------- | | \--* FIELD int _freeList [000177] ------------ | | \--* LCL_VAR ref V00 this [000183] ------------ | \--* CNS_INT int -1 [000185] ------------ \--* CNS_INT int 0 Argument #1: is a constant [000187] ------------ * CNS_STR ref INLINER: inlineInfo.tokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool,System.String) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Diagnostics.Debug:Assert(bool,System.String) : IL to import: IL_0000 02 ldarg.0 IL_0001 03 ldarg.1 IL_0002 7e 68 02 00 04 ldsfld 0x4000268 IL_0007 28 fb 5c 00 06 call 0x6005CFB IL_000c 2a ret INLINER impTokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool,System.String) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Diagnostics.Debug:Assert(bool,System.String) Jump targets: none New Basic Block BB69 [0073] created. BB69 [000..00D) Basic block list for 'System.Diagnostics.Debug:Assert(bool,System.String)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB69 [0073] 1 1 [000..00D) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000188] Starting PHASE Pre-import *************** Inline @[000188] Finishing PHASE Pre-import *************** Inline @[000188] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000188] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB69 [0073] 1 1 [000..00D) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB69 [000..00D) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000188] Starting PHASE Importation *************** In impImport() for System.Diagnostics.Debug:Assert(bool,System.String) impImportBlockPending for BB69 Importing BB69 (PC=000) of 'System.Diagnostics.Debug:Assert(bool,System.String)' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 49 (V49 tmp35) called for Inlining Arg. [ 1] 1 (0x001) ldarg.1 [ 2] 2 (0x002) ldsfld 04000268 [ 3] 7 (0x007) call 06005CFB In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000685] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000686] ------------ arg0 +--* PUTARG_TYPE bool [000681] ------------ | \--* LCL_VAR int V49 tmp35 [000682] ------------ arg1 +--* CNS_STR ref [000684] #---G------- arg2 \--* IND ref [000683] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [ 0] 12 (0x00c) ret *************** Inline @[000188] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB69 [0073] 1 1 [000..00D) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB69 [000..00D) (return), preds={} succs={} ***** BB69 [000685] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000686] ------------ arg0 +--* PUTARG_TYPE bool [000681] ------------ | \--* LCL_VAR int V49 tmp35 [000682] ------------ arg1 +--* CNS_STR ref [000684] #---G------- arg2 \--* IND ref [000683] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000188] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000188] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000188] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000188] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000188] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000188] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000188] ----------- Arguments setup: STMT00120 (IL 0x1F5... ???) [000688] -A-XG------- * ASG bool [000687] D------N---- +--* LCL_VAR bool V49 tmp35 [000680] ---XG------- \--* CAST int <- bool <- int [000186] ---XG------- \--* EQ int [000184] ---XG------- +--* LT int [000182] ---XG------- | +--* SUB int [000175] ------------ | | +--* CNS_INT int -3 [000181] ---XG------- | | \--* FIELD int next [000180] ---XG------- | | \--* ADDR byref [000179] ---XG--N---- | | \--* INDEX struct [000176] ------------ | | +--* LCL_VAR ref V04 loc0 [000178] ---XG------- | | \--* FIELD int _freeList [000177] ------------ | | \--* LCL_VAR ref V00 this [000183] ------------ | \--* CNS_INT int -1 [000185] ------------ \--* CNS_INT int 0 Inlinee method body: STMT00119 (IL 0x1F5... ???) [000685] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000686] ------------ arg0 +--* PUTARG_TYPE bool [000681] ------------ | \--* LCL_VAR int V49 tmp35 [000682] ------------ arg1 +--* CNS_STR ref [000684] #---G------- arg2 \--* IND ref [000683] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Diagnostics.Debug:Assert(bool,System.String) (13 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Diagnostics.Debug:Assert(bool,System.String)' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement STMT00119 in BB32: STMT00119 (IL 0x1F5... ???) [000685] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000686] ------------ arg0 +--* PUTARG_TYPE bool [000681] ------------ | \--* LCL_VAR int V49 tmp35 [000682] ------------ arg1 +--* CNS_STR ref [000684] #---G------- arg2 \--* IND ref [000683] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] Argument #0: is a local var [000681] ------------ * LCL_VAR int V49 tmp35 Argument #1: is a constant [000682] ------------ * CNS_STR ref Argument #2: has global refs [000684] #---G------- * IND ref [000683] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] INLINER: inlineInfo.tokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool,System.String,System.String) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Diagnostics.Debug:Assert(bool,System.String,System.String) : IL to import: IL_0000 02 ldarg.0 IL_0001 2d 07 brtrue.s 7 (IL_000a) IL_0003 03 ldarg.1 IL_0004 04 ldarg.2 IL_0005 28 fe 5c 00 06 call 0x6005CFE IL_000a 2a ret INLINER impTokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool,System.String,System.String) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Diagnostics.Debug:Assert(bool,System.String,System.String) Jump targets: IL_000a New Basic Block BB70 [0074] created. BB70 [000..003) New Basic Block BB71 [0075] created. BB71 [003..00A) New Basic Block BB72 [0076] created. BB72 [00A..00B) Basic block list for 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB70 [0074] 1 1 [000..003)-> BB72 ( cond ) BB71 [0075] 1 1 [003..00A) BB72 [0076] 2 1 [00A..00B) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000685] Starting PHASE Pre-import *************** Inline @[000685] Finishing PHASE Pre-import *************** Inline @[000685] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000685] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB70 [0074] 1 1 [000..003)-> BB72 ( cond ) BB71 [0075] 1 1 [003..00A) BB72 [0076] 2 1 [00A..00B) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB70 [000..003) -> BB72 (cond), preds={} succs={BB71,BB72} ------------ BB71 [003..00A), preds={} succs={BB72} ------------ BB72 [00A..00B) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000685] Starting PHASE Importation *************** In impImport() for System.Diagnostics.Debug:Assert(bool,System.String,System.String) impImportBlockPending for BB70 Importing BB70 (PC=000) of 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) brtrue.s [000693] ------------ * JTRUE void [000692] ------------ \--* NE int [000690] ------------ +--* LCL_VAR int V49 tmp35 [000691] ------------ \--* CNS_INT int 0 impImportBlockPending for BB71 impImportBlockPending for BB72 Importing BB72 (PC=010) of 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' [ 0] 10 (0x00a) ret Importing BB71 (PC=003) of 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' [ 0] 3 (0x003) ldarg.1 [ 1] 4 (0x004) ldarg.2 lvaGrabTemp returning 50 (V50 tmp36) called for Inlining Arg. Marked V50 as a single def temp lvaSetClass: setting class for V50 to (00000000D1FFAB1E) System.String [ 2] 5 (0x005) call 06005CFE In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' calling 'System.Diagnostics.Debug:Fail(System.String,System.String)' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' [000696] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000694] ------------ arg0 +--* CNS_STR ref [000695] ------------ arg1 \--* LCL_VAR ref V50 tmp36 impImportBlockPending for BB72 ** Note: inlinee IL was partially imported -- imported 10 of 11 bytes of method IL *************** Inline @[000685] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB70 [0074] 1 1 [000..003)-> BB72 ( cond ) i BB71 [0075] 1 1 [003..00A) i BB72 [0076] 2 1 [00A..00B) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB70 [000..003) -> BB72 (cond), preds={} succs={BB71,BB72} ***** BB70 [000693] ------------ * JTRUE void [000692] ------------ \--* NE int [000690] ------------ +--* LCL_VAR int V49 tmp35 [000691] ------------ \--* CNS_INT int 0 ------------ BB71 [003..00A), preds={} succs={BB72} ***** BB71 [000696] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000694] ------------ arg0 +--* CNS_STR ref [000695] ------------ arg1 \--* LCL_VAR ref V50 tmp36 ------------ BB72 [00A..00B) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000685] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000685] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000685] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000685] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000685] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000685] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000685] ----------- Arguments setup: STMT00123 (IL 0x1F5... ???) [000698] -A--G------- * ASG ref [000697] D------N---- +--* LCL_VAR ref V50 tmp36 [000684] #---G------- \--* IND ref [000683] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] Inlinee method body:New Basic Block BB73 [0077] created. Convert bbJumpKind of BB72 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB70 [0074] 1 1 [1F5..1F6)-> BB72 ( cond ) i BB71 [0075] 1 1 [1F5..1F6) i BB72 [0076] 2 1 [1F5..1F6) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB70 [1F5..1F6) -> BB72 (cond), preds={} succs={BB71,BB72} ***** BB70 STMT00121 (IL 0x1F5... ???) [000693] ------------ * JTRUE void [000692] ------------ \--* NE int [000690] ------------ +--* LCL_VAR int V49 tmp35 [000691] ------------ \--* CNS_INT int 0 ------------ BB71 [1F5..1F6), preds={} succs={BB72} ***** BB71 STMT00122 (IL 0x1F5... ???) [000696] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000694] ------------ arg0 +--* CNS_STR ref [000695] ------------ arg1 \--* LCL_VAR ref V50 tmp36 ------------ BB72 [1F5..1F6), preds={} succs={BB73} ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Diagnostics.Debug:Assert(bool,System.String,System.String) (11 IL bytes) (depth 2) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement STMT00032 in BB34: STMT00032 (IL 0x252...0x25F) [000164] I-C-G------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize (exactContextHnd=0x00000000D1FFAB1E) [000163] ------------ this in rcx \--* LCL_VAR ref V00 this thisArg: is a local var [000163] ------------ * LCL_VAR ref V00 this INLINER: inlineInfo.tokenLookupContextHandle for System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize():this set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize():this : IL to import: IL_0000 02 ldarg.0 IL_0001 02 ldarg.0 IL_0002 7b 07 0c 00 0a ldfld 0xA000C07 IL_0007 28 a6 63 00 06 call 0x60063A6 IL_000c 16 ldc.i4.0 IL_000d 28 2d 0c 00 0a call 0xA000C2D IL_0012 2a ret INLINER impTokenLookupContextHandle for System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize():this is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize():this weight= 10 : state 3 [ ldarg.0 ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 79 : state 40 [ call ] weight= 15 : state 23 [ ldc.i4.0 ] weight= 79 : state 40 [ call ] weight= 19 : state 42 [ ret ] Inline candidate looks like a wrapper method. Multiplier increased to 1. Inline candidate is mostly loads and stores. Multiplier increased to 4. Inline candidate callsite is boring. Multiplier increased to 5.3. calleeNativeSizeEstimate=233 callsiteNativeSizeEstimate=85 benefit multiplier=5.3 threshold=450 Native estimate for function size is within threshold for inlining 23.3 <= 45 (multiplier = 5.3) Jump targets: none New Basic Block BB74 [0078] created. BB74 [000..013) Basic block list for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize():this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB74 [0078] 1 1 [000..013) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000164] Starting PHASE Pre-import *************** Inline @[000164] Finishing PHASE Pre-import *************** Inline @[000164] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000164] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB74 [0078] 1 1 [000..013) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB74 [000..013) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000164] Starting PHASE Importation *************** In impImport() for System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize():this impImportBlockPending for BB74 Importing BB74 (PC=000) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize():this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldarg.0 [ 2] 2 (0x002) ldfld 0A000C07 [ 2] 7 (0x007) call 060063A6 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 [000702] I-CXG------- * CALL int System.Collections.HashHelpers.ExpandPrime (exactContextHnd=0x00000000D1FFAB1E) [000701] ---XG------- arg0 \--* FIELD int _count [000700] ------------ \--* LCL_VAR ref V00 this [ 2] 12 (0x00c) ldc.i4.0 0 [ 3] 13 (0x00d) call 0A000C2D In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize():this' calling 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize(int,bool):this' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' [000705] --C-G------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [000163] ------------ this in rcx +--* LCL_VAR ref V00 this [000703] --C--------- arg1 +--* RET_EXPR int (inl return expr [000702]) [000706] ------------ arg2 \--* PUTARG_TYPE bool [000704] ------------ \--* CNS_INT int 0 [ 0] 18 (0x012) ret *************** Inline @[000164] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB74 [0078] 1 1 [000..013) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB74 [000..013) (return), preds={} succs={} ***** BB74 [000702] I-CXG------- * CALL int System.Collections.HashHelpers.ExpandPrime (exactContextHnd=0x00000000D1FFAB1E) [000701] ---XG------- arg0 \--* FIELD int _count [000700] ------------ \--* LCL_VAR ref V00 this ***** BB74 [000705] --C-G------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [000163] ------------ this in rcx +--* LCL_VAR ref V00 this [000703] --C--------- arg1 +--* RET_EXPR int (inl return expr [000702]) [000706] ------------ arg2 \--* PUTARG_TYPE bool [000704] ------------ \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000164] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000164] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000164] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000164] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000164] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000164] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000164] ----------- Arguments setup: Inlinee method body: STMT00124 (IL 0x252... ???) [000702] I-CXG------- * CALL int System.Collections.HashHelpers.ExpandPrime (exactContextHnd=0x00000000D1FFAB1E) [000701] ---XG------- arg0 \--* FIELD int _count [000700] ------------ \--* LCL_VAR ref V00 this STMT00125 (IL 0x252... ???) [000705] --C-G------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [000163] ------------ this in rcx +--* LCL_VAR ref V00 this [000703] --C--------- arg1 +--* RET_EXPR int (inl return expr [000702]) [000706] ------------ arg2 \--* PUTARG_TYPE bool [000704] ------------ \--* CNS_INT int 0 fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize():this (19 IL bytes) (depth 1) [profitable inline] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'profitable inline' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize():this' INLINER: during 'fgInline' result 'success' reason 'profitable inline' Expanding INLINE_CANDIDATE in statement STMT00124 in BB34: STMT00124 (IL 0x252... ???) [000702] I-CXG------- * CALL int System.Collections.HashHelpers.ExpandPrime (exactContextHnd=0x00000000D1FFAB1E) [000701] ---XG------- arg0 \--* FIELD int _count [000700] ------------ \--* LCL_VAR ref V00 this Argument #0: has global refs has side effects [000701] ---XG------- * FIELD int _count [000700] ------------ \--* LCL_VAR ref V00 this INLINER: inlineInfo.tokenLookupContextHandle for System.Collections.HashHelpers:ExpandPrime(int):int set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Collections.HashHelpers:ExpandPrime(int):int : IL to import: IL_0000 18 ldc.i4.2 IL_0001 02 ldarg.0 IL_0002 5a mul IL_0003 0a stloc.0 IL_0004 06 ldloc.0 IL_0005 20 c3 ff ff 7f ldc.i4 0x7FFFFFC3 IL_000a 36 29 ble.un.s 41 (IL_0035) IL_000c 20 c3 ff ff 7f ldc.i4 0x7FFFFFC3 IL_0011 02 ldarg.0 IL_0012 31 21 ble.s 33 (IL_0035) IL_0014 20 c3 ff ff 7f ldc.i4 0x7FFFFFC3 IL_0019 20 c3 ff ff 7f ldc.i4 0x7FFFFFC3 IL_001e 28 a5 63 00 06 call 0x60063A5 IL_0023 fe 01 ceq IL_0025 72 e4 40 03 70 ldstr 0x700340E4 IL_002a 28 fa 5c 00 06 call 0x6005CFA IL_002f 20 c3 ff ff 7f ldc.i4 0x7FFFFFC3 IL_0034 2a ret IL_0035 06 ldloc.0 IL_0036 28 a5 63 00 06 call 0x60063A5 IL_003b 2a ret INLINER impTokenLookupContextHandle for System.Collections.HashHelpers:ExpandPrime(int):int is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Collections.HashHelpers:ExpandPrime(int):int weight= 34 : state 25 [ ldc.i4.2 ] weight= 10 : state 3 [ ldarg.0 ] weight= -9 : state 78 [ mul ] weight= 20 : state 199 [ stloc.0 -> ldloc.0 ] weight= 38 : state 33 [ ldc.i4 ] weight=147 : state 54 [ ble.un.s ] weight= 38 : state 33 [ ldc.i4 ] weight= 10 : state 3 [ ldarg.0 ] weight= 53 : state 49 [ ble.s ] weight= 38 : state 33 [ ldc.i4 ] weight= 38 : state 33 [ ldc.i4 ] weight= 79 : state 40 [ call ] weight= 20 : state 168 [ ceq ] weight= 66 : state 102 [ ldstr ] weight= 79 : state 40 [ call ] weight= 38 : state 33 [ ldc.i4 ] weight= 19 : state 42 [ ret ] weight= 12 : state 7 [ ldloc.0 ] weight= 79 : state 40 [ call ] weight= 19 : state 42 [ ret ] Inline candidate looks like a wrapper method. Multiplier increased to 1. Inline candidate has an arg that feeds a constant test. Multiplier increased to 2. Inline candidate callsite is boring. Multiplier increased to 3.3. calleeNativeSizeEstimate=828 callsiteNativeSizeEstimate=85 benefit multiplier=3.3 threshold=280 Native estimate for function size exceeds threshold for inlining 82.8 > 28 (multiplier = 3.3) Inline expansion aborted, inline not profitable Inlining [000702] failed, so bashing STMT00124 to NOP INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Collections.HashHelpers:ExpandPrime(int):int' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Replacing the return expression placeholder [000703] with [000702] [000703] --C--------- * RET_EXPR int (inl return expr [000702]) Inserting the inline return expression [000702] --CXG------- * CALL int System.Collections.HashHelpers.ExpandPrime [000701] ---XG------- arg0 \--* FIELD int _count [000700] ------------ \--* LCL_VAR ref V00 this Expanding INLINE_CANDIDATE in statement STMT00033 in BB34: STMT00033 (IL 0x258... ???) [000167] I-C-G------- * CALL byref System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].GetBucket (exactContextHnd=0x00000000D1FFAB1E) [000165] ------------ this in rcx +--* LCL_VAR ref V00 this [000166] ------------ arg1 \--* LCL_VAR int V06 loc2 thisArg: is a local var [000165] ------------ * LCL_VAR ref V00 this Argument #1: is a local var [000166] ------------ * LCL_VAR int V06 loc2 INLINER: inlineInfo.tokenLookupContextHandle for System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:GetBucket(int):byref:this set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:GetBucket(int):byref:this : IL to import: IL_0000 02 ldarg.0 IL_0001 7b 21 0c 00 0a ldfld 0xA000C21 IL_0006 0a stloc.0 IL_0007 06 ldloc.0 IL_0008 03 ldarg.1 IL_0009 06 ldloc.0 IL_000a 8e ldlen IL_000b 69 conv.i4 IL_000c 02 ldarg.0 IL_000d 7b 2b 0c 00 0a ldfld 0xA000C2B IL_0012 28 a8 63 00 06 call 0x60063A8 IL_0017 8f 41 01 00 02 ldelema 0x2000141 IL_001c 2a ret INLINER impTokenLookupContextHandle for System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:GetBucket(int):byref:this is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:GetBucket(int):byref:this Jump targets: none New Basic Block BB75 [0079] created. BB75 [000..01D) lvaGrabTemp returning 51 (V51 tmp37) (a long lifetime temp) called for Inline return value spill temp. Basic block list for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:GetBucket(int):byref:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB75 [0079] 1 1 [000..01D) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000167] Starting PHASE Pre-import *************** Inline @[000167] Finishing PHASE Pre-import *************** Inline @[000167] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000167] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB75 [0079] 1 1 [000..01D) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB75 [000..01D) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000167] Starting PHASE Importation *************** In impImport() for System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:GetBucket(int):byref:this impImportBlockPending for BB75 Importing BB75 (PC=000) of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:GetBucket(int):byref:this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 0A000C21 [ 1] 6 (0x006) stloc.0 lvaGrabTemp returning 52 (V52 tmp38) (a long lifetime temp) called for Inline stloc first use temp. Marked V52 as a single def temp lvaSetClass: setting class for V52 to (00000000D1FFAB1E) System.Int32[] Querying runtime about current class of field System.Collections.Generic.Dictionary`2[System.__Canon,System.__Canon]._buckets (declared as System.Int32[]) Field's current class not available [000711] -A-XG------- * ASG ref [000710] D------N---- +--* LCL_VAR ref V52 tmp38 [000709] ---XG------- \--* FIELD ref _buckets [000165] ------------ \--* LCL_VAR ref V00 this [ 0] 7 (0x007) ldloc.0 [ 1] 8 (0x008) ldarg.1 [ 2] 9 (0x009) ldloc.0 [ 3] 10 (0x00a) ldlen [ 3] 11 (0x00b) conv.i4 [ 3] 12 (0x00c) ldarg.0 [ 4] 13 (0x00d) ldfld 0A000C2B [ 4] 18 (0x012) call 060063A8 In Compiler::impImportCall: opcode is call, kind=0, callRetType is int, structSize is 0 [000717] I-CXG------- * CALL int System.Collections.HashHelpers.FastMod (exactContextHnd=0x00000000D1FFAB1E) [000166] ------------ arg0 +--* LCL_VAR int V06 loc2 [000714] ---X-------- arg1 +--* ARR_LENGTH int [000713] ------------ | \--* LCL_VAR ref V52 tmp38 [000716] ---XG------- arg2 \--* FIELD long _fastModMultiplier [000715] ------------ \--* LCL_VAR ref V00 this [ 2] 23 (0x017) ldelema 02000141 [ 1] 28 (0x01c) ret Inlinee Return expression (before normalization) => [000720] --CXG------- * ADDR byref [000719] --CXG--N---- \--* INDEX int [000712] ------------ +--* LCL_VAR ref V52 tmp38 [000718] --C--------- \--* RET_EXPR int (inl return expr [000717]) [000722] -ACXG------- * ASG byref [000721] D------N---- +--* LCL_VAR byref V51 tmp37 [000720] --CXG------- \--* ADDR byref [000719] --CXG--N---- \--* INDEX int [000712] ------------ +--* LCL_VAR ref V52 tmp38 [000718] --C--------- \--* RET_EXPR int (inl return expr [000717]) Inlinee Return expression (after normalization) => [000723] ------------ * LCL_VAR byref V51 tmp37 *************** Inline @[000167] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB75 [0079] 1 1 [000..01D) (return) i idxlen ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB75 [000..01D) (return), preds={} succs={} ***** BB75 [000711] -A-XG------- * ASG ref [000710] D------N---- +--* LCL_VAR ref V52 tmp38 [000709] ---XG------- \--* FIELD ref _buckets [000165] ------------ \--* LCL_VAR ref V00 this ***** BB75 [000717] I-CXG------- * CALL int System.Collections.HashHelpers.FastMod (exactContextHnd=0x00000000D1FFAB1E) [000166] ------------ arg0 +--* LCL_VAR int V06 loc2 [000714] ---X-------- arg1 +--* ARR_LENGTH int [000713] ------------ | \--* LCL_VAR ref V52 tmp38 [000716] ---XG------- arg2 \--* FIELD long _fastModMultiplier [000715] ------------ \--* LCL_VAR ref V00 this ***** BB75 [000722] -ACXG------- * ASG byref [000721] D------N---- +--* LCL_VAR byref V51 tmp37 [000720] --CXG------- \--* ADDR byref [000719] --CXG--N---- \--* INDEX int [000712] ------------ +--* LCL_VAR ref V52 tmp38 [000718] --C--------- \--* RET_EXPR int (inl return expr [000717]) ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000167] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000167] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000167] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000167] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000167] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000167] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000167] ----------- Arguments setup: Inlinee method body: STMT00126 (IL 0x258... ???) [000711] -A-XG------- * ASG ref [000710] D------N---- +--* LCL_VAR ref V52 tmp38 [000709] ---XG------- \--* FIELD ref _buckets [000165] ------------ \--* LCL_VAR ref V00 this STMT00127 (IL 0x258... ???) [000717] I-CXG------- * CALL int System.Collections.HashHelpers.FastMod (exactContextHnd=0x00000000D1FFAB1E) [000166] ------------ arg0 +--* LCL_VAR int V06 loc2 [000714] ---X-------- arg1 +--* ARR_LENGTH int [000713] ------------ | \--* LCL_VAR ref V52 tmp38 [000716] ---XG------- arg2 \--* FIELD long _fastModMultiplier [000715] ------------ \--* LCL_VAR ref V00 this STMT00128 (IL 0x258... ???) [000722] -ACXG------- * ASG byref [000721] D------N---- +--* LCL_VAR byref V51 tmp37 [000720] --CXG------- \--* ADDR byref [000719] --CXG--N---- \--* INDEX int [000712] ------------ +--* LCL_VAR ref V52 tmp38 [000718] --C--------- \--* RET_EXPR int (inl return expr [000717]) fgInlineAppendStatements: nulling out gc ref inlinee locals. STMT00129 (IL 0x258... ???) [000726] -A---------- * ASG ref [000725] D------N---- +--* LCL_VAR ref V52 tmp38 [000724] ------------ \--* CNS_INT ref null Return expression for call at [000167] is [000723] ------------ * LCL_VAR byref V51 tmp37 Successfully inlined System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:GetBucket(int):byref:this (29 IL bytes) (depth 1) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:GetBucket(int):byref:this' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Querying runtime about current class of field System.Collections.Generic.Dictionary`2[System.__Canon,System.__Canon]._buckets (declared as System.Int32[]) Field's current class not available Expanding INLINE_CANDIDATE in statement STMT00127 in BB34: STMT00127 (IL 0x258... ???) [000717] I-CXG------- * CALL int System.Collections.HashHelpers.FastMod (exactContextHnd=0x00000000D1FFAB1E) [000166] ------------ arg0 +--* LCL_VAR int V06 loc2 [000714] ---X-------- arg1 +--* ARR_LENGTH int [000713] ------------ | \--* LCL_VAR ref V52 tmp38 [000716] ---XG------- arg2 \--* FIELD long _fastModMultiplier [000715] ------------ \--* LCL_VAR ref V00 this Argument #0: is a local var [000166] ------------ * LCL_VAR int V06 loc2 Argument #1: has side effects [000714] ---X-------- * ARR_LENGTH int [000713] ------------ \--* LCL_VAR ref V52 tmp38 Argument #2: has global refs has side effects [000716] ---XG------- * FIELD long _fastModMultiplier [000715] ------------ \--* LCL_VAR ref V00 this INLINER: inlineInfo.tokenLookupContextHandle for System.Collections.HashHelpers:FastMod(int,int,long):int set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Collections.HashHelpers:FastMod(int,int,long):int : IL to import: IL_0000 03 ldarg.1 IL_0001 20 ff ff ff 7f ldc.i4 0x7FFFFFFF IL_0006 fe 03 cgt.un IL_0008 16 ldc.i4.0 IL_0009 fe 01 ceq IL_000b 28 f9 5c 00 06 call 0x6005CF9 IL_0010 04 ldarg.2 IL_0011 02 ldarg.0 IL_0012 6e conv.u8 IL_0013 5a mul IL_0014 1f 20 ldc.i4.s 0x20 IL_0016 64 shr.un IL_0017 17 ldc.i4.1 IL_0018 6a conv.i8 IL_0019 58 add IL_001a 03 ldarg.1 IL_001b 6e conv.u8 IL_001c 5a mul IL_001d 1f 20 ldc.i4.s 0x20 IL_001f 64 shr.un IL_0020 6d conv.u4 IL_0021 0a stloc.0 IL_0022 06 ldloc.0 IL_0023 02 ldarg.0 IL_0024 03 ldarg.1 IL_0025 5e rem.un IL_0026 fe 01 ceq IL_0028 28 f9 5c 00 06 call 0x6005CF9 IL_002d 06 ldloc.0 IL_002e 2a ret INLINER impTokenLookupContextHandle for System.Collections.HashHelpers:FastMod(int,int,long):int is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Collections.HashHelpers:FastMod(int,int,long):int Jump targets: none New Basic Block BB76 [0080] created. BB76 [000..02F) Basic block list for 'System.Collections.HashHelpers:FastMod(int,int,long):int' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB76 [0080] 1 1 [000..02F) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000717] Starting PHASE Pre-import *************** Inline @[000717] Finishing PHASE Pre-import *************** Inline @[000717] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000717] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB76 [0080] 1 1 [000..02F) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB76 [000..02F) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000717] Starting PHASE Importation *************** In impImport() for System.Collections.HashHelpers:FastMod(int,int,long):int impImportBlockPending for BB76 Importing BB76 (PC=000) of 'System.Collections.HashHelpers:FastMod(int,int,long):int' [ 0] 0 (0x000) ldarg.1 lvaGrabTemp returning 53 (V53 tmp39) called for Inlining Arg. [ 1] 1 (0x001) ldc.i4 2147483647 [ 2] 6 (0x006) cgt.un [ 1] 8 (0x008) ldc.i4.0 0 [ 2] 9 (0x009) ceq [ 1] 11 (0x00b) call 06005CF9 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000733] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000734] ------------ arg0 \--* PUTARG_TYPE bool [000732] ------------ \--* EQ int [000730] N--------U-- +--* GT int [000728] ------------ | +--* LCL_VAR int V53 tmp39 [000729] ------------ | \--* CNS_INT int 0x7FFFFFFF [000731] ------------ \--* CNS_INT int 0 [ 0] 16 (0x010) ldarg.2 lvaGrabTemp returning 54 (V54 tmp40) called for Inlining Arg. [ 1] 17 (0x011) ldarg.0 [ 2] 18 (0x012) conv.u8 [ 2] 19 (0x013) mul [ 1] 20 (0x014) ldc.i4.s 32 [ 2] 22 (0x016) shr.un [ 1] 23 (0x017) ldc.i4.1 1 [ 2] 24 (0x018) conv.i8 Folding long operator with constant nodes into a constant: [000741] ------------ * CAST long <- int [000740] ------------ \--* CNS_INT int 1 Bashed to long constant: [000741] ------------ * CNS_INT long 1 [ 2] 25 (0x019) add [ 1] 26 (0x01a) ldarg.1 [ 2] 27 (0x01b) conv.u8 [ 2] 28 (0x01c) mul [ 1] 29 (0x01d) ldc.i4.s 32 [ 2] 31 (0x01f) shr.un [ 1] 32 (0x020) conv.u4 [ 1] 33 (0x021) stloc.0 lvaGrabTemp returning 55 (V55 tmp41) (a long lifetime temp) called for Inline stloc first use temp. [000750] -A---------- * ASG int [000749] D------N---- +--* LCL_VAR int V55 tmp41 [000748] ------------ \--* CAST int <- uint <- long [000747] ------------ \--* RSZ long [000745] ------------ +--* MUL long [000742] ------------ | +--* ADD long [000739] ------------ | | +--* RSZ long [000737] ------------ | | | +--* MUL long [000735] ------------ | | | | +--* LCL_VAR long V54 tmp40 [000736] ---------U-- | | | | \--* CAST long <- ulong <- uint [000166] ------------ | | | | \--* LCL_VAR int V06 loc2 [000738] ------------ | | | \--* CNS_INT int 32 [000741] ------------ | | \--* CNS_INT long 1 [000744] ---------U-- | \--* CAST long <- ulong <- uint [000743] ------------ | \--* LCL_VAR int V53 tmp39 [000746] ------------ \--* CNS_INT int 32 [ 0] 34 (0x022) ldloc.0 [ 1] 35 (0x023) ldarg.0 [ 2] 36 (0x024) ldarg.1 [ 3] 37 (0x025) rem.un [ 2] 38 (0x026) ceq [ 1] 40 (0x028) call 06005CF9 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000756] I-CXG------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000757] ---X-------- arg0 \--* PUTARG_TYPE bool [000755] ---X-------- \--* EQ int [000751] ------------ +--* LCL_VAR int V55 tmp41 [000754] ---X-------- \--* UMOD int [000752] ------------ +--* LCL_VAR int V06 loc2 [000753] ------------ \--* LCL_VAR int V53 tmp39 [ 0] 45 (0x02d) ldloc.0 [ 1] 46 (0x02e) ret Inlinee Return expression (before normalization) => [000758] ------------ * LCL_VAR int V55 tmp41 Inlinee Return expression (after normalization) => [000758] ------------ * LCL_VAR int V55 tmp41 *************** Inline @[000717] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB76 [0080] 1 1 [000..02F) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB76 [000..02F) (return), preds={} succs={} ***** BB76 [000733] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000734] ------------ arg0 \--* PUTARG_TYPE bool [000732] ------------ \--* EQ int [000730] N--------U-- +--* GT int [000728] ------------ | +--* LCL_VAR int V53 tmp39 [000729] ------------ | \--* CNS_INT int 0x7FFFFFFF [000731] ------------ \--* CNS_INT int 0 ***** BB76 [000750] -A---------- * ASG int [000749] D------N---- +--* LCL_VAR int V55 tmp41 [000748] ------------ \--* CAST int <- uint <- long [000747] ------------ \--* RSZ long [000745] ------------ +--* MUL long [000742] ------------ | +--* ADD long [000739] ------------ | | +--* RSZ long [000737] ------------ | | | +--* MUL long [000735] ------------ | | | | +--* LCL_VAR long V54 tmp40 [000736] ---------U-- | | | | \--* CAST long <- ulong <- uint [000166] ------------ | | | | \--* LCL_VAR int V06 loc2 [000738] ------------ | | | \--* CNS_INT int 32 [000741] ------------ | | \--* CNS_INT long 1 [000744] ---------U-- | \--* CAST long <- ulong <- uint [000743] ------------ | \--* LCL_VAR int V53 tmp39 [000746] ------------ \--* CNS_INT int 32 ***** BB76 [000756] I-CXG------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000757] ---X-------- arg0 \--* PUTARG_TYPE bool [000755] ---X-------- \--* EQ int [000751] ------------ +--* LCL_VAR int V55 tmp41 [000754] ---X-------- \--* UMOD int [000752] ------------ +--* LCL_VAR int V06 loc2 [000753] ------------ \--* LCL_VAR int V53 tmp39 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000717] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000717] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000717] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000717] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000717] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000717] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000717] ----------- Arguments setup: STMT00133 (IL 0x258... ???) [000760] -A-X-------- * ASG int [000759] D------N---- +--* LCL_VAR int V53 tmp39 [000714] ---X-------- \--* ARR_LENGTH int [000713] ------------ \--* LCL_VAR ref V52 tmp38 STMT00134 (IL 0x258... ???) [000762] -A-XG------- * ASG long [000761] D------N---- +--* LCL_VAR long V54 tmp40 [000716] ---XG------- \--* FIELD long _fastModMultiplier [000715] ------------ \--* LCL_VAR ref V00 this Inlinee method body: STMT00130 (IL 0x258... ???) [000733] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000734] ------------ arg0 \--* PUTARG_TYPE bool [000732] ------------ \--* EQ int [000730] N--------U-- +--* GT int [000728] ------------ | +--* LCL_VAR int V53 tmp39 [000729] ------------ | \--* CNS_INT int 0x7FFFFFFF [000731] ------------ \--* CNS_INT int 0 STMT00131 (IL 0x258... ???) [000750] -A---------- * ASG int [000749] D------N---- +--* LCL_VAR int V55 tmp41 [000748] ------------ \--* CAST int <- uint <- long [000747] ------------ \--* RSZ long [000745] ------------ +--* MUL long [000742] ------------ | +--* ADD long [000739] ------------ | | +--* RSZ long [000737] ------------ | | | +--* MUL long [000735] ------------ | | | | +--* LCL_VAR long V54 tmp40 [000736] ---------U-- | | | | \--* CAST long <- ulong <- uint [000166] ------------ | | | | \--* LCL_VAR int V06 loc2 [000738] ------------ | | | \--* CNS_INT int 32 [000741] ------------ | | \--* CNS_INT long 1 [000744] ---------U-- | \--* CAST long <- ulong <- uint [000743] ------------ | \--* LCL_VAR int V53 tmp39 [000746] ------------ \--* CNS_INT int 32 STMT00132 (IL 0x258... ???) [000756] I-CXG------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000757] ---X-------- arg0 \--* PUTARG_TYPE bool [000755] ---X-------- \--* EQ int [000751] ------------ +--* LCL_VAR int V55 tmp41 [000754] ---X-------- \--* UMOD int [000752] ------------ +--* LCL_VAR int V06 loc2 [000753] ------------ \--* LCL_VAR int V53 tmp39 fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000717] is [000758] ------------ * LCL_VAR int V55 tmp41 Successfully inlined System.Collections.HashHelpers:FastMod(int,int,long):int (47 IL bytes) (depth 2) [aggressive inline attribute] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Collections.HashHelpers:FastMod(int,int,long):int' INLINER: during 'fgInline' result 'success' reason 'aggressive inline attribute' Expanding INLINE_CANDIDATE in statement STMT00130 in BB34: STMT00130 (IL 0x258... ???) [000733] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000734] ------------ arg0 \--* PUTARG_TYPE bool [000732] ------------ \--* EQ int [000730] N--------U-- +--* GT int [000728] ------------ | +--* LCL_VAR int V53 tmp39 [000729] ------------ | \--* CNS_INT int 0x7FFFFFFF [000731] ------------ \--* CNS_INT int 0 Argument #0: [000732] ------------ * EQ int [000730] N--------U-- +--* GT int [000728] ------------ | +--* LCL_VAR int V53 tmp39 [000729] ------------ | \--* CNS_INT int 0x7FFFFFFF [000731] ------------ \--* CNS_INT int 0 INLINER: inlineInfo.tokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Diagnostics.Debug:Assert(bool) : IL to import: IL_0000 02 ldarg.0 IL_0001 7e 68 02 00 04 ldsfld 0x4000268 IL_0006 7e 68 02 00 04 ldsfld 0x4000268 IL_000b 28 fb 5c 00 06 call 0x6005CFB IL_0010 2a ret INLINER impTokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Diagnostics.Debug:Assert(bool) weight= 10 : state 3 [ ldarg.0 ] weight=159 : state 112 [ ldsfld ] weight=159 : state 112 [ ldsfld ] weight= 79 : state 40 [ call ] weight= 19 : state 42 [ ret ] Inline candidate looks like a wrapper method. Multiplier increased to 1. Inline candidate is mostly loads and stores. Multiplier increased to 4. Inline candidate callsite is boring. Multiplier increased to 5.3. calleeNativeSizeEstimate=426 callsiteNativeSizeEstimate=85 benefit multiplier=5.3 threshold=450 Native estimate for function size is within threshold for inlining 42.6 <= 45 (multiplier = 5.3) Jump targets: none New Basic Block BB77 [0081] created. BB77 [000..011) Basic block list for 'System.Diagnostics.Debug:Assert(bool)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB77 [0081] 1 1 [000..011) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000733] Starting PHASE Pre-import *************** Inline @[000733] Finishing PHASE Pre-import *************** Inline @[000733] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000733] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB77 [0081] 1 1 [000..011) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB77 [000..011) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000733] Starting PHASE Importation *************** In impImport() for System.Diagnostics.Debug:Assert(bool) impImportBlockPending for BB77 Importing BB77 (PC=000) of 'System.Diagnostics.Debug:Assert(bool)' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 56 (V56 tmp42) called for Inlining Arg. [ 1] 1 (0x001) ldsfld 04000268 [ 2] 6 (0x006) ldsfld 04000268 [ 3] 11 (0x00b) call 06005CFB In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000770] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000771] ------------ arg0 +--* PUTARG_TYPE bool [000765] ------------ | \--* LCL_VAR int V56 tmp42 [000767] #---G------- arg1 +--* IND ref [000766] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [000769] #---G------- arg2 \--* IND ref [000768] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [ 0] 16 (0x010) ret *************** Inline @[000733] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB77 [0081] 1 1 [000..011) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB77 [000..011) (return), preds={} succs={} ***** BB77 [000770] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000771] ------------ arg0 +--* PUTARG_TYPE bool [000765] ------------ | \--* LCL_VAR int V56 tmp42 [000767] #---G------- arg1 +--* IND ref [000766] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [000769] #---G------- arg2 \--* IND ref [000768] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000733] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000733] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000733] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000733] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000733] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000733] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000733] ----------- Arguments setup: STMT00136 (IL 0x258... ???) [000773] -A---------- * ASG bool [000772] D------N---- +--* LCL_VAR bool V56 tmp42 [000764] ------------ \--* CAST int <- bool <- int [000732] ------------ \--* EQ int [000730] N--------U-- +--* GT int [000728] ------------ | +--* LCL_VAR int V53 tmp39 [000729] ------------ | \--* CNS_INT int 0x7FFFFFFF [000731] ------------ \--* CNS_INT int 0 Inlinee method body: STMT00135 (IL 0x258... ???) [000770] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000771] ------------ arg0 +--* PUTARG_TYPE bool [000765] ------------ | \--* LCL_VAR int V56 tmp42 [000767] #---G------- arg1 +--* IND ref [000766] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [000769] #---G------- arg2 \--* IND ref [000768] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Diagnostics.Debug:Assert(bool) (17 IL bytes) (depth 3) [profitable inline] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'profitable inline' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Diagnostics.Debug:Assert(bool)' INLINER: during 'fgInline' result 'success' reason 'profitable inline' Expanding INLINE_CANDIDATE in statement STMT00135 in BB34: STMT00135 (IL 0x258... ???) [000770] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000771] ------------ arg0 +--* PUTARG_TYPE bool [000765] ------------ | \--* LCL_VAR int V56 tmp42 [000767] #---G------- arg1 +--* IND ref [000766] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [000769] #---G------- arg2 \--* IND ref [000768] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] Argument #0: is a local var [000765] ------------ * LCL_VAR int V56 tmp42 Argument #1: has global refs [000767] #---G------- * IND ref [000766] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] Argument #2: has global refs [000769] #---G------- * IND ref [000768] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] INLINER: inlineInfo.tokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool,System.String,System.String) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Diagnostics.Debug:Assert(bool,System.String,System.String) : IL to import: IL_0000 02 ldarg.0 IL_0001 2d 07 brtrue.s 7 (IL_000a) IL_0003 03 ldarg.1 IL_0004 04 ldarg.2 IL_0005 28 fe 5c 00 06 call 0x6005CFE IL_000a 2a ret INLINER impTokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool,System.String,System.String) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Diagnostics.Debug:Assert(bool,System.String,System.String) Jump targets: IL_000a New Basic Block BB78 [0082] created. BB78 [000..003) New Basic Block BB79 [0083] created. BB79 [003..00A) New Basic Block BB80 [0084] created. BB80 [00A..00B) Basic block list for 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB78 [0082] 1 1 [000..003)-> BB80 ( cond ) BB79 [0083] 1 1 [003..00A) BB80 [0084] 2 1 [00A..00B) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000770] Starting PHASE Pre-import *************** Inline @[000770] Finishing PHASE Pre-import *************** Inline @[000770] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000770] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB78 [0082] 1 1 [000..003)-> BB80 ( cond ) BB79 [0083] 1 1 [003..00A) BB80 [0084] 2 1 [00A..00B) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB78 [000..003) -> BB80 (cond), preds={} succs={BB79,BB80} ------------ BB79 [003..00A), preds={} succs={BB80} ------------ BB80 [00A..00B) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000770] Starting PHASE Importation *************** In impImport() for System.Diagnostics.Debug:Assert(bool,System.String,System.String) impImportBlockPending for BB78 Importing BB78 (PC=000) of 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) brtrue.s [000778] ------------ * JTRUE void [000777] ------------ \--* NE int [000775] ------------ +--* LCL_VAR int V56 tmp42 [000776] ------------ \--* CNS_INT int 0 impImportBlockPending for BB79 impImportBlockPending for BB80 Importing BB80 (PC=010) of 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' [ 0] 10 (0x00a) ret Importing BB79 (PC=003) of 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' [ 0] 3 (0x003) ldarg.1 lvaGrabTemp returning 57 (V57 tmp43) called for Inlining Arg. Marked V57 as a single def temp lvaSetClass: setting class for V57 to (00000000D1FFAB1E) System.String [ 1] 4 (0x004) ldarg.2 lvaGrabTemp returning 58 (V58 tmp44) called for Inlining Arg. Marked V58 as a single def temp lvaSetClass: setting class for V58 to (00000000D1FFAB1E) System.String [ 2] 5 (0x005) call 06005CFE In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' calling 'System.Diagnostics.Debug:Fail(System.String,System.String)' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' [000781] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000779] ------------ arg0 +--* LCL_VAR ref V57 tmp43 [000780] ------------ arg1 \--* LCL_VAR ref V58 tmp44 impImportBlockPending for BB80 ** Note: inlinee IL was partially imported -- imported 10 of 11 bytes of method IL *************** Inline @[000770] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB78 [0082] 1 1 [000..003)-> BB80 ( cond ) i BB79 [0083] 1 1 [003..00A) i BB80 [0084] 2 1 [00A..00B) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB78 [000..003) -> BB80 (cond), preds={} succs={BB79,BB80} ***** BB78 [000778] ------------ * JTRUE void [000777] ------------ \--* NE int [000775] ------------ +--* LCL_VAR int V56 tmp42 [000776] ------------ \--* CNS_INT int 0 ------------ BB79 [003..00A), preds={} succs={BB80} ***** BB79 [000781] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000779] ------------ arg0 +--* LCL_VAR ref V57 tmp43 [000780] ------------ arg1 \--* LCL_VAR ref V58 tmp44 ------------ BB80 [00A..00B) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000770] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000770] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000770] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000770] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000770] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000770] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000770] ----------- Arguments setup: STMT00139 (IL 0x258... ???) [000783] -A--G------- * ASG ref [000782] D------N---- +--* LCL_VAR ref V57 tmp43 [000767] #---G------- \--* IND ref [000766] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] STMT00140 (IL 0x258... ???) [000785] -A--G------- * ASG ref [000784] D------N---- +--* LCL_VAR ref V58 tmp44 [000769] #---G------- \--* IND ref [000768] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] Inlinee method body:New Basic Block BB81 [0085] created. Convert bbJumpKind of BB80 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB78 [0082] 1 1 [258..259)-> BB80 ( cond ) i BB79 [0083] 1 1 [258..259) i BB80 [0084] 2 1 [258..259) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB78 [258..259) -> BB80 (cond), preds={} succs={BB79,BB80} ***** BB78 STMT00137 (IL 0x258... ???) [000778] ------------ * JTRUE void [000777] ------------ \--* NE int [000775] ------------ +--* LCL_VAR int V56 tmp42 [000776] ------------ \--* CNS_INT int 0 ------------ BB79 [258..259), preds={} succs={BB80} ***** BB79 STMT00138 (IL 0x258... ???) [000781] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000779] ------------ arg0 +--* LCL_VAR ref V57 tmp43 [000780] ------------ arg1 \--* LCL_VAR ref V58 tmp44 ------------ BB80 [258..259), preds={} succs={BB81} ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Diagnostics.Debug:Assert(bool,System.String,System.String) (11 IL bytes) (depth 4) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement STMT00132 in BB81: STMT00132 (IL 0x258... ???) [000756] I-CXG------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000757] ---X-------- arg0 \--* PUTARG_TYPE bool [000755] ---X-------- \--* EQ int [000751] ------------ +--* LCL_VAR int V55 tmp41 [000754] ---X-------- \--* UMOD int [000752] ------------ +--* LCL_VAR int V06 loc2 [000753] ------------ \--* LCL_VAR int V53 tmp39 Argument #0: has side effects [000755] ---X-------- * EQ int [000751] ------------ +--* LCL_VAR int V55 tmp41 [000754] ---X-------- \--* UMOD int [000752] ------------ +--* LCL_VAR int V06 loc2 [000753] ------------ \--* LCL_VAR int V53 tmp39 INLINER: inlineInfo.tokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Diagnostics.Debug:Assert(bool) : IL to import: IL_0000 02 ldarg.0 IL_0001 7e 68 02 00 04 ldsfld 0x4000268 IL_0006 7e 68 02 00 04 ldsfld 0x4000268 IL_000b 28 fb 5c 00 06 call 0x6005CFB IL_0010 2a ret INLINER impTokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Diagnostics.Debug:Assert(bool) weight= 10 : state 3 [ ldarg.0 ] weight=159 : state 112 [ ldsfld ] weight=159 : state 112 [ ldsfld ] weight= 79 : state 40 [ call ] weight= 19 : state 42 [ ret ] Inline candidate looks like a wrapper method. Multiplier increased to 1. Inline candidate is mostly loads and stores. Multiplier increased to 4. Inline candidate callsite is boring. Multiplier increased to 5.3. calleeNativeSizeEstimate=426 callsiteNativeSizeEstimate=85 benefit multiplier=5.3 threshold=450 Native estimate for function size is within threshold for inlining 42.6 <= 45 (multiplier = 5.3) Jump targets: none New Basic Block BB82 [0086] created. BB82 [000..011) Basic block list for 'System.Diagnostics.Debug:Assert(bool)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB82 [0086] 1 1 [000..011) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000756] Starting PHASE Pre-import *************** Inline @[000756] Finishing PHASE Pre-import *************** Inline @[000756] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000756] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB82 [0086] 1 1 [000..011) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB82 [000..011) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000756] Starting PHASE Importation *************** In impImport() for System.Diagnostics.Debug:Assert(bool) impImportBlockPending for BB82 Importing BB82 (PC=000) of 'System.Diagnostics.Debug:Assert(bool)' [ 0] 0 (0x000) ldarg.0 lvaGrabTemp returning 59 (V59 tmp45) called for Inlining Arg. [ 1] 1 (0x001) ldsfld 04000268 [ 2] 6 (0x006) ldsfld 04000268 [ 3] 11 (0x00b) call 06005CFB In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000793] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000794] ------------ arg0 +--* PUTARG_TYPE bool [000788] ------------ | \--* LCL_VAR int V59 tmp45 [000790] #---G------- arg1 +--* IND ref [000789] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [000792] #---G------- arg2 \--* IND ref [000791] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [ 0] 16 (0x010) ret *************** Inline @[000756] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB82 [0086] 1 1 [000..011) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB82 [000..011) (return), preds={} succs={} ***** BB82 [000793] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000794] ------------ arg0 +--* PUTARG_TYPE bool [000788] ------------ | \--* LCL_VAR int V59 tmp45 [000790] #---G------- arg1 +--* IND ref [000789] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [000792] #---G------- arg2 \--* IND ref [000791] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000756] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000756] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000756] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000756] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000756] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000756] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000756] ----------- Arguments setup: STMT00142 (IL 0x258... ???) [000796] -A-X-------- * ASG bool [000795] D------N---- +--* LCL_VAR bool V59 tmp45 [000787] ---X-------- \--* CAST int <- bool <- int [000755] ---X-------- \--* EQ int [000751] ------------ +--* LCL_VAR int V55 tmp41 [000754] ---X-------- \--* UMOD int [000752] ------------ +--* LCL_VAR int V06 loc2 [000753] ------------ \--* LCL_VAR int V53 tmp39 Inlinee method body: STMT00141 (IL 0x258... ???) [000793] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000794] ------------ arg0 +--* PUTARG_TYPE bool [000788] ------------ | \--* LCL_VAR int V59 tmp45 [000790] #---G------- arg1 +--* IND ref [000789] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [000792] #---G------- arg2 \--* IND ref [000791] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.Diagnostics.Debug:Assert(bool) (17 IL bytes) (depth 3) [profitable inline] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'profitable inline' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Diagnostics.Debug:Assert(bool)' INLINER: during 'fgInline' result 'success' reason 'profitable inline' Expanding INLINE_CANDIDATE in statement STMT00141 in BB81: STMT00141 (IL 0x258... ???) [000793] I-C-G------- * CALL void System.Diagnostics.Debug.Assert (exactContextHnd=0x00000000D1FFAB1E) [000794] ------------ arg0 +--* PUTARG_TYPE bool [000788] ------------ | \--* LCL_VAR int V59 tmp45 [000790] #---G------- arg1 +--* IND ref [000789] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] [000792] #---G------- arg2 \--* IND ref [000791] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] Argument #0: is a local var [000788] ------------ * LCL_VAR int V59 tmp45 Argument #1: has global refs [000790] #---G------- * IND ref [000789] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] Argument #2: has global refs [000792] #---G------- * IND ref [000791] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] INLINER: inlineInfo.tokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool,System.String,System.String) set to 0x00000000D1FFAB1E: Invoking compiler for the inlinee method System.Diagnostics.Debug:Assert(bool,System.String,System.String) : IL to import: IL_0000 02 ldarg.0 IL_0001 2d 07 brtrue.s 7 (IL_000a) IL_0003 03 ldarg.1 IL_0004 04 ldarg.2 IL_0005 28 fe 5c 00 06 call 0x6005CFE IL_000a 2a ret INLINER impTokenLookupContextHandle for System.Diagnostics.Debug:Assert(bool,System.String,System.String) is 0x00000000D1FFAB1E. *************** In fgFindBasicBlocks() for System.Diagnostics.Debug:Assert(bool,System.String,System.String) Jump targets: IL_000a New Basic Block BB83 [0087] created. BB83 [000..003) New Basic Block BB84 [0088] created. BB84 [003..00A) New Basic Block BB85 [0089] created. BB85 [00A..00B) Basic block list for 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB83 [0087] 1 1 [000..003)-> BB85 ( cond ) BB84 [0088] 1 1 [003..00A) BB85 [0089] 2 1 [00A..00B) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000793] Starting PHASE Pre-import *************** Inline @[000793] Finishing PHASE Pre-import *************** Inline @[000793] Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) Computing inlinee profile scale: ... no callee profile data, will use non-pgo weight to scale ... call site not profiled, will use non-pgo weight to scale call site count 100 callee entry count 100 scale 1 Scaling inlinee blocks *************** Inline @[000793] Finishing PHASE Profile incorporation Trees after Profile incorporation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB83 [0087] 1 1 [000..003)-> BB85 ( cond ) BB84 [0088] 1 1 [003..00A) BB85 [0089] 2 1 [00A..00B) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB83 [000..003) -> BB85 (cond), preds={} succs={BB84,BB85} ------------ BB84 [003..00A), preds={} succs={BB85} ------------ BB85 [00A..00B) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000793] Starting PHASE Importation *************** In impImport() for System.Diagnostics.Debug:Assert(bool,System.String,System.String) impImportBlockPending for BB83 Importing BB83 (PC=000) of 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) brtrue.s [000801] ------------ * JTRUE void [000800] ------------ \--* NE int [000798] ------------ +--* LCL_VAR int V59 tmp45 [000799] ------------ \--* CNS_INT int 0 impImportBlockPending for BB84 impImportBlockPending for BB85 Importing BB85 (PC=010) of 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' [ 0] 10 (0x00a) ret Importing BB84 (PC=003) of 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' [ 0] 3 (0x003) ldarg.1 lvaGrabTemp returning 60 (V60 tmp46) called for Inlining Arg. Marked V60 as a single def temp lvaSetClass: setting class for V60 to (00000000D1FFAB1E) System.String [ 1] 4 (0x004) ldarg.2 lvaGrabTemp returning 61 (V61 tmp47) called for Inlining Arg. Marked V61 as a single def temp lvaSetClass: setting class for V61 to (00000000D1FFAB1E) System.String [ 2] 5 (0x005) call 06005CFE In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' for 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' calling 'System.Diagnostics.Debug:Fail(System.String,System.String)' INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'noinline per IL/cached result' [000804] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000802] ------------ arg0 +--* LCL_VAR ref V60 tmp46 [000803] ------------ arg1 \--* LCL_VAR ref V61 tmp47 impImportBlockPending for BB85 ** Note: inlinee IL was partially imported -- imported 10 of 11 bytes of method IL *************** Inline @[000793] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB83 [0087] 1 1 [000..003)-> BB85 ( cond ) i BB84 [0088] 1 1 [003..00A) i BB85 [0089] 2 1 [00A..00B) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB83 [000..003) -> BB85 (cond), preds={} succs={BB84,BB85} ***** BB83 [000801] ------------ * JTRUE void [000800] ------------ \--* NE int [000798] ------------ +--* LCL_VAR int V59 tmp45 [000799] ------------ \--* CNS_INT int 0 ------------ BB84 [003..00A), preds={} succs={BB85} ***** BB84 [000804] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000802] ------------ arg0 +--* LCL_VAR ref V60 tmp46 [000803] ------------ arg1 \--* LCL_VAR ref V61 tmp47 ------------ BB85 [00A..00B) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000793] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000793] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000793] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000793] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000793] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000793] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000793] ----------- Arguments setup: STMT00145 (IL 0x258... ???) [000806] -A--G------- * ASG ref [000805] D------N---- +--* LCL_VAR ref V60 tmp46 [000790] #---G------- \--* IND ref [000789] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] STMT00146 (IL 0x258... ???) [000808] -A--G------- * ASG ref [000807] D------N---- +--* LCL_VAR ref V61 tmp47 [000792] #---G------- \--* IND ref [000791] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] Inlinee method body:New Basic Block BB86 [0090] created. Convert bbJumpKind of BB85 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB83 [0087] 1 1 [258..259)-> BB85 ( cond ) i BB84 [0088] 1 1 [258..259) i BB85 [0089] 2 1 [258..259) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB83 [258..259) -> BB85 (cond), preds={} succs={BB84,BB85} ***** BB83 STMT00143 (IL 0x258... ???) [000801] ------------ * JTRUE void [000800] ------------ \--* NE int [000798] ------------ +--* LCL_VAR int V59 tmp45 [000799] ------------ \--* CNS_INT int 0 ------------ BB84 [258..259), preds={} succs={BB85} ***** BB84 STMT00144 (IL 0x258... ???) [000804] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000802] ------------ arg0 +--* LCL_VAR ref V60 tmp46 [000803] ------------ arg1 \--* LCL_VAR ref V61 tmp47 ------------ BB85 [258..259), preds={} succs={BB86} ------------------------------------------------------------------------------------------------------------------- Successfully inlined System.Diagnostics.Debug:Assert(bool,System.String,System.String) (11 IL bytes) (depth 4) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' calling 'System.Diagnostics.Debug:Assert(bool,System.String,System.String)' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Replacing the return expression placeholder [000718] with [000758] [000718] --C--------- * RET_EXPR int (inl return expr [000758]) Inserting the inline return expression [000758] ------------ * LCL_VAR int V55 tmp41 Replacing the return expression placeholder [000168] with [000723] [000168] --C--------- * RET_EXPR byref (inl return expr [000723]) Inserting the inline return expression [000723] ------------ * LCL_VAR byref V51 tmp37 **************** Inline Tree Inlines into 06006574 [via DefaultPolicy] System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this [0 IL=0009 TR=000533 0600193F] [FAILED: does not return] System.ThrowHelper:ThrowArgumentNullException(int) [0 IL=0024 TR=000528 06006573] [FAILED: unprofitable inline] System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Initialize(int):int:this [1 IL=0039 TR=000013 06005CF9] [profitable inline] System.Diagnostics.Debug:Assert(bool) [2 IL=0011 TR=000541 06005CFB] [below ALWAYS_INLINE size] System.Diagnostics.Debug:Assert(bool,System.String,System.String) [0 IL=0005 TR=000552 06005CFE] [FAILED: noinline per IL/cached result] System.Diagnostics.Debug:Fail(System.String,System.String) [3 IL=0060 TR=000023 06005CFA] [below ALWAYS_INLINE size] System.Diagnostics.Debug:Assert(bool,System.String) [4 IL=0007 TR=000563 06005CFB] [below ALWAYS_INLINE size] System.Diagnostics.Debug:Assert(bool,System.String,System.String) [0 IL=0005 TR=000574 06005CFE] [FAILED: noinline per IL/cached result] System.Diagnostics.Debug:Fail(System.String,System.String) [0 IL=0092 TR=000035 060004E4] [FAILED: target not direct] System.Object:GetHashCode():int:this [5 IL=0102 TR=000048 06006591] [aggressive inline attribute] System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:GetBucket(int):byref:this [6 IL=0018 TR=000586 060063A8] [aggressive inline attribute] System.Collections.HashHelpers:FastMod(int,int,long):int [7 IL=0011 TR=000602 06005CF9] [profitable inline] System.Diagnostics.Debug:Assert(bool) [8 IL=0011 TR=000639 06005CFB] [below ALWAYS_INLINE size] System.Diagnostics.Debug:Assert(bool,System.String,System.String) [0 IL=0005 TR=000650 06005CFE] [FAILED: noinline per IL/cached result] System.Diagnostics.Debug:Fail(System.String,System.String) [9 IL=0040 TR=000625 06005CF9] [profitable inline] System.Diagnostics.Debug:Assert(bool) [10 IL=0011 TR=000662 06005CFB] [below ALWAYS_INLINE size] System.Diagnostics.Debug:Assert(bool,System.String,System.String) [0 IL=0005 TR=000673 06005CFE] [FAILED: noinline per IL/cached result] System.Diagnostics.Debug:Fail(System.String,System.String) [0 IL=0255 TR=000352 06006516] [FAILED: ldfld needs helper] System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon]:get_Default():System.Collections.Generic.EqualityComparer`1[__Canon] [0 IL=0304 TR=000425 06006517] [FAILED: target not direct] System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon]:Equals(System.__Canon,System.__Canon):bool:this [0 IL=0336 TR=000440 0600193A] [FAILED: does not return] System.ThrowHelper:ThrowAddingDuplicateWithKeyArgumentException(System.__Canon) [0 IL=0368 TR=000417 0600195C] [FAILED: does not return] System.ThrowHelper:ThrowInvalidOperationException_ConcurrentOperationsNotSupported() [0 IL=0445 TR=000295 0600193A] [FAILED: does not return] System.ThrowHelper:ThrowAddingDuplicateWithKeyArgumentException(System.__Canon) [0 IL=0477 TR=000233 0600195C] [FAILED: does not return] System.ThrowHelper:ThrowInvalidOperationException_ConcurrentOperationsNotSupported() [11 IL=0532 TR=000188 06005CFA] [below ALWAYS_INLINE size] System.Diagnostics.Debug:Assert(bool,System.String) [12 IL=0007 TR=000685 06005CFB] [below ALWAYS_INLINE size] System.Diagnostics.Debug:Assert(bool,System.String,System.String) [0 IL=0005 TR=000696 06005CFE] [FAILED: noinline per IL/cached result] System.Diagnostics.Debug:Fail(System.String,System.String) [13 IL=0595 TR=000164 06006576] [profitable inline] System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize():this [0 IL=0007 TR=000702 060063A6] [FAILED: unprofitable inline] System.Collections.HashHelpers:ExpandPrime(int):int [0 IL=0013 TR=000705 06006577] [FAILED: noinline per IL/cached result] System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize(int,bool):this [14 IL=0602 TR=000167 06006591] [aggressive inline attribute] System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:GetBucket(int):byref:this [15 IL=0018 TR=000717 060063A8] [aggressive inline attribute] System.Collections.HashHelpers:FastMod(int,int,long):int [16 IL=0011 TR=000733 06005CF9] [profitable inline] System.Diagnostics.Debug:Assert(bool) [17 IL=0011 TR=000770 06005CFB] [below ALWAYS_INLINE size] System.Diagnostics.Debug:Assert(bool,System.String,System.String) [0 IL=0005 TR=000781 06005CFE] [FAILED: noinline per IL/cached result] System.Diagnostics.Debug:Fail(System.String,System.String) [18 IL=0040 TR=000756 06005CF9] [profitable inline] System.Diagnostics.Debug:Assert(bool) [19 IL=0011 TR=000793 06005CFB] [below ALWAYS_INLINE size] System.Diagnostics.Debug:Assert(bool,System.String,System.String) [0 IL=0005 TR=000804 06005CFE] [FAILED: noinline per IL/cached result] System.Diagnostics.Debug:Fail(System.String,System.String) [0 IL=0732 TR=000161 06006577] [FAILED: too many il bytes] System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize(int,bool):this Budget: initialTime=2277, finalTime=2715, initialBudget=22770, currentBudget=23018 Budget: increased by 248 because of force inlines Budget: initialSize=16980, finalSize=18833 *************** Finishing PHASE Morph - Inlining Trees after Morph - Inlining ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 1 [008..00E) i BB03 [0002] 2 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 1 [016..01E) i BB05 [0004] 2 1 [01E..04B) i BB43 [0051] 1 1 [01E..01F)-> BB45 ( cond ) i BB44 [0052] 1 1 [01E..01F) i BB45 [0053] 2 1 [01E..01F) i BB46 [0054] 1 1 [???..???) i internal BB48 [0056] 1 1 [033..034)-> BB50 ( cond ) i BB49 [0057] 1 1 [033..034) i BB50 [0058] 2 1 [033..034) i BB51 [0059] 1 1 [???..???)-> BB07 ( cond ) internal BB06 [0005] 1 1 [04B..054)-> BB08 (always) i BB07 [0006] 1 1 [054..061) i BB08 [0007] 2 1 [061..07A) i idxlen BB55 [0063] 1 1 [064..065)-> BB57 ( cond ) i BB56 [0064] 1 1 [064..065) i BB57 [0065] 2 1 [064..065) i BB58 [0066] 1 1 [???..???) i internal idxlen BB60 [0068] 1 1 [064..065)-> BB62 ( cond ) i BB61 [0069] 1 1 [064..065) i BB62 [0070] 2 1 [064..065) i BB63 [0071] 1 1 [???..???)-> BB21 ( cond ) internal idxlen BB09 [0008] 1 1 [07A..08B)-> BB10 (always) i BB10 [0019] 1 1 [0FF..106) i BB11 [0020] 3 1 [106..110)-> BB31 ( cond ) i idxlen bwd bwd-target BB12 [0021] 1 1 [110..120)-> BB19 ( cond ) i idxlen bwd BB13 [0022] 1 1 [120..137)-> BB19 ( cond ) i idxlen bwd BB14 [0023] 1 1 [137..13B)-> BB16 ( cond ) i bwd BB15 [0024] 1 1 [13B..14B) (return) i idxlen BB16 [0025] 1 1 [14B..14F)-> BB18 ( cond ) i bwd BB17 [0026] 1 1 [14F..155) i bwd BB18 [0027] 2 1 [155..157) (return) i BB19 [0028] 2 1 [157..170)-> BB11 ( cond ) i idxlen bwd BB20 [0029] 1 1 [170..177)-> BB11 (always) i bwd BB21 [0030] 3 1 [177..17E)-> BB31 ( cond ) i idxlen bwd bwd-target BB22 [0031] 1 1 [17E..18E)-> BB29 ( cond ) i idxlen bwd BB23 [0032] 1 1 [18E..1A4)-> BB29 ( cond ) i idxlen bwd BB24 [0033] 1 1 [1A4..1A8)-> BB26 ( cond ) i bwd BB25 [0034] 1 1 [1A8..1B8) (return) i idxlen BB26 [0035] 1 1 [1B8..1BC)-> BB28 ( cond ) i bwd BB27 [0036] 1 1 [1BC..1C2) i bwd BB28 [0037] 2 1 [1C2..1C4) (return) i BB29 [0038] 2 1 [1C4..1DD)-> BB21 ( cond ) i idxlen bwd BB30 [0039] 1 1 [1DD..1E4)-> BB21 (always) i bwd BB31 [0040] 3 1 [1E4..1ED)-> BB33 ( cond ) i BB32 [0041] 1 1 [1ED..243) i BB70 [0074] 1 1 [1F5..1F6)-> BB72 ( cond ) i BB71 [0075] 1 1 [1F5..1F6) i BB72 [0076] 2 1 [1F5..1F6) i BB73 [0077] 1 1 [???..???)-> BB36 (always) internal BB33 [0042] 1 1 [243..252)-> BB35 ( cond ) i idxlen BB34 [0043] 1 1 [252..261) i idxlen BB78 [0082] 1 1 [258..259)-> BB80 ( cond ) i BB79 [0083] 1 1 [258..259) i BB80 [0084] 2 1 [258..259) i BB81 [0085] 1 1 [???..???) i internal idxlen BB83 [0087] 1 1 [258..259)-> BB85 ( cond ) i BB84 [0088] 1 1 [258..259) i BB85 [0089] 2 1 [258..259) i BB86 [0090] 1 1 [???..???) internal idxlen BB35 [0044] 2 1 [261..276) i BB36 [0045] 2 1 [276..2CA) i idxlen BB37 [0046] 1 1 [2CA..2CF)-> BB40 ( cond ) i BB38 [0047] 1 1 [2CF..2D7)-> BB40 ( cond ) i BB39 [0048] 1 1 [2D7..2E1) i idxlen BB40 [0049] 4 1 [2E1..2E3) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 (IL 0x000...0x006) [000003] ------------ * JTRUE void [000002] ------------ \--* NE int [000000] ------------ +--* LCL_VAR ref V01 arg1 [000001] ------------ \--* CNS_INT ref null ------------ BB02 [008..00E), preds={} succs={BB03} ***** BB02 STMT00086 (IL 0x008...0x009) [000533] --C-G------- * CALL void System.ThrowHelper.ThrowArgumentNullException [000532] ------------ arg0 \--* CNS_INT int 4 ------------ BB03 [00E..016) -> BB05 (cond), preds={} succs={BB04,BB05} ***** BB03 STMT00001 (IL 0x00E...0x014) [000008] ---XG------- * JTRUE void [000007] ---XG------- \--* NE int [000005] ---XG------- +--* FIELD ref _buckets [000004] ------------ | \--* LCL_VAR ref V00 this [000006] ------------ \--* CNS_INT ref null ------------ BB04 [016..01E), preds={} succs={BB05} ***** BB04 STMT00085 (IL ???... ???) [000528] --C-G------- * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize [000526] ------------ this in rcx +--* LCL_VAR ref V00 this [000527] ------------ arg1 \--* CNS_INT int 0 ------------ BB05 [01E..04B), preds={} succs={BB43} ***** BB05 STMT00088 (IL 0x01E... ???) [000544] -A-XG------- * ASG bool [000543] D------N---- +--* LCL_VAR bool V33 tmp19 [000535] ---XG------- \--* CAST int <- bool <- int [000012] N--XG----U-- \--* GT int [000010] ---XG------- +--* FIELD ref _buckets [000009] ------------ | \--* LCL_VAR ref V00 this [000011] ------------ \--* CNS_INT ref null ***** BB05 STMT00091 (IL 0x01E... ???) [000554] -A--G------- * ASG ref [000553] D------N---- +--* LCL_VAR ref V34 tmp20 [000538] #---G------- \--* IND ref [000537] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB05 STMT00092 (IL 0x01E... ???) [000556] -A--G------- * ASG ref [000555] D------N---- +--* LCL_VAR ref V35 tmp21 [000540] #---G------- \--* IND ref [000539] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ------------ BB43 [01E..01F) -> BB45 (cond), preds={} succs={BB44,BB45} ***** BB43 STMT00089 (IL 0x01E... ???) [000549] ------------ * JTRUE void [000548] ------------ \--* NE int [000546] ------------ +--* LCL_VAR int V33 tmp19 [000547] ------------ \--* CNS_INT int 0 ------------ BB44 [01E..01F), preds={} succs={BB45} ***** BB44 STMT00090 (IL 0x01E... ???) [000552] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000550] ------------ arg0 +--* LCL_VAR ref V34 tmp20 [000551] ------------ arg1 \--* LCL_VAR ref V35 tmp21 ------------ BB45 [01E..01F), preds={} succs={BB46} ------------ BB46 [???..???), preds={} succs={BB48} ***** BB46 STMT00003 (IL 0x02C... ???) [000018] -A-XG------- * ASG ref [000017] D------N---- +--* LCL_VAR ref V04 loc0 [000016] ---XG------- \--* FIELD ref _entries [000015] ------------ \--* LCL_VAR ref V00 this ***** BB46 STMT00094 (IL 0x033... ???) [000566] -A---------- * ASG bool [000565] D------N---- +--* LCL_VAR bool V36 tmp22 [000558] ------------ \--* CAST int <- bool <- int [000021] N--------U-- \--* GT int [000019] ------------ +--* LCL_VAR ref V04 loc0 [000020] ------------ \--* CNS_INT ref null ***** BB46 STMT00097 (IL 0x033... ???) [000576] -A--G------- * ASG ref [000575] D------N---- +--* LCL_VAR ref V37 tmp23 [000562] #---G------- \--* IND ref [000561] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ------------ BB48 [033..034) -> BB50 (cond), preds={} succs={BB49,BB50} ***** BB48 STMT00095 (IL 0x033... ???) [000571] ------------ * JTRUE void [000570] ------------ \--* NE int [000568] ------------ +--* LCL_VAR int V36 tmp22 [000569] ------------ \--* CNS_INT int 0 ------------ BB49 [033..034), preds={} succs={BB50} ***** BB49 STMT00096 (IL 0x033... ???) [000574] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000572] ------------ arg0 +--* CNS_STR ref [000573] ------------ arg1 \--* LCL_VAR ref V37 tmp23 ------------ BB50 [033..034), preds={} succs={BB51} ------------ BB51 [???..???) -> BB07 (cond), preds={} succs={BB06,BB07} ***** BB51 STMT00005 (IL 0x041... ???) [000028] -A-XG------- * ASG ref [000027] D------N---- +--* LCL_VAR ref V05 loc1 [000026] ---XG------- \--* FIELD ref _comparer [000025] ------------ \--* LCL_VAR ref V00 this ***** BB51 STMT00006 (IL 0x048...0x049) [000032] ------------ * JTRUE void [000031] ------------ \--* EQ int [000029] ------------ +--* LCL_VAR ref V05 loc1 [000030] ------------ \--* CNS_INT ref null ------------ BB06 [04B..054) -> BB08 (always), preds={} succs={BB08} ***** BB06 STMT00079 (IL 0x04B...0x052) [000489] -A-X-------- * ASG long [000488] D------N---- +--* LCL_VAR long V29 tmp15 [000487] #--X-------- \--* IND long [000486] !----------- \--* LCL_VAR ref V00 this ***** BB06 STMT00080 (IL ???... ???) [000499] -A---------- * ASG ref [000498] D------N---- +--* LCL_VAR ref V30 tmp16 [000485] ------------ \--* LCL_VAR ref V01 arg1 ***** BB06 STMT00081 (IL ???... ???) [000517] -AC-G------- * ASG long [000516] D------N---- +--* LCL_VAR long V31 tmp17 [000515] --C-G------- \--* QMARK long [000505] Q----------- if +--* NE int [000501] n----------- | +--* IND long [000497] ------------ | | \--* ADD long [000495] #----------- | | +--* IND long [000494] #----------- | | | \--* IND long [000493] ------------ | | | \--* ADD long [000491] ------------ | | | +--* LCL_VAR long V29 tmp15 [000492] ------------ | | | \--* CNS_INT long 56 [000496] ------------ | | \--* CNS_INT long 64 [000504] ------------ | \--* CNS_INT long 0 [000514] --C-G------- if \--* COLON long [000503] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000490] ------------ arg0 | +--* LCL_VAR long V29 tmp15 [000502] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000506] n----------- then \--* IND long [000507] ------------ \--* ADD long [000508] #----------- +--* IND long [000509] #----------- | \--* IND long [000510] ------------ | \--* ADD long [000511] ------------ | +--* LCL_VAR long V29 tmp15 [000512] ------------ | \--* CNS_INT long 56 [000513] ------------ \--* CNS_INT long 64 ***** BB06 STMT00082 (IL ???... ???) [000520] -A---------- * ASG long [000519] D------N---- +--* LCL_VAR long V32 tmp18 [000518] ------------ \--* LCL_VAR long V31 tmp17 ***** BB06 STMT00083 (IL ???... ???) [000524] -ACXG------- * ASG int [000523] D------N---- +--* LCL_VAR int V15 tmp1 [000522] --CXG------- \--* CALL ind stub int [000484] ------------ this in rcx +--* LCL_VAR ref V05 loc1 [000500] ------------ arg1 +--* LCL_VAR ref V30 tmp16 [000521] ------------ calli tgt \--* LCL_VAR long V32 tmp18 ------------ BB07 [054..061), preds={} succs={BB08} ***** BB07 STMT00007 (IL 0x054...0x05C) [000038] -ACXG------- * ASG int [000037] D------N---- +--* LCL_VAR int V15 tmp1 [000035] --CXG------- \--* CALLV vt-ind int System.Object.GetHashCode [000036] *--XG------- this in rcx \--* IND ref [000034] ------------ \--* ADDR long [000033] -------N---- \--* LCL_VAR ref V01 arg1 ------------ BB08 [061..07A), preds={} succs={BB55} ***** BB08 STMT00008 (IL ???...0x061) [000042] -A---------- * ASG int [000041] D------N---- +--* LCL_VAR int V06 loc2 [000040] ------------ \--* LCL_VAR int V15 tmp1 ***** BB08 STMT00009 (IL 0x062...0x063) [000045] -A---------- * ASG int [000044] D------N---- +--* LCL_VAR int V07 loc3 [000043] ------------ \--* CNS_INT int 0 ***** BB08 STMT00098 (IL 0x064... ???) [000580] -A-XG------- * ASG ref [000579] D------N---- +--* LCL_VAR ref V39 tmp25 [000578] ---XG------- \--* FIELD ref _buckets [000046] ------------ \--* LCL_VAR ref V00 this ***** BB08 STMT00105 (IL 0x064... ???) [000629] -A-X-------- * ASG int [000628] D------N---- +--* LCL_VAR int V40 tmp26 [000583] ---X-------- \--* ARR_LENGTH int [000582] ------------ \--* LCL_VAR ref V39 tmp25 ***** BB08 STMT00106 (IL 0x064... ???) [000631] -A-XG------- * ASG long [000630] D------N---- +--* LCL_VAR long V41 tmp27 [000585] ---XG------- \--* FIELD long _fastModMultiplier [000584] ------------ \--* LCL_VAR ref V00 this ***** BB08 STMT00108 (IL 0x064... ???) [000642] -A---------- * ASG bool [000641] D------N---- +--* LCL_VAR bool V43 tmp29 [000633] ------------ \--* CAST int <- bool <- int [000601] ------------ \--* EQ int [000599] N--------U-- +--* GT int [000597] ------------ | +--* LCL_VAR int V40 tmp26 [000598] ------------ | \--* CNS_INT int 0x7FFFFFFF [000600] ------------ \--* CNS_INT int 0 ***** BB08 STMT00111 (IL 0x064... ???) [000652] -A--G------- * ASG ref [000651] D------N---- +--* LCL_VAR ref V44 tmp30 [000636] #---G------- \--* IND ref [000635] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB08 STMT00112 (IL 0x064... ???) [000654] -A--G------- * ASG ref [000653] D------N---- +--* LCL_VAR ref V45 tmp31 [000638] #---G------- \--* IND ref [000637] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ------------ BB55 [064..065) -> BB57 (cond), preds={} succs={BB56,BB57} ***** BB55 STMT00109 (IL 0x064... ???) [000647] ------------ * JTRUE void [000646] ------------ \--* NE int [000644] ------------ +--* LCL_VAR int V43 tmp29 [000645] ------------ \--* CNS_INT int 0 ------------ BB56 [064..065), preds={} succs={BB57} ***** BB56 STMT00110 (IL 0x064... ???) [000650] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000648] ------------ arg0 +--* LCL_VAR ref V44 tmp30 [000649] ------------ arg1 \--* LCL_VAR ref V45 tmp31 ------------ BB57 [064..065), preds={} succs={BB58} ------------ BB58 [???..???), preds={} succs={BB60} ***** BB58 STMT00103 (IL 0x064... ???) [000619] -A---------- * ASG int [000618] D------N---- +--* LCL_VAR int V42 tmp28 [000617] ------------ \--* CAST int <- uint <- long [000616] ------------ \--* RSZ long [000614] ------------ +--* MUL long [000611] ------------ | +--* ADD long [000608] ------------ | | +--* RSZ long [000606] ------------ | | | +--* MUL long [000604] ------------ | | | | +--* LCL_VAR long V41 tmp27 [000605] ---------U-- | | | | \--* CAST long <- ulong <- uint [000047] ------------ | | | | \--* LCL_VAR int V06 loc2 [000607] ------------ | | | \--* CNS_INT int 32 [000610] ------------ | | \--* CNS_INT long 1 [000613] ---------U-- | \--* CAST long <- ulong <- uint [000612] ------------ | \--* LCL_VAR int V40 tmp26 [000615] ------------ \--* CNS_INT int 32 ***** BB58 STMT00114 (IL 0x064... ???) [000665] -A-X-------- * ASG bool [000664] D------N---- +--* LCL_VAR bool V46 tmp32 [000656] ---X-------- \--* CAST int <- bool <- int [000624] ---X-------- \--* EQ int [000620] ------------ +--* LCL_VAR int V42 tmp28 [000623] ---X-------- \--* UMOD int [000621] ------------ +--* LCL_VAR int V06 loc2 [000622] ------------ \--* LCL_VAR int V40 tmp26 ***** BB58 STMT00117 (IL 0x064... ???) [000675] -A--G------- * ASG ref [000674] D------N---- +--* LCL_VAR ref V47 tmp33 [000659] #---G------- \--* IND ref [000658] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB58 STMT00118 (IL 0x064... ???) [000677] -A--G------- * ASG ref [000676] D------N---- +--* LCL_VAR ref V48 tmp34 [000661] #---G------- \--* IND ref [000660] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ------------ BB60 [064..065) -> BB62 (cond), preds={} succs={BB61,BB62} ***** BB60 STMT00115 (IL 0x064... ???) [000670] ------------ * JTRUE void [000669] ------------ \--* NE int [000667] ------------ +--* LCL_VAR int V46 tmp32 [000668] ------------ \--* CNS_INT int 0 ------------ BB61 [064..065), preds={} succs={BB62} ***** BB61 STMT00116 (IL 0x064... ???) [000673] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000671] ------------ arg0 +--* LCL_VAR ref V47 tmp33 [000672] ------------ arg1 \--* LCL_VAR ref V48 tmp34 ------------ BB62 [064..065), preds={} succs={BB63} ------------ BB63 [???..???) -> BB21 (cond), preds={} succs={BB09,BB21} ***** BB63 STMT00100 (IL 0x064... ???) [000591] -ACXG------- * ASG byref [000590] D------N---- +--* LCL_VAR byref V38 tmp24 [000589] --CXG------- \--* ADDR byref [000588] --CXG--N---- \--* INDEX int [000581] ------------ +--* LCL_VAR ref V39 tmp25 [000627] ------------ \--* LCL_VAR int V42 tmp28 ***** BB63 STMT00101 (IL 0x064... ???) [000595] -A---------- * ASG ref [000594] D------N---- +--* LCL_VAR ref V39 tmp25 [000593] ------------ \--* CNS_INT ref null ***** BB63 STMT00011 (IL ???... ???) [000051] -AC--------- * ASG byref [000050] D------N---- +--* LCL_VAR byref V08 loc4 [000592] ------------ \--* LCL_VAR byref V38 tmp24 ***** BB63 STMT00012 (IL 0x06D...0x072) [000057] -A-XG------- * ASG int [000056] D------N---- +--* LCL_VAR int V09 loc5 [000055] ---XG------- \--* SUB int [000053] *--XG------- +--* IND int [000052] ------------ | \--* LCL_VAR byref V08 loc4 [000054] ------------ \--* CNS_INT int 1 ***** BB63 STMT00013 (IL 0x074...0x075) [000061] ------------ * JTRUE void [000060] ------------ \--* NE int [000058] ------------ +--* LCL_VAR ref V05 loc1 [000059] ------------ \--* CNS_INT ref null ------------ BB09 [07A..08B) -> BB10 (always), preds={} succs={BB10} ------------ BB10 [0FF..106), preds={} succs={BB11} ***** BB10 STMT00059 (IL 0x0FF...0x104) [000356] -A-X-------- * ASG long [000355] D------N---- +--* LCL_VAR long V24 tmp10 [000354] #--X-------- \--* IND long [000353] !----------- \--* LCL_VAR ref V00 this ***** BB10 STMT00060 (IL ???... ???) [000381] -AC-G------- * ASG long [000380] D------N---- +--* LCL_VAR long V25 tmp11 [000379] --C-G------- \--* QMARK long [000369] Q----------- if +--* NE int [000365] n----------- | +--* IND long [000364] ------------ | | \--* ADD long [000362] #----------- | | +--* IND long [000361] #----------- | | | \--* IND long [000360] ------------ | | | \--* ADD long [000358] ------------ | | | +--* LCL_VAR long V24 tmp10 [000359] ------------ | | | \--* CNS_INT long 56 [000363] ------------ | | \--* CNS_INT long 32 [000368] ------------ | \--* CNS_INT long 0 [000378] --C-G------- if \--* COLON long [000367] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000357] ------------ arg0 | +--* LCL_VAR long V24 tmp10 [000366] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000370] n----------- then \--* IND long [000371] ------------ \--* ADD long [000372] #----------- +--* IND long [000373] #----------- | \--* IND long [000374] ------------ | \--* ADD long [000375] ------------ | +--* LCL_VAR long V24 tmp10 [000376] ------------ | \--* CNS_INT long 56 [000377] ------------ \--* CNS_INT long 32 ***** BB10 STMT00062 (IL ???... ???) [000386] -AC--------- * ASG ref [000385] D------N---- +--* LCL_VAR ref V12 loc8 [000352] --C-G------- \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default [000383] ------------ arg0 \--* RUNTIMELOOKUP long 0xd1ffab1e class [000382] ------------ \--* LCL_VAR long V25 tmp11 ------------ BB11 [106..110) -> BB31 (cond), preds={} succs={BB12,BB31} ***** BB11 STMT00063 (IL 0x106...0x10B) [000391] ---X-------- * JTRUE void [000390] N--X-----U-- \--* GE int [000387] ------------ +--* LCL_VAR int V09 loc5 [000389] ---X-------- \--* ARR_LENGTH int [000388] ------------ \--* LCL_VAR ref V04 loc0 ------------ BB12 [110..120) -> BB19 (cond), preds={} succs={BB13,BB19} ***** BB12 STMT00064 (IL 0x110...0x11E) [000399] ---XG------- * JTRUE void [000398] N--XG----U-- \--* NE int [000396] ---XG------- +--* FIELD int hashCode [000395] ---XG------- | \--* ADDR byref [000394] ---XG--N---- | \--* INDEX struct [000392] ------------ | +--* LCL_VAR ref V04 loc0 [000393] ------------ | \--* LCL_VAR int V09 loc5 [000397] ------------ \--* LCL_VAR int V06 loc2 ------------ BB13 [120..137) -> BB19 (cond), preds={} succs={BB14,BB19} ***** BB13 STMT00069 (IL 0x120...0x135) [000428] --CXG------- * JTRUE void [000427] --CXG------- \--* EQ int [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 [000423] ---XG------- arg1 | +--* FIELD ref key [000422] ---XG------- | | \--* ADDR byref [000421] ---XG--N---- | | \--* INDEX struct [000419] ------------ | | +--* LCL_VAR ref V04 loc0 [000420] ------------ | | \--* LCL_VAR int V09 loc5 [000424] ------------ arg2 | \--* LCL_VAR ref V01 arg1 [000426] ------------ \--* CNS_INT int 0 ------------ BB14 [137..13B) -> BB16 (cond), preds={} succs={BB15,BB16} ***** BB14 STMT00070 (IL 0x137...0x139) [000432] ------------ * JTRUE void [000431] N--------U-- \--* NE int [000429] ------------ +--* LCL_VAR ubyte V03 arg3 [000430] ------------ \--* CNS_INT int 1 ------------ BB15 [13B..14B) (return), preds={} succs={} ***** BB15 STMT00077 (IL 0x13B...0x144) [000481] -A-XG------- * ASG ref [000480] ---XG--N---- +--* FIELD ref value [000478] ---XG------- | \--* ADDR byref [000477] ---XG--N---- | \--* INDEX struct [000475] ------------ | +--* LCL_VAR ref V04 loc0 [000476] ------------ | \--* LCL_VAR int V09 loc5 [000479] ------------ \--* LCL_VAR ref V02 arg2 ***** BB15 STMT00078 (IL 0x149...0x14A) [000483] ------------ * RETURN int [000482] ------------ \--* CNS_INT int 1 ------------ BB16 [14B..14F) -> BB18 (cond), preds={} succs={BB17,BB18} ***** BB16 STMT00071 (IL 0x14B...0x14D) [000436] ------------ * JTRUE void [000435] N--------U-- \--* NE int [000433] ------------ +--* LCL_VAR ubyte V03 arg3 [000434] ------------ \--* CNS_INT int 2 ------------ BB17 [14F..155), preds={} succs={BB18} ***** BB17 STMT00073 (IL 0x14F...0x150) [000444] -A-X-------- * ASG long [000443] D------N---- +--* LCL_VAR long V26 tmp12 [000442] #--X-------- \--* IND long [000441] !----------- \--* LCL_VAR ref V00 this ***** BB17 STMT00074 (IL ???... ???) [000454] -A---------- * ASG ref [000453] D------N---- +--* LCL_VAR ref V27 tmp13 [000439] ------------ \--* LCL_VAR ref V01 arg1 ***** BB17 STMT00075 (IL ???... ???) [000472] -AC-G------- * ASG long [000471] D------N---- +--* LCL_VAR long V28 tmp14 [000470] --C-G------- \--* QMARK long [000460] Q----------- if +--* NE int [000456] n----------- | +--* IND long [000452] ------------ | | \--* ADD long [000450] #----------- | | +--* IND long [000449] #----------- | | | \--* IND long [000448] ------------ | | | \--* ADD long [000446] ------------ | | | +--* LCL_VAR long V26 tmp12 [000447] ------------ | | | \--* CNS_INT long 56 [000451] ------------ | | \--* CNS_INT long 56 [000459] ------------ | \--* CNS_INT long 0 [000469] --C-G------- if \--* COLON long [000458] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000445] ------------ arg0 | +--* LCL_VAR long V26 tmp12 [000457] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000461] n----------- then \--* IND long [000462] ------------ \--* ADD long [000463] #----------- +--* IND long [000464] #----------- | \--* IND long [000465] ------------ | \--* ADD long [000466] ------------ | +--* LCL_VAR long V26 tmp12 [000467] ------------ | \--* CNS_INT long 56 [000468] ------------ \--* CNS_INT long 56 ***** BB17 STMT00076 (IL ???... ???) [000440] --C-G------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000474] ------------ arg0 +--* RUNTIMELOOKUP long 0xd1ffab1e method [000473] ------------ | \--* LCL_VAR long V28 tmp14 [000455] ------------ arg1 \--* LCL_VAR ref V27 tmp13 ------------ BB18 [155..157) (return), preds={} succs={} ***** BB18 STMT00072 (IL 0x155...0x156) [000438] ------------ * RETURN int [000437] ------------ \--* CNS_INT int 0 ------------ BB19 [157..170) -> BB11 (cond), preds={} succs={BB20,BB11} ***** BB19 STMT00065 (IL 0x157...0x164) [000406] -A-XG------- * ASG int [000405] D------N---- +--* LCL_VAR int V09 loc5 [000404] ---XG------- \--* FIELD int next [000403] ---XG------- \--* ADDR byref [000402] ---XG--N---- \--* INDEX struct [000400] ------------ +--* LCL_VAR ref V04 loc0 [000401] ------------ \--* LCL_VAR int V09 loc5 ***** BB19 STMT00066 (IL 0x166...0x169) [000411] -A---------- * ASG int [000410] D------N---- +--* LCL_VAR int V07 loc3 [000409] ------------ \--* ADD int [000407] ------------ +--* LCL_VAR int V07 loc3 [000408] ------------ \--* CNS_INT int 1 ***** BB19 STMT00067 (IL 0x16A...0x16E) [000416] ---X-------- * JTRUE void [000415] N--X-----U-- \--* LE int [000412] ------------ +--* LCL_VAR int V07 loc3 [000414] ---X-------- \--* ARR_LENGTH int [000413] ------------ \--* LCL_VAR ref V04 loc0 ------------ BB20 [170..177) -> BB11 (always), preds={} succs={BB11} ***** BB20 STMT00068 (IL 0x170...0x175) [000417] --C-G------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported ------------ BB21 [177..17E) -> BB31 (cond), preds={} succs={BB22,BB31} ***** BB21 STMT00014 (IL 0x177...0x17C) [000066] ---X-------- * JTRUE void [000065] N--X-----U-- \--* GE int [000062] ------------ +--* LCL_VAR int V09 loc5 [000064] ---X-------- \--* ARR_LENGTH int [000063] ------------ \--* LCL_VAR ref V04 loc0 ------------ BB22 [17E..18E) -> BB29 (cond), preds={} succs={BB23,BB29} ***** BB22 STMT00039 (IL 0x17E...0x18C) [000215] ---XG------- * JTRUE void [000214] N--XG----U-- \--* NE int [000212] ---XG------- +--* FIELD int hashCode [000211] ---XG------- | \--* ADDR byref [000210] ---XG--N---- | \--* INDEX struct [000208] ------------ | +--* LCL_VAR ref V04 loc0 [000209] ------------ | \--* LCL_VAR int V09 loc5 [000213] ------------ \--* LCL_VAR int V06 loc2 ------------ BB23 [18E..1A4) -> BB29 (cond), preds={} succs={BB24,BB29} ***** BB23 STMT00045 (IL 0x18E...0x1A2) [000246] -A-XG------- * ASG ref [000245] D------N---- +--* LCL_VAR ref V17 tmp3 [000239] ---XG------- \--* FIELD ref key [000238] ---XG------- \--* ADDR byref [000237] ---XG--N---- \--* INDEX struct [000235] ------------ +--* LCL_VAR ref V04 loc0 [000236] ------------ \--* LCL_VAR int V09 loc5 ***** BB23 STMT00044 (IL 0x18E... ???) [000244] -A-X-------- * ASG long [000243] D------N---- +--* LCL_VAR long V16 tmp2 [000242] #--X-------- \--* IND long [000241] !----------- \--* LCL_VAR ref V00 this ***** BB23 STMT00046 (IL ???... ???) [000257] -A---------- * ASG ref [000256] D------N---- +--* LCL_VAR ref V18 tmp4 [000240] ------------ \--* LCL_VAR ref V01 arg1 ***** BB23 STMT00047 (IL ???... ???) [000275] -AC-G------- * ASG long [000274] D------N---- +--* LCL_VAR long V19 tmp5 [000273] --C-G------- \--* QMARK long [000263] Q----------- if +--* NE int [000259] n----------- | +--* IND long [000255] ------------ | | \--* ADD long [000253] #----------- | | +--* IND long [000252] #----------- | | | \--* IND long [000251] ------------ | | | \--* ADD long [000249] ------------ | | | +--* LCL_VAR long V16 tmp2 [000250] ------------ | | | \--* CNS_INT long 56 [000254] ------------ | | \--* CNS_INT long 48 [000262] ------------ | \--* CNS_INT long 0 [000272] --C-G------- if \--* COLON long [000261] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000248] ------------ arg0 | +--* LCL_VAR long V16 tmp2 [000260] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000264] n----------- then \--* IND long [000265] ------------ \--* ADD long [000266] #----------- +--* IND long [000267] #----------- | \--* IND long [000268] ------------ | \--* ADD long [000269] ------------ | +--* LCL_VAR long V16 tmp2 [000270] ------------ | \--* CNS_INT long 56 [000271] ------------ \--* CNS_INT long 48 ***** BB23 STMT00048 (IL ???... ???) [000278] -A---------- * ASG long [000277] D------N---- +--* LCL_VAR long V20 tmp6 [000276] ------------ \--* LCL_VAR long V19 tmp5 ***** BB23 STMT00049 (IL ???... ???) [000283] --CXG------- * JTRUE void [000282] --CXG------- \--* EQ int [000280] --CXG------- +--* CALL ind stub int [000234] ------------ this in rcx | +--* LCL_VAR ref V05 loc1 [000247] ------------ arg1 | +--* LCL_VAR ref V17 tmp3 [000258] ------------ arg2 | +--* LCL_VAR ref V18 tmp4 [000279] ------------ calli tgt | \--* LCL_VAR long V20 tmp6 [000281] ------------ \--* CNS_INT int 0 ------------ BB24 [1A4..1A8) -> BB26 (cond), preds={} succs={BB25,BB26} ***** BB24 STMT00050 (IL 0x1A4...0x1A6) [000287] ------------ * JTRUE void [000286] N--------U-- \--* NE int [000284] ------------ +--* LCL_VAR ubyte V03 arg3 [000285] ------------ \--* CNS_INT int 1 ------------ BB25 [1A8..1B8) (return), preds={} succs={} ***** BB25 STMT00057 (IL 0x1A8...0x1B1) [000336] -A-XG------- * ASG ref [000335] ---XG--N---- +--* FIELD ref value [000333] ---XG------- | \--* ADDR byref [000332] ---XG--N---- | \--* INDEX struct [000330] ------------ | +--* LCL_VAR ref V04 loc0 [000331] ------------ | \--* LCL_VAR int V09 loc5 [000334] ------------ \--* LCL_VAR ref V02 arg2 ***** BB25 STMT00058 (IL 0x1B6...0x1B7) [000338] ------------ * RETURN int [000337] ------------ \--* CNS_INT int 1 ------------ BB26 [1B8..1BC) -> BB28 (cond), preds={} succs={BB27,BB28} ***** BB26 STMT00051 (IL 0x1B8...0x1BA) [000291] ------------ * JTRUE void [000290] N--------U-- \--* NE int [000288] ------------ +--* LCL_VAR ubyte V03 arg3 [000289] ------------ \--* CNS_INT int 2 ------------ BB27 [1BC..1C2), preds={} succs={BB28} ***** BB27 STMT00053 (IL 0x1BC...0x1BD) [000299] -A-X-------- * ASG long [000298] D------N---- +--* LCL_VAR long V21 tmp7 [000297] #--X-------- \--* IND long [000296] !----------- \--* LCL_VAR ref V00 this ***** BB27 STMT00054 (IL ???... ???) [000309] -A---------- * ASG ref [000308] D------N---- +--* LCL_VAR ref V22 tmp8 [000294] ------------ \--* LCL_VAR ref V01 arg1 ***** BB27 STMT00055 (IL ???... ???) [000327] -AC-G------- * ASG long [000326] D------N---- +--* LCL_VAR long V23 tmp9 [000325] --C-G------- \--* QMARK long [000315] Q----------- if +--* NE int [000311] n----------- | +--* IND long [000307] ------------ | | \--* ADD long [000305] #----------- | | +--* IND long [000304] #----------- | | | \--* IND long [000303] ------------ | | | \--* ADD long [000301] ------------ | | | +--* LCL_VAR long V21 tmp7 [000302] ------------ | | | \--* CNS_INT long 56 [000306] ------------ | | \--* CNS_INT long 56 [000314] ------------ | \--* CNS_INT long 0 [000324] --C-G------- if \--* COLON long [000313] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000300] ------------ arg0 | +--* LCL_VAR long V21 tmp7 [000312] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000316] n----------- then \--* IND long [000317] ------------ \--* ADD long [000318] #----------- +--* IND long [000319] #----------- | \--* IND long [000320] ------------ | \--* ADD long [000321] ------------ | +--* LCL_VAR long V21 tmp7 [000322] ------------ | \--* CNS_INT long 56 [000323] ------------ \--* CNS_INT long 56 ***** BB27 STMT00056 (IL ???... ???) [000295] --C-G------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000329] ------------ arg0 +--* RUNTIMELOOKUP long 0xd1ffab1e method [000328] ------------ | \--* LCL_VAR long V23 tmp9 [000310] ------------ arg1 \--* LCL_VAR ref V22 tmp8 ------------ BB28 [1C2..1C4) (return), preds={} succs={} ***** BB28 STMT00052 (IL 0x1C2...0x1C3) [000293] ------------ * RETURN int [000292] ------------ \--* CNS_INT int 0 ------------ BB29 [1C4..1DD) -> BB21 (cond), preds={} succs={BB30,BB21} ***** BB29 STMT00040 (IL 0x1C4...0x1D1) [000222] -A-XG------- * ASG int [000221] D------N---- +--* LCL_VAR int V09 loc5 [000220] ---XG------- \--* FIELD int next [000219] ---XG------- \--* ADDR byref [000218] ---XG--N---- \--* INDEX struct [000216] ------------ +--* LCL_VAR ref V04 loc0 [000217] ------------ \--* LCL_VAR int V09 loc5 ***** BB29 STMT00041 (IL 0x1D3...0x1D6) [000227] -A---------- * ASG int [000226] D------N---- +--* LCL_VAR int V07 loc3 [000225] ------------ \--* ADD int [000223] ------------ +--* LCL_VAR int V07 loc3 [000224] ------------ \--* CNS_INT int 1 ***** BB29 STMT00042 (IL 0x1D7...0x1DB) [000232] ---X-------- * JTRUE void [000231] N--X-----U-- \--* LE int [000228] ------------ +--* LCL_VAR int V07 loc3 [000230] ---X-------- \--* ARR_LENGTH int [000229] ------------ \--* LCL_VAR ref V04 loc0 ------------ BB30 [1DD..1E4) -> BB21 (always), preds={} succs={BB21} ***** BB30 STMT00043 (IL 0x1DD...0x1E2) [000233] --C-G------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported ------------ BB31 [1E4..1ED) -> BB33 (cond), preds={} succs={BB32,BB33} ***** BB31 STMT00015 (IL 0x1E4...0x1EB) [000071] ---XG------- * JTRUE void [000070] ---XG------- \--* LE int [000068] ---XG------- +--* FIELD int _freeCount [000067] ------------ | \--* LCL_VAR ref V00 this [000069] ------------ \--* CNS_INT int 0 ------------ BB32 [1ED..243), preds={} succs={BB70} ***** BB32 STMT00035 (IL 0x1ED...0x1F3) [000174] -A-XG------- * ASG int [000173] D------N---- +--* LCL_VAR int V10 loc6 [000172] ---XG------- \--* FIELD int _freeList [000171] ------------ \--* LCL_VAR ref V00 this ***** BB32 STMT00120 (IL 0x1F5... ???) [000688] -A-XG------- * ASG bool [000687] D------N---- +--* LCL_VAR bool V49 tmp35 [000680] ---XG------- \--* CAST int <- bool <- int [000186] ---XG------- \--* EQ int [000184] ---XG------- +--* LT int [000182] ---XG------- | +--* SUB int [000175] ------------ | | +--* CNS_INT int -3 [000181] ---XG------- | | \--* FIELD int next [000180] ---XG------- | | \--* ADDR byref [000179] ---XG--N---- | | \--* INDEX struct [000176] ------------ | | +--* LCL_VAR ref V04 loc0 [000178] ---XG------- | | \--* FIELD int _freeList [000177] ------------ | | \--* LCL_VAR ref V00 this [000183] ------------ | \--* CNS_INT int -1 [000185] ------------ \--* CNS_INT int 0 ***** BB32 STMT00123 (IL 0x1F5... ???) [000698] -A--G------- * ASG ref [000697] D------N---- +--* LCL_VAR ref V50 tmp36 [000684] #---G------- \--* IND ref [000683] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ------------ BB70 [1F5..1F6) -> BB72 (cond), preds={} succs={BB71,BB72} ***** BB70 STMT00121 (IL 0x1F5... ???) [000693] ------------ * JTRUE void [000692] ------------ \--* NE int [000690] ------------ +--* LCL_VAR int V49 tmp35 [000691] ------------ \--* CNS_INT int 0 ------------ BB71 [1F5..1F6), preds={} succs={BB72} ***** BB71 STMT00122 (IL 0x1F5... ???) [000696] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000694] ------------ arg0 +--* CNS_STR ref [000695] ------------ arg1 \--* LCL_VAR ref V50 tmp36 ------------ BB72 [1F5..1F6), preds={} succs={BB73} ------------ BB73 [???..???) -> BB36 (always), preds={} succs={BB36} ***** BB73 STMT00037 (IL 0x219... ???) [000200] -A-XG------- * ASG int [000199] ---XG--N---- +--* FIELD int _freeList [000190] ------------ | \--* LCL_VAR ref V00 this [000198] ---XG------- \--* SUB int [000191] ------------ +--* CNS_INT int -3 [000197] ---XG------- \--* FIELD int next [000196] ---XG------- \--* ADDR byref [000195] ---XG--N---- \--* INDEX struct [000192] ------------ +--* LCL_VAR ref V04 loc0 [000194] ---XG------- \--* FIELD int _freeList [000193] ------------ \--* LCL_VAR ref V00 this ***** BB73 STMT00038 (IL 0x233...0x23C) [000207] -A-XG------- * ASG int [000206] ---XG--N---- +--* FIELD int _freeCount [000201] ------------ | \--* LCL_VAR ref V00 this [000205] ---XG------- \--* SUB int [000203] ---XG------- +--* FIELD int _freeCount [000202] ------------ | \--* LCL_VAR ref V00 this [000204] ------------ \--* CNS_INT int 1 ------------ BB33 [243..252) -> BB35 (cond), preds={} succs={BB34,BB35} ***** BB33 STMT00016 (IL 0x243...0x249) [000075] -A-XG------- * ASG int [000074] D------N---- +--* LCL_VAR int V13 loc9 [000073] ---XG------- \--* FIELD int _count [000072] ------------ \--* LCL_VAR ref V00 this ***** BB33 STMT00017 (IL 0x24B...0x250) [000080] ---X-------- * JTRUE void [000079] N--X-----U-- \--* NE int [000076] ------------ +--* LCL_VAR int V13 loc9 [000078] ---X-------- \--* ARR_LENGTH int [000077] ------------ \--* LCL_VAR ref V04 loc0 ------------ BB34 [252..261), preds={} succs={BB78} ***** BB34 STMT00125 (IL 0x252... ???) [000705] --C-G------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [000163] ------------ this in rcx +--* LCL_VAR ref V00 this [000702] --CXG------- arg1 +--* CALL int System.Collections.HashHelpers.ExpandPrime [000701] ---XG------- arg0 | \--* FIELD int _count [000700] ------------ | \--* LCL_VAR ref V00 this [000706] ------------ arg2 \--* PUTARG_TYPE bool [000704] ------------ \--* CNS_INT int 0 ***** BB34 STMT00126 (IL 0x258... ???) [000711] -A-XG------- * ASG ref [000710] D------N---- +--* LCL_VAR ref V52 tmp38 [000709] ---XG------- \--* FIELD ref _buckets [000165] ------------ \--* LCL_VAR ref V00 this ***** BB34 STMT00133 (IL 0x258... ???) [000760] -A-X-------- * ASG int [000759] D------N---- +--* LCL_VAR int V53 tmp39 [000714] ---X-------- \--* ARR_LENGTH int [000713] ------------ \--* LCL_VAR ref V52 tmp38 ***** BB34 STMT00134 (IL 0x258... ???) [000762] -A-XG------- * ASG long [000761] D------N---- +--* LCL_VAR long V54 tmp40 [000716] ---XG------- \--* FIELD long _fastModMultiplier [000715] ------------ \--* LCL_VAR ref V00 this ***** BB34 STMT00136 (IL 0x258... ???) [000773] -A---------- * ASG bool [000772] D------N---- +--* LCL_VAR bool V56 tmp42 [000764] ------------ \--* CAST int <- bool <- int [000732] ------------ \--* EQ int [000730] N--------U-- +--* GT int [000728] ------------ | +--* LCL_VAR int V53 tmp39 [000729] ------------ | \--* CNS_INT int 0x7FFFFFFF [000731] ------------ \--* CNS_INT int 0 ***** BB34 STMT00139 (IL 0x258... ???) [000783] -A--G------- * ASG ref [000782] D------N---- +--* LCL_VAR ref V57 tmp43 [000767] #---G------- \--* IND ref [000766] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB34 STMT00140 (IL 0x258... ???) [000785] -A--G------- * ASG ref [000784] D------N---- +--* LCL_VAR ref V58 tmp44 [000769] #---G------- \--* IND ref [000768] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ------------ BB78 [258..259) -> BB80 (cond), preds={} succs={BB79,BB80} ***** BB78 STMT00137 (IL 0x258... ???) [000778] ------------ * JTRUE void [000777] ------------ \--* NE int [000775] ------------ +--* LCL_VAR int V56 tmp42 [000776] ------------ \--* CNS_INT int 0 ------------ BB79 [258..259), preds={} succs={BB80} ***** BB79 STMT00138 (IL 0x258... ???) [000781] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000779] ------------ arg0 +--* LCL_VAR ref V57 tmp43 [000780] ------------ arg1 \--* LCL_VAR ref V58 tmp44 ------------ BB80 [258..259), preds={} succs={BB81} ------------ BB81 [???..???), preds={} succs={BB83} ***** BB81 STMT00131 (IL 0x258... ???) [000750] -A---------- * ASG int [000749] D------N---- +--* LCL_VAR int V55 tmp41 [000748] ------------ \--* CAST int <- uint <- long [000747] ------------ \--* RSZ long [000745] ------------ +--* MUL long [000742] ------------ | +--* ADD long [000739] ------------ | | +--* RSZ long [000737] ------------ | | | +--* MUL long [000735] ------------ | | | | +--* LCL_VAR long V54 tmp40 [000736] ---------U-- | | | | \--* CAST long <- ulong <- uint [000166] ------------ | | | | \--* LCL_VAR int V06 loc2 [000738] ------------ | | | \--* CNS_INT int 32 [000741] ------------ | | \--* CNS_INT long 1 [000744] ---------U-- | \--* CAST long <- ulong <- uint [000743] ------------ | \--* LCL_VAR int V53 tmp39 [000746] ------------ \--* CNS_INT int 32 ***** BB81 STMT00142 (IL 0x258... ???) [000796] -A-X-------- * ASG bool [000795] D------N---- +--* LCL_VAR bool V59 tmp45 [000787] ---X-------- \--* CAST int <- bool <- int [000755] ---X-------- \--* EQ int [000751] ------------ +--* LCL_VAR int V55 tmp41 [000754] ---X-------- \--* UMOD int [000752] ------------ +--* LCL_VAR int V06 loc2 [000753] ------------ \--* LCL_VAR int V53 tmp39 ***** BB81 STMT00145 (IL 0x258... ???) [000806] -A--G------- * ASG ref [000805] D------N---- +--* LCL_VAR ref V60 tmp46 [000790] #---G------- \--* IND ref [000789] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB81 STMT00146 (IL 0x258... ???) [000808] -A--G------- * ASG ref [000807] D------N---- +--* LCL_VAR ref V61 tmp47 [000792] #---G------- \--* IND ref [000791] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ------------ BB83 [258..259) -> BB85 (cond), preds={} succs={BB84,BB85} ***** BB83 STMT00143 (IL 0x258... ???) [000801] ------------ * JTRUE void [000800] ------------ \--* NE int [000798] ------------ +--* LCL_VAR int V59 tmp45 [000799] ------------ \--* CNS_INT int 0 ------------ BB84 [258..259), preds={} succs={BB85} ***** BB84 STMT00144 (IL 0x258... ???) [000804] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000802] ------------ arg0 +--* LCL_VAR ref V60 tmp46 [000803] ------------ arg1 \--* LCL_VAR ref V61 tmp47 ------------ BB85 [258..259), preds={} succs={BB86} ------------ BB86 [???..???), preds={} succs={BB35} ***** BB86 STMT00128 (IL 0x258... ???) [000722] -ACXG------- * ASG byref [000721] D------N---- +--* LCL_VAR byref V51 tmp37 [000720] --CXG------- \--* ADDR byref [000719] --CXG--N---- \--* INDEX int [000712] ------------ +--* LCL_VAR ref V52 tmp38 [000758] ------------ \--* LCL_VAR int V55 tmp41 ***** BB86 STMT00129 (IL 0x258... ???) [000726] -A---------- * ASG ref [000725] D------N---- +--* LCL_VAR ref V52 tmp38 [000724] ------------ \--* CNS_INT ref null ***** BB86 STMT00034 (IL ???... ???) [000170] -AC--------- * ASG byref [000169] D------N---- +--* LCL_VAR byref V08 loc4 [000723] ------------ \--* LCL_VAR byref V51 tmp37 ------------ BB35 [261..276), preds={} succs={BB36} ***** BB35 STMT00018 (IL 0x261...0x263) [000083] -A---------- * ASG int [000082] D------N---- +--* LCL_VAR int V10 loc6 [000081] ------------ \--* LCL_VAR int V13 loc9 ***** BB35 STMT00019 (IL 0x265...0x26A) [000089] -A-XG------- * ASG int [000088] ---XG--N---- +--* FIELD int _count [000084] ------------ | \--* LCL_VAR ref V00 this [000087] ------------ \--* ADD int [000085] ------------ +--* LCL_VAR int V13 loc9 [000086] ------------ \--* CNS_INT int 1 ***** BB35 STMT00020 (IL 0x26F...0x275) [000093] -A-XG------- * ASG ref [000092] D------N---- +--* LCL_VAR ref V04 loc0 [000091] ---XG------- \--* FIELD ref _entries [000090] ------------ \--* LCL_VAR ref V00 this ------------ BB36 [276..2CA), preds={} succs={BB37} ***** BB36 STMT00021 (IL 0x276...0x27E) [000099] -A-XG------- * ASG byref [000098] D------N---- +--* LCL_VAR byref V11 loc7 [000097] ---XG------- \--* ADDR byref [000096] ---XG--N---- \--* INDEX struct [000094] ------------ +--* LCL_VAR ref V04 loc0 [000095] ------------ \--* LCL_VAR int V10 loc6 ***** BB36 STMT00022 (IL 0x280...0x283) [000103] -A-XG------- * ASG int [000102] ---XG--N---- +--* FIELD int hashCode [000100] ------------ | \--* LCL_VAR byref V11 loc7 [000101] ------------ \--* LCL_VAR int V06 loc2 ***** BB36 STMT00023 (IL 0x288...0x28F) [000110] -A-XG------- * ASG int [000109] ---XG--N---- +--* FIELD int next [000104] ------------ | \--* LCL_VAR byref V11 loc7 [000108] ---XG------- \--* SUB int [000106] *--XG------- +--* IND int [000105] ------------ | \--* LCL_VAR byref V08 loc4 [000107] ------------ \--* CNS_INT int 1 ***** BB36 STMT00024 (IL 0x294...0x297) [000114] -A-XG------- * ASG ref [000113] ---XG--N---- +--* FIELD ref key [000111] ------------ | \--* LCL_VAR byref V11 loc7 [000112] ------------ \--* LCL_VAR ref V01 arg1 ***** BB36 STMT00025 (IL 0x29C...0x29F) [000118] -A-XG------- * ASG ref [000117] ---XG--N---- +--* FIELD ref value [000115] ------------ | \--* LCL_VAR byref V11 loc7 [000116] ------------ \--* LCL_VAR ref V02 arg2 ***** BB36 STMT00026 (IL 0x2A4...0x2AA) [000124] -A-XG------- * ASG int [000123] *------N---- +--* IND int [000119] ------------ | \--* LCL_VAR byref V08 loc4 [000122] ------------ \--* ADD int [000120] ------------ +--* LCL_VAR int V10 loc6 [000121] ------------ \--* CNS_INT int 1 ***** BB36 STMT00027 (IL 0x2AB...0x2B4) [000131] -A-XG------- * ASG int [000130] ---XG--N---- +--* FIELD int _version [000125] ------------ | \--* LCL_VAR ref V00 this [000129] ---XG------- \--* ADD int [000127] ---XG------- +--* FIELD int _version [000126] ------------ | \--* LCL_VAR ref V00 this [000128] ------------ \--* CNS_INT int 1 ------------ BB37 [2CA..2CF) -> BB40 (cond), preds={} succs={BB38,BB40} ***** BB37 STMT00028 (IL 0x2CA...0x2CD) [000148] ------------ * JTRUE void [000147] N--------U-- \--* LE int [000145] ------------ +--* LCL_VAR int V07 loc3 [000146] ------------ \--* CNS_INT int 100 ------------ BB38 [2CF..2D7) -> BB40 (cond), preds={} succs={BB39,BB40} ***** BB38 STMT00030 (IL 0x2CF...0x2D5) [000156] --C-G------- * JTRUE void [000155] --C-G------- \--* EQ int [000153] --C-G------- +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS [000152] H------N---- arg0 | +--* CNS_INT(h) long 0xd1ffab1e class [000151] ------------ arg1 | \--* LCL_VAR ref V05 loc1 [000154] ------------ \--* CNS_INT ref null ------------ BB39 [2D7..2E1), preds={} succs={BB40} ***** BB39 STMT00031 (IL 0x2D7...0x2DC) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [000157] ------------ this in rcx +--* LCL_VAR ref V00 this [000159] ---X-------- arg1 +--* ARR_LENGTH int [000158] ------------ | \--* LCL_VAR ref V04 loc0 [000162] ------------ arg2 \--* PUTARG_TYPE bool [000160] ------------ \--* CNS_INT int 1 ------------ BB40 [2E1..2E3) (return), preds={} succs={} ***** BB40 STMT00029 (IL 0x2E1...0x2E2) [000150] ------------ * RETURN int [000149] ------------ \--* CNS_INT int 1 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Allocate Objects no newobjs in this method; punting *************** Finishing PHASE Allocate Objects [no changes] *************** Starting PHASE Morph - Add internal blocks fgNewBBinRegion(jumpKind=4, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=true): inserting after BB40 New Basic Block BB87 [0091] created. newReturnBB [BB87] created mergeReturns statement tree [000810] added to genReturnBB BB87 [0091] [000810] ------------ * RETURN int [000482] ------------ \--* CNS_INT int 1 removing useless STMT00078 (IL 0x149...0x14A) [000483] ------------ * RETURN int [000482] ------------ \--* CNS_INT int 1 from BB15 fgNewBBinRegion(jumpKind=4, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=false, insertAtEnd=true): inserting after BB87 New Basic Block BB88 [0092] created. newReturnBB [BB88] created mergeReturns statement tree [000811] added to genReturnBB BB88 [0092] [000811] ------------ * RETURN int [000437] ------------ \--* CNS_INT int 0 removing useless STMT00072 (IL 0x155...0x156) [000438] ------------ * RETURN int [000437] ------------ \--* CNS_INT int 0 from BB18 BB18 becomes empty removing useless STMT00058 (IL 0x1B6...0x1B7) [000338] ------------ * RETURN int [000337] ------------ \--* CNS_INT int 1 from BB25 removing useless STMT00052 (IL 0x1C2...0x1C3) [000293] ------------ * RETURN int [000292] ------------ \--* CNS_INT int 0 from BB28 BB28 becomes empty removing useless STMT00029 (IL 0x2E1...0x2E2) [000150] ------------ * RETURN int [000149] ------------ \--* CNS_INT int 1 from BB40 BB40 becomes empty Relocated block [BB87..BB87] inserted after BB40 Relocated block [BB88..BB88] inserted after BB28 *************** After fgAddInternal() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 1 [008..00E) i BB03 [0002] 2 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 1 [016..01E) i BB05 [0004] 2 1 [01E..04B) i BB43 [0051] 1 1 [01E..01F)-> BB45 ( cond ) i BB44 [0052] 1 1 [01E..01F) i BB45 [0053] 2 1 [01E..01F) i BB46 [0054] 1 1 [???..???) i internal BB48 [0056] 1 1 [033..034)-> BB50 ( cond ) i BB49 [0057] 1 1 [033..034) i BB50 [0058] 2 1 [033..034) i BB51 [0059] 1 1 [???..???)-> BB07 ( cond ) internal BB06 [0005] 1 1 [04B..054)-> BB08 (always) i BB07 [0006] 1 1 [054..061) i BB08 [0007] 2 1 [061..07A) i idxlen BB55 [0063] 1 1 [064..065)-> BB57 ( cond ) i BB56 [0064] 1 1 [064..065) i BB57 [0065] 2 1 [064..065) i BB58 [0066] 1 1 [???..???) i internal idxlen BB60 [0068] 1 1 [064..065)-> BB62 ( cond ) i BB61 [0069] 1 1 [064..065) i BB62 [0070] 2 1 [064..065) i BB63 [0071] 1 1 [???..???)-> BB21 ( cond ) internal idxlen BB09 [0008] 1 1 [07A..08B)-> BB10 (always) i BB10 [0019] 1 1 [0FF..106) i BB11 [0020] 3 1 [106..110)-> BB31 ( cond ) i idxlen bwd bwd-target BB12 [0021] 1 1 [110..120)-> BB19 ( cond ) i idxlen bwd BB13 [0022] 1 1 [120..137)-> BB19 ( cond ) i idxlen bwd BB14 [0023] 1 1 [137..13B)-> BB16 ( cond ) i bwd BB15 [0024] 1 1 [13B..14B)-> BB87 (always) i idxlen BB16 [0025] 1 1 [14B..14F)-> BB18 ( cond ) i bwd BB17 [0026] 1 1 [14F..155) i bwd BB18 [0027] 2 1 [155..157)-> BB88 (always) i BB19 [0028] 2 1 [157..170)-> BB11 ( cond ) i idxlen bwd BB20 [0029] 1 1 [170..177)-> BB11 (always) i bwd BB21 [0030] 3 1 [177..17E)-> BB31 ( cond ) i idxlen bwd bwd-target BB22 [0031] 1 1 [17E..18E)-> BB29 ( cond ) i idxlen bwd BB23 [0032] 1 1 [18E..1A4)-> BB29 ( cond ) i idxlen bwd BB24 [0033] 1 1 [1A4..1A8)-> BB26 ( cond ) i bwd BB25 [0034] 1 1 [1A8..1B8)-> BB87 (always) i idxlen BB26 [0035] 1 1 [1B8..1BC)-> BB28 ( cond ) i bwd BB27 [0036] 1 1 [1BC..1C2) i bwd BB28 [0037] 2 1 [1C2..1C4)-> BB88 (always) i BB88 [0092] 1 1 [???..???) (return) internal BB29 [0038] 2 1 [1C4..1DD)-> BB21 ( cond ) i idxlen bwd BB30 [0039] 1 1 [1DD..1E4)-> BB21 (always) i bwd BB31 [0040] 3 1 [1E4..1ED)-> BB33 ( cond ) i BB32 [0041] 1 1 [1ED..243) i BB70 [0074] 1 1 [1F5..1F6)-> BB72 ( cond ) i BB71 [0075] 1 1 [1F5..1F6) i BB72 [0076] 2 1 [1F5..1F6) i BB73 [0077] 1 1 [???..???)-> BB36 (always) internal BB33 [0042] 1 1 [243..252)-> BB35 ( cond ) i idxlen BB34 [0043] 1 1 [252..261) i idxlen BB78 [0082] 1 1 [258..259)-> BB80 ( cond ) i BB79 [0083] 1 1 [258..259) i BB80 [0084] 2 1 [258..259) i BB81 [0085] 1 1 [???..???) i internal idxlen BB83 [0087] 1 1 [258..259)-> BB85 ( cond ) i BB84 [0088] 1 1 [258..259) i BB85 [0089] 2 1 [258..259) i BB86 [0090] 1 1 [???..???) internal idxlen BB35 [0044] 2 1 [261..276) i BB36 [0045] 2 1 [276..2CA) i idxlen BB37 [0046] 1 1 [2CA..2CF)-> BB40 ( cond ) i BB38 [0047] 1 1 [2CF..2D7)-> BB40 ( cond ) i BB39 [0048] 1 1 [2D7..2E1) i idxlen BB40 [0049] 4 1 [2E1..2E3)-> BB87 (always) i BB87 [0091] 1 1 [???..???) (return) internal ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** Finishing PHASE Morph - Add internal blocks *************** Starting PHASE Remove empty try *************** In fgRemoveEmptyTry() No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty try [no changes] *************** Starting PHASE Remove empty finally No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty finally [no changes] *************** Starting PHASE Merge callfinally chains No EH in this method, nothing to merge. *************** Finishing PHASE Merge callfinally chains [no changes] *************** Starting PHASE Clone finally No EH in this method, no cloning. *************** Finishing PHASE Clone finally [no changes] *************** Starting PHASE Compute preds Renumbering the basic blocks for fgComputePred *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 1 [008..00E) i BB03 [0002] 2 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 1 [016..01E) i BB05 [0004] 2 1 [01E..04B) i BB43 [0051] 1 1 [01E..01F)-> BB45 ( cond ) i BB44 [0052] 1 1 [01E..01F) i BB45 [0053] 2 1 [01E..01F) i BB46 [0054] 1 1 [???..???) i internal BB48 [0056] 1 1 [033..034)-> BB50 ( cond ) i BB49 [0057] 1 1 [033..034) i BB50 [0058] 2 1 [033..034) i BB51 [0059] 1 1 [???..???)-> BB07 ( cond ) internal BB06 [0005] 1 1 [04B..054)-> BB08 (always) i BB07 [0006] 1 1 [054..061) i BB08 [0007] 2 1 [061..07A) i idxlen BB55 [0063] 1 1 [064..065)-> BB57 ( cond ) i BB56 [0064] 1 1 [064..065) i BB57 [0065] 2 1 [064..065) i BB58 [0066] 1 1 [???..???) i internal idxlen BB60 [0068] 1 1 [064..065)-> BB62 ( cond ) i BB61 [0069] 1 1 [064..065) i BB62 [0070] 2 1 [064..065) i BB63 [0071] 1 1 [???..???)-> BB21 ( cond ) internal idxlen BB09 [0008] 1 1 [07A..08B)-> BB10 (always) i BB10 [0019] 1 1 [0FF..106) i BB11 [0020] 3 1 [106..110)-> BB31 ( cond ) i idxlen bwd bwd-target BB12 [0021] 1 1 [110..120)-> BB19 ( cond ) i idxlen bwd BB13 [0022] 1 1 [120..137)-> BB19 ( cond ) i idxlen bwd BB14 [0023] 1 1 [137..13B)-> BB16 ( cond ) i bwd BB15 [0024] 1 1 [13B..14B)-> BB87 (always) i idxlen BB16 [0025] 1 1 [14B..14F)-> BB18 ( cond ) i bwd BB17 [0026] 1 1 [14F..155) i bwd BB18 [0027] 2 1 [155..157)-> BB88 (always) i BB19 [0028] 2 1 [157..170)-> BB11 ( cond ) i idxlen bwd BB20 [0029] 1 1 [170..177)-> BB11 (always) i bwd BB21 [0030] 3 1 [177..17E)-> BB31 ( cond ) i idxlen bwd bwd-target BB22 [0031] 1 1 [17E..18E)-> BB29 ( cond ) i idxlen bwd BB23 [0032] 1 1 [18E..1A4)-> BB29 ( cond ) i idxlen bwd BB24 [0033] 1 1 [1A4..1A8)-> BB26 ( cond ) i bwd BB25 [0034] 1 1 [1A8..1B8)-> BB87 (always) i idxlen BB26 [0035] 1 1 [1B8..1BC)-> BB28 ( cond ) i bwd BB27 [0036] 1 1 [1BC..1C2) i bwd BB28 [0037] 2 1 [1C2..1C4)-> BB88 (always) i BB88 [0092] 1 1 [???..???) (return) internal BB29 [0038] 2 1 [1C4..1DD)-> BB21 ( cond ) i idxlen bwd BB30 [0039] 1 1 [1DD..1E4)-> BB21 (always) i bwd BB31 [0040] 3 1 [1E4..1ED)-> BB33 ( cond ) i BB32 [0041] 1 1 [1ED..243) i BB70 [0074] 1 1 [1F5..1F6)-> BB72 ( cond ) i BB71 [0075] 1 1 [1F5..1F6) i BB72 [0076] 2 1 [1F5..1F6) i BB73 [0077] 1 1 [???..???)-> BB36 (always) internal BB33 [0042] 1 1 [243..252)-> BB35 ( cond ) i idxlen BB34 [0043] 1 1 [252..261) i idxlen BB78 [0082] 1 1 [258..259)-> BB80 ( cond ) i BB79 [0083] 1 1 [258..259) i BB80 [0084] 2 1 [258..259) i BB81 [0085] 1 1 [???..???) i internal idxlen BB83 [0087] 1 1 [258..259)-> BB85 ( cond ) i BB84 [0088] 1 1 [258..259) i BB85 [0089] 2 1 [258..259) i BB86 [0090] 1 1 [???..???) internal idxlen BB35 [0044] 2 1 [261..276) i BB36 [0045] 2 1 [276..2CA) i idxlen BB37 [0046] 1 1 [2CA..2CF)-> BB40 ( cond ) i BB38 [0047] 1 1 [2CF..2D7)-> BB40 ( cond ) i BB39 [0048] 1 1 [2D7..2E1) i idxlen BB40 [0049] 4 1 [2E1..2E3)-> BB87 (always) i BB87 [0091] 1 1 [???..???) (return) internal ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB43 to BB06 Renumber BB44 to BB07 Renumber BB45 to BB08 Renumber BB46 to BB09 Renumber BB48 to BB10 Renumber BB49 to BB11 Renumber BB50 to BB12 Renumber BB51 to BB13 Renumber BB06 to BB14 Renumber BB07 to BB15 Renumber BB08 to BB16 Renumber BB55 to BB17 Renumber BB56 to BB18 Renumber BB57 to BB19 Renumber BB58 to BB20 Renumber BB60 to BB21 Renumber BB61 to BB22 Renumber BB62 to BB23 Renumber BB63 to BB24 Renumber BB09 to BB25 Renumber BB10 to BB26 Renumber BB11 to BB27 Renumber BB12 to BB28 Renumber BB13 to BB29 Renumber BB14 to BB30 Renumber BB15 to BB31 Renumber BB16 to BB32 Renumber BB17 to BB33 Renumber BB18 to BB34 Renumber BB19 to BB35 Renumber BB20 to BB36 Renumber BB21 to BB37 Renumber BB22 to BB38 Renumber BB23 to BB39 Renumber BB24 to BB40 Renumber BB25 to BB41 Renumber BB26 to BB42 Renumber BB27 to BB43 Renumber BB28 to BB44 Renumber BB88 to BB45 Renumber BB29 to BB46 Renumber BB30 to BB47 Renumber BB31 to BB48 Renumber BB32 to BB49 Renumber BB70 to BB50 Renumber BB71 to BB51 Renumber BB72 to BB52 Renumber BB73 to BB53 Renumber BB33 to BB54 Renumber BB34 to BB55 Renumber BB78 to BB56 Renumber BB79 to BB57 Renumber BB80 to BB58 Renumber BB81 to BB59 Renumber BB83 to BB60 Renumber BB84 to BB61 Renumber BB85 to BB62 Renumber BB86 to BB63 Renumber BB35 to BB64 Renumber BB36 to BB65 Renumber BB37 to BB66 Renumber BB38 to BB67 Renumber BB39 to BB68 Renumber BB40 to BB69 Renumber BB87 to BB70 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 1 [008..00E) i BB03 [0002] 2 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 1 [016..01E) i BB05 [0004] 2 1 [01E..04B) i BB06 [0051] 1 1 [01E..01F)-> BB08 ( cond ) i BB07 [0052] 1 1 [01E..01F) i BB08 [0053] 2 1 [01E..01F) i BB09 [0054] 1 1 [???..???) i internal BB10 [0056] 1 1 [033..034)-> BB12 ( cond ) i BB11 [0057] 1 1 [033..034) i BB12 [0058] 2 1 [033..034) i BB13 [0059] 1 1 [???..???)-> BB15 ( cond ) internal BB14 [0005] 1 1 [04B..054)-> BB16 (always) i BB15 [0006] 1 1 [054..061) i BB16 [0007] 2 1 [061..07A) i idxlen BB17 [0063] 1 1 [064..065)-> BB19 ( cond ) i BB18 [0064] 1 1 [064..065) i BB19 [0065] 2 1 [064..065) i BB20 [0066] 1 1 [???..???) i internal idxlen BB21 [0068] 1 1 [064..065)-> BB23 ( cond ) i BB22 [0069] 1 1 [064..065) i BB23 [0070] 2 1 [064..065) i BB24 [0071] 1 1 [???..???)-> BB37 ( cond ) internal idxlen BB25 [0008] 1 1 [07A..08B)-> BB26 (always) i BB26 [0019] 1 1 [0FF..106) i BB27 [0020] 3 1 [106..110)-> BB48 ( cond ) i idxlen bwd bwd-target BB28 [0021] 1 1 [110..120)-> BB35 ( cond ) i idxlen bwd BB29 [0022] 1 1 [120..137)-> BB35 ( cond ) i idxlen bwd BB30 [0023] 1 1 [137..13B)-> BB32 ( cond ) i bwd BB31 [0024] 1 1 [13B..14B)-> BB70 (always) i idxlen BB32 [0025] 1 1 [14B..14F)-> BB34 ( cond ) i bwd BB33 [0026] 1 1 [14F..155) i bwd BB34 [0027] 2 1 [155..157)-> BB45 (always) i BB35 [0028] 2 1 [157..170)-> BB27 ( cond ) i idxlen bwd BB36 [0029] 1 1 [170..177)-> BB27 (always) i bwd BB37 [0030] 3 1 [177..17E)-> BB48 ( cond ) i idxlen bwd bwd-target BB38 [0031] 1 1 [17E..18E)-> BB46 ( cond ) i idxlen bwd BB39 [0032] 1 1 [18E..1A4)-> BB46 ( cond ) i idxlen bwd BB40 [0033] 1 1 [1A4..1A8)-> BB42 ( cond ) i bwd BB41 [0034] 1 1 [1A8..1B8)-> BB70 (always) i idxlen BB42 [0035] 1 1 [1B8..1BC)-> BB44 ( cond ) i bwd BB43 [0036] 1 1 [1BC..1C2) i bwd BB44 [0037] 2 1 [1C2..1C4)-> BB45 (always) i BB45 [0092] 1 1 [???..???) (return) internal BB46 [0038] 2 1 [1C4..1DD)-> BB37 ( cond ) i idxlen bwd BB47 [0039] 1 1 [1DD..1E4)-> BB37 (always) i bwd BB48 [0040] 3 1 [1E4..1ED)-> BB54 ( cond ) i BB49 [0041] 1 1 [1ED..243) i BB50 [0074] 1 1 [1F5..1F6)-> BB52 ( cond ) i BB51 [0075] 1 1 [1F5..1F6) i BB52 [0076] 2 1 [1F5..1F6) i BB53 [0077] 1 1 [???..???)-> BB65 (always) internal BB54 [0042] 1 1 [243..252)-> BB64 ( cond ) i idxlen BB55 [0043] 1 1 [252..261) i idxlen BB56 [0082] 1 1 [258..259)-> BB58 ( cond ) i BB57 [0083] 1 1 [258..259) i BB58 [0084] 2 1 [258..259) i BB59 [0085] 1 1 [???..???) i internal idxlen BB60 [0087] 1 1 [258..259)-> BB62 ( cond ) i BB61 [0088] 1 1 [258..259) i BB62 [0089] 2 1 [258..259) i BB63 [0090] 1 1 [???..???) internal idxlen BB64 [0044] 2 1 [261..276) i BB65 [0045] 2 1 [276..2CA) i idxlen BB66 [0046] 1 1 [2CA..2CF)-> BB69 ( cond ) i BB67 [0047] 1 1 [2CF..2D7)-> BB69 ( cond ) i BB68 [0048] 1 1 [2D7..2E1) i idxlen BB69 [0049] 4 1 [2E1..2E3)-> BB70 (always) i BB70 [0091] 1 1 [???..???) (return) internal ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 3, # of blocks (including unused BB00): 71, bitset array size: 2 (long); NOTE: BlockSet size was previously short! *************** In fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 1 [008..00E) i BB03 [0002] 2 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 1 [016..01E) i BB05 [0004] 2 1 [01E..04B) i BB06 [0051] 1 1 [01E..01F)-> BB08 ( cond ) i BB07 [0052] 1 1 [01E..01F) i BB08 [0053] 2 1 [01E..01F) i BB09 [0054] 1 1 [???..???) i internal BB10 [0056] 1 1 [033..034)-> BB12 ( cond ) i BB11 [0057] 1 1 [033..034) i BB12 [0058] 2 1 [033..034) i BB13 [0059] 1 1 [???..???)-> BB15 ( cond ) internal BB14 [0005] 1 1 [04B..054)-> BB16 (always) i BB15 [0006] 1 1 [054..061) i BB16 [0007] 2 1 [061..07A) i idxlen BB17 [0063] 1 1 [064..065)-> BB19 ( cond ) i BB18 [0064] 1 1 [064..065) i BB19 [0065] 2 1 [064..065) i BB20 [0066] 1 1 [???..???) i internal idxlen BB21 [0068] 1 1 [064..065)-> BB23 ( cond ) i BB22 [0069] 1 1 [064..065) i BB23 [0070] 2 1 [064..065) i BB24 [0071] 1 1 [???..???)-> BB37 ( cond ) internal idxlen BB25 [0008] 1 1 [07A..08B)-> BB26 (always) i BB26 [0019] 1 1 [0FF..106) i BB27 [0020] 3 1 [106..110)-> BB48 ( cond ) i idxlen bwd bwd-target BB28 [0021] 1 1 [110..120)-> BB35 ( cond ) i idxlen bwd BB29 [0022] 1 1 [120..137)-> BB35 ( cond ) i idxlen bwd BB30 [0023] 1 1 [137..13B)-> BB32 ( cond ) i bwd BB31 [0024] 1 1 [13B..14B)-> BB70 (always) i idxlen BB32 [0025] 1 1 [14B..14F)-> BB34 ( cond ) i bwd BB33 [0026] 1 1 [14F..155) i bwd BB34 [0027] 2 1 [155..157)-> BB45 (always) i BB35 [0028] 2 1 [157..170)-> BB27 ( cond ) i idxlen bwd BB36 [0029] 1 1 [170..177)-> BB27 (always) i bwd BB37 [0030] 3 1 [177..17E)-> BB48 ( cond ) i idxlen bwd bwd-target BB38 [0031] 1 1 [17E..18E)-> BB46 ( cond ) i idxlen bwd BB39 [0032] 1 1 [18E..1A4)-> BB46 ( cond ) i idxlen bwd BB40 [0033] 1 1 [1A4..1A8)-> BB42 ( cond ) i bwd BB41 [0034] 1 1 [1A8..1B8)-> BB70 (always) i idxlen BB42 [0035] 1 1 [1B8..1BC)-> BB44 ( cond ) i bwd BB43 [0036] 1 1 [1BC..1C2) i bwd BB44 [0037] 2 1 [1C2..1C4)-> BB45 (always) i BB45 [0092] 1 1 [???..???) (return) internal BB46 [0038] 2 1 [1C4..1DD)-> BB37 ( cond ) i idxlen bwd BB47 [0039] 1 1 [1DD..1E4)-> BB37 (always) i bwd BB48 [0040] 3 1 [1E4..1ED)-> BB54 ( cond ) i BB49 [0041] 1 1 [1ED..243) i BB50 [0074] 1 1 [1F5..1F6)-> BB52 ( cond ) i BB51 [0075] 1 1 [1F5..1F6) i BB52 [0076] 2 1 [1F5..1F6) i BB53 [0077] 1 1 [???..???)-> BB65 (always) internal BB54 [0042] 1 1 [243..252)-> BB64 ( cond ) i idxlen BB55 [0043] 1 1 [252..261) i idxlen BB56 [0082] 1 1 [258..259)-> BB58 ( cond ) i BB57 [0083] 1 1 [258..259) i BB58 [0084] 2 1 [258..259) i BB59 [0085] 1 1 [???..???) i internal idxlen BB60 [0087] 1 1 [258..259)-> BB62 ( cond ) i BB61 [0088] 1 1 [258..259) i BB62 [0089] 2 1 [258..259) i BB63 [0090] 1 1 [???..???) internal idxlen BB64 [0044] 2 1 [261..276) i BB65 [0045] 2 1 [276..2CA) i idxlen BB66 [0046] 1 1 [2CA..2CF)-> BB69 ( cond ) i BB67 [0047] 1 1 [2CF..2D7)-> BB69 ( cond ) i BB68 [0048] 1 1 [2D7..2E1) i idxlen BB69 [0049] 4 1 [2E1..2E3)-> BB70 (always) i BB70 [0091] 1 1 [???..???) (return) internal ----------------------------------------------------------------------------------------------------------------------------------------- Setting edge weights for BB01 -> BB03 to [0 .. 3.402823e+38] Setting edge weights for BB01 -> BB02 to [0 .. 3.402823e+38] Setting edge weights for BB02 -> BB03 to [0 .. 3.402823e+38] Setting edge weights for BB03 -> BB05 to [0 .. 3.402823e+38] Setting edge weights for BB03 -> BB04 to [0 .. 3.402823e+38] Setting edge weights for BB04 -> BB05 to [0 .. 3.402823e+38] Setting edge weights for BB05 -> BB06 to [0 .. 3.402823e+38] Setting edge weights for BB06 -> BB08 to [0 .. 3.402823e+38] Setting edge weights for BB06 -> BB07 to [0 .. 3.402823e+38] Setting edge weights for BB07 -> BB08 to [0 .. 3.402823e+38] Setting edge weights for BB08 -> BB09 to [0 .. 3.402823e+38] Setting edge weights for BB09 -> BB10 to [0 .. 3.402823e+38] Setting edge weights for BB10 -> BB12 to [0 .. 3.402823e+38] Setting edge weights for BB10 -> BB11 to [0 .. 3.402823e+38] Setting edge weights for BB11 -> BB12 to [0 .. 3.402823e+38] Setting edge weights for BB12 -> BB13 to [0 .. 3.402823e+38] Setting edge weights for BB13 -> BB15 to [0 .. 3.402823e+38] Setting edge weights for BB13 -> BB14 to [0 .. 3.402823e+38] Setting edge weights for BB14 -> BB16 to [0 .. 3.402823e+38] Setting edge weights for BB15 -> BB16 to [0 .. 3.402823e+38] Setting edge weights for BB16 -> BB17 to [0 .. 3.402823e+38] Setting edge weights for BB17 -> BB19 to [0 .. 3.402823e+38] Setting edge weights for BB17 -> BB18 to [0 .. 3.402823e+38] Setting edge weights for BB18 -> BB19 to [0 .. 3.402823e+38] Setting edge weights for BB19 -> BB20 to [0 .. 3.402823e+38] Setting edge weights for BB20 -> BB21 to [0 .. 3.402823e+38] Setting edge weights for BB21 -> BB23 to [0 .. 3.402823e+38] Setting edge weights for BB21 -> BB22 to [0 .. 3.402823e+38] Setting edge weights for BB22 -> BB23 to [0 .. 3.402823e+38] Setting edge weights for BB23 -> BB24 to [0 .. 3.402823e+38] Setting edge weights for BB24 -> BB37 to [0 .. 3.402823e+38] Setting edge weights for BB24 -> BB25 to [0 .. 3.402823e+38] Setting edge weights for BB25 -> BB26 to [0 .. 3.402823e+38] Setting edge weights for BB26 -> BB27 to [0 .. 3.402823e+38] Setting edge weights for BB27 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB27 -> BB28 to [0 .. 3.402823e+38] Setting edge weights for BB28 -> BB35 to [0 .. 3.402823e+38] Setting edge weights for BB28 -> BB29 to [0 .. 3.402823e+38] Setting edge weights for BB29 -> BB35 to [0 .. 3.402823e+38] Setting edge weights for BB29 -> BB30 to [0 .. 3.402823e+38] Setting edge weights for BB30 -> BB32 to [0 .. 3.402823e+38] Setting edge weights for BB30 -> BB31 to [0 .. 3.402823e+38] Setting edge weights for BB31 -> BB70 to [0 .. 3.402823e+38] Setting edge weights for BB32 -> BB34 to [0 .. 3.402823e+38] Setting edge weights for BB32 -> BB33 to [0 .. 3.402823e+38] Setting edge weights for BB33 -> BB34 to [0 .. 3.402823e+38] Setting edge weights for BB34 -> BB45 to [0 .. 3.402823e+38] Setting edge weights for BB35 -> BB27 to [0 .. 3.402823e+38] Setting edge weights for BB35 -> BB36 to [0 .. 3.402823e+38] Setting edge weights for BB36 -> BB27 to [0 .. 3.402823e+38] Setting edge weights for BB37 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB37 -> BB38 to [0 .. 3.402823e+38] Setting edge weights for BB38 -> BB46 to [0 .. 3.402823e+38] Setting edge weights for BB38 -> BB39 to [0 .. 3.402823e+38] Setting edge weights for BB39 -> BB46 to [0 .. 3.402823e+38] Setting edge weights for BB39 -> BB40 to [0 .. 3.402823e+38] Setting edge weights for BB40 -> BB42 to [0 .. 3.402823e+38] Setting edge weights for BB40 -> BB41 to [0 .. 3.402823e+38] Setting edge weights for BB41 -> BB70 to [0 .. 3.402823e+38] Setting edge weights for BB42 -> BB44 to [0 .. 3.402823e+38] Setting edge weights for BB42 -> BB43 to [0 .. 3.402823e+38] Setting edge weights for BB43 -> BB44 to [0 .. 3.402823e+38] Setting edge weights for BB44 -> BB45 to [0 .. 3.402823e+38] Setting edge weights for BB46 -> BB37 to [0 .. 3.402823e+38] Setting edge weights for BB46 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB47 -> BB37 to [0 .. 3.402823e+38] Setting edge weights for BB48 -> BB54 to [0 .. 3.402823e+38] Setting edge weights for BB48 -> BB49 to [0 .. 3.402823e+38] Setting edge weights for BB49 -> BB50 to [0 .. 3.402823e+38] Setting edge weights for BB50 -> BB52 to [0 .. 3.402823e+38] Setting edge weights for BB50 -> BB51 to [0 .. 3.402823e+38] Setting edge weights for BB51 -> BB52 to [0 .. 3.402823e+38] Setting edge weights for BB52 -> BB53 to [0 .. 3.402823e+38] Setting edge weights for BB53 -> BB65 to [0 .. 3.402823e+38] Setting edge weights for BB54 -> BB64 to [0 .. 3.402823e+38] Setting edge weights for BB54 -> BB55 to [0 .. 3.402823e+38] Setting edge weights for BB55 -> BB56 to [0 .. 3.402823e+38] Setting edge weights for BB56 -> BB58 to [0 .. 3.402823e+38] Setting edge weights for BB56 -> BB57 to [0 .. 3.402823e+38] Setting edge weights for BB57 -> BB58 to [0 .. 3.402823e+38] Setting edge weights for BB58 -> BB59 to [0 .. 3.402823e+38] Setting edge weights for BB59 -> BB60 to [0 .. 3.402823e+38] Setting edge weights for BB60 -> BB62 to [0 .. 3.402823e+38] Setting edge weights for BB60 -> BB61 to [0 .. 3.402823e+38] Setting edge weights for BB61 -> BB62 to [0 .. 3.402823e+38] Setting edge weights for BB62 -> BB63 to [0 .. 3.402823e+38] Setting edge weights for BB63 -> BB64 to [0 .. 3.402823e+38] Setting edge weights for BB64 -> BB65 to [0 .. 3.402823e+38] Setting edge weights for BB65 -> BB66 to [0 .. 3.402823e+38] Setting edge weights for BB66 -> BB69 to [0 .. 3.402823e+38] Setting edge weights for BB66 -> BB67 to [0 .. 3.402823e+38] Setting edge weights for BB67 -> BB69 to [0 .. 3.402823e+38] Setting edge weights for BB67 -> BB68 to [0 .. 3.402823e+38] Setting edge weights for BB68 -> BB69 to [0 .. 3.402823e+38] Setting edge weights for BB69 -> BB70 to [0 .. 3.402823e+38] *************** After fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 BB01 1 [008..00E) i BB03 [0002] 2 BB01,BB02 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i BB05 [0004] 2 BB03,BB04 1 [01E..04B) i BB06 [0051] 1 BB05 1 [01E..01F)-> BB08 ( cond ) i BB07 [0052] 1 BB06 1 [01E..01F) i BB08 [0053] 2 BB06,BB07 1 [01E..01F) i BB09 [0054] 1 BB08 1 [???..???) i internal BB10 [0056] 1 BB09 1 [033..034)-> BB12 ( cond ) i BB11 [0057] 1 BB10 1 [033..034) i BB12 [0058] 2 BB10,BB11 1 [033..034) i BB13 [0059] 1 BB12 1 [???..???)-> BB15 ( cond ) internal BB14 [0005] 1 BB13 1 [04B..054)-> BB16 (always) i BB15 [0006] 1 BB13 1 [054..061) i BB16 [0007] 2 BB14,BB15 1 [061..07A) i idxlen BB17 [0063] 1 BB16 1 [064..065)-> BB19 ( cond ) i BB18 [0064] 1 BB17 1 [064..065) i BB19 [0065] 2 BB17,BB18 1 [064..065) i BB20 [0066] 1 BB19 1 [???..???) i internal idxlen BB21 [0068] 1 BB20 1 [064..065)-> BB23 ( cond ) i BB22 [0069] 1 BB21 1 [064..065) i BB23 [0070] 2 BB21,BB22 1 [064..065) i BB24 [0071] 1 BB23 1 [???..???)-> BB37 ( cond ) internal idxlen BB25 [0008] 1 BB24 1 [07A..08B)-> BB26 (always) i BB26 [0019] 1 BB25 1 [0FF..106) i BB27 [0020] 3 BB26,BB35,BB36 1 [106..110)-> BB48 ( cond ) i idxlen bwd bwd-target BB28 [0021] 1 BB27 1 [110..120)-> BB35 ( cond ) i idxlen bwd BB29 [0022] 1 BB28 1 [120..137)-> BB35 ( cond ) i idxlen bwd BB30 [0023] 1 BB29 1 [137..13B)-> BB32 ( cond ) i bwd BB31 [0024] 1 BB30 1 [13B..14B)-> BB70 (always) i idxlen BB32 [0025] 1 BB30 1 [14B..14F)-> BB34 ( cond ) i bwd BB33 [0026] 1 BB32 1 [14F..155) i bwd BB34 [0027] 2 BB32,BB33 1 [155..157)-> BB45 (always) i BB35 [0028] 2 BB28,BB29 1 [157..170)-> BB27 ( cond ) i idxlen bwd BB36 [0029] 1 BB35 1 [170..177)-> BB27 (always) i bwd BB37 [0030] 3 BB24,BB46,BB47 1 [177..17E)-> BB48 ( cond ) i idxlen bwd bwd-target BB38 [0031] 1 BB37 1 [17E..18E)-> BB46 ( cond ) i idxlen bwd BB39 [0032] 1 BB38 1 [18E..1A4)-> BB46 ( cond ) i idxlen bwd BB40 [0033] 1 BB39 1 [1A4..1A8)-> BB42 ( cond ) i bwd BB41 [0034] 1 BB40 1 [1A8..1B8)-> BB70 (always) i idxlen BB42 [0035] 1 BB40 1 [1B8..1BC)-> BB44 ( cond ) i bwd BB43 [0036] 1 BB42 1 [1BC..1C2) i bwd BB44 [0037] 2 BB42,BB43 1 [1C2..1C4)-> BB45 (always) i BB45 [0092] 2 BB34,BB44 1 [???..???) (return) internal BB46 [0038] 2 BB38,BB39 1 [1C4..1DD)-> BB37 ( cond ) i idxlen bwd BB47 [0039] 1 BB46 1 [1DD..1E4)-> BB37 (always) i bwd BB48 [0040] 2 BB27,BB37 1 [1E4..1ED)-> BB54 ( cond ) i BB49 [0041] 1 BB48 1 [1ED..243) i BB50 [0074] 1 BB49 1 [1F5..1F6)-> BB52 ( cond ) i BB51 [0075] 1 BB50 1 [1F5..1F6) i BB52 [0076] 2 BB50,BB51 1 [1F5..1F6) i BB53 [0077] 1 BB52 1 [???..???)-> BB65 (always) internal BB54 [0042] 1 BB48 1 [243..252)-> BB64 ( cond ) i idxlen BB55 [0043] 1 BB54 1 [252..261) i idxlen BB56 [0082] 1 BB55 1 [258..259)-> BB58 ( cond ) i BB57 [0083] 1 BB56 1 [258..259) i BB58 [0084] 2 BB56,BB57 1 [258..259) i BB59 [0085] 1 BB58 1 [???..???) i internal idxlen BB60 [0087] 1 BB59 1 [258..259)-> BB62 ( cond ) i BB61 [0088] 1 BB60 1 [258..259) i BB62 [0089] 2 BB60,BB61 1 [258..259) i BB63 [0090] 1 BB62 1 [???..???) internal idxlen BB64 [0044] 2 BB54,BB63 1 [261..276) i BB65 [0045] 2 BB53,BB64 1 [276..2CA) i idxlen BB66 [0046] 1 BB65 1 [2CA..2CF)-> BB69 ( cond ) i BB67 [0047] 1 BB66 1 [2CF..2D7)-> BB69 ( cond ) i BB68 [0048] 1 BB67 1 [2D7..2E1) i idxlen BB69 [0049] 3 BB66,BB67,BB68 1 [2E1..2E3)-> BB70 (always) i BB70 [0091] 3 BB31,BB41,BB69 1 [???..???) (return) internal ----------------------------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Compute preds *************** Starting PHASE Merge throw blocks *************** In fgTailMergeThrows Scanning the 5 candidates *** Does not return call [000233] --C-G------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported in BB47 is unique, marking it as canonical *** Does not return call [000417] --C-G------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported in BB36 can be dup'd to canonical BB47 *** Does not return call [000533] --C-G------- * CALL void System.ThrowHelper.ThrowArgumentNullException [000532] ------------ arg0 \--* CNS_INT int 4 in BB02 is unique, marking it as canonical *** found 1 merge candidates, rewriting flow New Basic Block BB71 [0093] created. *** BB35 now falling through to empty BB71 and then to BB47 Setting edge weights for BB35 -> BB71 to [0 .. 3.402823e+38] Setting edge weights for BB71 -> BB47 to [0 .. 3.402823e+38] Made 1 updates *************** Finishing PHASE Merge throw blocks Trees after Merge throw blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 BB01 1 [008..00E) i BB03 [0002] 2 BB01,BB02 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i BB05 [0004] 2 BB03,BB04 1 [01E..04B) i BB06 [0051] 1 BB05 1 [01E..01F)-> BB08 ( cond ) i BB07 [0052] 1 BB06 1 [01E..01F) i BB08 [0053] 2 BB06,BB07 1 [01E..01F) i BB09 [0054] 1 BB08 1 [???..???) i internal BB10 [0056] 1 BB09 1 [033..034)-> BB12 ( cond ) i BB11 [0057] 1 BB10 1 [033..034) i BB12 [0058] 2 BB10,BB11 1 [033..034) i BB13 [0059] 1 BB12 1 [???..???)-> BB15 ( cond ) internal BB14 [0005] 1 BB13 1 [04B..054)-> BB16 (always) i BB15 [0006] 1 BB13 1 [054..061) i BB16 [0007] 2 BB14,BB15 1 [061..07A) i idxlen BB17 [0063] 1 BB16 1 [064..065)-> BB19 ( cond ) i BB18 [0064] 1 BB17 1 [064..065) i BB19 [0065] 2 BB17,BB18 1 [064..065) i BB20 [0066] 1 BB19 1 [???..???) i internal idxlen BB21 [0068] 1 BB20 1 [064..065)-> BB23 ( cond ) i BB22 [0069] 1 BB21 1 [064..065) i BB23 [0070] 2 BB21,BB22 1 [064..065) i BB24 [0071] 1 BB23 1 [???..???)-> BB37 ( cond ) internal idxlen BB25 [0008] 1 BB24 1 [07A..08B)-> BB26 (always) i BB26 [0019] 1 BB25 1 [0FF..106) i BB27 [0020] 3 BB26,BB35,BB36 1 [106..110)-> BB48 ( cond ) i idxlen bwd bwd-target BB28 [0021] 1 BB27 1 [110..120)-> BB35 ( cond ) i idxlen bwd BB29 [0022] 1 BB28 1 [120..137)-> BB35 ( cond ) i idxlen bwd BB30 [0023] 1 BB29 1 [137..13B)-> BB32 ( cond ) i bwd BB31 [0024] 1 BB30 1 [13B..14B)-> BB70 (always) i idxlen BB32 [0025] 1 BB30 1 [14B..14F)-> BB34 ( cond ) i bwd BB33 [0026] 1 BB32 1 [14F..155) i bwd BB34 [0027] 2 BB32,BB33 1 [155..157)-> BB45 (always) i BB35 [0028] 2 BB28,BB29 1 [157..170)-> BB27 ( cond ) i idxlen bwd BB71 [0093] 1 BB35 1 [???..???)-> BB47 (always) internal BB36 [0029] 0 1 [170..177)-> BB27 (always) i bwd BB37 [0030] 3 BB24,BB46,BB47 1 [177..17E)-> BB48 ( cond ) i idxlen bwd bwd-target BB38 [0031] 1 BB37 1 [17E..18E)-> BB46 ( cond ) i idxlen bwd BB39 [0032] 1 BB38 1 [18E..1A4)-> BB46 ( cond ) i idxlen bwd BB40 [0033] 1 BB39 1 [1A4..1A8)-> BB42 ( cond ) i bwd BB41 [0034] 1 BB40 1 [1A8..1B8)-> BB70 (always) i idxlen BB42 [0035] 1 BB40 1 [1B8..1BC)-> BB44 ( cond ) i bwd BB43 [0036] 1 BB42 1 [1BC..1C2) i bwd BB44 [0037] 2 BB42,BB43 1 [1C2..1C4)-> BB45 (always) i BB45 [0092] 2 BB34,BB44 1 [???..???) (return) internal BB46 [0038] 2 BB38,BB39 1 [1C4..1DD)-> BB37 ( cond ) i idxlen bwd BB47 [0039] 2 BB46,BB71 1 [1DD..1E4)-> BB37 (always) i bwd BB48 [0040] 2 BB27,BB37 1 [1E4..1ED)-> BB54 ( cond ) i BB49 [0041] 1 BB48 1 [1ED..243) i BB50 [0074] 1 BB49 1 [1F5..1F6)-> BB52 ( cond ) i BB51 [0075] 1 BB50 1 [1F5..1F6) i BB52 [0076] 2 BB50,BB51 1 [1F5..1F6) i BB53 [0077] 1 BB52 1 [???..???)-> BB65 (always) internal BB54 [0042] 1 BB48 1 [243..252)-> BB64 ( cond ) i idxlen BB55 [0043] 1 BB54 1 [252..261) i idxlen BB56 [0082] 1 BB55 1 [258..259)-> BB58 ( cond ) i BB57 [0083] 1 BB56 1 [258..259) i BB58 [0084] 2 BB56,BB57 1 [258..259) i BB59 [0085] 1 BB58 1 [???..???) i internal idxlen BB60 [0087] 1 BB59 1 [258..259)-> BB62 ( cond ) i BB61 [0088] 1 BB60 1 [258..259) i BB62 [0089] 2 BB60,BB61 1 [258..259) i BB63 [0090] 1 BB62 1 [???..???) internal idxlen BB64 [0044] 2 BB54,BB63 1 [261..276) i BB65 [0045] 2 BB53,BB64 1 [276..2CA) i idxlen BB66 [0046] 1 BB65 1 [2CA..2CF)-> BB69 ( cond ) i BB67 [0047] 1 BB66 1 [2CF..2D7)-> BB69 ( cond ) i BB68 [0048] 1 BB67 1 [2D7..2E1) i idxlen BB69 [0049] 3 BB66,BB67,BB68 1 [2E1..2E3)-> BB70 (always) i BB70 [0091] 3 BB31,BB41,BB69 1 [???..???) (return) internal ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 (IL 0x000...0x006) [000003] ------------ * JTRUE void [000002] ------------ \--* NE int [000000] ------------ +--* LCL_VAR ref V01 arg1 [000001] ------------ \--* CNS_INT ref null ------------ BB02 [008..00E), preds={BB01} succs={BB03} ***** BB02 STMT00086 (IL 0x008...0x009) [000533] --C-G------- * CALL void System.ThrowHelper.ThrowArgumentNullException [000532] ------------ arg0 \--* CNS_INT int 4 ------------ BB03 [00E..016) -> BB05 (cond), preds={BB01,BB02} succs={BB04,BB05} ***** BB03 STMT00001 (IL 0x00E...0x014) [000008] ---XG------- * JTRUE void [000007] ---XG------- \--* NE int [000005] ---XG------- +--* FIELD ref _buckets [000004] ------------ | \--* LCL_VAR ref V00 this [000006] ------------ \--* CNS_INT ref null ------------ BB04 [016..01E), preds={BB03} succs={BB05} ***** BB04 STMT00085 (IL ???... ???) [000528] --C-G------- * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize [000526] ------------ this in rcx +--* LCL_VAR ref V00 this [000527] ------------ arg1 \--* CNS_INT int 0 ------------ BB05 [01E..04B), preds={BB03,BB04} succs={BB06} ***** BB05 STMT00088 (IL 0x01E... ???) [000544] -A-XG------- * ASG bool [000543] D------N---- +--* LCL_VAR bool V33 tmp19 [000535] ---XG------- \--* CAST int <- bool <- int [000012] N--XG----U-- \--* GT int [000010] ---XG------- +--* FIELD ref _buckets [000009] ------------ | \--* LCL_VAR ref V00 this [000011] ------------ \--* CNS_INT ref null ***** BB05 STMT00091 (IL 0x01E... ???) [000554] -A--G------- * ASG ref [000553] D------N---- +--* LCL_VAR ref V34 tmp20 [000538] #---G------- \--* IND ref [000537] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB05 STMT00092 (IL 0x01E... ???) [000556] -A--G------- * ASG ref [000555] D------N---- +--* LCL_VAR ref V35 tmp21 [000540] #---G------- \--* IND ref [000539] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ------------ BB06 [01E..01F) -> BB08 (cond), preds={BB05} succs={BB07,BB08} ***** BB06 STMT00089 (IL 0x01E... ???) [000549] ------------ * JTRUE void [000548] ------------ \--* NE int [000546] ------------ +--* LCL_VAR int V33 tmp19 [000547] ------------ \--* CNS_INT int 0 ------------ BB07 [01E..01F), preds={BB06} succs={BB08} ***** BB07 STMT00090 (IL 0x01E... ???) [000552] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000550] ------------ arg0 +--* LCL_VAR ref V34 tmp20 [000551] ------------ arg1 \--* LCL_VAR ref V35 tmp21 ------------ BB08 [01E..01F), preds={BB06,BB07} succs={BB09} ------------ BB09 [???..???), preds={BB08} succs={BB10} ***** BB09 STMT00003 (IL 0x02C... ???) [000018] -A-XG------- * ASG ref [000017] D------N---- +--* LCL_VAR ref V04 loc0 [000016] ---XG------- \--* FIELD ref _entries [000015] ------------ \--* LCL_VAR ref V00 this ***** BB09 STMT00094 (IL 0x033... ???) [000566] -A---------- * ASG bool [000565] D------N---- +--* LCL_VAR bool V36 tmp22 [000558] ------------ \--* CAST int <- bool <- int [000021] N--------U-- \--* GT int [000019] ------------ +--* LCL_VAR ref V04 loc0 [000020] ------------ \--* CNS_INT ref null ***** BB09 STMT00097 (IL 0x033... ???) [000576] -A--G------- * ASG ref [000575] D------N---- +--* LCL_VAR ref V37 tmp23 [000562] #---G------- \--* IND ref [000561] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ------------ BB10 [033..034) -> BB12 (cond), preds={BB09} succs={BB11,BB12} ***** BB10 STMT00095 (IL 0x033... ???) [000571] ------------ * JTRUE void [000570] ------------ \--* NE int [000568] ------------ +--* LCL_VAR int V36 tmp22 [000569] ------------ \--* CNS_INT int 0 ------------ BB11 [033..034), preds={BB10} succs={BB12} ***** BB11 STMT00096 (IL 0x033... ???) [000574] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000572] ------------ arg0 +--* CNS_STR ref [000573] ------------ arg1 \--* LCL_VAR ref V37 tmp23 ------------ BB12 [033..034), preds={BB10,BB11} succs={BB13} ------------ BB13 [???..???) -> BB15 (cond), preds={BB12} succs={BB14,BB15} ***** BB13 STMT00005 (IL 0x041... ???) [000028] -A-XG------- * ASG ref [000027] D------N---- +--* LCL_VAR ref V05 loc1 [000026] ---XG------- \--* FIELD ref _comparer [000025] ------------ \--* LCL_VAR ref V00 this ***** BB13 STMT00006 (IL 0x048...0x049) [000032] ------------ * JTRUE void [000031] ------------ \--* EQ int [000029] ------------ +--* LCL_VAR ref V05 loc1 [000030] ------------ \--* CNS_INT ref null ------------ BB14 [04B..054) -> BB16 (always), preds={BB13} succs={BB16} ***** BB14 STMT00079 (IL 0x04B...0x052) [000489] -A-X-------- * ASG long [000488] D------N---- +--* LCL_VAR long V29 tmp15 [000487] #--X-------- \--* IND long [000486] !----------- \--* LCL_VAR ref V00 this ***** BB14 STMT00080 (IL ???... ???) [000499] -A---------- * ASG ref [000498] D------N---- +--* LCL_VAR ref V30 tmp16 [000485] ------------ \--* LCL_VAR ref V01 arg1 ***** BB14 STMT00081 (IL ???... ???) [000517] -AC-G------- * ASG long [000516] D------N---- +--* LCL_VAR long V31 tmp17 [000515] --C-G------- \--* QMARK long [000505] Q----------- if +--* NE int [000501] n----------- | +--* IND long [000497] ------------ | | \--* ADD long [000495] #----------- | | +--* IND long [000494] #----------- | | | \--* IND long [000493] ------------ | | | \--* ADD long [000491] ------------ | | | +--* LCL_VAR long V29 tmp15 [000492] ------------ | | | \--* CNS_INT long 56 [000496] ------------ | | \--* CNS_INT long 64 [000504] ------------ | \--* CNS_INT long 0 [000514] --C-G------- if \--* COLON long [000503] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000490] ------------ arg0 | +--* LCL_VAR long V29 tmp15 [000502] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000506] n----------- then \--* IND long [000507] ------------ \--* ADD long [000508] #----------- +--* IND long [000509] #----------- | \--* IND long [000510] ------------ | \--* ADD long [000511] ------------ | +--* LCL_VAR long V29 tmp15 [000512] ------------ | \--* CNS_INT long 56 [000513] ------------ \--* CNS_INT long 64 ***** BB14 STMT00082 (IL ???... ???) [000520] -A---------- * ASG long [000519] D------N---- +--* LCL_VAR long V32 tmp18 [000518] ------------ \--* LCL_VAR long V31 tmp17 ***** BB14 STMT00083 (IL ???... ???) [000524] -ACXG------- * ASG int [000523] D------N---- +--* LCL_VAR int V15 tmp1 [000522] --CXG------- \--* CALL ind stub int [000484] ------------ this in rcx +--* LCL_VAR ref V05 loc1 [000500] ------------ arg1 +--* LCL_VAR ref V30 tmp16 [000521] ------------ calli tgt \--* LCL_VAR long V32 tmp18 ------------ BB15 [054..061), preds={BB13} succs={BB16} ***** BB15 STMT00007 (IL 0x054...0x05C) [000038] -ACXG------- * ASG int [000037] D------N---- +--* LCL_VAR int V15 tmp1 [000035] --CXG------- \--* CALLV vt-ind int System.Object.GetHashCode [000036] *--XG------- this in rcx \--* IND ref [000034] ------------ \--* ADDR long [000033] -------N---- \--* LCL_VAR ref V01 arg1 ------------ BB16 [061..07A), preds={BB14,BB15} succs={BB17} ***** BB16 STMT00008 (IL ???...0x061) [000042] -A---------- * ASG int [000041] D------N---- +--* LCL_VAR int V06 loc2 [000040] ------------ \--* LCL_VAR int V15 tmp1 ***** BB16 STMT00009 (IL 0x062...0x063) [000045] -A---------- * ASG int [000044] D------N---- +--* LCL_VAR int V07 loc3 [000043] ------------ \--* CNS_INT int 0 ***** BB16 STMT00098 (IL 0x064... ???) [000580] -A-XG------- * ASG ref [000579] D------N---- +--* LCL_VAR ref V39 tmp25 [000578] ---XG------- \--* FIELD ref _buckets [000046] ------------ \--* LCL_VAR ref V00 this ***** BB16 STMT00105 (IL 0x064... ???) [000629] -A-X-------- * ASG int [000628] D------N---- +--* LCL_VAR int V40 tmp26 [000583] ---X-------- \--* ARR_LENGTH int [000582] ------------ \--* LCL_VAR ref V39 tmp25 ***** BB16 STMT00106 (IL 0x064... ???) [000631] -A-XG------- * ASG long [000630] D------N---- +--* LCL_VAR long V41 tmp27 [000585] ---XG------- \--* FIELD long _fastModMultiplier [000584] ------------ \--* LCL_VAR ref V00 this ***** BB16 STMT00108 (IL 0x064... ???) [000642] -A---------- * ASG bool [000641] D------N---- +--* LCL_VAR bool V43 tmp29 [000633] ------------ \--* CAST int <- bool <- int [000601] ------------ \--* EQ int [000599] N--------U-- +--* GT int [000597] ------------ | +--* LCL_VAR int V40 tmp26 [000598] ------------ | \--* CNS_INT int 0x7FFFFFFF [000600] ------------ \--* CNS_INT int 0 ***** BB16 STMT00111 (IL 0x064... ???) [000652] -A--G------- * ASG ref [000651] D------N---- +--* LCL_VAR ref V44 tmp30 [000636] #---G------- \--* IND ref [000635] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB16 STMT00112 (IL 0x064... ???) [000654] -A--G------- * ASG ref [000653] D------N---- +--* LCL_VAR ref V45 tmp31 [000638] #---G------- \--* IND ref [000637] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ------------ BB17 [064..065) -> BB19 (cond), preds={BB16} succs={BB18,BB19} ***** BB17 STMT00109 (IL 0x064... ???) [000647] ------------ * JTRUE void [000646] ------------ \--* NE int [000644] ------------ +--* LCL_VAR int V43 tmp29 [000645] ------------ \--* CNS_INT int 0 ------------ BB18 [064..065), preds={BB17} succs={BB19} ***** BB18 STMT00110 (IL 0x064... ???) [000650] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000648] ------------ arg0 +--* LCL_VAR ref V44 tmp30 [000649] ------------ arg1 \--* LCL_VAR ref V45 tmp31 ------------ BB19 [064..065), preds={BB17,BB18} succs={BB20} ------------ BB20 [???..???), preds={BB19} succs={BB21} ***** BB20 STMT00103 (IL 0x064... ???) [000619] -A---------- * ASG int [000618] D------N---- +--* LCL_VAR int V42 tmp28 [000617] ------------ \--* CAST int <- uint <- long [000616] ------------ \--* RSZ long [000614] ------------ +--* MUL long [000611] ------------ | +--* ADD long [000608] ------------ | | +--* RSZ long [000606] ------------ | | | +--* MUL long [000604] ------------ | | | | +--* LCL_VAR long V41 tmp27 [000605] ---------U-- | | | | \--* CAST long <- ulong <- uint [000047] ------------ | | | | \--* LCL_VAR int V06 loc2 [000607] ------------ | | | \--* CNS_INT int 32 [000610] ------------ | | \--* CNS_INT long 1 [000613] ---------U-- | \--* CAST long <- ulong <- uint [000612] ------------ | \--* LCL_VAR int V40 tmp26 [000615] ------------ \--* CNS_INT int 32 ***** BB20 STMT00114 (IL 0x064... ???) [000665] -A-X-------- * ASG bool [000664] D------N---- +--* LCL_VAR bool V46 tmp32 [000656] ---X-------- \--* CAST int <- bool <- int [000624] ---X-------- \--* EQ int [000620] ------------ +--* LCL_VAR int V42 tmp28 [000623] ---X-------- \--* UMOD int [000621] ------------ +--* LCL_VAR int V06 loc2 [000622] ------------ \--* LCL_VAR int V40 tmp26 ***** BB20 STMT00117 (IL 0x064... ???) [000675] -A--G------- * ASG ref [000674] D------N---- +--* LCL_VAR ref V47 tmp33 [000659] #---G------- \--* IND ref [000658] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB20 STMT00118 (IL 0x064... ???) [000677] -A--G------- * ASG ref [000676] D------N---- +--* LCL_VAR ref V48 tmp34 [000661] #---G------- \--* IND ref [000660] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ------------ BB21 [064..065) -> BB23 (cond), preds={BB20} succs={BB22,BB23} ***** BB21 STMT00115 (IL 0x064... ???) [000670] ------------ * JTRUE void [000669] ------------ \--* NE int [000667] ------------ +--* LCL_VAR int V46 tmp32 [000668] ------------ \--* CNS_INT int 0 ------------ BB22 [064..065), preds={BB21} succs={BB23} ***** BB22 STMT00116 (IL 0x064... ???) [000673] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000671] ------------ arg0 +--* LCL_VAR ref V47 tmp33 [000672] ------------ arg1 \--* LCL_VAR ref V48 tmp34 ------------ BB23 [064..065), preds={BB21,BB22} succs={BB24} ------------ BB24 [???..???) -> BB37 (cond), preds={BB23} succs={BB25,BB37} ***** BB24 STMT00100 (IL 0x064... ???) [000591] -ACXG------- * ASG byref [000590] D------N---- +--* LCL_VAR byref V38 tmp24 [000589] --CXG------- \--* ADDR byref [000588] --CXG--N---- \--* INDEX int [000581] ------------ +--* LCL_VAR ref V39 tmp25 [000627] ------------ \--* LCL_VAR int V42 tmp28 ***** BB24 STMT00101 (IL 0x064... ???) [000595] -A---------- * ASG ref [000594] D------N---- +--* LCL_VAR ref V39 tmp25 [000593] ------------ \--* CNS_INT ref null ***** BB24 STMT00011 (IL ???... ???) [000051] -AC--------- * ASG byref [000050] D------N---- +--* LCL_VAR byref V08 loc4 [000592] ------------ \--* LCL_VAR byref V38 tmp24 ***** BB24 STMT00012 (IL 0x06D...0x072) [000057] -A-XG------- * ASG int [000056] D------N---- +--* LCL_VAR int V09 loc5 [000055] ---XG------- \--* SUB int [000053] *--XG------- +--* IND int [000052] ------------ | \--* LCL_VAR byref V08 loc4 [000054] ------------ \--* CNS_INT int 1 ***** BB24 STMT00013 (IL 0x074...0x075) [000061] ------------ * JTRUE void [000060] ------------ \--* NE int [000058] ------------ +--* LCL_VAR ref V05 loc1 [000059] ------------ \--* CNS_INT ref null ------------ BB25 [07A..08B) -> BB26 (always), preds={BB24} succs={BB26} ------------ BB26 [0FF..106), preds={BB25} succs={BB27} ***** BB26 STMT00059 (IL 0x0FF...0x104) [000356] -A-X-------- * ASG long [000355] D------N---- +--* LCL_VAR long V24 tmp10 [000354] #--X-------- \--* IND long [000353] !----------- \--* LCL_VAR ref V00 this ***** BB26 STMT00060 (IL ???... ???) [000381] -AC-G------- * ASG long [000380] D------N---- +--* LCL_VAR long V25 tmp11 [000379] --C-G------- \--* QMARK long [000369] Q----------- if +--* NE int [000365] n----------- | +--* IND long [000364] ------------ | | \--* ADD long [000362] #----------- | | +--* IND long [000361] #----------- | | | \--* IND long [000360] ------------ | | | \--* ADD long [000358] ------------ | | | +--* LCL_VAR long V24 tmp10 [000359] ------------ | | | \--* CNS_INT long 56 [000363] ------------ | | \--* CNS_INT long 32 [000368] ------------ | \--* CNS_INT long 0 [000378] --C-G------- if \--* COLON long [000367] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000357] ------------ arg0 | +--* LCL_VAR long V24 tmp10 [000366] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000370] n----------- then \--* IND long [000371] ------------ \--* ADD long [000372] #----------- +--* IND long [000373] #----------- | \--* IND long [000374] ------------ | \--* ADD long [000375] ------------ | +--* LCL_VAR long V24 tmp10 [000376] ------------ | \--* CNS_INT long 56 [000377] ------------ \--* CNS_INT long 32 ***** BB26 STMT00062 (IL ???... ???) [000386] -AC--------- * ASG ref [000385] D------N---- +--* LCL_VAR ref V12 loc8 [000352] --C-G------- \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default [000383] ------------ arg0 \--* RUNTIMELOOKUP long 0xd1ffab1e class [000382] ------------ \--* LCL_VAR long V25 tmp11 ------------ BB27 [106..110) -> BB48 (cond), preds={BB26,BB35,BB36} succs={BB28,BB48} ***** BB27 STMT00063 (IL 0x106...0x10B) [000391] ---X-------- * JTRUE void [000390] N--X-----U-- \--* GE int [000387] ------------ +--* LCL_VAR int V09 loc5 [000389] ---X-------- \--* ARR_LENGTH int [000388] ------------ \--* LCL_VAR ref V04 loc0 ------------ BB28 [110..120) -> BB35 (cond), preds={BB27} succs={BB29,BB35} ***** BB28 STMT00064 (IL 0x110...0x11E) [000399] ---XG------- * JTRUE void [000398] N--XG----U-- \--* NE int [000396] ---XG------- +--* FIELD int hashCode [000395] ---XG------- | \--* ADDR byref [000394] ---XG--N---- | \--* INDEX struct [000392] ------------ | +--* LCL_VAR ref V04 loc0 [000393] ------------ | \--* LCL_VAR int V09 loc5 [000397] ------------ \--* LCL_VAR int V06 loc2 ------------ BB29 [120..137) -> BB35 (cond), preds={BB28} succs={BB30,BB35} ***** BB29 STMT00069 (IL 0x120...0x135) [000428] --CXG------- * JTRUE void [000427] --CXG------- \--* EQ int [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 [000423] ---XG------- arg1 | +--* FIELD ref key [000422] ---XG------- | | \--* ADDR byref [000421] ---XG--N---- | | \--* INDEX struct [000419] ------------ | | +--* LCL_VAR ref V04 loc0 [000420] ------------ | | \--* LCL_VAR int V09 loc5 [000424] ------------ arg2 | \--* LCL_VAR ref V01 arg1 [000426] ------------ \--* CNS_INT int 0 ------------ BB30 [137..13B) -> BB32 (cond), preds={BB29} succs={BB31,BB32} ***** BB30 STMT00070 (IL 0x137...0x139) [000432] ------------ * JTRUE void [000431] N--------U-- \--* NE int [000429] ------------ +--* LCL_VAR ubyte V03 arg3 [000430] ------------ \--* CNS_INT int 1 ------------ BB31 [13B..14B) -> BB70 (always), preds={BB30} succs={BB70} ***** BB31 STMT00077 (IL 0x13B...0x144) [000481] -A-XG------- * ASG ref [000480] ---XG--N---- +--* FIELD ref value [000478] ---XG------- | \--* ADDR byref [000477] ---XG--N---- | \--* INDEX struct [000475] ------------ | +--* LCL_VAR ref V04 loc0 [000476] ------------ | \--* LCL_VAR int V09 loc5 [000479] ------------ \--* LCL_VAR ref V02 arg2 ------------ BB32 [14B..14F) -> BB34 (cond), preds={BB30} succs={BB33,BB34} ***** BB32 STMT00071 (IL 0x14B...0x14D) [000436] ------------ * JTRUE void [000435] N--------U-- \--* NE int [000433] ------------ +--* LCL_VAR ubyte V03 arg3 [000434] ------------ \--* CNS_INT int 2 ------------ BB33 [14F..155), preds={BB32} succs={BB34} ***** BB33 STMT00073 (IL 0x14F...0x150) [000444] -A-X-------- * ASG long [000443] D------N---- +--* LCL_VAR long V26 tmp12 [000442] #--X-------- \--* IND long [000441] !----------- \--* LCL_VAR ref V00 this ***** BB33 STMT00074 (IL ???... ???) [000454] -A---------- * ASG ref [000453] D------N---- +--* LCL_VAR ref V27 tmp13 [000439] ------------ \--* LCL_VAR ref V01 arg1 ***** BB33 STMT00075 (IL ???... ???) [000472] -AC-G------- * ASG long [000471] D------N---- +--* LCL_VAR long V28 tmp14 [000470] --C-G------- \--* QMARK long [000460] Q----------- if +--* NE int [000456] n----------- | +--* IND long [000452] ------------ | | \--* ADD long [000450] #----------- | | +--* IND long [000449] #----------- | | | \--* IND long [000448] ------------ | | | \--* ADD long [000446] ------------ | | | +--* LCL_VAR long V26 tmp12 [000447] ------------ | | | \--* CNS_INT long 56 [000451] ------------ | | \--* CNS_INT long 56 [000459] ------------ | \--* CNS_INT long 0 [000469] --C-G------- if \--* COLON long [000458] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000445] ------------ arg0 | +--* LCL_VAR long V26 tmp12 [000457] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000461] n----------- then \--* IND long [000462] ------------ \--* ADD long [000463] #----------- +--* IND long [000464] #----------- | \--* IND long [000465] ------------ | \--* ADD long [000466] ------------ | +--* LCL_VAR long V26 tmp12 [000467] ------------ | \--* CNS_INT long 56 [000468] ------------ \--* CNS_INT long 56 ***** BB33 STMT00076 (IL ???... ???) [000440] --C-G------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000474] ------------ arg0 +--* RUNTIMELOOKUP long 0xd1ffab1e method [000473] ------------ | \--* LCL_VAR long V28 tmp14 [000455] ------------ arg1 \--* LCL_VAR ref V27 tmp13 ------------ BB34 [155..157) -> BB45 (always), preds={BB32,BB33} succs={BB45} ------------ BB35 [157..170) -> BB27 (cond), preds={BB28,BB29} succs={BB71,BB27} ***** BB35 STMT00065 (IL 0x157...0x164) [000406] -A-XG------- * ASG int [000405] D------N---- +--* LCL_VAR int V09 loc5 [000404] ---XG------- \--* FIELD int next [000403] ---XG------- \--* ADDR byref [000402] ---XG--N---- \--* INDEX struct [000400] ------------ +--* LCL_VAR ref V04 loc0 [000401] ------------ \--* LCL_VAR int V09 loc5 ***** BB35 STMT00066 (IL 0x166...0x169) [000411] -A---------- * ASG int [000410] D------N---- +--* LCL_VAR int V07 loc3 [000409] ------------ \--* ADD int [000407] ------------ +--* LCL_VAR int V07 loc3 [000408] ------------ \--* CNS_INT int 1 ***** BB35 STMT00067 (IL 0x16A...0x16E) [000416] ---X-------- * JTRUE void [000415] N--X-----U-- \--* LE int [000412] ------------ +--* LCL_VAR int V07 loc3 [000414] ---X-------- \--* ARR_LENGTH int [000413] ------------ \--* LCL_VAR ref V04 loc0 ------------ BB71 [???..???) -> BB47 (always), preds={BB35} succs={BB47} ------------ BB36 [170..177) -> BB27 (always), preds={} succs={BB27} ***** BB36 STMT00068 (IL 0x170...0x175) [000417] --C-G------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported ------------ BB37 [177..17E) -> BB48 (cond), preds={BB24,BB46,BB47} succs={BB38,BB48} ***** BB37 STMT00014 (IL 0x177...0x17C) [000066] ---X-------- * JTRUE void [000065] N--X-----U-- \--* GE int [000062] ------------ +--* LCL_VAR int V09 loc5 [000064] ---X-------- \--* ARR_LENGTH int [000063] ------------ \--* LCL_VAR ref V04 loc0 ------------ BB38 [17E..18E) -> BB46 (cond), preds={BB37} succs={BB39,BB46} ***** BB38 STMT00039 (IL 0x17E...0x18C) [000215] ---XG------- * JTRUE void [000214] N--XG----U-- \--* NE int [000212] ---XG------- +--* FIELD int hashCode [000211] ---XG------- | \--* ADDR byref [000210] ---XG--N---- | \--* INDEX struct [000208] ------------ | +--* LCL_VAR ref V04 loc0 [000209] ------------ | \--* LCL_VAR int V09 loc5 [000213] ------------ \--* LCL_VAR int V06 loc2 ------------ BB39 [18E..1A4) -> BB46 (cond), preds={BB38} succs={BB40,BB46} ***** BB39 STMT00045 (IL 0x18E...0x1A2) [000246] -A-XG------- * ASG ref [000245] D------N---- +--* LCL_VAR ref V17 tmp3 [000239] ---XG------- \--* FIELD ref key [000238] ---XG------- \--* ADDR byref [000237] ---XG--N---- \--* INDEX struct [000235] ------------ +--* LCL_VAR ref V04 loc0 [000236] ------------ \--* LCL_VAR int V09 loc5 ***** BB39 STMT00044 (IL 0x18E... ???) [000244] -A-X-------- * ASG long [000243] D------N---- +--* LCL_VAR long V16 tmp2 [000242] #--X-------- \--* IND long [000241] !----------- \--* LCL_VAR ref V00 this ***** BB39 STMT00046 (IL ???... ???) [000257] -A---------- * ASG ref [000256] D------N---- +--* LCL_VAR ref V18 tmp4 [000240] ------------ \--* LCL_VAR ref V01 arg1 ***** BB39 STMT00047 (IL ???... ???) [000275] -AC-G------- * ASG long [000274] D------N---- +--* LCL_VAR long V19 tmp5 [000273] --C-G------- \--* QMARK long [000263] Q----------- if +--* NE int [000259] n----------- | +--* IND long [000255] ------------ | | \--* ADD long [000253] #----------- | | +--* IND long [000252] #----------- | | | \--* IND long [000251] ------------ | | | \--* ADD long [000249] ------------ | | | +--* LCL_VAR long V16 tmp2 [000250] ------------ | | | \--* CNS_INT long 56 [000254] ------------ | | \--* CNS_INT long 48 [000262] ------------ | \--* CNS_INT long 0 [000272] --C-G------- if \--* COLON long [000261] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000248] ------------ arg0 | +--* LCL_VAR long V16 tmp2 [000260] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000264] n----------- then \--* IND long [000265] ------------ \--* ADD long [000266] #----------- +--* IND long [000267] #----------- | \--* IND long [000268] ------------ | \--* ADD long [000269] ------------ | +--* LCL_VAR long V16 tmp2 [000270] ------------ | \--* CNS_INT long 56 [000271] ------------ \--* CNS_INT long 48 ***** BB39 STMT00048 (IL ???... ???) [000278] -A---------- * ASG long [000277] D------N---- +--* LCL_VAR long V20 tmp6 [000276] ------------ \--* LCL_VAR long V19 tmp5 ***** BB39 STMT00049 (IL ???... ???) [000283] --CXG------- * JTRUE void [000282] --CXG------- \--* EQ int [000280] --CXG------- +--* CALL ind stub int [000234] ------------ this in rcx | +--* LCL_VAR ref V05 loc1 [000247] ------------ arg1 | +--* LCL_VAR ref V17 tmp3 [000258] ------------ arg2 | +--* LCL_VAR ref V18 tmp4 [000279] ------------ calli tgt | \--* LCL_VAR long V20 tmp6 [000281] ------------ \--* CNS_INT int 0 ------------ BB40 [1A4..1A8) -> BB42 (cond), preds={BB39} succs={BB41,BB42} ***** BB40 STMT00050 (IL 0x1A4...0x1A6) [000287] ------------ * JTRUE void [000286] N--------U-- \--* NE int [000284] ------------ +--* LCL_VAR ubyte V03 arg3 [000285] ------------ \--* CNS_INT int 1 ------------ BB41 [1A8..1B8) -> BB70 (always), preds={BB40} succs={BB70} ***** BB41 STMT00057 (IL 0x1A8...0x1B1) [000336] -A-XG------- * ASG ref [000335] ---XG--N---- +--* FIELD ref value [000333] ---XG------- | \--* ADDR byref [000332] ---XG--N---- | \--* INDEX struct [000330] ------------ | +--* LCL_VAR ref V04 loc0 [000331] ------------ | \--* LCL_VAR int V09 loc5 [000334] ------------ \--* LCL_VAR ref V02 arg2 ------------ BB42 [1B8..1BC) -> BB44 (cond), preds={BB40} succs={BB43,BB44} ***** BB42 STMT00051 (IL 0x1B8...0x1BA) [000291] ------------ * JTRUE void [000290] N--------U-- \--* NE int [000288] ------------ +--* LCL_VAR ubyte V03 arg3 [000289] ------------ \--* CNS_INT int 2 ------------ BB43 [1BC..1C2), preds={BB42} succs={BB44} ***** BB43 STMT00053 (IL 0x1BC...0x1BD) [000299] -A-X-------- * ASG long [000298] D------N---- +--* LCL_VAR long V21 tmp7 [000297] #--X-------- \--* IND long [000296] !----------- \--* LCL_VAR ref V00 this ***** BB43 STMT00054 (IL ???... ???) [000309] -A---------- * ASG ref [000308] D------N---- +--* LCL_VAR ref V22 tmp8 [000294] ------------ \--* LCL_VAR ref V01 arg1 ***** BB43 STMT00055 (IL ???... ???) [000327] -AC-G------- * ASG long [000326] D------N---- +--* LCL_VAR long V23 tmp9 [000325] --C-G------- \--* QMARK long [000315] Q----------- if +--* NE int [000311] n----------- | +--* IND long [000307] ------------ | | \--* ADD long [000305] #----------- | | +--* IND long [000304] #----------- | | | \--* IND long [000303] ------------ | | | \--* ADD long [000301] ------------ | | | +--* LCL_VAR long V21 tmp7 [000302] ------------ | | | \--* CNS_INT long 56 [000306] ------------ | | \--* CNS_INT long 56 [000314] ------------ | \--* CNS_INT long 0 [000324] --C-G------- if \--* COLON long [000313] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000300] ------------ arg0 | +--* LCL_VAR long V21 tmp7 [000312] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000316] n----------- then \--* IND long [000317] ------------ \--* ADD long [000318] #----------- +--* IND long [000319] #----------- | \--* IND long [000320] ------------ | \--* ADD long [000321] ------------ | +--* LCL_VAR long V21 tmp7 [000322] ------------ | \--* CNS_INT long 56 [000323] ------------ \--* CNS_INT long 56 ***** BB43 STMT00056 (IL ???... ???) [000295] --C-G------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000329] ------------ arg0 +--* RUNTIMELOOKUP long 0xd1ffab1e method [000328] ------------ | \--* LCL_VAR long V23 tmp9 [000310] ------------ arg1 \--* LCL_VAR ref V22 tmp8 ------------ BB44 [1C2..1C4) -> BB45 (always), preds={BB42,BB43} succs={BB45} ------------ BB45 [???..???) (return), preds={BB34,BB44} succs={} ***** BB45 STMT00148 (IL ???... ???) [000811] ------------ * RETURN int [000437] ------------ \--* CNS_INT int 0 ------------ BB46 [1C4..1DD) -> BB37 (cond), preds={BB38,BB39} succs={BB47,BB37} ***** BB46 STMT00040 (IL 0x1C4...0x1D1) [000222] -A-XG------- * ASG int [000221] D------N---- +--* LCL_VAR int V09 loc5 [000220] ---XG------- \--* FIELD int next [000219] ---XG------- \--* ADDR byref [000218] ---XG--N---- \--* INDEX struct [000216] ------------ +--* LCL_VAR ref V04 loc0 [000217] ------------ \--* LCL_VAR int V09 loc5 ***** BB46 STMT00041 (IL 0x1D3...0x1D6) [000227] -A---------- * ASG int [000226] D------N---- +--* LCL_VAR int V07 loc3 [000225] ------------ \--* ADD int [000223] ------------ +--* LCL_VAR int V07 loc3 [000224] ------------ \--* CNS_INT int 1 ***** BB46 STMT00042 (IL 0x1D7...0x1DB) [000232] ---X-------- * JTRUE void [000231] N--X-----U-- \--* LE int [000228] ------------ +--* LCL_VAR int V07 loc3 [000230] ---X-------- \--* ARR_LENGTH int [000229] ------------ \--* LCL_VAR ref V04 loc0 ------------ BB47 [1DD..1E4) -> BB37 (always), preds={BB46,BB71} succs={BB37} ***** BB47 STMT00043 (IL 0x1DD...0x1E2) [000233] --C-G------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported ------------ BB48 [1E4..1ED) -> BB54 (cond), preds={BB27,BB37} succs={BB49,BB54} ***** BB48 STMT00015 (IL 0x1E4...0x1EB) [000071] ---XG------- * JTRUE void [000070] ---XG------- \--* LE int [000068] ---XG------- +--* FIELD int _freeCount [000067] ------------ | \--* LCL_VAR ref V00 this [000069] ------------ \--* CNS_INT int 0 ------------ BB49 [1ED..243), preds={BB48} succs={BB50} ***** BB49 STMT00035 (IL 0x1ED...0x1F3) [000174] -A-XG------- * ASG int [000173] D------N---- +--* LCL_VAR int V10 loc6 [000172] ---XG------- \--* FIELD int _freeList [000171] ------------ \--* LCL_VAR ref V00 this ***** BB49 STMT00120 (IL 0x1F5... ???) [000688] -A-XG------- * ASG bool [000687] D------N---- +--* LCL_VAR bool V49 tmp35 [000680] ---XG------- \--* CAST int <- bool <- int [000186] ---XG------- \--* EQ int [000184] ---XG------- +--* LT int [000182] ---XG------- | +--* SUB int [000175] ------------ | | +--* CNS_INT int -3 [000181] ---XG------- | | \--* FIELD int next [000180] ---XG------- | | \--* ADDR byref [000179] ---XG--N---- | | \--* INDEX struct [000176] ------------ | | +--* LCL_VAR ref V04 loc0 [000178] ---XG------- | | \--* FIELD int _freeList [000177] ------------ | | \--* LCL_VAR ref V00 this [000183] ------------ | \--* CNS_INT int -1 [000185] ------------ \--* CNS_INT int 0 ***** BB49 STMT00123 (IL 0x1F5... ???) [000698] -A--G------- * ASG ref [000697] D------N---- +--* LCL_VAR ref V50 tmp36 [000684] #---G------- \--* IND ref [000683] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ------------ BB50 [1F5..1F6) -> BB52 (cond), preds={BB49} succs={BB51,BB52} ***** BB50 STMT00121 (IL 0x1F5... ???) [000693] ------------ * JTRUE void [000692] ------------ \--* NE int [000690] ------------ +--* LCL_VAR int V49 tmp35 [000691] ------------ \--* CNS_INT int 0 ------------ BB51 [1F5..1F6), preds={BB50} succs={BB52} ***** BB51 STMT00122 (IL 0x1F5... ???) [000696] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000694] ------------ arg0 +--* CNS_STR ref [000695] ------------ arg1 \--* LCL_VAR ref V50 tmp36 ------------ BB52 [1F5..1F6), preds={BB50,BB51} succs={BB53} ------------ BB53 [???..???) -> BB65 (always), preds={BB52} succs={BB65} ***** BB53 STMT00037 (IL 0x219... ???) [000200] -A-XG------- * ASG int [000199] ---XG--N---- +--* FIELD int _freeList [000190] ------------ | \--* LCL_VAR ref V00 this [000198] ---XG------- \--* SUB int [000191] ------------ +--* CNS_INT int -3 [000197] ---XG------- \--* FIELD int next [000196] ---XG------- \--* ADDR byref [000195] ---XG--N---- \--* INDEX struct [000192] ------------ +--* LCL_VAR ref V04 loc0 [000194] ---XG------- \--* FIELD int _freeList [000193] ------------ \--* LCL_VAR ref V00 this ***** BB53 STMT00038 (IL 0x233...0x23C) [000207] -A-XG------- * ASG int [000206] ---XG--N---- +--* FIELD int _freeCount [000201] ------------ | \--* LCL_VAR ref V00 this [000205] ---XG------- \--* SUB int [000203] ---XG------- +--* FIELD int _freeCount [000202] ------------ | \--* LCL_VAR ref V00 this [000204] ------------ \--* CNS_INT int 1 ------------ BB54 [243..252) -> BB64 (cond), preds={BB48} succs={BB55,BB64} ***** BB54 STMT00016 (IL 0x243...0x249) [000075] -A-XG------- * ASG int [000074] D------N---- +--* LCL_VAR int V13 loc9 [000073] ---XG------- \--* FIELD int _count [000072] ------------ \--* LCL_VAR ref V00 this ***** BB54 STMT00017 (IL 0x24B...0x250) [000080] ---X-------- * JTRUE void [000079] N--X-----U-- \--* NE int [000076] ------------ +--* LCL_VAR int V13 loc9 [000078] ---X-------- \--* ARR_LENGTH int [000077] ------------ \--* LCL_VAR ref V04 loc0 ------------ BB55 [252..261), preds={BB54} succs={BB56} ***** BB55 STMT00125 (IL 0x252... ???) [000705] --C-G------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [000163] ------------ this in rcx +--* LCL_VAR ref V00 this [000702] --CXG------- arg1 +--* CALL int System.Collections.HashHelpers.ExpandPrime [000701] ---XG------- arg0 | \--* FIELD int _count [000700] ------------ | \--* LCL_VAR ref V00 this [000706] ------------ arg2 \--* PUTARG_TYPE bool [000704] ------------ \--* CNS_INT int 0 ***** BB55 STMT00126 (IL 0x258... ???) [000711] -A-XG------- * ASG ref [000710] D------N---- +--* LCL_VAR ref V52 tmp38 [000709] ---XG------- \--* FIELD ref _buckets [000165] ------------ \--* LCL_VAR ref V00 this ***** BB55 STMT00133 (IL 0x258... ???) [000760] -A-X-------- * ASG int [000759] D------N---- +--* LCL_VAR int V53 tmp39 [000714] ---X-------- \--* ARR_LENGTH int [000713] ------------ \--* LCL_VAR ref V52 tmp38 ***** BB55 STMT00134 (IL 0x258... ???) [000762] -A-XG------- * ASG long [000761] D------N---- +--* LCL_VAR long V54 tmp40 [000716] ---XG------- \--* FIELD long _fastModMultiplier [000715] ------------ \--* LCL_VAR ref V00 this ***** BB55 STMT00136 (IL 0x258... ???) [000773] -A---------- * ASG bool [000772] D------N---- +--* LCL_VAR bool V56 tmp42 [000764] ------------ \--* CAST int <- bool <- int [000732] ------------ \--* EQ int [000730] N--------U-- +--* GT int [000728] ------------ | +--* LCL_VAR int V53 tmp39 [000729] ------------ | \--* CNS_INT int 0x7FFFFFFF [000731] ------------ \--* CNS_INT int 0 ***** BB55 STMT00139 (IL 0x258... ???) [000783] -A--G------- * ASG ref [000782] D------N---- +--* LCL_VAR ref V57 tmp43 [000767] #---G------- \--* IND ref [000766] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB55 STMT00140 (IL 0x258... ???) [000785] -A--G------- * ASG ref [000784] D------N---- +--* LCL_VAR ref V58 tmp44 [000769] #---G------- \--* IND ref [000768] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ------------ BB56 [258..259) -> BB58 (cond), preds={BB55} succs={BB57,BB58} ***** BB56 STMT00137 (IL 0x258... ???) [000778] ------------ * JTRUE void [000777] ------------ \--* NE int [000775] ------------ +--* LCL_VAR int V56 tmp42 [000776] ------------ \--* CNS_INT int 0 ------------ BB57 [258..259), preds={BB56} succs={BB58} ***** BB57 STMT00138 (IL 0x258... ???) [000781] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000779] ------------ arg0 +--* LCL_VAR ref V57 tmp43 [000780] ------------ arg1 \--* LCL_VAR ref V58 tmp44 ------------ BB58 [258..259), preds={BB56,BB57} succs={BB59} ------------ BB59 [???..???), preds={BB58} succs={BB60} ***** BB59 STMT00131 (IL 0x258... ???) [000750] -A---------- * ASG int [000749] D------N---- +--* LCL_VAR int V55 tmp41 [000748] ------------ \--* CAST int <- uint <- long [000747] ------------ \--* RSZ long [000745] ------------ +--* MUL long [000742] ------------ | +--* ADD long [000739] ------------ | | +--* RSZ long [000737] ------------ | | | +--* MUL long [000735] ------------ | | | | +--* LCL_VAR long V54 tmp40 [000736] ---------U-- | | | | \--* CAST long <- ulong <- uint [000166] ------------ | | | | \--* LCL_VAR int V06 loc2 [000738] ------------ | | | \--* CNS_INT int 32 [000741] ------------ | | \--* CNS_INT long 1 [000744] ---------U-- | \--* CAST long <- ulong <- uint [000743] ------------ | \--* LCL_VAR int V53 tmp39 [000746] ------------ \--* CNS_INT int 32 ***** BB59 STMT00142 (IL 0x258... ???) [000796] -A-X-------- * ASG bool [000795] D------N---- +--* LCL_VAR bool V59 tmp45 [000787] ---X-------- \--* CAST int <- bool <- int [000755] ---X-------- \--* EQ int [000751] ------------ +--* LCL_VAR int V55 tmp41 [000754] ---X-------- \--* UMOD int [000752] ------------ +--* LCL_VAR int V06 loc2 [000753] ------------ \--* LCL_VAR int V53 tmp39 ***** BB59 STMT00145 (IL 0x258... ???) [000806] -A--G------- * ASG ref [000805] D------N---- +--* LCL_VAR ref V60 tmp46 [000790] #---G------- \--* IND ref [000789] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB59 STMT00146 (IL 0x258... ???) [000808] -A--G------- * ASG ref [000807] D------N---- +--* LCL_VAR ref V61 tmp47 [000792] #---G------- \--* IND ref [000791] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ------------ BB60 [258..259) -> BB62 (cond), preds={BB59} succs={BB61,BB62} ***** BB60 STMT00143 (IL 0x258... ???) [000801] ------------ * JTRUE void [000800] ------------ \--* NE int [000798] ------------ +--* LCL_VAR int V59 tmp45 [000799] ------------ \--* CNS_INT int 0 ------------ BB61 [258..259), preds={BB60} succs={BB62} ***** BB61 STMT00144 (IL 0x258... ???) [000804] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000802] ------------ arg0 +--* LCL_VAR ref V60 tmp46 [000803] ------------ arg1 \--* LCL_VAR ref V61 tmp47 ------------ BB62 [258..259), preds={BB60,BB61} succs={BB63} ------------ BB63 [???..???), preds={BB62} succs={BB64} ***** BB63 STMT00128 (IL 0x258... ???) [000722] -ACXG------- * ASG byref [000721] D------N---- +--* LCL_VAR byref V51 tmp37 [000720] --CXG------- \--* ADDR byref [000719] --CXG--N---- \--* INDEX int [000712] ------------ +--* LCL_VAR ref V52 tmp38 [000758] ------------ \--* LCL_VAR int V55 tmp41 ***** BB63 STMT00129 (IL 0x258... ???) [000726] -A---------- * ASG ref [000725] D------N---- +--* LCL_VAR ref V52 tmp38 [000724] ------------ \--* CNS_INT ref null ***** BB63 STMT00034 (IL ???... ???) [000170] -AC--------- * ASG byref [000169] D------N---- +--* LCL_VAR byref V08 loc4 [000723] ------------ \--* LCL_VAR byref V51 tmp37 ------------ BB64 [261..276), preds={BB54,BB63} succs={BB65} ***** BB64 STMT00018 (IL 0x261...0x263) [000083] -A---------- * ASG int [000082] D------N---- +--* LCL_VAR int V10 loc6 [000081] ------------ \--* LCL_VAR int V13 loc9 ***** BB64 STMT00019 (IL 0x265...0x26A) [000089] -A-XG------- * ASG int [000088] ---XG--N---- +--* FIELD int _count [000084] ------------ | \--* LCL_VAR ref V00 this [000087] ------------ \--* ADD int [000085] ------------ +--* LCL_VAR int V13 loc9 [000086] ------------ \--* CNS_INT int 1 ***** BB64 STMT00020 (IL 0x26F...0x275) [000093] -A-XG------- * ASG ref [000092] D------N---- +--* LCL_VAR ref V04 loc0 [000091] ---XG------- \--* FIELD ref _entries [000090] ------------ \--* LCL_VAR ref V00 this ------------ BB65 [276..2CA), preds={BB53,BB64} succs={BB66} ***** BB65 STMT00021 (IL 0x276...0x27E) [000099] -A-XG------- * ASG byref [000098] D------N---- +--* LCL_VAR byref V11 loc7 [000097] ---XG------- \--* ADDR byref [000096] ---XG--N---- \--* INDEX struct [000094] ------------ +--* LCL_VAR ref V04 loc0 [000095] ------------ \--* LCL_VAR int V10 loc6 ***** BB65 STMT00022 (IL 0x280...0x283) [000103] -A-XG------- * ASG int [000102] ---XG--N---- +--* FIELD int hashCode [000100] ------------ | \--* LCL_VAR byref V11 loc7 [000101] ------------ \--* LCL_VAR int V06 loc2 ***** BB65 STMT00023 (IL 0x288...0x28F) [000110] -A-XG------- * ASG int [000109] ---XG--N---- +--* FIELD int next [000104] ------------ | \--* LCL_VAR byref V11 loc7 [000108] ---XG------- \--* SUB int [000106] *--XG------- +--* IND int [000105] ------------ | \--* LCL_VAR byref V08 loc4 [000107] ------------ \--* CNS_INT int 1 ***** BB65 STMT00024 (IL 0x294...0x297) [000114] -A-XG------- * ASG ref [000113] ---XG--N---- +--* FIELD ref key [000111] ------------ | \--* LCL_VAR byref V11 loc7 [000112] ------------ \--* LCL_VAR ref V01 arg1 ***** BB65 STMT00025 (IL 0x29C...0x29F) [000118] -A-XG------- * ASG ref [000117] ---XG--N---- +--* FIELD ref value [000115] ------------ | \--* LCL_VAR byref V11 loc7 [000116] ------------ \--* LCL_VAR ref V02 arg2 ***** BB65 STMT00026 (IL 0x2A4...0x2AA) [000124] -A-XG------- * ASG int [000123] *------N---- +--* IND int [000119] ------------ | \--* LCL_VAR byref V08 loc4 [000122] ------------ \--* ADD int [000120] ------------ +--* LCL_VAR int V10 loc6 [000121] ------------ \--* CNS_INT int 1 ***** BB65 STMT00027 (IL 0x2AB...0x2B4) [000131] -A-XG------- * ASG int [000130] ---XG--N---- +--* FIELD int _version [000125] ------------ | \--* LCL_VAR ref V00 this [000129] ---XG------- \--* ADD int [000127] ---XG------- +--* FIELD int _version [000126] ------------ | \--* LCL_VAR ref V00 this [000128] ------------ \--* CNS_INT int 1 ------------ BB66 [2CA..2CF) -> BB69 (cond), preds={BB65} succs={BB67,BB69} ***** BB66 STMT00028 (IL 0x2CA...0x2CD) [000148] ------------ * JTRUE void [000147] N--------U-- \--* LE int [000145] ------------ +--* LCL_VAR int V07 loc3 [000146] ------------ \--* CNS_INT int 100 ------------ BB67 [2CF..2D7) -> BB69 (cond), preds={BB66} succs={BB68,BB69} ***** BB67 STMT00030 (IL 0x2CF...0x2D5) [000156] --C-G------- * JTRUE void [000155] --C-G------- \--* EQ int [000153] --C-G------- +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS [000152] H------N---- arg0 | +--* CNS_INT(h) long 0xd1ffab1e class [000151] ------------ arg1 | \--* LCL_VAR ref V05 loc1 [000154] ------------ \--* CNS_INT ref null ------------ BB68 [2D7..2E1), preds={BB67} succs={BB69} ***** BB68 STMT00031 (IL 0x2D7...0x2DC) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [000157] ------------ this in rcx +--* LCL_VAR ref V00 this [000159] ---X-------- arg1 +--* ARR_LENGTH int [000158] ------------ | \--* LCL_VAR ref V04 loc0 [000162] ------------ arg2 \--* PUTARG_TYPE bool [000160] ------------ \--* CNS_INT int 1 ------------ BB69 [2E1..2E3) -> BB70 (always), preds={BB66,BB67,BB68} succs={BB70} ------------ BB70 [???..???) (return), preds={BB31,BB41,BB69} succs={} ***** BB70 STMT00147 (IL ???... ???) [000810] ------------ * RETURN int [000482] ------------ \--* CNS_INT int 1 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Update flow graph early pass *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 BB01 1 [008..00E) i BB03 [0002] 2 BB01,BB02 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i BB05 [0004] 2 BB03,BB04 1 [01E..04B) i BB06 [0051] 1 BB05 1 [01E..01F)-> BB08 ( cond ) i BB07 [0052] 1 BB06 1 [01E..01F) i BB08 [0053] 2 BB06,BB07 1 [01E..01F) i BB09 [0054] 1 BB08 1 [???..???) i internal BB10 [0056] 1 BB09 1 [033..034)-> BB12 ( cond ) i BB11 [0057] 1 BB10 1 [033..034) i BB12 [0058] 2 BB10,BB11 1 [033..034) i BB13 [0059] 1 BB12 1 [???..???)-> BB15 ( cond ) internal BB14 [0005] 1 BB13 1 [04B..054)-> BB16 (always) i BB15 [0006] 1 BB13 1 [054..061) i BB16 [0007] 2 BB14,BB15 1 [061..07A) i idxlen BB17 [0063] 1 BB16 1 [064..065)-> BB19 ( cond ) i BB18 [0064] 1 BB17 1 [064..065) i BB19 [0065] 2 BB17,BB18 1 [064..065) i BB20 [0066] 1 BB19 1 [???..???) i internal idxlen BB21 [0068] 1 BB20 1 [064..065)-> BB23 ( cond ) i BB22 [0069] 1 BB21 1 [064..065) i BB23 [0070] 2 BB21,BB22 1 [064..065) i BB24 [0071] 1 BB23 1 [???..???)-> BB37 ( cond ) internal idxlen BB25 [0008] 1 BB24 1 [07A..08B)-> BB26 (always) i BB26 [0019] 1 BB25 1 [0FF..106) i BB27 [0020] 3 BB26,BB35,BB36 1 [106..110)-> BB48 ( cond ) i idxlen bwd bwd-target BB28 [0021] 1 BB27 1 [110..120)-> BB35 ( cond ) i idxlen bwd BB29 [0022] 1 BB28 1 [120..137)-> BB35 ( cond ) i idxlen bwd BB30 [0023] 1 BB29 1 [137..13B)-> BB32 ( cond ) i bwd BB31 [0024] 1 BB30 1 [13B..14B)-> BB70 (always) i idxlen BB32 [0025] 1 BB30 1 [14B..14F)-> BB34 ( cond ) i bwd BB33 [0026] 1 BB32 1 [14F..155) i bwd BB34 [0027] 2 BB32,BB33 1 [155..157)-> BB45 (always) i BB35 [0028] 2 BB28,BB29 1 [157..170)-> BB27 ( cond ) i idxlen bwd BB71 [0093] 1 BB35 1 [???..???)-> BB47 (always) internal BB36 [0029] 0 1 [170..177)-> BB27 (always) i bwd BB37 [0030] 3 BB24,BB46,BB47 1 [177..17E)-> BB48 ( cond ) i idxlen bwd bwd-target BB38 [0031] 1 BB37 1 [17E..18E)-> BB46 ( cond ) i idxlen bwd BB39 [0032] 1 BB38 1 [18E..1A4)-> BB46 ( cond ) i idxlen bwd BB40 [0033] 1 BB39 1 [1A4..1A8)-> BB42 ( cond ) i bwd BB41 [0034] 1 BB40 1 [1A8..1B8)-> BB70 (always) i idxlen BB42 [0035] 1 BB40 1 [1B8..1BC)-> BB44 ( cond ) i bwd BB43 [0036] 1 BB42 1 [1BC..1C2) i bwd BB44 [0037] 2 BB42,BB43 1 [1C2..1C4)-> BB45 (always) i BB45 [0092] 2 BB34,BB44 1 [???..???) (return) internal BB46 [0038] 2 BB38,BB39 1 [1C4..1DD)-> BB37 ( cond ) i idxlen bwd BB47 [0039] 2 BB46,BB71 1 [1DD..1E4)-> BB37 (always) i bwd BB48 [0040] 2 BB27,BB37 1 [1E4..1ED)-> BB54 ( cond ) i BB49 [0041] 1 BB48 1 [1ED..243) i BB50 [0074] 1 BB49 1 [1F5..1F6)-> BB52 ( cond ) i BB51 [0075] 1 BB50 1 [1F5..1F6) i BB52 [0076] 2 BB50,BB51 1 [1F5..1F6) i BB53 [0077] 1 BB52 1 [???..???)-> BB65 (always) internal BB54 [0042] 1 BB48 1 [243..252)-> BB64 ( cond ) i idxlen BB55 [0043] 1 BB54 1 [252..261) i idxlen BB56 [0082] 1 BB55 1 [258..259)-> BB58 ( cond ) i BB57 [0083] 1 BB56 1 [258..259) i BB58 [0084] 2 BB56,BB57 1 [258..259) i BB59 [0085] 1 BB58 1 [???..???) i internal idxlen BB60 [0087] 1 BB59 1 [258..259)-> BB62 ( cond ) i BB61 [0088] 1 BB60 1 [258..259) i BB62 [0089] 2 BB60,BB61 1 [258..259) i BB63 [0090] 1 BB62 1 [???..???) internal idxlen BB64 [0044] 2 BB54,BB63 1 [261..276) i BB65 [0045] 2 BB53,BB64 1 [276..2CA) i idxlen BB66 [0046] 1 BB65 1 [2CA..2CF)-> BB69 ( cond ) i BB67 [0047] 1 BB66 1 [2CF..2D7)-> BB69 ( cond ) i BB68 [0048] 1 BB67 1 [2D7..2E1) i idxlen BB69 [0049] 3 BB66,BB67,BB68 1 [2E1..2E3)-> BB70 (always) i BB70 [0091] 3 BB31,BB41,BB69 1 [???..???) (return) internal ----------------------------------------------------------------------------------------------------------------------------------------- Compacting blocks BB05 and BB06: *************** In fgDebugCheckBBlist Compacting blocks BB08 and BB09: *************** In fgDebugCheckBBlist Compacting blocks BB08 and BB10: *************** In fgDebugCheckBBlist Compacting blocks BB12 and BB13: *************** In fgDebugCheckBBlist Compacting blocks BB16 and BB17: *************** In fgDebugCheckBBlist Compacting blocks BB19 and BB20: *************** In fgDebugCheckBBlist Compacting blocks BB19 and BB21: *************** In fgDebugCheckBBlist Compacting blocks BB23 and BB24: *************** In fgDebugCheckBBlist Removing unconditional jump to next block (BB25 -> BB26) (converted BB25 to fall-through) Compacting blocks BB25 and BB26: *************** In fgDebugCheckBBlist Optimizing a jump to an unconditional jump (BB32 -> BB34 -> BB45) Setting edge weights for BB32 -> BB45 to [0 .. 3.402823e+38] Compacting blocks BB33 and BB34: *************** In fgDebugCheckBBlist fgRemoveBlock BB36 Removing unreachable BB36 removing useless STMT00068 (IL 0x170...0x175) [000417] --C-G------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported from BB36 BB36 becomes empty Optimizing a jump to an unconditional jump (BB42 -> BB44 -> BB45) Setting edge weights for BB42 -> BB45 to [0 .. 3.402823e+38] Compacting blocks BB43 and BB44: *************** In fgDebugCheckBBlist Removing unconditional jump to next block (BB43 -> BB45) (converted BB43 to fall-through) Compacting blocks BB49 and BB50: *************** In fgDebugCheckBBlist Compacting blocks BB52 and BB53: *************** In fgDebugCheckBBlist Compacting blocks BB55 and BB56: *************** In fgDebugCheckBBlist Compacting blocks BB58 and BB59: *************** In fgDebugCheckBBlist Compacting blocks BB58 and BB60: *************** In fgDebugCheckBBlist Compacting blocks BB62 and BB63: *************** In fgDebugCheckBBlist Compacting blocks BB65 and BB66: *************** In fgDebugCheckBBlist Optimizing a jump to an unconditional jump (BB65 -> BB69 -> BB70) Setting edge weights for BB65 -> BB70 to [0 .. 3.402823e+38] Optimizing a jump to an unconditional jump (BB67 -> BB69 -> BB70) Setting edge weights for BB67 -> BB70 to [0 .. 3.402823e+38] Compacting blocks BB68 and BB69: *************** In fgDebugCheckBBlist Removing unconditional jump to next block (BB68 -> BB70) (converted BB68 to fall-through) After updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 BB01 1 [008..00E) i BB03 [0002] 2 BB01,BB02 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i BB05 [0004] 2 BB03,BB04 1 [01E..04B)-> BB08 ( cond ) i BB07 [0052] 1 BB05 1 [01E..01F) i BB08 [0053] 2 BB05,BB07 1 [01E..034)-> BB12 ( cond ) i BB11 [0057] 1 BB08 1 [033..034) i BB12 [0058] 2 BB08,BB11 1 [033..034)-> BB15 ( cond ) i BB14 [0005] 1 BB12 1 [04B..054)-> BB16 (always) i BB15 [0006] 1 BB12 1 [054..061) i BB16 [0007] 2 BB14,BB15 1 [061..07A)-> BB19 ( cond ) i idxlen BB18 [0064] 1 BB16 1 [064..065) i BB19 [0065] 2 BB16,BB18 1 [064..065)-> BB23 ( cond ) i idxlen BB22 [0069] 1 BB19 1 [064..065) i BB23 [0070] 2 BB19,BB22 1 [064..065)-> BB37 ( cond ) i idxlen BB25 [0008] 1 BB23 1 [07A..106) i BB27 [0020] 2 BB25,BB35 1 [106..110)-> BB48 ( cond ) i idxlen bwd bwd-target BB28 [0021] 1 BB27 1 [110..120)-> BB35 ( cond ) i idxlen bwd BB29 [0022] 1 BB28 1 [120..137)-> BB35 ( cond ) i idxlen bwd BB30 [0023] 1 BB29 1 [137..13B)-> BB32 ( cond ) i bwd BB31 [0024] 1 BB30 1 [13B..14B)-> BB70 (always) i idxlen BB32 [0025] 1 BB30 1 [14B..14F)-> BB45 ( cond ) i bwd BB33 [0026] 1 BB32 1 [14F..157)-> BB45 (always) i bwd BB35 [0028] 2 BB28,BB29 1 [157..170)-> BB27 ( cond ) i idxlen bwd BB71 [0093] 1 BB35 1 [???..???)-> BB47 (always) internal BB37 [0030] 3 BB23,BB46,BB47 1 [177..17E)-> BB48 ( cond ) i idxlen bwd bwd-target BB38 [0031] 1 BB37 1 [17E..18E)-> BB46 ( cond ) i idxlen bwd BB39 [0032] 1 BB38 1 [18E..1A4)-> BB46 ( cond ) i idxlen bwd BB40 [0033] 1 BB39 1 [1A4..1A8)-> BB42 ( cond ) i bwd BB41 [0034] 1 BB40 1 [1A8..1B8)-> BB70 (always) i idxlen BB42 [0035] 1 BB40 1 [1B8..1BC)-> BB45 ( cond ) i bwd BB43 [0036] 1 BB42 1 [1BC..1C4) i bwd BB45 [0092] 4 BB32,BB33,BB42,BB43 1 [???..???) (return) internal BB46 [0038] 2 BB38,BB39 1 [1C4..1DD)-> BB37 ( cond ) i idxlen bwd BB47 [0039] 2 BB46,BB71 1 [1DD..1E4)-> BB37 (always) i bwd BB48 [0040] 2 BB27,BB37 1 [1E4..1ED)-> BB54 ( cond ) i BB49 [0041] 1 BB48 1 [1ED..243)-> BB52 ( cond ) i BB51 [0075] 1 BB49 1 [1F5..1F6) i BB52 [0076] 2 BB49,BB51 1 [1F5..1F6)-> BB65 (always) i BB54 [0042] 1 BB48 1 [243..252)-> BB64 ( cond ) i idxlen BB55 [0043] 1 BB54 1 [252..261)-> BB58 ( cond ) i idxlen BB57 [0083] 1 BB55 1 [258..259) i BB58 [0084] 2 BB55,BB57 1 [258..259)-> BB62 ( cond ) i idxlen BB61 [0088] 1 BB58 1 [258..259) i BB62 [0089] 2 BB58,BB61 1 [258..259) i idxlen BB64 [0044] 2 BB54,BB62 1 [261..276) i BB65 [0045] 2 BB52,BB64 1 [276..2CF)-> BB70 ( cond ) i idxlen BB67 [0047] 1 BB65 1 [2CF..2D7)-> BB70 ( cond ) i BB68 [0048] 1 BB67 1 [2D7..2E3) i idxlen BB70 [0091] 5 BB31,BB41,BB65,BB67,BB68 1 [???..???) (return) internal ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** Finishing PHASE Update flow graph early pass *************** Starting PHASE Morph - Promote Structs *************** In fgResetImplicitByRefRefCount() *************** In fgPromoteStructs() lvaTable before fgPromoteStructs ; Initial local variable assignments ; ; V00 this ref this class-hnd ; V01 arg1 ref ld-addr-op class-hnd ; V02 arg2 ref class-hnd ; V03 arg3 ubyte ; V04 loc0 ref class-hnd ; V05 loc1 ref class-hnd ; V06 loc2 int ; V07 loc3 int ; V08 loc4 byref ; V09 loc5 int ; V10 loc6 int ; V11 loc7 byref ; V12 loc8 ref class-hnd ; V13 loc9 int ; V14 OutArgs lclBlk "OutgoingArgSpace" ; V15 tmp1 int ; V16 tmp2 long "impRuntimeLookup slot" ; V17 tmp3 ref class-hnd "impAppendStmt" ; V18 tmp4 ref class-hnd "bubbling QMark1" ; V19 tmp5 long "spilling Runtime Lookup tree" ; V20 tmp6 long "VirtualCall with runtime lookup" ; V21 tmp7 long "impRuntimeLookup slot" ; V22 tmp8 ref class-hnd "bubbling QMark1" ; V23 tmp9 long "spilling Runtime Lookup tree" ; V24 tmp10 long "impRuntimeLookup slot" ; V25 tmp11 long "spilling Runtime Lookup tree" ; V26 tmp12 long "impRuntimeLookup slot" ; V27 tmp13 ref class-hnd "bubbling QMark1" ; V28 tmp14 long "spilling Runtime Lookup tree" ; V29 tmp15 long "impRuntimeLookup slot" ; V30 tmp16 ref class-hnd "bubbling QMark1" ; V31 tmp17 long "spilling Runtime Lookup tree" ; V32 tmp18 long "VirtualCall with runtime lookup" ; V33 tmp19 bool "Inlining Arg" ; V34 tmp20 ref class-hnd "Inlining Arg" ; V35 tmp21 ref class-hnd "Inlining Arg" ; V36 tmp22 bool "Inlining Arg" ; V37 tmp23 ref class-hnd "Inlining Arg" ; V38 tmp24 byref "Inline return value spill temp" ; V39 tmp25 ref class-hnd "Inline stloc first use temp" ; V40 tmp26 int "Inlining Arg" ; V41 tmp27 long "Inlining Arg" ; V42 tmp28 int "Inline stloc first use temp" ; V43 tmp29 bool "Inlining Arg" ; V44 tmp30 ref class-hnd "Inlining Arg" ; V45 tmp31 ref class-hnd "Inlining Arg" ; V46 tmp32 bool "Inlining Arg" ; V47 tmp33 ref class-hnd "Inlining Arg" ; V48 tmp34 ref class-hnd "Inlining Arg" ; V49 tmp35 bool "Inlining Arg" ; V50 tmp36 ref class-hnd "Inlining Arg" ; V51 tmp37 byref "Inline return value spill temp" ; V52 tmp38 ref class-hnd "Inline stloc first use temp" ; V53 tmp39 int "Inlining Arg" ; V54 tmp40 long "Inlining Arg" ; V55 tmp41 int "Inline stloc first use temp" ; V56 tmp42 bool "Inlining Arg" ; V57 tmp43 ref class-hnd "Inlining Arg" ; V58 tmp44 ref class-hnd "Inlining Arg" ; V59 tmp45 bool "Inlining Arg" ; V60 tmp46 ref class-hnd "Inlining Arg" ; V61 tmp47 ref class-hnd "Inlining Arg" lvaTable after fgPromoteStructs ; Initial local variable assignments ; ; V00 this ref this class-hnd ; V01 arg1 ref ld-addr-op class-hnd ; V02 arg2 ref class-hnd ; V03 arg3 ubyte ; V04 loc0 ref class-hnd ; V05 loc1 ref class-hnd ; V06 loc2 int ; V07 loc3 int ; V08 loc4 byref ; V09 loc5 int ; V10 loc6 int ; V11 loc7 byref ; V12 loc8 ref class-hnd ; V13 loc9 int ; V14 OutArgs lclBlk "OutgoingArgSpace" ; V15 tmp1 int ; V16 tmp2 long "impRuntimeLookup slot" ; V17 tmp3 ref class-hnd "impAppendStmt" ; V18 tmp4 ref class-hnd "bubbling QMark1" ; V19 tmp5 long "spilling Runtime Lookup tree" ; V20 tmp6 long "VirtualCall with runtime lookup" ; V21 tmp7 long "impRuntimeLookup slot" ; V22 tmp8 ref class-hnd "bubbling QMark1" ; V23 tmp9 long "spilling Runtime Lookup tree" ; V24 tmp10 long "impRuntimeLookup slot" ; V25 tmp11 long "spilling Runtime Lookup tree" ; V26 tmp12 long "impRuntimeLookup slot" ; V27 tmp13 ref class-hnd "bubbling QMark1" ; V28 tmp14 long "spilling Runtime Lookup tree" ; V29 tmp15 long "impRuntimeLookup slot" ; V30 tmp16 ref class-hnd "bubbling QMark1" ; V31 tmp17 long "spilling Runtime Lookup tree" ; V32 tmp18 long "VirtualCall with runtime lookup" ; V33 tmp19 bool "Inlining Arg" ; V34 tmp20 ref class-hnd "Inlining Arg" ; V35 tmp21 ref class-hnd "Inlining Arg" ; V36 tmp22 bool "Inlining Arg" ; V37 tmp23 ref class-hnd "Inlining Arg" ; V38 tmp24 byref "Inline return value spill temp" ; V39 tmp25 ref class-hnd "Inline stloc first use temp" ; V40 tmp26 int "Inlining Arg" ; V41 tmp27 long "Inlining Arg" ; V42 tmp28 int "Inline stloc first use temp" ; V43 tmp29 bool "Inlining Arg" ; V44 tmp30 ref class-hnd "Inlining Arg" ; V45 tmp31 ref class-hnd "Inlining Arg" ; V46 tmp32 bool "Inlining Arg" ; V47 tmp33 ref class-hnd "Inlining Arg" ; V48 tmp34 ref class-hnd "Inlining Arg" ; V49 tmp35 bool "Inlining Arg" ; V50 tmp36 ref class-hnd "Inlining Arg" ; V51 tmp37 byref "Inline return value spill temp" ; V52 tmp38 ref class-hnd "Inline stloc first use temp" ; V53 tmp39 int "Inlining Arg" ; V54 tmp40 long "Inlining Arg" ; V55 tmp41 int "Inline stloc first use temp" ; V56 tmp42 bool "Inlining Arg" ; V57 tmp43 ref class-hnd "Inlining Arg" ; V58 tmp44 ref class-hnd "Inlining Arg" ; V59 tmp45 bool "Inlining Arg" ; V60 tmp46 ref class-hnd "Inlining Arg" ; V61 tmp47 ref class-hnd "Inlining Arg" *************** Finishing PHASE Morph - Promote Structs *************** Starting PHASE Morph - Structs/AddrExp *************** In fgMarkAddressExposedLocals() LocalAddressVisitor visiting statement: STMT00000 (IL 0x000...0x006) [000003] ------------ * JTRUE void [000002] ------------ \--* NE int [000000] ------------ +--* LCL_VAR ref V01 arg1 [000001] ------------ \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00086 (IL 0x008...0x009) [000533] --C-G------- * CALL void System.ThrowHelper.ThrowArgumentNullException [000532] ------------ arg0 \--* CNS_INT int 4 LocalAddressVisitor visiting statement: STMT00001 (IL 0x00E...0x014) [000008] ---XG------- * JTRUE void [000007] ---XG------- \--* NE int [000005] ---XG------- +--* FIELD ref _buckets [000004] ------------ | \--* LCL_VAR ref V00 this [000006] ------------ \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00085 (IL ???... ???) [000528] --C-G------- * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize [000526] ------------ this in rcx +--* LCL_VAR ref V00 this [000527] ------------ arg1 \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00088 (IL 0x01E... ???) [000544] -A-XG------- * ASG bool [000543] D------N---- +--* LCL_VAR bool V33 tmp19 [000535] ---XG------- \--* CAST int <- bool <- int [000012] N--XG----U-- \--* GT int [000010] ---XG------- +--* FIELD ref _buckets [000009] ------------ | \--* LCL_VAR ref V00 this [000011] ------------ \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00091 (IL 0x01E... ???) [000554] -A--G------- * ASG ref [000553] D------N---- +--* LCL_VAR ref V34 tmp20 [000538] #---G------- \--* IND ref [000537] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] LocalAddressVisitor visiting statement: STMT00092 (IL 0x01E... ???) [000556] -A--G------- * ASG ref [000555] D------N---- +--* LCL_VAR ref V35 tmp21 [000540] #---G------- \--* IND ref [000539] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] LocalAddressVisitor visiting statement: STMT00089 (IL 0x01E... ???) [000549] ------------ * JTRUE void [000548] ------------ \--* NE int [000546] ------------ +--* LCL_VAR int V33 tmp19 [000547] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00090 (IL 0x01E... ???) [000552] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000550] ------------ arg0 +--* LCL_VAR ref V34 tmp20 [000551] ------------ arg1 \--* LCL_VAR ref V35 tmp21 LocalAddressVisitor visiting statement: STMT00003 (IL 0x02C... ???) [000018] -A-XG------- * ASG ref [000017] D------N---- +--* LCL_VAR ref V04 loc0 [000016] ---XG------- \--* FIELD ref _entries [000015] ------------ \--* LCL_VAR ref V00 this LocalAddressVisitor visiting statement: STMT00094 (IL 0x033... ???) [000566] -A---------- * ASG bool [000565] D------N---- +--* LCL_VAR bool V36 tmp22 [000558] ------------ \--* CAST int <- bool <- int [000021] N--------U-- \--* GT int [000019] ------------ +--* LCL_VAR ref V04 loc0 [000020] ------------ \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00097 (IL 0x033... ???) [000576] -A--G------- * ASG ref [000575] D------N---- +--* LCL_VAR ref V37 tmp23 [000562] #---G------- \--* IND ref [000561] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] LocalAddressVisitor visiting statement: STMT00095 (IL 0x033... ???) [000571] ------------ * JTRUE void [000570] ------------ \--* NE int [000568] ------------ +--* LCL_VAR int V36 tmp22 [000569] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00096 (IL 0x033... ???) [000574] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000572] ------------ arg0 +--* CNS_STR ref [000573] ------------ arg1 \--* LCL_VAR ref V37 tmp23 LocalAddressVisitor visiting statement: STMT00005 (IL 0x041... ???) [000028] -A-XG------- * ASG ref [000027] D------N---- +--* LCL_VAR ref V05 loc1 [000026] ---XG------- \--* FIELD ref _comparer [000025] ------------ \--* LCL_VAR ref V00 this LocalAddressVisitor visiting statement: STMT00006 (IL 0x048...0x049) [000032] ------------ * JTRUE void [000031] ------------ \--* EQ int [000029] ------------ +--* LCL_VAR ref V05 loc1 [000030] ------------ \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00079 (IL 0x04B...0x052) [000489] -A-X-------- * ASG long [000488] D------N---- +--* LCL_VAR long V29 tmp15 [000487] #--X-------- \--* IND long [000486] !----------- \--* LCL_VAR ref V00 this LocalAddressVisitor visiting statement: STMT00080 (IL ???... ???) [000499] -A---------- * ASG ref [000498] D------N---- +--* LCL_VAR ref V30 tmp16 [000485] ------------ \--* LCL_VAR ref V01 arg1 LocalAddressVisitor visiting statement: STMT00081 (IL ???... ???) [000517] -AC-G------- * ASG long [000516] D------N---- +--* LCL_VAR long V31 tmp17 [000515] --C-G------- \--* QMARK long [000505] Q----------- if +--* NE int [000501] n----------- | +--* IND long [000497] ------------ | | \--* ADD long [000495] #----------- | | +--* IND long [000494] #----------- | | | \--* IND long [000493] ------------ | | | \--* ADD long [000491] ------------ | | | +--* LCL_VAR long V29 tmp15 [000492] ------------ | | | \--* CNS_INT long 56 [000496] ------------ | | \--* CNS_INT long 64 [000504] ------------ | \--* CNS_INT long 0 [000514] --C-G------- if \--* COLON long [000503] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000490] ------------ arg0 | +--* LCL_VAR long V29 tmp15 [000502] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000506] n----------- then \--* IND long [000507] ------------ \--* ADD long [000508] #----------- +--* IND long [000509] #----------- | \--* IND long [000510] ------------ | \--* ADD long [000511] ------------ | +--* LCL_VAR long V29 tmp15 [000512] ------------ | \--* CNS_INT long 56 [000513] ------------ \--* CNS_INT long 64 LocalAddressVisitor visiting statement: STMT00082 (IL ???... ???) [000520] -A---------- * ASG long [000519] D------N---- +--* LCL_VAR long V32 tmp18 [000518] ------------ \--* LCL_VAR long V31 tmp17 LocalAddressVisitor visiting statement: STMT00083 (IL ???... ???) [000524] -ACXG------- * ASG int [000523] D------N---- +--* LCL_VAR int V15 tmp1 [000522] --CXG------- \--* CALL ind stub int [000484] ------------ this in rcx +--* LCL_VAR ref V05 loc1 [000500] ------------ arg1 +--* LCL_VAR ref V30 tmp16 [000521] ------------ calli tgt \--* LCL_VAR long V32 tmp18 LocalAddressVisitor visiting statement: STMT00007 (IL 0x054...0x05C) [000038] -ACXG------- * ASG int [000037] D------N---- +--* LCL_VAR int V15 tmp1 [000035] --CXG------- \--* CALLV vt-ind int System.Object.GetHashCode [000036] *--XG------- this in rcx \--* IND ref [000034] ------------ \--* ADDR long [000033] -------N---- \--* LCL_VAR ref V01 arg1 LocalAddressVisitor visiting statement: STMT00008 (IL ???...0x061) [000042] -A---------- * ASG int [000041] D------N---- +--* LCL_VAR int V06 loc2 [000040] ------------ \--* LCL_VAR int V15 tmp1 LocalAddressVisitor visiting statement: STMT00009 (IL 0x062...0x063) [000045] -A---------- * ASG int [000044] D------N---- +--* LCL_VAR int V07 loc3 [000043] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00098 (IL 0x064... ???) [000580] -A-XG------- * ASG ref [000579] D------N---- +--* LCL_VAR ref V39 tmp25 [000578] ---XG------- \--* FIELD ref _buckets [000046] ------------ \--* LCL_VAR ref V00 this LocalAddressVisitor visiting statement: STMT00105 (IL 0x064... ???) [000629] -A-X-------- * ASG int [000628] D------N---- +--* LCL_VAR int V40 tmp26 [000583] ---X-------- \--* ARR_LENGTH int [000582] ------------ \--* LCL_VAR ref V39 tmp25 LocalAddressVisitor visiting statement: STMT00106 (IL 0x064... ???) [000631] -A-XG------- * ASG long [000630] D------N---- +--* LCL_VAR long V41 tmp27 [000585] ---XG------- \--* FIELD long _fastModMultiplier [000584] ------------ \--* LCL_VAR ref V00 this LocalAddressVisitor visiting statement: STMT00108 (IL 0x064... ???) [000642] -A---------- * ASG bool [000641] D------N---- +--* LCL_VAR bool V43 tmp29 [000633] ------------ \--* CAST int <- bool <- int [000601] ------------ \--* EQ int [000599] N--------U-- +--* GT int [000597] ------------ | +--* LCL_VAR int V40 tmp26 [000598] ------------ | \--* CNS_INT int 0x7FFFFFFF [000600] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00111 (IL 0x064... ???) [000652] -A--G------- * ASG ref [000651] D------N---- +--* LCL_VAR ref V44 tmp30 [000636] #---G------- \--* IND ref [000635] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] LocalAddressVisitor visiting statement: STMT00112 (IL 0x064... ???) [000654] -A--G------- * ASG ref [000653] D------N---- +--* LCL_VAR ref V45 tmp31 [000638] #---G------- \--* IND ref [000637] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] LocalAddressVisitor visiting statement: STMT00109 (IL 0x064... ???) [000647] ------------ * JTRUE void [000646] ------------ \--* NE int [000644] ------------ +--* LCL_VAR int V43 tmp29 [000645] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00110 (IL 0x064... ???) [000650] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000648] ------------ arg0 +--* LCL_VAR ref V44 tmp30 [000649] ------------ arg1 \--* LCL_VAR ref V45 tmp31 LocalAddressVisitor visiting statement: STMT00103 (IL 0x064... ???) [000619] -A---------- * ASG int [000618] D------N---- +--* LCL_VAR int V42 tmp28 [000617] ------------ \--* CAST int <- uint <- long [000616] ------------ \--* RSZ long [000614] ------------ +--* MUL long [000611] ------------ | +--* ADD long [000608] ------------ | | +--* RSZ long [000606] ------------ | | | +--* MUL long [000604] ------------ | | | | +--* LCL_VAR long V41 tmp27 [000605] ---------U-- | | | | \--* CAST long <- ulong <- uint [000047] ------------ | | | | \--* LCL_VAR int V06 loc2 [000607] ------------ | | | \--* CNS_INT int 32 [000610] ------------ | | \--* CNS_INT long 1 [000613] ---------U-- | \--* CAST long <- ulong <- uint [000612] ------------ | \--* LCL_VAR int V40 tmp26 [000615] ------------ \--* CNS_INT int 32 LocalAddressVisitor visiting statement: STMT00114 (IL 0x064... ???) [000665] -A-X-------- * ASG bool [000664] D------N---- +--* LCL_VAR bool V46 tmp32 [000656] ---X-------- \--* CAST int <- bool <- int [000624] ---X-------- \--* EQ int [000620] ------------ +--* LCL_VAR int V42 tmp28 [000623] ---X-------- \--* UMOD int [000621] ------------ +--* LCL_VAR int V06 loc2 [000622] ------------ \--* LCL_VAR int V40 tmp26 LocalAddressVisitor visiting statement: STMT00117 (IL 0x064... ???) [000675] -A--G------- * ASG ref [000674] D------N---- +--* LCL_VAR ref V47 tmp33 [000659] #---G------- \--* IND ref [000658] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] LocalAddressVisitor visiting statement: STMT00118 (IL 0x064... ???) [000677] -A--G------- * ASG ref [000676] D------N---- +--* LCL_VAR ref V48 tmp34 [000661] #---G------- \--* IND ref [000660] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] LocalAddressVisitor visiting statement: STMT00115 (IL 0x064... ???) [000670] ------------ * JTRUE void [000669] ------------ \--* NE int [000667] ------------ +--* LCL_VAR int V46 tmp32 [000668] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00116 (IL 0x064... ???) [000673] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000671] ------------ arg0 +--* LCL_VAR ref V47 tmp33 [000672] ------------ arg1 \--* LCL_VAR ref V48 tmp34 LocalAddressVisitor visiting statement: STMT00100 (IL 0x064... ???) [000591] -ACXG------- * ASG byref [000590] D------N---- +--* LCL_VAR byref V38 tmp24 [000589] --CXG------- \--* ADDR byref [000588] --CXG--N---- \--* INDEX int [000581] ------------ +--* LCL_VAR ref V39 tmp25 [000627] ------------ \--* LCL_VAR int V42 tmp28 LocalAddressVisitor visiting statement: STMT00101 (IL 0x064... ???) [000595] -A---------- * ASG ref [000594] D------N---- +--* LCL_VAR ref V39 tmp25 [000593] ------------ \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00011 (IL ???... ???) [000051] -AC--------- * ASG byref [000050] D------N---- +--* LCL_VAR byref V08 loc4 [000592] ------------ \--* LCL_VAR byref V38 tmp24 LocalAddressVisitor visiting statement: STMT00012 (IL 0x06D...0x072) [000057] -A-XG------- * ASG int [000056] D------N---- +--* LCL_VAR int V09 loc5 [000055] ---XG------- \--* SUB int [000053] *--XG------- +--* IND int [000052] ------------ | \--* LCL_VAR byref V08 loc4 [000054] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00013 (IL 0x074...0x075) [000061] ------------ * JTRUE void [000060] ------------ \--* NE int [000058] ------------ +--* LCL_VAR ref V05 loc1 [000059] ------------ \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00059 (IL 0x0FF...0x104) [000356] -A-X-------- * ASG long [000355] D------N---- +--* LCL_VAR long V24 tmp10 [000354] #--X-------- \--* IND long [000353] !----------- \--* LCL_VAR ref V00 this LocalAddressVisitor visiting statement: STMT00060 (IL ???... ???) [000381] -AC-G------- * ASG long [000380] D------N---- +--* LCL_VAR long V25 tmp11 [000379] --C-G------- \--* QMARK long [000369] Q----------- if +--* NE int [000365] n----------- | +--* IND long [000364] ------------ | | \--* ADD long [000362] #----------- | | +--* IND long [000361] #----------- | | | \--* IND long [000360] ------------ | | | \--* ADD long [000358] ------------ | | | +--* LCL_VAR long V24 tmp10 [000359] ------------ | | | \--* CNS_INT long 56 [000363] ------------ | | \--* CNS_INT long 32 [000368] ------------ | \--* CNS_INT long 0 [000378] --C-G------- if \--* COLON long [000367] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000357] ------------ arg0 | +--* LCL_VAR long V24 tmp10 [000366] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000370] n----------- then \--* IND long [000371] ------------ \--* ADD long [000372] #----------- +--* IND long [000373] #----------- | \--* IND long [000374] ------------ | \--* ADD long [000375] ------------ | +--* LCL_VAR long V24 tmp10 [000376] ------------ | \--* CNS_INT long 56 [000377] ------------ \--* CNS_INT long 32 LocalAddressVisitor visiting statement: STMT00062 (IL ???... ???) [000386] -AC--------- * ASG ref [000385] D------N---- +--* LCL_VAR ref V12 loc8 [000352] --C-G------- \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default [000383] ------------ arg0 \--* RUNTIMELOOKUP long 0xd1ffab1e class [000382] ------------ \--* LCL_VAR long V25 tmp11 LocalAddressVisitor visiting statement: STMT00063 (IL 0x106...0x10B) [000391] ---X-------- * JTRUE void [000390] N--X-----U-- \--* GE int [000387] ------------ +--* LCL_VAR int V09 loc5 [000389] ---X-------- \--* ARR_LENGTH int [000388] ------------ \--* LCL_VAR ref V04 loc0 LocalAddressVisitor visiting statement: STMT00064 (IL 0x110...0x11E) [000399] ---XG------- * JTRUE void [000398] N--XG----U-- \--* NE int [000396] ---XG------- +--* FIELD int hashCode [000395] ---XG------- | \--* ADDR byref [000394] ---XG--N---- | \--* INDEX struct [000392] ------------ | +--* LCL_VAR ref V04 loc0 [000393] ------------ | \--* LCL_VAR int V09 loc5 [000397] ------------ \--* LCL_VAR int V06 loc2 LocalAddressVisitor visiting statement: STMT00069 (IL 0x120...0x135) [000428] --CXG------- * JTRUE void [000427] --CXG------- \--* EQ int [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 [000423] ---XG------- arg1 | +--* FIELD ref key [000422] ---XG------- | | \--* ADDR byref [000421] ---XG--N---- | | \--* INDEX struct [000419] ------------ | | +--* LCL_VAR ref V04 loc0 [000420] ------------ | | \--* LCL_VAR int V09 loc5 [000424] ------------ arg2 | \--* LCL_VAR ref V01 arg1 [000426] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00070 (IL 0x137...0x139) [000432] ------------ * JTRUE void [000431] N--------U-- \--* NE int [000429] ------------ +--* LCL_VAR ubyte V03 arg3 [000430] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00077 (IL 0x13B...0x144) [000481] -A-XG------- * ASG ref [000480] ---XG--N---- +--* FIELD ref value [000478] ---XG------- | \--* ADDR byref [000477] ---XG--N---- | \--* INDEX struct [000475] ------------ | +--* LCL_VAR ref V04 loc0 [000476] ------------ | \--* LCL_VAR int V09 loc5 [000479] ------------ \--* LCL_VAR ref V02 arg2 LocalAddressVisitor visiting statement: STMT00071 (IL 0x14B...0x14D) [000436] ------------ * JTRUE void [000435] N--------U-- \--* NE int [000433] ------------ +--* LCL_VAR ubyte V03 arg3 [000434] ------------ \--* CNS_INT int 2 LocalAddressVisitor visiting statement: STMT00073 (IL 0x14F...0x150) [000444] -A-X-------- * ASG long [000443] D------N---- +--* LCL_VAR long V26 tmp12 [000442] #--X-------- \--* IND long [000441] !----------- \--* LCL_VAR ref V00 this LocalAddressVisitor visiting statement: STMT00074 (IL ???... ???) [000454] -A---------- * ASG ref [000453] D------N---- +--* LCL_VAR ref V27 tmp13 [000439] ------------ \--* LCL_VAR ref V01 arg1 LocalAddressVisitor visiting statement: STMT00075 (IL ???... ???) [000472] -AC-G------- * ASG long [000471] D------N---- +--* LCL_VAR long V28 tmp14 [000470] --C-G------- \--* QMARK long [000460] Q----------- if +--* NE int [000456] n----------- | +--* IND long [000452] ------------ | | \--* ADD long [000450] #----------- | | +--* IND long [000449] #----------- | | | \--* IND long [000448] ------------ | | | \--* ADD long [000446] ------------ | | | +--* LCL_VAR long V26 tmp12 [000447] ------------ | | | \--* CNS_INT long 56 [000451] ------------ | | \--* CNS_INT long 56 [000459] ------------ | \--* CNS_INT long 0 [000469] --C-G------- if \--* COLON long [000458] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000445] ------------ arg0 | +--* LCL_VAR long V26 tmp12 [000457] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000461] n----------- then \--* IND long [000462] ------------ \--* ADD long [000463] #----------- +--* IND long [000464] #----------- | \--* IND long [000465] ------------ | \--* ADD long [000466] ------------ | +--* LCL_VAR long V26 tmp12 [000467] ------------ | \--* CNS_INT long 56 [000468] ------------ \--* CNS_INT long 56 LocalAddressVisitor visiting statement: STMT00076 (IL ???... ???) [000440] --C-G------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000474] ------------ arg0 +--* RUNTIMELOOKUP long 0xd1ffab1e method [000473] ------------ | \--* LCL_VAR long V28 tmp14 [000455] ------------ arg1 \--* LCL_VAR ref V27 tmp13 LocalAddressVisitor visiting statement: STMT00065 (IL 0x157...0x164) [000406] -A-XG------- * ASG int [000405] D------N---- +--* LCL_VAR int V09 loc5 [000404] ---XG------- \--* FIELD int next [000403] ---XG------- \--* ADDR byref [000402] ---XG--N---- \--* INDEX struct [000400] ------------ +--* LCL_VAR ref V04 loc0 [000401] ------------ \--* LCL_VAR int V09 loc5 LocalAddressVisitor visiting statement: STMT00066 (IL 0x166...0x169) [000411] -A---------- * ASG int [000410] D------N---- +--* LCL_VAR int V07 loc3 [000409] ------------ \--* ADD int [000407] ------------ +--* LCL_VAR int V07 loc3 [000408] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00067 (IL 0x16A...0x16E) [000416] ---X-------- * JTRUE void [000415] N--X-----U-- \--* LE int [000412] ------------ +--* LCL_VAR int V07 loc3 [000414] ---X-------- \--* ARR_LENGTH int [000413] ------------ \--* LCL_VAR ref V04 loc0 LocalAddressVisitor visiting statement: STMT00014 (IL 0x177...0x17C) [000066] ---X-------- * JTRUE void [000065] N--X-----U-- \--* GE int [000062] ------------ +--* LCL_VAR int V09 loc5 [000064] ---X-------- \--* ARR_LENGTH int [000063] ------------ \--* LCL_VAR ref V04 loc0 LocalAddressVisitor visiting statement: STMT00039 (IL 0x17E...0x18C) [000215] ---XG------- * JTRUE void [000214] N--XG----U-- \--* NE int [000212] ---XG------- +--* FIELD int hashCode [000211] ---XG------- | \--* ADDR byref [000210] ---XG--N---- | \--* INDEX struct [000208] ------------ | +--* LCL_VAR ref V04 loc0 [000209] ------------ | \--* LCL_VAR int V09 loc5 [000213] ------------ \--* LCL_VAR int V06 loc2 LocalAddressVisitor visiting statement: STMT00045 (IL 0x18E...0x1A2) [000246] -A-XG------- * ASG ref [000245] D------N---- +--* LCL_VAR ref V17 tmp3 [000239] ---XG------- \--* FIELD ref key [000238] ---XG------- \--* ADDR byref [000237] ---XG--N---- \--* INDEX struct [000235] ------------ +--* LCL_VAR ref V04 loc0 [000236] ------------ \--* LCL_VAR int V09 loc5 LocalAddressVisitor visiting statement: STMT00044 (IL 0x18E... ???) [000244] -A-X-------- * ASG long [000243] D------N---- +--* LCL_VAR long V16 tmp2 [000242] #--X-------- \--* IND long [000241] !----------- \--* LCL_VAR ref V00 this LocalAddressVisitor visiting statement: STMT00046 (IL ???... ???) [000257] -A---------- * ASG ref [000256] D------N---- +--* LCL_VAR ref V18 tmp4 [000240] ------------ \--* LCL_VAR ref V01 arg1 LocalAddressVisitor visiting statement: STMT00047 (IL ???... ???) [000275] -AC-G------- * ASG long [000274] D------N---- +--* LCL_VAR long V19 tmp5 [000273] --C-G------- \--* QMARK long [000263] Q----------- if +--* NE int [000259] n----------- | +--* IND long [000255] ------------ | | \--* ADD long [000253] #----------- | | +--* IND long [000252] #----------- | | | \--* IND long [000251] ------------ | | | \--* ADD long [000249] ------------ | | | +--* LCL_VAR long V16 tmp2 [000250] ------------ | | | \--* CNS_INT long 56 [000254] ------------ | | \--* CNS_INT long 48 [000262] ------------ | \--* CNS_INT long 0 [000272] --C-G------- if \--* COLON long [000261] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000248] ------------ arg0 | +--* LCL_VAR long V16 tmp2 [000260] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000264] n----------- then \--* IND long [000265] ------------ \--* ADD long [000266] #----------- +--* IND long [000267] #----------- | \--* IND long [000268] ------------ | \--* ADD long [000269] ------------ | +--* LCL_VAR long V16 tmp2 [000270] ------------ | \--* CNS_INT long 56 [000271] ------------ \--* CNS_INT long 48 LocalAddressVisitor visiting statement: STMT00048 (IL ???... ???) [000278] -A---------- * ASG long [000277] D------N---- +--* LCL_VAR long V20 tmp6 [000276] ------------ \--* LCL_VAR long V19 tmp5 LocalAddressVisitor visiting statement: STMT00049 (IL ???... ???) [000283] --CXG------- * JTRUE void [000282] --CXG------- \--* EQ int [000280] --CXG------- +--* CALL ind stub int [000234] ------------ this in rcx | +--* LCL_VAR ref V05 loc1 [000247] ------------ arg1 | +--* LCL_VAR ref V17 tmp3 [000258] ------------ arg2 | +--* LCL_VAR ref V18 tmp4 [000279] ------------ calli tgt | \--* LCL_VAR long V20 tmp6 [000281] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00050 (IL 0x1A4...0x1A6) [000287] ------------ * JTRUE void [000286] N--------U-- \--* NE int [000284] ------------ +--* LCL_VAR ubyte V03 arg3 [000285] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00057 (IL 0x1A8...0x1B1) [000336] -A-XG------- * ASG ref [000335] ---XG--N---- +--* FIELD ref value [000333] ---XG------- | \--* ADDR byref [000332] ---XG--N---- | \--* INDEX struct [000330] ------------ | +--* LCL_VAR ref V04 loc0 [000331] ------------ | \--* LCL_VAR int V09 loc5 [000334] ------------ \--* LCL_VAR ref V02 arg2 LocalAddressVisitor visiting statement: STMT00051 (IL 0x1B8...0x1BA) [000291] ------------ * JTRUE void [000290] N--------U-- \--* NE int [000288] ------------ +--* LCL_VAR ubyte V03 arg3 [000289] ------------ \--* CNS_INT int 2 LocalAddressVisitor visiting statement: STMT00053 (IL 0x1BC...0x1BD) [000299] -A-X-------- * ASG long [000298] D------N---- +--* LCL_VAR long V21 tmp7 [000297] #--X-------- \--* IND long [000296] !----------- \--* LCL_VAR ref V00 this LocalAddressVisitor visiting statement: STMT00054 (IL ???... ???) [000309] -A---------- * ASG ref [000308] D------N---- +--* LCL_VAR ref V22 tmp8 [000294] ------------ \--* LCL_VAR ref V01 arg1 LocalAddressVisitor visiting statement: STMT00055 (IL ???... ???) [000327] -AC-G------- * ASG long [000326] D------N---- +--* LCL_VAR long V23 tmp9 [000325] --C-G------- \--* QMARK long [000315] Q----------- if +--* NE int [000311] n----------- | +--* IND long [000307] ------------ | | \--* ADD long [000305] #----------- | | +--* IND long [000304] #----------- | | | \--* IND long [000303] ------------ | | | \--* ADD long [000301] ------------ | | | +--* LCL_VAR long V21 tmp7 [000302] ------------ | | | \--* CNS_INT long 56 [000306] ------------ | | \--* CNS_INT long 56 [000314] ------------ | \--* CNS_INT long 0 [000324] --C-G------- if \--* COLON long [000313] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000300] ------------ arg0 | +--* LCL_VAR long V21 tmp7 [000312] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000316] n----------- then \--* IND long [000317] ------------ \--* ADD long [000318] #----------- +--* IND long [000319] #----------- | \--* IND long [000320] ------------ | \--* ADD long [000321] ------------ | +--* LCL_VAR long V21 tmp7 [000322] ------------ | \--* CNS_INT long 56 [000323] ------------ \--* CNS_INT long 56 LocalAddressVisitor visiting statement: STMT00056 (IL ???... ???) [000295] --C-G------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000329] ------------ arg0 +--* RUNTIMELOOKUP long 0xd1ffab1e method [000328] ------------ | \--* LCL_VAR long V23 tmp9 [000310] ------------ arg1 \--* LCL_VAR ref V22 tmp8 LocalAddressVisitor visiting statement: STMT00148 (IL ???... ???) [000811] ------------ * RETURN int [000437] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00040 (IL 0x1C4...0x1D1) [000222] -A-XG------- * ASG int [000221] D------N---- +--* LCL_VAR int V09 loc5 [000220] ---XG------- \--* FIELD int next [000219] ---XG------- \--* ADDR byref [000218] ---XG--N---- \--* INDEX struct [000216] ------------ +--* LCL_VAR ref V04 loc0 [000217] ------------ \--* LCL_VAR int V09 loc5 LocalAddressVisitor visiting statement: STMT00041 (IL 0x1D3...0x1D6) [000227] -A---------- * ASG int [000226] D------N---- +--* LCL_VAR int V07 loc3 [000225] ------------ \--* ADD int [000223] ------------ +--* LCL_VAR int V07 loc3 [000224] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00042 (IL 0x1D7...0x1DB) [000232] ---X-------- * JTRUE void [000231] N--X-----U-- \--* LE int [000228] ------------ +--* LCL_VAR int V07 loc3 [000230] ---X-------- \--* ARR_LENGTH int [000229] ------------ \--* LCL_VAR ref V04 loc0 LocalAddressVisitor visiting statement: STMT00043 (IL 0x1DD...0x1E2) [000233] --C-G------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported LocalAddressVisitor visiting statement: STMT00015 (IL 0x1E4...0x1EB) [000071] ---XG------- * JTRUE void [000070] ---XG------- \--* LE int [000068] ---XG------- +--* FIELD int _freeCount [000067] ------------ | \--* LCL_VAR ref V00 this [000069] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00035 (IL 0x1ED...0x1F3) [000174] -A-XG------- * ASG int [000173] D------N---- +--* LCL_VAR int V10 loc6 [000172] ---XG------- \--* FIELD int _freeList [000171] ------------ \--* LCL_VAR ref V00 this LocalAddressVisitor visiting statement: STMT00120 (IL 0x1F5... ???) [000688] -A-XG------- * ASG bool [000687] D------N---- +--* LCL_VAR bool V49 tmp35 [000680] ---XG------- \--* CAST int <- bool <- int [000186] ---XG------- \--* EQ int [000184] ---XG------- +--* LT int [000182] ---XG------- | +--* SUB int [000175] ------------ | | +--* CNS_INT int -3 [000181] ---XG------- | | \--* FIELD int next [000180] ---XG------- | | \--* ADDR byref [000179] ---XG--N---- | | \--* INDEX struct [000176] ------------ | | +--* LCL_VAR ref V04 loc0 [000178] ---XG------- | | \--* FIELD int _freeList [000177] ------------ | | \--* LCL_VAR ref V00 this [000183] ------------ | \--* CNS_INT int -1 [000185] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00123 (IL 0x1F5... ???) [000698] -A--G------- * ASG ref [000697] D------N---- +--* LCL_VAR ref V50 tmp36 [000684] #---G------- \--* IND ref [000683] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] LocalAddressVisitor visiting statement: STMT00121 (IL 0x1F5... ???) [000693] ------------ * JTRUE void [000692] ------------ \--* NE int [000690] ------------ +--* LCL_VAR int V49 tmp35 [000691] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00122 (IL 0x1F5... ???) [000696] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000694] ------------ arg0 +--* CNS_STR ref [000695] ------------ arg1 \--* LCL_VAR ref V50 tmp36 LocalAddressVisitor visiting statement: STMT00037 (IL 0x219... ???) [000200] -A-XG------- * ASG int [000199] ---XG--N---- +--* FIELD int _freeList [000190] ------------ | \--* LCL_VAR ref V00 this [000198] ---XG------- \--* SUB int [000191] ------------ +--* CNS_INT int -3 [000197] ---XG------- \--* FIELD int next [000196] ---XG------- \--* ADDR byref [000195] ---XG--N---- \--* INDEX struct [000192] ------------ +--* LCL_VAR ref V04 loc0 [000194] ---XG------- \--* FIELD int _freeList [000193] ------------ \--* LCL_VAR ref V00 this LocalAddressVisitor visiting statement: STMT00038 (IL 0x233...0x23C) [000207] -A-XG------- * ASG int [000206] ---XG--N---- +--* FIELD int _freeCount [000201] ------------ | \--* LCL_VAR ref V00 this [000205] ---XG------- \--* SUB int [000203] ---XG------- +--* FIELD int _freeCount [000202] ------------ | \--* LCL_VAR ref V00 this [000204] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00016 (IL 0x243...0x249) [000075] -A-XG------- * ASG int [000074] D------N---- +--* LCL_VAR int V13 loc9 [000073] ---XG------- \--* FIELD int _count [000072] ------------ \--* LCL_VAR ref V00 this LocalAddressVisitor visiting statement: STMT00017 (IL 0x24B...0x250) [000080] ---X-------- * JTRUE void [000079] N--X-----U-- \--* NE int [000076] ------------ +--* LCL_VAR int V13 loc9 [000078] ---X-------- \--* ARR_LENGTH int [000077] ------------ \--* LCL_VAR ref V04 loc0 LocalAddressVisitor visiting statement: STMT00125 (IL 0x252... ???) [000705] --C-G------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [000163] ------------ this in rcx +--* LCL_VAR ref V00 this [000702] --CXG------- arg1 +--* CALL int System.Collections.HashHelpers.ExpandPrime [000701] ---XG------- arg0 | \--* FIELD int _count [000700] ------------ | \--* LCL_VAR ref V00 this [000706] ------------ arg2 \--* PUTARG_TYPE bool [000704] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00126 (IL 0x258... ???) [000711] -A-XG------- * ASG ref [000710] D------N---- +--* LCL_VAR ref V52 tmp38 [000709] ---XG------- \--* FIELD ref _buckets [000165] ------------ \--* LCL_VAR ref V00 this LocalAddressVisitor visiting statement: STMT00133 (IL 0x258... ???) [000760] -A-X-------- * ASG int [000759] D------N---- +--* LCL_VAR int V53 tmp39 [000714] ---X-------- \--* ARR_LENGTH int [000713] ------------ \--* LCL_VAR ref V52 tmp38 LocalAddressVisitor visiting statement: STMT00134 (IL 0x258... ???) [000762] -A-XG------- * ASG long [000761] D------N---- +--* LCL_VAR long V54 tmp40 [000716] ---XG------- \--* FIELD long _fastModMultiplier [000715] ------------ \--* LCL_VAR ref V00 this LocalAddressVisitor visiting statement: STMT00136 (IL 0x258... ???) [000773] -A---------- * ASG bool [000772] D------N---- +--* LCL_VAR bool V56 tmp42 [000764] ------------ \--* CAST int <- bool <- int [000732] ------------ \--* EQ int [000730] N--------U-- +--* GT int [000728] ------------ | +--* LCL_VAR int V53 tmp39 [000729] ------------ | \--* CNS_INT int 0x7FFFFFFF [000731] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00139 (IL 0x258... ???) [000783] -A--G------- * ASG ref [000782] D------N---- +--* LCL_VAR ref V57 tmp43 [000767] #---G------- \--* IND ref [000766] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] LocalAddressVisitor visiting statement: STMT00140 (IL 0x258... ???) [000785] -A--G------- * ASG ref [000784] D------N---- +--* LCL_VAR ref V58 tmp44 [000769] #---G------- \--* IND ref [000768] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] LocalAddressVisitor visiting statement: STMT00137 (IL 0x258... ???) [000778] ------------ * JTRUE void [000777] ------------ \--* NE int [000775] ------------ +--* LCL_VAR int V56 tmp42 [000776] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00138 (IL 0x258... ???) [000781] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000779] ------------ arg0 +--* LCL_VAR ref V57 tmp43 [000780] ------------ arg1 \--* LCL_VAR ref V58 tmp44 LocalAddressVisitor visiting statement: STMT00131 (IL 0x258... ???) [000750] -A---------- * ASG int [000749] D------N---- +--* LCL_VAR int V55 tmp41 [000748] ------------ \--* CAST int <- uint <- long [000747] ------------ \--* RSZ long [000745] ------------ +--* MUL long [000742] ------------ | +--* ADD long [000739] ------------ | | +--* RSZ long [000737] ------------ | | | +--* MUL long [000735] ------------ | | | | +--* LCL_VAR long V54 tmp40 [000736] ---------U-- | | | | \--* CAST long <- ulong <- uint [000166] ------------ | | | | \--* LCL_VAR int V06 loc2 [000738] ------------ | | | \--* CNS_INT int 32 [000741] ------------ | | \--* CNS_INT long 1 [000744] ---------U-- | \--* CAST long <- ulong <- uint [000743] ------------ | \--* LCL_VAR int V53 tmp39 [000746] ------------ \--* CNS_INT int 32 LocalAddressVisitor visiting statement: STMT00142 (IL 0x258... ???) [000796] -A-X-------- * ASG bool [000795] D------N---- +--* LCL_VAR bool V59 tmp45 [000787] ---X-------- \--* CAST int <- bool <- int [000755] ---X-------- \--* EQ int [000751] ------------ +--* LCL_VAR int V55 tmp41 [000754] ---X-------- \--* UMOD int [000752] ------------ +--* LCL_VAR int V06 loc2 [000753] ------------ \--* LCL_VAR int V53 tmp39 LocalAddressVisitor visiting statement: STMT00145 (IL 0x258... ???) [000806] -A--G------- * ASG ref [000805] D------N---- +--* LCL_VAR ref V60 tmp46 [000790] #---G------- \--* IND ref [000789] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] LocalAddressVisitor visiting statement: STMT00146 (IL 0x258... ???) [000808] -A--G------- * ASG ref [000807] D------N---- +--* LCL_VAR ref V61 tmp47 [000792] #---G------- \--* IND ref [000791] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] LocalAddressVisitor visiting statement: STMT00143 (IL 0x258... ???) [000801] ------------ * JTRUE void [000800] ------------ \--* NE int [000798] ------------ +--* LCL_VAR int V59 tmp45 [000799] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00144 (IL 0x258... ???) [000804] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000802] ------------ arg0 +--* LCL_VAR ref V60 tmp46 [000803] ------------ arg1 \--* LCL_VAR ref V61 tmp47 LocalAddressVisitor visiting statement: STMT00128 (IL 0x258... ???) [000722] -ACXG------- * ASG byref [000721] D------N---- +--* LCL_VAR byref V51 tmp37 [000720] --CXG------- \--* ADDR byref [000719] --CXG--N---- \--* INDEX int [000712] ------------ +--* LCL_VAR ref V52 tmp38 [000758] ------------ \--* LCL_VAR int V55 tmp41 LocalAddressVisitor visiting statement: STMT00129 (IL 0x258... ???) [000726] -A---------- * ASG ref [000725] D------N---- +--* LCL_VAR ref V52 tmp38 [000724] ------------ \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00034 (IL ???... ???) [000170] -AC--------- * ASG byref [000169] D------N---- +--* LCL_VAR byref V08 loc4 [000723] ------------ \--* LCL_VAR byref V51 tmp37 LocalAddressVisitor visiting statement: STMT00018 (IL 0x261...0x263) [000083] -A---------- * ASG int [000082] D------N---- +--* LCL_VAR int V10 loc6 [000081] ------------ \--* LCL_VAR int V13 loc9 LocalAddressVisitor visiting statement: STMT00019 (IL 0x265...0x26A) [000089] -A-XG------- * ASG int [000088] ---XG--N---- +--* FIELD int _count [000084] ------------ | \--* LCL_VAR ref V00 this [000087] ------------ \--* ADD int [000085] ------------ +--* LCL_VAR int V13 loc9 [000086] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00020 (IL 0x26F...0x275) [000093] -A-XG------- * ASG ref [000092] D------N---- +--* LCL_VAR ref V04 loc0 [000091] ---XG------- \--* FIELD ref _entries [000090] ------------ \--* LCL_VAR ref V00 this LocalAddressVisitor visiting statement: STMT00021 (IL 0x276...0x27E) [000099] -A-XG------- * ASG byref [000098] D------N---- +--* LCL_VAR byref V11 loc7 [000097] ---XG------- \--* ADDR byref [000096] ---XG--N---- \--* INDEX struct [000094] ------------ +--* LCL_VAR ref V04 loc0 [000095] ------------ \--* LCL_VAR int V10 loc6 LocalAddressVisitor visiting statement: STMT00022 (IL 0x280...0x283) [000103] -A-XG------- * ASG int [000102] ---XG--N---- +--* FIELD int hashCode [000100] ------------ | \--* LCL_VAR byref V11 loc7 [000101] ------------ \--* LCL_VAR int V06 loc2 LocalAddressVisitor visiting statement: STMT00023 (IL 0x288...0x28F) [000110] -A-XG------- * ASG int [000109] ---XG--N---- +--* FIELD int next [000104] ------------ | \--* LCL_VAR byref V11 loc7 [000108] ---XG------- \--* SUB int [000106] *--XG------- +--* IND int [000105] ------------ | \--* LCL_VAR byref V08 loc4 [000107] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00024 (IL 0x294...0x297) [000114] -A-XG------- * ASG ref [000113] ---XG--N---- +--* FIELD ref key [000111] ------------ | \--* LCL_VAR byref V11 loc7 [000112] ------------ \--* LCL_VAR ref V01 arg1 LocalAddressVisitor visiting statement: STMT00025 (IL 0x29C...0x29F) [000118] -A-XG------- * ASG ref [000117] ---XG--N---- +--* FIELD ref value [000115] ------------ | \--* LCL_VAR byref V11 loc7 [000116] ------------ \--* LCL_VAR ref V02 arg2 LocalAddressVisitor visiting statement: STMT00026 (IL 0x2A4...0x2AA) [000124] -A-XG------- * ASG int [000123] *------N---- +--* IND int [000119] ------------ | \--* LCL_VAR byref V08 loc4 [000122] ------------ \--* ADD int [000120] ------------ +--* LCL_VAR int V10 loc6 [000121] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00027 (IL 0x2AB...0x2B4) [000131] -A-XG------- * ASG int [000130] ---XG--N---- +--* FIELD int _version [000125] ------------ | \--* LCL_VAR ref V00 this [000129] ---XG------- \--* ADD int [000127] ---XG------- +--* FIELD int _version [000126] ------------ | \--* LCL_VAR ref V00 this [000128] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00028 (IL 0x2CA...0x2CD) [000148] ------------ * JTRUE void [000147] N--------U-- \--* LE int [000145] ------------ +--* LCL_VAR int V07 loc3 [000146] ------------ \--* CNS_INT int 100 LocalAddressVisitor visiting statement: STMT00030 (IL 0x2CF...0x2D5) [000156] --C-G------- * JTRUE void [000155] --C-G------- \--* EQ int [000153] --C-G------- +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS [000152] H------N---- arg0 | +--* CNS_INT(h) long 0xd1ffab1e class [000151] ------------ arg1 | \--* LCL_VAR ref V05 loc1 [000154] ------------ \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00031 (IL 0x2D7...0x2DC) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [000157] ------------ this in rcx +--* LCL_VAR ref V00 this [000159] ---X-------- arg1 +--* ARR_LENGTH int [000158] ------------ | \--* LCL_VAR ref V04 loc0 [000162] ------------ arg2 \--* PUTARG_TYPE bool [000160] ------------ \--* CNS_INT int 1 LocalAddressVisitor visiting statement: STMT00147 (IL ???... ???) [000810] ------------ * RETURN int [000482] ------------ \--* CNS_INT int 1 *************** Finishing PHASE Morph - Structs/AddrExp *************** Starting PHASE Morph - ByRefs *************** In fgRetypeImplicitByRefArgs() *************** Finishing PHASE Morph - ByRefs *************** Starting PHASE Morph - Global *************** In fgMorphBlocks() Morphing BB01 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB01, STMT00000 (before) [000003] ------------ * JTRUE void [000002] ------------ \--* NE int [000000] ------------ +--* LCL_VAR ref V01 arg1 [000001] ------------ \--* CNS_INT ref null Morphing BB02 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB02, STMT00086 (before) [000533] --C-G------- * CALL void System.ThrowHelper.ThrowArgumentNullException [000532] ------------ arg0 \--* CNS_INT int 4 Initializing arg info for 533.CALL: ArgTable for 533.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 532.CNS_INT int (By ref), 1 reg: rcx, byteAlignment=8] Morphing args for 533.CALL: argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000532] -----+------ * CNS_INT int 4 Replaced with placeholder node: [000812] ----------L- * ARGPLACE int Shuffled argument table: rcx ArgTable for 533.CALL after fgMorphArgs: fgArgTabEntry[arg 0 532.CNS_INT int (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgMorphTree BB02, STMT00086 (after) [000533] --CXG+------ * CALL void System.ThrowHelper.ThrowArgumentNullException [000532] -----+------ arg0 in rcx \--* CNS_INT int 4 Converting BB02 to BBJ_THROW Morphing BB03 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB03, STMT00001 (before) [000008] ---XG------- * JTRUE void [000007] ---XG------- \--* NE int [000005] ---XG------- +--* FIELD ref _buckets [000004] ------------ | \--* LCL_VAR ref V00 this [000006] ------------ \--* CNS_INT ref null Querying runtime about current class of field System.Collections.Generic.Dictionary`2[System.__Canon,System.__Canon]._buckets (declared as System.Int32[]) Field's current class not available Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000005] ---XG------- * IND ref [000814] -----+------ \--* ADD byref [000004] -----+------ +--* LCL_VAR ref V00 this [000813] -----+------ \--* CNS_INT long 8 field offset Fseq[_buckets] GenTreeNode creates assertion: [000005] ---XG------- * IND ref In BB03 New Local Constant Assertion: V00 != null index=#01, mask=0000000000000001 fgMorphTree BB03, STMT00001 (after) [000008] ---XG+------ * JTRUE void [000007] J--XG+-N---- \--* NE int [000005] ---XG+------ +--* IND ref [000814] -----+------ | \--* ADD byref [000004] -----+------ | +--* LCL_VAR ref V00 this [000813] -----+------ | \--* CNS_INT long 8 field offset Fseq[_buckets] [000006] -----+------ \--* CNS_INT ref null Morphing BB04 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB04, STMT00085 (before) [000528] --C-G------- * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize [000526] ------------ this in rcx +--* LCL_VAR ref V00 this [000527] ------------ arg1 \--* CNS_INT int 0 Initializing arg info for 528.CALL: ArgTable for 528.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 526.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 527.CNS_INT int (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 528.CALL: argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000526] -----+------ * LCL_VAR ref V00 this Replaced with placeholder node: [000815] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000527] -----+------ * CNS_INT int 0 Replaced with placeholder node: [000816] ----------L- * ARGPLACE int Shuffled argument table: rcx rdx ArgTable for 528.CALL after fgMorphArgs: fgArgTabEntry[arg 0 526.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 527.CNS_INT int (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB04, STMT00085 (after) [000528] --CXG+------ * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize [000526] -----+------ this in rcx +--* LCL_VAR ref V00 this [000527] -----+------ arg1 in rdx \--* CNS_INT int 0 Morphing BB05 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB05, STMT00088 (before) [000544] -A-XG------- * ASG bool [000543] D------N---- +--* LCL_VAR bool V33 tmp19 [000535] ---XG------- \--* CAST int <- bool <- int [000012] N--XG----U-- \--* GT int [000010] ---XG------- +--* FIELD ref _buckets [000009] ------------ | \--* LCL_VAR ref V00 this [000011] ------------ \--* CNS_INT ref null Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000010] ---XG------- * IND ref [000818] -----+------ \--* ADD byref [000009] -----+------ +--* LCL_VAR ref V00 this [000817] -----+------ \--* CNS_INT long 8 field offset Fseq[_buckets] GenTreeNode creates assertion: [000010] ---XG------- * IND ref In BB05 New Local Constant Assertion: V00 != null index=#01, mask=0000000000000001 GenTreeNode creates assertion: [000544] -A-XG------- * ASG bool In BB05 New Local Subrange Assertion: V33 in [0..1] index=#02, mask=0000000000000002 fgMorphTree BB05, STMT00088 (after) [000544] -A-XG+------ * ASG bool [000543] D----+-N---- +--* LCL_VAR int V33 tmp19 [000012] N--XG+------ \--* NE int [000010] ---XG+------ +--* IND ref [000818] -----+------ | \--* ADD byref [000009] -----+------ | +--* LCL_VAR ref V00 this [000817] -----+------ | \--* CNS_INT long 8 field offset Fseq[_buckets] [000011] -----+------ \--* CNS_INT ref null fgMorphTree BB05, STMT00091 (before) [000554] -A--G------- * ASG ref [000553] D------N---- +--* LCL_VAR ref V34 tmp20 [000538] #---G------- \--* IND ref [000537] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] fgMorphTree BB05, STMT00092 (before) [000556] -A--G------- * ASG ref [000555] D------N---- +--* LCL_VAR ref V35 tmp21 [000540] #---G------- \--* IND ref [000539] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] fgMorphTree BB05, STMT00089 (before) [000549] ------------ * JTRUE void [000548] ------------ \--* NE int [000546] ------------ +--* LCL_VAR int V33 tmp19 [000547] ------------ \--* CNS_INT int 0 Morphing BB07 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB07, STMT00090 (before) [000552] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000550] ------------ arg0 +--* LCL_VAR ref V34 tmp20 [000551] ------------ arg1 \--* LCL_VAR ref V35 tmp21 Initializing arg info for 552.CALL: ArgTable for 552.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 550.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 551.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 552.CALL: argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000550] -----+------ * LCL_VAR ref V34 tmp20 Replaced with placeholder node: [000819] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000551] -----+------ * LCL_VAR ref V35 tmp21 Replaced with placeholder node: [000820] ----------L- * ARGPLACE ref Shuffled argument table: rcx rdx ArgTable for 552.CALL after fgMorphArgs: fgArgTabEntry[arg 0 550.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 551.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB07, STMT00090 (after) [000552] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000550] -----+------ arg0 in rcx +--* LCL_VAR ref V34 tmp20 [000551] -----+------ arg1 in rdx \--* LCL_VAR ref V35 tmp21 Morphing BB08 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB08, STMT00003 (before) [000018] -A-XG------- * ASG ref [000017] D------N---- +--* LCL_VAR ref V04 loc0 [000016] ---XG------- \--* FIELD ref _entries [000015] ------------ \--* LCL_VAR ref V00 this Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000016] ---XG------- * IND ref [000822] -----+------ \--* ADD byref [000015] -----+------ +--* LCL_VAR ref V00 this [000821] -----+------ \--* CNS_INT long 16 field offset Fseq[_entries] GenTreeNode creates assertion: [000016] ---XG------- * IND ref In BB08 New Local Constant Assertion: V00 != null index=#01, mask=0000000000000001 fgMorphTree BB08, STMT00003 (after) [000018] -A-XG+------ * ASG ref [000017] D----+-N---- +--* LCL_VAR ref V04 loc0 [000016] ---XG+------ \--* IND ref [000822] -----+------ \--* ADD byref [000015] -----+------ +--* LCL_VAR ref V00 this [000821] -----+------ \--* CNS_INT long 16 field offset Fseq[_entries] fgMorphTree BB08, STMT00094 (before) [000566] -A---------- * ASG bool [000565] D------N---- +--* LCL_VAR bool V36 tmp22 [000558] ------------ \--* CAST int <- bool <- int [000021] N--------U-- \--* GT int [000019] ------------ +--* LCL_VAR ref V04 loc0 [000020] ------------ \--* CNS_INT ref null GenTreeNode creates assertion: [000566] -A---------- * ASG bool In BB08 New Local Subrange Assertion: V36 in [0..1] index=#02, mask=0000000000000002 fgMorphTree BB08, STMT00094 (after) [000566] -A---+------ * ASG bool [000565] D----+-N---- +--* LCL_VAR int V36 tmp22 [000021] N----+------ \--* NE int [000019] -----+------ +--* LCL_VAR ref V04 loc0 [000020] -----+------ \--* CNS_INT ref null fgMorphTree BB08, STMT00097 (before) [000576] -A--G------- * ASG ref [000575] D------N---- +--* LCL_VAR ref V37 tmp23 [000562] #---G------- \--* IND ref [000561] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] fgMorphTree BB08, STMT00095 (before) [000571] ------------ * JTRUE void [000570] ------------ \--* NE int [000568] ------------ +--* LCL_VAR int V36 tmp22 [000569] ------------ \--* CNS_INT int 0 Morphing BB11 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB11, STMT00096 (before) [000574] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000572] ------------ arg0 +--* CNS_STR ref [000573] ------------ arg1 \--* LCL_VAR ref V37 tmp23 Initializing arg info for 574.CALL: ArgTable for 574.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 572.CNS_STR ref (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 573.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 574.CALL: argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000824] #---G+------ * IND ref [000823] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" Replaced with placeholder node: [000825] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000573] -----+------ * LCL_VAR ref V37 tmp23 Replaced with placeholder node: [000826] ----------L- * ARGPLACE ref Shuffled argument table: rcx rdx ArgTable for 574.CALL after fgMorphArgs: fgArgTabEntry[arg 0 824.IND ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 573.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB11, STMT00096 (after) [000574] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000824] #---G+------ arg0 in rcx +--* IND ref [000823] H----+------ | \--* CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" [000573] -----+------ arg1 in rdx \--* LCL_VAR ref V37 tmp23 Morphing BB12 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB12, STMT00005 (before) [000028] -A-XG------- * ASG ref [000027] D------N---- +--* LCL_VAR ref V05 loc1 [000026] ---XG------- \--* FIELD ref _comparer [000025] ------------ \--* LCL_VAR ref V00 this Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000026] ---XG------- * IND ref [000828] -----+------ \--* ADD byref [000025] -----+------ +--* LCL_VAR ref V00 this [000827] -----+------ \--* CNS_INT long 24 field offset Fseq[_comparer] GenTreeNode creates assertion: [000026] ---XG------- * IND ref In BB12 New Local Constant Assertion: V00 != null index=#01, mask=0000000000000001 fgMorphTree BB12, STMT00005 (after) [000028] -A-XG+------ * ASG ref [000027] D----+-N---- +--* LCL_VAR ref V05 loc1 [000026] ---XG+------ \--* IND ref [000828] -----+------ \--* ADD byref [000025] -----+------ +--* LCL_VAR ref V00 this [000827] -----+------ \--* CNS_INT long 24 field offset Fseq[_comparer] fgMorphTree BB12, STMT00006 (before) [000032] ------------ * JTRUE void [000031] ------------ \--* EQ int [000029] ------------ +--* LCL_VAR ref V05 loc1 [000030] ------------ \--* CNS_INT ref null Morphing BB14 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB14, STMT00079 (before) [000489] -A-X-------- * ASG long [000488] D------N---- +--* LCL_VAR long V29 tmp15 [000487] #--X-------- \--* IND long [000486] !----------- \--* LCL_VAR ref V00 this GenTreeNode creates assertion: [000487] #--X-------- * IND long In BB14 New Local Constant Assertion: V00 != null index=#01, mask=0000000000000001 fgMorphTree BB14, STMT00080 (before) [000499] -A---------- * ASG ref [000498] D------N---- +--* LCL_VAR ref V30 tmp16 [000485] ------------ \--* LCL_VAR ref V01 arg1 GenTreeNode creates assertion: [000499] -A---------- * ASG ref In BB14 New Local Copy Assertion: V30 == V01 index=#02, mask=0000000000000002 fgMorphTree BB14, STMT00081 (before) [000517] -AC-G------- * ASG long [000516] D------N---- +--* LCL_VAR long V31 tmp17 [000515] --C-G------- \--* QMARK long [000505] Q----------- if +--* NE int [000501] n----------- | +--* IND long [000497] ------------ | | \--* ADD long [000495] #----------- | | +--* IND long [000494] #----------- | | | \--* IND long [000493] ------------ | | | \--* ADD long [000491] ------------ | | | +--* LCL_VAR long V29 tmp15 [000492] ------------ | | | \--* CNS_INT long 56 [000496] ------------ | | \--* CNS_INT long 64 [000504] ------------ | \--* CNS_INT long 0 [000514] --C-G------- if \--* COLON long [000503] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000490] ------------ arg0 | +--* LCL_VAR long V29 tmp15 [000502] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000506] n----------- then \--* IND long [000507] ------------ \--* ADD long [000508] #----------- +--* IND long [000509] #----------- | \--* IND long [000510] ------------ | \--* ADD long [000511] ------------ | +--* LCL_VAR long V29 tmp15 [000512] ------------ | \--* CNS_INT long 56 [000513] ------------ \--* CNS_INT long 64 Initializing arg info for 503.CALL: ArgTable for 503.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 490.LCL_VAR long (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 502.CNS_INT long (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 503.CALL: argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000490] -----+------ * LCL_VAR long V29 tmp15 Replaced with placeholder node: [000829] ----------L- * ARGPLACE long Deferred argument ('rdx'): [000502] H----+------ * CNS_INT(h) long 0xd1ffab1e global ptr Replaced with placeholder node: [000830] ----------L- * ARGPLACE long Shuffled argument table: rcx rdx ArgTable for 503.CALL after fgMorphArgs: fgArgTabEntry[arg 0 490.LCL_VAR long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 502.CNS_INT long (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB14, STMT00081 (after) [000517] -AC-G+------ * ASG long [000516] D----+-N---- +--* LCL_VAR long V31 tmp17 [000515] --C-G+------ \--* QMARK long [000505] J----+-N---- if +--* NE int [000501] n----+------ | +--* IND long [000497] -----+------ | | \--* ADD long [000495] #----+------ | | +--* IND long [000494] #----+------ | | | \--* IND long [000493] -----+------ | | | \--* ADD long [000491] -----+------ | | | +--* LCL_VAR long V29 tmp15 [000492] -----+------ | | | \--* CNS_INT long 56 [000496] -----+------ | | \--* CNS_INT long 64 [000504] -----+------ | \--* CNS_INT long 0 [000514] --C-G+?----- if \--* COLON long [000503] --C-G+?----- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000490] -----+?----- arg0 in rcx | +--* LCL_VAR long V29 tmp15 [000502] H----+?----- arg1 in rdx | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000506] n----+?----- then \--* IND long [000507] -----+?----- \--* ADD long [000508] #----+?----- +--* IND long [000509] #----+?----- | \--* IND long [000510] -----+?----- | \--* ADD long [000511] -----+?----- | +--* LCL_VAR long V29 tmp15 [000512] -----+?----- | \--* CNS_INT long 56 [000513] -----+?----- \--* CNS_INT long 64 fgMorphTree BB14, STMT00082 (before) [000520] -A---------- * ASG long [000519] D------N---- +--* LCL_VAR long V32 tmp18 [000518] ------------ \--* LCL_VAR long V31 tmp17 GenTreeNode creates assertion: [000520] -A---------- * ASG long In BB14 New Local Copy Assertion: V32 == V31 index=#03, mask=0000000000000004 fgMorphTree BB14, STMT00083 (before) [000524] -ACXG------- * ASG int [000523] D------N---- +--* LCL_VAR int V15 tmp1 [000522] --CXG------- \--* CALL ind stub int [000484] ------------ this in rcx +--* LCL_VAR ref V05 loc1 [000500] ------------ arg1 +--* LCL_VAR ref V30 tmp16 [000521] ------------ calli tgt \--* LCL_VAR long V32 tmp18 Initializing arg info for 522.CALL: ArgTable for 522.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 484.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 831.LCL_VAR long (By ref), 1 reg: r11, byteAlignment=8, isNonStandard] fgArgTabEntry[arg 2 500.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 522.CALL: Assertion prop in BB14: Copy Assertion: V32 == V31 index=#03, mask=0000000000000004 [000831] ------------ * LCL_VAR long V31 tmp17 r11 REG r11 Assertion prop in BB14: Copy Assertion: V30 == V01 index=#02, mask=0000000000000002 [000500] ------------ * LCL_VAR ref V01 arg1 Assertion prop in BB14: Copy Assertion: V32 == V31 index=#03, mask=0000000000000004 [000521] ------------ * LCL_VAR long V31 tmp17 argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000484] -----+------ * LCL_VAR ref V05 loc1 Replaced with placeholder node: [000832] ----------L- * ARGPLACE ref Deferred argument ('r11'): [000831] -----+------ * LCL_VAR long V31 tmp17 r11 REG r11 Replaced with placeholder node: [000833] ----------L- * ARGPLACE long Deferred argument ('rdx'): [000500] -----+------ * LCL_VAR ref V01 arg1 Replaced with placeholder node: [000834] ----------L- * ARGPLACE ref Shuffled argument table: rcx r11 rdx ArgTable for 522.CALL after fgMorphArgs: fgArgTabEntry[arg 0 484.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 831.LCL_VAR long (By ref), 1 reg: r11, byteAlignment=8, lateArgInx=1, processed, isNonStandard] fgArgTabEntry[arg 2 500.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=2, processed] GenTreeNode creates assertion: [000522] --CXG------- * CALL ind stub int In BB14 New Local Constant Assertion: V05 != null index=#04, mask=0000000000000008 fgMorphTree BB14, STMT00083 (after) [000524] -ACXG+------ * ASG int [000523] D----+-N---- +--* LCL_VAR int V15 tmp1 [000522] --CXG+------ \--* CALL ind stub int [000521] -----+------ calli tgt \--* LCL_VAR long V31 tmp17 [000484] -----+------ this in rcx +--* LCL_VAR ref V05 loc1 [000831] -----+------ arg1 in r11 +--* LCL_VAR long V31 tmp17 r11 REG r11 [000500] -----+------ arg2 in rdx \--* LCL_VAR ref V01 arg1 Morphing BB15 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB15, STMT00007 (before) [000038] -ACXG------- * ASG int [000037] D------N---- +--* LCL_VAR int V15 tmp1 [000035] --CXG------- \--* CALLV vt-ind int System.Object.GetHashCode [000036] *--XG------- this in rcx \--* IND ref [000034] ------------ \--* ADDR long [000033] -------N---- \--* LCL_VAR ref V01 arg1 Initializing arg info for 35.CALL: ArgTable for 35.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 36.IND ref (By ref), 1 reg: rcx, byteAlignment=8] Morphing args for 35.CALL: argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000033] -----+------ * LCL_VAR ref V01 arg1 Replaced with placeholder node: [000835] ----------L- * ARGPLACE ref Shuffled argument table: rcx ArgTable for 35.CALL after fgMorphArgs: fgArgTabEntry[arg 0 33.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] Expanding virtual call target for 35.CALL: GenTreeNode creates assertion: [000837] #--X-------- * IND long In BB15 New Local Constant Assertion: V01 != null index=#01, mask=0000000000000001 fgMorphTree BB15, STMT00007 (after) [000038] -ACXG+------ * ASG int [000037] D----+-N---- +--* LCL_VAR int V15 tmp1 [000035] --CXG+------ \--* CALLV vt-ind int System.Object.GetHashCode [000843] n--X-+------ control expr \--* IND long [000842] ---X-+------ \--* ADD long [000840] #--X-+------ +--* IND long [000839] ---X-+------ | \--* ADD long [000837] #--X-+------ | +--* IND long [000836] -----+------ | | \--* LCL_VAR ref V01 arg1 [000838] -----+------ | \--* CNS_INT int 72 [000841] -----+------ \--* CNS_INT int 24 [000033] -----+------ this in rcx \--* LCL_VAR ref V01 arg1 Morphing BB16 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB16, STMT00008 (before) [000042] -A---------- * ASG int [000041] D------N---- +--* LCL_VAR int V06 loc2 [000040] ------------ \--* LCL_VAR int V15 tmp1 GenTreeNode creates assertion: [000042] -A---------- * ASG int In BB16 New Local Copy Assertion: V06 == V15 index=#01, mask=0000000000000001 fgMorphTree BB16, STMT00009 (before) [000045] -A---------- * ASG int [000044] D------N---- +--* LCL_VAR int V07 loc3 [000043] ------------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000045] -A---------- * ASG int In BB16 New Local Constant Assertion: V07 == 0 index=#02, mask=0000000000000002 fgMorphTree BB16, STMT00098 (before) [000580] -A-XG------- * ASG ref [000579] D------N---- +--* LCL_VAR ref V39 tmp25 [000578] ---XG------- \--* FIELD ref _buckets [000046] ------------ \--* LCL_VAR ref V00 this Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000578] ---XG------- * IND ref [000845] -----+------ \--* ADD byref [000046] -----+------ +--* LCL_VAR ref V00 this [000844] -----+------ \--* CNS_INT long 8 field offset Fseq[_buckets] GenTreeNode creates assertion: [000578] ---XG------- * IND ref In BB16 New Local Constant Assertion: V00 != null index=#03, mask=0000000000000004 fgMorphTree BB16, STMT00098 (after) [000580] -A-XG+------ * ASG ref [000579] D----+-N---- +--* LCL_VAR ref V39 tmp25 [000578] ---XG+------ \--* IND ref [000845] -----+------ \--* ADD byref [000046] -----+------ +--* LCL_VAR ref V00 this [000844] -----+------ \--* CNS_INT long 8 field offset Fseq[_buckets] fgMorphTree BB16, STMT00105 (before) [000629] -A-X-------- * ASG int [000628] D------N---- +--* LCL_VAR int V40 tmp26 [000583] ---X-------- \--* ARR_LENGTH int [000582] ------------ \--* LCL_VAR ref V39 tmp25 GenTreeNode creates assertion: [000583] ---X-------- * ARR_LENGTH int In BB16 New Local Constant Assertion: V39 != null index=#04, mask=0000000000000008 fgMorphTree BB16, STMT00106 (before) [000631] -A-XG------- * ASG long [000630] D------N---- +--* LCL_VAR long V41 tmp27 [000585] ---XG------- \--* FIELD long _fastModMultiplier [000584] ------------ \--* LCL_VAR ref V00 this Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000585] ---XG------- * IND long [000847] -----+------ \--* ADD byref [000584] -----+------ +--* LCL_VAR ref V00 this [000846] -----+------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] fgMorphTree BB16, STMT00106 (after) [000631] -A-XG+------ * ASG long [000630] D----+-N---- +--* LCL_VAR long V41 tmp27 [000585] ---XG+------ \--* IND long [000847] -----+------ \--* ADD byref [000584] -----+------ +--* LCL_VAR ref V00 this [000846] -----+------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] fgMorphTree BB16, STMT00108 (before) [000642] -A---------- * ASG bool [000641] D------N---- +--* LCL_VAR bool V43 tmp29 [000633] ------------ \--* CAST int <- bool <- int [000601] ------------ \--* EQ int [000599] N--------U-- +--* GT int [000597] ------------ | +--* LCL_VAR int V40 tmp26 [000598] ------------ | \--* CNS_INT int 0x7FFFFFFF [000600] ------------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000642] -A---------- * ASG bool In BB16 New Local Subrange Assertion: V43 in [0..1] index=#05, mask=0000000000000010 fgMorphTree BB16, STMT00108 (after) [000642] -A---+------ * ASG bool [000641] D----+-N---- +--* LCL_VAR int V43 tmp29 [000599] N----+---U-- \--* LE int [000597] -----+------ +--* LCL_VAR int V40 tmp26 [000598] -----+------ \--* CNS_INT int 0x7FFFFFFF fgMorphTree BB16, STMT00111 (before) [000652] -A--G------- * ASG ref [000651] D------N---- +--* LCL_VAR ref V44 tmp30 [000636] #---G------- \--* IND ref [000635] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] fgMorphTree BB16, STMT00112 (before) [000654] -A--G------- * ASG ref [000653] D------N---- +--* LCL_VAR ref V45 tmp31 [000638] #---G------- \--* IND ref [000637] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] fgMorphTree BB16, STMT00109 (before) [000647] ------------ * JTRUE void [000646] ------------ \--* NE int [000644] ------------ +--* LCL_VAR int V43 tmp29 [000645] ------------ \--* CNS_INT int 0 Morphing BB18 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB18, STMT00110 (before) [000650] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000648] ------------ arg0 +--* LCL_VAR ref V44 tmp30 [000649] ------------ arg1 \--* LCL_VAR ref V45 tmp31 Initializing arg info for 650.CALL: ArgTable for 650.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 648.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 649.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 650.CALL: argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000648] -----+------ * LCL_VAR ref V44 tmp30 Replaced with placeholder node: [000848] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000649] -----+------ * LCL_VAR ref V45 tmp31 Replaced with placeholder node: [000849] ----------L- * ARGPLACE ref Shuffled argument table: rcx rdx ArgTable for 650.CALL after fgMorphArgs: fgArgTabEntry[arg 0 648.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 649.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB18, STMT00110 (after) [000650] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000648] -----+------ arg0 in rcx +--* LCL_VAR ref V44 tmp30 [000649] -----+------ arg1 in rdx \--* LCL_VAR ref V45 tmp31 Morphing BB19 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB19, STMT00103 (before) [000619] -A---------- * ASG int [000618] D------N---- +--* LCL_VAR int V42 tmp28 [000617] ------------ \--* CAST int <- uint <- long [000616] ------------ \--* RSZ long [000614] ------------ +--* MUL long [000611] ------------ | +--* ADD long [000608] ------------ | | +--* RSZ long [000606] ------------ | | | +--* MUL long [000604] ------------ | | | | +--* LCL_VAR long V41 tmp27 [000605] ---------U-- | | | | \--* CAST long <- ulong <- uint [000047] ------------ | | | | \--* LCL_VAR int V06 loc2 [000607] ------------ | | | \--* CNS_INT int 32 [000610] ------------ | | \--* CNS_INT long 1 [000613] ---------U-- | \--* CAST long <- ulong <- uint [000612] ------------ | \--* LCL_VAR int V40 tmp26 [000615] ------------ \--* CNS_INT int 32 GenTreeNode creates assertion: [000619] -A---------- * ASG int In BB19 New Local Subrange Assertion: V42 in [0..-1] index=#01, mask=0000000000000001 fgMorphTree BB19, STMT00114 (before) [000665] -A-X-------- * ASG bool [000664] D------N---- +--* LCL_VAR bool V46 tmp32 [000656] ---X-------- \--* CAST int <- bool <- int [000624] ---X-------- \--* EQ int [000620] ------------ +--* LCL_VAR int V42 tmp28 [000623] ---X-------- \--* UMOD int [000621] ------------ +--* LCL_VAR int V06 loc2 [000622] ------------ \--* LCL_VAR int V40 tmp26 GenTreeNode creates assertion: [000665] -A-X-------- * ASG bool In BB19 New Local Subrange Assertion: V46 in [0..1] index=#02, mask=0000000000000002 fgMorphTree BB19, STMT00114 (after) [000665] -A-X-+------ * ASG bool [000664] D----+-N---- +--* LCL_VAR int V46 tmp32 [000624] ---X-+------ \--* EQ int [000620] -----+------ +--* LCL_VAR int V42 tmp28 [000623] ---X-+------ \--* UMOD int [000621] -----+------ +--* LCL_VAR int V06 loc2 [000622] -----+------ \--* LCL_VAR int V40 tmp26 fgMorphTree BB19, STMT00117 (before) [000675] -A--G------- * ASG ref [000674] D------N---- +--* LCL_VAR ref V47 tmp33 [000659] #---G------- \--* IND ref [000658] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] fgMorphTree BB19, STMT00118 (before) [000677] -A--G------- * ASG ref [000676] D------N---- +--* LCL_VAR ref V48 tmp34 [000661] #---G------- \--* IND ref [000660] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] fgMorphTree BB19, STMT00115 (before) [000670] ------------ * JTRUE void [000669] ------------ \--* NE int [000667] ------------ +--* LCL_VAR int V46 tmp32 [000668] ------------ \--* CNS_INT int 0 Morphing BB22 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB22, STMT00116 (before) [000673] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000671] ------------ arg0 +--* LCL_VAR ref V47 tmp33 [000672] ------------ arg1 \--* LCL_VAR ref V48 tmp34 Initializing arg info for 673.CALL: ArgTable for 673.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 671.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 672.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 673.CALL: argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000671] -----+------ * LCL_VAR ref V47 tmp33 Replaced with placeholder node: [000850] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000672] -----+------ * LCL_VAR ref V48 tmp34 Replaced with placeholder node: [000851] ----------L- * ARGPLACE ref Shuffled argument table: rcx rdx ArgTable for 673.CALL after fgMorphArgs: fgArgTabEntry[arg 0 671.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 672.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB22, STMT00116 (after) [000673] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000671] -----+------ arg0 in rcx +--* LCL_VAR ref V47 tmp33 [000672] -----+------ arg1 in rdx \--* LCL_VAR ref V48 tmp34 Morphing BB23 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB23, STMT00100 (before) [000591] -ACXG------- * ASG byref [000590] D------N---- +--* LCL_VAR byref V38 tmp24 [000589] --CXG------- \--* ADDR byref [000588] --CXG--N---- \--* INDEX int [000581] ------------ +--* LCL_VAR ref V39 tmp25 [000627] ------------ \--* LCL_VAR int V42 tmp28 GenTreeNode creates assertion: [000854] ---X-------- * ARR_LENGTH int In BB23 New Local Constant Assertion: V39 != null index=#01, mask=0000000000000001 fgMorphTree BB23, STMT00100 (after) [000591] -A-XG+------ * ASG byref [000590] D----+-N---- +--* LCL_VAR byref V38 tmp24 [000862] ---XG+------ \--* COMMA byref [000855] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000627] -----+------ | +--* LCL_VAR int V42 tmp28 [000854] ---X-+------ | \--* ARR_LENGTH int [000581] -----+------ | \--* LCL_VAR ref V39 tmp25 [000863] ----G------- \--* ADDR byref [000588] a---G+-N---- \--* IND int [000861] -----+------ \--* ADD byref [000852] -----+------ +--* LCL_VAR ref V39 tmp25 [000860] -----+------ \--* ADD long [000858] -----+------ +--* LSH long [000856] -----+------ | +--* CAST long <- int [000853] i----+------ | | \--* LCL_VAR int V42 tmp28 [000857] -----+-N---- | \--* CNS_INT long 2 [000859] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] fgMorphTree BB23, STMT00101 (before) [000595] -A---------- * ASG ref [000594] D------N---- +--* LCL_VAR ref V39 tmp25 [000593] ------------ \--* CNS_INT ref null The assignment [000595] using V39 removes: Constant Assertion: V39 != null GenTreeNode creates assertion: [000595] -A---------- * ASG ref In BB23 New Local Constant Assertion: V39 == null index=#01, mask=0000000000000001 fgMorphTree BB23, STMT00011 (before) [000051] -AC--------- * ASG byref [000050] D------N---- +--* LCL_VAR byref V08 loc4 [000592] ------------ \--* LCL_VAR byref V38 tmp24 GenTreeNode creates assertion: [000051] -A---------- * ASG byref In BB23 New Local Copy Assertion: V08 == V38 index=#02, mask=0000000000000002 fgMorphTree BB23, STMT00012 (before) [000057] -A-XG------- * ASG int [000056] D------N---- +--* LCL_VAR int V09 loc5 [000055] ---XG------- \--* SUB int [000053] *--XG------- +--* IND int [000052] ------------ | \--* LCL_VAR byref V08 loc4 [000054] ------------ \--* CNS_INT int 1 Assertion prop in BB23: Copy Assertion: V08 == V38 index=#02, mask=0000000000000002 [000052] ------------ * LCL_VAR byref V38 tmp24 fgMorphTree BB23, STMT00012 (after) [000057] -A-XG+------ * ASG int [000056] D----+-N---- +--* LCL_VAR int V09 loc5 [000055] ---XG+------ \--* ADD int [000053] *--XG+------ +--* IND int [000052] -----+------ | \--* LCL_VAR byref V38 tmp24 [000054] -----+------ \--* CNS_INT int -1 fgMorphTree BB23, STMT00013 (before) [000061] ------------ * JTRUE void [000060] ------------ \--* NE int [000058] ------------ +--* LCL_VAR ref V05 loc1 [000059] ------------ \--* CNS_INT ref null Morphing BB25 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB25, STMT00059 (before) [000356] -A-X-------- * ASG long [000355] D------N---- +--* LCL_VAR long V24 tmp10 [000354] #--X-------- \--* IND long [000353] !----------- \--* LCL_VAR ref V00 this GenTreeNode creates assertion: [000354] #--X-------- * IND long In BB25 New Local Constant Assertion: V00 != null index=#01, mask=0000000000000001 fgMorphTree BB25, STMT00060 (before) [000381] -AC-G------- * ASG long [000380] D------N---- +--* LCL_VAR long V25 tmp11 [000379] --C-G------- \--* QMARK long [000369] Q----------- if +--* NE int [000365] n----------- | +--* IND long [000364] ------------ | | \--* ADD long [000362] #----------- | | +--* IND long [000361] #----------- | | | \--* IND long [000360] ------------ | | | \--* ADD long [000358] ------------ | | | +--* LCL_VAR long V24 tmp10 [000359] ------------ | | | \--* CNS_INT long 56 [000363] ------------ | | \--* CNS_INT long 32 [000368] ------------ | \--* CNS_INT long 0 [000378] --C-G------- if \--* COLON long [000367] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000357] ------------ arg0 | +--* LCL_VAR long V24 tmp10 [000366] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000370] n----------- then \--* IND long [000371] ------------ \--* ADD long [000372] #----------- +--* IND long [000373] #----------- | \--* IND long [000374] ------------ | \--* ADD long [000375] ------------ | +--* LCL_VAR long V24 tmp10 [000376] ------------ | \--* CNS_INT long 56 [000377] ------------ \--* CNS_INT long 32 Initializing arg info for 367.CALL: ArgTable for 367.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 357.LCL_VAR long (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 366.CNS_INT long (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 367.CALL: argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000357] -----+------ * LCL_VAR long V24 tmp10 Replaced with placeholder node: [000864] ----------L- * ARGPLACE long Deferred argument ('rdx'): [000366] H----+------ * CNS_INT(h) long 0xd1ffab1e global ptr Replaced with placeholder node: [000865] ----------L- * ARGPLACE long Shuffled argument table: rcx rdx ArgTable for 367.CALL after fgMorphArgs: fgArgTabEntry[arg 0 357.LCL_VAR long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 366.CNS_INT long (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB25, STMT00060 (after) [000381] -AC-G+------ * ASG long [000380] D----+-N---- +--* LCL_VAR long V25 tmp11 [000379] --C-G+------ \--* QMARK long [000369] J----+-N---- if +--* NE int [000365] n----+------ | +--* IND long [000364] -----+------ | | \--* ADD long [000362] #----+------ | | +--* IND long [000361] #----+------ | | | \--* IND long [000360] -----+------ | | | \--* ADD long [000358] -----+------ | | | +--* LCL_VAR long V24 tmp10 [000359] -----+------ | | | \--* CNS_INT long 56 [000363] -----+------ | | \--* CNS_INT long 32 [000368] -----+------ | \--* CNS_INT long 0 [000378] --C-G+?----- if \--* COLON long [000367] --C-G+?----- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000357] -----+?----- arg0 in rcx | +--* LCL_VAR long V24 tmp10 [000366] H----+?----- arg1 in rdx | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000370] n----+?----- then \--* IND long [000371] -----+?----- \--* ADD long [000372] #----+?----- +--* IND long [000373] #----+?----- | \--* IND long [000374] -----+?----- | \--* ADD long [000375] -----+?----- | +--* LCL_VAR long V24 tmp10 [000376] -----+?----- | \--* CNS_INT long 56 [000377] -----+?----- \--* CNS_INT long 32 fgMorphTree BB25, STMT00062 (before) [000386] -AC--------- * ASG ref [000385] D------N---- +--* LCL_VAR ref V12 loc8 [000352] --C-G------- \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default [000383] ------------ arg0 \--* RUNTIMELOOKUP long 0xd1ffab1e class [000382] ------------ \--* LCL_VAR long V25 tmp11 Named Intrinsic System.Collections.Generic.EqualityComparer`1.get_Default: Recognized Initializing arg info for 352.CALL: ArgTable for 352.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 383.RUNTIMELOOKUP long (By ref), 1 reg: rcx, byteAlignment=8] Morphing args for 352.CALL: argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000382] -----+------ * LCL_VAR long V25 tmp11 Replaced with placeholder node: [000866] ----------L- * ARGPLACE long Shuffled argument table: rcx ArgTable for 352.CALL after fgMorphArgs: fgArgTabEntry[arg 0 382.LCL_VAR long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgMorphTree BB25, STMT00062 (after) [000386] -ACXG+------ * ASG ref [000385] D----+-N---- +--* LCL_VAR ref V12 loc8 [000352] --CXG+------ \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default [000382] -----+------ arg0 in rcx \--* LCL_VAR long V25 tmp11 Morphing BB27 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB27, STMT00063 (before) [000391] ---X-------- * JTRUE void [000390] N--X-----U-- \--* GE int [000387] ------------ +--* LCL_VAR int V09 loc5 [000389] ---X-------- \--* ARR_LENGTH int [000388] ------------ \--* LCL_VAR ref V04 loc0 GenTreeNode creates assertion: [000389] ---X-------- * ARR_LENGTH int In BB27 New Local Constant Assertion: V04 != null index=#01, mask=0000000000000001 Morphing BB28 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB28, STMT00064 (before) [000399] ---XG------- * JTRUE void [000398] N--XG----U-- \--* NE int [000396] ---XG------- +--* FIELD int hashCode [000395] ---XG------- | \--* ADDR byref [000394] ---XG--N---- | \--* INDEX struct [000392] ------------ | +--* LCL_VAR ref V04 loc0 [000393] ------------ | \--* LCL_VAR int V09 loc5 [000397] ------------ \--* LCL_VAR int V06 loc2 GenTreeNode creates assertion: [000871] ---X-------- * ARR_LENGTH int In BB28 New Local Constant Assertion: V04 != null index=#01, mask=0000000000000001 Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000396] *--XG------- * IND int [000868] ---XG+------ \--* ADD byref [000879] ---XG+------ +--* COMMA byref [000872] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000393] -----+------ | | +--* LCL_VAR int V09 loc5 [000871] ---X-+------ | | \--* ARR_LENGTH int [000392] -----+------ | | \--* LCL_VAR ref V04 loc0 [000882] ----G------- | \--* ADDR byref [000394] a---G+-N---- | \--* IND struct [000878] -----+------ | \--* ADD byref [000869] -----+------ | +--* LCL_VAR ref V04 loc0 [000877] -----+------ | \--* ADD long [000875] -----+------ | +--* LSH long [000881] -----+------ | | +--* MUL long [000873] -----+------ | | | +--* CAST long <- int [000870] i----+------ | | | | \--* LCL_VAR int V09 loc5 [000880] ------------ | | | \--* CNS_INT long 3 [000874] -----+-N---- | | \--* CNS_INT long 3 [000876] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [000867] -----+------ \--* CNS_INT long 16 field offset Fseq[hashCode] fgMorphTree BB28, STMT00064 (after) [000399] ---XG+------ * JTRUE void [000398] N--XG+-N-U-- \--* NE int [000396] *--XG+------ +--* IND int [000868] ---XG+------ | \--* ADD byref [000879] ---XG+------ | +--* COMMA byref [000872] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000393] -----+------ | | | +--* LCL_VAR int V09 loc5 [000871] ---X-+------ | | | \--* ARR_LENGTH int [000392] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000882] ----G------- | | \--* ADDR byref [000394] a---G+-N---- | | \--* IND struct [000878] -----+------ | | \--* ADD byref [000869] -----+------ | | +--* LCL_VAR ref V04 loc0 [000877] -----+------ | | \--* ADD long [000875] -----+------ | | +--* LSH long [000881] -----+------ | | | +--* MUL long [000873] -----+------ | | | | +--* CAST long <- int [000870] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000880] ------------ | | | | \--* CNS_INT long 3 [000874] -----+-N---- | | | \--* CNS_INT long 3 [000876] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000867] -----+------ | \--* CNS_INT long 16 field offset Fseq[hashCode] [000397] -----+------ \--* LCL_VAR int V06 loc2 Morphing BB29 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB29, STMT00069 (before) [000428] --CXG------- * JTRUE void [000427] --CXG------- \--* EQ int [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 [000423] ---XG------- arg1 | +--* FIELD ref key [000422] ---XG------- | | \--* ADDR byref [000421] ---XG--N---- | | \--* INDEX struct [000419] ------------ | | +--* LCL_VAR ref V04 loc0 [000420] ------------ | | \--* LCL_VAR int V09 loc5 [000424] ------------ arg2 | \--* LCL_VAR ref V01 arg1 [000426] ------------ \--* CNS_INT int 0 Initializing arg info for 425.CALL: ArgTable for 425.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 418.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 423.FIELD ref (By ref), 1 reg: rdx, byteAlignment=8] fgArgTabEntry[arg 2 424.LCL_VAR ref (By ref), 1 reg: r8, byteAlignment=8] Morphing args for 425.CALL: Before calling fgAddFieldSeqForZeroOffset: [000423] *--XG------- * IND ref [000422] ---XG------- \--* ADDR byref [000421] ---XG--N---- \--* INDEX struct [000419] ------------ +--* LCL_VAR ref V04 loc0 [000420] ------------ \--* LCL_VAR int V09 loc5 fgAddFieldSeqForZeroOffset for Fseq[key] addr (Before) [000422] ---XG------- ADDR byref (After) [000422] ---XG------- ADDR byref Zero Fseq[key] GenTreeNode creates assertion: [000885] ---X-------- * ARR_LENGTH int In BB29 New Local Constant Assertion: V04 != null index=#01, mask=0000000000000001 fgAddFieldSeqForZeroOffset for Fseq[key] addr (Before) [000896] ----G------- ADDR byref (After) [000896] ----G------- ADDR byref Zero Fseq[key] Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000893] ---XG+------ * COMMA ref [000886] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000420] -----+------ | +--* LCL_VAR int V09 loc5 [000885] ---X-+------ | \--* ARR_LENGTH int [000419] -----+------ | \--* LCL_VAR ref V04 loc0 [000897] *---G+------ \--* IND ref [000896] ----G------- \--* ADDR byref Zero Fseq[key] [000421] a---G+-N---- \--* IND struct [000892] -----+------ \--* ADD byref [000883] -----+------ +--* LCL_VAR ref V04 loc0 [000891] -----+------ \--* ADD long [000889] -----+------ +--* LSH long [000895] -----+------ | +--* MUL long [000887] -----+------ | | +--* CAST long <- int [000884] i----+------ | | | \--* LCL_VAR int V09 loc5 [000894] ------------ | | \--* CNS_INT long 3 [000888] -----+-N---- | \--* CNS_INT long 3 [000890] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] argSlots=3, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rdx'): [000893] ---XG+------ * COMMA ref [000886] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000420] -----+------ | +--* LCL_VAR int V09 loc5 [000885] ---X-+------ | \--* ARR_LENGTH int [000419] -----+------ | \--* LCL_VAR ref V04 loc0 [000897] *---G+------ \--* IND ref [000896] ----G------- \--* ADDR byref Zero Fseq[key] [000421] a---G+-N---- \--* IND struct [000892] -----+------ \--* ADD byref [000883] -----+------ +--* LCL_VAR ref V04 loc0 [000891] -----+------ \--* ADD long [000889] -----+------ +--* LSH long [000895] -----+------ | +--* MUL long [000887] -----+------ | | +--* CAST long <- int [000884] i----+------ | | | \--* LCL_VAR int V09 loc5 [000894] ------------ | | \--* CNS_INT long 3 [000888] -----+-N---- | \--* CNS_INT long 3 [000890] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] Replaced with placeholder node: [000898] ----------L- * ARGPLACE ref Deferred argument ('rcx'): [000418] -----+------ * LCL_VAR ref V12 loc8 Replaced with placeholder node: [000899] ----------L- * ARGPLACE ref Deferred argument ('r8'): [000424] -----+------ * LCL_VAR ref V01 arg1 Replaced with placeholder node: [000900] ----------L- * ARGPLACE ref Shuffled argument table: rdx rcx r8 ArgTable for 425.CALL after fgMorphArgs: fgArgTabEntry[arg 1 893.COMMA ref (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 0 418.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=1, processed] fgArgTabEntry[arg 2 424.LCL_VAR ref (By ref), 1 reg: r8, byteAlignment=8, lateArgInx=2, processed] Expanding virtual call target for 425.CALL: GenTreeNode creates assertion: [000902] #--X-------- * IND long In BB29 New Local Constant Assertion: V12 != null index=#02, mask=0000000000000002 fgMorphTree BB29, STMT00069 (after) [000428] --CXG+------ * JTRUE void [000427] J-CXG+-N---- \--* EQ int [000425] --CXG+------ +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals [000908] n--X-+------ control expr | \--* IND long [000907] ---X-+------ | \--* ADD long [000905] #--X-+------ | +--* IND long [000904] ---X-+------ | | \--* ADD long [000902] #--X-+------ | | +--* IND long [000901] -----+------ | | | \--* LCL_VAR ref V12 loc8 [000903] -----+------ | | \--* CNS_INT int 72 [000906] -----+------ | \--* CNS_INT int 32 [000893] ---XG+------ arg1 in rdx | +--* COMMA ref [000886] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000420] -----+------ | | | +--* LCL_VAR int V09 loc5 [000885] ---X-+------ | | | \--* ARR_LENGTH int [000419] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000897] *---G+------ | | \--* IND ref [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] [000421] a---G+-N---- | | \--* IND struct [000892] -----+------ | | \--* ADD byref [000883] -----+------ | | +--* LCL_VAR ref V04 loc0 [000891] -----+------ | | \--* ADD long [000889] -----+------ | | +--* LSH long [000895] -----+------ | | | +--* MUL long [000887] -----+------ | | | | +--* CAST long <- int [000884] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000894] ------------ | | | | \--* CNS_INT long 3 [000888] -----+-N---- | | | \--* CNS_INT long 3 [000890] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000418] -----+------ this in rcx | +--* LCL_VAR ref V12 loc8 [000424] -----+------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 [000426] -----+------ \--* CNS_INT int 0 Morphing BB30 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB30, STMT00070 (before) [000432] ------------ * JTRUE void [000431] N--------U-- \--* NE int [000429] ------------ +--* LCL_VAR ubyte V03 arg3 [000430] ------------ \--* CNS_INT int 1 fgMorphTree BB30, STMT00070 (after) [000432] -----+------ * JTRUE void [000431] N----+-N-U-- \--* NE int [000909] -----+------ +--* CAST int <- ubyte <- int [000429] -----+------ | \--* LCL_VAR int V03 arg3 [000430] -----+------ \--* CNS_INT int 1 Morphing BB31 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB31, STMT00077 (before) [000481] -A-XG------- * ASG ref [000480] ---XG--N---- +--* FIELD ref value [000478] ---XG------- | \--* ADDR byref [000477] ---XG--N---- | \--* INDEX struct [000475] ------------ | +--* LCL_VAR ref V04 loc0 [000476] ------------ | \--* LCL_VAR int V09 loc5 [000479] ------------ \--* LCL_VAR ref V02 arg2 GenTreeNode creates assertion: [000914] ---X-------- * ARR_LENGTH int In BB31 New Local Constant Assertion: V04 != null index=#01, mask=0000000000000001 Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000480] *--XG--N---- * IND ref [000911] ---XG+------ \--* ADD byref [000922] ---XG+------ +--* COMMA byref [000915] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000476] -----+------ | | +--* LCL_VAR int V09 loc5 [000914] ---X-+------ | | \--* ARR_LENGTH int [000475] -----+------ | | \--* LCL_VAR ref V04 loc0 [000925] ----G------- | \--* ADDR byref [000477] a---G+-N---- | \--* IND struct [000921] -----+------ | \--* ADD byref [000912] -----+------ | +--* LCL_VAR ref V04 loc0 [000920] -----+------ | \--* ADD long [000918] -----+------ | +--* LSH long [000924] -----+------ | | +--* MUL long [000916] -----+------ | | | +--* CAST long <- int [000913] i----+------ | | | | \--* LCL_VAR int V09 loc5 [000923] ------------ | | | \--* CNS_INT long 3 [000917] -----+-N---- | | \--* CNS_INT long 3 [000919] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [000910] -----+------ \--* CNS_INT long 8 field offset Fseq[value] fgMorphTree BB31, STMT00077 (after) [000481] -A-XG+------ * ASG ref [000480] *--XG+-N---- +--* IND ref [000911] ---XG+------ | \--* ADD byref [000922] ---XG+------ | +--* COMMA byref [000915] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000476] -----+------ | | | +--* LCL_VAR int V09 loc5 [000914] ---X-+------ | | | \--* ARR_LENGTH int [000475] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000925] ----G------- | | \--* ADDR byref [000477] a---G+-N---- | | \--* IND struct [000921] -----+------ | | \--* ADD byref [000912] -----+------ | | +--* LCL_VAR ref V04 loc0 [000920] -----+------ | | \--* ADD long [000918] -----+------ | | +--* LSH long [000924] -----+------ | | | +--* MUL long [000916] -----+------ | | | | +--* CAST long <- int [000913] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000923] ------------ | | | | \--* CNS_INT long 3 [000917] -----+-N---- | | | \--* CNS_INT long 3 [000919] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000910] -----+------ | \--* CNS_INT long 8 field offset Fseq[value] [000479] -----+------ \--* LCL_VAR ref V02 arg2 Morphing BB32 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB32, STMT00071 (before) [000436] ------------ * JTRUE void [000435] N--------U-- \--* NE int [000433] ------------ +--* LCL_VAR ubyte V03 arg3 [000434] ------------ \--* CNS_INT int 2 fgMorphTree BB32, STMT00071 (after) [000436] -----+------ * JTRUE void [000435] N----+-N-U-- \--* NE int [000926] -----+------ +--* CAST int <- ubyte <- int [000433] -----+------ | \--* LCL_VAR int V03 arg3 [000434] -----+------ \--* CNS_INT int 2 Morphing BB33 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB33, STMT00073 (before) [000444] -A-X-------- * ASG long [000443] D------N---- +--* LCL_VAR long V26 tmp12 [000442] #--X-------- \--* IND long [000441] !----------- \--* LCL_VAR ref V00 this GenTreeNode creates assertion: [000442] #--X-------- * IND long In BB33 New Local Constant Assertion: V00 != null index=#01, mask=0000000000000001 fgMorphTree BB33, STMT00074 (before) [000454] -A---------- * ASG ref [000453] D------N---- +--* LCL_VAR ref V27 tmp13 [000439] ------------ \--* LCL_VAR ref V01 arg1 GenTreeNode creates assertion: [000454] -A---------- * ASG ref In BB33 New Local Copy Assertion: V27 == V01 index=#02, mask=0000000000000002 fgMorphTree BB33, STMT00075 (before) [000472] -AC-G------- * ASG long [000471] D------N---- +--* LCL_VAR long V28 tmp14 [000470] --C-G------- \--* QMARK long [000460] Q----------- if +--* NE int [000456] n----------- | +--* IND long [000452] ------------ | | \--* ADD long [000450] #----------- | | +--* IND long [000449] #----------- | | | \--* IND long [000448] ------------ | | | \--* ADD long [000446] ------------ | | | +--* LCL_VAR long V26 tmp12 [000447] ------------ | | | \--* CNS_INT long 56 [000451] ------------ | | \--* CNS_INT long 56 [000459] ------------ | \--* CNS_INT long 0 [000469] --C-G------- if \--* COLON long [000458] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000445] ------------ arg0 | +--* LCL_VAR long V26 tmp12 [000457] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000461] n----------- then \--* IND long [000462] ------------ \--* ADD long [000463] #----------- +--* IND long [000464] #----------- | \--* IND long [000465] ------------ | \--* ADD long [000466] ------------ | +--* LCL_VAR long V26 tmp12 [000467] ------------ | \--* CNS_INT long 56 [000468] ------------ \--* CNS_INT long 56 Initializing arg info for 458.CALL: ArgTable for 458.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 445.LCL_VAR long (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 457.CNS_INT long (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 458.CALL: argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000445] -----+------ * LCL_VAR long V26 tmp12 Replaced with placeholder node: [000927] ----------L- * ARGPLACE long Deferred argument ('rdx'): [000457] H----+------ * CNS_INT(h) long 0xd1ffab1e global ptr Replaced with placeholder node: [000928] ----------L- * ARGPLACE long Shuffled argument table: rcx rdx ArgTable for 458.CALL after fgMorphArgs: fgArgTabEntry[arg 0 445.LCL_VAR long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 457.CNS_INT long (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB33, STMT00075 (after) [000472] -AC-G+------ * ASG long [000471] D----+-N---- +--* LCL_VAR long V28 tmp14 [000470] --C-G+------ \--* QMARK long [000460] J----+-N---- if +--* NE int [000456] n----+------ | +--* IND long [000452] -----+------ | | \--* ADD long [000450] #----+------ | | +--* IND long [000449] #----+------ | | | \--* IND long [000448] -----+------ | | | \--* ADD long [000446] -----+------ | | | +--* LCL_VAR long V26 tmp12 [000447] -----+------ | | | \--* CNS_INT long 56 [000451] -----+------ | | \--* CNS_INT long 56 [000459] -----+------ | \--* CNS_INT long 0 [000469] --C-G+?----- if \--* COLON long [000458] --C-G+?----- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000445] -----+?----- arg0 in rcx | +--* LCL_VAR long V26 tmp12 [000457] H----+?----- arg1 in rdx | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000461] n----+?----- then \--* IND long [000462] -----+?----- \--* ADD long [000463] #----+?----- +--* IND long [000464] #----+?----- | \--* IND long [000465] -----+?----- | \--* ADD long [000466] -----+?----- | +--* LCL_VAR long V26 tmp12 [000467] -----+?----- | \--* CNS_INT long 56 [000468] -----+?----- \--* CNS_INT long 56 fgMorphTree BB33, STMT00076 (before) [000440] --C-G------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000474] ------------ arg0 +--* RUNTIMELOOKUP long 0xd1ffab1e method [000473] ------------ | \--* LCL_VAR long V28 tmp14 [000455] ------------ arg1 \--* LCL_VAR ref V27 tmp13 Initializing arg info for 440.CALL: ArgTable for 440.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 474.RUNTIMELOOKUP long (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 455.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 440.CALL: Assertion prop in BB33: Copy Assertion: V27 == V01 index=#02, mask=0000000000000002 [000455] ------------ * LCL_VAR ref V01 arg1 argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000473] -----+------ * LCL_VAR long V28 tmp14 Replaced with placeholder node: [000929] ----------L- * ARGPLACE long Deferred argument ('rdx'): [000455] -----+------ * LCL_VAR ref V01 arg1 Replaced with placeholder node: [000930] ----------L- * ARGPLACE ref Shuffled argument table: rcx rdx ArgTable for 440.CALL after fgMorphArgs: fgArgTabEntry[arg 0 473.LCL_VAR long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 455.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB33, STMT00076 (after) [000440] --CXG+------ * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000473] -----+------ arg0 in rcx +--* LCL_VAR long V28 tmp14 [000455] -----+------ arg1 in rdx \--* LCL_VAR ref V01 arg1 Converting BB33 to BBJ_THROW Morphing BB35 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB35, STMT00065 (before) [000406] -A-XG------- * ASG int [000405] D------N---- +--* LCL_VAR int V09 loc5 [000404] ---XG------- \--* FIELD int next [000403] ---XG------- \--* ADDR byref [000402] ---XG--N---- \--* INDEX struct [000400] ------------ +--* LCL_VAR ref V04 loc0 [000401] ------------ \--* LCL_VAR int V09 loc5 GenTreeNode creates assertion: [000935] ---X-------- * ARR_LENGTH int In BB35 New Local Constant Assertion: V04 != null index=#01, mask=0000000000000001 Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000404] *--XG------- * IND int [000932] ---XG+------ \--* ADD byref [000943] ---XG+------ +--* COMMA byref [000936] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000401] -----+------ | | +--* LCL_VAR int V09 loc5 [000935] ---X-+------ | | \--* ARR_LENGTH int [000400] -----+------ | | \--* LCL_VAR ref V04 loc0 [000946] ----G------- | \--* ADDR byref [000402] a---G+-N---- | \--* IND struct [000942] -----+------ | \--* ADD byref [000933] -----+------ | +--* LCL_VAR ref V04 loc0 [000941] -----+------ | \--* ADD long [000939] -----+------ | +--* LSH long [000945] -----+------ | | +--* MUL long [000937] -----+------ | | | +--* CAST long <- int [000934] i----+------ | | | | \--* LCL_VAR int V09 loc5 [000944] ------------ | | | \--* CNS_INT long 3 [000938] -----+-N---- | | \--* CNS_INT long 3 [000940] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [000931] -----+------ \--* CNS_INT long 20 field offset Fseq[next] GenTreeNode creates assertion: [000406] -A-XG------- * ASG int In BB35 New Local Subrange Assertion: V09 in [-2147483648..2147483647] index=#02, mask=0000000000000002 fgMorphTree BB35, STMT00065 (after) [000406] -A-XG+------ * ASG int [000405] D----+-N---- +--* LCL_VAR int V09 loc5 [000404] *--XG+------ \--* IND int [000932] ---XG+------ \--* ADD byref [000943] ---XG+------ +--* COMMA byref [000936] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000401] -----+------ | | +--* LCL_VAR int V09 loc5 [000935] ---X-+------ | | \--* ARR_LENGTH int [000400] -----+------ | | \--* LCL_VAR ref V04 loc0 [000946] ----G------- | \--* ADDR byref [000402] a---G+-N---- | \--* IND struct [000942] -----+------ | \--* ADD byref [000933] -----+------ | +--* LCL_VAR ref V04 loc0 [000941] -----+------ | \--* ADD long [000939] -----+------ | +--* LSH long [000945] -----+------ | | +--* MUL long [000937] -----+------ | | | +--* CAST long <- int [000934] i----+------ | | | | \--* LCL_VAR int V09 loc5 [000944] ------------ | | | \--* CNS_INT long 3 [000938] -----+-N---- | | \--* CNS_INT long 3 [000940] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [000931] -----+------ \--* CNS_INT long 20 field offset Fseq[next] fgMorphTree BB35, STMT00066 (before) [000411] -A---------- * ASG int [000410] D------N---- +--* LCL_VAR int V07 loc3 [000409] ------------ \--* ADD int [000407] ------------ +--* LCL_VAR int V07 loc3 [000408] ------------ \--* CNS_INT int 1 fgMorphTree BB35, STMT00067 (before) [000416] ---X-------- * JTRUE void [000415] N--X-----U-- \--* LE int [000412] ------------ +--* LCL_VAR int V07 loc3 [000414] ---X-------- \--* ARR_LENGTH int [000413] ------------ \--* LCL_VAR ref V04 loc0 Morphing BB71 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' Morphing BB37 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB37, STMT00014 (before) [000066] ---X-------- * JTRUE void [000065] N--X-----U-- \--* GE int [000062] ------------ +--* LCL_VAR int V09 loc5 [000064] ---X-------- \--* ARR_LENGTH int [000063] ------------ \--* LCL_VAR ref V04 loc0 GenTreeNode creates assertion: [000064] ---X-------- * ARR_LENGTH int In BB37 New Local Constant Assertion: V04 != null index=#01, mask=0000000000000001 Morphing BB38 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB38, STMT00039 (before) [000215] ---XG------- * JTRUE void [000214] N--XG----U-- \--* NE int [000212] ---XG------- +--* FIELD int hashCode [000211] ---XG------- | \--* ADDR byref [000210] ---XG--N---- | \--* INDEX struct [000208] ------------ | +--* LCL_VAR ref V04 loc0 [000209] ------------ | \--* LCL_VAR int V09 loc5 [000213] ------------ \--* LCL_VAR int V06 loc2 GenTreeNode creates assertion: [000951] ---X-------- * ARR_LENGTH int In BB38 New Local Constant Assertion: V04 != null index=#01, mask=0000000000000001 Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000212] *--XG------- * IND int [000948] ---XG+------ \--* ADD byref [000959] ---XG+------ +--* COMMA byref [000952] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000209] -----+------ | | +--* LCL_VAR int V09 loc5 [000951] ---X-+------ | | \--* ARR_LENGTH int [000208] -----+------ | | \--* LCL_VAR ref V04 loc0 [000962] ----G------- | \--* ADDR byref [000210] a---G+-N---- | \--* IND struct [000958] -----+------ | \--* ADD byref [000949] -----+------ | +--* LCL_VAR ref V04 loc0 [000957] -----+------ | \--* ADD long [000955] -----+------ | +--* LSH long [000961] -----+------ | | +--* MUL long [000953] -----+------ | | | +--* CAST long <- int [000950] i----+------ | | | | \--* LCL_VAR int V09 loc5 [000960] ------------ | | | \--* CNS_INT long 3 [000954] -----+-N---- | | \--* CNS_INT long 3 [000956] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [000947] -----+------ \--* CNS_INT long 16 field offset Fseq[hashCode] fgMorphTree BB38, STMT00039 (after) [000215] ---XG+------ * JTRUE void [000214] N--XG+-N-U-- \--* NE int [000212] *--XG+------ +--* IND int [000948] ---XG+------ | \--* ADD byref [000959] ---XG+------ | +--* COMMA byref [000952] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000209] -----+------ | | | +--* LCL_VAR int V09 loc5 [000951] ---X-+------ | | | \--* ARR_LENGTH int [000208] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000962] ----G------- | | \--* ADDR byref [000210] a---G+-N---- | | \--* IND struct [000958] -----+------ | | \--* ADD byref [000949] -----+------ | | +--* LCL_VAR ref V04 loc0 [000957] -----+------ | | \--* ADD long [000955] -----+------ | | +--* LSH long [000961] -----+------ | | | +--* MUL long [000953] -----+------ | | | | +--* CAST long <- int [000950] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000960] ------------ | | | | \--* CNS_INT long 3 [000954] -----+-N---- | | | \--* CNS_INT long 3 [000956] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000947] -----+------ | \--* CNS_INT long 16 field offset Fseq[hashCode] [000213] -----+------ \--* LCL_VAR int V06 loc2 Morphing BB39 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB39, STMT00045 (before) [000246] -A-XG------- * ASG ref [000245] D------N---- +--* LCL_VAR ref V17 tmp3 [000239] ---XG------- \--* FIELD ref key [000238] ---XG------- \--* ADDR byref [000237] ---XG--N---- \--* INDEX struct [000235] ------------ +--* LCL_VAR ref V04 loc0 [000236] ------------ \--* LCL_VAR int V09 loc5 Before calling fgAddFieldSeqForZeroOffset: [000239] *--XG------- * IND ref [000238] ---XG------- \--* ADDR byref [000237] ---XG--N---- \--* INDEX struct [000235] ------------ +--* LCL_VAR ref V04 loc0 [000236] ------------ \--* LCL_VAR int V09 loc5 fgAddFieldSeqForZeroOffset for Fseq[key] addr (Before) [000238] ---XG------- ADDR byref (After) [000238] ---XG------- ADDR byref Zero Fseq[key] GenTreeNode creates assertion: [000965] ---X-------- * ARR_LENGTH int In BB39 New Local Constant Assertion: V04 != null index=#01, mask=0000000000000001 fgAddFieldSeqForZeroOffset for Fseq[key] addr (Before) [000976] ----G------- ADDR byref (After) [000976] ----G------- ADDR byref Zero Fseq[key] Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000973] ---XG+------ * COMMA ref [000966] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000236] -----+------ | +--* LCL_VAR int V09 loc5 [000965] ---X-+------ | \--* ARR_LENGTH int [000235] -----+------ | \--* LCL_VAR ref V04 loc0 [000977] *---G+------ \--* IND ref [000976] ----G------- \--* ADDR byref Zero Fseq[key] [000237] a---G+-N---- \--* IND struct [000972] -----+------ \--* ADD byref [000963] -----+------ +--* LCL_VAR ref V04 loc0 [000971] -----+------ \--* ADD long [000969] -----+------ +--* LSH long [000975] -----+------ | +--* MUL long [000967] -----+------ | | +--* CAST long <- int [000964] i----+------ | | | \--* LCL_VAR int V09 loc5 [000974] ------------ | | \--* CNS_INT long 3 [000968] -----+-N---- | \--* CNS_INT long 3 [000970] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] fgMorphTree BB39, STMT00045 (after) [000246] -A-XG+------ * ASG ref [000245] D----+-N---- +--* LCL_VAR ref V17 tmp3 [000973] ---XG+------ \--* COMMA ref [000966] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000236] -----+------ | +--* LCL_VAR int V09 loc5 [000965] ---X-+------ | \--* ARR_LENGTH int [000235] -----+------ | \--* LCL_VAR ref V04 loc0 [000977] *---G+------ \--* IND ref [000976] ----G------- \--* ADDR byref Zero Fseq[key] [000237] a---G+-N---- \--* IND struct [000972] -----+------ \--* ADD byref [000963] -----+------ +--* LCL_VAR ref V04 loc0 [000971] -----+------ \--* ADD long [000969] -----+------ +--* LSH long [000975] -----+------ | +--* MUL long [000967] -----+------ | | +--* CAST long <- int [000964] i----+------ | | | \--* LCL_VAR int V09 loc5 [000974] ------------ | | \--* CNS_INT long 3 [000968] -----+-N---- | \--* CNS_INT long 3 [000970] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] fgMorphTree BB39, STMT00044 (before) [000244] -A-X-------- * ASG long [000243] D------N---- +--* LCL_VAR long V16 tmp2 [000242] #--X-------- \--* IND long [000241] !----------- \--* LCL_VAR ref V00 this GenTreeNode creates assertion: [000242] #--X-------- * IND long In BB39 New Local Constant Assertion: V00 != null index=#02, mask=0000000000000002 fgMorphTree BB39, STMT00046 (before) [000257] -A---------- * ASG ref [000256] D------N---- +--* LCL_VAR ref V18 tmp4 [000240] ------------ \--* LCL_VAR ref V01 arg1 GenTreeNode creates assertion: [000257] -A---------- * ASG ref In BB39 New Local Copy Assertion: V18 == V01 index=#03, mask=0000000000000004 fgMorphTree BB39, STMT00047 (before) [000275] -AC-G------- * ASG long [000274] D------N---- +--* LCL_VAR long V19 tmp5 [000273] --C-G------- \--* QMARK long [000263] Q----------- if +--* NE int [000259] n----------- | +--* IND long [000255] ------------ | | \--* ADD long [000253] #----------- | | +--* IND long [000252] #----------- | | | \--* IND long [000251] ------------ | | | \--* ADD long [000249] ------------ | | | +--* LCL_VAR long V16 tmp2 [000250] ------------ | | | \--* CNS_INT long 56 [000254] ------------ | | \--* CNS_INT long 48 [000262] ------------ | \--* CNS_INT long 0 [000272] --C-G------- if \--* COLON long [000261] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000248] ------------ arg0 | +--* LCL_VAR long V16 tmp2 [000260] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000264] n----------- then \--* IND long [000265] ------------ \--* ADD long [000266] #----------- +--* IND long [000267] #----------- | \--* IND long [000268] ------------ | \--* ADD long [000269] ------------ | +--* LCL_VAR long V16 tmp2 [000270] ------------ | \--* CNS_INT long 56 [000271] ------------ \--* CNS_INT long 48 Initializing arg info for 261.CALL: ArgTable for 261.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 248.LCL_VAR long (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 260.CNS_INT long (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 261.CALL: argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000248] -----+------ * LCL_VAR long V16 tmp2 Replaced with placeholder node: [000978] ----------L- * ARGPLACE long Deferred argument ('rdx'): [000260] H----+------ * CNS_INT(h) long 0xd1ffab1e global ptr Replaced with placeholder node: [000979] ----------L- * ARGPLACE long Shuffled argument table: rcx rdx ArgTable for 261.CALL after fgMorphArgs: fgArgTabEntry[arg 0 248.LCL_VAR long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 260.CNS_INT long (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB39, STMT00047 (after) [000275] -AC-G+------ * ASG long [000274] D----+-N---- +--* LCL_VAR long V19 tmp5 [000273] --C-G+------ \--* QMARK long [000263] J----+-N---- if +--* NE int [000259] n----+------ | +--* IND long [000255] -----+------ | | \--* ADD long [000253] #----+------ | | +--* IND long [000252] #----+------ | | | \--* IND long [000251] -----+------ | | | \--* ADD long [000249] -----+------ | | | +--* LCL_VAR long V16 tmp2 [000250] -----+------ | | | \--* CNS_INT long 56 [000254] -----+------ | | \--* CNS_INT long 48 [000262] -----+------ | \--* CNS_INT long 0 [000272] --C-G+?----- if \--* COLON long [000261] --C-G+?----- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000248] -----+?----- arg0 in rcx | +--* LCL_VAR long V16 tmp2 [000260] H----+?----- arg1 in rdx | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000264] n----+?----- then \--* IND long [000265] -----+?----- \--* ADD long [000266] #----+?----- +--* IND long [000267] #----+?----- | \--* IND long [000268] -----+?----- | \--* ADD long [000269] -----+?----- | +--* LCL_VAR long V16 tmp2 [000270] -----+?----- | \--* CNS_INT long 56 [000271] -----+?----- \--* CNS_INT long 48 fgMorphTree BB39, STMT00048 (before) [000278] -A---------- * ASG long [000277] D------N---- +--* LCL_VAR long V20 tmp6 [000276] ------------ \--* LCL_VAR long V19 tmp5 GenTreeNode creates assertion: [000278] -A---------- * ASG long In BB39 New Local Copy Assertion: V20 == V19 index=#04, mask=0000000000000008 fgMorphTree BB39, STMT00049 (before) [000283] --CXG------- * JTRUE void [000282] --CXG------- \--* EQ int [000280] --CXG------- +--* CALL ind stub int [000234] ------------ this in rcx | +--* LCL_VAR ref V05 loc1 [000247] ------------ arg1 | +--* LCL_VAR ref V17 tmp3 [000258] ------------ arg2 | +--* LCL_VAR ref V18 tmp4 [000279] ------------ calli tgt | \--* LCL_VAR long V20 tmp6 [000281] ------------ \--* CNS_INT int 0 Initializing arg info for 280.CALL: ArgTable for 280.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 234.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 980.LCL_VAR long (By ref), 1 reg: r11, byteAlignment=8, isNonStandard] fgArgTabEntry[arg 2 247.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8] fgArgTabEntry[arg 3 258.LCL_VAR ref (By ref), 1 reg: r8, byteAlignment=8] Morphing args for 280.CALL: Assertion prop in BB39: Copy Assertion: V20 == V19 index=#04, mask=0000000000000008 [000980] ------------ * LCL_VAR long V19 tmp5 r11 REG r11 Assertion prop in BB39: Copy Assertion: V18 == V01 index=#03, mask=0000000000000004 [000258] ------------ * LCL_VAR ref V01 arg1 Assertion prop in BB39: Copy Assertion: V20 == V19 index=#04, mask=0000000000000008 [000279] ------------ * LCL_VAR long V19 tmp5 argSlots=3, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000234] -----+------ * LCL_VAR ref V05 loc1 Replaced with placeholder node: [000981] ----------L- * ARGPLACE ref Deferred argument ('r11'): [000980] -----+------ * LCL_VAR long V19 tmp5 r11 REG r11 Replaced with placeholder node: [000982] ----------L- * ARGPLACE long Deferred argument ('rdx'): [000247] -----+------ * LCL_VAR ref V17 tmp3 Replaced with placeholder node: [000983] ----------L- * ARGPLACE ref Deferred argument ('r8'): [000258] -----+------ * LCL_VAR ref V01 arg1 Replaced with placeholder node: [000984] ----------L- * ARGPLACE ref Shuffled argument table: rcx r11 rdx r8 ArgTable for 280.CALL after fgMorphArgs: fgArgTabEntry[arg 0 234.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 980.LCL_VAR long (By ref), 1 reg: r11, byteAlignment=8, lateArgInx=1, processed, isNonStandard] fgArgTabEntry[arg 2 247.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=2, processed] fgArgTabEntry[arg 3 258.LCL_VAR ref (By ref), 1 reg: r8, byteAlignment=8, lateArgInx=3, processed] GenTreeNode creates assertion: [000280] --CXG------- * CALL ind stub int In BB39 New Local Constant Assertion: V05 != null index=#05, mask=0000000000000010 fgMorphTree BB39, STMT00049 (after) [000283] --CXG+------ * JTRUE void [000282] J-CXG+-N---- \--* EQ int [000280] --CXG+------ +--* CALL ind stub int [000279] -----+------ calli tgt | \--* LCL_VAR long V19 tmp5 [000234] -----+------ this in rcx | +--* LCL_VAR ref V05 loc1 [000980] -----+------ arg1 in r11 | +--* LCL_VAR long V19 tmp5 r11 REG r11 [000247] -----+------ arg2 in rdx | +--* LCL_VAR ref V17 tmp3 [000258] -----+------ arg3 in r8 | \--* LCL_VAR ref V01 arg1 [000281] -----+------ \--* CNS_INT int 0 Morphing BB40 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB40, STMT00050 (before) [000287] ------------ * JTRUE void [000286] N--------U-- \--* NE int [000284] ------------ +--* LCL_VAR ubyte V03 arg3 [000285] ------------ \--* CNS_INT int 1 fgMorphTree BB40, STMT00050 (after) [000287] -----+------ * JTRUE void [000286] N----+-N-U-- \--* NE int [000985] -----+------ +--* CAST int <- ubyte <- int [000284] -----+------ | \--* LCL_VAR int V03 arg3 [000285] -----+------ \--* CNS_INT int 1 Morphing BB41 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB41, STMT00057 (before) [000336] -A-XG------- * ASG ref [000335] ---XG--N---- +--* FIELD ref value [000333] ---XG------- | \--* ADDR byref [000332] ---XG--N---- | \--* INDEX struct [000330] ------------ | +--* LCL_VAR ref V04 loc0 [000331] ------------ | \--* LCL_VAR int V09 loc5 [000334] ------------ \--* LCL_VAR ref V02 arg2 GenTreeNode creates assertion: [000990] ---X-------- * ARR_LENGTH int In BB41 New Local Constant Assertion: V04 != null index=#01, mask=0000000000000001 Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000335] *--XG--N---- * IND ref [000987] ---XG+------ \--* ADD byref [000998] ---XG+------ +--* COMMA byref [000991] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000331] -----+------ | | +--* LCL_VAR int V09 loc5 [000990] ---X-+------ | | \--* ARR_LENGTH int [000330] -----+------ | | \--* LCL_VAR ref V04 loc0 [001001] ----G------- | \--* ADDR byref [000332] a---G+-N---- | \--* IND struct [000997] -----+------ | \--* ADD byref [000988] -----+------ | +--* LCL_VAR ref V04 loc0 [000996] -----+------ | \--* ADD long [000994] -----+------ | +--* LSH long [001000] -----+------ | | +--* MUL long [000992] -----+------ | | | +--* CAST long <- int [000989] i----+------ | | | | \--* LCL_VAR int V09 loc5 [000999] ------------ | | | \--* CNS_INT long 3 [000993] -----+-N---- | | \--* CNS_INT long 3 [000995] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [000986] -----+------ \--* CNS_INT long 8 field offset Fseq[value] fgMorphTree BB41, STMT00057 (after) [000336] -A-XG+------ * ASG ref [000335] *--XG+-N---- +--* IND ref [000987] ---XG+------ | \--* ADD byref [000998] ---XG+------ | +--* COMMA byref [000991] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000331] -----+------ | | | +--* LCL_VAR int V09 loc5 [000990] ---X-+------ | | | \--* ARR_LENGTH int [000330] -----+------ | | | \--* LCL_VAR ref V04 loc0 [001001] ----G------- | | \--* ADDR byref [000332] a---G+-N---- | | \--* IND struct [000997] -----+------ | | \--* ADD byref [000988] -----+------ | | +--* LCL_VAR ref V04 loc0 [000996] -----+------ | | \--* ADD long [000994] -----+------ | | +--* LSH long [001000] -----+------ | | | +--* MUL long [000992] -----+------ | | | | +--* CAST long <- int [000989] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000999] ------------ | | | | \--* CNS_INT long 3 [000993] -----+-N---- | | | \--* CNS_INT long 3 [000995] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000986] -----+------ | \--* CNS_INT long 8 field offset Fseq[value] [000334] -----+------ \--* LCL_VAR ref V02 arg2 Morphing BB42 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB42, STMT00051 (before) [000291] ------------ * JTRUE void [000290] N--------U-- \--* NE int [000288] ------------ +--* LCL_VAR ubyte V03 arg3 [000289] ------------ \--* CNS_INT int 2 fgMorphTree BB42, STMT00051 (after) [000291] -----+------ * JTRUE void [000290] N----+-N-U-- \--* NE int [001002] -----+------ +--* CAST int <- ubyte <- int [000288] -----+------ | \--* LCL_VAR int V03 arg3 [000289] -----+------ \--* CNS_INT int 2 Morphing BB43 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB43, STMT00053 (before) [000299] -A-X-------- * ASG long [000298] D------N---- +--* LCL_VAR long V21 tmp7 [000297] #--X-------- \--* IND long [000296] !----------- \--* LCL_VAR ref V00 this GenTreeNode creates assertion: [000297] #--X-------- * IND long In BB43 New Local Constant Assertion: V00 != null index=#01, mask=0000000000000001 fgMorphTree BB43, STMT00054 (before) [000309] -A---------- * ASG ref [000308] D------N---- +--* LCL_VAR ref V22 tmp8 [000294] ------------ \--* LCL_VAR ref V01 arg1 GenTreeNode creates assertion: [000309] -A---------- * ASG ref In BB43 New Local Copy Assertion: V22 == V01 index=#02, mask=0000000000000002 fgMorphTree BB43, STMT00055 (before) [000327] -AC-G------- * ASG long [000326] D------N---- +--* LCL_VAR long V23 tmp9 [000325] --C-G------- \--* QMARK long [000315] Q----------- if +--* NE int [000311] n----------- | +--* IND long [000307] ------------ | | \--* ADD long [000305] #----------- | | +--* IND long [000304] #----------- | | | \--* IND long [000303] ------------ | | | \--* ADD long [000301] ------------ | | | +--* LCL_VAR long V21 tmp7 [000302] ------------ | | | \--* CNS_INT long 56 [000306] ------------ | | \--* CNS_INT long 56 [000314] ------------ | \--* CNS_INT long 0 [000324] --C-G------- if \--* COLON long [000313] --C-G------- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000300] ------------ arg0 | +--* LCL_VAR long V21 tmp7 [000312] H----------- arg1 | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000316] n----------- then \--* IND long [000317] ------------ \--* ADD long [000318] #----------- +--* IND long [000319] #----------- | \--* IND long [000320] ------------ | \--* ADD long [000321] ------------ | +--* LCL_VAR long V21 tmp7 [000322] ------------ | \--* CNS_INT long 56 [000323] ------------ \--* CNS_INT long 56 Initializing arg info for 313.CALL: ArgTable for 313.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 300.LCL_VAR long (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 312.CNS_INT long (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 313.CALL: argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000300] -----+------ * LCL_VAR long V21 tmp7 Replaced with placeholder node: [001003] ----------L- * ARGPLACE long Deferred argument ('rdx'): [000312] H----+------ * CNS_INT(h) long 0xd1ffab1e global ptr Replaced with placeholder node: [001004] ----------L- * ARGPLACE long Shuffled argument table: rcx rdx ArgTable for 313.CALL after fgMorphArgs: fgArgTabEntry[arg 0 300.LCL_VAR long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 312.CNS_INT long (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB43, STMT00055 (after) [000327] -AC-G+------ * ASG long [000326] D----+-N---- +--* LCL_VAR long V23 tmp9 [000325] --C-G+------ \--* QMARK long [000315] J----+-N---- if +--* NE int [000311] n----+------ | +--* IND long [000307] -----+------ | | \--* ADD long [000305] #----+------ | | +--* IND long [000304] #----+------ | | | \--* IND long [000303] -----+------ | | | \--* ADD long [000301] -----+------ | | | +--* LCL_VAR long V21 tmp7 [000302] -----+------ | | | \--* CNS_INT long 56 [000306] -----+------ | | \--* CNS_INT long 56 [000314] -----+------ | \--* CNS_INT long 0 [000324] --C-G+?----- if \--* COLON long [000313] --C-G+?----- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000300] -----+?----- arg0 in rcx | +--* LCL_VAR long V21 tmp7 [000312] H----+?----- arg1 in rdx | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000316] n----+?----- then \--* IND long [000317] -----+?----- \--* ADD long [000318] #----+?----- +--* IND long [000319] #----+?----- | \--* IND long [000320] -----+?----- | \--* ADD long [000321] -----+?----- | +--* LCL_VAR long V21 tmp7 [000322] -----+?----- | \--* CNS_INT long 56 [000323] -----+?----- \--* CNS_INT long 56 fgMorphTree BB43, STMT00056 (before) [000295] --C-G------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000329] ------------ arg0 +--* RUNTIMELOOKUP long 0xd1ffab1e method [000328] ------------ | \--* LCL_VAR long V23 tmp9 [000310] ------------ arg1 \--* LCL_VAR ref V22 tmp8 Initializing arg info for 295.CALL: ArgTable for 295.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 329.RUNTIMELOOKUP long (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 310.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 295.CALL: Assertion prop in BB43: Copy Assertion: V22 == V01 index=#02, mask=0000000000000002 [000310] ------------ * LCL_VAR ref V01 arg1 argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000328] -----+------ * LCL_VAR long V23 tmp9 Replaced with placeholder node: [001005] ----------L- * ARGPLACE long Deferred argument ('rdx'): [000310] -----+------ * LCL_VAR ref V01 arg1 Replaced with placeholder node: [001006] ----------L- * ARGPLACE ref Shuffled argument table: rcx rdx ArgTable for 295.CALL after fgMorphArgs: fgArgTabEntry[arg 0 328.LCL_VAR long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 310.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB43, STMT00056 (after) [000295] --CXG+------ * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000328] -----+------ arg0 in rcx +--* LCL_VAR long V23 tmp9 [000310] -----+------ arg1 in rdx \--* LCL_VAR ref V01 arg1 Converting BB43 to BBJ_THROW Morphing BB45 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB45, STMT00148 (before) [000811] ------------ * RETURN int [000437] ------------ \--* CNS_INT int 0 Morphing BB46 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB46, STMT00040 (before) [000222] -A-XG------- * ASG int [000221] D------N---- +--* LCL_VAR int V09 loc5 [000220] ---XG------- \--* FIELD int next [000219] ---XG------- \--* ADDR byref [000218] ---XG--N---- \--* INDEX struct [000216] ------------ +--* LCL_VAR ref V04 loc0 [000217] ------------ \--* LCL_VAR int V09 loc5 GenTreeNode creates assertion: [001012] ---X-------- * ARR_LENGTH int In BB46 New Local Constant Assertion: V04 != null index=#01, mask=0000000000000001 Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000220] *--XG------- * IND int [001009] ---XG+------ \--* ADD byref [001020] ---XG+------ +--* COMMA byref [001013] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000217] -----+------ | | +--* LCL_VAR int V09 loc5 [001012] ---X-+------ | | \--* ARR_LENGTH int [000216] -----+------ | | \--* LCL_VAR ref V04 loc0 [001023] ----G------- | \--* ADDR byref [000218] a---G+-N---- | \--* IND struct [001019] -----+------ | \--* ADD byref [001010] -----+------ | +--* LCL_VAR ref V04 loc0 [001018] -----+------ | \--* ADD long [001016] -----+------ | +--* LSH long [001022] -----+------ | | +--* MUL long [001014] -----+------ | | | +--* CAST long <- int [001011] i----+------ | | | | \--* LCL_VAR int V09 loc5 [001021] ------------ | | | \--* CNS_INT long 3 [001015] -----+-N---- | | \--* CNS_INT long 3 [001017] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [001008] -----+------ \--* CNS_INT long 20 field offset Fseq[next] GenTreeNode creates assertion: [000222] -A-XG------- * ASG int In BB46 New Local Subrange Assertion: V09 in [-2147483648..2147483647] index=#02, mask=0000000000000002 fgMorphTree BB46, STMT00040 (after) [000222] -A-XG+------ * ASG int [000221] D----+-N---- +--* LCL_VAR int V09 loc5 [000220] *--XG+------ \--* IND int [001009] ---XG+------ \--* ADD byref [001020] ---XG+------ +--* COMMA byref [001013] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000217] -----+------ | | +--* LCL_VAR int V09 loc5 [001012] ---X-+------ | | \--* ARR_LENGTH int [000216] -----+------ | | \--* LCL_VAR ref V04 loc0 [001023] ----G------- | \--* ADDR byref [000218] a---G+-N---- | \--* IND struct [001019] -----+------ | \--* ADD byref [001010] -----+------ | +--* LCL_VAR ref V04 loc0 [001018] -----+------ | \--* ADD long [001016] -----+------ | +--* LSH long [001022] -----+------ | | +--* MUL long [001014] -----+------ | | | +--* CAST long <- int [001011] i----+------ | | | | \--* LCL_VAR int V09 loc5 [001021] ------------ | | | \--* CNS_INT long 3 [001015] -----+-N---- | | \--* CNS_INT long 3 [001017] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [001008] -----+------ \--* CNS_INT long 20 field offset Fseq[next] fgMorphTree BB46, STMT00041 (before) [000227] -A---------- * ASG int [000226] D------N---- +--* LCL_VAR int V07 loc3 [000225] ------------ \--* ADD int [000223] ------------ +--* LCL_VAR int V07 loc3 [000224] ------------ \--* CNS_INT int 1 fgMorphTree BB46, STMT00042 (before) [000232] ---X-------- * JTRUE void [000231] N--X-----U-- \--* LE int [000228] ------------ +--* LCL_VAR int V07 loc3 [000230] ---X-------- \--* ARR_LENGTH int [000229] ------------ \--* LCL_VAR ref V04 loc0 Morphing BB47 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB47, STMT00043 (before) [000233] --C-G------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported Initializing arg info for 233.CALL: ArgTable for 233.CALL after fgInitArgInfo: Morphing args for 233.CALL: argSlots=0, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 ArgTable for 233.CALL after fgMorphArgs: Converting BB47 to BBJ_THROW Morphing BB48 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB48, STMT00015 (before) [000071] ---XG------- * JTRUE void [000070] ---XG------- \--* LE int [000068] ---XG------- +--* FIELD int _freeCount [000067] ------------ | \--* LCL_VAR ref V00 this [000069] ------------ \--* CNS_INT int 0 Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000068] ---XG------- * IND int [001025] -----+------ \--* ADD byref [000067] -----+------ +--* LCL_VAR ref V00 this [001024] -----+------ \--* CNS_INT long 64 field offset Fseq[_freeCount] GenTreeNode creates assertion: [000068] ---XG------- * IND int In BB48 New Local Constant Assertion: V00 != null index=#01, mask=0000000000000001 fgMorphTree BB48, STMT00015 (after) [000071] ---XG+------ * JTRUE void [000070] J--XG+-N---- \--* LE int [000068] ---XG+------ +--* IND int [001025] -----+------ | \--* ADD byref [000067] -----+------ | +--* LCL_VAR ref V00 this [001024] -----+------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] [000069] -----+------ \--* CNS_INT int 0 Morphing BB49 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB49, STMT00035 (before) [000174] -A-XG------- * ASG int [000173] D------N---- +--* LCL_VAR int V10 loc6 [000172] ---XG------- \--* FIELD int _freeList [000171] ------------ \--* LCL_VAR ref V00 this Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000172] ---XG------- * IND int [001027] -----+------ \--* ADD byref [000171] -----+------ +--* LCL_VAR ref V00 this [001026] -----+------ \--* CNS_INT long 60 field offset Fseq[_freeList] GenTreeNode creates assertion: [000172] ---XG------- * IND int In BB49 New Local Constant Assertion: V00 != null index=#01, mask=0000000000000001 GenTreeNode creates assertion: [000174] -A-XG------- * ASG int In BB49 New Local Subrange Assertion: V10 in [-2147483648..2147483647] index=#02, mask=0000000000000002 fgMorphTree BB49, STMT00035 (after) [000174] -A-XG+------ * ASG int [000173] D----+-N---- +--* LCL_VAR int V10 loc6 [000172] ---XG+------ \--* IND int [001027] -----+------ \--* ADD byref [000171] -----+------ +--* LCL_VAR ref V00 this [001026] -----+------ \--* CNS_INT long 60 field offset Fseq[_freeList] fgMorphTree BB49, STMT00120 (before) [000688] -A-XG------- * ASG bool [000687] D------N---- +--* LCL_VAR bool V49 tmp35 [000680] ---XG------- \--* CAST int <- bool <- int [000186] ---XG------- \--* EQ int [000184] ---XG------- +--* LT int [000182] ---XG------- | +--* SUB int [000175] ------------ | | +--* CNS_INT int -3 [000181] ---XG------- | | \--* FIELD int next [000180] ---XG------- | | \--* ADDR byref [000179] ---XG--N---- | | \--* INDEX struct [000176] ------------ | | +--* LCL_VAR ref V04 loc0 [000178] ---XG------- | | \--* FIELD int _freeList [000177] ------------ | | \--* LCL_VAR ref V00 this [000183] ------------ | \--* CNS_INT int -1 [000185] ------------ \--* CNS_INT int 0 lvaGrabTemp returning 62 (V62 tmp48) called for index expr. Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000178] ---XG------- * IND int [001046] -----+------ \--* ADD byref [000177] -----+------ +--* LCL_VAR ref V00 this [001045] -----+------ \--* CNS_INT long 60 field offset Fseq[_freeList] GenTreeNode creates assertion: [001032] -A-XG------- * ASG int In BB49 New Local Subrange Assertion: V62 in [-2147483648..2147483647] index=#03, mask=0000000000000004 GenTreeNode creates assertion: [001035] ---X-------- * ARR_LENGTH int In BB49 New Local Constant Assertion: V04 != null index=#04, mask=0000000000000008 Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000181] *A-XG------- * IND int [001029] -A-XG+------ \--* ADD byref [001044] -A-XG+------ +--* COMMA byref [001032] -A-XG+------ | +--* ASG int [001031] D----+-N---- | | +--* LCL_VAR int V62 tmp48 [000178] ---XG+------ | | \--* IND int [001046] -----+------ | | \--* ADD byref [000177] -----+------ | | +--* LCL_VAR ref V00 this [001045] -----+------ | | \--* CNS_INT long 60 field offset Fseq[_freeList] [001043] ---XG+------ | \--* COMMA byref [001036] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [001033] -----+------ | | +--* LCL_VAR int V62 tmp48 [001035] ---X-+------ | | \--* ARR_LENGTH int [000176] -----+------ | | \--* LCL_VAR ref V04 loc0 [001049] ----G------- | \--* ADDR byref [000179] a---G+-N---- | \--* IND struct [001042] -----+------ | \--* ADD byref [001030] -----+------ | +--* LCL_VAR ref V04 loc0 [001041] -----+------ | \--* ADD long [001039] -----+------ | +--* LSH long [001048] -----+------ | | +--* MUL long [001037] -----+------ | | | +--* CAST long <- int [001034] i----+------ | | | | \--* LCL_VAR int V62 tmp48 [001047] ------------ | | | \--* CNS_INT long 3 [001038] -----+-N---- | | \--* CNS_INT long 3 [001040] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [001028] -----+------ \--* CNS_INT long 20 field offset Fseq[next] GenTreeNode creates assertion: [000688] -A-XG------- * ASG bool In BB49 New Local Subrange Assertion: V49 in [0..1] index=#05, mask=0000000000000010 fgMorphTree BB49, STMT00120 (after) [000688] -A-XG+------ * ASG bool [000687] D----+-N---- +--* LCL_VAR int V49 tmp35 [000184] -A-XG+------ \--* GE int [000182] -A-XG+------ +--* ADD int [001050] -A-XG+------ | +--* NEG int [000181] *A-XG+------ | | \--* IND int [001029] -A-XG+------ | | \--* ADD byref [001044] -A-XG+------ | | +--* COMMA byref [001032] -A-XG+------ | | | +--* ASG int [001031] D----+-N---- | | | | +--* LCL_VAR int V62 tmp48 [000178] ---XG+------ | | | | \--* IND int [001046] -----+------ | | | | \--* ADD byref [000177] -----+------ | | | | +--* LCL_VAR ref V00 this [001045] -----+------ | | | | \--* CNS_INT long 60 field offset Fseq[_freeList] [001043] ---XG+------ | | | \--* COMMA byref [001036] ---X-+------ | | | +--* ARR_BOUNDS_CHECK_Rng void [001033] -----+------ | | | | +--* LCL_VAR int V62 tmp48 [001035] ---X-+------ | | | | \--* ARR_LENGTH int [000176] -----+------ | | | | \--* LCL_VAR ref V04 loc0 [001049] ----G------- | | | \--* ADDR byref [000179] a---G+-N---- | | | \--* IND struct [001042] -----+------ | | | \--* ADD byref [001030] -----+------ | | | +--* LCL_VAR ref V04 loc0 [001041] -----+------ | | | \--* ADD long [001039] -----+------ | | | +--* LSH long [001048] -----+------ | | | | +--* MUL long [001037] -----+------ | | | | | +--* CAST long <- int [001034] i----+------ | | | | | | \--* LCL_VAR int V62 tmp48 [001047] ------------ | | | | | \--* CNS_INT long 3 [001038] -----+-N---- | | | | \--* CNS_INT long 3 [001040] -----+------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] [001028] -----+------ | | \--* CNS_INT long 20 field offset Fseq[next] [000175] -----+------ | \--* CNS_INT int -3 [000183] -----+------ \--* CNS_INT int -1 fgMorphTree BB49, STMT00123 (before) [000698] -A--G------- * ASG ref [000697] D------N---- +--* LCL_VAR ref V50 tmp36 [000684] #---G------- \--* IND ref [000683] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] fgMorphTree BB49, STMT00121 (before) [000693] ------------ * JTRUE void [000692] ------------ \--* NE int [000690] ------------ +--* LCL_VAR int V49 tmp35 [000691] ------------ \--* CNS_INT int 0 Morphing BB51 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB51, STMT00122 (before) [000696] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000694] ------------ arg0 +--* CNS_STR ref [000695] ------------ arg1 \--* LCL_VAR ref V50 tmp36 Initializing arg info for 696.CALL: ArgTable for 696.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 694.CNS_STR ref (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 695.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 696.CALL: argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [001052] #---G+------ * IND ref [001051] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" Replaced with placeholder node: [001053] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000695] -----+------ * LCL_VAR ref V50 tmp36 Replaced with placeholder node: [001054] ----------L- * ARGPLACE ref Shuffled argument table: rcx rdx ArgTable for 696.CALL after fgMorphArgs: fgArgTabEntry[arg 0 1052.IND ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 695.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB51, STMT00122 (after) [000696] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [001052] #---G+------ arg0 in rcx +--* IND ref [001051] H----+------ | \--* CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" [000695] -----+------ arg1 in rdx \--* LCL_VAR ref V50 tmp36 Morphing BB52 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB52, STMT00037 (before) [000200] -A-XG------- * ASG int [000199] ---XG--N---- +--* FIELD int _freeList [000190] ------------ | \--* LCL_VAR ref V00 this [000198] ---XG------- \--* SUB int [000191] ------------ +--* CNS_INT int -3 [000197] ---XG------- \--* FIELD int next [000196] ---XG------- \--* ADDR byref [000195] ---XG--N---- \--* INDEX struct [000192] ------------ +--* LCL_VAR ref V04 loc0 [000194] ---XG------- \--* FIELD int _freeList [000193] ------------ \--* LCL_VAR ref V00 this Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000199] ---XG--N---- * IND int [001056] -----+------ \--* ADD byref [000190] -----+------ +--* LCL_VAR ref V00 this [001055] -----+------ \--* CNS_INT long 60 field offset Fseq[_freeList] GenTreeNode creates assertion: [000199] ---XG--N---- * IND int In BB52 New Local Constant Assertion: V00 != null index=#01, mask=0000000000000001 lvaGrabTemp returning 63 (V63 tmp49) called for index expr. Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000194] ---XG------- * IND int [001075] -----+------ \--* ADD byref [000193] -----+------ +--* LCL_VAR ref V00 this [001074] -----+------ \--* CNS_INT long 60 field offset Fseq[_freeList] GenTreeNode creates assertion: [001061] -A-XG------- * ASG int In BB52 New Local Subrange Assertion: V63 in [-2147483648..2147483647] index=#02, mask=0000000000000002 GenTreeNode creates assertion: [001064] ---X-------- * ARR_LENGTH int In BB52 New Local Constant Assertion: V04 != null index=#03, mask=0000000000000004 Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000197] *A-XG------- * IND int [001058] -A-XG+------ \--* ADD byref [001073] -A-XG+------ +--* COMMA byref [001061] -A-XG+------ | +--* ASG int [001060] D----+-N---- | | +--* LCL_VAR int V63 tmp49 [000194] ---XG+------ | | \--* IND int [001075] -----+------ | | \--* ADD byref [000193] -----+------ | | +--* LCL_VAR ref V00 this [001074] -----+------ | | \--* CNS_INT long 60 field offset Fseq[_freeList] [001072] ---XG+------ | \--* COMMA byref [001065] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [001062] -----+------ | | +--* LCL_VAR int V63 tmp49 [001064] ---X-+------ | | \--* ARR_LENGTH int [000192] -----+------ | | \--* LCL_VAR ref V04 loc0 [001078] ----G------- | \--* ADDR byref [000195] a---G+-N---- | \--* IND struct [001071] -----+------ | \--* ADD byref [001059] -----+------ | +--* LCL_VAR ref V04 loc0 [001070] -----+------ | \--* ADD long [001068] -----+------ | +--* LSH long [001077] -----+------ | | +--* MUL long [001066] -----+------ | | | +--* CAST long <- int [001063] i----+------ | | | | \--* LCL_VAR int V63 tmp49 [001076] ------------ | | | \--* CNS_INT long 3 [001067] -----+-N---- | | \--* CNS_INT long 3 [001069] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [001057] -----+------ \--* CNS_INT long 20 field offset Fseq[next] fgMorphTree BB52, STMT00037 (after) [000200] -A-XG+------ * ASG int [000199] ---XG+-N---- +--* IND int [001056] -----+------ | \--* ADD byref [000190] -----+------ | +--* LCL_VAR ref V00 this [001055] -----+------ | \--* CNS_INT long 60 field offset Fseq[_freeList] [000198] -A-XG+------ \--* ADD int [001079] -A-XG+------ +--* NEG int [000197] *A-XG+------ | \--* IND int [001058] -A-XG+------ | \--* ADD byref [001073] -A-XG+------ | +--* COMMA byref [001061] -A-XG+------ | | +--* ASG int [001060] D----+-N---- | | | +--* LCL_VAR int V63 tmp49 [000194] ---XG+------ | | | \--* IND int [001075] -----+------ | | | \--* ADD byref [000193] -----+------ | | | +--* LCL_VAR ref V00 this [001074] -----+------ | | | \--* CNS_INT long 60 field offset Fseq[_freeList] [001072] ---XG+------ | | \--* COMMA byref [001065] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [001062] -----+------ | | | +--* LCL_VAR int V63 tmp49 [001064] ---X-+------ | | | \--* ARR_LENGTH int [000192] -----+------ | | | \--* LCL_VAR ref V04 loc0 [001078] ----G------- | | \--* ADDR byref [000195] a---G+-N---- | | \--* IND struct [001071] -----+------ | | \--* ADD byref [001059] -----+------ | | +--* LCL_VAR ref V04 loc0 [001070] -----+------ | | \--* ADD long [001068] -----+------ | | +--* LSH long [001077] -----+------ | | | +--* MUL long [001066] -----+------ | | | | +--* CAST long <- int [001063] i----+------ | | | | | \--* LCL_VAR int V63 tmp49 [001076] ------------ | | | | \--* CNS_INT long 3 [001067] -----+-N---- | | | \--* CNS_INT long 3 [001069] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [001057] -----+------ | \--* CNS_INT long 20 field offset Fseq[next] [000191] -----+------ \--* CNS_INT int -3 fgMorphTree BB52, STMT00038 (before) [000207] -A-XG------- * ASG int [000206] ---XG--N---- +--* FIELD int _freeCount [000201] ------------ | \--* LCL_VAR ref V00 this [000205] ---XG------- \--* SUB int [000203] ---XG------- +--* FIELD int _freeCount [000202] ------------ | \--* LCL_VAR ref V00 this [000204] ------------ \--* CNS_INT int 1 Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000206] ---XG--N---- * IND int [001081] -----+------ \--* ADD byref [000201] -----+------ +--* LCL_VAR ref V00 this [001080] -----+------ \--* CNS_INT long 64 field offset Fseq[_freeCount] Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000203] ---XG------- * IND int [001083] -----+------ \--* ADD byref [000202] -----+------ +--* LCL_VAR ref V00 this [001082] -----+------ \--* CNS_INT long 64 field offset Fseq[_freeCount] fgMorphTree BB52, STMT00038 (after) [000207] -A-XG+------ * ASG int [000206] ---XG+-N---- +--* IND int [001081] -----+------ | \--* ADD byref [000201] -----+------ | +--* LCL_VAR ref V00 this [001080] -----+------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] [000205] ---XG+------ \--* ADD int [000203] ---XG+------ +--* IND int [001083] -----+------ | \--* ADD byref [000202] -----+------ | +--* LCL_VAR ref V00 this [001082] -----+------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] [000204] -----+------ \--* CNS_INT int -1 Morphing BB54 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB54, STMT00016 (before) [000075] -A-XG------- * ASG int [000074] D------N---- +--* LCL_VAR int V13 loc9 [000073] ---XG------- \--* FIELD int _count [000072] ------------ \--* LCL_VAR ref V00 this Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000073] ---XG------- * IND int [001085] -----+------ \--* ADD byref [000072] -----+------ +--* LCL_VAR ref V00 this [001084] -----+------ \--* CNS_INT long 56 field offset Fseq[_count] GenTreeNode creates assertion: [000073] ---XG------- * IND int In BB54 New Local Constant Assertion: V00 != null index=#01, mask=0000000000000001 GenTreeNode creates assertion: [000075] -A-XG------- * ASG int In BB54 New Local Subrange Assertion: V13 in [-2147483648..2147483647] index=#02, mask=0000000000000002 fgMorphTree BB54, STMT00016 (after) [000075] -A-XG+------ * ASG int [000074] D----+-N---- +--* LCL_VAR int V13 loc9 [000073] ---XG+------ \--* IND int [001085] -----+------ \--* ADD byref [000072] -----+------ +--* LCL_VAR ref V00 this [001084] -----+------ \--* CNS_INT long 56 field offset Fseq[_count] fgMorphTree BB54, STMT00017 (before) [000080] ---X-------- * JTRUE void [000079] N--X-----U-- \--* NE int [000076] ------------ +--* LCL_VAR int V13 loc9 [000078] ---X-------- \--* ARR_LENGTH int [000077] ------------ \--* LCL_VAR ref V04 loc0 GenTreeNode creates assertion: [000078] ---X-------- * ARR_LENGTH int In BB54 New Local Constant Assertion: V04 != null index=#03, mask=0000000000000004 Morphing BB55 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB55, STMT00125 (before) [000705] --C-G------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [000163] ------------ this in rcx +--* LCL_VAR ref V00 this [000702] --CXG------- arg1 +--* CALL int System.Collections.HashHelpers.ExpandPrime [000701] ---XG------- arg0 | \--* FIELD int _count [000700] ------------ | \--* LCL_VAR ref V00 this [000706] ------------ arg2 \--* PUTARG_TYPE bool [000704] ------------ \--* CNS_INT int 0 Initializing arg info for 705.CALL: ArgTable for 705.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 163.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 702.CALL int (By ref), 1 reg: rdx, byteAlignment=8] fgArgTabEntry[arg 2 706.PUTARG_TYPE int (By ref), 1 reg: r8, byteAlignment=8] Morphing args for 705.CALL: Initializing arg info for 702.CALL: ArgTable for 702.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 701.FIELD int (By ref), 1 reg: rcx, byteAlignment=8] Morphing args for 702.CALL: Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000701] ---XG------- * IND int [001087] -----+------ \--* ADD byref [000700] -----+------ +--* LCL_VAR ref V00 this [001086] -----+------ \--* CNS_INT long 56 field offset Fseq[_count] GenTreeNode creates assertion: [000701] ---XG------- * IND int In BB55 New Local Constant Assertion: V00 != null index=#01, mask=0000000000000001 argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000701] ---XG+------ * IND int [001087] -----+------ \--* ADD byref [000700] -----+------ +--* LCL_VAR ref V00 this [001086] -----+------ \--* CNS_INT long 56 field offset Fseq[_count] Replaced with placeholder node: [001088] ----------L- * ARGPLACE int Shuffled argument table: rcx ArgTable for 702.CALL after fgMorphArgs: fgArgTabEntry[arg 0 701.IND int (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] argSlots=3, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Argument with 'side effect'... [000702] --CXG+------ * CALL int System.Collections.HashHelpers.ExpandPrime [000701] ---XG+------ arg0 in rcx \--* IND int [001087] -----+------ \--* ADD byref [000700] -----+------ +--* LCL_VAR ref V00 this [001086] -----+------ \--* CNS_INT long 56 field offset Fseq[_count] lvaGrabTemp returning 64 (V64 tmp50) called for argument with side effect. Evaluate to a temp: [001090] -ACXG-----L- * ASG int [001089] D------N---- +--* LCL_VAR int V64 tmp50 [000702] --CXG+------ \--* CALL int System.Collections.HashHelpers.ExpandPrime [000701] ---XG+------ arg0 in rcx \--* IND int [001087] -----+------ \--* ADD byref [000700] -----+------ +--* LCL_VAR ref V00 this [001086] -----+------ \--* CNS_INT long 56 field offset Fseq[_count] Deferred argument ('rcx'): [000163] -----+------ * LCL_VAR ref V00 this Replaced with placeholder node: [001092] ----------L- * ARGPLACE ref Deferred argument ('r8'): [000704] -----+------ * CNS_INT int 0 Replaced with placeholder node: [001093] ----------L- * ARGPLACE int Shuffled argument table: rdx rcx r8 ArgTable for 705.CALL after fgMorphArgs: fgArgTabEntry[arg 1 1091.LCL_VAR int (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=0, tmpNum=V64, isTmp, processed] fgArgTabEntry[arg 0 163.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=1, processed] fgArgTabEntry[arg 2 704.CNS_INT int (By ref), 1 reg: r8, byteAlignment=8, lateArgInx=2, processed] fgMorphTree BB55, STMT00125 (after) [000705] --CXG+------ * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [001090] -ACXG-----L- arg1 SETUP +--* ASG int [001089] D------N---- | +--* LCL_VAR int V64 tmp50 [000702] --CXG+------ | \--* CALL int System.Collections.HashHelpers.ExpandPrime [000701] ---XG+------ arg0 in rcx | \--* IND int [001087] -----+------ | \--* ADD byref [000700] -----+------ | +--* LCL_VAR ref V00 this [001086] -----+------ | \--* CNS_INT long 56 field offset Fseq[_count] [001091] ------------ arg1 in rdx +--* LCL_VAR int V64 tmp50 [000163] -----+------ this in rcx +--* LCL_VAR ref V00 this [000704] -----+------ arg2 in r8 \--* CNS_INT int 0 fgMorphTree BB55, STMT00126 (before) [000711] -A-XG------- * ASG ref [000710] D------N---- +--* LCL_VAR ref V52 tmp38 [000709] ---XG------- \--* FIELD ref _buckets [000165] ------------ \--* LCL_VAR ref V00 this Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000709] ---XG------- * IND ref [001095] -----+------ \--* ADD byref [000165] -----+------ +--* LCL_VAR ref V00 this [001094] -----+------ \--* CNS_INT long 8 field offset Fseq[_buckets] fgMorphTree BB55, STMT00126 (after) [000711] -A-XG+------ * ASG ref [000710] D----+-N---- +--* LCL_VAR ref V52 tmp38 [000709] ---XG+------ \--* IND ref [001095] -----+------ \--* ADD byref [000165] -----+------ +--* LCL_VAR ref V00 this [001094] -----+------ \--* CNS_INT long 8 field offset Fseq[_buckets] fgMorphTree BB55, STMT00133 (before) [000760] -A-X-------- * ASG int [000759] D------N---- +--* LCL_VAR int V53 tmp39 [000714] ---X-------- \--* ARR_LENGTH int [000713] ------------ \--* LCL_VAR ref V52 tmp38 GenTreeNode creates assertion: [000714] ---X-------- * ARR_LENGTH int In BB55 New Local Constant Assertion: V52 != null index=#02, mask=0000000000000002 fgMorphTree BB55, STMT00134 (before) [000762] -A-XG------- * ASG long [000761] D------N---- +--* LCL_VAR long V54 tmp40 [000716] ---XG------- \--* FIELD long _fastModMultiplier [000715] ------------ \--* LCL_VAR ref V00 this Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000716] ---XG------- * IND long [001097] -----+------ \--* ADD byref [000715] -----+------ +--* LCL_VAR ref V00 this [001096] -----+------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] fgMorphTree BB55, STMT00134 (after) [000762] -A-XG+------ * ASG long [000761] D----+-N---- +--* LCL_VAR long V54 tmp40 [000716] ---XG+------ \--* IND long [001097] -----+------ \--* ADD byref [000715] -----+------ +--* LCL_VAR ref V00 this [001096] -----+------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] fgMorphTree BB55, STMT00136 (before) [000773] -A---------- * ASG bool [000772] D------N---- +--* LCL_VAR bool V56 tmp42 [000764] ------------ \--* CAST int <- bool <- int [000732] ------------ \--* EQ int [000730] N--------U-- +--* GT int [000728] ------------ | +--* LCL_VAR int V53 tmp39 [000729] ------------ | \--* CNS_INT int 0x7FFFFFFF [000731] ------------ \--* CNS_INT int 0 GenTreeNode creates assertion: [000773] -A---------- * ASG bool In BB55 New Local Subrange Assertion: V56 in [0..1] index=#03, mask=0000000000000004 fgMorphTree BB55, STMT00136 (after) [000773] -A---+------ * ASG bool [000772] D----+-N---- +--* LCL_VAR int V56 tmp42 [000730] N----+---U-- \--* LE int [000728] -----+------ +--* LCL_VAR int V53 tmp39 [000729] -----+------ \--* CNS_INT int 0x7FFFFFFF fgMorphTree BB55, STMT00139 (before) [000783] -A--G------- * ASG ref [000782] D------N---- +--* LCL_VAR ref V57 tmp43 [000767] #---G------- \--* IND ref [000766] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] fgMorphTree BB55, STMT00140 (before) [000785] -A--G------- * ASG ref [000784] D------N---- +--* LCL_VAR ref V58 tmp44 [000769] #---G------- \--* IND ref [000768] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] fgMorphTree BB55, STMT00137 (before) [000778] ------------ * JTRUE void [000777] ------------ \--* NE int [000775] ------------ +--* LCL_VAR int V56 tmp42 [000776] ------------ \--* CNS_INT int 0 Morphing BB57 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB57, STMT00138 (before) [000781] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000779] ------------ arg0 +--* LCL_VAR ref V57 tmp43 [000780] ------------ arg1 \--* LCL_VAR ref V58 tmp44 Initializing arg info for 781.CALL: ArgTable for 781.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 779.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 780.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 781.CALL: argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000779] -----+------ * LCL_VAR ref V57 tmp43 Replaced with placeholder node: [001098] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000780] -----+------ * LCL_VAR ref V58 tmp44 Replaced with placeholder node: [001099] ----------L- * ARGPLACE ref Shuffled argument table: rcx rdx ArgTable for 781.CALL after fgMorphArgs: fgArgTabEntry[arg 0 779.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 780.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB57, STMT00138 (after) [000781] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000779] -----+------ arg0 in rcx +--* LCL_VAR ref V57 tmp43 [000780] -----+------ arg1 in rdx \--* LCL_VAR ref V58 tmp44 Morphing BB58 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB58, STMT00131 (before) [000750] -A---------- * ASG int [000749] D------N---- +--* LCL_VAR int V55 tmp41 [000748] ------------ \--* CAST int <- uint <- long [000747] ------------ \--* RSZ long [000745] ------------ +--* MUL long [000742] ------------ | +--* ADD long [000739] ------------ | | +--* RSZ long [000737] ------------ | | | +--* MUL long [000735] ------------ | | | | +--* LCL_VAR long V54 tmp40 [000736] ---------U-- | | | | \--* CAST long <- ulong <- uint [000166] ------------ | | | | \--* LCL_VAR int V06 loc2 [000738] ------------ | | | \--* CNS_INT int 32 [000741] ------------ | | \--* CNS_INT long 1 [000744] ---------U-- | \--* CAST long <- ulong <- uint [000743] ------------ | \--* LCL_VAR int V53 tmp39 [000746] ------------ \--* CNS_INT int 32 GenTreeNode creates assertion: [000750] -A---------- * ASG int In BB58 New Local Subrange Assertion: V55 in [0..-1] index=#01, mask=0000000000000001 fgMorphTree BB58, STMT00142 (before) [000796] -A-X-------- * ASG bool [000795] D------N---- +--* LCL_VAR bool V59 tmp45 [000787] ---X-------- \--* CAST int <- bool <- int [000755] ---X-------- \--* EQ int [000751] ------------ +--* LCL_VAR int V55 tmp41 [000754] ---X-------- \--* UMOD int [000752] ------------ +--* LCL_VAR int V06 loc2 [000753] ------------ \--* LCL_VAR int V53 tmp39 GenTreeNode creates assertion: [000796] -A-X-------- * ASG bool In BB58 New Local Subrange Assertion: V59 in [0..1] index=#02, mask=0000000000000002 fgMorphTree BB58, STMT00142 (after) [000796] -A-X-+------ * ASG bool [000795] D----+-N---- +--* LCL_VAR int V59 tmp45 [000755] ---X-+------ \--* EQ int [000751] -----+------ +--* LCL_VAR int V55 tmp41 [000754] ---X-+------ \--* UMOD int [000752] -----+------ +--* LCL_VAR int V06 loc2 [000753] -----+------ \--* LCL_VAR int V53 tmp39 fgMorphTree BB58, STMT00145 (before) [000806] -A--G------- * ASG ref [000805] D------N---- +--* LCL_VAR ref V60 tmp46 [000790] #---G------- \--* IND ref [000789] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] fgMorphTree BB58, STMT00146 (before) [000808] -A--G------- * ASG ref [000807] D------N---- +--* LCL_VAR ref V61 tmp47 [000792] #---G------- \--* IND ref [000791] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] fgMorphTree BB58, STMT00143 (before) [000801] ------------ * JTRUE void [000800] ------------ \--* NE int [000798] ------------ +--* LCL_VAR int V59 tmp45 [000799] ------------ \--* CNS_INT int 0 Morphing BB61 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB61, STMT00144 (before) [000804] --C-G------- * CALL void System.Diagnostics.Debug.Fail [000802] ------------ arg0 +--* LCL_VAR ref V60 tmp46 [000803] ------------ arg1 \--* LCL_VAR ref V61 tmp47 Initializing arg info for 804.CALL: ArgTable for 804.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 802.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 803.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 804.CALL: argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rcx'): [000802] -----+------ * LCL_VAR ref V60 tmp46 Replaced with placeholder node: [001100] ----------L- * ARGPLACE ref Deferred argument ('rdx'): [000803] -----+------ * LCL_VAR ref V61 tmp47 Replaced with placeholder node: [001101] ----------L- * ARGPLACE ref Shuffled argument table: rcx rdx ArgTable for 804.CALL after fgMorphArgs: fgArgTabEntry[arg 0 802.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 1 803.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB61, STMT00144 (after) [000804] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000802] -----+------ arg0 in rcx +--* LCL_VAR ref V60 tmp46 [000803] -----+------ arg1 in rdx \--* LCL_VAR ref V61 tmp47 Morphing BB62 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB62, STMT00128 (before) [000722] -ACXG------- * ASG byref [000721] D------N---- +--* LCL_VAR byref V51 tmp37 [000720] --CXG------- \--* ADDR byref [000719] --CXG--N---- \--* INDEX int [000712] ------------ +--* LCL_VAR ref V52 tmp38 [000758] ------------ \--* LCL_VAR int V55 tmp41 GenTreeNode creates assertion: [001104] ---X-------- * ARR_LENGTH int In BB62 New Local Constant Assertion: V52 != null index=#01, mask=0000000000000001 fgMorphTree BB62, STMT00128 (after) [000722] -A-XG+------ * ASG byref [000721] D----+-N---- +--* LCL_VAR byref V51 tmp37 [001112] ---XG+------ \--* COMMA byref [001105] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000758] -----+------ | +--* LCL_VAR int V55 tmp41 [001104] ---X-+------ | \--* ARR_LENGTH int [000712] -----+------ | \--* LCL_VAR ref V52 tmp38 [001113] ----G------- \--* ADDR byref [000719] a---G+-N---- \--* IND int [001111] -----+------ \--* ADD byref [001102] -----+------ +--* LCL_VAR ref V52 tmp38 [001110] -----+------ \--* ADD long [001108] -----+------ +--* LSH long [001106] -----+------ | +--* CAST long <- int [001103] i----+------ | | \--* LCL_VAR int V55 tmp41 [001107] -----+-N---- | \--* CNS_INT long 2 [001109] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] fgMorphTree BB62, STMT00129 (before) [000726] -A---------- * ASG ref [000725] D------N---- +--* LCL_VAR ref V52 tmp38 [000724] ------------ \--* CNS_INT ref null The assignment [000726] using V52 removes: Constant Assertion: V52 != null GenTreeNode creates assertion: [000726] -A---------- * ASG ref In BB62 New Local Constant Assertion: V52 == null index=#01, mask=0000000000000001 fgMorphTree BB62, STMT00034 (before) [000170] -AC--------- * ASG byref [000169] D------N---- +--* LCL_VAR byref V08 loc4 [000723] ------------ \--* LCL_VAR byref V51 tmp37 GenTreeNode creates assertion: [000170] -A---------- * ASG byref In BB62 New Local Copy Assertion: V08 == V51 index=#02, mask=0000000000000002 Morphing BB64 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB64, STMT00018 (before) [000083] -A---------- * ASG int [000082] D------N---- +--* LCL_VAR int V10 loc6 [000081] ------------ \--* LCL_VAR int V13 loc9 GenTreeNode creates assertion: [000083] -A---------- * ASG int In BB64 New Local Copy Assertion: V10 == V13 index=#01, mask=0000000000000001 fgMorphTree BB64, STMT00019 (before) [000089] -A-XG------- * ASG int [000088] ---XG--N---- +--* FIELD int _count [000084] ------------ | \--* LCL_VAR ref V00 this [000087] ------------ \--* ADD int [000085] ------------ +--* LCL_VAR int V13 loc9 [000086] ------------ \--* CNS_INT int 1 Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000088] ---XG--N---- * IND int [001115] -----+------ \--* ADD byref [000084] -----+------ +--* LCL_VAR ref V00 this [001114] -----+------ \--* CNS_INT long 56 field offset Fseq[_count] GenTreeNode creates assertion: [000088] ---XG--N---- * IND int In BB64 New Local Constant Assertion: V00 != null index=#02, mask=0000000000000002 fgMorphTree BB64, STMT00019 (after) [000089] -A-XG+------ * ASG int [000088] ---XG+-N---- +--* IND int [001115] -----+------ | \--* ADD byref [000084] -----+------ | +--* LCL_VAR ref V00 this [001114] -----+------ | \--* CNS_INT long 56 field offset Fseq[_count] [000087] -----+------ \--* ADD int [000085] -----+------ +--* LCL_VAR int V13 loc9 [000086] -----+------ \--* CNS_INT int 1 fgMorphTree BB64, STMT00020 (before) [000093] -A-XG------- * ASG ref [000092] D------N---- +--* LCL_VAR ref V04 loc0 [000091] ---XG------- \--* FIELD ref _entries [000090] ------------ \--* LCL_VAR ref V00 this Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000091] ---XG------- * IND ref [001117] -----+------ \--* ADD byref [000090] -----+------ +--* LCL_VAR ref V00 this [001116] -----+------ \--* CNS_INT long 16 field offset Fseq[_entries] fgMorphTree BB64, STMT00020 (after) [000093] -A-XG+------ * ASG ref [000092] D----+-N---- +--* LCL_VAR ref V04 loc0 [000091] ---XG+------ \--* IND ref [001117] -----+------ \--* ADD byref [000090] -----+------ +--* LCL_VAR ref V00 this [001116] -----+------ \--* CNS_INT long 16 field offset Fseq[_entries] Morphing BB65 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB65, STMT00021 (before) [000099] -A-XG------- * ASG byref [000098] D------N---- +--* LCL_VAR byref V11 loc7 [000097] ---XG------- \--* ADDR byref [000096] ---XG--N---- \--* INDEX struct [000094] ------------ +--* LCL_VAR ref V04 loc0 [000095] ------------ \--* LCL_VAR int V10 loc6 GenTreeNode creates assertion: [001120] ---X-------- * ARR_LENGTH int In BB65 New Local Constant Assertion: V04 != null index=#01, mask=0000000000000001 fgMorphTree BB65, STMT00021 (after) [000099] -A-XG+------ * ASG byref [000098] D----+-N---- +--* LCL_VAR byref V11 loc7 [001128] ---XG+------ \--* COMMA byref [001121] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000095] -----+------ | +--* LCL_VAR int V10 loc6 [001120] ---X-+------ | \--* ARR_LENGTH int [000094] -----+------ | \--* LCL_VAR ref V04 loc0 [001131] ----G------- \--* ADDR byref [000096] a---G+-N---- \--* IND struct [001127] -----+------ \--* ADD byref [001118] -----+------ +--* LCL_VAR ref V04 loc0 [001126] -----+------ \--* ADD long [001124] -----+------ +--* LSH long [001130] -----+------ | +--* MUL long [001122] -----+------ | | +--* CAST long <- int [001119] i----+------ | | | \--* LCL_VAR int V10 loc6 [001129] ------------ | | \--* CNS_INT long 3 [001123] -----+-N---- | \--* CNS_INT long 3 [001125] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] fgMorphTree BB65, STMT00022 (before) [000103] -A-XG------- * ASG int [000102] ---XG--N---- +--* FIELD int hashCode [000100] ------------ | \--* LCL_VAR byref V11 loc7 [000101] ------------ \--* LCL_VAR int V06 loc2 Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000102] *--XG--N---- * IND int [001133] -----+------ \--* ADD byref [000100] -----+------ +--* LCL_VAR byref V11 loc7 [001132] -----+------ \--* CNS_INT long 16 field offset Fseq[hashCode] fgMorphTree BB65, STMT00022 (after) [000103] -A-XG+------ * ASG int [000102] *--XG+-N---- +--* IND int [001133] -----+------ | \--* ADD byref [000100] -----+------ | +--* LCL_VAR byref V11 loc7 [001132] -----+------ | \--* CNS_INT long 16 field offset Fseq[hashCode] [000101] -----+------ \--* LCL_VAR int V06 loc2 fgMorphTree BB65, STMT00023 (before) [000110] -A-XG------- * ASG int [000109] ---XG--N---- +--* FIELD int next [000104] ------------ | \--* LCL_VAR byref V11 loc7 [000108] ---XG------- \--* SUB int [000106] *--XG------- +--* IND int [000105] ------------ | \--* LCL_VAR byref V08 loc4 [000107] ------------ \--* CNS_INT int 1 Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000109] *--XG--N---- * IND int [001135] -----+------ \--* ADD byref [000104] -----+------ +--* LCL_VAR byref V11 loc7 [001134] -----+------ \--* CNS_INT long 20 field offset Fseq[next] fgMorphTree BB65, STMT00023 (after) [000110] -A-XG+------ * ASG int [000109] *--XG+-N---- +--* IND int [001135] -----+------ | \--* ADD byref [000104] -----+------ | +--* LCL_VAR byref V11 loc7 [001134] -----+------ | \--* CNS_INT long 20 field offset Fseq[next] [000108] ---XG+------ \--* ADD int [000106] *--XG+------ +--* IND int [000105] -----+------ | \--* LCL_VAR byref V08 loc4 [000107] -----+------ \--* CNS_INT int -1 fgMorphTree BB65, STMT00024 (before) [000114] -A-XG------- * ASG ref [000113] ---XG--N---- +--* FIELD ref key [000111] ------------ | \--* LCL_VAR byref V11 loc7 [000112] ------------ \--* LCL_VAR ref V01 arg1 Before calling fgAddFieldSeqForZeroOffset: [000113] *--XG--N---- * IND ref [000111] ------------ \--* LCL_VAR byref V11 loc7 fgAddFieldSeqForZeroOffset for Fseq[key] addr (Before) [000111] ------------ LCL_VAR byref (After) [000111] ------------ LCL_VAR byref Zero Fseq[key] Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000113] *--XG--N---- * IND ref [000111] -----+------ \--* LCL_VAR byref V11 loc7 Zero Fseq[key] fgMorphTree BB65, STMT00024 (after) [000114] -A-XG+------ * ASG ref [000113] *--XG+-N---- +--* IND ref [000111] -----+------ | \--* LCL_VAR byref V11 loc7 Zero Fseq[key] [000112] -----+------ \--* LCL_VAR ref V01 arg1 fgMorphTree BB65, STMT00025 (before) [000118] -A-XG------- * ASG ref [000117] ---XG--N---- +--* FIELD ref value [000115] ------------ | \--* LCL_VAR byref V11 loc7 [000116] ------------ \--* LCL_VAR ref V02 arg2 Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000117] *--XG--N---- * IND ref [001137] -----+------ \--* ADD byref [000115] -----+------ +--* LCL_VAR byref V11 loc7 [001136] -----+------ \--* CNS_INT long 8 field offset Fseq[value] fgMorphTree BB65, STMT00025 (after) [000118] -A-XG+------ * ASG ref [000117] *--XG+-N---- +--* IND ref [001137] -----+------ | \--* ADD byref [000115] -----+------ | +--* LCL_VAR byref V11 loc7 [001136] -----+------ | \--* CNS_INT long 8 field offset Fseq[value] [000116] -----+------ \--* LCL_VAR ref V02 arg2 fgMorphTree BB65, STMT00026 (before) [000124] -A-XG------- * ASG int [000123] *------N---- +--* IND int [000119] ------------ | \--* LCL_VAR byref V08 loc4 [000122] ------------ \--* ADD int [000120] ------------ +--* LCL_VAR int V10 loc6 [000121] ------------ \--* CNS_INT int 1 fgMorphTree BB65, STMT00027 (before) [000131] -A-XG------- * ASG int [000130] ---XG--N---- +--* FIELD int _version [000125] ------------ | \--* LCL_VAR ref V00 this [000129] ---XG------- \--* ADD int [000127] ---XG------- +--* FIELD int _version [000126] ------------ | \--* LCL_VAR ref V00 this [000128] ------------ \--* CNS_INT int 1 Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000130] ---XG--N---- * IND int [001139] -----+------ \--* ADD byref [000125] -----+------ +--* LCL_VAR ref V00 this [001138] -----+------ \--* CNS_INT long 68 field offset Fseq[_version] GenTreeNode creates assertion: [000130] ---XG--N---- * IND int In BB65 New Local Constant Assertion: V00 != null index=#02, mask=0000000000000002 Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000127] ---XG------- * IND int [001141] -----+------ \--* ADD byref [000126] -----+------ +--* LCL_VAR ref V00 this [001140] -----+------ \--* CNS_INT long 68 field offset Fseq[_version] fgMorphTree BB65, STMT00027 (after) [000131] -A-XG+------ * ASG int [000130] ---XG+-N---- +--* IND int [001139] -----+------ | \--* ADD byref [000125] -----+------ | +--* LCL_VAR ref V00 this [001138] -----+------ | \--* CNS_INT long 68 field offset Fseq[_version] [000129] ---XG+------ \--* ADD int [000127] ---XG+------ +--* IND int [001141] -----+------ | \--* ADD byref [000126] -----+------ | +--* LCL_VAR ref V00 this [001140] -----+------ | \--* CNS_INT long 68 field offset Fseq[_version] [000128] -----+------ \--* CNS_INT int 1 fgMorphTree BB65, STMT00028 (before) [000148] ------------ * JTRUE void [000147] N--------U-- \--* LE int [000145] ------------ +--* LCL_VAR int V07 loc3 [000146] ------------ \--* CNS_INT int 100 Morphing BB67 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB67, STMT00030 (before) [000156] --C-G------- * JTRUE void [000155] --C-G------- \--* EQ int [000153] --C-G------- +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS [000152] H------N---- arg0 | +--* CNS_INT(h) long 0xd1ffab1e class [000151] ------------ arg1 | \--* LCL_VAR ref V05 loc1 [000154] ------------ \--* CNS_INT ref null Initializing arg info for 153.CALL: ArgTable for 153.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 152.CNS_INT long (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 151.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8] Morphing args for 153.CALL: argSlots=2, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rdx'): [000151] -----+------ * LCL_VAR ref V05 loc1 Replaced with placeholder node: [001142] ----------L- * ARGPLACE ref Deferred argument ('rcx'): [000152] H----+-N---- * CNS_INT(h) long 0xd1ffab1e class Replaced with placeholder node: [001143] ----------L- * ARGPLACE long Shuffled argument table: rdx rcx ArgTable for 153.CALL after fgMorphArgs: fgArgTabEntry[arg 1 151.LCL_VAR ref (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 0 152.CNS_INT long (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=1, processed] fgMorphTree BB67, STMT00030 (after) [000156] --C-G+------ * JTRUE void [000155] J-C-G+-N---- \--* EQ int [000153] --C-G+------ +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS [000151] -----+------ arg1 in rdx | +--* LCL_VAR ref V05 loc1 [000152] H----+-N---- arg0 in rcx | \--* CNS_INT(h) long 0xd1ffab1e class [000154] -----+------ \--* CNS_INT ref null Morphing BB68 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB68, STMT00031 (before) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [000157] ------------ this in rcx +--* LCL_VAR ref V00 this [000159] ---X-------- arg1 +--* ARR_LENGTH int [000158] ------------ | \--* LCL_VAR ref V04 loc0 [000162] ------------ arg2 \--* PUTARG_TYPE bool [000160] ------------ \--* CNS_INT int 1 Initializing arg info for 161.CALL: ArgTable for 161.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 157.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8] fgArgTabEntry[arg 1 159.ARR_LENGTH int (By ref), 1 reg: rdx, byteAlignment=8] fgArgTabEntry[arg 2 162.PUTARG_TYPE int (By ref), 1 reg: r8, byteAlignment=8] Morphing args for 161.CALL: GenTreeNode creates assertion: [000159] ---X-------- * ARR_LENGTH int In BB68 New Local Constant Assertion: V04 != null index=#01, mask=0000000000000001 argSlots=3, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rdx'): [000159] ---X-+------ * ARR_LENGTH int [000158] -----+------ \--* LCL_VAR ref V04 loc0 Replaced with placeholder node: [001144] ----------L- * ARGPLACE int Deferred argument ('rcx'): [000157] -----+------ * LCL_VAR ref V00 this Replaced with placeholder node: [001145] ----------L- * ARGPLACE ref Deferred argument ('r8'): [000160] -----+------ * CNS_INT int 1 Replaced with placeholder node: [001146] ----------L- * ARGPLACE int Shuffled argument table: rdx rcx r8 ArgTable for 161.CALL after fgMorphArgs: fgArgTabEntry[arg 1 159.ARR_LENGTH int (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 0 157.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=1, processed] fgArgTabEntry[arg 2 160.CNS_INT int (By ref), 1 reg: r8, byteAlignment=8, lateArgInx=2, processed] fgMorphTree BB68, STMT00031 (after) [000161] --CXG+------ * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [000159] ---X-+------ arg1 in rdx +--* ARR_LENGTH int [000158] -----+------ | \--* LCL_VAR ref V04 loc0 [000157] -----+------ this in rcx +--* LCL_VAR ref V00 this [000160] -----+------ arg2 in r8 \--* CNS_INT int 1 Morphing BB70 of 'System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this' fgMorphTree BB70, STMT00147 (before) [000810] ------------ * RETURN int [000482] ------------ \--* CNS_INT int 1 Expanding top-level qmark in BB14 (before) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB14 [0005] 1 BB12 1 [04B..054)-> BB16 (always) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB14 [04B..054) -> BB16 (always), preds={BB12} succs={BB16} ***** BB14 STMT00079 (IL 0x04B...0x052) [000489] -A-X-+------ * ASG long [000488] D----+-N---- +--* LCL_VAR long V29 tmp15 [000487] #--X-+------ \--* IND long [000486] !----+------ \--* LCL_VAR ref V00 this ***** BB14 STMT00080 (IL ???... ???) [000499] -A---+------ * ASG ref [000498] D----+-N---- +--* LCL_VAR ref V30 tmp16 [000485] -----+------ \--* LCL_VAR ref V01 arg1 ***** BB14 STMT00081 (IL ???... ???) [000517] -AC-G+------ * ASG long [000516] D----+-N---- +--* LCL_VAR long V31 tmp17 [000515] --C-G+------ \--* QMARK long [000505] J----+-N---- if +--* NE int [000501] n----+------ | +--* IND long [000497] -----+------ | | \--* ADD long [000495] #----+------ | | +--* IND long [000494] #----+------ | | | \--* IND long [000493] -----+------ | | | \--* ADD long [000491] -----+------ | | | +--* LCL_VAR long V29 tmp15 [000492] -----+------ | | | \--* CNS_INT long 56 [000496] -----+------ | | \--* CNS_INT long 64 [000504] -----+------ | \--* CNS_INT long 0 [000514] --C-G+?----- if \--* COLON long [000503] --C-G+?----- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000490] -----+?----- arg0 in rcx | +--* LCL_VAR long V29 tmp15 [000502] H----+?----- arg1 in rdx | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000506] n----+?----- then \--* IND long [000507] -----+?----- \--* ADD long [000508] #----+?----- +--* IND long [000509] #----+?----- | \--* IND long [000510] -----+?----- | \--* ADD long [000511] -----+?----- | +--* LCL_VAR long V29 tmp15 [000512] -----+?----- | \--* CNS_INT long 56 [000513] -----+?----- \--* CNS_INT long 64 ***** BB14 STMT00082 (IL ???... ???) [000520] -A---+------ * ASG long [000519] D----+-N---- +--* LCL_VAR long V32 tmp18 [000518] -----+------ \--* LCL_VAR long V31 tmp17 ***** BB14 STMT00083 (IL ???... ???) [000524] -ACXG+------ * ASG int [000523] D----+-N---- +--* LCL_VAR int V15 tmp1 [000522] --CXG+------ \--* CALL ind stub int [000521] -----+------ calli tgt \--* LCL_VAR long V31 tmp17 [000484] -----+------ this in rcx +--* LCL_VAR ref V05 loc1 [000831] -----+------ arg1 in r11 +--* LCL_VAR long V31 tmp17 r11 REG r11 [000500] -----+------ arg2 in rdx \--* LCL_VAR ref V01 arg1 ------------------------------------------------------------------------------------------------------------------- New Basic Block BB72 [0094] created. BB16 previous predecessor was BB14, now is BB72 Setting edge weights for BB14 -> BB72 to [0 .. 3.402823e+38] New Basic Block BB73 [0095] created. New Basic Block BB74 [0096] created. Setting edge weights for BB14 -> BB73 to [0 .. 3.402823e+38] Setting edge weights for BB73 -> BB74 to [0 .. 3.402823e+38] Setting edge weights for BB74 -> BB72 to [0 .. 3.402823e+38] New Basic Block BB75 [0097] created. Setting edge weights for BB73 -> BB75 to [0 .. 3.402823e+38] Setting edge weights for BB75 -> BB72 to [0 .. 3.402823e+38] removing useless STMT00081 (IL ???... ???) [000517] -AC-G+------ * ASG long [000516] D----+-N---- +--* LCL_VAR long V31 tmp17 [000515] --C-G+------ \--* QMARK long [000505] J----+-N---- if +--* EQ int [000501] n----+------ | +--* IND long [000497] -----+------ | | \--* ADD long [000495] #----+------ | | +--* IND long [000494] #----+------ | | | \--* IND long [000493] -----+------ | | | \--* ADD long [000491] -----+------ | | | +--* LCL_VAR long V29 tmp15 [000492] -----+------ | | | \--* CNS_INT long 56 [000496] -----+------ | | \--* CNS_INT long 64 [000504] -----+------ | \--* CNS_INT long 0 [000514] --C-G+?----- if \--* COLON long [000503] --C-G+?----- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000490] -----+?----- arg0 in rcx | +--* LCL_VAR long V29 tmp15 [000502] H----+?----- arg1 in rdx | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000506] n----+?----- then \--* IND long [000507] -----+?----- \--* ADD long [000508] #----+?----- +--* IND long [000509] #----+?----- | \--* IND long [000510] -----+?----- | \--* ADD long [000511] -----+?----- | +--* LCL_VAR long V29 tmp15 [000512] -----+?----- | \--* CNS_INT long 56 [000513] -----+?----- \--* CNS_INT long 64 from BB14 Expanding top-level qmark in BB14 (after) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB14 [0005] 1 BB12 1 [04B..???) i hascall gcsafe BB73 [0095] 1 BB14 1 [???..???)-> BB74 ( cond ) i BB75 [0097] 1 BB73 0.50 [???..???)-> BB72 (always) i BB74 [0096] 1 BB73 0.50 [???..???) i BB72 [0094] 2 BB74,BB75 1 [???..054)-> BB16 (always) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB14 [04B..???), preds={BB12} succs={BB73} ***** BB14 STMT00079 (IL 0x04B...0x052) [000489] -A-X-+------ * ASG long [000488] D----+-N---- +--* LCL_VAR long V29 tmp15 [000487] #--X-+------ \--* IND long [000486] !----+------ \--* LCL_VAR ref V00 this ***** BB14 STMT00080 (IL ???... ???) [000499] -A---+------ * ASG ref [000498] D----+-N---- +--* LCL_VAR ref V30 tmp16 [000485] -----+------ \--* LCL_VAR ref V01 arg1 ------------ BB73 [???..???) -> BB74 (cond), preds={BB14} succs={BB75,BB74} ***** BB73 STMT00149 (IL ???... ???) [001148] ------------ * JTRUE void [000505] J----+-N---- \--* EQ int [000501] n----+------ +--* IND long [000497] -----+------ | \--* ADD long [000495] #----+------ | +--* IND long [000494] #----+------ | | \--* IND long [000493] -----+------ | | \--* ADD long [000491] -----+------ | | +--* LCL_VAR long V29 tmp15 [000492] -----+------ | | \--* CNS_INT long 56 [000496] -----+------ | \--* CNS_INT long 64 [000504] -----+------ \--* CNS_INT long 0 ------------ BB75 [???..???) -> BB72 (always), preds={BB73} succs={BB72} ***** BB75 STMT00150 (IL ???... ???) [001150] -A---------- * ASG long [001149] D------N---- +--* LCL_VAR long V31 tmp17 [000506] n----+?----- \--* IND long [000507] -----+?----- \--* ADD long [000508] #----+?----- +--* IND long [000509] #----+?----- | \--* IND long [000510] -----+?----- | \--* ADD long [000511] -----+?----- | +--* LCL_VAR long V29 tmp15 [000512] -----+?----- | \--* CNS_INT long 56 [000513] -----+?----- \--* CNS_INT long 64 ------------ BB74 [???..???), preds={BB73} succs={BB72} ***** BB74 STMT00151 (IL ???... ???) [001152] -AC-G------- * ASG long [001151] D------N---- +--* LCL_VAR long V31 tmp17 [000503] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000490] -----+?----- arg0 in rcx +--* LCL_VAR long V29 tmp15 [000502] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB72 [???..054) -> BB16 (always), preds={BB74,BB75} succs={BB16} ***** BB72 STMT00082 (IL ???... ???) [000520] -A---+------ * ASG long [000519] D----+-N---- +--* LCL_VAR long V32 tmp18 [000518] -----+------ \--* LCL_VAR long V31 tmp17 ***** BB72 STMT00083 (IL ???... ???) [000524] -ACXG+------ * ASG int [000523] D----+-N---- +--* LCL_VAR int V15 tmp1 [000522] --CXG+------ \--* CALL ind stub int [000521] -----+------ calli tgt \--* LCL_VAR long V31 tmp17 [000484] -----+------ this in rcx +--* LCL_VAR ref V05 loc1 [000831] -----+------ arg1 in r11 +--* LCL_VAR long V31 tmp17 r11 REG r11 [000500] -----+------ arg2 in rdx \--* LCL_VAR ref V01 arg1 ------------------------------------------------------------------------------------------------------------------- Expanding top-level qmark in BB25 (before) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB25 [0008] 1 BB23 1 [07A..106) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB25 [07A..106), preds={BB23} succs={BB27} ***** BB25 STMT00059 (IL 0x0FF...0x104) [000356] -A-X-+------ * ASG long [000355] D----+-N---- +--* LCL_VAR long V24 tmp10 [000354] #--X-+------ \--* IND long [000353] !----+------ \--* LCL_VAR ref V00 this ***** BB25 STMT00060 (IL ???... ???) [000381] -AC-G+------ * ASG long [000380] D----+-N---- +--* LCL_VAR long V25 tmp11 [000379] --C-G+------ \--* QMARK long [000369] J----+-N---- if +--* NE int [000365] n----+------ | +--* IND long [000364] -----+------ | | \--* ADD long [000362] #----+------ | | +--* IND long [000361] #----+------ | | | \--* IND long [000360] -----+------ | | | \--* ADD long [000358] -----+------ | | | +--* LCL_VAR long V24 tmp10 [000359] -----+------ | | | \--* CNS_INT long 56 [000363] -----+------ | | \--* CNS_INT long 32 [000368] -----+------ | \--* CNS_INT long 0 [000378] --C-G+?----- if \--* COLON long [000367] --C-G+?----- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000357] -----+?----- arg0 in rcx | +--* LCL_VAR long V24 tmp10 [000366] H----+?----- arg1 in rdx | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000370] n----+?----- then \--* IND long [000371] -----+?----- \--* ADD long [000372] #----+?----- +--* IND long [000373] #----+?----- | \--* IND long [000374] -----+?----- | \--* ADD long [000375] -----+?----- | +--* LCL_VAR long V24 tmp10 [000376] -----+?----- | \--* CNS_INT long 56 [000377] -----+?----- \--* CNS_INT long 32 ***** BB25 STMT00062 (IL ???... ???) [000386] -ACXG+------ * ASG ref [000385] D----+-N---- +--* LCL_VAR ref V12 loc8 [000352] --CXG+------ \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default [000382] -----+------ arg0 in rcx \--* LCL_VAR long V25 tmp11 ------------------------------------------------------------------------------------------------------------------- New Basic Block BB76 [0098] created. BB27 previous predecessor was BB25, now is BB76 Setting edge weights for BB25 -> BB76 to [0 .. 3.402823e+38] New Basic Block BB77 [0099] created. New Basic Block BB78 [0100] created. Setting edge weights for BB25 -> BB77 to [0 .. 3.402823e+38] Setting edge weights for BB77 -> BB78 to [0 .. 3.402823e+38] Setting edge weights for BB78 -> BB76 to [0 .. 3.402823e+38] New Basic Block BB79 [0101] created. Setting edge weights for BB77 -> BB79 to [0 .. 3.402823e+38] Setting edge weights for BB79 -> BB76 to [0 .. 3.402823e+38] removing useless STMT00060 (IL ???... ???) [000381] -AC-G+------ * ASG long [000380] D----+-N---- +--* LCL_VAR long V25 tmp11 [000379] --C-G+------ \--* QMARK long [000369] J----+-N---- if +--* EQ int [000365] n----+------ | +--* IND long [000364] -----+------ | | \--* ADD long [000362] #----+------ | | +--* IND long [000361] #----+------ | | | \--* IND long [000360] -----+------ | | | \--* ADD long [000358] -----+------ | | | +--* LCL_VAR long V24 tmp10 [000359] -----+------ | | | \--* CNS_INT long 56 [000363] -----+------ | | \--* CNS_INT long 32 [000368] -----+------ | \--* CNS_INT long 0 [000378] --C-G+?----- if \--* COLON long [000367] --C-G+?----- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000357] -----+?----- arg0 in rcx | +--* LCL_VAR long V24 tmp10 [000366] H----+?----- arg1 in rdx | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000370] n----+?----- then \--* IND long [000371] -----+?----- \--* ADD long [000372] #----+?----- +--* IND long [000373] #----+?----- | \--* IND long [000374] -----+?----- | \--* ADD long [000375] -----+?----- | +--* LCL_VAR long V24 tmp10 [000376] -----+?----- | \--* CNS_INT long 56 [000377] -----+?----- \--* CNS_INT long 32 from BB25 Expanding top-level qmark in BB25 (after) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB25 [0008] 1 BB23 1 [07A..???) i hascall gcsafe BB77 [0099] 1 BB25 1 [???..???)-> BB78 ( cond ) i BB79 [0101] 1 BB77 0.50 [???..???)-> BB76 (always) i BB78 [0100] 1 BB77 0.50 [???..???) i BB76 [0098] 2 BB78,BB79 1 [???..106) i hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB25 [07A..???), preds={BB23} succs={BB77} ***** BB25 STMT00059 (IL 0x0FF...0x104) [000356] -A-X-+------ * ASG long [000355] D----+-N---- +--* LCL_VAR long V24 tmp10 [000354] #--X-+------ \--* IND long [000353] !----+------ \--* LCL_VAR ref V00 this ------------ BB77 [???..???) -> BB78 (cond), preds={BB25} succs={BB79,BB78} ***** BB77 STMT00152 (IL ???... ???) [001153] ------------ * JTRUE void [000369] J----+-N---- \--* EQ int [000365] n----+------ +--* IND long [000364] -----+------ | \--* ADD long [000362] #----+------ | +--* IND long [000361] #----+------ | | \--* IND long [000360] -----+------ | | \--* ADD long [000358] -----+------ | | +--* LCL_VAR long V24 tmp10 [000359] -----+------ | | \--* CNS_INT long 56 [000363] -----+------ | \--* CNS_INT long 32 [000368] -----+------ \--* CNS_INT long 0 ------------ BB79 [???..???) -> BB76 (always), preds={BB77} succs={BB76} ***** BB79 STMT00153 (IL ???... ???) [001155] -A---------- * ASG long [001154] D------N---- +--* LCL_VAR long V25 tmp11 [000370] n----+?----- \--* IND long [000371] -----+?----- \--* ADD long [000372] #----+?----- +--* IND long [000373] #----+?----- | \--* IND long [000374] -----+?----- | \--* ADD long [000375] -----+?----- | +--* LCL_VAR long V24 tmp10 [000376] -----+?----- | \--* CNS_INT long 56 [000377] -----+?----- \--* CNS_INT long 32 ------------ BB78 [???..???), preds={BB77} succs={BB76} ***** BB78 STMT00154 (IL ???... ???) [001157] -AC-G------- * ASG long [001156] D------N---- +--* LCL_VAR long V25 tmp11 [000367] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000357] -----+?----- arg0 in rcx +--* LCL_VAR long V24 tmp10 [000366] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB76 [???..106), preds={BB78,BB79} succs={BB27} ***** BB76 STMT00062 (IL ???... ???) [000386] -ACXG+------ * ASG ref [000385] D----+-N---- +--* LCL_VAR ref V12 loc8 [000352] --CXG+------ \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default [000382] -----+------ arg0 in rcx \--* LCL_VAR long V25 tmp11 ------------------------------------------------------------------------------------------------------------------- Expanding top-level qmark in BB33 (before) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB33 [0026] 1 BB32 0 [14F..157) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB33 [14F..157) (throw), preds={BB32} succs={} ***** BB33 STMT00073 (IL 0x14F...0x150) [000444] -A-X-+------ * ASG long [000443] D----+-N---- +--* LCL_VAR long V26 tmp12 [000442] #--X-+------ \--* IND long [000441] !----+------ \--* LCL_VAR ref V00 this ***** BB33 STMT00074 (IL ???... ???) [000454] -A---+------ * ASG ref [000453] D----+-N---- +--* LCL_VAR ref V27 tmp13 [000439] -----+------ \--* LCL_VAR ref V01 arg1 ***** BB33 STMT00075 (IL ???... ???) [000472] -AC-G+------ * ASG long [000471] D----+-N---- +--* LCL_VAR long V28 tmp14 [000470] --C-G+------ \--* QMARK long [000460] J----+-N---- if +--* NE int [000456] n----+------ | +--* IND long [000452] -----+------ | | \--* ADD long [000450] #----+------ | | +--* IND long [000449] #----+------ | | | \--* IND long [000448] -----+------ | | | \--* ADD long [000446] -----+------ | | | +--* LCL_VAR long V26 tmp12 [000447] -----+------ | | | \--* CNS_INT long 56 [000451] -----+------ | | \--* CNS_INT long 56 [000459] -----+------ | \--* CNS_INT long 0 [000469] --C-G+?----- if \--* COLON long [000458] --C-G+?----- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000445] -----+?----- arg0 in rcx | +--* LCL_VAR long V26 tmp12 [000457] H----+?----- arg1 in rdx | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000461] n----+?----- then \--* IND long [000462] -----+?----- \--* ADD long [000463] #----+?----- +--* IND long [000464] #----+?----- | \--* IND long [000465] -----+?----- | \--* ADD long [000466] -----+?----- | +--* LCL_VAR long V26 tmp12 [000467] -----+?----- | \--* CNS_INT long 56 [000468] -----+?----- \--* CNS_INT long 56 ***** BB33 STMT00076 (IL ???... ???) [000440] --CXG+------ * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000473] -----+------ arg0 in rcx +--* LCL_VAR long V28 tmp14 [000455] -----+------ arg1 in rdx \--* LCL_VAR ref V01 arg1 ------------------------------------------------------------------------------------------------------------------- New Basic Block BB80 [0102] created. Setting edge weights for BB33 -> BB80 to [0 .. 3.402823e+38] New Basic Block BB81 [0103] created. New Basic Block BB82 [0104] created. Setting edge weights for BB33 -> BB81 to [0 .. 3.402823e+38] Setting edge weights for BB81 -> BB82 to [0 .. 3.402823e+38] Setting edge weights for BB82 -> BB80 to [0 .. 3.402823e+38] New Basic Block BB83 [0105] created. Setting edge weights for BB81 -> BB83 to [0 .. 3.402823e+38] Setting edge weights for BB83 -> BB80 to [0 .. 3.402823e+38] removing useless STMT00075 (IL ???... ???) [000472] -AC-G+------ * ASG long [000471] D----+-N---- +--* LCL_VAR long V28 tmp14 [000470] --C-G+------ \--* QMARK long [000460] J----+-N---- if +--* EQ int [000456] n----+------ | +--* IND long [000452] -----+------ | | \--* ADD long [000450] #----+------ | | +--* IND long [000449] #----+------ | | | \--* IND long [000448] -----+------ | | | \--* ADD long [000446] -----+------ | | | +--* LCL_VAR long V26 tmp12 [000447] -----+------ | | | \--* CNS_INT long 56 [000451] -----+------ | | \--* CNS_INT long 56 [000459] -----+------ | \--* CNS_INT long 0 [000469] --C-G+?----- if \--* COLON long [000458] --C-G+?----- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000445] -----+?----- arg0 in rcx | +--* LCL_VAR long V26 tmp12 [000457] H----+?----- arg1 in rdx | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000461] n----+?----- then \--* IND long [000462] -----+?----- \--* ADD long [000463] #----+?----- +--* IND long [000464] #----+?----- | \--* IND long [000465] -----+?----- | \--* ADD long [000466] -----+?----- | +--* LCL_VAR long V26 tmp12 [000467] -----+?----- | \--* CNS_INT long 56 [000468] -----+?----- \--* CNS_INT long 56 from BB33 Expanding top-level qmark in BB33 (after) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB33 [0026] 1 BB32 0 [14F..???) i rare hascall gcsafe bwd BB81 [0103] 1 BB33 0 [???..???)-> BB82 ( cond ) i rare BB83 [0105] 1 BB81 0 [???..???)-> BB80 (always) i rare BB82 [0104] 1 BB81 0 [???..???) i rare BB80 [0102] 2 BB82,BB83 0 [???..157) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB33 [14F..???), preds={BB32} succs={BB81} ***** BB33 STMT00073 (IL 0x14F...0x150) [000444] -A-X-+------ * ASG long [000443] D----+-N---- +--* LCL_VAR long V26 tmp12 [000442] #--X-+------ \--* IND long [000441] !----+------ \--* LCL_VAR ref V00 this ***** BB33 STMT00074 (IL ???... ???) [000454] -A---+------ * ASG ref [000453] D----+-N---- +--* LCL_VAR ref V27 tmp13 [000439] -----+------ \--* LCL_VAR ref V01 arg1 ------------ BB81 [???..???) -> BB82 (cond), preds={BB33} succs={BB83,BB82} ***** BB81 STMT00155 (IL ???... ???) [001158] ------------ * JTRUE void [000460] J----+-N---- \--* EQ int [000456] n----+------ +--* IND long [000452] -----+------ | \--* ADD long [000450] #----+------ | +--* IND long [000449] #----+------ | | \--* IND long [000448] -----+------ | | \--* ADD long [000446] -----+------ | | +--* LCL_VAR long V26 tmp12 [000447] -----+------ | | \--* CNS_INT long 56 [000451] -----+------ | \--* CNS_INT long 56 [000459] -----+------ \--* CNS_INT long 0 ------------ BB83 [???..???) -> BB80 (always), preds={BB81} succs={BB80} ***** BB83 STMT00156 (IL ???... ???) [001160] -A---------- * ASG long [001159] D------N---- +--* LCL_VAR long V28 tmp14 [000461] n----+?----- \--* IND long [000462] -----+?----- \--* ADD long [000463] #----+?----- +--* IND long [000464] #----+?----- | \--* IND long [000465] -----+?----- | \--* ADD long [000466] -----+?----- | +--* LCL_VAR long V26 tmp12 [000467] -----+?----- | \--* CNS_INT long 56 [000468] -----+?----- \--* CNS_INT long 56 ------------ BB82 [???..???), preds={BB81} succs={BB80} ***** BB82 STMT00157 (IL ???... ???) [001162] -AC-G------- * ASG long [001161] D------N---- +--* LCL_VAR long V28 tmp14 [000458] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000445] -----+?----- arg0 in rcx +--* LCL_VAR long V26 tmp12 [000457] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB80 [???..157) (throw), preds={BB82,BB83} succs={} ***** BB80 STMT00076 (IL ???... ???) [000440] --CXG+------ * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000473] -----+------ arg0 in rcx +--* LCL_VAR long V28 tmp14 [000455] -----+------ arg1 in rdx \--* LCL_VAR ref V01 arg1 ------------------------------------------------------------------------------------------------------------------- Expanding top-level qmark in BB39 (before) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB39 [0032] 1 BB38 1 [18E..1A4)-> BB46 ( cond ) i hascall gcsafe idxlen bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB39 [18E..1A4) -> BB46 (cond), preds={BB38} succs={BB40,BB46} ***** BB39 STMT00045 (IL 0x18E...0x1A2) [000246] -A-XG+------ * ASG ref [000245] D----+-N---- +--* LCL_VAR ref V17 tmp3 [000973] ---XG+------ \--* COMMA ref [000966] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000236] -----+------ | +--* LCL_VAR int V09 loc5 [000965] ---X-+------ | \--* ARR_LENGTH int [000235] -----+------ | \--* LCL_VAR ref V04 loc0 [000977] *---G+------ \--* IND ref [000976] ----G------- \--* ADDR byref Zero Fseq[key] [000237] a---G+-N---- \--* IND struct [000972] -----+------ \--* ADD byref [000963] -----+------ +--* LCL_VAR ref V04 loc0 [000971] -----+------ \--* ADD long [000969] -----+------ +--* LSH long [000975] -----+------ | +--* MUL long [000967] -----+------ | | +--* CAST long <- int [000964] i----+------ | | | \--* LCL_VAR int V09 loc5 [000974] ------------ | | \--* CNS_INT long 3 [000968] -----+-N---- | \--* CNS_INT long 3 [000970] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB39 STMT00044 (IL 0x18E... ???) [000244] -A-X-+------ * ASG long [000243] D----+-N---- +--* LCL_VAR long V16 tmp2 [000242] #--X-+------ \--* IND long [000241] !----+------ \--* LCL_VAR ref V00 this ***** BB39 STMT00046 (IL ???... ???) [000257] -A---+------ * ASG ref [000256] D----+-N---- +--* LCL_VAR ref V18 tmp4 [000240] -----+------ \--* LCL_VAR ref V01 arg1 ***** BB39 STMT00047 (IL ???... ???) [000275] -AC-G+------ * ASG long [000274] D----+-N---- +--* LCL_VAR long V19 tmp5 [000273] --C-G+------ \--* QMARK long [000263] J----+-N---- if +--* NE int [000259] n----+------ | +--* IND long [000255] -----+------ | | \--* ADD long [000253] #----+------ | | +--* IND long [000252] #----+------ | | | \--* IND long [000251] -----+------ | | | \--* ADD long [000249] -----+------ | | | +--* LCL_VAR long V16 tmp2 [000250] -----+------ | | | \--* CNS_INT long 56 [000254] -----+------ | | \--* CNS_INT long 48 [000262] -----+------ | \--* CNS_INT long 0 [000272] --C-G+?----- if \--* COLON long [000261] --C-G+?----- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000248] -----+?----- arg0 in rcx | +--* LCL_VAR long V16 tmp2 [000260] H----+?----- arg1 in rdx | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000264] n----+?----- then \--* IND long [000265] -----+?----- \--* ADD long [000266] #----+?----- +--* IND long [000267] #----+?----- | \--* IND long [000268] -----+?----- | \--* ADD long [000269] -----+?----- | +--* LCL_VAR long V16 tmp2 [000270] -----+?----- | \--* CNS_INT long 56 [000271] -----+?----- \--* CNS_INT long 48 ***** BB39 STMT00048 (IL ???... ???) [000278] -A---+------ * ASG long [000277] D----+-N---- +--* LCL_VAR long V20 tmp6 [000276] -----+------ \--* LCL_VAR long V19 tmp5 ***** BB39 STMT00049 (IL ???... ???) [000283] --CXG+------ * JTRUE void [000282] J-CXG+-N---- \--* EQ int [000280] --CXG+------ +--* CALL ind stub int [000279] -----+------ calli tgt | \--* LCL_VAR long V19 tmp5 [000234] -----+------ this in rcx | +--* LCL_VAR ref V05 loc1 [000980] -----+------ arg1 in r11 | +--* LCL_VAR long V19 tmp5 r11 REG r11 [000247] -----+------ arg2 in rdx | +--* LCL_VAR ref V17 tmp3 [000258] -----+------ arg3 in r8 | \--* LCL_VAR ref V01 arg1 [000281] -----+------ \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- New Basic Block BB84 [0106] created. BB40 previous predecessor was BB39, now is BB84 BB46 previous predecessor was BB39, now is BB84 Setting edge weights for BB39 -> BB84 to [0 .. 3.402823e+38] New Basic Block BB85 [0107] created. New Basic Block BB86 [0108] created. Setting edge weights for BB39 -> BB85 to [0 .. 3.402823e+38] Setting edge weights for BB85 -> BB86 to [0 .. 3.402823e+38] Setting edge weights for BB86 -> BB84 to [0 .. 3.402823e+38] New Basic Block BB87 [0109] created. Setting edge weights for BB85 -> BB87 to [0 .. 3.402823e+38] Setting edge weights for BB87 -> BB84 to [0 .. 3.402823e+38] removing useless STMT00047 (IL ???... ???) [000275] -AC-G+------ * ASG long [000274] D----+-N---- +--* LCL_VAR long V19 tmp5 [000273] --C-G+------ \--* QMARK long [000263] J----+-N---- if +--* EQ int [000259] n----+------ | +--* IND long [000255] -----+------ | | \--* ADD long [000253] #----+------ | | +--* IND long [000252] #----+------ | | | \--* IND long [000251] -----+------ | | | \--* ADD long [000249] -----+------ | | | +--* LCL_VAR long V16 tmp2 [000250] -----+------ | | | \--* CNS_INT long 56 [000254] -----+------ | | \--* CNS_INT long 48 [000262] -----+------ | \--* CNS_INT long 0 [000272] --C-G+?----- if \--* COLON long [000261] --C-G+?----- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000248] -----+?----- arg0 in rcx | +--* LCL_VAR long V16 tmp2 [000260] H----+?----- arg1 in rdx | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000264] n----+?----- then \--* IND long [000265] -----+?----- \--* ADD long [000266] #----+?----- +--* IND long [000267] #----+?----- | \--* IND long [000268] -----+?----- | \--* ADD long [000269] -----+?----- | +--* LCL_VAR long V16 tmp2 [000270] -----+?----- | \--* CNS_INT long 56 [000271] -----+?----- \--* CNS_INT long 48 from BB39 Expanding top-level qmark in BB39 (after) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB39 [0032] 1 BB38 1 [18E..???) i hascall gcsafe idxlen bwd BB85 [0107] 1 BB39 1 [???..???)-> BB86 ( cond ) i BB87 [0109] 1 BB85 0.50 [???..???)-> BB84 (always) i BB86 [0108] 1 BB85 0.50 [???..???) i BB84 [0106] 2 BB86,BB87 1 [???..1A4)-> BB46 ( cond ) i hascall gcsafe idxlen bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB39 [18E..???), preds={BB38} succs={BB85} ***** BB39 STMT00045 (IL 0x18E...0x1A2) [000246] -A-XG+------ * ASG ref [000245] D----+-N---- +--* LCL_VAR ref V17 tmp3 [000973] ---XG+------ \--* COMMA ref [000966] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000236] -----+------ | +--* LCL_VAR int V09 loc5 [000965] ---X-+------ | \--* ARR_LENGTH int [000235] -----+------ | \--* LCL_VAR ref V04 loc0 [000977] *---G+------ \--* IND ref [000976] ----G------- \--* ADDR byref Zero Fseq[key] [000237] a---G+-N---- \--* IND struct [000972] -----+------ \--* ADD byref [000963] -----+------ +--* LCL_VAR ref V04 loc0 [000971] -----+------ \--* ADD long [000969] -----+------ +--* LSH long [000975] -----+------ | +--* MUL long [000967] -----+------ | | +--* CAST long <- int [000964] i----+------ | | | \--* LCL_VAR int V09 loc5 [000974] ------------ | | \--* CNS_INT long 3 [000968] -----+-N---- | \--* CNS_INT long 3 [000970] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB39 STMT00044 (IL 0x18E... ???) [000244] -A-X-+------ * ASG long [000243] D----+-N---- +--* LCL_VAR long V16 tmp2 [000242] #--X-+------ \--* IND long [000241] !----+------ \--* LCL_VAR ref V00 this ***** BB39 STMT00046 (IL ???... ???) [000257] -A---+------ * ASG ref [000256] D----+-N---- +--* LCL_VAR ref V18 tmp4 [000240] -----+------ \--* LCL_VAR ref V01 arg1 ------------ BB85 [???..???) -> BB86 (cond), preds={BB39} succs={BB87,BB86} ***** BB85 STMT00158 (IL ???... ???) [001163] ------------ * JTRUE void [000263] J----+-N---- \--* EQ int [000259] n----+------ +--* IND long [000255] -----+------ | \--* ADD long [000253] #----+------ | +--* IND long [000252] #----+------ | | \--* IND long [000251] -----+------ | | \--* ADD long [000249] -----+------ | | +--* LCL_VAR long V16 tmp2 [000250] -----+------ | | \--* CNS_INT long 56 [000254] -----+------ | \--* CNS_INT long 48 [000262] -----+------ \--* CNS_INT long 0 ------------ BB87 [???..???) -> BB84 (always), preds={BB85} succs={BB84} ***** BB87 STMT00159 (IL ???... ???) [001165] -A---------- * ASG long [001164] D------N---- +--* LCL_VAR long V19 tmp5 [000264] n----+?----- \--* IND long [000265] -----+?----- \--* ADD long [000266] #----+?----- +--* IND long [000267] #----+?----- | \--* IND long [000268] -----+?----- | \--* ADD long [000269] -----+?----- | +--* LCL_VAR long V16 tmp2 [000270] -----+?----- | \--* CNS_INT long 56 [000271] -----+?----- \--* CNS_INT long 48 ------------ BB86 [???..???), preds={BB85} succs={BB84} ***** BB86 STMT00160 (IL ???... ???) [001167] -AC-G------- * ASG long [001166] D------N---- +--* LCL_VAR long V19 tmp5 [000261] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000248] -----+?----- arg0 in rcx +--* LCL_VAR long V16 tmp2 [000260] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB84 [???..1A4) -> BB46 (cond), preds={BB86,BB87} succs={BB40,BB46} ***** BB84 STMT00048 (IL ???... ???) [000278] -A---+------ * ASG long [000277] D----+-N---- +--* LCL_VAR long V20 tmp6 [000276] -----+------ \--* LCL_VAR long V19 tmp5 ***** BB84 STMT00049 (IL ???... ???) [000283] --CXG+------ * JTRUE void [000282] J-CXG+-N---- \--* EQ int [000280] --CXG+------ +--* CALL ind stub int [000279] -----+------ calli tgt | \--* LCL_VAR long V19 tmp5 [000234] -----+------ this in rcx | +--* LCL_VAR ref V05 loc1 [000980] -----+------ arg1 in r11 | +--* LCL_VAR long V19 tmp5 r11 REG r11 [000247] -----+------ arg2 in rdx | +--* LCL_VAR ref V17 tmp3 [000258] -----+------ arg3 in r8 | \--* LCL_VAR ref V01 arg1 [000281] -----+------ \--* CNS_INT int 0 ------------------------------------------------------------------------------------------------------------------- Expanding top-level qmark in BB43 (before) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB43 [0036] 1 BB42 0 [1BC..1C4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB43 [1BC..1C4) (throw), preds={BB42} succs={} ***** BB43 STMT00053 (IL 0x1BC...0x1BD) [000299] -A-X-+------ * ASG long [000298] D----+-N---- +--* LCL_VAR long V21 tmp7 [000297] #--X-+------ \--* IND long [000296] !----+------ \--* LCL_VAR ref V00 this ***** BB43 STMT00054 (IL ???... ???) [000309] -A---+------ * ASG ref [000308] D----+-N---- +--* LCL_VAR ref V22 tmp8 [000294] -----+------ \--* LCL_VAR ref V01 arg1 ***** BB43 STMT00055 (IL ???... ???) [000327] -AC-G+------ * ASG long [000326] D----+-N---- +--* LCL_VAR long V23 tmp9 [000325] --C-G+------ \--* QMARK long [000315] J----+-N---- if +--* NE int [000311] n----+------ | +--* IND long [000307] -----+------ | | \--* ADD long [000305] #----+------ | | +--* IND long [000304] #----+------ | | | \--* IND long [000303] -----+------ | | | \--* ADD long [000301] -----+------ | | | +--* LCL_VAR long V21 tmp7 [000302] -----+------ | | | \--* CNS_INT long 56 [000306] -----+------ | | \--* CNS_INT long 56 [000314] -----+------ | \--* CNS_INT long 0 [000324] --C-G+?----- if \--* COLON long [000313] --C-G+?----- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000300] -----+?----- arg0 in rcx | +--* LCL_VAR long V21 tmp7 [000312] H----+?----- arg1 in rdx | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000316] n----+?----- then \--* IND long [000317] -----+?----- \--* ADD long [000318] #----+?----- +--* IND long [000319] #----+?----- | \--* IND long [000320] -----+?----- | \--* ADD long [000321] -----+?----- | +--* LCL_VAR long V21 tmp7 [000322] -----+?----- | \--* CNS_INT long 56 [000323] -----+?----- \--* CNS_INT long 56 ***** BB43 STMT00056 (IL ???... ???) [000295] --CXG+------ * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000328] -----+------ arg0 in rcx +--* LCL_VAR long V23 tmp9 [000310] -----+------ arg1 in rdx \--* LCL_VAR ref V01 arg1 ------------------------------------------------------------------------------------------------------------------- New Basic Block BB88 [0110] created. Setting edge weights for BB43 -> BB88 to [0 .. 3.402823e+38] New Basic Block BB89 [0111] created. New Basic Block BB90 [0112] created. Setting edge weights for BB43 -> BB89 to [0 .. 3.402823e+38] Setting edge weights for BB89 -> BB90 to [0 .. 3.402823e+38] Setting edge weights for BB90 -> BB88 to [0 .. 3.402823e+38] New Basic Block BB91 [0113] created. Setting edge weights for BB89 -> BB91 to [0 .. 3.402823e+38] Setting edge weights for BB91 -> BB88 to [0 .. 3.402823e+38] removing useless STMT00055 (IL ???... ???) [000327] -AC-G+------ * ASG long [000326] D----+-N---- +--* LCL_VAR long V23 tmp9 [000325] --C-G+------ \--* QMARK long [000315] J----+-N---- if +--* EQ int [000311] n----+------ | +--* IND long [000307] -----+------ | | \--* ADD long [000305] #----+------ | | +--* IND long [000304] #----+------ | | | \--* IND long [000303] -----+------ | | | \--* ADD long [000301] -----+------ | | | +--* LCL_VAR long V21 tmp7 [000302] -----+------ | | | \--* CNS_INT long 56 [000306] -----+------ | | \--* CNS_INT long 56 [000314] -----+------ | \--* CNS_INT long 0 [000324] --C-G+?----- if \--* COLON long [000313] --C-G+?----- else +--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000300] -----+?----- arg0 in rcx | +--* LCL_VAR long V21 tmp7 [000312] H----+?----- arg1 in rdx | \--* CNS_INT(h) long 0xd1ffab1e global ptr [000316] n----+?----- then \--* IND long [000317] -----+?----- \--* ADD long [000318] #----+?----- +--* IND long [000319] #----+?----- | \--* IND long [000320] -----+?----- | \--* ADD long [000321] -----+?----- | +--* LCL_VAR long V21 tmp7 [000322] -----+?----- | \--* CNS_INT long 56 [000323] -----+?----- \--* CNS_INT long 56 from BB43 Expanding top-level qmark in BB43 (after) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB43 [0036] 1 BB42 0 [1BC..???) i rare hascall gcsafe bwd BB89 [0111] 1 BB43 0 [???..???)-> BB90 ( cond ) i rare BB91 [0113] 1 BB89 0 [???..???)-> BB88 (always) i rare BB90 [0112] 1 BB89 0 [???..???) i rare BB88 [0110] 2 BB90,BB91 0 [???..1C4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB43 [1BC..???), preds={BB42} succs={BB89} ***** BB43 STMT00053 (IL 0x1BC...0x1BD) [000299] -A-X-+------ * ASG long [000298] D----+-N---- +--* LCL_VAR long V21 tmp7 [000297] #--X-+------ \--* IND long [000296] !----+------ \--* LCL_VAR ref V00 this ***** BB43 STMT00054 (IL ???... ???) [000309] -A---+------ * ASG ref [000308] D----+-N---- +--* LCL_VAR ref V22 tmp8 [000294] -----+------ \--* LCL_VAR ref V01 arg1 ------------ BB89 [???..???) -> BB90 (cond), preds={BB43} succs={BB91,BB90} ***** BB89 STMT00161 (IL ???... ???) [001168] ------------ * JTRUE void [000315] J----+-N---- \--* EQ int [000311] n----+------ +--* IND long [000307] -----+------ | \--* ADD long [000305] #----+------ | +--* IND long [000304] #----+------ | | \--* IND long [000303] -----+------ | | \--* ADD long [000301] -----+------ | | +--* LCL_VAR long V21 tmp7 [000302] -----+------ | | \--* CNS_INT long 56 [000306] -----+------ | \--* CNS_INT long 56 [000314] -----+------ \--* CNS_INT long 0 ------------ BB91 [???..???) -> BB88 (always), preds={BB89} succs={BB88} ***** BB91 STMT00162 (IL ???... ???) [001170] -A---------- * ASG long [001169] D------N---- +--* LCL_VAR long V23 tmp9 [000316] n----+?----- \--* IND long [000317] -----+?----- \--* ADD long [000318] #----+?----- +--* IND long [000319] #----+?----- | \--* IND long [000320] -----+?----- | \--* ADD long [000321] -----+?----- | +--* LCL_VAR long V21 tmp7 [000322] -----+?----- | \--* CNS_INT long 56 [000323] -----+?----- \--* CNS_INT long 56 ------------ BB90 [???..???), preds={BB89} succs={BB88} ***** BB90 STMT00163 (IL ???... ???) [001172] -AC-G------- * ASG long [001171] D------N---- +--* LCL_VAR long V23 tmp9 [000313] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000300] -----+?----- arg0 in rcx +--* LCL_VAR long V21 tmp7 [000312] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB88 [???..1C4) (throw), preds={BB90,BB91} succs={} ***** BB88 STMT00056 (IL ???... ???) [000295] --CXG+------ * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000328] -----+------ arg0 in rcx +--* LCL_VAR long V23 tmp9 [000310] -----+------ arg1 in rdx \--* LCL_VAR ref V01 arg1 ------------------------------------------------------------------------------------------------------------------- *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB03 [0002] 1 BB01 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i hascall gcsafe BB05 [0004] 2 BB03,BB04 1 [01E..04B)-> BB08 ( cond ) i BB07 [0052] 1 BB05 1 [01E..01F) i hascall gcsafe BB08 [0053] 2 BB05,BB07 1 [01E..034)-> BB12 ( cond ) i BB11 [0057] 1 BB08 1 [033..034) i hascall gcsafe BB12 [0058] 2 BB08,BB11 1 [033..034)-> BB15 ( cond ) i BB14 [0005] 1 BB12 1 [04B..???) i hascall gcsafe BB73 [0095] 1 BB14 1 [???..???)-> BB74 ( cond ) i BB75 [0097] 1 BB73 0.50 [???..???)-> BB72 (always) i BB74 [0096] 1 BB73 0.50 [???..???) i BB72 [0094] 2 BB74,BB75 1 [???..054)-> BB16 (always) i hascall gcsafe BB15 [0006] 1 BB12 1 [054..061) i hascall gcsafe BB16 [0007] 2 BB15,BB72 1 [061..07A)-> BB19 ( cond ) i idxlen BB18 [0064] 1 BB16 1 [064..065) i hascall gcsafe BB19 [0065] 2 BB16,BB18 1 [064..065)-> BB23 ( cond ) i idxlen BB22 [0069] 1 BB19 1 [064..065) i hascall gcsafe BB23 [0070] 2 BB19,BB22 1 [064..065)-> BB37 ( cond ) i idxlen BB25 [0008] 1 BB23 1 [07A..???) i hascall gcsafe BB77 [0099] 1 BB25 1 [???..???)-> BB78 ( cond ) i BB79 [0101] 1 BB77 0.50 [???..???)-> BB76 (always) i BB78 [0100] 1 BB77 0.50 [???..???) i BB76 [0098] 2 BB78,BB79 1 [???..106) i hascall gcsafe BB27 [0020] 2 BB35,BB76 1 [106..110)-> BB48 ( cond ) i idxlen bwd bwd-target BB28 [0021] 1 BB27 1 [110..120)-> BB35 ( cond ) i idxlen bwd BB29 [0022] 1 BB28 1 [120..137)-> BB35 ( cond ) i hascall gcsafe idxlen bwd BB30 [0023] 1 BB29 1 [137..13B)-> BB32 ( cond ) i bwd BB31 [0024] 1 BB30 1 [13B..14B)-> BB70 (always) i idxlen BB32 [0025] 1 BB30 1 [14B..14F)-> BB45 ( cond ) i bwd BB33 [0026] 1 BB32 0 [14F..???) i rare hascall gcsafe bwd BB81 [0103] 1 BB33 0 [???..???)-> BB82 ( cond ) i rare BB83 [0105] 1 BB81 0 [???..???)-> BB80 (always) i rare BB82 [0104] 1 BB81 0 [???..???) i rare BB80 [0102] 2 BB82,BB83 0 [???..157) (throw ) i rare hascall gcsafe bwd BB35 [0028] 2 BB28,BB29 1 [157..170)-> BB27 ( cond ) i idxlen bwd BB71 [0093] 1 BB35 1 [???..???)-> BB47 (always) internal BB37 [0030] 2 BB23,BB46 1 [177..17E)-> BB48 ( cond ) i idxlen bwd bwd-target BB38 [0031] 1 BB37 1 [17E..18E)-> BB46 ( cond ) i idxlen bwd BB39 [0032] 1 BB38 1 [18E..???) i hascall gcsafe idxlen bwd BB85 [0107] 1 BB39 1 [???..???)-> BB86 ( cond ) i BB87 [0109] 1 BB85 0.50 [???..???)-> BB84 (always) i BB86 [0108] 1 BB85 0.50 [???..???) i BB84 [0106] 2 BB86,BB87 1 [???..1A4)-> BB46 ( cond ) i hascall gcsafe idxlen bwd BB40 [0033] 1 BB84 1 [1A4..1A8)-> BB42 ( cond ) i bwd BB41 [0034] 1 BB40 1 [1A8..1B8)-> BB70 (always) i idxlen BB42 [0035] 1 BB40 1 [1B8..1BC)-> BB45 ( cond ) i bwd BB43 [0036] 1 BB42 0 [1BC..???) i rare hascall gcsafe bwd BB89 [0111] 1 BB43 0 [???..???)-> BB90 ( cond ) i rare BB91 [0113] 1 BB89 0 [???..???)-> BB88 (always) i rare BB90 [0112] 1 BB89 0 [???..???) i rare BB88 [0110] 2 BB90,BB91 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB45 [0092] 2 BB32,BB42 1 [???..???) (return) internal BB46 [0038] 2 BB38,BB84 1 [1C4..1DD)-> BB37 ( cond ) i idxlen bwd BB47 [0039] 2 BB46,BB71 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd BB48 [0040] 2 BB27,BB37 1 [1E4..1ED)-> BB54 ( cond ) i BB49 [0041] 1 BB48 1 [1ED..243)-> BB52 ( cond ) i idxlen BB51 [0075] 1 BB49 1 [1F5..1F6) i hascall gcsafe BB52 [0076] 2 BB49,BB51 1 [1F5..1F6)-> BB65 (always) i idxlen BB54 [0042] 1 BB48 1 [243..252)-> BB64 ( cond ) i idxlen BB55 [0043] 1 BB54 1 [252..261)-> BB58 ( cond ) i hascall gcsafe idxlen BB57 [0083] 1 BB55 1 [258..259) i hascall gcsafe BB58 [0084] 2 BB55,BB57 1 [258..259)-> BB62 ( cond ) i idxlen BB61 [0088] 1 BB58 1 [258..259) i hascall gcsafe BB62 [0089] 2 BB58,BB61 1 [258..259) i idxlen BB64 [0044] 2 BB54,BB62 1 [261..276) i BB65 [0045] 2 BB52,BB64 1 [276..2CF)-> BB70 ( cond ) i idxlen BB67 [0047] 1 BB65 1 [2CF..2D7)-> BB70 ( cond ) i hascall BB68 [0048] 1 BB67 1 [2D7..2E3) i hascall gcsafe idxlen BB70 [0091] 5 BB31,BB41,BB65,BB67,BB68 1 [???..???) (return) internal ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB07 to BB06 Renumber BB08 to BB07 Renumber BB11 to BB08 Renumber BB12 to BB09 Renumber BB14 to BB10 Renumber BB73 to BB11 Renumber BB75 to BB12 Renumber BB74 to BB13 Renumber BB72 to BB14 Renumber BB18 to BB17 Renumber BB19 to BB18 Renumber BB22 to BB19 Renumber BB23 to BB20 Renumber BB25 to BB21 Renumber BB77 to BB22 Renumber BB79 to BB23 Renumber BB78 to BB24 Renumber BB76 to BB25 Renumber BB27 to BB26 Renumber BB28 to BB27 Renumber BB29 to BB28 Renumber BB30 to BB29 Renumber BB31 to BB30 Renumber BB32 to BB31 Renumber BB33 to BB32 Renumber BB81 to BB33 Renumber BB83 to BB34 Renumber BB82 to BB35 Renumber BB80 to BB36 Renumber BB35 to BB37 Renumber BB71 to BB38 Renumber BB37 to BB39 Renumber BB38 to BB40 Renumber BB39 to BB41 Renumber BB85 to BB42 Renumber BB87 to BB43 Renumber BB86 to BB44 Renumber BB84 to BB45 Renumber BB40 to BB46 Renumber BB41 to BB47 Renumber BB42 to BB48 Renumber BB43 to BB49 Renumber BB89 to BB50 Renumber BB91 to BB51 Renumber BB90 to BB52 Renumber BB88 to BB53 Renumber BB45 to BB54 Renumber BB46 to BB55 Renumber BB47 to BB56 Renumber BB48 to BB57 Renumber BB49 to BB58 Renumber BB51 to BB59 Renumber BB52 to BB60 Renumber BB54 to BB61 Renumber BB55 to BB62 Renumber BB57 to BB63 Renumber BB58 to BB64 Renumber BB61 to BB65 Renumber BB62 to BB66 Renumber BB64 to BB67 Renumber BB65 to BB68 Renumber BB67 to BB69 Renumber BB68 to BB70 Renumber BB70 to BB71 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB03 [0002] 1 BB01 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i hascall gcsafe BB05 [0004] 2 BB03,BB04 1 [01E..04B)-> BB07 ( cond ) i BB06 [0052] 1 BB05 1 [01E..01F) i hascall gcsafe BB07 [0053] 2 BB05,BB06 1 [01E..034)-> BB09 ( cond ) i BB08 [0057] 1 BB07 1 [033..034) i hascall gcsafe BB09 [0058] 2 BB07,BB08 1 [033..034)-> BB15 ( cond ) i BB10 [0005] 1 BB09 1 [04B..???) i hascall gcsafe BB11 [0095] 1 BB10 1 [???..???)-> BB13 ( cond ) i BB12 [0097] 1 BB11 0.50 [???..???)-> BB14 (always) i BB13 [0096] 1 BB11 0.50 [???..???) i BB14 [0094] 2 BB12,BB13 1 [???..054)-> BB16 (always) i hascall gcsafe BB15 [0006] 1 BB09 1 [054..061) i hascall gcsafe BB16 [0007] 2 BB14,BB15 1 [061..07A)-> BB18 ( cond ) i idxlen BB17 [0064] 1 BB16 1 [064..065) i hascall gcsafe BB18 [0065] 2 BB16,BB17 1 [064..065)-> BB20 ( cond ) i idxlen BB19 [0069] 1 BB18 1 [064..065) i hascall gcsafe BB20 [0070] 2 BB18,BB19 1 [064..065)-> BB39 ( cond ) i idxlen BB21 [0008] 1 BB20 1 [07A..???) i hascall gcsafe BB22 [0099] 1 BB21 1 [???..???)-> BB24 ( cond ) i BB23 [0101] 1 BB22 0.50 [???..???)-> BB25 (always) i BB24 [0100] 1 BB22 0.50 [???..???) i BB25 [0098] 2 BB23,BB24 1 [???..106) i hascall gcsafe BB26 [0020] 2 BB25,BB37 1 [106..110)-> BB57 ( cond ) i idxlen bwd bwd-target BB27 [0021] 1 BB26 1 [110..120)-> BB37 ( cond ) i idxlen bwd BB28 [0022] 1 BB27 1 [120..137)-> BB37 ( cond ) i hascall gcsafe idxlen bwd BB29 [0023] 1 BB28 1 [137..13B)-> BB31 ( cond ) i bwd BB30 [0024] 1 BB29 1 [13B..14B)-> BB71 (always) i idxlen BB31 [0025] 1 BB29 1 [14B..14F)-> BB54 ( cond ) i bwd BB32 [0026] 1 BB31 0 [14F..???) i rare hascall gcsafe bwd BB33 [0103] 1 BB32 0 [???..???)-> BB35 ( cond ) i rare BB34 [0105] 1 BB33 0 [???..???)-> BB36 (always) i rare BB35 [0104] 1 BB33 0 [???..???) i rare BB36 [0102] 2 BB34,BB35 0 [???..157) (throw ) i rare hascall gcsafe bwd BB37 [0028] 2 BB27,BB28 1 [157..170)-> BB26 ( cond ) i idxlen bwd BB38 [0093] 1 BB37 1 [???..???)-> BB56 (always) internal BB39 [0030] 2 BB20,BB55 1 [177..17E)-> BB57 ( cond ) i idxlen bwd bwd-target BB40 [0031] 1 BB39 1 [17E..18E)-> BB55 ( cond ) i idxlen bwd BB41 [0032] 1 BB40 1 [18E..???) i hascall gcsafe idxlen bwd BB42 [0107] 1 BB41 1 [???..???)-> BB44 ( cond ) i BB43 [0109] 1 BB42 0.50 [???..???)-> BB45 (always) i BB44 [0108] 1 BB42 0.50 [???..???) i BB45 [0106] 2 BB43,BB44 1 [???..1A4)-> BB55 ( cond ) i hascall gcsafe idxlen bwd BB46 [0033] 1 BB45 1 [1A4..1A8)-> BB48 ( cond ) i bwd BB47 [0034] 1 BB46 1 [1A8..1B8)-> BB71 (always) i idxlen BB48 [0035] 1 BB46 1 [1B8..1BC)-> BB54 ( cond ) i bwd BB49 [0036] 1 BB48 0 [1BC..???) i rare hascall gcsafe bwd BB50 [0111] 1 BB49 0 [???..???)-> BB52 ( cond ) i rare BB51 [0113] 1 BB50 0 [???..???)-> BB53 (always) i rare BB52 [0112] 1 BB50 0 [???..???) i rare BB53 [0110] 2 BB51,BB52 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB54 [0092] 2 BB31,BB48 1 [???..???) (return) internal BB55 [0038] 2 BB40,BB45 1 [1C4..1DD)-> BB39 ( cond ) i idxlen bwd BB56 [0039] 2 BB38,BB55 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd BB57 [0040] 2 BB26,BB39 1 [1E4..1ED)-> BB61 ( cond ) i BB58 [0041] 1 BB57 1 [1ED..243)-> BB60 ( cond ) i idxlen BB59 [0075] 1 BB58 1 [1F5..1F6) i hascall gcsafe BB60 [0076] 2 BB58,BB59 1 [1F5..1F6)-> BB68 (always) i idxlen BB61 [0042] 1 BB57 1 [243..252)-> BB67 ( cond ) i idxlen BB62 [0043] 1 BB61 1 [252..261)-> BB64 ( cond ) i hascall gcsafe idxlen BB63 [0083] 1 BB62 1 [258..259) i hascall gcsafe BB64 [0084] 2 BB62,BB63 1 [258..259)-> BB66 ( cond ) i idxlen BB65 [0088] 1 BB64 1 [258..259) i hascall gcsafe BB66 [0089] 2 BB64,BB65 1 [258..259) i idxlen BB67 [0044] 2 BB61,BB66 1 [261..276) i BB68 [0045] 2 BB60,BB67 1 [276..2CF)-> BB71 ( cond ) i idxlen BB69 [0047] 1 BB68 1 [2CF..2D7)-> BB71 ( cond ) i hascall BB70 [0048] 1 BB69 1 [2D7..2E3) i hascall gcsafe idxlen BB71 [0091] 5 BB30,BB47,BB68,BB69,BB70 1 [???..???) (return) internal ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 4, # of blocks (including unused BB00): 72, bitset array size: 2 (long) *************** Finishing PHASE Morph - Global Trees after Morph - Global ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB03 [0002] 1 BB01 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i hascall gcsafe BB05 [0004] 2 BB03,BB04 1 [01E..04B)-> BB07 ( cond ) i BB06 [0052] 1 BB05 1 [01E..01F) i hascall gcsafe BB07 [0053] 2 BB05,BB06 1 [01E..034)-> BB09 ( cond ) i BB08 [0057] 1 BB07 1 [033..034) i hascall gcsafe BB09 [0058] 2 BB07,BB08 1 [033..034)-> BB15 ( cond ) i BB10 [0005] 1 BB09 1 [04B..???) i hascall gcsafe BB11 [0095] 1 BB10 1 [???..???)-> BB13 ( cond ) i BB12 [0097] 1 BB11 0.50 [???..???)-> BB14 (always) i BB13 [0096] 1 BB11 0.50 [???..???) i BB14 [0094] 2 BB12,BB13 1 [???..054)-> BB16 (always) i hascall gcsafe BB15 [0006] 1 BB09 1 [054..061) i hascall gcsafe BB16 [0007] 2 BB14,BB15 1 [061..07A)-> BB18 ( cond ) i idxlen BB17 [0064] 1 BB16 1 [064..065) i hascall gcsafe BB18 [0065] 2 BB16,BB17 1 [064..065)-> BB20 ( cond ) i idxlen BB19 [0069] 1 BB18 1 [064..065) i hascall gcsafe BB20 [0070] 2 BB18,BB19 1 [064..065)-> BB39 ( cond ) i idxlen BB21 [0008] 1 BB20 1 [07A..???) i hascall gcsafe BB22 [0099] 1 BB21 1 [???..???)-> BB24 ( cond ) i BB23 [0101] 1 BB22 0.50 [???..???)-> BB25 (always) i BB24 [0100] 1 BB22 0.50 [???..???) i BB25 [0098] 2 BB23,BB24 1 [???..106) i hascall gcsafe BB26 [0020] 2 BB25,BB37 1 [106..110)-> BB57 ( cond ) i idxlen bwd bwd-target BB27 [0021] 1 BB26 1 [110..120)-> BB37 ( cond ) i idxlen bwd BB28 [0022] 1 BB27 1 [120..137)-> BB37 ( cond ) i hascall gcsafe idxlen bwd BB29 [0023] 1 BB28 1 [137..13B)-> BB31 ( cond ) i bwd BB30 [0024] 1 BB29 1 [13B..14B)-> BB71 (always) i idxlen BB31 [0025] 1 BB29 1 [14B..14F)-> BB54 ( cond ) i bwd BB32 [0026] 1 BB31 0 [14F..???) i rare hascall gcsafe bwd BB33 [0103] 1 BB32 0 [???..???)-> BB35 ( cond ) i rare BB34 [0105] 1 BB33 0 [???..???)-> BB36 (always) i rare BB35 [0104] 1 BB33 0 [???..???) i rare BB36 [0102] 2 BB34,BB35 0 [???..157) (throw ) i rare hascall gcsafe bwd BB37 [0028] 2 BB27,BB28 1 [157..170)-> BB26 ( cond ) i idxlen bwd BB38 [0093] 1 BB37 1 [???..???)-> BB56 (always) internal BB39 [0030] 2 BB20,BB55 1 [177..17E)-> BB57 ( cond ) i idxlen bwd bwd-target BB40 [0031] 1 BB39 1 [17E..18E)-> BB55 ( cond ) i idxlen bwd BB41 [0032] 1 BB40 1 [18E..???) i hascall gcsafe idxlen bwd BB42 [0107] 1 BB41 1 [???..???)-> BB44 ( cond ) i BB43 [0109] 1 BB42 0.50 [???..???)-> BB45 (always) i BB44 [0108] 1 BB42 0.50 [???..???) i BB45 [0106] 2 BB43,BB44 1 [???..1A4)-> BB55 ( cond ) i hascall gcsafe idxlen bwd BB46 [0033] 1 BB45 1 [1A4..1A8)-> BB48 ( cond ) i bwd BB47 [0034] 1 BB46 1 [1A8..1B8)-> BB71 (always) i idxlen BB48 [0035] 1 BB46 1 [1B8..1BC)-> BB54 ( cond ) i bwd BB49 [0036] 1 BB48 0 [1BC..???) i rare hascall gcsafe bwd BB50 [0111] 1 BB49 0 [???..???)-> BB52 ( cond ) i rare BB51 [0113] 1 BB50 0 [???..???)-> BB53 (always) i rare BB52 [0112] 1 BB50 0 [???..???) i rare BB53 [0110] 2 BB51,BB52 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB54 [0092] 2 BB31,BB48 1 [???..???) (return) internal BB55 [0038] 2 BB40,BB45 1 [1C4..1DD)-> BB39 ( cond ) i idxlen bwd BB56 [0039] 2 BB38,BB55 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd BB57 [0040] 2 BB26,BB39 1 [1E4..1ED)-> BB61 ( cond ) i BB58 [0041] 1 BB57 1 [1ED..243)-> BB60 ( cond ) i idxlen BB59 [0075] 1 BB58 1 [1F5..1F6) i hascall gcsafe BB60 [0076] 2 BB58,BB59 1 [1F5..1F6)-> BB68 (always) i idxlen BB61 [0042] 1 BB57 1 [243..252)-> BB67 ( cond ) i idxlen BB62 [0043] 1 BB61 1 [252..261)-> BB64 ( cond ) i hascall gcsafe idxlen BB63 [0083] 1 BB62 1 [258..259) i hascall gcsafe BB64 [0084] 2 BB62,BB63 1 [258..259)-> BB66 ( cond ) i idxlen BB65 [0088] 1 BB64 1 [258..259) i hascall gcsafe BB66 [0089] 2 BB64,BB65 1 [258..259) i idxlen BB67 [0044] 2 BB61,BB66 1 [261..276) i BB68 [0045] 2 BB60,BB67 1 [276..2CF)-> BB71 ( cond ) i idxlen BB69 [0047] 1 BB68 1 [2CF..2D7)-> BB71 ( cond ) i hascall BB70 [0048] 1 BB69 1 [2D7..2E3) i hascall gcsafe idxlen BB71 [0091] 5 BB30,BB47,BB68,BB69,BB70 1 [???..???) (return) internal ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 (IL 0x000...0x006) [000003] -----+------ * JTRUE void [000002] J----+-N---- \--* NE int [000000] -----+------ +--* LCL_VAR ref V01 arg1 [000001] -----+------ \--* CNS_INT ref null ------------ BB02 [008..00E) (throw), preds={BB01} succs={} ***** BB02 STMT00086 (IL 0x008...0x009) [000533] --CXG+------ * CALL void System.ThrowHelper.ThrowArgumentNullException [000532] -----+------ arg0 in rcx \--* CNS_INT int 4 ------------ BB03 [00E..016) -> BB05 (cond), preds={BB01} succs={BB04,BB05} ***** BB03 STMT00001 (IL 0x00E...0x014) [000008] ---XG+------ * JTRUE void [000007] J--XG+-N---- \--* NE int [000005] ---XG+------ +--* IND ref [000814] -----+------ | \--* ADD byref [000004] -----+------ | +--* LCL_VAR ref V00 this [000813] -----+------ | \--* CNS_INT long 8 field offset Fseq[_buckets] [000006] -----+------ \--* CNS_INT ref null ------------ BB04 [016..01E), preds={BB03} succs={BB05} ***** BB04 STMT00085 (IL ???... ???) [000528] --CXG+------ * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize [000526] -----+------ this in rcx +--* LCL_VAR ref V00 this [000527] -----+------ arg1 in rdx \--* CNS_INT int 0 ------------ BB05 [01E..04B) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07} ***** BB05 STMT00088 (IL 0x01E... ???) [000544] -A-XG+------ * ASG bool [000543] D----+-N---- +--* LCL_VAR int V33 tmp19 [000012] N--XG+------ \--* NE int [000010] ---XG+------ +--* IND ref [000818] -----+------ | \--* ADD byref [000009] -----+------ | +--* LCL_VAR ref V00 this [000817] -----+------ | \--* CNS_INT long 8 field offset Fseq[_buckets] [000011] -----+------ \--* CNS_INT ref null ***** BB05 STMT00091 (IL 0x01E... ???) [000554] -A--G+------ * ASG ref [000553] D----+-N---- +--* LCL_VAR ref V34 tmp20 [000538] #---G+------ \--* IND ref [000537] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB05 STMT00092 (IL 0x01E... ???) [000556] -A--G+------ * ASG ref [000555] D----+-N---- +--* LCL_VAR ref V35 tmp21 [000540] #---G+------ \--* IND ref [000539] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB05 STMT00089 (IL 0x01E... ???) [000549] -----+------ * JTRUE void [000548] J----+-N---- \--* NE int [000546] -----+------ +--* LCL_VAR int V33 tmp19 [000547] -----+------ \--* CNS_INT int 0 ------------ BB06 [01E..01F), preds={BB05} succs={BB07} ***** BB06 STMT00090 (IL 0x01E... ???) [000552] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000550] -----+------ arg0 in rcx +--* LCL_VAR ref V34 tmp20 [000551] -----+------ arg1 in rdx \--* LCL_VAR ref V35 tmp21 ------------ BB07 [01E..034) -> BB09 (cond), preds={BB05,BB06} succs={BB08,BB09} ***** BB07 STMT00003 (IL 0x02C... ???) [000018] -A-XG+------ * ASG ref [000017] D----+-N---- +--* LCL_VAR ref V04 loc0 [000016] ---XG+------ \--* IND ref [000822] -----+------ \--* ADD byref [000015] -----+------ +--* LCL_VAR ref V00 this [000821] -----+------ \--* CNS_INT long 16 field offset Fseq[_entries] ***** BB07 STMT00094 (IL 0x033... ???) [000566] -A---+------ * ASG bool [000565] D----+-N---- +--* LCL_VAR int V36 tmp22 [000021] N----+------ \--* NE int [000019] -----+------ +--* LCL_VAR ref V04 loc0 [000020] -----+------ \--* CNS_INT ref null ***** BB07 STMT00097 (IL 0x033... ???) [000576] -A--G+------ * ASG ref [000575] D----+-N---- +--* LCL_VAR ref V37 tmp23 [000562] #---G+------ \--* IND ref [000561] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB07 STMT00095 (IL 0x033... ???) [000571] -----+------ * JTRUE void [000570] J----+-N---- \--* NE int [000568] -----+------ +--* LCL_VAR int V36 tmp22 [000569] -----+------ \--* CNS_INT int 0 ------------ BB08 [033..034), preds={BB07} succs={BB09} ***** BB08 STMT00096 (IL 0x033... ???) [000574] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000824] #---G+------ arg0 in rcx +--* IND ref [000823] H----+------ | \--* CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" [000573] -----+------ arg1 in rdx \--* LCL_VAR ref V37 tmp23 ------------ BB09 [033..034) -> BB15 (cond), preds={BB07,BB08} succs={BB10,BB15} ***** BB09 STMT00005 (IL 0x041... ???) [000028] -A-XG+------ * ASG ref [000027] D----+-N---- +--* LCL_VAR ref V05 loc1 [000026] ---XG+------ \--* IND ref [000828] -----+------ \--* ADD byref [000025] -----+------ +--* LCL_VAR ref V00 this [000827] -----+------ \--* CNS_INT long 24 field offset Fseq[_comparer] ***** BB09 STMT00006 (IL 0x048...0x049) [000032] -----+------ * JTRUE void [000031] J----+-N---- \--* EQ int [000029] -----+------ +--* LCL_VAR ref V05 loc1 [000030] -----+------ \--* CNS_INT ref null ------------ BB10 [04B..???), preds={BB09} succs={BB11} ***** BB10 STMT00079 (IL 0x04B...0x052) [000489] -A-X-+------ * ASG long [000488] D----+-N---- +--* LCL_VAR long V29 tmp15 [000487] #--X-+------ \--* IND long [000486] !----+------ \--* LCL_VAR ref V00 this ***** BB10 STMT00080 (IL ???... ???) [000499] -A---+------ * ASG ref [000498] D----+-N---- +--* LCL_VAR ref V30 tmp16 [000485] -----+------ \--* LCL_VAR ref V01 arg1 ------------ BB11 [???..???) -> BB13 (cond), preds={BB10} succs={BB12,BB13} ***** BB11 STMT00149 (IL ???... ???) [001148] ------------ * JTRUE void [000505] J----+-N---- \--* EQ int [000501] n----+------ +--* IND long [000497] -----+------ | \--* ADD long [000495] #----+------ | +--* IND long [000494] #----+------ | | \--* IND long [000493] -----+------ | | \--* ADD long [000491] -----+------ | | +--* LCL_VAR long V29 tmp15 [000492] -----+------ | | \--* CNS_INT long 56 [000496] -----+------ | \--* CNS_INT long 64 [000504] -----+------ \--* CNS_INT long 0 ------------ BB12 [???..???) -> BB14 (always), preds={BB11} succs={BB14} ***** BB12 STMT00150 (IL ???... ???) [001150] -A---------- * ASG long [001149] D------N---- +--* LCL_VAR long V31 tmp17 [000506] n----+?----- \--* IND long [000507] -----+?----- \--* ADD long [000508] #----+?----- +--* IND long [000509] #----+?----- | \--* IND long [000510] -----+?----- | \--* ADD long [000511] -----+?----- | +--* LCL_VAR long V29 tmp15 [000512] -----+?----- | \--* CNS_INT long 56 [000513] -----+?----- \--* CNS_INT long 64 ------------ BB13 [???..???), preds={BB11} succs={BB14} ***** BB13 STMT00151 (IL ???... ???) [001152] -AC-G------- * ASG long [001151] D------N---- +--* LCL_VAR long V31 tmp17 [000503] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000490] -----+?----- arg0 in rcx +--* LCL_VAR long V29 tmp15 [000502] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB14 [???..054) -> BB16 (always), preds={BB12,BB13} succs={BB16} ***** BB14 STMT00082 (IL ???... ???) [000520] -A---+------ * ASG long [000519] D----+-N---- +--* LCL_VAR long V32 tmp18 [000518] -----+------ \--* LCL_VAR long V31 tmp17 ***** BB14 STMT00083 (IL ???... ???) [000524] -ACXG+------ * ASG int [000523] D----+-N---- +--* LCL_VAR int V15 tmp1 [000522] --CXG+------ \--* CALL ind stub int [000521] -----+------ calli tgt \--* LCL_VAR long V31 tmp17 [000484] -----+------ this in rcx +--* LCL_VAR ref V05 loc1 [000831] -----+------ arg1 in r11 +--* LCL_VAR long V31 tmp17 r11 REG r11 [000500] -----+------ arg2 in rdx \--* LCL_VAR ref V01 arg1 ------------ BB15 [054..061), preds={BB09} succs={BB16} ***** BB15 STMT00007 (IL 0x054...0x05C) [000038] -ACXG+------ * ASG int [000037] D----+-N---- +--* LCL_VAR int V15 tmp1 [000035] --CXG+------ \--* CALLV vt-ind int System.Object.GetHashCode [000843] n--X-+------ control expr \--* IND long [000842] ---X-+------ \--* ADD long [000840] #--X-+------ +--* IND long [000839] ---X-+------ | \--* ADD long [000837] #--X-+------ | +--* IND long [000836] -----+------ | | \--* LCL_VAR ref V01 arg1 [000838] -----+------ | \--* CNS_INT int 72 [000841] -----+------ \--* CNS_INT int 24 [000033] -----+------ this in rcx \--* LCL_VAR ref V01 arg1 ------------ BB16 [061..07A) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} ***** BB16 STMT00008 (IL ???...0x061) [000042] -A---+------ * ASG int [000041] D----+-N---- +--* LCL_VAR int V06 loc2 [000040] -----+------ \--* LCL_VAR int V15 tmp1 ***** BB16 STMT00009 (IL 0x062...0x063) [000045] -A---+------ * ASG int [000044] D----+-N---- +--* LCL_VAR int V07 loc3 [000043] -----+------ \--* CNS_INT int 0 ***** BB16 STMT00098 (IL 0x064... ???) [000580] -A-XG+------ * ASG ref [000579] D----+-N---- +--* LCL_VAR ref V39 tmp25 [000578] ---XG+------ \--* IND ref [000845] -----+------ \--* ADD byref [000046] -----+------ +--* LCL_VAR ref V00 this [000844] -----+------ \--* CNS_INT long 8 field offset Fseq[_buckets] ***** BB16 STMT00105 (IL 0x064... ???) [000629] -A-X-+------ * ASG int [000628] D----+-N---- +--* LCL_VAR int V40 tmp26 [000583] ---X-+------ \--* ARR_LENGTH int [000582] -----+------ \--* LCL_VAR ref V39 tmp25 ***** BB16 STMT00106 (IL 0x064... ???) [000631] -A-XG+------ * ASG long [000630] D----+-N---- +--* LCL_VAR long V41 tmp27 [000585] ---XG+------ \--* IND long [000847] -----+------ \--* ADD byref [000584] -----+------ +--* LCL_VAR ref V00 this [000846] -----+------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] ***** BB16 STMT00108 (IL 0x064... ???) [000642] -A---+------ * ASG bool [000641] D----+-N---- +--* LCL_VAR int V43 tmp29 [000599] N----+---U-- \--* LE int [000597] -----+------ +--* LCL_VAR int V40 tmp26 [000598] -----+------ \--* CNS_INT int 0x7FFFFFFF ***** BB16 STMT00111 (IL 0x064... ???) [000652] -A--G+------ * ASG ref [000651] D----+-N---- +--* LCL_VAR ref V44 tmp30 [000636] #---G+------ \--* IND ref [000635] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB16 STMT00112 (IL 0x064... ???) [000654] -A--G+------ * ASG ref [000653] D----+-N---- +--* LCL_VAR ref V45 tmp31 [000638] #---G+------ \--* IND ref [000637] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB16 STMT00109 (IL 0x064... ???) [000647] -----+------ * JTRUE void [000646] J----+-N---- \--* NE int [000644] -----+------ +--* LCL_VAR int V43 tmp29 [000645] -----+------ \--* CNS_INT int 0 ------------ BB17 [064..065), preds={BB16} succs={BB18} ***** BB17 STMT00110 (IL 0x064... ???) [000650] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000648] -----+------ arg0 in rcx +--* LCL_VAR ref V44 tmp30 [000649] -----+------ arg1 in rdx \--* LCL_VAR ref V45 tmp31 ------------ BB18 [064..065) -> BB20 (cond), preds={BB16,BB17} succs={BB19,BB20} ***** BB18 STMT00103 (IL 0x064... ???) [000619] -A---+------ * ASG int [000618] D----+-N---- +--* LCL_VAR int V42 tmp28 [000617] -----+------ \--* CAST int <- uint <- long [000616] -----+------ \--* RSZ long [000614] -----+------ +--* MUL long [000611] -----+------ | +--* ADD long [000608] -----+------ | | +--* RSZ long [000606] -----+------ | | | +--* MUL long [000604] -----+------ | | | | +--* LCL_VAR long V41 tmp27 [000605] -----+---U-- | | | | \--* CAST long <- ulong <- uint [000047] -----+------ | | | | \--* LCL_VAR int V06 loc2 [000607] -----+------ | | | \--* CNS_INT int 32 [000610] -----+------ | | \--* CNS_INT long 1 [000613] -----+---U-- | \--* CAST long <- ulong <- uint [000612] -----+------ | \--* LCL_VAR int V40 tmp26 [000615] -----+------ \--* CNS_INT int 32 ***** BB18 STMT00114 (IL 0x064... ???) [000665] -A-X-+------ * ASG bool [000664] D----+-N---- +--* LCL_VAR int V46 tmp32 [000624] ---X-+------ \--* EQ int [000620] -----+------ +--* LCL_VAR int V42 tmp28 [000623] ---X-+------ \--* UMOD int [000621] -----+------ +--* LCL_VAR int V06 loc2 [000622] -----+------ \--* LCL_VAR int V40 tmp26 ***** BB18 STMT00117 (IL 0x064... ???) [000675] -A--G+------ * ASG ref [000674] D----+-N---- +--* LCL_VAR ref V47 tmp33 [000659] #---G+------ \--* IND ref [000658] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB18 STMT00118 (IL 0x064... ???) [000677] -A--G+------ * ASG ref [000676] D----+-N---- +--* LCL_VAR ref V48 tmp34 [000661] #---G+------ \--* IND ref [000660] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB18 STMT00115 (IL 0x064... ???) [000670] -----+------ * JTRUE void [000669] J----+-N---- \--* NE int [000667] -----+------ +--* LCL_VAR int V46 tmp32 [000668] -----+------ \--* CNS_INT int 0 ------------ BB19 [064..065), preds={BB18} succs={BB20} ***** BB19 STMT00116 (IL 0x064... ???) [000673] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000671] -----+------ arg0 in rcx +--* LCL_VAR ref V47 tmp33 [000672] -----+------ arg1 in rdx \--* LCL_VAR ref V48 tmp34 ------------ BB20 [064..065) -> BB39 (cond), preds={BB18,BB19} succs={BB21,BB39} ***** BB20 STMT00100 (IL 0x064... ???) [000591] -A-XG+------ * ASG byref [000590] D----+-N---- +--* LCL_VAR byref V38 tmp24 [000862] ---XG+------ \--* COMMA byref [000855] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000627] -----+------ | +--* LCL_VAR int V42 tmp28 [000854] ---X-+------ | \--* ARR_LENGTH int [000581] -----+------ | \--* LCL_VAR ref V39 tmp25 [000863] ----G------- \--* ADDR byref [000588] a---G+-N---- \--* IND int [000861] -----+------ \--* ADD byref [000852] -----+------ +--* LCL_VAR ref V39 tmp25 [000860] -----+------ \--* ADD long [000858] -----+------ +--* LSH long [000856] -----+------ | +--* CAST long <- int [000853] i----+------ | | \--* LCL_VAR int V42 tmp28 [000857] -----+-N---- | \--* CNS_INT long 2 [000859] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB20 STMT00101 (IL 0x064... ???) [000595] -A---+------ * ASG ref [000594] D----+-N---- +--* LCL_VAR ref V39 tmp25 [000593] -----+------ \--* CNS_INT ref null ***** BB20 STMT00011 (IL ???... ???) [000051] -A---+------ * ASG byref [000050] D----+-N---- +--* LCL_VAR byref V08 loc4 [000592] -----+------ \--* LCL_VAR byref V38 tmp24 ***** BB20 STMT00012 (IL 0x06D...0x072) [000057] -A-XG+------ * ASG int [000056] D----+-N---- +--* LCL_VAR int V09 loc5 [000055] ---XG+------ \--* ADD int [000053] *--XG+------ +--* IND int [000052] -----+------ | \--* LCL_VAR byref V38 tmp24 [000054] -----+------ \--* CNS_INT int -1 ***** BB20 STMT00013 (IL 0x074...0x075) [000061] -----+------ * JTRUE void [000060] J----+-N---- \--* NE int [000058] -----+------ +--* LCL_VAR ref V05 loc1 [000059] -----+------ \--* CNS_INT ref null ------------ BB21 [07A..???), preds={BB20} succs={BB22} ***** BB21 STMT00059 (IL 0x0FF...0x104) [000356] -A-X-+------ * ASG long [000355] D----+-N---- +--* LCL_VAR long V24 tmp10 [000354] #--X-+------ \--* IND long [000353] !----+------ \--* LCL_VAR ref V00 this ------------ BB22 [???..???) -> BB24 (cond), preds={BB21} succs={BB23,BB24} ***** BB22 STMT00152 (IL ???... ???) [001153] ------------ * JTRUE void [000369] J----+-N---- \--* EQ int [000365] n----+------ +--* IND long [000364] -----+------ | \--* ADD long [000362] #----+------ | +--* IND long [000361] #----+------ | | \--* IND long [000360] -----+------ | | \--* ADD long [000358] -----+------ | | +--* LCL_VAR long V24 tmp10 [000359] -----+------ | | \--* CNS_INT long 56 [000363] -----+------ | \--* CNS_INT long 32 [000368] -----+------ \--* CNS_INT long 0 ------------ BB23 [???..???) -> BB25 (always), preds={BB22} succs={BB25} ***** BB23 STMT00153 (IL ???... ???) [001155] -A---------- * ASG long [001154] D------N---- +--* LCL_VAR long V25 tmp11 [000370] n----+?----- \--* IND long [000371] -----+?----- \--* ADD long [000372] #----+?----- +--* IND long [000373] #----+?----- | \--* IND long [000374] -----+?----- | \--* ADD long [000375] -----+?----- | +--* LCL_VAR long V24 tmp10 [000376] -----+?----- | \--* CNS_INT long 56 [000377] -----+?----- \--* CNS_INT long 32 ------------ BB24 [???..???), preds={BB22} succs={BB25} ***** BB24 STMT00154 (IL ???... ???) [001157] -AC-G------- * ASG long [001156] D------N---- +--* LCL_VAR long V25 tmp11 [000367] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000357] -----+?----- arg0 in rcx +--* LCL_VAR long V24 tmp10 [000366] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB25 [???..106), preds={BB23,BB24} succs={BB26} ***** BB25 STMT00062 (IL ???... ???) [000386] -ACXG+------ * ASG ref [000385] D----+-N---- +--* LCL_VAR ref V12 loc8 [000352] --CXG+------ \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default [000382] -----+------ arg0 in rcx \--* LCL_VAR long V25 tmp11 ------------ BB26 [106..110) -> BB57 (cond), preds={BB25,BB37} succs={BB27,BB57} ***** BB26 STMT00063 (IL 0x106...0x10B) [000391] ---X-+------ * JTRUE void [000390] N--X-+-N-U-- \--* GE int [000387] -----+------ +--* LCL_VAR int V09 loc5 [000389] ---X-+------ \--* ARR_LENGTH int [000388] -----+------ \--* LCL_VAR ref V04 loc0 ------------ BB27 [110..120) -> BB37 (cond), preds={BB26} succs={BB28,BB37} ***** BB27 STMT00064 (IL 0x110...0x11E) [000399] ---XG+------ * JTRUE void [000398] N--XG+-N-U-- \--* NE int [000396] *--XG+------ +--* IND int [000868] ---XG+------ | \--* ADD byref [000879] ---XG+------ | +--* COMMA byref [000872] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000393] -----+------ | | | +--* LCL_VAR int V09 loc5 [000871] ---X-+------ | | | \--* ARR_LENGTH int [000392] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000882] ----G------- | | \--* ADDR byref [000394] a---G+-N---- | | \--* IND struct [000878] -----+------ | | \--* ADD byref [000869] -----+------ | | +--* LCL_VAR ref V04 loc0 [000877] -----+------ | | \--* ADD long [000875] -----+------ | | +--* LSH long [000881] -----+------ | | | +--* MUL long [000873] -----+------ | | | | +--* CAST long <- int [000870] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000880] ------------ | | | | \--* CNS_INT long 3 [000874] -----+-N---- | | | \--* CNS_INT long 3 [000876] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000867] -----+------ | \--* CNS_INT long 16 field offset Fseq[hashCode] [000397] -----+------ \--* LCL_VAR int V06 loc2 ------------ BB28 [120..137) -> BB37 (cond), preds={BB27} succs={BB29,BB37} ***** BB28 STMT00069 (IL 0x120...0x135) [000428] --CXG+------ * JTRUE void [000427] J-CXG+-N---- \--* EQ int [000425] --CXG+------ +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals [000908] n--X-+------ control expr | \--* IND long [000907] ---X-+------ | \--* ADD long [000905] #--X-+------ | +--* IND long [000904] ---X-+------ | | \--* ADD long [000902] #--X-+------ | | +--* IND long [000901] -----+------ | | | \--* LCL_VAR ref V12 loc8 [000903] -----+------ | | \--* CNS_INT int 72 [000906] -----+------ | \--* CNS_INT int 32 [000893] ---XG+------ arg1 in rdx | +--* COMMA ref [000886] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000420] -----+------ | | | +--* LCL_VAR int V09 loc5 [000885] ---X-+------ | | | \--* ARR_LENGTH int [000419] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000897] *---G+------ | | \--* IND ref [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] [000421] a---G+-N---- | | \--* IND struct [000892] -----+------ | | \--* ADD byref [000883] -----+------ | | +--* LCL_VAR ref V04 loc0 [000891] -----+------ | | \--* ADD long [000889] -----+------ | | +--* LSH long [000895] -----+------ | | | +--* MUL long [000887] -----+------ | | | | +--* CAST long <- int [000884] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000894] ------------ | | | | \--* CNS_INT long 3 [000888] -----+-N---- | | | \--* CNS_INT long 3 [000890] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000418] -----+------ this in rcx | +--* LCL_VAR ref V12 loc8 [000424] -----+------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 [000426] -----+------ \--* CNS_INT int 0 ------------ BB29 [137..13B) -> BB31 (cond), preds={BB28} succs={BB30,BB31} ***** BB29 STMT00070 (IL 0x137...0x139) [000432] -----+------ * JTRUE void [000431] N----+-N-U-- \--* NE int [000909] -----+------ +--* CAST int <- ubyte <- int [000429] -----+------ | \--* LCL_VAR int V03 arg3 [000430] -----+------ \--* CNS_INT int 1 ------------ BB30 [13B..14B) -> BB71 (always), preds={BB29} succs={BB71} ***** BB30 STMT00077 (IL 0x13B...0x144) [000481] -A-XG+------ * ASG ref [000480] *--XG+-N---- +--* IND ref [000911] ---XG+------ | \--* ADD byref [000922] ---XG+------ | +--* COMMA byref [000915] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000476] -----+------ | | | +--* LCL_VAR int V09 loc5 [000914] ---X-+------ | | | \--* ARR_LENGTH int [000475] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000925] ----G------- | | \--* ADDR byref [000477] a---G+-N---- | | \--* IND struct [000921] -----+------ | | \--* ADD byref [000912] -----+------ | | +--* LCL_VAR ref V04 loc0 [000920] -----+------ | | \--* ADD long [000918] -----+------ | | +--* LSH long [000924] -----+------ | | | +--* MUL long [000916] -----+------ | | | | +--* CAST long <- int [000913] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000923] ------------ | | | | \--* CNS_INT long 3 [000917] -----+-N---- | | | \--* CNS_INT long 3 [000919] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000910] -----+------ | \--* CNS_INT long 8 field offset Fseq[value] [000479] -----+------ \--* LCL_VAR ref V02 arg2 ------------ BB31 [14B..14F) -> BB54 (cond), preds={BB29} succs={BB32,BB54} ***** BB31 STMT00071 (IL 0x14B...0x14D) [000436] -----+------ * JTRUE void [000435] N----+-N-U-- \--* NE int [000926] -----+------ +--* CAST int <- ubyte <- int [000433] -----+------ | \--* LCL_VAR int V03 arg3 [000434] -----+------ \--* CNS_INT int 2 ------------ BB32 [14F..???), preds={BB31} succs={BB33} ***** BB32 STMT00073 (IL 0x14F...0x150) [000444] -A-X-+------ * ASG long [000443] D----+-N---- +--* LCL_VAR long V26 tmp12 [000442] #--X-+------ \--* IND long [000441] !----+------ \--* LCL_VAR ref V00 this ***** BB32 STMT00074 (IL ???... ???) [000454] -A---+------ * ASG ref [000453] D----+-N---- +--* LCL_VAR ref V27 tmp13 [000439] -----+------ \--* LCL_VAR ref V01 arg1 ------------ BB33 [???..???) -> BB35 (cond), preds={BB32} succs={BB34,BB35} ***** BB33 STMT00155 (IL ???... ???) [001158] ------------ * JTRUE void [000460] J----+-N---- \--* EQ int [000456] n----+------ +--* IND long [000452] -----+------ | \--* ADD long [000450] #----+------ | +--* IND long [000449] #----+------ | | \--* IND long [000448] -----+------ | | \--* ADD long [000446] -----+------ | | +--* LCL_VAR long V26 tmp12 [000447] -----+------ | | \--* CNS_INT long 56 [000451] -----+------ | \--* CNS_INT long 56 [000459] -----+------ \--* CNS_INT long 0 ------------ BB34 [???..???) -> BB36 (always), preds={BB33} succs={BB36} ***** BB34 STMT00156 (IL ???... ???) [001160] -A---------- * ASG long [001159] D------N---- +--* LCL_VAR long V28 tmp14 [000461] n----+?----- \--* IND long [000462] -----+?----- \--* ADD long [000463] #----+?----- +--* IND long [000464] #----+?----- | \--* IND long [000465] -----+?----- | \--* ADD long [000466] -----+?----- | +--* LCL_VAR long V26 tmp12 [000467] -----+?----- | \--* CNS_INT long 56 [000468] -----+?----- \--* CNS_INT long 56 ------------ BB35 [???..???), preds={BB33} succs={BB36} ***** BB35 STMT00157 (IL ???... ???) [001162] -AC-G------- * ASG long [001161] D------N---- +--* LCL_VAR long V28 tmp14 [000458] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000445] -----+?----- arg0 in rcx +--* LCL_VAR long V26 tmp12 [000457] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB36 [???..157) (throw), preds={BB34,BB35} succs={} ***** BB36 STMT00076 (IL ???... ???) [000440] --CXG+------ * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000473] -----+------ arg0 in rcx +--* LCL_VAR long V28 tmp14 [000455] -----+------ arg1 in rdx \--* LCL_VAR ref V01 arg1 ------------ BB37 [157..170) -> BB26 (cond), preds={BB27,BB28} succs={BB38,BB26} ***** BB37 STMT00065 (IL 0x157...0x164) [000406] -A-XG+------ * ASG int [000405] D----+-N---- +--* LCL_VAR int V09 loc5 [000404] *--XG+------ \--* IND int [000932] ---XG+------ \--* ADD byref [000943] ---XG+------ +--* COMMA byref [000936] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000401] -----+------ | | +--* LCL_VAR int V09 loc5 [000935] ---X-+------ | | \--* ARR_LENGTH int [000400] -----+------ | | \--* LCL_VAR ref V04 loc0 [000946] ----G------- | \--* ADDR byref [000402] a---G+-N---- | \--* IND struct [000942] -----+------ | \--* ADD byref [000933] -----+------ | +--* LCL_VAR ref V04 loc0 [000941] -----+------ | \--* ADD long [000939] -----+------ | +--* LSH long [000945] -----+------ | | +--* MUL long [000937] -----+------ | | | +--* CAST long <- int [000934] i----+------ | | | | \--* LCL_VAR int V09 loc5 [000944] ------------ | | | \--* CNS_INT long 3 [000938] -----+-N---- | | \--* CNS_INT long 3 [000940] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [000931] -----+------ \--* CNS_INT long 20 field offset Fseq[next] ***** BB37 STMT00066 (IL 0x166...0x169) [000411] -A---+------ * ASG int [000410] D----+-N---- +--* LCL_VAR int V07 loc3 [000409] -----+------ \--* ADD int [000407] -----+------ +--* LCL_VAR int V07 loc3 [000408] -----+------ \--* CNS_INT int 1 ***** BB37 STMT00067 (IL 0x16A...0x16E) [000416] ---X-+------ * JTRUE void [000415] N--X-+-N-U-- \--* LE int [000412] -----+------ +--* LCL_VAR int V07 loc3 [000414] ---X-+------ \--* ARR_LENGTH int [000413] -----+------ \--* LCL_VAR ref V04 loc0 ------------ BB38 [???..???) -> BB56 (always), preds={BB37} succs={BB56} ------------ BB39 [177..17E) -> BB57 (cond), preds={BB20,BB55} succs={BB40,BB57} ***** BB39 STMT00014 (IL 0x177...0x17C) [000066] ---X-+------ * JTRUE void [000065] N--X-+-N-U-- \--* GE int [000062] -----+------ +--* LCL_VAR int V09 loc5 [000064] ---X-+------ \--* ARR_LENGTH int [000063] -----+------ \--* LCL_VAR ref V04 loc0 ------------ BB40 [17E..18E) -> BB55 (cond), preds={BB39} succs={BB41,BB55} ***** BB40 STMT00039 (IL 0x17E...0x18C) [000215] ---XG+------ * JTRUE void [000214] N--XG+-N-U-- \--* NE int [000212] *--XG+------ +--* IND int [000948] ---XG+------ | \--* ADD byref [000959] ---XG+------ | +--* COMMA byref [000952] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000209] -----+------ | | | +--* LCL_VAR int V09 loc5 [000951] ---X-+------ | | | \--* ARR_LENGTH int [000208] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000962] ----G------- | | \--* ADDR byref [000210] a---G+-N---- | | \--* IND struct [000958] -----+------ | | \--* ADD byref [000949] -----+------ | | +--* LCL_VAR ref V04 loc0 [000957] -----+------ | | \--* ADD long [000955] -----+------ | | +--* LSH long [000961] -----+------ | | | +--* MUL long [000953] -----+------ | | | | +--* CAST long <- int [000950] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000960] ------------ | | | | \--* CNS_INT long 3 [000954] -----+-N---- | | | \--* CNS_INT long 3 [000956] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000947] -----+------ | \--* CNS_INT long 16 field offset Fseq[hashCode] [000213] -----+------ \--* LCL_VAR int V06 loc2 ------------ BB41 [18E..???), preds={BB40} succs={BB42} ***** BB41 STMT00045 (IL 0x18E...0x1A2) [000246] -A-XG+------ * ASG ref [000245] D----+-N---- +--* LCL_VAR ref V17 tmp3 [000973] ---XG+------ \--* COMMA ref [000966] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000236] -----+------ | +--* LCL_VAR int V09 loc5 [000965] ---X-+------ | \--* ARR_LENGTH int [000235] -----+------ | \--* LCL_VAR ref V04 loc0 [000977] *---G+------ \--* IND ref [000976] ----G------- \--* ADDR byref Zero Fseq[key] [000237] a---G+-N---- \--* IND struct [000972] -----+------ \--* ADD byref [000963] -----+------ +--* LCL_VAR ref V04 loc0 [000971] -----+------ \--* ADD long [000969] -----+------ +--* LSH long [000975] -----+------ | +--* MUL long [000967] -----+------ | | +--* CAST long <- int [000964] i----+------ | | | \--* LCL_VAR int V09 loc5 [000974] ------------ | | \--* CNS_INT long 3 [000968] -----+-N---- | \--* CNS_INT long 3 [000970] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB41 STMT00044 (IL 0x18E... ???) [000244] -A-X-+------ * ASG long [000243] D----+-N---- +--* LCL_VAR long V16 tmp2 [000242] #--X-+------ \--* IND long [000241] !----+------ \--* LCL_VAR ref V00 this ***** BB41 STMT00046 (IL ???... ???) [000257] -A---+------ * ASG ref [000256] D----+-N---- +--* LCL_VAR ref V18 tmp4 [000240] -----+------ \--* LCL_VAR ref V01 arg1 ------------ BB42 [???..???) -> BB44 (cond), preds={BB41} succs={BB43,BB44} ***** BB42 STMT00158 (IL ???... ???) [001163] ------------ * JTRUE void [000263] J----+-N---- \--* EQ int [000259] n----+------ +--* IND long [000255] -----+------ | \--* ADD long [000253] #----+------ | +--* IND long [000252] #----+------ | | \--* IND long [000251] -----+------ | | \--* ADD long [000249] -----+------ | | +--* LCL_VAR long V16 tmp2 [000250] -----+------ | | \--* CNS_INT long 56 [000254] -----+------ | \--* CNS_INT long 48 [000262] -----+------ \--* CNS_INT long 0 ------------ BB43 [???..???) -> BB45 (always), preds={BB42} succs={BB45} ***** BB43 STMT00159 (IL ???... ???) [001165] -A---------- * ASG long [001164] D------N---- +--* LCL_VAR long V19 tmp5 [000264] n----+?----- \--* IND long [000265] -----+?----- \--* ADD long [000266] #----+?----- +--* IND long [000267] #----+?----- | \--* IND long [000268] -----+?----- | \--* ADD long [000269] -----+?----- | +--* LCL_VAR long V16 tmp2 [000270] -----+?----- | \--* CNS_INT long 56 [000271] -----+?----- \--* CNS_INT long 48 ------------ BB44 [???..???), preds={BB42} succs={BB45} ***** BB44 STMT00160 (IL ???... ???) [001167] -AC-G------- * ASG long [001166] D------N---- +--* LCL_VAR long V19 tmp5 [000261] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000248] -----+?----- arg0 in rcx +--* LCL_VAR long V16 tmp2 [000260] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB45 [???..1A4) -> BB55 (cond), preds={BB43,BB44} succs={BB46,BB55} ***** BB45 STMT00048 (IL ???... ???) [000278] -A---+------ * ASG long [000277] D----+-N---- +--* LCL_VAR long V20 tmp6 [000276] -----+------ \--* LCL_VAR long V19 tmp5 ***** BB45 STMT00049 (IL ???... ???) [000283] --CXG+------ * JTRUE void [000282] J-CXG+-N---- \--* EQ int [000280] --CXG+------ +--* CALL ind stub int [000279] -----+------ calli tgt | \--* LCL_VAR long V19 tmp5 [000234] -----+------ this in rcx | +--* LCL_VAR ref V05 loc1 [000980] -----+------ arg1 in r11 | +--* LCL_VAR long V19 tmp5 r11 REG r11 [000247] -----+------ arg2 in rdx | +--* LCL_VAR ref V17 tmp3 [000258] -----+------ arg3 in r8 | \--* LCL_VAR ref V01 arg1 [000281] -----+------ \--* CNS_INT int 0 ------------ BB46 [1A4..1A8) -> BB48 (cond), preds={BB45} succs={BB47,BB48} ***** BB46 STMT00050 (IL 0x1A4...0x1A6) [000287] -----+------ * JTRUE void [000286] N----+-N-U-- \--* NE int [000985] -----+------ +--* CAST int <- ubyte <- int [000284] -----+------ | \--* LCL_VAR int V03 arg3 [000285] -----+------ \--* CNS_INT int 1 ------------ BB47 [1A8..1B8) -> BB71 (always), preds={BB46} succs={BB71} ***** BB47 STMT00057 (IL 0x1A8...0x1B1) [000336] -A-XG+------ * ASG ref [000335] *--XG+-N---- +--* IND ref [000987] ---XG+------ | \--* ADD byref [000998] ---XG+------ | +--* COMMA byref [000991] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000331] -----+------ | | | +--* LCL_VAR int V09 loc5 [000990] ---X-+------ | | | \--* ARR_LENGTH int [000330] -----+------ | | | \--* LCL_VAR ref V04 loc0 [001001] ----G------- | | \--* ADDR byref [000332] a---G+-N---- | | \--* IND struct [000997] -----+------ | | \--* ADD byref [000988] -----+------ | | +--* LCL_VAR ref V04 loc0 [000996] -----+------ | | \--* ADD long [000994] -----+------ | | +--* LSH long [001000] -----+------ | | | +--* MUL long [000992] -----+------ | | | | +--* CAST long <- int [000989] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000999] ------------ | | | | \--* CNS_INT long 3 [000993] -----+-N---- | | | \--* CNS_INT long 3 [000995] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000986] -----+------ | \--* CNS_INT long 8 field offset Fseq[value] [000334] -----+------ \--* LCL_VAR ref V02 arg2 ------------ BB48 [1B8..1BC) -> BB54 (cond), preds={BB46} succs={BB49,BB54} ***** BB48 STMT00051 (IL 0x1B8...0x1BA) [000291] -----+------ * JTRUE void [000290] N----+-N-U-- \--* NE int [001002] -----+------ +--* CAST int <- ubyte <- int [000288] -----+------ | \--* LCL_VAR int V03 arg3 [000289] -----+------ \--* CNS_INT int 2 ------------ BB49 [1BC..???), preds={BB48} succs={BB50} ***** BB49 STMT00053 (IL 0x1BC...0x1BD) [000299] -A-X-+------ * ASG long [000298] D----+-N---- +--* LCL_VAR long V21 tmp7 [000297] #--X-+------ \--* IND long [000296] !----+------ \--* LCL_VAR ref V00 this ***** BB49 STMT00054 (IL ???... ???) [000309] -A---+------ * ASG ref [000308] D----+-N---- +--* LCL_VAR ref V22 tmp8 [000294] -----+------ \--* LCL_VAR ref V01 arg1 ------------ BB50 [???..???) -> BB52 (cond), preds={BB49} succs={BB51,BB52} ***** BB50 STMT00161 (IL ???... ???) [001168] ------------ * JTRUE void [000315] J----+-N---- \--* EQ int [000311] n----+------ +--* IND long [000307] -----+------ | \--* ADD long [000305] #----+------ | +--* IND long [000304] #----+------ | | \--* IND long [000303] -----+------ | | \--* ADD long [000301] -----+------ | | +--* LCL_VAR long V21 tmp7 [000302] -----+------ | | \--* CNS_INT long 56 [000306] -----+------ | \--* CNS_INT long 56 [000314] -----+------ \--* CNS_INT long 0 ------------ BB51 [???..???) -> BB53 (always), preds={BB50} succs={BB53} ***** BB51 STMT00162 (IL ???... ???) [001170] -A---------- * ASG long [001169] D------N---- +--* LCL_VAR long V23 tmp9 [000316] n----+?----- \--* IND long [000317] -----+?----- \--* ADD long [000318] #----+?----- +--* IND long [000319] #----+?----- | \--* IND long [000320] -----+?----- | \--* ADD long [000321] -----+?----- | +--* LCL_VAR long V21 tmp7 [000322] -----+?----- | \--* CNS_INT long 56 [000323] -----+?----- \--* CNS_INT long 56 ------------ BB52 [???..???), preds={BB50} succs={BB53} ***** BB52 STMT00163 (IL ???... ???) [001172] -AC-G------- * ASG long [001171] D------N---- +--* LCL_VAR long V23 tmp9 [000313] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000300] -----+?----- arg0 in rcx +--* LCL_VAR long V21 tmp7 [000312] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB53 [???..1C4) (throw), preds={BB51,BB52} succs={} ***** BB53 STMT00056 (IL ???... ???) [000295] --CXG+------ * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000328] -----+------ arg0 in rcx +--* LCL_VAR long V23 tmp9 [000310] -----+------ arg1 in rdx \--* LCL_VAR ref V01 arg1 ------------ BB54 [???..???) (return), preds={BB31,BB48} succs={} ***** BB54 STMT00148 (IL ???... ???) [000811] -----+------ * RETURN int [000437] -----+------ \--* CNS_INT int 0 ------------ BB55 [1C4..1DD) -> BB39 (cond), preds={BB40,BB45} succs={BB56,BB39} ***** BB55 STMT00040 (IL 0x1C4...0x1D1) [000222] -A-XG+------ * ASG int [000221] D----+-N---- +--* LCL_VAR int V09 loc5 [000220] *--XG+------ \--* IND int [001009] ---XG+------ \--* ADD byref [001020] ---XG+------ +--* COMMA byref [001013] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000217] -----+------ | | +--* LCL_VAR int V09 loc5 [001012] ---X-+------ | | \--* ARR_LENGTH int [000216] -----+------ | | \--* LCL_VAR ref V04 loc0 [001023] ----G------- | \--* ADDR byref [000218] a---G+-N---- | \--* IND struct [001019] -----+------ | \--* ADD byref [001010] -----+------ | +--* LCL_VAR ref V04 loc0 [001018] -----+------ | \--* ADD long [001016] -----+------ | +--* LSH long [001022] -----+------ | | +--* MUL long [001014] -----+------ | | | +--* CAST long <- int [001011] i----+------ | | | | \--* LCL_VAR int V09 loc5 [001021] ------------ | | | \--* CNS_INT long 3 [001015] -----+-N---- | | \--* CNS_INT long 3 [001017] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [001008] -----+------ \--* CNS_INT long 20 field offset Fseq[next] ***** BB55 STMT00041 (IL 0x1D3...0x1D6) [000227] -A---+------ * ASG int [000226] D----+-N---- +--* LCL_VAR int V07 loc3 [000225] -----+------ \--* ADD int [000223] -----+------ +--* LCL_VAR int V07 loc3 [000224] -----+------ \--* CNS_INT int 1 ***** BB55 STMT00042 (IL 0x1D7...0x1DB) [000232] ---X-+------ * JTRUE void [000231] N--X-+-N-U-- \--* LE int [000228] -----+------ +--* LCL_VAR int V07 loc3 [000230] ---X-+------ \--* ARR_LENGTH int [000229] -----+------ \--* LCL_VAR ref V04 loc0 ------------ BB56 [1DD..1E4) (throw), preds={BB38,BB55} succs={} ***** BB56 STMT00043 (IL 0x1DD...0x1E2) [000233] --CXG+------ * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported ------------ BB57 [1E4..1ED) -> BB61 (cond), preds={BB26,BB39} succs={BB58,BB61} ***** BB57 STMT00015 (IL 0x1E4...0x1EB) [000071] ---XG+------ * JTRUE void [000070] J--XG+-N---- \--* LE int [000068] ---XG+------ +--* IND int [001025] -----+------ | \--* ADD byref [000067] -----+------ | +--* LCL_VAR ref V00 this [001024] -----+------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] [000069] -----+------ \--* CNS_INT int 0 ------------ BB58 [1ED..243) -> BB60 (cond), preds={BB57} succs={BB59,BB60} ***** BB58 STMT00035 (IL 0x1ED...0x1F3) [000174] -A-XG+------ * ASG int [000173] D----+-N---- +--* LCL_VAR int V10 loc6 [000172] ---XG+------ \--* IND int [001027] -----+------ \--* ADD byref [000171] -----+------ +--* LCL_VAR ref V00 this [001026] -----+------ \--* CNS_INT long 60 field offset Fseq[_freeList] ***** BB58 STMT00120 (IL 0x1F5... ???) [000688] -A-XG+------ * ASG bool [000687] D----+-N---- +--* LCL_VAR int V49 tmp35 [000184] -A-XG+------ \--* GE int [000182] -A-XG+------ +--* ADD int [001050] -A-XG+------ | +--* NEG int [000181] *A-XG+------ | | \--* IND int [001029] -A-XG+------ | | \--* ADD byref [001044] -A-XG+------ | | +--* COMMA byref [001032] -A-XG+------ | | | +--* ASG int [001031] D----+-N---- | | | | +--* LCL_VAR int V62 tmp48 [000178] ---XG+------ | | | | \--* IND int [001046] -----+------ | | | | \--* ADD byref [000177] -----+------ | | | | +--* LCL_VAR ref V00 this [001045] -----+------ | | | | \--* CNS_INT long 60 field offset Fseq[_freeList] [001043] ---XG+------ | | | \--* COMMA byref [001036] ---X-+------ | | | +--* ARR_BOUNDS_CHECK_Rng void [001033] -----+------ | | | | +--* LCL_VAR int V62 tmp48 [001035] ---X-+------ | | | | \--* ARR_LENGTH int [000176] -----+------ | | | | \--* LCL_VAR ref V04 loc0 [001049] ----G------- | | | \--* ADDR byref [000179] a---G+-N---- | | | \--* IND struct [001042] -----+------ | | | \--* ADD byref [001030] -----+------ | | | +--* LCL_VAR ref V04 loc0 [001041] -----+------ | | | \--* ADD long [001039] -----+------ | | | +--* LSH long [001048] -----+------ | | | | +--* MUL long [001037] -----+------ | | | | | +--* CAST long <- int [001034] i----+------ | | | | | | \--* LCL_VAR int V62 tmp48 [001047] ------------ | | | | | \--* CNS_INT long 3 [001038] -----+-N---- | | | | \--* CNS_INT long 3 [001040] -----+------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] [001028] -----+------ | | \--* CNS_INT long 20 field offset Fseq[next] [000175] -----+------ | \--* CNS_INT int -3 [000183] -----+------ \--* CNS_INT int -1 ***** BB58 STMT00123 (IL 0x1F5... ???) [000698] -A--G+------ * ASG ref [000697] D----+-N---- +--* LCL_VAR ref V50 tmp36 [000684] #---G+------ \--* IND ref [000683] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB58 STMT00121 (IL 0x1F5... ???) [000693] -----+------ * JTRUE void [000692] J----+-N---- \--* NE int [000690] -----+------ +--* LCL_VAR int V49 tmp35 [000691] -----+------ \--* CNS_INT int 0 ------------ BB59 [1F5..1F6), preds={BB58} succs={BB60} ***** BB59 STMT00122 (IL 0x1F5... ???) [000696] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [001052] #---G+------ arg0 in rcx +--* IND ref [001051] H----+------ | \--* CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" [000695] -----+------ arg1 in rdx \--* LCL_VAR ref V50 tmp36 ------------ BB60 [1F5..1F6) -> BB68 (always), preds={BB58,BB59} succs={BB68} ***** BB60 STMT00037 (IL 0x219... ???) [000200] -A-XG+------ * ASG int [000199] ---XG+-N---- +--* IND int [001056] -----+------ | \--* ADD byref [000190] -----+------ | +--* LCL_VAR ref V00 this [001055] -----+------ | \--* CNS_INT long 60 field offset Fseq[_freeList] [000198] -A-XG+------ \--* ADD int [001079] -A-XG+------ +--* NEG int [000197] *A-XG+------ | \--* IND int [001058] -A-XG+------ | \--* ADD byref [001073] -A-XG+------ | +--* COMMA byref [001061] -A-XG+------ | | +--* ASG int [001060] D----+-N---- | | | +--* LCL_VAR int V63 tmp49 [000194] ---XG+------ | | | \--* IND int [001075] -----+------ | | | \--* ADD byref [000193] -----+------ | | | +--* LCL_VAR ref V00 this [001074] -----+------ | | | \--* CNS_INT long 60 field offset Fseq[_freeList] [001072] ---XG+------ | | \--* COMMA byref [001065] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [001062] -----+------ | | | +--* LCL_VAR int V63 tmp49 [001064] ---X-+------ | | | \--* ARR_LENGTH int [000192] -----+------ | | | \--* LCL_VAR ref V04 loc0 [001078] ----G------- | | \--* ADDR byref [000195] a---G+-N---- | | \--* IND struct [001071] -----+------ | | \--* ADD byref [001059] -----+------ | | +--* LCL_VAR ref V04 loc0 [001070] -----+------ | | \--* ADD long [001068] -----+------ | | +--* LSH long [001077] -----+------ | | | +--* MUL long [001066] -----+------ | | | | +--* CAST long <- int [001063] i----+------ | | | | | \--* LCL_VAR int V63 tmp49 [001076] ------------ | | | | \--* CNS_INT long 3 [001067] -----+-N---- | | | \--* CNS_INT long 3 [001069] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [001057] -----+------ | \--* CNS_INT long 20 field offset Fseq[next] [000191] -----+------ \--* CNS_INT int -3 ***** BB60 STMT00038 (IL 0x233...0x23C) [000207] -A-XG+------ * ASG int [000206] ---XG+-N---- +--* IND int [001081] -----+------ | \--* ADD byref [000201] -----+------ | +--* LCL_VAR ref V00 this [001080] -----+------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] [000205] ---XG+------ \--* ADD int [000203] ---XG+------ +--* IND int [001083] -----+------ | \--* ADD byref [000202] -----+------ | +--* LCL_VAR ref V00 this [001082] -----+------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] [000204] -----+------ \--* CNS_INT int -1 ------------ BB61 [243..252) -> BB67 (cond), preds={BB57} succs={BB62,BB67} ***** BB61 STMT00016 (IL 0x243...0x249) [000075] -A-XG+------ * ASG int [000074] D----+-N---- +--* LCL_VAR int V13 loc9 [000073] ---XG+------ \--* IND int [001085] -----+------ \--* ADD byref [000072] -----+------ +--* LCL_VAR ref V00 this [001084] -----+------ \--* CNS_INT long 56 field offset Fseq[_count] ***** BB61 STMT00017 (IL 0x24B...0x250) [000080] ---X-+------ * JTRUE void [000079] N--X-+-N-U-- \--* NE int [000076] -----+------ +--* LCL_VAR int V13 loc9 [000078] ---X-+------ \--* ARR_LENGTH int [000077] -----+------ \--* LCL_VAR ref V04 loc0 ------------ BB62 [252..261) -> BB64 (cond), preds={BB61} succs={BB63,BB64} ***** BB62 STMT00125 (IL 0x252... ???) [000705] --CXG+------ * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [001090] -ACXG-----L- arg1 SETUP +--* ASG int [001089] D------N---- | +--* LCL_VAR int V64 tmp50 [000702] --CXG+------ | \--* CALL int System.Collections.HashHelpers.ExpandPrime [000701] ---XG+------ arg0 in rcx | \--* IND int [001087] -----+------ | \--* ADD byref [000700] -----+------ | +--* LCL_VAR ref V00 this [001086] -----+------ | \--* CNS_INT long 56 field offset Fseq[_count] [001091] ------------ arg1 in rdx +--* LCL_VAR int V64 tmp50 [000163] -----+------ this in rcx +--* LCL_VAR ref V00 this [000704] -----+------ arg2 in r8 \--* CNS_INT int 0 ***** BB62 STMT00126 (IL 0x258... ???) [000711] -A-XG+------ * ASG ref [000710] D----+-N---- +--* LCL_VAR ref V52 tmp38 [000709] ---XG+------ \--* IND ref [001095] -----+------ \--* ADD byref [000165] -----+------ +--* LCL_VAR ref V00 this [001094] -----+------ \--* CNS_INT long 8 field offset Fseq[_buckets] ***** BB62 STMT00133 (IL 0x258... ???) [000760] -A-X-+------ * ASG int [000759] D----+-N---- +--* LCL_VAR int V53 tmp39 [000714] ---X-+------ \--* ARR_LENGTH int [000713] -----+------ \--* LCL_VAR ref V52 tmp38 ***** BB62 STMT00134 (IL 0x258... ???) [000762] -A-XG+------ * ASG long [000761] D----+-N---- +--* LCL_VAR long V54 tmp40 [000716] ---XG+------ \--* IND long [001097] -----+------ \--* ADD byref [000715] -----+------ +--* LCL_VAR ref V00 this [001096] -----+------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] ***** BB62 STMT00136 (IL 0x258... ???) [000773] -A---+------ * ASG bool [000772] D----+-N---- +--* LCL_VAR int V56 tmp42 [000730] N----+---U-- \--* LE int [000728] -----+------ +--* LCL_VAR int V53 tmp39 [000729] -----+------ \--* CNS_INT int 0x7FFFFFFF ***** BB62 STMT00139 (IL 0x258... ???) [000783] -A--G+------ * ASG ref [000782] D----+-N---- +--* LCL_VAR ref V57 tmp43 [000767] #---G+------ \--* IND ref [000766] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB62 STMT00140 (IL 0x258... ???) [000785] -A--G+------ * ASG ref [000784] D----+-N---- +--* LCL_VAR ref V58 tmp44 [000769] #---G+------ \--* IND ref [000768] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB62 STMT00137 (IL 0x258... ???) [000778] -----+------ * JTRUE void [000777] J----+-N---- \--* NE int [000775] -----+------ +--* LCL_VAR int V56 tmp42 [000776] -----+------ \--* CNS_INT int 0 ------------ BB63 [258..259), preds={BB62} succs={BB64} ***** BB63 STMT00138 (IL 0x258... ???) [000781] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000779] -----+------ arg0 in rcx +--* LCL_VAR ref V57 tmp43 [000780] -----+------ arg1 in rdx \--* LCL_VAR ref V58 tmp44 ------------ BB64 [258..259) -> BB66 (cond), preds={BB62,BB63} succs={BB65,BB66} ***** BB64 STMT00131 (IL 0x258... ???) [000750] -A---+------ * ASG int [000749] D----+-N---- +--* LCL_VAR int V55 tmp41 [000748] -----+------ \--* CAST int <- uint <- long [000747] -----+------ \--* RSZ long [000745] -----+------ +--* MUL long [000742] -----+------ | +--* ADD long [000739] -----+------ | | +--* RSZ long [000737] -----+------ | | | +--* MUL long [000735] -----+------ | | | | +--* LCL_VAR long V54 tmp40 [000736] -----+---U-- | | | | \--* CAST long <- ulong <- uint [000166] -----+------ | | | | \--* LCL_VAR int V06 loc2 [000738] -----+------ | | | \--* CNS_INT int 32 [000741] -----+------ | | \--* CNS_INT long 1 [000744] -----+---U-- | \--* CAST long <- ulong <- uint [000743] -----+------ | \--* LCL_VAR int V53 tmp39 [000746] -----+------ \--* CNS_INT int 32 ***** BB64 STMT00142 (IL 0x258... ???) [000796] -A-X-+------ * ASG bool [000795] D----+-N---- +--* LCL_VAR int V59 tmp45 [000755] ---X-+------ \--* EQ int [000751] -----+------ +--* LCL_VAR int V55 tmp41 [000754] ---X-+------ \--* UMOD int [000752] -----+------ +--* LCL_VAR int V06 loc2 [000753] -----+------ \--* LCL_VAR int V53 tmp39 ***** BB64 STMT00145 (IL 0x258... ???) [000806] -A--G+------ * ASG ref [000805] D----+-N---- +--* LCL_VAR ref V60 tmp46 [000790] #---G+------ \--* IND ref [000789] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB64 STMT00146 (IL 0x258... ???) [000808] -A--G+------ * ASG ref [000807] D----+-N---- +--* LCL_VAR ref V61 tmp47 [000792] #---G+------ \--* IND ref [000791] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB64 STMT00143 (IL 0x258... ???) [000801] -----+------ * JTRUE void [000800] J----+-N---- \--* NE int [000798] -----+------ +--* LCL_VAR int V59 tmp45 [000799] -----+------ \--* CNS_INT int 0 ------------ BB65 [258..259), preds={BB64} succs={BB66} ***** BB65 STMT00144 (IL 0x258... ???) [000804] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000802] -----+------ arg0 in rcx +--* LCL_VAR ref V60 tmp46 [000803] -----+------ arg1 in rdx \--* LCL_VAR ref V61 tmp47 ------------ BB66 [258..259), preds={BB64,BB65} succs={BB67} ***** BB66 STMT00128 (IL 0x258... ???) [000722] -A-XG+------ * ASG byref [000721] D----+-N---- +--* LCL_VAR byref V51 tmp37 [001112] ---XG+------ \--* COMMA byref [001105] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000758] -----+------ | +--* LCL_VAR int V55 tmp41 [001104] ---X-+------ | \--* ARR_LENGTH int [000712] -----+------ | \--* LCL_VAR ref V52 tmp38 [001113] ----G------- \--* ADDR byref [000719] a---G+-N---- \--* IND int [001111] -----+------ \--* ADD byref [001102] -----+------ +--* LCL_VAR ref V52 tmp38 [001110] -----+------ \--* ADD long [001108] -----+------ +--* LSH long [001106] -----+------ | +--* CAST long <- int [001103] i----+------ | | \--* LCL_VAR int V55 tmp41 [001107] -----+-N---- | \--* CNS_INT long 2 [001109] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB66 STMT00129 (IL 0x258... ???) [000726] -A---+------ * ASG ref [000725] D----+-N---- +--* LCL_VAR ref V52 tmp38 [000724] -----+------ \--* CNS_INT ref null ***** BB66 STMT00034 (IL ???... ???) [000170] -A---+------ * ASG byref [000169] D----+-N---- +--* LCL_VAR byref V08 loc4 [000723] -----+------ \--* LCL_VAR byref V51 tmp37 ------------ BB67 [261..276), preds={BB61,BB66} succs={BB68} ***** BB67 STMT00018 (IL 0x261...0x263) [000083] -A---+------ * ASG int [000082] D----+-N---- +--* LCL_VAR int V10 loc6 [000081] -----+------ \--* LCL_VAR int V13 loc9 ***** BB67 STMT00019 (IL 0x265...0x26A) [000089] -A-XG+------ * ASG int [000088] ---XG+-N---- +--* IND int [001115] -----+------ | \--* ADD byref [000084] -----+------ | +--* LCL_VAR ref V00 this [001114] -----+------ | \--* CNS_INT long 56 field offset Fseq[_count] [000087] -----+------ \--* ADD int [000085] -----+------ +--* LCL_VAR int V13 loc9 [000086] -----+------ \--* CNS_INT int 1 ***** BB67 STMT00020 (IL 0x26F...0x275) [000093] -A-XG+------ * ASG ref [000092] D----+-N---- +--* LCL_VAR ref V04 loc0 [000091] ---XG+------ \--* IND ref [001117] -----+------ \--* ADD byref [000090] -----+------ +--* LCL_VAR ref V00 this [001116] -----+------ \--* CNS_INT long 16 field offset Fseq[_entries] ------------ BB68 [276..2CF) -> BB71 (cond), preds={BB60,BB67} succs={BB69,BB71} ***** BB68 STMT00021 (IL 0x276...0x27E) [000099] -A-XG+------ * ASG byref [000098] D----+-N---- +--* LCL_VAR byref V11 loc7 [001128] ---XG+------ \--* COMMA byref [001121] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000095] -----+------ | +--* LCL_VAR int V10 loc6 [001120] ---X-+------ | \--* ARR_LENGTH int [000094] -----+------ | \--* LCL_VAR ref V04 loc0 [001131] ----G------- \--* ADDR byref [000096] a---G+-N---- \--* IND struct [001127] -----+------ \--* ADD byref [001118] -----+------ +--* LCL_VAR ref V04 loc0 [001126] -----+------ \--* ADD long [001124] -----+------ +--* LSH long [001130] -----+------ | +--* MUL long [001122] -----+------ | | +--* CAST long <- int [001119] i----+------ | | | \--* LCL_VAR int V10 loc6 [001129] ------------ | | \--* CNS_INT long 3 [001123] -----+-N---- | \--* CNS_INT long 3 [001125] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB68 STMT00022 (IL 0x280...0x283) [000103] -A-XG+------ * ASG int [000102] *--XG+-N---- +--* IND int [001133] -----+------ | \--* ADD byref [000100] -----+------ | +--* LCL_VAR byref V11 loc7 [001132] -----+------ | \--* CNS_INT long 16 field offset Fseq[hashCode] [000101] -----+------ \--* LCL_VAR int V06 loc2 ***** BB68 STMT00023 (IL 0x288...0x28F) [000110] -A-XG+------ * ASG int [000109] *--XG+-N---- +--* IND int [001135] -----+------ | \--* ADD byref [000104] -----+------ | +--* LCL_VAR byref V11 loc7 [001134] -----+------ | \--* CNS_INT long 20 field offset Fseq[next] [000108] ---XG+------ \--* ADD int [000106] *--XG+------ +--* IND int [000105] -----+------ | \--* LCL_VAR byref V08 loc4 [000107] -----+------ \--* CNS_INT int -1 ***** BB68 STMT00024 (IL 0x294...0x297) [000114] -A-XG+------ * ASG ref [000113] *--XG+-N---- +--* IND ref [000111] -----+------ | \--* LCL_VAR byref V11 loc7 Zero Fseq[key] [000112] -----+------ \--* LCL_VAR ref V01 arg1 ***** BB68 STMT00025 (IL 0x29C...0x29F) [000118] -A-XG+------ * ASG ref [000117] *--XG+-N---- +--* IND ref [001137] -----+------ | \--* ADD byref [000115] -----+------ | +--* LCL_VAR byref V11 loc7 [001136] -----+------ | \--* CNS_INT long 8 field offset Fseq[value] [000116] -----+------ \--* LCL_VAR ref V02 arg2 ***** BB68 STMT00026 (IL 0x2A4...0x2AA) [000124] -A-XG+------ * ASG int [000123] *--X-+-N---- +--* IND int [000119] -----+------ | \--* LCL_VAR byref V08 loc4 [000122] -----+------ \--* ADD int [000120] -----+------ +--* LCL_VAR int V10 loc6 [000121] -----+------ \--* CNS_INT int 1 ***** BB68 STMT00027 (IL 0x2AB...0x2B4) [000131] -A-XG+------ * ASG int [000130] ---XG+-N---- +--* IND int [001139] -----+------ | \--* ADD byref [000125] -----+------ | +--* LCL_VAR ref V00 this [001138] -----+------ | \--* CNS_INT long 68 field offset Fseq[_version] [000129] ---XG+------ \--* ADD int [000127] ---XG+------ +--* IND int [001141] -----+------ | \--* ADD byref [000126] -----+------ | +--* LCL_VAR ref V00 this [001140] -----+------ | \--* CNS_INT long 68 field offset Fseq[_version] [000128] -----+------ \--* CNS_INT int 1 ***** BB68 STMT00028 (IL 0x2CA...0x2CD) [000148] -----+------ * JTRUE void [000147] N----+-N-U-- \--* LE int [000145] -----+------ +--* LCL_VAR int V07 loc3 [000146] -----+------ \--* CNS_INT int 100 ------------ BB69 [2CF..2D7) -> BB71 (cond), preds={BB68} succs={BB70,BB71} ***** BB69 STMT00030 (IL 0x2CF...0x2D5) [000156] --C-G+------ * JTRUE void [000155] J-C-G+-N---- \--* EQ int [000153] --C-G+------ +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS [000151] -----+------ arg1 in rdx | +--* LCL_VAR ref V05 loc1 [000152] H----+-N---- arg0 in rcx | \--* CNS_INT(h) long 0xd1ffab1e class [000154] -----+------ \--* CNS_INT ref null ------------ BB70 [2D7..2E3), preds={BB69} succs={BB71} ***** BB70 STMT00031 (IL 0x2D7...0x2DC) [000161] --CXG+------ * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [000159] ---X-+------ arg1 in rdx +--* ARR_LENGTH int [000158] -----+------ | \--* LCL_VAR ref V04 loc0 [000157] -----+------ this in rcx +--* LCL_VAR ref V00 this [000160] -----+------ arg2 in r8 \--* CNS_INT int 1 ------------ BB71 [???..???) (return), preds={BB30,BB47,BB68,BB69,BB70} succs={} ***** BB71 STMT00147 (IL ???... ???) [000810] -----+------ * RETURN int [000482] -----+------ \--* CNS_INT int 1 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE GS Cookie No GS security needed *************** Finishing PHASE GS Cookie *************** Starting PHASE Compute edge weights (1, false) *************** In fgComputeBlockAndEdgeWeights() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB03 [0002] 1 BB01 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i hascall gcsafe BB05 [0004] 2 BB03,BB04 1 [01E..04B)-> BB07 ( cond ) i BB06 [0052] 1 BB05 1 [01E..01F) i hascall gcsafe BB07 [0053] 2 BB05,BB06 1 [01E..034)-> BB09 ( cond ) i BB08 [0057] 1 BB07 1 [033..034) i hascall gcsafe BB09 [0058] 2 BB07,BB08 1 [033..034)-> BB15 ( cond ) i BB10 [0005] 1 BB09 1 [04B..???) i hascall gcsafe BB11 [0095] 1 BB10 1 [???..???)-> BB13 ( cond ) i BB12 [0097] 1 BB11 0.50 [???..???)-> BB14 (always) i BB13 [0096] 1 BB11 0.50 [???..???) i BB14 [0094] 2 BB12,BB13 1 [???..054)-> BB16 (always) i hascall gcsafe BB15 [0006] 1 BB09 1 [054..061) i hascall gcsafe BB16 [0007] 2 BB14,BB15 1 [061..07A)-> BB18 ( cond ) i idxlen BB17 [0064] 1 BB16 1 [064..065) i hascall gcsafe BB18 [0065] 2 BB16,BB17 1 [064..065)-> BB20 ( cond ) i idxlen BB19 [0069] 1 BB18 1 [064..065) i hascall gcsafe BB20 [0070] 2 BB18,BB19 1 [064..065)-> BB39 ( cond ) i idxlen BB21 [0008] 1 BB20 1 [07A..???) i hascall gcsafe BB22 [0099] 1 BB21 1 [???..???)-> BB24 ( cond ) i BB23 [0101] 1 BB22 0.50 [???..???)-> BB25 (always) i BB24 [0100] 1 BB22 0.50 [???..???) i BB25 [0098] 2 BB23,BB24 1 [???..106) i hascall gcsafe BB26 [0020] 2 BB25,BB37 1 [106..110)-> BB57 ( cond ) i idxlen bwd bwd-target BB27 [0021] 1 BB26 1 [110..120)-> BB37 ( cond ) i idxlen bwd BB28 [0022] 1 BB27 1 [120..137)-> BB37 ( cond ) i hascall gcsafe idxlen bwd BB29 [0023] 1 BB28 1 [137..13B)-> BB31 ( cond ) i bwd BB30 [0024] 1 BB29 1 [13B..14B)-> BB71 (always) i idxlen BB31 [0025] 1 BB29 1 [14B..14F)-> BB54 ( cond ) i bwd BB32 [0026] 1 BB31 0 [14F..???) i rare hascall gcsafe bwd BB33 [0103] 1 BB32 0 [???..???)-> BB35 ( cond ) i rare BB34 [0105] 1 BB33 0 [???..???)-> BB36 (always) i rare BB35 [0104] 1 BB33 0 [???..???) i rare BB36 [0102] 2 BB34,BB35 0 [???..157) (throw ) i rare hascall gcsafe bwd BB37 [0028] 2 BB27,BB28 1 [157..170)-> BB26 ( cond ) i idxlen bwd BB38 [0093] 1 BB37 1 [???..???)-> BB56 (always) internal BB39 [0030] 2 BB20,BB55 1 [177..17E)-> BB57 ( cond ) i idxlen bwd bwd-target BB40 [0031] 1 BB39 1 [17E..18E)-> BB55 ( cond ) i idxlen bwd BB41 [0032] 1 BB40 1 [18E..???) i hascall gcsafe idxlen bwd BB42 [0107] 1 BB41 1 [???..???)-> BB44 ( cond ) i BB43 [0109] 1 BB42 0.50 [???..???)-> BB45 (always) i BB44 [0108] 1 BB42 0.50 [???..???) i BB45 [0106] 2 BB43,BB44 1 [???..1A4)-> BB55 ( cond ) i hascall gcsafe idxlen bwd BB46 [0033] 1 BB45 1 [1A4..1A8)-> BB48 ( cond ) i bwd BB47 [0034] 1 BB46 1 [1A8..1B8)-> BB71 (always) i idxlen BB48 [0035] 1 BB46 1 [1B8..1BC)-> BB54 ( cond ) i bwd BB49 [0036] 1 BB48 0 [1BC..???) i rare hascall gcsafe bwd BB50 [0111] 1 BB49 0 [???..???)-> BB52 ( cond ) i rare BB51 [0113] 1 BB50 0 [???..???)-> BB53 (always) i rare BB52 [0112] 1 BB50 0 [???..???) i rare BB53 [0110] 2 BB51,BB52 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB54 [0092] 2 BB31,BB48 1 [???..???) (return) internal BB55 [0038] 2 BB40,BB45 1 [1C4..1DD)-> BB39 ( cond ) i idxlen bwd BB56 [0039] 2 BB38,BB55 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd BB57 [0040] 2 BB26,BB39 1 [1E4..1ED)-> BB61 ( cond ) i BB58 [0041] 1 BB57 1 [1ED..243)-> BB60 ( cond ) i idxlen BB59 [0075] 1 BB58 1 [1F5..1F6) i hascall gcsafe BB60 [0076] 2 BB58,BB59 1 [1F5..1F6)-> BB68 (always) i idxlen BB61 [0042] 1 BB57 1 [243..252)-> BB67 ( cond ) i idxlen BB62 [0043] 1 BB61 1 [252..261)-> BB64 ( cond ) i hascall gcsafe idxlen BB63 [0083] 1 BB62 1 [258..259) i hascall gcsafe BB64 [0084] 2 BB62,BB63 1 [258..259)-> BB66 ( cond ) i idxlen BB65 [0088] 1 BB64 1 [258..259) i hascall gcsafe BB66 [0089] 2 BB64,BB65 1 [258..259) i idxlen BB67 [0044] 2 BB61,BB66 1 [261..276) i BB68 [0045] 2 BB60,BB67 1 [276..2CF)-> BB71 ( cond ) i idxlen BB69 [0047] 1 BB68 1 [2CF..2D7)-> BB71 ( cond ) i hascall BB70 [0048] 1 BB69 1 [2D7..2E3) i hascall gcsafe idxlen BB71 [0091] 5 BB30,BB47,BB68,BB69,BB70 1 [???..???) (return) internal ----------------------------------------------------------------------------------------------------------------------------------------- -- no profile data, so using default called count -- not optimizing or no profile data, so not computing edge weights *************** Finishing PHASE Compute edge weights (1, false) *************** Starting PHASE Create EH funclets *************** In fgCreateFunclets() After fgCreateFunclets() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB03 [0002] 1 BB01 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i hascall gcsafe BB05 [0004] 2 BB03,BB04 1 [01E..04B)-> BB07 ( cond ) i BB06 [0052] 1 BB05 1 [01E..01F) i hascall gcsafe BB07 [0053] 2 BB05,BB06 1 [01E..034)-> BB09 ( cond ) i BB08 [0057] 1 BB07 1 [033..034) i hascall gcsafe BB09 [0058] 2 BB07,BB08 1 [033..034)-> BB15 ( cond ) i BB10 [0005] 1 BB09 1 [04B..???) i hascall gcsafe BB11 [0095] 1 BB10 1 [???..???)-> BB13 ( cond ) i BB12 [0097] 1 BB11 0.50 [???..???)-> BB14 (always) i BB13 [0096] 1 BB11 0.50 [???..???) i BB14 [0094] 2 BB12,BB13 1 [???..054)-> BB16 (always) i hascall gcsafe BB15 [0006] 1 BB09 1 [054..061) i hascall gcsafe BB16 [0007] 2 BB14,BB15 1 [061..07A)-> BB18 ( cond ) i idxlen BB17 [0064] 1 BB16 1 [064..065) i hascall gcsafe BB18 [0065] 2 BB16,BB17 1 [064..065)-> BB20 ( cond ) i idxlen BB19 [0069] 1 BB18 1 [064..065) i hascall gcsafe BB20 [0070] 2 BB18,BB19 1 [064..065)-> BB39 ( cond ) i idxlen BB21 [0008] 1 BB20 1 [07A..???) i hascall gcsafe BB22 [0099] 1 BB21 1 [???..???)-> BB24 ( cond ) i BB23 [0101] 1 BB22 0.50 [???..???)-> BB25 (always) i BB24 [0100] 1 BB22 0.50 [???..???) i BB25 [0098] 2 BB23,BB24 1 [???..106) i hascall gcsafe BB26 [0020] 2 BB25,BB37 1 [106..110)-> BB57 ( cond ) i idxlen bwd bwd-target BB27 [0021] 1 BB26 1 [110..120)-> BB37 ( cond ) i idxlen bwd BB28 [0022] 1 BB27 1 [120..137)-> BB37 ( cond ) i hascall gcsafe idxlen bwd BB29 [0023] 1 BB28 1 [137..13B)-> BB31 ( cond ) i bwd BB30 [0024] 1 BB29 1 [13B..14B)-> BB71 (always) i idxlen BB31 [0025] 1 BB29 1 [14B..14F)-> BB54 ( cond ) i bwd BB32 [0026] 1 BB31 0 [14F..???) i rare hascall gcsafe bwd BB33 [0103] 1 BB32 0 [???..???)-> BB35 ( cond ) i rare BB34 [0105] 1 BB33 0 [???..???)-> BB36 (always) i rare BB35 [0104] 1 BB33 0 [???..???) i rare BB36 [0102] 2 BB34,BB35 0 [???..157) (throw ) i rare hascall gcsafe bwd BB37 [0028] 2 BB27,BB28 1 [157..170)-> BB26 ( cond ) i idxlen bwd BB38 [0093] 1 BB37 1 [???..???)-> BB56 (always) internal BB39 [0030] 2 BB20,BB55 1 [177..17E)-> BB57 ( cond ) i idxlen bwd bwd-target BB40 [0031] 1 BB39 1 [17E..18E)-> BB55 ( cond ) i idxlen bwd BB41 [0032] 1 BB40 1 [18E..???) i hascall gcsafe idxlen bwd BB42 [0107] 1 BB41 1 [???..???)-> BB44 ( cond ) i BB43 [0109] 1 BB42 0.50 [???..???)-> BB45 (always) i BB44 [0108] 1 BB42 0.50 [???..???) i BB45 [0106] 2 BB43,BB44 1 [???..1A4)-> BB55 ( cond ) i hascall gcsafe idxlen bwd BB46 [0033] 1 BB45 1 [1A4..1A8)-> BB48 ( cond ) i bwd BB47 [0034] 1 BB46 1 [1A8..1B8)-> BB71 (always) i idxlen BB48 [0035] 1 BB46 1 [1B8..1BC)-> BB54 ( cond ) i bwd BB49 [0036] 1 BB48 0 [1BC..???) i rare hascall gcsafe bwd BB50 [0111] 1 BB49 0 [???..???)-> BB52 ( cond ) i rare BB51 [0113] 1 BB50 0 [???..???)-> BB53 (always) i rare BB52 [0112] 1 BB50 0 [???..???) i rare BB53 [0110] 2 BB51,BB52 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB54 [0092] 2 BB31,BB48 1 [???..???) (return) internal BB55 [0038] 2 BB40,BB45 1 [1C4..1DD)-> BB39 ( cond ) i idxlen bwd BB56 [0039] 2 BB38,BB55 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd BB57 [0040] 2 BB26,BB39 1 [1E4..1ED)-> BB61 ( cond ) i BB58 [0041] 1 BB57 1 [1ED..243)-> BB60 ( cond ) i idxlen BB59 [0075] 1 BB58 1 [1F5..1F6) i hascall gcsafe BB60 [0076] 2 BB58,BB59 1 [1F5..1F6)-> BB68 (always) i idxlen BB61 [0042] 1 BB57 1 [243..252)-> BB67 ( cond ) i idxlen BB62 [0043] 1 BB61 1 [252..261)-> BB64 ( cond ) i hascall gcsafe idxlen BB63 [0083] 1 BB62 1 [258..259) i hascall gcsafe BB64 [0084] 2 BB62,BB63 1 [258..259)-> BB66 ( cond ) i idxlen BB65 [0088] 1 BB64 1 [258..259) i hascall gcsafe BB66 [0089] 2 BB64,BB65 1 [258..259) i idxlen BB67 [0044] 2 BB61,BB66 1 [261..276) i BB68 [0045] 2 BB60,BB67 1 [276..2CF)-> BB71 ( cond ) i idxlen BB69 [0047] 1 BB68 1 [2CF..2D7)-> BB71 ( cond ) i hascall BB70 [0048] 1 BB69 1 [2D7..2E3) i hascall gcsafe idxlen BB71 [0091] 5 BB30,BB47,BB68,BB69,BB70 1 [???..???) (return) internal ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** Finishing PHASE Create EH funclets *************** Starting PHASE Invert loops *************** Finishing PHASE Invert loops [no changes] *************** Starting PHASE Optimize layout *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB03 [0002] 1 BB01 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i hascall gcsafe BB05 [0004] 2 BB03,BB04 1 [01E..04B)-> BB07 ( cond ) i BB06 [0052] 1 BB05 1 [01E..01F) i hascall gcsafe BB07 [0053] 2 BB05,BB06 1 [01E..034)-> BB09 ( cond ) i BB08 [0057] 1 BB07 1 [033..034) i hascall gcsafe BB09 [0058] 2 BB07,BB08 1 [033..034)-> BB15 ( cond ) i BB10 [0005] 1 BB09 1 [04B..???) i hascall gcsafe BB11 [0095] 1 BB10 1 [???..???)-> BB13 ( cond ) i BB12 [0097] 1 BB11 0.50 [???..???)-> BB14 (always) i BB13 [0096] 1 BB11 0.50 [???..???) i BB14 [0094] 2 BB12,BB13 1 [???..054)-> BB16 (always) i hascall gcsafe BB15 [0006] 1 BB09 1 [054..061) i hascall gcsafe BB16 [0007] 2 BB14,BB15 1 [061..07A)-> BB18 ( cond ) i idxlen BB17 [0064] 1 BB16 1 [064..065) i hascall gcsafe BB18 [0065] 2 BB16,BB17 1 [064..065)-> BB20 ( cond ) i idxlen BB19 [0069] 1 BB18 1 [064..065) i hascall gcsafe BB20 [0070] 2 BB18,BB19 1 [064..065)-> BB39 ( cond ) i idxlen BB21 [0008] 1 BB20 1 [07A..???) i hascall gcsafe BB22 [0099] 1 BB21 1 [???..???)-> BB24 ( cond ) i BB23 [0101] 1 BB22 0.50 [???..???)-> BB25 (always) i BB24 [0100] 1 BB22 0.50 [???..???) i BB25 [0098] 2 BB23,BB24 1 [???..106) i hascall gcsafe BB26 [0020] 2 BB25,BB37 1 [106..110)-> BB57 ( cond ) i idxlen bwd bwd-target BB27 [0021] 1 BB26 1 [110..120)-> BB37 ( cond ) i idxlen bwd BB28 [0022] 1 BB27 1 [120..137)-> BB37 ( cond ) i hascall gcsafe idxlen bwd BB29 [0023] 1 BB28 1 [137..13B)-> BB31 ( cond ) i bwd BB30 [0024] 1 BB29 1 [13B..14B)-> BB71 (always) i idxlen BB31 [0025] 1 BB29 1 [14B..14F)-> BB54 ( cond ) i bwd BB32 [0026] 1 BB31 0 [14F..???) i rare hascall gcsafe bwd BB33 [0103] 1 BB32 0 [???..???)-> BB35 ( cond ) i rare BB34 [0105] 1 BB33 0 [???..???)-> BB36 (always) i rare BB35 [0104] 1 BB33 0 [???..???) i rare BB36 [0102] 2 BB34,BB35 0 [???..157) (throw ) i rare hascall gcsafe bwd BB37 [0028] 2 BB27,BB28 1 [157..170)-> BB26 ( cond ) i idxlen bwd BB38 [0093] 1 BB37 1 [???..???)-> BB56 (always) internal BB39 [0030] 2 BB20,BB55 1 [177..17E)-> BB57 ( cond ) i idxlen bwd bwd-target BB40 [0031] 1 BB39 1 [17E..18E)-> BB55 ( cond ) i idxlen bwd BB41 [0032] 1 BB40 1 [18E..???) i hascall gcsafe idxlen bwd BB42 [0107] 1 BB41 1 [???..???)-> BB44 ( cond ) i BB43 [0109] 1 BB42 0.50 [???..???)-> BB45 (always) i BB44 [0108] 1 BB42 0.50 [???..???) i BB45 [0106] 2 BB43,BB44 1 [???..1A4)-> BB55 ( cond ) i hascall gcsafe idxlen bwd BB46 [0033] 1 BB45 1 [1A4..1A8)-> BB48 ( cond ) i bwd BB47 [0034] 1 BB46 1 [1A8..1B8)-> BB71 (always) i idxlen BB48 [0035] 1 BB46 1 [1B8..1BC)-> BB54 ( cond ) i bwd BB49 [0036] 1 BB48 0 [1BC..???) i rare hascall gcsafe bwd BB50 [0111] 1 BB49 0 [???..???)-> BB52 ( cond ) i rare BB51 [0113] 1 BB50 0 [???..???)-> BB53 (always) i rare BB52 [0112] 1 BB50 0 [???..???) i rare BB53 [0110] 2 BB51,BB52 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB54 [0092] 2 BB31,BB48 1 [???..???) (return) internal BB55 [0038] 2 BB40,BB45 1 [1C4..1DD)-> BB39 ( cond ) i idxlen bwd BB56 [0039] 2 BB38,BB55 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd BB57 [0040] 2 BB26,BB39 1 [1E4..1ED)-> BB61 ( cond ) i BB58 [0041] 1 BB57 1 [1ED..243)-> BB60 ( cond ) i idxlen BB59 [0075] 1 BB58 1 [1F5..1F6) i hascall gcsafe BB60 [0076] 2 BB58,BB59 1 [1F5..1F6)-> BB68 (always) i idxlen BB61 [0042] 1 BB57 1 [243..252)-> BB67 ( cond ) i idxlen BB62 [0043] 1 BB61 1 [252..261)-> BB64 ( cond ) i hascall gcsafe idxlen BB63 [0083] 1 BB62 1 [258..259) i hascall gcsafe BB64 [0084] 2 BB62,BB63 1 [258..259)-> BB66 ( cond ) i idxlen BB65 [0088] 1 BB64 1 [258..259) i hascall gcsafe BB66 [0089] 2 BB64,BB65 1 [258..259) i idxlen BB67 [0044] 2 BB61,BB66 1 [261..276) i BB68 [0045] 2 BB60,BB67 1 [276..2CF)-> BB71 ( cond ) i idxlen BB69 [0047] 1 BB68 1 [2CF..2D7)-> BB71 ( cond ) i hascall BB70 [0048] 1 BB69 1 [2D7..2E3) i hascall gcsafe idxlen BB71 [0091] 5 BB30,BB47,BB68,BB69,BB70 1 [???..???) (return) internal ----------------------------------------------------------------------------------------------------------------------------------------- Compacting blocks BB10 and BB11: *************** In fgDebugCheckBBlist Compacting blocks BB21 and BB22: *************** In fgDebugCheckBBlist Compacting blocks BB32 and BB33: *************** In fgDebugCheckBBlist Compacting blocks BB41 and BB42: *************** In fgDebugCheckBBlist Compacting blocks BB49 and BB50: *************** In fgDebugCheckBBlist After updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB03 [0002] 1 BB01 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i hascall gcsafe BB05 [0004] 2 BB03,BB04 1 [01E..04B)-> BB07 ( cond ) i BB06 [0052] 1 BB05 1 [01E..01F) i hascall gcsafe BB07 [0053] 2 BB05,BB06 1 [01E..034)-> BB09 ( cond ) i BB08 [0057] 1 BB07 1 [033..034) i hascall gcsafe BB09 [0058] 2 BB07,BB08 1 [033..034)-> BB15 ( cond ) i BB10 [0005] 1 BB09 1 [04B..???)-> BB13 ( cond ) i hascall gcsafe BB12 [0097] 1 BB10 0.50 [???..???)-> BB14 (always) i BB13 [0096] 1 BB10 0.50 [???..???) i BB14 [0094] 2 BB12,BB13 1 [???..054)-> BB16 (always) i hascall gcsafe BB15 [0006] 1 BB09 1 [054..061) i hascall gcsafe BB16 [0007] 2 BB14,BB15 1 [061..07A)-> BB18 ( cond ) i idxlen BB17 [0064] 1 BB16 1 [064..065) i hascall gcsafe BB18 [0065] 2 BB16,BB17 1 [064..065)-> BB20 ( cond ) i idxlen BB19 [0069] 1 BB18 1 [064..065) i hascall gcsafe BB20 [0070] 2 BB18,BB19 1 [064..065)-> BB39 ( cond ) i idxlen BB21 [0008] 1 BB20 1 [07A..???)-> BB24 ( cond ) i hascall gcsafe BB23 [0101] 1 BB21 0.50 [???..???)-> BB25 (always) i BB24 [0100] 1 BB21 0.50 [???..???) i BB25 [0098] 2 BB23,BB24 1 [???..106) i hascall gcsafe BB26 [0020] 2 BB25,BB37 1 [106..110)-> BB57 ( cond ) i idxlen bwd bwd-target BB27 [0021] 1 BB26 1 [110..120)-> BB37 ( cond ) i idxlen bwd BB28 [0022] 1 BB27 1 [120..137)-> BB37 ( cond ) i hascall gcsafe idxlen bwd BB29 [0023] 1 BB28 1 [137..13B)-> BB31 ( cond ) i bwd BB30 [0024] 1 BB29 1 [13B..14B)-> BB71 (always) i idxlen BB31 [0025] 1 BB29 1 [14B..14F)-> BB54 ( cond ) i bwd BB32 [0026] 1 BB31 0 [14F..???)-> BB35 ( cond ) i rare hascall gcsafe bwd BB34 [0105] 1 BB32 0 [???..???)-> BB36 (always) i rare BB35 [0104] 1 BB32 0 [???..???) i rare BB36 [0102] 2 BB34,BB35 0 [???..157) (throw ) i rare hascall gcsafe bwd BB37 [0028] 2 BB27,BB28 1 [157..170)-> BB26 ( cond ) i idxlen bwd BB38 [0093] 1 BB37 1 [???..???)-> BB56 (always) internal BB39 [0030] 2 BB20,BB55 1 [177..17E)-> BB57 ( cond ) i idxlen bwd bwd-target BB40 [0031] 1 BB39 1 [17E..18E)-> BB55 ( cond ) i idxlen bwd BB41 [0032] 1 BB40 1 [18E..???)-> BB44 ( cond ) i hascall gcsafe idxlen bwd BB43 [0109] 1 BB41 0.50 [???..???)-> BB45 (always) i BB44 [0108] 1 BB41 0.50 [???..???) i BB45 [0106] 2 BB43,BB44 1 [???..1A4)-> BB55 ( cond ) i hascall gcsafe idxlen bwd BB46 [0033] 1 BB45 1 [1A4..1A8)-> BB48 ( cond ) i bwd BB47 [0034] 1 BB46 1 [1A8..1B8)-> BB71 (always) i idxlen BB48 [0035] 1 BB46 1 [1B8..1BC)-> BB54 ( cond ) i bwd BB49 [0036] 1 BB48 0 [1BC..???)-> BB52 ( cond ) i rare hascall gcsafe bwd BB51 [0113] 1 BB49 0 [???..???)-> BB53 (always) i rare BB52 [0112] 1 BB49 0 [???..???) i rare BB53 [0110] 2 BB51,BB52 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB54 [0092] 2 BB31,BB48 1 [???..???) (return) internal BB55 [0038] 2 BB40,BB45 1 [1C4..1DD)-> BB39 ( cond ) i idxlen bwd BB56 [0039] 2 BB38,BB55 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd BB57 [0040] 2 BB26,BB39 1 [1E4..1ED)-> BB61 ( cond ) i BB58 [0041] 1 BB57 1 [1ED..243)-> BB60 ( cond ) i idxlen BB59 [0075] 1 BB58 1 [1F5..1F6) i hascall gcsafe BB60 [0076] 2 BB58,BB59 1 [1F5..1F6)-> BB68 (always) i idxlen BB61 [0042] 1 BB57 1 [243..252)-> BB67 ( cond ) i idxlen BB62 [0043] 1 BB61 1 [252..261)-> BB64 ( cond ) i hascall gcsafe idxlen BB63 [0083] 1 BB62 1 [258..259) i hascall gcsafe BB64 [0084] 2 BB62,BB63 1 [258..259)-> BB66 ( cond ) i idxlen BB65 [0088] 1 BB64 1 [258..259) i hascall gcsafe BB66 [0089] 2 BB64,BB65 1 [258..259) i idxlen BB67 [0044] 2 BB61,BB66 1 [261..276) i BB68 [0045] 2 BB60,BB67 1 [276..2CF)-> BB71 ( cond ) i idxlen BB69 [0047] 1 BB68 1 [2CF..2D7)-> BB71 ( cond ) i hascall BB70 [0048] 1 BB69 1 [2D7..2E3) i hascall gcsafe idxlen BB71 [0091] 5 BB30,BB47,BB68,BB69,BB70 1 [???..???) (return) internal ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In fgExpandRarelyRunBlocks() Unconditional jump to a rarely run block, marking BB38 as rarely run *************** In fgReorderBlocks() Initial BasicBlocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB03 [0002] 1 BB01 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i hascall gcsafe BB05 [0004] 2 BB03,BB04 1 [01E..04B)-> BB07 ( cond ) i BB06 [0052] 1 BB05 1 [01E..01F) i hascall gcsafe BB07 [0053] 2 BB05,BB06 1 [01E..034)-> BB09 ( cond ) i BB08 [0057] 1 BB07 1 [033..034) i hascall gcsafe BB09 [0058] 2 BB07,BB08 1 [033..034)-> BB15 ( cond ) i BB10 [0005] 1 BB09 1 [04B..???)-> BB13 ( cond ) i hascall gcsafe BB12 [0097] 1 BB10 0.50 [???..???)-> BB14 (always) i BB13 [0096] 1 BB10 0.50 [???..???) i BB14 [0094] 2 BB12,BB13 1 [???..054)-> BB16 (always) i hascall gcsafe BB15 [0006] 1 BB09 1 [054..061) i hascall gcsafe BB16 [0007] 2 BB14,BB15 1 [061..07A)-> BB18 ( cond ) i idxlen BB17 [0064] 1 BB16 1 [064..065) i hascall gcsafe BB18 [0065] 2 BB16,BB17 1 [064..065)-> BB20 ( cond ) i idxlen BB19 [0069] 1 BB18 1 [064..065) i hascall gcsafe BB20 [0070] 2 BB18,BB19 1 [064..065)-> BB39 ( cond ) i idxlen BB21 [0008] 1 BB20 1 [07A..???)-> BB24 ( cond ) i hascall gcsafe BB23 [0101] 1 BB21 0.50 [???..???)-> BB25 (always) i BB24 [0100] 1 BB21 0.50 [???..???) i BB25 [0098] 2 BB23,BB24 1 [???..106) i hascall gcsafe BB26 [0020] 2 BB25,BB37 1 [106..110)-> BB57 ( cond ) i idxlen bwd bwd-target BB27 [0021] 1 BB26 1 [110..120)-> BB37 ( cond ) i idxlen bwd BB28 [0022] 1 BB27 1 [120..137)-> BB37 ( cond ) i hascall gcsafe idxlen bwd BB29 [0023] 1 BB28 1 [137..13B)-> BB31 ( cond ) i bwd BB30 [0024] 1 BB29 1 [13B..14B)-> BB71 (always) i idxlen BB31 [0025] 1 BB29 1 [14B..14F)-> BB54 ( cond ) i bwd BB32 [0026] 1 BB31 0 [14F..???)-> BB35 ( cond ) i rare hascall gcsafe bwd BB34 [0105] 1 BB32 0 [???..???)-> BB36 (always) i rare BB35 [0104] 1 BB32 0 [???..???) i rare BB36 [0102] 2 BB34,BB35 0 [???..157) (throw ) i rare hascall gcsafe bwd BB37 [0028] 2 BB27,BB28 1 [157..170)-> BB26 ( cond ) i idxlen bwd BB38 [0093] 1 BB37 0 [???..???)-> BB56 (always) internal rare BB39 [0030] 2 BB20,BB55 1 [177..17E)-> BB57 ( cond ) i idxlen bwd bwd-target BB40 [0031] 1 BB39 1 [17E..18E)-> BB55 ( cond ) i idxlen bwd BB41 [0032] 1 BB40 1 [18E..???)-> BB44 ( cond ) i hascall gcsafe idxlen bwd BB43 [0109] 1 BB41 0.50 [???..???)-> BB45 (always) i BB44 [0108] 1 BB41 0.50 [???..???) i BB45 [0106] 2 BB43,BB44 1 [???..1A4)-> BB55 ( cond ) i hascall gcsafe idxlen bwd BB46 [0033] 1 BB45 1 [1A4..1A8)-> BB48 ( cond ) i bwd BB47 [0034] 1 BB46 1 [1A8..1B8)-> BB71 (always) i idxlen BB48 [0035] 1 BB46 1 [1B8..1BC)-> BB54 ( cond ) i bwd BB49 [0036] 1 BB48 0 [1BC..???)-> BB52 ( cond ) i rare hascall gcsafe bwd BB51 [0113] 1 BB49 0 [???..???)-> BB53 (always) i rare BB52 [0112] 1 BB49 0 [???..???) i rare BB53 [0110] 2 BB51,BB52 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB54 [0092] 2 BB31,BB48 1 [???..???) (return) internal BB55 [0038] 2 BB40,BB45 1 [1C4..1DD)-> BB39 ( cond ) i idxlen bwd BB56 [0039] 2 BB38,BB55 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd BB57 [0040] 2 BB26,BB39 1 [1E4..1ED)-> BB61 ( cond ) i BB58 [0041] 1 BB57 1 [1ED..243)-> BB60 ( cond ) i idxlen BB59 [0075] 1 BB58 1 [1F5..1F6) i hascall gcsafe BB60 [0076] 2 BB58,BB59 1 [1F5..1F6)-> BB68 (always) i idxlen BB61 [0042] 1 BB57 1 [243..252)-> BB67 ( cond ) i idxlen BB62 [0043] 1 BB61 1 [252..261)-> BB64 ( cond ) i hascall gcsafe idxlen BB63 [0083] 1 BB62 1 [258..259) i hascall gcsafe BB64 [0084] 2 BB62,BB63 1 [258..259)-> BB66 ( cond ) i idxlen BB65 [0088] 1 BB64 1 [258..259) i hascall gcsafe BB66 [0089] 2 BB64,BB65 1 [258..259) i idxlen BB67 [0044] 2 BB61,BB66 1 [261..276) i BB68 [0045] 2 BB60,BB67 1 [276..2CF)-> BB71 ( cond ) i idxlen BB69 [0047] 1 BB68 1 [2CF..2D7)-> BB71 ( cond ) i hascall BB70 [0048] 1 BB69 1 [2D7..2E3) i hascall gcsafe idxlen BB71 [0091] 5 BB30,BB47,BB68,BB69,BB70 1 [???..???) (return) internal ----------------------------------------------------------------------------------------------------------------------------------------- Decided to reverse conditional branch at block BB01 branch to BB03 since it falls into a rarely run block Relocated rarely run block BB02 by reversing conditional jump at BB01 Relocated block [BB02..BB02] inserted after BB71 at the end of method After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB02 ( cond ) i BB03 [0002] 1 BB01 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i hascall gcsafe BB05 [0004] 2 BB03,BB04 1 [01E..04B)-> BB07 ( cond ) i BB06 [0052] 1 BB05 1 [01E..01F) i hascall gcsafe BB07 [0053] 2 BB05,BB06 1 [01E..034)-> BB09 ( cond ) i BB08 [0057] 1 BB07 1 [033..034) i hascall gcsafe BB09 [0058] 2 BB07,BB08 1 [033..034)-> BB15 ( cond ) i BB10 [0005] 1 BB09 1 [04B..???)-> BB13 ( cond ) i hascall gcsafe BB12 [0097] 1 BB10 0.50 [???..???)-> BB14 (always) i BB13 [0096] 1 BB10 0.50 [???..???) i BB14 [0094] 2 BB12,BB13 1 [???..054)-> BB16 (always) i hascall gcsafe BB15 [0006] 1 BB09 1 [054..061) i hascall gcsafe BB16 [0007] 2 BB14,BB15 1 [061..07A)-> BB18 ( cond ) i idxlen BB17 [0064] 1 BB16 1 [064..065) i hascall gcsafe BB18 [0065] 2 BB16,BB17 1 [064..065)-> BB20 ( cond ) i idxlen BB19 [0069] 1 BB18 1 [064..065) i hascall gcsafe BB20 [0070] 2 BB18,BB19 1 [064..065)-> BB39 ( cond ) i idxlen BB21 [0008] 1 BB20 1 [07A..???)-> BB24 ( cond ) i hascall gcsafe BB23 [0101] 1 BB21 0.50 [???..???)-> BB25 (always) i BB24 [0100] 1 BB21 0.50 [???..???) i BB25 [0098] 2 BB23,BB24 1 [???..106) i hascall gcsafe BB26 [0020] 2 BB25,BB37 1 [106..110)-> BB57 ( cond ) i idxlen bwd bwd-target BB27 [0021] 1 BB26 1 [110..120)-> BB37 ( cond ) i idxlen bwd BB28 [0022] 1 BB27 1 [120..137)-> BB37 ( cond ) i hascall gcsafe idxlen bwd BB29 [0023] 1 BB28 1 [137..13B)-> BB31 ( cond ) i bwd BB30 [0024] 1 BB29 1 [13B..14B)-> BB71 (always) i idxlen BB31 [0025] 1 BB29 1 [14B..14F)-> BB54 ( cond ) i bwd BB32 [0026] 1 BB31 0 [14F..???)-> BB35 ( cond ) i rare hascall gcsafe bwd BB34 [0105] 1 BB32 0 [???..???)-> BB36 (always) i rare BB35 [0104] 1 BB32 0 [???..???) i rare BB36 [0102] 2 BB34,BB35 0 [???..157) (throw ) i rare hascall gcsafe bwd BB37 [0028] 2 BB27,BB28 1 [157..170)-> BB26 ( cond ) i idxlen bwd BB38 [0093] 1 BB37 0 [???..???)-> BB56 (always) internal rare BB39 [0030] 2 BB20,BB55 1 [177..17E)-> BB57 ( cond ) i idxlen bwd bwd-target BB40 [0031] 1 BB39 1 [17E..18E)-> BB55 ( cond ) i idxlen bwd BB41 [0032] 1 BB40 1 [18E..???)-> BB44 ( cond ) i hascall gcsafe idxlen bwd BB43 [0109] 1 BB41 0.50 [???..???)-> BB45 (always) i BB44 [0108] 1 BB41 0.50 [???..???) i BB45 [0106] 2 BB43,BB44 1 [???..1A4)-> BB55 ( cond ) i hascall gcsafe idxlen bwd BB46 [0033] 1 BB45 1 [1A4..1A8)-> BB48 ( cond ) i bwd BB47 [0034] 1 BB46 1 [1A8..1B8)-> BB71 (always) i idxlen BB48 [0035] 1 BB46 1 [1B8..1BC)-> BB54 ( cond ) i bwd BB49 [0036] 1 BB48 0 [1BC..???)-> BB52 ( cond ) i rare hascall gcsafe bwd BB51 [0113] 1 BB49 0 [???..???)-> BB53 (always) i rare BB52 [0112] 1 BB49 0 [???..???) i rare BB53 [0110] 2 BB51,BB52 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB54 [0092] 2 BB31,BB48 1 [???..???) (return) internal BB55 [0038] 2 BB40,BB45 1 [1C4..1DD)-> BB39 ( cond ) i idxlen bwd BB56 [0039] 2 BB38,BB55 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd BB57 [0040] 2 BB26,BB39 1 [1E4..1ED)-> BB61 ( cond ) i BB58 [0041] 1 BB57 1 [1ED..243)-> BB60 ( cond ) i idxlen BB59 [0075] 1 BB58 1 [1F5..1F6) i hascall gcsafe BB60 [0076] 2 BB58,BB59 1 [1F5..1F6)-> BB68 (always) i idxlen BB61 [0042] 1 BB57 1 [243..252)-> BB67 ( cond ) i idxlen BB62 [0043] 1 BB61 1 [252..261)-> BB64 ( cond ) i hascall gcsafe idxlen BB63 [0083] 1 BB62 1 [258..259) i hascall gcsafe BB64 [0084] 2 BB62,BB63 1 [258..259)-> BB66 ( cond ) i idxlen BB65 [0088] 1 BB64 1 [258..259) i hascall gcsafe BB66 [0089] 2 BB64,BB65 1 [258..259) i idxlen BB67 [0044] 2 BB61,BB66 1 [261..276) i BB68 [0045] 2 BB60,BB67 1 [276..2CF)-> BB71 ( cond ) i idxlen BB69 [0047] 1 BB68 1 [2CF..2D7)-> BB71 ( cond ) i hascall BB70 [0048] 1 BB69 1 [2D7..2E3) i hascall gcsafe idxlen BB71 [0091] 5 BB30,BB47,BB68,BB69,BB70 1 [???..???) (return) internal BB02 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- Decided to reverse conditional branch at block BB31 branch to BB54 since it falls into a rarely run block Relocated hot block BB54 by reversing conditional jump at BB31 Relocated block [BB54..BB54] inserted after BB31 After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB02 ( cond ) i BB03 [0002] 1 BB01 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i hascall gcsafe BB05 [0004] 2 BB03,BB04 1 [01E..04B)-> BB07 ( cond ) i BB06 [0052] 1 BB05 1 [01E..01F) i hascall gcsafe BB07 [0053] 2 BB05,BB06 1 [01E..034)-> BB09 ( cond ) i BB08 [0057] 1 BB07 1 [033..034) i hascall gcsafe BB09 [0058] 2 BB07,BB08 1 [033..034)-> BB15 ( cond ) i BB10 [0005] 1 BB09 1 [04B..???)-> BB13 ( cond ) i hascall gcsafe BB12 [0097] 1 BB10 0.50 [???..???)-> BB14 (always) i BB13 [0096] 1 BB10 0.50 [???..???) i BB14 [0094] 2 BB12,BB13 1 [???..054)-> BB16 (always) i hascall gcsafe BB15 [0006] 1 BB09 1 [054..061) i hascall gcsafe BB16 [0007] 2 BB14,BB15 1 [061..07A)-> BB18 ( cond ) i idxlen BB17 [0064] 1 BB16 1 [064..065) i hascall gcsafe BB18 [0065] 2 BB16,BB17 1 [064..065)-> BB20 ( cond ) i idxlen BB19 [0069] 1 BB18 1 [064..065) i hascall gcsafe BB20 [0070] 2 BB18,BB19 1 [064..065)-> BB39 ( cond ) i idxlen BB21 [0008] 1 BB20 1 [07A..???)-> BB24 ( cond ) i hascall gcsafe BB23 [0101] 1 BB21 0.50 [???..???)-> BB25 (always) i BB24 [0100] 1 BB21 0.50 [???..???) i BB25 [0098] 2 BB23,BB24 1 [???..106) i hascall gcsafe BB26 [0020] 2 BB25,BB37 1 [106..110)-> BB57 ( cond ) i idxlen bwd bwd-target BB27 [0021] 1 BB26 1 [110..120)-> BB37 ( cond ) i idxlen bwd BB28 [0022] 1 BB27 1 [120..137)-> BB37 ( cond ) i hascall gcsafe idxlen bwd BB29 [0023] 1 BB28 1 [137..13B)-> BB31 ( cond ) i bwd BB30 [0024] 1 BB29 1 [13B..14B)-> BB71 (always) i idxlen BB31 [0025] 1 BB29 1 [14B..14F)-> BB32 ( cond ) i bwd BB54 [0092] 2 BB31,BB48 1 [???..???) (return) internal BB32 [0026] 1 BB31 0 [14F..???)-> BB35 ( cond ) i rare hascall gcsafe bwd BB34 [0105] 1 BB32 0 [???..???)-> BB36 (always) i rare BB35 [0104] 1 BB32 0 [???..???) i rare BB36 [0102] 2 BB34,BB35 0 [???..157) (throw ) i rare hascall gcsafe bwd BB37 [0028] 2 BB27,BB28 1 [157..170)-> BB26 ( cond ) i idxlen bwd BB38 [0093] 1 BB37 0 [???..???)-> BB56 (always) internal rare BB39 [0030] 2 BB20,BB55 1 [177..17E)-> BB57 ( cond ) i idxlen bwd bwd-target BB40 [0031] 1 BB39 1 [17E..18E)-> BB55 ( cond ) i idxlen bwd BB41 [0032] 1 BB40 1 [18E..???)-> BB44 ( cond ) i hascall gcsafe idxlen bwd BB43 [0109] 1 BB41 0.50 [???..???)-> BB45 (always) i BB44 [0108] 1 BB41 0.50 [???..???) i BB45 [0106] 2 BB43,BB44 1 [???..1A4)-> BB55 ( cond ) i hascall gcsafe idxlen bwd BB46 [0033] 1 BB45 1 [1A4..1A8)-> BB48 ( cond ) i bwd BB47 [0034] 1 BB46 1 [1A8..1B8)-> BB71 (always) i idxlen BB48 [0035] 1 BB46 1 [1B8..1BC)-> BB54 ( cond ) i bwd BB49 [0036] 1 BB48 0 [1BC..???)-> BB52 ( cond ) i rare hascall gcsafe bwd BB51 [0113] 1 BB49 0 [???..???)-> BB53 (always) i rare BB52 [0112] 1 BB49 0 [???..???) i rare BB53 [0110] 2 BB51,BB52 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB55 [0038] 2 BB40,BB45 1 [1C4..1DD)-> BB39 ( cond ) i idxlen bwd BB56 [0039] 2 BB38,BB55 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd BB57 [0040] 2 BB26,BB39 1 [1E4..1ED)-> BB61 ( cond ) i BB58 [0041] 1 BB57 1 [1ED..243)-> BB60 ( cond ) i idxlen BB59 [0075] 1 BB58 1 [1F5..1F6) i hascall gcsafe BB60 [0076] 2 BB58,BB59 1 [1F5..1F6)-> BB68 (always) i idxlen BB61 [0042] 1 BB57 1 [243..252)-> BB67 ( cond ) i idxlen BB62 [0043] 1 BB61 1 [252..261)-> BB64 ( cond ) i hascall gcsafe idxlen BB63 [0083] 1 BB62 1 [258..259) i hascall gcsafe BB64 [0084] 2 BB62,BB63 1 [258..259)-> BB66 ( cond ) i idxlen BB65 [0088] 1 BB64 1 [258..259) i hascall gcsafe BB66 [0089] 2 BB64,BB65 1 [258..259) i idxlen BB67 [0044] 2 BB61,BB66 1 [261..276) i BB68 [0045] 2 BB60,BB67 1 [276..2CF)-> BB71 ( cond ) i idxlen BB69 [0047] 1 BB68 1 [2CF..2D7)-> BB71 ( cond ) i hascall BB70 [0048] 1 BB69 1 [2D7..2E3) i hascall gcsafe idxlen BB71 [0091] 5 BB30,BB47,BB68,BB69,BB70 1 [???..???) (return) internal BB02 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- Decided to relocate block(s) after block BB54 since they are rarely run block(s) Relocated rarely run blocks (BB32 .. BB36) Relocated blocks [BB32..BB36] inserted after BB02 at the end of method After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB02 ( cond ) i BB03 [0002] 1 BB01 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i hascall gcsafe BB05 [0004] 2 BB03,BB04 1 [01E..04B)-> BB07 ( cond ) i BB06 [0052] 1 BB05 1 [01E..01F) i hascall gcsafe BB07 [0053] 2 BB05,BB06 1 [01E..034)-> BB09 ( cond ) i BB08 [0057] 1 BB07 1 [033..034) i hascall gcsafe BB09 [0058] 2 BB07,BB08 1 [033..034)-> BB15 ( cond ) i BB10 [0005] 1 BB09 1 [04B..???)-> BB13 ( cond ) i hascall gcsafe BB12 [0097] 1 BB10 0.50 [???..???)-> BB14 (always) i BB13 [0096] 1 BB10 0.50 [???..???) i BB14 [0094] 2 BB12,BB13 1 [???..054)-> BB16 (always) i hascall gcsafe BB15 [0006] 1 BB09 1 [054..061) i hascall gcsafe BB16 [0007] 2 BB14,BB15 1 [061..07A)-> BB18 ( cond ) i idxlen BB17 [0064] 1 BB16 1 [064..065) i hascall gcsafe BB18 [0065] 2 BB16,BB17 1 [064..065)-> BB20 ( cond ) i idxlen BB19 [0069] 1 BB18 1 [064..065) i hascall gcsafe BB20 [0070] 2 BB18,BB19 1 [064..065)-> BB39 ( cond ) i idxlen BB21 [0008] 1 BB20 1 [07A..???)-> BB24 ( cond ) i hascall gcsafe BB23 [0101] 1 BB21 0.50 [???..???)-> BB25 (always) i BB24 [0100] 1 BB21 0.50 [???..???) i BB25 [0098] 2 BB23,BB24 1 [???..106) i hascall gcsafe BB26 [0020] 2 BB25,BB37 1 [106..110)-> BB57 ( cond ) i idxlen bwd bwd-target BB27 [0021] 1 BB26 1 [110..120)-> BB37 ( cond ) i idxlen bwd BB28 [0022] 1 BB27 1 [120..137)-> BB37 ( cond ) i hascall gcsafe idxlen bwd BB29 [0023] 1 BB28 1 [137..13B)-> BB31 ( cond ) i bwd BB30 [0024] 1 BB29 1 [13B..14B)-> BB71 (always) i idxlen BB31 [0025] 1 BB29 1 [14B..14F)-> BB32 ( cond ) i bwd BB54 [0092] 2 BB31,BB48 1 [???..???) (return) internal BB37 [0028] 2 BB27,BB28 1 [157..170)-> BB26 ( cond ) i idxlen bwd BB38 [0093] 1 BB37 0 [???..???)-> BB56 (always) internal rare BB39 [0030] 2 BB20,BB55 1 [177..17E)-> BB57 ( cond ) i idxlen bwd bwd-target BB40 [0031] 1 BB39 1 [17E..18E)-> BB55 ( cond ) i idxlen bwd BB41 [0032] 1 BB40 1 [18E..???)-> BB44 ( cond ) i hascall gcsafe idxlen bwd BB43 [0109] 1 BB41 0.50 [???..???)-> BB45 (always) i BB44 [0108] 1 BB41 0.50 [???..???) i BB45 [0106] 2 BB43,BB44 1 [???..1A4)-> BB55 ( cond ) i hascall gcsafe idxlen bwd BB46 [0033] 1 BB45 1 [1A4..1A8)-> BB48 ( cond ) i bwd BB47 [0034] 1 BB46 1 [1A8..1B8)-> BB71 (always) i idxlen BB48 [0035] 1 BB46 1 [1B8..1BC)-> BB54 ( cond ) i bwd BB49 [0036] 1 BB48 0 [1BC..???)-> BB52 ( cond ) i rare hascall gcsafe bwd BB51 [0113] 1 BB49 0 [???..???)-> BB53 (always) i rare BB52 [0112] 1 BB49 0 [???..???) i rare BB53 [0110] 2 BB51,BB52 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB55 [0038] 2 BB40,BB45 1 [1C4..1DD)-> BB39 ( cond ) i idxlen bwd BB56 [0039] 2 BB38,BB55 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd BB57 [0040] 2 BB26,BB39 1 [1E4..1ED)-> BB61 ( cond ) i BB58 [0041] 1 BB57 1 [1ED..243)-> BB60 ( cond ) i idxlen BB59 [0075] 1 BB58 1 [1F5..1F6) i hascall gcsafe BB60 [0076] 2 BB58,BB59 1 [1F5..1F6)-> BB68 (always) i idxlen BB61 [0042] 1 BB57 1 [243..252)-> BB67 ( cond ) i idxlen BB62 [0043] 1 BB61 1 [252..261)-> BB64 ( cond ) i hascall gcsafe idxlen BB63 [0083] 1 BB62 1 [258..259) i hascall gcsafe BB64 [0084] 2 BB62,BB63 1 [258..259)-> BB66 ( cond ) i idxlen BB65 [0088] 1 BB64 1 [258..259) i hascall gcsafe BB66 [0089] 2 BB64,BB65 1 [258..259) i idxlen BB67 [0044] 2 BB61,BB66 1 [261..276) i BB68 [0045] 2 BB60,BB67 1 [276..2CF)-> BB71 ( cond ) i idxlen BB69 [0047] 1 BB68 1 [2CF..2D7)-> BB71 ( cond ) i hascall BB70 [0048] 1 BB69 1 [2D7..2E3) i hascall gcsafe idxlen BB71 [0091] 5 BB30,BB47,BB68,BB69,BB70 1 [???..???) (return) internal BB02 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB32 [0026] 1 BB31 0 [14F..???)-> BB35 ( cond ) i rare hascall gcsafe bwd BB34 [0105] 1 BB32 0 [???..???)-> BB36 (always) i rare BB35 [0104] 1 BB32 0 [???..???) i rare BB36 [0102] 2 BB34,BB35 0 [???..157) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- Decided to reverse conditional branch at block BB37 branch to BB26 since it falls into a rarely run block Relocated rarely run block BB38 by reversing conditional jump at BB37 Relocated block [BB38..BB38] inserted after BB36 at the end of method New Basic Block BB72 [0114] created. Setting edge weights for BB37 -> BB72 to [0 .. 3.402823e+38] Added an unconditional jump to BB26 after block BB37 After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB02 ( cond ) i BB03 [0002] 1 BB01 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i hascall gcsafe BB05 [0004] 2 BB03,BB04 1 [01E..04B)-> BB07 ( cond ) i BB06 [0052] 1 BB05 1 [01E..01F) i hascall gcsafe BB07 [0053] 2 BB05,BB06 1 [01E..034)-> BB09 ( cond ) i BB08 [0057] 1 BB07 1 [033..034) i hascall gcsafe BB09 [0058] 2 BB07,BB08 1 [033..034)-> BB15 ( cond ) i BB10 [0005] 1 BB09 1 [04B..???)-> BB13 ( cond ) i hascall gcsafe BB12 [0097] 1 BB10 0.50 [???..???)-> BB14 (always) i BB13 [0096] 1 BB10 0.50 [???..???) i BB14 [0094] 2 BB12,BB13 1 [???..054)-> BB16 (always) i hascall gcsafe BB15 [0006] 1 BB09 1 [054..061) i hascall gcsafe BB16 [0007] 2 BB14,BB15 1 [061..07A)-> BB18 ( cond ) i idxlen BB17 [0064] 1 BB16 1 [064..065) i hascall gcsafe BB18 [0065] 2 BB16,BB17 1 [064..065)-> BB20 ( cond ) i idxlen BB19 [0069] 1 BB18 1 [064..065) i hascall gcsafe BB20 [0070] 2 BB18,BB19 1 [064..065)-> BB39 ( cond ) i idxlen BB21 [0008] 1 BB20 1 [07A..???)-> BB24 ( cond ) i hascall gcsafe BB23 [0101] 1 BB21 0.50 [???..???)-> BB25 (always) i BB24 [0100] 1 BB21 0.50 [???..???) i BB25 [0098] 2 BB23,BB24 1 [???..106) i hascall gcsafe BB26 [0020] 2 BB25,BB72 1 [106..110)-> BB57 ( cond ) i idxlen bwd bwd-target BB27 [0021] 1 BB26 1 [110..120)-> BB37 ( cond ) i idxlen bwd BB28 [0022] 1 BB27 1 [120..137)-> BB37 ( cond ) i hascall gcsafe idxlen bwd BB29 [0023] 1 BB28 1 [137..13B)-> BB31 ( cond ) i bwd BB30 [0024] 1 BB29 1 [13B..14B)-> BB71 (always) i idxlen BB31 [0025] 1 BB29 1 [14B..14F)-> BB32 ( cond ) i bwd BB54 [0092] 2 BB31,BB48 1 [???..???) (return) internal BB37 [0028] 2 BB27,BB28 1 [157..170)-> BB38 ( cond ) i idxlen bwd BB72 [0114] 1 BB37 1 [???..???)-> BB26 (always) internal BB39 [0030] 2 BB20,BB55 1 [177..17E)-> BB57 ( cond ) i idxlen bwd bwd-target BB40 [0031] 1 BB39 1 [17E..18E)-> BB55 ( cond ) i idxlen bwd BB41 [0032] 1 BB40 1 [18E..???)-> BB44 ( cond ) i hascall gcsafe idxlen bwd BB43 [0109] 1 BB41 0.50 [???..???)-> BB45 (always) i BB44 [0108] 1 BB41 0.50 [???..???) i BB45 [0106] 2 BB43,BB44 1 [???..1A4)-> BB55 ( cond ) i hascall gcsafe idxlen bwd BB46 [0033] 1 BB45 1 [1A4..1A8)-> BB48 ( cond ) i bwd BB47 [0034] 1 BB46 1 [1A8..1B8)-> BB71 (always) i idxlen BB48 [0035] 1 BB46 1 [1B8..1BC)-> BB54 ( cond ) i bwd BB49 [0036] 1 BB48 0 [1BC..???)-> BB52 ( cond ) i rare hascall gcsafe bwd BB51 [0113] 1 BB49 0 [???..???)-> BB53 (always) i rare BB52 [0112] 1 BB49 0 [???..???) i rare BB53 [0110] 2 BB51,BB52 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB55 [0038] 2 BB40,BB45 1 [1C4..1DD)-> BB39 ( cond ) i idxlen bwd BB56 [0039] 2 BB38,BB55 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd BB57 [0040] 2 BB26,BB39 1 [1E4..1ED)-> BB61 ( cond ) i BB58 [0041] 1 BB57 1 [1ED..243)-> BB60 ( cond ) i idxlen BB59 [0075] 1 BB58 1 [1F5..1F6) i hascall gcsafe BB60 [0076] 2 BB58,BB59 1 [1F5..1F6)-> BB68 (always) i idxlen BB61 [0042] 1 BB57 1 [243..252)-> BB67 ( cond ) i idxlen BB62 [0043] 1 BB61 1 [252..261)-> BB64 ( cond ) i hascall gcsafe idxlen BB63 [0083] 1 BB62 1 [258..259) i hascall gcsafe BB64 [0084] 2 BB62,BB63 1 [258..259)-> BB66 ( cond ) i idxlen BB65 [0088] 1 BB64 1 [258..259) i hascall gcsafe BB66 [0089] 2 BB64,BB65 1 [258..259) i idxlen BB67 [0044] 2 BB61,BB66 1 [261..276) i BB68 [0045] 2 BB60,BB67 1 [276..2CF)-> BB71 ( cond ) i idxlen BB69 [0047] 1 BB68 1 [2CF..2D7)-> BB71 ( cond ) i hascall BB70 [0048] 1 BB69 1 [2D7..2E3) i hascall gcsafe idxlen BB71 [0091] 5 BB30,BB47,BB68,BB69,BB70 1 [???..???) (return) internal BB02 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB32 [0026] 1 BB31 0 [14F..???)-> BB35 ( cond ) i rare hascall gcsafe bwd BB34 [0105] 1 BB32 0 [???..???)-> BB36 (always) i rare BB35 [0104] 1 BB32 0 [???..???) i rare BB36 [0102] 2 BB34,BB35 0 [???..157) (throw ) i rare hascall gcsafe bwd BB38 [0093] 1 BB37 0 [???..???)-> BB56 (always) internal rare ----------------------------------------------------------------------------------------------------------------------------------------- Decided to reverse conditional branch at block BB48 branch to BB54 since it falls into a rarely run block Relocated rarely run blocks (BB49 .. BB53) by reversing conditional jump at BB48 Relocated blocks [BB49..BB53] inserted after BB38 at the end of method New Basic Block BB73 [0115] created. Setting edge weights for BB48 -> BB73 to [0 .. 3.402823e+38] Added an unconditional jump to BB54 after block BB48 After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB02 ( cond ) i BB03 [0002] 1 BB01 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i hascall gcsafe BB05 [0004] 2 BB03,BB04 1 [01E..04B)-> BB07 ( cond ) i BB06 [0052] 1 BB05 1 [01E..01F) i hascall gcsafe BB07 [0053] 2 BB05,BB06 1 [01E..034)-> BB09 ( cond ) i BB08 [0057] 1 BB07 1 [033..034) i hascall gcsafe BB09 [0058] 2 BB07,BB08 1 [033..034)-> BB15 ( cond ) i BB10 [0005] 1 BB09 1 [04B..???)-> BB13 ( cond ) i hascall gcsafe BB12 [0097] 1 BB10 0.50 [???..???)-> BB14 (always) i BB13 [0096] 1 BB10 0.50 [???..???) i BB14 [0094] 2 BB12,BB13 1 [???..054)-> BB16 (always) i hascall gcsafe BB15 [0006] 1 BB09 1 [054..061) i hascall gcsafe BB16 [0007] 2 BB14,BB15 1 [061..07A)-> BB18 ( cond ) i idxlen BB17 [0064] 1 BB16 1 [064..065) i hascall gcsafe BB18 [0065] 2 BB16,BB17 1 [064..065)-> BB20 ( cond ) i idxlen BB19 [0069] 1 BB18 1 [064..065) i hascall gcsafe BB20 [0070] 2 BB18,BB19 1 [064..065)-> BB39 ( cond ) i idxlen BB21 [0008] 1 BB20 1 [07A..???)-> BB24 ( cond ) i hascall gcsafe BB23 [0101] 1 BB21 0.50 [???..???)-> BB25 (always) i BB24 [0100] 1 BB21 0.50 [???..???) i BB25 [0098] 2 BB23,BB24 1 [???..106) i hascall gcsafe BB26 [0020] 2 BB25,BB72 1 [106..110)-> BB57 ( cond ) i idxlen bwd bwd-target BB27 [0021] 1 BB26 1 [110..120)-> BB37 ( cond ) i idxlen bwd BB28 [0022] 1 BB27 1 [120..137)-> BB37 ( cond ) i hascall gcsafe idxlen bwd BB29 [0023] 1 BB28 1 [137..13B)-> BB31 ( cond ) i bwd BB30 [0024] 1 BB29 1 [13B..14B)-> BB71 (always) i idxlen BB31 [0025] 1 BB29 1 [14B..14F)-> BB32 ( cond ) i bwd BB54 [0092] 2 BB31,BB73 1 [???..???) (return) internal BB37 [0028] 2 BB27,BB28 1 [157..170)-> BB38 ( cond ) i idxlen bwd BB72 [0114] 1 BB37 1 [???..???)-> BB26 (always) internal BB39 [0030] 2 BB20,BB55 1 [177..17E)-> BB57 ( cond ) i idxlen bwd bwd-target BB40 [0031] 1 BB39 1 [17E..18E)-> BB55 ( cond ) i idxlen bwd BB41 [0032] 1 BB40 1 [18E..???)-> BB44 ( cond ) i hascall gcsafe idxlen bwd BB43 [0109] 1 BB41 0.50 [???..???)-> BB45 (always) i BB44 [0108] 1 BB41 0.50 [???..???) i BB45 [0106] 2 BB43,BB44 1 [???..1A4)-> BB55 ( cond ) i hascall gcsafe idxlen bwd BB46 [0033] 1 BB45 1 [1A4..1A8)-> BB48 ( cond ) i bwd BB47 [0034] 1 BB46 1 [1A8..1B8)-> BB71 (always) i idxlen BB48 [0035] 1 BB46 1 [1B8..1BC)-> BB49 ( cond ) i bwd BB73 [0115] 1 BB48 1 [???..???)-> BB54 (always) internal BB55 [0038] 2 BB40,BB45 1 [1C4..1DD)-> BB39 ( cond ) i idxlen bwd BB56 [0039] 2 BB38,BB55 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd BB57 [0040] 2 BB26,BB39 1 [1E4..1ED)-> BB61 ( cond ) i BB58 [0041] 1 BB57 1 [1ED..243)-> BB60 ( cond ) i idxlen BB59 [0075] 1 BB58 1 [1F5..1F6) i hascall gcsafe BB60 [0076] 2 BB58,BB59 1 [1F5..1F6)-> BB68 (always) i idxlen BB61 [0042] 1 BB57 1 [243..252)-> BB67 ( cond ) i idxlen BB62 [0043] 1 BB61 1 [252..261)-> BB64 ( cond ) i hascall gcsafe idxlen BB63 [0083] 1 BB62 1 [258..259) i hascall gcsafe BB64 [0084] 2 BB62,BB63 1 [258..259)-> BB66 ( cond ) i idxlen BB65 [0088] 1 BB64 1 [258..259) i hascall gcsafe BB66 [0089] 2 BB64,BB65 1 [258..259) i idxlen BB67 [0044] 2 BB61,BB66 1 [261..276) i BB68 [0045] 2 BB60,BB67 1 [276..2CF)-> BB71 ( cond ) i idxlen BB69 [0047] 1 BB68 1 [2CF..2D7)-> BB71 ( cond ) i hascall BB70 [0048] 1 BB69 1 [2D7..2E3) i hascall gcsafe idxlen BB71 [0091] 5 BB30,BB47,BB68,BB69,BB70 1 [???..???) (return) internal BB02 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB32 [0026] 1 BB31 0 [14F..???)-> BB35 ( cond ) i rare hascall gcsafe bwd BB34 [0105] 1 BB32 0 [???..???)-> BB36 (always) i rare BB35 [0104] 1 BB32 0 [???..???) i rare BB36 [0102] 2 BB34,BB35 0 [???..157) (throw ) i rare hascall gcsafe bwd BB38 [0093] 1 BB37 0 [???..???)-> BB56 (always) internal rare BB49 [0036] 1 BB48 0 [1BC..???)-> BB52 ( cond ) i rare hascall gcsafe bwd BB51 [0113] 1 BB49 0 [???..???)-> BB53 (always) i rare BB52 [0112] 1 BB49 0 [???..???) i rare BB53 [0110] 2 BB51,BB52 0 [???..1C4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- Decided to reverse conditional branch at block BB55 branch to BB39 since it falls into a rarely run block Relocated rarely run block BB56 by reversing conditional jump at BB55 Relocated block [BB56..BB56] inserted after BB53 at the end of method New Basic Block BB74 [0116] created. Setting edge weights for BB55 -> BB74 to [0 .. 3.402823e+38] Added an unconditional jump to BB39 after block BB55 After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB02 ( cond ) i BB03 [0002] 1 BB01 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i hascall gcsafe BB05 [0004] 2 BB03,BB04 1 [01E..04B)-> BB07 ( cond ) i BB06 [0052] 1 BB05 1 [01E..01F) i hascall gcsafe BB07 [0053] 2 BB05,BB06 1 [01E..034)-> BB09 ( cond ) i BB08 [0057] 1 BB07 1 [033..034) i hascall gcsafe BB09 [0058] 2 BB07,BB08 1 [033..034)-> BB15 ( cond ) i BB10 [0005] 1 BB09 1 [04B..???)-> BB13 ( cond ) i hascall gcsafe BB12 [0097] 1 BB10 0.50 [???..???)-> BB14 (always) i BB13 [0096] 1 BB10 0.50 [???..???) i BB14 [0094] 2 BB12,BB13 1 [???..054)-> BB16 (always) i hascall gcsafe BB15 [0006] 1 BB09 1 [054..061) i hascall gcsafe BB16 [0007] 2 BB14,BB15 1 [061..07A)-> BB18 ( cond ) i idxlen BB17 [0064] 1 BB16 1 [064..065) i hascall gcsafe BB18 [0065] 2 BB16,BB17 1 [064..065)-> BB20 ( cond ) i idxlen BB19 [0069] 1 BB18 1 [064..065) i hascall gcsafe BB20 [0070] 2 BB18,BB19 1 [064..065)-> BB39 ( cond ) i idxlen BB21 [0008] 1 BB20 1 [07A..???)-> BB24 ( cond ) i hascall gcsafe BB23 [0101] 1 BB21 0.50 [???..???)-> BB25 (always) i BB24 [0100] 1 BB21 0.50 [???..???) i BB25 [0098] 2 BB23,BB24 1 [???..106) i hascall gcsafe BB26 [0020] 2 BB25,BB72 1 [106..110)-> BB57 ( cond ) i idxlen bwd bwd-target BB27 [0021] 1 BB26 1 [110..120)-> BB37 ( cond ) i idxlen bwd BB28 [0022] 1 BB27 1 [120..137)-> BB37 ( cond ) i hascall gcsafe idxlen bwd BB29 [0023] 1 BB28 1 [137..13B)-> BB31 ( cond ) i bwd BB30 [0024] 1 BB29 1 [13B..14B)-> BB71 (always) i idxlen BB31 [0025] 1 BB29 1 [14B..14F)-> BB32 ( cond ) i bwd BB54 [0092] 2 BB31,BB73 1 [???..???) (return) internal BB37 [0028] 2 BB27,BB28 1 [157..170)-> BB38 ( cond ) i idxlen bwd BB72 [0114] 1 BB37 1 [???..???)-> BB26 (always) internal BB39 [0030] 2 BB20,BB74 1 [177..17E)-> BB57 ( cond ) i idxlen bwd bwd-target BB40 [0031] 1 BB39 1 [17E..18E)-> BB55 ( cond ) i idxlen bwd BB41 [0032] 1 BB40 1 [18E..???)-> BB44 ( cond ) i hascall gcsafe idxlen bwd BB43 [0109] 1 BB41 0.50 [???..???)-> BB45 (always) i BB44 [0108] 1 BB41 0.50 [???..???) i BB45 [0106] 2 BB43,BB44 1 [???..1A4)-> BB55 ( cond ) i hascall gcsafe idxlen bwd BB46 [0033] 1 BB45 1 [1A4..1A8)-> BB48 ( cond ) i bwd BB47 [0034] 1 BB46 1 [1A8..1B8)-> BB71 (always) i idxlen BB48 [0035] 1 BB46 1 [1B8..1BC)-> BB49 ( cond ) i bwd BB73 [0115] 1 BB48 1 [???..???)-> BB54 (always) internal BB55 [0038] 2 BB40,BB45 1 [1C4..1DD)-> BB56 ( cond ) i idxlen bwd BB74 [0116] 1 BB55 1 [???..???)-> BB39 (always) internal BB57 [0040] 2 BB26,BB39 1 [1E4..1ED)-> BB61 ( cond ) i BB58 [0041] 1 BB57 1 [1ED..243)-> BB60 ( cond ) i idxlen BB59 [0075] 1 BB58 1 [1F5..1F6) i hascall gcsafe BB60 [0076] 2 BB58,BB59 1 [1F5..1F6)-> BB68 (always) i idxlen BB61 [0042] 1 BB57 1 [243..252)-> BB67 ( cond ) i idxlen BB62 [0043] 1 BB61 1 [252..261)-> BB64 ( cond ) i hascall gcsafe idxlen BB63 [0083] 1 BB62 1 [258..259) i hascall gcsafe BB64 [0084] 2 BB62,BB63 1 [258..259)-> BB66 ( cond ) i idxlen BB65 [0088] 1 BB64 1 [258..259) i hascall gcsafe BB66 [0089] 2 BB64,BB65 1 [258..259) i idxlen BB67 [0044] 2 BB61,BB66 1 [261..276) i BB68 [0045] 2 BB60,BB67 1 [276..2CF)-> BB71 ( cond ) i idxlen BB69 [0047] 1 BB68 1 [2CF..2D7)-> BB71 ( cond ) i hascall BB70 [0048] 1 BB69 1 [2D7..2E3) i hascall gcsafe idxlen BB71 [0091] 5 BB30,BB47,BB68,BB69,BB70 1 [???..???) (return) internal BB02 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB32 [0026] 1 BB31 0 [14F..???)-> BB35 ( cond ) i rare hascall gcsafe bwd BB34 [0105] 1 BB32 0 [???..???)-> BB36 (always) i rare BB35 [0104] 1 BB32 0 [???..???) i rare BB36 [0102] 2 BB34,BB35 0 [???..157) (throw ) i rare hascall gcsafe bwd BB38 [0093] 1 BB37 0 [???..???)-> BB56 (always) internal rare BB49 [0036] 1 BB48 0 [1BC..???)-> BB52 ( cond ) i rare hascall gcsafe bwd BB51 [0113] 1 BB49 0 [???..???)-> BB53 (always) i rare BB52 [0112] 1 BB49 0 [???..???) i rare BB53 [0110] 2 BB51,BB52 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB56 [0039] 2 BB38,BB55 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- Duplication of the conditional block BB39 (always branch from BB74) not done, because the cost of duplication (9) is greater than 6, validProfileWeights = false *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB02 ( cond ) i BB03 [0002] 1 BB01 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i hascall gcsafe BB05 [0004] 2 BB03,BB04 1 [01E..04B)-> BB07 ( cond ) i BB06 [0052] 1 BB05 1 [01E..01F) i hascall gcsafe BB07 [0053] 2 BB05,BB06 1 [01E..034)-> BB09 ( cond ) i BB08 [0057] 1 BB07 1 [033..034) i hascall gcsafe BB09 [0058] 2 BB07,BB08 1 [033..034)-> BB15 ( cond ) i BB10 [0005] 1 BB09 1 [04B..???)-> BB13 ( cond ) i hascall gcsafe BB12 [0097] 1 BB10 0.50 [???..???)-> BB14 (always) i BB13 [0096] 1 BB10 0.50 [???..???) i BB14 [0094] 2 BB12,BB13 1 [???..054)-> BB16 (always) i hascall gcsafe BB15 [0006] 1 BB09 1 [054..061) i hascall gcsafe BB16 [0007] 2 BB14,BB15 1 [061..07A)-> BB18 ( cond ) i idxlen BB17 [0064] 1 BB16 1 [064..065) i hascall gcsafe BB18 [0065] 2 BB16,BB17 1 [064..065)-> BB20 ( cond ) i idxlen BB19 [0069] 1 BB18 1 [064..065) i hascall gcsafe BB20 [0070] 2 BB18,BB19 1 [064..065)-> BB39 ( cond ) i idxlen BB21 [0008] 1 BB20 1 [07A..???)-> BB24 ( cond ) i hascall gcsafe BB23 [0101] 1 BB21 0.50 [???..???)-> BB25 (always) i BB24 [0100] 1 BB21 0.50 [???..???) i BB25 [0098] 2 BB23,BB24 1 [???..106) i hascall gcsafe BB26 [0020] 2 BB25,BB72 1 [106..110)-> BB57 ( cond ) i idxlen bwd bwd-target BB27 [0021] 1 BB26 1 [110..120)-> BB37 ( cond ) i idxlen bwd BB28 [0022] 1 BB27 1 [120..137)-> BB37 ( cond ) i hascall gcsafe idxlen bwd BB29 [0023] 1 BB28 1 [137..13B)-> BB31 ( cond ) i bwd BB30 [0024] 1 BB29 1 [13B..14B)-> BB71 (always) i idxlen BB31 [0025] 1 BB29 1 [14B..14F)-> BB32 ( cond ) i bwd BB54 [0092] 2 BB31,BB73 1 [???..???) (return) internal BB37 [0028] 2 BB27,BB28 1 [157..170)-> BB38 ( cond ) i idxlen bwd BB72 [0114] 1 BB37 1 [???..???)-> BB26 (always) internal BB39 [0030] 2 BB20,BB74 1 [177..17E)-> BB57 ( cond ) i idxlen bwd bwd-target BB40 [0031] 1 BB39 1 [17E..18E)-> BB55 ( cond ) i idxlen bwd BB41 [0032] 1 BB40 1 [18E..???)-> BB44 ( cond ) i hascall gcsafe idxlen bwd BB43 [0109] 1 BB41 0.50 [???..???)-> BB45 (always) i BB44 [0108] 1 BB41 0.50 [???..???) i BB45 [0106] 2 BB43,BB44 1 [???..1A4)-> BB55 ( cond ) i hascall gcsafe idxlen bwd BB46 [0033] 1 BB45 1 [1A4..1A8)-> BB48 ( cond ) i bwd BB47 [0034] 1 BB46 1 [1A8..1B8)-> BB71 (always) i idxlen BB48 [0035] 1 BB46 1 [1B8..1BC)-> BB49 ( cond ) i bwd BB73 [0115] 1 BB48 1 [???..???)-> BB54 (always) internal BB55 [0038] 2 BB40,BB45 1 [1C4..1DD)-> BB56 ( cond ) i idxlen bwd BB74 [0116] 1 BB55 1 [???..???)-> BB39 (always) internal BB57 [0040] 2 BB26,BB39 1 [1E4..1ED)-> BB61 ( cond ) i BB58 [0041] 1 BB57 1 [1ED..243)-> BB60 ( cond ) i idxlen BB59 [0075] 1 BB58 1 [1F5..1F6) i hascall gcsafe BB60 [0076] 2 BB58,BB59 1 [1F5..1F6)-> BB68 (always) i idxlen BB61 [0042] 1 BB57 1 [243..252)-> BB67 ( cond ) i idxlen BB62 [0043] 1 BB61 1 [252..261)-> BB64 ( cond ) i hascall gcsafe idxlen BB63 [0083] 1 BB62 1 [258..259) i hascall gcsafe BB64 [0084] 2 BB62,BB63 1 [258..259)-> BB66 ( cond ) i idxlen BB65 [0088] 1 BB64 1 [258..259) i hascall gcsafe BB66 [0089] 2 BB64,BB65 1 [258..259) i idxlen BB67 [0044] 2 BB61,BB66 1 [261..276) i BB68 [0045] 2 BB60,BB67 1 [276..2CF)-> BB71 ( cond ) i idxlen BB69 [0047] 1 BB68 1 [2CF..2D7)-> BB71 ( cond ) i hascall BB70 [0048] 1 BB69 1 [2D7..2E3) i hascall gcsafe idxlen BB71 [0091] 5 BB30,BB47,BB68,BB69,BB70 1 [???..???) (return) internal BB02 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB32 [0026] 1 BB31 0 [14F..???)-> BB35 ( cond ) i rare hascall gcsafe bwd BB34 [0105] 1 BB32 0 [???..???)-> BB36 (always) i rare BB35 [0104] 1 BB32 0 [???..???) i rare BB36 [0102] 2 BB34,BB35 0 [???..157) (throw ) i rare hascall gcsafe bwd BB38 [0093] 1 BB37 0 [???..???)-> BB56 (always) internal rare BB49 [0036] 1 BB48 0 [1BC..???)-> BB52 ( cond ) i rare hascall gcsafe bwd BB51 [0113] 1 BB49 0 [???..???)-> BB53 (always) i rare BB52 [0112] 1 BB49 0 [???..???) i rare BB53 [0110] 2 BB51,BB52 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB56 [0039] 2 BB38,BB55 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- Optimizing a jump to an unconditional jump (BB37 -> BB38 -> BB56) Setting edge weights for BB37 -> BB56 to [0 .. 3.402823e+38] fgRemoveBlock BB38 Removing unreachable BB38 After updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB02 ( cond ) i BB03 [0002] 1 BB01 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i hascall gcsafe BB05 [0004] 2 BB03,BB04 1 [01E..04B)-> BB07 ( cond ) i BB06 [0052] 1 BB05 1 [01E..01F) i hascall gcsafe BB07 [0053] 2 BB05,BB06 1 [01E..034)-> BB09 ( cond ) i BB08 [0057] 1 BB07 1 [033..034) i hascall gcsafe BB09 [0058] 2 BB07,BB08 1 [033..034)-> BB15 ( cond ) i BB10 [0005] 1 BB09 1 [04B..???)-> BB13 ( cond ) i hascall gcsafe BB12 [0097] 1 BB10 0.50 [???..???)-> BB14 (always) i BB13 [0096] 1 BB10 0.50 [???..???) i BB14 [0094] 2 BB12,BB13 1 [???..054)-> BB16 (always) i hascall gcsafe BB15 [0006] 1 BB09 1 [054..061) i hascall gcsafe BB16 [0007] 2 BB14,BB15 1 [061..07A)-> BB18 ( cond ) i idxlen BB17 [0064] 1 BB16 1 [064..065) i hascall gcsafe BB18 [0065] 2 BB16,BB17 1 [064..065)-> BB20 ( cond ) i idxlen BB19 [0069] 1 BB18 1 [064..065) i hascall gcsafe BB20 [0070] 2 BB18,BB19 1 [064..065)-> BB39 ( cond ) i idxlen BB21 [0008] 1 BB20 1 [07A..???)-> BB24 ( cond ) i hascall gcsafe BB23 [0101] 1 BB21 0.50 [???..???)-> BB25 (always) i BB24 [0100] 1 BB21 0.50 [???..???) i BB25 [0098] 2 BB23,BB24 1 [???..106) i hascall gcsafe BB26 [0020] 2 BB25,BB72 1 [106..110)-> BB57 ( cond ) i idxlen bwd bwd-target BB27 [0021] 1 BB26 1 [110..120)-> BB37 ( cond ) i idxlen bwd BB28 [0022] 1 BB27 1 [120..137)-> BB37 ( cond ) i hascall gcsafe idxlen bwd BB29 [0023] 1 BB28 1 [137..13B)-> BB31 ( cond ) i bwd BB30 [0024] 1 BB29 1 [13B..14B)-> BB71 (always) i idxlen BB31 [0025] 1 BB29 1 [14B..14F)-> BB32 ( cond ) i bwd BB54 [0092] 2 BB31,BB73 1 [???..???) (return) internal BB37 [0028] 2 BB27,BB28 1 [157..170)-> BB56 ( cond ) i idxlen bwd BB72 [0114] 1 BB37 1 [???..???)-> BB26 (always) internal BB39 [0030] 2 BB20,BB74 1 [177..17E)-> BB57 ( cond ) i idxlen bwd bwd-target BB40 [0031] 1 BB39 1 [17E..18E)-> BB55 ( cond ) i idxlen bwd BB41 [0032] 1 BB40 1 [18E..???)-> BB44 ( cond ) i hascall gcsafe idxlen bwd BB43 [0109] 1 BB41 0.50 [???..???)-> BB45 (always) i BB44 [0108] 1 BB41 0.50 [???..???) i BB45 [0106] 2 BB43,BB44 1 [???..1A4)-> BB55 ( cond ) i hascall gcsafe idxlen bwd BB46 [0033] 1 BB45 1 [1A4..1A8)-> BB48 ( cond ) i bwd BB47 [0034] 1 BB46 1 [1A8..1B8)-> BB71 (always) i idxlen BB48 [0035] 1 BB46 1 [1B8..1BC)-> BB49 ( cond ) i bwd BB73 [0115] 1 BB48 1 [???..???)-> BB54 (always) internal BB55 [0038] 2 BB40,BB45 1 [1C4..1DD)-> BB56 ( cond ) i idxlen bwd BB74 [0116] 1 BB55 1 [???..???)-> BB39 (always) internal BB57 [0040] 2 BB26,BB39 1 [1E4..1ED)-> BB61 ( cond ) i BB58 [0041] 1 BB57 1 [1ED..243)-> BB60 ( cond ) i idxlen BB59 [0075] 1 BB58 1 [1F5..1F6) i hascall gcsafe BB60 [0076] 2 BB58,BB59 1 [1F5..1F6)-> BB68 (always) i idxlen BB61 [0042] 1 BB57 1 [243..252)-> BB67 ( cond ) i idxlen BB62 [0043] 1 BB61 1 [252..261)-> BB64 ( cond ) i hascall gcsafe idxlen BB63 [0083] 1 BB62 1 [258..259) i hascall gcsafe BB64 [0084] 2 BB62,BB63 1 [258..259)-> BB66 ( cond ) i idxlen BB65 [0088] 1 BB64 1 [258..259) i hascall gcsafe BB66 [0089] 2 BB64,BB65 1 [258..259) i idxlen BB67 [0044] 2 BB61,BB66 1 [261..276) i BB68 [0045] 2 BB60,BB67 1 [276..2CF)-> BB71 ( cond ) i idxlen BB69 [0047] 1 BB68 1 [2CF..2D7)-> BB71 ( cond ) i hascall BB70 [0048] 1 BB69 1 [2D7..2E3) i hascall gcsafe idxlen BB71 [0091] 5 BB30,BB47,BB68,BB69,BB70 1 [???..???) (return) internal BB02 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB32 [0026] 1 BB31 0 [14F..???)-> BB35 ( cond ) i rare hascall gcsafe bwd BB34 [0105] 1 BB32 0 [???..???)-> BB36 (always) i rare BB35 [0104] 1 BB32 0 [???..???) i rare BB36 [0102] 2 BB34,BB35 0 [???..157) (throw ) i rare hascall gcsafe bwd BB49 [0036] 1 BB48 0 [1BC..???)-> BB52 ( cond ) i rare hascall gcsafe bwd BB51 [0113] 1 BB49 0 [???..???)-> BB53 (always) i rare BB52 [0112] 1 BB49 0 [???..???) i rare BB53 [0110] 2 BB51,BB52 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB56 [0039] 2 BB37,BB55 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize layout Trees after Optimize layout ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB02 ( cond ) i BB03 [0002] 1 BB01 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i hascall gcsafe BB05 [0004] 2 BB03,BB04 1 [01E..04B)-> BB07 ( cond ) i BB06 [0052] 1 BB05 1 [01E..01F) i hascall gcsafe BB07 [0053] 2 BB05,BB06 1 [01E..034)-> BB09 ( cond ) i BB08 [0057] 1 BB07 1 [033..034) i hascall gcsafe BB09 [0058] 2 BB07,BB08 1 [033..034)-> BB15 ( cond ) i BB10 [0005] 1 BB09 1 [04B..???)-> BB13 ( cond ) i hascall gcsafe BB12 [0097] 1 BB10 0.50 [???..???)-> BB14 (always) i BB13 [0096] 1 BB10 0.50 [???..???) i BB14 [0094] 2 BB12,BB13 1 [???..054)-> BB16 (always) i hascall gcsafe BB15 [0006] 1 BB09 1 [054..061) i hascall gcsafe BB16 [0007] 2 BB14,BB15 1 [061..07A)-> BB18 ( cond ) i idxlen BB17 [0064] 1 BB16 1 [064..065) i hascall gcsafe BB18 [0065] 2 BB16,BB17 1 [064..065)-> BB20 ( cond ) i idxlen BB19 [0069] 1 BB18 1 [064..065) i hascall gcsafe BB20 [0070] 2 BB18,BB19 1 [064..065)-> BB39 ( cond ) i idxlen BB21 [0008] 1 BB20 1 [07A..???)-> BB24 ( cond ) i hascall gcsafe BB23 [0101] 1 BB21 0.50 [???..???)-> BB25 (always) i BB24 [0100] 1 BB21 0.50 [???..???) i BB25 [0098] 2 BB23,BB24 1 [???..106) i hascall gcsafe BB26 [0020] 2 BB25,BB72 1 [106..110)-> BB57 ( cond ) i idxlen bwd bwd-target BB27 [0021] 1 BB26 1 [110..120)-> BB37 ( cond ) i idxlen bwd BB28 [0022] 1 BB27 1 [120..137)-> BB37 ( cond ) i hascall gcsafe idxlen bwd BB29 [0023] 1 BB28 1 [137..13B)-> BB31 ( cond ) i bwd BB30 [0024] 1 BB29 1 [13B..14B)-> BB71 (always) i idxlen BB31 [0025] 1 BB29 1 [14B..14F)-> BB32 ( cond ) i bwd BB54 [0092] 2 BB31,BB73 1 [???..???) (return) internal BB37 [0028] 2 BB27,BB28 1 [157..170)-> BB56 ( cond ) i idxlen bwd BB72 [0114] 1 BB37 1 [???..???)-> BB26 (always) internal BB39 [0030] 2 BB20,BB74 1 [177..17E)-> BB57 ( cond ) i idxlen bwd bwd-target BB40 [0031] 1 BB39 1 [17E..18E)-> BB55 ( cond ) i idxlen bwd BB41 [0032] 1 BB40 1 [18E..???)-> BB44 ( cond ) i hascall gcsafe idxlen bwd BB43 [0109] 1 BB41 0.50 [???..???)-> BB45 (always) i BB44 [0108] 1 BB41 0.50 [???..???) i BB45 [0106] 2 BB43,BB44 1 [???..1A4)-> BB55 ( cond ) i hascall gcsafe idxlen bwd BB46 [0033] 1 BB45 1 [1A4..1A8)-> BB48 ( cond ) i bwd BB47 [0034] 1 BB46 1 [1A8..1B8)-> BB71 (always) i idxlen BB48 [0035] 1 BB46 1 [1B8..1BC)-> BB49 ( cond ) i bwd BB73 [0115] 1 BB48 1 [???..???)-> BB54 (always) internal BB55 [0038] 2 BB40,BB45 1 [1C4..1DD)-> BB56 ( cond ) i idxlen bwd BB74 [0116] 1 BB55 1 [???..???)-> BB39 (always) internal BB57 [0040] 2 BB26,BB39 1 [1E4..1ED)-> BB61 ( cond ) i BB58 [0041] 1 BB57 1 [1ED..243)-> BB60 ( cond ) i idxlen BB59 [0075] 1 BB58 1 [1F5..1F6) i hascall gcsafe BB60 [0076] 2 BB58,BB59 1 [1F5..1F6)-> BB68 (always) i idxlen BB61 [0042] 1 BB57 1 [243..252)-> BB67 ( cond ) i idxlen BB62 [0043] 1 BB61 1 [252..261)-> BB64 ( cond ) i hascall gcsafe idxlen BB63 [0083] 1 BB62 1 [258..259) i hascall gcsafe BB64 [0084] 2 BB62,BB63 1 [258..259)-> BB66 ( cond ) i idxlen BB65 [0088] 1 BB64 1 [258..259) i hascall gcsafe BB66 [0089] 2 BB64,BB65 1 [258..259) i idxlen BB67 [0044] 2 BB61,BB66 1 [261..276) i BB68 [0045] 2 BB60,BB67 1 [276..2CF)-> BB71 ( cond ) i idxlen BB69 [0047] 1 BB68 1 [2CF..2D7)-> BB71 ( cond ) i hascall BB70 [0048] 1 BB69 1 [2D7..2E3) i hascall gcsafe idxlen BB71 [0091] 5 BB30,BB47,BB68,BB69,BB70 1 [???..???) (return) internal BB02 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB32 [0026] 1 BB31 0 [14F..???)-> BB35 ( cond ) i rare hascall gcsafe bwd BB34 [0105] 1 BB32 0 [???..???)-> BB36 (always) i rare BB35 [0104] 1 BB32 0 [???..???) i rare BB36 [0102] 2 BB34,BB35 0 [???..157) (throw ) i rare hascall gcsafe bwd BB49 [0036] 1 BB48 0 [1BC..???)-> BB52 ( cond ) i rare hascall gcsafe bwd BB51 [0113] 1 BB49 0 [???..???)-> BB53 (always) i rare BB52 [0112] 1 BB49 0 [???..???) i rare BB53 [0110] 2 BB51,BB52 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB56 [0039] 2 BB37,BB55 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB02 (cond), preds={} succs={BB03,BB02} ***** BB01 STMT00000 (IL 0x000...0x006) [000003] -----+------ * JTRUE void [000002] J----+-N---- \--* EQ int [000000] -----+------ +--* LCL_VAR ref V01 arg1 [000001] -----+------ \--* CNS_INT ref null ------------ BB03 [00E..016) -> BB05 (cond), preds={BB01} succs={BB04,BB05} ***** BB03 STMT00001 (IL 0x00E...0x014) [000008] ---XG+------ * JTRUE void [000007] J--XG+-N---- \--* NE int [000005] ---XG+------ +--* IND ref [000814] -----+------ | \--* ADD byref [000004] -----+------ | +--* LCL_VAR ref V00 this [000813] -----+------ | \--* CNS_INT long 8 field offset Fseq[_buckets] [000006] -----+------ \--* CNS_INT ref null ------------ BB04 [016..01E), preds={BB03} succs={BB05} ***** BB04 STMT00085 (IL ???... ???) [000528] --CXG+------ * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize [000526] -----+------ this in rcx +--* LCL_VAR ref V00 this [000527] -----+------ arg1 in rdx \--* CNS_INT int 0 ------------ BB05 [01E..04B) -> BB07 (cond), preds={BB03,BB04} succs={BB06,BB07} ***** BB05 STMT00088 (IL 0x01E... ???) [000544] -A-XG+------ * ASG bool [000543] D----+-N---- +--* LCL_VAR int V33 tmp19 [000012] N--XG+------ \--* NE int [000010] ---XG+------ +--* IND ref [000818] -----+------ | \--* ADD byref [000009] -----+------ | +--* LCL_VAR ref V00 this [000817] -----+------ | \--* CNS_INT long 8 field offset Fseq[_buckets] [000011] -----+------ \--* CNS_INT ref null ***** BB05 STMT00091 (IL 0x01E... ???) [000554] -A--G+------ * ASG ref [000553] D----+-N---- +--* LCL_VAR ref V34 tmp20 [000538] #---G+------ \--* IND ref [000537] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB05 STMT00092 (IL 0x01E... ???) [000556] -A--G+------ * ASG ref [000555] D----+-N---- +--* LCL_VAR ref V35 tmp21 [000540] #---G+------ \--* IND ref [000539] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB05 STMT00089 (IL 0x01E... ???) [000549] -----+------ * JTRUE void [000548] J----+-N---- \--* NE int [000546] -----+------ +--* LCL_VAR int V33 tmp19 [000547] -----+------ \--* CNS_INT int 0 ------------ BB06 [01E..01F), preds={BB05} succs={BB07} ***** BB06 STMT00090 (IL 0x01E... ???) [000552] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000550] -----+------ arg0 in rcx +--* LCL_VAR ref V34 tmp20 [000551] -----+------ arg1 in rdx \--* LCL_VAR ref V35 tmp21 ------------ BB07 [01E..034) -> BB09 (cond), preds={BB05,BB06} succs={BB08,BB09} ***** BB07 STMT00003 (IL 0x02C... ???) [000018] -A-XG+------ * ASG ref [000017] D----+-N---- +--* LCL_VAR ref V04 loc0 [000016] ---XG+------ \--* IND ref [000822] -----+------ \--* ADD byref [000015] -----+------ +--* LCL_VAR ref V00 this [000821] -----+------ \--* CNS_INT long 16 field offset Fseq[_entries] ***** BB07 STMT00094 (IL 0x033... ???) [000566] -A---+------ * ASG bool [000565] D----+-N---- +--* LCL_VAR int V36 tmp22 [000021] N----+------ \--* NE int [000019] -----+------ +--* LCL_VAR ref V04 loc0 [000020] -----+------ \--* CNS_INT ref null ***** BB07 STMT00097 (IL 0x033... ???) [000576] -A--G+------ * ASG ref [000575] D----+-N---- +--* LCL_VAR ref V37 tmp23 [000562] #---G+------ \--* IND ref [000561] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB07 STMT00095 (IL 0x033... ???) [000571] -----+------ * JTRUE void [000570] J----+-N---- \--* NE int [000568] -----+------ +--* LCL_VAR int V36 tmp22 [000569] -----+------ \--* CNS_INT int 0 ------------ BB08 [033..034), preds={BB07} succs={BB09} ***** BB08 STMT00096 (IL 0x033... ???) [000574] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000824] #---G+------ arg0 in rcx +--* IND ref [000823] H----+------ | \--* CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" [000573] -----+------ arg1 in rdx \--* LCL_VAR ref V37 tmp23 ------------ BB09 [033..034) -> BB15 (cond), preds={BB07,BB08} succs={BB10,BB15} ***** BB09 STMT00005 (IL 0x041... ???) [000028] -A-XG+------ * ASG ref [000027] D----+-N---- +--* LCL_VAR ref V05 loc1 [000026] ---XG+------ \--* IND ref [000828] -----+------ \--* ADD byref [000025] -----+------ +--* LCL_VAR ref V00 this [000827] -----+------ \--* CNS_INT long 24 field offset Fseq[_comparer] ***** BB09 STMT00006 (IL 0x048...0x049) [000032] -----+------ * JTRUE void [000031] J----+-N---- \--* EQ int [000029] -----+------ +--* LCL_VAR ref V05 loc1 [000030] -----+------ \--* CNS_INT ref null ------------ BB10 [04B..???) -> BB13 (cond), preds={BB09} succs={BB12,BB13} ***** BB10 STMT00079 (IL 0x04B...0x052) [000489] -A-X-+------ * ASG long [000488] D----+-N---- +--* LCL_VAR long V29 tmp15 [000487] #--X-+------ \--* IND long [000486] !----+------ \--* LCL_VAR ref V00 this ***** BB10 STMT00080 (IL ???... ???) [000499] -A---+------ * ASG ref [000498] D----+-N---- +--* LCL_VAR ref V30 tmp16 [000485] -----+------ \--* LCL_VAR ref V01 arg1 ***** BB10 STMT00149 (IL ???... ???) [001148] ------------ * JTRUE void [000505] J----+-N---- \--* EQ int [000501] n----+------ +--* IND long [000497] -----+------ | \--* ADD long [000495] #----+------ | +--* IND long [000494] #----+------ | | \--* IND long [000493] -----+------ | | \--* ADD long [000491] -----+------ | | +--* LCL_VAR long V29 tmp15 [000492] -----+------ | | \--* CNS_INT long 56 [000496] -----+------ | \--* CNS_INT long 64 [000504] -----+------ \--* CNS_INT long 0 ------------ BB12 [???..???) -> BB14 (always), preds={BB10} succs={BB14} ***** BB12 STMT00150 (IL ???... ???) [001150] -A---------- * ASG long [001149] D------N---- +--* LCL_VAR long V31 tmp17 [000506] n----+?----- \--* IND long [000507] -----+?----- \--* ADD long [000508] #----+?----- +--* IND long [000509] #----+?----- | \--* IND long [000510] -----+?----- | \--* ADD long [000511] -----+?----- | +--* LCL_VAR long V29 tmp15 [000512] -----+?----- | \--* CNS_INT long 56 [000513] -----+?----- \--* CNS_INT long 64 ------------ BB13 [???..???), preds={BB10} succs={BB14} ***** BB13 STMT00151 (IL ???... ???) [001152] -AC-G------- * ASG long [001151] D------N---- +--* LCL_VAR long V31 tmp17 [000503] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000490] -----+?----- arg0 in rcx +--* LCL_VAR long V29 tmp15 [000502] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB14 [???..054) -> BB16 (always), preds={BB12,BB13} succs={BB16} ***** BB14 STMT00082 (IL ???... ???) [000520] -A---+------ * ASG long [000519] D----+-N---- +--* LCL_VAR long V32 tmp18 [000518] -----+------ \--* LCL_VAR long V31 tmp17 ***** BB14 STMT00083 (IL ???... ???) [000524] -ACXG+------ * ASG int [000523] D----+-N---- +--* LCL_VAR int V15 tmp1 [000522] --CXG+------ \--* CALL ind stub int [000521] -----+------ calli tgt \--* LCL_VAR long V31 tmp17 [000484] -----+------ this in rcx +--* LCL_VAR ref V05 loc1 [000831] -----+------ arg1 in r11 +--* LCL_VAR long V31 tmp17 r11 REG r11 [000500] -----+------ arg2 in rdx \--* LCL_VAR ref V01 arg1 ------------ BB15 [054..061), preds={BB09} succs={BB16} ***** BB15 STMT00007 (IL 0x054...0x05C) [000038] -ACXG+------ * ASG int [000037] D----+-N---- +--* LCL_VAR int V15 tmp1 [000035] --CXG+------ \--* CALLV vt-ind int System.Object.GetHashCode [000843] n--X-+------ control expr \--* IND long [000842] ---X-+------ \--* ADD long [000840] #--X-+------ +--* IND long [000839] ---X-+------ | \--* ADD long [000837] #--X-+------ | +--* IND long [000836] -----+------ | | \--* LCL_VAR ref V01 arg1 [000838] -----+------ | \--* CNS_INT int 72 [000841] -----+------ \--* CNS_INT int 24 [000033] -----+------ this in rcx \--* LCL_VAR ref V01 arg1 ------------ BB16 [061..07A) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} ***** BB16 STMT00008 (IL ???...0x061) [000042] -A---+------ * ASG int [000041] D----+-N---- +--* LCL_VAR int V06 loc2 [000040] -----+------ \--* LCL_VAR int V15 tmp1 ***** BB16 STMT00009 (IL 0x062...0x063) [000045] -A---+------ * ASG int [000044] D----+-N---- +--* LCL_VAR int V07 loc3 [000043] -----+------ \--* CNS_INT int 0 ***** BB16 STMT00098 (IL 0x064... ???) [000580] -A-XG+------ * ASG ref [000579] D----+-N---- +--* LCL_VAR ref V39 tmp25 [000578] ---XG+------ \--* IND ref [000845] -----+------ \--* ADD byref [000046] -----+------ +--* LCL_VAR ref V00 this [000844] -----+------ \--* CNS_INT long 8 field offset Fseq[_buckets] ***** BB16 STMT00105 (IL 0x064... ???) [000629] -A-X-+------ * ASG int [000628] D----+-N---- +--* LCL_VAR int V40 tmp26 [000583] ---X-+------ \--* ARR_LENGTH int [000582] -----+------ \--* LCL_VAR ref V39 tmp25 ***** BB16 STMT00106 (IL 0x064... ???) [000631] -A-XG+------ * ASG long [000630] D----+-N---- +--* LCL_VAR long V41 tmp27 [000585] ---XG+------ \--* IND long [000847] -----+------ \--* ADD byref [000584] -----+------ +--* LCL_VAR ref V00 this [000846] -----+------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] ***** BB16 STMT00108 (IL 0x064... ???) [000642] -A---+------ * ASG bool [000641] D----+-N---- +--* LCL_VAR int V43 tmp29 [000599] N----+---U-- \--* LE int [000597] -----+------ +--* LCL_VAR int V40 tmp26 [000598] -----+------ \--* CNS_INT int 0x7FFFFFFF ***** BB16 STMT00111 (IL 0x064... ???) [000652] -A--G+------ * ASG ref [000651] D----+-N---- +--* LCL_VAR ref V44 tmp30 [000636] #---G+------ \--* IND ref [000635] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB16 STMT00112 (IL 0x064... ???) [000654] -A--G+------ * ASG ref [000653] D----+-N---- +--* LCL_VAR ref V45 tmp31 [000638] #---G+------ \--* IND ref [000637] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB16 STMT00109 (IL 0x064... ???) [000647] -----+------ * JTRUE void [000646] J----+-N---- \--* NE int [000644] -----+------ +--* LCL_VAR int V43 tmp29 [000645] -----+------ \--* CNS_INT int 0 ------------ BB17 [064..065), preds={BB16} succs={BB18} ***** BB17 STMT00110 (IL 0x064... ???) [000650] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000648] -----+------ arg0 in rcx +--* LCL_VAR ref V44 tmp30 [000649] -----+------ arg1 in rdx \--* LCL_VAR ref V45 tmp31 ------------ BB18 [064..065) -> BB20 (cond), preds={BB16,BB17} succs={BB19,BB20} ***** BB18 STMT00103 (IL 0x064... ???) [000619] -A---+------ * ASG int [000618] D----+-N---- +--* LCL_VAR int V42 tmp28 [000617] -----+------ \--* CAST int <- uint <- long [000616] -----+------ \--* RSZ long [000614] -----+------ +--* MUL long [000611] -----+------ | +--* ADD long [000608] -----+------ | | +--* RSZ long [000606] -----+------ | | | +--* MUL long [000604] -----+------ | | | | +--* LCL_VAR long V41 tmp27 [000605] -----+---U-- | | | | \--* CAST long <- ulong <- uint [000047] -----+------ | | | | \--* LCL_VAR int V06 loc2 [000607] -----+------ | | | \--* CNS_INT int 32 [000610] -----+------ | | \--* CNS_INT long 1 [000613] -----+---U-- | \--* CAST long <- ulong <- uint [000612] -----+------ | \--* LCL_VAR int V40 tmp26 [000615] -----+------ \--* CNS_INT int 32 ***** BB18 STMT00114 (IL 0x064... ???) [000665] -A-X-+------ * ASG bool [000664] D----+-N---- +--* LCL_VAR int V46 tmp32 [000624] ---X-+------ \--* EQ int [000620] -----+------ +--* LCL_VAR int V42 tmp28 [000623] ---X-+------ \--* UMOD int [000621] -----+------ +--* LCL_VAR int V06 loc2 [000622] -----+------ \--* LCL_VAR int V40 tmp26 ***** BB18 STMT00117 (IL 0x064... ???) [000675] -A--G+------ * ASG ref [000674] D----+-N---- +--* LCL_VAR ref V47 tmp33 [000659] #---G+------ \--* IND ref [000658] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB18 STMT00118 (IL 0x064... ???) [000677] -A--G+------ * ASG ref [000676] D----+-N---- +--* LCL_VAR ref V48 tmp34 [000661] #---G+------ \--* IND ref [000660] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB18 STMT00115 (IL 0x064... ???) [000670] -----+------ * JTRUE void [000669] J----+-N---- \--* NE int [000667] -----+------ +--* LCL_VAR int V46 tmp32 [000668] -----+------ \--* CNS_INT int 0 ------------ BB19 [064..065), preds={BB18} succs={BB20} ***** BB19 STMT00116 (IL 0x064... ???) [000673] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000671] -----+------ arg0 in rcx +--* LCL_VAR ref V47 tmp33 [000672] -----+------ arg1 in rdx \--* LCL_VAR ref V48 tmp34 ------------ BB20 [064..065) -> BB39 (cond), preds={BB18,BB19} succs={BB21,BB39} ***** BB20 STMT00100 (IL 0x064... ???) [000591] -A-XG+------ * ASG byref [000590] D----+-N---- +--* LCL_VAR byref V38 tmp24 [000862] ---XG+------ \--* COMMA byref [000855] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000627] -----+------ | +--* LCL_VAR int V42 tmp28 [000854] ---X-+------ | \--* ARR_LENGTH int [000581] -----+------ | \--* LCL_VAR ref V39 tmp25 [000863] ----G------- \--* ADDR byref [000588] a---G+-N---- \--* IND int [000861] -----+------ \--* ADD byref [000852] -----+------ +--* LCL_VAR ref V39 tmp25 [000860] -----+------ \--* ADD long [000858] -----+------ +--* LSH long [000856] -----+------ | +--* CAST long <- int [000853] i----+------ | | \--* LCL_VAR int V42 tmp28 [000857] -----+-N---- | \--* CNS_INT long 2 [000859] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB20 STMT00101 (IL 0x064... ???) [000595] -A---+------ * ASG ref [000594] D----+-N---- +--* LCL_VAR ref V39 tmp25 [000593] -----+------ \--* CNS_INT ref null ***** BB20 STMT00011 (IL ???... ???) [000051] -A---+------ * ASG byref [000050] D----+-N---- +--* LCL_VAR byref V08 loc4 [000592] -----+------ \--* LCL_VAR byref V38 tmp24 ***** BB20 STMT00012 (IL 0x06D...0x072) [000057] -A-XG+------ * ASG int [000056] D----+-N---- +--* LCL_VAR int V09 loc5 [000055] ---XG+------ \--* ADD int [000053] *--XG+------ +--* IND int [000052] -----+------ | \--* LCL_VAR byref V38 tmp24 [000054] -----+------ \--* CNS_INT int -1 ***** BB20 STMT00013 (IL 0x074...0x075) [000061] -----+------ * JTRUE void [000060] J----+-N---- \--* NE int [000058] -----+------ +--* LCL_VAR ref V05 loc1 [000059] -----+------ \--* CNS_INT ref null ------------ BB21 [07A..???) -> BB24 (cond), preds={BB20} succs={BB23,BB24} ***** BB21 STMT00059 (IL 0x0FF...0x104) [000356] -A-X-+------ * ASG long [000355] D----+-N---- +--* LCL_VAR long V24 tmp10 [000354] #--X-+------ \--* IND long [000353] !----+------ \--* LCL_VAR ref V00 this ***** BB21 STMT00152 (IL ???... ???) [001153] ------------ * JTRUE void [000369] J----+-N---- \--* EQ int [000365] n----+------ +--* IND long [000364] -----+------ | \--* ADD long [000362] #----+------ | +--* IND long [000361] #----+------ | | \--* IND long [000360] -----+------ | | \--* ADD long [000358] -----+------ | | +--* LCL_VAR long V24 tmp10 [000359] -----+------ | | \--* CNS_INT long 56 [000363] -----+------ | \--* CNS_INT long 32 [000368] -----+------ \--* CNS_INT long 0 ------------ BB23 [???..???) -> BB25 (always), preds={BB21} succs={BB25} ***** BB23 STMT00153 (IL ???... ???) [001155] -A---------- * ASG long [001154] D------N---- +--* LCL_VAR long V25 tmp11 [000370] n----+?----- \--* IND long [000371] -----+?----- \--* ADD long [000372] #----+?----- +--* IND long [000373] #----+?----- | \--* IND long [000374] -----+?----- | \--* ADD long [000375] -----+?----- | +--* LCL_VAR long V24 tmp10 [000376] -----+?----- | \--* CNS_INT long 56 [000377] -----+?----- \--* CNS_INT long 32 ------------ BB24 [???..???), preds={BB21} succs={BB25} ***** BB24 STMT00154 (IL ???... ???) [001157] -AC-G------- * ASG long [001156] D------N---- +--* LCL_VAR long V25 tmp11 [000367] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000357] -----+?----- arg0 in rcx +--* LCL_VAR long V24 tmp10 [000366] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB25 [???..106), preds={BB23,BB24} succs={BB26} ***** BB25 STMT00062 (IL ???... ???) [000386] -ACXG+------ * ASG ref [000385] D----+-N---- +--* LCL_VAR ref V12 loc8 [000352] --CXG+------ \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default [000382] -----+------ arg0 in rcx \--* LCL_VAR long V25 tmp11 ------------ BB26 [106..110) -> BB57 (cond), preds={BB25,BB72} succs={BB27,BB57} ***** BB26 STMT00063 (IL 0x106...0x10B) [000391] ---X-+------ * JTRUE void [000390] N--X-+-N-U-- \--* GE int [000387] -----+------ +--* LCL_VAR int V09 loc5 [000389] ---X-+------ \--* ARR_LENGTH int [000388] -----+------ \--* LCL_VAR ref V04 loc0 ------------ BB27 [110..120) -> BB37 (cond), preds={BB26} succs={BB28,BB37} ***** BB27 STMT00064 (IL 0x110...0x11E) [000399] ---XG+------ * JTRUE void [000398] N--XG+-N-U-- \--* NE int [000396] *--XG+------ +--* IND int [000868] ---XG+------ | \--* ADD byref [000879] ---XG+------ | +--* COMMA byref [000872] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000393] -----+------ | | | +--* LCL_VAR int V09 loc5 [000871] ---X-+------ | | | \--* ARR_LENGTH int [000392] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000882] ----G------- | | \--* ADDR byref [000394] a---G+-N---- | | \--* IND struct [000878] -----+------ | | \--* ADD byref [000869] -----+------ | | +--* LCL_VAR ref V04 loc0 [000877] -----+------ | | \--* ADD long [000875] -----+------ | | +--* LSH long [000881] -----+------ | | | +--* MUL long [000873] -----+------ | | | | +--* CAST long <- int [000870] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000880] ------------ | | | | \--* CNS_INT long 3 [000874] -----+-N---- | | | \--* CNS_INT long 3 [000876] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000867] -----+------ | \--* CNS_INT long 16 field offset Fseq[hashCode] [000397] -----+------ \--* LCL_VAR int V06 loc2 ------------ BB28 [120..137) -> BB37 (cond), preds={BB27} succs={BB29,BB37} ***** BB28 STMT00069 (IL 0x120...0x135) [000428] --CXG+------ * JTRUE void [000427] J-CXG+-N---- \--* EQ int [000425] --CXG+------ +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals [000908] n--X-+------ control expr | \--* IND long [000907] ---X-+------ | \--* ADD long [000905] #--X-+------ | +--* IND long [000904] ---X-+------ | | \--* ADD long [000902] #--X-+------ | | +--* IND long [000901] -----+------ | | | \--* LCL_VAR ref V12 loc8 [000903] -----+------ | | \--* CNS_INT int 72 [000906] -----+------ | \--* CNS_INT int 32 [000893] ---XG+------ arg1 in rdx | +--* COMMA ref [000886] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000420] -----+------ | | | +--* LCL_VAR int V09 loc5 [000885] ---X-+------ | | | \--* ARR_LENGTH int [000419] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000897] *---G+------ | | \--* IND ref [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] [000421] a---G+-N---- | | \--* IND struct [000892] -----+------ | | \--* ADD byref [000883] -----+------ | | +--* LCL_VAR ref V04 loc0 [000891] -----+------ | | \--* ADD long [000889] -----+------ | | +--* LSH long [000895] -----+------ | | | +--* MUL long [000887] -----+------ | | | | +--* CAST long <- int [000884] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000894] ------------ | | | | \--* CNS_INT long 3 [000888] -----+-N---- | | | \--* CNS_INT long 3 [000890] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000418] -----+------ this in rcx | +--* LCL_VAR ref V12 loc8 [000424] -----+------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 [000426] -----+------ \--* CNS_INT int 0 ------------ BB29 [137..13B) -> BB31 (cond), preds={BB28} succs={BB30,BB31} ***** BB29 STMT00070 (IL 0x137...0x139) [000432] -----+------ * JTRUE void [000431] N----+-N-U-- \--* NE int [000909] -----+------ +--* CAST int <- ubyte <- int [000429] -----+------ | \--* LCL_VAR int V03 arg3 [000430] -----+------ \--* CNS_INT int 1 ------------ BB30 [13B..14B) -> BB71 (always), preds={BB29} succs={BB71} ***** BB30 STMT00077 (IL 0x13B...0x144) [000481] -A-XG+------ * ASG ref [000480] *--XG+-N---- +--* IND ref [000911] ---XG+------ | \--* ADD byref [000922] ---XG+------ | +--* COMMA byref [000915] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000476] -----+------ | | | +--* LCL_VAR int V09 loc5 [000914] ---X-+------ | | | \--* ARR_LENGTH int [000475] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000925] ----G------- | | \--* ADDR byref [000477] a---G+-N---- | | \--* IND struct [000921] -----+------ | | \--* ADD byref [000912] -----+------ | | +--* LCL_VAR ref V04 loc0 [000920] -----+------ | | \--* ADD long [000918] -----+------ | | +--* LSH long [000924] -----+------ | | | +--* MUL long [000916] -----+------ | | | | +--* CAST long <- int [000913] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000923] ------------ | | | | \--* CNS_INT long 3 [000917] -----+-N---- | | | \--* CNS_INT long 3 [000919] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000910] -----+------ | \--* CNS_INT long 8 field offset Fseq[value] [000479] -----+------ \--* LCL_VAR ref V02 arg2 ------------ BB31 [14B..14F) -> BB32 (cond), preds={BB29} succs={BB54,BB32} ***** BB31 STMT00071 (IL 0x14B...0x14D) [000436] -----+------ * JTRUE void [000435] N----+-N-U-- \--* EQ int [000926] -----+------ +--* CAST int <- ubyte <- int [000433] -----+------ | \--* LCL_VAR int V03 arg3 [000434] -----+------ \--* CNS_INT int 2 ------------ BB54 [???..???) (return), preds={BB31,BB73} succs={} ***** BB54 STMT00148 (IL ???... ???) [000811] -----+------ * RETURN int [000437] -----+------ \--* CNS_INT int 0 ------------ BB37 [157..170) -> BB56 (cond), preds={BB27,BB28} succs={BB72,BB56} ***** BB37 STMT00065 (IL 0x157...0x164) [000406] -A-XG+------ * ASG int [000405] D----+-N---- +--* LCL_VAR int V09 loc5 [000404] *--XG+------ \--* IND int [000932] ---XG+------ \--* ADD byref [000943] ---XG+------ +--* COMMA byref [000936] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000401] -----+------ | | +--* LCL_VAR int V09 loc5 [000935] ---X-+------ | | \--* ARR_LENGTH int [000400] -----+------ | | \--* LCL_VAR ref V04 loc0 [000946] ----G------- | \--* ADDR byref [000402] a---G+-N---- | \--* IND struct [000942] -----+------ | \--* ADD byref [000933] -----+------ | +--* LCL_VAR ref V04 loc0 [000941] -----+------ | \--* ADD long [000939] -----+------ | +--* LSH long [000945] -----+------ | | +--* MUL long [000937] -----+------ | | | +--* CAST long <- int [000934] i----+------ | | | | \--* LCL_VAR int V09 loc5 [000944] ------------ | | | \--* CNS_INT long 3 [000938] -----+-N---- | | \--* CNS_INT long 3 [000940] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [000931] -----+------ \--* CNS_INT long 20 field offset Fseq[next] ***** BB37 STMT00066 (IL 0x166...0x169) [000411] -A---+------ * ASG int [000410] D----+-N---- +--* LCL_VAR int V07 loc3 [000409] -----+------ \--* ADD int [000407] -----+------ +--* LCL_VAR int V07 loc3 [000408] -----+------ \--* CNS_INT int 1 ***** BB37 STMT00067 (IL 0x16A...0x16E) [000416] ---X-+------ * JTRUE void [000415] N--X-+-N-U-- \--* GT int [000412] -----+------ +--* LCL_VAR int V07 loc3 [000414] ---X-+------ \--* ARR_LENGTH int [000413] -----+------ \--* LCL_VAR ref V04 loc0 ------------ BB72 [???..???) -> BB26 (always), preds={BB37} succs={BB26} ------------ BB39 [177..17E) -> BB57 (cond), preds={BB20,BB74} succs={BB40,BB57} ***** BB39 STMT00014 (IL 0x177...0x17C) ( 11, 9) [000066] ---X-------- * JTRUE void ( 9, 7) [000065] N--X---N-U-- \--* LE int ( 5, 4) [000064] ---X-------- +--* ARR_LENGTH int ( 3, 2) [000063] ------------ | \--* LCL_VAR ref V04 loc0 ( 3, 2) [000062] ------------ \--* LCL_VAR int V09 loc5 ------------ BB40 [17E..18E) -> BB55 (cond), preds={BB39} succs={BB41,BB55} ***** BB40 STMT00039 (IL 0x17E...0x18C) [000215] ---XG+------ * JTRUE void [000214] N--XG+-N-U-- \--* NE int [000212] *--XG+------ +--* IND int [000948] ---XG+------ | \--* ADD byref [000959] ---XG+------ | +--* COMMA byref [000952] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000209] -----+------ | | | +--* LCL_VAR int V09 loc5 [000951] ---X-+------ | | | \--* ARR_LENGTH int [000208] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000962] ----G------- | | \--* ADDR byref [000210] a---G+-N---- | | \--* IND struct [000958] -----+------ | | \--* ADD byref [000949] -----+------ | | +--* LCL_VAR ref V04 loc0 [000957] -----+------ | | \--* ADD long [000955] -----+------ | | +--* LSH long [000961] -----+------ | | | +--* MUL long [000953] -----+------ | | | | +--* CAST long <- int [000950] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000960] ------------ | | | | \--* CNS_INT long 3 [000954] -----+-N---- | | | \--* CNS_INT long 3 [000956] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000947] -----+------ | \--* CNS_INT long 16 field offset Fseq[hashCode] [000213] -----+------ \--* LCL_VAR int V06 loc2 ------------ BB41 [18E..???) -> BB44 (cond), preds={BB40} succs={BB43,BB44} ***** BB41 STMT00045 (IL 0x18E...0x1A2) [000246] -A-XG+------ * ASG ref [000245] D----+-N---- +--* LCL_VAR ref V17 tmp3 [000973] ---XG+------ \--* COMMA ref [000966] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000236] -----+------ | +--* LCL_VAR int V09 loc5 [000965] ---X-+------ | \--* ARR_LENGTH int [000235] -----+------ | \--* LCL_VAR ref V04 loc0 [000977] *---G+------ \--* IND ref [000976] ----G------- \--* ADDR byref Zero Fseq[key] [000237] a---G+-N---- \--* IND struct [000972] -----+------ \--* ADD byref [000963] -----+------ +--* LCL_VAR ref V04 loc0 [000971] -----+------ \--* ADD long [000969] -----+------ +--* LSH long [000975] -----+------ | +--* MUL long [000967] -----+------ | | +--* CAST long <- int [000964] i----+------ | | | \--* LCL_VAR int V09 loc5 [000974] ------------ | | \--* CNS_INT long 3 [000968] -----+-N---- | \--* CNS_INT long 3 [000970] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB41 STMT00044 (IL 0x18E... ???) [000244] -A-X-+------ * ASG long [000243] D----+-N---- +--* LCL_VAR long V16 tmp2 [000242] #--X-+------ \--* IND long [000241] !----+------ \--* LCL_VAR ref V00 this ***** BB41 STMT00046 (IL ???... ???) [000257] -A---+------ * ASG ref [000256] D----+-N---- +--* LCL_VAR ref V18 tmp4 [000240] -----+------ \--* LCL_VAR ref V01 arg1 ***** BB41 STMT00158 (IL ???... ???) [001163] ------------ * JTRUE void [000263] J----+-N---- \--* EQ int [000259] n----+------ +--* IND long [000255] -----+------ | \--* ADD long [000253] #----+------ | +--* IND long [000252] #----+------ | | \--* IND long [000251] -----+------ | | \--* ADD long [000249] -----+------ | | +--* LCL_VAR long V16 tmp2 [000250] -----+------ | | \--* CNS_INT long 56 [000254] -----+------ | \--* CNS_INT long 48 [000262] -----+------ \--* CNS_INT long 0 ------------ BB43 [???..???) -> BB45 (always), preds={BB41} succs={BB45} ***** BB43 STMT00159 (IL ???... ???) [001165] -A---------- * ASG long [001164] D------N---- +--* LCL_VAR long V19 tmp5 [000264] n----+?----- \--* IND long [000265] -----+?----- \--* ADD long [000266] #----+?----- +--* IND long [000267] #----+?----- | \--* IND long [000268] -----+?----- | \--* ADD long [000269] -----+?----- | +--* LCL_VAR long V16 tmp2 [000270] -----+?----- | \--* CNS_INT long 56 [000271] -----+?----- \--* CNS_INT long 48 ------------ BB44 [???..???), preds={BB41} succs={BB45} ***** BB44 STMT00160 (IL ???... ???) [001167] -AC-G------- * ASG long [001166] D------N---- +--* LCL_VAR long V19 tmp5 [000261] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000248] -----+?----- arg0 in rcx +--* LCL_VAR long V16 tmp2 [000260] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB45 [???..1A4) -> BB55 (cond), preds={BB43,BB44} succs={BB46,BB55} ***** BB45 STMT00048 (IL ???... ???) [000278] -A---+------ * ASG long [000277] D----+-N---- +--* LCL_VAR long V20 tmp6 [000276] -----+------ \--* LCL_VAR long V19 tmp5 ***** BB45 STMT00049 (IL ???... ???) [000283] --CXG+------ * JTRUE void [000282] J-CXG+-N---- \--* EQ int [000280] --CXG+------ +--* CALL ind stub int [000279] -----+------ calli tgt | \--* LCL_VAR long V19 tmp5 [000234] -----+------ this in rcx | +--* LCL_VAR ref V05 loc1 [000980] -----+------ arg1 in r11 | +--* LCL_VAR long V19 tmp5 r11 REG r11 [000247] -----+------ arg2 in rdx | +--* LCL_VAR ref V17 tmp3 [000258] -----+------ arg3 in r8 | \--* LCL_VAR ref V01 arg1 [000281] -----+------ \--* CNS_INT int 0 ------------ BB46 [1A4..1A8) -> BB48 (cond), preds={BB45} succs={BB47,BB48} ***** BB46 STMT00050 (IL 0x1A4...0x1A6) [000287] -----+------ * JTRUE void [000286] N----+-N-U-- \--* NE int [000985] -----+------ +--* CAST int <- ubyte <- int [000284] -----+------ | \--* LCL_VAR int V03 arg3 [000285] -----+------ \--* CNS_INT int 1 ------------ BB47 [1A8..1B8) -> BB71 (always), preds={BB46} succs={BB71} ***** BB47 STMT00057 (IL 0x1A8...0x1B1) [000336] -A-XG+------ * ASG ref [000335] *--XG+-N---- +--* IND ref [000987] ---XG+------ | \--* ADD byref [000998] ---XG+------ | +--* COMMA byref [000991] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000331] -----+------ | | | +--* LCL_VAR int V09 loc5 [000990] ---X-+------ | | | \--* ARR_LENGTH int [000330] -----+------ | | | \--* LCL_VAR ref V04 loc0 [001001] ----G------- | | \--* ADDR byref [000332] a---G+-N---- | | \--* IND struct [000997] -----+------ | | \--* ADD byref [000988] -----+------ | | +--* LCL_VAR ref V04 loc0 [000996] -----+------ | | \--* ADD long [000994] -----+------ | | +--* LSH long [001000] -----+------ | | | +--* MUL long [000992] -----+------ | | | | +--* CAST long <- int [000989] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000999] ------------ | | | | \--* CNS_INT long 3 [000993] -----+-N---- | | | \--* CNS_INT long 3 [000995] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000986] -----+------ | \--* CNS_INT long 8 field offset Fseq[value] [000334] -----+------ \--* LCL_VAR ref V02 arg2 ------------ BB48 [1B8..1BC) -> BB49 (cond), preds={BB46} succs={BB73,BB49} ***** BB48 STMT00051 (IL 0x1B8...0x1BA) [000291] -----+------ * JTRUE void [000290] N----+-N-U-- \--* EQ int [001002] -----+------ +--* CAST int <- ubyte <- int [000288] -----+------ | \--* LCL_VAR int V03 arg3 [000289] -----+------ \--* CNS_INT int 2 ------------ BB73 [???..???) -> BB54 (always), preds={BB48} succs={BB54} ------------ BB55 [1C4..1DD) -> BB56 (cond), preds={BB40,BB45} succs={BB74,BB56} ***** BB55 STMT00040 (IL 0x1C4...0x1D1) [000222] -A-XG+------ * ASG int [000221] D----+-N---- +--* LCL_VAR int V09 loc5 [000220] *--XG+------ \--* IND int [001009] ---XG+------ \--* ADD byref [001020] ---XG+------ +--* COMMA byref [001013] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000217] -----+------ | | +--* LCL_VAR int V09 loc5 [001012] ---X-+------ | | \--* ARR_LENGTH int [000216] -----+------ | | \--* LCL_VAR ref V04 loc0 [001023] ----G------- | \--* ADDR byref [000218] a---G+-N---- | \--* IND struct [001019] -----+------ | \--* ADD byref [001010] -----+------ | +--* LCL_VAR ref V04 loc0 [001018] -----+------ | \--* ADD long [001016] -----+------ | +--* LSH long [001022] -----+------ | | +--* MUL long [001014] -----+------ | | | +--* CAST long <- int [001011] i----+------ | | | | \--* LCL_VAR int V09 loc5 [001021] ------------ | | | \--* CNS_INT long 3 [001015] -----+-N---- | | \--* CNS_INT long 3 [001017] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [001008] -----+------ \--* CNS_INT long 20 field offset Fseq[next] ***** BB55 STMT00041 (IL 0x1D3...0x1D6) [000227] -A---+------ * ASG int [000226] D----+-N---- +--* LCL_VAR int V07 loc3 [000225] -----+------ \--* ADD int [000223] -----+------ +--* LCL_VAR int V07 loc3 [000224] -----+------ \--* CNS_INT int 1 ***** BB55 STMT00042 (IL 0x1D7...0x1DB) [000232] ---X-+------ * JTRUE void [000231] N--X-+-N-U-- \--* GT int [000228] -----+------ +--* LCL_VAR int V07 loc3 [000230] ---X-+------ \--* ARR_LENGTH int [000229] -----+------ \--* LCL_VAR ref V04 loc0 ------------ BB74 [???..???) -> BB39 (always), preds={BB55} succs={BB39} ------------ BB57 [1E4..1ED) -> BB61 (cond), preds={BB26,BB39} succs={BB58,BB61} ***** BB57 STMT00015 (IL 0x1E4...0x1EB) [000071] ---XG+------ * JTRUE void [000070] J--XG+-N---- \--* LE int [000068] ---XG+------ +--* IND int [001025] -----+------ | \--* ADD byref [000067] -----+------ | +--* LCL_VAR ref V00 this [001024] -----+------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] [000069] -----+------ \--* CNS_INT int 0 ------------ BB58 [1ED..243) -> BB60 (cond), preds={BB57} succs={BB59,BB60} ***** BB58 STMT00035 (IL 0x1ED...0x1F3) [000174] -A-XG+------ * ASG int [000173] D----+-N---- +--* LCL_VAR int V10 loc6 [000172] ---XG+------ \--* IND int [001027] -----+------ \--* ADD byref [000171] -----+------ +--* LCL_VAR ref V00 this [001026] -----+------ \--* CNS_INT long 60 field offset Fseq[_freeList] ***** BB58 STMT00120 (IL 0x1F5... ???) [000688] -A-XG+------ * ASG bool [000687] D----+-N---- +--* LCL_VAR int V49 tmp35 [000184] -A-XG+------ \--* GE int [000182] -A-XG+------ +--* ADD int [001050] -A-XG+------ | +--* NEG int [000181] *A-XG+------ | | \--* IND int [001029] -A-XG+------ | | \--* ADD byref [001044] -A-XG+------ | | +--* COMMA byref [001032] -A-XG+------ | | | +--* ASG int [001031] D----+-N---- | | | | +--* LCL_VAR int V62 tmp48 [000178] ---XG+------ | | | | \--* IND int [001046] -----+------ | | | | \--* ADD byref [000177] -----+------ | | | | +--* LCL_VAR ref V00 this [001045] -----+------ | | | | \--* CNS_INT long 60 field offset Fseq[_freeList] [001043] ---XG+------ | | | \--* COMMA byref [001036] ---X-+------ | | | +--* ARR_BOUNDS_CHECK_Rng void [001033] -----+------ | | | | +--* LCL_VAR int V62 tmp48 [001035] ---X-+------ | | | | \--* ARR_LENGTH int [000176] -----+------ | | | | \--* LCL_VAR ref V04 loc0 [001049] ----G------- | | | \--* ADDR byref [000179] a---G+-N---- | | | \--* IND struct [001042] -----+------ | | | \--* ADD byref [001030] -----+------ | | | +--* LCL_VAR ref V04 loc0 [001041] -----+------ | | | \--* ADD long [001039] -----+------ | | | +--* LSH long [001048] -----+------ | | | | +--* MUL long [001037] -----+------ | | | | | +--* CAST long <- int [001034] i----+------ | | | | | | \--* LCL_VAR int V62 tmp48 [001047] ------------ | | | | | \--* CNS_INT long 3 [001038] -----+-N---- | | | | \--* CNS_INT long 3 [001040] -----+------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] [001028] -----+------ | | \--* CNS_INT long 20 field offset Fseq[next] [000175] -----+------ | \--* CNS_INT int -3 [000183] -----+------ \--* CNS_INT int -1 ***** BB58 STMT00123 (IL 0x1F5... ???) [000698] -A--G+------ * ASG ref [000697] D----+-N---- +--* LCL_VAR ref V50 tmp36 [000684] #---G+------ \--* IND ref [000683] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB58 STMT00121 (IL 0x1F5... ???) [000693] -----+------ * JTRUE void [000692] J----+-N---- \--* NE int [000690] -----+------ +--* LCL_VAR int V49 tmp35 [000691] -----+------ \--* CNS_INT int 0 ------------ BB59 [1F5..1F6), preds={BB58} succs={BB60} ***** BB59 STMT00122 (IL 0x1F5... ???) [000696] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [001052] #---G+------ arg0 in rcx +--* IND ref [001051] H----+------ | \--* CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" [000695] -----+------ arg1 in rdx \--* LCL_VAR ref V50 tmp36 ------------ BB60 [1F5..1F6) -> BB68 (always), preds={BB58,BB59} succs={BB68} ***** BB60 STMT00037 (IL 0x219... ???) [000200] -A-XG+------ * ASG int [000199] ---XG+-N---- +--* IND int [001056] -----+------ | \--* ADD byref [000190] -----+------ | +--* LCL_VAR ref V00 this [001055] -----+------ | \--* CNS_INT long 60 field offset Fseq[_freeList] [000198] -A-XG+------ \--* ADD int [001079] -A-XG+------ +--* NEG int [000197] *A-XG+------ | \--* IND int [001058] -A-XG+------ | \--* ADD byref [001073] -A-XG+------ | +--* COMMA byref [001061] -A-XG+------ | | +--* ASG int [001060] D----+-N---- | | | +--* LCL_VAR int V63 tmp49 [000194] ---XG+------ | | | \--* IND int [001075] -----+------ | | | \--* ADD byref [000193] -----+------ | | | +--* LCL_VAR ref V00 this [001074] -----+------ | | | \--* CNS_INT long 60 field offset Fseq[_freeList] [001072] ---XG+------ | | \--* COMMA byref [001065] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [001062] -----+------ | | | +--* LCL_VAR int V63 tmp49 [001064] ---X-+------ | | | \--* ARR_LENGTH int [000192] -----+------ | | | \--* LCL_VAR ref V04 loc0 [001078] ----G------- | | \--* ADDR byref [000195] a---G+-N---- | | \--* IND struct [001071] -----+------ | | \--* ADD byref [001059] -----+------ | | +--* LCL_VAR ref V04 loc0 [001070] -----+------ | | \--* ADD long [001068] -----+------ | | +--* LSH long [001077] -----+------ | | | +--* MUL long [001066] -----+------ | | | | +--* CAST long <- int [001063] i----+------ | | | | | \--* LCL_VAR int V63 tmp49 [001076] ------------ | | | | \--* CNS_INT long 3 [001067] -----+-N---- | | | \--* CNS_INT long 3 [001069] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [001057] -----+------ | \--* CNS_INT long 20 field offset Fseq[next] [000191] -----+------ \--* CNS_INT int -3 ***** BB60 STMT00038 (IL 0x233...0x23C) [000207] -A-XG+------ * ASG int [000206] ---XG+-N---- +--* IND int [001081] -----+------ | \--* ADD byref [000201] -----+------ | +--* LCL_VAR ref V00 this [001080] -----+------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] [000205] ---XG+------ \--* ADD int [000203] ---XG+------ +--* IND int [001083] -----+------ | \--* ADD byref [000202] -----+------ | +--* LCL_VAR ref V00 this [001082] -----+------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] [000204] -----+------ \--* CNS_INT int -1 ------------ BB61 [243..252) -> BB67 (cond), preds={BB57} succs={BB62,BB67} ***** BB61 STMT00016 (IL 0x243...0x249) [000075] -A-XG+------ * ASG int [000074] D----+-N---- +--* LCL_VAR int V13 loc9 [000073] ---XG+------ \--* IND int [001085] -----+------ \--* ADD byref [000072] -----+------ +--* LCL_VAR ref V00 this [001084] -----+------ \--* CNS_INT long 56 field offset Fseq[_count] ***** BB61 STMT00017 (IL 0x24B...0x250) [000080] ---X-+------ * JTRUE void [000079] N--X-+-N-U-- \--* NE int [000076] -----+------ +--* LCL_VAR int V13 loc9 [000078] ---X-+------ \--* ARR_LENGTH int [000077] -----+------ \--* LCL_VAR ref V04 loc0 ------------ BB62 [252..261) -> BB64 (cond), preds={BB61} succs={BB63,BB64} ***** BB62 STMT00125 (IL 0x252... ???) [000705] --CXG+------ * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [001090] -ACXG-----L- arg1 SETUP +--* ASG int [001089] D------N---- | +--* LCL_VAR int V64 tmp50 [000702] --CXG+------ | \--* CALL int System.Collections.HashHelpers.ExpandPrime [000701] ---XG+------ arg0 in rcx | \--* IND int [001087] -----+------ | \--* ADD byref [000700] -----+------ | +--* LCL_VAR ref V00 this [001086] -----+------ | \--* CNS_INT long 56 field offset Fseq[_count] [001091] ------------ arg1 in rdx +--* LCL_VAR int V64 tmp50 [000163] -----+------ this in rcx +--* LCL_VAR ref V00 this [000704] -----+------ arg2 in r8 \--* CNS_INT int 0 ***** BB62 STMT00126 (IL 0x258... ???) [000711] -A-XG+------ * ASG ref [000710] D----+-N---- +--* LCL_VAR ref V52 tmp38 [000709] ---XG+------ \--* IND ref [001095] -----+------ \--* ADD byref [000165] -----+------ +--* LCL_VAR ref V00 this [001094] -----+------ \--* CNS_INT long 8 field offset Fseq[_buckets] ***** BB62 STMT00133 (IL 0x258... ???) [000760] -A-X-+------ * ASG int [000759] D----+-N---- +--* LCL_VAR int V53 tmp39 [000714] ---X-+------ \--* ARR_LENGTH int [000713] -----+------ \--* LCL_VAR ref V52 tmp38 ***** BB62 STMT00134 (IL 0x258... ???) [000762] -A-XG+------ * ASG long [000761] D----+-N---- +--* LCL_VAR long V54 tmp40 [000716] ---XG+------ \--* IND long [001097] -----+------ \--* ADD byref [000715] -----+------ +--* LCL_VAR ref V00 this [001096] -----+------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] ***** BB62 STMT00136 (IL 0x258... ???) [000773] -A---+------ * ASG bool [000772] D----+-N---- +--* LCL_VAR int V56 tmp42 [000730] N----+---U-- \--* LE int [000728] -----+------ +--* LCL_VAR int V53 tmp39 [000729] -----+------ \--* CNS_INT int 0x7FFFFFFF ***** BB62 STMT00139 (IL 0x258... ???) [000783] -A--G+------ * ASG ref [000782] D----+-N---- +--* LCL_VAR ref V57 tmp43 [000767] #---G+------ \--* IND ref [000766] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB62 STMT00140 (IL 0x258... ???) [000785] -A--G+------ * ASG ref [000784] D----+-N---- +--* LCL_VAR ref V58 tmp44 [000769] #---G+------ \--* IND ref [000768] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB62 STMT00137 (IL 0x258... ???) [000778] -----+------ * JTRUE void [000777] J----+-N---- \--* NE int [000775] -----+------ +--* LCL_VAR int V56 tmp42 [000776] -----+------ \--* CNS_INT int 0 ------------ BB63 [258..259), preds={BB62} succs={BB64} ***** BB63 STMT00138 (IL 0x258... ???) [000781] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000779] -----+------ arg0 in rcx +--* LCL_VAR ref V57 tmp43 [000780] -----+------ arg1 in rdx \--* LCL_VAR ref V58 tmp44 ------------ BB64 [258..259) -> BB66 (cond), preds={BB62,BB63} succs={BB65,BB66} ***** BB64 STMT00131 (IL 0x258... ???) [000750] -A---+------ * ASG int [000749] D----+-N---- +--* LCL_VAR int V55 tmp41 [000748] -----+------ \--* CAST int <- uint <- long [000747] -----+------ \--* RSZ long [000745] -----+------ +--* MUL long [000742] -----+------ | +--* ADD long [000739] -----+------ | | +--* RSZ long [000737] -----+------ | | | +--* MUL long [000735] -----+------ | | | | +--* LCL_VAR long V54 tmp40 [000736] -----+---U-- | | | | \--* CAST long <- ulong <- uint [000166] -----+------ | | | | \--* LCL_VAR int V06 loc2 [000738] -----+------ | | | \--* CNS_INT int 32 [000741] -----+------ | | \--* CNS_INT long 1 [000744] -----+---U-- | \--* CAST long <- ulong <- uint [000743] -----+------ | \--* LCL_VAR int V53 tmp39 [000746] -----+------ \--* CNS_INT int 32 ***** BB64 STMT00142 (IL 0x258... ???) [000796] -A-X-+------ * ASG bool [000795] D----+-N---- +--* LCL_VAR int V59 tmp45 [000755] ---X-+------ \--* EQ int [000751] -----+------ +--* LCL_VAR int V55 tmp41 [000754] ---X-+------ \--* UMOD int [000752] -----+------ +--* LCL_VAR int V06 loc2 [000753] -----+------ \--* LCL_VAR int V53 tmp39 ***** BB64 STMT00145 (IL 0x258... ???) [000806] -A--G+------ * ASG ref [000805] D----+-N---- +--* LCL_VAR ref V60 tmp46 [000790] #---G+------ \--* IND ref [000789] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB64 STMT00146 (IL 0x258... ???) [000808] -A--G+------ * ASG ref [000807] D----+-N---- +--* LCL_VAR ref V61 tmp47 [000792] #---G+------ \--* IND ref [000791] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB64 STMT00143 (IL 0x258... ???) [000801] -----+------ * JTRUE void [000800] J----+-N---- \--* NE int [000798] -----+------ +--* LCL_VAR int V59 tmp45 [000799] -----+------ \--* CNS_INT int 0 ------------ BB65 [258..259), preds={BB64} succs={BB66} ***** BB65 STMT00144 (IL 0x258... ???) [000804] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000802] -----+------ arg0 in rcx +--* LCL_VAR ref V60 tmp46 [000803] -----+------ arg1 in rdx \--* LCL_VAR ref V61 tmp47 ------------ BB66 [258..259), preds={BB64,BB65} succs={BB67} ***** BB66 STMT00128 (IL 0x258... ???) [000722] -A-XG+------ * ASG byref [000721] D----+-N---- +--* LCL_VAR byref V51 tmp37 [001112] ---XG+------ \--* COMMA byref [001105] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000758] -----+------ | +--* LCL_VAR int V55 tmp41 [001104] ---X-+------ | \--* ARR_LENGTH int [000712] -----+------ | \--* LCL_VAR ref V52 tmp38 [001113] ----G------- \--* ADDR byref [000719] a---G+-N---- \--* IND int [001111] -----+------ \--* ADD byref [001102] -----+------ +--* LCL_VAR ref V52 tmp38 [001110] -----+------ \--* ADD long [001108] -----+------ +--* LSH long [001106] -----+------ | +--* CAST long <- int [001103] i----+------ | | \--* LCL_VAR int V55 tmp41 [001107] -----+-N---- | \--* CNS_INT long 2 [001109] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB66 STMT00129 (IL 0x258... ???) [000726] -A---+------ * ASG ref [000725] D----+-N---- +--* LCL_VAR ref V52 tmp38 [000724] -----+------ \--* CNS_INT ref null ***** BB66 STMT00034 (IL ???... ???) [000170] -A---+------ * ASG byref [000169] D----+-N---- +--* LCL_VAR byref V08 loc4 [000723] -----+------ \--* LCL_VAR byref V51 tmp37 ------------ BB67 [261..276), preds={BB61,BB66} succs={BB68} ***** BB67 STMT00018 (IL 0x261...0x263) [000083] -A---+------ * ASG int [000082] D----+-N---- +--* LCL_VAR int V10 loc6 [000081] -----+------ \--* LCL_VAR int V13 loc9 ***** BB67 STMT00019 (IL 0x265...0x26A) [000089] -A-XG+------ * ASG int [000088] ---XG+-N---- +--* IND int [001115] -----+------ | \--* ADD byref [000084] -----+------ | +--* LCL_VAR ref V00 this [001114] -----+------ | \--* CNS_INT long 56 field offset Fseq[_count] [000087] -----+------ \--* ADD int [000085] -----+------ +--* LCL_VAR int V13 loc9 [000086] -----+------ \--* CNS_INT int 1 ***** BB67 STMT00020 (IL 0x26F...0x275) [000093] -A-XG+------ * ASG ref [000092] D----+-N---- +--* LCL_VAR ref V04 loc0 [000091] ---XG+------ \--* IND ref [001117] -----+------ \--* ADD byref [000090] -----+------ +--* LCL_VAR ref V00 this [001116] -----+------ \--* CNS_INT long 16 field offset Fseq[_entries] ------------ BB68 [276..2CF) -> BB71 (cond), preds={BB60,BB67} succs={BB69,BB71} ***** BB68 STMT00021 (IL 0x276...0x27E) [000099] -A-XG+------ * ASG byref [000098] D----+-N---- +--* LCL_VAR byref V11 loc7 [001128] ---XG+------ \--* COMMA byref [001121] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000095] -----+------ | +--* LCL_VAR int V10 loc6 [001120] ---X-+------ | \--* ARR_LENGTH int [000094] -----+------ | \--* LCL_VAR ref V04 loc0 [001131] ----G------- \--* ADDR byref [000096] a---G+-N---- \--* IND struct [001127] -----+------ \--* ADD byref [001118] -----+------ +--* LCL_VAR ref V04 loc0 [001126] -----+------ \--* ADD long [001124] -----+------ +--* LSH long [001130] -----+------ | +--* MUL long [001122] -----+------ | | +--* CAST long <- int [001119] i----+------ | | | \--* LCL_VAR int V10 loc6 [001129] ------------ | | \--* CNS_INT long 3 [001123] -----+-N---- | \--* CNS_INT long 3 [001125] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB68 STMT00022 (IL 0x280...0x283) [000103] -A-XG+------ * ASG int [000102] *--XG+-N---- +--* IND int [001133] -----+------ | \--* ADD byref [000100] -----+------ | +--* LCL_VAR byref V11 loc7 [001132] -----+------ | \--* CNS_INT long 16 field offset Fseq[hashCode] [000101] -----+------ \--* LCL_VAR int V06 loc2 ***** BB68 STMT00023 (IL 0x288...0x28F) [000110] -A-XG+------ * ASG int [000109] *--XG+-N---- +--* IND int [001135] -----+------ | \--* ADD byref [000104] -----+------ | +--* LCL_VAR byref V11 loc7 [001134] -----+------ | \--* CNS_INT long 20 field offset Fseq[next] [000108] ---XG+------ \--* ADD int [000106] *--XG+------ +--* IND int [000105] -----+------ | \--* LCL_VAR byref V08 loc4 [000107] -----+------ \--* CNS_INT int -1 ***** BB68 STMT00024 (IL 0x294...0x297) [000114] -A-XG+------ * ASG ref [000113] *--XG+-N---- +--* IND ref [000111] -----+------ | \--* LCL_VAR byref V11 loc7 Zero Fseq[key] [000112] -----+------ \--* LCL_VAR ref V01 arg1 ***** BB68 STMT00025 (IL 0x29C...0x29F) [000118] -A-XG+------ * ASG ref [000117] *--XG+-N---- +--* IND ref [001137] -----+------ | \--* ADD byref [000115] -----+------ | +--* LCL_VAR byref V11 loc7 [001136] -----+------ | \--* CNS_INT long 8 field offset Fseq[value] [000116] -----+------ \--* LCL_VAR ref V02 arg2 ***** BB68 STMT00026 (IL 0x2A4...0x2AA) [000124] -A-XG+------ * ASG int [000123] *--X-+-N---- +--* IND int [000119] -----+------ | \--* LCL_VAR byref V08 loc4 [000122] -----+------ \--* ADD int [000120] -----+------ +--* LCL_VAR int V10 loc6 [000121] -----+------ \--* CNS_INT int 1 ***** BB68 STMT00027 (IL 0x2AB...0x2B4) [000131] -A-XG+------ * ASG int [000130] ---XG+-N---- +--* IND int [001139] -----+------ | \--* ADD byref [000125] -----+------ | +--* LCL_VAR ref V00 this [001138] -----+------ | \--* CNS_INT long 68 field offset Fseq[_version] [000129] ---XG+------ \--* ADD int [000127] ---XG+------ +--* IND int [001141] -----+------ | \--* ADD byref [000126] -----+------ | +--* LCL_VAR ref V00 this [001140] -----+------ | \--* CNS_INT long 68 field offset Fseq[_version] [000128] -----+------ \--* CNS_INT int 1 ***** BB68 STMT00028 (IL 0x2CA...0x2CD) [000148] -----+------ * JTRUE void [000147] N----+-N-U-- \--* LE int [000145] -----+------ +--* LCL_VAR int V07 loc3 [000146] -----+------ \--* CNS_INT int 100 ------------ BB69 [2CF..2D7) -> BB71 (cond), preds={BB68} succs={BB70,BB71} ***** BB69 STMT00030 (IL 0x2CF...0x2D5) [000156] --C-G+------ * JTRUE void [000155] J-C-G+-N---- \--* EQ int [000153] --C-G+------ +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS [000151] -----+------ arg1 in rdx | +--* LCL_VAR ref V05 loc1 [000152] H----+-N---- arg0 in rcx | \--* CNS_INT(h) long 0xd1ffab1e class [000154] -----+------ \--* CNS_INT ref null ------------ BB70 [2D7..2E3), preds={BB69} succs={BB71} ***** BB70 STMT00031 (IL 0x2D7...0x2DC) [000161] --CXG+------ * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [000159] ---X-+------ arg1 in rdx +--* ARR_LENGTH int [000158] -----+------ | \--* LCL_VAR ref V04 loc0 [000157] -----+------ this in rcx +--* LCL_VAR ref V00 this [000160] -----+------ arg2 in r8 \--* CNS_INT int 1 ------------ BB71 [???..???) (return), preds={BB30,BB47,BB68,BB69,BB70} succs={} ***** BB71 STMT00147 (IL ???... ???) [000810] -----+------ * RETURN int [000482] -----+------ \--* CNS_INT int 1 ------------ BB02 [008..00E) (throw), preds={BB01} succs={} ***** BB02 STMT00086 (IL 0x008...0x009) [000533] --CXG+------ * CALL void System.ThrowHelper.ThrowArgumentNullException [000532] -----+------ arg0 in rcx \--* CNS_INT int 4 ------------ BB32 [14F..???) -> BB35 (cond), preds={BB31} succs={BB34,BB35} ***** BB32 STMT00073 (IL 0x14F...0x150) [000444] -A-X-+------ * ASG long [000443] D----+-N---- +--* LCL_VAR long V26 tmp12 [000442] #--X-+------ \--* IND long [000441] !----+------ \--* LCL_VAR ref V00 this ***** BB32 STMT00074 (IL ???... ???) [000454] -A---+------ * ASG ref [000453] D----+-N---- +--* LCL_VAR ref V27 tmp13 [000439] -----+------ \--* LCL_VAR ref V01 arg1 ***** BB32 STMT00155 (IL ???... ???) [001158] ------------ * JTRUE void [000460] J----+-N---- \--* EQ int [000456] n----+------ +--* IND long [000452] -----+------ | \--* ADD long [000450] #----+------ | +--* IND long [000449] #----+------ | | \--* IND long [000448] -----+------ | | \--* ADD long [000446] -----+------ | | +--* LCL_VAR long V26 tmp12 [000447] -----+------ | | \--* CNS_INT long 56 [000451] -----+------ | \--* CNS_INT long 56 [000459] -----+------ \--* CNS_INT long 0 ------------ BB34 [???..???) -> BB36 (always), preds={BB32} succs={BB36} ***** BB34 STMT00156 (IL ???... ???) [001160] -A---------- * ASG long [001159] D------N---- +--* LCL_VAR long V28 tmp14 [000461] n----+?----- \--* IND long [000462] -----+?----- \--* ADD long [000463] #----+?----- +--* IND long [000464] #----+?----- | \--* IND long [000465] -----+?----- | \--* ADD long [000466] -----+?----- | +--* LCL_VAR long V26 tmp12 [000467] -----+?----- | \--* CNS_INT long 56 [000468] -----+?----- \--* CNS_INT long 56 ------------ BB35 [???..???), preds={BB32} succs={BB36} ***** BB35 STMT00157 (IL ???... ???) [001162] -AC-G------- * ASG long [001161] D------N---- +--* LCL_VAR long V28 tmp14 [000458] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000445] -----+?----- arg0 in rcx +--* LCL_VAR long V26 tmp12 [000457] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB36 [???..157) (throw), preds={BB34,BB35} succs={} ***** BB36 STMT00076 (IL ???... ???) [000440] --CXG+------ * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000473] -----+------ arg0 in rcx +--* LCL_VAR long V28 tmp14 [000455] -----+------ arg1 in rdx \--* LCL_VAR ref V01 arg1 ------------ BB49 [1BC..???) -> BB52 (cond), preds={BB48} succs={BB51,BB52} ***** BB49 STMT00053 (IL 0x1BC...0x1BD) [000299] -A-X-+------ * ASG long [000298] D----+-N---- +--* LCL_VAR long V21 tmp7 [000297] #--X-+------ \--* IND long [000296] !----+------ \--* LCL_VAR ref V00 this ***** BB49 STMT00054 (IL ???... ???) [000309] -A---+------ * ASG ref [000308] D----+-N---- +--* LCL_VAR ref V22 tmp8 [000294] -----+------ \--* LCL_VAR ref V01 arg1 ***** BB49 STMT00161 (IL ???... ???) [001168] ------------ * JTRUE void [000315] J----+-N---- \--* EQ int [000311] n----+------ +--* IND long [000307] -----+------ | \--* ADD long [000305] #----+------ | +--* IND long [000304] #----+------ | | \--* IND long [000303] -----+------ | | \--* ADD long [000301] -----+------ | | +--* LCL_VAR long V21 tmp7 [000302] -----+------ | | \--* CNS_INT long 56 [000306] -----+------ | \--* CNS_INT long 56 [000314] -----+------ \--* CNS_INT long 0 ------------ BB51 [???..???) -> BB53 (always), preds={BB49} succs={BB53} ***** BB51 STMT00162 (IL ???... ???) [001170] -A---------- * ASG long [001169] D------N---- +--* LCL_VAR long V23 tmp9 [000316] n----+?----- \--* IND long [000317] -----+?----- \--* ADD long [000318] #----+?----- +--* IND long [000319] #----+?----- | \--* IND long [000320] -----+?----- | \--* ADD long [000321] -----+?----- | +--* LCL_VAR long V21 tmp7 [000322] -----+?----- | \--* CNS_INT long 56 [000323] -----+?----- \--* CNS_INT long 56 ------------ BB52 [???..???), preds={BB49} succs={BB53} ***** BB52 STMT00163 (IL ???... ???) [001172] -AC-G------- * ASG long [001171] D------N---- +--* LCL_VAR long V23 tmp9 [000313] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000300] -----+?----- arg0 in rcx +--* LCL_VAR long V21 tmp7 [000312] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB53 [???..1C4) (throw), preds={BB51,BB52} succs={} ***** BB53 STMT00056 (IL ???... ???) [000295] --CXG+------ * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000328] -----+------ arg0 in rcx +--* LCL_VAR long V23 tmp9 [000310] -----+------ arg1 in rdx \--* LCL_VAR ref V01 arg1 ------------ BB56 [1DD..1E4) (throw), preds={BB37,BB55} succs={} ***** BB56 STMT00043 (IL 0x1DD...0x1E2) [000233] --CXG+------ * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Compute blocks reachability *************** In fgComputeReachability *************** In fgDebugCheckBBlist Renumbering the basic blocks for fgComputeReachability pass #1 *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB02 ( cond ) i BB03 [0002] 1 BB01 1 [00E..016)-> BB05 ( cond ) i BB04 [0003] 1 BB03 1 [016..01E) i hascall gcsafe BB05 [0004] 2 BB03,BB04 1 [01E..04B)-> BB07 ( cond ) i BB06 [0052] 1 BB05 1 [01E..01F) i hascall gcsafe BB07 [0053] 2 BB05,BB06 1 [01E..034)-> BB09 ( cond ) i BB08 [0057] 1 BB07 1 [033..034) i hascall gcsafe BB09 [0058] 2 BB07,BB08 1 [033..034)-> BB15 ( cond ) i BB10 [0005] 1 BB09 1 [04B..???)-> BB13 ( cond ) i hascall gcsafe BB12 [0097] 1 BB10 0.50 [???..???)-> BB14 (always) i BB13 [0096] 1 BB10 0.50 [???..???) i BB14 [0094] 2 BB12,BB13 1 [???..054)-> BB16 (always) i hascall gcsafe BB15 [0006] 1 BB09 1 [054..061) i hascall gcsafe BB16 [0007] 2 BB14,BB15 1 [061..07A)-> BB18 ( cond ) i idxlen BB17 [0064] 1 BB16 1 [064..065) i hascall gcsafe BB18 [0065] 2 BB16,BB17 1 [064..065)-> BB20 ( cond ) i idxlen BB19 [0069] 1 BB18 1 [064..065) i hascall gcsafe BB20 [0070] 2 BB18,BB19 1 [064..065)-> BB39 ( cond ) i idxlen BB21 [0008] 1 BB20 1 [07A..???)-> BB24 ( cond ) i hascall gcsafe BB23 [0101] 1 BB21 0.50 [???..???)-> BB25 (always) i BB24 [0100] 1 BB21 0.50 [???..???) i BB25 [0098] 2 BB23,BB24 1 [???..106) i hascall gcsafe BB26 [0020] 2 BB25,BB72 1 [106..110)-> BB57 ( cond ) i idxlen bwd bwd-target BB27 [0021] 1 BB26 1 [110..120)-> BB37 ( cond ) i idxlen bwd BB28 [0022] 1 BB27 1 [120..137)-> BB37 ( cond ) i hascall gcsafe idxlen bwd BB29 [0023] 1 BB28 1 [137..13B)-> BB31 ( cond ) i bwd BB30 [0024] 1 BB29 1 [13B..14B)-> BB71 (always) i idxlen BB31 [0025] 1 BB29 1 [14B..14F)-> BB32 ( cond ) i bwd BB54 [0092] 2 BB31,BB73 1 [???..???) (return) internal BB37 [0028] 2 BB27,BB28 1 [157..170)-> BB56 ( cond ) i idxlen bwd BB72 [0114] 1 BB37 1 [???..???)-> BB26 (always) internal BB39 [0030] 2 BB20,BB74 1 [177..17E)-> BB57 ( cond ) i idxlen bwd bwd-target BB40 [0031] 1 BB39 1 [17E..18E)-> BB55 ( cond ) i idxlen bwd BB41 [0032] 1 BB40 1 [18E..???)-> BB44 ( cond ) i hascall gcsafe idxlen bwd BB43 [0109] 1 BB41 0.50 [???..???)-> BB45 (always) i BB44 [0108] 1 BB41 0.50 [???..???) i BB45 [0106] 2 BB43,BB44 1 [???..1A4)-> BB55 ( cond ) i hascall gcsafe idxlen bwd BB46 [0033] 1 BB45 1 [1A4..1A8)-> BB48 ( cond ) i bwd BB47 [0034] 1 BB46 1 [1A8..1B8)-> BB71 (always) i idxlen BB48 [0035] 1 BB46 1 [1B8..1BC)-> BB49 ( cond ) i bwd BB73 [0115] 1 BB48 1 [???..???)-> BB54 (always) internal BB55 [0038] 2 BB40,BB45 1 [1C4..1DD)-> BB56 ( cond ) i idxlen bwd BB74 [0116] 1 BB55 1 [???..???)-> BB39 (always) internal BB57 [0040] 2 BB26,BB39 1 [1E4..1ED)-> BB61 ( cond ) i BB58 [0041] 1 BB57 1 [1ED..243)-> BB60 ( cond ) i idxlen BB59 [0075] 1 BB58 1 [1F5..1F6) i hascall gcsafe BB60 [0076] 2 BB58,BB59 1 [1F5..1F6)-> BB68 (always) i idxlen BB61 [0042] 1 BB57 1 [243..252)-> BB67 ( cond ) i idxlen BB62 [0043] 1 BB61 1 [252..261)-> BB64 ( cond ) i hascall gcsafe idxlen BB63 [0083] 1 BB62 1 [258..259) i hascall gcsafe BB64 [0084] 2 BB62,BB63 1 [258..259)-> BB66 ( cond ) i idxlen BB65 [0088] 1 BB64 1 [258..259) i hascall gcsafe BB66 [0089] 2 BB64,BB65 1 [258..259) i idxlen BB67 [0044] 2 BB61,BB66 1 [261..276) i BB68 [0045] 2 BB60,BB67 1 [276..2CF)-> BB71 ( cond ) i idxlen BB69 [0047] 1 BB68 1 [2CF..2D7)-> BB71 ( cond ) i hascall BB70 [0048] 1 BB69 1 [2D7..2E3) i hascall gcsafe idxlen BB71 [0091] 5 BB30,BB47,BB68,BB69,BB70 1 [???..???) (return) internal BB02 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB32 [0026] 1 BB31 0 [14F..???)-> BB35 ( cond ) i rare hascall gcsafe bwd BB34 [0105] 1 BB32 0 [???..???)-> BB36 (always) i rare BB35 [0104] 1 BB32 0 [???..???) i rare BB36 [0102] 2 BB34,BB35 0 [???..157) (throw ) i rare hascall gcsafe bwd BB49 [0036] 1 BB48 0 [1BC..???)-> BB52 ( cond ) i rare hascall gcsafe bwd BB51 [0113] 1 BB49 0 [???..???)-> BB53 (always) i rare BB52 [0112] 1 BB49 0 [???..???) i rare BB53 [0110] 2 BB51,BB52 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB56 [0039] 2 BB37,BB55 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB03 to BB02 Renumber BB04 to BB03 Renumber BB05 to BB04 Renumber BB06 to BB05 Renumber BB07 to BB06 Renumber BB08 to BB07 Renumber BB09 to BB08 Renumber BB10 to BB09 Renumber BB12 to BB10 Renumber BB13 to BB11 Renumber BB14 to BB12 Renumber BB15 to BB13 Renumber BB16 to BB14 Renumber BB17 to BB15 Renumber BB18 to BB16 Renumber BB19 to BB17 Renumber BB20 to BB18 Renumber BB21 to BB19 Renumber BB23 to BB20 Renumber BB24 to BB21 Renumber BB25 to BB22 Renumber BB26 to BB23 Renumber BB27 to BB24 Renumber BB28 to BB25 Renumber BB29 to BB26 Renumber BB30 to BB27 Renumber BB31 to BB28 Renumber BB54 to BB29 Renumber BB37 to BB30 Renumber BB72 to BB31 Renumber BB39 to BB32 Renumber BB40 to BB33 Renumber BB41 to BB34 Renumber BB43 to BB35 Renumber BB44 to BB36 Renumber BB45 to BB37 Renumber BB46 to BB38 Renumber BB47 to BB39 Renumber BB48 to BB40 Renumber BB73 to BB41 Renumber BB55 to BB42 Renumber BB74 to BB43 Renumber BB57 to BB44 Renumber BB58 to BB45 Renumber BB59 to BB46 Renumber BB60 to BB47 Renumber BB61 to BB48 Renumber BB62 to BB49 Renumber BB63 to BB50 Renumber BB64 to BB51 Renumber BB65 to BB52 Renumber BB66 to BB53 Renumber BB67 to BB54 Renumber BB68 to BB55 Renumber BB69 to BB56 Renumber BB70 to BB57 Renumber BB71 to BB58 Renumber BB02 to BB59 Renumber BB32 to BB60 Renumber BB34 to BB61 Renumber BB35 to BB62 Renumber BB36 to BB63 Renumber BB49 to BB64 Renumber BB51 to BB65 Renumber BB52 to BB66 Renumber BB53 to BB67 Renumber BB56 to BB68 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 1 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 1 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 1 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 1 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.50 [???..???)-> BB12 (always) i BB11 [0096] 1 BB09 0.50 [???..???) i BB12 [0094] 2 BB10,BB11 1 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 1 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i idxlen BB15 [0064] 1 BB14 1 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i idxlen BB17 [0069] 1 BB16 1 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i idxlen BB19 [0008] 1 BB18 1 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.50 [???..???)-> BB22 (always) i BB21 [0100] 1 BB19 0.50 [???..???) i BB22 [0098] 2 BB20,BB21 1 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB31 1 [106..110)-> BB44 ( cond ) i idxlen bwd bwd-target BB24 [0021] 1 BB23 1 [110..120)-> BB30 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 1 [120..137)-> BB30 ( cond ) i hascall gcsafe idxlen bwd BB26 [0023] 1 BB25 1 [137..13B)-> BB28 ( cond ) i bwd BB27 [0024] 1 BB26 1 [13B..14B)-> BB58 (always) i idxlen BB28 [0025] 1 BB26 1 [14B..14F)-> BB60 ( cond ) i bwd BB29 [0092] 2 BB28,BB41 1 [???..???) (return) internal BB30 [0028] 2 BB24,BB25 1 [157..170)-> BB68 ( cond ) i idxlen bwd BB31 [0114] 1 BB30 1 [???..???)-> BB23 (always) internal BB32 [0030] 2 BB18,BB43 1 [177..17E)-> BB44 ( cond ) i idxlen bwd bwd-target BB33 [0031] 1 BB32 1 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 1 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 0.50 [???..???)-> BB37 (always) i BB36 [0108] 1 BB34 0.50 [???..???) i BB37 [0106] 2 BB35,BB36 1 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 1 [1A4..1A8)-> BB40 ( cond ) i bwd BB39 [0034] 1 BB38 1 [1A8..1B8)-> BB58 (always) i idxlen BB40 [0035] 1 BB38 1 [1B8..1BC)-> BB64 ( cond ) i bwd BB41 [0115] 1 BB40 1 [???..???)-> BB29 (always) internal BB42 [0038] 2 BB33,BB37 1 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 1 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 1 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 1 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 1 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 1 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 1 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 1 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 1 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 1 [258..259)-> BB53 ( cond ) i idxlen BB52 [0088] 1 BB51 1 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 1 [258..259) i idxlen BB54 [0044] 2 BB48,BB53 1 [261..276) i BB55 [0045] 2 BB47,BB54 1 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 1 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 1 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB27,BB39,BB55,BB56,BB57 1 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB28 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare BB62 [0104] 1 BB60 0 [???..???) i rare BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare BB66 [0112] 1 BB64 0 [???..???) i rare BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB30,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 5, # of blocks (including unused BB00): 69, bitset array size: 2 (long) Enter blocks: BB01 After computing reachability sets: ------------------------------------------------ BBnum Reachable by ------------------------------------------------ BB01 : BB01 BB02 : BB01 BB02 BB03 : BB01 BB02 BB03 BB04 : BB01 BB02 BB03 BB04 BB05 : BB01 BB02 BB03 BB04 BB05 BB06 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB13 BB14 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB21 BB22 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB30 BB31 BB24 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB30 BB31 BB25 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB30 BB31 BB26 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB30 BB31 BB27 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB30 BB31 BB28 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB28 BB30 BB31 BB29 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB28 BB29 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB40 BB41 BB42 BB43 BB30 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB30 BB31 BB31 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB30 BB31 BB32 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB33 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB34 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB35 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB36 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB37 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB38 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB42 BB43 BB39 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB42 BB43 BB40 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB40 BB42 BB43 BB41 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB40 BB41 BB42 BB43 BB42 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB43 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB45 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB45 BB46 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB45 BB46 BB47 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB45 BB46 BB47 BB48 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB48 BB49 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB48 BB49 BB50 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB48 BB49 BB50 BB51 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB48 BB49 BB50 BB51 BB52 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB48 BB49 BB50 BB51 BB52 BB53 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB48 BB49 BB50 BB51 BB52 BB53 BB54 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 BB58 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 BB58 BB59 : BB01 BB59 BB60 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB28 BB30 BB31 BB60 BB61 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB28 BB30 BB31 BB60 BB61 BB62 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB28 BB30 BB31 BB60 BB62 BB63 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB28 BB30 BB31 BB60 BB61 BB62 BB63 BB64 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB40 BB42 BB43 BB64 BB65 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB40 BB42 BB43 BB64 BB65 BB66 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB40 BB42 BB43 BB64 BB66 BB67 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB40 BB42 BB43 BB64 BB65 BB66 BB67 BB68 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB68 After computing reachability: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 1 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 1 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 1 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 1 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.50 [???..???)-> BB12 (always) i gcsafe BB11 [0096] 1 BB09 0.50 [???..???) i gcsafe BB12 [0094] 2 BB10,BB11 1 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 1 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen BB15 [0064] 1 BB14 1 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen BB17 [0069] 1 BB16 1 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen BB19 [0008] 1 BB18 1 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.50 [???..???)-> BB22 (always) i gcsafe BB21 [0100] 1 BB19 0.50 [???..???) i gcsafe BB22 [0098] 2 BB20,BB21 1 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB31 1 [106..110)-> BB44 ( cond ) i Loop idxlen bwd bwd-target BB24 [0021] 1 BB23 1 [110..120)-> BB30 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 1 [120..137)-> BB30 ( cond ) i hascall gcsafe idxlen bwd BB26 [0023] 1 BB25 1 [137..13B)-> BB28 ( cond ) i gcsafe bwd BB27 [0024] 1 BB26 1 [13B..14B)-> BB58 (always) i gcsafe idxlen BB28 [0025] 1 BB26 1 [14B..14F)-> BB60 ( cond ) i gcsafe bwd BB29 [0092] 2 BB28,BB41 1 [???..???) (return) internal gcsafe BB30 [0028] 2 BB24,BB25 1 [157..170)-> BB68 ( cond ) i idxlen bwd BB31 [0114] 1 BB30 1 [???..???)-> BB23 (always) internal BB32 [0030] 2 BB18,BB43 1 [177..17E)-> BB44 ( cond ) i Loop idxlen bwd bwd-target BB33 [0031] 1 BB32 1 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 1 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 0.50 [???..???)-> BB37 (always) i gcsafe BB36 [0108] 1 BB34 0.50 [???..???) i gcsafe BB37 [0106] 2 BB35,BB36 1 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 1 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd BB39 [0034] 1 BB38 1 [1A8..1B8)-> BB58 (always) i gcsafe idxlen BB40 [0035] 1 BB38 1 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd BB41 [0115] 1 BB40 1 [???..???)-> BB29 (always) internal gcsafe BB42 [0038] 2 BB33,BB37 1 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 1 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 1 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 1 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 1 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 1 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 1 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 1 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 1 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 1 [258..259)-> BB53 ( cond ) i gcsafe idxlen BB52 [0088] 1 BB51 1 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 1 [258..259) i gcsafe idxlen BB54 [0044] 2 BB48,BB53 1 [261..276) i BB55 [0045] 2 BB47,BB54 1 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 1 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 1 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB27,BB39,BB55,BB56,BB57 1 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB28 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB30,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgComputeDoms *************** In fgDebugCheckBBlist Dominator computation start blocks (those blocks with no incoming edges): BB01 ------------------------------------------------ BBnum Dominated by ------------------------------------------------ BB01: BB01 BB02: BB02 BB01 BB03: BB03 BB02 BB01 BB04: BB04 BB02 BB01 BB05: BB05 BB04 BB02 BB01 BB06: BB06 BB04 BB02 BB01 BB07: BB07 BB06 BB04 BB02 BB01 BB08: BB08 BB06 BB04 BB02 BB01 BB09: BB09 BB08 BB06 BB04 BB02 BB01 BB10: BB10 BB09 BB08 BB06 BB04 BB02 BB01 BB11: BB11 BB09 BB08 BB06 BB04 BB02 BB01 BB12: BB12 BB09 BB08 BB06 BB04 BB02 BB01 BB13: BB13 BB08 BB06 BB04 BB02 BB01 BB14: BB14 BB08 BB06 BB04 BB02 BB01 BB15: BB15 BB14 BB08 BB06 BB04 BB02 BB01 BB16: BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB17: BB17 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB18: BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB19: BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB20: BB20 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB21: BB21 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB22: BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB23: BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB24: BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB25: BB25 BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB26: BB26 BB25 BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB27: BB27 BB26 BB25 BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB28: BB28 BB26 BB25 BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB60: BB60 BB28 BB26 BB25 BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB61: BB61 BB60 BB28 BB26 BB25 BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB62: BB62 BB60 BB28 BB26 BB25 BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB63: BB63 BB60 BB28 BB26 BB25 BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB30: BB30 BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB31: BB31 BB30 BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB32: BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB33: BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB34: BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB35: BB35 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB36: BB36 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB37: BB37 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB38: BB38 BB37 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB39: BB39 BB38 BB37 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB40: BB40 BB38 BB37 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB41: BB41 BB40 BB38 BB37 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB29: BB29 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB64: BB64 BB40 BB38 BB37 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB65: BB65 BB64 BB40 BB38 BB37 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB66: BB66 BB64 BB40 BB38 BB37 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB67: BB67 BB64 BB40 BB38 BB37 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB42: BB42 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB43: BB43 BB42 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB68: BB68 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB44: BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB45: BB45 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB46: BB46 BB45 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB47: BB47 BB45 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB48: BB48 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB49: BB49 BB48 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB50: BB50 BB49 BB48 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB51: BB51 BB49 BB48 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB52: BB52 BB51 BB49 BB48 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB53: BB53 BB51 BB49 BB48 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB54: BB54 BB48 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB55: BB55 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB56: BB56 BB55 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB57: BB57 BB56 BB55 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB58: BB58 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB59: BB59 BB01 Inside fgBuildDomTree After computing the Dominance Tree: BB01 : BB59 BB02 BB02 : BB04 BB03 BB04 : BB06 BB05 BB06 : BB08 BB07 BB08 : BB14 BB13 BB09 BB09 : BB12 BB11 BB10 BB14 : BB16 BB15 BB16 : BB18 BB17 BB18 : BB68 BB58 BB44 BB32 BB29 BB19 BB19 : BB22 BB21 BB20 BB22 : BB23 BB23 : BB24 BB24 : BB30 BB25 BB25 : BB26 BB26 : BB28 BB27 BB28 : BB60 BB30 : BB31 BB32 : BB33 BB33 : BB42 BB34 BB34 : BB37 BB36 BB35 BB37 : BB38 BB38 : BB40 BB39 BB40 : BB64 BB41 BB42 : BB43 BB44 : BB55 BB48 BB45 BB45 : BB47 BB46 BB48 : BB54 BB49 BB49 : BB51 BB50 BB51 : BB53 BB52 BB55 : BB56 BB56 : BB57 BB60 : BB63 BB62 BB61 BB64 : BB67 BB66 BB65 After numbering the dominator tree: BB01: pre=01, post=68 BB02: pre=03, post=67 BB03: pre=68, post=66 BB04: pre=04, post=65 BB05: pre=67, post=64 BB06: pre=05, post=63 BB07: pre=66, post=62 BB08: pre=06, post=61 BB09: pre=62, post=60 BB10: pre=65, post=59 BB11: pre=64, post=58 BB12: pre=63, post=57 BB13: pre=61, post=56 BB14: pre=07, post=55 BB15: pre=60, post=54 BB16: pre=08, post=53 BB17: pre=59, post=52 BB18: pre=09, post=51 BB19: pre=43, post=50 BB20: pre=58, post=49 BB21: pre=57, post=48 BB22: pre=44, post=47 BB23: pre=45, post=46 BB24: pre=46, post=45 BB25: pre=49, post=44 BB26: pre=50, post=43 BB27: pre=56, post=42 BB28: pre=51, post=41 BB29: pre=42, post=34 BB30: pre=47, post=36 BB31: pre=48, post=35 BB32: pre=26, post=33 BB33: pre=27, post=32 BB34: pre=30, post=31 BB35: pre=41, post=30 BB36: pre=40, post=29 BB37: pre=31, post=28 BB38: pre=32, post=27 BB39: pre=39, post=26 BB40: pre=33, post=25 BB41: pre=38, post=24 BB42: pre=28, post=19 BB43: pre=29, post=18 BB44: pre=12, post=17 BB45: pre=23, post=16 BB46: pre=25, post=15 BB47: pre=24, post=14 BB48: pre=16, post=13 BB49: pre=18, post=12 BB50: pre=22, post=11 BB51: pre=19, post=10 BB52: pre=21, post=09 BB53: pre=20, post=08 BB54: pre=17, post=07 BB55: pre=13, post=06 BB56: pre=14, post=05 BB57: pre=15, post=04 BB58: pre=11, post=03 BB59: pre=02, post=01 BB60: pre=52, post=40 BB61: pre=55, post=39 BB62: pre=54, post=38 BB63: pre=53, post=37 BB64: pre=34, post=23 BB65: pre=37, post=22 BB66: pre=36, post=21 BB67: pre=35, post=20 BB68: pre=10, post=02 *************** Finishing PHASE Compute blocks reachability *************** Starting PHASE Find loops *************** In optFindLoops() After optSetBlockWeights: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB31 0.50 [106..110)-> BB44 ( cond ) i Loop idxlen bwd bwd-target BB24 [0021] 1 BB23 0.50 [110..120)-> BB30 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 0.50 [120..137)-> BB30 ( cond ) i hascall gcsafe idxlen bwd BB26 [0023] 1 BB25 0.50 [137..13B)-> BB28 ( cond ) i gcsafe bwd BB27 [0024] 1 BB26 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen BB28 [0025] 1 BB26 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd BB29 [0092] 2 BB28,BB41 0.50 [???..???) (return) internal gcsafe BB30 [0028] 2 BB24,BB25 0.50 [157..170)-> BB68 ( cond ) i idxlen bwd BB31 [0114] 1 BB30 0.50 [???..???)-> BB23 (always) internal BB32 [0030] 2 BB18,BB43 0.50 [177..17E)-> BB44 ( cond ) i Loop idxlen bwd bwd-target BB33 [0031] 1 BB32 0.50 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 0.50 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 0.25 [???..???)-> BB37 (always) i gcsafe BB36 [0108] 1 BB34 0.25 [???..???) i gcsafe BB37 [0106] 2 BB35,BB36 0.50 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd BB41 [0115] 1 BB40 0.50 [???..???)-> BB29 (always) internal gcsafe BB42 [0038] 2 BB33,BB37 0.50 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 0.50 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen BB54 [0044] 2 BB48,BB53 0.50 [261..276) i BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB27,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB28 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB30,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In optFindNaturalLoops() Relocated blocks [BB26..BB29] inserted after BB31 Recorded loop L00, from BB23 to BB31 (Head=BB22, Entry=BB23, ExitCnt=3) *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB31 0.50 [106..110)-> BB44 ( cond ) i Loop idxlen bwd bwd-target BB24 [0021] 1 BB23 0.50 [110..120)-> BB30 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 0.50 [120..137)-> BB26 ( cond ) i hascall gcsafe idxlen bwd BB30 [0028] 2 BB24,BB25 0.50 [157..170)-> BB68 ( cond ) i idxlen bwd BB31 [0114] 1 BB30 0.50 [???..???)-> BB23 (always) internal BB26 [0023] 1 BB25 0.50 [137..13B)-> BB28 ( cond ) i gcsafe bwd BB27 [0024] 1 BB26 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen BB28 [0025] 1 BB26 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd BB29 [0092] 2 BB28,BB41 0.50 [???..???) (return) internal gcsafe BB32 [0030] 2 BB18,BB43 0.50 [177..17E)-> BB44 ( cond ) i Loop idxlen bwd bwd-target BB33 [0031] 1 BB32 0.50 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 0.50 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 0.25 [???..???)-> BB37 (always) i gcsafe BB36 [0108] 1 BB34 0.25 [???..???) i gcsafe BB37 [0106] 2 BB35,BB36 0.50 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd BB41 [0115] 1 BB40 0.50 [???..???)-> BB29 (always) internal gcsafe BB42 [0038] 2 BB33,BB37 0.50 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 0.50 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen BB54 [0044] 2 BB48,BB53 0.50 [261..276) i BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB27,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB28 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB30,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB30 to BB26 Renumber BB31 to BB27 Renumber BB26 to BB28 Renumber BB27 to BB29 Renumber BB28 to BB30 Renumber BB29 to BB31 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB27 0.50 [106..110)-> BB44 ( cond ) i Loop idxlen bwd bwd-target BB24 [0021] 1 BB23 0.50 [110..120)-> BB26 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 0.50 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd BB26 [0028] 2 BB24,BB25 0.50 [157..170)-> BB68 ( cond ) i idxlen bwd BB27 [0114] 1 BB26 0.50 [???..???)-> BB23 (always) internal BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal gcsafe BB32 [0030] 2 BB18,BB43 0.50 [177..17E)-> BB44 ( cond ) i Loop idxlen bwd bwd-target BB33 [0031] 1 BB32 0.50 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 0.50 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 0.25 [???..???)-> BB37 (always) i gcsafe BB36 [0108] 1 BB34 0.25 [???..???) i gcsafe BB37 [0106] 2 BB35,BB36 0.50 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe BB42 [0038] 2 BB33,BB37 0.50 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 0.50 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen BB54 [0044] 2 BB48,BB53 0.50 [261..276) i BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 6, # of blocks (including unused BB00): 69, bitset array size: 2 (long) Renumbering the basic blocks for fgUpdateChangeFlowGraph *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB27 0.50 0 [106..110)-> BB44 ( cond ) i Loop idxlen bwd bwd-target BB24 [0021] 1 BB23 0.50 0 [110..120)-> BB26 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 0.50 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd BB26 [0028] 2 BB24,BB25 0.50 0 [157..170)-> BB68 ( cond ) i idxlen bwd BB27 [0114] 1 BB26 0.50 0 [???..???)-> BB23 (always) internal BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal gcsafe BB32 [0030] 2 BB18,BB43 0.50 [177..17E)-> BB44 ( cond ) i Loop idxlen bwd bwd-target BB33 [0031] 1 BB32 0.50 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 0.50 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 0.25 [???..???)-> BB37 (always) i gcsafe BB36 [0108] 1 BB34 0.25 [???..???) i gcsafe BB37 [0106] 2 BB35,BB36 0.50 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe BB42 [0038] 2 BB33,BB37 0.50 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 0.50 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen BB54 [0044] 2 BB48,BB53 0.50 [261..276) i BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** After renumbering the basic blocks =============== No blocks renumbered! *************** In fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB27 0.50 0 [106..110)-> BB44 ( cond ) i Loop idxlen bwd bwd-target BB24 [0021] 1 BB23 0.50 0 [110..120)-> BB26 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 0.50 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd BB26 [0028] 2 BB24,BB25 0.50 0 [157..170)-> BB68 ( cond ) i idxlen bwd BB27 [0114] 1 BB26 0.50 0 [???..???)-> BB23 (always) internal BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal gcsafe BB32 [0030] 2 BB18,BB43 0.50 [177..17E)-> BB44 ( cond ) i Loop idxlen bwd bwd-target BB33 [0031] 1 BB32 0.50 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 0.50 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 0.25 [???..???)-> BB37 (always) i gcsafe BB36 [0108] 1 BB34 0.25 [???..???) i gcsafe BB37 [0106] 2 BB35,BB36 0.50 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe BB42 [0038] 2 BB33,BB37 0.50 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 0.50 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen BB54 [0044] 2 BB48,BB53 0.50 [261..276) i BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- Setting edge weights for BB01 -> BB59 to [0 .. 3.402823e+38] Setting edge weights for BB01 -> BB02 to [0 .. 3.402823e+38] Setting edge weights for BB02 -> BB04 to [0 .. 3.402823e+38] Setting edge weights for BB02 -> BB03 to [0 .. 3.402823e+38] Setting edge weights for BB03 -> BB04 to [0 .. 3.402823e+38] Setting edge weights for BB04 -> BB06 to [0 .. 3.402823e+38] Setting edge weights for BB04 -> BB05 to [0 .. 3.402823e+38] Setting edge weights for BB05 -> BB06 to [0 .. 3.402823e+38] Setting edge weights for BB06 -> BB08 to [0 .. 3.402823e+38] Setting edge weights for BB06 -> BB07 to [0 .. 3.402823e+38] Setting edge weights for BB07 -> BB08 to [0 .. 3.402823e+38] Setting edge weights for BB08 -> BB13 to [0 .. 3.402823e+38] Setting edge weights for BB08 -> BB09 to [0 .. 3.402823e+38] Setting edge weights for BB09 -> BB11 to [0 .. 3.402823e+38] Setting edge weights for BB09 -> BB10 to [0 .. 3.402823e+38] Setting edge weights for BB10 -> BB12 to [0 .. 3.402823e+38] Setting edge weights for BB11 -> BB12 to [0 .. 3.402823e+38] Setting edge weights for BB12 -> BB14 to [0 .. 3.402823e+38] Setting edge weights for BB13 -> BB14 to [0 .. 3.402823e+38] Setting edge weights for BB14 -> BB16 to [0 .. 3.402823e+38] Setting edge weights for BB14 -> BB15 to [0 .. 3.402823e+38] Setting edge weights for BB15 -> BB16 to [0 .. 3.402823e+38] Setting edge weights for BB16 -> BB18 to [0 .. 3.402823e+38] Setting edge weights for BB16 -> BB17 to [0 .. 3.402823e+38] Setting edge weights for BB17 -> BB18 to [0 .. 3.402823e+38] Setting edge weights for BB18 -> BB32 to [0 .. 3.402823e+38] Setting edge weights for BB18 -> BB19 to [0 .. 3.402823e+38] Setting edge weights for BB19 -> BB21 to [0 .. 3.402823e+38] Setting edge weights for BB19 -> BB20 to [0 .. 3.402823e+38] Setting edge weights for BB20 -> BB22 to [0 .. 3.402823e+38] Setting edge weights for BB21 -> BB22 to [0 .. 3.402823e+38] Setting edge weights for BB22 -> BB23 to [0 .. 3.402823e+38] Setting edge weights for BB23 -> BB44 to [0 .. 3.402823e+38] Setting edge weights for BB23 -> BB24 to [0 .. 3.402823e+38] Setting edge weights for BB24 -> BB26 to [0 .. 3.402823e+38] Setting edge weights for BB24 -> BB25 to [0 .. 3.402823e+38] Setting edge weights for BB25 -> BB28 to [0 .. 3.402823e+38] Setting edge weights for BB25 -> BB26 to [0 .. 3.402823e+38] Setting edge weights for BB26 -> BB68 to [0 .. 3.402823e+38] Setting edge weights for BB26 -> BB27 to [0 .. 3.402823e+38] Setting edge weights for BB27 -> BB23 to [0 .. 3.402823e+38] Setting edge weights for BB28 -> BB30 to [0 .. 3.402823e+38] Setting edge weights for BB28 -> BB29 to [0 .. 3.402823e+38] Setting edge weights for BB29 -> BB58 to [0 .. 3.402823e+38] Setting edge weights for BB30 -> BB60 to [0 .. 3.402823e+38] Setting edge weights for BB30 -> BB31 to [0 .. 3.402823e+38] Setting edge weights for BB32 -> BB44 to [0 .. 3.402823e+38] Setting edge weights for BB32 -> BB33 to [0 .. 3.402823e+38] Setting edge weights for BB33 -> BB42 to [0 .. 3.402823e+38] Setting edge weights for BB33 -> BB34 to [0 .. 3.402823e+38] Setting edge weights for BB34 -> BB36 to [0 .. 3.402823e+38] Setting edge weights for BB34 -> BB35 to [0 .. 3.402823e+38] Setting edge weights for BB35 -> BB37 to [0 .. 3.402823e+38] Setting edge weights for BB36 -> BB37 to [0 .. 3.402823e+38] Setting edge weights for BB37 -> BB42 to [0 .. 3.402823e+38] Setting edge weights for BB37 -> BB38 to [0 .. 3.402823e+38] Setting edge weights for BB38 -> BB40 to [0 .. 3.402823e+38] Setting edge weights for BB38 -> BB39 to [0 .. 3.402823e+38] Setting edge weights for BB39 -> BB58 to [0 .. 3.402823e+38] Setting edge weights for BB40 -> BB64 to [0 .. 3.402823e+38] Setting edge weights for BB40 -> BB41 to [0 .. 3.402823e+38] Setting edge weights for BB41 -> BB31 to [0 .. 3.402823e+38] Setting edge weights for BB42 -> BB68 to [0 .. 3.402823e+38] Setting edge weights for BB42 -> BB43 to [0 .. 3.402823e+38] Setting edge weights for BB43 -> BB32 to [0 .. 3.402823e+38] Setting edge weights for BB44 -> BB48 to [0 .. 3.402823e+38] Setting edge weights for BB44 -> BB45 to [0 .. 3.402823e+38] Setting edge weights for BB45 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB45 -> BB46 to [0 .. 3.402823e+38] Setting edge weights for BB46 -> BB47 to [0 .. 3.402823e+38] Setting edge weights for BB47 -> BB55 to [0 .. 3.402823e+38] Setting edge weights for BB48 -> BB54 to [0 .. 3.402823e+38] Setting edge weights for BB48 -> BB49 to [0 .. 3.402823e+38] Setting edge weights for BB49 -> BB51 to [0 .. 3.402823e+38] Setting edge weights for BB49 -> BB50 to [0 .. 3.402823e+38] Setting edge weights for BB50 -> BB51 to [0 .. 3.402823e+38] Setting edge weights for BB51 -> BB53 to [0 .. 3.402823e+38] Setting edge weights for BB51 -> BB52 to [0 .. 3.402823e+38] Setting edge weights for BB52 -> BB53 to [0 .. 3.402823e+38] Setting edge weights for BB53 -> BB54 to [0 .. 3.402823e+38] Setting edge weights for BB54 -> BB55 to [0 .. 3.402823e+38] Setting edge weights for BB55 -> BB58 to [0 .. 3.402823e+38] Setting edge weights for BB55 -> BB56 to [0 .. 3.402823e+38] Setting edge weights for BB56 -> BB58 to [0 .. 3.402823e+38] Setting edge weights for BB56 -> BB57 to [0 .. 3.402823e+38] Setting edge weights for BB57 -> BB58 to [0 .. 3.402823e+38] Setting edge weights for BB60 -> BB62 to [0 .. 3.402823e+38] Setting edge weights for BB60 -> BB61 to [0 .. 3.402823e+38] Setting edge weights for BB61 -> BB63 to [0 .. 3.402823e+38] Setting edge weights for BB62 -> BB63 to [0 .. 3.402823e+38] Setting edge weights for BB64 -> BB66 to [0 .. 3.402823e+38] Setting edge weights for BB64 -> BB65 to [0 .. 3.402823e+38] Setting edge weights for BB65 -> BB67 to [0 .. 3.402823e+38] Setting edge weights for BB66 -> BB67 to [0 .. 3.402823e+38] *************** After fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB27 0.50 0 [106..110)-> BB44 ( cond ) i Loop idxlen bwd bwd-target BB24 [0021] 1 BB23 0.50 0 [110..120)-> BB26 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 0.50 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd BB26 [0028] 2 BB24,BB25 0.50 0 [157..170)-> BB68 ( cond ) i idxlen bwd BB27 [0114] 1 BB26 0.50 0 [???..???)-> BB23 (always) internal BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal gcsafe BB32 [0030] 2 BB18,BB43 0.50 [177..17E)-> BB44 ( cond ) i Loop idxlen bwd bwd-target BB33 [0031] 1 BB32 0.50 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 0.50 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 0.25 [???..???)-> BB37 (always) i gcsafe BB36 [0108] 1 BB34 0.25 [???..???) i gcsafe BB37 [0106] 2 BB35,BB36 0.50 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe BB42 [0038] 2 BB33,BB37 0.50 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 0.50 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen BB54 [0044] 2 BB48,BB53 0.50 [261..276) i BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- Enter blocks: BB01 After computing reachability sets: ------------------------------------------------ BBnum Reachable by ------------------------------------------------ BB01 : BB01 BB02 : BB01 BB02 BB03 : BB01 BB02 BB03 BB04 : BB01 BB02 BB03 BB04 BB05 : BB01 BB02 BB03 BB04 BB05 BB06 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB11 BB12 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB13 BB14 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB21 BB22 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB24 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB25 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB26 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB27 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB29 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB30 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB30 BB31 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB30 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB40 BB41 BB42 BB43 BB32 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB33 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB34 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB35 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB36 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB37 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB38 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB42 BB43 BB39 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB42 BB43 BB40 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB40 BB42 BB43 BB41 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB40 BB41 BB42 BB43 BB42 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB43 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB45 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB45 BB46 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB45 BB46 BB47 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB45 BB46 BB47 BB48 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB48 BB49 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB48 BB49 BB50 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB48 BB49 BB50 BB51 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB48 BB49 BB50 BB51 BB52 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB48 BB49 BB50 BB51 BB52 BB53 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB48 BB49 BB50 BB51 BB52 BB53 BB54 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 BB58 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB29 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB39 BB42 BB43 BB44 BB45 BB46 BB47 BB48 BB49 BB50 BB51 BB52 BB53 BB54 BB55 BB56 BB57 BB58 BB59 : BB01 BB59 BB60 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB30 BB60 BB61 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB30 BB60 BB61 BB62 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB30 BB60 BB62 BB63 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB28 BB30 BB60 BB61 BB62 BB63 BB64 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB40 BB42 BB43 BB64 BB65 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB40 BB42 BB43 BB64 BB65 BB66 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB40 BB42 BB43 BB64 BB66 BB67 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BB40 BB42 BB43 BB64 BB65 BB66 BB67 BB68 : BB01 BB02 BB03 BB04 BB05 BB06 BB07 BB08 BB09 BB10 BB11 BB12 BB13 BB14 BB15 BB16 BB17 BB18 BB19 BB20 BB21 BB22 BB23 BB24 BB25 BB26 BB27 BB32 BB33 BB34 BB35 BB36 BB37 BB42 BB43 BB68 *************** In fgComputeDoms *************** In fgDebugCheckBBlist Dominator computation start blocks (those blocks with no incoming edges): BB01 ------------------------------------------------ BBnum Dominated by ------------------------------------------------ BB01: BB01 BB02: BB02 BB01 BB03: BB03 BB02 BB01 BB04: BB04 BB02 BB01 BB05: BB05 BB04 BB02 BB01 BB06: BB06 BB04 BB02 BB01 BB07: BB07 BB06 BB04 BB02 BB01 BB08: BB08 BB06 BB04 BB02 BB01 BB09: BB09 BB08 BB06 BB04 BB02 BB01 BB10: BB10 BB09 BB08 BB06 BB04 BB02 BB01 BB11: BB11 BB09 BB08 BB06 BB04 BB02 BB01 BB12: BB12 BB09 BB08 BB06 BB04 BB02 BB01 BB13: BB13 BB08 BB06 BB04 BB02 BB01 BB14: BB14 BB08 BB06 BB04 BB02 BB01 BB15: BB15 BB14 BB08 BB06 BB04 BB02 BB01 BB16: BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB17: BB17 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB18: BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB19: BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB20: BB20 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB21: BB21 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB22: BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB23: BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB24: BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB25: BB25 BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB28: BB28 BB25 BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB29: BB29 BB28 BB25 BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB30: BB30 BB28 BB25 BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB60: BB60 BB30 BB28 BB25 BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB61: BB61 BB60 BB30 BB28 BB25 BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB62: BB62 BB60 BB30 BB28 BB25 BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB63: BB63 BB60 BB30 BB28 BB25 BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB26: BB26 BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB27: BB27 BB26 BB24 BB23 BB22 BB19 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB32: BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB33: BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB34: BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB35: BB35 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB36: BB36 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB37: BB37 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB38: BB38 BB37 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB39: BB39 BB38 BB37 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB40: BB40 BB38 BB37 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB41: BB41 BB40 BB38 BB37 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB31: BB31 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB64: BB64 BB40 BB38 BB37 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB65: BB65 BB64 BB40 BB38 BB37 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB66: BB66 BB64 BB40 BB38 BB37 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB67: BB67 BB64 BB40 BB38 BB37 BB34 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB42: BB42 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB43: BB43 BB42 BB33 BB32 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB68: BB68 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB44: BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB45: BB45 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB46: BB46 BB45 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB47: BB47 BB45 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB48: BB48 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB49: BB49 BB48 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB50: BB50 BB49 BB48 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB51: BB51 BB49 BB48 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB52: BB52 BB51 BB49 BB48 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB53: BB53 BB51 BB49 BB48 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB54: BB54 BB48 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB55: BB55 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB56: BB56 BB55 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB57: BB57 BB56 BB55 BB44 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB58: BB58 BB18 BB16 BB14 BB08 BB06 BB04 BB02 BB01 BB59: BB59 BB01 Inside fgBuildDomTree After computing the Dominance Tree: BB01 : BB59 BB02 BB02 : BB04 BB03 BB04 : BB06 BB05 BB06 : BB08 BB07 BB08 : BB14 BB13 BB09 BB09 : BB12 BB11 BB10 BB14 : BB16 BB15 BB16 : BB18 BB17 BB18 : BB68 BB58 BB44 BB32 BB31 BB19 BB19 : BB22 BB21 BB20 BB22 : BB23 BB23 : BB24 BB24 : BB26 BB25 BB25 : BB28 BB26 : BB27 BB28 : BB30 BB29 BB30 : BB60 BB32 : BB33 BB33 : BB42 BB34 BB34 : BB37 BB36 BB35 BB37 : BB38 BB38 : BB40 BB39 BB40 : BB64 BB41 BB42 : BB43 BB44 : BB55 BB48 BB45 BB45 : BB47 BB46 BB48 : BB54 BB49 BB49 : BB51 BB50 BB51 : BB53 BB52 BB55 : BB56 BB56 : BB57 BB60 : BB63 BB62 BB61 BB64 : BB67 BB66 BB65 After numbering the dominator tree: BB01: pre=01, post=68 BB02: pre=03, post=67 BB03: pre=68, post=66 BB04: pre=04, post=65 BB05: pre=67, post=64 BB06: pre=05, post=63 BB07: pre=66, post=62 BB08: pre=06, post=61 BB09: pre=62, post=60 BB10: pre=65, post=59 BB11: pre=64, post=58 BB12: pre=63, post=57 BB13: pre=61, post=56 BB14: pre=07, post=55 BB15: pre=60, post=54 BB16: pre=08, post=53 BB17: pre=59, post=52 BB18: pre=09, post=51 BB19: pre=43, post=50 BB20: pre=58, post=49 BB21: pre=57, post=48 BB22: pre=44, post=47 BB23: pre=45, post=46 BB24: pre=46, post=45 BB25: pre=49, post=44 BB26: pre=47, post=36 BB27: pre=48, post=35 BB28: pre=50, post=43 BB29: pre=56, post=42 BB30: pre=51, post=41 BB31: pre=42, post=34 BB32: pre=26, post=33 BB33: pre=27, post=32 BB34: pre=30, post=31 BB35: pre=41, post=30 BB36: pre=40, post=29 BB37: pre=31, post=28 BB38: pre=32, post=27 BB39: pre=39, post=26 BB40: pre=33, post=25 BB41: pre=38, post=24 BB42: pre=28, post=19 BB43: pre=29, post=18 BB44: pre=12, post=17 BB45: pre=23, post=16 BB46: pre=25, post=15 BB47: pre=24, post=14 BB48: pre=16, post=13 BB49: pre=18, post=12 BB50: pre=22, post=11 BB51: pre=19, post=10 BB52: pre=21, post=09 BB53: pre=20, post=08 BB54: pre=17, post=07 BB55: pre=13, post=06 BB56: pre=14, post=05 BB57: pre=15, post=04 BB58: pre=11, post=03 BB59: pre=02, post=01 BB60: pre=52, post=40 BB61: pre=55, post=39 BB62: pre=54, post=38 BB63: pre=53, post=37 BB64: pre=34, post=23 BB65: pre=37, post=22 BB66: pre=36, post=21 BB67: pre=35, post=20 BB68: pre=10, post=02 Final natural loop table: L00, from BB23 to BB27 (Head=BB22, Entry=BB23, ExitCnt=3) Marking a loop from BB23 to BB27 BB23(wt=400) BB24(wt=400) BB25(wt=200) BB26(wt=400) BB27(wt=400) Marking a loop from BB32 to BB43 BB32(wt=400) BB33(wt=400) BB34(wt=200) BB35(wt=100) BB36(wt=100) BB37(wt=200) BB42(wt=400) BB43(wt=400) L00 that starts at BB23 needs alignment, weight=400. Found a total of 2 loops. After loop weight marking: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop idxlen bwd bwd-target align BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal gcsafe BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop idxlen bwd bwd-target BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe BB36 [0108] 1 BB34 1 [???..???) i gcsafe BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen BB54 [0044] 2 BB48,BB53 0.50 [261..276) i BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Find loops Trees after Find loops ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop idxlen bwd bwd-target align BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal gcsafe BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop idxlen bwd bwd-target BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe BB36 [0108] 1 BB34 1 [???..???) i gcsafe BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen BB54 [0044] 2 BB48,BB53 0.50 [261..276) i BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} ***** BB01 STMT00000 (IL 0x000...0x006) [000003] -----+------ * JTRUE void [000002] J----+-N---- \--* EQ int [000000] -----+------ +--* LCL_VAR ref V01 arg1 [000001] -----+------ \--* CNS_INT ref null ------------ BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00001 (IL 0x00E...0x014) [000008] ---XG+------ * JTRUE void [000007] J--XG+-N---- \--* NE int [000005] ---XG+------ +--* IND ref [000814] -----+------ | \--* ADD byref [000004] -----+------ | +--* LCL_VAR ref V00 this [000813] -----+------ | \--* CNS_INT long 8 field offset Fseq[_buckets] [000006] -----+------ \--* CNS_INT ref null ------------ BB03 [016..01E), preds={BB02} succs={BB04} ***** BB03 STMT00085 (IL ???... ???) [000528] --CXG+------ * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize [000526] -----+------ this in rcx +--* LCL_VAR ref V00 this [000527] -----+------ arg1 in rdx \--* CNS_INT int 0 ------------ BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ***** BB04 STMT00088 (IL 0x01E... ???) [000544] -A-XG+------ * ASG bool [000543] D----+-N---- +--* LCL_VAR int V33 tmp19 [000012] N--XG+------ \--* NE int [000010] ---XG+------ +--* IND ref [000818] -----+------ | \--* ADD byref [000009] -----+------ | +--* LCL_VAR ref V00 this [000817] -----+------ | \--* CNS_INT long 8 field offset Fseq[_buckets] [000011] -----+------ \--* CNS_INT ref null ***** BB04 STMT00091 (IL 0x01E... ???) [000554] -A--G+------ * ASG ref [000553] D----+-N---- +--* LCL_VAR ref V34 tmp20 [000538] #---G+------ \--* IND ref [000537] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB04 STMT00092 (IL 0x01E... ???) [000556] -A--G+------ * ASG ref [000555] D----+-N---- +--* LCL_VAR ref V35 tmp21 [000540] #---G+------ \--* IND ref [000539] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB04 STMT00089 (IL 0x01E... ???) [000549] -----+------ * JTRUE void [000548] J----+-N---- \--* NE int [000546] -----+------ +--* LCL_VAR int V33 tmp19 [000547] -----+------ \--* CNS_INT int 0 ------------ BB05 [01E..01F), preds={BB04} succs={BB06} ***** BB05 STMT00090 (IL 0x01E... ???) [000552] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000550] -----+------ arg0 in rcx +--* LCL_VAR ref V34 tmp20 [000551] -----+------ arg1 in rdx \--* LCL_VAR ref V35 tmp21 ------------ BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} ***** BB06 STMT00003 (IL 0x02C... ???) [000018] -A-XG+------ * ASG ref [000017] D----+-N---- +--* LCL_VAR ref V04 loc0 [000016] ---XG+------ \--* IND ref [000822] -----+------ \--* ADD byref [000015] -----+------ +--* LCL_VAR ref V00 this [000821] -----+------ \--* CNS_INT long 16 field offset Fseq[_entries] ***** BB06 STMT00094 (IL 0x033... ???) [000566] -A---+------ * ASG bool [000565] D----+-N---- +--* LCL_VAR int V36 tmp22 [000021] N----+------ \--* NE int [000019] -----+------ +--* LCL_VAR ref V04 loc0 [000020] -----+------ \--* CNS_INT ref null ***** BB06 STMT00097 (IL 0x033... ???) [000576] -A--G+------ * ASG ref [000575] D----+-N---- +--* LCL_VAR ref V37 tmp23 [000562] #---G+------ \--* IND ref [000561] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB06 STMT00095 (IL 0x033... ???) [000571] -----+------ * JTRUE void [000570] J----+-N---- \--* NE int [000568] -----+------ +--* LCL_VAR int V36 tmp22 [000569] -----+------ \--* CNS_INT int 0 ------------ BB07 [033..034), preds={BB06} succs={BB08} ***** BB07 STMT00096 (IL 0x033... ???) [000574] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000824] #---G+------ arg0 in rcx +--* IND ref [000823] H----+------ | \--* CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" [000573] -----+------ arg1 in rdx \--* LCL_VAR ref V37 tmp23 ------------ BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} ***** BB08 STMT00005 (IL 0x041... ???) [000028] -A-XG+------ * ASG ref [000027] D----+-N---- +--* LCL_VAR ref V05 loc1 [000026] ---XG+------ \--* IND ref [000828] -----+------ \--* ADD byref [000025] -----+------ +--* LCL_VAR ref V00 this [000827] -----+------ \--* CNS_INT long 24 field offset Fseq[_comparer] ***** BB08 STMT00006 (IL 0x048...0x049) [000032] -----+------ * JTRUE void [000031] J----+-N---- \--* EQ int [000029] -----+------ +--* LCL_VAR ref V05 loc1 [000030] -----+------ \--* CNS_INT ref null ------------ BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} ***** BB09 STMT00079 (IL 0x04B...0x052) [000489] -A-X-+------ * ASG long [000488] D----+-N---- +--* LCL_VAR long V29 tmp15 [000487] #--X-+------ \--* IND long [000486] !----+------ \--* LCL_VAR ref V00 this ***** BB09 STMT00080 (IL ???... ???) [000499] -A---+------ * ASG ref [000498] D----+-N---- +--* LCL_VAR ref V30 tmp16 [000485] -----+------ \--* LCL_VAR ref V01 arg1 ***** BB09 STMT00149 (IL ???... ???) [001148] ------------ * JTRUE void [000505] J----+-N---- \--* EQ int [000501] n----+------ +--* IND long [000497] -----+------ | \--* ADD long [000495] #----+------ | +--* IND long [000494] #----+------ | | \--* IND long [000493] -----+------ | | \--* ADD long [000491] -----+------ | | +--* LCL_VAR long V29 tmp15 [000492] -----+------ | | \--* CNS_INT long 56 [000496] -----+------ | \--* CNS_INT long 64 [000504] -----+------ \--* CNS_INT long 0 ------------ BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} ***** BB10 STMT00150 (IL ???... ???) [001150] -A---------- * ASG long [001149] D------N---- +--* LCL_VAR long V31 tmp17 [000506] n----+?----- \--* IND long [000507] -----+?----- \--* ADD long [000508] #----+?----- +--* IND long [000509] #----+?----- | \--* IND long [000510] -----+?----- | \--* ADD long [000511] -----+?----- | +--* LCL_VAR long V29 tmp15 [000512] -----+?----- | \--* CNS_INT long 56 [000513] -----+?----- \--* CNS_INT long 64 ------------ BB11 [???..???), preds={BB09} succs={BB12} ***** BB11 STMT00151 (IL ???... ???) [001152] -AC-G------- * ASG long [001151] D------N---- +--* LCL_VAR long V31 tmp17 [000503] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000490] -----+?----- arg0 in rcx +--* LCL_VAR long V29 tmp15 [000502] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} ***** BB12 STMT00082 (IL ???... ???) [000520] -A---+------ * ASG long [000519] D----+-N---- +--* LCL_VAR long V32 tmp18 [000518] -----+------ \--* LCL_VAR long V31 tmp17 ***** BB12 STMT00083 (IL ???... ???) [000524] -ACXG+------ * ASG int [000523] D----+-N---- +--* LCL_VAR int V15 tmp1 [000522] --CXG+------ \--* CALL ind stub int [000521] -----+------ calli tgt \--* LCL_VAR long V31 tmp17 [000484] -----+------ this in rcx +--* LCL_VAR ref V05 loc1 [000831] -----+------ arg1 in r11 +--* LCL_VAR long V31 tmp17 r11 REG r11 [000500] -----+------ arg2 in rdx \--* LCL_VAR ref V01 arg1 ------------ BB13 [054..061), preds={BB08} succs={BB14} ***** BB13 STMT00007 (IL 0x054...0x05C) [000038] -ACXG+------ * ASG int [000037] D----+-N---- +--* LCL_VAR int V15 tmp1 [000035] --CXG+------ \--* CALLV vt-ind int System.Object.GetHashCode [000843] n--X-+------ control expr \--* IND long [000842] ---X-+------ \--* ADD long [000840] #--X-+------ +--* IND long [000839] ---X-+------ | \--* ADD long [000837] #--X-+------ | +--* IND long [000836] -----+------ | | \--* LCL_VAR ref V01 arg1 [000838] -----+------ | \--* CNS_INT int 72 [000841] -----+------ \--* CNS_INT int 24 [000033] -----+------ this in rcx \--* LCL_VAR ref V01 arg1 ------------ BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ***** BB14 STMT00008 (IL ???...0x061) [000042] -A---+------ * ASG int [000041] D----+-N---- +--* LCL_VAR int V06 loc2 [000040] -----+------ \--* LCL_VAR int V15 tmp1 ***** BB14 STMT00009 (IL 0x062...0x063) [000045] -A---+------ * ASG int [000044] D----+-N---- +--* LCL_VAR int V07 loc3 [000043] -----+------ \--* CNS_INT int 0 ***** BB14 STMT00098 (IL 0x064... ???) [000580] -A-XG+------ * ASG ref [000579] D----+-N---- +--* LCL_VAR ref V39 tmp25 [000578] ---XG+------ \--* IND ref [000845] -----+------ \--* ADD byref [000046] -----+------ +--* LCL_VAR ref V00 this [000844] -----+------ \--* CNS_INT long 8 field offset Fseq[_buckets] ***** BB14 STMT00105 (IL 0x064... ???) [000629] -A-X-+------ * ASG int [000628] D----+-N---- +--* LCL_VAR int V40 tmp26 [000583] ---X-+------ \--* ARR_LENGTH int [000582] -----+------ \--* LCL_VAR ref V39 tmp25 ***** BB14 STMT00106 (IL 0x064... ???) [000631] -A-XG+------ * ASG long [000630] D----+-N---- +--* LCL_VAR long V41 tmp27 [000585] ---XG+------ \--* IND long [000847] -----+------ \--* ADD byref [000584] -----+------ +--* LCL_VAR ref V00 this [000846] -----+------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] ***** BB14 STMT00108 (IL 0x064... ???) [000642] -A---+------ * ASG bool [000641] D----+-N---- +--* LCL_VAR int V43 tmp29 [000599] N----+---U-- \--* LE int [000597] -----+------ +--* LCL_VAR int V40 tmp26 [000598] -----+------ \--* CNS_INT int 0x7FFFFFFF ***** BB14 STMT00111 (IL 0x064... ???) [000652] -A--G+------ * ASG ref [000651] D----+-N---- +--* LCL_VAR ref V44 tmp30 [000636] #---G+------ \--* IND ref [000635] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB14 STMT00112 (IL 0x064... ???) [000654] -A--G+------ * ASG ref [000653] D----+-N---- +--* LCL_VAR ref V45 tmp31 [000638] #---G+------ \--* IND ref [000637] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB14 STMT00109 (IL 0x064... ???) [000647] -----+------ * JTRUE void [000646] J----+-N---- \--* NE int [000644] -----+------ +--* LCL_VAR int V43 tmp29 [000645] -----+------ \--* CNS_INT int 0 ------------ BB15 [064..065), preds={BB14} succs={BB16} ***** BB15 STMT00110 (IL 0x064... ???) [000650] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000648] -----+------ arg0 in rcx +--* LCL_VAR ref V44 tmp30 [000649] -----+------ arg1 in rdx \--* LCL_VAR ref V45 tmp31 ------------ BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} ***** BB16 STMT00103 (IL 0x064... ???) [000619] -A---+------ * ASG int [000618] D----+-N---- +--* LCL_VAR int V42 tmp28 [000617] -----+------ \--* CAST int <- uint <- long [000616] -----+------ \--* RSZ long [000614] -----+------ +--* MUL long [000611] -----+------ | +--* ADD long [000608] -----+------ | | +--* RSZ long [000606] -----+------ | | | +--* MUL long [000604] -----+------ | | | | +--* LCL_VAR long V41 tmp27 [000605] -----+---U-- | | | | \--* CAST long <- ulong <- uint [000047] -----+------ | | | | \--* LCL_VAR int V06 loc2 [000607] -----+------ | | | \--* CNS_INT int 32 [000610] -----+------ | | \--* CNS_INT long 1 [000613] -----+---U-- | \--* CAST long <- ulong <- uint [000612] -----+------ | \--* LCL_VAR int V40 tmp26 [000615] -----+------ \--* CNS_INT int 32 ***** BB16 STMT00114 (IL 0x064... ???) [000665] -A-X-+------ * ASG bool [000664] D----+-N---- +--* LCL_VAR int V46 tmp32 [000624] ---X-+------ \--* EQ int [000620] -----+------ +--* LCL_VAR int V42 tmp28 [000623] ---X-+------ \--* UMOD int [000621] -----+------ +--* LCL_VAR int V06 loc2 [000622] -----+------ \--* LCL_VAR int V40 tmp26 ***** BB16 STMT00117 (IL 0x064... ???) [000675] -A--G+------ * ASG ref [000674] D----+-N---- +--* LCL_VAR ref V47 tmp33 [000659] #---G+------ \--* IND ref [000658] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB16 STMT00118 (IL 0x064... ???) [000677] -A--G+------ * ASG ref [000676] D----+-N---- +--* LCL_VAR ref V48 tmp34 [000661] #---G+------ \--* IND ref [000660] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB16 STMT00115 (IL 0x064... ???) [000670] -----+------ * JTRUE void [000669] J----+-N---- \--* NE int [000667] -----+------ +--* LCL_VAR int V46 tmp32 [000668] -----+------ \--* CNS_INT int 0 ------------ BB17 [064..065), preds={BB16} succs={BB18} ***** BB17 STMT00116 (IL 0x064... ???) [000673] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000671] -----+------ arg0 in rcx +--* LCL_VAR ref V47 tmp33 [000672] -----+------ arg1 in rdx \--* LCL_VAR ref V48 tmp34 ------------ BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} ***** BB18 STMT00100 (IL 0x064... ???) [000591] -A-XG+------ * ASG byref [000590] D----+-N---- +--* LCL_VAR byref V38 tmp24 [000862] ---XG+------ \--* COMMA byref [000855] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000627] -----+------ | +--* LCL_VAR int V42 tmp28 [000854] ---X-+------ | \--* ARR_LENGTH int [000581] -----+------ | \--* LCL_VAR ref V39 tmp25 [000863] ----G------- \--* ADDR byref [000588] a---G+-N---- \--* IND int [000861] -----+------ \--* ADD byref [000852] -----+------ +--* LCL_VAR ref V39 tmp25 [000860] -----+------ \--* ADD long [000858] -----+------ +--* LSH long [000856] -----+------ | +--* CAST long <- int [000853] i----+------ | | \--* LCL_VAR int V42 tmp28 [000857] -----+-N---- | \--* CNS_INT long 2 [000859] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB18 STMT00101 (IL 0x064... ???) [000595] -A---+------ * ASG ref [000594] D----+-N---- +--* LCL_VAR ref V39 tmp25 [000593] -----+------ \--* CNS_INT ref null ***** BB18 STMT00011 (IL ???... ???) [000051] -A---+------ * ASG byref [000050] D----+-N---- +--* LCL_VAR byref V08 loc4 [000592] -----+------ \--* LCL_VAR byref V38 tmp24 ***** BB18 STMT00012 (IL 0x06D...0x072) [000057] -A-XG+------ * ASG int [000056] D----+-N---- +--* LCL_VAR int V09 loc5 [000055] ---XG+------ \--* ADD int [000053] *--XG+------ +--* IND int [000052] -----+------ | \--* LCL_VAR byref V38 tmp24 [000054] -----+------ \--* CNS_INT int -1 ***** BB18 STMT00013 (IL 0x074...0x075) [000061] -----+------ * JTRUE void [000060] J----+-N---- \--* NE int [000058] -----+------ +--* LCL_VAR ref V05 loc1 [000059] -----+------ \--* CNS_INT ref null ------------ BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} ***** BB19 STMT00059 (IL 0x0FF...0x104) [000356] -A-X-+------ * ASG long [000355] D----+-N---- +--* LCL_VAR long V24 tmp10 [000354] #--X-+------ \--* IND long [000353] !----+------ \--* LCL_VAR ref V00 this ***** BB19 STMT00152 (IL ???... ???) [001153] ------------ * JTRUE void [000369] J----+-N---- \--* EQ int [000365] n----+------ +--* IND long [000364] -----+------ | \--* ADD long [000362] #----+------ | +--* IND long [000361] #----+------ | | \--* IND long [000360] -----+------ | | \--* ADD long [000358] -----+------ | | +--* LCL_VAR long V24 tmp10 [000359] -----+------ | | \--* CNS_INT long 56 [000363] -----+------ | \--* CNS_INT long 32 [000368] -----+------ \--* CNS_INT long 0 ------------ BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} ***** BB20 STMT00153 (IL ???... ???) [001155] -A---------- * ASG long [001154] D------N---- +--* LCL_VAR long V25 tmp11 [000370] n----+?----- \--* IND long [000371] -----+?----- \--* ADD long [000372] #----+?----- +--* IND long [000373] #----+?----- | \--* IND long [000374] -----+?----- | \--* ADD long [000375] -----+?----- | +--* LCL_VAR long V24 tmp10 [000376] -----+?----- | \--* CNS_INT long 56 [000377] -----+?----- \--* CNS_INT long 32 ------------ BB21 [???..???), preds={BB19} succs={BB22} ***** BB21 STMT00154 (IL ???... ???) [001157] -AC-G------- * ASG long [001156] D------N---- +--* LCL_VAR long V25 tmp11 [000367] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000357] -----+?----- arg0 in rcx +--* LCL_VAR long V24 tmp10 [000366] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB22 [???..106), preds={BB20,BB21} succs={BB23} ***** BB22 STMT00062 (IL ???... ???) [000386] -ACXG+------ * ASG ref [000385] D----+-N---- +--* LCL_VAR ref V12 loc8 [000352] --CXG+------ \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default [000382] -----+------ arg0 in rcx \--* LCL_VAR long V25 tmp11 ------------ BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} ***** BB23 STMT00063 (IL 0x106...0x10B) [000391] ---X-+------ * JTRUE void [000390] N--X-+-N-U-- \--* GE int [000387] -----+------ +--* LCL_VAR int V09 loc5 [000389] ---X-+------ \--* ARR_LENGTH int [000388] -----+------ \--* LCL_VAR ref V04 loc0 ------------ BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} ***** BB24 STMT00064 (IL 0x110...0x11E) [000399] ---XG+------ * JTRUE void [000398] N--XG+-N-U-- \--* NE int [000396] *--XG+------ +--* IND int [000868] ---XG+------ | \--* ADD byref [000879] ---XG+------ | +--* COMMA byref [000872] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000393] -----+------ | | | +--* LCL_VAR int V09 loc5 [000871] ---X-+------ | | | \--* ARR_LENGTH int [000392] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000882] ----G------- | | \--* ADDR byref [000394] a---G+-N---- | | \--* IND struct [000878] -----+------ | | \--* ADD byref [000869] -----+------ | | +--* LCL_VAR ref V04 loc0 [000877] -----+------ | | \--* ADD long [000875] -----+------ | | +--* LSH long [000881] -----+------ | | | +--* MUL long [000873] -----+------ | | | | +--* CAST long <- int [000870] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000880] ------------ | | | | \--* CNS_INT long 3 [000874] -----+-N---- | | | \--* CNS_INT long 3 [000876] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000867] -----+------ | \--* CNS_INT long 16 field offset Fseq[hashCode] [000397] -----+------ \--* LCL_VAR int V06 loc2 ------------ BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} ***** BB25 STMT00069 (IL 0x120...0x135) [000428] --CXG+------ * JTRUE void [000427] J-CXG+-N---- \--* NE int [000425] --CXG+------ +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals [000908] n--X-+------ control expr | \--* IND long [000907] ---X-+------ | \--* ADD long [000905] #--X-+------ | +--* IND long [000904] ---X-+------ | | \--* ADD long [000902] #--X-+------ | | +--* IND long [000901] -----+------ | | | \--* LCL_VAR ref V12 loc8 [000903] -----+------ | | \--* CNS_INT int 72 [000906] -----+------ | \--* CNS_INT int 32 [000893] ---XG+------ arg1 in rdx | +--* COMMA ref [000886] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000420] -----+------ | | | +--* LCL_VAR int V09 loc5 [000885] ---X-+------ | | | \--* ARR_LENGTH int [000419] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000897] *---G+------ | | \--* IND ref [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] [000421] a---G+-N---- | | \--* IND struct [000892] -----+------ | | \--* ADD byref [000883] -----+------ | | +--* LCL_VAR ref V04 loc0 [000891] -----+------ | | \--* ADD long [000889] -----+------ | | +--* LSH long [000895] -----+------ | | | +--* MUL long [000887] -----+------ | | | | +--* CAST long <- int [000884] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000894] ------------ | | | | \--* CNS_INT long 3 [000888] -----+-N---- | | | \--* CNS_INT long 3 [000890] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000418] -----+------ this in rcx | +--* LCL_VAR ref V12 loc8 [000424] -----+------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 [000426] -----+------ \--* CNS_INT int 0 ------------ BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} ***** BB26 STMT00065 (IL 0x157...0x164) [000406] -A-XG+------ * ASG int [000405] D----+-N---- +--* LCL_VAR int V09 loc5 [000404] *--XG+------ \--* IND int [000932] ---XG+------ \--* ADD byref [000943] ---XG+------ +--* COMMA byref [000936] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000401] -----+------ | | +--* LCL_VAR int V09 loc5 [000935] ---X-+------ | | \--* ARR_LENGTH int [000400] -----+------ | | \--* LCL_VAR ref V04 loc0 [000946] ----G------- | \--* ADDR byref [000402] a---G+-N---- | \--* IND struct [000942] -----+------ | \--* ADD byref [000933] -----+------ | +--* LCL_VAR ref V04 loc0 [000941] -----+------ | \--* ADD long [000939] -----+------ | +--* LSH long [000945] -----+------ | | +--* MUL long [000937] -----+------ | | | +--* CAST long <- int [000934] i----+------ | | | | \--* LCL_VAR int V09 loc5 [000944] ------------ | | | \--* CNS_INT long 3 [000938] -----+-N---- | | \--* CNS_INT long 3 [000940] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [000931] -----+------ \--* CNS_INT long 20 field offset Fseq[next] ***** BB26 STMT00066 (IL 0x166...0x169) [000411] -A---+------ * ASG int [000410] D----+-N---- +--* LCL_VAR int V07 loc3 [000409] -----+------ \--* ADD int [000407] -----+------ +--* LCL_VAR int V07 loc3 [000408] -----+------ \--* CNS_INT int 1 ***** BB26 STMT00067 (IL 0x16A...0x16E) [000416] ---X-+------ * JTRUE void [000415] N--X-+-N-U-- \--* GT int [000412] -----+------ +--* LCL_VAR int V07 loc3 [000414] ---X-+------ \--* ARR_LENGTH int [000413] -----+------ \--* LCL_VAR ref V04 loc0 ------------ BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} ------------ BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} ***** BB28 STMT00070 (IL 0x137...0x139) [000432] -----+------ * JTRUE void [000431] N----+-N-U-- \--* NE int [000909] -----+------ +--* CAST int <- ubyte <- int [000429] -----+------ | \--* LCL_VAR int V03 arg3 [000430] -----+------ \--* CNS_INT int 1 ------------ BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} ***** BB29 STMT00077 (IL 0x13B...0x144) [000481] -A-XG+------ * ASG ref [000480] *--XG+-N---- +--* IND ref [000911] ---XG+------ | \--* ADD byref [000922] ---XG+------ | +--* COMMA byref [000915] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000476] -----+------ | | | +--* LCL_VAR int V09 loc5 [000914] ---X-+------ | | | \--* ARR_LENGTH int [000475] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000925] ----G------- | | \--* ADDR byref [000477] a---G+-N---- | | \--* IND struct [000921] -----+------ | | \--* ADD byref [000912] -----+------ | | +--* LCL_VAR ref V04 loc0 [000920] -----+------ | | \--* ADD long [000918] -----+------ | | +--* LSH long [000924] -----+------ | | | +--* MUL long [000916] -----+------ | | | | +--* CAST long <- int [000913] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000923] ------------ | | | | \--* CNS_INT long 3 [000917] -----+-N---- | | | \--* CNS_INT long 3 [000919] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000910] -----+------ | \--* CNS_INT long 8 field offset Fseq[value] [000479] -----+------ \--* LCL_VAR ref V02 arg2 ------------ BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} ***** BB30 STMT00071 (IL 0x14B...0x14D) [000436] -----+------ * JTRUE void [000435] N----+-N-U-- \--* EQ int [000926] -----+------ +--* CAST int <- ubyte <- int [000433] -----+------ | \--* LCL_VAR int V03 arg3 [000434] -----+------ \--* CNS_INT int 2 ------------ BB31 [???..???) (return), preds={BB30,BB41} succs={} ***** BB31 STMT00148 (IL ???... ???) [000811] -----+------ * RETURN int [000437] -----+------ \--* CNS_INT int 0 ------------ BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} ***** BB32 STMT00014 (IL 0x177...0x17C) ( 11, 9) [000066] ---X-------- * JTRUE void ( 9, 7) [000065] N--X---N-U-- \--* LE int ( 5, 4) [000064] ---X-------- +--* ARR_LENGTH int ( 3, 2) [000063] ------------ | \--* LCL_VAR ref V04 loc0 ( 3, 2) [000062] ------------ \--* LCL_VAR int V09 loc5 ------------ BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} ***** BB33 STMT00039 (IL 0x17E...0x18C) [000215] ---XG+------ * JTRUE void [000214] N--XG+-N-U-- \--* NE int [000212] *--XG+------ +--* IND int [000948] ---XG+------ | \--* ADD byref [000959] ---XG+------ | +--* COMMA byref [000952] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000209] -----+------ | | | +--* LCL_VAR int V09 loc5 [000951] ---X-+------ | | | \--* ARR_LENGTH int [000208] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000962] ----G------- | | \--* ADDR byref [000210] a---G+-N---- | | \--* IND struct [000958] -----+------ | | \--* ADD byref [000949] -----+------ | | +--* LCL_VAR ref V04 loc0 [000957] -----+------ | | \--* ADD long [000955] -----+------ | | +--* LSH long [000961] -----+------ | | | +--* MUL long [000953] -----+------ | | | | +--* CAST long <- int [000950] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000960] ------------ | | | | \--* CNS_INT long 3 [000954] -----+-N---- | | | \--* CNS_INT long 3 [000956] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000947] -----+------ | \--* CNS_INT long 16 field offset Fseq[hashCode] [000213] -----+------ \--* LCL_VAR int V06 loc2 ------------ BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} ***** BB34 STMT00045 (IL 0x18E...0x1A2) [000246] -A-XG+------ * ASG ref [000245] D----+-N---- +--* LCL_VAR ref V17 tmp3 [000973] ---XG+------ \--* COMMA ref [000966] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000236] -----+------ | +--* LCL_VAR int V09 loc5 [000965] ---X-+------ | \--* ARR_LENGTH int [000235] -----+------ | \--* LCL_VAR ref V04 loc0 [000977] *---G+------ \--* IND ref [000976] ----G------- \--* ADDR byref Zero Fseq[key] [000237] a---G+-N---- \--* IND struct [000972] -----+------ \--* ADD byref [000963] -----+------ +--* LCL_VAR ref V04 loc0 [000971] -----+------ \--* ADD long [000969] -----+------ +--* LSH long [000975] -----+------ | +--* MUL long [000967] -----+------ | | +--* CAST long <- int [000964] i----+------ | | | \--* LCL_VAR int V09 loc5 [000974] ------------ | | \--* CNS_INT long 3 [000968] -----+-N---- | \--* CNS_INT long 3 [000970] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB34 STMT00044 (IL 0x18E... ???) [000244] -A-X-+------ * ASG long [000243] D----+-N---- +--* LCL_VAR long V16 tmp2 [000242] #--X-+------ \--* IND long [000241] !----+------ \--* LCL_VAR ref V00 this ***** BB34 STMT00046 (IL ???... ???) [000257] -A---+------ * ASG ref [000256] D----+-N---- +--* LCL_VAR ref V18 tmp4 [000240] -----+------ \--* LCL_VAR ref V01 arg1 ***** BB34 STMT00158 (IL ???... ???) [001163] ------------ * JTRUE void [000263] J----+-N---- \--* EQ int [000259] n----+------ +--* IND long [000255] -----+------ | \--* ADD long [000253] #----+------ | +--* IND long [000252] #----+------ | | \--* IND long [000251] -----+------ | | \--* ADD long [000249] -----+------ | | +--* LCL_VAR long V16 tmp2 [000250] -----+------ | | \--* CNS_INT long 56 [000254] -----+------ | \--* CNS_INT long 48 [000262] -----+------ \--* CNS_INT long 0 ------------ BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} ***** BB35 STMT00159 (IL ???... ???) [001165] -A---------- * ASG long [001164] D------N---- +--* LCL_VAR long V19 tmp5 [000264] n----+?----- \--* IND long [000265] -----+?----- \--* ADD long [000266] #----+?----- +--* IND long [000267] #----+?----- | \--* IND long [000268] -----+?----- | \--* ADD long [000269] -----+?----- | +--* LCL_VAR long V16 tmp2 [000270] -----+?----- | \--* CNS_INT long 56 [000271] -----+?----- \--* CNS_INT long 48 ------------ BB36 [???..???), preds={BB34} succs={BB37} ***** BB36 STMT00160 (IL ???... ???) [001167] -AC-G------- * ASG long [001166] D------N---- +--* LCL_VAR long V19 tmp5 [000261] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000248] -----+?----- arg0 in rcx +--* LCL_VAR long V16 tmp2 [000260] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} ***** BB37 STMT00048 (IL ???... ???) [000278] -A---+------ * ASG long [000277] D----+-N---- +--* LCL_VAR long V20 tmp6 [000276] -----+------ \--* LCL_VAR long V19 tmp5 ***** BB37 STMT00049 (IL ???... ???) [000283] --CXG+------ * JTRUE void [000282] J-CXG+-N---- \--* EQ int [000280] --CXG+------ +--* CALL ind stub int [000279] -----+------ calli tgt | \--* LCL_VAR long V19 tmp5 [000234] -----+------ this in rcx | +--* LCL_VAR ref V05 loc1 [000980] -----+------ arg1 in r11 | +--* LCL_VAR long V19 tmp5 r11 REG r11 [000247] -----+------ arg2 in rdx | +--* LCL_VAR ref V17 tmp3 [000258] -----+------ arg3 in r8 | \--* LCL_VAR ref V01 arg1 [000281] -----+------ \--* CNS_INT int 0 ------------ BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} ***** BB38 STMT00050 (IL 0x1A4...0x1A6) [000287] -----+------ * JTRUE void [000286] N----+-N-U-- \--* NE int [000985] -----+------ +--* CAST int <- ubyte <- int [000284] -----+------ | \--* LCL_VAR int V03 arg3 [000285] -----+------ \--* CNS_INT int 1 ------------ BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} ***** BB39 STMT00057 (IL 0x1A8...0x1B1) [000336] -A-XG+------ * ASG ref [000335] *--XG+-N---- +--* IND ref [000987] ---XG+------ | \--* ADD byref [000998] ---XG+------ | +--* COMMA byref [000991] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000331] -----+------ | | | +--* LCL_VAR int V09 loc5 [000990] ---X-+------ | | | \--* ARR_LENGTH int [000330] -----+------ | | | \--* LCL_VAR ref V04 loc0 [001001] ----G------- | | \--* ADDR byref [000332] a---G+-N---- | | \--* IND struct [000997] -----+------ | | \--* ADD byref [000988] -----+------ | | +--* LCL_VAR ref V04 loc0 [000996] -----+------ | | \--* ADD long [000994] -----+------ | | +--* LSH long [001000] -----+------ | | | +--* MUL long [000992] -----+------ | | | | +--* CAST long <- int [000989] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000999] ------------ | | | | \--* CNS_INT long 3 [000993] -----+-N---- | | | \--* CNS_INT long 3 [000995] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000986] -----+------ | \--* CNS_INT long 8 field offset Fseq[value] [000334] -----+------ \--* LCL_VAR ref V02 arg2 ------------ BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} ***** BB40 STMT00051 (IL 0x1B8...0x1BA) [000291] -----+------ * JTRUE void [000290] N----+-N-U-- \--* EQ int [001002] -----+------ +--* CAST int <- ubyte <- int [000288] -----+------ | \--* LCL_VAR int V03 arg3 [000289] -----+------ \--* CNS_INT int 2 ------------ BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} ------------ BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} ***** BB42 STMT00040 (IL 0x1C4...0x1D1) [000222] -A-XG+------ * ASG int [000221] D----+-N---- +--* LCL_VAR int V09 loc5 [000220] *--XG+------ \--* IND int [001009] ---XG+------ \--* ADD byref [001020] ---XG+------ +--* COMMA byref [001013] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000217] -----+------ | | +--* LCL_VAR int V09 loc5 [001012] ---X-+------ | | \--* ARR_LENGTH int [000216] -----+------ | | \--* LCL_VAR ref V04 loc0 [001023] ----G------- | \--* ADDR byref [000218] a---G+-N---- | \--* IND struct [001019] -----+------ | \--* ADD byref [001010] -----+------ | +--* LCL_VAR ref V04 loc0 [001018] -----+------ | \--* ADD long [001016] -----+------ | +--* LSH long [001022] -----+------ | | +--* MUL long [001014] -----+------ | | | +--* CAST long <- int [001011] i----+------ | | | | \--* LCL_VAR int V09 loc5 [001021] ------------ | | | \--* CNS_INT long 3 [001015] -----+-N---- | | \--* CNS_INT long 3 [001017] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [001008] -----+------ \--* CNS_INT long 20 field offset Fseq[next] ***** BB42 STMT00041 (IL 0x1D3...0x1D6) [000227] -A---+------ * ASG int [000226] D----+-N---- +--* LCL_VAR int V07 loc3 [000225] -----+------ \--* ADD int [000223] -----+------ +--* LCL_VAR int V07 loc3 [000224] -----+------ \--* CNS_INT int 1 ***** BB42 STMT00042 (IL 0x1D7...0x1DB) [000232] ---X-+------ * JTRUE void [000231] N--X-+-N-U-- \--* GT int [000228] -----+------ +--* LCL_VAR int V07 loc3 [000230] ---X-+------ \--* ARR_LENGTH int [000229] -----+------ \--* LCL_VAR ref V04 loc0 ------------ BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} ------------ BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} ***** BB44 STMT00015 (IL 0x1E4...0x1EB) [000071] ---XG+------ * JTRUE void [000070] J--XG+-N---- \--* LE int [000068] ---XG+------ +--* IND int [001025] -----+------ | \--* ADD byref [000067] -----+------ | +--* LCL_VAR ref V00 this [001024] -----+------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] [000069] -----+------ \--* CNS_INT int 0 ------------ BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} ***** BB45 STMT00035 (IL 0x1ED...0x1F3) [000174] -A-XG+------ * ASG int [000173] D----+-N---- +--* LCL_VAR int V10 loc6 [000172] ---XG+------ \--* IND int [001027] -----+------ \--* ADD byref [000171] -----+------ +--* LCL_VAR ref V00 this [001026] -----+------ \--* CNS_INT long 60 field offset Fseq[_freeList] ***** BB45 STMT00120 (IL 0x1F5... ???) [000688] -A-XG+------ * ASG bool [000687] D----+-N---- +--* LCL_VAR int V49 tmp35 [000184] -A-XG+------ \--* GE int [000182] -A-XG+------ +--* ADD int [001050] -A-XG+------ | +--* NEG int [000181] *A-XG+------ | | \--* IND int [001029] -A-XG+------ | | \--* ADD byref [001044] -A-XG+------ | | +--* COMMA byref [001032] -A-XG+------ | | | +--* ASG int [001031] D----+-N---- | | | | +--* LCL_VAR int V62 tmp48 [000178] ---XG+------ | | | | \--* IND int [001046] -----+------ | | | | \--* ADD byref [000177] -----+------ | | | | +--* LCL_VAR ref V00 this [001045] -----+------ | | | | \--* CNS_INT long 60 field offset Fseq[_freeList] [001043] ---XG+------ | | | \--* COMMA byref [001036] ---X-+------ | | | +--* ARR_BOUNDS_CHECK_Rng void [001033] -----+------ | | | | +--* LCL_VAR int V62 tmp48 [001035] ---X-+------ | | | | \--* ARR_LENGTH int [000176] -----+------ | | | | \--* LCL_VAR ref V04 loc0 [001049] ----G------- | | | \--* ADDR byref [000179] a---G+-N---- | | | \--* IND struct [001042] -----+------ | | | \--* ADD byref [001030] -----+------ | | | +--* LCL_VAR ref V04 loc0 [001041] -----+------ | | | \--* ADD long [001039] -----+------ | | | +--* LSH long [001048] -----+------ | | | | +--* MUL long [001037] -----+------ | | | | | +--* CAST long <- int [001034] i----+------ | | | | | | \--* LCL_VAR int V62 tmp48 [001047] ------------ | | | | | \--* CNS_INT long 3 [001038] -----+-N---- | | | | \--* CNS_INT long 3 [001040] -----+------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] [001028] -----+------ | | \--* CNS_INT long 20 field offset Fseq[next] [000175] -----+------ | \--* CNS_INT int -3 [000183] -----+------ \--* CNS_INT int -1 ***** BB45 STMT00123 (IL 0x1F5... ???) [000698] -A--G+------ * ASG ref [000697] D----+-N---- +--* LCL_VAR ref V50 tmp36 [000684] #---G+------ \--* IND ref [000683] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB45 STMT00121 (IL 0x1F5... ???) [000693] -----+------ * JTRUE void [000692] J----+-N---- \--* NE int [000690] -----+------ +--* LCL_VAR int V49 tmp35 [000691] -----+------ \--* CNS_INT int 0 ------------ BB46 [1F5..1F6), preds={BB45} succs={BB47} ***** BB46 STMT00122 (IL 0x1F5... ???) [000696] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [001052] #---G+------ arg0 in rcx +--* IND ref [001051] H----+------ | \--* CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" [000695] -----+------ arg1 in rdx \--* LCL_VAR ref V50 tmp36 ------------ BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} ***** BB47 STMT00037 (IL 0x219... ???) [000200] -A-XG+------ * ASG int [000199] ---XG+-N---- +--* IND int [001056] -----+------ | \--* ADD byref [000190] -----+------ | +--* LCL_VAR ref V00 this [001055] -----+------ | \--* CNS_INT long 60 field offset Fseq[_freeList] [000198] -A-XG+------ \--* ADD int [001079] -A-XG+------ +--* NEG int [000197] *A-XG+------ | \--* IND int [001058] -A-XG+------ | \--* ADD byref [001073] -A-XG+------ | +--* COMMA byref [001061] -A-XG+------ | | +--* ASG int [001060] D----+-N---- | | | +--* LCL_VAR int V63 tmp49 [000194] ---XG+------ | | | \--* IND int [001075] -----+------ | | | \--* ADD byref [000193] -----+------ | | | +--* LCL_VAR ref V00 this [001074] -----+------ | | | \--* CNS_INT long 60 field offset Fseq[_freeList] [001072] ---XG+------ | | \--* COMMA byref [001065] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [001062] -----+------ | | | +--* LCL_VAR int V63 tmp49 [001064] ---X-+------ | | | \--* ARR_LENGTH int [000192] -----+------ | | | \--* LCL_VAR ref V04 loc0 [001078] ----G------- | | \--* ADDR byref [000195] a---G+-N---- | | \--* IND struct [001071] -----+------ | | \--* ADD byref [001059] -----+------ | | +--* LCL_VAR ref V04 loc0 [001070] -----+------ | | \--* ADD long [001068] -----+------ | | +--* LSH long [001077] -----+------ | | | +--* MUL long [001066] -----+------ | | | | +--* CAST long <- int [001063] i----+------ | | | | | \--* LCL_VAR int V63 tmp49 [001076] ------------ | | | | \--* CNS_INT long 3 [001067] -----+-N---- | | | \--* CNS_INT long 3 [001069] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [001057] -----+------ | \--* CNS_INT long 20 field offset Fseq[next] [000191] -----+------ \--* CNS_INT int -3 ***** BB47 STMT00038 (IL 0x233...0x23C) [000207] -A-XG+------ * ASG int [000206] ---XG+-N---- +--* IND int [001081] -----+------ | \--* ADD byref [000201] -----+------ | +--* LCL_VAR ref V00 this [001080] -----+------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] [000205] ---XG+------ \--* ADD int [000203] ---XG+------ +--* IND int [001083] -----+------ | \--* ADD byref [000202] -----+------ | +--* LCL_VAR ref V00 this [001082] -----+------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] [000204] -----+------ \--* CNS_INT int -1 ------------ BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} ***** BB48 STMT00016 (IL 0x243...0x249) [000075] -A-XG+------ * ASG int [000074] D----+-N---- +--* LCL_VAR int V13 loc9 [000073] ---XG+------ \--* IND int [001085] -----+------ \--* ADD byref [000072] -----+------ +--* LCL_VAR ref V00 this [001084] -----+------ \--* CNS_INT long 56 field offset Fseq[_count] ***** BB48 STMT00017 (IL 0x24B...0x250) [000080] ---X-+------ * JTRUE void [000079] N--X-+-N-U-- \--* NE int [000076] -----+------ +--* LCL_VAR int V13 loc9 [000078] ---X-+------ \--* ARR_LENGTH int [000077] -----+------ \--* LCL_VAR ref V04 loc0 ------------ BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00125 (IL 0x252... ???) [000705] --CXG+------ * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [001090] -ACXG-----L- arg1 SETUP +--* ASG int [001089] D------N---- | +--* LCL_VAR int V64 tmp50 [000702] --CXG+------ | \--* CALL int System.Collections.HashHelpers.ExpandPrime [000701] ---XG+------ arg0 in rcx | \--* IND int [001087] -----+------ | \--* ADD byref [000700] -----+------ | +--* LCL_VAR ref V00 this [001086] -----+------ | \--* CNS_INT long 56 field offset Fseq[_count] [001091] ------------ arg1 in rdx +--* LCL_VAR int V64 tmp50 [000163] -----+------ this in rcx +--* LCL_VAR ref V00 this [000704] -----+------ arg2 in r8 \--* CNS_INT int 0 ***** BB49 STMT00126 (IL 0x258... ???) [000711] -A-XG+------ * ASG ref [000710] D----+-N---- +--* LCL_VAR ref V52 tmp38 [000709] ---XG+------ \--* IND ref [001095] -----+------ \--* ADD byref [000165] -----+------ +--* LCL_VAR ref V00 this [001094] -----+------ \--* CNS_INT long 8 field offset Fseq[_buckets] ***** BB49 STMT00133 (IL 0x258... ???) [000760] -A-X-+------ * ASG int [000759] D----+-N---- +--* LCL_VAR int V53 tmp39 [000714] ---X-+------ \--* ARR_LENGTH int [000713] -----+------ \--* LCL_VAR ref V52 tmp38 ***** BB49 STMT00134 (IL 0x258... ???) [000762] -A-XG+------ * ASG long [000761] D----+-N---- +--* LCL_VAR long V54 tmp40 [000716] ---XG+------ \--* IND long [001097] -----+------ \--* ADD byref [000715] -----+------ +--* LCL_VAR ref V00 this [001096] -----+------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] ***** BB49 STMT00136 (IL 0x258... ???) [000773] -A---+------ * ASG bool [000772] D----+-N---- +--* LCL_VAR int V56 tmp42 [000730] N----+---U-- \--* LE int [000728] -----+------ +--* LCL_VAR int V53 tmp39 [000729] -----+------ \--* CNS_INT int 0x7FFFFFFF ***** BB49 STMT00139 (IL 0x258... ???) [000783] -A--G+------ * ASG ref [000782] D----+-N---- +--* LCL_VAR ref V57 tmp43 [000767] #---G+------ \--* IND ref [000766] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB49 STMT00140 (IL 0x258... ???) [000785] -A--G+------ * ASG ref [000784] D----+-N---- +--* LCL_VAR ref V58 tmp44 [000769] #---G+------ \--* IND ref [000768] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB49 STMT00137 (IL 0x258... ???) [000778] -----+------ * JTRUE void [000777] J----+-N---- \--* NE int [000775] -----+------ +--* LCL_VAR int V56 tmp42 [000776] -----+------ \--* CNS_INT int 0 ------------ BB50 [258..259), preds={BB49} succs={BB51} ***** BB50 STMT00138 (IL 0x258... ???) [000781] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000779] -----+------ arg0 in rcx +--* LCL_VAR ref V57 tmp43 [000780] -----+------ arg1 in rdx \--* LCL_VAR ref V58 tmp44 ------------ BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00131 (IL 0x258... ???) [000750] -A---+------ * ASG int [000749] D----+-N---- +--* LCL_VAR int V55 tmp41 [000748] -----+------ \--* CAST int <- uint <- long [000747] -----+------ \--* RSZ long [000745] -----+------ +--* MUL long [000742] -----+------ | +--* ADD long [000739] -----+------ | | +--* RSZ long [000737] -----+------ | | | +--* MUL long [000735] -----+------ | | | | +--* LCL_VAR long V54 tmp40 [000736] -----+---U-- | | | | \--* CAST long <- ulong <- uint [000166] -----+------ | | | | \--* LCL_VAR int V06 loc2 [000738] -----+------ | | | \--* CNS_INT int 32 [000741] -----+------ | | \--* CNS_INT long 1 [000744] -----+---U-- | \--* CAST long <- ulong <- uint [000743] -----+------ | \--* LCL_VAR int V53 tmp39 [000746] -----+------ \--* CNS_INT int 32 ***** BB51 STMT00142 (IL 0x258... ???) [000796] -A-X-+------ * ASG bool [000795] D----+-N---- +--* LCL_VAR int V59 tmp45 [000755] ---X-+------ \--* EQ int [000751] -----+------ +--* LCL_VAR int V55 tmp41 [000754] ---X-+------ \--* UMOD int [000752] -----+------ +--* LCL_VAR int V06 loc2 [000753] -----+------ \--* LCL_VAR int V53 tmp39 ***** BB51 STMT00145 (IL 0x258... ???) [000806] -A--G+------ * ASG ref [000805] D----+-N---- +--* LCL_VAR ref V60 tmp46 [000790] #---G+------ \--* IND ref [000789] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB51 STMT00146 (IL 0x258... ???) [000808] -A--G+------ * ASG ref [000807] D----+-N---- +--* LCL_VAR ref V61 tmp47 [000792] #---G+------ \--* IND ref [000791] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB51 STMT00143 (IL 0x258... ???) [000801] -----+------ * JTRUE void [000800] J----+-N---- \--* NE int [000798] -----+------ +--* LCL_VAR int V59 tmp45 [000799] -----+------ \--* CNS_INT int 0 ------------ BB52 [258..259), preds={BB51} succs={BB53} ***** BB52 STMT00144 (IL 0x258... ???) [000804] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000802] -----+------ arg0 in rcx +--* LCL_VAR ref V60 tmp46 [000803] -----+------ arg1 in rdx \--* LCL_VAR ref V61 tmp47 ------------ BB53 [258..259), preds={BB51,BB52} succs={BB54} ***** BB53 STMT00128 (IL 0x258... ???) [000722] -A-XG+------ * ASG byref [000721] D----+-N---- +--* LCL_VAR byref V51 tmp37 [001112] ---XG+------ \--* COMMA byref [001105] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000758] -----+------ | +--* LCL_VAR int V55 tmp41 [001104] ---X-+------ | \--* ARR_LENGTH int [000712] -----+------ | \--* LCL_VAR ref V52 tmp38 [001113] ----G------- \--* ADDR byref [000719] a---G+-N---- \--* IND int [001111] -----+------ \--* ADD byref [001102] -----+------ +--* LCL_VAR ref V52 tmp38 [001110] -----+------ \--* ADD long [001108] -----+------ +--* LSH long [001106] -----+------ | +--* CAST long <- int [001103] i----+------ | | \--* LCL_VAR int V55 tmp41 [001107] -----+-N---- | \--* CNS_INT long 2 [001109] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB53 STMT00129 (IL 0x258... ???) [000726] -A---+------ * ASG ref [000725] D----+-N---- +--* LCL_VAR ref V52 tmp38 [000724] -----+------ \--* CNS_INT ref null ***** BB53 STMT00034 (IL ???... ???) [000170] -A---+------ * ASG byref [000169] D----+-N---- +--* LCL_VAR byref V08 loc4 [000723] -----+------ \--* LCL_VAR byref V51 tmp37 ------------ BB54 [261..276), preds={BB48,BB53} succs={BB55} ***** BB54 STMT00018 (IL 0x261...0x263) [000083] -A---+------ * ASG int [000082] D----+-N---- +--* LCL_VAR int V10 loc6 [000081] -----+------ \--* LCL_VAR int V13 loc9 ***** BB54 STMT00019 (IL 0x265...0x26A) [000089] -A-XG+------ * ASG int [000088] ---XG+-N---- +--* IND int [001115] -----+------ | \--* ADD byref [000084] -----+------ | +--* LCL_VAR ref V00 this [001114] -----+------ | \--* CNS_INT long 56 field offset Fseq[_count] [000087] -----+------ \--* ADD int [000085] -----+------ +--* LCL_VAR int V13 loc9 [000086] -----+------ \--* CNS_INT int 1 ***** BB54 STMT00020 (IL 0x26F...0x275) [000093] -A-XG+------ * ASG ref [000092] D----+-N---- +--* LCL_VAR ref V04 loc0 [000091] ---XG+------ \--* IND ref [001117] -----+------ \--* ADD byref [000090] -----+------ +--* LCL_VAR ref V00 this [001116] -----+------ \--* CNS_INT long 16 field offset Fseq[_entries] ------------ BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} ***** BB55 STMT00021 (IL 0x276...0x27E) [000099] -A-XG+------ * ASG byref [000098] D----+-N---- +--* LCL_VAR byref V11 loc7 [001128] ---XG+------ \--* COMMA byref [001121] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000095] -----+------ | +--* LCL_VAR int V10 loc6 [001120] ---X-+------ | \--* ARR_LENGTH int [000094] -----+------ | \--* LCL_VAR ref V04 loc0 [001131] ----G------- \--* ADDR byref [000096] a---G+-N---- \--* IND struct [001127] -----+------ \--* ADD byref [001118] -----+------ +--* LCL_VAR ref V04 loc0 [001126] -----+------ \--* ADD long [001124] -----+------ +--* LSH long [001130] -----+------ | +--* MUL long [001122] -----+------ | | +--* CAST long <- int [001119] i----+------ | | | \--* LCL_VAR int V10 loc6 [001129] ------------ | | \--* CNS_INT long 3 [001123] -----+-N---- | \--* CNS_INT long 3 [001125] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB55 STMT00022 (IL 0x280...0x283) [000103] -A-XG+------ * ASG int [000102] *--XG+-N---- +--* IND int [001133] -----+------ | \--* ADD byref [000100] -----+------ | +--* LCL_VAR byref V11 loc7 [001132] -----+------ | \--* CNS_INT long 16 field offset Fseq[hashCode] [000101] -----+------ \--* LCL_VAR int V06 loc2 ***** BB55 STMT00023 (IL 0x288...0x28F) [000110] -A-XG+------ * ASG int [000109] *--XG+-N---- +--* IND int [001135] -----+------ | \--* ADD byref [000104] -----+------ | +--* LCL_VAR byref V11 loc7 [001134] -----+------ | \--* CNS_INT long 20 field offset Fseq[next] [000108] ---XG+------ \--* ADD int [000106] *--XG+------ +--* IND int [000105] -----+------ | \--* LCL_VAR byref V08 loc4 [000107] -----+------ \--* CNS_INT int -1 ***** BB55 STMT00024 (IL 0x294...0x297) [000114] -A-XG+------ * ASG ref [000113] *--XG+-N---- +--* IND ref [000111] -----+------ | \--* LCL_VAR byref V11 loc7 Zero Fseq[key] [000112] -----+------ \--* LCL_VAR ref V01 arg1 ***** BB55 STMT00025 (IL 0x29C...0x29F) [000118] -A-XG+------ * ASG ref [000117] *--XG+-N---- +--* IND ref [001137] -----+------ | \--* ADD byref [000115] -----+------ | +--* LCL_VAR byref V11 loc7 [001136] -----+------ | \--* CNS_INT long 8 field offset Fseq[value] [000116] -----+------ \--* LCL_VAR ref V02 arg2 ***** BB55 STMT00026 (IL 0x2A4...0x2AA) [000124] -A-XG+------ * ASG int [000123] *--X-+-N---- +--* IND int [000119] -----+------ | \--* LCL_VAR byref V08 loc4 [000122] -----+------ \--* ADD int [000120] -----+------ +--* LCL_VAR int V10 loc6 [000121] -----+------ \--* CNS_INT int 1 ***** BB55 STMT00027 (IL 0x2AB...0x2B4) [000131] -A-XG+------ * ASG int [000130] ---XG+-N---- +--* IND int [001139] -----+------ | \--* ADD byref [000125] -----+------ | +--* LCL_VAR ref V00 this [001138] -----+------ | \--* CNS_INT long 68 field offset Fseq[_version] [000129] ---XG+------ \--* ADD int [000127] ---XG+------ +--* IND int [001141] -----+------ | \--* ADD byref [000126] -----+------ | +--* LCL_VAR ref V00 this [001140] -----+------ | \--* CNS_INT long 68 field offset Fseq[_version] [000128] -----+------ \--* CNS_INT int 1 ***** BB55 STMT00028 (IL 0x2CA...0x2CD) [000148] -----+------ * JTRUE void [000147] N----+-N-U-- \--* LE int [000145] -----+------ +--* LCL_VAR int V07 loc3 [000146] -----+------ \--* CNS_INT int 100 ------------ BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} ***** BB56 STMT00030 (IL 0x2CF...0x2D5) [000156] --C-G+------ * JTRUE void [000155] J-C-G+-N---- \--* EQ int [000153] --C-G+------ +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS [000151] -----+------ arg1 in rdx | +--* LCL_VAR ref V05 loc1 [000152] H----+-N---- arg0 in rcx | \--* CNS_INT(h) long 0xd1ffab1e class [000154] -----+------ \--* CNS_INT ref null ------------ BB57 [2D7..2E3), preds={BB56} succs={BB58} ***** BB57 STMT00031 (IL 0x2D7...0x2DC) [000161] --CXG+------ * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [000159] ---X-+------ arg1 in rdx +--* ARR_LENGTH int [000158] -----+------ | \--* LCL_VAR ref V04 loc0 [000157] -----+------ this in rcx +--* LCL_VAR ref V00 this [000160] -----+------ arg2 in r8 \--* CNS_INT int 1 ------------ BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} ***** BB58 STMT00147 (IL ???... ???) [000810] -----+------ * RETURN int [000482] -----+------ \--* CNS_INT int 1 ------------ BB59 [008..00E) (throw), preds={BB01} succs={} ***** BB59 STMT00086 (IL 0x008...0x009) [000533] --CXG+------ * CALL void System.ThrowHelper.ThrowArgumentNullException [000532] -----+------ arg0 in rcx \--* CNS_INT int 4 ------------ BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} ***** BB60 STMT00073 (IL 0x14F...0x150) [000444] -A-X-+------ * ASG long [000443] D----+-N---- +--* LCL_VAR long V26 tmp12 [000442] #--X-+------ \--* IND long [000441] !----+------ \--* LCL_VAR ref V00 this ***** BB60 STMT00074 (IL ???... ???) [000454] -A---+------ * ASG ref [000453] D----+-N---- +--* LCL_VAR ref V27 tmp13 [000439] -----+------ \--* LCL_VAR ref V01 arg1 ***** BB60 STMT00155 (IL ???... ???) [001158] ------------ * JTRUE void [000460] J----+-N---- \--* EQ int [000456] n----+------ +--* IND long [000452] -----+------ | \--* ADD long [000450] #----+------ | +--* IND long [000449] #----+------ | | \--* IND long [000448] -----+------ | | \--* ADD long [000446] -----+------ | | +--* LCL_VAR long V26 tmp12 [000447] -----+------ | | \--* CNS_INT long 56 [000451] -----+------ | \--* CNS_INT long 56 [000459] -----+------ \--* CNS_INT long 0 ------------ BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} ***** BB61 STMT00156 (IL ???... ???) [001160] -A---------- * ASG long [001159] D------N---- +--* LCL_VAR long V28 tmp14 [000461] n----+?----- \--* IND long [000462] -----+?----- \--* ADD long [000463] #----+?----- +--* IND long [000464] #----+?----- | \--* IND long [000465] -----+?----- | \--* ADD long [000466] -----+?----- | +--* LCL_VAR long V26 tmp12 [000467] -----+?----- | \--* CNS_INT long 56 [000468] -----+?----- \--* CNS_INT long 56 ------------ BB62 [???..???), preds={BB60} succs={BB63} ***** BB62 STMT00157 (IL ???... ???) [001162] -AC-G------- * ASG long [001161] D------N---- +--* LCL_VAR long V28 tmp14 [000458] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000445] -----+?----- arg0 in rcx +--* LCL_VAR long V26 tmp12 [000457] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB63 [???..157) (throw), preds={BB61,BB62} succs={} ***** BB63 STMT00076 (IL ???... ???) [000440] --CXG+------ * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000473] -----+------ arg0 in rcx +--* LCL_VAR long V28 tmp14 [000455] -----+------ arg1 in rdx \--* LCL_VAR ref V01 arg1 ------------ BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} ***** BB64 STMT00053 (IL 0x1BC...0x1BD) [000299] -A-X-+------ * ASG long [000298] D----+-N---- +--* LCL_VAR long V21 tmp7 [000297] #--X-+------ \--* IND long [000296] !----+------ \--* LCL_VAR ref V00 this ***** BB64 STMT00054 (IL ???... ???) [000309] -A---+------ * ASG ref [000308] D----+-N---- +--* LCL_VAR ref V22 tmp8 [000294] -----+------ \--* LCL_VAR ref V01 arg1 ***** BB64 STMT00161 (IL ???... ???) [001168] ------------ * JTRUE void [000315] J----+-N---- \--* EQ int [000311] n----+------ +--* IND long [000307] -----+------ | \--* ADD long [000305] #----+------ | +--* IND long [000304] #----+------ | | \--* IND long [000303] -----+------ | | \--* ADD long [000301] -----+------ | | +--* LCL_VAR long V21 tmp7 [000302] -----+------ | | \--* CNS_INT long 56 [000306] -----+------ | \--* CNS_INT long 56 [000314] -----+------ \--* CNS_INT long 0 ------------ BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} ***** BB65 STMT00162 (IL ???... ???) [001170] -A---------- * ASG long [001169] D------N---- +--* LCL_VAR long V23 tmp9 [000316] n----+?----- \--* IND long [000317] -----+?----- \--* ADD long [000318] #----+?----- +--* IND long [000319] #----+?----- | \--* IND long [000320] -----+?----- | \--* ADD long [000321] -----+?----- | +--* LCL_VAR long V21 tmp7 [000322] -----+?----- | \--* CNS_INT long 56 [000323] -----+?----- \--* CNS_INT long 56 ------------ BB66 [???..???), preds={BB64} succs={BB67} ***** BB66 STMT00163 (IL ???... ???) [001172] -AC-G------- * ASG long [001171] D------N---- +--* LCL_VAR long V23 tmp9 [000313] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000300] -----+?----- arg0 in rcx +--* LCL_VAR long V21 tmp7 [000312] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} ***** BB67 STMT00056 (IL ???... ???) [000295] --CXG+------ * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000328] -----+------ arg0 in rcx +--* LCL_VAR long V23 tmp9 [000310] -----+------ arg1 in rdx \--* LCL_VAR ref V01 arg1 ------------ BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} ***** BB68 STMT00043 (IL 0x1DD...0x1E2) [000233] --CXG+------ * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Clone loops *************** In optCloneLoops() Before loop cloning: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop idxlen bwd bwd-target align BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal gcsafe BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop idxlen bwd bwd-target BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe BB36 [0108] 1 BB34 1 [???..???) i gcsafe BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen BB54 [0044] 2 BB48,BB53 0.50 [261..276) i BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} ***** BB01 STMT00000 (IL 0x000...0x006) [000003] -----+------ * JTRUE void [000002] J----+-N---- \--* EQ int [000000] -----+------ +--* LCL_VAR ref V01 arg1 [000001] -----+------ \--* CNS_INT ref null ------------ BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00001 (IL 0x00E...0x014) [000008] ---XG+------ * JTRUE void [000007] J--XG+-N---- \--* NE int [000005] ---XG+------ +--* IND ref [000814] -----+------ | \--* ADD byref [000004] -----+------ | +--* LCL_VAR ref V00 this [000813] -----+------ | \--* CNS_INT long 8 field offset Fseq[_buckets] [000006] -----+------ \--* CNS_INT ref null ------------ BB03 [016..01E), preds={BB02} succs={BB04} ***** BB03 STMT00085 (IL ???... ???) [000528] --CXG+------ * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize [000526] -----+------ this in rcx +--* LCL_VAR ref V00 this [000527] -----+------ arg1 in rdx \--* CNS_INT int 0 ------------ BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ***** BB04 STMT00088 (IL 0x01E... ???) [000544] -A-XG+------ * ASG bool [000543] D----+-N---- +--* LCL_VAR int V33 tmp19 [000012] N--XG+------ \--* NE int [000010] ---XG+------ +--* IND ref [000818] -----+------ | \--* ADD byref [000009] -----+------ | +--* LCL_VAR ref V00 this [000817] -----+------ | \--* CNS_INT long 8 field offset Fseq[_buckets] [000011] -----+------ \--* CNS_INT ref null ***** BB04 STMT00091 (IL 0x01E... ???) [000554] -A--G+------ * ASG ref [000553] D----+-N---- +--* LCL_VAR ref V34 tmp20 [000538] #---G+------ \--* IND ref [000537] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB04 STMT00092 (IL 0x01E... ???) [000556] -A--G+------ * ASG ref [000555] D----+-N---- +--* LCL_VAR ref V35 tmp21 [000540] #---G+------ \--* IND ref [000539] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB04 STMT00089 (IL 0x01E... ???) [000549] -----+------ * JTRUE void [000548] J----+-N---- \--* NE int [000546] -----+------ +--* LCL_VAR int V33 tmp19 [000547] -----+------ \--* CNS_INT int 0 ------------ BB05 [01E..01F), preds={BB04} succs={BB06} ***** BB05 STMT00090 (IL 0x01E... ???) [000552] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000550] -----+------ arg0 in rcx +--* LCL_VAR ref V34 tmp20 [000551] -----+------ arg1 in rdx \--* LCL_VAR ref V35 tmp21 ------------ BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} ***** BB06 STMT00003 (IL 0x02C... ???) [000018] -A-XG+------ * ASG ref [000017] D----+-N---- +--* LCL_VAR ref V04 loc0 [000016] ---XG+------ \--* IND ref [000822] -----+------ \--* ADD byref [000015] -----+------ +--* LCL_VAR ref V00 this [000821] -----+------ \--* CNS_INT long 16 field offset Fseq[_entries] ***** BB06 STMT00094 (IL 0x033... ???) [000566] -A---+------ * ASG bool [000565] D----+-N---- +--* LCL_VAR int V36 tmp22 [000021] N----+------ \--* NE int [000019] -----+------ +--* LCL_VAR ref V04 loc0 [000020] -----+------ \--* CNS_INT ref null ***** BB06 STMT00097 (IL 0x033... ???) [000576] -A--G+------ * ASG ref [000575] D----+-N---- +--* LCL_VAR ref V37 tmp23 [000562] #---G+------ \--* IND ref [000561] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB06 STMT00095 (IL 0x033... ???) [000571] -----+------ * JTRUE void [000570] J----+-N---- \--* NE int [000568] -----+------ +--* LCL_VAR int V36 tmp22 [000569] -----+------ \--* CNS_INT int 0 ------------ BB07 [033..034), preds={BB06} succs={BB08} ***** BB07 STMT00096 (IL 0x033... ???) [000574] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000824] #---G+------ arg0 in rcx +--* IND ref [000823] H----+------ | \--* CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" [000573] -----+------ arg1 in rdx \--* LCL_VAR ref V37 tmp23 ------------ BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} ***** BB08 STMT00005 (IL 0x041... ???) [000028] -A-XG+------ * ASG ref [000027] D----+-N---- +--* LCL_VAR ref V05 loc1 [000026] ---XG+------ \--* IND ref [000828] -----+------ \--* ADD byref [000025] -----+------ +--* LCL_VAR ref V00 this [000827] -----+------ \--* CNS_INT long 24 field offset Fseq[_comparer] ***** BB08 STMT00006 (IL 0x048...0x049) [000032] -----+------ * JTRUE void [000031] J----+-N---- \--* EQ int [000029] -----+------ +--* LCL_VAR ref V05 loc1 [000030] -----+------ \--* CNS_INT ref null ------------ BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} ***** BB09 STMT00079 (IL 0x04B...0x052) [000489] -A-X-+------ * ASG long [000488] D----+-N---- +--* LCL_VAR long V29 tmp15 [000487] #--X-+------ \--* IND long [000486] !----+------ \--* LCL_VAR ref V00 this ***** BB09 STMT00080 (IL ???... ???) [000499] -A---+------ * ASG ref [000498] D----+-N---- +--* LCL_VAR ref V30 tmp16 [000485] -----+------ \--* LCL_VAR ref V01 arg1 ***** BB09 STMT00149 (IL ???... ???) [001148] ------------ * JTRUE void [000505] J----+-N---- \--* EQ int [000501] n----+------ +--* IND long [000497] -----+------ | \--* ADD long [000495] #----+------ | +--* IND long [000494] #----+------ | | \--* IND long [000493] -----+------ | | \--* ADD long [000491] -----+------ | | +--* LCL_VAR long V29 tmp15 [000492] -----+------ | | \--* CNS_INT long 56 [000496] -----+------ | \--* CNS_INT long 64 [000504] -----+------ \--* CNS_INT long 0 ------------ BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} ***** BB10 STMT00150 (IL ???... ???) [001150] -A---------- * ASG long [001149] D------N---- +--* LCL_VAR long V31 tmp17 [000506] n----+?----- \--* IND long [000507] -----+?----- \--* ADD long [000508] #----+?----- +--* IND long [000509] #----+?----- | \--* IND long [000510] -----+?----- | \--* ADD long [000511] -----+?----- | +--* LCL_VAR long V29 tmp15 [000512] -----+?----- | \--* CNS_INT long 56 [000513] -----+?----- \--* CNS_INT long 64 ------------ BB11 [???..???), preds={BB09} succs={BB12} ***** BB11 STMT00151 (IL ???... ???) [001152] -AC-G------- * ASG long [001151] D------N---- +--* LCL_VAR long V31 tmp17 [000503] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000490] -----+?----- arg0 in rcx +--* LCL_VAR long V29 tmp15 [000502] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} ***** BB12 STMT00082 (IL ???... ???) [000520] -A---+------ * ASG long [000519] D----+-N---- +--* LCL_VAR long V32 tmp18 [000518] -----+------ \--* LCL_VAR long V31 tmp17 ***** BB12 STMT00083 (IL ???... ???) [000524] -ACXG+------ * ASG int [000523] D----+-N---- +--* LCL_VAR int V15 tmp1 [000522] --CXG+------ \--* CALL ind stub int [000521] -----+------ calli tgt \--* LCL_VAR long V31 tmp17 [000484] -----+------ this in rcx +--* LCL_VAR ref V05 loc1 [000831] -----+------ arg1 in r11 +--* LCL_VAR long V31 tmp17 r11 REG r11 [000500] -----+------ arg2 in rdx \--* LCL_VAR ref V01 arg1 ------------ BB13 [054..061), preds={BB08} succs={BB14} ***** BB13 STMT00007 (IL 0x054...0x05C) [000038] -ACXG+------ * ASG int [000037] D----+-N---- +--* LCL_VAR int V15 tmp1 [000035] --CXG+------ \--* CALLV vt-ind int System.Object.GetHashCode [000843] n--X-+------ control expr \--* IND long [000842] ---X-+------ \--* ADD long [000840] #--X-+------ +--* IND long [000839] ---X-+------ | \--* ADD long [000837] #--X-+------ | +--* IND long [000836] -----+------ | | \--* LCL_VAR ref V01 arg1 [000838] -----+------ | \--* CNS_INT int 72 [000841] -----+------ \--* CNS_INT int 24 [000033] -----+------ this in rcx \--* LCL_VAR ref V01 arg1 ------------ BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ***** BB14 STMT00008 (IL ???...0x061) [000042] -A---+------ * ASG int [000041] D----+-N---- +--* LCL_VAR int V06 loc2 [000040] -----+------ \--* LCL_VAR int V15 tmp1 ***** BB14 STMT00009 (IL 0x062...0x063) [000045] -A---+------ * ASG int [000044] D----+-N---- +--* LCL_VAR int V07 loc3 [000043] -----+------ \--* CNS_INT int 0 ***** BB14 STMT00098 (IL 0x064... ???) [000580] -A-XG+------ * ASG ref [000579] D----+-N---- +--* LCL_VAR ref V39 tmp25 [000578] ---XG+------ \--* IND ref [000845] -----+------ \--* ADD byref [000046] -----+------ +--* LCL_VAR ref V00 this [000844] -----+------ \--* CNS_INT long 8 field offset Fseq[_buckets] ***** BB14 STMT00105 (IL 0x064... ???) [000629] -A-X-+------ * ASG int [000628] D----+-N---- +--* LCL_VAR int V40 tmp26 [000583] ---X-+------ \--* ARR_LENGTH int [000582] -----+------ \--* LCL_VAR ref V39 tmp25 ***** BB14 STMT00106 (IL 0x064... ???) [000631] -A-XG+------ * ASG long [000630] D----+-N---- +--* LCL_VAR long V41 tmp27 [000585] ---XG+------ \--* IND long [000847] -----+------ \--* ADD byref [000584] -----+------ +--* LCL_VAR ref V00 this [000846] -----+------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] ***** BB14 STMT00108 (IL 0x064... ???) [000642] -A---+------ * ASG bool [000641] D----+-N---- +--* LCL_VAR int V43 tmp29 [000599] N----+---U-- \--* LE int [000597] -----+------ +--* LCL_VAR int V40 tmp26 [000598] -----+------ \--* CNS_INT int 0x7FFFFFFF ***** BB14 STMT00111 (IL 0x064... ???) [000652] -A--G+------ * ASG ref [000651] D----+-N---- +--* LCL_VAR ref V44 tmp30 [000636] #---G+------ \--* IND ref [000635] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB14 STMT00112 (IL 0x064... ???) [000654] -A--G+------ * ASG ref [000653] D----+-N---- +--* LCL_VAR ref V45 tmp31 [000638] #---G+------ \--* IND ref [000637] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB14 STMT00109 (IL 0x064... ???) [000647] -----+------ * JTRUE void [000646] J----+-N---- \--* NE int [000644] -----+------ +--* LCL_VAR int V43 tmp29 [000645] -----+------ \--* CNS_INT int 0 ------------ BB15 [064..065), preds={BB14} succs={BB16} ***** BB15 STMT00110 (IL 0x064... ???) [000650] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000648] -----+------ arg0 in rcx +--* LCL_VAR ref V44 tmp30 [000649] -----+------ arg1 in rdx \--* LCL_VAR ref V45 tmp31 ------------ BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} ***** BB16 STMT00103 (IL 0x064... ???) [000619] -A---+------ * ASG int [000618] D----+-N---- +--* LCL_VAR int V42 tmp28 [000617] -----+------ \--* CAST int <- uint <- long [000616] -----+------ \--* RSZ long [000614] -----+------ +--* MUL long [000611] -----+------ | +--* ADD long [000608] -----+------ | | +--* RSZ long [000606] -----+------ | | | +--* MUL long [000604] -----+------ | | | | +--* LCL_VAR long V41 tmp27 [000605] -----+---U-- | | | | \--* CAST long <- ulong <- uint [000047] -----+------ | | | | \--* LCL_VAR int V06 loc2 [000607] -----+------ | | | \--* CNS_INT int 32 [000610] -----+------ | | \--* CNS_INT long 1 [000613] -----+---U-- | \--* CAST long <- ulong <- uint [000612] -----+------ | \--* LCL_VAR int V40 tmp26 [000615] -----+------ \--* CNS_INT int 32 ***** BB16 STMT00114 (IL 0x064... ???) [000665] -A-X-+------ * ASG bool [000664] D----+-N---- +--* LCL_VAR int V46 tmp32 [000624] ---X-+------ \--* EQ int [000620] -----+------ +--* LCL_VAR int V42 tmp28 [000623] ---X-+------ \--* UMOD int [000621] -----+------ +--* LCL_VAR int V06 loc2 [000622] -----+------ \--* LCL_VAR int V40 tmp26 ***** BB16 STMT00117 (IL 0x064... ???) [000675] -A--G+------ * ASG ref [000674] D----+-N---- +--* LCL_VAR ref V47 tmp33 [000659] #---G+------ \--* IND ref [000658] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB16 STMT00118 (IL 0x064... ???) [000677] -A--G+------ * ASG ref [000676] D----+-N---- +--* LCL_VAR ref V48 tmp34 [000661] #---G+------ \--* IND ref [000660] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB16 STMT00115 (IL 0x064... ???) [000670] -----+------ * JTRUE void [000669] J----+-N---- \--* NE int [000667] -----+------ +--* LCL_VAR int V46 tmp32 [000668] -----+------ \--* CNS_INT int 0 ------------ BB17 [064..065), preds={BB16} succs={BB18} ***** BB17 STMT00116 (IL 0x064... ???) [000673] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000671] -----+------ arg0 in rcx +--* LCL_VAR ref V47 tmp33 [000672] -----+------ arg1 in rdx \--* LCL_VAR ref V48 tmp34 ------------ BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} ***** BB18 STMT00100 (IL 0x064... ???) [000591] -A-XG+------ * ASG byref [000590] D----+-N---- +--* LCL_VAR byref V38 tmp24 [000862] ---XG+------ \--* COMMA byref [000855] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000627] -----+------ | +--* LCL_VAR int V42 tmp28 [000854] ---X-+------ | \--* ARR_LENGTH int [000581] -----+------ | \--* LCL_VAR ref V39 tmp25 [000863] ----G------- \--* ADDR byref [000588] a---G+-N---- \--* IND int [000861] -----+------ \--* ADD byref [000852] -----+------ +--* LCL_VAR ref V39 tmp25 [000860] -----+------ \--* ADD long [000858] -----+------ +--* LSH long [000856] -----+------ | +--* CAST long <- int [000853] i----+------ | | \--* LCL_VAR int V42 tmp28 [000857] -----+-N---- | \--* CNS_INT long 2 [000859] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB18 STMT00101 (IL 0x064... ???) [000595] -A---+------ * ASG ref [000594] D----+-N---- +--* LCL_VAR ref V39 tmp25 [000593] -----+------ \--* CNS_INT ref null ***** BB18 STMT00011 (IL ???... ???) [000051] -A---+------ * ASG byref [000050] D----+-N---- +--* LCL_VAR byref V08 loc4 [000592] -----+------ \--* LCL_VAR byref V38 tmp24 ***** BB18 STMT00012 (IL 0x06D...0x072) [000057] -A-XG+------ * ASG int [000056] D----+-N---- +--* LCL_VAR int V09 loc5 [000055] ---XG+------ \--* ADD int [000053] *--XG+------ +--* IND int [000052] -----+------ | \--* LCL_VAR byref V38 tmp24 [000054] -----+------ \--* CNS_INT int -1 ***** BB18 STMT00013 (IL 0x074...0x075) [000061] -----+------ * JTRUE void [000060] J----+-N---- \--* NE int [000058] -----+------ +--* LCL_VAR ref V05 loc1 [000059] -----+------ \--* CNS_INT ref null ------------ BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} ***** BB19 STMT00059 (IL 0x0FF...0x104) [000356] -A-X-+------ * ASG long [000355] D----+-N---- +--* LCL_VAR long V24 tmp10 [000354] #--X-+------ \--* IND long [000353] !----+------ \--* LCL_VAR ref V00 this ***** BB19 STMT00152 (IL ???... ???) [001153] ------------ * JTRUE void [000369] J----+-N---- \--* EQ int [000365] n----+------ +--* IND long [000364] -----+------ | \--* ADD long [000362] #----+------ | +--* IND long [000361] #----+------ | | \--* IND long [000360] -----+------ | | \--* ADD long [000358] -----+------ | | +--* LCL_VAR long V24 tmp10 [000359] -----+------ | | \--* CNS_INT long 56 [000363] -----+------ | \--* CNS_INT long 32 [000368] -----+------ \--* CNS_INT long 0 ------------ BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} ***** BB20 STMT00153 (IL ???... ???) [001155] -A---------- * ASG long [001154] D------N---- +--* LCL_VAR long V25 tmp11 [000370] n----+?----- \--* IND long [000371] -----+?----- \--* ADD long [000372] #----+?----- +--* IND long [000373] #----+?----- | \--* IND long [000374] -----+?----- | \--* ADD long [000375] -----+?----- | +--* LCL_VAR long V24 tmp10 [000376] -----+?----- | \--* CNS_INT long 56 [000377] -----+?----- \--* CNS_INT long 32 ------------ BB21 [???..???), preds={BB19} succs={BB22} ***** BB21 STMT00154 (IL ???... ???) [001157] -AC-G------- * ASG long [001156] D------N---- +--* LCL_VAR long V25 tmp11 [000367] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000357] -----+?----- arg0 in rcx +--* LCL_VAR long V24 tmp10 [000366] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB22 [???..106), preds={BB20,BB21} succs={BB23} ***** BB22 STMT00062 (IL ???... ???) [000386] -ACXG+------ * ASG ref [000385] D----+-N---- +--* LCL_VAR ref V12 loc8 [000352] --CXG+------ \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default [000382] -----+------ arg0 in rcx \--* LCL_VAR long V25 tmp11 ------------ BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} ***** BB23 STMT00063 (IL 0x106...0x10B) [000391] ---X-+------ * JTRUE void [000390] N--X-+-N-U-- \--* GE int [000387] -----+------ +--* LCL_VAR int V09 loc5 [000389] ---X-+------ \--* ARR_LENGTH int [000388] -----+------ \--* LCL_VAR ref V04 loc0 ------------ BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} ***** BB24 STMT00064 (IL 0x110...0x11E) [000399] ---XG+------ * JTRUE void [000398] N--XG+-N-U-- \--* NE int [000396] *--XG+------ +--* IND int [000868] ---XG+------ | \--* ADD byref [000879] ---XG+------ | +--* COMMA byref [000872] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000393] -----+------ | | | +--* LCL_VAR int V09 loc5 [000871] ---X-+------ | | | \--* ARR_LENGTH int [000392] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000882] ----G------- | | \--* ADDR byref [000394] a---G+-N---- | | \--* IND struct [000878] -----+------ | | \--* ADD byref [000869] -----+------ | | +--* LCL_VAR ref V04 loc0 [000877] -----+------ | | \--* ADD long [000875] -----+------ | | +--* LSH long [000881] -----+------ | | | +--* MUL long [000873] -----+------ | | | | +--* CAST long <- int [000870] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000880] ------------ | | | | \--* CNS_INT long 3 [000874] -----+-N---- | | | \--* CNS_INT long 3 [000876] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000867] -----+------ | \--* CNS_INT long 16 field offset Fseq[hashCode] [000397] -----+------ \--* LCL_VAR int V06 loc2 ------------ BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} ***** BB25 STMT00069 (IL 0x120...0x135) [000428] --CXG+------ * JTRUE void [000427] J-CXG+-N---- \--* NE int [000425] --CXG+------ +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals [000908] n--X-+------ control expr | \--* IND long [000907] ---X-+------ | \--* ADD long [000905] #--X-+------ | +--* IND long [000904] ---X-+------ | | \--* ADD long [000902] #--X-+------ | | +--* IND long [000901] -----+------ | | | \--* LCL_VAR ref V12 loc8 [000903] -----+------ | | \--* CNS_INT int 72 [000906] -----+------ | \--* CNS_INT int 32 [000893] ---XG+------ arg1 in rdx | +--* COMMA ref [000886] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000420] -----+------ | | | +--* LCL_VAR int V09 loc5 [000885] ---X-+------ | | | \--* ARR_LENGTH int [000419] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000897] *---G+------ | | \--* IND ref [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] [000421] a---G+-N---- | | \--* IND struct [000892] -----+------ | | \--* ADD byref [000883] -----+------ | | +--* LCL_VAR ref V04 loc0 [000891] -----+------ | | \--* ADD long [000889] -----+------ | | +--* LSH long [000895] -----+------ | | | +--* MUL long [000887] -----+------ | | | | +--* CAST long <- int [000884] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000894] ------------ | | | | \--* CNS_INT long 3 [000888] -----+-N---- | | | \--* CNS_INT long 3 [000890] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000418] -----+------ this in rcx | +--* LCL_VAR ref V12 loc8 [000424] -----+------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 [000426] -----+------ \--* CNS_INT int 0 ------------ BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} ***** BB26 STMT00065 (IL 0x157...0x164) [000406] -A-XG+------ * ASG int [000405] D----+-N---- +--* LCL_VAR int V09 loc5 [000404] *--XG+------ \--* IND int [000932] ---XG+------ \--* ADD byref [000943] ---XG+------ +--* COMMA byref [000936] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000401] -----+------ | | +--* LCL_VAR int V09 loc5 [000935] ---X-+------ | | \--* ARR_LENGTH int [000400] -----+------ | | \--* LCL_VAR ref V04 loc0 [000946] ----G------- | \--* ADDR byref [000402] a---G+-N---- | \--* IND struct [000942] -----+------ | \--* ADD byref [000933] -----+------ | +--* LCL_VAR ref V04 loc0 [000941] -----+------ | \--* ADD long [000939] -----+------ | +--* LSH long [000945] -----+------ | | +--* MUL long [000937] -----+------ | | | +--* CAST long <- int [000934] i----+------ | | | | \--* LCL_VAR int V09 loc5 [000944] ------------ | | | \--* CNS_INT long 3 [000938] -----+-N---- | | \--* CNS_INT long 3 [000940] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [000931] -----+------ \--* CNS_INT long 20 field offset Fseq[next] ***** BB26 STMT00066 (IL 0x166...0x169) [000411] -A---+------ * ASG int [000410] D----+-N---- +--* LCL_VAR int V07 loc3 [000409] -----+------ \--* ADD int [000407] -----+------ +--* LCL_VAR int V07 loc3 [000408] -----+------ \--* CNS_INT int 1 ***** BB26 STMT00067 (IL 0x16A...0x16E) [000416] ---X-+------ * JTRUE void [000415] N--X-+-N-U-- \--* GT int [000412] -----+------ +--* LCL_VAR int V07 loc3 [000414] ---X-+------ \--* ARR_LENGTH int [000413] -----+------ \--* LCL_VAR ref V04 loc0 ------------ BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} ------------ BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} ***** BB28 STMT00070 (IL 0x137...0x139) [000432] -----+------ * JTRUE void [000431] N----+-N-U-- \--* NE int [000909] -----+------ +--* CAST int <- ubyte <- int [000429] -----+------ | \--* LCL_VAR int V03 arg3 [000430] -----+------ \--* CNS_INT int 1 ------------ BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} ***** BB29 STMT00077 (IL 0x13B...0x144) [000481] -A-XG+------ * ASG ref [000480] *--XG+-N---- +--* IND ref [000911] ---XG+------ | \--* ADD byref [000922] ---XG+------ | +--* COMMA byref [000915] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000476] -----+------ | | | +--* LCL_VAR int V09 loc5 [000914] ---X-+------ | | | \--* ARR_LENGTH int [000475] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000925] ----G------- | | \--* ADDR byref [000477] a---G+-N---- | | \--* IND struct [000921] -----+------ | | \--* ADD byref [000912] -----+------ | | +--* LCL_VAR ref V04 loc0 [000920] -----+------ | | \--* ADD long [000918] -----+------ | | +--* LSH long [000924] -----+------ | | | +--* MUL long [000916] -----+------ | | | | +--* CAST long <- int [000913] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000923] ------------ | | | | \--* CNS_INT long 3 [000917] -----+-N---- | | | \--* CNS_INT long 3 [000919] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000910] -----+------ | \--* CNS_INT long 8 field offset Fseq[value] [000479] -----+------ \--* LCL_VAR ref V02 arg2 ------------ BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} ***** BB30 STMT00071 (IL 0x14B...0x14D) [000436] -----+------ * JTRUE void [000435] N----+-N-U-- \--* EQ int [000926] -----+------ +--* CAST int <- ubyte <- int [000433] -----+------ | \--* LCL_VAR int V03 arg3 [000434] -----+------ \--* CNS_INT int 2 ------------ BB31 [???..???) (return), preds={BB30,BB41} succs={} ***** BB31 STMT00148 (IL ???... ???) [000811] -----+------ * RETURN int [000437] -----+------ \--* CNS_INT int 0 ------------ BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} ***** BB32 STMT00014 (IL 0x177...0x17C) ( 11, 9) [000066] ---X-------- * JTRUE void ( 9, 7) [000065] N--X---N-U-- \--* LE int ( 5, 4) [000064] ---X-------- +--* ARR_LENGTH int ( 3, 2) [000063] ------------ | \--* LCL_VAR ref V04 loc0 ( 3, 2) [000062] ------------ \--* LCL_VAR int V09 loc5 ------------ BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} ***** BB33 STMT00039 (IL 0x17E...0x18C) [000215] ---XG+------ * JTRUE void [000214] N--XG+-N-U-- \--* NE int [000212] *--XG+------ +--* IND int [000948] ---XG+------ | \--* ADD byref [000959] ---XG+------ | +--* COMMA byref [000952] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000209] -----+------ | | | +--* LCL_VAR int V09 loc5 [000951] ---X-+------ | | | \--* ARR_LENGTH int [000208] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000962] ----G------- | | \--* ADDR byref [000210] a---G+-N---- | | \--* IND struct [000958] -----+------ | | \--* ADD byref [000949] -----+------ | | +--* LCL_VAR ref V04 loc0 [000957] -----+------ | | \--* ADD long [000955] -----+------ | | +--* LSH long [000961] -----+------ | | | +--* MUL long [000953] -----+------ | | | | +--* CAST long <- int [000950] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000960] ------------ | | | | \--* CNS_INT long 3 [000954] -----+-N---- | | | \--* CNS_INT long 3 [000956] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000947] -----+------ | \--* CNS_INT long 16 field offset Fseq[hashCode] [000213] -----+------ \--* LCL_VAR int V06 loc2 ------------ BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} ***** BB34 STMT00045 (IL 0x18E...0x1A2) [000246] -A-XG+------ * ASG ref [000245] D----+-N---- +--* LCL_VAR ref V17 tmp3 [000973] ---XG+------ \--* COMMA ref [000966] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000236] -----+------ | +--* LCL_VAR int V09 loc5 [000965] ---X-+------ | \--* ARR_LENGTH int [000235] -----+------ | \--* LCL_VAR ref V04 loc0 [000977] *---G+------ \--* IND ref [000976] ----G------- \--* ADDR byref Zero Fseq[key] [000237] a---G+-N---- \--* IND struct [000972] -----+------ \--* ADD byref [000963] -----+------ +--* LCL_VAR ref V04 loc0 [000971] -----+------ \--* ADD long [000969] -----+------ +--* LSH long [000975] -----+------ | +--* MUL long [000967] -----+------ | | +--* CAST long <- int [000964] i----+------ | | | \--* LCL_VAR int V09 loc5 [000974] ------------ | | \--* CNS_INT long 3 [000968] -----+-N---- | \--* CNS_INT long 3 [000970] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB34 STMT00044 (IL 0x18E... ???) [000244] -A-X-+------ * ASG long [000243] D----+-N---- +--* LCL_VAR long V16 tmp2 [000242] #--X-+------ \--* IND long [000241] !----+------ \--* LCL_VAR ref V00 this ***** BB34 STMT00046 (IL ???... ???) [000257] -A---+------ * ASG ref [000256] D----+-N---- +--* LCL_VAR ref V18 tmp4 [000240] -----+------ \--* LCL_VAR ref V01 arg1 ***** BB34 STMT00158 (IL ???... ???) [001163] ------------ * JTRUE void [000263] J----+-N---- \--* EQ int [000259] n----+------ +--* IND long [000255] -----+------ | \--* ADD long [000253] #----+------ | +--* IND long [000252] #----+------ | | \--* IND long [000251] -----+------ | | \--* ADD long [000249] -----+------ | | +--* LCL_VAR long V16 tmp2 [000250] -----+------ | | \--* CNS_INT long 56 [000254] -----+------ | \--* CNS_INT long 48 [000262] -----+------ \--* CNS_INT long 0 ------------ BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} ***** BB35 STMT00159 (IL ???... ???) [001165] -A---------- * ASG long [001164] D------N---- +--* LCL_VAR long V19 tmp5 [000264] n----+?----- \--* IND long [000265] -----+?----- \--* ADD long [000266] #----+?----- +--* IND long [000267] #----+?----- | \--* IND long [000268] -----+?----- | \--* ADD long [000269] -----+?----- | +--* LCL_VAR long V16 tmp2 [000270] -----+?----- | \--* CNS_INT long 56 [000271] -----+?----- \--* CNS_INT long 48 ------------ BB36 [???..???), preds={BB34} succs={BB37} ***** BB36 STMT00160 (IL ???... ???) [001167] -AC-G------- * ASG long [001166] D------N---- +--* LCL_VAR long V19 tmp5 [000261] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000248] -----+?----- arg0 in rcx +--* LCL_VAR long V16 tmp2 [000260] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} ***** BB37 STMT00048 (IL ???... ???) [000278] -A---+------ * ASG long [000277] D----+-N---- +--* LCL_VAR long V20 tmp6 [000276] -----+------ \--* LCL_VAR long V19 tmp5 ***** BB37 STMT00049 (IL ???... ???) [000283] --CXG+------ * JTRUE void [000282] J-CXG+-N---- \--* EQ int [000280] --CXG+------ +--* CALL ind stub int [000279] -----+------ calli tgt | \--* LCL_VAR long V19 tmp5 [000234] -----+------ this in rcx | +--* LCL_VAR ref V05 loc1 [000980] -----+------ arg1 in r11 | +--* LCL_VAR long V19 tmp5 r11 REG r11 [000247] -----+------ arg2 in rdx | +--* LCL_VAR ref V17 tmp3 [000258] -----+------ arg3 in r8 | \--* LCL_VAR ref V01 arg1 [000281] -----+------ \--* CNS_INT int 0 ------------ BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} ***** BB38 STMT00050 (IL 0x1A4...0x1A6) [000287] -----+------ * JTRUE void [000286] N----+-N-U-- \--* NE int [000985] -----+------ +--* CAST int <- ubyte <- int [000284] -----+------ | \--* LCL_VAR int V03 arg3 [000285] -----+------ \--* CNS_INT int 1 ------------ BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} ***** BB39 STMT00057 (IL 0x1A8...0x1B1) [000336] -A-XG+------ * ASG ref [000335] *--XG+-N---- +--* IND ref [000987] ---XG+------ | \--* ADD byref [000998] ---XG+------ | +--* COMMA byref [000991] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000331] -----+------ | | | +--* LCL_VAR int V09 loc5 [000990] ---X-+------ | | | \--* ARR_LENGTH int [000330] -----+------ | | | \--* LCL_VAR ref V04 loc0 [001001] ----G------- | | \--* ADDR byref [000332] a---G+-N---- | | \--* IND struct [000997] -----+------ | | \--* ADD byref [000988] -----+------ | | +--* LCL_VAR ref V04 loc0 [000996] -----+------ | | \--* ADD long [000994] -----+------ | | +--* LSH long [001000] -----+------ | | | +--* MUL long [000992] -----+------ | | | | +--* CAST long <- int [000989] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000999] ------------ | | | | \--* CNS_INT long 3 [000993] -----+-N---- | | | \--* CNS_INT long 3 [000995] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000986] -----+------ | \--* CNS_INT long 8 field offset Fseq[value] [000334] -----+------ \--* LCL_VAR ref V02 arg2 ------------ BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} ***** BB40 STMT00051 (IL 0x1B8...0x1BA) [000291] -----+------ * JTRUE void [000290] N----+-N-U-- \--* EQ int [001002] -----+------ +--* CAST int <- ubyte <- int [000288] -----+------ | \--* LCL_VAR int V03 arg3 [000289] -----+------ \--* CNS_INT int 2 ------------ BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} ------------ BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} ***** BB42 STMT00040 (IL 0x1C4...0x1D1) [000222] -A-XG+------ * ASG int [000221] D----+-N---- +--* LCL_VAR int V09 loc5 [000220] *--XG+------ \--* IND int [001009] ---XG+------ \--* ADD byref [001020] ---XG+------ +--* COMMA byref [001013] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000217] -----+------ | | +--* LCL_VAR int V09 loc5 [001012] ---X-+------ | | \--* ARR_LENGTH int [000216] -----+------ | | \--* LCL_VAR ref V04 loc0 [001023] ----G------- | \--* ADDR byref [000218] a---G+-N---- | \--* IND struct [001019] -----+------ | \--* ADD byref [001010] -----+------ | +--* LCL_VAR ref V04 loc0 [001018] -----+------ | \--* ADD long [001016] -----+------ | +--* LSH long [001022] -----+------ | | +--* MUL long [001014] -----+------ | | | +--* CAST long <- int [001011] i----+------ | | | | \--* LCL_VAR int V09 loc5 [001021] ------------ | | | \--* CNS_INT long 3 [001015] -----+-N---- | | \--* CNS_INT long 3 [001017] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [001008] -----+------ \--* CNS_INT long 20 field offset Fseq[next] ***** BB42 STMT00041 (IL 0x1D3...0x1D6) [000227] -A---+------ * ASG int [000226] D----+-N---- +--* LCL_VAR int V07 loc3 [000225] -----+------ \--* ADD int [000223] -----+------ +--* LCL_VAR int V07 loc3 [000224] -----+------ \--* CNS_INT int 1 ***** BB42 STMT00042 (IL 0x1D7...0x1DB) [000232] ---X-+------ * JTRUE void [000231] N--X-+-N-U-- \--* GT int [000228] -----+------ +--* LCL_VAR int V07 loc3 [000230] ---X-+------ \--* ARR_LENGTH int [000229] -----+------ \--* LCL_VAR ref V04 loc0 ------------ BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} ------------ BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} ***** BB44 STMT00015 (IL 0x1E4...0x1EB) [000071] ---XG+------ * JTRUE void [000070] J--XG+-N---- \--* LE int [000068] ---XG+------ +--* IND int [001025] -----+------ | \--* ADD byref [000067] -----+------ | +--* LCL_VAR ref V00 this [001024] -----+------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] [000069] -----+------ \--* CNS_INT int 0 ------------ BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} ***** BB45 STMT00035 (IL 0x1ED...0x1F3) [000174] -A-XG+------ * ASG int [000173] D----+-N---- +--* LCL_VAR int V10 loc6 [000172] ---XG+------ \--* IND int [001027] -----+------ \--* ADD byref [000171] -----+------ +--* LCL_VAR ref V00 this [001026] -----+------ \--* CNS_INT long 60 field offset Fseq[_freeList] ***** BB45 STMT00120 (IL 0x1F5... ???) [000688] -A-XG+------ * ASG bool [000687] D----+-N---- +--* LCL_VAR int V49 tmp35 [000184] -A-XG+------ \--* GE int [000182] -A-XG+------ +--* ADD int [001050] -A-XG+------ | +--* NEG int [000181] *A-XG+------ | | \--* IND int [001029] -A-XG+------ | | \--* ADD byref [001044] -A-XG+------ | | +--* COMMA byref [001032] -A-XG+------ | | | +--* ASG int [001031] D----+-N---- | | | | +--* LCL_VAR int V62 tmp48 [000178] ---XG+------ | | | | \--* IND int [001046] -----+------ | | | | \--* ADD byref [000177] -----+------ | | | | +--* LCL_VAR ref V00 this [001045] -----+------ | | | | \--* CNS_INT long 60 field offset Fseq[_freeList] [001043] ---XG+------ | | | \--* COMMA byref [001036] ---X-+------ | | | +--* ARR_BOUNDS_CHECK_Rng void [001033] -----+------ | | | | +--* LCL_VAR int V62 tmp48 [001035] ---X-+------ | | | | \--* ARR_LENGTH int [000176] -----+------ | | | | \--* LCL_VAR ref V04 loc0 [001049] ----G------- | | | \--* ADDR byref [000179] a---G+-N---- | | | \--* IND struct [001042] -----+------ | | | \--* ADD byref [001030] -----+------ | | | +--* LCL_VAR ref V04 loc0 [001041] -----+------ | | | \--* ADD long [001039] -----+------ | | | +--* LSH long [001048] -----+------ | | | | +--* MUL long [001037] -----+------ | | | | | +--* CAST long <- int [001034] i----+------ | | | | | | \--* LCL_VAR int V62 tmp48 [001047] ------------ | | | | | \--* CNS_INT long 3 [001038] -----+-N---- | | | | \--* CNS_INT long 3 [001040] -----+------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] [001028] -----+------ | | \--* CNS_INT long 20 field offset Fseq[next] [000175] -----+------ | \--* CNS_INT int -3 [000183] -----+------ \--* CNS_INT int -1 ***** BB45 STMT00123 (IL 0x1F5... ???) [000698] -A--G+------ * ASG ref [000697] D----+-N---- +--* LCL_VAR ref V50 tmp36 [000684] #---G+------ \--* IND ref [000683] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB45 STMT00121 (IL 0x1F5... ???) [000693] -----+------ * JTRUE void [000692] J----+-N---- \--* NE int [000690] -----+------ +--* LCL_VAR int V49 tmp35 [000691] -----+------ \--* CNS_INT int 0 ------------ BB46 [1F5..1F6), preds={BB45} succs={BB47} ***** BB46 STMT00122 (IL 0x1F5... ???) [000696] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [001052] #---G+------ arg0 in rcx +--* IND ref [001051] H----+------ | \--* CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" [000695] -----+------ arg1 in rdx \--* LCL_VAR ref V50 tmp36 ------------ BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} ***** BB47 STMT00037 (IL 0x219... ???) [000200] -A-XG+------ * ASG int [000199] ---XG+-N---- +--* IND int [001056] -----+------ | \--* ADD byref [000190] -----+------ | +--* LCL_VAR ref V00 this [001055] -----+------ | \--* CNS_INT long 60 field offset Fseq[_freeList] [000198] -A-XG+------ \--* ADD int [001079] -A-XG+------ +--* NEG int [000197] *A-XG+------ | \--* IND int [001058] -A-XG+------ | \--* ADD byref [001073] -A-XG+------ | +--* COMMA byref [001061] -A-XG+------ | | +--* ASG int [001060] D----+-N---- | | | +--* LCL_VAR int V63 tmp49 [000194] ---XG+------ | | | \--* IND int [001075] -----+------ | | | \--* ADD byref [000193] -----+------ | | | +--* LCL_VAR ref V00 this [001074] -----+------ | | | \--* CNS_INT long 60 field offset Fseq[_freeList] [001072] ---XG+------ | | \--* COMMA byref [001065] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [001062] -----+------ | | | +--* LCL_VAR int V63 tmp49 [001064] ---X-+------ | | | \--* ARR_LENGTH int [000192] -----+------ | | | \--* LCL_VAR ref V04 loc0 [001078] ----G------- | | \--* ADDR byref [000195] a---G+-N---- | | \--* IND struct [001071] -----+------ | | \--* ADD byref [001059] -----+------ | | +--* LCL_VAR ref V04 loc0 [001070] -----+------ | | \--* ADD long [001068] -----+------ | | +--* LSH long [001077] -----+------ | | | +--* MUL long [001066] -----+------ | | | | +--* CAST long <- int [001063] i----+------ | | | | | \--* LCL_VAR int V63 tmp49 [001076] ------------ | | | | \--* CNS_INT long 3 [001067] -----+-N---- | | | \--* CNS_INT long 3 [001069] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [001057] -----+------ | \--* CNS_INT long 20 field offset Fseq[next] [000191] -----+------ \--* CNS_INT int -3 ***** BB47 STMT00038 (IL 0x233...0x23C) [000207] -A-XG+------ * ASG int [000206] ---XG+-N---- +--* IND int [001081] -----+------ | \--* ADD byref [000201] -----+------ | +--* LCL_VAR ref V00 this [001080] -----+------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] [000205] ---XG+------ \--* ADD int [000203] ---XG+------ +--* IND int [001083] -----+------ | \--* ADD byref [000202] -----+------ | +--* LCL_VAR ref V00 this [001082] -----+------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] [000204] -----+------ \--* CNS_INT int -1 ------------ BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} ***** BB48 STMT00016 (IL 0x243...0x249) [000075] -A-XG+------ * ASG int [000074] D----+-N---- +--* LCL_VAR int V13 loc9 [000073] ---XG+------ \--* IND int [001085] -----+------ \--* ADD byref [000072] -----+------ +--* LCL_VAR ref V00 this [001084] -----+------ \--* CNS_INT long 56 field offset Fseq[_count] ***** BB48 STMT00017 (IL 0x24B...0x250) [000080] ---X-+------ * JTRUE void [000079] N--X-+-N-U-- \--* NE int [000076] -----+------ +--* LCL_VAR int V13 loc9 [000078] ---X-+------ \--* ARR_LENGTH int [000077] -----+------ \--* LCL_VAR ref V04 loc0 ------------ BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00125 (IL 0x252... ???) [000705] --CXG+------ * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [001090] -ACXG-----L- arg1 SETUP +--* ASG int [001089] D------N---- | +--* LCL_VAR int V64 tmp50 [000702] --CXG+------ | \--* CALL int System.Collections.HashHelpers.ExpandPrime [000701] ---XG+------ arg0 in rcx | \--* IND int [001087] -----+------ | \--* ADD byref [000700] -----+------ | +--* LCL_VAR ref V00 this [001086] -----+------ | \--* CNS_INT long 56 field offset Fseq[_count] [001091] ------------ arg1 in rdx +--* LCL_VAR int V64 tmp50 [000163] -----+------ this in rcx +--* LCL_VAR ref V00 this [000704] -----+------ arg2 in r8 \--* CNS_INT int 0 ***** BB49 STMT00126 (IL 0x258... ???) [000711] -A-XG+------ * ASG ref [000710] D----+-N---- +--* LCL_VAR ref V52 tmp38 [000709] ---XG+------ \--* IND ref [001095] -----+------ \--* ADD byref [000165] -----+------ +--* LCL_VAR ref V00 this [001094] -----+------ \--* CNS_INT long 8 field offset Fseq[_buckets] ***** BB49 STMT00133 (IL 0x258... ???) [000760] -A-X-+------ * ASG int [000759] D----+-N---- +--* LCL_VAR int V53 tmp39 [000714] ---X-+------ \--* ARR_LENGTH int [000713] -----+------ \--* LCL_VAR ref V52 tmp38 ***** BB49 STMT00134 (IL 0x258... ???) [000762] -A-XG+------ * ASG long [000761] D----+-N---- +--* LCL_VAR long V54 tmp40 [000716] ---XG+------ \--* IND long [001097] -----+------ \--* ADD byref [000715] -----+------ +--* LCL_VAR ref V00 this [001096] -----+------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] ***** BB49 STMT00136 (IL 0x258... ???) [000773] -A---+------ * ASG bool [000772] D----+-N---- +--* LCL_VAR int V56 tmp42 [000730] N----+---U-- \--* LE int [000728] -----+------ +--* LCL_VAR int V53 tmp39 [000729] -----+------ \--* CNS_INT int 0x7FFFFFFF ***** BB49 STMT00139 (IL 0x258... ???) [000783] -A--G+------ * ASG ref [000782] D----+-N---- +--* LCL_VAR ref V57 tmp43 [000767] #---G+------ \--* IND ref [000766] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB49 STMT00140 (IL 0x258... ???) [000785] -A--G+------ * ASG ref [000784] D----+-N---- +--* LCL_VAR ref V58 tmp44 [000769] #---G+------ \--* IND ref [000768] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB49 STMT00137 (IL 0x258... ???) [000778] -----+------ * JTRUE void [000777] J----+-N---- \--* NE int [000775] -----+------ +--* LCL_VAR int V56 tmp42 [000776] -----+------ \--* CNS_INT int 0 ------------ BB50 [258..259), preds={BB49} succs={BB51} ***** BB50 STMT00138 (IL 0x258... ???) [000781] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000779] -----+------ arg0 in rcx +--* LCL_VAR ref V57 tmp43 [000780] -----+------ arg1 in rdx \--* LCL_VAR ref V58 tmp44 ------------ BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00131 (IL 0x258... ???) [000750] -A---+------ * ASG int [000749] D----+-N---- +--* LCL_VAR int V55 tmp41 [000748] -----+------ \--* CAST int <- uint <- long [000747] -----+------ \--* RSZ long [000745] -----+------ +--* MUL long [000742] -----+------ | +--* ADD long [000739] -----+------ | | +--* RSZ long [000737] -----+------ | | | +--* MUL long [000735] -----+------ | | | | +--* LCL_VAR long V54 tmp40 [000736] -----+---U-- | | | | \--* CAST long <- ulong <- uint [000166] -----+------ | | | | \--* LCL_VAR int V06 loc2 [000738] -----+------ | | | \--* CNS_INT int 32 [000741] -----+------ | | \--* CNS_INT long 1 [000744] -----+---U-- | \--* CAST long <- ulong <- uint [000743] -----+------ | \--* LCL_VAR int V53 tmp39 [000746] -----+------ \--* CNS_INT int 32 ***** BB51 STMT00142 (IL 0x258... ???) [000796] -A-X-+------ * ASG bool [000795] D----+-N---- +--* LCL_VAR int V59 tmp45 [000755] ---X-+------ \--* EQ int [000751] -----+------ +--* LCL_VAR int V55 tmp41 [000754] ---X-+------ \--* UMOD int [000752] -----+------ +--* LCL_VAR int V06 loc2 [000753] -----+------ \--* LCL_VAR int V53 tmp39 ***** BB51 STMT00145 (IL 0x258... ???) [000806] -A--G+------ * ASG ref [000805] D----+-N---- +--* LCL_VAR ref V60 tmp46 [000790] #---G+------ \--* IND ref [000789] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB51 STMT00146 (IL 0x258... ???) [000808] -A--G+------ * ASG ref [000807] D----+-N---- +--* LCL_VAR ref V61 tmp47 [000792] #---G+------ \--* IND ref [000791] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB51 STMT00143 (IL 0x258... ???) [000801] -----+------ * JTRUE void [000800] J----+-N---- \--* NE int [000798] -----+------ +--* LCL_VAR int V59 tmp45 [000799] -----+------ \--* CNS_INT int 0 ------------ BB52 [258..259), preds={BB51} succs={BB53} ***** BB52 STMT00144 (IL 0x258... ???) [000804] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000802] -----+------ arg0 in rcx +--* LCL_VAR ref V60 tmp46 [000803] -----+------ arg1 in rdx \--* LCL_VAR ref V61 tmp47 ------------ BB53 [258..259), preds={BB51,BB52} succs={BB54} ***** BB53 STMT00128 (IL 0x258... ???) [000722] -A-XG+------ * ASG byref [000721] D----+-N---- +--* LCL_VAR byref V51 tmp37 [001112] ---XG+------ \--* COMMA byref [001105] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000758] -----+------ | +--* LCL_VAR int V55 tmp41 [001104] ---X-+------ | \--* ARR_LENGTH int [000712] -----+------ | \--* LCL_VAR ref V52 tmp38 [001113] ----G------- \--* ADDR byref [000719] a---G+-N---- \--* IND int [001111] -----+------ \--* ADD byref [001102] -----+------ +--* LCL_VAR ref V52 tmp38 [001110] -----+------ \--* ADD long [001108] -----+------ +--* LSH long [001106] -----+------ | +--* CAST long <- int [001103] i----+------ | | \--* LCL_VAR int V55 tmp41 [001107] -----+-N---- | \--* CNS_INT long 2 [001109] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB53 STMT00129 (IL 0x258... ???) [000726] -A---+------ * ASG ref [000725] D----+-N---- +--* LCL_VAR ref V52 tmp38 [000724] -----+------ \--* CNS_INT ref null ***** BB53 STMT00034 (IL ???... ???) [000170] -A---+------ * ASG byref [000169] D----+-N---- +--* LCL_VAR byref V08 loc4 [000723] -----+------ \--* LCL_VAR byref V51 tmp37 ------------ BB54 [261..276), preds={BB48,BB53} succs={BB55} ***** BB54 STMT00018 (IL 0x261...0x263) [000083] -A---+------ * ASG int [000082] D----+-N---- +--* LCL_VAR int V10 loc6 [000081] -----+------ \--* LCL_VAR int V13 loc9 ***** BB54 STMT00019 (IL 0x265...0x26A) [000089] -A-XG+------ * ASG int [000088] ---XG+-N---- +--* IND int [001115] -----+------ | \--* ADD byref [000084] -----+------ | +--* LCL_VAR ref V00 this [001114] -----+------ | \--* CNS_INT long 56 field offset Fseq[_count] [000087] -----+------ \--* ADD int [000085] -----+------ +--* LCL_VAR int V13 loc9 [000086] -----+------ \--* CNS_INT int 1 ***** BB54 STMT00020 (IL 0x26F...0x275) [000093] -A-XG+------ * ASG ref [000092] D----+-N---- +--* LCL_VAR ref V04 loc0 [000091] ---XG+------ \--* IND ref [001117] -----+------ \--* ADD byref [000090] -----+------ +--* LCL_VAR ref V00 this [001116] -----+------ \--* CNS_INT long 16 field offset Fseq[_entries] ------------ BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} ***** BB55 STMT00021 (IL 0x276...0x27E) [000099] -A-XG+------ * ASG byref [000098] D----+-N---- +--* LCL_VAR byref V11 loc7 [001128] ---XG+------ \--* COMMA byref [001121] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000095] -----+------ | +--* LCL_VAR int V10 loc6 [001120] ---X-+------ | \--* ARR_LENGTH int [000094] -----+------ | \--* LCL_VAR ref V04 loc0 [001131] ----G------- \--* ADDR byref [000096] a---G+-N---- \--* IND struct [001127] -----+------ \--* ADD byref [001118] -----+------ +--* LCL_VAR ref V04 loc0 [001126] -----+------ \--* ADD long [001124] -----+------ +--* LSH long [001130] -----+------ | +--* MUL long [001122] -----+------ | | +--* CAST long <- int [001119] i----+------ | | | \--* LCL_VAR int V10 loc6 [001129] ------------ | | \--* CNS_INT long 3 [001123] -----+-N---- | \--* CNS_INT long 3 [001125] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB55 STMT00022 (IL 0x280...0x283) [000103] -A-XG+------ * ASG int [000102] *--XG+-N---- +--* IND int [001133] -----+------ | \--* ADD byref [000100] -----+------ | +--* LCL_VAR byref V11 loc7 [001132] -----+------ | \--* CNS_INT long 16 field offset Fseq[hashCode] [000101] -----+------ \--* LCL_VAR int V06 loc2 ***** BB55 STMT00023 (IL 0x288...0x28F) [000110] -A-XG+------ * ASG int [000109] *--XG+-N---- +--* IND int [001135] -----+------ | \--* ADD byref [000104] -----+------ | +--* LCL_VAR byref V11 loc7 [001134] -----+------ | \--* CNS_INT long 20 field offset Fseq[next] [000108] ---XG+------ \--* ADD int [000106] *--XG+------ +--* IND int [000105] -----+------ | \--* LCL_VAR byref V08 loc4 [000107] -----+------ \--* CNS_INT int -1 ***** BB55 STMT00024 (IL 0x294...0x297) [000114] -A-XG+------ * ASG ref [000113] *--XG+-N---- +--* IND ref [000111] -----+------ | \--* LCL_VAR byref V11 loc7 Zero Fseq[key] [000112] -----+------ \--* LCL_VAR ref V01 arg1 ***** BB55 STMT00025 (IL 0x29C...0x29F) [000118] -A-XG+------ * ASG ref [000117] *--XG+-N---- +--* IND ref [001137] -----+------ | \--* ADD byref [000115] -----+------ | +--* LCL_VAR byref V11 loc7 [001136] -----+------ | \--* CNS_INT long 8 field offset Fseq[value] [000116] -----+------ \--* LCL_VAR ref V02 arg2 ***** BB55 STMT00026 (IL 0x2A4...0x2AA) [000124] -A-XG+------ * ASG int [000123] *--X-+-N---- +--* IND int [000119] -----+------ | \--* LCL_VAR byref V08 loc4 [000122] -----+------ \--* ADD int [000120] -----+------ +--* LCL_VAR int V10 loc6 [000121] -----+------ \--* CNS_INT int 1 ***** BB55 STMT00027 (IL 0x2AB...0x2B4) [000131] -A-XG+------ * ASG int [000130] ---XG+-N---- +--* IND int [001139] -----+------ | \--* ADD byref [000125] -----+------ | +--* LCL_VAR ref V00 this [001138] -----+------ | \--* CNS_INT long 68 field offset Fseq[_version] [000129] ---XG+------ \--* ADD int [000127] ---XG+------ +--* IND int [001141] -----+------ | \--* ADD byref [000126] -----+------ | +--* LCL_VAR ref V00 this [001140] -----+------ | \--* CNS_INT long 68 field offset Fseq[_version] [000128] -----+------ \--* CNS_INT int 1 ***** BB55 STMT00028 (IL 0x2CA...0x2CD) [000148] -----+------ * JTRUE void [000147] N----+-N-U-- \--* LE int [000145] -----+------ +--* LCL_VAR int V07 loc3 [000146] -----+------ \--* CNS_INT int 100 ------------ BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} ***** BB56 STMT00030 (IL 0x2CF...0x2D5) [000156] --C-G+------ * JTRUE void [000155] J-C-G+-N---- \--* EQ int [000153] --C-G+------ +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS [000151] -----+------ arg1 in rdx | +--* LCL_VAR ref V05 loc1 [000152] H----+-N---- arg0 in rcx | \--* CNS_INT(h) long 0xd1ffab1e class [000154] -----+------ \--* CNS_INT ref null ------------ BB57 [2D7..2E3), preds={BB56} succs={BB58} ***** BB57 STMT00031 (IL 0x2D7...0x2DC) [000161] --CXG+------ * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [000159] ---X-+------ arg1 in rdx +--* ARR_LENGTH int [000158] -----+------ | \--* LCL_VAR ref V04 loc0 [000157] -----+------ this in rcx +--* LCL_VAR ref V00 this [000160] -----+------ arg2 in r8 \--* CNS_INT int 1 ------------ BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} ***** BB58 STMT00147 (IL ???... ???) [000810] -----+------ * RETURN int [000482] -----+------ \--* CNS_INT int 1 ------------ BB59 [008..00E) (throw), preds={BB01} succs={} ***** BB59 STMT00086 (IL 0x008...0x009) [000533] --CXG+------ * CALL void System.ThrowHelper.ThrowArgumentNullException [000532] -----+------ arg0 in rcx \--* CNS_INT int 4 ------------ BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} ***** BB60 STMT00073 (IL 0x14F...0x150) [000444] -A-X-+------ * ASG long [000443] D----+-N---- +--* LCL_VAR long V26 tmp12 [000442] #--X-+------ \--* IND long [000441] !----+------ \--* LCL_VAR ref V00 this ***** BB60 STMT00074 (IL ???... ???) [000454] -A---+------ * ASG ref [000453] D----+-N---- +--* LCL_VAR ref V27 tmp13 [000439] -----+------ \--* LCL_VAR ref V01 arg1 ***** BB60 STMT00155 (IL ???... ???) [001158] ------------ * JTRUE void [000460] J----+-N---- \--* EQ int [000456] n----+------ +--* IND long [000452] -----+------ | \--* ADD long [000450] #----+------ | +--* IND long [000449] #----+------ | | \--* IND long [000448] -----+------ | | \--* ADD long [000446] -----+------ | | +--* LCL_VAR long V26 tmp12 [000447] -----+------ | | \--* CNS_INT long 56 [000451] -----+------ | \--* CNS_INT long 56 [000459] -----+------ \--* CNS_INT long 0 ------------ BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} ***** BB61 STMT00156 (IL ???... ???) [001160] -A---------- * ASG long [001159] D------N---- +--* LCL_VAR long V28 tmp14 [000461] n----+?----- \--* IND long [000462] -----+?----- \--* ADD long [000463] #----+?----- +--* IND long [000464] #----+?----- | \--* IND long [000465] -----+?----- | \--* ADD long [000466] -----+?----- | +--* LCL_VAR long V26 tmp12 [000467] -----+?----- | \--* CNS_INT long 56 [000468] -----+?----- \--* CNS_INT long 56 ------------ BB62 [???..???), preds={BB60} succs={BB63} ***** BB62 STMT00157 (IL ???... ???) [001162] -AC-G------- * ASG long [001161] D------N---- +--* LCL_VAR long V28 tmp14 [000458] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000445] -----+?----- arg0 in rcx +--* LCL_VAR long V26 tmp12 [000457] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB63 [???..157) (throw), preds={BB61,BB62} succs={} ***** BB63 STMT00076 (IL ???... ???) [000440] --CXG+------ * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000473] -----+------ arg0 in rcx +--* LCL_VAR long V28 tmp14 [000455] -----+------ arg1 in rdx \--* LCL_VAR ref V01 arg1 ------------ BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} ***** BB64 STMT00053 (IL 0x1BC...0x1BD) [000299] -A-X-+------ * ASG long [000298] D----+-N---- +--* LCL_VAR long V21 tmp7 [000297] #--X-+------ \--* IND long [000296] !----+------ \--* LCL_VAR ref V00 this ***** BB64 STMT00054 (IL ???... ???) [000309] -A---+------ * ASG ref [000308] D----+-N---- +--* LCL_VAR ref V22 tmp8 [000294] -----+------ \--* LCL_VAR ref V01 arg1 ***** BB64 STMT00161 (IL ???... ???) [001168] ------------ * JTRUE void [000315] J----+-N---- \--* EQ int [000311] n----+------ +--* IND long [000307] -----+------ | \--* ADD long [000305] #----+------ | +--* IND long [000304] #----+------ | | \--* IND long [000303] -----+------ | | \--* ADD long [000301] -----+------ | | +--* LCL_VAR long V21 tmp7 [000302] -----+------ | | \--* CNS_INT long 56 [000306] -----+------ | \--* CNS_INT long 56 [000314] -----+------ \--* CNS_INT long 0 ------------ BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} ***** BB65 STMT00162 (IL ???... ???) [001170] -A---------- * ASG long [001169] D------N---- +--* LCL_VAR long V23 tmp9 [000316] n----+?----- \--* IND long [000317] -----+?----- \--* ADD long [000318] #----+?----- +--* IND long [000319] #----+?----- | \--* IND long [000320] -----+?----- | \--* ADD long [000321] -----+?----- | +--* LCL_VAR long V21 tmp7 [000322] -----+?----- | \--* CNS_INT long 56 [000323] -----+?----- \--* CNS_INT long 56 ------------ BB66 [???..???), preds={BB64} succs={BB67} ***** BB66 STMT00163 (IL ???... ???) [001172] -AC-G------- * ASG long [001171] D------N---- +--* LCL_VAR long V23 tmp9 [000313] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000300] -----+?----- arg0 in rcx +--* LCL_VAR long V21 tmp7 [000312] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} ***** BB67 STMT00056 (IL ???... ???) [000295] --CXG+------ * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000328] -----+------ arg0 in rcx +--* LCL_VAR long V23 tmp9 [000310] -----+------ arg1 in rdx \--* LCL_VAR ref V01 arg1 ------------ BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} ***** BB68 STMT00043 (IL 0x1DD...0x1E2) [000233] --CXG+------ * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported ------------------------------------------------------------------------------------------------------------------- Considering loop L00 to clone for optimizations. Loop cloning: rejecting loop L00. No LPFLG_ITER flag. ------------------------------------------------------------ No clonable loops *************** Finishing PHASE Clone loops *************** Starting PHASE Unroll loops *************** In optUnrollLoops() *************** In fgDebugCheckBBlist *************** Finishing PHASE Unroll loops *************** Starting PHASE Mark local vars *************** In lvaMarkLocalVars() *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** *** marking local variables in block BB01 (weight=1 ) STMT00000 (IL 0x000...0x006) [000003] -----+------ * JTRUE void [000002] J----+-N---- \--* EQ int [000000] -----+------ +--* LCL_VAR ref V01 arg1 [000001] -----+------ \--* CNS_INT ref null New refCnts for V01: refCnt = 1, refCntWtd = 1 *** marking local variables in block BB02 (weight=1 ) STMT00001 (IL 0x00E...0x014) [000008] ---XG+------ * JTRUE void [000007] J--XG+-N---- \--* NE int [000005] ---XG+------ +--* IND ref [000814] -----+------ | \--* ADD byref [000004] -----+------ | +--* LCL_VAR ref V00 this [000813] -----+------ | \--* CNS_INT long 8 field offset Fseq[_buckets] [000006] -----+------ \--* CNS_INT ref null New refCnts for V00: refCnt = 1, refCntWtd = 1 *** marking local variables in block BB03 (weight=0.50) STMT00085 (IL ???... ???) [000528] --CXG+------ * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize [000526] -----+------ this in rcx +--* LCL_VAR ref V00 this [000527] -----+------ arg1 in rdx \--* CNS_INT int 0 New refCnts for V00: refCnt = 2, refCntWtd = 1.50 *** marking local variables in block BB04 (weight=1 ) STMT00088 (IL 0x01E... ???) [000544] -A-XG+------ * ASG bool [000543] D----+-N---- +--* LCL_VAR int V33 tmp19 [000012] N--XG+------ \--* NE int [000010] ---XG+------ +--* IND ref [000818] -----+------ | \--* ADD byref [000009] -----+------ | +--* LCL_VAR ref V00 this [000817] -----+------ | \--* CNS_INT long 8 field offset Fseq[_buckets] [000011] -----+------ \--* CNS_INT ref null New refCnts for V33: refCnt = 1, refCntWtd = 2 EH Var V33 needs explicit zero init. Disqualified as a register candidate. New refCnts for V00: refCnt = 3, refCntWtd = 2.50 STMT00091 (IL 0x01E... ???) [000554] -A--G+------ * ASG ref [000553] D----+-N---- +--* LCL_VAR ref V34 tmp20 [000538] #---G+------ \--* IND ref [000537] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] New refCnts for V34: refCnt = 1, refCntWtd = 2 Marking EH Var V34 as a register candidate. STMT00092 (IL 0x01E... ???) [000556] -A--G+------ * ASG ref [000555] D----+-N---- +--* LCL_VAR ref V35 tmp21 [000540] #---G+------ \--* IND ref [000539] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] New refCnts for V35: refCnt = 1, refCntWtd = 2 Marking EH Var V35 as a register candidate. STMT00089 (IL 0x01E... ???) [000549] -----+------ * JTRUE void [000548] J----+-N---- \--* NE int [000546] -----+------ +--* LCL_VAR int V33 tmp19 [000547] -----+------ \--* CNS_INT int 0 New refCnts for V33: refCnt = 2, refCntWtd = 4 *** marking local variables in block BB05 (weight=0.50) STMT00090 (IL 0x01E... ???) [000552] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000550] -----+------ arg0 in rcx +--* LCL_VAR ref V34 tmp20 [000551] -----+------ arg1 in rdx \--* LCL_VAR ref V35 tmp21 New refCnts for V34: refCnt = 2, refCntWtd = 3 New refCnts for V35: refCnt = 2, refCntWtd = 3 *** marking local variables in block BB06 (weight=1 ) STMT00003 (IL 0x02C... ???) [000018] -A-XG+------ * ASG ref [000017] D----+-N---- +--* LCL_VAR ref V04 loc0 [000016] ---XG+------ \--* IND ref [000822] -----+------ \--* ADD byref [000015] -----+------ +--* LCL_VAR ref V00 this [000821] -----+------ \--* CNS_INT long 16 field offset Fseq[_entries] New refCnts for V04: refCnt = 1, refCntWtd = 1 Marking EH Var V04 as a register candidate. New refCnts for V00: refCnt = 4, refCntWtd = 3.50 STMT00094 (IL 0x033... ???) [000566] -A---+------ * ASG bool [000565] D----+-N---- +--* LCL_VAR int V36 tmp22 [000021] N----+------ \--* NE int [000019] -----+------ +--* LCL_VAR ref V04 loc0 [000020] -----+------ \--* CNS_INT ref null New refCnts for V36: refCnt = 1, refCntWtd = 2 EH Var V36 needs explicit zero init. Disqualified as a register candidate. New refCnts for V04: refCnt = 2, refCntWtd = 2 STMT00097 (IL 0x033... ???) [000576] -A--G+------ * ASG ref [000575] D----+-N---- +--* LCL_VAR ref V37 tmp23 [000562] #---G+------ \--* IND ref [000561] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] New refCnts for V37: refCnt = 1, refCntWtd = 2 Marking EH Var V37 as a register candidate. STMT00095 (IL 0x033... ???) [000571] -----+------ * JTRUE void [000570] J----+-N---- \--* NE int [000568] -----+------ +--* LCL_VAR int V36 tmp22 [000569] -----+------ \--* CNS_INT int 0 New refCnts for V36: refCnt = 2, refCntWtd = 4 *** marking local variables in block BB07 (weight=0.50) STMT00096 (IL 0x033... ???) [000574] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000824] #---G+------ arg0 in rcx +--* IND ref [000823] H----+------ | \--* CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" [000573] -----+------ arg1 in rdx \--* LCL_VAR ref V37 tmp23 New refCnts for V37: refCnt = 2, refCntWtd = 3 *** marking local variables in block BB08 (weight=1 ) STMT00005 (IL 0x041... ???) [000028] -A-XG+------ * ASG ref [000027] D----+-N---- +--* LCL_VAR ref V05 loc1 [000026] ---XG+------ \--* IND ref [000828] -----+------ \--* ADD byref [000025] -----+------ +--* LCL_VAR ref V00 this [000827] -----+------ \--* CNS_INT long 24 field offset Fseq[_comparer] New refCnts for V05: refCnt = 1, refCntWtd = 1 Marking EH Var V05 as a register candidate. New refCnts for V00: refCnt = 5, refCntWtd = 4.50 STMT00006 (IL 0x048...0x049) [000032] -----+------ * JTRUE void [000031] J----+-N---- \--* EQ int [000029] -----+------ +--* LCL_VAR ref V05 loc1 [000030] -----+------ \--* CNS_INT ref null New refCnts for V05: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB09 (weight=0.50) STMT00079 (IL 0x04B...0x052) [000489] -A-X-+------ * ASG long [000488] D----+-N---- +--* LCL_VAR long V29 tmp15 [000487] #--X-+------ \--* IND long [000486] !----+------ \--* LCL_VAR ref V00 this New refCnts for V29: refCnt = 1, refCntWtd = 1 EH Var V29 needs explicit zero init. Disqualified as a register candidate. -- generic context in use at [000486] New refCnts for V00: refCnt = 6, refCntWtd = 5 STMT00080 (IL ???... ???) [000499] -A---+------ * ASG ref [000498] D----+-N---- +--* LCL_VAR ref V30 tmp16 [000485] -----+------ \--* LCL_VAR ref V01 arg1 New refCnts for V30: refCnt = 1, refCntWtd = 1 Marking EH Var V30 as a register candidate. New refCnts for V01: refCnt = 2, refCntWtd = 1.50 STMT00149 (IL ???... ???) [001148] ------------ * JTRUE void [000505] J----+-N---- \--* EQ int [000501] n----+------ +--* IND long [000497] -----+------ | \--* ADD long [000495] #----+------ | +--* IND long [000494] #----+------ | | \--* IND long [000493] -----+------ | | \--* ADD long [000491] -----+------ | | +--* LCL_VAR long V29 tmp15 [000492] -----+------ | | \--* CNS_INT long 56 [000496] -----+------ | \--* CNS_INT long 64 [000504] -----+------ \--* CNS_INT long 0 New refCnts for V29: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB10 (weight=0.25) STMT00150 (IL ???... ???) [001150] -A---------- * ASG long [001149] D------N---- +--* LCL_VAR long V31 tmp17 [000506] n----+?----- \--* IND long [000507] -----+?----- \--* ADD long [000508] #----+?----- +--* IND long [000509] #----+?----- | \--* IND long [000510] -----+?----- | \--* ADD long [000511] -----+?----- | +--* LCL_VAR long V29 tmp15 [000512] -----+?----- | \--* CNS_INT long 56 [000513] -----+?----- \--* CNS_INT long 64 New refCnts for V31: refCnt = 1, refCntWtd = 0.50 EH Var V31 needs explicit zero init. Disqualified as a register candidate. New refCnts for V29: refCnt = 3, refCntWtd = 2.50 *** marking local variables in block BB11 (weight=0.25) STMT00151 (IL ???... ???) [001152] -AC-G------- * ASG long [001151] D------N---- +--* LCL_VAR long V31 tmp17 [000503] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000490] -----+?----- arg0 in rcx +--* LCL_VAR long V29 tmp15 [000502] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr New refCnts for V31: refCnt = 2, refCntWtd = 1 New refCnts for V29: refCnt = 4, refCntWtd = 3 *** marking local variables in block BB12 (weight=0.50) STMT00082 (IL ???... ???) [000520] -A---+------ * ASG long [000519] D----+-N---- +--* LCL_VAR long V32 tmp18 [000518] -----+------ \--* LCL_VAR long V31 tmp17 New refCnts for V32: refCnt = 1, refCntWtd = 1 EH Var V32 needs explicit zero init. Disqualified as a register candidate. New refCnts for V31: refCnt = 3, refCntWtd = 2 STMT00083 (IL ???... ???) [000524] -ACXG+------ * ASG int [000523] D----+-N---- +--* LCL_VAR int V15 tmp1 [000522] --CXG+------ \--* CALL ind stub int [000521] -----+------ calli tgt \--* LCL_VAR long V31 tmp17 [000484] -----+------ this in rcx +--* LCL_VAR ref V05 loc1 [000831] -----+------ arg1 in r11 +--* LCL_VAR long V31 tmp17 r11 REG r11 [000500] -----+------ arg2 in rdx \--* LCL_VAR ref V01 arg1 New refCnts for V15: refCnt = 1, refCntWtd = 0.50 EH Var V15 needs explicit zero init. Disqualified as a register candidate. New refCnts for V05: refCnt = 3, refCntWtd = 2.50 New refCnts for V31: refCnt = 4, refCntWtd = 3 New refCnts for V01: refCnt = 3, refCntWtd = 2 New refCnts for V31: refCnt = 5, refCntWtd = 4 *** marking local variables in block BB13 (weight=0.50) STMT00007 (IL 0x054...0x05C) [000038] -ACXG+------ * ASG int [000037] D----+-N---- +--* LCL_VAR int V15 tmp1 [000035] --CXG+------ \--* CALLV vt-ind int System.Object.GetHashCode [000843] n--X-+------ control expr \--* IND long [000842] ---X-+------ \--* ADD long [000840] #--X-+------ +--* IND long [000839] ---X-+------ | \--* ADD long [000837] #--X-+------ | +--* IND long [000836] -----+------ | | \--* LCL_VAR ref V01 arg1 [000838] -----+------ | \--* CNS_INT int 72 [000841] -----+------ \--* CNS_INT int 24 [000033] -----+------ this in rcx \--* LCL_VAR ref V01 arg1 New refCnts for V15: refCnt = 2, refCntWtd = 1 New refCnts for V01: refCnt = 4, refCntWtd = 2.50 New refCnts for V01: refCnt = 5, refCntWtd = 3 *** marking local variables in block BB14 (weight=1 ) STMT00008 (IL ???...0x061) [000042] -A---+------ * ASG int [000041] D----+-N---- +--* LCL_VAR int V06 loc2 [000040] -----+------ \--* LCL_VAR int V15 tmp1 New refCnts for V06: refCnt = 1, refCntWtd = 1 EH Var V06 needs explicit zero init. Disqualified as a register candidate. New refCnts for V15: refCnt = 3, refCntWtd = 2 STMT00009 (IL 0x062...0x063) [000045] -A---+------ * ASG int [000044] D----+-N---- +--* LCL_VAR int V07 loc3 [000043] -----+------ \--* CNS_INT int 0 New refCnts for V07: refCnt = 1, refCntWtd = 1 EH Var V07 needs explicit zero init. Disqualified as a register candidate. STMT00098 (IL 0x064... ???) [000580] -A-XG+------ * ASG ref [000579] D----+-N---- +--* LCL_VAR ref V39 tmp25 [000578] ---XG+------ \--* IND ref [000845] -----+------ \--* ADD byref [000046] -----+------ +--* LCL_VAR ref V00 this [000844] -----+------ \--* CNS_INT long 8 field offset Fseq[_buckets] New refCnts for V39: refCnt = 1, refCntWtd = 1 Marking EH Var V39 as a register candidate. New refCnts for V00: refCnt = 7, refCntWtd = 6 STMT00105 (IL 0x064... ???) [000629] -A-X-+------ * ASG int [000628] D----+-N---- +--* LCL_VAR int V40 tmp26 [000583] ---X-+------ \--* ARR_LENGTH int [000582] -----+------ \--* LCL_VAR ref V39 tmp25 New refCnts for V40: refCnt = 1, refCntWtd = 2 EH Var V40 needs explicit zero init. Disqualified as a register candidate. New refCnts for V39: refCnt = 2, refCntWtd = 2 STMT00106 (IL 0x064... ???) [000631] -A-XG+------ * ASG long [000630] D----+-N---- +--* LCL_VAR long V41 tmp27 [000585] ---XG+------ \--* IND long [000847] -----+------ \--* ADD byref [000584] -----+------ +--* LCL_VAR ref V00 this [000846] -----+------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] New refCnts for V41: refCnt = 1, refCntWtd = 2 EH Var V41 needs explicit zero init. Disqualified as a register candidate. New refCnts for V00: refCnt = 8, refCntWtd = 7 STMT00108 (IL 0x064... ???) [000642] -A---+------ * ASG bool [000641] D----+-N---- +--* LCL_VAR int V43 tmp29 [000599] N----+---U-- \--* LE int [000597] -----+------ +--* LCL_VAR int V40 tmp26 [000598] -----+------ \--* CNS_INT int 0x7FFFFFFF New refCnts for V43: refCnt = 1, refCntWtd = 2 EH Var V43 needs explicit zero init. Disqualified as a register candidate. New refCnts for V40: refCnt = 2, refCntWtd = 4 STMT00111 (IL 0x064... ???) [000652] -A--G+------ * ASG ref [000651] D----+-N---- +--* LCL_VAR ref V44 tmp30 [000636] #---G+------ \--* IND ref [000635] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] New refCnts for V44: refCnt = 1, refCntWtd = 2 Marking EH Var V44 as a register candidate. STMT00112 (IL 0x064... ???) [000654] -A--G+------ * ASG ref [000653] D----+-N---- +--* LCL_VAR ref V45 tmp31 [000638] #---G+------ \--* IND ref [000637] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] New refCnts for V45: refCnt = 1, refCntWtd = 2 Marking EH Var V45 as a register candidate. STMT00109 (IL 0x064... ???) [000647] -----+------ * JTRUE void [000646] J----+-N---- \--* NE int [000644] -----+------ +--* LCL_VAR int V43 tmp29 [000645] -----+------ \--* CNS_INT int 0 New refCnts for V43: refCnt = 2, refCntWtd = 4 *** marking local variables in block BB15 (weight=0.50) STMT00110 (IL 0x064... ???) [000650] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000648] -----+------ arg0 in rcx +--* LCL_VAR ref V44 tmp30 [000649] -----+------ arg1 in rdx \--* LCL_VAR ref V45 tmp31 New refCnts for V44: refCnt = 2, refCntWtd = 3 New refCnts for V45: refCnt = 2, refCntWtd = 3 *** marking local variables in block BB16 (weight=1 ) STMT00103 (IL 0x064... ???) [000619] -A---+------ * ASG int [000618] D----+-N---- +--* LCL_VAR int V42 tmp28 [000617] -----+------ \--* CAST int <- uint <- long [000616] -----+------ \--* RSZ long [000614] -----+------ +--* MUL long [000611] -----+------ | +--* ADD long [000608] -----+------ | | +--* RSZ long [000606] -----+------ | | | +--* MUL long [000604] -----+------ | | | | +--* LCL_VAR long V41 tmp27 [000605] -----+---U-- | | | | \--* CAST long <- ulong <- uint [000047] -----+------ | | | | \--* LCL_VAR int V06 loc2 [000607] -----+------ | | | \--* CNS_INT int 32 [000610] -----+------ | | \--* CNS_INT long 1 [000613] -----+---U-- | \--* CAST long <- ulong <- uint [000612] -----+------ | \--* LCL_VAR int V40 tmp26 [000615] -----+------ \--* CNS_INT int 32 New refCnts for V42: refCnt = 1, refCntWtd = 1 EH Var V42 needs explicit zero init. Disqualified as a register candidate. New refCnts for V41: refCnt = 2, refCntWtd = 4 New refCnts for V06: refCnt = 2, refCntWtd = 2 New refCnts for V40: refCnt = 3, refCntWtd = 6 STMT00114 (IL 0x064... ???) [000665] -A-X-+------ * ASG bool [000664] D----+-N---- +--* LCL_VAR int V46 tmp32 [000624] ---X-+------ \--* EQ int [000620] -----+------ +--* LCL_VAR int V42 tmp28 [000623] ---X-+------ \--* UMOD int [000621] -----+------ +--* LCL_VAR int V06 loc2 [000622] -----+------ \--* LCL_VAR int V40 tmp26 New refCnts for V46: refCnt = 1, refCntWtd = 2 EH Var V46 needs explicit zero init. Disqualified as a register candidate. New refCnts for V42: refCnt = 2, refCntWtd = 2 New refCnts for V06: refCnt = 3, refCntWtd = 3 New refCnts for V40: refCnt = 4, refCntWtd = 8 STMT00117 (IL 0x064... ???) [000675] -A--G+------ * ASG ref [000674] D----+-N---- +--* LCL_VAR ref V47 tmp33 [000659] #---G+------ \--* IND ref [000658] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] New refCnts for V47: refCnt = 1, refCntWtd = 2 Marking EH Var V47 as a register candidate. STMT00118 (IL 0x064... ???) [000677] -A--G+------ * ASG ref [000676] D----+-N---- +--* LCL_VAR ref V48 tmp34 [000661] #---G+------ \--* IND ref [000660] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] New refCnts for V48: refCnt = 1, refCntWtd = 2 Marking EH Var V48 as a register candidate. STMT00115 (IL 0x064... ???) [000670] -----+------ * JTRUE void [000669] J----+-N---- \--* NE int [000667] -----+------ +--* LCL_VAR int V46 tmp32 [000668] -----+------ \--* CNS_INT int 0 New refCnts for V46: refCnt = 2, refCntWtd = 4 *** marking local variables in block BB17 (weight=0.50) STMT00116 (IL 0x064... ???) [000673] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000671] -----+------ arg0 in rcx +--* LCL_VAR ref V47 tmp33 [000672] -----+------ arg1 in rdx \--* LCL_VAR ref V48 tmp34 New refCnts for V47: refCnt = 2, refCntWtd = 3 New refCnts for V48: refCnt = 2, refCntWtd = 3 *** marking local variables in block BB18 (weight=1 ) STMT00100 (IL 0x064... ???) [000591] -A-XG+------ * ASG byref [000590] D----+-N---- +--* LCL_VAR byref V38 tmp24 [000862] ---XG+------ \--* COMMA byref [000855] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000627] -----+------ | +--* LCL_VAR int V42 tmp28 [000854] ---X-+------ | \--* ARR_LENGTH int [000581] -----+------ | \--* LCL_VAR ref V39 tmp25 [000863] ----G------- \--* ADDR byref [000588] a---G+-N---- \--* IND int [000861] -----+------ \--* ADD byref [000852] -----+------ +--* LCL_VAR ref V39 tmp25 [000860] -----+------ \--* ADD long [000858] -----+------ +--* LSH long [000856] -----+------ | +--* CAST long <- int [000853] i----+------ | | \--* LCL_VAR int V42 tmp28 [000857] -----+-N---- | \--* CNS_INT long 2 [000859] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] New refCnts for V38: refCnt = 1, refCntWtd = 1 Marking EH Var V38 as a register candidate. New refCnts for V42: refCnt = 3, refCntWtd = 3 New refCnts for V39: refCnt = 3, refCntWtd = 3 New refCnts for V39: refCnt = 4, refCntWtd = 4 New refCnts for V42: refCnt = 4, refCntWtd = 4 STMT00101 (IL 0x064... ???) [000595] -A---+------ * ASG ref [000594] D----+-N---- +--* LCL_VAR ref V39 tmp25 [000593] -----+------ \--* CNS_INT ref null New refCnts for V39: refCnt = 5, refCntWtd = 5 EH Var V39 has multiple definitions. Disqualified as a register candidate. STMT00011 (IL ???... ???) [000051] -A---+------ * ASG byref [000050] D----+-N---- +--* LCL_VAR byref V08 loc4 [000592] -----+------ \--* LCL_VAR byref V38 tmp24 New refCnts for V08: refCnt = 1, refCntWtd = 1 Marking EH Var V08 as a register candidate. New refCnts for V38: refCnt = 2, refCntWtd = 2 STMT00012 (IL 0x06D...0x072) [000057] -A-XG+------ * ASG int [000056] D----+-N---- +--* LCL_VAR int V09 loc5 [000055] ---XG+------ \--* ADD int [000053] *--XG+------ +--* IND int [000052] -----+------ | \--* LCL_VAR byref V38 tmp24 [000054] -----+------ \--* CNS_INT int -1 New refCnts for V09: refCnt = 1, refCntWtd = 1 EH Var V09 needs explicit zero init. Disqualified as a register candidate. New refCnts for V38: refCnt = 3, refCntWtd = 3 STMT00013 (IL 0x074...0x075) [000061] -----+------ * JTRUE void [000060] J----+-N---- \--* NE int [000058] -----+------ +--* LCL_VAR ref V05 loc1 [000059] -----+------ \--* CNS_INT ref null New refCnts for V05: refCnt = 4, refCntWtd = 3.50 *** marking local variables in block BB19 (weight=0.50) STMT00059 (IL 0x0FF...0x104) [000356] -A-X-+------ * ASG long [000355] D----+-N---- +--* LCL_VAR long V24 tmp10 [000354] #--X-+------ \--* IND long [000353] !----+------ \--* LCL_VAR ref V00 this New refCnts for V24: refCnt = 1, refCntWtd = 1 EH Var V24 needs explicit zero init. Disqualified as a register candidate. New refCnts for V00: refCnt = 9, refCntWtd = 7.50 STMT00152 (IL ???... ???) [001153] ------------ * JTRUE void [000369] J----+-N---- \--* EQ int [000365] n----+------ +--* IND long [000364] -----+------ | \--* ADD long [000362] #----+------ | +--* IND long [000361] #----+------ | | \--* IND long [000360] -----+------ | | \--* ADD long [000358] -----+------ | | +--* LCL_VAR long V24 tmp10 [000359] -----+------ | | \--* CNS_INT long 56 [000363] -----+------ | \--* CNS_INT long 32 [000368] -----+------ \--* CNS_INT long 0 New refCnts for V24: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB20 (weight=0.25) STMT00153 (IL ???... ???) [001155] -A---------- * ASG long [001154] D------N---- +--* LCL_VAR long V25 tmp11 [000370] n----+?----- \--* IND long [000371] -----+?----- \--* ADD long [000372] #----+?----- +--* IND long [000373] #----+?----- | \--* IND long [000374] -----+?----- | \--* ADD long [000375] -----+?----- | +--* LCL_VAR long V24 tmp10 [000376] -----+?----- | \--* CNS_INT long 56 [000377] -----+?----- \--* CNS_INT long 32 New refCnts for V25: refCnt = 1, refCntWtd = 0.50 EH Var V25 needs explicit zero init. Disqualified as a register candidate. New refCnts for V24: refCnt = 3, refCntWtd = 2.50 *** marking local variables in block BB21 (weight=0.25) STMT00154 (IL ???... ???) [001157] -AC-G------- * ASG long [001156] D------N---- +--* LCL_VAR long V25 tmp11 [000367] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000357] -----+?----- arg0 in rcx +--* LCL_VAR long V24 tmp10 [000366] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr New refCnts for V25: refCnt = 2, refCntWtd = 1 New refCnts for V24: refCnt = 4, refCntWtd = 3 *** marking local variables in block BB22 (weight=0.50) STMT00062 (IL ???... ???) [000386] -ACXG+------ * ASG ref [000385] D----+-N---- +--* LCL_VAR ref V12 loc8 [000352] --CXG+------ \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default [000382] -----+------ arg0 in rcx \--* LCL_VAR long V25 tmp11 New refCnts for V12: refCnt = 1, refCntWtd = 0.50 Marking EH Var V12 as a register candidate. New refCnts for V25: refCnt = 3, refCntWtd = 2 *** marking local variables in block BB23 (weight=4 ) STMT00063 (IL 0x106...0x10B) [000391] ---X-+------ * JTRUE void [000390] N--X-+-N-U-- \--* GE int [000387] -----+------ +--* LCL_VAR int V09 loc5 [000389] ---X-+------ \--* ARR_LENGTH int [000388] -----+------ \--* LCL_VAR ref V04 loc0 New refCnts for V09: refCnt = 2, refCntWtd = 5 New refCnts for V04: refCnt = 3, refCntWtd = 6 *** marking local variables in block BB24 (weight=4 ) STMT00064 (IL 0x110...0x11E) [000399] ---XG+------ * JTRUE void [000398] N--XG+-N-U-- \--* NE int [000396] *--XG+------ +--* IND int [000868] ---XG+------ | \--* ADD byref [000879] ---XG+------ | +--* COMMA byref [000872] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000393] -----+------ | | | +--* LCL_VAR int V09 loc5 [000871] ---X-+------ | | | \--* ARR_LENGTH int [000392] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000882] ----G------- | | \--* ADDR byref [000394] a---G+-N---- | | \--* IND struct [000878] -----+------ | | \--* ADD byref [000869] -----+------ | | +--* LCL_VAR ref V04 loc0 [000877] -----+------ | | \--* ADD long [000875] -----+------ | | +--* LSH long [000881] -----+------ | | | +--* MUL long [000873] -----+------ | | | | +--* CAST long <- int [000870] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000880] ------------ | | | | \--* CNS_INT long 3 [000874] -----+-N---- | | | \--* CNS_INT long 3 [000876] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000867] -----+------ | \--* CNS_INT long 16 field offset Fseq[hashCode] [000397] -----+------ \--* LCL_VAR int V06 loc2 New refCnts for V09: refCnt = 3, refCntWtd = 9 New refCnts for V04: refCnt = 4, refCntWtd = 10 New refCnts for V04: refCnt = 5, refCntWtd = 14 New refCnts for V09: refCnt = 4, refCntWtd = 13 New refCnts for V06: refCnt = 4, refCntWtd = 7 *** marking local variables in block BB25 (weight=2 ) STMT00069 (IL 0x120...0x135) [000428] --CXG+------ * JTRUE void [000427] J-CXG+-N---- \--* NE int [000425] --CXG+------ +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals [000908] n--X-+------ control expr | \--* IND long [000907] ---X-+------ | \--* ADD long [000905] #--X-+------ | +--* IND long [000904] ---X-+------ | | \--* ADD long [000902] #--X-+------ | | +--* IND long [000901] -----+------ | | | \--* LCL_VAR ref V12 loc8 [000903] -----+------ | | \--* CNS_INT int 72 [000906] -----+------ | \--* CNS_INT int 32 [000893] ---XG+------ arg1 in rdx | +--* COMMA ref [000886] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000420] -----+------ | | | +--* LCL_VAR int V09 loc5 [000885] ---X-+------ | | | \--* ARR_LENGTH int [000419] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000897] *---G+------ | | \--* IND ref [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] [000421] a---G+-N---- | | \--* IND struct [000892] -----+------ | | \--* ADD byref [000883] -----+------ | | +--* LCL_VAR ref V04 loc0 [000891] -----+------ | | \--* ADD long [000889] -----+------ | | +--* LSH long [000895] -----+------ | | | +--* MUL long [000887] -----+------ | | | | +--* CAST long <- int [000884] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000894] ------------ | | | | \--* CNS_INT long 3 [000888] -----+-N---- | | | \--* CNS_INT long 3 [000890] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000418] -----+------ this in rcx | +--* LCL_VAR ref V12 loc8 [000424] -----+------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 [000426] -----+------ \--* CNS_INT int 0 New refCnts for V09: refCnt = 5, refCntWtd = 15 New refCnts for V04: refCnt = 6, refCntWtd = 16 New refCnts for V04: refCnt = 7, refCntWtd = 18 New refCnts for V09: refCnt = 6, refCntWtd = 17 New refCnts for V12: refCnt = 2, refCntWtd = 2.50 New refCnts for V01: refCnt = 6, refCntWtd = 5 New refCnts for V12: refCnt = 3, refCntWtd = 4.50 *** marking local variables in block BB26 (weight=4 ) STMT00065 (IL 0x157...0x164) [000406] -A-XG+------ * ASG int [000405] D----+-N---- +--* LCL_VAR int V09 loc5 [000404] *--XG+------ \--* IND int [000932] ---XG+------ \--* ADD byref [000943] ---XG+------ +--* COMMA byref [000936] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000401] -----+------ | | +--* LCL_VAR int V09 loc5 [000935] ---X-+------ | | \--* ARR_LENGTH int [000400] -----+------ | | \--* LCL_VAR ref V04 loc0 [000946] ----G------- | \--* ADDR byref [000402] a---G+-N---- | \--* IND struct [000942] -----+------ | \--* ADD byref [000933] -----+------ | +--* LCL_VAR ref V04 loc0 [000941] -----+------ | \--* ADD long [000939] -----+------ | +--* LSH long [000945] -----+------ | | +--* MUL long [000937] -----+------ | | | +--* CAST long <- int [000934] i----+------ | | | | \--* LCL_VAR int V09 loc5 [000944] ------------ | | | \--* CNS_INT long 3 [000938] -----+-N---- | | \--* CNS_INT long 3 [000940] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [000931] -----+------ \--* CNS_INT long 20 field offset Fseq[next] New refCnts for V09: refCnt = 7, refCntWtd = 21 New refCnts for V09: refCnt = 8, refCntWtd = 25 New refCnts for V04: refCnt = 8, refCntWtd = 22 New refCnts for V04: refCnt = 9, refCntWtd = 26 New refCnts for V09: refCnt = 9, refCntWtd = 29 STMT00066 (IL 0x166...0x169) [000411] -A---+------ * ASG int [000410] D----+-N---- +--* LCL_VAR int V07 loc3 [000409] -----+------ \--* ADD int [000407] -----+------ +--* LCL_VAR int V07 loc3 [000408] -----+------ \--* CNS_INT int 1 New refCnts for V07: refCnt = 2, refCntWtd = 5 New refCnts for V07: refCnt = 3, refCntWtd = 9 STMT00067 (IL 0x16A...0x16E) [000416] ---X-+------ * JTRUE void [000415] N--X-+-N-U-- \--* GT int [000412] -----+------ +--* LCL_VAR int V07 loc3 [000414] ---X-+------ \--* ARR_LENGTH int [000413] -----+------ \--* LCL_VAR ref V04 loc0 New refCnts for V07: refCnt = 4, refCntWtd = 13 New refCnts for V04: refCnt = 10, refCntWtd = 30 *** marking local variables in block BB27 (weight=4 ) *** marking local variables in block BB28 (weight=0.50) STMT00070 (IL 0x137...0x139) [000432] -----+------ * JTRUE void [000431] N----+-N-U-- \--* NE int [000909] -----+------ +--* CAST int <- ubyte <- int [000429] -----+------ | \--* LCL_VAR int V03 arg3 [000430] -----+------ \--* CNS_INT int 1 New refCnts for V03: refCnt = 1, refCntWtd = 0.50 *** marking local variables in block BB29 (weight=0.50) STMT00077 (IL 0x13B...0x144) [000481] -A-XG+------ * ASG ref [000480] *--XG+-N---- +--* IND ref [000911] ---XG+------ | \--* ADD byref [000922] ---XG+------ | +--* COMMA byref [000915] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000476] -----+------ | | | +--* LCL_VAR int V09 loc5 [000914] ---X-+------ | | | \--* ARR_LENGTH int [000475] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000925] ----G------- | | \--* ADDR byref [000477] a---G+-N---- | | \--* IND struct [000921] -----+------ | | \--* ADD byref [000912] -----+------ | | +--* LCL_VAR ref V04 loc0 [000920] -----+------ | | \--* ADD long [000918] -----+------ | | +--* LSH long [000924] -----+------ | | | +--* MUL long [000916] -----+------ | | | | +--* CAST long <- int [000913] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000923] ------------ | | | | \--* CNS_INT long 3 [000917] -----+-N---- | | | \--* CNS_INT long 3 [000919] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000910] -----+------ | \--* CNS_INT long 8 field offset Fseq[value] [000479] -----+------ \--* LCL_VAR ref V02 arg2 New refCnts for V09: refCnt = 10, refCntWtd = 29.50 New refCnts for V04: refCnt = 11, refCntWtd = 30.50 New refCnts for V04: refCnt = 12, refCntWtd = 31 New refCnts for V09: refCnt = 11, refCntWtd = 30 New refCnts for V02: refCnt = 1, refCntWtd = 0.50 *** marking local variables in block BB30 (weight=0.50) STMT00071 (IL 0x14B...0x14D) [000436] -----+------ * JTRUE void [000435] N----+-N-U-- \--* EQ int [000926] -----+------ +--* CAST int <- ubyte <- int [000433] -----+------ | \--* LCL_VAR int V03 arg3 [000434] -----+------ \--* CNS_INT int 2 New refCnts for V03: refCnt = 2, refCntWtd = 1 *** marking local variables in block BB31 (weight=0.50) STMT00148 (IL ???... ???) [000811] -----+------ * RETURN int [000437] -----+------ \--* CNS_INT int 0 *** marking local variables in block BB32 (weight=4 ) STMT00014 (IL 0x177...0x17C) ( 11, 9) [000066] ---X-------- * JTRUE void ( 9, 7) [000065] N--X---N-U-- \--* LE int ( 5, 4) [000064] ---X-------- +--* ARR_LENGTH int ( 3, 2) [000063] ------------ | \--* LCL_VAR ref V04 loc0 ( 3, 2) [000062] ------------ \--* LCL_VAR int V09 loc5 New refCnts for V04: refCnt = 13, refCntWtd = 35 New refCnts for V09: refCnt = 12, refCntWtd = 34 *** marking local variables in block BB33 (weight=4 ) STMT00039 (IL 0x17E...0x18C) [000215] ---XG+------ * JTRUE void [000214] N--XG+-N-U-- \--* NE int [000212] *--XG+------ +--* IND int [000948] ---XG+------ | \--* ADD byref [000959] ---XG+------ | +--* COMMA byref [000952] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000209] -----+------ | | | +--* LCL_VAR int V09 loc5 [000951] ---X-+------ | | | \--* ARR_LENGTH int [000208] -----+------ | | | \--* LCL_VAR ref V04 loc0 [000962] ----G------- | | \--* ADDR byref [000210] a---G+-N---- | | \--* IND struct [000958] -----+------ | | \--* ADD byref [000949] -----+------ | | +--* LCL_VAR ref V04 loc0 [000957] -----+------ | | \--* ADD long [000955] -----+------ | | +--* LSH long [000961] -----+------ | | | +--* MUL long [000953] -----+------ | | | | +--* CAST long <- int [000950] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000960] ------------ | | | | \--* CNS_INT long 3 [000954] -----+-N---- | | | \--* CNS_INT long 3 [000956] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000947] -----+------ | \--* CNS_INT long 16 field offset Fseq[hashCode] [000213] -----+------ \--* LCL_VAR int V06 loc2 New refCnts for V09: refCnt = 13, refCntWtd = 38 New refCnts for V04: refCnt = 14, refCntWtd = 39 New refCnts for V04: refCnt = 15, refCntWtd = 43 New refCnts for V09: refCnt = 14, refCntWtd = 42 New refCnts for V06: refCnt = 5, refCntWtd = 11 *** marking local variables in block BB34 (weight=2 ) STMT00045 (IL 0x18E...0x1A2) [000246] -A-XG+------ * ASG ref [000245] D----+-N---- +--* LCL_VAR ref V17 tmp3 [000973] ---XG+------ \--* COMMA ref [000966] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000236] -----+------ | +--* LCL_VAR int V09 loc5 [000965] ---X-+------ | \--* ARR_LENGTH int [000235] -----+------ | \--* LCL_VAR ref V04 loc0 [000977] *---G+------ \--* IND ref [000976] ----G------- \--* ADDR byref Zero Fseq[key] [000237] a---G+-N---- \--* IND struct [000972] -----+------ \--* ADD byref [000963] -----+------ +--* LCL_VAR ref V04 loc0 [000971] -----+------ \--* ADD long [000969] -----+------ +--* LSH long [000975] -----+------ | +--* MUL long [000967] -----+------ | | +--* CAST long <- int [000964] i----+------ | | | \--* LCL_VAR int V09 loc5 [000974] ------------ | | \--* CNS_INT long 3 [000968] -----+-N---- | \--* CNS_INT long 3 [000970] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] New refCnts for V17: refCnt = 1, refCntWtd = 4 EH Var V17 needs explicit zero init. Disqualified as a register candidate. New refCnts for V09: refCnt = 15, refCntWtd = 44 New refCnts for V04: refCnt = 16, refCntWtd = 45 New refCnts for V04: refCnt = 17, refCntWtd = 47 New refCnts for V09: refCnt = 16, refCntWtd = 46 STMT00044 (IL 0x18E... ???) [000244] -A-X-+------ * ASG long [000243] D----+-N---- +--* LCL_VAR long V16 tmp2 [000242] #--X-+------ \--* IND long [000241] !----+------ \--* LCL_VAR ref V00 this New refCnts for V16: refCnt = 1, refCntWtd = 4 EH Var V16 needs explicit zero init. Disqualified as a register candidate. New refCnts for V00: refCnt = 10, refCntWtd = 9.50 STMT00046 (IL ???... ???) [000257] -A---+------ * ASG ref [000256] D----+-N---- +--* LCL_VAR ref V18 tmp4 [000240] -----+------ \--* LCL_VAR ref V01 arg1 New refCnts for V18: refCnt = 1, refCntWtd = 4 EH Var V18 needs explicit zero init. Disqualified as a register candidate. New refCnts for V01: refCnt = 7, refCntWtd = 7 STMT00158 (IL ???... ???) [001163] ------------ * JTRUE void [000263] J----+-N---- \--* EQ int [000259] n----+------ +--* IND long [000255] -----+------ | \--* ADD long [000253] #----+------ | +--* IND long [000252] #----+------ | | \--* IND long [000251] -----+------ | | \--* ADD long [000249] -----+------ | | +--* LCL_VAR long V16 tmp2 [000250] -----+------ | | \--* CNS_INT long 56 [000254] -----+------ | \--* CNS_INT long 48 [000262] -----+------ \--* CNS_INT long 0 New refCnts for V16: refCnt = 2, refCntWtd = 8 *** marking local variables in block BB35 (weight=1 ) STMT00159 (IL ???... ???) [001165] -A---------- * ASG long [001164] D------N---- +--* LCL_VAR long V19 tmp5 [000264] n----+?----- \--* IND long [000265] -----+?----- \--* ADD long [000266] #----+?----- +--* IND long [000267] #----+?----- | \--* IND long [000268] -----+?----- | \--* ADD long [000269] -----+?----- | +--* LCL_VAR long V16 tmp2 [000270] -----+?----- | \--* CNS_INT long 56 [000271] -----+?----- \--* CNS_INT long 48 New refCnts for V19: refCnt = 1, refCntWtd = 2 EH Var V19 needs explicit zero init. Disqualified as a register candidate. New refCnts for V16: refCnt = 3, refCntWtd = 10 *** marking local variables in block BB36 (weight=1 ) STMT00160 (IL ???... ???) [001167] -AC-G------- * ASG long [001166] D------N---- +--* LCL_VAR long V19 tmp5 [000261] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000248] -----+?----- arg0 in rcx +--* LCL_VAR long V16 tmp2 [000260] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr New refCnts for V19: refCnt = 2, refCntWtd = 4 New refCnts for V16: refCnt = 4, refCntWtd = 12 *** marking local variables in block BB37 (weight=2 ) STMT00048 (IL ???... ???) [000278] -A---+------ * ASG long [000277] D----+-N---- +--* LCL_VAR long V20 tmp6 [000276] -----+------ \--* LCL_VAR long V19 tmp5 New refCnts for V20: refCnt = 1, refCntWtd = 4 EH Var V20 needs explicit zero init. Disqualified as a register candidate. New refCnts for V19: refCnt = 3, refCntWtd = 8 STMT00049 (IL ???... ???) [000283] --CXG+------ * JTRUE void [000282] J-CXG+-N---- \--* EQ int [000280] --CXG+------ +--* CALL ind stub int [000279] -----+------ calli tgt | \--* LCL_VAR long V19 tmp5 [000234] -----+------ this in rcx | +--* LCL_VAR ref V05 loc1 [000980] -----+------ arg1 in r11 | +--* LCL_VAR long V19 tmp5 r11 REG r11 [000247] -----+------ arg2 in rdx | +--* LCL_VAR ref V17 tmp3 [000258] -----+------ arg3 in r8 | \--* LCL_VAR ref V01 arg1 [000281] -----+------ \--* CNS_INT int 0 New refCnts for V05: refCnt = 5, refCntWtd = 5.50 New refCnts for V19: refCnt = 4, refCntWtd = 12 New refCnts for V17: refCnt = 2, refCntWtd = 8 New refCnts for V01: refCnt = 8, refCntWtd = 9 New refCnts for V19: refCnt = 5, refCntWtd = 16 *** marking local variables in block BB38 (weight=0.50) STMT00050 (IL 0x1A4...0x1A6) [000287] -----+------ * JTRUE void [000286] N----+-N-U-- \--* NE int [000985] -----+------ +--* CAST int <- ubyte <- int [000284] -----+------ | \--* LCL_VAR int V03 arg3 [000285] -----+------ \--* CNS_INT int 1 New refCnts for V03: refCnt = 3, refCntWtd = 1.50 *** marking local variables in block BB39 (weight=0.50) STMT00057 (IL 0x1A8...0x1B1) [000336] -A-XG+------ * ASG ref [000335] *--XG+-N---- +--* IND ref [000987] ---XG+------ | \--* ADD byref [000998] ---XG+------ | +--* COMMA byref [000991] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [000331] -----+------ | | | +--* LCL_VAR int V09 loc5 [000990] ---X-+------ | | | \--* ARR_LENGTH int [000330] -----+------ | | | \--* LCL_VAR ref V04 loc0 [001001] ----G------- | | \--* ADDR byref [000332] a---G+-N---- | | \--* IND struct [000997] -----+------ | | \--* ADD byref [000988] -----+------ | | +--* LCL_VAR ref V04 loc0 [000996] -----+------ | | \--* ADD long [000994] -----+------ | | +--* LSH long [001000] -----+------ | | | +--* MUL long [000992] -----+------ | | | | +--* CAST long <- int [000989] i----+------ | | | | | \--* LCL_VAR int V09 loc5 [000999] ------------ | | | | \--* CNS_INT long 3 [000993] -----+-N---- | | | \--* CNS_INT long 3 [000995] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [000986] -----+------ | \--* CNS_INT long 8 field offset Fseq[value] [000334] -----+------ \--* LCL_VAR ref V02 arg2 New refCnts for V09: refCnt = 17, refCntWtd = 46.50 New refCnts for V04: refCnt = 18, refCntWtd = 47.50 New refCnts for V04: refCnt = 19, refCntWtd = 48 New refCnts for V09: refCnt = 18, refCntWtd = 47 New refCnts for V02: refCnt = 2, refCntWtd = 1 *** marking local variables in block BB40 (weight=0.50) STMT00051 (IL 0x1B8...0x1BA) [000291] -----+------ * JTRUE void [000290] N----+-N-U-- \--* EQ int [001002] -----+------ +--* CAST int <- ubyte <- int [000288] -----+------ | \--* LCL_VAR int V03 arg3 [000289] -----+------ \--* CNS_INT int 2 New refCnts for V03: refCnt = 4, refCntWtd = 2 *** marking local variables in block BB41 (weight=0.50) *** marking local variables in block BB42 (weight=4 ) STMT00040 (IL 0x1C4...0x1D1) [000222] -A-XG+------ * ASG int [000221] D----+-N---- +--* LCL_VAR int V09 loc5 [000220] *--XG+------ \--* IND int [001009] ---XG+------ \--* ADD byref [001020] ---XG+------ +--* COMMA byref [001013] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000217] -----+------ | | +--* LCL_VAR int V09 loc5 [001012] ---X-+------ | | \--* ARR_LENGTH int [000216] -----+------ | | \--* LCL_VAR ref V04 loc0 [001023] ----G------- | \--* ADDR byref [000218] a---G+-N---- | \--* IND struct [001019] -----+------ | \--* ADD byref [001010] -----+------ | +--* LCL_VAR ref V04 loc0 [001018] -----+------ | \--* ADD long [001016] -----+------ | +--* LSH long [001022] -----+------ | | +--* MUL long [001014] -----+------ | | | +--* CAST long <- int [001011] i----+------ | | | | \--* LCL_VAR int V09 loc5 [001021] ------------ | | | \--* CNS_INT long 3 [001015] -----+-N---- | | \--* CNS_INT long 3 [001017] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] [001008] -----+------ \--* CNS_INT long 20 field offset Fseq[next] New refCnts for V09: refCnt = 19, refCntWtd = 51 New refCnts for V09: refCnt = 20, refCntWtd = 55 New refCnts for V04: refCnt = 20, refCntWtd = 52 New refCnts for V04: refCnt = 21, refCntWtd = 56 New refCnts for V09: refCnt = 21, refCntWtd = 59 STMT00041 (IL 0x1D3...0x1D6) [000227] -A---+------ * ASG int [000226] D----+-N---- +--* LCL_VAR int V07 loc3 [000225] -----+------ \--* ADD int [000223] -----+------ +--* LCL_VAR int V07 loc3 [000224] -----+------ \--* CNS_INT int 1 New refCnts for V07: refCnt = 5, refCntWtd = 17 New refCnts for V07: refCnt = 6, refCntWtd = 21 STMT00042 (IL 0x1D7...0x1DB) [000232] ---X-+------ * JTRUE void [000231] N--X-+-N-U-- \--* GT int [000228] -----+------ +--* LCL_VAR int V07 loc3 [000230] ---X-+------ \--* ARR_LENGTH int [000229] -----+------ \--* LCL_VAR ref V04 loc0 New refCnts for V07: refCnt = 7, refCntWtd = 25 New refCnts for V04: refCnt = 22, refCntWtd = 60 *** marking local variables in block BB43 (weight=4 ) *** marking local variables in block BB44 (weight=0.50) STMT00015 (IL 0x1E4...0x1EB) [000071] ---XG+------ * JTRUE void [000070] J--XG+-N---- \--* LE int [000068] ---XG+------ +--* IND int [001025] -----+------ | \--* ADD byref [000067] -----+------ | +--* LCL_VAR ref V00 this [001024] -----+------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] [000069] -----+------ \--* CNS_INT int 0 New refCnts for V00: refCnt = 11, refCntWtd = 10 *** marking local variables in block BB45 (weight=0.50) STMT00035 (IL 0x1ED...0x1F3) [000174] -A-XG+------ * ASG int [000173] D----+-N---- +--* LCL_VAR int V10 loc6 [000172] ---XG+------ \--* IND int [001027] -----+------ \--* ADD byref [000171] -----+------ +--* LCL_VAR ref V00 this [001026] -----+------ \--* CNS_INT long 60 field offset Fseq[_freeList] New refCnts for V10: refCnt = 1, refCntWtd = 0.50 EH Var V10 needs explicit zero init. Disqualified as a register candidate. New refCnts for V00: refCnt = 12, refCntWtd = 10.50 STMT00120 (IL 0x1F5... ???) [000688] -A-XG+------ * ASG bool [000687] D----+-N---- +--* LCL_VAR int V49 tmp35 [000184] -A-XG+------ \--* GE int [000182] -A-XG+------ +--* ADD int [001050] -A-XG+------ | +--* NEG int [000181] *A-XG+------ | | \--* IND int [001029] -A-XG+------ | | \--* ADD byref [001044] -A-XG+------ | | +--* COMMA byref [001032] -A-XG+------ | | | +--* ASG int [001031] D----+-N---- | | | | +--* LCL_VAR int V62 tmp48 [000178] ---XG+------ | | | | \--* IND int [001046] -----+------ | | | | \--* ADD byref [000177] -----+------ | | | | +--* LCL_VAR ref V00 this [001045] -----+------ | | | | \--* CNS_INT long 60 field offset Fseq[_freeList] [001043] ---XG+------ | | | \--* COMMA byref [001036] ---X-+------ | | | +--* ARR_BOUNDS_CHECK_Rng void [001033] -----+------ | | | | +--* LCL_VAR int V62 tmp48 [001035] ---X-+------ | | | | \--* ARR_LENGTH int [000176] -----+------ | | | | \--* LCL_VAR ref V04 loc0 [001049] ----G------- | | | \--* ADDR byref [000179] a---G+-N---- | | | \--* IND struct [001042] -----+------ | | | \--* ADD byref [001030] -----+------ | | | +--* LCL_VAR ref V04 loc0 [001041] -----+------ | | | \--* ADD long [001039] -----+------ | | | +--* LSH long [001048] -----+------ | | | | +--* MUL long [001037] -----+------ | | | | | +--* CAST long <- int [001034] i----+------ | | | | | | \--* LCL_VAR int V62 tmp48 [001047] ------------ | | | | | \--* CNS_INT long 3 [001038] -----+-N---- | | | | \--* CNS_INT long 3 [001040] -----+------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] [001028] -----+------ | | \--* CNS_INT long 20 field offset Fseq[next] [000175] -----+------ | \--* CNS_INT int -3 [000183] -----+------ \--* CNS_INT int -1 New refCnts for V49: refCnt = 1, refCntWtd = 1 EH Var V49 needs explicit zero init. Disqualified as a register candidate. New refCnts for V62: refCnt = 1, refCntWtd = 1 EH Var V62 needs explicit zero init. Disqualified as a register candidate. New refCnts for V00: refCnt = 13, refCntWtd = 11 New refCnts for V62: refCnt = 2, refCntWtd = 2 New refCnts for V04: refCnt = 23, refCntWtd = 60.50 New refCnts for V04: refCnt = 24, refCntWtd = 61 New refCnts for V62: refCnt = 3, refCntWtd = 3 STMT00123 (IL 0x1F5... ???) [000698] -A--G+------ * ASG ref [000697] D----+-N---- +--* LCL_VAR ref V50 tmp36 [000684] #---G+------ \--* IND ref [000683] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] New refCnts for V50: refCnt = 1, refCntWtd = 1 Marking EH Var V50 as a register candidate. STMT00121 (IL 0x1F5... ???) [000693] -----+------ * JTRUE void [000692] J----+-N---- \--* NE int [000690] -----+------ +--* LCL_VAR int V49 tmp35 [000691] -----+------ \--* CNS_INT int 0 New refCnts for V49: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB46 (weight=0.50) STMT00122 (IL 0x1F5... ???) [000696] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [001052] #---G+------ arg0 in rcx +--* IND ref [001051] H----+------ | \--* CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" [000695] -----+------ arg1 in rdx \--* LCL_VAR ref V50 tmp36 New refCnts for V50: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB47 (weight=0.50) STMT00037 (IL 0x219... ???) [000200] -A-XG+------ * ASG int [000199] ---XG+-N---- +--* IND int [001056] -----+------ | \--* ADD byref [000190] -----+------ | +--* LCL_VAR ref V00 this [001055] -----+------ | \--* CNS_INT long 60 field offset Fseq[_freeList] [000198] -A-XG+------ \--* ADD int [001079] -A-XG+------ +--* NEG int [000197] *A-XG+------ | \--* IND int [001058] -A-XG+------ | \--* ADD byref [001073] -A-XG+------ | +--* COMMA byref [001061] -A-XG+------ | | +--* ASG int [001060] D----+-N---- | | | +--* LCL_VAR int V63 tmp49 [000194] ---XG+------ | | | \--* IND int [001075] -----+------ | | | \--* ADD byref [000193] -----+------ | | | +--* LCL_VAR ref V00 this [001074] -----+------ | | | \--* CNS_INT long 60 field offset Fseq[_freeList] [001072] ---XG+------ | | \--* COMMA byref [001065] ---X-+------ | | +--* ARR_BOUNDS_CHECK_Rng void [001062] -----+------ | | | +--* LCL_VAR int V63 tmp49 [001064] ---X-+------ | | | \--* ARR_LENGTH int [000192] -----+------ | | | \--* LCL_VAR ref V04 loc0 [001078] ----G------- | | \--* ADDR byref [000195] a---G+-N---- | | \--* IND struct [001071] -----+------ | | \--* ADD byref [001059] -----+------ | | +--* LCL_VAR ref V04 loc0 [001070] -----+------ | | \--* ADD long [001068] -----+------ | | +--* LSH long [001077] -----+------ | | | +--* MUL long [001066] -----+------ | | | | +--* CAST long <- int [001063] i----+------ | | | | | \--* LCL_VAR int V63 tmp49 [001076] ------------ | | | | \--* CNS_INT long 3 [001067] -----+-N---- | | | \--* CNS_INT long 3 [001069] -----+------ | | \--* CNS_INT long 16 Fseq[#FirstElem] [001057] -----+------ | \--* CNS_INT long 20 field offset Fseq[next] [000191] -----+------ \--* CNS_INT int -3 New refCnts for V00: refCnt = 14, refCntWtd = 11.50 New refCnts for V63: refCnt = 1, refCntWtd = 1 EH Var V63 needs explicit zero init. Disqualified as a register candidate. New refCnts for V00: refCnt = 15, refCntWtd = 12 New refCnts for V63: refCnt = 2, refCntWtd = 2 New refCnts for V04: refCnt = 25, refCntWtd = 61.50 New refCnts for V04: refCnt = 26, refCntWtd = 62 New refCnts for V63: refCnt = 3, refCntWtd = 3 STMT00038 (IL 0x233...0x23C) [000207] -A-XG+------ * ASG int [000206] ---XG+-N---- +--* IND int [001081] -----+------ | \--* ADD byref [000201] -----+------ | +--* LCL_VAR ref V00 this [001080] -----+------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] [000205] ---XG+------ \--* ADD int [000203] ---XG+------ +--* IND int [001083] -----+------ | \--* ADD byref [000202] -----+------ | +--* LCL_VAR ref V00 this [001082] -----+------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] [000204] -----+------ \--* CNS_INT int -1 New refCnts for V00: refCnt = 16, refCntWtd = 12.50 New refCnts for V00: refCnt = 17, refCntWtd = 13 *** marking local variables in block BB48 (weight=0.50) STMT00016 (IL 0x243...0x249) [000075] -A-XG+------ * ASG int [000074] D----+-N---- +--* LCL_VAR int V13 loc9 [000073] ---XG+------ \--* IND int [001085] -----+------ \--* ADD byref [000072] -----+------ +--* LCL_VAR ref V00 this [001084] -----+------ \--* CNS_INT long 56 field offset Fseq[_count] New refCnts for V13: refCnt = 1, refCntWtd = 0.50 EH Var V13 needs explicit zero init. Disqualified as a register candidate. New refCnts for V00: refCnt = 18, refCntWtd = 13.50 STMT00017 (IL 0x24B...0x250) [000080] ---X-+------ * JTRUE void [000079] N--X-+-N-U-- \--* NE int [000076] -----+------ +--* LCL_VAR int V13 loc9 [000078] ---X-+------ \--* ARR_LENGTH int [000077] -----+------ \--* LCL_VAR ref V04 loc0 New refCnts for V13: refCnt = 2, refCntWtd = 1 New refCnts for V04: refCnt = 27, refCntWtd = 62.50 *** marking local variables in block BB49 (weight=0.50) STMT00125 (IL 0x252... ???) [000705] --CXG+------ * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [001090] -ACXG-----L- arg1 SETUP +--* ASG int [001089] D------N---- | +--* LCL_VAR int V64 tmp50 [000702] --CXG+------ | \--* CALL int System.Collections.HashHelpers.ExpandPrime [000701] ---XG+------ arg0 in rcx | \--* IND int [001087] -----+------ | \--* ADD byref [000700] -----+------ | +--* LCL_VAR ref V00 this [001086] -----+------ | \--* CNS_INT long 56 field offset Fseq[_count] [001091] ------------ arg1 in rdx +--* LCL_VAR int V64 tmp50 [000163] -----+------ this in rcx +--* LCL_VAR ref V00 this [000704] -----+------ arg2 in r8 \--* CNS_INT int 0 New refCnts for V64: refCnt = 1, refCntWtd = 1 EH Var V64 needs explicit zero init. Disqualified as a register candidate. New refCnts for V00: refCnt = 19, refCntWtd = 14 New refCnts for V64: refCnt = 2, refCntWtd = 2 New refCnts for V00: refCnt = 20, refCntWtd = 14.50 STMT00126 (IL 0x258... ???) [000711] -A-XG+------ * ASG ref [000710] D----+-N---- +--* LCL_VAR ref V52 tmp38 [000709] ---XG+------ \--* IND ref [001095] -----+------ \--* ADD byref [000165] -----+------ +--* LCL_VAR ref V00 this [001094] -----+------ \--* CNS_INT long 8 field offset Fseq[_buckets] New refCnts for V52: refCnt = 1, refCntWtd = 0.50 Marking EH Var V52 as a register candidate. New refCnts for V00: refCnt = 21, refCntWtd = 15 STMT00133 (IL 0x258... ???) [000760] -A-X-+------ * ASG int [000759] D----+-N---- +--* LCL_VAR int V53 tmp39 [000714] ---X-+------ \--* ARR_LENGTH int [000713] -----+------ \--* LCL_VAR ref V52 tmp38 New refCnts for V53: refCnt = 1, refCntWtd = 1 EH Var V53 needs explicit zero init. Disqualified as a register candidate. New refCnts for V52: refCnt = 2, refCntWtd = 1 STMT00134 (IL 0x258... ???) [000762] -A-XG+------ * ASG long [000761] D----+-N---- +--* LCL_VAR long V54 tmp40 [000716] ---XG+------ \--* IND long [001097] -----+------ \--* ADD byref [000715] -----+------ +--* LCL_VAR ref V00 this [001096] -----+------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] New refCnts for V54: refCnt = 1, refCntWtd = 1 EH Var V54 needs explicit zero init. Disqualified as a register candidate. New refCnts for V00: refCnt = 22, refCntWtd = 15.50 STMT00136 (IL 0x258... ???) [000773] -A---+------ * ASG bool [000772] D----+-N---- +--* LCL_VAR int V56 tmp42 [000730] N----+---U-- \--* LE int [000728] -----+------ +--* LCL_VAR int V53 tmp39 [000729] -----+------ \--* CNS_INT int 0x7FFFFFFF New refCnts for V56: refCnt = 1, refCntWtd = 1 EH Var V56 needs explicit zero init. Disqualified as a register candidate. New refCnts for V53: refCnt = 2, refCntWtd = 2 STMT00139 (IL 0x258... ???) [000783] -A--G+------ * ASG ref [000782] D----+-N---- +--* LCL_VAR ref V57 tmp43 [000767] #---G+------ \--* IND ref [000766] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] New refCnts for V57: refCnt = 1, refCntWtd = 1 Marking EH Var V57 as a register candidate. STMT00140 (IL 0x258... ???) [000785] -A--G+------ * ASG ref [000784] D----+-N---- +--* LCL_VAR ref V58 tmp44 [000769] #---G+------ \--* IND ref [000768] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] New refCnts for V58: refCnt = 1, refCntWtd = 1 Marking EH Var V58 as a register candidate. STMT00137 (IL 0x258... ???) [000778] -----+------ * JTRUE void [000777] J----+-N---- \--* NE int [000775] -----+------ +--* LCL_VAR int V56 tmp42 [000776] -----+------ \--* CNS_INT int 0 New refCnts for V56: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB50 (weight=0.50) STMT00138 (IL 0x258... ???) [000781] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000779] -----+------ arg0 in rcx +--* LCL_VAR ref V57 tmp43 [000780] -----+------ arg1 in rdx \--* LCL_VAR ref V58 tmp44 New refCnts for V57: refCnt = 2, refCntWtd = 2 New refCnts for V58: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB51 (weight=0.50) STMT00131 (IL 0x258... ???) [000750] -A---+------ * ASG int [000749] D----+-N---- +--* LCL_VAR int V55 tmp41 [000748] -----+------ \--* CAST int <- uint <- long [000747] -----+------ \--* RSZ long [000745] -----+------ +--* MUL long [000742] -----+------ | +--* ADD long [000739] -----+------ | | +--* RSZ long [000737] -----+------ | | | +--* MUL long [000735] -----+------ | | | | +--* LCL_VAR long V54 tmp40 [000736] -----+---U-- | | | | \--* CAST long <- ulong <- uint [000166] -----+------ | | | | \--* LCL_VAR int V06 loc2 [000738] -----+------ | | | \--* CNS_INT int 32 [000741] -----+------ | | \--* CNS_INT long 1 [000744] -----+---U-- | \--* CAST long <- ulong <- uint [000743] -----+------ | \--* LCL_VAR int V53 tmp39 [000746] -----+------ \--* CNS_INT int 32 New refCnts for V55: refCnt = 1, refCntWtd = 0.50 EH Var V55 needs explicit zero init. Disqualified as a register candidate. New refCnts for V54: refCnt = 2, refCntWtd = 2 New refCnts for V06: refCnt = 6, refCntWtd = 11.50 New refCnts for V53: refCnt = 3, refCntWtd = 3 STMT00142 (IL 0x258... ???) [000796] -A-X-+------ * ASG bool [000795] D----+-N---- +--* LCL_VAR int V59 tmp45 [000755] ---X-+------ \--* EQ int [000751] -----+------ +--* LCL_VAR int V55 tmp41 [000754] ---X-+------ \--* UMOD int [000752] -----+------ +--* LCL_VAR int V06 loc2 [000753] -----+------ \--* LCL_VAR int V53 tmp39 New refCnts for V59: refCnt = 1, refCntWtd = 1 EH Var V59 needs explicit zero init. Disqualified as a register candidate. New refCnts for V55: refCnt = 2, refCntWtd = 1 New refCnts for V06: refCnt = 7, refCntWtd = 12 New refCnts for V53: refCnt = 4, refCntWtd = 4 STMT00145 (IL 0x258... ???) [000806] -A--G+------ * ASG ref [000805] D----+-N---- +--* LCL_VAR ref V60 tmp46 [000790] #---G+------ \--* IND ref [000789] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] New refCnts for V60: refCnt = 1, refCntWtd = 1 Marking EH Var V60 as a register candidate. STMT00146 (IL 0x258... ???) [000808] -A--G+------ * ASG ref [000807] D----+-N---- +--* LCL_VAR ref V61 tmp47 [000792] #---G+------ \--* IND ref [000791] H----+------ \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] New refCnts for V61: refCnt = 1, refCntWtd = 1 Marking EH Var V61 as a register candidate. STMT00143 (IL 0x258... ???) [000801] -----+------ * JTRUE void [000800] J----+-N---- \--* NE int [000798] -----+------ +--* LCL_VAR int V59 tmp45 [000799] -----+------ \--* CNS_INT int 0 New refCnts for V59: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB52 (weight=0.50) STMT00144 (IL 0x258... ???) [000804] --CXG+------ * CALL void System.Diagnostics.Debug.Fail [000802] -----+------ arg0 in rcx +--* LCL_VAR ref V60 tmp46 [000803] -----+------ arg1 in rdx \--* LCL_VAR ref V61 tmp47 New refCnts for V60: refCnt = 2, refCntWtd = 2 New refCnts for V61: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB53 (weight=0.50) STMT00128 (IL 0x258... ???) [000722] -A-XG+------ * ASG byref [000721] D----+-N---- +--* LCL_VAR byref V51 tmp37 [001112] ---XG+------ \--* COMMA byref [001105] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000758] -----+------ | +--* LCL_VAR int V55 tmp41 [001104] ---X-+------ | \--* ARR_LENGTH int [000712] -----+------ | \--* LCL_VAR ref V52 tmp38 [001113] ----G------- \--* ADDR byref [000719] a---G+-N---- \--* IND int [001111] -----+------ \--* ADD byref [001102] -----+------ +--* LCL_VAR ref V52 tmp38 [001110] -----+------ \--* ADD long [001108] -----+------ +--* LSH long [001106] -----+------ | +--* CAST long <- int [001103] i----+------ | | \--* LCL_VAR int V55 tmp41 [001107] -----+-N---- | \--* CNS_INT long 2 [001109] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] New refCnts for V51: refCnt = 1, refCntWtd = 0.50 Marking EH Var V51 as a register candidate. New refCnts for V55: refCnt = 3, refCntWtd = 1.50 New refCnts for V52: refCnt = 3, refCntWtd = 1.50 New refCnts for V52: refCnt = 4, refCntWtd = 2 New refCnts for V55: refCnt = 4, refCntWtd = 2 STMT00129 (IL 0x258... ???) [000726] -A---+------ * ASG ref [000725] D----+-N---- +--* LCL_VAR ref V52 tmp38 [000724] -----+------ \--* CNS_INT ref null New refCnts for V52: refCnt = 5, refCntWtd = 2.50 EH Var V52 has multiple definitions. Disqualified as a register candidate. STMT00034 (IL ???... ???) [000170] -A---+------ * ASG byref [000169] D----+-N---- +--* LCL_VAR byref V08 loc4 [000723] -----+------ \--* LCL_VAR byref V51 tmp37 New refCnts for V08: refCnt = 2, refCntWtd = 1.50 EH Var V08 has multiple definitions. Disqualified as a register candidate. New refCnts for V51: refCnt = 2, refCntWtd = 1 *** marking local variables in block BB54 (weight=0.50) STMT00018 (IL 0x261...0x263) [000083] -A---+------ * ASG int [000082] D----+-N---- +--* LCL_VAR int V10 loc6 [000081] -----+------ \--* LCL_VAR int V13 loc9 New refCnts for V10: refCnt = 2, refCntWtd = 1 New refCnts for V13: refCnt = 3, refCntWtd = 1.50 STMT00019 (IL 0x265...0x26A) [000089] -A-XG+------ * ASG int [000088] ---XG+-N---- +--* IND int [001115] -----+------ | \--* ADD byref [000084] -----+------ | +--* LCL_VAR ref V00 this [001114] -----+------ | \--* CNS_INT long 56 field offset Fseq[_count] [000087] -----+------ \--* ADD int [000085] -----+------ +--* LCL_VAR int V13 loc9 [000086] -----+------ \--* CNS_INT int 1 New refCnts for V00: refCnt = 23, refCntWtd = 16 New refCnts for V13: refCnt = 4, refCntWtd = 2 STMT00020 (IL 0x26F...0x275) [000093] -A-XG+------ * ASG ref [000092] D----+-N---- +--* LCL_VAR ref V04 loc0 [000091] ---XG+------ \--* IND ref [001117] -----+------ \--* ADD byref [000090] -----+------ +--* LCL_VAR ref V00 this [001116] -----+------ \--* CNS_INT long 16 field offset Fseq[_entries] New refCnts for V04: refCnt = 28, refCntWtd = 63 EH Var V04 has multiple definitions. Disqualified as a register candidate. New refCnts for V00: refCnt = 24, refCntWtd = 16.50 *** marking local variables in block BB55 (weight=0.50) STMT00021 (IL 0x276...0x27E) [000099] -A-XG+------ * ASG byref [000098] D----+-N---- +--* LCL_VAR byref V11 loc7 [001128] ---XG+------ \--* COMMA byref [001121] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000095] -----+------ | +--* LCL_VAR int V10 loc6 [001120] ---X-+------ | \--* ARR_LENGTH int [000094] -----+------ | \--* LCL_VAR ref V04 loc0 [001131] ----G------- \--* ADDR byref [000096] a---G+-N---- \--* IND struct [001127] -----+------ \--* ADD byref [001118] -----+------ +--* LCL_VAR ref V04 loc0 [001126] -----+------ \--* ADD long [001124] -----+------ +--* LSH long [001130] -----+------ | +--* MUL long [001122] -----+------ | | +--* CAST long <- int [001119] i----+------ | | | \--* LCL_VAR int V10 loc6 [001129] ------------ | | \--* CNS_INT long 3 [001123] -----+-N---- | \--* CNS_INT long 3 [001125] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] New refCnts for V11: refCnt = 1, refCntWtd = 0.50 Marking EH Var V11 as a register candidate. New refCnts for V10: refCnt = 3, refCntWtd = 1.50 New refCnts for V04: refCnt = 29, refCntWtd = 63.50 New refCnts for V04: refCnt = 30, refCntWtd = 64 New refCnts for V10: refCnt = 4, refCntWtd = 2 STMT00022 (IL 0x280...0x283) [000103] -A-XG+------ * ASG int [000102] *--XG+-N---- +--* IND int [001133] -----+------ | \--* ADD byref [000100] -----+------ | +--* LCL_VAR byref V11 loc7 [001132] -----+------ | \--* CNS_INT long 16 field offset Fseq[hashCode] [000101] -----+------ \--* LCL_VAR int V06 loc2 New refCnts for V11: refCnt = 2, refCntWtd = 1 New refCnts for V06: refCnt = 8, refCntWtd = 12.50 STMT00023 (IL 0x288...0x28F) [000110] -A-XG+------ * ASG int [000109] *--XG+-N---- +--* IND int [001135] -----+------ | \--* ADD byref [000104] -----+------ | +--* LCL_VAR byref V11 loc7 [001134] -----+------ | \--* CNS_INT long 20 field offset Fseq[next] [000108] ---XG+------ \--* ADD int [000106] *--XG+------ +--* IND int [000105] -----+------ | \--* LCL_VAR byref V08 loc4 [000107] -----+------ \--* CNS_INT int -1 New refCnts for V11: refCnt = 3, refCntWtd = 1.50 New refCnts for V08: refCnt = 3, refCntWtd = 2 STMT00024 (IL 0x294...0x297) [000114] -A-XG+------ * ASG ref [000113] *--XG+-N---- +--* IND ref [000111] -----+------ | \--* LCL_VAR byref V11 loc7 Zero Fseq[key] [000112] -----+------ \--* LCL_VAR ref V01 arg1 New refCnts for V11: refCnt = 4, refCntWtd = 2 New refCnts for V01: refCnt = 9, refCntWtd = 9.50 STMT00025 (IL 0x29C...0x29F) [000118] -A-XG+------ * ASG ref [000117] *--XG+-N---- +--* IND ref [001137] -----+------ | \--* ADD byref [000115] -----+------ | +--* LCL_VAR byref V11 loc7 [001136] -----+------ | \--* CNS_INT long 8 field offset Fseq[value] [000116] -----+------ \--* LCL_VAR ref V02 arg2 New refCnts for V11: refCnt = 5, refCntWtd = 2.50 New refCnts for V02: refCnt = 3, refCntWtd = 1.50 STMT00026 (IL 0x2A4...0x2AA) [000124] -A-XG+------ * ASG int [000123] *--X-+-N---- +--* IND int [000119] -----+------ | \--* LCL_VAR byref V08 loc4 [000122] -----+------ \--* ADD int [000120] -----+------ +--* LCL_VAR int V10 loc6 [000121] -----+------ \--* CNS_INT int 1 New refCnts for V08: refCnt = 4, refCntWtd = 2.50 New refCnts for V10: refCnt = 5, refCntWtd = 2.50 STMT00027 (IL 0x2AB...0x2B4) [000131] -A-XG+------ * ASG int [000130] ---XG+-N---- +--* IND int [001139] -----+------ | \--* ADD byref [000125] -----+------ | +--* LCL_VAR ref V00 this [001138] -----+------ | \--* CNS_INT long 68 field offset Fseq[_version] [000129] ---XG+------ \--* ADD int [000127] ---XG+------ +--* IND int [001141] -----+------ | \--* ADD byref [000126] -----+------ | +--* LCL_VAR ref V00 this [001140] -----+------ | \--* CNS_INT long 68 field offset Fseq[_version] [000128] -----+------ \--* CNS_INT int 1 New refCnts for V00: refCnt = 25, refCntWtd = 17 New refCnts for V00: refCnt = 26, refCntWtd = 17.50 STMT00028 (IL 0x2CA...0x2CD) [000148] -----+------ * JTRUE void [000147] N----+-N-U-- \--* LE int [000145] -----+------ +--* LCL_VAR int V07 loc3 [000146] -----+------ \--* CNS_INT int 100 New refCnts for V07: refCnt = 8, refCntWtd = 25.50 *** marking local variables in block BB56 (weight=0.50) STMT00030 (IL 0x2CF...0x2D5) [000156] --C-G+------ * JTRUE void [000155] J-C-G+-N---- \--* EQ int [000153] --C-G+------ +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS [000151] -----+------ arg1 in rdx | +--* LCL_VAR ref V05 loc1 [000152] H----+-N---- arg0 in rcx | \--* CNS_INT(h) long 0xd1ffab1e class [000154] -----+------ \--* CNS_INT ref null New refCnts for V05: refCnt = 6, refCntWtd = 6 *** marking local variables in block BB57 (weight=0.50) STMT00031 (IL 0x2D7...0x2DC) [000161] --CXG+------ * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize [000159] ---X-+------ arg1 in rdx +--* ARR_LENGTH int [000158] -----+------ | \--* LCL_VAR ref V04 loc0 [000157] -----+------ this in rcx +--* LCL_VAR ref V00 this [000160] -----+------ arg2 in r8 \--* CNS_INT int 1 New refCnts for V04: refCnt = 31, refCntWtd = 64.50 New refCnts for V00: refCnt = 27, refCntWtd = 18 *** marking local variables in block BB58 (weight=0.50) STMT00147 (IL ???... ???) [000810] -----+------ * RETURN int [000482] -----+------ \--* CNS_INT int 1 *** marking local variables in block BB59 (weight=0 ) STMT00086 (IL 0x008...0x009) [000533] --CXG+------ * CALL void System.ThrowHelper.ThrowArgumentNullException [000532] -----+------ arg0 in rcx \--* CNS_INT int 4 *** marking local variables in block BB60 (weight=0 ) STMT00073 (IL 0x14F...0x150) [000444] -A-X-+------ * ASG long [000443] D----+-N---- +--* LCL_VAR long V26 tmp12 [000442] #--X-+------ \--* IND long [000441] !----+------ \--* LCL_VAR ref V00 this New refCnts for V26: refCnt = 1, refCntWtd = 0 EH Var V26 needs explicit zero init. Disqualified as a register candidate. New refCnts for V00: refCnt = 28, refCntWtd = 18 STMT00074 (IL ???... ???) [000454] -A---+------ * ASG ref [000453] D----+-N---- +--* LCL_VAR ref V27 tmp13 [000439] -----+------ \--* LCL_VAR ref V01 arg1 New refCnts for V27: refCnt = 1, refCntWtd = 0 EH Var V27 needs explicit zero init. Disqualified as a register candidate. New refCnts for V01: refCnt = 10, refCntWtd = 9.50 STMT00155 (IL ???... ???) [001158] ------------ * JTRUE void [000460] J----+-N---- \--* EQ int [000456] n----+------ +--* IND long [000452] -----+------ | \--* ADD long [000450] #----+------ | +--* IND long [000449] #----+------ | | \--* IND long [000448] -----+------ | | \--* ADD long [000446] -----+------ | | +--* LCL_VAR long V26 tmp12 [000447] -----+------ | | \--* CNS_INT long 56 [000451] -----+------ | \--* CNS_INT long 56 [000459] -----+------ \--* CNS_INT long 0 New refCnts for V26: refCnt = 2, refCntWtd = 0 *** marking local variables in block BB61 (weight=0 ) STMT00156 (IL ???... ???) [001160] -A---------- * ASG long [001159] D------N---- +--* LCL_VAR long V28 tmp14 [000461] n----+?----- \--* IND long [000462] -----+?----- \--* ADD long [000463] #----+?----- +--* IND long [000464] #----+?----- | \--* IND long [000465] -----+?----- | \--* ADD long [000466] -----+?----- | +--* LCL_VAR long V26 tmp12 [000467] -----+?----- | \--* CNS_INT long 56 [000468] -----+?----- \--* CNS_INT long 56 New refCnts for V28: refCnt = 1, refCntWtd = 0 EH Var V28 needs explicit zero init. Disqualified as a register candidate. New refCnts for V26: refCnt = 3, refCntWtd = 0 *** marking local variables in block BB62 (weight=0 ) STMT00157 (IL ???... ???) [001162] -AC-G------- * ASG long [001161] D------N---- +--* LCL_VAR long V28 tmp14 [000458] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000445] -----+?----- arg0 in rcx +--* LCL_VAR long V26 tmp12 [000457] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr New refCnts for V28: refCnt = 2, refCntWtd = 0 New refCnts for V26: refCnt = 4, refCntWtd = 0 *** marking local variables in block BB63 (weight=0 ) STMT00076 (IL ???... ???) [000440] --CXG+------ * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000473] -----+------ arg0 in rcx +--* LCL_VAR long V28 tmp14 [000455] -----+------ arg1 in rdx \--* LCL_VAR ref V01 arg1 New refCnts for V28: refCnt = 3, refCntWtd = 0 New refCnts for V01: refCnt = 11, refCntWtd = 9.50 *** marking local variables in block BB64 (weight=0 ) STMT00053 (IL 0x1BC...0x1BD) [000299] -A-X-+------ * ASG long [000298] D----+-N---- +--* LCL_VAR long V21 tmp7 [000297] #--X-+------ \--* IND long [000296] !----+------ \--* LCL_VAR ref V00 this New refCnts for V21: refCnt = 1, refCntWtd = 0 EH Var V21 needs explicit zero init. Disqualified as a register candidate. New refCnts for V00: refCnt = 29, refCntWtd = 18 STMT00054 (IL ???... ???) [000309] -A---+------ * ASG ref [000308] D----+-N---- +--* LCL_VAR ref V22 tmp8 [000294] -----+------ \--* LCL_VAR ref V01 arg1 New refCnts for V22: refCnt = 1, refCntWtd = 0 EH Var V22 needs explicit zero init. Disqualified as a register candidate. New refCnts for V01: refCnt = 12, refCntWtd = 9.50 STMT00161 (IL ???... ???) [001168] ------------ * JTRUE void [000315] J----+-N---- \--* EQ int [000311] n----+------ +--* IND long [000307] -----+------ | \--* ADD long [000305] #----+------ | +--* IND long [000304] #----+------ | | \--* IND long [000303] -----+------ | | \--* ADD long [000301] -----+------ | | +--* LCL_VAR long V21 tmp7 [000302] -----+------ | | \--* CNS_INT long 56 [000306] -----+------ | \--* CNS_INT long 56 [000314] -----+------ \--* CNS_INT long 0 New refCnts for V21: refCnt = 2, refCntWtd = 0 *** marking local variables in block BB65 (weight=0 ) STMT00162 (IL ???... ???) [001170] -A---------- * ASG long [001169] D------N---- +--* LCL_VAR long V23 tmp9 [000316] n----+?----- \--* IND long [000317] -----+?----- \--* ADD long [000318] #----+?----- +--* IND long [000319] #----+?----- | \--* IND long [000320] -----+?----- | \--* ADD long [000321] -----+?----- | +--* LCL_VAR long V21 tmp7 [000322] -----+?----- | \--* CNS_INT long 56 [000323] -----+?----- \--* CNS_INT long 56 New refCnts for V23: refCnt = 1, refCntWtd = 0 EH Var V23 needs explicit zero init. Disqualified as a register candidate. New refCnts for V21: refCnt = 3, refCntWtd = 0 *** marking local variables in block BB66 (weight=0 ) STMT00163 (IL ???... ???) [001172] -AC-G------- * ASG long [001171] D------N---- +--* LCL_VAR long V23 tmp9 [000313] --C-G+?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS [000300] -----+?----- arg0 in rcx +--* LCL_VAR long V21 tmp7 [000312] H----+?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr New refCnts for V23: refCnt = 2, refCntWtd = 0 New refCnts for V21: refCnt = 4, refCntWtd = 0 *** marking local variables in block BB67 (weight=0 ) STMT00056 (IL ???... ???) [000295] --CXG+------ * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException [000328] -----+------ arg0 in rcx +--* LCL_VAR long V23 tmp9 [000310] -----+------ arg1 in rdx \--* LCL_VAR ref V01 arg1 New refCnts for V23: refCnt = 3, refCntWtd = 0 New refCnts for V01: refCnt = 13, refCntWtd = 9.50 *** marking local variables in block BB68 (weight=0 ) STMT00043 (IL 0x1DD...0x1E2) [000233] --CXG+------ * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 30, refCntWtd = 19 New refCnts for V00: refCnt = 31, refCntWtd = 20 New refCnts for V01: refCnt = 14, refCntWtd = 10.50 New refCnts for V01: refCnt = 15, refCntWtd = 11.50 New refCnts for V02: refCnt = 4, refCntWtd = 2.50 New refCnts for V02: refCnt = 5, refCntWtd = 3.50 New refCnts for V03: refCnt = 5, refCntWtd = 3 New refCnts for V03: refCnt = 6, refCntWtd = 4 Reporting this as generic context: referenced *************** In optAddCopies() *************** Finishing PHASE Mark local vars *************** Starting PHASE Optimize bools *************** In optOptimizeBools() *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize bools *************** Starting PHASE Find oper order *************** In fgFindOperOrder() *************** Finishing PHASE Find oper order *************** Starting PHASE Set block order *************** In fgSetBlockOrder() fgMarkLoopHead: Checking loop head block BB23: no guaranteed callsite exits, marking method as fully interruptible fgMarkLoopHead: Checking loop head block BB32: method is already fully interruptible The biggest BB has 35 tree nodes *************** Finishing PHASE Set block order Trees before Build SSA representation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target align BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal Loop1 gcsafe BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe BB36 [0108] 1 BB34 1 [???..???) i gcsafe BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen BB54 [0044] 2 BB48,BB53 0.50 [261..276) i BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} ***** BB01 STMT00000 (IL 0x000...0x006) N004 ( 5, 5) [000003] ------------ * JTRUE void N003 ( 3, 3) [000002] J------N---- \--* EQ int N001 ( 1, 1) [000000] ------------ +--* LCL_VAR ref V01 arg1 N002 ( 1, 1) [000001] ------------ \--* CNS_INT ref null ------------ BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00001 (IL 0x00E...0x014) N007 ( 8, 8) [000008] ---XG------- * JTRUE void N006 ( 6, 6) [000007] J--XG--N---- \--* NE int N004 ( 4, 4) [000005] ---XG------- +--* IND ref N003 ( 2, 2) [000814] -------N---- | \--* ADD byref N001 ( 1, 1) [000004] ------------ | +--* LCL_VAR ref V00 this N002 ( 1, 1) [000813] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] N005 ( 1, 1) [000006] ------------ \--* CNS_INT ref null ------------ BB03 [016..01E), preds={BB02} succs={BB04} ***** BB03 STMT00085 (IL ???... ???) N005 ( 16, 10) [000528] --CXG------- * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize N003 ( 1, 1) [000526] ------------ this in rcx +--* LCL_VAR ref V00 this N004 ( 1, 1) [000527] ------------ arg1 in rdx \--* CNS_INT int 0 ------------ BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ***** BB04 STMT00088 (IL 0x01E... ???) N008 ( 9, 6) [000544] -A-XG---R--- * ASG bool N007 ( 1, 1) [000543] D------N---- +--* LCL_VAR int V33 tmp19 N006 ( 9, 6) [000012] N--XG------- \--* NE int N004 ( 4, 4) [000010] ---XG------- +--* IND ref N003 ( 2, 2) [000818] -------N---- | \--* ADD byref N001 ( 1, 1) [000009] ------------ | +--* LCL_VAR ref V00 this N002 ( 1, 1) [000817] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] N005 ( 1, 1) [000011] ------------ \--* CNS_INT ref null ***** BB04 STMT00091 (IL 0x01E... ???) N004 ( 4, 12) [000554] -A--G---R--- * ASG ref N003 ( 1, 1) [000553] D------N---- +--* LCL_VAR ref V34 tmp20 N002 ( 4, 12) [000538] #---G------- \--* IND ref N001 ( 2, 10) [000537] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB04 STMT00092 (IL 0x01E... ???) N004 ( 4, 12) [000556] -A--G---R--- * ASG ref N003 ( 1, 1) [000555] D------N---- +--* LCL_VAR ref V35 tmp21 N002 ( 4, 12) [000540] #---G------- \--* IND ref N001 ( 2, 10) [000539] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB04 STMT00089 (IL 0x01E... ???) N004 ( 5, 5) [000549] ------------ * JTRUE void N003 ( 3, 3) [000548] J------N---- \--* NE int N001 ( 1, 1) [000546] ------------ +--* LCL_VAR int V33 tmp19 N002 ( 1, 1) [000547] ------------ \--* CNS_INT int 0 ------------ BB05 [01E..01F), preds={BB04} succs={BB06} ***** BB05 STMT00090 (IL 0x01E... ???) N005 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 1, 1) [000550] ------------ arg0 in rcx +--* LCL_VAR ref V34 tmp20 N004 ( 1, 1) [000551] ------------ arg1 in rdx \--* LCL_VAR ref V35 tmp21 ------------ BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} ***** BB06 STMT00003 (IL 0x02C... ???) N006 ( 4, 4) [000018] -A-XG---R--- * ASG ref N005 ( 1, 1) [000017] D------N---- +--* LCL_VAR ref V04 loc0 N004 ( 4, 4) [000016] ---XG------- \--* IND ref N003 ( 2, 2) [000822] -------N---- \--* ADD byref N001 ( 1, 1) [000015] ------------ +--* LCL_VAR ref V00 this N002 ( 1, 1) [000821] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] ***** BB06 STMT00094 (IL 0x033... ???) N005 ( 6, 3) [000566] -A------R--- * ASG bool N004 ( 1, 1) [000565] D------N---- +--* LCL_VAR int V36 tmp22 N003 ( 6, 3) [000021] N----------- \--* NE int N001 ( 1, 1) [000019] ------------ +--* LCL_VAR ref V04 loc0 N002 ( 1, 1) [000020] ------------ \--* CNS_INT ref null ***** BB06 STMT00097 (IL 0x033... ???) N004 ( 4, 12) [000576] -A--G---R--- * ASG ref N003 ( 1, 1) [000575] D------N---- +--* LCL_VAR ref V37 tmp23 N002 ( 4, 12) [000562] #---G------- \--* IND ref N001 ( 2, 10) [000561] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB06 STMT00095 (IL 0x033... ???) N004 ( 5, 5) [000571] ------------ * JTRUE void N003 ( 3, 3) [000570] J------N---- \--* NE int N001 ( 1, 1) [000568] ------------ +--* LCL_VAR int V36 tmp22 N002 ( 1, 1) [000569] ------------ \--* CNS_INT int 0 ------------ BB07 [033..034), preds={BB06} succs={BB08} ***** BB07 STMT00096 (IL 0x033... ???) N006 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail N004 ( 4, 12) [000824] #---G------- arg0 in rcx +--* IND ref N003 ( 2, 10) [000823] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" N005 ( 1, 1) [000573] ------------ arg1 in rdx \--* LCL_VAR ref V37 tmp23 ------------ BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} ***** BB08 STMT00005 (IL 0x041... ???) N006 ( 4, 4) [000028] -A-XG---R--- * ASG ref N005 ( 1, 1) [000027] D------N---- +--* LCL_VAR ref V05 loc1 N004 ( 4, 4) [000026] ---XG------- \--* IND ref N003 ( 2, 2) [000828] -------N---- \--* ADD byref N001 ( 1, 1) [000025] ------------ +--* LCL_VAR ref V00 this N002 ( 1, 1) [000827] ------------ \--* CNS_INT long 24 field offset Fseq[_comparer] ***** BB08 STMT00006 (IL 0x048...0x049) N004 ( 5, 5) [000032] ------------ * JTRUE void N003 ( 3, 3) [000031] J------N---- \--* EQ int N001 ( 1, 1) [000029] ------------ +--* LCL_VAR ref V05 loc1 N002 ( 1, 1) [000030] ------------ \--* CNS_INT ref null ------------ BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} ***** BB09 STMT00079 (IL 0x04B...0x052) N004 ( 3, 3) [000489] -A-X----R--- * ASG long N003 ( 1, 1) [000488] D------N---- +--* LCL_VAR long V29 tmp15 N002 ( 3, 2) [000487] #--X-------- \--* IND long N001 ( 1, 1) [000486] !----------- \--* LCL_VAR ref V00 this ***** BB09 STMT00080 (IL ???... ???) N003 ( 5, 4) [000499] -A------R--- * ASG ref N002 ( 3, 2) [000498] D------N---- +--* LCL_VAR ref V30 tmp16 N001 ( 1, 1) [000485] ------------ \--* LCL_VAR ref V01 arg1 ***** BB09 STMT00149 (IL ???... ???) N011 ( 14, 13) [001148] ------------ * JTRUE void N010 ( 12, 11) [000505] J------N---- \--* EQ int N008 ( 10, 9) [000501] n----------- +--* IND long N007 ( 8, 7) [000497] -------N---- | \--* ADD long N005 ( 7, 6) [000495] #----------- | +--* IND long N004 ( 4, 4) [000494] #----------- | | \--* IND long N003 ( 2, 2) [000493] -------N---- | | \--* ADD long N001 ( 1, 1) [000491] ------------ | | +--* LCL_VAR long V29 tmp15 N002 ( 1, 1) [000492] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000496] ------------ | \--* CNS_INT long 64 N009 ( 1, 1) [000504] ------------ \--* CNS_INT long 0 ------------ BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} ***** BB10 STMT00150 (IL ???... ???) N010 ( 10, 9) [001150] -A------R--- * ASG long N009 ( 1, 1) [001149] D------N---- +--* LCL_VAR long V31 tmp17 N008 ( 10, 9) [000506] n-----?----- \--* IND long N007 ( 8, 7) [000507] ------?N---- \--* ADD long N005 ( 7, 6) [000508] #-----?----- +--* IND long N004 ( 4, 4) [000509] #-----?----- | \--* IND long N003 ( 2, 2) [000510] ------?N---- | \--* ADD long N001 ( 1, 1) [000511] ------?----- | +--* LCL_VAR long V29 tmp15 N002 ( 1, 1) [000512] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000513] ------?----- \--* CNS_INT long 64 ------------ BB11 [???..???), preds={BB09} succs={BB12} ***** BB11 STMT00151 (IL ???... ???) N007 ( 17, 18) [001152] -AC-G---R--- * ASG long N006 ( 1, 1) [001151] D------N---- +--* LCL_VAR long V31 tmp17 N005 ( 17, 18) [000503] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 1, 1) [000490] ------?----- arg0 in rcx +--* LCL_VAR long V29 tmp15 N004 ( 2, 10) [000502] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} ***** BB12 STMT00082 (IL ???... ???) N003 ( 5, 4) [000520] -A------R--- * ASG long N002 ( 3, 2) [000519] D------N---- +--* LCL_VAR long V32 tmp18 N001 ( 1, 1) [000518] ------------ \--* LCL_VAR long V31 tmp17 ***** BB12 STMT00083 (IL ???... ???) N010 ( 31, 15) [000524] -ACXG---R--- * ASG int N009 ( 3, 2) [000523] D------N---- +--* LCL_VAR int V15 tmp1 N008 ( 27, 12) [000522] --CXG------- \--* CALL ind stub int N007 ( 1, 1) [000521] ------------ calli tgt \--* LCL_VAR long V31 tmp17 N004 ( 1, 1) [000484] ------------ this in rcx +--* LCL_VAR ref V05 loc1 N005 ( 1, 1) [000831] ------------ arg1 in r11 +--* LCL_VAR long V31 tmp17 r11 REG r11 N006 ( 1, 1) [000500] ------------ arg2 in rdx \--* LCL_VAR ref V01 arg1 ------------ BB13 [054..061), preds={BB08} succs={BB14} ***** BB13 STMT00007 (IL 0x054...0x05C) N013 ( 34, 21) [000038] -ACXG---R--- * ASG int N012 ( 3, 2) [000037] D------N---- +--* LCL_VAR int V15 tmp1 N011 ( 30, 18) [000035] --CXG------- \--* CALLV vt-ind int System.Object.GetHashCode N010 ( 9, 8) [000843] n--X-------- control expr \--* IND long N009 ( 7, 6) [000842] ---X---N---- \--* ADD long N007 ( 6, 5) [000840] #--X-------- +--* IND long N006 ( 4, 3) [000839] ---X---N---- | \--* ADD long N004 ( 3, 2) [000837] #--X-------- | +--* IND long N003 ( 1, 1) [000836] ------------ | | \--* LCL_VAR ref V01 arg1 N005 ( 1, 1) [000838] ------------ | \--* CNS_INT int 72 N008 ( 1, 1) [000841] ------------ \--* CNS_INT int 24 N002 ( 1, 1) [000033] ------------ this in rcx \--* LCL_VAR ref V01 arg1 ------------ BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ***** BB14 STMT00008 (IL ???...0x061) N003 ( 3, 3) [000042] -A------R--- * ASG int N002 ( 1, 1) [000041] D------N---- +--* LCL_VAR int V06 loc2 N001 ( 3, 2) [000040] ------------ \--* LCL_VAR int V15 tmp1 ***** BB14 STMT00009 (IL 0x062...0x063) N003 ( 1, 3) [000045] -A------R--- * ASG int N002 ( 1, 1) [000044] D------N---- +--* LCL_VAR int V07 loc3 N001 ( 1, 1) [000043] ------------ \--* CNS_INT int 0 ***** BB14 STMT00098 (IL 0x064... ???) N006 ( 4, 4) [000580] -A-XG---R--- * ASG ref N005 ( 1, 1) [000579] D------N---- +--* LCL_VAR ref V39 tmp25 N004 ( 4, 4) [000578] ---XG------- \--* IND ref N003 ( 2, 2) [000845] -------N---- \--* ADD byref N001 ( 1, 1) [000046] ------------ +--* LCL_VAR ref V00 this N002 ( 1, 1) [000844] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] ***** BB14 STMT00105 (IL 0x064... ???) N004 ( 3, 3) [000629] -A-X----R--- * ASG int N003 ( 1, 1) [000628] D------N---- +--* LCL_VAR int V40 tmp26 N002 ( 3, 3) [000583] ---X-------- \--* ARR_LENGTH int N001 ( 1, 1) [000582] ------------ \--* LCL_VAR ref V39 tmp25 ***** BB14 STMT00106 (IL 0x064... ???) N006 ( 4, 4) [000631] -A-XG---R--- * ASG long N005 ( 1, 1) [000630] D------N---- +--* LCL_VAR long V41 tmp27 N004 ( 4, 4) [000585] ---XG------- \--* IND long N003 ( 2, 2) [000847] -------N---- \--* ADD byref N001 ( 1, 1) [000584] ------------ +--* LCL_VAR ref V00 this N002 ( 1, 1) [000846] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] ***** BB14 STMT00108 (IL 0x064... ???) N005 ( 6, 6) [000642] -A------R--- * ASG bool N004 ( 1, 1) [000641] D------N---- +--* LCL_VAR int V43 tmp29 N003 ( 6, 6) [000599] N--------U-- \--* LE int N001 ( 1, 1) [000597] ------------ +--* LCL_VAR int V40 tmp26 N002 ( 1, 4) [000598] ------------ \--* CNS_INT int 0x7FFFFFFF ***** BB14 STMT00111 (IL 0x064... ???) N004 ( 4, 12) [000652] -A--G---R--- * ASG ref N003 ( 1, 1) [000651] D------N---- +--* LCL_VAR ref V44 tmp30 N002 ( 4, 12) [000636] #---G------- \--* IND ref N001 ( 2, 10) [000635] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB14 STMT00112 (IL 0x064... ???) N004 ( 4, 12) [000654] -A--G---R--- * ASG ref N003 ( 1, 1) [000653] D------N---- +--* LCL_VAR ref V45 tmp31 N002 ( 4, 12) [000638] #---G------- \--* IND ref N001 ( 2, 10) [000637] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB14 STMT00109 (IL 0x064... ???) N004 ( 5, 5) [000647] ------------ * JTRUE void N003 ( 3, 3) [000646] J------N---- \--* NE int N001 ( 1, 1) [000644] ------------ +--* LCL_VAR int V43 tmp29 N002 ( 1, 1) [000645] ------------ \--* CNS_INT int 0 ------------ BB15 [064..065), preds={BB14} succs={BB16} ***** BB15 STMT00110 (IL 0x064... ???) N005 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 1, 1) [000648] ------------ arg0 in rcx +--* LCL_VAR ref V44 tmp30 N004 ( 1, 1) [000649] ------------ arg1 in rdx \--* LCL_VAR ref V45 tmp31 ------------ BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} ***** BB16 STMT00103 (IL 0x064... ???) N016 ( 20, 21) [000619] -A------R--- * ASG int N015 ( 1, 1) [000618] D------N---- +--* LCL_VAR int V42 tmp28 N014 ( 20, 21) [000617] ------------ \--* CAST int <- uint <- long N013 ( 19, 19) [000616] ------------ \--* RSZ long N011 ( 17, 17) [000614] ------------ +--* MUL long N008 ( 11, 11) [000611] ------------ | +--* ADD long N006 ( 9, 9) [000608] ------------ | | +--* RSZ long N004 ( 7, 7) [000606] ------------ | | | +--* MUL long N001 ( 1, 1) [000604] ------------ | | | | +--* LCL_VAR long V41 tmp27 N003 ( 2, 3) [000605] ---------U-- | | | | \--* CAST long <- ulong <- uint N002 ( 1, 1) [000047] ------------ | | | | \--* LCL_VAR int V06 loc2 N005 ( 1, 1) [000607] ------------ | | | \--* CNS_INT int 32 N007 ( 1, 1) [000610] ------------ | | \--* CNS_INT long 1 N010 ( 2, 3) [000613] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000612] ------------ | \--* LCL_VAR int V40 tmp26 N012 ( 1, 1) [000615] ------------ \--* CNS_INT int 32 ***** BB16 STMT00114 (IL 0x064... ???) N007 ( 27, 7) [000665] -A-X----R--- * ASG bool N006 ( 1, 1) [000664] D------N---- +--* LCL_VAR int V46 tmp32 N005 ( 27, 7) [000624] ---X-------- \--* EQ int N003 ( 22, 5) [000623] ---X-------- +--* UMOD int N001 ( 1, 1) [000621] ------------ | +--* LCL_VAR int V06 loc2 N002 ( 1, 1) [000622] ------------ | \--* LCL_VAR int V40 tmp26 N004 ( 1, 1) [000620] ------------ \--* LCL_VAR int V42 tmp28 ***** BB16 STMT00117 (IL 0x064... ???) N004 ( 4, 12) [000675] -A--G---R--- * ASG ref N003 ( 1, 1) [000674] D------N---- +--* LCL_VAR ref V47 tmp33 N002 ( 4, 12) [000659] #---G------- \--* IND ref N001 ( 2, 10) [000658] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB16 STMT00118 (IL 0x064... ???) N004 ( 4, 12) [000677] -A--G---R--- * ASG ref N003 ( 1, 1) [000676] D------N---- +--* LCL_VAR ref V48 tmp34 N002 ( 4, 12) [000661] #---G------- \--* IND ref N001 ( 2, 10) [000660] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB16 STMT00115 (IL 0x064... ???) N004 ( 5, 5) [000670] ------------ * JTRUE void N003 ( 3, 3) [000669] J------N---- \--* NE int N001 ( 1, 1) [000667] ------------ +--* LCL_VAR int V46 tmp32 N002 ( 1, 1) [000668] ------------ \--* CNS_INT int 0 ------------ BB17 [064..065), preds={BB16} succs={BB18} ***** BB17 STMT00116 (IL 0x064... ???) N005 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 1, 1) [000671] ------------ arg0 in rcx +--* LCL_VAR ref V47 tmp33 N004 ( 1, 1) [000672] ------------ arg1 in rdx \--* LCL_VAR ref V48 tmp34 ------------ BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} ***** BB18 STMT00100 (IL 0x064... ???) N017 ( 19, 24) [000591] -A-XG---R--- * ASG byref N016 ( 1, 1) [000590] D------N---- +--* LCL_VAR byref V38 tmp24 N015 ( 19, 24) [000862] ---XG------- \--* COMMA byref N004 ( 8, 11) [000855] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000627] ------------ | +--* LCL_VAR int V42 tmp28 N003 ( 3, 3) [000854] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000581] ------------ | \--* LCL_VAR ref V39 tmp25 N014 ( 11, 13) [000863] ----G------- \--* ADDR byref N013 ( 6, 7) [000588] a---G--N---- \--* IND int N012 ( 5, 6) [000861] -------N---- \--* ADD byref N005 ( 1, 1) [000852] ------------ +--* LCL_VAR ref V39 tmp25 N011 ( 4, 5) [000860] -------N---- \--* ADD long N009 ( 3, 4) [000858] -------N---- +--* LSH long N007 ( 2, 3) [000856] ------------ | +--* CAST long <- int N006 ( 1, 1) [000853] i----------- | | \--* LCL_VAR int V42 tmp28 N008 ( 1, 1) [000857] -------N---- | \--* CNS_INT long 2 N010 ( 1, 1) [000859] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB18 STMT00101 (IL 0x064... ???) N003 ( 1, 3) [000595] -A------R--- * ASG ref N002 ( 1, 1) [000594] D------N---- +--* LCL_VAR ref V39 tmp25 N001 ( 1, 1) [000593] ------------ \--* CNS_INT ref null ***** BB18 STMT00011 (IL ???... ???) N003 ( 5, 4) [000051] -A------R--- * ASG byref N002 ( 3, 2) [000050] D------N---- +--* LCL_VAR byref V08 loc4 N001 ( 1, 1) [000592] ------------ \--* LCL_VAR byref V38 tmp24 ***** BB18 STMT00012 (IL 0x06D...0x072) N006 ( 5, 4) [000057] -A-XG---R--- * ASG int N005 ( 1, 1) [000056] D------N---- +--* LCL_VAR int V09 loc5 N004 ( 5, 4) [000055] ---XG------- \--* ADD int N002 ( 3, 2) [000053] *--XG------- +--* IND int N001 ( 1, 1) [000052] ------------ | \--* LCL_VAR byref V38 tmp24 N003 ( 1, 1) [000054] ------------ \--* CNS_INT int -1 ***** BB18 STMT00013 (IL 0x074...0x075) N004 ( 5, 5) [000061] ------------ * JTRUE void N003 ( 3, 3) [000060] J------N---- \--* NE int N001 ( 1, 1) [000058] ------------ +--* LCL_VAR ref V05 loc1 N002 ( 1, 1) [000059] ------------ \--* CNS_INT ref null ------------ BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} ***** BB19 STMT00059 (IL 0x0FF...0x104) N004 ( 3, 3) [000356] -A-X----R--- * ASG long N003 ( 1, 1) [000355] D------N---- +--* LCL_VAR long V24 tmp10 N002 ( 3, 2) [000354] #--X-------- \--* IND long N001 ( 1, 1) [000353] !----------- \--* LCL_VAR ref V00 this ***** BB19 STMT00152 (IL ???... ???) N011 ( 14, 13) [001153] ------------ * JTRUE void N010 ( 12, 11) [000369] J------N---- \--* EQ int N008 ( 10, 9) [000365] n----------- +--* IND long N007 ( 8, 7) [000364] -------N---- | \--* ADD long N005 ( 7, 6) [000362] #----------- | +--* IND long N004 ( 4, 4) [000361] #----------- | | \--* IND long N003 ( 2, 2) [000360] -------N---- | | \--* ADD long N001 ( 1, 1) [000358] ------------ | | +--* LCL_VAR long V24 tmp10 N002 ( 1, 1) [000359] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000363] ------------ | \--* CNS_INT long 32 N009 ( 1, 1) [000368] ------------ \--* CNS_INT long 0 ------------ BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} ***** BB20 STMT00153 (IL ???... ???) N010 ( 14, 12) [001155] -A------R--- * ASG long N009 ( 3, 2) [001154] D------N---- +--* LCL_VAR long V25 tmp11 N008 ( 10, 9) [000370] n-----?----- \--* IND long N007 ( 8, 7) [000371] ------?N---- \--* ADD long N005 ( 7, 6) [000372] #-----?----- +--* IND long N004 ( 4, 4) [000373] #-----?----- | \--* IND long N003 ( 2, 2) [000374] ------?N---- | \--* ADD long N001 ( 1, 1) [000375] ------?----- | +--* LCL_VAR long V24 tmp10 N002 ( 1, 1) [000376] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000377] ------?----- \--* CNS_INT long 32 ------------ BB21 [???..???), preds={BB19} succs={BB22} ***** BB21 STMT00154 (IL ???... ???) N007 ( 21, 21) [001157] -AC-G---R--- * ASG long N006 ( 3, 2) [001156] D------N---- +--* LCL_VAR long V25 tmp11 N005 ( 17, 18) [000367] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 1, 1) [000357] ------?----- arg0 in rcx +--* LCL_VAR long V24 tmp10 N004 ( 2, 10) [000366] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB22 [???..106), preds={BB20,BB21} succs={BB23} ***** BB22 STMT00062 (IL ???... ???) N005 ( 17, 8) [000386] -ACXG---R--- * ASG ref N004 ( 1, 1) [000385] D------N---- +--* LCL_VAR ref V12 loc8 N003 ( 17, 8) [000352] --CXG------- \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default N002 ( 3, 2) [000382] ------------ arg0 in rcx \--* LCL_VAR long V25 tmp11 ------------ BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} ***** BB23 STMT00063 (IL 0x106...0x10B) N005 ( 7, 7) [000391] ---X-------- * JTRUE void N004 ( 5, 5) [000390] N--X---N-U-- \--* LE int N002 ( 3, 3) [000389] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000388] ------------ | \--* LCL_VAR ref V04 loc0 N003 ( 1, 1) [000387] ------------ \--* LCL_VAR int V09 loc5 ------------ BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} ***** BB24 STMT00064 (IL 0x110...0x11E) N023 ( 36, 39) [000399] ---XG------- * JTRUE void N022 ( 34, 37) [000398] N--XG--N-U-- \--* NE int N020 ( 32, 35) [000396] *--XG------- +--* IND int N019 ( 30, 33) [000868] ---XG--N---- | \--* ADD byref N017 ( 29, 32) [000879] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000872] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000393] ------------ | | | +--* LCL_VAR int V09 loc5 N003 ( 3, 3) [000871] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000392] ------------ | | | \--* LCL_VAR ref V04 loc0 N016 ( 21, 21) [000882] ----G------- | | \--* ADDR byref N015 ( 11, 11) [000394] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000878] -------N---- | | \--* ADD byref N005 ( 1, 1) [000869] ------------ | | +--* LCL_VAR ref V04 loc0 N013 ( 9, 9) [000877] -------N---- | | \--* ADD long N011 ( 8, 8) [000875] -------N---- | | +--* LSH long N009 ( 7, 7) [000881] ------------ | | | +--* MUL long N007 ( 2, 3) [000873] ------------ | | | | +--* CAST long <- int N006 ( 1, 1) [000870] i----------- | | | | | \--* LCL_VAR int V09 loc5 N008 ( 1, 1) [000880] ------------ | | | | \--* CNS_INT long 3 N010 ( 1, 1) [000874] -------N---- | | | \--* CNS_INT long 3 N012 ( 1, 1) [000876] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000867] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] N021 ( 1, 1) [000397] ------------ \--* LCL_VAR int V06 loc2 ------------ BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} ***** BB25 STMT00069 (IL 0x120...0x135) N035 ( 67, 59) [000428] --CXG------- * JTRUE void N034 ( 65, 57) [000427] J-CXG--N---- \--* NE int N032 ( 63, 55) [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals N031 ( 9, 8) [000908] n--X-------- control expr | \--* IND long N030 ( 7, 6) [000907] ---X---N---- | \--* ADD long N028 ( 6, 5) [000905] #--X-------- | +--* IND long N027 ( 4, 3) [000904] ---X---N---- | | \--* ADD long N025 ( 3, 2) [000902] #--X-------- | | +--* IND long N024 ( 1, 1) [000901] ------------ | | | \--* LCL_VAR ref V12 loc8 N026 ( 1, 1) [000903] ------------ | | \--* CNS_INT int 72 N029 ( 1, 1) [000906] ------------ | \--* CNS_INT int 32 N021 ( 32, 34) [000893] ---XG------- arg1 in rdx | +--* COMMA ref N007 ( 8, 11) [000886] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N004 ( 1, 1) [000420] ------------ | | | +--* LCL_VAR int V09 loc5 N006 ( 3, 3) [000885] ---X-------- | | | \--* ARR_LENGTH int N005 ( 1, 1) [000419] ------------ | | | \--* LCL_VAR ref V04 loc0 N020 ( 24, 23) [000897] *---G------- | | \--* IND ref N019 ( 21, 21) [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] N018 ( 11, 11) [000421] a---G--N---- | | \--* IND struct N017 ( 10, 10) [000892] -------N---- | | \--* ADD byref N008 ( 1, 1) [000883] ------------ | | +--* LCL_VAR ref V04 loc0 N016 ( 9, 9) [000891] -------N---- | | \--* ADD long N014 ( 8, 8) [000889] -------N---- | | +--* LSH long N012 ( 7, 7) [000895] ------------ | | | +--* MUL long N010 ( 2, 3) [000887] ------------ | | | | +--* CAST long <- int N009 ( 1, 1) [000884] i----------- | | | | | \--* LCL_VAR int V09 loc5 N011 ( 1, 1) [000894] ------------ | | | | \--* CNS_INT long 3 N013 ( 1, 1) [000888] -------N---- | | | \--* CNS_INT long 3 N015 ( 1, 1) [000890] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N022 ( 1, 1) [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 N023 ( 1, 1) [000424] ------------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 N033 ( 1, 1) [000426] ------------ \--* CNS_INT int 0 ------------ BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} ***** BB26 STMT00065 (IL 0x157...0x164) N022 ( 32, 35) [000406] -A-XG---R--- * ASG int N021 ( 1, 1) [000405] D------N---- +--* LCL_VAR int V09 loc5 N020 ( 32, 35) [000404] *--XG------- \--* IND int N019 ( 30, 33) [000932] ---XG--N---- \--* ADD byref N017 ( 29, 32) [000943] ---XG------- +--* COMMA byref N004 ( 8, 11) [000936] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000401] ------------ | | +--* LCL_VAR int V09 loc5 N003 ( 3, 3) [000935] ---X-------- | | \--* ARR_LENGTH int N002 ( 1, 1) [000400] ------------ | | \--* LCL_VAR ref V04 loc0 N016 ( 21, 21) [000946] ----G------- | \--* ADDR byref N015 ( 11, 11) [000402] a---G--N---- | \--* IND struct N014 ( 10, 10) [000942] -------N---- | \--* ADD byref N005 ( 1, 1) [000933] ------------ | +--* LCL_VAR ref V04 loc0 N013 ( 9, 9) [000941] -------N---- | \--* ADD long N011 ( 8, 8) [000939] -------N---- | +--* LSH long N009 ( 7, 7) [000945] ------------ | | +--* MUL long N007 ( 2, 3) [000937] ------------ | | | +--* CAST long <- int N006 ( 1, 1) [000934] i----------- | | | | \--* LCL_VAR int V09 loc5 N008 ( 1, 1) [000944] ------------ | | | \--* CNS_INT long 3 N010 ( 1, 1) [000938] -------N---- | | \--* CNS_INT long 3 N012 ( 1, 1) [000940] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000931] ------------ \--* CNS_INT long 20 field offset Fseq[next] ***** BB26 STMT00066 (IL 0x166...0x169) N005 ( 3, 3) [000411] -A------R--- * ASG int N004 ( 1, 1) [000410] D------N---- +--* LCL_VAR int V07 loc3 N003 ( 3, 3) [000409] ------------ \--* ADD int N001 ( 1, 1) [000407] ------------ +--* LCL_VAR int V07 loc3 N002 ( 1, 1) [000408] ------------ \--* CNS_INT int 1 ***** BB26 STMT00067 (IL 0x16A...0x16E) N005 ( 7, 7) [000416] ---X-------- * JTRUE void N004 ( 5, 5) [000415] N--X---N-U-- \--* LT int N002 ( 3, 3) [000414] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000413] ------------ | \--* LCL_VAR ref V04 loc0 N003 ( 1, 1) [000412] ------------ \--* LCL_VAR int V07 loc3 ------------ BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} ------------ BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} ***** BB28 STMT00070 (IL 0x137...0x139) N005 ( 7, 8) [000432] ------------ * JTRUE void N004 ( 5, 6) [000431] N------N-U-- \--* NE int N002 ( 3, 4) [000909] ------------ +--* CAST int <- ubyte <- int N001 ( 2, 2) [000429] ------------ | \--* LCL_VAR int V03 arg3 N003 ( 1, 1) [000430] ------------ \--* CNS_INT int 1 ------------ BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} ***** BB29 STMT00077 (IL 0x13B...0x144) N022 ( 34, 37) [000481] -A-XG------- * ASG ref N020 ( 32, 35) [000480] *--XG--N---- +--* IND ref N019 ( 30, 33) [000911] ---XG--N---- | \--* ADD byref N017 ( 29, 32) [000922] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000915] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000476] ------------ | | | +--* LCL_VAR int V09 loc5 N003 ( 3, 3) [000914] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000475] ------------ | | | \--* LCL_VAR ref V04 loc0 N016 ( 21, 21) [000925] ----G------- | | \--* ADDR byref N015 ( 11, 11) [000477] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000921] -------N---- | | \--* ADD byref N005 ( 1, 1) [000912] ------------ | | +--* LCL_VAR ref V04 loc0 N013 ( 9, 9) [000920] -------N---- | | \--* ADD long N011 ( 8, 8) [000918] -------N---- | | +--* LSH long N009 ( 7, 7) [000924] ------------ | | | +--* MUL long N007 ( 2, 3) [000916] ------------ | | | | +--* CAST long <- int N006 ( 1, 1) [000913] i----------- | | | | | \--* LCL_VAR int V09 loc5 N008 ( 1, 1) [000923] ------------ | | | | \--* CNS_INT long 3 N010 ( 1, 1) [000917] -------N---- | | | \--* CNS_INT long 3 N012 ( 1, 1) [000919] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000910] ------------ | \--* CNS_INT long 8 field offset Fseq[value] N021 ( 1, 1) [000479] ------------ \--* LCL_VAR ref V02 arg2 ------------ BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} ***** BB30 STMT00071 (IL 0x14B...0x14D) N005 ( 7, 8) [000436] ------------ * JTRUE void N004 ( 5, 6) [000435] N------N-U-- \--* EQ int N002 ( 3, 4) [000926] ------------ +--* CAST int <- ubyte <- int N001 ( 2, 2) [000433] ------------ | \--* LCL_VAR int V03 arg3 N003 ( 1, 1) [000434] ------------ \--* CNS_INT int 2 ------------ BB31 [???..???) (return), preds={BB30,BB41} succs={} ***** BB31 STMT00148 (IL ???... ???) N002 ( 2, 2) [000811] ------------ * RETURN int N001 ( 1, 1) [000437] ------------ \--* CNS_INT int 0 ------------ BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} ***** BB32 STMT00014 (IL 0x177...0x17C) N005 ( 7, 7) [000066] ---X-------- * JTRUE void N004 ( 5, 5) [000065] N--X---N-U-- \--* LE int N002 ( 3, 3) [000064] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000063] ------------ | \--* LCL_VAR ref V04 loc0 N003 ( 1, 1) [000062] ------------ \--* LCL_VAR int V09 loc5 ------------ BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} ***** BB33 STMT00039 (IL 0x17E...0x18C) N023 ( 36, 39) [000215] ---XG------- * JTRUE void N022 ( 34, 37) [000214] N--XG--N-U-- \--* NE int N020 ( 32, 35) [000212] *--XG------- +--* IND int N019 ( 30, 33) [000948] ---XG--N---- | \--* ADD byref N017 ( 29, 32) [000959] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000952] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000209] ------------ | | | +--* LCL_VAR int V09 loc5 N003 ( 3, 3) [000951] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000208] ------------ | | | \--* LCL_VAR ref V04 loc0 N016 ( 21, 21) [000962] ----G------- | | \--* ADDR byref N015 ( 11, 11) [000210] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000958] -------N---- | | \--* ADD byref N005 ( 1, 1) [000949] ------------ | | +--* LCL_VAR ref V04 loc0 N013 ( 9, 9) [000957] -------N---- | | \--* ADD long N011 ( 8, 8) [000955] -------N---- | | +--* LSH long N009 ( 7, 7) [000961] ------------ | | | +--* MUL long N007 ( 2, 3) [000953] ------------ | | | | +--* CAST long <- int N006 ( 1, 1) [000950] i----------- | | | | | \--* LCL_VAR int V09 loc5 N008 ( 1, 1) [000960] ------------ | | | | \--* CNS_INT long 3 N010 ( 1, 1) [000954] -------N---- | | | \--* CNS_INT long 3 N012 ( 1, 1) [000956] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000947] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] N021 ( 1, 1) [000213] ------------ \--* LCL_VAR int V06 loc2 ------------ BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} ***** BB34 STMT00045 (IL 0x18E...0x1A2) N020 ( 32, 34) [000246] -A-XG---R--- * ASG ref N019 ( 1, 1) [000245] D------N---- +--* LCL_VAR ref V17 tmp3 N018 ( 32, 34) [000973] ---XG------- \--* COMMA ref N004 ( 8, 11) [000966] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000236] ------------ | +--* LCL_VAR int V09 loc5 N003 ( 3, 3) [000965] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000235] ------------ | \--* LCL_VAR ref V04 loc0 N017 ( 24, 23) [000977] *---G------- \--* IND ref N016 ( 21, 21) [000976] ----G------- \--* ADDR byref Zero Fseq[key] N015 ( 11, 11) [000237] a---G--N---- \--* IND struct N014 ( 10, 10) [000972] -------N---- \--* ADD byref N005 ( 1, 1) [000963] ------------ +--* LCL_VAR ref V04 loc0 N013 ( 9, 9) [000971] -------N---- \--* ADD long N011 ( 8, 8) [000969] -------N---- +--* LSH long N009 ( 7, 7) [000975] ------------ | +--* MUL long N007 ( 2, 3) [000967] ------------ | | +--* CAST long <- int N006 ( 1, 1) [000964] i----------- | | | \--* LCL_VAR int V09 loc5 N008 ( 1, 1) [000974] ------------ | | \--* CNS_INT long 3 N010 ( 1, 1) [000968] -------N---- | \--* CNS_INT long 3 N012 ( 1, 1) [000970] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB34 STMT00044 (IL 0x18E... ???) N004 ( 3, 3) [000244] -A-X----R--- * ASG long N003 ( 1, 1) [000243] D------N---- +--* LCL_VAR long V16 tmp2 N002 ( 3, 2) [000242] #--X-------- \--* IND long N001 ( 1, 1) [000241] !----------- \--* LCL_VAR ref V00 this ***** BB34 STMT00046 (IL ???... ???) N003 ( 1, 3) [000257] -A------R--- * ASG ref N002 ( 1, 1) [000256] D------N---- +--* LCL_VAR ref V18 tmp4 N001 ( 1, 1) [000240] ------------ \--* LCL_VAR ref V01 arg1 ***** BB34 STMT00158 (IL ???... ???) N011 ( 14, 13) [001163] ------------ * JTRUE void N010 ( 12, 11) [000263] J------N---- \--* EQ int N008 ( 10, 9) [000259] n----------- +--* IND long N007 ( 8, 7) [000255] -------N---- | \--* ADD long N005 ( 7, 6) [000253] #----------- | +--* IND long N004 ( 4, 4) [000252] #----------- | | \--* IND long N003 ( 2, 2) [000251] -------N---- | | \--* ADD long N001 ( 1, 1) [000249] ------------ | | +--* LCL_VAR long V16 tmp2 N002 ( 1, 1) [000250] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000254] ------------ | \--* CNS_INT long 48 N009 ( 1, 1) [000262] ------------ \--* CNS_INT long 0 ------------ BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} ***** BB35 STMT00159 (IL ???... ???) N010 ( 10, 9) [001165] -A------R--- * ASG long N009 ( 1, 1) [001164] D------N---- +--* LCL_VAR long V19 tmp5 N008 ( 10, 9) [000264] n-----?----- \--* IND long N007 ( 8, 7) [000265] ------?N---- \--* ADD long N005 ( 7, 6) [000266] #-----?----- +--* IND long N004 ( 4, 4) [000267] #-----?----- | \--* IND long N003 ( 2, 2) [000268] ------?N---- | \--* ADD long N001 ( 1, 1) [000269] ------?----- | +--* LCL_VAR long V16 tmp2 N002 ( 1, 1) [000270] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000271] ------?----- \--* CNS_INT long 48 ------------ BB36 [???..???), preds={BB34} succs={BB37} ***** BB36 STMT00160 (IL ???... ???) N007 ( 17, 18) [001167] -AC-G---R--- * ASG long N006 ( 1, 1) [001166] D------N---- +--* LCL_VAR long V19 tmp5 N005 ( 17, 18) [000261] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 1, 1) [000248] ------?----- arg0 in rcx +--* LCL_VAR long V16 tmp2 N004 ( 2, 10) [000260] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} ***** BB37 STMT00048 (IL ???... ???) N003 ( 1, 3) [000278] -A------R--- * ASG long N002 ( 1, 1) [000277] D------N---- +--* LCL_VAR long V20 tmp6 N001 ( 1, 1) [000276] ------------ \--* LCL_VAR long V19 tmp5 ***** BB37 STMT00049 (IL ???... ???) N013 ( 32, 18) [000283] --CXG------- * JTRUE void N012 ( 30, 16) [000282] J-CXG--N---- \--* EQ int N010 ( 28, 14) [000280] --CXG------- +--* CALL ind stub int N009 ( 1, 1) [000279] ------------ calli tgt | \--* LCL_VAR long V19 tmp5 N005 ( 1, 1) [000234] ------------ this in rcx | +--* LCL_VAR ref V05 loc1 N006 ( 1, 1) [000980] ------------ arg1 in r11 | +--* LCL_VAR long V19 tmp5 r11 REG r11 N007 ( 1, 1) [000247] ------------ arg2 in rdx | +--* LCL_VAR ref V17 tmp3 N008 ( 1, 1) [000258] ------------ arg3 in r8 | \--* LCL_VAR ref V01 arg1 N011 ( 1, 1) [000281] ------------ \--* CNS_INT int 0 ------------ BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} ***** BB38 STMT00050 (IL 0x1A4...0x1A6) N005 ( 7, 8) [000287] ------------ * JTRUE void N004 ( 5, 6) [000286] N------N-U-- \--* NE int N002 ( 3, 4) [000985] ------------ +--* CAST int <- ubyte <- int N001 ( 2, 2) [000284] ------------ | \--* LCL_VAR int V03 arg3 N003 ( 1, 1) [000285] ------------ \--* CNS_INT int 1 ------------ BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} ***** BB39 STMT00057 (IL 0x1A8...0x1B1) N022 ( 34, 37) [000336] -A-XG------- * ASG ref N020 ( 32, 35) [000335] *--XG--N---- +--* IND ref N019 ( 30, 33) [000987] ---XG--N---- | \--* ADD byref N017 ( 29, 32) [000998] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000991] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000331] ------------ | | | +--* LCL_VAR int V09 loc5 N003 ( 3, 3) [000990] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000330] ------------ | | | \--* LCL_VAR ref V04 loc0 N016 ( 21, 21) [001001] ----G------- | | \--* ADDR byref N015 ( 11, 11) [000332] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000997] -------N---- | | \--* ADD byref N005 ( 1, 1) [000988] ------------ | | +--* LCL_VAR ref V04 loc0 N013 ( 9, 9) [000996] -------N---- | | \--* ADD long N011 ( 8, 8) [000994] -------N---- | | +--* LSH long N009 ( 7, 7) [001000] ------------ | | | +--* MUL long N007 ( 2, 3) [000992] ------------ | | | | +--* CAST long <- int N006 ( 1, 1) [000989] i----------- | | | | | \--* LCL_VAR int V09 loc5 N008 ( 1, 1) [000999] ------------ | | | | \--* CNS_INT long 3 N010 ( 1, 1) [000993] -------N---- | | | \--* CNS_INT long 3 N012 ( 1, 1) [000995] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000986] ------------ | \--* CNS_INT long 8 field offset Fseq[value] N021 ( 1, 1) [000334] ------------ \--* LCL_VAR ref V02 arg2 ------------ BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} ***** BB40 STMT00051 (IL 0x1B8...0x1BA) N005 ( 7, 8) [000291] ------------ * JTRUE void N004 ( 5, 6) [000290] N------N-U-- \--* EQ int N002 ( 3, 4) [001002] ------------ +--* CAST int <- ubyte <- int N001 ( 2, 2) [000288] ------------ | \--* LCL_VAR int V03 arg3 N003 ( 1, 1) [000289] ------------ \--* CNS_INT int 2 ------------ BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} ------------ BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} ***** BB42 STMT00040 (IL 0x1C4...0x1D1) N022 ( 32, 35) [000222] -A-XG---R--- * ASG int N021 ( 1, 1) [000221] D------N---- +--* LCL_VAR int V09 loc5 N020 ( 32, 35) [000220] *--XG------- \--* IND int N019 ( 30, 33) [001009] ---XG--N---- \--* ADD byref N017 ( 29, 32) [001020] ---XG------- +--* COMMA byref N004 ( 8, 11) [001013] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000217] ------------ | | +--* LCL_VAR int V09 loc5 N003 ( 3, 3) [001012] ---X-------- | | \--* ARR_LENGTH int N002 ( 1, 1) [000216] ------------ | | \--* LCL_VAR ref V04 loc0 N016 ( 21, 21) [001023] ----G------- | \--* ADDR byref N015 ( 11, 11) [000218] a---G--N---- | \--* IND struct N014 ( 10, 10) [001019] -------N---- | \--* ADD byref N005 ( 1, 1) [001010] ------------ | +--* LCL_VAR ref V04 loc0 N013 ( 9, 9) [001018] -------N---- | \--* ADD long N011 ( 8, 8) [001016] -------N---- | +--* LSH long N009 ( 7, 7) [001022] ------------ | | +--* MUL long N007 ( 2, 3) [001014] ------------ | | | +--* CAST long <- int N006 ( 1, 1) [001011] i----------- | | | | \--* LCL_VAR int V09 loc5 N008 ( 1, 1) [001021] ------------ | | | \--* CNS_INT long 3 N010 ( 1, 1) [001015] -------N---- | | \--* CNS_INT long 3 N012 ( 1, 1) [001017] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [001008] ------------ \--* CNS_INT long 20 field offset Fseq[next] ***** BB42 STMT00041 (IL 0x1D3...0x1D6) N005 ( 3, 3) [000227] -A------R--- * ASG int N004 ( 1, 1) [000226] D------N---- +--* LCL_VAR int V07 loc3 N003 ( 3, 3) [000225] ------------ \--* ADD int N001 ( 1, 1) [000223] ------------ +--* LCL_VAR int V07 loc3 N002 ( 1, 1) [000224] ------------ \--* CNS_INT int 1 ***** BB42 STMT00042 (IL 0x1D7...0x1DB) N005 ( 7, 7) [000232] ---X-------- * JTRUE void N004 ( 5, 5) [000231] N--X---N-U-- \--* LT int N002 ( 3, 3) [000230] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000229] ------------ | \--* LCL_VAR ref V04 loc0 N003 ( 1, 1) [000228] ------------ \--* LCL_VAR int V07 loc3 ------------ BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} ------------ BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} ***** BB44 STMT00015 (IL 0x1E4...0x1EB) N007 ( 8, 8) [000071] ---XG------- * JTRUE void N006 ( 6, 6) [000070] J--XG--N---- \--* LE int N004 ( 4, 4) [000068] ---XG------- +--* IND int N003 ( 2, 2) [001025] -------N---- | \--* ADD byref N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR ref V00 this N002 ( 1, 1) [001024] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] N005 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 ------------ BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} ***** BB45 STMT00035 (IL 0x1ED...0x1F3) N006 ( 8, 7) [000174] -A-XG---R--- * ASG int N005 ( 3, 2) [000173] D------N---- +--* LCL_VAR int V10 loc6 N004 ( 4, 4) [000172] ---XG------- \--* IND int N003 ( 2, 2) [001027] -------N---- \--* ADD byref N001 ( 1, 1) [000171] ------------ +--* LCL_VAR ref V00 this N002 ( 1, 1) [001026] ------------ \--* CNS_INT long 60 field offset Fseq[_freeList] ***** BB45 STMT00120 (IL 0x1F5... ???) N034 ( 48, 47) [000688] -A-XG---R--- * ASG bool N033 ( 3, 2) [000687] D------N---- +--* LCL_VAR int V49 tmp35 N032 ( 44, 44) [000184] -A-XG------- \--* GE int N030 ( 39, 42) [000182] -A-XG------- +--* ADD int N028 ( 37, 40) [001050] -A-XG------- | +--* NEG int N027 ( 36, 39) [000181] *A-XG------- | | \--* IND int N026 ( 34, 37) [001029] -A-XG--N---- | | \--* ADD byref N024 ( 33, 36) [001044] -A-XG------- | | +--* COMMA byref N006 ( 4, 4) [001032] -A-XG---R--- | | | +--* ASG int N005 ( 1, 1) [001031] D------N---- | | | | +--* LCL_VAR int V62 tmp48 N004 ( 4, 4) [000178] ---XG------- | | | | \--* IND int N003 ( 2, 2) [001046] -------N---- | | | | \--* ADD byref N001 ( 1, 1) [000177] ------------ | | | | +--* LCL_VAR ref V00 this N002 ( 1, 1) [001045] ------------ | | | | \--* CNS_INT long 60 field offset Fseq[_freeList] N023 ( 29, 32) [001043] ---XG------- | | | \--* COMMA byref N010 ( 8, 11) [001036] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [001033] ------------ | | | | +--* LCL_VAR int V62 tmp48 N009 ( 3, 3) [001035] ---X-------- | | | | \--* ARR_LENGTH int N008 ( 1, 1) [000176] ------------ | | | | \--* LCL_VAR ref V04 loc0 N022 ( 21, 21) [001049] ----G------- | | | \--* ADDR byref N021 ( 11, 11) [000179] a---G--N---- | | | \--* IND struct N020 ( 10, 10) [001042] -------N---- | | | \--* ADD byref N011 ( 1, 1) [001030] ------------ | | | +--* LCL_VAR ref V04 loc0 N019 ( 9, 9) [001041] -------N---- | | | \--* ADD long N017 ( 8, 8) [001039] -------N---- | | | +--* LSH long N015 ( 7, 7) [001048] ------------ | | | | +--* MUL long N013 ( 2, 3) [001037] ------------ | | | | | +--* CAST long <- int N012 ( 1, 1) [001034] i----------- | | | | | | \--* LCL_VAR int V62 tmp48 N014 ( 1, 1) [001047] ------------ | | | | | \--* CNS_INT long 3 N016 ( 1, 1) [001038] -------N---- | | | | \--* CNS_INT long 3 N018 ( 1, 1) [001040] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] N025 ( 1, 1) [001028] ------------ | | \--* CNS_INT long 20 field offset Fseq[next] N029 ( 1, 1) [000175] ------------ | \--* CNS_INT int -3 N031 ( 1, 1) [000183] ------------ \--* CNS_INT int -1 ***** BB45 STMT00123 (IL 0x1F5... ???) N004 ( 8, 15) [000698] -A--G---R--- * ASG ref N003 ( 3, 2) [000697] D------N---- +--* LCL_VAR ref V50 tmp36 N002 ( 4, 12) [000684] #---G------- \--* IND ref N001 ( 2, 10) [000683] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB45 STMT00121 (IL 0x1F5... ???) N004 ( 7, 6) [000693] ------------ * JTRUE void N003 ( 5, 4) [000692] J------N---- \--* NE int N001 ( 3, 2) [000690] ------------ +--* LCL_VAR int V49 tmp35 N002 ( 1, 1) [000691] ------------ \--* CNS_INT int 0 ------------ BB46 [1F5..1F6), preds={BB45} succs={BB47} ***** BB46 STMT00122 (IL 0x1F5... ???) N006 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail N004 ( 4, 12) [001052] #---G------- arg0 in rcx +--* IND ref N003 ( 2, 10) [001051] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" N005 ( 3, 2) [000695] ------------ arg1 in rdx \--* LCL_VAR ref V50 tmp36 ------------ BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} ***** BB47 STMT00037 (IL 0x219... ???) N035 ( 44, 47) [000200] -A-XG------- * ASG int N004 ( 4, 4) [000199] ---XG--N---- +--* IND int N003 ( 2, 2) [001056] -------N---- | \--* ADD byref N001 ( 1, 1) [000190] ------------ | +--* LCL_VAR ref V00 this N002 ( 1, 1) [001055] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] N034 ( 39, 42) [000198] -A-XG------- \--* ADD int N032 ( 37, 40) [001079] -A-XG------- +--* NEG int N031 ( 36, 39) [000197] *A-XG------- | \--* IND int N030 ( 34, 37) [001058] -A-XG--N---- | \--* ADD byref N028 ( 33, 36) [001073] -A-XG------- | +--* COMMA byref N010 ( 4, 4) [001061] -A-XG---R--- | | +--* ASG int N009 ( 1, 1) [001060] D------N---- | | | +--* LCL_VAR int V63 tmp49 N008 ( 4, 4) [000194] ---XG------- | | | \--* IND int N007 ( 2, 2) [001075] -------N---- | | | \--* ADD byref N005 ( 1, 1) [000193] ------------ | | | +--* LCL_VAR ref V00 this N006 ( 1, 1) [001074] ------------ | | | \--* CNS_INT long 60 field offset Fseq[_freeList] N027 ( 29, 32) [001072] ---XG------- | | \--* COMMA byref N014 ( 8, 11) [001065] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N011 ( 1, 1) [001062] ------------ | | | +--* LCL_VAR int V63 tmp49 N013 ( 3, 3) [001064] ---X-------- | | | \--* ARR_LENGTH int N012 ( 1, 1) [000192] ------------ | | | \--* LCL_VAR ref V04 loc0 N026 ( 21, 21) [001078] ----G------- | | \--* ADDR byref N025 ( 11, 11) [000195] a---G--N---- | | \--* IND struct N024 ( 10, 10) [001071] -------N---- | | \--* ADD byref N015 ( 1, 1) [001059] ------------ | | +--* LCL_VAR ref V04 loc0 N023 ( 9, 9) [001070] -------N---- | | \--* ADD long N021 ( 8, 8) [001068] -------N---- | | +--* LSH long N019 ( 7, 7) [001077] ------------ | | | +--* MUL long N017 ( 2, 3) [001066] ------------ | | | | +--* CAST long <- int N016 ( 1, 1) [001063] i----------- | | | | | \--* LCL_VAR int V63 tmp49 N018 ( 1, 1) [001076] ------------ | | | | \--* CNS_INT long 3 N020 ( 1, 1) [001067] -------N---- | | | \--* CNS_INT long 3 N022 ( 1, 1) [001069] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N029 ( 1, 1) [001057] ------------ | \--* CNS_INT long 20 field offset Fseq[next] N033 ( 1, 1) [000191] ------------ \--* CNS_INT int -3 ***** BB47 STMT00038 (IL 0x233...0x23C) N011 ( 11, 11) [000207] -A-XG---R--- * ASG int N010 ( 4, 4) [000206] ---XG--N---- +--* IND int N009 ( 2, 2) [001081] -------N---- | \--* ADD byref N007 ( 1, 1) [000201] ------------ | +--* LCL_VAR ref V00 this N008 ( 1, 1) [001080] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] N006 ( 6, 6) [000205] ---XG------- \--* ADD int N004 ( 4, 4) [000203] ---XG------- +--* IND int N003 ( 2, 2) [001083] -------N---- | \--* ADD byref N001 ( 1, 1) [000202] ------------ | +--* LCL_VAR ref V00 this N002 ( 1, 1) [001082] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] N005 ( 1, 1) [000204] ------------ \--* CNS_INT int -1 ------------ BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} ***** BB48 STMT00016 (IL 0x243...0x249) N006 ( 8, 7) [000075] -A-XG---R--- * ASG int N005 ( 3, 2) [000074] D------N---- +--* LCL_VAR int V13 loc9 N004 ( 4, 4) [000073] ---XG------- \--* IND int N003 ( 2, 2) [001085] -------N---- \--* ADD byref N001 ( 1, 1) [000072] ------------ +--* LCL_VAR ref V00 this N002 ( 1, 1) [001084] ------------ \--* CNS_INT long 56 field offset Fseq[_count] ***** BB48 STMT00017 (IL 0x24B...0x250) N005 ( 9, 8) [000080] ---X-------- * JTRUE void N004 ( 7, 6) [000079] N--X---N-U-- \--* NE int N002 ( 3, 3) [000078] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000077] ------------ | \--* LCL_VAR ref V04 loc0 N003 ( 3, 2) [000076] ------------ \--* LCL_VAR int V13 loc9 ------------ BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00125 (IL 0x252... ???) N014 ( 44, 26) [000705] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize N009 ( 22, 13) [001090] -ACXG---R-L- arg1 SETUP +--* ASG int N008 ( 3, 2) [001089] D------N---- | +--* LCL_VAR int V64 tmp50 N007 ( 18, 10) [000702] --CXG------- | \--* CALL int System.Collections.HashHelpers.ExpandPrime N006 ( 4, 4) [000701] ---XG------- arg0 in rcx | \--* IND int N005 ( 2, 2) [001087] -------N---- | \--* ADD byref N003 ( 1, 1) [000700] ------------ | +--* LCL_VAR ref V00 this N004 ( 1, 1) [001086] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] N011 ( 3, 2) [001091] ------------ arg1 in rdx +--* LCL_VAR int V64 tmp50 N012 ( 1, 1) [000163] ------------ this in rcx +--* LCL_VAR ref V00 this N013 ( 1, 1) [000704] ------------ arg2 in r8 \--* CNS_INT int 0 ***** BB49 STMT00126 (IL 0x258... ???) N006 ( 8, 7) [000711] -A-XG---R--- * ASG ref N005 ( 3, 2) [000710] D------N---- +--* LCL_VAR ref V52 tmp38 N004 ( 4, 4) [000709] ---XG------- \--* IND ref N003 ( 2, 2) [001095] -------N---- \--* ADD byref N001 ( 1, 1) [000165] ------------ +--* LCL_VAR ref V00 this N002 ( 1, 1) [001094] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] ***** BB49 STMT00133 (IL 0x258... ???) N004 ( 5, 4) [000760] -A-X----R--- * ASG int N003 ( 1, 1) [000759] D------N---- +--* LCL_VAR int V53 tmp39 N002 ( 5, 4) [000714] ---X-------- \--* ARR_LENGTH int N001 ( 3, 2) [000713] ------------ \--* LCL_VAR ref V52 tmp38 ***** BB49 STMT00134 (IL 0x258... ???) N006 ( 8, 7) [000762] -A-XG---R--- * ASG long N005 ( 3, 2) [000761] D------N---- +--* LCL_VAR long V54 tmp40 N004 ( 4, 4) [000716] ---XG------- \--* IND long N003 ( 2, 2) [001097] -------N---- \--* ADD byref N001 ( 1, 1) [000715] ------------ +--* LCL_VAR ref V00 this N002 ( 1, 1) [001096] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] ***** BB49 STMT00136 (IL 0x258... ???) N005 ( 10, 9) [000773] -A------R--- * ASG bool N004 ( 3, 2) [000772] D------N---- +--* LCL_VAR int V56 tmp42 N003 ( 6, 6) [000730] N--------U-- \--* LE int N001 ( 1, 1) [000728] ------------ +--* LCL_VAR int V53 tmp39 N002 ( 1, 4) [000729] ------------ \--* CNS_INT int 0x7FFFFFFF ***** BB49 STMT00139 (IL 0x258... ???) N004 ( 8, 15) [000783] -A--G---R--- * ASG ref N003 ( 3, 2) [000782] D------N---- +--* LCL_VAR ref V57 tmp43 N002 ( 4, 12) [000767] #---G------- \--* IND ref N001 ( 2, 10) [000766] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB49 STMT00140 (IL 0x258... ???) N004 ( 8, 15) [000785] -A--G---R--- * ASG ref N003 ( 3, 2) [000784] D------N---- +--* LCL_VAR ref V58 tmp44 N002 ( 4, 12) [000769] #---G------- \--* IND ref N001 ( 2, 10) [000768] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB49 STMT00137 (IL 0x258... ???) N004 ( 7, 6) [000778] ------------ * JTRUE void N003 ( 5, 4) [000777] J------N---- \--* NE int N001 ( 3, 2) [000775] ------------ +--* LCL_VAR int V56 tmp42 N002 ( 1, 1) [000776] ------------ \--* CNS_INT int 0 ------------ BB50 [258..259), preds={BB49} succs={BB51} ***** BB50 STMT00138 (IL 0x258... ???) N005 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 3, 2) [000779] ------------ arg0 in rcx +--* LCL_VAR ref V57 tmp43 N004 ( 3, 2) [000780] ------------ arg1 in rdx \--* LCL_VAR ref V58 tmp44 ------------ BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00131 (IL 0x258... ???) N016 ( 26, 25) [000750] -A------R--- * ASG int N015 ( 3, 2) [000749] D------N---- +--* LCL_VAR int V55 tmp41 N014 ( 22, 22) [000748] ------------ \--* CAST int <- uint <- long N013 ( 21, 20) [000747] ------------ \--* RSZ long N011 ( 19, 18) [000745] ------------ +--* MUL long N008 ( 13, 12) [000742] ------------ | +--* ADD long N006 ( 11, 10) [000739] ------------ | | +--* RSZ long N004 ( 9, 8) [000737] ------------ | | | +--* MUL long N001 ( 3, 2) [000735] ------------ | | | | +--* LCL_VAR long V54 tmp40 N003 ( 2, 3) [000736] ---------U-- | | | | \--* CAST long <- ulong <- uint N002 ( 1, 1) [000166] ------------ | | | | \--* LCL_VAR int V06 loc2 N005 ( 1, 1) [000738] ------------ | | | \--* CNS_INT int 32 N007 ( 1, 1) [000741] ------------ | | \--* CNS_INT long 1 N010 ( 2, 3) [000744] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000743] ------------ | \--* LCL_VAR int V53 tmp39 N012 ( 1, 1) [000746] ------------ \--* CNS_INT int 32 ***** BB51 STMT00142 (IL 0x258... ???) N007 ( 33, 11) [000796] -A-X----R--- * ASG bool N006 ( 3, 2) [000795] D------N---- +--* LCL_VAR int V59 tmp45 N005 ( 29, 8) [000755] ---X-------- \--* EQ int N003 ( 22, 5) [000754] ---X-------- +--* UMOD int N001 ( 1, 1) [000752] ------------ | +--* LCL_VAR int V06 loc2 N002 ( 1, 1) [000753] ------------ | \--* LCL_VAR int V53 tmp39 N004 ( 3, 2) [000751] ------------ \--* LCL_VAR int V55 tmp41 ***** BB51 STMT00145 (IL 0x258... ???) N004 ( 8, 15) [000806] -A--G---R--- * ASG ref N003 ( 3, 2) [000805] D------N---- +--* LCL_VAR ref V60 tmp46 N002 ( 4, 12) [000790] #---G------- \--* IND ref N001 ( 2, 10) [000789] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB51 STMT00146 (IL 0x258... ???) N004 ( 8, 15) [000808] -A--G---R--- * ASG ref N003 ( 3, 2) [000807] D------N---- +--* LCL_VAR ref V61 tmp47 N002 ( 4, 12) [000792] #---G------- \--* IND ref N001 ( 2, 10) [000791] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB51 STMT00143 (IL 0x258... ???) N004 ( 7, 6) [000801] ------------ * JTRUE void N003 ( 5, 4) [000800] J------N---- \--* NE int N001 ( 3, 2) [000798] ------------ +--* LCL_VAR int V59 tmp45 N002 ( 1, 1) [000799] ------------ \--* CNS_INT int 0 ------------ BB52 [258..259), preds={BB51} succs={BB53} ***** BB52 STMT00144 (IL 0x258... ???) N005 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 3, 2) [000802] ------------ arg0 in rcx +--* LCL_VAR ref V60 tmp46 N004 ( 3, 2) [000803] ------------ arg1 in rdx \--* LCL_VAR ref V61 tmp47 ------------ BB53 [258..259), preds={BB51,BB52} succs={BB54} ***** BB53 STMT00128 (IL 0x258... ???) N017 ( 35, 33) [000722] -A-XG---R--- * ASG byref N016 ( 3, 2) [000721] D------N---- +--* LCL_VAR byref V51 tmp37 N015 ( 31, 30) [001112] ---XG------- \--* COMMA byref N004 ( 12, 13) [001105] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 3, 2) [000758] ------------ | +--* LCL_VAR int V55 tmp41 N003 ( 5, 4) [001104] ---X-------- | \--* ARR_LENGTH int N002 ( 3, 2) [000712] ------------ | \--* LCL_VAR ref V52 tmp38 N014 ( 19, 17) [001113] ----G------- \--* ADDR byref N013 ( 10, 9) [000719] a---G--N---- \--* IND int N012 ( 9, 8) [001111] -------N---- \--* ADD byref N005 ( 3, 2) [001102] ------------ +--* LCL_VAR ref V52 tmp38 N011 ( 6, 6) [001110] -------N---- \--* ADD long N009 ( 5, 5) [001108] -------N---- +--* LSH long N007 ( 4, 4) [001106] ------------ | +--* CAST long <- int N006 ( 3, 2) [001103] i----------- | | \--* LCL_VAR int V55 tmp41 N008 ( 1, 1) [001107] -------N---- | \--* CNS_INT long 2 N010 ( 1, 1) [001109] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB53 STMT00129 (IL 0x258... ???) N003 ( 5, 4) [000726] -A------R--- * ASG ref N002 ( 3, 2) [000725] D------N---- +--* LCL_VAR ref V52 tmp38 N001 ( 1, 1) [000724] ------------ \--* CNS_INT ref null ***** BB53 STMT00034 (IL ???... ???) N003 ( 7, 5) [000170] -A------R--- * ASG byref N002 ( 3, 2) [000169] D------N---- +--* LCL_VAR byref V08 loc4 N001 ( 3, 2) [000723] ------------ \--* LCL_VAR byref V51 tmp37 ------------ BB54 [261..276), preds={BB48,BB53} succs={BB55} ***** BB54 STMT00018 (IL 0x261...0x263) N003 ( 7, 5) [000083] -A------R--- * ASG int N002 ( 3, 2) [000082] D------N---- +--* LCL_VAR int V10 loc6 N001 ( 3, 2) [000081] ------------ \--* LCL_VAR int V13 loc9 ***** BB54 STMT00019 (IL 0x265...0x26A) N008 ( 10, 9) [000089] -A-XG---R--- * ASG int N007 ( 4, 4) [000088] ---XG--N---- +--* IND int N006 ( 2, 2) [001115] -------N---- | \--* ADD byref N004 ( 1, 1) [000084] ------------ | +--* LCL_VAR ref V00 this N005 ( 1, 1) [001114] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] N003 ( 5, 4) [000087] ------------ \--* ADD int N001 ( 3, 2) [000085] ------------ +--* LCL_VAR int V13 loc9 N002 ( 1, 1) [000086] ------------ \--* CNS_INT int 1 ***** BB54 STMT00020 (IL 0x26F...0x275) N006 ( 4, 4) [000093] -A-XG---R--- * ASG ref N005 ( 1, 1) [000092] D------N---- +--* LCL_VAR ref V04 loc0 N004 ( 4, 4) [000091] ---XG------- \--* IND ref N003 ( 2, 2) [001117] -------N---- \--* ADD byref N001 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V00 this N002 ( 1, 1) [001116] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] ------------ BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} ***** BB55 STMT00021 (IL 0x276...0x27E) N019 ( 39, 38) [000099] -A-XG---R--- * ASG byref N018 ( 3, 2) [000098] D------N---- +--* LCL_VAR byref V11 loc7 N017 ( 35, 35) [001128] ---XG------- \--* COMMA byref N004 ( 10, 12) [001121] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 3, 2) [000095] ------------ | +--* LCL_VAR int V10 loc6 N003 ( 3, 3) [001120] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000094] ------------ | \--* LCL_VAR ref V04 loc0 N016 ( 25, 23) [001131] ----G------- \--* ADDR byref N015 ( 13, 12) [000096] a---G--N---- \--* IND struct N014 ( 12, 11) [001127] -------N---- \--* ADD byref N005 ( 1, 1) [001118] ------------ +--* LCL_VAR ref V04 loc0 N013 ( 11, 10) [001126] -------N---- \--* ADD long N011 ( 10, 9) [001124] -------N---- +--* LSH long N009 ( 9, 8) [001130] ------------ | +--* MUL long N007 ( 4, 4) [001122] ------------ | | +--* CAST long <- int N006 ( 3, 2) [001119] i----------- | | | \--* LCL_VAR int V10 loc6 N008 ( 1, 1) [001129] ------------ | | \--* CNS_INT long 3 N010 ( 1, 1) [001123] -------N---- | \--* CNS_INT long 3 N012 ( 1, 1) [001125] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB55 STMT00022 (IL 0x280...0x283) N006 ( 8, 7) [000103] -A-XG------- * ASG int N004 ( 6, 5) [000102] *--XG--N---- +--* IND int N003 ( 4, 3) [001133] -------N---- | \--* ADD byref N001 ( 3, 2) [000100] ------------ | +--* LCL_VAR byref V11 loc7 N002 ( 1, 1) [001132] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] N005 ( 1, 1) [000101] ------------ \--* LCL_VAR int V06 loc2 ***** BB55 STMT00023 (IL 0x288...0x28F) N009 ( 15, 12) [000110] -A-XG---R--- * ASG int N008 ( 6, 5) [000109] *--XG--N---- +--* IND int N007 ( 4, 3) [001135] -------N---- | \--* ADD byref N005 ( 3, 2) [000104] ------------ | +--* LCL_VAR byref V11 loc7 N006 ( 1, 1) [001134] ------------ | \--* CNS_INT long 20 field offset Fseq[next] N004 ( 8, 6) [000108] ---XG------- \--* ADD int N002 ( 6, 4) [000106] *--XG------- +--* IND int N001 ( 3, 2) [000105] ------------ | \--* LCL_VAR byref V08 loc4 N003 ( 1, 1) [000107] ------------ \--* CNS_INT int -1 ***** BB55 STMT00024 (IL 0x294...0x297) N004 ( 8, 6) [000114] -A-XG------- * ASG ref N002 ( 6, 4) [000113] *--XG--N---- +--* IND ref N001 ( 3, 2) [000111] ------------ | \--* LCL_VAR byref V11 loc7 Zero Fseq[key] N003 ( 1, 1) [000112] ------------ \--* LCL_VAR ref V01 arg1 ***** BB55 STMT00025 (IL 0x29C...0x29F) N006 ( 8, 7) [000118] -A-XG------- * ASG ref N004 ( 6, 5) [000117] *--XG--N---- +--* IND ref N003 ( 4, 3) [001137] -------N---- | \--* ADD byref N001 ( 3, 2) [000115] ------------ | +--* LCL_VAR byref V11 loc7 N002 ( 1, 1) [001136] ------------ | \--* CNS_INT long 8 field offset Fseq[value] N005 ( 1, 1) [000116] ------------ \--* LCL_VAR ref V02 arg2 ***** BB55 STMT00026 (IL 0x2A4...0x2AA) N006 ( 12, 9) [000124] -A-XG---R--- * ASG int N005 ( 6, 4) [000123] *--X---N---- +--* IND int N004 ( 3, 2) [000119] ------------ | \--* LCL_VAR byref V08 loc4 N003 ( 5, 4) [000122] ------------ \--* ADD int N001 ( 3, 2) [000120] ------------ +--* LCL_VAR int V10 loc6 N002 ( 1, 1) [000121] ------------ \--* CNS_INT int 1 ***** BB55 STMT00027 (IL 0x2AB...0x2B4) N011 ( 11, 11) [000131] -A-XG---R--- * ASG int N010 ( 4, 4) [000130] ---XG--N---- +--* IND int N009 ( 2, 2) [001139] -------N---- | \--* ADD byref N007 ( 1, 1) [000125] ------------ | +--* LCL_VAR ref V00 this N008 ( 1, 1) [001138] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] N006 ( 6, 6) [000129] ---XG------- \--* ADD int N004 ( 4, 4) [000127] ---XG------- +--* IND int N003 ( 2, 2) [001141] -------N---- | \--* ADD byref N001 ( 1, 1) [000126] ------------ | +--* LCL_VAR ref V00 this N002 ( 1, 1) [001140] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] N005 ( 1, 1) [000128] ------------ \--* CNS_INT int 1 ***** BB55 STMT00028 (IL 0x2CA...0x2CD) N004 ( 5, 5) [000148] ------------ * JTRUE void N003 ( 3, 3) [000147] N------N-U-- \--* LE int N001 ( 1, 1) [000145] ------------ +--* LCL_VAR int V07 loc3 N002 ( 1, 1) [000146] ------------ \--* CNS_INT int 100 ------------ BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} ***** BB56 STMT00030 (IL 0x2CF...0x2D5) N008 ( 21, 22) [000156] --C-G------- * JTRUE void N007 ( 19, 20) [000155] J-C-G--N---- \--* EQ int N005 ( 17, 18) [000153] --C-G------- +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS N003 ( 1, 1) [000151] ------------ arg1 in rdx | +--* LCL_VAR ref V05 loc1 N004 ( 2, 10) [000152] H------N---- arg0 in rcx | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 1, 1) [000154] ------------ \--* CNS_INT ref null ------------ BB57 [2D7..2E3), preds={BB56} succs={BB58} ***** BB57 STMT00031 (IL 0x2D7...0x2DC) N008 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize N005 ( 3, 3) [000159] ---X-------- arg1 in rdx +--* ARR_LENGTH int N004 ( 1, 1) [000158] ------------ | \--* LCL_VAR ref V04 loc0 N006 ( 1, 1) [000157] ------------ this in rcx +--* LCL_VAR ref V00 this N007 ( 1, 1) [000160] ------------ arg2 in r8 \--* CNS_INT int 1 ------------ BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} ***** BB58 STMT00147 (IL ???... ???) N002 ( 2, 2) [000810] ------------ * RETURN int N001 ( 1, 1) [000482] ------------ \--* CNS_INT int 1 ------------ BB59 [008..00E) (throw), preds={BB01} succs={} ***** BB59 STMT00086 (IL 0x008...0x009) N003 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException N002 ( 1, 1) [000532] ------------ arg0 in rcx \--* CNS_INT int 4 ------------ BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} ***** BB60 STMT00073 (IL 0x14F...0x150) N004 ( 7, 5) [000444] -A-X----R--- * ASG long N003 ( 3, 2) [000443] D------N---- +--* LCL_VAR long V26 tmp12 N002 ( 3, 2) [000442] #--X-------- \--* IND long N001 ( 1, 1) [000441] !----------- \--* LCL_VAR ref V00 this ***** BB60 STMT00074 (IL ???... ???) N003 ( 5, 4) [000454] -A------R--- * ASG ref N002 ( 3, 2) [000453] D------N---- +--* LCL_VAR ref V27 tmp13 N001 ( 1, 1) [000439] ------------ \--* LCL_VAR ref V01 arg1 ***** BB60 STMT00155 (IL ???... ???) N011 ( 16, 14) [001158] ------------ * JTRUE void N010 ( 14, 12) [000460] J------N---- \--* EQ int N008 ( 12, 10) [000456] n----------- +--* IND long N007 ( 10, 8) [000452] -------N---- | \--* ADD long N005 ( 9, 7) [000450] #----------- | +--* IND long N004 ( 6, 5) [000449] #----------- | | \--* IND long N003 ( 4, 3) [000448] -------N---- | | \--* ADD long N001 ( 3, 2) [000446] ------------ | | +--* LCL_VAR long V26 tmp12 N002 ( 1, 1) [000447] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000451] ------------ | \--* CNS_INT long 56 N009 ( 1, 1) [000459] ------------ \--* CNS_INT long 0 ------------ BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} ***** BB61 STMT00156 (IL ???... ???) N010 ( 16, 13) [001160] -A------R--- * ASG long N009 ( 3, 2) [001159] D------N---- +--* LCL_VAR long V28 tmp14 N008 ( 12, 10) [000461] n-----?----- \--* IND long N007 ( 10, 8) [000462] ------?N---- \--* ADD long N005 ( 9, 7) [000463] #-----?----- +--* IND long N004 ( 6, 5) [000464] #-----?----- | \--* IND long N003 ( 4, 3) [000465] ------?N---- | \--* ADD long N001 ( 3, 2) [000466] ------?----- | +--* LCL_VAR long V26 tmp12 N002 ( 1, 1) [000467] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000468] ------?----- \--* CNS_INT long 56 ------------ BB62 [???..???), preds={BB60} succs={BB63} ***** BB62 STMT00157 (IL ???... ???) N007 ( 23, 22) [001162] -AC-G---R--- * ASG long N006 ( 3, 2) [001161] D------N---- +--* LCL_VAR long V28 tmp14 N005 ( 19, 19) [000458] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 3, 2) [000445] ------?----- arg0 in rcx +--* LCL_VAR long V26 tmp12 N004 ( 2, 10) [000457] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB63 [???..157) (throw), preds={BB61,BB62} succs={} ***** BB63 STMT00076 (IL ???... ???) N005 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException N003 ( 3, 2) [000473] ------------ arg0 in rcx +--* LCL_VAR long V28 tmp14 N004 ( 1, 1) [000455] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 ------------ BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} ***** BB64 STMT00053 (IL 0x1BC...0x1BD) N004 ( 7, 5) [000299] -A-X----R--- * ASG long N003 ( 3, 2) [000298] D------N---- +--* LCL_VAR long V21 tmp7 N002 ( 3, 2) [000297] #--X-------- \--* IND long N001 ( 1, 1) [000296] !----------- \--* LCL_VAR ref V00 this ***** BB64 STMT00054 (IL ???... ???) N003 ( 5, 4) [000309] -A------R--- * ASG ref N002 ( 3, 2) [000308] D------N---- +--* LCL_VAR ref V22 tmp8 N001 ( 1, 1) [000294] ------------ \--* LCL_VAR ref V01 arg1 ***** BB64 STMT00161 (IL ???... ???) N011 ( 16, 14) [001168] ------------ * JTRUE void N010 ( 14, 12) [000315] J------N---- \--* EQ int N008 ( 12, 10) [000311] n----------- +--* IND long N007 ( 10, 8) [000307] -------N---- | \--* ADD long N005 ( 9, 7) [000305] #----------- | +--* IND long N004 ( 6, 5) [000304] #----------- | | \--* IND long N003 ( 4, 3) [000303] -------N---- | | \--* ADD long N001 ( 3, 2) [000301] ------------ | | +--* LCL_VAR long V21 tmp7 N002 ( 1, 1) [000302] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000306] ------------ | \--* CNS_INT long 56 N009 ( 1, 1) [000314] ------------ \--* CNS_INT long 0 ------------ BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} ***** BB65 STMT00162 (IL ???... ???) N010 ( 16, 13) [001170] -A------R--- * ASG long N009 ( 3, 2) [001169] D------N---- +--* LCL_VAR long V23 tmp9 N008 ( 12, 10) [000316] n-----?----- \--* IND long N007 ( 10, 8) [000317] ------?N---- \--* ADD long N005 ( 9, 7) [000318] #-----?----- +--* IND long N004 ( 6, 5) [000319] #-----?----- | \--* IND long N003 ( 4, 3) [000320] ------?N---- | \--* ADD long N001 ( 3, 2) [000321] ------?----- | +--* LCL_VAR long V21 tmp7 N002 ( 1, 1) [000322] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000323] ------?----- \--* CNS_INT long 56 ------------ BB66 [???..???), preds={BB64} succs={BB67} ***** BB66 STMT00163 (IL ???... ???) N007 ( 23, 22) [001172] -AC-G---R--- * ASG long N006 ( 3, 2) [001171] D------N---- +--* LCL_VAR long V23 tmp9 N005 ( 19, 19) [000313] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 3, 2) [000300] ------?----- arg0 in rcx +--* LCL_VAR long V21 tmp7 N004 ( 2, 10) [000312] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} ***** BB67 STMT00056 (IL ???... ???) N005 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException N003 ( 3, 2) [000328] ------------ arg0 in rcx +--* LCL_VAR long V23 tmp9 N004 ( 1, 1) [000310] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 ------------ BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} ***** BB68 STMT00043 (IL 0x1DD...0x1E2) N001 ( 14, 5) [000233] --CXG------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Build SSA representation *************** In SsaBuilder::Build() [SsaBuilder] Max block count is 69. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target align BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal Loop1 gcsafe BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe BB36 [0108] 1 BB34 1 [???..???) i gcsafe BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen BB54 [0044] 2 BB48,BB53 0.50 [261..276) i BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty [SsaBuilder] Topologically sorted the graph. [SsaBuilder::ComputeImmediateDom] Inside fgBuildDomTree After computing the Dominance Tree: BB01 : BB59 BB02 BB02 : BB04 BB03 BB04 : BB06 BB05 BB06 : BB08 BB07 BB08 : BB14 BB13 BB09 BB09 : BB12 BB11 BB10 BB14 : BB16 BB15 BB16 : BB18 BB17 BB18 : BB68 BB58 BB44 BB32 BB31 BB19 BB19 : BB22 BB21 BB20 BB22 : BB23 BB23 : BB24 BB24 : BB26 BB25 BB25 : BB28 BB26 : BB27 BB28 : BB30 BB29 BB30 : BB60 BB32 : BB33 BB33 : BB42 BB34 BB34 : BB37 BB36 BB35 BB37 : BB38 BB38 : BB40 BB39 BB40 : BB64 BB41 BB42 : BB43 BB44 : BB55 BB48 BB45 BB45 : BB47 BB46 BB48 : BB54 BB49 BB49 : BB51 BB50 BB51 : BB53 BB52 BB55 : BB56 BB56 : BB57 BB60 : BB63 BB62 BB61 BB64 : BB67 BB66 BB65 *************** In fgLocalVarLiveness() In fgLocalVarLivenessInit Tracked variable (64 out of 65) table: V04 loc0 [ ref]: refCnt = 31, refCntWtd = 64.50 V09 loc5 [ int]: refCnt = 21, refCntWtd = 59 V07 loc3 [ int]: refCnt = 8, refCntWtd = 25.50 V00 this [ ref]: refCnt = 31, refCntWtd = 20 V19 tmp5 [ long]: refCnt = 5, refCntWtd = 16 V01 arg1 [ ref]: refCnt = 15, refCntWtd = 11.50 V06 loc2 [ int]: refCnt = 8, refCntWtd = 12.50 V16 tmp2 [ long]: refCnt = 4, refCntWtd = 12 V40 tmp26 [ int]: refCnt = 4, refCntWtd = 8 V17 tmp3 [ ref]: refCnt = 2, refCntWtd = 8 V05 loc1 [ ref]: refCnt = 6, refCntWtd = 6 V03 arg3 [ ubyte]: refCnt = 6, refCntWtd = 4 V02 arg2 [ ref]: refCnt = 5, refCntWtd = 3.50 V39 tmp25 [ ref]: refCnt = 5, refCntWtd = 5 V12 loc8 [ ref]: refCnt = 3, refCntWtd = 4.50 V31 tmp17 [ long]: refCnt = 5, refCntWtd = 4 V42 tmp28 [ int]: refCnt = 4, refCntWtd = 4 V53 tmp39 [ int]: refCnt = 4, refCntWtd = 4 V33 tmp19 [ bool]: refCnt = 2, refCntWtd = 4 V36 tmp22 [ bool]: refCnt = 2, refCntWtd = 4 V41 tmp27 [ long]: refCnt = 2, refCntWtd = 4 V43 tmp29 [ bool]: refCnt = 2, refCntWtd = 4 V46 tmp32 [ bool]: refCnt = 2, refCntWtd = 4 V18 tmp4 [ ref]: refCnt = 1, refCntWtd = 4 V20 tmp6 [ long]: refCnt = 1, refCntWtd = 4 V24 tmp10 [ long]: refCnt = 4, refCntWtd = 3 V29 tmp15 [ long]: refCnt = 4, refCntWtd = 3 V38 tmp24 [ byref]: refCnt = 3, refCntWtd = 3 V62 tmp48 [ int]: refCnt = 3, refCntWtd = 3 V63 tmp49 [ int]: refCnt = 3, refCntWtd = 3 V34 tmp20 [ ref]: refCnt = 2, refCntWtd = 3 V35 tmp21 [ ref]: refCnt = 2, refCntWtd = 3 V37 tmp23 [ ref]: refCnt = 2, refCntWtd = 3 V44 tmp30 [ ref]: refCnt = 2, refCntWtd = 3 V45 tmp31 [ ref]: refCnt = 2, refCntWtd = 3 V47 tmp33 [ ref]: refCnt = 2, refCntWtd = 3 V48 tmp34 [ ref]: refCnt = 2, refCntWtd = 3 V11 loc7 [ byref]: refCnt = 5, refCntWtd = 2.50 V52 tmp38 [ ref]: refCnt = 5, refCntWtd = 2.50 V10 loc6 [ int]: refCnt = 5, refCntWtd = 2.50 V08 loc4 [ byref]: refCnt = 4, refCntWtd = 2.50 V13 loc9 [ int]: refCnt = 4, refCntWtd = 2 V55 tmp41 [ int]: refCnt = 4, refCntWtd = 2 V15 tmp1 [ int]: refCnt = 3, refCntWtd = 2 V25 tmp11 [ long]: refCnt = 3, refCntWtd = 2 V50 tmp36 [ ref]: refCnt = 2, refCntWtd = 2 V57 tmp43 [ ref]: refCnt = 2, refCntWtd = 2 V58 tmp44 [ ref]: refCnt = 2, refCntWtd = 2 V60 tmp46 [ ref]: refCnt = 2, refCntWtd = 2 V61 tmp47 [ ref]: refCnt = 2, refCntWtd = 2 V49 tmp35 [ bool]: refCnt = 2, refCntWtd = 2 V54 tmp40 [ long]: refCnt = 2, refCntWtd = 2 V56 tmp42 [ bool]: refCnt = 2, refCntWtd = 2 V59 tmp45 [ bool]: refCnt = 2, refCntWtd = 2 V64 tmp50 [ int]: refCnt = 2, refCntWtd = 2 V51 tmp37 [ byref]: refCnt = 2, refCntWtd = 1 V30 tmp16 [ ref]: refCnt = 1, refCntWtd = 1 V32 tmp18 [ long]: refCnt = 1, refCntWtd = 1 V21 tmp7 [ long]: refCnt = 4, refCntWtd = 0 V26 tmp12 [ long]: refCnt = 4, refCntWtd = 0 V23 tmp9 [ long]: refCnt = 3, refCntWtd = 0 V28 tmp14 [ long]: refCnt = 3, refCntWtd = 0 V22 tmp8 [ ref]: refCnt = 1, refCntWtd = 0 V27 tmp13 [ ref]: refCnt = 1, refCntWtd = 0 *************** In fgPerBlockLocalVarLiveness() BB01 USE(1)={V01} DEF(0)={ } BB02 USE(1)={V00} + ByrefExposed + GcHeap DEF(0)={ } BB03 USE(1)={V00} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB04 USE(1)={V00 } + ByrefExposed + GcHeap DEF(3)={ V33 V34 V35} BB05 USE(2)={V34 V35} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB06 USE(1)={ V00 } + ByrefExposed + GcHeap DEF(3)={V04 V36 V37} BB07 USE(1)={V37} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB08 USE(1)={V00 } + ByrefExposed + GcHeap DEF(1)={ V05} BB09 USE(2)={V00 V01 } + ByrefExposed + GcHeap DEF(2)={ V29 V30} BB10 USE(1)={ V29} + ByrefExposed + GcHeap DEF(1)={V31 } BB11 USE(1)={ V29} DEF(1)={V31 } BB12 USE(3)={V01 V05 V31 } + ByrefExposed + GcHeap DEF(2)={ V15 V32} + ByrefExposed* + GcHeap* BB13 USE(1)={V01 } + ByrefExposed + GcHeap DEF(1)={ V15} + ByrefExposed* + GcHeap* BB14 USE(2)={ V00 V15} + ByrefExposed + GcHeap DEF(8)={V07 V06 V40 V39 V41 V43 V44 V45 } BB15 USE(2)={V44 V45} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB16 USE(3)={V06 V40 V41 } + ByrefExposed + GcHeap DEF(4)={ V42 V46 V47 V48} BB17 USE(2)={V47 V48} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB18 USE(3)={ V05 V39 V42 } + ByrefExposed + GcHeap DEF(4)={V09 V39 V38 V08} BB19 USE(1)={V00 } + ByrefExposed + GcHeap DEF(1)={ V24} BB20 USE(1)={V24 } + ByrefExposed + GcHeap DEF(1)={ V25} BB21 USE(1)={V24 } DEF(1)={ V25} BB22 USE(1)={ V25} + ByrefExposed + GcHeap DEF(1)={V12 } + ByrefExposed* + GcHeap* BB23 USE(2)={V04 V09} DEF(0)={ } BB24 USE(3)={V04 V09 V06} + ByrefExposed + GcHeap DEF(0)={ } BB25 USE(4)={V04 V09 V01 V12} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB26 USE(3)={V04 V09 V07} + ByrefExposed + GcHeap DEF(2)={ V09 V07} BB27 USE(0)={} DEF(0)={} BB28 USE(1)={V03} DEF(0)={ } BB29 USE(3)={V04 V09 V02} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed + GcHeap BB30 USE(1)={V03} DEF(0)={ } BB31 USE(0)={} DEF(0)={} BB32 USE(2)={V04 V09} DEF(0)={ } BB33 USE(3)={V04 V09 V06} + ByrefExposed + GcHeap DEF(0)={ } BB34 USE(4)={V04 V09 V00 V01 } + ByrefExposed + GcHeap DEF(3)={ V16 V17 V18} BB35 USE(1)={ V16} + ByrefExposed + GcHeap DEF(1)={V19 } BB36 USE(1)={ V16} DEF(1)={V19 } BB37 USE(4)={V19 V01 V17 V05 } + ByrefExposed + GcHeap DEF(1)={ V20} + ByrefExposed* + GcHeap* BB38 USE(1)={V03} DEF(0)={ } BB39 USE(3)={V04 V09 V02} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed + GcHeap BB40 USE(1)={V03} DEF(0)={ } BB41 USE(0)={} DEF(0)={} BB42 USE(3)={V04 V09 V07} + ByrefExposed + GcHeap DEF(2)={ V09 V07} BB43 USE(0)={} DEF(0)={} BB44 USE(1)={V00} + ByrefExposed + GcHeap DEF(0)={ } BB45 USE(2)={V04 V00 } + ByrefExposed + GcHeap DEF(4)={ V62 V10 V50 V49} BB46 USE(1)={V50} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB47 USE(2)={V04 V00 } + ByrefExposed + GcHeap DEF(1)={ V63} + ByrefExposed + GcHeap BB48 USE(2)={V04 V00 } + ByrefExposed + GcHeap DEF(1)={ V13} BB49 USE(1)={V00 } + ByrefExposed + GcHeap DEF(7)={ V53 V52 V57 V58 V54 V56 V64} + ByrefExposed* + GcHeap* BB50 USE(2)={V57 V58} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB51 USE(3)={V06 V53 V54 } + ByrefExposed + GcHeap DEF(4)={ V55 V60 V61 V59} BB52 USE(2)={V60 V61} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB53 USE(2)={V52 V55 } + ByrefExposed + GcHeap DEF(3)={V52 V08 V51} BB54 USE(2)={ V00 V13} + ByrefExposed + GcHeap DEF(2)={V04 V10 } + ByrefExposed + GcHeap BB55 USE(8)={V04 V07 V00 V01 V06 V02 V10 V08} + ByrefExposed + GcHeap DEF(1)={ V11 } + ByrefExposed + GcHeap BB56 USE(1)={V05} DEF(0)={ } BB57 USE(2)={V04 V00} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB58 USE(0)={} DEF(0)={} BB59 USE(0)={} + ByrefExposed + GcHeap DEF(0)={} + ByrefExposed* + GcHeap* BB60 USE(2)={V00 V01 } + ByrefExposed + GcHeap DEF(2)={ V26 V27} BB61 USE(1)={V26 } + ByrefExposed + GcHeap DEF(1)={ V28} BB62 USE(1)={V26 } DEF(1)={ V28} BB63 USE(2)={V01 V28} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB64 USE(2)={V00 V01 } + ByrefExposed + GcHeap DEF(2)={ V21 V22} BB65 USE(1)={V21 } + ByrefExposed + GcHeap DEF(1)={ V23} BB66 USE(1)={V21 } DEF(1)={ V23} BB67 USE(2)={V01 V23} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB68 USE(0)={} + ByrefExposed + GcHeap DEF(0)={} + ByrefExposed* + GcHeap* ** Memory liveness computed, GcHeap states and ByrefExposed states match *************** In fgInterBlockLocalVarLiveness() Reporting this as generic context: referenced BB liveness after fgLiveVarAnalysis(): BB01 IN (4)={V00 V01 V03 V02} + ByrefExposed + GcHeap OUT(4)={V00 V01 V03 V02} + ByrefExposed + GcHeap BB02 IN (4)={V00 V01 V03 V02} + ByrefExposed + GcHeap OUT(4)={V00 V01 V03 V02} + ByrefExposed + GcHeap BB03 IN (4)={V00 V01 V03 V02} + ByrefExposed + GcHeap OUT(4)={V00 V01 V03 V02} + ByrefExposed + GcHeap BB04 IN (4)={V00 V01 V03 V02 } + ByrefExposed + GcHeap OUT(6)={V00 V01 V03 V02 V34 V35} + ByrefExposed + GcHeap BB05 IN (6)={V00 V01 V03 V02 V34 V35} + ByrefExposed + GcHeap OUT(4)={V00 V01 V03 V02 } + ByrefExposed + GcHeap BB06 IN (4)={ V00 V01 V03 V02 } + ByrefExposed + GcHeap OUT(6)={V04 V00 V01 V03 V02 V37} + ByrefExposed + GcHeap BB07 IN (6)={V04 V00 V01 V03 V02 V37} + ByrefExposed + GcHeap OUT(5)={V04 V00 V01 V03 V02 } + ByrefExposed + GcHeap BB08 IN (5)={V04 V00 V01 V03 V02} + ByrefExposed + GcHeap OUT(6)={V04 V00 V01 V05 V03 V02} + ByrefExposed + GcHeap BB09 IN (6)={V04 V00 V01 V05 V03 V02 } + ByrefExposed + GcHeap OUT(7)={V04 V00 V01 V05 V03 V02 V29} + ByrefExposed + GcHeap BB10 IN (7)={V04 V00 V01 V05 V03 V02 V29} + ByrefExposed + GcHeap OUT(7)={V04 V00 V01 V05 V03 V02 V31 } + ByrefExposed + GcHeap BB11 IN (7)={V04 V00 V01 V05 V03 V02 V29} + ByrefExposed + GcHeap OUT(7)={V04 V00 V01 V05 V03 V02 V31 } + ByrefExposed + GcHeap BB12 IN (7)={V04 V00 V01 V05 V03 V02 V31 } + ByrefExposed + GcHeap OUT(7)={V04 V00 V01 V05 V03 V02 V15} + ByrefExposed + GcHeap BB13 IN (6)={V04 V00 V01 V05 V03 V02 } + ByrefExposed + GcHeap OUT(7)={V04 V00 V01 V05 V03 V02 V15} + ByrefExposed + GcHeap BB14 IN (7)={V04 V00 V01 V05 V03 V02 V15} + ByrefExposed + GcHeap OUT(13)={V04 V07 V00 V01 V06 V40 V05 V03 V02 V39 V41 V44 V45 } + ByrefExposed + GcHeap BB15 IN (13)={V04 V07 V00 V01 V06 V40 V05 V03 V02 V39 V41 V44 V45} + ByrefExposed + GcHeap OUT(11)={V04 V07 V00 V01 V06 V40 V05 V03 V02 V39 V41 } + ByrefExposed + GcHeap BB16 IN (11)={V04 V07 V00 V01 V06 V40 V05 V03 V02 V39 V41 } + ByrefExposed + GcHeap OUT(12)={V04 V07 V00 V01 V06 V05 V03 V02 V39 V42 V47 V48} + ByrefExposed + GcHeap BB17 IN (12)={V04 V07 V00 V01 V06 V05 V03 V02 V39 V42 V47 V48} + ByrefExposed + GcHeap OUT(10)={V04 V07 V00 V01 V06 V05 V03 V02 V39 V42 } + ByrefExposed + GcHeap BB18 IN (10)={V04 V07 V00 V01 V06 V05 V03 V02 V39 V42 } + ByrefExposed + GcHeap OUT(10)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V08} + ByrefExposed + GcHeap BB19 IN (10)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(11)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V24 V08} + ByrefExposed + GcHeap BB20 IN (11)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V24 V08 } + ByrefExposed + GcHeap OUT(11)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V08 V25} + ByrefExposed + GcHeap BB21 IN (11)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V24 V08 } + ByrefExposed + GcHeap OUT(11)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V08 V25} + ByrefExposed + GcHeap BB22 IN (11)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V08 V25} + ByrefExposed + GcHeap OUT(11)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V12 V08 } + ByrefExposed + GcHeap BB23 IN (11)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap OUT(11)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap BB24 IN (11)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap OUT(11)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap BB25 IN (11)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap OUT(11)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap BB26 IN (11)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap OUT(11)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap BB27 IN (11)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap OUT(11)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap BB28 IN (6)={V04 V09 V00 V01 V03 V02} + ByrefExposed + GcHeap OUT(6)={V04 V09 V00 V01 V03 V02} + ByrefExposed + GcHeap BB29 IN (4)={V04 V09 V00 V02} + ByrefExposed + GcHeap OUT(1)={ V00 } BB30 IN (3)={V00 V01 V03} + ByrefExposed + GcHeap OUT(2)={V00 V01 } + ByrefExposed + GcHeap BB31 IN (1)={V00} OUT(1)={V00} BB32 IN (10)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(10)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V08} + ByrefExposed + GcHeap BB33 IN (10)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(10)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V08} + ByrefExposed + GcHeap BB34 IN (10)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(12)={V04 V09 V07 V00 V01 V06 V16 V17 V05 V03 V02 V08} + ByrefExposed + GcHeap BB35 IN (12)={V04 V09 V07 V00 V01 V06 V16 V17 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(12)={V04 V09 V07 V00 V19 V01 V06 V17 V05 V03 V02 V08} + ByrefExposed + GcHeap BB36 IN (12)={V04 V09 V07 V00 V01 V06 V16 V17 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(12)={V04 V09 V07 V00 V19 V01 V06 V17 V05 V03 V02 V08} + ByrefExposed + GcHeap BB37 IN (12)={V04 V09 V07 V00 V19 V01 V06 V17 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(10)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V08} + ByrefExposed + GcHeap BB38 IN (6)={V04 V09 V00 V01 V03 V02} + ByrefExposed + GcHeap OUT(6)={V04 V09 V00 V01 V03 V02} + ByrefExposed + GcHeap BB39 IN (4)={V04 V09 V00 V02} + ByrefExposed + GcHeap OUT(1)={ V00 } BB40 IN (3)={V00 V01 V03} + ByrefExposed + GcHeap OUT(2)={V00 V01 } + ByrefExposed + GcHeap BB41 IN (1)={V00} OUT(1)={V00} BB42 IN (10)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(10)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V08} + ByrefExposed + GcHeap BB43 IN (10)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(10)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V08} + ByrefExposed + GcHeap BB44 IN (8)={V04 V07 V00 V01 V06 V05 V02 V08} + ByrefExposed + GcHeap OUT(8)={V04 V07 V00 V01 V06 V05 V02 V08} + ByrefExposed + GcHeap BB45 IN (8)={V04 V07 V00 V01 V06 V05 V02 V08 } + ByrefExposed + GcHeap OUT(10)={V04 V07 V00 V01 V06 V05 V02 V10 V08 V50} + ByrefExposed + GcHeap BB46 IN (10)={V04 V07 V00 V01 V06 V05 V02 V10 V08 V50} + ByrefExposed + GcHeap OUT(9)={V04 V07 V00 V01 V06 V05 V02 V10 V08 } + ByrefExposed + GcHeap BB47 IN (9)={V04 V07 V00 V01 V06 V05 V02 V10 V08} + ByrefExposed + GcHeap OUT(9)={V04 V07 V00 V01 V06 V05 V02 V10 V08} + ByrefExposed + GcHeap BB48 IN (8)={V04 V07 V00 V01 V06 V05 V02 V08 } + ByrefExposed + GcHeap OUT(8)={ V07 V00 V01 V06 V05 V02 V08 V13} + ByrefExposed + GcHeap BB49 IN (7)={V07 V00 V01 V06 V05 V02 V13 } + ByrefExposed + GcHeap OUT(12)={V07 V00 V01 V06 V05 V02 V53 V52 V13 V57 V58 V54} + ByrefExposed + GcHeap BB50 IN (12)={V07 V00 V01 V06 V05 V02 V53 V52 V13 V57 V58 V54} + ByrefExposed + GcHeap OUT(10)={V07 V00 V01 V06 V05 V02 V53 V52 V13 V54} + ByrefExposed + GcHeap BB51 IN (10)={V07 V00 V01 V06 V05 V02 V53 V52 V13 V54} + ByrefExposed + GcHeap OUT(11)={V07 V00 V01 V06 V05 V02 V52 V13 V55 V60 V61 } + ByrefExposed + GcHeap BB52 IN (11)={V07 V00 V01 V06 V05 V02 V52 V13 V55 V60 V61} + ByrefExposed + GcHeap OUT(9)={V07 V00 V01 V06 V05 V02 V52 V13 V55 } + ByrefExposed + GcHeap BB53 IN (9)={V07 V00 V01 V06 V05 V02 V52 V13 V55} + ByrefExposed + GcHeap OUT(8)={V07 V00 V01 V06 V05 V02 V08 V13 } + ByrefExposed + GcHeap BB54 IN (8)={ V07 V00 V01 V06 V05 V02 V08 V13} + ByrefExposed + GcHeap OUT(9)={V04 V07 V00 V01 V06 V05 V02 V10 V08 } + ByrefExposed + GcHeap BB55 IN (9)={V04 V07 V00 V01 V06 V05 V02 V10 V08} + ByrefExposed + GcHeap OUT(3)={V04 V00 V05 } + ByrefExposed + GcHeap BB56 IN (3)={V04 V00 V05} + ByrefExposed + GcHeap OUT(2)={V04 V00 } + ByrefExposed + GcHeap BB57 IN (2)={V04 V00} + ByrefExposed + GcHeap OUT(1)={ V00} BB58 IN (1)={V00} OUT(1)={V00} BB59 IN (1)={V00} + ByrefExposed + GcHeap OUT(1)={V00} BB60 IN (2)={V00 V01 } + ByrefExposed + GcHeap OUT(3)={V00 V01 V26} + ByrefExposed + GcHeap BB61 IN (3)={V00 V01 V26 } + ByrefExposed + GcHeap OUT(3)={V00 V01 V28} + ByrefExposed + GcHeap BB62 IN (3)={V00 V01 V26 } + ByrefExposed + GcHeap OUT(3)={V00 V01 V28} + ByrefExposed + GcHeap BB63 IN (3)={V00 V01 V28} + ByrefExposed + GcHeap OUT(1)={V00 } BB64 IN (2)={V00 V01 } + ByrefExposed + GcHeap OUT(3)={V00 V01 V21} + ByrefExposed + GcHeap BB65 IN (3)={V00 V01 V21 } + ByrefExposed + GcHeap OUT(3)={V00 V01 V23} + ByrefExposed + GcHeap BB66 IN (3)={V00 V01 V21 } + ByrefExposed + GcHeap OUT(3)={V00 V01 V23} + ByrefExposed + GcHeap BB67 IN (3)={V00 V01 V23} + ByrefExposed + GcHeap OUT(1)={V00 } BB68 IN (1)={V00} + ByrefExposed + GcHeap OUT(1)={V00} top level assign removing stmt with no side effects removing useless STMT00080 (IL ???... ???) N003 ( 5, 4) [000499] -A------R--- * ASG ref N002 ( 3, 2) [000498] D------N---- +--* LCL_VAR ref V30 tmp16 N001 ( 1, 1) [000485] ------------ \--* LCL_VAR ref V01 arg1 from BB09 top level assign removing stmt with no side effects removing useless STMT00082 (IL ???... ???) N003 ( 5, 4) [000520] -A------R--- * ASG long N002 ( 3, 2) [000519] D------N---- +--* LCL_VAR long V32 tmp18 N001 ( 1, 1) [000518] ------------ \--* LCL_VAR long V31 tmp17 from BB12 top level assign removing stmt with no side effects removing useless STMT00101 (IL 0x064... ???) N003 ( 1, 3) [000595] -A------R--- * ASG ref N002 ( 1, 1) [000594] D------N---- +--* LCL_VAR ref V39 tmp25 N001 ( 1, 1) [000593] ------------ \--* CNS_INT ref null from BB18 top level assign removing stmt with no side effects removing useless STMT00046 (IL ???... ???) N003 ( 1, 3) [000257] -A------R--- * ASG ref N002 ( 1, 1) [000256] D------N---- +--* LCL_VAR ref V18 tmp4 N001 ( 1, 1) [000240] ------------ \--* LCL_VAR ref V01 arg1 from BB34 top level assign removing stmt with no side effects removing useless STMT00048 (IL ???... ???) N003 ( 1, 3) [000278] -A------R--- * ASG long N002 ( 1, 1) [000277] D------N---- +--* LCL_VAR long V20 tmp6 N001 ( 1, 1) [000276] ------------ \--* LCL_VAR long V19 tmp5 from BB37 top level assign removing stmt with no side effects removing useless STMT00129 (IL 0x258... ???) N003 ( 5, 4) [000726] -A------R--- * ASG ref N002 ( 3, 2) [000725] D------N---- +--* LCL_VAR ref V52 tmp38 N001 ( 1, 1) [000724] ------------ \--* CNS_INT ref null from BB53 top level assign removing stmt with no side effects removing useless STMT00074 (IL ???... ???) N003 ( 5, 4) [000454] -A------R--- * ASG ref N002 ( 3, 2) [000453] D------N---- +--* LCL_VAR ref V27 tmp13 N001 ( 1, 1) [000439] ------------ \--* LCL_VAR ref V01 arg1 from BB60 top level assign removing stmt with no side effects removing useless STMT00054 (IL ???... ???) N003 ( 5, 4) [000309] -A------R--- * ASG ref N002 ( 3, 2) [000308] D------N---- +--* LCL_VAR ref V22 tmp8 N001 ( 1, 1) [000294] ------------ \--* LCL_VAR ref V01 arg1 from BB64 *************** In optRemoveRedundantZeroInits() *************** In SsaBuilder::InsertPhiFunctions() Inserting phi functions: Added PHI definition for V09 at start of BB23. Added PHI definition for V07 at start of BB23. Added PHI definition for V07 at start of BB44. Added PHI definition for V28 at start of BB63. Inserting phi definition for ByrefExposed at start of BB26. Inserting phi definition for ByrefExposed at start of BB68. Inserting phi definition for ByrefExposed at start of BB23. Inserting phi definition for ByrefExposed at start of BB44. Inserting phi definition for ByrefExposed at start of BB55. Inserting phi definition for ByrefExposed at start of BB47. Added PHI definition for V10 at start of BB55. Added PHI definition for V04 at start of BB55. Added PHI definition for V08 at start of BB54. Added PHI definition for V08 at start of BB55. Inserting phi definition for ByrefExposed at start of BB53. Inserting phi definition for ByrefExposed at start of BB54. Inserting phi definition for ByrefExposed at start of BB51. Added PHI definition for V25 at start of BB22. Added PHI definition for V23 at start of BB67. Added PHI definition for V09 at start of BB32. Added PHI definition for V07 at start of BB32. Inserting phi definition for ByrefExposed at start of BB42. Inserting phi definition for ByrefExposed at start of BB32. Added PHI definition for V19 at start of BB37. Inserting phi definition for ByrefExposed at start of BB18. Inserting phi definition for ByrefExposed at start of BB16. Added PHI definition for V15 at start of BB14. Inserting phi definition for ByrefExposed at start of BB14. Added PHI definition for V31 at start of BB12. Inserting phi definition for ByrefExposed at start of BB08. Inserting phi definition for ByrefExposed at start of BB06. Inserting phi definition for ByrefExposed at start of BB04. *************** In SsaBuilder::RenameVariables() After fgSsaBuild: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target align BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal Loop1 gcsafe BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe BB36 [0108] 1 BB34 1 [???..???) i gcsafe BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen BB54 [0044] 2 BB48,BB53 0.50 [261..276) i BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} ***** BB01 STMT00000 (IL 0x000...0x006) N004 ( 5, 5) [000003] ------------ * JTRUE void N003 ( 3, 3) [000002] J------N---- \--* EQ int N001 ( 1, 1) [000000] ------------ +--* LCL_VAR ref V01 arg1 u:1 N002 ( 1, 1) [000001] ------------ \--* CNS_INT ref null ------------ BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00001 (IL 0x00E...0x014) N007 ( 8, 8) [000008] ---XG------- * JTRUE void N006 ( 6, 6) [000007] J--XG--N---- \--* NE int N004 ( 4, 4) [000005] ---XG------- +--* IND ref N003 ( 2, 2) [000814] -------N---- | \--* ADD byref N001 ( 1, 1) [000004] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000813] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] N005 ( 1, 1) [000006] ------------ \--* CNS_INT ref null ------------ BB03 [016..01E), preds={BB02} succs={BB04} ***** BB03 STMT00085 (IL ???... ???) N005 ( 16, 10) [000528] --CXG------- * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize N003 ( 1, 1) [000526] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 N004 ( 1, 1) [000527] ------------ arg1 in rdx \--* CNS_INT int 0 ------------ BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ***** BB04 STMT00088 (IL 0x01E... ???) N008 ( 9, 6) [000544] -A-XG---R--- * ASG bool N007 ( 1, 1) [000543] D------N---- +--* LCL_VAR int V33 tmp19 d:1 N006 ( 9, 6) [000012] N--XG------- \--* NE int N004 ( 4, 4) [000010] ---XG------- +--* IND ref N003 ( 2, 2) [000818] -------N---- | \--* ADD byref N001 ( 1, 1) [000009] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000817] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] N005 ( 1, 1) [000011] ------------ \--* CNS_INT ref null ***** BB04 STMT00091 (IL 0x01E... ???) N004 ( 4, 12) [000554] -A--G---R--- * ASG ref N003 ( 1, 1) [000553] D------N---- +--* LCL_VAR ref V34 tmp20 d:1 N002 ( 4, 12) [000538] #---G------- \--* IND ref N001 ( 2, 10) [000537] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB04 STMT00092 (IL 0x01E... ???) N004 ( 4, 12) [000556] -A--G---R--- * ASG ref N003 ( 1, 1) [000555] D------N---- +--* LCL_VAR ref V35 tmp21 d:1 N002 ( 4, 12) [000540] #---G------- \--* IND ref N001 ( 2, 10) [000539] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB04 STMT00089 (IL 0x01E... ???) N004 ( 5, 5) [000549] ------------ * JTRUE void N003 ( 3, 3) [000548] J------N---- \--* NE int N001 ( 1, 1) [000546] ------------ +--* LCL_VAR int V33 tmp19 u:1 (last use) N002 ( 1, 1) [000547] ------------ \--* CNS_INT int 0 ------------ BB05 [01E..01F), preds={BB04} succs={BB06} ***** BB05 STMT00090 (IL 0x01E... ???) N005 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 1, 1) [000550] ------------ arg0 in rcx +--* LCL_VAR ref V34 tmp20 u:1 (last use) N004 ( 1, 1) [000551] ------------ arg1 in rdx \--* LCL_VAR ref V35 tmp21 u:1 (last use) ------------ BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} ***** BB06 STMT00003 (IL 0x02C... ???) N006 ( 4, 4) [000018] -A-XG---R--- * ASG ref N005 ( 1, 1) [000017] D------N---- +--* LCL_VAR ref V04 loc0 d:1 N004 ( 4, 4) [000016] ---XG------- \--* IND ref N003 ( 2, 2) [000822] -------N---- \--* ADD byref N001 ( 1, 1) [000015] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000821] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] ***** BB06 STMT00094 (IL 0x033... ???) N005 ( 6, 3) [000566] -A------R--- * ASG bool N004 ( 1, 1) [000565] D------N---- +--* LCL_VAR int V36 tmp22 d:1 N003 ( 6, 3) [000021] N----------- \--* NE int N001 ( 1, 1) [000019] ------------ +--* LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000020] ------------ \--* CNS_INT ref null ***** BB06 STMT00097 (IL 0x033... ???) N004 ( 4, 12) [000576] -A--G---R--- * ASG ref N003 ( 1, 1) [000575] D------N---- +--* LCL_VAR ref V37 tmp23 d:1 N002 ( 4, 12) [000562] #---G------- \--* IND ref N001 ( 2, 10) [000561] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB06 STMT00095 (IL 0x033... ???) N004 ( 5, 5) [000571] ------------ * JTRUE void N003 ( 3, 3) [000570] J------N---- \--* NE int N001 ( 1, 1) [000568] ------------ +--* LCL_VAR int V36 tmp22 u:1 (last use) N002 ( 1, 1) [000569] ------------ \--* CNS_INT int 0 ------------ BB07 [033..034), preds={BB06} succs={BB08} ***** BB07 STMT00096 (IL 0x033... ???) N006 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail N004 ( 4, 12) [000824] #---G------- arg0 in rcx +--* IND ref N003 ( 2, 10) [000823] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" N005 ( 1, 1) [000573] ------------ arg1 in rdx \--* LCL_VAR ref V37 tmp23 u:1 (last use) ------------ BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} ***** BB08 STMT00005 (IL 0x041... ???) N006 ( 4, 4) [000028] -A-XG---R--- * ASG ref N005 ( 1, 1) [000027] D------N---- +--* LCL_VAR ref V05 loc1 d:1 N004 ( 4, 4) [000026] ---XG------- \--* IND ref N003 ( 2, 2) [000828] -------N---- \--* ADD byref N001 ( 1, 1) [000025] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000827] ------------ \--* CNS_INT long 24 field offset Fseq[_comparer] ***** BB08 STMT00006 (IL 0x048...0x049) N004 ( 5, 5) [000032] ------------ * JTRUE void N003 ( 3, 3) [000031] J------N---- \--* EQ int N001 ( 1, 1) [000029] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000030] ------------ \--* CNS_INT ref null ------------ BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} ***** BB09 STMT00079 (IL 0x04B...0x052) N004 ( 3, 3) [000489] -A-X----R--- * ASG long N003 ( 1, 1) [000488] D------N---- +--* LCL_VAR long V29 tmp15 d:1 N002 ( 3, 2) [000487] #--X-------- \--* IND long N001 ( 1, 1) [000486] !----------- \--* LCL_VAR ref V00 this u:1 ***** BB09 STMT00149 (IL ???... ???) N011 ( 14, 13) [001148] ------------ * JTRUE void N010 ( 12, 11) [000505] J------N---- \--* EQ int N008 ( 10, 9) [000501] n----------- +--* IND long N007 ( 8, 7) [000497] -------N---- | \--* ADD long N005 ( 7, 6) [000495] #----------- | +--* IND long N004 ( 4, 4) [000494] #----------- | | \--* IND long N003 ( 2, 2) [000493] -------N---- | | \--* ADD long N001 ( 1, 1) [000491] ------------ | | +--* LCL_VAR long V29 tmp15 u:1 N002 ( 1, 1) [000492] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000496] ------------ | \--* CNS_INT long 64 N009 ( 1, 1) [000504] ------------ \--* CNS_INT long 0 ------------ BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} ***** BB10 STMT00150 (IL ???... ???) N010 ( 10, 9) [001150] -A------R--- * ASG long N009 ( 1, 1) [001149] D------N---- +--* LCL_VAR long V31 tmp17 d:3 N008 ( 10, 9) [000506] n-----?----- \--* IND long N007 ( 8, 7) [000507] ------?N---- \--* ADD long N005 ( 7, 6) [000508] #-----?----- +--* IND long N004 ( 4, 4) [000509] #-----?----- | \--* IND long N003 ( 2, 2) [000510] ------?N---- | \--* ADD long N001 ( 1, 1) [000511] ------?----- | +--* LCL_VAR long V29 tmp15 u:1 (last use) N002 ( 1, 1) [000512] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000513] ------?----- \--* CNS_INT long 64 ------------ BB11 [???..???), preds={BB09} succs={BB12} ***** BB11 STMT00151 (IL ???... ???) N007 ( 17, 18) [001152] -AC-G---R--- * ASG long N006 ( 1, 1) [001151] D------N---- +--* LCL_VAR long V31 tmp17 d:2 N005 ( 17, 18) [000503] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 1, 1) [000490] ------?----- arg0 in rcx +--* LCL_VAR long V29 tmp15 u:1 (last use) N004 ( 2, 10) [000502] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} ***** BB12 STMT00178 (IL ???... ???) N005 ( 0, 0) [001217] -A------R--- * ASG long N004 ( 0, 0) [001215] D------N---- +--* LCL_VAR long V31 tmp17 d:1 N003 ( 0, 0) [001216] ------------ \--* PHI long N001 ( 0, 0) [001247] ------------ pred BB10 +--* PHI_ARG long V31 tmp17 u:3 N002 ( 0, 0) [001246] ------------ pred BB11 \--* PHI_ARG long V31 tmp17 u:2 ***** BB12 STMT00083 (IL ???... ???) N010 ( 31, 15) [000524] -ACXG---R--- * ASG int N009 ( 3, 2) [000523] D------N---- +--* LCL_VAR int V15 tmp1 d:3 N008 ( 27, 12) [000522] --CXG------- \--* CALL ind stub int N007 ( 1, 1) [000521] ------------ calli tgt \--* LCL_VAR long V31 tmp17 u:1 (last use) N004 ( 1, 1) [000484] ------------ this in rcx +--* LCL_VAR ref V05 loc1 u:1 N005 ( 1, 1) [000831] ------------ arg1 in r11 +--* LCL_VAR long V31 tmp17 u:1 r11 REG r11 N006 ( 1, 1) [000500] ------------ arg2 in rdx \--* LCL_VAR ref V01 arg1 u:1 ------------ BB13 [054..061), preds={BB08} succs={BB14} ***** BB13 STMT00007 (IL 0x054...0x05C) N013 ( 34, 21) [000038] -ACXG---R--- * ASG int N012 ( 3, 2) [000037] D------N---- +--* LCL_VAR int V15 tmp1 d:2 N011 ( 30, 18) [000035] --CXG------- \--* CALLV vt-ind int System.Object.GetHashCode N010 ( 9, 8) [000843] n--X-------- control expr \--* IND long N009 ( 7, 6) [000842] ---X---N---- \--* ADD long N007 ( 6, 5) [000840] #--X-------- +--* IND long N006 ( 4, 3) [000839] ---X---N---- | \--* ADD long N004 ( 3, 2) [000837] #--X-------- | +--* IND long N003 ( 1, 1) [000836] ------------ | | \--* LCL_VAR ref V01 arg1 u:1 N005 ( 1, 1) [000838] ------------ | \--* CNS_INT int 72 N008 ( 1, 1) [000841] ------------ \--* CNS_INT int 24 N002 ( 1, 1) [000033] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 ------------ BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ***** BB14 STMT00177 (IL ???... ???) N005 ( 0, 0) [001214] -A------R--- * ASG int N004 ( 0, 0) [001212] D------N---- +--* LCL_VAR int V15 tmp1 d:1 N003 ( 0, 0) [001213] ------------ \--* PHI int N001 ( 0, 0) [001245] ------------ pred BB12 +--* PHI_ARG int V15 tmp1 u:3 N002 ( 0, 0) [001244] ------------ pred BB13 \--* PHI_ARG int V15 tmp1 u:2 ***** BB14 STMT00008 (IL ???...0x061) N003 ( 3, 3) [000042] -A------R--- * ASG int N002 ( 1, 1) [000041] D------N---- +--* LCL_VAR int V06 loc2 d:1 N001 ( 3, 2) [000040] ------------ \--* LCL_VAR int V15 tmp1 u:1 (last use) ***** BB14 STMT00009 (IL 0x062...0x063) N003 ( 1, 3) [000045] -A------R--- * ASG int N002 ( 1, 1) [000044] D------N---- +--* LCL_VAR int V07 loc3 d:1 N001 ( 1, 1) [000043] ------------ \--* CNS_INT int 0 ***** BB14 STMT00098 (IL 0x064... ???) N006 ( 4, 4) [000580] -A-XG---R--- * ASG ref N005 ( 1, 1) [000579] D------N---- +--* LCL_VAR ref V39 tmp25 d:1 N004 ( 4, 4) [000578] ---XG------- \--* IND ref N003 ( 2, 2) [000845] -------N---- \--* ADD byref N001 ( 1, 1) [000046] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000844] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] ***** BB14 STMT00105 (IL 0x064... ???) N004 ( 3, 3) [000629] -A-X----R--- * ASG int N003 ( 1, 1) [000628] D------N---- +--* LCL_VAR int V40 tmp26 d:1 N002 ( 3, 3) [000583] ---X-------- \--* ARR_LENGTH int N001 ( 1, 1) [000582] ------------ \--* LCL_VAR ref V39 tmp25 u:1 ***** BB14 STMT00106 (IL 0x064... ???) N006 ( 4, 4) [000631] -A-XG---R--- * ASG long N005 ( 1, 1) [000630] D------N---- +--* LCL_VAR long V41 tmp27 d:1 N004 ( 4, 4) [000585] ---XG------- \--* IND long N003 ( 2, 2) [000847] -------N---- \--* ADD byref N001 ( 1, 1) [000584] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000846] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] ***** BB14 STMT00108 (IL 0x064... ???) N005 ( 6, 6) [000642] -A------R--- * ASG bool N004 ( 1, 1) [000641] D------N---- +--* LCL_VAR int V43 tmp29 d:1 N003 ( 6, 6) [000599] N--------U-- \--* LE int N001 ( 1, 1) [000597] ------------ +--* LCL_VAR int V40 tmp26 u:1 N002 ( 1, 4) [000598] ------------ \--* CNS_INT int 0x7FFFFFFF ***** BB14 STMT00111 (IL 0x064... ???) N004 ( 4, 12) [000652] -A--G---R--- * ASG ref N003 ( 1, 1) [000651] D------N---- +--* LCL_VAR ref V44 tmp30 d:1 N002 ( 4, 12) [000636] #---G------- \--* IND ref N001 ( 2, 10) [000635] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB14 STMT00112 (IL 0x064... ???) N004 ( 4, 12) [000654] -A--G---R--- * ASG ref N003 ( 1, 1) [000653] D------N---- +--* LCL_VAR ref V45 tmp31 d:1 N002 ( 4, 12) [000638] #---G------- \--* IND ref N001 ( 2, 10) [000637] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB14 STMT00109 (IL 0x064... ???) N004 ( 5, 5) [000647] ------------ * JTRUE void N003 ( 3, 3) [000646] J------N---- \--* NE int N001 ( 1, 1) [000644] ------------ +--* LCL_VAR int V43 tmp29 u:1 (last use) N002 ( 1, 1) [000645] ------------ \--* CNS_INT int 0 ------------ BB15 [064..065), preds={BB14} succs={BB16} ***** BB15 STMT00110 (IL 0x064... ???) N005 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 1, 1) [000648] ------------ arg0 in rcx +--* LCL_VAR ref V44 tmp30 u:1 (last use) N004 ( 1, 1) [000649] ------------ arg1 in rdx \--* LCL_VAR ref V45 tmp31 u:1 (last use) ------------ BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} ***** BB16 STMT00103 (IL 0x064... ???) N016 ( 20, 21) [000619] -A------R--- * ASG int N015 ( 1, 1) [000618] D------N---- +--* LCL_VAR int V42 tmp28 d:1 N014 ( 20, 21) [000617] ------------ \--* CAST int <- uint <- long N013 ( 19, 19) [000616] ------------ \--* RSZ long N011 ( 17, 17) [000614] ------------ +--* MUL long N008 ( 11, 11) [000611] ------------ | +--* ADD long N006 ( 9, 9) [000608] ------------ | | +--* RSZ long N004 ( 7, 7) [000606] ------------ | | | +--* MUL long N001 ( 1, 1) [000604] ------------ | | | | +--* LCL_VAR long V41 tmp27 u:1 (last use) N003 ( 2, 3) [000605] ---------U-- | | | | \--* CAST long <- ulong <- uint N002 ( 1, 1) [000047] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 N005 ( 1, 1) [000607] ------------ | | | \--* CNS_INT int 32 N007 ( 1, 1) [000610] ------------ | | \--* CNS_INT long 1 N010 ( 2, 3) [000613] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000612] ------------ | \--* LCL_VAR int V40 tmp26 u:1 N012 ( 1, 1) [000615] ------------ \--* CNS_INT int 32 ***** BB16 STMT00114 (IL 0x064... ???) N007 ( 27, 7) [000665] -A-X----R--- * ASG bool N006 ( 1, 1) [000664] D------N---- +--* LCL_VAR int V46 tmp32 d:1 N005 ( 27, 7) [000624] ---X-------- \--* EQ int N003 ( 22, 5) [000623] ---X-------- +--* UMOD int N001 ( 1, 1) [000621] ------------ | +--* LCL_VAR int V06 loc2 u:1 N002 ( 1, 1) [000622] ------------ | \--* LCL_VAR int V40 tmp26 u:1 (last use) N004 ( 1, 1) [000620] ------------ \--* LCL_VAR int V42 tmp28 u:1 ***** BB16 STMT00117 (IL 0x064... ???) N004 ( 4, 12) [000675] -A--G---R--- * ASG ref N003 ( 1, 1) [000674] D------N---- +--* LCL_VAR ref V47 tmp33 d:1 N002 ( 4, 12) [000659] #---G------- \--* IND ref N001 ( 2, 10) [000658] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB16 STMT00118 (IL 0x064... ???) N004 ( 4, 12) [000677] -A--G---R--- * ASG ref N003 ( 1, 1) [000676] D------N---- +--* LCL_VAR ref V48 tmp34 d:1 N002 ( 4, 12) [000661] #---G------- \--* IND ref N001 ( 2, 10) [000660] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB16 STMT00115 (IL 0x064... ???) N004 ( 5, 5) [000670] ------------ * JTRUE void N003 ( 3, 3) [000669] J------N---- \--* NE int N001 ( 1, 1) [000667] ------------ +--* LCL_VAR int V46 tmp32 u:1 (last use) N002 ( 1, 1) [000668] ------------ \--* CNS_INT int 0 ------------ BB17 [064..065), preds={BB16} succs={BB18} ***** BB17 STMT00116 (IL 0x064... ???) N005 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 1, 1) [000671] ------------ arg0 in rcx +--* LCL_VAR ref V47 tmp33 u:1 (last use) N004 ( 1, 1) [000672] ------------ arg1 in rdx \--* LCL_VAR ref V48 tmp34 u:1 (last use) ------------ BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} ***** BB18 STMT00100 (IL 0x064... ???) N017 ( 19, 24) [000591] -A-XG---R--- * ASG byref N016 ( 1, 1) [000590] D------N---- +--* LCL_VAR byref V38 tmp24 d:1 N015 ( 19, 24) [000862] ---XG------- \--* COMMA byref N004 ( 8, 11) [000855] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000627] ------------ | +--* LCL_VAR int V42 tmp28 u:1 N003 ( 3, 3) [000854] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000581] ------------ | \--* LCL_VAR ref V39 tmp25 u:1 N014 ( 11, 13) [000863] ----G------- \--* ADDR byref N013 ( 6, 7) [000588] a---G--N---- \--* IND int N012 ( 5, 6) [000861] -------N---- \--* ADD byref N005 ( 1, 1) [000852] ------------ +--* LCL_VAR ref V39 tmp25 u:1 (last use) N011 ( 4, 5) [000860] -------N---- \--* ADD long N009 ( 3, 4) [000858] -------N---- +--* LSH long N007 ( 2, 3) [000856] ------------ | +--* CAST long <- int N006 ( 1, 1) [000853] i----------- | | \--* LCL_VAR int V42 tmp28 u:1 (last use) N008 ( 1, 1) [000857] -------N---- | \--* CNS_INT long 2 N010 ( 1, 1) [000859] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB18 STMT00011 (IL ???... ???) N003 ( 5, 4) [000051] -A------R--- * ASG byref N002 ( 3, 2) [000050] D------N---- +--* LCL_VAR byref V08 loc4 d:1 N001 ( 1, 1) [000592] ------------ \--* LCL_VAR byref V38 tmp24 u:1 ***** BB18 STMT00012 (IL 0x06D...0x072) N006 ( 5, 4) [000057] -A-XG---R--- * ASG int N005 ( 1, 1) [000056] D------N---- +--* LCL_VAR int V09 loc5 d:1 N004 ( 5, 4) [000055] ---XG------- \--* ADD int N002 ( 3, 2) [000053] *--XG------- +--* IND int N001 ( 1, 1) [000052] ------------ | \--* LCL_VAR byref V38 tmp24 u:1 (last use) N003 ( 1, 1) [000054] ------------ \--* CNS_INT int -1 ***** BB18 STMT00013 (IL 0x074...0x075) N004 ( 5, 5) [000061] ------------ * JTRUE void N003 ( 3, 3) [000060] J------N---- \--* NE int N001 ( 1, 1) [000058] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000059] ------------ \--* CNS_INT ref null ------------ BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} ***** BB19 STMT00059 (IL 0x0FF...0x104) N004 ( 3, 3) [000356] -A-X----R--- * ASG long N003 ( 1, 1) [000355] D------N---- +--* LCL_VAR long V24 tmp10 d:1 N002 ( 3, 2) [000354] #--X-------- \--* IND long N001 ( 1, 1) [000353] !----------- \--* LCL_VAR ref V00 this u:1 ***** BB19 STMT00152 (IL ???... ???) N011 ( 14, 13) [001153] ------------ * JTRUE void N010 ( 12, 11) [000369] J------N---- \--* EQ int N008 ( 10, 9) [000365] n----------- +--* IND long N007 ( 8, 7) [000364] -------N---- | \--* ADD long N005 ( 7, 6) [000362] #----------- | +--* IND long N004 ( 4, 4) [000361] #----------- | | \--* IND long N003 ( 2, 2) [000360] -------N---- | | \--* ADD long N001 ( 1, 1) [000358] ------------ | | +--* LCL_VAR long V24 tmp10 u:1 N002 ( 1, 1) [000359] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000363] ------------ | \--* CNS_INT long 32 N009 ( 1, 1) [000368] ------------ \--* CNS_INT long 0 ------------ BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} ***** BB20 STMT00153 (IL ???... ???) N010 ( 14, 12) [001155] -A------R--- * ASG long N009 ( 3, 2) [001154] D------N---- +--* LCL_VAR long V25 tmp11 d:3 N008 ( 10, 9) [000370] n-----?----- \--* IND long N007 ( 8, 7) [000371] ------?N---- \--* ADD long N005 ( 7, 6) [000372] #-----?----- +--* IND long N004 ( 4, 4) [000373] #-----?----- | \--* IND long N003 ( 2, 2) [000374] ------?N---- | \--* ADD long N001 ( 1, 1) [000375] ------?----- | +--* LCL_VAR long V24 tmp10 u:1 (last use) N002 ( 1, 1) [000376] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000377] ------?----- \--* CNS_INT long 32 ------------ BB21 [???..???), preds={BB19} succs={BB22} ***** BB21 STMT00154 (IL ???... ???) N007 ( 21, 21) [001157] -AC-G---R--- * ASG long N006 ( 3, 2) [001156] D------N---- +--* LCL_VAR long V25 tmp11 d:2 N005 ( 17, 18) [000367] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 1, 1) [000357] ------?----- arg0 in rcx +--* LCL_VAR long V24 tmp10 u:1 (last use) N004 ( 2, 10) [000366] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB22 [???..106), preds={BB20,BB21} succs={BB23} ***** BB22 STMT00172 (IL ???... ???) N005 ( 0, 0) [001199] -A------R--- * ASG long N004 ( 0, 0) [001197] D------N---- +--* LCL_VAR long V25 tmp11 d:1 N003 ( 0, 0) [001198] ------------ \--* PHI long N001 ( 0, 0) [001243] ------------ pred BB20 +--* PHI_ARG long V25 tmp11 u:3 N002 ( 0, 0) [001242] ------------ pred BB21 \--* PHI_ARG long V25 tmp11 u:2 ***** BB22 STMT00062 (IL ???... ???) N005 ( 17, 8) [000386] -ACXG---R--- * ASG ref N004 ( 1, 1) [000385] D------N---- +--* LCL_VAR ref V12 loc8 d:1 N003 ( 17, 8) [000352] --CXG------- \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default N002 ( 3, 2) [000382] ------------ arg0 in rcx \--* LCL_VAR long V25 tmp11 u:1 (last use) ------------ BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} ***** BB23 STMT00165 (IL ???... ???) N005 ( 0, 0) [001178] -A------R--- * ASG int N004 ( 0, 0) [001176] D------N---- +--* LCL_VAR int V07 loc3 d:5 N003 ( 0, 0) [001177] ------------ \--* PHI int N001 ( 0, 0) [001238] ------------ pred BB27 +--* PHI_ARG int V07 loc3 u:6 N002 ( 0, 0) [001235] ------------ pred BB22 \--* PHI_ARG int V07 loc3 u:1 ***** BB23 STMT00164 (IL ???... ???) N005 ( 0, 0) [001175] -A------R--- * ASG int N004 ( 0, 0) [001173] D------N---- +--* LCL_VAR int V09 loc5 d:4 N003 ( 0, 0) [001174] ------------ \--* PHI int N001 ( 0, 0) [001239] ------------ pred BB27 +--* PHI_ARG int V09 loc5 u:5 N002 ( 0, 0) [001236] ------------ pred BB22 \--* PHI_ARG int V09 loc5 u:1 ***** BB23 STMT00063 (IL 0x106...0x10B) N005 ( 7, 7) [000391] ---X-------- * JTRUE void N004 ( 5, 5) [000390] N--X---N-U-- \--* LE int N002 ( 3, 3) [000389] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000388] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000387] ------------ \--* LCL_VAR int V09 loc5 u:4 ------------ BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} ***** BB24 STMT00064 (IL 0x110...0x11E) N023 ( 36, 39) [000399] ---XG------- * JTRUE void N022 ( 34, 37) [000398] N--XG--N-U-- \--* NE int N020 ( 32, 35) [000396] *--XG------- +--* IND int N019 ( 30, 33) [000868] ---XG--N---- | \--* ADD byref N017 ( 29, 32) [000879] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000872] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000393] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 N003 ( 3, 3) [000871] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000392] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000882] ----G------- | | \--* ADDR byref N015 ( 11, 11) [000394] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000878] -------N---- | | \--* ADD byref N005 ( 1, 1) [000869] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000877] -------N---- | | \--* ADD long N011 ( 8, 8) [000875] -------N---- | | +--* LSH long N009 ( 7, 7) [000881] ------------ | | | +--* MUL long N007 ( 2, 3) [000873] ------------ | | | | +--* CAST long <- int N006 ( 1, 1) [000870] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 N008 ( 1, 1) [000880] ------------ | | | | \--* CNS_INT long 3 N010 ( 1, 1) [000874] -------N---- | | | \--* CNS_INT long 3 N012 ( 1, 1) [000876] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000867] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] N021 ( 1, 1) [000397] ------------ \--* LCL_VAR int V06 loc2 u:1 ------------ BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} ***** BB25 STMT00069 (IL 0x120...0x135) N035 ( 67, 59) [000428] --CXG------- * JTRUE void N034 ( 65, 57) [000427] J-CXG--N---- \--* NE int N032 ( 63, 55) [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals N031 ( 9, 8) [000908] n--X-------- control expr | \--* IND long N030 ( 7, 6) [000907] ---X---N---- | \--* ADD long N028 ( 6, 5) [000905] #--X-------- | +--* IND long N027 ( 4, 3) [000904] ---X---N---- | | \--* ADD long N025 ( 3, 2) [000902] #--X-------- | | +--* IND long N024 ( 1, 1) [000901] ------------ | | | \--* LCL_VAR ref V12 loc8 u:1 N026 ( 1, 1) [000903] ------------ | | \--* CNS_INT int 72 N029 ( 1, 1) [000906] ------------ | \--* CNS_INT int 32 N021 ( 32, 34) [000893] ---XG------- arg1 in rdx | +--* COMMA ref N007 ( 8, 11) [000886] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N004 ( 1, 1) [000420] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 N006 ( 3, 3) [000885] ---X-------- | | | \--* ARR_LENGTH int N005 ( 1, 1) [000419] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N020 ( 24, 23) [000897] *---G------- | | \--* IND ref N019 ( 21, 21) [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] N018 ( 11, 11) [000421] a---G--N---- | | \--* IND struct N017 ( 10, 10) [000892] -------N---- | | \--* ADD byref N008 ( 1, 1) [000883] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N016 ( 9, 9) [000891] -------N---- | | \--* ADD long N014 ( 8, 8) [000889] -------N---- | | +--* LSH long N012 ( 7, 7) [000895] ------------ | | | +--* MUL long N010 ( 2, 3) [000887] ------------ | | | | +--* CAST long <- int N009 ( 1, 1) [000884] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 N011 ( 1, 1) [000894] ------------ | | | | \--* CNS_INT long 3 N013 ( 1, 1) [000888] -------N---- | | | \--* CNS_INT long 3 N015 ( 1, 1) [000890] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N022 ( 1, 1) [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 u:1 N023 ( 1, 1) [000424] ------------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 u:1 N033 ( 1, 1) [000426] ------------ \--* CNS_INT int 0 ------------ BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} ***** BB26 STMT00065 (IL 0x157...0x164) N022 ( 32, 35) [000406] -A-XG---R--- * ASG int N021 ( 1, 1) [000405] D------N---- +--* LCL_VAR int V09 loc5 d:5 N020 ( 32, 35) [000404] *--XG------- \--* IND int N019 ( 30, 33) [000932] ---XG--N---- \--* ADD byref N017 ( 29, 32) [000943] ---XG------- +--* COMMA byref N004 ( 8, 11) [000936] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000401] ------------ | | +--* LCL_VAR int V09 loc5 u:4 N003 ( 3, 3) [000935] ---X-------- | | \--* ARR_LENGTH int N002 ( 1, 1) [000400] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000946] ----G------- | \--* ADDR byref N015 ( 11, 11) [000402] a---G--N---- | \--* IND struct N014 ( 10, 10) [000942] -------N---- | \--* ADD byref N005 ( 1, 1) [000933] ------------ | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000941] -------N---- | \--* ADD long N011 ( 8, 8) [000939] -------N---- | +--* LSH long N009 ( 7, 7) [000945] ------------ | | +--* MUL long N007 ( 2, 3) [000937] ------------ | | | +--* CAST long <- int N006 ( 1, 1) [000934] i----------- | | | | \--* LCL_VAR int V09 loc5 u:4 (last use) N008 ( 1, 1) [000944] ------------ | | | \--* CNS_INT long 3 N010 ( 1, 1) [000938] -------N---- | | \--* CNS_INT long 3 N012 ( 1, 1) [000940] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000931] ------------ \--* CNS_INT long 20 field offset Fseq[next] ***** BB26 STMT00066 (IL 0x166...0x169) N005 ( 3, 3) [000411] -A------R--- * ASG int N004 ( 1, 1) [000410] D------N---- +--* LCL_VAR int V07 loc3 d:6 N003 ( 3, 3) [000409] ------------ \--* ADD int N001 ( 1, 1) [000407] ------------ +--* LCL_VAR int V07 loc3 u:5 (last use) N002 ( 1, 1) [000408] ------------ \--* CNS_INT int 1 ***** BB26 STMT00067 (IL 0x16A...0x16E) N005 ( 7, 7) [000416] ---X-------- * JTRUE void N004 ( 5, 5) [000415] N--X---N-U-- \--* LT int N002 ( 3, 3) [000414] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000413] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000412] ------------ \--* LCL_VAR int V07 loc3 u:6 ------------ BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} ------------ BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} ***** BB28 STMT00070 (IL 0x137...0x139) N005 ( 7, 8) [000432] ------------ * JTRUE void N004 ( 5, 6) [000431] N------N-U-- \--* NE int N002 ( 3, 4) [000909] ------------ +--* CAST int <- ubyte <- int N001 ( 2, 2) [000429] ------------ | \--* LCL_VAR int V03 arg3 u:1 N003 ( 1, 1) [000430] ------------ \--* CNS_INT int 1 ------------ BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} ***** BB29 STMT00077 (IL 0x13B...0x144) N022 ( 34, 37) [000481] -A-XG------- * ASG ref N020 ( 32, 35) [000480] *--XG--N---- +--* IND ref N019 ( 30, 33) [000911] ---XG--N---- | \--* ADD byref N017 ( 29, 32) [000922] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000915] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000476] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 N003 ( 3, 3) [000914] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000475] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000925] ----G------- | | \--* ADDR byref N015 ( 11, 11) [000477] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000921] -------N---- | | \--* ADD byref N005 ( 1, 1) [000912] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 (last use) N013 ( 9, 9) [000920] -------N---- | | \--* ADD long N011 ( 8, 8) [000918] -------N---- | | +--* LSH long N009 ( 7, 7) [000924] ------------ | | | +--* MUL long N007 ( 2, 3) [000916] ------------ | | | | +--* CAST long <- int N006 ( 1, 1) [000913] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 (last use) N008 ( 1, 1) [000923] ------------ | | | | \--* CNS_INT long 3 N010 ( 1, 1) [000917] -------N---- | | | \--* CNS_INT long 3 N012 ( 1, 1) [000919] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000910] ------------ | \--* CNS_INT long 8 field offset Fseq[value] N021 ( 1, 1) [000479] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) ------------ BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} ***** BB30 STMT00071 (IL 0x14B...0x14D) N005 ( 7, 8) [000436] ------------ * JTRUE void N004 ( 5, 6) [000435] N------N-U-- \--* EQ int N002 ( 3, 4) [000926] ------------ +--* CAST int <- ubyte <- int N001 ( 2, 2) [000433] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) N003 ( 1, 1) [000434] ------------ \--* CNS_INT int 2 ------------ BB31 [???..???) (return), preds={BB30,BB41} succs={} ***** BB31 STMT00148 (IL ???... ???) N002 ( 2, 2) [000811] ------------ * RETURN int N001 ( 1, 1) [000437] ------------ \--* CNS_INT int 0 ------------ BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} ***** BB32 STMT00175 (IL ???... ???) N005 ( 0, 0) [001208] -A------R--- * ASG int N004 ( 0, 0) [001206] D------N---- +--* LCL_VAR int V07 loc3 d:3 N003 ( 0, 0) [001207] ------------ \--* PHI int N001 ( 0, 0) [001229] ------------ pred BB43 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [001218] ------------ pred BB18 \--* PHI_ARG int V07 loc3 u:1 ***** BB32 STMT00174 (IL ???... ???) N005 ( 0, 0) [001205] -A------R--- * ASG int N004 ( 0, 0) [001203] D------N---- +--* LCL_VAR int V09 loc5 d:2 N003 ( 0, 0) [001204] ------------ \--* PHI int N001 ( 0, 0) [001230] ------------ pred BB43 +--* PHI_ARG int V09 loc5 u:3 N002 ( 0, 0) [001219] ------------ pred BB18 \--* PHI_ARG int V09 loc5 u:1 ***** BB32 STMT00014 (IL 0x177...0x17C) N005 ( 7, 7) [000066] ---X-------- * JTRUE void N004 ( 5, 5) [000065] N--X---N-U-- \--* LE int N002 ( 3, 3) [000064] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000063] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000062] ------------ \--* LCL_VAR int V09 loc5 u:2 ------------ BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} ***** BB33 STMT00039 (IL 0x17E...0x18C) N023 ( 36, 39) [000215] ---XG------- * JTRUE void N022 ( 34, 37) [000214] N--XG--N-U-- \--* NE int N020 ( 32, 35) [000212] *--XG------- +--* IND int N019 ( 30, 33) [000948] ---XG--N---- | \--* ADD byref N017 ( 29, 32) [000959] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000952] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000209] ------------ | | | +--* LCL_VAR int V09 loc5 u:2 N003 ( 3, 3) [000951] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000208] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000962] ----G------- | | \--* ADDR byref N015 ( 11, 11) [000210] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000958] -------N---- | | \--* ADD byref N005 ( 1, 1) [000949] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000957] -------N---- | | \--* ADD long N011 ( 8, 8) [000955] -------N---- | | +--* LSH long N009 ( 7, 7) [000961] ------------ | | | +--* MUL long N007 ( 2, 3) [000953] ------------ | | | | +--* CAST long <- int N006 ( 1, 1) [000950] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:2 N008 ( 1, 1) [000960] ------------ | | | | \--* CNS_INT long 3 N010 ( 1, 1) [000954] -------N---- | | | \--* CNS_INT long 3 N012 ( 1, 1) [000956] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000947] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] N021 ( 1, 1) [000213] ------------ \--* LCL_VAR int V06 loc2 u:1 ------------ BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} ***** BB34 STMT00045 (IL 0x18E...0x1A2) N020 ( 32, 34) [000246] -A-XG---R--- * ASG ref N019 ( 1, 1) [000245] D------N---- +--* LCL_VAR ref V17 tmp3 d:1 N018 ( 32, 34) [000973] ---XG------- \--* COMMA ref N004 ( 8, 11) [000966] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000236] ------------ | +--* LCL_VAR int V09 loc5 u:2 N003 ( 3, 3) [000965] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000235] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N017 ( 24, 23) [000977] *---G------- \--* IND ref N016 ( 21, 21) [000976] ----G------- \--* ADDR byref Zero Fseq[key] N015 ( 11, 11) [000237] a---G--N---- \--* IND struct N014 ( 10, 10) [000972] -------N---- \--* ADD byref N005 ( 1, 1) [000963] ------------ +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000971] -------N---- \--* ADD long N011 ( 8, 8) [000969] -------N---- +--* LSH long N009 ( 7, 7) [000975] ------------ | +--* MUL long N007 ( 2, 3) [000967] ------------ | | +--* CAST long <- int N006 ( 1, 1) [000964] i----------- | | | \--* LCL_VAR int V09 loc5 u:2 N008 ( 1, 1) [000974] ------------ | | \--* CNS_INT long 3 N010 ( 1, 1) [000968] -------N---- | \--* CNS_INT long 3 N012 ( 1, 1) [000970] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB34 STMT00044 (IL 0x18E... ???) N004 ( 3, 3) [000244] -A-X----R--- * ASG long N003 ( 1, 1) [000243] D------N---- +--* LCL_VAR long V16 tmp2 d:1 N002 ( 3, 2) [000242] #--X-------- \--* IND long N001 ( 1, 1) [000241] !----------- \--* LCL_VAR ref V00 this u:1 ***** BB34 STMT00158 (IL ???... ???) N011 ( 14, 13) [001163] ------------ * JTRUE void N010 ( 12, 11) [000263] J------N---- \--* EQ int N008 ( 10, 9) [000259] n----------- +--* IND long N007 ( 8, 7) [000255] -------N---- | \--* ADD long N005 ( 7, 6) [000253] #----------- | +--* IND long N004 ( 4, 4) [000252] #----------- | | \--* IND long N003 ( 2, 2) [000251] -------N---- | | \--* ADD long N001 ( 1, 1) [000249] ------------ | | +--* LCL_VAR long V16 tmp2 u:1 N002 ( 1, 1) [000250] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000254] ------------ | \--* CNS_INT long 48 N009 ( 1, 1) [000262] ------------ \--* CNS_INT long 0 ------------ BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} ***** BB35 STMT00159 (IL ???... ???) N010 ( 10, 9) [001165] -A------R--- * ASG long N009 ( 1, 1) [001164] D------N---- +--* LCL_VAR long V19 tmp5 d:3 N008 ( 10, 9) [000264] n-----?----- \--* IND long N007 ( 8, 7) [000265] ------?N---- \--* ADD long N005 ( 7, 6) [000266] #-----?----- +--* IND long N004 ( 4, 4) [000267] #-----?----- | \--* IND long N003 ( 2, 2) [000268] ------?N---- | \--* ADD long N001 ( 1, 1) [000269] ------?----- | +--* LCL_VAR long V16 tmp2 u:1 (last use) N002 ( 1, 1) [000270] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000271] ------?----- \--* CNS_INT long 48 ------------ BB36 [???..???), preds={BB34} succs={BB37} ***** BB36 STMT00160 (IL ???... ???) N007 ( 17, 18) [001167] -AC-G---R--- * ASG long N006 ( 1, 1) [001166] D------N---- +--* LCL_VAR long V19 tmp5 d:2 N005 ( 17, 18) [000261] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 1, 1) [000248] ------?----- arg0 in rcx +--* LCL_VAR long V16 tmp2 u:1 (last use) N004 ( 2, 10) [000260] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} ***** BB37 STMT00176 (IL ???... ???) N005 ( 0, 0) [001211] -A------R--- * ASG long N004 ( 0, 0) [001209] D------N---- +--* LCL_VAR long V19 tmp5 d:1 N003 ( 0, 0) [001210] ------------ \--* PHI long N001 ( 0, 0) [001234] ------------ pred BB35 +--* PHI_ARG long V19 tmp5 u:3 N002 ( 0, 0) [001233] ------------ pred BB36 \--* PHI_ARG long V19 tmp5 u:2 ***** BB37 STMT00049 (IL ???... ???) N013 ( 32, 18) [000283] --CXG------- * JTRUE void N012 ( 30, 16) [000282] J-CXG--N---- \--* EQ int N010 ( 28, 14) [000280] --CXG------- +--* CALL ind stub int N009 ( 1, 1) [000279] ------------ calli tgt | \--* LCL_VAR long V19 tmp5 u:1 (last use) N005 ( 1, 1) [000234] ------------ this in rcx | +--* LCL_VAR ref V05 loc1 u:1 N006 ( 1, 1) [000980] ------------ arg1 in r11 | +--* LCL_VAR long V19 tmp5 u:1 r11 REG r11 N007 ( 1, 1) [000247] ------------ arg2 in rdx | +--* LCL_VAR ref V17 tmp3 u:1 (last use) N008 ( 1, 1) [000258] ------------ arg3 in r8 | \--* LCL_VAR ref V01 arg1 u:1 N011 ( 1, 1) [000281] ------------ \--* CNS_INT int 0 ------------ BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} ***** BB38 STMT00050 (IL 0x1A4...0x1A6) N005 ( 7, 8) [000287] ------------ * JTRUE void N004 ( 5, 6) [000286] N------N-U-- \--* NE int N002 ( 3, 4) [000985] ------------ +--* CAST int <- ubyte <- int N001 ( 2, 2) [000284] ------------ | \--* LCL_VAR int V03 arg3 u:1 N003 ( 1, 1) [000285] ------------ \--* CNS_INT int 1 ------------ BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} ***** BB39 STMT00057 (IL 0x1A8...0x1B1) N022 ( 34, 37) [000336] -A-XG------- * ASG ref N020 ( 32, 35) [000335] *--XG--N---- +--* IND ref N019 ( 30, 33) [000987] ---XG--N---- | \--* ADD byref N017 ( 29, 32) [000998] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000991] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000331] ------------ | | | +--* LCL_VAR int V09 loc5 u:2 N003 ( 3, 3) [000990] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000330] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [001001] ----G------- | | \--* ADDR byref N015 ( 11, 11) [000332] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000997] -------N---- | | \--* ADD byref N005 ( 1, 1) [000988] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 (last use) N013 ( 9, 9) [000996] -------N---- | | \--* ADD long N011 ( 8, 8) [000994] -------N---- | | +--* LSH long N009 ( 7, 7) [001000] ------------ | | | +--* MUL long N007 ( 2, 3) [000992] ------------ | | | | +--* CAST long <- int N006 ( 1, 1) [000989] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:2 (last use) N008 ( 1, 1) [000999] ------------ | | | | \--* CNS_INT long 3 N010 ( 1, 1) [000993] -------N---- | | | \--* CNS_INT long 3 N012 ( 1, 1) [000995] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000986] ------------ | \--* CNS_INT long 8 field offset Fseq[value] N021 ( 1, 1) [000334] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) ------------ BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} ***** BB40 STMT00051 (IL 0x1B8...0x1BA) N005 ( 7, 8) [000291] ------------ * JTRUE void N004 ( 5, 6) [000290] N------N-U-- \--* EQ int N002 ( 3, 4) [001002] ------------ +--* CAST int <- ubyte <- int N001 ( 2, 2) [000288] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) N003 ( 1, 1) [000289] ------------ \--* CNS_INT int 2 ------------ BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} ------------ BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} ***** BB42 STMT00040 (IL 0x1C4...0x1D1) N022 ( 32, 35) [000222] -A-XG---R--- * ASG int N021 ( 1, 1) [000221] D------N---- +--* LCL_VAR int V09 loc5 d:3 N020 ( 32, 35) [000220] *--XG------- \--* IND int N019 ( 30, 33) [001009] ---XG--N---- \--* ADD byref N017 ( 29, 32) [001020] ---XG------- +--* COMMA byref N004 ( 8, 11) [001013] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000217] ------------ | | +--* LCL_VAR int V09 loc5 u:2 N003 ( 3, 3) [001012] ---X-------- | | \--* ARR_LENGTH int N002 ( 1, 1) [000216] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [001023] ----G------- | \--* ADDR byref N015 ( 11, 11) [000218] a---G--N---- | \--* IND struct N014 ( 10, 10) [001019] -------N---- | \--* ADD byref N005 ( 1, 1) [001010] ------------ | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [001018] -------N---- | \--* ADD long N011 ( 8, 8) [001016] -------N---- | +--* LSH long N009 ( 7, 7) [001022] ------------ | | +--* MUL long N007 ( 2, 3) [001014] ------------ | | | +--* CAST long <- int N006 ( 1, 1) [001011] i----------- | | | | \--* LCL_VAR int V09 loc5 u:2 (last use) N008 ( 1, 1) [001021] ------------ | | | \--* CNS_INT long 3 N010 ( 1, 1) [001015] -------N---- | | \--* CNS_INT long 3 N012 ( 1, 1) [001017] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [001008] ------------ \--* CNS_INT long 20 field offset Fseq[next] ***** BB42 STMT00041 (IL 0x1D3...0x1D6) N005 ( 3, 3) [000227] -A------R--- * ASG int N004 ( 1, 1) [000226] D------N---- +--* LCL_VAR int V07 loc3 d:4 N003 ( 3, 3) [000225] ------------ \--* ADD int N001 ( 1, 1) [000223] ------------ +--* LCL_VAR int V07 loc3 u:3 (last use) N002 ( 1, 1) [000224] ------------ \--* CNS_INT int 1 ***** BB42 STMT00042 (IL 0x1D7...0x1DB) N005 ( 7, 7) [000232] ---X-------- * JTRUE void N004 ( 5, 5) [000231] N--X---N-U-- \--* LT int N002 ( 3, 3) [000230] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000229] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000228] ------------ \--* LCL_VAR int V07 loc3 u:4 ------------ BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} ------------ BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} ***** BB44 STMT00166 (IL ???... ???) N005 ( 0, 0) [001181] -A------R--- * ASG int N004 ( 0, 0) [001179] D------N---- +--* LCL_VAR int V07 loc3 d:2 N003 ( 0, 0) [001180] ------------ \--* PHI int N001 ( 0, 0) [001237] ------------ pred BB23 +--* PHI_ARG int V07 loc3 u:5 N002 ( 0, 0) [001228] ------------ pred BB32 \--* PHI_ARG int V07 loc3 u:3 ***** BB44 STMT00015 (IL 0x1E4...0x1EB) N007 ( 8, 8) [000071] ---XG------- * JTRUE void N006 ( 6, 6) [000070] J--XG--N---- \--* LE int N004 ( 4, 4) [000068] ---XG------- +--* IND int N003 ( 2, 2) [001025] -------N---- | \--* ADD byref N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001024] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] N005 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 ------------ BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} ***** BB45 STMT00035 (IL 0x1ED...0x1F3) N006 ( 8, 7) [000174] -A-XG---R--- * ASG int N005 ( 3, 2) [000173] D------N---- +--* LCL_VAR int V10 loc6 d:3 N004 ( 4, 4) [000172] ---XG------- \--* IND int N003 ( 2, 2) [001027] -------N---- \--* ADD byref N001 ( 1, 1) [000171] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001026] ------------ \--* CNS_INT long 60 field offset Fseq[_freeList] ***** BB45 STMT00120 (IL 0x1F5... ???) N034 ( 48, 47) [000688] -A-XG---R--- * ASG bool N033 ( 3, 2) [000687] D------N---- +--* LCL_VAR int V49 tmp35 d:1 N032 ( 44, 44) [000184] -A-XG------- \--* GE int N030 ( 39, 42) [000182] -A-XG------- +--* ADD int N028 ( 37, 40) [001050] -A-XG------- | +--* NEG int N027 ( 36, 39) [000181] *A-XG------- | | \--* IND int N026 ( 34, 37) [001029] -A-XG--N---- | | \--* ADD byref N024 ( 33, 36) [001044] -A-XG------- | | +--* COMMA byref N006 ( 4, 4) [001032] -A-XG---R--- | | | +--* ASG int N005 ( 1, 1) [001031] D------N---- | | | | +--* LCL_VAR int V62 tmp48 d:1 N004 ( 4, 4) [000178] ---XG------- | | | | \--* IND int N003 ( 2, 2) [001046] -------N---- | | | | \--* ADD byref N001 ( 1, 1) [000177] ------------ | | | | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001045] ------------ | | | | \--* CNS_INT long 60 field offset Fseq[_freeList] N023 ( 29, 32) [001043] ---XG------- | | | \--* COMMA byref N010 ( 8, 11) [001036] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [001033] ------------ | | | | +--* LCL_VAR int V62 tmp48 u:1 N009 ( 3, 3) [001035] ---X-------- | | | | \--* ARR_LENGTH int N008 ( 1, 1) [000176] ------------ | | | | \--* LCL_VAR ref V04 loc0 u:1 N022 ( 21, 21) [001049] ----G------- | | | \--* ADDR byref N021 ( 11, 11) [000179] a---G--N---- | | | \--* IND struct N020 ( 10, 10) [001042] -------N---- | | | \--* ADD byref N011 ( 1, 1) [001030] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N019 ( 9, 9) [001041] -------N---- | | | \--* ADD long N017 ( 8, 8) [001039] -------N---- | | | +--* LSH long N015 ( 7, 7) [001048] ------------ | | | | +--* MUL long N013 ( 2, 3) [001037] ------------ | | | | | +--* CAST long <- int N012 ( 1, 1) [001034] i----------- | | | | | | \--* LCL_VAR int V62 tmp48 u:1 (last use) N014 ( 1, 1) [001047] ------------ | | | | | \--* CNS_INT long 3 N016 ( 1, 1) [001038] -------N---- | | | | \--* CNS_INT long 3 N018 ( 1, 1) [001040] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] N025 ( 1, 1) [001028] ------------ | | \--* CNS_INT long 20 field offset Fseq[next] N029 ( 1, 1) [000175] ------------ | \--* CNS_INT int -3 N031 ( 1, 1) [000183] ------------ \--* CNS_INT int -1 ***** BB45 STMT00123 (IL 0x1F5... ???) N004 ( 8, 15) [000698] -A--G---R--- * ASG ref N003 ( 3, 2) [000697] D------N---- +--* LCL_VAR ref V50 tmp36 d:1 N002 ( 4, 12) [000684] #---G------- \--* IND ref N001 ( 2, 10) [000683] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB45 STMT00121 (IL 0x1F5... ???) N004 ( 7, 6) [000693] ------------ * JTRUE void N003 ( 5, 4) [000692] J------N---- \--* NE int N001 ( 3, 2) [000690] ------------ +--* LCL_VAR int V49 tmp35 u:1 (last use) N002 ( 1, 1) [000691] ------------ \--* CNS_INT int 0 ------------ BB46 [1F5..1F6), preds={BB45} succs={BB47} ***** BB46 STMT00122 (IL 0x1F5... ???) N006 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail N004 ( 4, 12) [001052] #---G------- arg0 in rcx +--* IND ref N003 ( 2, 10) [001051] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" N005 ( 3, 2) [000695] ------------ arg1 in rdx \--* LCL_VAR ref V50 tmp36 u:1 (last use) ------------ BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} ***** BB47 STMT00037 (IL 0x219... ???) N035 ( 44, 47) [000200] -A-XG------- * ASG int N004 ( 4, 4) [000199] D--XG--N---- +--* IND int N003 ( 2, 2) [001056] -------N---- | \--* ADD byref N001 ( 1, 1) [000190] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001055] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] N034 ( 39, 42) [000198] -A-XG------- \--* ADD int N032 ( 37, 40) [001079] -A-XG------- +--* NEG int N031 ( 36, 39) [000197] *A-XG------- | \--* IND int N030 ( 34, 37) [001058] -A-XG--N---- | \--* ADD byref N028 ( 33, 36) [001073] -A-XG------- | +--* COMMA byref N010 ( 4, 4) [001061] -A-XG---R--- | | +--* ASG int N009 ( 1, 1) [001060] D------N---- | | | +--* LCL_VAR int V63 tmp49 d:1 N008 ( 4, 4) [000194] ---XG------- | | | \--* IND int N007 ( 2, 2) [001075] -------N---- | | | \--* ADD byref N005 ( 1, 1) [000193] ------------ | | | +--* LCL_VAR ref V00 this u:1 N006 ( 1, 1) [001074] ------------ | | | \--* CNS_INT long 60 field offset Fseq[_freeList] N027 ( 29, 32) [001072] ---XG------- | | \--* COMMA byref N014 ( 8, 11) [001065] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N011 ( 1, 1) [001062] ------------ | | | +--* LCL_VAR int V63 tmp49 u:1 N013 ( 3, 3) [001064] ---X-------- | | | \--* ARR_LENGTH int N012 ( 1, 1) [000192] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N026 ( 21, 21) [001078] ----G------- | | \--* ADDR byref N025 ( 11, 11) [000195] a---G--N---- | | \--* IND struct N024 ( 10, 10) [001071] -------N---- | | \--* ADD byref N015 ( 1, 1) [001059] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N023 ( 9, 9) [001070] -------N---- | | \--* ADD long N021 ( 8, 8) [001068] -------N---- | | +--* LSH long N019 ( 7, 7) [001077] ------------ | | | +--* MUL long N017 ( 2, 3) [001066] ------------ | | | | +--* CAST long <- int N016 ( 1, 1) [001063] i----------- | | | | | \--* LCL_VAR int V63 tmp49 u:1 (last use) N018 ( 1, 1) [001076] ------------ | | | | \--* CNS_INT long 3 N020 ( 1, 1) [001067] -------N---- | | | \--* CNS_INT long 3 N022 ( 1, 1) [001069] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N029 ( 1, 1) [001057] ------------ | \--* CNS_INT long 20 field offset Fseq[next] N033 ( 1, 1) [000191] ------------ \--* CNS_INT int -3 ***** BB47 STMT00038 (IL 0x233...0x23C) N011 ( 11, 11) [000207] -A-XG---R--- * ASG int N010 ( 4, 4) [000206] D--XG--N---- +--* IND int N009 ( 2, 2) [001081] -------N---- | \--* ADD byref N007 ( 1, 1) [000201] ------------ | +--* LCL_VAR ref V00 this u:1 N008 ( 1, 1) [001080] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] N006 ( 6, 6) [000205] ---XG------- \--* ADD int N004 ( 4, 4) [000203] ---XG------- +--* IND int N003 ( 2, 2) [001083] -------N---- | \--* ADD byref N001 ( 1, 1) [000202] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001082] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] N005 ( 1, 1) [000204] ------------ \--* CNS_INT int -1 ------------ BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} ***** BB48 STMT00016 (IL 0x243...0x249) N006 ( 8, 7) [000075] -A-XG---R--- * ASG int N005 ( 3, 2) [000074] D------N---- +--* LCL_VAR int V13 loc9 d:1 N004 ( 4, 4) [000073] ---XG------- \--* IND int N003 ( 2, 2) [001085] -------N---- \--* ADD byref N001 ( 1, 1) [000072] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001084] ------------ \--* CNS_INT long 56 field offset Fseq[_count] ***** BB48 STMT00017 (IL 0x24B...0x250) N005 ( 9, 8) [000080] ---X-------- * JTRUE void N004 ( 7, 6) [000079] N--X---N-U-- \--* NE int N002 ( 3, 3) [000078] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000077] ------------ | \--* LCL_VAR ref V04 loc0 u:1 (last use) N003 ( 3, 2) [000076] ------------ \--* LCL_VAR int V13 loc9 u:1 ------------ BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00125 (IL 0x252... ???) N014 ( 44, 26) [000705] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize N009 ( 22, 13) [001090] -ACXG---R-L- arg1 SETUP +--* ASG int N008 ( 3, 2) [001089] D------N---- | +--* LCL_VAR int V64 tmp50 d:1 N007 ( 18, 10) [000702] --CXG------- | \--* CALL int System.Collections.HashHelpers.ExpandPrime N006 ( 4, 4) [000701] ---XG------- arg0 in rcx | \--* IND int N005 ( 2, 2) [001087] -------N---- | \--* ADD byref N003 ( 1, 1) [000700] ------------ | +--* LCL_VAR ref V00 this u:1 N004 ( 1, 1) [001086] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] N011 ( 3, 2) [001091] ------------ arg1 in rdx +--* LCL_VAR int V64 tmp50 u:1 (last use) N012 ( 1, 1) [000163] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 N013 ( 1, 1) [000704] ------------ arg2 in r8 \--* CNS_INT int 0 ***** BB49 STMT00126 (IL 0x258... ???) N006 ( 8, 7) [000711] -A-XG---R--- * ASG ref N005 ( 3, 2) [000710] D------N---- +--* LCL_VAR ref V52 tmp38 d:1 N004 ( 4, 4) [000709] ---XG------- \--* IND ref N003 ( 2, 2) [001095] -------N---- \--* ADD byref N001 ( 1, 1) [000165] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001094] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] ***** BB49 STMT00133 (IL 0x258... ???) N004 ( 5, 4) [000760] -A-X----R--- * ASG int N003 ( 1, 1) [000759] D------N---- +--* LCL_VAR int V53 tmp39 d:1 N002 ( 5, 4) [000714] ---X-------- \--* ARR_LENGTH int N001 ( 3, 2) [000713] ------------ \--* LCL_VAR ref V52 tmp38 u:1 ***** BB49 STMT00134 (IL 0x258... ???) N006 ( 8, 7) [000762] -A-XG---R--- * ASG long N005 ( 3, 2) [000761] D------N---- +--* LCL_VAR long V54 tmp40 d:1 N004 ( 4, 4) [000716] ---XG------- \--* IND long N003 ( 2, 2) [001097] -------N---- \--* ADD byref N001 ( 1, 1) [000715] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001096] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] ***** BB49 STMT00136 (IL 0x258... ???) N005 ( 10, 9) [000773] -A------R--- * ASG bool N004 ( 3, 2) [000772] D------N---- +--* LCL_VAR int V56 tmp42 d:1 N003 ( 6, 6) [000730] N--------U-- \--* LE int N001 ( 1, 1) [000728] ------------ +--* LCL_VAR int V53 tmp39 u:1 N002 ( 1, 4) [000729] ------------ \--* CNS_INT int 0x7FFFFFFF ***** BB49 STMT00139 (IL 0x258... ???) N004 ( 8, 15) [000783] -A--G---R--- * ASG ref N003 ( 3, 2) [000782] D------N---- +--* LCL_VAR ref V57 tmp43 d:1 N002 ( 4, 12) [000767] #---G------- \--* IND ref N001 ( 2, 10) [000766] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB49 STMT00140 (IL 0x258... ???) N004 ( 8, 15) [000785] -A--G---R--- * ASG ref N003 ( 3, 2) [000784] D------N---- +--* LCL_VAR ref V58 tmp44 d:1 N002 ( 4, 12) [000769] #---G------- \--* IND ref N001 ( 2, 10) [000768] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB49 STMT00137 (IL 0x258... ???) N004 ( 7, 6) [000778] ------------ * JTRUE void N003 ( 5, 4) [000777] J------N---- \--* NE int N001 ( 3, 2) [000775] ------------ +--* LCL_VAR int V56 tmp42 u:1 (last use) N002 ( 1, 1) [000776] ------------ \--* CNS_INT int 0 ------------ BB50 [258..259), preds={BB49} succs={BB51} ***** BB50 STMT00138 (IL 0x258... ???) N005 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 3, 2) [000779] ------------ arg0 in rcx +--* LCL_VAR ref V57 tmp43 u:1 (last use) N004 ( 3, 2) [000780] ------------ arg1 in rdx \--* LCL_VAR ref V58 tmp44 u:1 (last use) ------------ BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00131 (IL 0x258... ???) N016 ( 26, 25) [000750] -A------R--- * ASG int N015 ( 3, 2) [000749] D------N---- +--* LCL_VAR int V55 tmp41 d:1 N014 ( 22, 22) [000748] ------------ \--* CAST int <- uint <- long N013 ( 21, 20) [000747] ------------ \--* RSZ long N011 ( 19, 18) [000745] ------------ +--* MUL long N008 ( 13, 12) [000742] ------------ | +--* ADD long N006 ( 11, 10) [000739] ------------ | | +--* RSZ long N004 ( 9, 8) [000737] ------------ | | | +--* MUL long N001 ( 3, 2) [000735] ------------ | | | | +--* LCL_VAR long V54 tmp40 u:1 (last use) N003 ( 2, 3) [000736] ---------U-- | | | | \--* CAST long <- ulong <- uint N002 ( 1, 1) [000166] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 N005 ( 1, 1) [000738] ------------ | | | \--* CNS_INT int 32 N007 ( 1, 1) [000741] ------------ | | \--* CNS_INT long 1 N010 ( 2, 3) [000744] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000743] ------------ | \--* LCL_VAR int V53 tmp39 u:1 N012 ( 1, 1) [000746] ------------ \--* CNS_INT int 32 ***** BB51 STMT00142 (IL 0x258... ???) N007 ( 33, 11) [000796] -A-X----R--- * ASG bool N006 ( 3, 2) [000795] D------N---- +--* LCL_VAR int V59 tmp45 d:1 N005 ( 29, 8) [000755] ---X-------- \--* EQ int N003 ( 22, 5) [000754] ---X-------- +--* UMOD int N001 ( 1, 1) [000752] ------------ | +--* LCL_VAR int V06 loc2 u:1 N002 ( 1, 1) [000753] ------------ | \--* LCL_VAR int V53 tmp39 u:1 (last use) N004 ( 3, 2) [000751] ------------ \--* LCL_VAR int V55 tmp41 u:1 ***** BB51 STMT00145 (IL 0x258... ???) N004 ( 8, 15) [000806] -A--G---R--- * ASG ref N003 ( 3, 2) [000805] D------N---- +--* LCL_VAR ref V60 tmp46 d:1 N002 ( 4, 12) [000790] #---G------- \--* IND ref N001 ( 2, 10) [000789] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB51 STMT00146 (IL 0x258... ???) N004 ( 8, 15) [000808] -A--G---R--- * ASG ref N003 ( 3, 2) [000807] D------N---- +--* LCL_VAR ref V61 tmp47 d:1 N002 ( 4, 12) [000792] #---G------- \--* IND ref N001 ( 2, 10) [000791] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB51 STMT00143 (IL 0x258... ???) N004 ( 7, 6) [000801] ------------ * JTRUE void N003 ( 5, 4) [000800] J------N---- \--* NE int N001 ( 3, 2) [000798] ------------ +--* LCL_VAR int V59 tmp45 u:1 (last use) N002 ( 1, 1) [000799] ------------ \--* CNS_INT int 0 ------------ BB52 [258..259), preds={BB51} succs={BB53} ***** BB52 STMT00144 (IL 0x258... ???) N005 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 3, 2) [000802] ------------ arg0 in rcx +--* LCL_VAR ref V60 tmp46 u:1 (last use) N004 ( 3, 2) [000803] ------------ arg1 in rdx \--* LCL_VAR ref V61 tmp47 u:1 (last use) ------------ BB53 [258..259), preds={BB51,BB52} succs={BB54} ***** BB53 STMT00128 (IL 0x258... ???) N017 ( 35, 33) [000722] -A-XG---R--- * ASG byref N016 ( 3, 2) [000721] D------N---- +--* LCL_VAR byref V51 tmp37 d:1 N015 ( 31, 30) [001112] ---XG------- \--* COMMA byref N004 ( 12, 13) [001105] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 3, 2) [000758] ------------ | +--* LCL_VAR int V55 tmp41 u:1 N003 ( 5, 4) [001104] ---X-------- | \--* ARR_LENGTH int N002 ( 3, 2) [000712] ------------ | \--* LCL_VAR ref V52 tmp38 u:1 N014 ( 19, 17) [001113] ----G------- \--* ADDR byref N013 ( 10, 9) [000719] a---G--N---- \--* IND int N012 ( 9, 8) [001111] -------N---- \--* ADD byref N005 ( 3, 2) [001102] ------------ +--* LCL_VAR ref V52 tmp38 u:1 (last use) N011 ( 6, 6) [001110] -------N---- \--* ADD long N009 ( 5, 5) [001108] -------N---- +--* LSH long N007 ( 4, 4) [001106] ------------ | +--* CAST long <- int N006 ( 3, 2) [001103] i----------- | | \--* LCL_VAR int V55 tmp41 u:1 (last use) N008 ( 1, 1) [001107] -------N---- | \--* CNS_INT long 2 N010 ( 1, 1) [001109] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB53 STMT00034 (IL ???... ???) N003 ( 7, 5) [000170] -A------R--- * ASG byref N002 ( 3, 2) [000169] D------N---- +--* LCL_VAR byref V08 loc4 d:4 N001 ( 3, 2) [000723] ------------ \--* LCL_VAR byref V51 tmp37 u:1 (last use) ------------ BB54 [261..276), preds={BB48,BB53} succs={BB55} ***** BB54 STMT00170 (IL ???... ???) N005 ( 0, 0) [001193] -A------R--- * ASG byref N004 ( 0, 0) [001191] D------N---- +--* LCL_VAR byref V08 loc4 d:3 N003 ( 0, 0) [001192] ------------ \--* PHI byref N001 ( 0, 0) [001224] ------------ pred BB53 +--* PHI_ARG byref V08 loc4 u:4 N002 ( 0, 0) [001220] ------------ pred BB48 \--* PHI_ARG byref V08 loc4 u:1 ***** BB54 STMT00018 (IL 0x261...0x263) N003 ( 7, 5) [000083] -A------R--- * ASG int N002 ( 3, 2) [000082] D------N---- +--* LCL_VAR int V10 loc6 d:2 N001 ( 3, 2) [000081] ------------ \--* LCL_VAR int V13 loc9 u:1 ***** BB54 STMT00019 (IL 0x265...0x26A) N008 ( 10, 9) [000089] -A-XG---R--- * ASG int N007 ( 4, 4) [000088] D--XG--N---- +--* IND int N006 ( 2, 2) [001115] -------N---- | \--* ADD byref N004 ( 1, 1) [000084] ------------ | +--* LCL_VAR ref V00 this u:1 N005 ( 1, 1) [001114] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] N003 ( 5, 4) [000087] ------------ \--* ADD int N001 ( 3, 2) [000085] ------------ +--* LCL_VAR int V13 loc9 u:1 (last use) N002 ( 1, 1) [000086] ------------ \--* CNS_INT int 1 ***** BB54 STMT00020 (IL 0x26F...0x275) N006 ( 4, 4) [000093] -A-XG---R--- * ASG ref N005 ( 1, 1) [000092] D------N---- +--* LCL_VAR ref V04 loc0 d:3 N004 ( 4, 4) [000091] ---XG------- \--* IND ref N003 ( 2, 2) [001117] -------N---- \--* ADD byref N001 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001116] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] ------------ BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} ***** BB55 STMT00171 (IL ???... ???) N005 ( 0, 0) [001196] -A------R--- * ASG byref N004 ( 0, 0) [001194] D------N---- +--* LCL_VAR byref V08 loc4 d:2 N003 ( 0, 0) [001195] ------------ \--* PHI byref N001 ( 0, 0) [001225] ------------ pred BB47 +--* PHI_ARG byref V08 loc4 u:1 N002 ( 0, 0) [001221] ------------ pred BB54 \--* PHI_ARG byref V08 loc4 u:3 ***** BB55 STMT00169 (IL ???... ???) N005 ( 0, 0) [001190] -A------R--- * ASG ref N004 ( 0, 0) [001188] D------N---- +--* LCL_VAR ref V04 loc0 d:2 N003 ( 0, 0) [001189] ------------ \--* PHI ref N001 ( 0, 0) [001226] ------------ pred BB47 +--* PHI_ARG ref V04 loc0 u:1 N002 ( 0, 0) [001222] ------------ pred BB54 \--* PHI_ARG ref V04 loc0 u:3 ***** BB55 STMT00168 (IL ???... ???) N005 ( 0, 0) [001187] -A------R--- * ASG int N004 ( 0, 0) [001185] D------N---- +--* LCL_VAR int V10 loc6 d:1 N003 ( 0, 0) [001186] ------------ \--* PHI int N001 ( 0, 0) [001227] ------------ pred BB47 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [001223] ------------ pred BB54 \--* PHI_ARG int V10 loc6 u:2 ***** BB55 STMT00021 (IL 0x276...0x27E) N019 ( 39, 38) [000099] -A-XG---R--- * ASG byref N018 ( 3, 2) [000098] D------N---- +--* LCL_VAR byref V11 loc7 d:1 N017 ( 35, 35) [001128] ---XG------- \--* COMMA byref N004 ( 10, 12) [001121] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 3, 2) [000095] ------------ | +--* LCL_VAR int V10 loc6 u:1 N003 ( 3, 3) [001120] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000094] ------------ | \--* LCL_VAR ref V04 loc0 u:2 N016 ( 25, 23) [001131] ----G------- \--* ADDR byref N015 ( 13, 12) [000096] a---G--N---- \--* IND struct N014 ( 12, 11) [001127] -------N---- \--* ADD byref N005 ( 1, 1) [001118] ------------ +--* LCL_VAR ref V04 loc0 u:2 N013 ( 11, 10) [001126] -------N---- \--* ADD long N011 ( 10, 9) [001124] -------N---- +--* LSH long N009 ( 9, 8) [001130] ------------ | +--* MUL long N007 ( 4, 4) [001122] ------------ | | +--* CAST long <- int N006 ( 3, 2) [001119] i----------- | | | \--* LCL_VAR int V10 loc6 u:1 N008 ( 1, 1) [001129] ------------ | | \--* CNS_INT long 3 N010 ( 1, 1) [001123] -------N---- | \--* CNS_INT long 3 N012 ( 1, 1) [001125] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB55 STMT00022 (IL 0x280...0x283) N006 ( 8, 7) [000103] -A-XG------- * ASG int N004 ( 6, 5) [000102] *--XG--N---- +--* IND int N003 ( 4, 3) [001133] -------N---- | \--* ADD byref N001 ( 3, 2) [000100] ------------ | +--* LCL_VAR byref V11 loc7 u:1 N002 ( 1, 1) [001132] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] N005 ( 1, 1) [000101] ------------ \--* LCL_VAR int V06 loc2 u:1 (last use) ***** BB55 STMT00023 (IL 0x288...0x28F) N009 ( 15, 12) [000110] -A-XG---R--- * ASG int N008 ( 6, 5) [000109] *--XG--N---- +--* IND int N007 ( 4, 3) [001135] -------N---- | \--* ADD byref N005 ( 3, 2) [000104] ------------ | +--* LCL_VAR byref V11 loc7 u:1 N006 ( 1, 1) [001134] ------------ | \--* CNS_INT long 20 field offset Fseq[next] N004 ( 8, 6) [000108] ---XG------- \--* ADD int N002 ( 6, 4) [000106] *--XG------- +--* IND int N001 ( 3, 2) [000105] ------------ | \--* LCL_VAR byref V08 loc4 u:2 N003 ( 1, 1) [000107] ------------ \--* CNS_INT int -1 ***** BB55 STMT00024 (IL 0x294...0x297) N004 ( 8, 6) [000114] -A-XG------- * ASG ref N002 ( 6, 4) [000113] *--XG--N---- +--* IND ref N001 ( 3, 2) [000111] ------------ | \--* LCL_VAR byref V11 loc7 u:1 Zero Fseq[key] N003 ( 1, 1) [000112] ------------ \--* LCL_VAR ref V01 arg1 u:1 (last use) ***** BB55 STMT00025 (IL 0x29C...0x29F) N006 ( 8, 7) [000118] -A-XG------- * ASG ref N004 ( 6, 5) [000117] *--XG--N---- +--* IND ref N003 ( 4, 3) [001137] -------N---- | \--* ADD byref N001 ( 3, 2) [000115] ------------ | +--* LCL_VAR byref V11 loc7 u:1 (last use) N002 ( 1, 1) [001136] ------------ | \--* CNS_INT long 8 field offset Fseq[value] N005 ( 1, 1) [000116] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) ***** BB55 STMT00026 (IL 0x2A4...0x2AA) N006 ( 12, 9) [000124] -A-XG---R--- * ASG int N005 ( 6, 4) [000123] *--X---N---- +--* IND int N004 ( 3, 2) [000119] ------------ | \--* LCL_VAR byref V08 loc4 u:2 (last use) N003 ( 5, 4) [000122] ------------ \--* ADD int N001 ( 3, 2) [000120] ------------ +--* LCL_VAR int V10 loc6 u:1 (last use) N002 ( 1, 1) [000121] ------------ \--* CNS_INT int 1 ***** BB55 STMT00027 (IL 0x2AB...0x2B4) N011 ( 11, 11) [000131] -A-XG---R--- * ASG int N010 ( 4, 4) [000130] D--XG--N---- +--* IND int N009 ( 2, 2) [001139] -------N---- | \--* ADD byref N007 ( 1, 1) [000125] ------------ | +--* LCL_VAR ref V00 this u:1 N008 ( 1, 1) [001138] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] N006 ( 6, 6) [000129] ---XG------- \--* ADD int N004 ( 4, 4) [000127] ---XG------- +--* IND int N003 ( 2, 2) [001141] -------N---- | \--* ADD byref N001 ( 1, 1) [000126] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001140] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] N005 ( 1, 1) [000128] ------------ \--* CNS_INT int 1 ***** BB55 STMT00028 (IL 0x2CA...0x2CD) N004 ( 5, 5) [000148] ------------ * JTRUE void N003 ( 3, 3) [000147] N------N-U-- \--* LE int N001 ( 1, 1) [000145] ------------ +--* LCL_VAR int V07 loc3 u:2 (last use) N002 ( 1, 1) [000146] ------------ \--* CNS_INT int 100 ------------ BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} ***** BB56 STMT00030 (IL 0x2CF...0x2D5) N008 ( 21, 22) [000156] --C-G------- * JTRUE void N007 ( 19, 20) [000155] J-C-G--N---- \--* EQ int N005 ( 17, 18) [000153] --C-G------- +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS N003 ( 1, 1) [000151] ------------ arg1 in rdx | +--* LCL_VAR ref V05 loc1 u:1 (last use) N004 ( 2, 10) [000152] H------N---- arg0 in rcx | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 1, 1) [000154] ------------ \--* CNS_INT ref null ------------ BB57 [2D7..2E3), preds={BB56} succs={BB58} ***** BB57 STMT00031 (IL 0x2D7...0x2DC) N008 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize N005 ( 3, 3) [000159] ---X-------- arg1 in rdx +--* ARR_LENGTH int N004 ( 1, 1) [000158] ------------ | \--* LCL_VAR ref V04 loc0 u:2 (last use) N006 ( 1, 1) [000157] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 N007 ( 1, 1) [000160] ------------ arg2 in r8 \--* CNS_INT int 1 ------------ BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} ***** BB58 STMT00147 (IL ???... ???) N002 ( 2, 2) [000810] ------------ * RETURN int N001 ( 1, 1) [000482] ------------ \--* CNS_INT int 1 ------------ BB59 [008..00E) (throw), preds={BB01} succs={} ***** BB59 STMT00086 (IL 0x008...0x009) N003 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException N002 ( 1, 1) [000532] ------------ arg0 in rcx \--* CNS_INT int 4 ------------ BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} ***** BB60 STMT00073 (IL 0x14F...0x150) N004 ( 7, 5) [000444] -A-X----R--- * ASG long N003 ( 3, 2) [000443] D------N---- +--* LCL_VAR long V26 tmp12 d:1 N002 ( 3, 2) [000442] #--X-------- \--* IND long N001 ( 1, 1) [000441] !----------- \--* LCL_VAR ref V00 this u:1 ***** BB60 STMT00155 (IL ???... ???) N011 ( 16, 14) [001158] ------------ * JTRUE void N010 ( 14, 12) [000460] J------N---- \--* EQ int N008 ( 12, 10) [000456] n----------- +--* IND long N007 ( 10, 8) [000452] -------N---- | \--* ADD long N005 ( 9, 7) [000450] #----------- | +--* IND long N004 ( 6, 5) [000449] #----------- | | \--* IND long N003 ( 4, 3) [000448] -------N---- | | \--* ADD long N001 ( 3, 2) [000446] ------------ | | +--* LCL_VAR long V26 tmp12 u:1 N002 ( 1, 1) [000447] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000451] ------------ | \--* CNS_INT long 56 N009 ( 1, 1) [000459] ------------ \--* CNS_INT long 0 ------------ BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} ***** BB61 STMT00156 (IL ???... ???) N010 ( 16, 13) [001160] -A------R--- * ASG long N009 ( 3, 2) [001159] D------N---- +--* LCL_VAR long V28 tmp14 d:3 N008 ( 12, 10) [000461] n-----?----- \--* IND long N007 ( 10, 8) [000462] ------?N---- \--* ADD long N005 ( 9, 7) [000463] #-----?----- +--* IND long N004 ( 6, 5) [000464] #-----?----- | \--* IND long N003 ( 4, 3) [000465] ------?N---- | \--* ADD long N001 ( 3, 2) [000466] ------?----- | +--* LCL_VAR long V26 tmp12 u:1 (last use) N002 ( 1, 1) [000467] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000468] ------?----- \--* CNS_INT long 56 ------------ BB62 [???..???), preds={BB60} succs={BB63} ***** BB62 STMT00157 (IL ???... ???) N007 ( 23, 22) [001162] -AC-G---R--- * ASG long N006 ( 3, 2) [001161] D------N---- +--* LCL_VAR long V28 tmp14 d:2 N005 ( 19, 19) [000458] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 3, 2) [000445] ------?----- arg0 in rcx +--* LCL_VAR long V26 tmp12 u:1 (last use) N004 ( 2, 10) [000457] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB63 [???..157) (throw), preds={BB61,BB62} succs={} ***** BB63 STMT00167 (IL ???... ???) N005 ( 0, 0) [001184] -A------R--- * ASG long N004 ( 0, 0) [001182] D------N---- +--* LCL_VAR long V28 tmp14 d:1 N003 ( 0, 0) [001183] ------------ \--* PHI long N001 ( 0, 0) [001241] ------------ pred BB61 +--* PHI_ARG long V28 tmp14 u:3 N002 ( 0, 0) [001240] ------------ pred BB62 \--* PHI_ARG long V28 tmp14 u:2 ***** BB63 STMT00076 (IL ???... ???) N005 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException N003 ( 3, 2) [000473] ------------ arg0 in rcx +--* LCL_VAR long V28 tmp14 u:1 (last use) N004 ( 1, 1) [000455] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) ------------ BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} ***** BB64 STMT00053 (IL 0x1BC...0x1BD) N004 ( 7, 5) [000299] -A-X----R--- * ASG long N003 ( 3, 2) [000298] D------N---- +--* LCL_VAR long V21 tmp7 d:1 N002 ( 3, 2) [000297] #--X-------- \--* IND long N001 ( 1, 1) [000296] !----------- \--* LCL_VAR ref V00 this u:1 ***** BB64 STMT00161 (IL ???... ???) N011 ( 16, 14) [001168] ------------ * JTRUE void N010 ( 14, 12) [000315] J------N---- \--* EQ int N008 ( 12, 10) [000311] n----------- +--* IND long N007 ( 10, 8) [000307] -------N---- | \--* ADD long N005 ( 9, 7) [000305] #----------- | +--* IND long N004 ( 6, 5) [000304] #----------- | | \--* IND long N003 ( 4, 3) [000303] -------N---- | | \--* ADD long N001 ( 3, 2) [000301] ------------ | | +--* LCL_VAR long V21 tmp7 u:1 N002 ( 1, 1) [000302] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000306] ------------ | \--* CNS_INT long 56 N009 ( 1, 1) [000314] ------------ \--* CNS_INT long 0 ------------ BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} ***** BB65 STMT00162 (IL ???... ???) N010 ( 16, 13) [001170] -A------R--- * ASG long N009 ( 3, 2) [001169] D------N---- +--* LCL_VAR long V23 tmp9 d:3 N008 ( 12, 10) [000316] n-----?----- \--* IND long N007 ( 10, 8) [000317] ------?N---- \--* ADD long N005 ( 9, 7) [000318] #-----?----- +--* IND long N004 ( 6, 5) [000319] #-----?----- | \--* IND long N003 ( 4, 3) [000320] ------?N---- | \--* ADD long N001 ( 3, 2) [000321] ------?----- | +--* LCL_VAR long V21 tmp7 u:1 (last use) N002 ( 1, 1) [000322] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000323] ------?----- \--* CNS_INT long 56 ------------ BB66 [???..???), preds={BB64} succs={BB67} ***** BB66 STMT00163 (IL ???... ???) N007 ( 23, 22) [001172] -AC-G---R--- * ASG long N006 ( 3, 2) [001171] D------N---- +--* LCL_VAR long V23 tmp9 d:2 N005 ( 19, 19) [000313] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 3, 2) [000300] ------?----- arg0 in rcx +--* LCL_VAR long V21 tmp7 u:1 (last use) N004 ( 2, 10) [000312] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} ***** BB67 STMT00173 (IL ???... ???) N005 ( 0, 0) [001202] -A------R--- * ASG long N004 ( 0, 0) [001200] D------N---- +--* LCL_VAR long V23 tmp9 d:1 N003 ( 0, 0) [001201] ------------ \--* PHI long N001 ( 0, 0) [001232] ------------ pred BB65 +--* PHI_ARG long V23 tmp9 u:3 N002 ( 0, 0) [001231] ------------ pred BB66 \--* PHI_ARG long V23 tmp9 u:2 ***** BB67 STMT00056 (IL ???... ???) N005 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException N003 ( 3, 2) [000328] ------------ arg0 in rcx +--* LCL_VAR long V23 tmp9 u:1 (last use) N004 ( 1, 1) [000310] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) ------------ BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} ***** BB68 STMT00043 (IL 0x1DD...0x1E2) N001 ( 14, 5) [000233] --CXG------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported ------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Build SSA representation Trees after Build SSA representation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target align BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal Loop1 gcsafe BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe BB36 [0108] 1 BB34 1 [???..???) i gcsafe BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen BB54 [0044] 2 BB48,BB53 0.50 [261..276) i BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} ***** BB01 STMT00000 (IL 0x000...0x006) N004 ( 5, 5) [000003] ------------ * JTRUE void N003 ( 3, 3) [000002] J------N---- \--* EQ int N001 ( 1, 1) [000000] ------------ +--* LCL_VAR ref V01 arg1 u:1 N002 ( 1, 1) [000001] ------------ \--* CNS_INT ref null ------------ BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00001 (IL 0x00E...0x014) N007 ( 8, 8) [000008] ---XG------- * JTRUE void N006 ( 6, 6) [000007] J--XG--N---- \--* NE int N004 ( 4, 4) [000005] ---XG------- +--* IND ref N003 ( 2, 2) [000814] -------N---- | \--* ADD byref N001 ( 1, 1) [000004] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000813] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] N005 ( 1, 1) [000006] ------------ \--* CNS_INT ref null ------------ BB03 [016..01E), preds={BB02} succs={BB04} ***** BB03 STMT00085 (IL ???... ???) N005 ( 16, 10) [000528] --CXG------- * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize N003 ( 1, 1) [000526] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 N004 ( 1, 1) [000527] ------------ arg1 in rdx \--* CNS_INT int 0 ------------ BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ***** BB04 STMT00088 (IL 0x01E... ???) N008 ( 9, 6) [000544] -A-XG---R--- * ASG bool N007 ( 1, 1) [000543] D------N---- +--* LCL_VAR int V33 tmp19 d:1 N006 ( 9, 6) [000012] N--XG------- \--* NE int N004 ( 4, 4) [000010] ---XG------- +--* IND ref N003 ( 2, 2) [000818] -------N---- | \--* ADD byref N001 ( 1, 1) [000009] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000817] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] N005 ( 1, 1) [000011] ------------ \--* CNS_INT ref null ***** BB04 STMT00091 (IL 0x01E... ???) N004 ( 4, 12) [000554] -A--G---R--- * ASG ref N003 ( 1, 1) [000553] D------N---- +--* LCL_VAR ref V34 tmp20 d:1 N002 ( 4, 12) [000538] #---G------- \--* IND ref N001 ( 2, 10) [000537] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB04 STMT00092 (IL 0x01E... ???) N004 ( 4, 12) [000556] -A--G---R--- * ASG ref N003 ( 1, 1) [000555] D------N---- +--* LCL_VAR ref V35 tmp21 d:1 N002 ( 4, 12) [000540] #---G------- \--* IND ref N001 ( 2, 10) [000539] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB04 STMT00089 (IL 0x01E... ???) N004 ( 5, 5) [000549] ------------ * JTRUE void N003 ( 3, 3) [000548] J------N---- \--* NE int N001 ( 1, 1) [000546] ------------ +--* LCL_VAR int V33 tmp19 u:1 (last use) N002 ( 1, 1) [000547] ------------ \--* CNS_INT int 0 ------------ BB05 [01E..01F), preds={BB04} succs={BB06} ***** BB05 STMT00090 (IL 0x01E... ???) N005 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 1, 1) [000550] ------------ arg0 in rcx +--* LCL_VAR ref V34 tmp20 u:1 (last use) N004 ( 1, 1) [000551] ------------ arg1 in rdx \--* LCL_VAR ref V35 tmp21 u:1 (last use) ------------ BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} ***** BB06 STMT00003 (IL 0x02C... ???) N006 ( 4, 4) [000018] -A-XG---R--- * ASG ref N005 ( 1, 1) [000017] D------N---- +--* LCL_VAR ref V04 loc0 d:1 N004 ( 4, 4) [000016] ---XG------- \--* IND ref N003 ( 2, 2) [000822] -------N---- \--* ADD byref N001 ( 1, 1) [000015] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000821] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] ***** BB06 STMT00094 (IL 0x033... ???) N005 ( 6, 3) [000566] -A------R--- * ASG bool N004 ( 1, 1) [000565] D------N---- +--* LCL_VAR int V36 tmp22 d:1 N003 ( 6, 3) [000021] N----------- \--* NE int N001 ( 1, 1) [000019] ------------ +--* LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000020] ------------ \--* CNS_INT ref null ***** BB06 STMT00097 (IL 0x033... ???) N004 ( 4, 12) [000576] -A--G---R--- * ASG ref N003 ( 1, 1) [000575] D------N---- +--* LCL_VAR ref V37 tmp23 d:1 N002 ( 4, 12) [000562] #---G------- \--* IND ref N001 ( 2, 10) [000561] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB06 STMT00095 (IL 0x033... ???) N004 ( 5, 5) [000571] ------------ * JTRUE void N003 ( 3, 3) [000570] J------N---- \--* NE int N001 ( 1, 1) [000568] ------------ +--* LCL_VAR int V36 tmp22 u:1 (last use) N002 ( 1, 1) [000569] ------------ \--* CNS_INT int 0 ------------ BB07 [033..034), preds={BB06} succs={BB08} ***** BB07 STMT00096 (IL 0x033... ???) N006 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail N004 ( 4, 12) [000824] #---G------- arg0 in rcx +--* IND ref N003 ( 2, 10) [000823] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" N005 ( 1, 1) [000573] ------------ arg1 in rdx \--* LCL_VAR ref V37 tmp23 u:1 (last use) ------------ BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} ***** BB08 STMT00005 (IL 0x041... ???) N006 ( 4, 4) [000028] -A-XG---R--- * ASG ref N005 ( 1, 1) [000027] D------N---- +--* LCL_VAR ref V05 loc1 d:1 N004 ( 4, 4) [000026] ---XG------- \--* IND ref N003 ( 2, 2) [000828] -------N---- \--* ADD byref N001 ( 1, 1) [000025] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000827] ------------ \--* CNS_INT long 24 field offset Fseq[_comparer] ***** BB08 STMT00006 (IL 0x048...0x049) N004 ( 5, 5) [000032] ------------ * JTRUE void N003 ( 3, 3) [000031] J------N---- \--* EQ int N001 ( 1, 1) [000029] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000030] ------------ \--* CNS_INT ref null ------------ BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} ***** BB09 STMT00079 (IL 0x04B...0x052) N004 ( 3, 3) [000489] -A-X----R--- * ASG long N003 ( 1, 1) [000488] D------N---- +--* LCL_VAR long V29 tmp15 d:1 N002 ( 3, 2) [000487] #--X-------- \--* IND long N001 ( 1, 1) [000486] !----------- \--* LCL_VAR ref V00 this u:1 ***** BB09 STMT00149 (IL ???... ???) N011 ( 14, 13) [001148] ------------ * JTRUE void N010 ( 12, 11) [000505] J------N---- \--* EQ int N008 ( 10, 9) [000501] n----------- +--* IND long N007 ( 8, 7) [000497] -------N---- | \--* ADD long N005 ( 7, 6) [000495] #----------- | +--* IND long N004 ( 4, 4) [000494] #----------- | | \--* IND long N003 ( 2, 2) [000493] -------N---- | | \--* ADD long N001 ( 1, 1) [000491] ------------ | | +--* LCL_VAR long V29 tmp15 u:1 N002 ( 1, 1) [000492] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000496] ------------ | \--* CNS_INT long 64 N009 ( 1, 1) [000504] ------------ \--* CNS_INT long 0 ------------ BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} ***** BB10 STMT00150 (IL ???... ???) N010 ( 10, 9) [001150] -A------R--- * ASG long N009 ( 1, 1) [001149] D------N---- +--* LCL_VAR long V31 tmp17 d:3 N008 ( 10, 9) [000506] n-----?----- \--* IND long N007 ( 8, 7) [000507] ------?N---- \--* ADD long N005 ( 7, 6) [000508] #-----?----- +--* IND long N004 ( 4, 4) [000509] #-----?----- | \--* IND long N003 ( 2, 2) [000510] ------?N---- | \--* ADD long N001 ( 1, 1) [000511] ------?----- | +--* LCL_VAR long V29 tmp15 u:1 (last use) N002 ( 1, 1) [000512] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000513] ------?----- \--* CNS_INT long 64 ------------ BB11 [???..???), preds={BB09} succs={BB12} ***** BB11 STMT00151 (IL ???... ???) N007 ( 17, 18) [001152] -AC-G---R--- * ASG long N006 ( 1, 1) [001151] D------N---- +--* LCL_VAR long V31 tmp17 d:2 N005 ( 17, 18) [000503] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 1, 1) [000490] ------?----- arg0 in rcx +--* LCL_VAR long V29 tmp15 u:1 (last use) N004 ( 2, 10) [000502] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} ***** BB12 STMT00178 (IL ???... ???) N005 ( 0, 0) [001217] -A------R--- * ASG long N004 ( 0, 0) [001215] D------N---- +--* LCL_VAR long V31 tmp17 d:1 N003 ( 0, 0) [001216] ------------ \--* PHI long N001 ( 0, 0) [001247] ------------ pred BB10 +--* PHI_ARG long V31 tmp17 u:3 N002 ( 0, 0) [001246] ------------ pred BB11 \--* PHI_ARG long V31 tmp17 u:2 ***** BB12 STMT00083 (IL ???... ???) N010 ( 31, 15) [000524] -ACXG---R--- * ASG int N009 ( 3, 2) [000523] D------N---- +--* LCL_VAR int V15 tmp1 d:3 N008 ( 27, 12) [000522] --CXG------- \--* CALL ind stub int N007 ( 1, 1) [000521] ------------ calli tgt \--* LCL_VAR long V31 tmp17 u:1 (last use) N004 ( 1, 1) [000484] ------------ this in rcx +--* LCL_VAR ref V05 loc1 u:1 N005 ( 1, 1) [000831] ------------ arg1 in r11 +--* LCL_VAR long V31 tmp17 u:1 r11 REG r11 N006 ( 1, 1) [000500] ------------ arg2 in rdx \--* LCL_VAR ref V01 arg1 u:1 ------------ BB13 [054..061), preds={BB08} succs={BB14} ***** BB13 STMT00007 (IL 0x054...0x05C) N013 ( 34, 21) [000038] -ACXG---R--- * ASG int N012 ( 3, 2) [000037] D------N---- +--* LCL_VAR int V15 tmp1 d:2 N011 ( 30, 18) [000035] --CXG------- \--* CALLV vt-ind int System.Object.GetHashCode N010 ( 9, 8) [000843] n--X-------- control expr \--* IND long N009 ( 7, 6) [000842] ---X---N---- \--* ADD long N007 ( 6, 5) [000840] #--X-------- +--* IND long N006 ( 4, 3) [000839] ---X---N---- | \--* ADD long N004 ( 3, 2) [000837] #--X-------- | +--* IND long N003 ( 1, 1) [000836] ------------ | | \--* LCL_VAR ref V01 arg1 u:1 N005 ( 1, 1) [000838] ------------ | \--* CNS_INT int 72 N008 ( 1, 1) [000841] ------------ \--* CNS_INT int 24 N002 ( 1, 1) [000033] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 ------------ BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ***** BB14 STMT00177 (IL ???... ???) N005 ( 0, 0) [001214] -A------R--- * ASG int N004 ( 0, 0) [001212] D------N---- +--* LCL_VAR int V15 tmp1 d:1 N003 ( 0, 0) [001213] ------------ \--* PHI int N001 ( 0, 0) [001245] ------------ pred BB12 +--* PHI_ARG int V15 tmp1 u:3 N002 ( 0, 0) [001244] ------------ pred BB13 \--* PHI_ARG int V15 tmp1 u:2 ***** BB14 STMT00008 (IL ???...0x061) N003 ( 3, 3) [000042] -A------R--- * ASG int N002 ( 1, 1) [000041] D------N---- +--* LCL_VAR int V06 loc2 d:1 N001 ( 3, 2) [000040] ------------ \--* LCL_VAR int V15 tmp1 u:1 (last use) ***** BB14 STMT00009 (IL 0x062...0x063) N003 ( 1, 3) [000045] -A------R--- * ASG int N002 ( 1, 1) [000044] D------N---- +--* LCL_VAR int V07 loc3 d:1 N001 ( 1, 1) [000043] ------------ \--* CNS_INT int 0 ***** BB14 STMT00098 (IL 0x064... ???) N006 ( 4, 4) [000580] -A-XG---R--- * ASG ref N005 ( 1, 1) [000579] D------N---- +--* LCL_VAR ref V39 tmp25 d:1 N004 ( 4, 4) [000578] ---XG------- \--* IND ref N003 ( 2, 2) [000845] -------N---- \--* ADD byref N001 ( 1, 1) [000046] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000844] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] ***** BB14 STMT00105 (IL 0x064... ???) N004 ( 3, 3) [000629] -A-X----R--- * ASG int N003 ( 1, 1) [000628] D------N---- +--* LCL_VAR int V40 tmp26 d:1 N002 ( 3, 3) [000583] ---X-------- \--* ARR_LENGTH int N001 ( 1, 1) [000582] ------------ \--* LCL_VAR ref V39 tmp25 u:1 ***** BB14 STMT00106 (IL 0x064... ???) N006 ( 4, 4) [000631] -A-XG---R--- * ASG long N005 ( 1, 1) [000630] D------N---- +--* LCL_VAR long V41 tmp27 d:1 N004 ( 4, 4) [000585] ---XG------- \--* IND long N003 ( 2, 2) [000847] -------N---- \--* ADD byref N001 ( 1, 1) [000584] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000846] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] ***** BB14 STMT00108 (IL 0x064... ???) N005 ( 6, 6) [000642] -A------R--- * ASG bool N004 ( 1, 1) [000641] D------N---- +--* LCL_VAR int V43 tmp29 d:1 N003 ( 6, 6) [000599] N--------U-- \--* LE int N001 ( 1, 1) [000597] ------------ +--* LCL_VAR int V40 tmp26 u:1 N002 ( 1, 4) [000598] ------------ \--* CNS_INT int 0x7FFFFFFF ***** BB14 STMT00111 (IL 0x064... ???) N004 ( 4, 12) [000652] -A--G---R--- * ASG ref N003 ( 1, 1) [000651] D------N---- +--* LCL_VAR ref V44 tmp30 d:1 N002 ( 4, 12) [000636] #---G------- \--* IND ref N001 ( 2, 10) [000635] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB14 STMT00112 (IL 0x064... ???) N004 ( 4, 12) [000654] -A--G---R--- * ASG ref N003 ( 1, 1) [000653] D------N---- +--* LCL_VAR ref V45 tmp31 d:1 N002 ( 4, 12) [000638] #---G------- \--* IND ref N001 ( 2, 10) [000637] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB14 STMT00109 (IL 0x064... ???) N004 ( 5, 5) [000647] ------------ * JTRUE void N003 ( 3, 3) [000646] J------N---- \--* NE int N001 ( 1, 1) [000644] ------------ +--* LCL_VAR int V43 tmp29 u:1 (last use) N002 ( 1, 1) [000645] ------------ \--* CNS_INT int 0 ------------ BB15 [064..065), preds={BB14} succs={BB16} ***** BB15 STMT00110 (IL 0x064... ???) N005 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 1, 1) [000648] ------------ arg0 in rcx +--* LCL_VAR ref V44 tmp30 u:1 (last use) N004 ( 1, 1) [000649] ------------ arg1 in rdx \--* LCL_VAR ref V45 tmp31 u:1 (last use) ------------ BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} ***** BB16 STMT00103 (IL 0x064... ???) N016 ( 20, 21) [000619] -A------R--- * ASG int N015 ( 1, 1) [000618] D------N---- +--* LCL_VAR int V42 tmp28 d:1 N014 ( 20, 21) [000617] ------------ \--* CAST int <- uint <- long N013 ( 19, 19) [000616] ------------ \--* RSZ long N011 ( 17, 17) [000614] ------------ +--* MUL long N008 ( 11, 11) [000611] ------------ | +--* ADD long N006 ( 9, 9) [000608] ------------ | | +--* RSZ long N004 ( 7, 7) [000606] ------------ | | | +--* MUL long N001 ( 1, 1) [000604] ------------ | | | | +--* LCL_VAR long V41 tmp27 u:1 (last use) N003 ( 2, 3) [000605] ---------U-- | | | | \--* CAST long <- ulong <- uint N002 ( 1, 1) [000047] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 N005 ( 1, 1) [000607] ------------ | | | \--* CNS_INT int 32 N007 ( 1, 1) [000610] ------------ | | \--* CNS_INT long 1 N010 ( 2, 3) [000613] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000612] ------------ | \--* LCL_VAR int V40 tmp26 u:1 N012 ( 1, 1) [000615] ------------ \--* CNS_INT int 32 ***** BB16 STMT00114 (IL 0x064... ???) N007 ( 27, 7) [000665] -A-X----R--- * ASG bool N006 ( 1, 1) [000664] D------N---- +--* LCL_VAR int V46 tmp32 d:1 N005 ( 27, 7) [000624] ---X-------- \--* EQ int N003 ( 22, 5) [000623] ---X-------- +--* UMOD int N001 ( 1, 1) [000621] ------------ | +--* LCL_VAR int V06 loc2 u:1 N002 ( 1, 1) [000622] ------------ | \--* LCL_VAR int V40 tmp26 u:1 (last use) N004 ( 1, 1) [000620] ------------ \--* LCL_VAR int V42 tmp28 u:1 ***** BB16 STMT00117 (IL 0x064... ???) N004 ( 4, 12) [000675] -A--G---R--- * ASG ref N003 ( 1, 1) [000674] D------N---- +--* LCL_VAR ref V47 tmp33 d:1 N002 ( 4, 12) [000659] #---G------- \--* IND ref N001 ( 2, 10) [000658] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB16 STMT00118 (IL 0x064... ???) N004 ( 4, 12) [000677] -A--G---R--- * ASG ref N003 ( 1, 1) [000676] D------N---- +--* LCL_VAR ref V48 tmp34 d:1 N002 ( 4, 12) [000661] #---G------- \--* IND ref N001 ( 2, 10) [000660] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB16 STMT00115 (IL 0x064... ???) N004 ( 5, 5) [000670] ------------ * JTRUE void N003 ( 3, 3) [000669] J------N---- \--* NE int N001 ( 1, 1) [000667] ------------ +--* LCL_VAR int V46 tmp32 u:1 (last use) N002 ( 1, 1) [000668] ------------ \--* CNS_INT int 0 ------------ BB17 [064..065), preds={BB16} succs={BB18} ***** BB17 STMT00116 (IL 0x064... ???) N005 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 1, 1) [000671] ------------ arg0 in rcx +--* LCL_VAR ref V47 tmp33 u:1 (last use) N004 ( 1, 1) [000672] ------------ arg1 in rdx \--* LCL_VAR ref V48 tmp34 u:1 (last use) ------------ BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} ***** BB18 STMT00100 (IL 0x064... ???) N017 ( 19, 24) [000591] -A-XG---R--- * ASG byref N016 ( 1, 1) [000590] D------N---- +--* LCL_VAR byref V38 tmp24 d:1 N015 ( 19, 24) [000862] ---XG------- \--* COMMA byref N004 ( 8, 11) [000855] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000627] ------------ | +--* LCL_VAR int V42 tmp28 u:1 N003 ( 3, 3) [000854] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000581] ------------ | \--* LCL_VAR ref V39 tmp25 u:1 N014 ( 11, 13) [000863] ----G------- \--* ADDR byref N013 ( 6, 7) [000588] a---G--N---- \--* IND int N012 ( 5, 6) [000861] -------N---- \--* ADD byref N005 ( 1, 1) [000852] ------------ +--* LCL_VAR ref V39 tmp25 u:1 (last use) N011 ( 4, 5) [000860] -------N---- \--* ADD long N009 ( 3, 4) [000858] -------N---- +--* LSH long N007 ( 2, 3) [000856] ------------ | +--* CAST long <- int N006 ( 1, 1) [000853] i----------- | | \--* LCL_VAR int V42 tmp28 u:1 (last use) N008 ( 1, 1) [000857] -------N---- | \--* CNS_INT long 2 N010 ( 1, 1) [000859] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB18 STMT00011 (IL ???... ???) N003 ( 5, 4) [000051] -A------R--- * ASG byref N002 ( 3, 2) [000050] D------N---- +--* LCL_VAR byref V08 loc4 d:1 N001 ( 1, 1) [000592] ------------ \--* LCL_VAR byref V38 tmp24 u:1 ***** BB18 STMT00012 (IL 0x06D...0x072) N006 ( 5, 4) [000057] -A-XG---R--- * ASG int N005 ( 1, 1) [000056] D------N---- +--* LCL_VAR int V09 loc5 d:1 N004 ( 5, 4) [000055] ---XG------- \--* ADD int N002 ( 3, 2) [000053] *--XG------- +--* IND int N001 ( 1, 1) [000052] ------------ | \--* LCL_VAR byref V38 tmp24 u:1 (last use) N003 ( 1, 1) [000054] ------------ \--* CNS_INT int -1 ***** BB18 STMT00013 (IL 0x074...0x075) N004 ( 5, 5) [000061] ------------ * JTRUE void N003 ( 3, 3) [000060] J------N---- \--* NE int N001 ( 1, 1) [000058] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000059] ------------ \--* CNS_INT ref null ------------ BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} ***** BB19 STMT00059 (IL 0x0FF...0x104) N004 ( 3, 3) [000356] -A-X----R--- * ASG long N003 ( 1, 1) [000355] D------N---- +--* LCL_VAR long V24 tmp10 d:1 N002 ( 3, 2) [000354] #--X-------- \--* IND long N001 ( 1, 1) [000353] !----------- \--* LCL_VAR ref V00 this u:1 ***** BB19 STMT00152 (IL ???... ???) N011 ( 14, 13) [001153] ------------ * JTRUE void N010 ( 12, 11) [000369] J------N---- \--* EQ int N008 ( 10, 9) [000365] n----------- +--* IND long N007 ( 8, 7) [000364] -------N---- | \--* ADD long N005 ( 7, 6) [000362] #----------- | +--* IND long N004 ( 4, 4) [000361] #----------- | | \--* IND long N003 ( 2, 2) [000360] -------N---- | | \--* ADD long N001 ( 1, 1) [000358] ------------ | | +--* LCL_VAR long V24 tmp10 u:1 N002 ( 1, 1) [000359] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000363] ------------ | \--* CNS_INT long 32 N009 ( 1, 1) [000368] ------------ \--* CNS_INT long 0 ------------ BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} ***** BB20 STMT00153 (IL ???... ???) N010 ( 14, 12) [001155] -A------R--- * ASG long N009 ( 3, 2) [001154] D------N---- +--* LCL_VAR long V25 tmp11 d:3 N008 ( 10, 9) [000370] n-----?----- \--* IND long N007 ( 8, 7) [000371] ------?N---- \--* ADD long N005 ( 7, 6) [000372] #-----?----- +--* IND long N004 ( 4, 4) [000373] #-----?----- | \--* IND long N003 ( 2, 2) [000374] ------?N---- | \--* ADD long N001 ( 1, 1) [000375] ------?----- | +--* LCL_VAR long V24 tmp10 u:1 (last use) N002 ( 1, 1) [000376] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000377] ------?----- \--* CNS_INT long 32 ------------ BB21 [???..???), preds={BB19} succs={BB22} ***** BB21 STMT00154 (IL ???... ???) N007 ( 21, 21) [001157] -AC-G---R--- * ASG long N006 ( 3, 2) [001156] D------N---- +--* LCL_VAR long V25 tmp11 d:2 N005 ( 17, 18) [000367] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 1, 1) [000357] ------?----- arg0 in rcx +--* LCL_VAR long V24 tmp10 u:1 (last use) N004 ( 2, 10) [000366] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB22 [???..106), preds={BB20,BB21} succs={BB23} ***** BB22 STMT00172 (IL ???... ???) N005 ( 0, 0) [001199] -A------R--- * ASG long N004 ( 0, 0) [001197] D------N---- +--* LCL_VAR long V25 tmp11 d:1 N003 ( 0, 0) [001198] ------------ \--* PHI long N001 ( 0, 0) [001243] ------------ pred BB20 +--* PHI_ARG long V25 tmp11 u:3 N002 ( 0, 0) [001242] ------------ pred BB21 \--* PHI_ARG long V25 tmp11 u:2 ***** BB22 STMT00062 (IL ???... ???) N005 ( 17, 8) [000386] -ACXG---R--- * ASG ref N004 ( 1, 1) [000385] D------N---- +--* LCL_VAR ref V12 loc8 d:1 N003 ( 17, 8) [000352] --CXG------- \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default N002 ( 3, 2) [000382] ------------ arg0 in rcx \--* LCL_VAR long V25 tmp11 u:1 (last use) ------------ BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} ***** BB23 STMT00165 (IL ???... ???) N005 ( 0, 0) [001178] -A------R--- * ASG int N004 ( 0, 0) [001176] D------N---- +--* LCL_VAR int V07 loc3 d:5 N003 ( 0, 0) [001177] ------------ \--* PHI int N001 ( 0, 0) [001238] ------------ pred BB27 +--* PHI_ARG int V07 loc3 u:6 N002 ( 0, 0) [001235] ------------ pred BB22 \--* PHI_ARG int V07 loc3 u:1 ***** BB23 STMT00164 (IL ???... ???) N005 ( 0, 0) [001175] -A------R--- * ASG int N004 ( 0, 0) [001173] D------N---- +--* LCL_VAR int V09 loc5 d:4 N003 ( 0, 0) [001174] ------------ \--* PHI int N001 ( 0, 0) [001239] ------------ pred BB27 +--* PHI_ARG int V09 loc5 u:5 N002 ( 0, 0) [001236] ------------ pred BB22 \--* PHI_ARG int V09 loc5 u:1 ***** BB23 STMT00063 (IL 0x106...0x10B) N005 ( 7, 7) [000391] ---X-------- * JTRUE void N004 ( 5, 5) [000390] N--X---N-U-- \--* LE int N002 ( 3, 3) [000389] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000388] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000387] ------------ \--* LCL_VAR int V09 loc5 u:4 ------------ BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} ***** BB24 STMT00064 (IL 0x110...0x11E) N023 ( 36, 39) [000399] ---XG------- * JTRUE void N022 ( 34, 37) [000398] N--XG--N-U-- \--* NE int N020 ( 32, 35) [000396] *--XG------- +--* IND int N019 ( 30, 33) [000868] ---XG--N---- | \--* ADD byref N017 ( 29, 32) [000879] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000872] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000393] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 N003 ( 3, 3) [000871] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000392] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000882] ----G------- | | \--* ADDR byref N015 ( 11, 11) [000394] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000878] -------N---- | | \--* ADD byref N005 ( 1, 1) [000869] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000877] -------N---- | | \--* ADD long N011 ( 8, 8) [000875] -------N---- | | +--* LSH long N009 ( 7, 7) [000881] ------------ | | | +--* MUL long N007 ( 2, 3) [000873] ------------ | | | | +--* CAST long <- int N006 ( 1, 1) [000870] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 N008 ( 1, 1) [000880] ------------ | | | | \--* CNS_INT long 3 N010 ( 1, 1) [000874] -------N---- | | | \--* CNS_INT long 3 N012 ( 1, 1) [000876] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000867] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] N021 ( 1, 1) [000397] ------------ \--* LCL_VAR int V06 loc2 u:1 ------------ BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} ***** BB25 STMT00069 (IL 0x120...0x135) N035 ( 67, 59) [000428] --CXG------- * JTRUE void N034 ( 65, 57) [000427] J-CXG--N---- \--* NE int N032 ( 63, 55) [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals N031 ( 9, 8) [000908] n--X-------- control expr | \--* IND long N030 ( 7, 6) [000907] ---X---N---- | \--* ADD long N028 ( 6, 5) [000905] #--X-------- | +--* IND long N027 ( 4, 3) [000904] ---X---N---- | | \--* ADD long N025 ( 3, 2) [000902] #--X-------- | | +--* IND long N024 ( 1, 1) [000901] ------------ | | | \--* LCL_VAR ref V12 loc8 u:1 N026 ( 1, 1) [000903] ------------ | | \--* CNS_INT int 72 N029 ( 1, 1) [000906] ------------ | \--* CNS_INT int 32 N021 ( 32, 34) [000893] ---XG------- arg1 in rdx | +--* COMMA ref N007 ( 8, 11) [000886] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N004 ( 1, 1) [000420] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 N006 ( 3, 3) [000885] ---X-------- | | | \--* ARR_LENGTH int N005 ( 1, 1) [000419] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N020 ( 24, 23) [000897] *---G------- | | \--* IND ref N019 ( 21, 21) [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] N018 ( 11, 11) [000421] a---G--N---- | | \--* IND struct N017 ( 10, 10) [000892] -------N---- | | \--* ADD byref N008 ( 1, 1) [000883] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N016 ( 9, 9) [000891] -------N---- | | \--* ADD long N014 ( 8, 8) [000889] -------N---- | | +--* LSH long N012 ( 7, 7) [000895] ------------ | | | +--* MUL long N010 ( 2, 3) [000887] ------------ | | | | +--* CAST long <- int N009 ( 1, 1) [000884] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 N011 ( 1, 1) [000894] ------------ | | | | \--* CNS_INT long 3 N013 ( 1, 1) [000888] -------N---- | | | \--* CNS_INT long 3 N015 ( 1, 1) [000890] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N022 ( 1, 1) [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 u:1 N023 ( 1, 1) [000424] ------------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 u:1 N033 ( 1, 1) [000426] ------------ \--* CNS_INT int 0 ------------ BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} ***** BB26 STMT00065 (IL 0x157...0x164) N022 ( 32, 35) [000406] -A-XG---R--- * ASG int N021 ( 1, 1) [000405] D------N---- +--* LCL_VAR int V09 loc5 d:5 N020 ( 32, 35) [000404] *--XG------- \--* IND int N019 ( 30, 33) [000932] ---XG--N---- \--* ADD byref N017 ( 29, 32) [000943] ---XG------- +--* COMMA byref N004 ( 8, 11) [000936] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000401] ------------ | | +--* LCL_VAR int V09 loc5 u:4 N003 ( 3, 3) [000935] ---X-------- | | \--* ARR_LENGTH int N002 ( 1, 1) [000400] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000946] ----G------- | \--* ADDR byref N015 ( 11, 11) [000402] a---G--N---- | \--* IND struct N014 ( 10, 10) [000942] -------N---- | \--* ADD byref N005 ( 1, 1) [000933] ------------ | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000941] -------N---- | \--* ADD long N011 ( 8, 8) [000939] -------N---- | +--* LSH long N009 ( 7, 7) [000945] ------------ | | +--* MUL long N007 ( 2, 3) [000937] ------------ | | | +--* CAST long <- int N006 ( 1, 1) [000934] i----------- | | | | \--* LCL_VAR int V09 loc5 u:4 (last use) N008 ( 1, 1) [000944] ------------ | | | \--* CNS_INT long 3 N010 ( 1, 1) [000938] -------N---- | | \--* CNS_INT long 3 N012 ( 1, 1) [000940] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000931] ------------ \--* CNS_INT long 20 field offset Fseq[next] ***** BB26 STMT00066 (IL 0x166...0x169) N005 ( 3, 3) [000411] -A------R--- * ASG int N004 ( 1, 1) [000410] D------N---- +--* LCL_VAR int V07 loc3 d:6 N003 ( 3, 3) [000409] ------------ \--* ADD int N001 ( 1, 1) [000407] ------------ +--* LCL_VAR int V07 loc3 u:5 (last use) N002 ( 1, 1) [000408] ------------ \--* CNS_INT int 1 ***** BB26 STMT00067 (IL 0x16A...0x16E) N005 ( 7, 7) [000416] ---X-------- * JTRUE void N004 ( 5, 5) [000415] N--X---N-U-- \--* LT int N002 ( 3, 3) [000414] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000413] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000412] ------------ \--* LCL_VAR int V07 loc3 u:6 ------------ BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} ------------ BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} ***** BB28 STMT00070 (IL 0x137...0x139) N005 ( 7, 8) [000432] ------------ * JTRUE void N004 ( 5, 6) [000431] N------N-U-- \--* NE int N002 ( 3, 4) [000909] ------------ +--* CAST int <- ubyte <- int N001 ( 2, 2) [000429] ------------ | \--* LCL_VAR int V03 arg3 u:1 N003 ( 1, 1) [000430] ------------ \--* CNS_INT int 1 ------------ BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} ***** BB29 STMT00077 (IL 0x13B...0x144) N022 ( 34, 37) [000481] -A-XG------- * ASG ref N020 ( 32, 35) [000480] *--XG--N---- +--* IND ref N019 ( 30, 33) [000911] ---XG--N---- | \--* ADD byref N017 ( 29, 32) [000922] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000915] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000476] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 N003 ( 3, 3) [000914] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000475] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000925] ----G------- | | \--* ADDR byref N015 ( 11, 11) [000477] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000921] -------N---- | | \--* ADD byref N005 ( 1, 1) [000912] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 (last use) N013 ( 9, 9) [000920] -------N---- | | \--* ADD long N011 ( 8, 8) [000918] -------N---- | | +--* LSH long N009 ( 7, 7) [000924] ------------ | | | +--* MUL long N007 ( 2, 3) [000916] ------------ | | | | +--* CAST long <- int N006 ( 1, 1) [000913] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 (last use) N008 ( 1, 1) [000923] ------------ | | | | \--* CNS_INT long 3 N010 ( 1, 1) [000917] -------N---- | | | \--* CNS_INT long 3 N012 ( 1, 1) [000919] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000910] ------------ | \--* CNS_INT long 8 field offset Fseq[value] N021 ( 1, 1) [000479] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) ------------ BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} ***** BB30 STMT00071 (IL 0x14B...0x14D) N005 ( 7, 8) [000436] ------------ * JTRUE void N004 ( 5, 6) [000435] N------N-U-- \--* EQ int N002 ( 3, 4) [000926] ------------ +--* CAST int <- ubyte <- int N001 ( 2, 2) [000433] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) N003 ( 1, 1) [000434] ------------ \--* CNS_INT int 2 ------------ BB31 [???..???) (return), preds={BB30,BB41} succs={} ***** BB31 STMT00148 (IL ???... ???) N002 ( 2, 2) [000811] ------------ * RETURN int N001 ( 1, 1) [000437] ------------ \--* CNS_INT int 0 ------------ BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} ***** BB32 STMT00175 (IL ???... ???) N005 ( 0, 0) [001208] -A------R--- * ASG int N004 ( 0, 0) [001206] D------N---- +--* LCL_VAR int V07 loc3 d:3 N003 ( 0, 0) [001207] ------------ \--* PHI int N001 ( 0, 0) [001229] ------------ pred BB43 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [001218] ------------ pred BB18 \--* PHI_ARG int V07 loc3 u:1 ***** BB32 STMT00174 (IL ???... ???) N005 ( 0, 0) [001205] -A------R--- * ASG int N004 ( 0, 0) [001203] D------N---- +--* LCL_VAR int V09 loc5 d:2 N003 ( 0, 0) [001204] ------------ \--* PHI int N001 ( 0, 0) [001230] ------------ pred BB43 +--* PHI_ARG int V09 loc5 u:3 N002 ( 0, 0) [001219] ------------ pred BB18 \--* PHI_ARG int V09 loc5 u:1 ***** BB32 STMT00014 (IL 0x177...0x17C) N005 ( 7, 7) [000066] ---X-------- * JTRUE void N004 ( 5, 5) [000065] N--X---N-U-- \--* LE int N002 ( 3, 3) [000064] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000063] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000062] ------------ \--* LCL_VAR int V09 loc5 u:2 ------------ BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} ***** BB33 STMT00039 (IL 0x17E...0x18C) N023 ( 36, 39) [000215] ---XG------- * JTRUE void N022 ( 34, 37) [000214] N--XG--N-U-- \--* NE int N020 ( 32, 35) [000212] *--XG------- +--* IND int N019 ( 30, 33) [000948] ---XG--N---- | \--* ADD byref N017 ( 29, 32) [000959] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000952] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000209] ------------ | | | +--* LCL_VAR int V09 loc5 u:2 N003 ( 3, 3) [000951] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000208] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000962] ----G------- | | \--* ADDR byref N015 ( 11, 11) [000210] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000958] -------N---- | | \--* ADD byref N005 ( 1, 1) [000949] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000957] -------N---- | | \--* ADD long N011 ( 8, 8) [000955] -------N---- | | +--* LSH long N009 ( 7, 7) [000961] ------------ | | | +--* MUL long N007 ( 2, 3) [000953] ------------ | | | | +--* CAST long <- int N006 ( 1, 1) [000950] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:2 N008 ( 1, 1) [000960] ------------ | | | | \--* CNS_INT long 3 N010 ( 1, 1) [000954] -------N---- | | | \--* CNS_INT long 3 N012 ( 1, 1) [000956] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000947] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] N021 ( 1, 1) [000213] ------------ \--* LCL_VAR int V06 loc2 u:1 ------------ BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} ***** BB34 STMT00045 (IL 0x18E...0x1A2) N020 ( 32, 34) [000246] -A-XG---R--- * ASG ref N019 ( 1, 1) [000245] D------N---- +--* LCL_VAR ref V17 tmp3 d:1 N018 ( 32, 34) [000973] ---XG------- \--* COMMA ref N004 ( 8, 11) [000966] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000236] ------------ | +--* LCL_VAR int V09 loc5 u:2 N003 ( 3, 3) [000965] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000235] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N017 ( 24, 23) [000977] *---G------- \--* IND ref N016 ( 21, 21) [000976] ----G------- \--* ADDR byref Zero Fseq[key] N015 ( 11, 11) [000237] a---G--N---- \--* IND struct N014 ( 10, 10) [000972] -------N---- \--* ADD byref N005 ( 1, 1) [000963] ------------ +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000971] -------N---- \--* ADD long N011 ( 8, 8) [000969] -------N---- +--* LSH long N009 ( 7, 7) [000975] ------------ | +--* MUL long N007 ( 2, 3) [000967] ------------ | | +--* CAST long <- int N006 ( 1, 1) [000964] i----------- | | | \--* LCL_VAR int V09 loc5 u:2 N008 ( 1, 1) [000974] ------------ | | \--* CNS_INT long 3 N010 ( 1, 1) [000968] -------N---- | \--* CNS_INT long 3 N012 ( 1, 1) [000970] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB34 STMT00044 (IL 0x18E... ???) N004 ( 3, 3) [000244] -A-X----R--- * ASG long N003 ( 1, 1) [000243] D------N---- +--* LCL_VAR long V16 tmp2 d:1 N002 ( 3, 2) [000242] #--X-------- \--* IND long N001 ( 1, 1) [000241] !----------- \--* LCL_VAR ref V00 this u:1 ***** BB34 STMT00158 (IL ???... ???) N011 ( 14, 13) [001163] ------------ * JTRUE void N010 ( 12, 11) [000263] J------N---- \--* EQ int N008 ( 10, 9) [000259] n----------- +--* IND long N007 ( 8, 7) [000255] -------N---- | \--* ADD long N005 ( 7, 6) [000253] #----------- | +--* IND long N004 ( 4, 4) [000252] #----------- | | \--* IND long N003 ( 2, 2) [000251] -------N---- | | \--* ADD long N001 ( 1, 1) [000249] ------------ | | +--* LCL_VAR long V16 tmp2 u:1 N002 ( 1, 1) [000250] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000254] ------------ | \--* CNS_INT long 48 N009 ( 1, 1) [000262] ------------ \--* CNS_INT long 0 ------------ BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} ***** BB35 STMT00159 (IL ???... ???) N010 ( 10, 9) [001165] -A------R--- * ASG long N009 ( 1, 1) [001164] D------N---- +--* LCL_VAR long V19 tmp5 d:3 N008 ( 10, 9) [000264] n-----?----- \--* IND long N007 ( 8, 7) [000265] ------?N---- \--* ADD long N005 ( 7, 6) [000266] #-----?----- +--* IND long N004 ( 4, 4) [000267] #-----?----- | \--* IND long N003 ( 2, 2) [000268] ------?N---- | \--* ADD long N001 ( 1, 1) [000269] ------?----- | +--* LCL_VAR long V16 tmp2 u:1 (last use) N002 ( 1, 1) [000270] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000271] ------?----- \--* CNS_INT long 48 ------------ BB36 [???..???), preds={BB34} succs={BB37} ***** BB36 STMT00160 (IL ???... ???) N007 ( 17, 18) [001167] -AC-G---R--- * ASG long N006 ( 1, 1) [001166] D------N---- +--* LCL_VAR long V19 tmp5 d:2 N005 ( 17, 18) [000261] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 1, 1) [000248] ------?----- arg0 in rcx +--* LCL_VAR long V16 tmp2 u:1 (last use) N004 ( 2, 10) [000260] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} ***** BB37 STMT00176 (IL ???... ???) N005 ( 0, 0) [001211] -A------R--- * ASG long N004 ( 0, 0) [001209] D------N---- +--* LCL_VAR long V19 tmp5 d:1 N003 ( 0, 0) [001210] ------------ \--* PHI long N001 ( 0, 0) [001234] ------------ pred BB35 +--* PHI_ARG long V19 tmp5 u:3 N002 ( 0, 0) [001233] ------------ pred BB36 \--* PHI_ARG long V19 tmp5 u:2 ***** BB37 STMT00049 (IL ???... ???) N013 ( 32, 18) [000283] --CXG------- * JTRUE void N012 ( 30, 16) [000282] J-CXG--N---- \--* EQ int N010 ( 28, 14) [000280] --CXG------- +--* CALL ind stub int N009 ( 1, 1) [000279] ------------ calli tgt | \--* LCL_VAR long V19 tmp5 u:1 (last use) N005 ( 1, 1) [000234] ------------ this in rcx | +--* LCL_VAR ref V05 loc1 u:1 N006 ( 1, 1) [000980] ------------ arg1 in r11 | +--* LCL_VAR long V19 tmp5 u:1 r11 REG r11 N007 ( 1, 1) [000247] ------------ arg2 in rdx | +--* LCL_VAR ref V17 tmp3 u:1 (last use) N008 ( 1, 1) [000258] ------------ arg3 in r8 | \--* LCL_VAR ref V01 arg1 u:1 N011 ( 1, 1) [000281] ------------ \--* CNS_INT int 0 ------------ BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} ***** BB38 STMT00050 (IL 0x1A4...0x1A6) N005 ( 7, 8) [000287] ------------ * JTRUE void N004 ( 5, 6) [000286] N------N-U-- \--* NE int N002 ( 3, 4) [000985] ------------ +--* CAST int <- ubyte <- int N001 ( 2, 2) [000284] ------------ | \--* LCL_VAR int V03 arg3 u:1 N003 ( 1, 1) [000285] ------------ \--* CNS_INT int 1 ------------ BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} ***** BB39 STMT00057 (IL 0x1A8...0x1B1) N022 ( 34, 37) [000336] -A-XG------- * ASG ref N020 ( 32, 35) [000335] *--XG--N---- +--* IND ref N019 ( 30, 33) [000987] ---XG--N---- | \--* ADD byref N017 ( 29, 32) [000998] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000991] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000331] ------------ | | | +--* LCL_VAR int V09 loc5 u:2 N003 ( 3, 3) [000990] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000330] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [001001] ----G------- | | \--* ADDR byref N015 ( 11, 11) [000332] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000997] -------N---- | | \--* ADD byref N005 ( 1, 1) [000988] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 (last use) N013 ( 9, 9) [000996] -------N---- | | \--* ADD long N011 ( 8, 8) [000994] -------N---- | | +--* LSH long N009 ( 7, 7) [001000] ------------ | | | +--* MUL long N007 ( 2, 3) [000992] ------------ | | | | +--* CAST long <- int N006 ( 1, 1) [000989] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:2 (last use) N008 ( 1, 1) [000999] ------------ | | | | \--* CNS_INT long 3 N010 ( 1, 1) [000993] -------N---- | | | \--* CNS_INT long 3 N012 ( 1, 1) [000995] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000986] ------------ | \--* CNS_INT long 8 field offset Fseq[value] N021 ( 1, 1) [000334] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) ------------ BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} ***** BB40 STMT00051 (IL 0x1B8...0x1BA) N005 ( 7, 8) [000291] ------------ * JTRUE void N004 ( 5, 6) [000290] N------N-U-- \--* EQ int N002 ( 3, 4) [001002] ------------ +--* CAST int <- ubyte <- int N001 ( 2, 2) [000288] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) N003 ( 1, 1) [000289] ------------ \--* CNS_INT int 2 ------------ BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} ------------ BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} ***** BB42 STMT00040 (IL 0x1C4...0x1D1) N022 ( 32, 35) [000222] -A-XG---R--- * ASG int N021 ( 1, 1) [000221] D------N---- +--* LCL_VAR int V09 loc5 d:3 N020 ( 32, 35) [000220] *--XG------- \--* IND int N019 ( 30, 33) [001009] ---XG--N---- \--* ADD byref N017 ( 29, 32) [001020] ---XG------- +--* COMMA byref N004 ( 8, 11) [001013] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000217] ------------ | | +--* LCL_VAR int V09 loc5 u:2 N003 ( 3, 3) [001012] ---X-------- | | \--* ARR_LENGTH int N002 ( 1, 1) [000216] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [001023] ----G------- | \--* ADDR byref N015 ( 11, 11) [000218] a---G--N---- | \--* IND struct N014 ( 10, 10) [001019] -------N---- | \--* ADD byref N005 ( 1, 1) [001010] ------------ | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [001018] -------N---- | \--* ADD long N011 ( 8, 8) [001016] -------N---- | +--* LSH long N009 ( 7, 7) [001022] ------------ | | +--* MUL long N007 ( 2, 3) [001014] ------------ | | | +--* CAST long <- int N006 ( 1, 1) [001011] i----------- | | | | \--* LCL_VAR int V09 loc5 u:2 (last use) N008 ( 1, 1) [001021] ------------ | | | \--* CNS_INT long 3 N010 ( 1, 1) [001015] -------N---- | | \--* CNS_INT long 3 N012 ( 1, 1) [001017] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [001008] ------------ \--* CNS_INT long 20 field offset Fseq[next] ***** BB42 STMT00041 (IL 0x1D3...0x1D6) N005 ( 3, 3) [000227] -A------R--- * ASG int N004 ( 1, 1) [000226] D------N---- +--* LCL_VAR int V07 loc3 d:4 N003 ( 3, 3) [000225] ------------ \--* ADD int N001 ( 1, 1) [000223] ------------ +--* LCL_VAR int V07 loc3 u:3 (last use) N002 ( 1, 1) [000224] ------------ \--* CNS_INT int 1 ***** BB42 STMT00042 (IL 0x1D7...0x1DB) N005 ( 7, 7) [000232] ---X-------- * JTRUE void N004 ( 5, 5) [000231] N--X---N-U-- \--* LT int N002 ( 3, 3) [000230] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000229] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000228] ------------ \--* LCL_VAR int V07 loc3 u:4 ------------ BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} ------------ BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} ***** BB44 STMT00166 (IL ???... ???) N005 ( 0, 0) [001181] -A------R--- * ASG int N004 ( 0, 0) [001179] D------N---- +--* LCL_VAR int V07 loc3 d:2 N003 ( 0, 0) [001180] ------------ \--* PHI int N001 ( 0, 0) [001237] ------------ pred BB23 +--* PHI_ARG int V07 loc3 u:5 N002 ( 0, 0) [001228] ------------ pred BB32 \--* PHI_ARG int V07 loc3 u:3 ***** BB44 STMT00015 (IL 0x1E4...0x1EB) N007 ( 8, 8) [000071] ---XG------- * JTRUE void N006 ( 6, 6) [000070] J--XG--N---- \--* LE int N004 ( 4, 4) [000068] ---XG------- +--* IND int N003 ( 2, 2) [001025] -------N---- | \--* ADD byref N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001024] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] N005 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 ------------ BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} ***** BB45 STMT00035 (IL 0x1ED...0x1F3) N006 ( 8, 7) [000174] -A-XG---R--- * ASG int N005 ( 3, 2) [000173] D------N---- +--* LCL_VAR int V10 loc6 d:3 N004 ( 4, 4) [000172] ---XG------- \--* IND int N003 ( 2, 2) [001027] -------N---- \--* ADD byref N001 ( 1, 1) [000171] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001026] ------------ \--* CNS_INT long 60 field offset Fseq[_freeList] ***** BB45 STMT00120 (IL 0x1F5... ???) N034 ( 48, 47) [000688] -A-XG---R--- * ASG bool N033 ( 3, 2) [000687] D------N---- +--* LCL_VAR int V49 tmp35 d:1 N032 ( 44, 44) [000184] -A-XG------- \--* GE int N030 ( 39, 42) [000182] -A-XG------- +--* ADD int N028 ( 37, 40) [001050] -A-XG------- | +--* NEG int N027 ( 36, 39) [000181] *A-XG------- | | \--* IND int N026 ( 34, 37) [001029] -A-XG--N---- | | \--* ADD byref N024 ( 33, 36) [001044] -A-XG------- | | +--* COMMA byref N006 ( 4, 4) [001032] -A-XG---R--- | | | +--* ASG int N005 ( 1, 1) [001031] D------N---- | | | | +--* LCL_VAR int V62 tmp48 d:1 N004 ( 4, 4) [000178] ---XG------- | | | | \--* IND int N003 ( 2, 2) [001046] -------N---- | | | | \--* ADD byref N001 ( 1, 1) [000177] ------------ | | | | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001045] ------------ | | | | \--* CNS_INT long 60 field offset Fseq[_freeList] N023 ( 29, 32) [001043] ---XG------- | | | \--* COMMA byref N010 ( 8, 11) [001036] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [001033] ------------ | | | | +--* LCL_VAR int V62 tmp48 u:1 N009 ( 3, 3) [001035] ---X-------- | | | | \--* ARR_LENGTH int N008 ( 1, 1) [000176] ------------ | | | | \--* LCL_VAR ref V04 loc0 u:1 N022 ( 21, 21) [001049] ----G------- | | | \--* ADDR byref N021 ( 11, 11) [000179] a---G--N---- | | | \--* IND struct N020 ( 10, 10) [001042] -------N---- | | | \--* ADD byref N011 ( 1, 1) [001030] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N019 ( 9, 9) [001041] -------N---- | | | \--* ADD long N017 ( 8, 8) [001039] -------N---- | | | +--* LSH long N015 ( 7, 7) [001048] ------------ | | | | +--* MUL long N013 ( 2, 3) [001037] ------------ | | | | | +--* CAST long <- int N012 ( 1, 1) [001034] i----------- | | | | | | \--* LCL_VAR int V62 tmp48 u:1 (last use) N014 ( 1, 1) [001047] ------------ | | | | | \--* CNS_INT long 3 N016 ( 1, 1) [001038] -------N---- | | | | \--* CNS_INT long 3 N018 ( 1, 1) [001040] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] N025 ( 1, 1) [001028] ------------ | | \--* CNS_INT long 20 field offset Fseq[next] N029 ( 1, 1) [000175] ------------ | \--* CNS_INT int -3 N031 ( 1, 1) [000183] ------------ \--* CNS_INT int -1 ***** BB45 STMT00123 (IL 0x1F5... ???) N004 ( 8, 15) [000698] -A--G---R--- * ASG ref N003 ( 3, 2) [000697] D------N---- +--* LCL_VAR ref V50 tmp36 d:1 N002 ( 4, 12) [000684] #---G------- \--* IND ref N001 ( 2, 10) [000683] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB45 STMT00121 (IL 0x1F5... ???) N004 ( 7, 6) [000693] ------------ * JTRUE void N003 ( 5, 4) [000692] J------N---- \--* NE int N001 ( 3, 2) [000690] ------------ +--* LCL_VAR int V49 tmp35 u:1 (last use) N002 ( 1, 1) [000691] ------------ \--* CNS_INT int 0 ------------ BB46 [1F5..1F6), preds={BB45} succs={BB47} ***** BB46 STMT00122 (IL 0x1F5... ???) N006 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail N004 ( 4, 12) [001052] #---G------- arg0 in rcx +--* IND ref N003 ( 2, 10) [001051] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" N005 ( 3, 2) [000695] ------------ arg1 in rdx \--* LCL_VAR ref V50 tmp36 u:1 (last use) ------------ BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} ***** BB47 STMT00037 (IL 0x219... ???) N035 ( 44, 47) [000200] -A-XG------- * ASG int N004 ( 4, 4) [000199] D--XG--N---- +--* IND int N003 ( 2, 2) [001056] -------N---- | \--* ADD byref N001 ( 1, 1) [000190] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001055] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] N034 ( 39, 42) [000198] -A-XG------- \--* ADD int N032 ( 37, 40) [001079] -A-XG------- +--* NEG int N031 ( 36, 39) [000197] *A-XG------- | \--* IND int N030 ( 34, 37) [001058] -A-XG--N---- | \--* ADD byref N028 ( 33, 36) [001073] -A-XG------- | +--* COMMA byref N010 ( 4, 4) [001061] -A-XG---R--- | | +--* ASG int N009 ( 1, 1) [001060] D------N---- | | | +--* LCL_VAR int V63 tmp49 d:1 N008 ( 4, 4) [000194] ---XG------- | | | \--* IND int N007 ( 2, 2) [001075] -------N---- | | | \--* ADD byref N005 ( 1, 1) [000193] ------------ | | | +--* LCL_VAR ref V00 this u:1 N006 ( 1, 1) [001074] ------------ | | | \--* CNS_INT long 60 field offset Fseq[_freeList] N027 ( 29, 32) [001072] ---XG------- | | \--* COMMA byref N014 ( 8, 11) [001065] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N011 ( 1, 1) [001062] ------------ | | | +--* LCL_VAR int V63 tmp49 u:1 N013 ( 3, 3) [001064] ---X-------- | | | \--* ARR_LENGTH int N012 ( 1, 1) [000192] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N026 ( 21, 21) [001078] ----G------- | | \--* ADDR byref N025 ( 11, 11) [000195] a---G--N---- | | \--* IND struct N024 ( 10, 10) [001071] -------N---- | | \--* ADD byref N015 ( 1, 1) [001059] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N023 ( 9, 9) [001070] -------N---- | | \--* ADD long N021 ( 8, 8) [001068] -------N---- | | +--* LSH long N019 ( 7, 7) [001077] ------------ | | | +--* MUL long N017 ( 2, 3) [001066] ------------ | | | | +--* CAST long <- int N016 ( 1, 1) [001063] i----------- | | | | | \--* LCL_VAR int V63 tmp49 u:1 (last use) N018 ( 1, 1) [001076] ------------ | | | | \--* CNS_INT long 3 N020 ( 1, 1) [001067] -------N---- | | | \--* CNS_INT long 3 N022 ( 1, 1) [001069] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N029 ( 1, 1) [001057] ------------ | \--* CNS_INT long 20 field offset Fseq[next] N033 ( 1, 1) [000191] ------------ \--* CNS_INT int -3 ***** BB47 STMT00038 (IL 0x233...0x23C) N011 ( 11, 11) [000207] -A-XG---R--- * ASG int N010 ( 4, 4) [000206] D--XG--N---- +--* IND int N009 ( 2, 2) [001081] -------N---- | \--* ADD byref N007 ( 1, 1) [000201] ------------ | +--* LCL_VAR ref V00 this u:1 N008 ( 1, 1) [001080] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] N006 ( 6, 6) [000205] ---XG------- \--* ADD int N004 ( 4, 4) [000203] ---XG------- +--* IND int N003 ( 2, 2) [001083] -------N---- | \--* ADD byref N001 ( 1, 1) [000202] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001082] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] N005 ( 1, 1) [000204] ------------ \--* CNS_INT int -1 ------------ BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} ***** BB48 STMT00016 (IL 0x243...0x249) N006 ( 8, 7) [000075] -A-XG---R--- * ASG int N005 ( 3, 2) [000074] D------N---- +--* LCL_VAR int V13 loc9 d:1 N004 ( 4, 4) [000073] ---XG------- \--* IND int N003 ( 2, 2) [001085] -------N---- \--* ADD byref N001 ( 1, 1) [000072] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001084] ------------ \--* CNS_INT long 56 field offset Fseq[_count] ***** BB48 STMT00017 (IL 0x24B...0x250) N005 ( 9, 8) [000080] ---X-------- * JTRUE void N004 ( 7, 6) [000079] N--X---N-U-- \--* NE int N002 ( 3, 3) [000078] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000077] ------------ | \--* LCL_VAR ref V04 loc0 u:1 (last use) N003 ( 3, 2) [000076] ------------ \--* LCL_VAR int V13 loc9 u:1 ------------ BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00125 (IL 0x252... ???) N014 ( 44, 26) [000705] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize N009 ( 22, 13) [001090] -ACXG---R-L- arg1 SETUP +--* ASG int N008 ( 3, 2) [001089] D------N---- | +--* LCL_VAR int V64 tmp50 d:1 N007 ( 18, 10) [000702] --CXG------- | \--* CALL int System.Collections.HashHelpers.ExpandPrime N006 ( 4, 4) [000701] ---XG------- arg0 in rcx | \--* IND int N005 ( 2, 2) [001087] -------N---- | \--* ADD byref N003 ( 1, 1) [000700] ------------ | +--* LCL_VAR ref V00 this u:1 N004 ( 1, 1) [001086] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] N011 ( 3, 2) [001091] ------------ arg1 in rdx +--* LCL_VAR int V64 tmp50 u:1 (last use) N012 ( 1, 1) [000163] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 N013 ( 1, 1) [000704] ------------ arg2 in r8 \--* CNS_INT int 0 ***** BB49 STMT00126 (IL 0x258... ???) N006 ( 8, 7) [000711] -A-XG---R--- * ASG ref N005 ( 3, 2) [000710] D------N---- +--* LCL_VAR ref V52 tmp38 d:1 N004 ( 4, 4) [000709] ---XG------- \--* IND ref N003 ( 2, 2) [001095] -------N---- \--* ADD byref N001 ( 1, 1) [000165] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001094] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] ***** BB49 STMT00133 (IL 0x258... ???) N004 ( 5, 4) [000760] -A-X----R--- * ASG int N003 ( 1, 1) [000759] D------N---- +--* LCL_VAR int V53 tmp39 d:1 N002 ( 5, 4) [000714] ---X-------- \--* ARR_LENGTH int N001 ( 3, 2) [000713] ------------ \--* LCL_VAR ref V52 tmp38 u:1 ***** BB49 STMT00134 (IL 0x258... ???) N006 ( 8, 7) [000762] -A-XG---R--- * ASG long N005 ( 3, 2) [000761] D------N---- +--* LCL_VAR long V54 tmp40 d:1 N004 ( 4, 4) [000716] ---XG------- \--* IND long N003 ( 2, 2) [001097] -------N---- \--* ADD byref N001 ( 1, 1) [000715] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001096] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] ***** BB49 STMT00136 (IL 0x258... ???) N005 ( 10, 9) [000773] -A------R--- * ASG bool N004 ( 3, 2) [000772] D------N---- +--* LCL_VAR int V56 tmp42 d:1 N003 ( 6, 6) [000730] N--------U-- \--* LE int N001 ( 1, 1) [000728] ------------ +--* LCL_VAR int V53 tmp39 u:1 N002 ( 1, 4) [000729] ------------ \--* CNS_INT int 0x7FFFFFFF ***** BB49 STMT00139 (IL 0x258... ???) N004 ( 8, 15) [000783] -A--G---R--- * ASG ref N003 ( 3, 2) [000782] D------N---- +--* LCL_VAR ref V57 tmp43 d:1 N002 ( 4, 12) [000767] #---G------- \--* IND ref N001 ( 2, 10) [000766] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB49 STMT00140 (IL 0x258... ???) N004 ( 8, 15) [000785] -A--G---R--- * ASG ref N003 ( 3, 2) [000784] D------N---- +--* LCL_VAR ref V58 tmp44 d:1 N002 ( 4, 12) [000769] #---G------- \--* IND ref N001 ( 2, 10) [000768] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB49 STMT00137 (IL 0x258... ???) N004 ( 7, 6) [000778] ------------ * JTRUE void N003 ( 5, 4) [000777] J------N---- \--* NE int N001 ( 3, 2) [000775] ------------ +--* LCL_VAR int V56 tmp42 u:1 (last use) N002 ( 1, 1) [000776] ------------ \--* CNS_INT int 0 ------------ BB50 [258..259), preds={BB49} succs={BB51} ***** BB50 STMT00138 (IL 0x258... ???) N005 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 3, 2) [000779] ------------ arg0 in rcx +--* LCL_VAR ref V57 tmp43 u:1 (last use) N004 ( 3, 2) [000780] ------------ arg1 in rdx \--* LCL_VAR ref V58 tmp44 u:1 (last use) ------------ BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00131 (IL 0x258... ???) N016 ( 26, 25) [000750] -A------R--- * ASG int N015 ( 3, 2) [000749] D------N---- +--* LCL_VAR int V55 tmp41 d:1 N014 ( 22, 22) [000748] ------------ \--* CAST int <- uint <- long N013 ( 21, 20) [000747] ------------ \--* RSZ long N011 ( 19, 18) [000745] ------------ +--* MUL long N008 ( 13, 12) [000742] ------------ | +--* ADD long N006 ( 11, 10) [000739] ------------ | | +--* RSZ long N004 ( 9, 8) [000737] ------------ | | | +--* MUL long N001 ( 3, 2) [000735] ------------ | | | | +--* LCL_VAR long V54 tmp40 u:1 (last use) N003 ( 2, 3) [000736] ---------U-- | | | | \--* CAST long <- ulong <- uint N002 ( 1, 1) [000166] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 N005 ( 1, 1) [000738] ------------ | | | \--* CNS_INT int 32 N007 ( 1, 1) [000741] ------------ | | \--* CNS_INT long 1 N010 ( 2, 3) [000744] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000743] ------------ | \--* LCL_VAR int V53 tmp39 u:1 N012 ( 1, 1) [000746] ------------ \--* CNS_INT int 32 ***** BB51 STMT00142 (IL 0x258... ???) N007 ( 33, 11) [000796] -A-X----R--- * ASG bool N006 ( 3, 2) [000795] D------N---- +--* LCL_VAR int V59 tmp45 d:1 N005 ( 29, 8) [000755] ---X-------- \--* EQ int N003 ( 22, 5) [000754] ---X-------- +--* UMOD int N001 ( 1, 1) [000752] ------------ | +--* LCL_VAR int V06 loc2 u:1 N002 ( 1, 1) [000753] ------------ | \--* LCL_VAR int V53 tmp39 u:1 (last use) N004 ( 3, 2) [000751] ------------ \--* LCL_VAR int V55 tmp41 u:1 ***** BB51 STMT00145 (IL 0x258... ???) N004 ( 8, 15) [000806] -A--G---R--- * ASG ref N003 ( 3, 2) [000805] D------N---- +--* LCL_VAR ref V60 tmp46 d:1 N002 ( 4, 12) [000790] #---G------- \--* IND ref N001 ( 2, 10) [000789] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB51 STMT00146 (IL 0x258... ???) N004 ( 8, 15) [000808] -A--G---R--- * ASG ref N003 ( 3, 2) [000807] D------N---- +--* LCL_VAR ref V61 tmp47 d:1 N002 ( 4, 12) [000792] #---G------- \--* IND ref N001 ( 2, 10) [000791] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB51 STMT00143 (IL 0x258... ???) N004 ( 7, 6) [000801] ------------ * JTRUE void N003 ( 5, 4) [000800] J------N---- \--* NE int N001 ( 3, 2) [000798] ------------ +--* LCL_VAR int V59 tmp45 u:1 (last use) N002 ( 1, 1) [000799] ------------ \--* CNS_INT int 0 ------------ BB52 [258..259), preds={BB51} succs={BB53} ***** BB52 STMT00144 (IL 0x258... ???) N005 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 3, 2) [000802] ------------ arg0 in rcx +--* LCL_VAR ref V60 tmp46 u:1 (last use) N004 ( 3, 2) [000803] ------------ arg1 in rdx \--* LCL_VAR ref V61 tmp47 u:1 (last use) ------------ BB53 [258..259), preds={BB51,BB52} succs={BB54} ***** BB53 STMT00128 (IL 0x258... ???) N017 ( 35, 33) [000722] -A-XG---R--- * ASG byref N016 ( 3, 2) [000721] D------N---- +--* LCL_VAR byref V51 tmp37 d:1 N015 ( 31, 30) [001112] ---XG------- \--* COMMA byref N004 ( 12, 13) [001105] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 3, 2) [000758] ------------ | +--* LCL_VAR int V55 tmp41 u:1 N003 ( 5, 4) [001104] ---X-------- | \--* ARR_LENGTH int N002 ( 3, 2) [000712] ------------ | \--* LCL_VAR ref V52 tmp38 u:1 N014 ( 19, 17) [001113] ----G------- \--* ADDR byref N013 ( 10, 9) [000719] a---G--N---- \--* IND int N012 ( 9, 8) [001111] -------N---- \--* ADD byref N005 ( 3, 2) [001102] ------------ +--* LCL_VAR ref V52 tmp38 u:1 (last use) N011 ( 6, 6) [001110] -------N---- \--* ADD long N009 ( 5, 5) [001108] -------N---- +--* LSH long N007 ( 4, 4) [001106] ------------ | +--* CAST long <- int N006 ( 3, 2) [001103] i----------- | | \--* LCL_VAR int V55 tmp41 u:1 (last use) N008 ( 1, 1) [001107] -------N---- | \--* CNS_INT long 2 N010 ( 1, 1) [001109] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB53 STMT00034 (IL ???... ???) N003 ( 7, 5) [000170] -A------R--- * ASG byref N002 ( 3, 2) [000169] D------N---- +--* LCL_VAR byref V08 loc4 d:4 N001 ( 3, 2) [000723] ------------ \--* LCL_VAR byref V51 tmp37 u:1 (last use) ------------ BB54 [261..276), preds={BB48,BB53} succs={BB55} ***** BB54 STMT00170 (IL ???... ???) N005 ( 0, 0) [001193] -A------R--- * ASG byref N004 ( 0, 0) [001191] D------N---- +--* LCL_VAR byref V08 loc4 d:3 N003 ( 0, 0) [001192] ------------ \--* PHI byref N001 ( 0, 0) [001224] ------------ pred BB53 +--* PHI_ARG byref V08 loc4 u:4 N002 ( 0, 0) [001220] ------------ pred BB48 \--* PHI_ARG byref V08 loc4 u:1 ***** BB54 STMT00018 (IL 0x261...0x263) N003 ( 7, 5) [000083] -A------R--- * ASG int N002 ( 3, 2) [000082] D------N---- +--* LCL_VAR int V10 loc6 d:2 N001 ( 3, 2) [000081] ------------ \--* LCL_VAR int V13 loc9 u:1 ***** BB54 STMT00019 (IL 0x265...0x26A) N008 ( 10, 9) [000089] -A-XG---R--- * ASG int N007 ( 4, 4) [000088] D--XG--N---- +--* IND int N006 ( 2, 2) [001115] -------N---- | \--* ADD byref N004 ( 1, 1) [000084] ------------ | +--* LCL_VAR ref V00 this u:1 N005 ( 1, 1) [001114] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] N003 ( 5, 4) [000087] ------------ \--* ADD int N001 ( 3, 2) [000085] ------------ +--* LCL_VAR int V13 loc9 u:1 (last use) N002 ( 1, 1) [000086] ------------ \--* CNS_INT int 1 ***** BB54 STMT00020 (IL 0x26F...0x275) N006 ( 4, 4) [000093] -A-XG---R--- * ASG ref N005 ( 1, 1) [000092] D------N---- +--* LCL_VAR ref V04 loc0 d:3 N004 ( 4, 4) [000091] ---XG------- \--* IND ref N003 ( 2, 2) [001117] -------N---- \--* ADD byref N001 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001116] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] ------------ BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} ***** BB55 STMT00171 (IL ???... ???) N005 ( 0, 0) [001196] -A------R--- * ASG byref N004 ( 0, 0) [001194] D------N---- +--* LCL_VAR byref V08 loc4 d:2 N003 ( 0, 0) [001195] ------------ \--* PHI byref N001 ( 0, 0) [001225] ------------ pred BB47 +--* PHI_ARG byref V08 loc4 u:1 N002 ( 0, 0) [001221] ------------ pred BB54 \--* PHI_ARG byref V08 loc4 u:3 ***** BB55 STMT00169 (IL ???... ???) N005 ( 0, 0) [001190] -A------R--- * ASG ref N004 ( 0, 0) [001188] D------N---- +--* LCL_VAR ref V04 loc0 d:2 N003 ( 0, 0) [001189] ------------ \--* PHI ref N001 ( 0, 0) [001226] ------------ pred BB47 +--* PHI_ARG ref V04 loc0 u:1 N002 ( 0, 0) [001222] ------------ pred BB54 \--* PHI_ARG ref V04 loc0 u:3 ***** BB55 STMT00168 (IL ???... ???) N005 ( 0, 0) [001187] -A------R--- * ASG int N004 ( 0, 0) [001185] D------N---- +--* LCL_VAR int V10 loc6 d:1 N003 ( 0, 0) [001186] ------------ \--* PHI int N001 ( 0, 0) [001227] ------------ pred BB47 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [001223] ------------ pred BB54 \--* PHI_ARG int V10 loc6 u:2 ***** BB55 STMT00021 (IL 0x276...0x27E) N019 ( 39, 38) [000099] -A-XG---R--- * ASG byref N018 ( 3, 2) [000098] D------N---- +--* LCL_VAR byref V11 loc7 d:1 N017 ( 35, 35) [001128] ---XG------- \--* COMMA byref N004 ( 10, 12) [001121] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 3, 2) [000095] ------------ | +--* LCL_VAR int V10 loc6 u:1 N003 ( 3, 3) [001120] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000094] ------------ | \--* LCL_VAR ref V04 loc0 u:2 N016 ( 25, 23) [001131] ----G------- \--* ADDR byref N015 ( 13, 12) [000096] a---G--N---- \--* IND struct N014 ( 12, 11) [001127] -------N---- \--* ADD byref N005 ( 1, 1) [001118] ------------ +--* LCL_VAR ref V04 loc0 u:2 N013 ( 11, 10) [001126] -------N---- \--* ADD long N011 ( 10, 9) [001124] -------N---- +--* LSH long N009 ( 9, 8) [001130] ------------ | +--* MUL long N007 ( 4, 4) [001122] ------------ | | +--* CAST long <- int N006 ( 3, 2) [001119] i----------- | | | \--* LCL_VAR int V10 loc6 u:1 N008 ( 1, 1) [001129] ------------ | | \--* CNS_INT long 3 N010 ( 1, 1) [001123] -------N---- | \--* CNS_INT long 3 N012 ( 1, 1) [001125] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB55 STMT00022 (IL 0x280...0x283) N006 ( 8, 7) [000103] -A-XG------- * ASG int N004 ( 6, 5) [000102] *--XG--N---- +--* IND int N003 ( 4, 3) [001133] -------N---- | \--* ADD byref N001 ( 3, 2) [000100] ------------ | +--* LCL_VAR byref V11 loc7 u:1 N002 ( 1, 1) [001132] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] N005 ( 1, 1) [000101] ------------ \--* LCL_VAR int V06 loc2 u:1 (last use) ***** BB55 STMT00023 (IL 0x288...0x28F) N009 ( 15, 12) [000110] -A-XG---R--- * ASG int N008 ( 6, 5) [000109] *--XG--N---- +--* IND int N007 ( 4, 3) [001135] -------N---- | \--* ADD byref N005 ( 3, 2) [000104] ------------ | +--* LCL_VAR byref V11 loc7 u:1 N006 ( 1, 1) [001134] ------------ | \--* CNS_INT long 20 field offset Fseq[next] N004 ( 8, 6) [000108] ---XG------- \--* ADD int N002 ( 6, 4) [000106] *--XG------- +--* IND int N001 ( 3, 2) [000105] ------------ | \--* LCL_VAR byref V08 loc4 u:2 N003 ( 1, 1) [000107] ------------ \--* CNS_INT int -1 ***** BB55 STMT00024 (IL 0x294...0x297) N004 ( 8, 6) [000114] -A-XG------- * ASG ref N002 ( 6, 4) [000113] *--XG--N---- +--* IND ref N001 ( 3, 2) [000111] ------------ | \--* LCL_VAR byref V11 loc7 u:1 Zero Fseq[key] N003 ( 1, 1) [000112] ------------ \--* LCL_VAR ref V01 arg1 u:1 (last use) ***** BB55 STMT00025 (IL 0x29C...0x29F) N006 ( 8, 7) [000118] -A-XG------- * ASG ref N004 ( 6, 5) [000117] *--XG--N---- +--* IND ref N003 ( 4, 3) [001137] -------N---- | \--* ADD byref N001 ( 3, 2) [000115] ------------ | +--* LCL_VAR byref V11 loc7 u:1 (last use) N002 ( 1, 1) [001136] ------------ | \--* CNS_INT long 8 field offset Fseq[value] N005 ( 1, 1) [000116] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) ***** BB55 STMT00026 (IL 0x2A4...0x2AA) N006 ( 12, 9) [000124] -A-XG---R--- * ASG int N005 ( 6, 4) [000123] *--X---N---- +--* IND int N004 ( 3, 2) [000119] ------------ | \--* LCL_VAR byref V08 loc4 u:2 (last use) N003 ( 5, 4) [000122] ------------ \--* ADD int N001 ( 3, 2) [000120] ------------ +--* LCL_VAR int V10 loc6 u:1 (last use) N002 ( 1, 1) [000121] ------------ \--* CNS_INT int 1 ***** BB55 STMT00027 (IL 0x2AB...0x2B4) N011 ( 11, 11) [000131] -A-XG---R--- * ASG int N010 ( 4, 4) [000130] D--XG--N---- +--* IND int N009 ( 2, 2) [001139] -------N---- | \--* ADD byref N007 ( 1, 1) [000125] ------------ | +--* LCL_VAR ref V00 this u:1 N008 ( 1, 1) [001138] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] N006 ( 6, 6) [000129] ---XG------- \--* ADD int N004 ( 4, 4) [000127] ---XG------- +--* IND int N003 ( 2, 2) [001141] -------N---- | \--* ADD byref N001 ( 1, 1) [000126] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001140] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] N005 ( 1, 1) [000128] ------------ \--* CNS_INT int 1 ***** BB55 STMT00028 (IL 0x2CA...0x2CD) N004 ( 5, 5) [000148] ------------ * JTRUE void N003 ( 3, 3) [000147] N------N-U-- \--* LE int N001 ( 1, 1) [000145] ------------ +--* LCL_VAR int V07 loc3 u:2 (last use) N002 ( 1, 1) [000146] ------------ \--* CNS_INT int 100 ------------ BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} ***** BB56 STMT00030 (IL 0x2CF...0x2D5) N008 ( 21, 22) [000156] --C-G------- * JTRUE void N007 ( 19, 20) [000155] J-C-G--N---- \--* EQ int N005 ( 17, 18) [000153] --C-G------- +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS N003 ( 1, 1) [000151] ------------ arg1 in rdx | +--* LCL_VAR ref V05 loc1 u:1 (last use) N004 ( 2, 10) [000152] H------N---- arg0 in rcx | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 1, 1) [000154] ------------ \--* CNS_INT ref null ------------ BB57 [2D7..2E3), preds={BB56} succs={BB58} ***** BB57 STMT00031 (IL 0x2D7...0x2DC) N008 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize N005 ( 3, 3) [000159] ---X-------- arg1 in rdx +--* ARR_LENGTH int N004 ( 1, 1) [000158] ------------ | \--* LCL_VAR ref V04 loc0 u:2 (last use) N006 ( 1, 1) [000157] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 N007 ( 1, 1) [000160] ------------ arg2 in r8 \--* CNS_INT int 1 ------------ BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} ***** BB58 STMT00147 (IL ???... ???) N002 ( 2, 2) [000810] ------------ * RETURN int N001 ( 1, 1) [000482] ------------ \--* CNS_INT int 1 ------------ BB59 [008..00E) (throw), preds={BB01} succs={} ***** BB59 STMT00086 (IL 0x008...0x009) N003 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException N002 ( 1, 1) [000532] ------------ arg0 in rcx \--* CNS_INT int 4 ------------ BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} ***** BB60 STMT00073 (IL 0x14F...0x150) N004 ( 7, 5) [000444] -A-X----R--- * ASG long N003 ( 3, 2) [000443] D------N---- +--* LCL_VAR long V26 tmp12 d:1 N002 ( 3, 2) [000442] #--X-------- \--* IND long N001 ( 1, 1) [000441] !----------- \--* LCL_VAR ref V00 this u:1 ***** BB60 STMT00155 (IL ???... ???) N011 ( 16, 14) [001158] ------------ * JTRUE void N010 ( 14, 12) [000460] J------N---- \--* EQ int N008 ( 12, 10) [000456] n----------- +--* IND long N007 ( 10, 8) [000452] -------N---- | \--* ADD long N005 ( 9, 7) [000450] #----------- | +--* IND long N004 ( 6, 5) [000449] #----------- | | \--* IND long N003 ( 4, 3) [000448] -------N---- | | \--* ADD long N001 ( 3, 2) [000446] ------------ | | +--* LCL_VAR long V26 tmp12 u:1 N002 ( 1, 1) [000447] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000451] ------------ | \--* CNS_INT long 56 N009 ( 1, 1) [000459] ------------ \--* CNS_INT long 0 ------------ BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} ***** BB61 STMT00156 (IL ???... ???) N010 ( 16, 13) [001160] -A------R--- * ASG long N009 ( 3, 2) [001159] D------N---- +--* LCL_VAR long V28 tmp14 d:3 N008 ( 12, 10) [000461] n-----?----- \--* IND long N007 ( 10, 8) [000462] ------?N---- \--* ADD long N005 ( 9, 7) [000463] #-----?----- +--* IND long N004 ( 6, 5) [000464] #-----?----- | \--* IND long N003 ( 4, 3) [000465] ------?N---- | \--* ADD long N001 ( 3, 2) [000466] ------?----- | +--* LCL_VAR long V26 tmp12 u:1 (last use) N002 ( 1, 1) [000467] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000468] ------?----- \--* CNS_INT long 56 ------------ BB62 [???..???), preds={BB60} succs={BB63} ***** BB62 STMT00157 (IL ???... ???) N007 ( 23, 22) [001162] -AC-G---R--- * ASG long N006 ( 3, 2) [001161] D------N---- +--* LCL_VAR long V28 tmp14 d:2 N005 ( 19, 19) [000458] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 3, 2) [000445] ------?----- arg0 in rcx +--* LCL_VAR long V26 tmp12 u:1 (last use) N004 ( 2, 10) [000457] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB63 [???..157) (throw), preds={BB61,BB62} succs={} ***** BB63 STMT00167 (IL ???... ???) N005 ( 0, 0) [001184] -A------R--- * ASG long N004 ( 0, 0) [001182] D------N---- +--* LCL_VAR long V28 tmp14 d:1 N003 ( 0, 0) [001183] ------------ \--* PHI long N001 ( 0, 0) [001241] ------------ pred BB61 +--* PHI_ARG long V28 tmp14 u:3 N002 ( 0, 0) [001240] ------------ pred BB62 \--* PHI_ARG long V28 tmp14 u:2 ***** BB63 STMT00076 (IL ???... ???) N005 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException N003 ( 3, 2) [000473] ------------ arg0 in rcx +--* LCL_VAR long V28 tmp14 u:1 (last use) N004 ( 1, 1) [000455] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) ------------ BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} ***** BB64 STMT00053 (IL 0x1BC...0x1BD) N004 ( 7, 5) [000299] -A-X----R--- * ASG long N003 ( 3, 2) [000298] D------N---- +--* LCL_VAR long V21 tmp7 d:1 N002 ( 3, 2) [000297] #--X-------- \--* IND long N001 ( 1, 1) [000296] !----------- \--* LCL_VAR ref V00 this u:1 ***** BB64 STMT00161 (IL ???... ???) N011 ( 16, 14) [001168] ------------ * JTRUE void N010 ( 14, 12) [000315] J------N---- \--* EQ int N008 ( 12, 10) [000311] n----------- +--* IND long N007 ( 10, 8) [000307] -------N---- | \--* ADD long N005 ( 9, 7) [000305] #----------- | +--* IND long N004 ( 6, 5) [000304] #----------- | | \--* IND long N003 ( 4, 3) [000303] -------N---- | | \--* ADD long N001 ( 3, 2) [000301] ------------ | | +--* LCL_VAR long V21 tmp7 u:1 N002 ( 1, 1) [000302] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000306] ------------ | \--* CNS_INT long 56 N009 ( 1, 1) [000314] ------------ \--* CNS_INT long 0 ------------ BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} ***** BB65 STMT00162 (IL ???... ???) N010 ( 16, 13) [001170] -A------R--- * ASG long N009 ( 3, 2) [001169] D------N---- +--* LCL_VAR long V23 tmp9 d:3 N008 ( 12, 10) [000316] n-----?----- \--* IND long N007 ( 10, 8) [000317] ------?N---- \--* ADD long N005 ( 9, 7) [000318] #-----?----- +--* IND long N004 ( 6, 5) [000319] #-----?----- | \--* IND long N003 ( 4, 3) [000320] ------?N---- | \--* ADD long N001 ( 3, 2) [000321] ------?----- | +--* LCL_VAR long V21 tmp7 u:1 (last use) N002 ( 1, 1) [000322] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000323] ------?----- \--* CNS_INT long 56 ------------ BB66 [???..???), preds={BB64} succs={BB67} ***** BB66 STMT00163 (IL ???... ???) N007 ( 23, 22) [001172] -AC-G---R--- * ASG long N006 ( 3, 2) [001171] D------N---- +--* LCL_VAR long V23 tmp9 d:2 N005 ( 19, 19) [000313] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 3, 2) [000300] ------?----- arg0 in rcx +--* LCL_VAR long V21 tmp7 u:1 (last use) N004 ( 2, 10) [000312] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} ***** BB67 STMT00173 (IL ???... ???) N005 ( 0, 0) [001202] -A------R--- * ASG long N004 ( 0, 0) [001200] D------N---- +--* LCL_VAR long V23 tmp9 d:1 N003 ( 0, 0) [001201] ------------ \--* PHI long N001 ( 0, 0) [001232] ------------ pred BB65 +--* PHI_ARG long V23 tmp9 u:3 N002 ( 0, 0) [001231] ------------ pred BB66 \--* PHI_ARG long V23 tmp9 u:2 ***** BB67 STMT00056 (IL ???... ???) N005 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException N003 ( 3, 2) [000328] ------------ arg0 in rcx +--* LCL_VAR long V23 tmp9 u:1 (last use) N004 ( 1, 1) [000310] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) ------------ BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} ***** BB68 STMT00043 (IL 0x1DD...0x1E2) N001 ( 14, 5) [000233] --CXG------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Early Value Propagation *************** In optEarlyProp() After optEarlyProp: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target align BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal Loop1 gcsafe BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe BB36 [0108] 1 BB34 1 [???..???) i gcsafe BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen BB54 [0044] 2 BB48,BB53 0.50 [261..276) i BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} ***** BB01 STMT00000 (IL 0x000...0x006) N004 ( 5, 5) [000003] ------------ * JTRUE void N003 ( 3, 3) [000002] J------N---- \--* EQ int N001 ( 1, 1) [000000] ------------ +--* LCL_VAR ref V01 arg1 u:1 N002 ( 1, 1) [000001] ------------ \--* CNS_INT ref null ------------ BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00001 (IL 0x00E...0x014) N007 ( 8, 8) [000008] ---XG------- * JTRUE void N006 ( 6, 6) [000007] J--XG--N---- \--* NE int N004 ( 4, 4) [000005] ---XG------- +--* IND ref N003 ( 2, 2) [000814] -------N---- | \--* ADD byref N001 ( 1, 1) [000004] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000813] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] N005 ( 1, 1) [000006] ------------ \--* CNS_INT ref null ------------ BB03 [016..01E), preds={BB02} succs={BB04} ***** BB03 STMT00085 (IL ???... ???) N005 ( 16, 10) [000528] --CXG------- * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize N003 ( 1, 1) [000526] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 N004 ( 1, 1) [000527] ------------ arg1 in rdx \--* CNS_INT int 0 ------------ BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ***** BB04 STMT00088 (IL 0x01E... ???) N008 ( 9, 6) [000544] -A-XG---R--- * ASG bool N007 ( 1, 1) [000543] D------N---- +--* LCL_VAR int V33 tmp19 d:1 N006 ( 9, 6) [000012] N--XG------- \--* NE int N004 ( 4, 4) [000010] ---XG------- +--* IND ref N003 ( 2, 2) [000818] -------N---- | \--* ADD byref N001 ( 1, 1) [000009] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000817] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] N005 ( 1, 1) [000011] ------------ \--* CNS_INT ref null ***** BB04 STMT00091 (IL 0x01E... ???) N004 ( 4, 12) [000554] -A--G---R--- * ASG ref N003 ( 1, 1) [000553] D------N---- +--* LCL_VAR ref V34 tmp20 d:1 N002 ( 4, 12) [000538] #---G------- \--* IND ref N001 ( 2, 10) [000537] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB04 STMT00092 (IL 0x01E... ???) N004 ( 4, 12) [000556] -A--G---R--- * ASG ref N003 ( 1, 1) [000555] D------N---- +--* LCL_VAR ref V35 tmp21 d:1 N002 ( 4, 12) [000540] #---G------- \--* IND ref N001 ( 2, 10) [000539] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB04 STMT00089 (IL 0x01E... ???) N004 ( 5, 5) [000549] ------------ * JTRUE void N003 ( 3, 3) [000548] J------N---- \--* NE int N001 ( 1, 1) [000546] ------------ +--* LCL_VAR int V33 tmp19 u:1 (last use) N002 ( 1, 1) [000547] ------------ \--* CNS_INT int 0 ------------ BB05 [01E..01F), preds={BB04} succs={BB06} ***** BB05 STMT00090 (IL 0x01E... ???) N005 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 1, 1) [000550] ------------ arg0 in rcx +--* LCL_VAR ref V34 tmp20 u:1 (last use) N004 ( 1, 1) [000551] ------------ arg1 in rdx \--* LCL_VAR ref V35 tmp21 u:1 (last use) ------------ BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} ***** BB06 STMT00003 (IL 0x02C... ???) N006 ( 4, 4) [000018] -A-XG---R--- * ASG ref N005 ( 1, 1) [000017] D------N---- +--* LCL_VAR ref V04 loc0 d:1 N004 ( 4, 4) [000016] ---XG------- \--* IND ref N003 ( 2, 2) [000822] -------N---- \--* ADD byref N001 ( 1, 1) [000015] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000821] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] ***** BB06 STMT00094 (IL 0x033... ???) N005 ( 6, 3) [000566] -A------R--- * ASG bool N004 ( 1, 1) [000565] D------N---- +--* LCL_VAR int V36 tmp22 d:1 N003 ( 6, 3) [000021] N----------- \--* NE int N001 ( 1, 1) [000019] ------------ +--* LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000020] ------------ \--* CNS_INT ref null ***** BB06 STMT00097 (IL 0x033... ???) N004 ( 4, 12) [000576] -A--G---R--- * ASG ref N003 ( 1, 1) [000575] D------N---- +--* LCL_VAR ref V37 tmp23 d:1 N002 ( 4, 12) [000562] #---G------- \--* IND ref N001 ( 2, 10) [000561] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB06 STMT00095 (IL 0x033... ???) N004 ( 5, 5) [000571] ------------ * JTRUE void N003 ( 3, 3) [000570] J------N---- \--* NE int N001 ( 1, 1) [000568] ------------ +--* LCL_VAR int V36 tmp22 u:1 (last use) N002 ( 1, 1) [000569] ------------ \--* CNS_INT int 0 ------------ BB07 [033..034), preds={BB06} succs={BB08} ***** BB07 STMT00096 (IL 0x033... ???) N006 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail N004 ( 4, 12) [000824] #---G------- arg0 in rcx +--* IND ref N003 ( 2, 10) [000823] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" N005 ( 1, 1) [000573] ------------ arg1 in rdx \--* LCL_VAR ref V37 tmp23 u:1 (last use) ------------ BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} ***** BB08 STMT00005 (IL 0x041... ???) N006 ( 4, 4) [000028] -A-XG---R--- * ASG ref N005 ( 1, 1) [000027] D------N---- +--* LCL_VAR ref V05 loc1 d:1 N004 ( 4, 4) [000026] ---XG------- \--* IND ref N003 ( 2, 2) [000828] -------N---- \--* ADD byref N001 ( 1, 1) [000025] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000827] ------------ \--* CNS_INT long 24 field offset Fseq[_comparer] ***** BB08 STMT00006 (IL 0x048...0x049) N004 ( 5, 5) [000032] ------------ * JTRUE void N003 ( 3, 3) [000031] J------N---- \--* EQ int N001 ( 1, 1) [000029] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000030] ------------ \--* CNS_INT ref null ------------ BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} ***** BB09 STMT00079 (IL 0x04B...0x052) N004 ( 3, 3) [000489] -A-X----R--- * ASG long N003 ( 1, 1) [000488] D------N---- +--* LCL_VAR long V29 tmp15 d:1 N002 ( 3, 2) [000487] #--X-------- \--* IND long N001 ( 1, 1) [000486] !----------- \--* LCL_VAR ref V00 this u:1 ***** BB09 STMT00149 (IL ???... ???) N011 ( 14, 13) [001148] ------------ * JTRUE void N010 ( 12, 11) [000505] J------N---- \--* EQ int N008 ( 10, 9) [000501] n----------- +--* IND long N007 ( 8, 7) [000497] -------N---- | \--* ADD long N005 ( 7, 6) [000495] #----------- | +--* IND long N004 ( 4, 4) [000494] #----------- | | \--* IND long N003 ( 2, 2) [000493] -------N---- | | \--* ADD long N001 ( 1, 1) [000491] ------------ | | +--* LCL_VAR long V29 tmp15 u:1 N002 ( 1, 1) [000492] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000496] ------------ | \--* CNS_INT long 64 N009 ( 1, 1) [000504] ------------ \--* CNS_INT long 0 ------------ BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} ***** BB10 STMT00150 (IL ???... ???) N010 ( 10, 9) [001150] -A------R--- * ASG long N009 ( 1, 1) [001149] D------N---- +--* LCL_VAR long V31 tmp17 d:3 N008 ( 10, 9) [000506] n-----?----- \--* IND long N007 ( 8, 7) [000507] ------?N---- \--* ADD long N005 ( 7, 6) [000508] #-----?----- +--* IND long N004 ( 4, 4) [000509] #-----?----- | \--* IND long N003 ( 2, 2) [000510] ------?N---- | \--* ADD long N001 ( 1, 1) [000511] ------?----- | +--* LCL_VAR long V29 tmp15 u:1 (last use) N002 ( 1, 1) [000512] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000513] ------?----- \--* CNS_INT long 64 ------------ BB11 [???..???), preds={BB09} succs={BB12} ***** BB11 STMT00151 (IL ???... ???) N007 ( 17, 18) [001152] -AC-G---R--- * ASG long N006 ( 1, 1) [001151] D------N---- +--* LCL_VAR long V31 tmp17 d:2 N005 ( 17, 18) [000503] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 1, 1) [000490] ------?----- arg0 in rcx +--* LCL_VAR long V29 tmp15 u:1 (last use) N004 ( 2, 10) [000502] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} ***** BB12 STMT00178 (IL ???... ???) N005 ( 0, 0) [001217] -A------R--- * ASG long N004 ( 0, 0) [001215] D------N---- +--* LCL_VAR long V31 tmp17 d:1 N003 ( 0, 0) [001216] ------------ \--* PHI long N001 ( 0, 0) [001247] ------------ pred BB10 +--* PHI_ARG long V31 tmp17 u:3 N002 ( 0, 0) [001246] ------------ pred BB11 \--* PHI_ARG long V31 tmp17 u:2 ***** BB12 STMT00083 (IL ???... ???) N010 ( 31, 15) [000524] -ACXG---R--- * ASG int N009 ( 3, 2) [000523] D------N---- +--* LCL_VAR int V15 tmp1 d:3 N008 ( 27, 12) [000522] --CXG------- \--* CALL ind stub int N007 ( 1, 1) [000521] ------------ calli tgt \--* LCL_VAR long V31 tmp17 u:1 (last use) N004 ( 1, 1) [000484] ------------ this in rcx +--* LCL_VAR ref V05 loc1 u:1 N005 ( 1, 1) [000831] ------------ arg1 in r11 +--* LCL_VAR long V31 tmp17 u:1 r11 REG r11 N006 ( 1, 1) [000500] ------------ arg2 in rdx \--* LCL_VAR ref V01 arg1 u:1 ------------ BB13 [054..061), preds={BB08} succs={BB14} ***** BB13 STMT00007 (IL 0x054...0x05C) N013 ( 34, 21) [000038] -ACXG---R--- * ASG int N012 ( 3, 2) [000037] D------N---- +--* LCL_VAR int V15 tmp1 d:2 N011 ( 30, 18) [000035] --CXG------- \--* CALLV vt-ind int System.Object.GetHashCode N010 ( 9, 8) [000843] n--X-------- control expr \--* IND long N009 ( 7, 6) [000842] ---X---N---- \--* ADD long N007 ( 6, 5) [000840] #--X-------- +--* IND long N006 ( 4, 3) [000839] ---X---N---- | \--* ADD long N004 ( 3, 2) [000837] #--X-------- | +--* IND long N003 ( 1, 1) [000836] ------------ | | \--* LCL_VAR ref V01 arg1 u:1 N005 ( 1, 1) [000838] ------------ | \--* CNS_INT int 72 N008 ( 1, 1) [000841] ------------ \--* CNS_INT int 24 N002 ( 1, 1) [000033] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 ------------ BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ***** BB14 STMT00177 (IL ???... ???) N005 ( 0, 0) [001214] -A------R--- * ASG int N004 ( 0, 0) [001212] D------N---- +--* LCL_VAR int V15 tmp1 d:1 N003 ( 0, 0) [001213] ------------ \--* PHI int N001 ( 0, 0) [001245] ------------ pred BB12 +--* PHI_ARG int V15 tmp1 u:3 N002 ( 0, 0) [001244] ------------ pred BB13 \--* PHI_ARG int V15 tmp1 u:2 ***** BB14 STMT00008 (IL ???...0x061) N003 ( 3, 3) [000042] -A------R--- * ASG int N002 ( 1, 1) [000041] D------N---- +--* LCL_VAR int V06 loc2 d:1 N001 ( 3, 2) [000040] ------------ \--* LCL_VAR int V15 tmp1 u:1 (last use) ***** BB14 STMT00009 (IL 0x062...0x063) N003 ( 1, 3) [000045] -A------R--- * ASG int N002 ( 1, 1) [000044] D------N---- +--* LCL_VAR int V07 loc3 d:1 N001 ( 1, 1) [000043] ------------ \--* CNS_INT int 0 ***** BB14 STMT00098 (IL 0x064... ???) N006 ( 4, 4) [000580] -A-XG---R--- * ASG ref N005 ( 1, 1) [000579] D------N---- +--* LCL_VAR ref V39 tmp25 d:1 N004 ( 4, 4) [000578] ---XG------- \--* IND ref N003 ( 2, 2) [000845] -------N---- \--* ADD byref N001 ( 1, 1) [000046] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000844] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] ***** BB14 STMT00105 (IL 0x064... ???) N004 ( 3, 3) [000629] -A-X----R--- * ASG int N003 ( 1, 1) [000628] D------N---- +--* LCL_VAR int V40 tmp26 d:1 N002 ( 3, 3) [000583] ---X-------- \--* ARR_LENGTH int N001 ( 1, 1) [000582] ------------ \--* LCL_VAR ref V39 tmp25 u:1 ***** BB14 STMT00106 (IL 0x064... ???) N006 ( 4, 4) [000631] -A-XG---R--- * ASG long N005 ( 1, 1) [000630] D------N---- +--* LCL_VAR long V41 tmp27 d:1 N004 ( 4, 4) [000585] ---XG------- \--* IND long N003 ( 2, 2) [000847] -------N---- \--* ADD byref N001 ( 1, 1) [000584] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000846] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] ***** BB14 STMT00108 (IL 0x064... ???) N005 ( 6, 6) [000642] -A------R--- * ASG bool N004 ( 1, 1) [000641] D------N---- +--* LCL_VAR int V43 tmp29 d:1 N003 ( 6, 6) [000599] N--------U-- \--* LE int N001 ( 1, 1) [000597] ------------ +--* LCL_VAR int V40 tmp26 u:1 N002 ( 1, 4) [000598] ------------ \--* CNS_INT int 0x7FFFFFFF ***** BB14 STMT00111 (IL 0x064... ???) N004 ( 4, 12) [000652] -A--G---R--- * ASG ref N003 ( 1, 1) [000651] D------N---- +--* LCL_VAR ref V44 tmp30 d:1 N002 ( 4, 12) [000636] #---G------- \--* IND ref N001 ( 2, 10) [000635] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB14 STMT00112 (IL 0x064... ???) N004 ( 4, 12) [000654] -A--G---R--- * ASG ref N003 ( 1, 1) [000653] D------N---- +--* LCL_VAR ref V45 tmp31 d:1 N002 ( 4, 12) [000638] #---G------- \--* IND ref N001 ( 2, 10) [000637] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB14 STMT00109 (IL 0x064... ???) N004 ( 5, 5) [000647] ------------ * JTRUE void N003 ( 3, 3) [000646] J------N---- \--* NE int N001 ( 1, 1) [000644] ------------ +--* LCL_VAR int V43 tmp29 u:1 (last use) N002 ( 1, 1) [000645] ------------ \--* CNS_INT int 0 ------------ BB15 [064..065), preds={BB14} succs={BB16} ***** BB15 STMT00110 (IL 0x064... ???) N005 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 1, 1) [000648] ------------ arg0 in rcx +--* LCL_VAR ref V44 tmp30 u:1 (last use) N004 ( 1, 1) [000649] ------------ arg1 in rdx \--* LCL_VAR ref V45 tmp31 u:1 (last use) ------------ BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} ***** BB16 STMT00103 (IL 0x064... ???) N016 ( 20, 21) [000619] -A------R--- * ASG int N015 ( 1, 1) [000618] D------N---- +--* LCL_VAR int V42 tmp28 d:1 N014 ( 20, 21) [000617] ------------ \--* CAST int <- uint <- long N013 ( 19, 19) [000616] ------------ \--* RSZ long N011 ( 17, 17) [000614] ------------ +--* MUL long N008 ( 11, 11) [000611] ------------ | +--* ADD long N006 ( 9, 9) [000608] ------------ | | +--* RSZ long N004 ( 7, 7) [000606] ------------ | | | +--* MUL long N001 ( 1, 1) [000604] ------------ | | | | +--* LCL_VAR long V41 tmp27 u:1 (last use) N003 ( 2, 3) [000605] ---------U-- | | | | \--* CAST long <- ulong <- uint N002 ( 1, 1) [000047] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 N005 ( 1, 1) [000607] ------------ | | | \--* CNS_INT int 32 N007 ( 1, 1) [000610] ------------ | | \--* CNS_INT long 1 N010 ( 2, 3) [000613] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000612] ------------ | \--* LCL_VAR int V40 tmp26 u:1 N012 ( 1, 1) [000615] ------------ \--* CNS_INT int 32 ***** BB16 STMT00114 (IL 0x064... ???) N007 ( 27, 7) [000665] -A-X----R--- * ASG bool N006 ( 1, 1) [000664] D------N---- +--* LCL_VAR int V46 tmp32 d:1 N005 ( 27, 7) [000624] ---X-------- \--* EQ int N003 ( 22, 5) [000623] ---X-------- +--* UMOD int N001 ( 1, 1) [000621] ------------ | +--* LCL_VAR int V06 loc2 u:1 N002 ( 1, 1) [000622] ------------ | \--* LCL_VAR int V40 tmp26 u:1 (last use) N004 ( 1, 1) [000620] ------------ \--* LCL_VAR int V42 tmp28 u:1 ***** BB16 STMT00117 (IL 0x064... ???) N004 ( 4, 12) [000675] -A--G---R--- * ASG ref N003 ( 1, 1) [000674] D------N---- +--* LCL_VAR ref V47 tmp33 d:1 N002 ( 4, 12) [000659] #---G------- \--* IND ref N001 ( 2, 10) [000658] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB16 STMT00118 (IL 0x064... ???) N004 ( 4, 12) [000677] -A--G---R--- * ASG ref N003 ( 1, 1) [000676] D------N---- +--* LCL_VAR ref V48 tmp34 d:1 N002 ( 4, 12) [000661] #---G------- \--* IND ref N001 ( 2, 10) [000660] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB16 STMT00115 (IL 0x064... ???) N004 ( 5, 5) [000670] ------------ * JTRUE void N003 ( 3, 3) [000669] J------N---- \--* NE int N001 ( 1, 1) [000667] ------------ +--* LCL_VAR int V46 tmp32 u:1 (last use) N002 ( 1, 1) [000668] ------------ \--* CNS_INT int 0 ------------ BB17 [064..065), preds={BB16} succs={BB18} ***** BB17 STMT00116 (IL 0x064... ???) N005 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 1, 1) [000671] ------------ arg0 in rcx +--* LCL_VAR ref V47 tmp33 u:1 (last use) N004 ( 1, 1) [000672] ------------ arg1 in rdx \--* LCL_VAR ref V48 tmp34 u:1 (last use) ------------ BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} ***** BB18 STMT00100 (IL 0x064... ???) N017 ( 19, 24) [000591] -A-XG---R--- * ASG byref N016 ( 1, 1) [000590] D------N---- +--* LCL_VAR byref V38 tmp24 d:1 N015 ( 19, 24) [000862] ---XG------- \--* COMMA byref N004 ( 8, 11) [000855] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000627] ------------ | +--* LCL_VAR int V42 tmp28 u:1 N003 ( 3, 3) [000854] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000581] ------------ | \--* LCL_VAR ref V39 tmp25 u:1 N014 ( 11, 13) [000863] ----G------- \--* ADDR byref N013 ( 6, 7) [000588] a---G--N---- \--* IND int N012 ( 5, 6) [000861] -------N---- \--* ADD byref N005 ( 1, 1) [000852] ------------ +--* LCL_VAR ref V39 tmp25 u:1 (last use) N011 ( 4, 5) [000860] -------N---- \--* ADD long N009 ( 3, 4) [000858] -------N---- +--* LSH long N007 ( 2, 3) [000856] ------------ | +--* CAST long <- int N006 ( 1, 1) [000853] i----------- | | \--* LCL_VAR int V42 tmp28 u:1 (last use) N008 ( 1, 1) [000857] -------N---- | \--* CNS_INT long 2 N010 ( 1, 1) [000859] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB18 STMT00011 (IL ???... ???) N003 ( 5, 4) [000051] -A------R--- * ASG byref N002 ( 3, 2) [000050] D------N---- +--* LCL_VAR byref V08 loc4 d:1 N001 ( 1, 1) [000592] ------------ \--* LCL_VAR byref V38 tmp24 u:1 ***** BB18 STMT00012 (IL 0x06D...0x072) N006 ( 5, 4) [000057] -A-XG---R--- * ASG int N005 ( 1, 1) [000056] D------N---- +--* LCL_VAR int V09 loc5 d:1 N004 ( 5, 4) [000055] ---XG------- \--* ADD int N002 ( 3, 2) [000053] *--XG------- +--* IND int N001 ( 1, 1) [000052] ------------ | \--* LCL_VAR byref V38 tmp24 u:1 (last use) N003 ( 1, 1) [000054] ------------ \--* CNS_INT int -1 ***** BB18 STMT00013 (IL 0x074...0x075) N004 ( 5, 5) [000061] ------------ * JTRUE void N003 ( 3, 3) [000060] J------N---- \--* NE int N001 ( 1, 1) [000058] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000059] ------------ \--* CNS_INT ref null ------------ BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} ***** BB19 STMT00059 (IL 0x0FF...0x104) N004 ( 3, 3) [000356] -A-X----R--- * ASG long N003 ( 1, 1) [000355] D------N---- +--* LCL_VAR long V24 tmp10 d:1 N002 ( 3, 2) [000354] #--X-------- \--* IND long N001 ( 1, 1) [000353] !----------- \--* LCL_VAR ref V00 this u:1 ***** BB19 STMT00152 (IL ???... ???) N011 ( 14, 13) [001153] ------------ * JTRUE void N010 ( 12, 11) [000369] J------N---- \--* EQ int N008 ( 10, 9) [000365] n----------- +--* IND long N007 ( 8, 7) [000364] -------N---- | \--* ADD long N005 ( 7, 6) [000362] #----------- | +--* IND long N004 ( 4, 4) [000361] #----------- | | \--* IND long N003 ( 2, 2) [000360] -------N---- | | \--* ADD long N001 ( 1, 1) [000358] ------------ | | +--* LCL_VAR long V24 tmp10 u:1 N002 ( 1, 1) [000359] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000363] ------------ | \--* CNS_INT long 32 N009 ( 1, 1) [000368] ------------ \--* CNS_INT long 0 ------------ BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} ***** BB20 STMT00153 (IL ???... ???) N010 ( 14, 12) [001155] -A------R--- * ASG long N009 ( 3, 2) [001154] D------N---- +--* LCL_VAR long V25 tmp11 d:3 N008 ( 10, 9) [000370] n-----?----- \--* IND long N007 ( 8, 7) [000371] ------?N---- \--* ADD long N005 ( 7, 6) [000372] #-----?----- +--* IND long N004 ( 4, 4) [000373] #-----?----- | \--* IND long N003 ( 2, 2) [000374] ------?N---- | \--* ADD long N001 ( 1, 1) [000375] ------?----- | +--* LCL_VAR long V24 tmp10 u:1 (last use) N002 ( 1, 1) [000376] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000377] ------?----- \--* CNS_INT long 32 ------------ BB21 [???..???), preds={BB19} succs={BB22} ***** BB21 STMT00154 (IL ???... ???) N007 ( 21, 21) [001157] -AC-G---R--- * ASG long N006 ( 3, 2) [001156] D------N---- +--* LCL_VAR long V25 tmp11 d:2 N005 ( 17, 18) [000367] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 1, 1) [000357] ------?----- arg0 in rcx +--* LCL_VAR long V24 tmp10 u:1 (last use) N004 ( 2, 10) [000366] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB22 [???..106), preds={BB20,BB21} succs={BB23} ***** BB22 STMT00172 (IL ???... ???) N005 ( 0, 0) [001199] -A------R--- * ASG long N004 ( 0, 0) [001197] D------N---- +--* LCL_VAR long V25 tmp11 d:1 N003 ( 0, 0) [001198] ------------ \--* PHI long N001 ( 0, 0) [001243] ------------ pred BB20 +--* PHI_ARG long V25 tmp11 u:3 N002 ( 0, 0) [001242] ------------ pred BB21 \--* PHI_ARG long V25 tmp11 u:2 ***** BB22 STMT00062 (IL ???... ???) N005 ( 17, 8) [000386] -ACXG---R--- * ASG ref N004 ( 1, 1) [000385] D------N---- +--* LCL_VAR ref V12 loc8 d:1 N003 ( 17, 8) [000352] --CXG------- \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default N002 ( 3, 2) [000382] ------------ arg0 in rcx \--* LCL_VAR long V25 tmp11 u:1 (last use) ------------ BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} ***** BB23 STMT00165 (IL ???... ???) N005 ( 0, 0) [001178] -A------R--- * ASG int N004 ( 0, 0) [001176] D------N---- +--* LCL_VAR int V07 loc3 d:5 N003 ( 0, 0) [001177] ------------ \--* PHI int N001 ( 0, 0) [001238] ------------ pred BB27 +--* PHI_ARG int V07 loc3 u:6 N002 ( 0, 0) [001235] ------------ pred BB22 \--* PHI_ARG int V07 loc3 u:1 ***** BB23 STMT00164 (IL ???... ???) N005 ( 0, 0) [001175] -A------R--- * ASG int N004 ( 0, 0) [001173] D------N---- +--* LCL_VAR int V09 loc5 d:4 N003 ( 0, 0) [001174] ------------ \--* PHI int N001 ( 0, 0) [001239] ------------ pred BB27 +--* PHI_ARG int V09 loc5 u:5 N002 ( 0, 0) [001236] ------------ pred BB22 \--* PHI_ARG int V09 loc5 u:1 ***** BB23 STMT00063 (IL 0x106...0x10B) N005 ( 7, 7) [000391] ---X-------- * JTRUE void N004 ( 5, 5) [000390] N--X---N-U-- \--* LE int N002 ( 3, 3) [000389] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000388] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000387] ------------ \--* LCL_VAR int V09 loc5 u:4 ------------ BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} ***** BB24 STMT00064 (IL 0x110...0x11E) N023 ( 36, 39) [000399] ---XG------- * JTRUE void N022 ( 34, 37) [000398] N--XG--N-U-- \--* NE int N020 ( 32, 35) [000396] *--XG------- +--* IND int N019 ( 30, 33) [000868] ---XG--N---- | \--* ADD byref N017 ( 29, 32) [000879] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000872] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000393] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 N003 ( 3, 3) [000871] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000392] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000882] ----G------- | | \--* ADDR byref N015 ( 11, 11) [000394] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000878] -------N---- | | \--* ADD byref N005 ( 1, 1) [000869] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000877] -------N---- | | \--* ADD long N011 ( 8, 8) [000875] -------N---- | | +--* LSH long N009 ( 7, 7) [000881] ------------ | | | +--* MUL long N007 ( 2, 3) [000873] ------------ | | | | +--* CAST long <- int N006 ( 1, 1) [000870] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 N008 ( 1, 1) [000880] ------------ | | | | \--* CNS_INT long 3 N010 ( 1, 1) [000874] -------N---- | | | \--* CNS_INT long 3 N012 ( 1, 1) [000876] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000867] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] N021 ( 1, 1) [000397] ------------ \--* LCL_VAR int V06 loc2 u:1 ------------ BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} ***** BB25 STMT00069 (IL 0x120...0x135) N035 ( 67, 59) [000428] --CXG------- * JTRUE void N034 ( 65, 57) [000427] J-CXG--N---- \--* NE int N032 ( 63, 55) [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals N031 ( 9, 8) [000908] n--X-------- control expr | \--* IND long N030 ( 7, 6) [000907] ---X---N---- | \--* ADD long N028 ( 6, 5) [000905] #--X-------- | +--* IND long N027 ( 4, 3) [000904] ---X---N---- | | \--* ADD long N025 ( 3, 2) [000902] #--X-------- | | +--* IND long N024 ( 1, 1) [000901] ------------ | | | \--* LCL_VAR ref V12 loc8 u:1 N026 ( 1, 1) [000903] ------------ | | \--* CNS_INT int 72 N029 ( 1, 1) [000906] ------------ | \--* CNS_INT int 32 N021 ( 32, 34) [000893] ---XG------- arg1 in rdx | +--* COMMA ref N007 ( 8, 11) [000886] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N004 ( 1, 1) [000420] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 N006 ( 3, 3) [000885] ---X-------- | | | \--* ARR_LENGTH int N005 ( 1, 1) [000419] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N020 ( 24, 23) [000897] *---G------- | | \--* IND ref N019 ( 21, 21) [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] N018 ( 11, 11) [000421] a---G--N---- | | \--* IND struct N017 ( 10, 10) [000892] -------N---- | | \--* ADD byref N008 ( 1, 1) [000883] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N016 ( 9, 9) [000891] -------N---- | | \--* ADD long N014 ( 8, 8) [000889] -------N---- | | +--* LSH long N012 ( 7, 7) [000895] ------------ | | | +--* MUL long N010 ( 2, 3) [000887] ------------ | | | | +--* CAST long <- int N009 ( 1, 1) [000884] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 N011 ( 1, 1) [000894] ------------ | | | | \--* CNS_INT long 3 N013 ( 1, 1) [000888] -------N---- | | | \--* CNS_INT long 3 N015 ( 1, 1) [000890] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N022 ( 1, 1) [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 u:1 N023 ( 1, 1) [000424] ------------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 u:1 N033 ( 1, 1) [000426] ------------ \--* CNS_INT int 0 ------------ BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} ***** BB26 STMT00065 (IL 0x157...0x164) N022 ( 32, 35) [000406] -A-XG---R--- * ASG int N021 ( 1, 1) [000405] D------N---- +--* LCL_VAR int V09 loc5 d:5 N020 ( 32, 35) [000404] *--XG------- \--* IND int N019 ( 30, 33) [000932] ---XG--N---- \--* ADD byref N017 ( 29, 32) [000943] ---XG------- +--* COMMA byref N004 ( 8, 11) [000936] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000401] ------------ | | +--* LCL_VAR int V09 loc5 u:4 N003 ( 3, 3) [000935] ---X-------- | | \--* ARR_LENGTH int N002 ( 1, 1) [000400] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000946] ----G------- | \--* ADDR byref N015 ( 11, 11) [000402] a---G--N---- | \--* IND struct N014 ( 10, 10) [000942] -------N---- | \--* ADD byref N005 ( 1, 1) [000933] ------------ | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000941] -------N---- | \--* ADD long N011 ( 8, 8) [000939] -------N---- | +--* LSH long N009 ( 7, 7) [000945] ------------ | | +--* MUL long N007 ( 2, 3) [000937] ------------ | | | +--* CAST long <- int N006 ( 1, 1) [000934] i----------- | | | | \--* LCL_VAR int V09 loc5 u:4 (last use) N008 ( 1, 1) [000944] ------------ | | | \--* CNS_INT long 3 N010 ( 1, 1) [000938] -------N---- | | \--* CNS_INT long 3 N012 ( 1, 1) [000940] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000931] ------------ \--* CNS_INT long 20 field offset Fseq[next] ***** BB26 STMT00066 (IL 0x166...0x169) N005 ( 3, 3) [000411] -A------R--- * ASG int N004 ( 1, 1) [000410] D------N---- +--* LCL_VAR int V07 loc3 d:6 N003 ( 3, 3) [000409] ------------ \--* ADD int N001 ( 1, 1) [000407] ------------ +--* LCL_VAR int V07 loc3 u:5 (last use) N002 ( 1, 1) [000408] ------------ \--* CNS_INT int 1 ***** BB26 STMT00067 (IL 0x16A...0x16E) N005 ( 7, 7) [000416] ---X-------- * JTRUE void N004 ( 5, 5) [000415] N--X---N-U-- \--* LT int N002 ( 3, 3) [000414] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000413] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000412] ------------ \--* LCL_VAR int V07 loc3 u:6 ------------ BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} ------------ BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} ***** BB28 STMT00070 (IL 0x137...0x139) N005 ( 7, 8) [000432] ------------ * JTRUE void N004 ( 5, 6) [000431] N------N-U-- \--* NE int N002 ( 3, 4) [000909] ------------ +--* CAST int <- ubyte <- int N001 ( 2, 2) [000429] ------------ | \--* LCL_VAR int V03 arg3 u:1 N003 ( 1, 1) [000430] ------------ \--* CNS_INT int 1 ------------ BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} ***** BB29 STMT00077 (IL 0x13B...0x144) N022 ( 34, 37) [000481] -A-XG------- * ASG ref N020 ( 32, 35) [000480] *--XG--N---- +--* IND ref N019 ( 30, 33) [000911] ---XG--N---- | \--* ADD byref N017 ( 29, 32) [000922] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000915] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000476] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 N003 ( 3, 3) [000914] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000475] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000925] ----G------- | | \--* ADDR byref N015 ( 11, 11) [000477] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000921] -------N---- | | \--* ADD byref N005 ( 1, 1) [000912] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 (last use) N013 ( 9, 9) [000920] -------N---- | | \--* ADD long N011 ( 8, 8) [000918] -------N---- | | +--* LSH long N009 ( 7, 7) [000924] ------------ | | | +--* MUL long N007 ( 2, 3) [000916] ------------ | | | | +--* CAST long <- int N006 ( 1, 1) [000913] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 (last use) N008 ( 1, 1) [000923] ------------ | | | | \--* CNS_INT long 3 N010 ( 1, 1) [000917] -------N---- | | | \--* CNS_INT long 3 N012 ( 1, 1) [000919] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000910] ------------ | \--* CNS_INT long 8 field offset Fseq[value] N021 ( 1, 1) [000479] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) ------------ BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} ***** BB30 STMT00071 (IL 0x14B...0x14D) N005 ( 7, 8) [000436] ------------ * JTRUE void N004 ( 5, 6) [000435] N------N-U-- \--* EQ int N002 ( 3, 4) [000926] ------------ +--* CAST int <- ubyte <- int N001 ( 2, 2) [000433] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) N003 ( 1, 1) [000434] ------------ \--* CNS_INT int 2 ------------ BB31 [???..???) (return), preds={BB30,BB41} succs={} ***** BB31 STMT00148 (IL ???... ???) N002 ( 2, 2) [000811] ------------ * RETURN int N001 ( 1, 1) [000437] ------------ \--* CNS_INT int 0 ------------ BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} ***** BB32 STMT00175 (IL ???... ???) N005 ( 0, 0) [001208] -A------R--- * ASG int N004 ( 0, 0) [001206] D------N---- +--* LCL_VAR int V07 loc3 d:3 N003 ( 0, 0) [001207] ------------ \--* PHI int N001 ( 0, 0) [001229] ------------ pred BB43 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [001218] ------------ pred BB18 \--* PHI_ARG int V07 loc3 u:1 ***** BB32 STMT00174 (IL ???... ???) N005 ( 0, 0) [001205] -A------R--- * ASG int N004 ( 0, 0) [001203] D------N---- +--* LCL_VAR int V09 loc5 d:2 N003 ( 0, 0) [001204] ------------ \--* PHI int N001 ( 0, 0) [001230] ------------ pred BB43 +--* PHI_ARG int V09 loc5 u:3 N002 ( 0, 0) [001219] ------------ pred BB18 \--* PHI_ARG int V09 loc5 u:1 ***** BB32 STMT00014 (IL 0x177...0x17C) N005 ( 7, 7) [000066] ---X-------- * JTRUE void N004 ( 5, 5) [000065] N--X---N-U-- \--* LE int N002 ( 3, 3) [000064] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000063] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000062] ------------ \--* LCL_VAR int V09 loc5 u:2 ------------ BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} ***** BB33 STMT00039 (IL 0x17E...0x18C) N023 ( 36, 39) [000215] ---XG------- * JTRUE void N022 ( 34, 37) [000214] N--XG--N-U-- \--* NE int N020 ( 32, 35) [000212] *--XG------- +--* IND int N019 ( 30, 33) [000948] ---XG--N---- | \--* ADD byref N017 ( 29, 32) [000959] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000952] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000209] ------------ | | | +--* LCL_VAR int V09 loc5 u:2 N003 ( 3, 3) [000951] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000208] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000962] ----G------- | | \--* ADDR byref N015 ( 11, 11) [000210] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000958] -------N---- | | \--* ADD byref N005 ( 1, 1) [000949] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000957] -------N---- | | \--* ADD long N011 ( 8, 8) [000955] -------N---- | | +--* LSH long N009 ( 7, 7) [000961] ------------ | | | +--* MUL long N007 ( 2, 3) [000953] ------------ | | | | +--* CAST long <- int N006 ( 1, 1) [000950] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:2 N008 ( 1, 1) [000960] ------------ | | | | \--* CNS_INT long 3 N010 ( 1, 1) [000954] -------N---- | | | \--* CNS_INT long 3 N012 ( 1, 1) [000956] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000947] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] N021 ( 1, 1) [000213] ------------ \--* LCL_VAR int V06 loc2 u:1 ------------ BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} ***** BB34 STMT00045 (IL 0x18E...0x1A2) N020 ( 32, 34) [000246] -A-XG---R--- * ASG ref N019 ( 1, 1) [000245] D------N---- +--* LCL_VAR ref V17 tmp3 d:1 N018 ( 32, 34) [000973] ---XG------- \--* COMMA ref N004 ( 8, 11) [000966] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000236] ------------ | +--* LCL_VAR int V09 loc5 u:2 N003 ( 3, 3) [000965] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000235] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N017 ( 24, 23) [000977] *---G------- \--* IND ref N016 ( 21, 21) [000976] ----G------- \--* ADDR byref Zero Fseq[key] N015 ( 11, 11) [000237] a---G--N---- \--* IND struct N014 ( 10, 10) [000972] -------N---- \--* ADD byref N005 ( 1, 1) [000963] ------------ +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000971] -------N---- \--* ADD long N011 ( 8, 8) [000969] -------N---- +--* LSH long N009 ( 7, 7) [000975] ------------ | +--* MUL long N007 ( 2, 3) [000967] ------------ | | +--* CAST long <- int N006 ( 1, 1) [000964] i----------- | | | \--* LCL_VAR int V09 loc5 u:2 N008 ( 1, 1) [000974] ------------ | | \--* CNS_INT long 3 N010 ( 1, 1) [000968] -------N---- | \--* CNS_INT long 3 N012 ( 1, 1) [000970] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB34 STMT00044 (IL 0x18E... ???) N004 ( 3, 3) [000244] -A-X----R--- * ASG long N003 ( 1, 1) [000243] D------N---- +--* LCL_VAR long V16 tmp2 d:1 N002 ( 3, 2) [000242] #--X-------- \--* IND long N001 ( 1, 1) [000241] !----------- \--* LCL_VAR ref V00 this u:1 ***** BB34 STMT00158 (IL ???... ???) N011 ( 14, 13) [001163] ------------ * JTRUE void N010 ( 12, 11) [000263] J------N---- \--* EQ int N008 ( 10, 9) [000259] n----------- +--* IND long N007 ( 8, 7) [000255] -------N---- | \--* ADD long N005 ( 7, 6) [000253] #----------- | +--* IND long N004 ( 4, 4) [000252] #----------- | | \--* IND long N003 ( 2, 2) [000251] -------N---- | | \--* ADD long N001 ( 1, 1) [000249] ------------ | | +--* LCL_VAR long V16 tmp2 u:1 N002 ( 1, 1) [000250] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000254] ------------ | \--* CNS_INT long 48 N009 ( 1, 1) [000262] ------------ \--* CNS_INT long 0 ------------ BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} ***** BB35 STMT00159 (IL ???... ???) N010 ( 10, 9) [001165] -A------R--- * ASG long N009 ( 1, 1) [001164] D------N---- +--* LCL_VAR long V19 tmp5 d:3 N008 ( 10, 9) [000264] n-----?----- \--* IND long N007 ( 8, 7) [000265] ------?N---- \--* ADD long N005 ( 7, 6) [000266] #-----?----- +--* IND long N004 ( 4, 4) [000267] #-----?----- | \--* IND long N003 ( 2, 2) [000268] ------?N---- | \--* ADD long N001 ( 1, 1) [000269] ------?----- | +--* LCL_VAR long V16 tmp2 u:1 (last use) N002 ( 1, 1) [000270] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000271] ------?----- \--* CNS_INT long 48 ------------ BB36 [???..???), preds={BB34} succs={BB37} ***** BB36 STMT00160 (IL ???... ???) N007 ( 17, 18) [001167] -AC-G---R--- * ASG long N006 ( 1, 1) [001166] D------N---- +--* LCL_VAR long V19 tmp5 d:2 N005 ( 17, 18) [000261] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 1, 1) [000248] ------?----- arg0 in rcx +--* LCL_VAR long V16 tmp2 u:1 (last use) N004 ( 2, 10) [000260] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} ***** BB37 STMT00176 (IL ???... ???) N005 ( 0, 0) [001211] -A------R--- * ASG long N004 ( 0, 0) [001209] D------N---- +--* LCL_VAR long V19 tmp5 d:1 N003 ( 0, 0) [001210] ------------ \--* PHI long N001 ( 0, 0) [001234] ------------ pred BB35 +--* PHI_ARG long V19 tmp5 u:3 N002 ( 0, 0) [001233] ------------ pred BB36 \--* PHI_ARG long V19 tmp5 u:2 ***** BB37 STMT00049 (IL ???... ???) N013 ( 32, 18) [000283] --CXG------- * JTRUE void N012 ( 30, 16) [000282] J-CXG--N---- \--* EQ int N010 ( 28, 14) [000280] --CXG------- +--* CALL ind stub int N009 ( 1, 1) [000279] ------------ calli tgt | \--* LCL_VAR long V19 tmp5 u:1 (last use) N005 ( 1, 1) [000234] ------------ this in rcx | +--* LCL_VAR ref V05 loc1 u:1 N006 ( 1, 1) [000980] ------------ arg1 in r11 | +--* LCL_VAR long V19 tmp5 u:1 r11 REG r11 N007 ( 1, 1) [000247] ------------ arg2 in rdx | +--* LCL_VAR ref V17 tmp3 u:1 (last use) N008 ( 1, 1) [000258] ------------ arg3 in r8 | \--* LCL_VAR ref V01 arg1 u:1 N011 ( 1, 1) [000281] ------------ \--* CNS_INT int 0 ------------ BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} ***** BB38 STMT00050 (IL 0x1A4...0x1A6) N005 ( 7, 8) [000287] ------------ * JTRUE void N004 ( 5, 6) [000286] N------N-U-- \--* NE int N002 ( 3, 4) [000985] ------------ +--* CAST int <- ubyte <- int N001 ( 2, 2) [000284] ------------ | \--* LCL_VAR int V03 arg3 u:1 N003 ( 1, 1) [000285] ------------ \--* CNS_INT int 1 ------------ BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} ***** BB39 STMT00057 (IL 0x1A8...0x1B1) N022 ( 34, 37) [000336] -A-XG------- * ASG ref N020 ( 32, 35) [000335] *--XG--N---- +--* IND ref N019 ( 30, 33) [000987] ---XG--N---- | \--* ADD byref N017 ( 29, 32) [000998] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000991] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000331] ------------ | | | +--* LCL_VAR int V09 loc5 u:2 N003 ( 3, 3) [000990] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000330] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [001001] ----G------- | | \--* ADDR byref N015 ( 11, 11) [000332] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000997] -------N---- | | \--* ADD byref N005 ( 1, 1) [000988] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 (last use) N013 ( 9, 9) [000996] -------N---- | | \--* ADD long N011 ( 8, 8) [000994] -------N---- | | +--* LSH long N009 ( 7, 7) [001000] ------------ | | | +--* MUL long N007 ( 2, 3) [000992] ------------ | | | | +--* CAST long <- int N006 ( 1, 1) [000989] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:2 (last use) N008 ( 1, 1) [000999] ------------ | | | | \--* CNS_INT long 3 N010 ( 1, 1) [000993] -------N---- | | | \--* CNS_INT long 3 N012 ( 1, 1) [000995] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000986] ------------ | \--* CNS_INT long 8 field offset Fseq[value] N021 ( 1, 1) [000334] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) ------------ BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} ***** BB40 STMT00051 (IL 0x1B8...0x1BA) N005 ( 7, 8) [000291] ------------ * JTRUE void N004 ( 5, 6) [000290] N------N-U-- \--* EQ int N002 ( 3, 4) [001002] ------------ +--* CAST int <- ubyte <- int N001 ( 2, 2) [000288] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) N003 ( 1, 1) [000289] ------------ \--* CNS_INT int 2 ------------ BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} ------------ BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} ***** BB42 STMT00040 (IL 0x1C4...0x1D1) N022 ( 32, 35) [000222] -A-XG---R--- * ASG int N021 ( 1, 1) [000221] D------N---- +--* LCL_VAR int V09 loc5 d:3 N020 ( 32, 35) [000220] *--XG------- \--* IND int N019 ( 30, 33) [001009] ---XG--N---- \--* ADD byref N017 ( 29, 32) [001020] ---XG------- +--* COMMA byref N004 ( 8, 11) [001013] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000217] ------------ | | +--* LCL_VAR int V09 loc5 u:2 N003 ( 3, 3) [001012] ---X-------- | | \--* ARR_LENGTH int N002 ( 1, 1) [000216] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [001023] ----G------- | \--* ADDR byref N015 ( 11, 11) [000218] a---G--N---- | \--* IND struct N014 ( 10, 10) [001019] -------N---- | \--* ADD byref N005 ( 1, 1) [001010] ------------ | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [001018] -------N---- | \--* ADD long N011 ( 8, 8) [001016] -------N---- | +--* LSH long N009 ( 7, 7) [001022] ------------ | | +--* MUL long N007 ( 2, 3) [001014] ------------ | | | +--* CAST long <- int N006 ( 1, 1) [001011] i----------- | | | | \--* LCL_VAR int V09 loc5 u:2 (last use) N008 ( 1, 1) [001021] ------------ | | | \--* CNS_INT long 3 N010 ( 1, 1) [001015] -------N---- | | \--* CNS_INT long 3 N012 ( 1, 1) [001017] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [001008] ------------ \--* CNS_INT long 20 field offset Fseq[next] ***** BB42 STMT00041 (IL 0x1D3...0x1D6) N005 ( 3, 3) [000227] -A------R--- * ASG int N004 ( 1, 1) [000226] D------N---- +--* LCL_VAR int V07 loc3 d:4 N003 ( 3, 3) [000225] ------------ \--* ADD int N001 ( 1, 1) [000223] ------------ +--* LCL_VAR int V07 loc3 u:3 (last use) N002 ( 1, 1) [000224] ------------ \--* CNS_INT int 1 ***** BB42 STMT00042 (IL 0x1D7...0x1DB) N005 ( 7, 7) [000232] ---X-------- * JTRUE void N004 ( 5, 5) [000231] N--X---N-U-- \--* LT int N002 ( 3, 3) [000230] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000229] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000228] ------------ \--* LCL_VAR int V07 loc3 u:4 ------------ BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} ------------ BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} ***** BB44 STMT00166 (IL ???... ???) N005 ( 0, 0) [001181] -A------R--- * ASG int N004 ( 0, 0) [001179] D------N---- +--* LCL_VAR int V07 loc3 d:2 N003 ( 0, 0) [001180] ------------ \--* PHI int N001 ( 0, 0) [001237] ------------ pred BB23 +--* PHI_ARG int V07 loc3 u:5 N002 ( 0, 0) [001228] ------------ pred BB32 \--* PHI_ARG int V07 loc3 u:3 ***** BB44 STMT00015 (IL 0x1E4...0x1EB) N007 ( 8, 8) [000071] ---XG------- * JTRUE void N006 ( 6, 6) [000070] J--XG--N---- \--* LE int N004 ( 4, 4) [000068] ---XG------- +--* IND int N003 ( 2, 2) [001025] -------N---- | \--* ADD byref N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001024] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] N005 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 ------------ BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} ***** BB45 STMT00035 (IL 0x1ED...0x1F3) N006 ( 8, 7) [000174] -A-XG---R--- * ASG int N005 ( 3, 2) [000173] D------N---- +--* LCL_VAR int V10 loc6 d:3 N004 ( 4, 4) [000172] ---XG------- \--* IND int N003 ( 2, 2) [001027] -------N---- \--* ADD byref N001 ( 1, 1) [000171] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001026] ------------ \--* CNS_INT long 60 field offset Fseq[_freeList] ***** BB45 STMT00120 (IL 0x1F5... ???) N034 ( 48, 47) [000688] -A-XG---R--- * ASG bool N033 ( 3, 2) [000687] D------N---- +--* LCL_VAR int V49 tmp35 d:1 N032 ( 44, 44) [000184] -A-XG------- \--* GE int N030 ( 39, 42) [000182] -A-XG------- +--* ADD int N028 ( 37, 40) [001050] -A-XG------- | +--* NEG int N027 ( 36, 39) [000181] *A-XG------- | | \--* IND int N026 ( 34, 37) [001029] -A-XG--N---- | | \--* ADD byref N024 ( 33, 36) [001044] -A-XG------- | | +--* COMMA byref N006 ( 4, 4) [001032] -A-XG---R--- | | | +--* ASG int N005 ( 1, 1) [001031] D------N---- | | | | +--* LCL_VAR int V62 tmp48 d:1 N004 ( 4, 4) [000178] ---XG------- | | | | \--* IND int N003 ( 2, 2) [001046] -------N---- | | | | \--* ADD byref N001 ( 1, 1) [000177] ------------ | | | | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001045] ------------ | | | | \--* CNS_INT long 60 field offset Fseq[_freeList] N023 ( 29, 32) [001043] ---XG------- | | | \--* COMMA byref N010 ( 8, 11) [001036] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [001033] ------------ | | | | +--* LCL_VAR int V62 tmp48 u:1 N009 ( 3, 3) [001035] ---X-------- | | | | \--* ARR_LENGTH int N008 ( 1, 1) [000176] ------------ | | | | \--* LCL_VAR ref V04 loc0 u:1 N022 ( 21, 21) [001049] ----G------- | | | \--* ADDR byref N021 ( 11, 11) [000179] a---G--N---- | | | \--* IND struct N020 ( 10, 10) [001042] -------N---- | | | \--* ADD byref N011 ( 1, 1) [001030] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N019 ( 9, 9) [001041] -------N---- | | | \--* ADD long N017 ( 8, 8) [001039] -------N---- | | | +--* LSH long N015 ( 7, 7) [001048] ------------ | | | | +--* MUL long N013 ( 2, 3) [001037] ------------ | | | | | +--* CAST long <- int N012 ( 1, 1) [001034] i----------- | | | | | | \--* LCL_VAR int V62 tmp48 u:1 (last use) N014 ( 1, 1) [001047] ------------ | | | | | \--* CNS_INT long 3 N016 ( 1, 1) [001038] -------N---- | | | | \--* CNS_INT long 3 N018 ( 1, 1) [001040] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] N025 ( 1, 1) [001028] ------------ | | \--* CNS_INT long 20 field offset Fseq[next] N029 ( 1, 1) [000175] ------------ | \--* CNS_INT int -3 N031 ( 1, 1) [000183] ------------ \--* CNS_INT int -1 ***** BB45 STMT00123 (IL 0x1F5... ???) N004 ( 8, 15) [000698] -A--G---R--- * ASG ref N003 ( 3, 2) [000697] D------N---- +--* LCL_VAR ref V50 tmp36 d:1 N002 ( 4, 12) [000684] #---G------- \--* IND ref N001 ( 2, 10) [000683] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB45 STMT00121 (IL 0x1F5... ???) N004 ( 7, 6) [000693] ------------ * JTRUE void N003 ( 5, 4) [000692] J------N---- \--* NE int N001 ( 3, 2) [000690] ------------ +--* LCL_VAR int V49 tmp35 u:1 (last use) N002 ( 1, 1) [000691] ------------ \--* CNS_INT int 0 ------------ BB46 [1F5..1F6), preds={BB45} succs={BB47} ***** BB46 STMT00122 (IL 0x1F5... ???) N006 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail N004 ( 4, 12) [001052] #---G------- arg0 in rcx +--* IND ref N003 ( 2, 10) [001051] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" N005 ( 3, 2) [000695] ------------ arg1 in rdx \--* LCL_VAR ref V50 tmp36 u:1 (last use) ------------ BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} ***** BB47 STMT00037 (IL 0x219... ???) N035 ( 44, 47) [000200] -A-XG------- * ASG int N004 ( 4, 4) [000199] D--XG--N---- +--* IND int N003 ( 2, 2) [001056] -------N---- | \--* ADD byref N001 ( 1, 1) [000190] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001055] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] N034 ( 39, 42) [000198] -A-XG------- \--* ADD int N032 ( 37, 40) [001079] -A-XG------- +--* NEG int N031 ( 36, 39) [000197] *A-XG------- | \--* IND int N030 ( 34, 37) [001058] -A-XG--N---- | \--* ADD byref N028 ( 33, 36) [001073] -A-XG------- | +--* COMMA byref N010 ( 4, 4) [001061] -A-XG---R--- | | +--* ASG int N009 ( 1, 1) [001060] D------N---- | | | +--* LCL_VAR int V63 tmp49 d:1 N008 ( 4, 4) [000194] ---XG------- | | | \--* IND int N007 ( 2, 2) [001075] -------N---- | | | \--* ADD byref N005 ( 1, 1) [000193] ------------ | | | +--* LCL_VAR ref V00 this u:1 N006 ( 1, 1) [001074] ------------ | | | \--* CNS_INT long 60 field offset Fseq[_freeList] N027 ( 29, 32) [001072] ---XG------- | | \--* COMMA byref N014 ( 8, 11) [001065] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N011 ( 1, 1) [001062] ------------ | | | +--* LCL_VAR int V63 tmp49 u:1 N013 ( 3, 3) [001064] ---X-------- | | | \--* ARR_LENGTH int N012 ( 1, 1) [000192] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N026 ( 21, 21) [001078] ----G------- | | \--* ADDR byref N025 ( 11, 11) [000195] a---G--N---- | | \--* IND struct N024 ( 10, 10) [001071] -------N---- | | \--* ADD byref N015 ( 1, 1) [001059] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N023 ( 9, 9) [001070] -------N---- | | \--* ADD long N021 ( 8, 8) [001068] -------N---- | | +--* LSH long N019 ( 7, 7) [001077] ------------ | | | +--* MUL long N017 ( 2, 3) [001066] ------------ | | | | +--* CAST long <- int N016 ( 1, 1) [001063] i----------- | | | | | \--* LCL_VAR int V63 tmp49 u:1 (last use) N018 ( 1, 1) [001076] ------------ | | | | \--* CNS_INT long 3 N020 ( 1, 1) [001067] -------N---- | | | \--* CNS_INT long 3 N022 ( 1, 1) [001069] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N029 ( 1, 1) [001057] ------------ | \--* CNS_INT long 20 field offset Fseq[next] N033 ( 1, 1) [000191] ------------ \--* CNS_INT int -3 ***** BB47 STMT00038 (IL 0x233...0x23C) N011 ( 11, 11) [000207] -A-XG---R--- * ASG int N010 ( 4, 4) [000206] D--XG--N---- +--* IND int N009 ( 2, 2) [001081] -------N---- | \--* ADD byref N007 ( 1, 1) [000201] ------------ | +--* LCL_VAR ref V00 this u:1 N008 ( 1, 1) [001080] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] N006 ( 6, 6) [000205] ---XG------- \--* ADD int N004 ( 4, 4) [000203] ---XG------- +--* IND int N003 ( 2, 2) [001083] -------N---- | \--* ADD byref N001 ( 1, 1) [000202] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001082] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] N005 ( 1, 1) [000204] ------------ \--* CNS_INT int -1 ------------ BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} ***** BB48 STMT00016 (IL 0x243...0x249) N006 ( 8, 7) [000075] -A-XG---R--- * ASG int N005 ( 3, 2) [000074] D------N---- +--* LCL_VAR int V13 loc9 d:1 N004 ( 4, 4) [000073] ---XG------- \--* IND int N003 ( 2, 2) [001085] -------N---- \--* ADD byref N001 ( 1, 1) [000072] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001084] ------------ \--* CNS_INT long 56 field offset Fseq[_count] ***** BB48 STMT00017 (IL 0x24B...0x250) N005 ( 9, 8) [000080] ---X-------- * JTRUE void N004 ( 7, 6) [000079] N--X---N-U-- \--* NE int N002 ( 3, 3) [000078] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000077] ------------ | \--* LCL_VAR ref V04 loc0 u:1 (last use) N003 ( 3, 2) [000076] ------------ \--* LCL_VAR int V13 loc9 u:1 ------------ BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00125 (IL 0x252... ???) N014 ( 44, 26) [000705] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize N009 ( 22, 13) [001090] -ACXG---R-L- arg1 SETUP +--* ASG int N008 ( 3, 2) [001089] D------N---- | +--* LCL_VAR int V64 tmp50 d:1 N007 ( 18, 10) [000702] --CXG------- | \--* CALL int System.Collections.HashHelpers.ExpandPrime N006 ( 4, 4) [000701] ---XG------- arg0 in rcx | \--* IND int N005 ( 2, 2) [001087] -------N---- | \--* ADD byref N003 ( 1, 1) [000700] ------------ | +--* LCL_VAR ref V00 this u:1 N004 ( 1, 1) [001086] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] N011 ( 3, 2) [001091] ------------ arg1 in rdx +--* LCL_VAR int V64 tmp50 u:1 (last use) N012 ( 1, 1) [000163] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 N013 ( 1, 1) [000704] ------------ arg2 in r8 \--* CNS_INT int 0 ***** BB49 STMT00126 (IL 0x258... ???) N006 ( 8, 7) [000711] -A-XG---R--- * ASG ref N005 ( 3, 2) [000710] D------N---- +--* LCL_VAR ref V52 tmp38 d:1 N004 ( 4, 4) [000709] ---XG------- \--* IND ref N003 ( 2, 2) [001095] -------N---- \--* ADD byref N001 ( 1, 1) [000165] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001094] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] ***** BB49 STMT00133 (IL 0x258... ???) N004 ( 5, 4) [000760] -A-X----R--- * ASG int N003 ( 1, 1) [000759] D------N---- +--* LCL_VAR int V53 tmp39 d:1 N002 ( 5, 4) [000714] ---X-------- \--* ARR_LENGTH int N001 ( 3, 2) [000713] ------------ \--* LCL_VAR ref V52 tmp38 u:1 ***** BB49 STMT00134 (IL 0x258... ???) N006 ( 8, 7) [000762] -A-XG---R--- * ASG long N005 ( 3, 2) [000761] D------N---- +--* LCL_VAR long V54 tmp40 d:1 N004 ( 4, 4) [000716] ---XG------- \--* IND long N003 ( 2, 2) [001097] -------N---- \--* ADD byref N001 ( 1, 1) [000715] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001096] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] ***** BB49 STMT00136 (IL 0x258... ???) N005 ( 10, 9) [000773] -A------R--- * ASG bool N004 ( 3, 2) [000772] D------N---- +--* LCL_VAR int V56 tmp42 d:1 N003 ( 6, 6) [000730] N--------U-- \--* LE int N001 ( 1, 1) [000728] ------------ +--* LCL_VAR int V53 tmp39 u:1 N002 ( 1, 4) [000729] ------------ \--* CNS_INT int 0x7FFFFFFF ***** BB49 STMT00139 (IL 0x258... ???) N004 ( 8, 15) [000783] -A--G---R--- * ASG ref N003 ( 3, 2) [000782] D------N---- +--* LCL_VAR ref V57 tmp43 d:1 N002 ( 4, 12) [000767] #---G------- \--* IND ref N001 ( 2, 10) [000766] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB49 STMT00140 (IL 0x258... ???) N004 ( 8, 15) [000785] -A--G---R--- * ASG ref N003 ( 3, 2) [000784] D------N---- +--* LCL_VAR ref V58 tmp44 d:1 N002 ( 4, 12) [000769] #---G------- \--* IND ref N001 ( 2, 10) [000768] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB49 STMT00137 (IL 0x258... ???) N004 ( 7, 6) [000778] ------------ * JTRUE void N003 ( 5, 4) [000777] J------N---- \--* NE int N001 ( 3, 2) [000775] ------------ +--* LCL_VAR int V56 tmp42 u:1 (last use) N002 ( 1, 1) [000776] ------------ \--* CNS_INT int 0 ------------ BB50 [258..259), preds={BB49} succs={BB51} ***** BB50 STMT00138 (IL 0x258... ???) N005 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 3, 2) [000779] ------------ arg0 in rcx +--* LCL_VAR ref V57 tmp43 u:1 (last use) N004 ( 3, 2) [000780] ------------ arg1 in rdx \--* LCL_VAR ref V58 tmp44 u:1 (last use) ------------ BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00131 (IL 0x258... ???) N016 ( 26, 25) [000750] -A------R--- * ASG int N015 ( 3, 2) [000749] D------N---- +--* LCL_VAR int V55 tmp41 d:1 N014 ( 22, 22) [000748] ------------ \--* CAST int <- uint <- long N013 ( 21, 20) [000747] ------------ \--* RSZ long N011 ( 19, 18) [000745] ------------ +--* MUL long N008 ( 13, 12) [000742] ------------ | +--* ADD long N006 ( 11, 10) [000739] ------------ | | +--* RSZ long N004 ( 9, 8) [000737] ------------ | | | +--* MUL long N001 ( 3, 2) [000735] ------------ | | | | +--* LCL_VAR long V54 tmp40 u:1 (last use) N003 ( 2, 3) [000736] ---------U-- | | | | \--* CAST long <- ulong <- uint N002 ( 1, 1) [000166] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 N005 ( 1, 1) [000738] ------------ | | | \--* CNS_INT int 32 N007 ( 1, 1) [000741] ------------ | | \--* CNS_INT long 1 N010 ( 2, 3) [000744] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000743] ------------ | \--* LCL_VAR int V53 tmp39 u:1 N012 ( 1, 1) [000746] ------------ \--* CNS_INT int 32 ***** BB51 STMT00142 (IL 0x258... ???) N007 ( 33, 11) [000796] -A-X----R--- * ASG bool N006 ( 3, 2) [000795] D------N---- +--* LCL_VAR int V59 tmp45 d:1 N005 ( 29, 8) [000755] ---X-------- \--* EQ int N003 ( 22, 5) [000754] ---X-------- +--* UMOD int N001 ( 1, 1) [000752] ------------ | +--* LCL_VAR int V06 loc2 u:1 N002 ( 1, 1) [000753] ------------ | \--* LCL_VAR int V53 tmp39 u:1 (last use) N004 ( 3, 2) [000751] ------------ \--* LCL_VAR int V55 tmp41 u:1 ***** BB51 STMT00145 (IL 0x258... ???) N004 ( 8, 15) [000806] -A--G---R--- * ASG ref N003 ( 3, 2) [000805] D------N---- +--* LCL_VAR ref V60 tmp46 d:1 N002 ( 4, 12) [000790] #---G------- \--* IND ref N001 ( 2, 10) [000789] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB51 STMT00146 (IL 0x258... ???) N004 ( 8, 15) [000808] -A--G---R--- * ASG ref N003 ( 3, 2) [000807] D------N---- +--* LCL_VAR ref V61 tmp47 d:1 N002 ( 4, 12) [000792] #---G------- \--* IND ref N001 ( 2, 10) [000791] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] ***** BB51 STMT00143 (IL 0x258... ???) N004 ( 7, 6) [000801] ------------ * JTRUE void N003 ( 5, 4) [000800] J------N---- \--* NE int N001 ( 3, 2) [000798] ------------ +--* LCL_VAR int V59 tmp45 u:1 (last use) N002 ( 1, 1) [000799] ------------ \--* CNS_INT int 0 ------------ BB52 [258..259), preds={BB51} succs={BB53} ***** BB52 STMT00144 (IL 0x258... ???) N005 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 3, 2) [000802] ------------ arg0 in rcx +--* LCL_VAR ref V60 tmp46 u:1 (last use) N004 ( 3, 2) [000803] ------------ arg1 in rdx \--* LCL_VAR ref V61 tmp47 u:1 (last use) ------------ BB53 [258..259), preds={BB51,BB52} succs={BB54} ***** BB53 STMT00128 (IL 0x258... ???) N017 ( 35, 33) [000722] -A-XG---R--- * ASG byref N016 ( 3, 2) [000721] D------N---- +--* LCL_VAR byref V51 tmp37 d:1 N015 ( 31, 30) [001112] ---XG------- \--* COMMA byref N004 ( 12, 13) [001105] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 3, 2) [000758] ------------ | +--* LCL_VAR int V55 tmp41 u:1 N003 ( 5, 4) [001104] ---X-------- | \--* ARR_LENGTH int N002 ( 3, 2) [000712] ------------ | \--* LCL_VAR ref V52 tmp38 u:1 N014 ( 19, 17) [001113] ----G------- \--* ADDR byref N013 ( 10, 9) [000719] a---G--N---- \--* IND int N012 ( 9, 8) [001111] -------N---- \--* ADD byref N005 ( 3, 2) [001102] ------------ +--* LCL_VAR ref V52 tmp38 u:1 (last use) N011 ( 6, 6) [001110] -------N---- \--* ADD long N009 ( 5, 5) [001108] -------N---- +--* LSH long N007 ( 4, 4) [001106] ------------ | +--* CAST long <- int N006 ( 3, 2) [001103] i----------- | | \--* LCL_VAR int V55 tmp41 u:1 (last use) N008 ( 1, 1) [001107] -------N---- | \--* CNS_INT long 2 N010 ( 1, 1) [001109] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB53 STMT00034 (IL ???... ???) N003 ( 7, 5) [000170] -A------R--- * ASG byref N002 ( 3, 2) [000169] D------N---- +--* LCL_VAR byref V08 loc4 d:4 N001 ( 3, 2) [000723] ------------ \--* LCL_VAR byref V51 tmp37 u:1 (last use) ------------ BB54 [261..276), preds={BB48,BB53} succs={BB55} ***** BB54 STMT00170 (IL ???... ???) N005 ( 0, 0) [001193] -A------R--- * ASG byref N004 ( 0, 0) [001191] D------N---- +--* LCL_VAR byref V08 loc4 d:3 N003 ( 0, 0) [001192] ------------ \--* PHI byref N001 ( 0, 0) [001224] ------------ pred BB53 +--* PHI_ARG byref V08 loc4 u:4 N002 ( 0, 0) [001220] ------------ pred BB48 \--* PHI_ARG byref V08 loc4 u:1 ***** BB54 STMT00018 (IL 0x261...0x263) N003 ( 7, 5) [000083] -A------R--- * ASG int N002 ( 3, 2) [000082] D------N---- +--* LCL_VAR int V10 loc6 d:2 N001 ( 3, 2) [000081] ------------ \--* LCL_VAR int V13 loc9 u:1 ***** BB54 STMT00019 (IL 0x265...0x26A) N008 ( 10, 9) [000089] -A-XG---R--- * ASG int N007 ( 4, 4) [000088] D--XG--N---- +--* IND int N006 ( 2, 2) [001115] -------N---- | \--* ADD byref N004 ( 1, 1) [000084] ------------ | +--* LCL_VAR ref V00 this u:1 N005 ( 1, 1) [001114] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] N003 ( 5, 4) [000087] ------------ \--* ADD int N001 ( 3, 2) [000085] ------------ +--* LCL_VAR int V13 loc9 u:1 (last use) N002 ( 1, 1) [000086] ------------ \--* CNS_INT int 1 ***** BB54 STMT00020 (IL 0x26F...0x275) N006 ( 4, 4) [000093] -A-XG---R--- * ASG ref N005 ( 1, 1) [000092] D------N---- +--* LCL_VAR ref V04 loc0 d:3 N004 ( 4, 4) [000091] ---XG------- \--* IND ref N003 ( 2, 2) [001117] -------N---- \--* ADD byref N001 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001116] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] ------------ BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} ***** BB55 STMT00171 (IL ???... ???) N005 ( 0, 0) [001196] -A------R--- * ASG byref N004 ( 0, 0) [001194] D------N---- +--* LCL_VAR byref V08 loc4 d:2 N003 ( 0, 0) [001195] ------------ \--* PHI byref N001 ( 0, 0) [001225] ------------ pred BB47 +--* PHI_ARG byref V08 loc4 u:1 N002 ( 0, 0) [001221] ------------ pred BB54 \--* PHI_ARG byref V08 loc4 u:3 ***** BB55 STMT00169 (IL ???... ???) N005 ( 0, 0) [001190] -A------R--- * ASG ref N004 ( 0, 0) [001188] D------N---- +--* LCL_VAR ref V04 loc0 d:2 N003 ( 0, 0) [001189] ------------ \--* PHI ref N001 ( 0, 0) [001226] ------------ pred BB47 +--* PHI_ARG ref V04 loc0 u:1 N002 ( 0, 0) [001222] ------------ pred BB54 \--* PHI_ARG ref V04 loc0 u:3 ***** BB55 STMT00168 (IL ???... ???) N005 ( 0, 0) [001187] -A------R--- * ASG int N004 ( 0, 0) [001185] D------N---- +--* LCL_VAR int V10 loc6 d:1 N003 ( 0, 0) [001186] ------------ \--* PHI int N001 ( 0, 0) [001227] ------------ pred BB47 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [001223] ------------ pred BB54 \--* PHI_ARG int V10 loc6 u:2 ***** BB55 STMT00021 (IL 0x276...0x27E) N019 ( 39, 38) [000099] -A-XG---R--- * ASG byref N018 ( 3, 2) [000098] D------N---- +--* LCL_VAR byref V11 loc7 d:1 N017 ( 35, 35) [001128] ---XG------- \--* COMMA byref N004 ( 10, 12) [001121] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 3, 2) [000095] ------------ | +--* LCL_VAR int V10 loc6 u:1 N003 ( 3, 3) [001120] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000094] ------------ | \--* LCL_VAR ref V04 loc0 u:2 N016 ( 25, 23) [001131] ----G------- \--* ADDR byref N015 ( 13, 12) [000096] a---G--N---- \--* IND struct N014 ( 12, 11) [001127] -------N---- \--* ADD byref N005 ( 1, 1) [001118] ------------ +--* LCL_VAR ref V04 loc0 u:2 N013 ( 11, 10) [001126] -------N---- \--* ADD long N011 ( 10, 9) [001124] -------N---- +--* LSH long N009 ( 9, 8) [001130] ------------ | +--* MUL long N007 ( 4, 4) [001122] ------------ | | +--* CAST long <- int N006 ( 3, 2) [001119] i----------- | | | \--* LCL_VAR int V10 loc6 u:1 N008 ( 1, 1) [001129] ------------ | | \--* CNS_INT long 3 N010 ( 1, 1) [001123] -------N---- | \--* CNS_INT long 3 N012 ( 1, 1) [001125] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] ***** BB55 STMT00022 (IL 0x280...0x283) N006 ( 8, 7) [000103] -A-XG------- * ASG int N004 ( 6, 5) [000102] *--XG--N---- +--* IND int N003 ( 4, 3) [001133] -------N---- | \--* ADD byref N001 ( 3, 2) [000100] ------------ | +--* LCL_VAR byref V11 loc7 u:1 N002 ( 1, 1) [001132] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] N005 ( 1, 1) [000101] ------------ \--* LCL_VAR int V06 loc2 u:1 (last use) ***** BB55 STMT00023 (IL 0x288...0x28F) N009 ( 15, 12) [000110] -A-XG---R--- * ASG int N008 ( 6, 5) [000109] *--XG--N---- +--* IND int N007 ( 4, 3) [001135] -------N---- | \--* ADD byref N005 ( 3, 2) [000104] ------------ | +--* LCL_VAR byref V11 loc7 u:1 N006 ( 1, 1) [001134] ------------ | \--* CNS_INT long 20 field offset Fseq[next] N004 ( 8, 6) [000108] ---XG------- \--* ADD int N002 ( 6, 4) [000106] *--XG------- +--* IND int N001 ( 3, 2) [000105] ------------ | \--* LCL_VAR byref V08 loc4 u:2 N003 ( 1, 1) [000107] ------------ \--* CNS_INT int -1 ***** BB55 STMT00024 (IL 0x294...0x297) N004 ( 8, 6) [000114] -A-XG------- * ASG ref N002 ( 6, 4) [000113] *--XG--N---- +--* IND ref N001 ( 3, 2) [000111] ------------ | \--* LCL_VAR byref V11 loc7 u:1 Zero Fseq[key] N003 ( 1, 1) [000112] ------------ \--* LCL_VAR ref V01 arg1 u:1 (last use) ***** BB55 STMT00025 (IL 0x29C...0x29F) N006 ( 8, 7) [000118] -A-XG------- * ASG ref N004 ( 6, 5) [000117] *--XG--N---- +--* IND ref N003 ( 4, 3) [001137] -------N---- | \--* ADD byref N001 ( 3, 2) [000115] ------------ | +--* LCL_VAR byref V11 loc7 u:1 (last use) N002 ( 1, 1) [001136] ------------ | \--* CNS_INT long 8 field offset Fseq[value] N005 ( 1, 1) [000116] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) ***** BB55 STMT00026 (IL 0x2A4...0x2AA) N006 ( 12, 9) [000124] -A-XG---R--- * ASG int N005 ( 6, 4) [000123] *--X---N---- +--* IND int N004 ( 3, 2) [000119] ------------ | \--* LCL_VAR byref V08 loc4 u:2 (last use) N003 ( 5, 4) [000122] ------------ \--* ADD int N001 ( 3, 2) [000120] ------------ +--* LCL_VAR int V10 loc6 u:1 (last use) N002 ( 1, 1) [000121] ------------ \--* CNS_INT int 1 ***** BB55 STMT00027 (IL 0x2AB...0x2B4) N011 ( 11, 11) [000131] -A-XG---R--- * ASG int N010 ( 4, 4) [000130] D--XG--N---- +--* IND int N009 ( 2, 2) [001139] -------N---- | \--* ADD byref N007 ( 1, 1) [000125] ------------ | +--* LCL_VAR ref V00 this u:1 N008 ( 1, 1) [001138] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] N006 ( 6, 6) [000129] ---XG------- \--* ADD int N004 ( 4, 4) [000127] ---XG------- +--* IND int N003 ( 2, 2) [001141] -------N---- | \--* ADD byref N001 ( 1, 1) [000126] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001140] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] N005 ( 1, 1) [000128] ------------ \--* CNS_INT int 1 ***** BB55 STMT00028 (IL 0x2CA...0x2CD) N004 ( 5, 5) [000148] ------------ * JTRUE void N003 ( 3, 3) [000147] N------N-U-- \--* LE int N001 ( 1, 1) [000145] ------------ +--* LCL_VAR int V07 loc3 u:2 (last use) N002 ( 1, 1) [000146] ------------ \--* CNS_INT int 100 ------------ BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} ***** BB56 STMT00030 (IL 0x2CF...0x2D5) N008 ( 21, 22) [000156] --C-G------- * JTRUE void N007 ( 19, 20) [000155] J-C-G--N---- \--* EQ int N005 ( 17, 18) [000153] --C-G------- +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS N003 ( 1, 1) [000151] ------------ arg1 in rdx | +--* LCL_VAR ref V05 loc1 u:1 (last use) N004 ( 2, 10) [000152] H------N---- arg0 in rcx | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 1, 1) [000154] ------------ \--* CNS_INT ref null ------------ BB57 [2D7..2E3), preds={BB56} succs={BB58} ***** BB57 STMT00031 (IL 0x2D7...0x2DC) N008 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize N005 ( 3, 3) [000159] ---X-------- arg1 in rdx +--* ARR_LENGTH int N004 ( 1, 1) [000158] ------------ | \--* LCL_VAR ref V04 loc0 u:2 (last use) N006 ( 1, 1) [000157] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 N007 ( 1, 1) [000160] ------------ arg2 in r8 \--* CNS_INT int 1 ------------ BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} ***** BB58 STMT00147 (IL ???... ???) N002 ( 2, 2) [000810] ------------ * RETURN int N001 ( 1, 1) [000482] ------------ \--* CNS_INT int 1 ------------ BB59 [008..00E) (throw), preds={BB01} succs={} ***** BB59 STMT00086 (IL 0x008...0x009) N003 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException N002 ( 1, 1) [000532] ------------ arg0 in rcx \--* CNS_INT int 4 ------------ BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} ***** BB60 STMT00073 (IL 0x14F...0x150) N004 ( 7, 5) [000444] -A-X----R--- * ASG long N003 ( 3, 2) [000443] D------N---- +--* LCL_VAR long V26 tmp12 d:1 N002 ( 3, 2) [000442] #--X-------- \--* IND long N001 ( 1, 1) [000441] !----------- \--* LCL_VAR ref V00 this u:1 ***** BB60 STMT00155 (IL ???... ???) N011 ( 16, 14) [001158] ------------ * JTRUE void N010 ( 14, 12) [000460] J------N---- \--* EQ int N008 ( 12, 10) [000456] n----------- +--* IND long N007 ( 10, 8) [000452] -------N---- | \--* ADD long N005 ( 9, 7) [000450] #----------- | +--* IND long N004 ( 6, 5) [000449] #----------- | | \--* IND long N003 ( 4, 3) [000448] -------N---- | | \--* ADD long N001 ( 3, 2) [000446] ------------ | | +--* LCL_VAR long V26 tmp12 u:1 N002 ( 1, 1) [000447] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000451] ------------ | \--* CNS_INT long 56 N009 ( 1, 1) [000459] ------------ \--* CNS_INT long 0 ------------ BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} ***** BB61 STMT00156 (IL ???... ???) N010 ( 16, 13) [001160] -A------R--- * ASG long N009 ( 3, 2) [001159] D------N---- +--* LCL_VAR long V28 tmp14 d:3 N008 ( 12, 10) [000461] n-----?----- \--* IND long N007 ( 10, 8) [000462] ------?N---- \--* ADD long N005 ( 9, 7) [000463] #-----?----- +--* IND long N004 ( 6, 5) [000464] #-----?----- | \--* IND long N003 ( 4, 3) [000465] ------?N---- | \--* ADD long N001 ( 3, 2) [000466] ------?----- | +--* LCL_VAR long V26 tmp12 u:1 (last use) N002 ( 1, 1) [000467] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000468] ------?----- \--* CNS_INT long 56 ------------ BB62 [???..???), preds={BB60} succs={BB63} ***** BB62 STMT00157 (IL ???... ???) N007 ( 23, 22) [001162] -AC-G---R--- * ASG long N006 ( 3, 2) [001161] D------N---- +--* LCL_VAR long V28 tmp14 d:2 N005 ( 19, 19) [000458] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 3, 2) [000445] ------?----- arg0 in rcx +--* LCL_VAR long V26 tmp12 u:1 (last use) N004 ( 2, 10) [000457] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB63 [???..157) (throw), preds={BB61,BB62} succs={} ***** BB63 STMT00167 (IL ???... ???) N005 ( 0, 0) [001184] -A------R--- * ASG long N004 ( 0, 0) [001182] D------N---- +--* LCL_VAR long V28 tmp14 d:1 N003 ( 0, 0) [001183] ------------ \--* PHI long N001 ( 0, 0) [001241] ------------ pred BB61 +--* PHI_ARG long V28 tmp14 u:3 N002 ( 0, 0) [001240] ------------ pred BB62 \--* PHI_ARG long V28 tmp14 u:2 ***** BB63 STMT00076 (IL ???... ???) N005 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException N003 ( 3, 2) [000473] ------------ arg0 in rcx +--* LCL_VAR long V28 tmp14 u:1 (last use) N004 ( 1, 1) [000455] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) ------------ BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} ***** BB64 STMT00053 (IL 0x1BC...0x1BD) N004 ( 7, 5) [000299] -A-X----R--- * ASG long N003 ( 3, 2) [000298] D------N---- +--* LCL_VAR long V21 tmp7 d:1 N002 ( 3, 2) [000297] #--X-------- \--* IND long N001 ( 1, 1) [000296] !----------- \--* LCL_VAR ref V00 this u:1 ***** BB64 STMT00161 (IL ???... ???) N011 ( 16, 14) [001168] ------------ * JTRUE void N010 ( 14, 12) [000315] J------N---- \--* EQ int N008 ( 12, 10) [000311] n----------- +--* IND long N007 ( 10, 8) [000307] -------N---- | \--* ADD long N005 ( 9, 7) [000305] #----------- | +--* IND long N004 ( 6, 5) [000304] #----------- | | \--* IND long N003 ( 4, 3) [000303] -------N---- | | \--* ADD long N001 ( 3, 2) [000301] ------------ | | +--* LCL_VAR long V21 tmp7 u:1 N002 ( 1, 1) [000302] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000306] ------------ | \--* CNS_INT long 56 N009 ( 1, 1) [000314] ------------ \--* CNS_INT long 0 ------------ BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} ***** BB65 STMT00162 (IL ???... ???) N010 ( 16, 13) [001170] -A------R--- * ASG long N009 ( 3, 2) [001169] D------N---- +--* LCL_VAR long V23 tmp9 d:3 N008 ( 12, 10) [000316] n-----?----- \--* IND long N007 ( 10, 8) [000317] ------?N---- \--* ADD long N005 ( 9, 7) [000318] #-----?----- +--* IND long N004 ( 6, 5) [000319] #-----?----- | \--* IND long N003 ( 4, 3) [000320] ------?N---- | \--* ADD long N001 ( 3, 2) [000321] ------?----- | +--* LCL_VAR long V21 tmp7 u:1 (last use) N002 ( 1, 1) [000322] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000323] ------?----- \--* CNS_INT long 56 ------------ BB66 [???..???), preds={BB64} succs={BB67} ***** BB66 STMT00163 (IL ???... ???) N007 ( 23, 22) [001172] -AC-G---R--- * ASG long N006 ( 3, 2) [001171] D------N---- +--* LCL_VAR long V23 tmp9 d:2 N005 ( 19, 19) [000313] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 3, 2) [000300] ------?----- arg0 in rcx +--* LCL_VAR long V21 tmp7 u:1 (last use) N004 ( 2, 10) [000312] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr ------------ BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} ***** BB67 STMT00173 (IL ???... ???) N005 ( 0, 0) [001202] -A------R--- * ASG long N004 ( 0, 0) [001200] D------N---- +--* LCL_VAR long V23 tmp9 d:1 N003 ( 0, 0) [001201] ------------ \--* PHI long N001 ( 0, 0) [001232] ------------ pred BB65 +--* PHI_ARG long V23 tmp9 u:3 N002 ( 0, 0) [001231] ------------ pred BB66 \--* PHI_ARG long V23 tmp9 u:2 ***** BB67 STMT00056 (IL ???... ???) N005 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException N003 ( 3, 2) [000328] ------------ arg0 in rcx +--* LCL_VAR long V23 tmp9 u:1 (last use) N004 ( 1, 1) [000310] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) ------------ BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} ***** BB68 STMT00043 (IL 0x1DD...0x1E2) N001 ( 14, 5) [000233] --CXG------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported ------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Early Value Propagation *************** Starting PHASE Do value numbering *************** In fgValueNumber() optComputeLoopSideEffects botNext is BB28, lnum is 0 optComputeLoopSideEffectsOfBlock BB23, mostNestedLoop 0 optComputeLoopSideEffectsOfBlock BB24, mostNestedLoop 0 optComputeLoopSideEffectsOfBlock BB25, mostNestedLoop 0 Removing LOOP_ALIGN flag for L00 that starts at BB23 because loop has a call. optComputeLoopSideEffectsOfBlock BB26, mostNestedLoop 0 optComputeLoopSideEffectsOfBlock BB27, mostNestedLoop 0 Memory Initial Value in BB01 is: $103 The SSA definition for ByrefExposed (#1) at start of BB01 is $103 {InitVal($c4)} The SSA definition for GcHeap (#1) at start of BB01 is $103 {InitVal($c4)} ***** BB01, STMT00000(before) N004 ( 5, 5) [000003] ------------ * JTRUE void N003 ( 3, 3) [000002] J------N---- \--* EQ int N001 ( 1, 1) [000000] ------------ +--* LCL_VAR ref V01 arg1 u:1 N002 ( 1, 1) [000001] ------------ \--* CNS_INT ref null N001 [000000] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} N002 [000001] CNS_INT null => $VN.Null N003 [000002] EQ => $180 {EQ($101, $0)} ***** BB01, STMT00000(after) N004 ( 5, 5) [000003] ------------ * JTRUE void N003 ( 3, 3) [000002] J------N---- \--* EQ int $180 N001 ( 1, 1) [000000] ------------ +--* LCL_VAR ref V01 arg1 u:1 $101 N002 ( 1, 1) [000001] ------------ \--* CNS_INT ref null $VN.Null finish(BB01). Succ(BB02). Not yet completed. All preds complete, adding to allDone. Succ(BB59). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#1) at start of BB59 is $103 {InitVal($c4)} The SSA definition for GcHeap (#1) at start of BB59 is $103 {InitVal($c4)} ***** BB59, STMT00086(before) N003 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException N002 ( 1, 1) [000532] ------------ arg0 in rcx \--* CNS_INT int 4 N001 [000812] ARGPLACE => $1c0 {1c0} N002 [000532] CNS_INT 4 => $c5 {IntCns 4} VN of ARGPLACE tree [000812] updated to $c5 {IntCns 4} fgCurMemoryVN[GcHeap] assigned for CALL at [000533] to VN: $200. N003 [000533] CALL => $VN.Void ***** BB59, STMT00086(after) N003 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException $VN.Void N002 ( 1, 1) [000532] ------------ arg0 in rcx \--* CNS_INT int 4 $c5 finish(BB59). The SSA definition for ByrefExposed (#1) at start of BB02 is $103 {InitVal($c4)} The SSA definition for GcHeap (#1) at start of BB02 is $103 {InitVal($c4)} ***** BB02, STMT00001(before) N007 ( 8, 8) [000008] ---XG------- * JTRUE void N006 ( 6, 6) [000007] J--XG--N---- \--* NE int N004 ( 4, 4) [000005] ---XG------- +--* IND ref N003 ( 2, 2) [000814] -------N---- | \--* ADD byref N001 ( 1, 1) [000004] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000813] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] N005 ( 1, 1) [000006] ------------ \--* CNS_INT ref null N001 [000004] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N002 [000813] CNS_INT 8 field offset Fseq[_buckets] => $240 {LngCns: 8} N003 [000814] ADD => $280 {ADD($100, $240)} VNApplySelectors: VNForHandle(_buckets) is $41, fieldType is ref VNForMapSelect($103, $41):ref returns $2c0 {$103[$41]} VNForMapSelect($2c0, $100):ref returns $2c1 {$2c0[$100]} N004 [000005] IND => N005 [000006] CNS_INT null => $VN.Null N006 [000007] NE => ***** BB02, STMT00001(after) N007 ( 8, 8) [000008] ---XG------- * JTRUE void N006 ( 6, 6) [000007] J--XG--N---- \--* NE int N004 ( 4, 4) [000005] ---XG------- +--* IND ref N003 ( 2, 2) [000814] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000004] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000813] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] $240 N005 ( 1, 1) [000006] ------------ \--* CNS_INT ref null $VN.Null finish(BB02). Succ(BB03). Not yet completed. All preds complete, adding to allDone. Succ(BB04). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#1) at start of BB03 is $103 {InitVal($c4)} The SSA definition for GcHeap (#1) at start of BB03 is $103 {InitVal($c4)} ***** BB03, STMT00085(before) N005 ( 16, 10) [000528] --CXG------- * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize N003 ( 1, 1) [000526] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 N004 ( 1, 1) [000527] ------------ arg1 in rdx \--* CNS_INT int 0 N001 [000815] ARGPLACE => $202 {202} N002 [000816] ARGPLACE => $1c1 {1c1} N003 [000526] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N004 [000527] CNS_INT 0 => $c0 {IntCns 0} VN of ARGPLACE tree [000816] updated to $100 {InitVal($c0)} fgCurMemoryVN[GcHeap] assigned for CALL at [000528] to VN: $203. N005 [000528] CALL => $1c2 {1c2} ***** BB03, STMT00085(after) N005 ( 16, 10) [000528] --CXG------- * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize $1c2 N003 ( 1, 1) [000526] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N004 ( 1, 1) [000527] ------------ arg1 in rdx \--* CNS_INT int 0 $c0 finish(BB03). Succ(BB04). Not yet completed. All preds complete, adding to allDone. Building phi application: $c6 = SSA# 42. Building phi application: $c1 = SSA# 1. Building phi application: $2c5 = phi($c1, $c6). The SSA definition for GcHeap (#3) at start of BB04 is $2c6 {PhiMemoryDef($42, $2c5)} ***** BB04, STMT00088(before) N008 ( 9, 6) [000544] -A-XG---R--- * ASG bool N007 ( 1, 1) [000543] D------N---- +--* LCL_VAR int V33 tmp19 d:1 N006 ( 9, 6) [000012] N--XG------- \--* NE int N004 ( 4, 4) [000010] ---XG------- +--* IND ref N003 ( 2, 2) [000818] -------N---- | \--* ADD byref N001 ( 1, 1) [000009] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000817] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] N005 ( 1, 1) [000011] ------------ \--* CNS_INT ref null N001 [000009] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N002 [000817] CNS_INT 8 field offset Fseq[_buckets] => $240 {LngCns: 8} N003 [000818] ADD => $280 {ADD($100, $240)} VNApplySelectors: VNForHandle(_buckets) is $41, fieldType is ref VNForMapSelect($2c6, $41):ref returns $2c8 {$2c6[$41]} VNForMapSelect($2c8, $100):ref returns $2c9 {$2c8[$100]} N004 [000010] IND => N005 [000011] CNS_INT null => $VN.Null N006 [000012] NE => N007 [000543] LCL_VAR V33 tmp19 d:1 => N008 [000544] ASG => ***** BB04, STMT00088(after) N008 ( 9, 6) [000544] -A-XG---R--- * ASG bool N007 ( 1, 1) [000543] D------N---- +--* LCL_VAR int V33 tmp19 d:1 N006 ( 9, 6) [000012] N--XG------- \--* NE int N004 ( 4, 4) [000010] ---XG------- +--* IND ref N003 ( 2, 2) [000818] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000009] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000817] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] $240 N005 ( 1, 1) [000011] ------------ \--* CNS_INT ref null $VN.Null --------- ***** BB04, STMT00091(before) N004 ( 4, 12) [000554] -A--G---R--- * ASG ref N003 ( 1, 1) [000553] D------N---- +--* LCL_VAR ref V34 tmp20 d:1 N002 ( 4, 12) [000538] #---G------- \--* IND ref N001 ( 2, 10) [000537] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] N001 [000537] CNS_INT(h) 0xD1FFAB1E [ICON_STR_HDL] => $43 {Hnd const: 0x00000000D1FFAB1E} N002 [000538] IND => $105 {NonNullIndirect($43)} N003 [000553] LCL_VAR V34 tmp20 d:1 => $105 {NonNullIndirect($43)} N004 [000554] ASG => $105 {NonNullIndirect($43)} ***** BB04, STMT00091(after) N004 ( 4, 12) [000554] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000553] D------N---- +--* LCL_VAR ref V34 tmp20 d:1 $105 N002 ( 4, 12) [000538] #---G------- \--* IND ref $105 N001 ( 2, 10) [000537] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 --------- ***** BB04, STMT00092(before) N004 ( 4, 12) [000556] -A--G---R--- * ASG ref N003 ( 1, 1) [000555] D------N---- +--* LCL_VAR ref V35 tmp21 d:1 N002 ( 4, 12) [000540] #---G------- \--* IND ref N001 ( 2, 10) [000539] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] N001 [000539] CNS_INT(h) 0xD1FFAB1E [ICON_STR_HDL] => $43 {Hnd const: 0x00000000D1FFAB1E} N002 [000540] IND => $105 {NonNullIndirect($43)} N003 [000555] LCL_VAR V35 tmp21 d:1 => $105 {NonNullIndirect($43)} N004 [000556] ASG => $105 {NonNullIndirect($43)} ***** BB04, STMT00092(after) N004 ( 4, 12) [000556] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000555] D------N---- +--* LCL_VAR ref V35 tmp21 d:1 $105 N002 ( 4, 12) [000540] #---G------- \--* IND ref $105 N001 ( 2, 10) [000539] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 --------- ***** BB04, STMT00089(before) N004 ( 5, 5) [000549] ------------ * JTRUE void N003 ( 3, 3) [000548] J------N---- \--* NE int N001 ( 1, 1) [000546] ------------ +--* LCL_VAR int V33 tmp19 u:1 (last use) N002 ( 1, 1) [000547] ------------ \--* CNS_INT int 0 N001 [000546] LCL_VAR V33 tmp19 u:1 (last use) => N002 [000547] CNS_INT 0 => $c0 {IntCns 0} N003 [000548] NE => ***** BB04, STMT00089(after) N004 ( 5, 5) [000549] ------------ * JTRUE void N003 ( 3, 3) [000548] J------N---- \--* NE int N001 ( 1, 1) [000546] ------------ +--* LCL_VAR int V33 tmp19 u:1 (last use) N002 ( 1, 1) [000547] ------------ \--* CNS_INT int 0 $c0 finish(BB04). Succ(BB05). Not yet completed. All preds complete, adding to allDone. Succ(BB06). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#3) at start of BB05 is $2c6 {PhiMemoryDef($42, $2c5)} The SSA definition for GcHeap (#3) at start of BB05 is $2c6 {PhiMemoryDef($42, $2c5)} ***** BB05, STMT00090(before) N005 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 1, 1) [000550] ------------ arg0 in rcx +--* LCL_VAR ref V34 tmp20 u:1 (last use) N004 ( 1, 1) [000551] ------------ arg1 in rdx \--* LCL_VAR ref V35 tmp21 u:1 (last use) N001 [000819] ARGPLACE => $207 {207} N002 [000820] ARGPLACE => $208 {208} N003 [000550] LCL_VAR V34 tmp20 u:1 (last use) => $105 {NonNullIndirect($43)} N004 [000551] LCL_VAR V35 tmp21 u:1 (last use) => $105 {NonNullIndirect($43)} VN of ARGPLACE tree [000819] updated to $105 {NonNullIndirect($43)} VN of ARGPLACE tree [000820] updated to $105 {NonNullIndirect($43)} fgCurMemoryVN[GcHeap] assigned for CALL at [000552] to VN: $209. N005 [000552] CALL => $VN.Void ***** BB05, STMT00090(after) N005 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 1, 1) [000550] ------------ arg0 in rcx +--* LCL_VAR ref V34 tmp20 u:1 (last use) $105 N004 ( 1, 1) [000551] ------------ arg1 in rdx \--* LCL_VAR ref V35 tmp21 u:1 (last use) $105 finish(BB05). Succ(BB06). Not yet completed. All preds complete, adding to allDone. Building phi application: $c7 = SSA# 41. Building phi application: $c3 = SSA# 3. Building phi application: $2cc = phi($c3, $c7). The SSA definition for GcHeap (#4) at start of BB06 is $2cd {PhiMemoryDef($44, $2cc)} ***** BB06, STMT00003(before) N006 ( 4, 4) [000018] -A-XG---R--- * ASG ref N005 ( 1, 1) [000017] D------N---- +--* LCL_VAR ref V04 loc0 d:1 N004 ( 4, 4) [000016] ---XG------- \--* IND ref N003 ( 2, 2) [000822] -------N---- \--* ADD byref N001 ( 1, 1) [000015] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000821] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] N001 [000015] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N002 [000821] CNS_INT 16 field offset Fseq[_entries] => $241 {LngCns: 16} N003 [000822] ADD => $281 {ADD($100, $241)} VNApplySelectors: VNForHandle(_entries) is $45, fieldType is ref VNForMapSelect($2cd, $45):ref returns $2d2 {$2cd[$45]} VNForMapSelect($2d2, $100):ref returns $2d3 {$2d2[$100]} N004 [000016] IND => N005 [000017] LCL_VAR V04 loc0 d:1 => N006 [000018] ASG => ***** BB06, STMT00003(after) N006 ( 4, 4) [000018] -A-XG---R--- * ASG ref N005 ( 1, 1) [000017] D------N---- +--* LCL_VAR ref V04 loc0 d:1 N004 ( 4, 4) [000016] ---XG------- \--* IND ref N003 ( 2, 2) [000822] -------N---- \--* ADD byref $281 N001 ( 1, 1) [000015] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000821] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] $241 --------- ***** BB06, STMT00094(before) N005 ( 6, 3) [000566] -A------R--- * ASG bool N004 ( 1, 1) [000565] D------N---- +--* LCL_VAR int V36 tmp22 d:1 N003 ( 6, 3) [000021] N----------- \--* NE int N001 ( 1, 1) [000019] ------------ +--* LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000020] ------------ \--* CNS_INT ref null N001 [000019] LCL_VAR V04 loc0 u:1 => N002 [000020] CNS_INT null => $VN.Null N003 [000021] NE => N004 [000565] LCL_VAR V36 tmp22 d:1 => N005 [000566] ASG => ***** BB06, STMT00094(after) N005 ( 6, 3) [000566] -A------R--- * ASG bool N004 ( 1, 1) [000565] D------N---- +--* LCL_VAR int V36 tmp22 d:1 N003 ( 6, 3) [000021] N----------- \--* NE int N001 ( 1, 1) [000019] ------------ +--* LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000020] ------------ \--* CNS_INT ref null $VN.Null --------- ***** BB06, STMT00097(before) N004 ( 4, 12) [000576] -A--G---R--- * ASG ref N003 ( 1, 1) [000575] D------N---- +--* LCL_VAR ref V37 tmp23 d:1 N002 ( 4, 12) [000562] #---G------- \--* IND ref N001 ( 2, 10) [000561] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] N001 [000561] CNS_INT(h) 0xD1FFAB1E [ICON_STR_HDL] => $43 {Hnd const: 0x00000000D1FFAB1E} N002 [000562] IND => $105 {NonNullIndirect($43)} N003 [000575] LCL_VAR V37 tmp23 d:1 => $105 {NonNullIndirect($43)} N004 [000576] ASG => $105 {NonNullIndirect($43)} ***** BB06, STMT00097(after) N004 ( 4, 12) [000576] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000575] D------N---- +--* LCL_VAR ref V37 tmp23 d:1 $105 N002 ( 4, 12) [000562] #---G------- \--* IND ref $105 N001 ( 2, 10) [000561] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 --------- ***** BB06, STMT00095(before) N004 ( 5, 5) [000571] ------------ * JTRUE void N003 ( 3, 3) [000570] J------N---- \--* NE int N001 ( 1, 1) [000568] ------------ +--* LCL_VAR int V36 tmp22 u:1 (last use) N002 ( 1, 1) [000569] ------------ \--* CNS_INT int 0 N001 [000568] LCL_VAR V36 tmp22 u:1 (last use) => N002 [000569] CNS_INT 0 => $c0 {IntCns 0} N003 [000570] NE => ***** BB06, STMT00095(after) N004 ( 5, 5) [000571] ------------ * JTRUE void N003 ( 3, 3) [000570] J------N---- \--* NE int N001 ( 1, 1) [000568] ------------ +--* LCL_VAR int V36 tmp22 u:1 (last use) N002 ( 1, 1) [000569] ------------ \--* CNS_INT int 0 $c0 finish(BB06). Succ(BB07). Not yet completed. All preds complete, adding to allDone. Succ(BB08). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#4) at start of BB07 is $2cd {PhiMemoryDef($44, $2cc)} The SSA definition for GcHeap (#4) at start of BB07 is $2cd {PhiMemoryDef($44, $2cc)} ***** BB07, STMT00096(before) N006 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail N004 ( 4, 12) [000824] #---G------- arg0 in rcx +--* IND ref N003 ( 2, 10) [000823] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" N005 ( 1, 1) [000573] ------------ arg1 in rdx \--* LCL_VAR ref V37 tmp23 u:1 (last use) N001 [000825] ARGPLACE => $20d {20d} N002 [000826] ARGPLACE => $20e {20e} N003 [000823] CNS_INT(h) 0xD1FFAB1E "expected entries to be non-null" => $46 {Hnd const: 0x00000000D1FFAB1E} N004 [000824] IND => $106 {NonNullIndirect($46)} N005 [000573] LCL_VAR V37 tmp23 u:1 (last use) => $105 {NonNullIndirect($43)} VN of ARGPLACE tree [000825] updated to $106 {NonNullIndirect($46)} VN of ARGPLACE tree [000826] updated to $105 {NonNullIndirect($43)} fgCurMemoryVN[GcHeap] assigned for CALL at [000574] to VN: $20f. N006 [000574] CALL => $VN.Void ***** BB07, STMT00096(after) N006 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N004 ( 4, 12) [000824] #---G------- arg0 in rcx +--* IND ref $106 N003 ( 2, 10) [000823] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" $46 N005 ( 1, 1) [000573] ------------ arg1 in rdx \--* LCL_VAR ref V37 tmp23 u:1 (last use) $105 finish(BB07). Succ(BB08). Not yet completed. All preds complete, adding to allDone. Building phi application: $c8 = SSA# 40. Building phi application: $c5 = SSA# 4. Building phi application: $2d6 = phi($c5, $c8). The SSA definition for GcHeap (#5) at start of BB08 is $2d7 {PhiMemoryDef($47, $2d6)} ***** BB08, STMT00005(before) N006 ( 4, 4) [000028] -A-XG---R--- * ASG ref N005 ( 1, 1) [000027] D------N---- +--* LCL_VAR ref V05 loc1 d:1 N004 ( 4, 4) [000026] ---XG------- \--* IND ref N003 ( 2, 2) [000828] -------N---- \--* ADD byref N001 ( 1, 1) [000025] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000827] ------------ \--* CNS_INT long 24 field offset Fseq[_comparer] N001 [000025] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N002 [000827] CNS_INT 24 field offset Fseq[_comparer] => $242 {LngCns: 24} N003 [000828] ADD => $282 {ADD($100, $242)} VNApplySelectors: VNForHandle(_comparer) is $48, fieldType is ref VNForMapSelect($2d7, $48):ref returns $2de {$2d7[$48]} VNForMapSelect($2de, $100):ref returns $2df {$2de[$100]} N004 [000026] IND => N005 [000027] LCL_VAR V05 loc1 d:1 => N006 [000028] ASG => ***** BB08, STMT00005(after) N006 ( 4, 4) [000028] -A-XG---R--- * ASG ref N005 ( 1, 1) [000027] D------N---- +--* LCL_VAR ref V05 loc1 d:1 N004 ( 4, 4) [000026] ---XG------- \--* IND ref N003 ( 2, 2) [000828] -------N---- \--* ADD byref $282 N001 ( 1, 1) [000025] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000827] ------------ \--* CNS_INT long 24 field offset Fseq[_comparer] $242 --------- ***** BB08, STMT00006(before) N004 ( 5, 5) [000032] ------------ * JTRUE void N003 ( 3, 3) [000031] J------N---- \--* EQ int N001 ( 1, 1) [000029] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000030] ------------ \--* CNS_INT ref null N001 [000029] LCL_VAR V05 loc1 u:1 => N002 [000030] CNS_INT null => $VN.Null N003 [000031] EQ => ***** BB08, STMT00006(after) N004 ( 5, 5) [000032] ------------ * JTRUE void N003 ( 3, 3) [000031] J------N---- \--* EQ int N001 ( 1, 1) [000029] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000030] ------------ \--* CNS_INT ref null $VN.Null finish(BB08). Succ(BB09). Not yet completed. All preds complete, adding to allDone. Succ(BB13). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#5) at start of BB13 is $2d7 {PhiMemoryDef($47, $2d6)} The SSA definition for GcHeap (#5) at start of BB13 is $2d7 {PhiMemoryDef($47, $2d6)} ***** BB13, STMT00007(before) N013 ( 34, 21) [000038] -ACXG---R--- * ASG int N012 ( 3, 2) [000037] D------N---- +--* LCL_VAR int V15 tmp1 d:2 N011 ( 30, 18) [000035] --CXG------- \--* CALLV vt-ind int System.Object.GetHashCode N010 ( 9, 8) [000843] n--X-------- control expr \--* IND long N009 ( 7, 6) [000842] ---X---N---- \--* ADD long N007 ( 6, 5) [000840] #--X-------- +--* IND long N006 ( 4, 3) [000839] ---X---N---- | \--* ADD long N004 ( 3, 2) [000837] #--X-------- | +--* IND long N003 ( 1, 1) [000836] ------------ | | \--* LCL_VAR ref V01 arg1 u:1 N005 ( 1, 1) [000838] ------------ | \--* CNS_INT int 72 N008 ( 1, 1) [000841] ------------ \--* CNS_INT int 24 N002 ( 1, 1) [000033] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 N001 [000835] ARGPLACE => $212 {212} N002 [000033] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} N003 [000836] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} VNForMapSelect($2, $101):ref returns $2e2 {$VN.ReadOnlyHeap[$101]} VNForMapSelect($2, $101):ref returns $2e2 {$VN.ReadOnlyHeap[$101]} N004 [000837] IND => $2e4 {norm=$2e2 {$VN.ReadOnlyHeap[$101]}, exc=$2e3 {NullPtrExc($101)}} N005 [000838] CNS_INT 72 => $c9 {IntCns 72} N006 [000839] ADD => $301 {norm=$300 {ADD($c9, $2e2)}, exc=$2e3 {NullPtrExc($101)}} VNForMapSelect($2, $300):ref returns $2e5 {$VN.ReadOnlyHeap[$300]} VNForMapSelect($2, $300):ref returns $2e5 {$VN.ReadOnlyHeap[$300]} N007 [000840] IND => $2e6 {norm=$2e5 {$VN.ReadOnlyHeap[$300]}, exc=$2e3 {NullPtrExc($101)}} N008 [000841] CNS_INT 24 => $ca {IntCns 24} N009 [000842] ADD => $303 {norm=$302 {ADD($ca, $2e5)}, exc=$2e3 {NullPtrExc($101)}} N010 [000843] IND => fgCurMemoryVN[GcHeap] assigned for CALL at [000035] to VN: $213. N011 [000035] CALLV vt-ind => $1c5 {1c5} N012 [000037] LCL_VAR V15 tmp1 d:2 => $1c5 {1c5} N013 [000038] ASG => $1c5 {1c5} ***** BB13, STMT00007(after) N013 ( 34, 21) [000038] -ACXG---R--- * ASG int $1c5 N012 ( 3, 2) [000037] D------N---- +--* LCL_VAR int V15 tmp1 d:2 $1c5 N011 ( 30, 18) [000035] --CXG------- \--* CALLV vt-ind int System.Object.GetHashCode $1c5 N010 ( 9, 8) [000843] n--X-------- control expr \--* IND long N009 ( 7, 6) [000842] ---X---N---- \--* ADD long $303 N007 ( 6, 5) [000840] #--X-------- +--* IND long $2e6 N006 ( 4, 3) [000839] ---X---N---- | \--* ADD long $301 N004 ( 3, 2) [000837] #--X-------- | +--* IND long $2e4 N003 ( 1, 1) [000836] ------------ | | \--* LCL_VAR ref V01 arg1 u:1 $101 N005 ( 1, 1) [000838] ------------ | \--* CNS_INT int 72 $c9 N008 ( 1, 1) [000841] ------------ \--* CNS_INT int 24 $ca N002 ( 1, 1) [000033] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 $101 finish(BB13). Succ(BB14). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#5) at start of BB09 is $2d7 {PhiMemoryDef($47, $2d6)} The SSA definition for GcHeap (#5) at start of BB09 is $2d7 {PhiMemoryDef($47, $2d6)} ***** BB09, STMT00079(before) N004 ( 3, 3) [000489] -A-X----R--- * ASG long N003 ( 1, 1) [000488] D------N---- +--* LCL_VAR long V29 tmp15 d:1 N002 ( 3, 2) [000487] #--X-------- \--* IND long N001 ( 1, 1) [000486] !----------- \--* LCL_VAR ref V00 this u:1 N001 [000486] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} VNForMapSelect($2, $100):ref returns $2e7 {$VN.ReadOnlyHeap[$100]} VNForMapSelect($2, $100):ref returns $2e7 {$VN.ReadOnlyHeap[$100]} N002 [000487] IND => $2e8 {norm=$2e7 {$VN.ReadOnlyHeap[$100]}, exc=$2c2 {NullPtrExc($100)}} N003 [000488] LCL_VAR V29 tmp15 d:1 => $2e7 {$VN.ReadOnlyHeap[$100]} N004 [000489] ASG => $2e8 {norm=$2e7 {$VN.ReadOnlyHeap[$100]}, exc=$2c2 {NullPtrExc($100)}} ***** BB09, STMT00079(after) N004 ( 3, 3) [000489] -A-X----R--- * ASG long $2e8 N003 ( 1, 1) [000488] D------N---- +--* LCL_VAR long V29 tmp15 d:1 $2e7 N002 ( 3, 2) [000487] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000486] !----------- \--* LCL_VAR ref V00 this u:1 $100 --------- ***** BB09, STMT00149(before) N011 ( 14, 13) [001148] ------------ * JTRUE void N010 ( 12, 11) [000505] J------N---- \--* EQ int N008 ( 10, 9) [000501] n----------- +--* IND long N007 ( 8, 7) [000497] -------N---- | \--* ADD long N005 ( 7, 6) [000495] #----------- | +--* IND long N004 ( 4, 4) [000494] #----------- | | \--* IND long N003 ( 2, 2) [000493] -------N---- | | \--* ADD long N001 ( 1, 1) [000491] ------------ | | +--* LCL_VAR long V29 tmp15 u:1 N002 ( 1, 1) [000492] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000496] ------------ | \--* CNS_INT long 64 N009 ( 1, 1) [000504] ------------ \--* CNS_INT long 0 N001 [000491] LCL_VAR V29 tmp15 u:1 => $2e7 {$VN.ReadOnlyHeap[$100]} N002 [000492] CNS_INT 56 => $244 {LngCns: 56} N003 [000493] ADD => $306 {ADD($244, $2e7)} VNForMapSelect($2, $306):ref returns $2e9 {$VN.ReadOnlyHeap[$306]} VNForMapSelect($2, $306):ref returns $2e9 {$VN.ReadOnlyHeap[$306]} N004 [000494] IND => $2e9 {$VN.ReadOnlyHeap[$306]} VNForMapSelect($2, $2e9):ref returns $2ea {$VN.ReadOnlyHeap[$2e9]} VNForMapSelect($2, $2e9):ref returns $2ea {$VN.ReadOnlyHeap[$2e9]} N005 [000495] IND => $2ea {$VN.ReadOnlyHeap[$2e9]} N006 [000496] CNS_INT 64 => $245 {LngCns: 64} N007 [000497] ADD => $307 {ADD($245, $2ea)} N008 [000501] IND => N009 [000504] CNS_INT 0 => $243 {LngCns: 0} N010 [000505] EQ => ***** BB09, STMT00149(after) N011 ( 14, 13) [001148] ------------ * JTRUE void N010 ( 12, 11) [000505] J------N---- \--* EQ int N008 ( 10, 9) [000501] n----------- +--* IND long N007 ( 8, 7) [000497] -------N---- | \--* ADD long $307 N005 ( 7, 6) [000495] #----------- | +--* IND long $2ea N004 ( 4, 4) [000494] #----------- | | \--* IND long $2e9 N003 ( 2, 2) [000493] -------N---- | | \--* ADD long $306 N001 ( 1, 1) [000491] ------------ | | +--* LCL_VAR long V29 tmp15 u:1 $2e7 N002 ( 1, 1) [000492] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000496] ------------ | \--* CNS_INT long 64 $245 N009 ( 1, 1) [000504] ------------ \--* CNS_INT long 0 $243 finish(BB09). Succ(BB10). Not yet completed. All preds complete, adding to allDone. Succ(BB11). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#5) at start of BB11 is $2d7 {PhiMemoryDef($47, $2d6)} The SSA definition for GcHeap (#5) at start of BB11 is $2d7 {PhiMemoryDef($47, $2d6)} ***** BB11, STMT00151(before) N007 ( 17, 18) [001152] -AC-G---R--- * ASG long N006 ( 1, 1) [001151] D------N---- +--* LCL_VAR long V31 tmp17 d:2 N005 ( 17, 18) [000503] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 1, 1) [000490] ------?----- arg0 in rcx +--* LCL_VAR long V29 tmp15 u:1 (last use) N004 ( 2, 10) [000502] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr N001 [000829] ARGPLACE => $383 {383} N002 [000830] ARGPLACE => $384 {384} N003 [000490] LCL_VAR V29 tmp15 u:1 (last use) => $2e7 {$VN.ReadOnlyHeap[$100]} N004 [000502] CNS_INT(h) 0xd1ffab1e global ptr => $49 {Hnd const: 0x00000000D1FFAB1E} VN of ARGPLACE tree [000829] updated to $2e7 {$VN.ReadOnlyHeap[$100]} VN of ARGPLACE tree [000830] updated to $49 {Hnd const: 0x00000000D1FFAB1E} N005 [000503] CALL help => $308 {RuntimeHandleClass($2e7, $49)} N006 [001151] LCL_VAR V31 tmp17 d:2 => $308 {RuntimeHandleClass($2e7, $49)} N007 [001152] ASG => $308 {RuntimeHandleClass($2e7, $49)} ***** BB11, STMT00151(after) N007 ( 17, 18) [001152] -AC-G---R--- * ASG long $308 N006 ( 1, 1) [001151] D------N---- +--* LCL_VAR long V31 tmp17 d:2 $308 N005 ( 17, 18) [000503] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $308 N003 ( 1, 1) [000490] ------?----- arg0 in rcx +--* LCL_VAR long V29 tmp15 u:1 (last use) $2e7 N004 ( 2, 10) [000502] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $49 finish(BB11). Succ(BB12). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#5) at start of BB10 is $2d7 {PhiMemoryDef($47, $2d6)} The SSA definition for GcHeap (#5) at start of BB10 is $2d7 {PhiMemoryDef($47, $2d6)} ***** BB10, STMT00150(before) N010 ( 10, 9) [001150] -A------R--- * ASG long N009 ( 1, 1) [001149] D------N---- +--* LCL_VAR long V31 tmp17 d:3 N008 ( 10, 9) [000506] n-----?----- \--* IND long N007 ( 8, 7) [000507] ------?N---- \--* ADD long N005 ( 7, 6) [000508] #-----?----- +--* IND long N004 ( 4, 4) [000509] #-----?----- | \--* IND long N003 ( 2, 2) [000510] ------?N---- | \--* ADD long N001 ( 1, 1) [000511] ------?----- | +--* LCL_VAR long V29 tmp15 u:1 (last use) N002 ( 1, 1) [000512] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000513] ------?----- \--* CNS_INT long 64 N001 [000511] LCL_VAR V29 tmp15 u:1 (last use) => $2e7 {$VN.ReadOnlyHeap[$100]} N002 [000512] CNS_INT 56 => $244 {LngCns: 56} N003 [000510] ADD => $306 {ADD($244, $2e7)} VNForMapSelect($2, $306):ref returns $2e9 {$VN.ReadOnlyHeap[$306]} VNForMapSelect($2, $306):ref returns $2e9 {$VN.ReadOnlyHeap[$306]} N004 [000509] IND => $2e9 {$VN.ReadOnlyHeap[$306]} VNForMapSelect($2, $2e9):ref returns $2ea {$VN.ReadOnlyHeap[$2e9]} VNForMapSelect($2, $2e9):ref returns $2ea {$VN.ReadOnlyHeap[$2e9]} N005 [000508] IND => $2ea {$VN.ReadOnlyHeap[$2e9]} N006 [000513] CNS_INT 64 => $245 {LngCns: 64} N007 [000507] ADD => $307 {ADD($245, $2ea)} N008 [000506] IND => N009 [001149] LCL_VAR V31 tmp17 d:3 => N010 [001150] ASG => ***** BB10, STMT00150(after) N010 ( 10, 9) [001150] -A------R--- * ASG long N009 ( 1, 1) [001149] D------N---- +--* LCL_VAR long V31 tmp17 d:3 N008 ( 10, 9) [000506] n-----?----- \--* IND long N007 ( 8, 7) [000507] ------?N---- \--* ADD long $307 N005 ( 7, 6) [000508] #-----?----- +--* IND long $2ea N004 ( 4, 4) [000509] #-----?----- | \--* IND long $2e9 N003 ( 2, 2) [000510] ------?N---- | \--* ADD long $306 N001 ( 1, 1) [000511] ------?----- | +--* LCL_VAR long V29 tmp15 u:1 (last use) $2e7 N002 ( 1, 1) [000512] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000513] ------?----- \--* CNS_INT long 64 $245 finish(BB10). Succ(BB12). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 31/1 to $342 {PhiDef($1f, $1, $309)} . The SSA definition for ByrefExposed (#5) at start of BB12 is $2d7 {PhiMemoryDef($47, $2d6)} The SSA definition for GcHeap (#5) at start of BB12 is $2d7 {PhiMemoryDef($47, $2d6)} ***** BB12, STMT00083(before) N010 ( 31, 15) [000524] -ACXG---R--- * ASG int N009 ( 3, 2) [000523] D------N---- +--* LCL_VAR int V15 tmp1 d:3 N008 ( 27, 12) [000522] --CXG------- \--* CALL ind stub int N007 ( 1, 1) [000521] ------------ calli tgt \--* LCL_VAR long V31 tmp17 u:1 (last use) N004 ( 1, 1) [000484] ------------ this in rcx +--* LCL_VAR ref V05 loc1 u:1 N005 ( 1, 1) [000831] ------------ arg1 in r11 +--* LCL_VAR long V31 tmp17 u:1 r11 REG r11 N006 ( 1, 1) [000500] ------------ arg2 in rdx \--* LCL_VAR ref V01 arg1 u:1 N001 [000832] ARGPLACE => $214 {214} N002 [000833] ARGPLACE => $388 {388} N003 [000834] ARGPLACE => $215 {215} N004 [000484] LCL_VAR V05 loc1 u:1 => N005 [000831] LCL_VAR V31 tmp17 u:1 r11 => $342 {PhiDef($1f, $1, $309)} N006 [000500] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} N007 [000521] LCL_VAR V31 tmp17 u:1 (last use) => $342 {PhiDef($1f, $1, $309)} VN of ARGPLACE tree [000833] updated to VN of ARGPLACE tree [000834] updated to $342 {PhiDef($1f, $1, $309)} fgCurMemoryVN[GcHeap] assigned for CALL at [000522] to VN: $216. N008 [000522] CALL ind stub => $1c7 {1c7} N009 [000523] LCL_VAR V15 tmp1 d:3 => $1c7 {1c7} N010 [000524] ASG => $1c7 {1c7} ***** BB12, STMT00083(after) N010 ( 31, 15) [000524] -ACXG---R--- * ASG int $1c7 N009 ( 3, 2) [000523] D------N---- +--* LCL_VAR int V15 tmp1 d:3 $1c7 N008 ( 27, 12) [000522] --CXG------- \--* CALL ind stub int $1c7 N007 ( 1, 1) [000521] ------------ calli tgt \--* LCL_VAR long V31 tmp17 u:1 (last use) $342 N004 ( 1, 1) [000484] ------------ this in rcx +--* LCL_VAR ref V05 loc1 u:1 N005 ( 1, 1) [000831] ------------ arg1 in r11 +--* LCL_VAR long V31 tmp17 u:1 r11 REG r11 $342 N006 ( 1, 1) [000500] ------------ arg2 in rdx \--* LCL_VAR ref V01 arg1 u:1 $101 finish(BB12). Succ(BB14). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 15/1 to $3c0 {PhiDef($f, $1, $309)} . Building phi application: $cc = SSA# 39. Building phi application: $cd = SSA# 38. Building phi application: $2eb = phi($cd, $cc). The SSA definition for GcHeap (#6) at start of BB14 is $2ec {PhiMemoryDef($4a, $2eb)} ***** BB14, STMT00008(before) N003 ( 3, 3) [000042] -A------R--- * ASG int N002 ( 1, 1) [000041] D------N---- +--* LCL_VAR int V06 loc2 d:1 N001 ( 3, 2) [000040] ------------ \--* LCL_VAR int V15 tmp1 u:1 (last use) N001 [000040] LCL_VAR V15 tmp1 u:1 (last use) => $3c0 {PhiDef($f, $1, $309)} N002 [000041] LCL_VAR V06 loc2 d:1 => $3c0 {PhiDef($f, $1, $309)} N003 [000042] ASG => $3c0 {PhiDef($f, $1, $309)} ***** BB14, STMT00008(after) N003 ( 3, 3) [000042] -A------R--- * ASG int $3c0 N002 ( 1, 1) [000041] D------N---- +--* LCL_VAR int V06 loc2 d:1 $3c0 N001 ( 3, 2) [000040] ------------ \--* LCL_VAR int V15 tmp1 u:1 (last use) $3c0 --------- ***** BB14, STMT00009(before) N003 ( 1, 3) [000045] -A------R--- * ASG int N002 ( 1, 1) [000044] D------N---- +--* LCL_VAR int V07 loc3 d:1 N001 ( 1, 1) [000043] ------------ \--* CNS_INT int 0 N001 [000043] CNS_INT 0 => $c0 {IntCns 0} N002 [000044] LCL_VAR V07 loc3 d:1 => $c0 {IntCns 0} N003 [000045] ASG => $c0 {IntCns 0} ***** BB14, STMT00009(after) N003 ( 1, 3) [000045] -A------R--- * ASG int $c0 N002 ( 1, 1) [000044] D------N---- +--* LCL_VAR int V07 loc3 d:1 $c0 N001 ( 1, 1) [000043] ------------ \--* CNS_INT int 0 $c0 --------- ***** BB14, STMT00098(before) N006 ( 4, 4) [000580] -A-XG---R--- * ASG ref N005 ( 1, 1) [000579] D------N---- +--* LCL_VAR ref V39 tmp25 d:1 N004 ( 4, 4) [000578] ---XG------- \--* IND ref N003 ( 2, 2) [000845] -------N---- \--* ADD byref N001 ( 1, 1) [000046] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000844] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] N001 [000046] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N002 [000844] CNS_INT 8 field offset Fseq[_buckets] => $240 {LngCns: 8} N003 [000845] ADD => $280 {ADD($100, $240)} VNApplySelectors: VNForHandle(_buckets) is $41, fieldType is ref VNForMapSelect($2ec, $41):ref returns $2ef {$2ec[$41]} VNForMapSelect($2ef, $100):ref returns $2f0 {$2ef[$100]} N004 [000578] IND => N005 [000579] LCL_VAR V39 tmp25 d:1 => N006 [000580] ASG => ***** BB14, STMT00098(after) N006 ( 4, 4) [000580] -A-XG---R--- * ASG ref N005 ( 1, 1) [000579] D------N---- +--* LCL_VAR ref V39 tmp25 d:1 N004 ( 4, 4) [000578] ---XG------- \--* IND ref N003 ( 2, 2) [000845] -------N---- \--* ADD byref $280 N001 ( 1, 1) [000046] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000844] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] $240 --------- ***** BB14, STMT00105(before) N004 ( 3, 3) [000629] -A-X----R--- * ASG int N003 ( 1, 1) [000628] D------N---- +--* LCL_VAR int V40 tmp26 d:1 N002 ( 3, 3) [000583] ---X-------- \--* ARR_LENGTH int N001 ( 1, 1) [000582] ------------ \--* LCL_VAR ref V39 tmp25 u:1 N001 [000582] LCL_VAR V39 tmp25 u:1 => N002 [000583] ARR_LENGTH => N003 [000628] LCL_VAR V40 tmp26 d:1 => N004 [000629] ASG => ***** BB14, STMT00105(after) N004 ( 3, 3) [000629] -A-X----R--- * ASG int N003 ( 1, 1) [000628] D------N---- +--* LCL_VAR int V40 tmp26 d:1 N002 ( 3, 3) [000583] ---X-------- \--* ARR_LENGTH int N001 ( 1, 1) [000582] ------------ \--* LCL_VAR ref V39 tmp25 u:1 --------- ***** BB14, STMT00106(before) N006 ( 4, 4) [000631] -A-XG---R--- * ASG long N005 ( 1, 1) [000630] D------N---- +--* LCL_VAR long V41 tmp27 d:1 N004 ( 4, 4) [000585] ---XG------- \--* IND long N003 ( 2, 2) [000847] -------N---- \--* ADD byref N001 ( 1, 1) [000584] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000846] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] N001 [000584] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N002 [000846] CNS_INT 48 field offset Fseq[_fastModMultiplier] => $246 {LngCns: 48} N003 [000847] ADD => $283 {ADD($100, $246)} VNApplySelectors: VNForHandle(_fastModMultiplier) is $4b, fieldType is long VNForMapSelect($2ec, $4b):long returns $30c {$2ec[$4b]} VNForMapSelect($30c, $100):long returns $30d {$30c[$100]} N004 [000585] IND => N005 [000630] LCL_VAR V41 tmp27 d:1 => N006 [000631] ASG => ***** BB14, STMT00106(after) N006 ( 4, 4) [000631] -A-XG---R--- * ASG long N005 ( 1, 1) [000630] D------N---- +--* LCL_VAR long V41 tmp27 d:1 N004 ( 4, 4) [000585] ---XG------- \--* IND long N003 ( 2, 2) [000847] -------N---- \--* ADD byref $283 N001 ( 1, 1) [000584] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000846] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 --------- ***** BB14, STMT00108(before) N005 ( 6, 6) [000642] -A------R--- * ASG bool N004 ( 1, 1) [000641] D------N---- +--* LCL_VAR int V43 tmp29 d:1 N003 ( 6, 6) [000599] N--------U-- \--* LE int N001 ( 1, 1) [000597] ------------ +--* LCL_VAR int V40 tmp26 u:1 N002 ( 1, 4) [000598] ------------ \--* CNS_INT int 0x7FFFFFFF N001 [000597] LCL_VAR V40 tmp26 u:1 => N002 [000598] CNS_INT 0x7FFFFFFF => $ce {IntCns 0x7FFFFFFF} N003 [000599] LE => N004 [000641] LCL_VAR V43 tmp29 d:1 => N005 [000642] ASG => ***** BB14, STMT00108(after) N005 ( 6, 6) [000642] -A------R--- * ASG bool N004 ( 1, 1) [000641] D------N---- +--* LCL_VAR int V43 tmp29 d:1 N003 ( 6, 6) [000599] N--------U-- \--* LE int N001 ( 1, 1) [000597] ------------ +--* LCL_VAR int V40 tmp26 u:1 N002 ( 1, 4) [000598] ------------ \--* CNS_INT int 0x7FFFFFFF $ce --------- ***** BB14, STMT00111(before) N004 ( 4, 12) [000652] -A--G---R--- * ASG ref N003 ( 1, 1) [000651] D------N---- +--* LCL_VAR ref V44 tmp30 d:1 N002 ( 4, 12) [000636] #---G------- \--* IND ref N001 ( 2, 10) [000635] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] N001 [000635] CNS_INT(h) 0xD1FFAB1E [ICON_STR_HDL] => $43 {Hnd const: 0x00000000D1FFAB1E} N002 [000636] IND => $105 {NonNullIndirect($43)} N003 [000651] LCL_VAR V44 tmp30 d:1 => $105 {NonNullIndirect($43)} N004 [000652] ASG => $105 {NonNullIndirect($43)} ***** BB14, STMT00111(after) N004 ( 4, 12) [000652] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000651] D------N---- +--* LCL_VAR ref V44 tmp30 d:1 $105 N002 ( 4, 12) [000636] #---G------- \--* IND ref $105 N001 ( 2, 10) [000635] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 --------- ***** BB14, STMT00112(before) N004 ( 4, 12) [000654] -A--G---R--- * ASG ref N003 ( 1, 1) [000653] D------N---- +--* LCL_VAR ref V45 tmp31 d:1 N002 ( 4, 12) [000638] #---G------- \--* IND ref N001 ( 2, 10) [000637] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] N001 [000637] CNS_INT(h) 0xD1FFAB1E [ICON_STR_HDL] => $43 {Hnd const: 0x00000000D1FFAB1E} N002 [000638] IND => $105 {NonNullIndirect($43)} N003 [000653] LCL_VAR V45 tmp31 d:1 => $105 {NonNullIndirect($43)} N004 [000654] ASG => $105 {NonNullIndirect($43)} ***** BB14, STMT00112(after) N004 ( 4, 12) [000654] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000653] D------N---- +--* LCL_VAR ref V45 tmp31 d:1 $105 N002 ( 4, 12) [000638] #---G------- \--* IND ref $105 N001 ( 2, 10) [000637] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 --------- ***** BB14, STMT00109(before) N004 ( 5, 5) [000647] ------------ * JTRUE void N003 ( 3, 3) [000646] J------N---- \--* NE int N001 ( 1, 1) [000644] ------------ +--* LCL_VAR int V43 tmp29 u:1 (last use) N002 ( 1, 1) [000645] ------------ \--* CNS_INT int 0 N001 [000644] LCL_VAR V43 tmp29 u:1 (last use) => N002 [000645] CNS_INT 0 => $c0 {IntCns 0} N003 [000646] NE => ***** BB14, STMT00109(after) N004 ( 5, 5) [000647] ------------ * JTRUE void N003 ( 3, 3) [000646] J------N---- \--* NE int N001 ( 1, 1) [000644] ------------ +--* LCL_VAR int V43 tmp29 u:1 (last use) N002 ( 1, 1) [000645] ------------ \--* CNS_INT int 0 $c0 finish(BB14). Succ(BB15). Not yet completed. All preds complete, adding to allDone. Succ(BB16). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#6) at start of BB15 is $2ec {PhiMemoryDef($4a, $2eb)} The SSA definition for GcHeap (#6) at start of BB15 is $2ec {PhiMemoryDef($4a, $2eb)} ***** BB15, STMT00110(before) N005 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 1, 1) [000648] ------------ arg0 in rcx +--* LCL_VAR ref V44 tmp30 u:1 (last use) N004 ( 1, 1) [000649] ------------ arg1 in rdx \--* LCL_VAR ref V45 tmp31 u:1 (last use) N001 [000848] ARGPLACE => $21b {21b} N002 [000849] ARGPLACE => $21c {21c} N003 [000648] LCL_VAR V44 tmp30 u:1 (last use) => $105 {NonNullIndirect($43)} N004 [000649] LCL_VAR V45 tmp31 u:1 (last use) => $105 {NonNullIndirect($43)} VN of ARGPLACE tree [000848] updated to $105 {NonNullIndirect($43)} VN of ARGPLACE tree [000849] updated to $105 {NonNullIndirect($43)} fgCurMemoryVN[GcHeap] assigned for CALL at [000650] to VN: $21d. N005 [000650] CALL => $VN.Void ***** BB15, STMT00110(after) N005 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 1, 1) [000648] ------------ arg0 in rcx +--* LCL_VAR ref V44 tmp30 u:1 (last use) $105 N004 ( 1, 1) [000649] ------------ arg1 in rdx \--* LCL_VAR ref V45 tmp31 u:1 (last use) $105 finish(BB15). Succ(BB16). Not yet completed. All preds complete, adding to allDone. Building phi application: $cf = SSA# 37. Building phi application: $d0 = SSA# 6. Building phi application: $2f5 = phi($d0, $cf). The SSA definition for GcHeap (#7) at start of BB16 is $2f6 {PhiMemoryDef($4c, $2f5)} ***** BB16, STMT00103(before) N016 ( 20, 21) [000619] -A------R--- * ASG int N015 ( 1, 1) [000618] D------N---- +--* LCL_VAR int V42 tmp28 d:1 N014 ( 20, 21) [000617] ------------ \--* CAST int <- uint <- long N013 ( 19, 19) [000616] ------------ \--* RSZ long N011 ( 17, 17) [000614] ------------ +--* MUL long N008 ( 11, 11) [000611] ------------ | +--* ADD long N006 ( 9, 9) [000608] ------------ | | +--* RSZ long N004 ( 7, 7) [000606] ------------ | | | +--* MUL long N001 ( 1, 1) [000604] ------------ | | | | +--* LCL_VAR long V41 tmp27 u:1 (last use) N003 ( 2, 3) [000605] ---------U-- | | | | \--* CAST long <- ulong <- uint N002 ( 1, 1) [000047] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 N005 ( 1, 1) [000607] ------------ | | | \--* CNS_INT int 32 N007 ( 1, 1) [000610] ------------ | | \--* CNS_INT long 1 N010 ( 2, 3) [000613] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000612] ------------ | \--* LCL_VAR int V40 tmp26 u:1 N012 ( 1, 1) [000615] ------------ \--* CNS_INT int 32 N001 [000604] LCL_VAR V41 tmp27 u:1 (last use) => N002 [000047] LCL_VAR V06 loc2 u:1 => $3c0 {PhiDef($f, $1, $309)} VNForCastOper(ulong, unsignedSrc) is $d1 N003 [000605] CAST => $310 {Cast($3c0, $d1)} N004 [000606] MUL => N005 [000607] CNS_INT 32 => $d2 {IntCns 32} N006 [000608] RSZ => N007 [000610] CNS_INT 1 => $247 {LngCns: 1} N008 [000611] ADD => N009 [000612] LCL_VAR V40 tmp26 u:1 => VNForCastOper(ulong, unsignedSrc) is $d1 N010 [000613] CAST => N011 [000614] MUL => N012 [000615] CNS_INT 32 => $d2 {IntCns 32} N013 [000616] RSZ => VNForCastOper(uint) is $d3 N014 [000617] CAST => N015 [000618] LCL_VAR V42 tmp28 d:1 => N016 [000619] ASG => ***** BB16, STMT00103(after) N016 ( 20, 21) [000619] -A------R--- * ASG int N015 ( 1, 1) [000618] D------N---- +--* LCL_VAR int V42 tmp28 d:1 N014 ( 20, 21) [000617] ------------ \--* CAST int <- uint <- long N013 ( 19, 19) [000616] ------------ \--* RSZ long N011 ( 17, 17) [000614] ------------ +--* MUL long N008 ( 11, 11) [000611] ------------ | +--* ADD long N006 ( 9, 9) [000608] ------------ | | +--* RSZ long N004 ( 7, 7) [000606] ------------ | | | +--* MUL long N001 ( 1, 1) [000604] ------------ | | | | +--* LCL_VAR long V41 tmp27 u:1 (last use) N003 ( 2, 3) [000605] ---------U-- | | | | \--* CAST long <- ulong <- uint $310 N002 ( 1, 1) [000047] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 $3c0 N005 ( 1, 1) [000607] ------------ | | | \--* CNS_INT int 32 $d2 N007 ( 1, 1) [000610] ------------ | | \--* CNS_INT long 1 $247 N010 ( 2, 3) [000613] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000612] ------------ | \--* LCL_VAR int V40 tmp26 u:1 N012 ( 1, 1) [000615] ------------ \--* CNS_INT int 32 $d2 --------- ***** BB16, STMT00114(before) N007 ( 27, 7) [000665] -A-X----R--- * ASG bool N006 ( 1, 1) [000664] D------N---- +--* LCL_VAR int V46 tmp32 d:1 N005 ( 27, 7) [000624] ---X-------- \--* EQ int N003 ( 22, 5) [000623] ---X-------- +--* UMOD int N001 ( 1, 1) [000621] ------------ | +--* LCL_VAR int V06 loc2 u:1 N002 ( 1, 1) [000622] ------------ | \--* LCL_VAR int V40 tmp26 u:1 (last use) N004 ( 1, 1) [000620] ------------ \--* LCL_VAR int V42 tmp28 u:1 N001 [000621] LCL_VAR V06 loc2 u:1 => $3c0 {PhiDef($f, $1, $309)} N002 [000622] LCL_VAR V40 tmp26 u:1 (last use) => N003 [000623] UMOD => N004 [000620] LCL_VAR V42 tmp28 u:1 => N005 [000624] EQ => N006 [000664] LCL_VAR V46 tmp32 d:1 => N007 [000665] ASG => ***** BB16, STMT00114(after) N007 ( 27, 7) [000665] -A-X----R--- * ASG bool N006 ( 1, 1) [000664] D------N---- +--* LCL_VAR int V46 tmp32 d:1 N005 ( 27, 7) [000624] ---X-------- \--* EQ int N003 ( 22, 5) [000623] ---X-------- +--* UMOD int N001 ( 1, 1) [000621] ------------ | +--* LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000622] ------------ | \--* LCL_VAR int V40 tmp26 u:1 (last use) N004 ( 1, 1) [000620] ------------ \--* LCL_VAR int V42 tmp28 u:1 --------- ***** BB16, STMT00117(before) N004 ( 4, 12) [000675] -A--G---R--- * ASG ref N003 ( 1, 1) [000674] D------N---- +--* LCL_VAR ref V47 tmp33 d:1 N002 ( 4, 12) [000659] #---G------- \--* IND ref N001 ( 2, 10) [000658] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] N001 [000658] CNS_INT(h) 0xD1FFAB1E [ICON_STR_HDL] => $43 {Hnd const: 0x00000000D1FFAB1E} N002 [000659] IND => $105 {NonNullIndirect($43)} N003 [000674] LCL_VAR V47 tmp33 d:1 => $105 {NonNullIndirect($43)} N004 [000675] ASG => $105 {NonNullIndirect($43)} ***** BB16, STMT00117(after) N004 ( 4, 12) [000675] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000674] D------N---- +--* LCL_VAR ref V47 tmp33 d:1 $105 N002 ( 4, 12) [000659] #---G------- \--* IND ref $105 N001 ( 2, 10) [000658] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 --------- ***** BB16, STMT00118(before) N004 ( 4, 12) [000677] -A--G---R--- * ASG ref N003 ( 1, 1) [000676] D------N---- +--* LCL_VAR ref V48 tmp34 d:1 N002 ( 4, 12) [000661] #---G------- \--* IND ref N001 ( 2, 10) [000660] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] N001 [000660] CNS_INT(h) 0xD1FFAB1E [ICON_STR_HDL] => $43 {Hnd const: 0x00000000D1FFAB1E} N002 [000661] IND => $105 {NonNullIndirect($43)} N003 [000676] LCL_VAR V48 tmp34 d:1 => $105 {NonNullIndirect($43)} N004 [000677] ASG => $105 {NonNullIndirect($43)} ***** BB16, STMT00118(after) N004 ( 4, 12) [000677] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000676] D------N---- +--* LCL_VAR ref V48 tmp34 d:1 $105 N002 ( 4, 12) [000661] #---G------- \--* IND ref $105 N001 ( 2, 10) [000660] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 --------- ***** BB16, STMT00115(before) N004 ( 5, 5) [000670] ------------ * JTRUE void N003 ( 3, 3) [000669] J------N---- \--* NE int N001 ( 1, 1) [000667] ------------ +--* LCL_VAR int V46 tmp32 u:1 (last use) N002 ( 1, 1) [000668] ------------ \--* CNS_INT int 0 N001 [000667] LCL_VAR V46 tmp32 u:1 (last use) => N002 [000668] CNS_INT 0 => $c0 {IntCns 0} N003 [000669] NE => ***** BB16, STMT00115(after) N004 ( 5, 5) [000670] ------------ * JTRUE void N003 ( 3, 3) [000669] J------N---- \--* NE int N001 ( 1, 1) [000667] ------------ +--* LCL_VAR int V46 tmp32 u:1 (last use) N002 ( 1, 1) [000668] ------------ \--* CNS_INT int 0 $c0 finish(BB16). Succ(BB17). Not yet completed. All preds complete, adding to allDone. Succ(BB18). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#7) at start of BB17 is $2f6 {PhiMemoryDef($4c, $2f5)} The SSA definition for GcHeap (#7) at start of BB17 is $2f6 {PhiMemoryDef($4c, $2f5)} ***** BB17, STMT00116(before) N005 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 1, 1) [000671] ------------ arg0 in rcx +--* LCL_VAR ref V47 tmp33 u:1 (last use) N004 ( 1, 1) [000672] ------------ arg1 in rdx \--* LCL_VAR ref V48 tmp34 u:1 (last use) N001 [000850] ARGPLACE => $220 {220} N002 [000851] ARGPLACE => $221 {221} N003 [000671] LCL_VAR V47 tmp33 u:1 (last use) => $105 {NonNullIndirect($43)} N004 [000672] LCL_VAR V48 tmp34 u:1 (last use) => $105 {NonNullIndirect($43)} VN of ARGPLACE tree [000850] updated to $105 {NonNullIndirect($43)} VN of ARGPLACE tree [000851] updated to $105 {NonNullIndirect($43)} fgCurMemoryVN[GcHeap] assigned for CALL at [000673] to VN: $222. N005 [000673] CALL => $VN.Void ***** BB17, STMT00116(after) N005 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 1, 1) [000671] ------------ arg0 in rcx +--* LCL_VAR ref V47 tmp33 u:1 (last use) $105 N004 ( 1, 1) [000672] ------------ arg1 in rdx \--* LCL_VAR ref V48 tmp34 u:1 (last use) $105 finish(BB17). Succ(BB18). Not yet completed. All preds complete, adding to allDone. Building phi application: $d4 = SSA# 36. Building phi application: $d5 = SSA# 7. Building phi application: $2f9 = phi($d5, $d4). The SSA definition for GcHeap (#8) at start of BB18 is $2fa {PhiMemoryDef($4d, $2f9)} ***** BB18, STMT00100(before) N017 ( 19, 24) [000591] -A-XG---R--- * ASG byref N016 ( 1, 1) [000590] D------N---- +--* LCL_VAR byref V38 tmp24 d:1 N015 ( 19, 24) [000862] ---XG------- \--* COMMA byref N004 ( 8, 11) [000855] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000627] ------------ | +--* LCL_VAR int V42 tmp28 u:1 N003 ( 3, 3) [000854] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000581] ------------ | \--* LCL_VAR ref V39 tmp25 u:1 N014 ( 11, 13) [000863] ----G------- \--* ADDR byref N013 ( 6, 7) [000588] a---G--N---- \--* IND int N012 ( 5, 6) [000861] -------N---- \--* ADD byref N005 ( 1, 1) [000852] ------------ +--* LCL_VAR ref V39 tmp25 u:1 (last use) N011 ( 4, 5) [000860] -------N---- \--* ADD long N009 ( 3, 4) [000858] -------N---- +--* LSH long N007 ( 2, 3) [000856] ------------ | +--* CAST long <- int N006 ( 1, 1) [000853] i----------- | | \--* LCL_VAR int V42 tmp28 u:1 (last use) N008 ( 1, 1) [000857] -------N---- | \--* CNS_INT long 2 N010 ( 1, 1) [000859] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] N001 [000627] LCL_VAR V42 tmp28 u:1 => N002 [000581] LCL_VAR V39 tmp25 u:1 => N003 [000854] ARR_LENGTH => N004 [000855] ARR_BOUNDS_CHECK_Rng => N005 [000852] LCL_VAR V39 tmp25 u:1 (last use) => N006 [000853] LCL_VAR V42 tmp28 u:1 (last use) => VNForCastOper(long) is $d6 N007 [000856] CAST => N008 [000857] CNS_INT 2 => $248 {LngCns: 2} N009 [000858] LSH => N010 [000859] CNS_INT 16 Fseq[#FirstElem] => $241 {LngCns: 16} N011 [000860] ADD => N012 [000861] ADD => VNForHandle(arrElemType: int) is $4e Relabeled IND_ARR_INDEX address node [000861] with l:$81: {PtrToArrElem($4e, $2f0, $31e, $0)} VNForMapSelect($2fa, $4e):ref returns $44b {$2fa[$4e]} VNForMapSelect($44b, $2f0):ref returns $44c {$44b[$2f0]} VNForMapSelect($44c, $31e):int returns $1a5 {$44c[$31e]} hAtArrType $44b is MapSelect(curGcHeap($2fa), int[]). hAtArrTypeAtArr $44c is MapSelect(hAtArrType($44b), arr=$2f0). wholeElem $1a5 is MapSelect(hAtArrTypeAtArr($44c), ind=$31e). N013 [000588] IND => N014 [000863] ADDR => $81 {PtrToArrElem($4e, $2f0, $31e, $0)} N015 [000862] COMMA => N016 [000590] LCL_VAR V38 tmp24 d:1 => $81 {PtrToArrElem($4e, $2f0, $31e, $0)} N017 [000591] ASG => ***** BB18, STMT00100(after) N017 ( 19, 24) [000591] -A-XG---R--- * ASG byref N016 ( 1, 1) [000590] D------N---- +--* LCL_VAR byref V38 tmp24 d:1 $81 N015 ( 19, 24) [000862] ---XG------- \--* COMMA byref N004 ( 8, 11) [000855] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000627] ------------ | +--* LCL_VAR int V42 tmp28 u:1 N003 ( 3, 3) [000854] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000581] ------------ | \--* LCL_VAR ref V39 tmp25 u:1 N014 ( 11, 13) [000863] ----G------- \--* ADDR byref $81 N013 ( 6, 7) [000588] a---G--N---- \--* IND int N012 ( 5, 6) [000861] -------N---- \--* ADD byref $81 N005 ( 1, 1) [000852] ------------ +--* LCL_VAR ref V39 tmp25 u:1 (last use) N011 ( 4, 5) [000860] -------N---- \--* ADD long N009 ( 3, 4) [000858] -------N---- +--* LSH long N007 ( 2, 3) [000856] ------------ | +--* CAST long <- int N006 ( 1, 1) [000853] i----------- | | \--* LCL_VAR int V42 tmp28 u:1 (last use) N008 ( 1, 1) [000857] -------N---- | \--* CNS_INT long 2 $248 N010 ( 1, 1) [000859] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 --------- ***** BB18, STMT00011(before) N003 ( 5, 4) [000051] -A------R--- * ASG byref N002 ( 3, 2) [000050] D------N---- +--* LCL_VAR byref V08 loc4 d:1 N001 ( 1, 1) [000592] ------------ \--* LCL_VAR byref V38 tmp24 u:1 N001 [000592] LCL_VAR V38 tmp24 u:1 => $81 {PtrToArrElem($4e, $2f0, $31e, $0)} N002 [000050] LCL_VAR V08 loc4 d:1 => $81 {PtrToArrElem($4e, $2f0, $31e, $0)} N003 [000051] ASG => $81 {PtrToArrElem($4e, $2f0, $31e, $0)} ***** BB18, STMT00011(after) N003 ( 5, 4) [000051] -A------R--- * ASG byref $81 N002 ( 3, 2) [000050] D------N---- +--* LCL_VAR byref V08 loc4 d:1 $81 N001 ( 1, 1) [000592] ------------ \--* LCL_VAR byref V38 tmp24 u:1 $81 --------- ***** BB18, STMT00012(before) N006 ( 5, 4) [000057] -A-XG---R--- * ASG int N005 ( 1, 1) [000056] D------N---- +--* LCL_VAR int V09 loc5 d:1 N004 ( 5, 4) [000055] ---XG------- \--* ADD int N002 ( 3, 2) [000053] *--XG------- +--* IND int N001 ( 1, 1) [000052] ------------ | \--* LCL_VAR byref V38 tmp24 u:1 (last use) N003 ( 1, 1) [000054] ------------ \--* CNS_INT int -1 N001 [000052] LCL_VAR V38 tmp24 u:1 (last use) => $81 {PtrToArrElem($4e, $2f0, $31e, $0)} VNForMapSelect($2fa, $4e):ref returns $44b {$2fa[$4e]} VNForMapSelect($44b, $2f0):ref returns $44c {$44b[$2f0]} VNForMapSelect($44c, $31e):int returns $1a5 {$44c[$31e]} hAtArrType $44b is MapSelect(curGcHeap($2fa), int[]). hAtArrTypeAtArr $44c is MapSelect(hAtArrType($44b), arr=$2f0). wholeElem $1a5 is MapSelect(hAtArrTypeAtArr($44c), ind=$31e). N002 [000053] IND => N003 [000054] CNS_INT -1 => $c4 {IntCns -1} N004 [000055] ADD => N005 [000056] LCL_VAR V09 loc5 d:1 => N006 [000057] ASG => ***** BB18, STMT00012(after) N006 ( 5, 4) [000057] -A-XG---R--- * ASG int N005 ( 1, 1) [000056] D------N---- +--* LCL_VAR int V09 loc5 d:1 N004 ( 5, 4) [000055] ---XG------- \--* ADD int N002 ( 3, 2) [000053] *--XG------- +--* IND int N001 ( 1, 1) [000052] ------------ | \--* LCL_VAR byref V38 tmp24 u:1 (last use) $81 N003 ( 1, 1) [000054] ------------ \--* CNS_INT int -1 $c4 --------- ***** BB18, STMT00013(before) N004 ( 5, 5) [000061] ------------ * JTRUE void N003 ( 3, 3) [000060] J------N---- \--* NE int N001 ( 1, 1) [000058] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000059] ------------ \--* CNS_INT ref null N001 [000058] LCL_VAR V05 loc1 u:1 => N002 [000059] CNS_INT null => $VN.Null N003 [000060] NE => ***** BB18, STMT00013(after) N004 ( 5, 5) [000061] ------------ * JTRUE void N003 ( 3, 3) [000060] J------N---- \--* NE int N001 ( 1, 1) [000058] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000059] ------------ \--* CNS_INT ref null $VN.Null finish(BB18). Succ(BB19). Not yet completed. All preds complete, adding to allDone. Succ(BB32). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#8) at start of BB19 is $2fa {PhiMemoryDef($4d, $2f9)} The SSA definition for GcHeap (#8) at start of BB19 is $2fa {PhiMemoryDef($4d, $2f9)} ***** BB19, STMT00059(before) N004 ( 3, 3) [000356] -A-X----R--- * ASG long N003 ( 1, 1) [000355] D------N---- +--* LCL_VAR long V24 tmp10 d:1 N002 ( 3, 2) [000354] #--X-------- \--* IND long N001 ( 1, 1) [000353] !----------- \--* LCL_VAR ref V00 this u:1 N001 [000353] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} VNForMapSelect($2, $100):ref returns $2e7 {$VN.ReadOnlyHeap[$100]} VNForMapSelect($2, $100):ref returns $2e7 {$VN.ReadOnlyHeap[$100]} N002 [000354] IND => $2e8 {norm=$2e7 {$VN.ReadOnlyHeap[$100]}, exc=$2c2 {NullPtrExc($100)}} N003 [000355] LCL_VAR V24 tmp10 d:1 => $2e7 {$VN.ReadOnlyHeap[$100]} N004 [000356] ASG => $2e8 {norm=$2e7 {$VN.ReadOnlyHeap[$100]}, exc=$2c2 {NullPtrExc($100)}} ***** BB19, STMT00059(after) N004 ( 3, 3) [000356] -A-X----R--- * ASG long $2e8 N003 ( 1, 1) [000355] D------N---- +--* LCL_VAR long V24 tmp10 d:1 $2e7 N002 ( 3, 2) [000354] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000353] !----------- \--* LCL_VAR ref V00 this u:1 $100 --------- ***** BB19, STMT00152(before) N011 ( 14, 13) [001153] ------------ * JTRUE void N010 ( 12, 11) [000369] J------N---- \--* EQ int N008 ( 10, 9) [000365] n----------- +--* IND long N007 ( 8, 7) [000364] -------N---- | \--* ADD long N005 ( 7, 6) [000362] #----------- | +--* IND long N004 ( 4, 4) [000361] #----------- | | \--* IND long N003 ( 2, 2) [000360] -------N---- | | \--* ADD long N001 ( 1, 1) [000358] ------------ | | +--* LCL_VAR long V24 tmp10 u:1 N002 ( 1, 1) [000359] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000363] ------------ | \--* CNS_INT long 32 N009 ( 1, 1) [000368] ------------ \--* CNS_INT long 0 N001 [000358] LCL_VAR V24 tmp10 u:1 => $2e7 {$VN.ReadOnlyHeap[$100]} N002 [000359] CNS_INT 56 => $244 {LngCns: 56} N003 [000360] ADD => $306 {ADD($244, $2e7)} VNForMapSelect($2, $306):ref returns $2e9 {$VN.ReadOnlyHeap[$306]} VNForMapSelect($2, $306):ref returns $2e9 {$VN.ReadOnlyHeap[$306]} N004 [000361] IND => $2e9 {$VN.ReadOnlyHeap[$306]} VNForMapSelect($2, $2e9):ref returns $2ea {$VN.ReadOnlyHeap[$2e9]} VNForMapSelect($2, $2e9):ref returns $2ea {$VN.ReadOnlyHeap[$2e9]} N005 [000362] IND => $2ea {$VN.ReadOnlyHeap[$2e9]} N006 [000363] CNS_INT 32 => $24a {LngCns: 32} N007 [000364] ADD => $324 {ADD($24a, $2ea)} N008 [000365] IND => N009 [000368] CNS_INT 0 => $243 {LngCns: 0} N010 [000369] EQ => ***** BB19, STMT00152(after) N011 ( 14, 13) [001153] ------------ * JTRUE void N010 ( 12, 11) [000369] J------N---- \--* EQ int N008 ( 10, 9) [000365] n----------- +--* IND long N007 ( 8, 7) [000364] -------N---- | \--* ADD long $324 N005 ( 7, 6) [000362] #----------- | +--* IND long $2ea N004 ( 4, 4) [000361] #----------- | | \--* IND long $2e9 N003 ( 2, 2) [000360] -------N---- | | \--* ADD long $306 N001 ( 1, 1) [000358] ------------ | | +--* LCL_VAR long V24 tmp10 u:1 $2e7 N002 ( 1, 1) [000359] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000363] ------------ | \--* CNS_INT long 32 $24a N009 ( 1, 1) [000368] ------------ \--* CNS_INT long 0 $243 finish(BB19). Succ(BB20). Not yet completed. All preds complete, adding to allDone. Succ(BB21). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#8) at start of BB21 is $2fa {PhiMemoryDef($4d, $2f9)} The SSA definition for GcHeap (#8) at start of BB21 is $2fa {PhiMemoryDef($4d, $2f9)} ***** BB21, STMT00154(before) N007 ( 21, 21) [001157] -AC-G---R--- * ASG long N006 ( 3, 2) [001156] D------N---- +--* LCL_VAR long V25 tmp11 d:2 N005 ( 17, 18) [000367] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 1, 1) [000357] ------?----- arg0 in rcx +--* LCL_VAR long V24 tmp10 u:1 (last use) N004 ( 2, 10) [000366] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr N001 [000864] ARGPLACE => $38d {38d} N002 [000865] ARGPLACE => $38e {38e} N003 [000357] LCL_VAR V24 tmp10 u:1 (last use) => $2e7 {$VN.ReadOnlyHeap[$100]} N004 [000366] CNS_INT(h) 0xd1ffab1e global ptr => $4f {Hnd const: 0x00000000D1FFAB1E} VN of ARGPLACE tree [000864] updated to $2e7 {$VN.ReadOnlyHeap[$100]} VN of ARGPLACE tree [000865] updated to $4f {Hnd const: 0x00000000D1FFAB1E} N005 [000367] CALL help => $325 {RuntimeHandleClass($2e7, $4f)} N006 [001156] LCL_VAR V25 tmp11 d:2 => $325 {RuntimeHandleClass($2e7, $4f)} N007 [001157] ASG => $325 {RuntimeHandleClass($2e7, $4f)} ***** BB21, STMT00154(after) N007 ( 21, 21) [001157] -AC-G---R--- * ASG long $325 N006 ( 3, 2) [001156] D------N---- +--* LCL_VAR long V25 tmp11 d:2 $325 N005 ( 17, 18) [000367] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $325 N003 ( 1, 1) [000357] ------?----- arg0 in rcx +--* LCL_VAR long V24 tmp10 u:1 (last use) $2e7 N004 ( 2, 10) [000366] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $4f finish(BB21). Succ(BB22). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#8) at start of BB20 is $2fa {PhiMemoryDef($4d, $2f9)} The SSA definition for GcHeap (#8) at start of BB20 is $2fa {PhiMemoryDef($4d, $2f9)} ***** BB20, STMT00153(before) N010 ( 14, 12) [001155] -A------R--- * ASG long N009 ( 3, 2) [001154] D------N---- +--* LCL_VAR long V25 tmp11 d:3 N008 ( 10, 9) [000370] n-----?----- \--* IND long N007 ( 8, 7) [000371] ------?N---- \--* ADD long N005 ( 7, 6) [000372] #-----?----- +--* IND long N004 ( 4, 4) [000373] #-----?----- | \--* IND long N003 ( 2, 2) [000374] ------?N---- | \--* ADD long N001 ( 1, 1) [000375] ------?----- | +--* LCL_VAR long V24 tmp10 u:1 (last use) N002 ( 1, 1) [000376] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000377] ------?----- \--* CNS_INT long 32 N001 [000375] LCL_VAR V24 tmp10 u:1 (last use) => $2e7 {$VN.ReadOnlyHeap[$100]} N002 [000376] CNS_INT 56 => $244 {LngCns: 56} N003 [000374] ADD => $306 {ADD($244, $2e7)} VNForMapSelect($2, $306):ref returns $2e9 {$VN.ReadOnlyHeap[$306]} VNForMapSelect($2, $306):ref returns $2e9 {$VN.ReadOnlyHeap[$306]} N004 [000373] IND => $2e9 {$VN.ReadOnlyHeap[$306]} VNForMapSelect($2, $2e9):ref returns $2ea {$VN.ReadOnlyHeap[$2e9]} VNForMapSelect($2, $2e9):ref returns $2ea {$VN.ReadOnlyHeap[$2e9]} N005 [000372] IND => $2ea {$VN.ReadOnlyHeap[$2e9]} N006 [000377] CNS_INT 32 => $24a {LngCns: 32} N007 [000371] ADD => $324 {ADD($24a, $2ea)} N008 [000370] IND => N009 [001154] LCL_VAR V25 tmp11 d:3 => N010 [001155] ASG => ***** BB20, STMT00153(after) N010 ( 14, 12) [001155] -A------R--- * ASG long N009 ( 3, 2) [001154] D------N---- +--* LCL_VAR long V25 tmp11 d:3 N008 ( 10, 9) [000370] n-----?----- \--* IND long N007 ( 8, 7) [000371] ------?N---- \--* ADD long $324 N005 ( 7, 6) [000372] #-----?----- +--* IND long $2ea N004 ( 4, 4) [000373] #-----?----- | \--* IND long $2e9 N003 ( 2, 2) [000374] ------?N---- | \--* ADD long $306 N001 ( 1, 1) [000375] ------?----- | +--* LCL_VAR long V24 tmp10 u:1 (last use) $2e7 N002 ( 1, 1) [000376] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000377] ------?----- \--* CNS_INT long 32 $24a finish(BB20). Succ(BB22). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 25/1 to $344 {PhiDef($19, $1, $309)} . The SSA definition for ByrefExposed (#8) at start of BB22 is $2fa {PhiMemoryDef($4d, $2f9)} The SSA definition for GcHeap (#8) at start of BB22 is $2fa {PhiMemoryDef($4d, $2f9)} ***** BB22, STMT00062(before) N005 ( 17, 8) [000386] -ACXG---R--- * ASG ref N004 ( 1, 1) [000385] D------N---- +--* LCL_VAR ref V12 loc8 d:1 N003 ( 17, 8) [000352] --CXG------- \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default N002 ( 3, 2) [000382] ------------ arg0 in rcx \--* LCL_VAR long V25 tmp11 u:1 (last use) N001 [000866] ARGPLACE => $392 {392} N002 [000382] LCL_VAR V25 tmp11 u:1 (last use) => $344 {PhiDef($19, $1, $309)} VN of ARGPLACE tree [000866] updated to $344 {PhiDef($19, $1, $309)} fgCurMemoryVN[GcHeap] assigned for CALL at [000352] to VN: $224. N003 [000352] CALL => $223 {223} N004 [000385] LCL_VAR V12 loc8 d:1 => $223 {223} N005 [000386] ASG => $223 {223} ***** BB22, STMT00062(after) N005 ( 17, 8) [000386] -ACXG---R--- * ASG ref $223 N004 ( 1, 1) [000385] D------N---- +--* LCL_VAR ref V12 loc8 d:1 $223 N003 ( 17, 8) [000352] --CXG------- \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default $223 N002 ( 3, 2) [000382] ------------ arg0 in rcx \--* LCL_VAR long V25 tmp11 u:1 (last use) $344 finish(BB22). Succ(BB23). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. SSA PHI definition: set VN of local 7/5 to $3c1 {PhiDef($7, $5, $1b0)} . SSA PHI definition: set VN of local 9/4 to $3c2 {PhiDef($9, $4, $1b1)} . Computing GcHeap state for block BB23, entry block for loops 0 to 0: Loop 0 has memory havoc effect; heap state is new unique $4c0. The SSA definition for GcHeap (#31) at start of BB23 is $4c0 {4c0} ***** BB23, STMT00063(before) N005 ( 7, 7) [000391] ---X-------- * JTRUE void N004 ( 5, 5) [000390] N--X---N-U-- \--* LE int N002 ( 3, 3) [000389] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000388] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000387] ------------ \--* LCL_VAR int V09 loc5 u:4 N001 [000388] LCL_VAR V04 loc0 u:1 => N002 [000389] ARR_LENGTH => N003 [000387] LCL_VAR V09 loc5 u:4 => $3c2 {PhiDef($9, $4, $1b1)} N004 [000390] LE => ***** BB23, STMT00063(after) N005 ( 7, 7) [000391] ---X-------- * JTRUE void N004 ( 5, 5) [000390] N--X---N-U-- \--* LE int N002 ( 3, 3) [000389] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000388] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000387] ------------ \--* LCL_VAR int V09 loc5 u:4 $3c2 finish(BB23). Succ(BB24). Not yet completed. All preds complete, adding to allDone. Succ(BB44). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#31) at start of BB24 is $4c0 {4c0} The SSA definition for GcHeap (#31) at start of BB24 is $4c0 {4c0} ***** BB24, STMT00064(before) N023 ( 36, 39) [000399] ---XG------- * JTRUE void N022 ( 34, 37) [000398] N--XG--N-U-- \--* NE int N020 ( 32, 35) [000396] *--XG------- +--* IND int N019 ( 30, 33) [000868] ---XG--N---- | \--* ADD byref N017 ( 29, 32) [000879] ---XG------- | +--* COMMA byref $80 N004 ( 8, 11) [000872] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000393] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 N003 ( 3, 3) [000871] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000392] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000882] ----G------- | | \--* ADDR byref $80 N015 ( 11, 11) [000394] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000878] -------N---- | | \--* ADD byref N005 ( 1, 1) [000869] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000877] -------N---- | | \--* ADD long N011 ( 8, 8) [000875] -------N---- | | +--* LSH long N009 ( 7, 7) [000881] ------------ | | | +--* MUL long N007 ( 2, 3) [000873] ------------ | | | | +--* CAST long <- int N006 ( 1, 1) [000870] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 N008 ( 1, 1) [000880] ------------ | | | | \--* CNS_INT long 3 N010 ( 1, 1) [000874] -------N---- | | | \--* CNS_INT long 3 N012 ( 1, 1) [000876] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000867] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] N021 ( 1, 1) [000397] ------------ \--* LCL_VAR int V06 loc2 u:1 N001 [000393] LCL_VAR V09 loc5 u:4 => $3c2 {PhiDef($9, $4, $1b1)} N002 [000392] LCL_VAR V04 loc0 u:1 => N003 [000871] ARR_LENGTH => N004 [000872] ARR_BOUNDS_CHECK_Rng => N005 [000869] LCL_VAR V04 loc0 u:1 => N006 [000870] LCL_VAR V09 loc5 u:4 => $3c2 {PhiDef($9, $4, $1b1)} VNForCastOper(long) is $d6 N007 [000873] CAST => $326 {Cast($3c2, $d6)} N008 [000880] CNS_INT 3 => $24b {LngCns: 3} N009 [000881] MUL => $327 {MUL($24b, $326)} N010 [000874] CNS_INT 3 => $24b {LngCns: 3} N011 [000875] LSH => $328 {LSH($327, $24b)} N012 [000876] CNS_INT 16 Fseq[#FirstElem] => $241 {LngCns: 16} N013 [000877] ADD => $329 {ADD($241, $328)} N014 [000878] ADD => VNForHandle(arrElemType: Entry[__Canon,__Canon]) is $40 Relabeled IND_ARR_INDEX address node [000878] with l:$82: {PtrToArrElem($40, $2d3, $326, $0)} VNForMapSelect($4c0, $40):ref returns $45a {$4c0[$40]} VNForMapSelect($45a, $2d3):ref returns $45b {$45a[$2d3]} VNForMapSelect($45b, $326):struct returns $500 {$45b[$326]} hAtArrType $45a is MapSelect(curGcHeap($4c0), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $45b is MapSelect(hAtArrType($45a), arr=$2d3). wholeElem $500 is MapSelect(hAtArrTypeAtArr($45b), ind=$326). N015 [000394] IND => N016 [000882] ADDR => $82 {PtrToArrElem($40, $2d3, $326, $0)} N017 [000879] COMMA => N018 [000867] CNS_INT 16 field offset Fseq[hashCode] => $241 {LngCns: 16} FieldSeq {hashCode} is $45c N019 [000868] ADD => $28c {norm=$83 {PtrToArrElem($40, $2d3, $326, $45c)}, exc=$457( {NullPtrExc($2d3)}, {IndexOutOfRangeExc($3c2, $403)})} VNForMapSelect($4c0, $40):ref returns $45a {$4c0[$40]} VNForMapSelect($45a, $2d3):ref returns $45b {$45a[$2d3]} VNForMapSelect($45b, $326):struct returns $500 {$45b[$326]} hAtArrType $45a is MapSelect(curGcHeap($4c0), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $45b is MapSelect(hAtArrType($45a), arr=$2d3). wholeElem $500 is MapSelect(hAtArrTypeAtArr($45b), ind=$326). VNApplySelectors: VNForHandle(hashCode) is $50, fieldType is int VNForMapSelect($500, $50):int returns $1b8 {$500[$50]} selectedElem is $1b9 after applying selectors. N020 [000396] IND => N021 [000397] LCL_VAR V06 loc2 u:1 => $3c0 {PhiDef($f, $1, $309)} N022 [000398] NE => ***** BB24, STMT00064(after) N023 ( 36, 39) [000399] ---XG------- * JTRUE void N022 ( 34, 37) [000398] N--XG--N-U-- \--* NE int N020 ( 32, 35) [000396] *--XG------- +--* IND int N019 ( 30, 33) [000868] ---XG--N---- | \--* ADD byref $28c N017 ( 29, 32) [000879] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000872] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000393] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N003 ( 3, 3) [000871] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000392] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000882] ----G------- | | \--* ADDR byref $82 N015 ( 11, 11) [000394] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000878] -------N---- | | \--* ADD byref $82 N005 ( 1, 1) [000869] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000877] -------N---- | | \--* ADD long $329 N011 ( 8, 8) [000875] -------N---- | | +--* LSH long $328 N009 ( 7, 7) [000881] ------------ | | | +--* MUL long $327 N007 ( 2, 3) [000873] ------------ | | | | +--* CAST long <- int $326 N006 ( 1, 1) [000870] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 $3c2 N008 ( 1, 1) [000880] ------------ | | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000874] -------N---- | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000876] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000867] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N021 ( 1, 1) [000397] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 finish(BB24). Succ(BB25). Not yet completed. All preds complete, adding to allDone. Succ(BB26). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#31) at start of BB25 is $4c0 {4c0} The SSA definition for GcHeap (#31) at start of BB25 is $4c0 {4c0} ***** BB25, STMT00069(before) N035 ( 67, 59) [000428] --CXG------- * JTRUE void N034 ( 65, 57) [000427] J-CXG--N---- \--* NE int N032 ( 63, 55) [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals N031 ( 9, 8) [000908] n--X-------- control expr | \--* IND long N030 ( 7, 6) [000907] ---X---N---- | \--* ADD long N028 ( 6, 5) [000905] #--X-------- | +--* IND long N027 ( 4, 3) [000904] ---X---N---- | | \--* ADD long N025 ( 3, 2) [000902] #--X-------- | | +--* IND long N024 ( 1, 1) [000901] ------------ | | | \--* LCL_VAR ref V12 loc8 u:1 N026 ( 1, 1) [000903] ------------ | | \--* CNS_INT int 72 N029 ( 1, 1) [000906] ------------ | \--* CNS_INT int 32 N021 ( 32, 34) [000893] ---XG------- arg1 in rdx | +--* COMMA ref N007 ( 8, 11) [000886] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N004 ( 1, 1) [000420] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 N006 ( 3, 3) [000885] ---X-------- | | | \--* ARR_LENGTH int N005 ( 1, 1) [000419] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N020 ( 24, 23) [000897] *---G------- | | \--* IND ref N019 ( 21, 21) [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] $80 N018 ( 11, 11) [000421] a---G--N---- | | \--* IND struct N017 ( 10, 10) [000892] -------N---- | | \--* ADD byref N008 ( 1, 1) [000883] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N016 ( 9, 9) [000891] -------N---- | | \--* ADD long N014 ( 8, 8) [000889] -------N---- | | +--* LSH long N012 ( 7, 7) [000895] ------------ | | | +--* MUL long N010 ( 2, 3) [000887] ------------ | | | | +--* CAST long <- int N009 ( 1, 1) [000884] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 N011 ( 1, 1) [000894] ------------ | | | | \--* CNS_INT long 3 N013 ( 1, 1) [000888] -------N---- | | | \--* CNS_INT long 3 N015 ( 1, 1) [000890] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N022 ( 1, 1) [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 u:1 N023 ( 1, 1) [000424] ------------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 u:1 N033 ( 1, 1) [000426] ------------ \--* CNS_INT int 0 N001 [000899] ARGPLACE => $4c1 {4c1} N002 [000898] ARGPLACE => $4c2 {4c2} N003 [000900] ARGPLACE => $4c3 {4c3} N004 [000420] LCL_VAR V09 loc5 u:4 => $3c2 {PhiDef($9, $4, $1b1)} N005 [000419] LCL_VAR V04 loc0 u:1 => N006 [000885] ARR_LENGTH => N007 [000886] ARR_BOUNDS_CHECK_Rng => N008 [000883] LCL_VAR V04 loc0 u:1 => N009 [000884] LCL_VAR V09 loc5 u:4 => $3c2 {PhiDef($9, $4, $1b1)} VNForCastOper(long) is $d6 N010 [000887] CAST => $326 {Cast($3c2, $d6)} N011 [000894] CNS_INT 3 => $24b {LngCns: 3} N012 [000895] MUL => $327 {MUL($24b, $326)} N013 [000888] CNS_INT 3 => $24b {LngCns: 3} N014 [000889] LSH => $328 {LSH($327, $24b)} N015 [000890] CNS_INT 16 Fseq[#FirstElem] => $241 {LngCns: 16} N016 [000891] ADD => $329 {ADD($241, $328)} N017 [000892] ADD => VNForHandle(arrElemType: Entry[__Canon,__Canon]) is $40 Relabeled IND_ARR_INDEX address node [000892] with l:$82: {PtrToArrElem($40, $2d3, $326, $0)} VNForMapSelect($4c0, $40):ref returns $45a {$4c0[$40]} VNForMapSelect($45a, $2d3):ref returns $45b {$45a[$2d3]} VNForMapSelect($45b, $326):struct returns $500 {$45b[$326]} hAtArrType $45a is MapSelect(curGcHeap($4c0), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $45b is MapSelect(hAtArrType($45a), arr=$2d3). wholeElem $500 is MapSelect(hAtArrTypeAtArr($45b), ind=$326). N018 [000421] IND => FieldSeq {key} is $45d N019 [000896] ADDR => $84 {PtrToArrElem($40, $2d3, $326, $45d)} VNForMapSelect($4c0, $40):ref returns $45a {$4c0[$40]} VNForMapSelect($45a, $2d3):ref returns $45b {$45a[$2d3]} VNForMapSelect($45b, $326):struct returns $500 {$45b[$326]} hAtArrType $45a is MapSelect(curGcHeap($4c0), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $45b is MapSelect(hAtArrType($45a), arr=$2d3). wholeElem $500 is MapSelect(hAtArrTypeAtArr($45b), ind=$326). VNApplySelectors: VNForHandle(key) is $51, fieldType is ref VNForMapSelect($500, $51):ref returns $45e {$500[$51]} selectedElem is $45e after applying selectors. N020 [000897] IND => N021 [000893] COMMA => N022 [000418] LCL_VAR V12 loc8 u:1 => $223 {223} N023 [000424] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} N024 [000901] LCL_VAR V12 loc8 u:1 => $223 {223} VNForMapSelect($2, $223):ref returns $461 {$VN.ReadOnlyHeap[$223]} VNForMapSelect($2, $223):ref returns $461 {$VN.ReadOnlyHeap[$223]} N025 [000902] IND => $463 {norm=$461 {$VN.ReadOnlyHeap[$223]}, exc=$462 {NullPtrExc($223)}} N026 [000903] CNS_INT 72 => $c9 {IntCns 72} N027 [000904] ADD => $32c {norm=$32b {ADD($c9, $461)}, exc=$462 {NullPtrExc($223)}} VNForMapSelect($2, $32b):ref returns $464 {$VN.ReadOnlyHeap[$32b]} VNForMapSelect($2, $32b):ref returns $464 {$VN.ReadOnlyHeap[$32b]} N028 [000905] IND => $465 {norm=$464 {$VN.ReadOnlyHeap[$32b]}, exc=$462 {NullPtrExc($223)}} N029 [000906] CNS_INT 32 => $d2 {IntCns 32} N030 [000907] ADD => $32e {norm=$32d {ADD($d2, $464)}, exc=$462 {NullPtrExc($223)}} N031 [000908] IND => VN of ARGPLACE tree [000898] updated to $223 {223} VN of ARGPLACE tree [000900] updated to fgCurMemoryVN[GcHeap] assigned for CALL at [000425] to VN: $4c5. N032 [000425] CALLV vt-ind => $581 {581} N033 [000426] CNS_INT 0 => $c0 {IntCns 0} N034 [000427] NE => $1bd {NE($581, $c0)} ***** BB25, STMT00069(after) N035 ( 67, 59) [000428] --CXG------- * JTRUE void N034 ( 65, 57) [000427] J-CXG--N---- \--* NE int $1bd N032 ( 63, 55) [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals $581 N031 ( 9, 8) [000908] n--X-------- control expr | \--* IND long N030 ( 7, 6) [000907] ---X---N---- | \--* ADD long $32e N028 ( 6, 5) [000905] #--X-------- | +--* IND long $465 N027 ( 4, 3) [000904] ---X---N---- | | \--* ADD long $32c N025 ( 3, 2) [000902] #--X-------- | | +--* IND long $463 N024 ( 1, 1) [000901] ------------ | | | \--* LCL_VAR ref V12 loc8 u:1 $223 N026 ( 1, 1) [000903] ------------ | | \--* CNS_INT int 72 $c9 N029 ( 1, 1) [000906] ------------ | \--* CNS_INT int 32 $d2 N021 ( 32, 34) [000893] ---XG------- arg1 in rdx | +--* COMMA ref N007 ( 8, 11) [000886] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N004 ( 1, 1) [000420] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N006 ( 3, 3) [000885] ---X-------- | | | \--* ARR_LENGTH int N005 ( 1, 1) [000419] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N020 ( 24, 23) [000897] *---G------- | | \--* IND ref N019 ( 21, 21) [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] $84 N018 ( 11, 11) [000421] a---G--N---- | | \--* IND struct N017 ( 10, 10) [000892] -------N---- | | \--* ADD byref $82 N008 ( 1, 1) [000883] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N016 ( 9, 9) [000891] -------N---- | | \--* ADD long $329 N014 ( 8, 8) [000889] -------N---- | | +--* LSH long $328 N012 ( 7, 7) [000895] ------------ | | | +--* MUL long $327 N010 ( 2, 3) [000887] ------------ | | | | +--* CAST long <- int $326 N009 ( 1, 1) [000884] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 $3c2 N011 ( 1, 1) [000894] ------------ | | | | \--* CNS_INT long 3 $24b N013 ( 1, 1) [000888] -------N---- | | | \--* CNS_INT long 3 $24b N015 ( 1, 1) [000890] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N022 ( 1, 1) [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 u:1 $223 N023 ( 1, 1) [000424] ------------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 u:1 $101 N033 ( 1, 1) [000426] ------------ \--* CNS_INT int 0 $c0 finish(BB25). Succ(BB26). Not yet completed. All preds complete, adding to allDone. Succ(BB28). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#33) at start of BB28 is $4c5 {4c5} The SSA definition for GcHeap (#33) at start of BB28 is $4c5 {4c5} ***** BB28, STMT00070(before) N005 ( 7, 8) [000432] ------------ * JTRUE void N004 ( 5, 6) [000431] N------N-U-- \--* NE int N002 ( 3, 4) [000909] ------------ +--* CAST int <- ubyte <- int N001 ( 2, 2) [000429] ------------ | \--* LCL_VAR int V03 arg3 u:1 N003 ( 1, 1) [000430] ------------ \--* CNS_INT int 1 N001 [000429] LCL_VAR V03 arg3 u:1 => $140 {InitVal($c3)} VNForCastOper(ubyte) is $d8 N002 [000909] CAST => $1be {Cast($140, $d8)} N003 [000430] CNS_INT 1 => $c1 {IntCns 1} N004 [000431] NE => $1bf {NE($1be, $c1)} ***** BB28, STMT00070(after) N005 ( 7, 8) [000432] ------------ * JTRUE void N004 ( 5, 6) [000431] N------N-U-- \--* NE int $1bf N002 ( 3, 4) [000909] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000429] ------------ | \--* LCL_VAR int V03 arg3 u:1 $140 N003 ( 1, 1) [000430] ------------ \--* CNS_INT int 1 $c1 finish(BB28). Succ(BB29). Not yet completed. All preds complete, adding to allDone. Succ(BB30). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#33) at start of BB30 is $4c5 {4c5} The SSA definition for GcHeap (#33) at start of BB30 is $4c5 {4c5} ***** BB30, STMT00071(before) N005 ( 7, 8) [000436] ------------ * JTRUE void N004 ( 5, 6) [000435] N------N-U-- \--* EQ int N002 ( 3, 4) [000926] ------------ +--* CAST int <- ubyte <- int N001 ( 2, 2) [000433] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) N003 ( 1, 1) [000434] ------------ \--* CNS_INT int 2 N001 [000433] LCL_VAR V03 arg3 u:1 (last use) => $140 {InitVal($c3)} VNForCastOper(ubyte) is $d8 N002 [000926] CAST => $1be {Cast($140, $d8)} N003 [000434] CNS_INT 2 => $c2 {IntCns 2} N004 [000435] EQ => $600 {EQ($1be, $c2)} ***** BB30, STMT00071(after) N005 ( 7, 8) [000436] ------------ * JTRUE void N004 ( 5, 6) [000435] N------N-U-- \--* EQ int $600 N002 ( 3, 4) [000926] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000433] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) $140 N003 ( 1, 1) [000434] ------------ \--* CNS_INT int 2 $c2 finish(BB30). Succ(BB31). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. Succ(BB60). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#33) at start of BB60 is $4c5 {4c5} The SSA definition for GcHeap (#33) at start of BB60 is $4c5 {4c5} ***** BB60, STMT00073(before) N004 ( 7, 5) [000444] -A-X----R--- * ASG long N003 ( 3, 2) [000443] D------N---- +--* LCL_VAR long V26 tmp12 d:1 N002 ( 3, 2) [000442] #--X-------- \--* IND long N001 ( 1, 1) [000441] !----------- \--* LCL_VAR ref V00 this u:1 N001 [000441] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} VNForMapSelect($2, $100):ref returns $2e7 {$VN.ReadOnlyHeap[$100]} VNForMapSelect($2, $100):ref returns $2e7 {$VN.ReadOnlyHeap[$100]} N002 [000442] IND => $2e8 {norm=$2e7 {$VN.ReadOnlyHeap[$100]}, exc=$2c2 {NullPtrExc($100)}} N003 [000443] LCL_VAR V26 tmp12 d:1 => $2e7 {$VN.ReadOnlyHeap[$100]} N004 [000444] ASG => $2e8 {norm=$2e7 {$VN.ReadOnlyHeap[$100]}, exc=$2c2 {NullPtrExc($100)}} ***** BB60, STMT00073(after) N004 ( 7, 5) [000444] -A-X----R--- * ASG long $2e8 N003 ( 3, 2) [000443] D------N---- +--* LCL_VAR long V26 tmp12 d:1 $2e7 N002 ( 3, 2) [000442] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000441] !----------- \--* LCL_VAR ref V00 this u:1 $100 --------- ***** BB60, STMT00155(before) N011 ( 16, 14) [001158] ------------ * JTRUE void N010 ( 14, 12) [000460] J------N---- \--* EQ int N008 ( 12, 10) [000456] n----------- +--* IND long N007 ( 10, 8) [000452] -------N---- | \--* ADD long N005 ( 9, 7) [000450] #----------- | +--* IND long N004 ( 6, 5) [000449] #----------- | | \--* IND long N003 ( 4, 3) [000448] -------N---- | | \--* ADD long N001 ( 3, 2) [000446] ------------ | | +--* LCL_VAR long V26 tmp12 u:1 N002 ( 1, 1) [000447] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000451] ------------ | \--* CNS_INT long 56 N009 ( 1, 1) [000459] ------------ \--* CNS_INT long 0 N001 [000446] LCL_VAR V26 tmp12 u:1 => $2e7 {$VN.ReadOnlyHeap[$100]} N002 [000447] CNS_INT 56 => $244 {LngCns: 56} N003 [000448] ADD => $306 {ADD($244, $2e7)} VNForMapSelect($2, $306):ref returns $2e9 {$VN.ReadOnlyHeap[$306]} VNForMapSelect($2, $306):ref returns $2e9 {$VN.ReadOnlyHeap[$306]} N004 [000449] IND => $2e9 {$VN.ReadOnlyHeap[$306]} VNForMapSelect($2, $2e9):ref returns $2ea {$VN.ReadOnlyHeap[$2e9]} VNForMapSelect($2, $2e9):ref returns $2ea {$VN.ReadOnlyHeap[$2e9]} N005 [000450] IND => $2ea {$VN.ReadOnlyHeap[$2e9]} N006 [000451] CNS_INT 56 => $244 {LngCns: 56} N007 [000452] ADD => $331 {ADD($244, $2ea)} N008 [000456] IND => N009 [000459] CNS_INT 0 => $243 {LngCns: 0} N010 [000460] EQ => ***** BB60, STMT00155(after) N011 ( 16, 14) [001158] ------------ * JTRUE void N010 ( 14, 12) [000460] J------N---- \--* EQ int N008 ( 12, 10) [000456] n----------- +--* IND long N007 ( 10, 8) [000452] -------N---- | \--* ADD long $331 N005 ( 9, 7) [000450] #----------- | +--* IND long $2ea N004 ( 6, 5) [000449] #----------- | | \--* IND long $2e9 N003 ( 4, 3) [000448] -------N---- | | \--* ADD long $306 N001 ( 3, 2) [000446] ------------ | | +--* LCL_VAR long V26 tmp12 u:1 $2e7 N002 ( 1, 1) [000447] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000451] ------------ | \--* CNS_INT long 56 $244 N009 ( 1, 1) [000459] ------------ \--* CNS_INT long 0 $243 finish(BB60). Succ(BB61). Not yet completed. All preds complete, adding to allDone. Succ(BB62). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#33) at start of BB62 is $4c5 {4c5} The SSA definition for GcHeap (#33) at start of BB62 is $4c5 {4c5} ***** BB62, STMT00157(before) N007 ( 23, 22) [001162] -AC-G---R--- * ASG long N006 ( 3, 2) [001161] D------N---- +--* LCL_VAR long V28 tmp14 d:2 N005 ( 19, 19) [000458] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 3, 2) [000445] ------?----- arg0 in rcx +--* LCL_VAR long V26 tmp12 u:1 (last use) N004 ( 2, 10) [000457] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr N001 [000927] ARGPLACE => $395 {395} N002 [000928] ARGPLACE => $396 {396} N003 [000445] LCL_VAR V26 tmp12 u:1 (last use) => $2e7 {$VN.ReadOnlyHeap[$100]} N004 [000457] CNS_INT(h) 0xd1ffab1e global ptr => $52 {Hnd const: 0x00000000D1FFAB1E} VN of ARGPLACE tree [000927] updated to $2e7 {$VN.ReadOnlyHeap[$100]} VN of ARGPLACE tree [000928] updated to $52 {Hnd const: 0x00000000D1FFAB1E} N005 [000458] CALL help => $332 {RuntimeHandleClass($2e7, $52)} N006 [001161] LCL_VAR V28 tmp14 d:2 => $332 {RuntimeHandleClass($2e7, $52)} N007 [001162] ASG => $332 {RuntimeHandleClass($2e7, $52)} ***** BB62, STMT00157(after) N007 ( 23, 22) [001162] -AC-G---R--- * ASG long $332 N006 ( 3, 2) [001161] D------N---- +--* LCL_VAR long V28 tmp14 d:2 $332 N005 ( 19, 19) [000458] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 N003 ( 3, 2) [000445] ------?----- arg0 in rcx +--* LCL_VAR long V26 tmp12 u:1 (last use) $2e7 N004 ( 2, 10) [000457] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $52 finish(BB62). Succ(BB63). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#33) at start of BB61 is $4c5 {4c5} The SSA definition for GcHeap (#33) at start of BB61 is $4c5 {4c5} ***** BB61, STMT00156(before) N010 ( 16, 13) [001160] -A------R--- * ASG long N009 ( 3, 2) [001159] D------N---- +--* LCL_VAR long V28 tmp14 d:3 N008 ( 12, 10) [000461] n-----?----- \--* IND long N007 ( 10, 8) [000462] ------?N---- \--* ADD long N005 ( 9, 7) [000463] #-----?----- +--* IND long N004 ( 6, 5) [000464] #-----?----- | \--* IND long N003 ( 4, 3) [000465] ------?N---- | \--* ADD long N001 ( 3, 2) [000466] ------?----- | +--* LCL_VAR long V26 tmp12 u:1 (last use) N002 ( 1, 1) [000467] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000468] ------?----- \--* CNS_INT long 56 N001 [000466] LCL_VAR V26 tmp12 u:1 (last use) => $2e7 {$VN.ReadOnlyHeap[$100]} N002 [000467] CNS_INT 56 => $244 {LngCns: 56} N003 [000465] ADD => $306 {ADD($244, $2e7)} VNForMapSelect($2, $306):ref returns $2e9 {$VN.ReadOnlyHeap[$306]} VNForMapSelect($2, $306):ref returns $2e9 {$VN.ReadOnlyHeap[$306]} N004 [000464] IND => $2e9 {$VN.ReadOnlyHeap[$306]} VNForMapSelect($2, $2e9):ref returns $2ea {$VN.ReadOnlyHeap[$2e9]} VNForMapSelect($2, $2e9):ref returns $2ea {$VN.ReadOnlyHeap[$2e9]} N005 [000463] IND => $2ea {$VN.ReadOnlyHeap[$2e9]} N006 [000468] CNS_INT 56 => $244 {LngCns: 56} N007 [000462] ADD => $331 {ADD($244, $2ea)} N008 [000461] IND => N009 [001159] LCL_VAR V28 tmp14 d:3 => N010 [001160] ASG => ***** BB61, STMT00156(after) N010 ( 16, 13) [001160] -A------R--- * ASG long N009 ( 3, 2) [001159] D------N---- +--* LCL_VAR long V28 tmp14 d:3 N008 ( 12, 10) [000461] n-----?----- \--* IND long N007 ( 10, 8) [000462] ------?N---- \--* ADD long $331 N005 ( 9, 7) [000463] #-----?----- +--* IND long $2ea N004 ( 6, 5) [000464] #-----?----- | \--* IND long $2e9 N003 ( 4, 3) [000465] ------?N---- | \--* ADD long $306 N001 ( 3, 2) [000466] ------?----- | +--* LCL_VAR long V26 tmp12 u:1 (last use) $2e7 N002 ( 1, 1) [000467] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000468] ------?----- \--* CNS_INT long 56 $244 finish(BB61). Succ(BB63). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 28/1 to $347 {PhiDef($1c, $1, $309)} . The SSA definition for ByrefExposed (#33) at start of BB63 is $4c5 {4c5} The SSA definition for GcHeap (#33) at start of BB63 is $4c5 {4c5} ***** BB63, STMT00076(before) N005 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException N003 ( 3, 2) [000473] ------------ arg0 in rcx +--* LCL_VAR long V28 tmp14 u:1 (last use) N004 ( 1, 1) [000455] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) N001 [000929] ARGPLACE => $39a {39a} N002 [000930] ARGPLACE => $226 {226} N003 [000473] LCL_VAR V28 tmp14 u:1 (last use) => $347 {PhiDef($1c, $1, $309)} N004 [000455] LCL_VAR V01 arg1 u:1 (last use) => $101 {InitVal($c1)} VN of ARGPLACE tree [000929] updated to $347 {PhiDef($1c, $1, $309)} VN of ARGPLACE tree [000930] updated to $101 {InitVal($c1)} fgCurMemoryVN[GcHeap] assigned for CALL at [000440] to VN: $227. N005 [000440] CALL => $VN.Void ***** BB63, STMT00076(after) N005 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void N003 ( 3, 2) [000473] ------------ arg0 in rcx +--* LCL_VAR long V28 tmp14 u:1 (last use) $347 N004 ( 1, 1) [000455] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) $101 finish(BB63). The SSA definition for ByrefExposed (#33) at start of BB29 is $4c5 {4c5} The SSA definition for GcHeap (#33) at start of BB29 is $4c5 {4c5} ***** BB29, STMT00077(before) N022 ( 34, 37) [000481] -A-XG------- * ASG ref N020 ( 32, 35) [000480] *--XG--N---- +--* IND ref N019 ( 30, 33) [000911] ---XG--N---- | \--* ADD byref N017 ( 29, 32) [000922] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000915] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000476] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 N003 ( 3, 3) [000914] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000475] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000925] ----G------- | | \--* ADDR byref N015 ( 11, 11) [000477] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000921] -------N---- | | \--* ADD byref N005 ( 1, 1) [000912] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 (last use) N013 ( 9, 9) [000920] -------N---- | | \--* ADD long N011 ( 8, 8) [000918] -------N---- | | +--* LSH long N009 ( 7, 7) [000924] ------------ | | | +--* MUL long N007 ( 2, 3) [000916] ------------ | | | | +--* CAST long <- int N006 ( 1, 1) [000913] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 (last use) N008 ( 1, 1) [000923] ------------ | | | | \--* CNS_INT long 3 N010 ( 1, 1) [000917] -------N---- | | | \--* CNS_INT long 3 N012 ( 1, 1) [000919] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000910] ------------ | \--* CNS_INT long 8 field offset Fseq[value] N021 ( 1, 1) [000479] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) N001 [000476] LCL_VAR V09 loc5 u:4 => $3c2 {PhiDef($9, $4, $1b1)} N002 [000475] LCL_VAR V04 loc0 u:1 => N003 [000914] ARR_LENGTH => N004 [000915] ARR_BOUNDS_CHECK_Rng => N005 [000912] LCL_VAR V04 loc0 u:1 (last use) => N006 [000913] LCL_VAR V09 loc5 u:4 (last use) => $3c2 {PhiDef($9, $4, $1b1)} VNForCastOper(long) is $d6 N007 [000916] CAST => $326 {Cast($3c2, $d6)} N008 [000923] CNS_INT 3 => $24b {LngCns: 3} N009 [000924] MUL => $327 {MUL($24b, $326)} N010 [000917] CNS_INT 3 => $24b {LngCns: 3} N011 [000918] LSH => $328 {LSH($327, $24b)} N012 [000919] CNS_INT 16 Fseq[#FirstElem] => $241 {LngCns: 16} N013 [000920] ADD => $329 {ADD($241, $328)} N014 [000921] ADD => VNForHandle(arrElemType: Entry[__Canon,__Canon]) is $40 Relabeled IND_ARR_INDEX address node [000921] with l:$82: {PtrToArrElem($40, $2d3, $326, $0)} VNForMapSelect($4c5, $40):ref returns $466 {$4c5[$40]} VNForMapSelect($466, $2d3):ref returns $467 {$466[$2d3]} VNForMapSelect($467, $326):struct returns $501 {$467[$326]} hAtArrType $466 is MapSelect(curGcHeap($4c5), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $467 is MapSelect(hAtArrType($466), arr=$2d3). wholeElem $501 is MapSelect(hAtArrTypeAtArr($467), ind=$326). N015 [000477] IND => N016 [000925] ADDR => $82 {PtrToArrElem($40, $2d3, $326, $0)} N017 [000922] COMMA => N018 [000910] CNS_INT 8 field offset Fseq[value] => $240 {LngCns: 8} FieldSeq {value} is $468 N019 [000911] ADD => $28d {norm=$85 {PtrToArrElem($40, $2d3, $326, $468)}, exc=$457( {NullPtrExc($2d3)}, {IndexOutOfRangeExc($3c2, $403)})} N021 [000479] LCL_VAR V02 arg2 u:1 (last use) => $102 {InitVal($c2)} Tree [000481] assigns to an array element: VNForMapSelect($4c5, $40):ref returns $466 {$4c5[$40]} VNForMapSelect($466, $2d3):ref returns $467 {$466[$2d3]} VNForMapSelect($467, $326):struct returns $501 {$467[$326]} VNApplySelectorsAssign: VNForHandle(value) is $53, fieldType is ref VNForMapStore($501, $53, $102):ref returns $680 {$501[$53 := $102]} VNForMapStore($467, $326, $680):ref returns $681 {$467[$326 := $680]} VNForMapStore($466, $2d3, $681):ref returns $682 {$466[$2d3 := $681]} hAtArrType $466 is MapSelect(curGcHeap($4c5), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $467 is MapSelect(hAtArrType($466), arr=$2d3) hAtArrTypeAtArrAtInx $501 is MapSelect(hAtArrTypeAtArr($467), inx=$326):struct newValAtInd $680 is {$501[$53 := $102]} newValAtArr $681 is {$467[$326 := $680]} newValAtArrType $682 is {$466[$2d3 := $681]} VNForMapStore($4c5, $40, $682):ref returns $683 {$4c5[$40 := $682]} fgCurMemoryVN[GcHeap] assigned for ArrIndexAssign (case 1) at [000481] to VN: $683. N022 [000481] ASG => $VN.Void ***** BB29, STMT00077(after) N022 ( 34, 37) [000481] -A-XG------- * ASG ref $VN.Void N020 ( 32, 35) [000480] *--XG--N---- +--* IND ref $102 N019 ( 30, 33) [000911] ---XG--N---- | \--* ADD byref $28d N017 ( 29, 32) [000922] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000915] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000476] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N003 ( 3, 3) [000914] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000475] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000925] ----G------- | | \--* ADDR byref $82 N015 ( 11, 11) [000477] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000921] -------N---- | | \--* ADD byref $82 N005 ( 1, 1) [000912] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 (last use) N013 ( 9, 9) [000920] -------N---- | | \--* ADD long $329 N011 ( 8, 8) [000918] -------N---- | | +--* LSH long $328 N009 ( 7, 7) [000924] ------------ | | | +--* MUL long $327 N007 ( 2, 3) [000916] ------------ | | | | +--* CAST long <- int $326 N006 ( 1, 1) [000913] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 (last use) $3c2 N008 ( 1, 1) [000923] ------------ | | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000917] -------N---- | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000919] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000910] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N021 ( 1, 1) [000479] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 finish(BB29). Succ(BB58). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. Building phi application: $d9 = SSA# 33. Building phi application: $da = SSA# 31. Building phi application: $469 = phi($da, $d9). The SSA definition for GcHeap (#32) at start of BB26 is $46a {PhiMemoryDef($54, $469)} ***** BB26, STMT00065(before) N022 ( 32, 35) [000406] -A-XG---R--- * ASG int N021 ( 1, 1) [000405] D------N---- +--* LCL_VAR int V09 loc5 d:5 N020 ( 32, 35) [000404] *--XG------- \--* IND int N019 ( 30, 33) [000932] ---XG--N---- \--* ADD byref N017 ( 29, 32) [000943] ---XG------- +--* COMMA byref $80 N004 ( 8, 11) [000936] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000401] ------------ | | +--* LCL_VAR int V09 loc5 u:4 N003 ( 3, 3) [000935] ---X-------- | | \--* ARR_LENGTH int N002 ( 1, 1) [000400] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000946] ----G------- | \--* ADDR byref $80 N015 ( 11, 11) [000402] a---G--N---- | \--* IND struct N014 ( 10, 10) [000942] -------N---- | \--* ADD byref N005 ( 1, 1) [000933] ------------ | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000941] -------N---- | \--* ADD long N011 ( 8, 8) [000939] -------N---- | +--* LSH long N009 ( 7, 7) [000945] ------------ | | +--* MUL long N007 ( 2, 3) [000937] ------------ | | | +--* CAST long <- int N006 ( 1, 1) [000934] i----------- | | | | \--* LCL_VAR int V09 loc5 u:4 (last use) N008 ( 1, 1) [000944] ------------ | | | \--* CNS_INT long 3 N010 ( 1, 1) [000938] -------N---- | | \--* CNS_INT long 3 N012 ( 1, 1) [000940] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000931] ------------ \--* CNS_INT long 20 field offset Fseq[next] N001 [000401] LCL_VAR V09 loc5 u:4 => $3c2 {PhiDef($9, $4, $1b1)} N002 [000400] LCL_VAR V04 loc0 u:1 => N003 [000935] ARR_LENGTH => N004 [000936] ARR_BOUNDS_CHECK_Rng => N005 [000933] LCL_VAR V04 loc0 u:1 => N006 [000934] LCL_VAR V09 loc5 u:4 (last use) => $3c2 {PhiDef($9, $4, $1b1)} VNForCastOper(long) is $d6 N007 [000937] CAST => $326 {Cast($3c2, $d6)} N008 [000944] CNS_INT 3 => $24b {LngCns: 3} N009 [000945] MUL => $327 {MUL($24b, $326)} N010 [000938] CNS_INT 3 => $24b {LngCns: 3} N011 [000939] LSH => $328 {LSH($327, $24b)} N012 [000940] CNS_INT 16 Fseq[#FirstElem] => $241 {LngCns: 16} N013 [000941] ADD => $329 {ADD($241, $328)} N014 [000942] ADD => VNForHandle(arrElemType: Entry[__Canon,__Canon]) is $40 Relabeled IND_ARR_INDEX address node [000942] with l:$82: {PtrToArrElem($40, $2d3, $326, $0)} VNForMapSelect($46a, $40):ref returns $46b {$46a[$40]} VNForMapSelect($46b, $2d3):ref returns $46c {$46b[$2d3]} VNForMapSelect($46c, $326):struct returns $502 {$46c[$326]} hAtArrType $46b is MapSelect(curGcHeap($46a), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $46c is MapSelect(hAtArrType($46b), arr=$2d3). wholeElem $502 is MapSelect(hAtArrTypeAtArr($46c), ind=$326). N015 [000402] IND => N016 [000946] ADDR => $82 {PtrToArrElem($40, $2d3, $326, $0)} N017 [000943] COMMA => N018 [000931] CNS_INT 20 field offset Fseq[next] => $24c {LngCns: 20} FieldSeq {next} is $46d N019 [000932] ADD => $28e {norm=$86 {PtrToArrElem($40, $2d3, $326, $46d)}, exc=$457( {NullPtrExc($2d3)}, {IndexOutOfRangeExc($3c2, $403)})} VNForMapSelect($46a, $40):ref returns $46b {$46a[$40]} VNForMapSelect($46b, $2d3):ref returns $46c {$46b[$2d3]} VNForMapSelect($46c, $326):struct returns $502 {$46c[$326]} hAtArrType $46b is MapSelect(curGcHeap($46a), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $46c is MapSelect(hAtArrType($46b), arr=$2d3). wholeElem $502 is MapSelect(hAtArrTypeAtArr($46c), ind=$326). VNApplySelectors: VNForHandle(next) is $55, fieldType is int VNForMapSelect($502, $55):int returns $603 {$502[$55]} selectedElem is $604 after applying selectors. N020 [000404] IND => N021 [000405] LCL_VAR V09 loc5 d:5 => N022 [000406] ASG => ***** BB26, STMT00065(after) N022 ( 32, 35) [000406] -A-XG---R--- * ASG int N021 ( 1, 1) [000405] D------N---- +--* LCL_VAR int V09 loc5 d:5 N020 ( 32, 35) [000404] *--XG------- \--* IND int N019 ( 30, 33) [000932] ---XG--N---- \--* ADD byref $28e N017 ( 29, 32) [000943] ---XG------- +--* COMMA byref N004 ( 8, 11) [000936] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000401] ------------ | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N003 ( 3, 3) [000935] ---X-------- | | \--* ARR_LENGTH int N002 ( 1, 1) [000400] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000946] ----G------- | \--* ADDR byref $82 N015 ( 11, 11) [000402] a---G--N---- | \--* IND struct N014 ( 10, 10) [000942] -------N---- | \--* ADD byref $82 N005 ( 1, 1) [000933] ------------ | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000941] -------N---- | \--* ADD long $329 N011 ( 8, 8) [000939] -------N---- | +--* LSH long $328 N009 ( 7, 7) [000945] ------------ | | +--* MUL long $327 N007 ( 2, 3) [000937] ------------ | | | +--* CAST long <- int $326 N006 ( 1, 1) [000934] i----------- | | | | \--* LCL_VAR int V09 loc5 u:4 (last use) $3c2 N008 ( 1, 1) [000944] ------------ | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000938] -------N---- | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000940] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000931] ------------ \--* CNS_INT long 20 field offset Fseq[next] $24c --------- ***** BB26, STMT00066(before) N005 ( 3, 3) [000411] -A------R--- * ASG int N004 ( 1, 1) [000410] D------N---- +--* LCL_VAR int V07 loc3 d:6 N003 ( 3, 3) [000409] ------------ \--* ADD int N001 ( 1, 1) [000407] ------------ +--* LCL_VAR int V07 loc3 u:5 (last use) N002 ( 1, 1) [000408] ------------ \--* CNS_INT int 1 N001 [000407] LCL_VAR V07 loc3 u:5 (last use) => $3c1 {PhiDef($7, $5, $1b0)} N002 [000408] CNS_INT 1 => $c1 {IntCns 1} N003 [000409] ADD => $605 {ADD($c1, $3c1)} N004 [000410] LCL_VAR V07 loc3 d:6 => $605 {ADD($c1, $3c1)} N005 [000411] ASG => $605 {ADD($c1, $3c1)} ***** BB26, STMT00066(after) N005 ( 3, 3) [000411] -A------R--- * ASG int $605 N004 ( 1, 1) [000410] D------N---- +--* LCL_VAR int V07 loc3 d:6 $605 N003 ( 3, 3) [000409] ------------ \--* ADD int $605 N001 ( 1, 1) [000407] ------------ +--* LCL_VAR int V07 loc3 u:5 (last use) $3c1 N002 ( 1, 1) [000408] ------------ \--* CNS_INT int 1 $c1 --------- ***** BB26, STMT00067(before) N005 ( 7, 7) [000416] ---X-------- * JTRUE void N004 ( 5, 5) [000415] N--X---N-U-- \--* LT int N002 ( 3, 3) [000414] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000413] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000412] ------------ \--* LCL_VAR int V07 loc3 u:6 N001 [000413] LCL_VAR V04 loc0 u:1 => N002 [000414] ARR_LENGTH => N003 [000412] LCL_VAR V07 loc3 u:6 => $605 {ADD($c1, $3c1)} N004 [000415] LT => ***** BB26, STMT00067(after) N005 ( 7, 7) [000416] ---X-------- * JTRUE void N004 ( 5, 5) [000415] N--X---N-U-- \--* LT int N002 ( 3, 3) [000414] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000413] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000412] ------------ \--* LCL_VAR int V07 loc3 u:6 $605 finish(BB26). Succ(BB27). Not yet completed. All preds complete, adding to allDone. Succ(BB68). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#32) at start of BB27 is $46a {PhiMemoryDef($54, $469)} The SSA definition for GcHeap (#32) at start of BB27 is $46a {PhiMemoryDef($54, $469)} finish(BB27). Succ(BB23). SSA PHI definition: set VN of local 7/3 to $3c3 {PhiDef($7, $3, $60a)} . SSA PHI definition: set VN of local 9/2 to $3c4 {PhiDef($9, $2, $60b)} . Building phi application: $db = SSA# 26. Building phi application: $d8 = SSA# 8. Building phi application: $46e = phi($d8, $db). The SSA definition for GcHeap (#25) at start of BB32 is $46f {PhiMemoryDef($56, $46e)} ***** BB32, STMT00014(before) N005 ( 7, 7) [000066] ---X-------- * JTRUE void N004 ( 5, 5) [000065] N--X---N-U-- \--* LE int N002 ( 3, 3) [000064] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000063] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000062] ------------ \--* LCL_VAR int V09 loc5 u:2 N001 [000063] LCL_VAR V04 loc0 u:1 => N002 [000064] ARR_LENGTH => N003 [000062] LCL_VAR V09 loc5 u:2 => $3c4 {PhiDef($9, $2, $60b)} N004 [000065] LE => ***** BB32, STMT00014(after) N005 ( 7, 7) [000066] ---X-------- * JTRUE void N004 ( 5, 5) [000065] N--X---N-U-- \--* LE int N002 ( 3, 3) [000064] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000063] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000062] ------------ \--* LCL_VAR int V09 loc5 u:2 $3c4 finish(BB32). Succ(BB33). Not yet completed. All preds complete, adding to allDone. Succ(BB44). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 7/2 to $3c5 {PhiDef($7, $2, $610)} . Building phi application: $da = SSA# 31. Building phi application: $dc = SSA# 25. Building phi application: $470 = phi($dc, $da). The SSA definition for GcHeap (#11) at start of BB44 is $471 {PhiMemoryDef($57, $470)} ***** BB44, STMT00015(before) N007 ( 8, 8) [000071] ---XG------- * JTRUE void N006 ( 6, 6) [000070] J--XG--N---- \--* LE int N004 ( 4, 4) [000068] ---XG------- +--* IND int N003 ( 2, 2) [001025] -------N---- | \--* ADD byref N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001024] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] N005 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 N001 [000067] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N002 [001024] CNS_INT 64 field offset Fseq[_freeCount] => $245 {LngCns: 64} N003 [001025] ADD => $28f {ADD($100, $245)} VNApplySelectors: VNForHandle(_freeCount) is $58, fieldType is int VNForMapSelect($471, $58):int returns $61a {$471[$58]} VNForMapSelect($61a, $100):int returns $61b {$61a[$100]} N004 [000068] IND => N005 [000069] CNS_INT 0 => $c0 {IntCns 0} N006 [000070] LE => ***** BB44, STMT00015(after) N007 ( 8, 8) [000071] ---XG------- * JTRUE void N006 ( 6, 6) [000070] J--XG--N---- \--* LE int N004 ( 4, 4) [000068] ---XG------- +--* IND int N003 ( 2, 2) [001025] -------N---- | \--* ADD byref $28f N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001024] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N005 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 $c0 finish(BB44). Succ(BB45). Not yet completed. All preds complete, adding to allDone. Succ(BB48). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#11) at start of BB48 is $471 {PhiMemoryDef($57, $470)} The SSA definition for GcHeap (#11) at start of BB48 is $471 {PhiMemoryDef($57, $470)} ***** BB48, STMT00016(before) N006 ( 8, 7) [000075] -A-XG---R--- * ASG int N005 ( 3, 2) [000074] D------N---- +--* LCL_VAR int V13 loc9 d:1 N004 ( 4, 4) [000073] ---XG------- \--* IND int N003 ( 2, 2) [001085] -------N---- \--* ADD byref N001 ( 1, 1) [000072] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001084] ------------ \--* CNS_INT long 56 field offset Fseq[_count] N001 [000072] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N002 [001084] CNS_INT 56 field offset Fseq[_count] => $244 {LngCns: 56} N003 [001085] ADD => $290 {ADD($100, $244)} VNApplySelectors: VNForHandle(_count) is $59, fieldType is int VNForMapSelect($471, $59):int returns $62b {$471[$59]} VNForMapSelect($62b, $100):int returns $62c {$62b[$100]} N004 [000073] IND => N005 [000074] LCL_VAR V13 loc9 d:1 => N006 [000075] ASG => ***** BB48, STMT00016(after) N006 ( 8, 7) [000075] -A-XG---R--- * ASG int N005 ( 3, 2) [000074] D------N---- +--* LCL_VAR int V13 loc9 d:1 N004 ( 4, 4) [000073] ---XG------- \--* IND int N003 ( 2, 2) [001085] -------N---- \--* ADD byref $290 N001 ( 1, 1) [000072] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001084] ------------ \--* CNS_INT long 56 field offset Fseq[_count] $244 --------- ***** BB48, STMT00017(before) N005 ( 9, 8) [000080] ---X-------- * JTRUE void N004 ( 7, 6) [000079] N--X---N-U-- \--* NE int N002 ( 3, 3) [000078] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000077] ------------ | \--* LCL_VAR ref V04 loc0 u:1 (last use) N003 ( 3, 2) [000076] ------------ \--* LCL_VAR int V13 loc9 u:1 N001 [000077] LCL_VAR V04 loc0 u:1 (last use) => N002 [000078] ARR_LENGTH => N003 [000076] LCL_VAR V13 loc9 u:1 => N004 [000079] NE => ***** BB48, STMT00017(after) N005 ( 9, 8) [000080] ---X-------- * JTRUE void N004 ( 7, 6) [000079] N--X---N-U-- \--* NE int N002 ( 3, 3) [000078] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000077] ------------ | \--* LCL_VAR ref V04 loc0 u:1 (last use) N003 ( 3, 2) [000076] ------------ \--* LCL_VAR int V13 loc9 u:1 finish(BB48). Succ(BB49). Not yet completed. All preds complete, adding to allDone. Succ(BB54). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#11) at start of BB49 is $471 {PhiMemoryDef($57, $470)} The SSA definition for GcHeap (#11) at start of BB49 is $471 {PhiMemoryDef($57, $470)} ***** BB49, STMT00125(before) N014 ( 44, 26) [000705] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize N009 ( 22, 13) [001090] -ACXG---R-L- arg1 SETUP +--* ASG int N008 ( 3, 2) [001089] D------N---- | +--* LCL_VAR int V64 tmp50 d:1 N007 ( 18, 10) [000702] --CXG------- | \--* CALL int System.Collections.HashHelpers.ExpandPrime N006 ( 4, 4) [000701] ---XG------- arg0 in rcx | \--* IND int N005 ( 2, 2) [001087] -------N---- | \--* ADD byref N003 ( 1, 1) [000700] ------------ | +--* LCL_VAR ref V00 this u:1 N004 ( 1, 1) [001086] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] N011 ( 3, 2) [001091] ------------ arg1 in rdx +--* LCL_VAR int V64 tmp50 u:1 (last use) N012 ( 1, 1) [000163] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 N013 ( 1, 1) [000704] ------------ arg2 in r8 \--* CNS_INT int 0 N001 [001092] ARGPLACE => $228 {228} N002 [001088] ARGPLACE => $1d5 {1d5} N003 [000700] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N004 [001086] CNS_INT 56 field offset Fseq[_count] => $244 {LngCns: 56} N005 [001087] ADD => $290 {ADD($100, $244)} VNApplySelectors: VNForHandle(_count) is $59, fieldType is int VNForMapSelect($471, $59):int returns $62b {$471[$59]} VNForMapSelect($62b, $100):int returns $62c {$62b[$100]} N006 [000701] IND => VN of ARGPLACE tree [001088] updated to fgCurMemoryVN[GcHeap] assigned for CALL at [000702] to VN: $229. N007 [000702] CALL => $1d7 {1d7} N008 [001089] LCL_VAR V64 tmp50 d:1 => $1d7 {1d7} N009 [001090] ASG => $1d7 {1d7} N010 [001093] ARGPLACE => $1d9 {1d9} N011 [001091] LCL_VAR V64 tmp50 u:1 (last use) => $1d7 {1d7} N012 [000163] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N013 [000704] CNS_INT 0 => $c0 {IntCns 0} VN of ARGPLACE tree [001093] updated to $1d7 {1d7} fgCurMemoryVN[GcHeap] assigned for CALL at [000705] to VN: $22a. N014 [000705] CALL => $VN.Void ***** BB49, STMT00125(after) N014 ( 44, 26) [000705] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void N009 ( 22, 13) [001090] -ACXG---R-L- arg1 SETUP +--* ASG int $1d7 N008 ( 3, 2) [001089] D------N---- | +--* LCL_VAR int V64 tmp50 d:1 $1d7 N007 ( 18, 10) [000702] --CXG------- | \--* CALL int System.Collections.HashHelpers.ExpandPrime $1d7 N006 ( 4, 4) [000701] ---XG------- arg0 in rcx | \--* IND int N005 ( 2, 2) [001087] -------N---- | \--* ADD byref $290 N003 ( 1, 1) [000700] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N004 ( 1, 1) [001086] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] $244 N011 ( 3, 2) [001091] ------------ arg1 in rdx +--* LCL_VAR int V64 tmp50 u:1 (last use) $1d7 N012 ( 1, 1) [000163] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N013 ( 1, 1) [000704] ------------ arg2 in r8 \--* CNS_INT int 0 $c0 --------- ***** BB49, STMT00126(before) N006 ( 8, 7) [000711] -A-XG---R--- * ASG ref N005 ( 3, 2) [000710] D------N---- +--* LCL_VAR ref V52 tmp38 d:1 N004 ( 4, 4) [000709] ---XG------- \--* IND ref N003 ( 2, 2) [001095] -------N---- \--* ADD byref N001 ( 1, 1) [000165] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001094] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] N001 [000165] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N002 [001094] CNS_INT 8 field offset Fseq[_buckets] => $240 {LngCns: 8} N003 [001095] ADD => $280 {ADD($100, $240)} VNApplySelectors: VNForHandle(_buckets) is $41, fieldType is ref VNForMapSelect($22a, $41):ref returns $472 {$22a[$41]} VNForMapSelect($472, $100):ref returns $473 {$472[$100]} N004 [000709] IND => N005 [000710] LCL_VAR V52 tmp38 d:1 => N006 [000711] ASG => ***** BB49, STMT00126(after) N006 ( 8, 7) [000711] -A-XG---R--- * ASG ref N005 ( 3, 2) [000710] D------N---- +--* LCL_VAR ref V52 tmp38 d:1 N004 ( 4, 4) [000709] ---XG------- \--* IND ref N003 ( 2, 2) [001095] -------N---- \--* ADD byref $280 N001 ( 1, 1) [000165] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001094] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] $240 --------- ***** BB49, STMT00133(before) N004 ( 5, 4) [000760] -A-X----R--- * ASG int N003 ( 1, 1) [000759] D------N---- +--* LCL_VAR int V53 tmp39 d:1 N002 ( 5, 4) [000714] ---X-------- \--* ARR_LENGTH int N001 ( 3, 2) [000713] ------------ \--* LCL_VAR ref V52 tmp38 u:1 N001 [000713] LCL_VAR V52 tmp38 u:1 => N002 [000714] ARR_LENGTH => N003 [000759] LCL_VAR V53 tmp39 d:1 => N004 [000760] ASG => ***** BB49, STMT00133(after) N004 ( 5, 4) [000760] -A-X----R--- * ASG int N003 ( 1, 1) [000759] D------N---- +--* LCL_VAR int V53 tmp39 d:1 N002 ( 5, 4) [000714] ---X-------- \--* ARR_LENGTH int N001 ( 3, 2) [000713] ------------ \--* LCL_VAR ref V52 tmp38 u:1 --------- ***** BB49, STMT00134(before) N006 ( 8, 7) [000762] -A-XG---R--- * ASG long N005 ( 3, 2) [000761] D------N---- +--* LCL_VAR long V54 tmp40 d:1 N004 ( 4, 4) [000716] ---XG------- \--* IND long N003 ( 2, 2) [001097] -------N---- \--* ADD byref N001 ( 1, 1) [000715] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001096] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] N001 [000715] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N002 [001096] CNS_INT 48 field offset Fseq[_fastModMultiplier] => $246 {LngCns: 48} N003 [001097] ADD => $283 {ADD($100, $246)} VNApplySelectors: VNForHandle(_fastModMultiplier) is $4b, fieldType is long VNForMapSelect($22a, $4b):long returns $333 {$22a[$4b]} VNForMapSelect($333, $100):long returns $334 {$333[$100]} N004 [000716] IND => N005 [000761] LCL_VAR V54 tmp40 d:1 => N006 [000762] ASG => ***** BB49, STMT00134(after) N006 ( 8, 7) [000762] -A-XG---R--- * ASG long N005 ( 3, 2) [000761] D------N---- +--* LCL_VAR long V54 tmp40 d:1 N004 ( 4, 4) [000716] ---XG------- \--* IND long N003 ( 2, 2) [001097] -------N---- \--* ADD byref $283 N001 ( 1, 1) [000715] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001096] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 --------- ***** BB49, STMT00136(before) N005 ( 10, 9) [000773] -A------R--- * ASG bool N004 ( 3, 2) [000772] D------N---- +--* LCL_VAR int V56 tmp42 d:1 N003 ( 6, 6) [000730] N--------U-- \--* LE int N001 ( 1, 1) [000728] ------------ +--* LCL_VAR int V53 tmp39 u:1 N002 ( 1, 4) [000729] ------------ \--* CNS_INT int 0x7FFFFFFF N001 [000728] LCL_VAR V53 tmp39 u:1 => N002 [000729] CNS_INT 0x7FFFFFFF => $ce {IntCns 0x7FFFFFFF} N003 [000730] LE => N004 [000772] LCL_VAR V56 tmp42 d:1 => N005 [000773] ASG => ***** BB49, STMT00136(after) N005 ( 10, 9) [000773] -A------R--- * ASG bool N004 ( 3, 2) [000772] D------N---- +--* LCL_VAR int V56 tmp42 d:1 N003 ( 6, 6) [000730] N--------U-- \--* LE int N001 ( 1, 1) [000728] ------------ +--* LCL_VAR int V53 tmp39 u:1 N002 ( 1, 4) [000729] ------------ \--* CNS_INT int 0x7FFFFFFF $ce --------- ***** BB49, STMT00139(before) N004 ( 8, 15) [000783] -A--G---R--- * ASG ref N003 ( 3, 2) [000782] D------N---- +--* LCL_VAR ref V57 tmp43 d:1 N002 ( 4, 12) [000767] #---G------- \--* IND ref N001 ( 2, 10) [000766] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] N001 [000766] CNS_INT(h) 0xD1FFAB1E [ICON_STR_HDL] => $43 {Hnd const: 0x00000000D1FFAB1E} N002 [000767] IND => $105 {NonNullIndirect($43)} N003 [000782] LCL_VAR V57 tmp43 d:1 => $105 {NonNullIndirect($43)} N004 [000783] ASG => $105 {NonNullIndirect($43)} ***** BB49, STMT00139(after) N004 ( 8, 15) [000783] -A--G---R--- * ASG ref $105 N003 ( 3, 2) [000782] D------N---- +--* LCL_VAR ref V57 tmp43 d:1 $105 N002 ( 4, 12) [000767] #---G------- \--* IND ref $105 N001 ( 2, 10) [000766] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 --------- ***** BB49, STMT00140(before) N004 ( 8, 15) [000785] -A--G---R--- * ASG ref N003 ( 3, 2) [000784] D------N---- +--* LCL_VAR ref V58 tmp44 d:1 N002 ( 4, 12) [000769] #---G------- \--* IND ref N001 ( 2, 10) [000768] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] N001 [000768] CNS_INT(h) 0xD1FFAB1E [ICON_STR_HDL] => $43 {Hnd const: 0x00000000D1FFAB1E} N002 [000769] IND => $105 {NonNullIndirect($43)} N003 [000784] LCL_VAR V58 tmp44 d:1 => $105 {NonNullIndirect($43)} N004 [000785] ASG => $105 {NonNullIndirect($43)} ***** BB49, STMT00140(after) N004 ( 8, 15) [000785] -A--G---R--- * ASG ref $105 N003 ( 3, 2) [000784] D------N---- +--* LCL_VAR ref V58 tmp44 d:1 $105 N002 ( 4, 12) [000769] #---G------- \--* IND ref $105 N001 ( 2, 10) [000768] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 --------- ***** BB49, STMT00137(before) N004 ( 7, 6) [000778] ------------ * JTRUE void N003 ( 5, 4) [000777] J------N---- \--* NE int N001 ( 3, 2) [000775] ------------ +--* LCL_VAR int V56 tmp42 u:1 (last use) N002 ( 1, 1) [000776] ------------ \--* CNS_INT int 0 N001 [000775] LCL_VAR V56 tmp42 u:1 (last use) => N002 [000776] CNS_INT 0 => $c0 {IntCns 0} N003 [000777] NE => ***** BB49, STMT00137(after) N004 ( 7, 6) [000778] ------------ * JTRUE void N003 ( 5, 4) [000777] J------N---- \--* NE int N001 ( 3, 2) [000775] ------------ +--* LCL_VAR int V56 tmp42 u:1 (last use) N002 ( 1, 1) [000776] ------------ \--* CNS_INT int 0 $c0 finish(BB49). Succ(BB50). Not yet completed. All preds complete, adding to allDone. Succ(BB51). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#17) at start of BB50 is $22a {22a} The SSA definition for GcHeap (#17) at start of BB50 is $22a {22a} ***** BB50, STMT00138(before) N005 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 3, 2) [000779] ------------ arg0 in rcx +--* LCL_VAR ref V57 tmp43 u:1 (last use) N004 ( 3, 2) [000780] ------------ arg1 in rdx \--* LCL_VAR ref V58 tmp44 u:1 (last use) N001 [001098] ARGPLACE => $22f {22f} N002 [001099] ARGPLACE => $230 {230} N003 [000779] LCL_VAR V57 tmp43 u:1 (last use) => $105 {NonNullIndirect($43)} N004 [000780] LCL_VAR V58 tmp44 u:1 (last use) => $105 {NonNullIndirect($43)} VN of ARGPLACE tree [001098] updated to $105 {NonNullIndirect($43)} VN of ARGPLACE tree [001099] updated to $105 {NonNullIndirect($43)} fgCurMemoryVN[GcHeap] assigned for CALL at [000781] to VN: $231. N005 [000781] CALL => $VN.Void ***** BB50, STMT00138(after) N005 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 3, 2) [000779] ------------ arg0 in rcx +--* LCL_VAR ref V57 tmp43 u:1 (last use) $105 N004 ( 3, 2) [000780] ------------ arg1 in rdx \--* LCL_VAR ref V58 tmp44 u:1 (last use) $105 finish(BB50). Succ(BB51). Not yet completed. All preds complete, adding to allDone. Building phi application: $d1 = SSA# 21. Building phi application: $dd = SSA# 17. Building phi application: $478 = phi($dd, $d1). The SSA definition for GcHeap (#18) at start of BB51 is $479 {PhiMemoryDef($5a, $478)} ***** BB51, STMT00131(before) N016 ( 26, 25) [000750] -A------R--- * ASG int N015 ( 3, 2) [000749] D------N---- +--* LCL_VAR int V55 tmp41 d:1 N014 ( 22, 22) [000748] ------------ \--* CAST int <- uint <- long N013 ( 21, 20) [000747] ------------ \--* RSZ long N011 ( 19, 18) [000745] ------------ +--* MUL long N008 ( 13, 12) [000742] ------------ | +--* ADD long N006 ( 11, 10) [000739] ------------ | | +--* RSZ long N004 ( 9, 8) [000737] ------------ | | | +--* MUL long N001 ( 3, 2) [000735] ------------ | | | | +--* LCL_VAR long V54 tmp40 u:1 (last use) N003 ( 2, 3) [000736] ---------U-- | | | | \--* CAST long <- ulong <- uint N002 ( 1, 1) [000166] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 N005 ( 1, 1) [000738] ------------ | | | \--* CNS_INT int 32 N007 ( 1, 1) [000741] ------------ | | \--* CNS_INT long 1 N010 ( 2, 3) [000744] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000743] ------------ | \--* LCL_VAR int V53 tmp39 u:1 N012 ( 1, 1) [000746] ------------ \--* CNS_INT int 32 N001 [000735] LCL_VAR V54 tmp40 u:1 (last use) => N002 [000166] LCL_VAR V06 loc2 u:1 => $3c0 {PhiDef($f, $1, $309)} VNForCastOper(ulong, unsignedSrc) is $d1 N003 [000736] CAST => $310 {Cast($3c0, $d1)} N004 [000737] MUL => N005 [000738] CNS_INT 32 => $d2 {IntCns 32} N006 [000739] RSZ => N007 [000741] CNS_INT 1 => $247 {LngCns: 1} N008 [000742] ADD => N009 [000743] LCL_VAR V53 tmp39 u:1 => VNForCastOper(ulong, unsignedSrc) is $d1 N010 [000744] CAST => N011 [000745] MUL => N012 [000746] CNS_INT 32 => $d2 {IntCns 32} N013 [000747] RSZ => VNForCastOper(uint) is $d3 N014 [000748] CAST => N015 [000749] LCL_VAR V55 tmp41 d:1 => N016 [000750] ASG => ***** BB51, STMT00131(after) N016 ( 26, 25) [000750] -A------R--- * ASG int N015 ( 3, 2) [000749] D------N---- +--* LCL_VAR int V55 tmp41 d:1 N014 ( 22, 22) [000748] ------------ \--* CAST int <- uint <- long N013 ( 21, 20) [000747] ------------ \--* RSZ long N011 ( 19, 18) [000745] ------------ +--* MUL long N008 ( 13, 12) [000742] ------------ | +--* ADD long N006 ( 11, 10) [000739] ------------ | | +--* RSZ long N004 ( 9, 8) [000737] ------------ | | | +--* MUL long N001 ( 3, 2) [000735] ------------ | | | | +--* LCL_VAR long V54 tmp40 u:1 (last use) N003 ( 2, 3) [000736] ---------U-- | | | | \--* CAST long <- ulong <- uint $310 N002 ( 1, 1) [000166] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 $3c0 N005 ( 1, 1) [000738] ------------ | | | \--* CNS_INT int 32 $d2 N007 ( 1, 1) [000741] ------------ | | \--* CNS_INT long 1 $247 N010 ( 2, 3) [000744] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000743] ------------ | \--* LCL_VAR int V53 tmp39 u:1 N012 ( 1, 1) [000746] ------------ \--* CNS_INT int 32 $d2 --------- ***** BB51, STMT00142(before) N007 ( 33, 11) [000796] -A-X----R--- * ASG bool N006 ( 3, 2) [000795] D------N---- +--* LCL_VAR int V59 tmp45 d:1 N005 ( 29, 8) [000755] ---X-------- \--* EQ int N003 ( 22, 5) [000754] ---X-------- +--* UMOD int N001 ( 1, 1) [000752] ------------ | +--* LCL_VAR int V06 loc2 u:1 N002 ( 1, 1) [000753] ------------ | \--* LCL_VAR int V53 tmp39 u:1 (last use) N004 ( 3, 2) [000751] ------------ \--* LCL_VAR int V55 tmp41 u:1 N001 [000752] LCL_VAR V06 loc2 u:1 => $3c0 {PhiDef($f, $1, $309)} N002 [000753] LCL_VAR V53 tmp39 u:1 (last use) => N003 [000754] UMOD => N004 [000751] LCL_VAR V55 tmp41 u:1 => N005 [000755] EQ => N006 [000795] LCL_VAR V59 tmp45 d:1 => N007 [000796] ASG => ***** BB51, STMT00142(after) N007 ( 33, 11) [000796] -A-X----R--- * ASG bool N006 ( 3, 2) [000795] D------N---- +--* LCL_VAR int V59 tmp45 d:1 N005 ( 29, 8) [000755] ---X-------- \--* EQ int N003 ( 22, 5) [000754] ---X-------- +--* UMOD int N001 ( 1, 1) [000752] ------------ | +--* LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000753] ------------ | \--* LCL_VAR int V53 tmp39 u:1 (last use) N004 ( 3, 2) [000751] ------------ \--* LCL_VAR int V55 tmp41 u:1 --------- ***** BB51, STMT00145(before) N004 ( 8, 15) [000806] -A--G---R--- * ASG ref N003 ( 3, 2) [000805] D------N---- +--* LCL_VAR ref V60 tmp46 d:1 N002 ( 4, 12) [000790] #---G------- \--* IND ref N001 ( 2, 10) [000789] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] N001 [000789] CNS_INT(h) 0xD1FFAB1E [ICON_STR_HDL] => $43 {Hnd const: 0x00000000D1FFAB1E} N002 [000790] IND => $105 {NonNullIndirect($43)} N003 [000805] LCL_VAR V60 tmp46 d:1 => $105 {NonNullIndirect($43)} N004 [000806] ASG => $105 {NonNullIndirect($43)} ***** BB51, STMT00145(after) N004 ( 8, 15) [000806] -A--G---R--- * ASG ref $105 N003 ( 3, 2) [000805] D------N---- +--* LCL_VAR ref V60 tmp46 d:1 $105 N002 ( 4, 12) [000790] #---G------- \--* IND ref $105 N001 ( 2, 10) [000789] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 --------- ***** BB51, STMT00146(before) N004 ( 8, 15) [000808] -A--G---R--- * ASG ref N003 ( 3, 2) [000807] D------N---- +--* LCL_VAR ref V61 tmp47 d:1 N002 ( 4, 12) [000792] #---G------- \--* IND ref N001 ( 2, 10) [000791] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] N001 [000791] CNS_INT(h) 0xD1FFAB1E [ICON_STR_HDL] => $43 {Hnd const: 0x00000000D1FFAB1E} N002 [000792] IND => $105 {NonNullIndirect($43)} N003 [000807] LCL_VAR V61 tmp47 d:1 => $105 {NonNullIndirect($43)} N004 [000808] ASG => $105 {NonNullIndirect($43)} ***** BB51, STMT00146(after) N004 ( 8, 15) [000808] -A--G---R--- * ASG ref $105 N003 ( 3, 2) [000807] D------N---- +--* LCL_VAR ref V61 tmp47 d:1 $105 N002 ( 4, 12) [000792] #---G------- \--* IND ref $105 N001 ( 2, 10) [000791] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 --------- ***** BB51, STMT00143(before) N004 ( 7, 6) [000801] ------------ * JTRUE void N003 ( 5, 4) [000800] J------N---- \--* NE int N001 ( 3, 2) [000798] ------------ +--* LCL_VAR int V59 tmp45 u:1 (last use) N002 ( 1, 1) [000799] ------------ \--* CNS_INT int 0 N001 [000798] LCL_VAR V59 tmp45 u:1 (last use) => N002 [000799] CNS_INT 0 => $c0 {IntCns 0} N003 [000800] NE => ***** BB51, STMT00143(after) N004 ( 7, 6) [000801] ------------ * JTRUE void N003 ( 5, 4) [000800] J------N---- \--* NE int N001 ( 3, 2) [000798] ------------ +--* LCL_VAR int V59 tmp45 u:1 (last use) N002 ( 1, 1) [000799] ------------ \--* CNS_INT int 0 $c0 finish(BB51). Succ(BB52). Not yet completed. All preds complete, adding to allDone. Succ(BB53). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#18) at start of BB52 is $479 {PhiMemoryDef($5a, $478)} The SSA definition for GcHeap (#18) at start of BB52 is $479 {PhiMemoryDef($5a, $478)} ***** BB52, STMT00144(before) N005 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail N003 ( 3, 2) [000802] ------------ arg0 in rcx +--* LCL_VAR ref V60 tmp46 u:1 (last use) N004 ( 3, 2) [000803] ------------ arg1 in rdx \--* LCL_VAR ref V61 tmp47 u:1 (last use) N001 [001100] ARGPLACE => $234 {234} N002 [001101] ARGPLACE => $235 {235} N003 [000802] LCL_VAR V60 tmp46 u:1 (last use) => $105 {NonNullIndirect($43)} N004 [000803] LCL_VAR V61 tmp47 u:1 (last use) => $105 {NonNullIndirect($43)} VN of ARGPLACE tree [001100] updated to $105 {NonNullIndirect($43)} VN of ARGPLACE tree [001101] updated to $105 {NonNullIndirect($43)} fgCurMemoryVN[GcHeap] assigned for CALL at [000804] to VN: $236. N005 [000804] CALL => $VN.Void ***** BB52, STMT00144(after) N005 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 3, 2) [000802] ------------ arg0 in rcx +--* LCL_VAR ref V60 tmp46 u:1 (last use) $105 N004 ( 3, 2) [000803] ------------ arg1 in rdx \--* LCL_VAR ref V61 tmp47 u:1 (last use) $105 finish(BB52). Succ(BB53). Not yet completed. All preds complete, adding to allDone. Building phi application: $de = SSA# 20. Building phi application: $d6 = SSA# 18. Building phi application: $47c = phi($d6, $de). The SSA definition for GcHeap (#19) at start of BB53 is $47d {PhiMemoryDef($5b, $47c)} ***** BB53, STMT00128(before) N017 ( 35, 33) [000722] -A-XG---R--- * ASG byref N016 ( 3, 2) [000721] D------N---- +--* LCL_VAR byref V51 tmp37 d:1 N015 ( 31, 30) [001112] ---XG------- \--* COMMA byref N004 ( 12, 13) [001105] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 3, 2) [000758] ------------ | +--* LCL_VAR int V55 tmp41 u:1 N003 ( 5, 4) [001104] ---X-------- | \--* ARR_LENGTH int N002 ( 3, 2) [000712] ------------ | \--* LCL_VAR ref V52 tmp38 u:1 N014 ( 19, 17) [001113] ----G------- \--* ADDR byref N013 ( 10, 9) [000719] a---G--N---- \--* IND int N012 ( 9, 8) [001111] -------N---- \--* ADD byref N005 ( 3, 2) [001102] ------------ +--* LCL_VAR ref V52 tmp38 u:1 (last use) N011 ( 6, 6) [001110] -------N---- \--* ADD long N009 ( 5, 5) [001108] -------N---- +--* LSH long N007 ( 4, 4) [001106] ------------ | +--* CAST long <- int N006 ( 3, 2) [001103] i----------- | | \--* LCL_VAR int V55 tmp41 u:1 (last use) N008 ( 1, 1) [001107] -------N---- | \--* CNS_INT long 2 N010 ( 1, 1) [001109] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] N001 [000758] LCL_VAR V55 tmp41 u:1 => N002 [000712] LCL_VAR V52 tmp38 u:1 => N003 [001104] ARR_LENGTH => N004 [001105] ARR_BOUNDS_CHECK_Rng => N005 [001102] LCL_VAR V52 tmp38 u:1 (last use) => N006 [001103] LCL_VAR V55 tmp41 u:1 (last use) => VNForCastOper(long) is $d6 N007 [001106] CAST => N008 [001107] CNS_INT 2 => $248 {LngCns: 2} N009 [001108] LSH => N010 [001109] CNS_INT 16 Fseq[#FirstElem] => $241 {LngCns: 16} N011 [001110] ADD => N012 [001111] ADD => VNForHandle(arrElemType: int) is $4e Relabeled IND_ARR_INDEX address node [001111] with l:$87: {PtrToArrElem($4e, $473, $6c4, $0)} VNForMapSelect($47d, $4e):ref returns $74c {$47d[$4e]} VNForMapSelect($74c, $473):ref returns $74d {$74c[$473]} VNForMapSelect($74d, $6c4):int returns $706 {$74d[$6c4]} hAtArrType $74c is MapSelect(curGcHeap($47d), int[]). hAtArrTypeAtArr $74d is MapSelect(hAtArrType($74c), arr=$473). wholeElem $706 is MapSelect(hAtArrTypeAtArr($74d), ind=$6c4). N013 [000719] IND => N014 [001113] ADDR => $87 {PtrToArrElem($4e, $473, $6c4, $0)} N015 [001112] COMMA => N016 [000721] LCL_VAR V51 tmp37 d:1 => $87 {PtrToArrElem($4e, $473, $6c4, $0)} N017 [000722] ASG => ***** BB53, STMT00128(after) N017 ( 35, 33) [000722] -A-XG---R--- * ASG byref N016 ( 3, 2) [000721] D------N---- +--* LCL_VAR byref V51 tmp37 d:1 $87 N015 ( 31, 30) [001112] ---XG------- \--* COMMA byref N004 ( 12, 13) [001105] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 3, 2) [000758] ------------ | +--* LCL_VAR int V55 tmp41 u:1 N003 ( 5, 4) [001104] ---X-------- | \--* ARR_LENGTH int N002 ( 3, 2) [000712] ------------ | \--* LCL_VAR ref V52 tmp38 u:1 N014 ( 19, 17) [001113] ----G------- \--* ADDR byref $87 N013 ( 10, 9) [000719] a---G--N---- \--* IND int N012 ( 9, 8) [001111] -------N---- \--* ADD byref $87 N005 ( 3, 2) [001102] ------------ +--* LCL_VAR ref V52 tmp38 u:1 (last use) N011 ( 6, 6) [001110] -------N---- \--* ADD long N009 ( 5, 5) [001108] -------N---- +--* LSH long N007 ( 4, 4) [001106] ------------ | +--* CAST long <- int N006 ( 3, 2) [001103] i----------- | | \--* LCL_VAR int V55 tmp41 u:1 (last use) N008 ( 1, 1) [001107] -------N---- | \--* CNS_INT long 2 $248 N010 ( 1, 1) [001109] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 --------- ***** BB53, STMT00034(before) N003 ( 7, 5) [000170] -A------R--- * ASG byref N002 ( 3, 2) [000169] D------N---- +--* LCL_VAR byref V08 loc4 d:4 N001 ( 3, 2) [000723] ------------ \--* LCL_VAR byref V51 tmp37 u:1 (last use) N001 [000723] LCL_VAR V51 tmp37 u:1 (last use) => $87 {PtrToArrElem($4e, $473, $6c4, $0)} N002 [000169] LCL_VAR V08 loc4 d:4 => $87 {PtrToArrElem($4e, $473, $6c4, $0)} N003 [000170] ASG => $87 {PtrToArrElem($4e, $473, $6c4, $0)} ***** BB53, STMT00034(after) N003 ( 7, 5) [000170] -A------R--- * ASG byref $87 N002 ( 3, 2) [000169] D------N---- +--* LCL_VAR byref V08 loc4 d:4 $87 N001 ( 3, 2) [000723] ------------ \--* LCL_VAR byref V51 tmp37 u:1 (last use) $87 finish(BB53). Succ(BB54). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 8/3 to $780 {PhiDef($8, $3, $60a)} . Building phi application: $df = SSA# 19. Building phi application: $e0 = SSA# 11. Building phi application: $74e = phi($e0, $df). The SSA definition for GcHeap (#15) at start of BB54 is $74f {PhiMemoryDef($5c, $74e)} ***** BB54, STMT00018(before) N003 ( 7, 5) [000083] -A------R--- * ASG int N002 ( 3, 2) [000082] D------N---- +--* LCL_VAR int V10 loc6 d:2 N001 ( 3, 2) [000081] ------------ \--* LCL_VAR int V13 loc9 u:1 N001 [000081] LCL_VAR V13 loc9 u:1 => N002 [000082] LCL_VAR V10 loc6 d:2 => N003 [000083] ASG => ***** BB54, STMT00018(after) N003 ( 7, 5) [000083] -A------R--- * ASG int N002 ( 3, 2) [000082] D------N---- +--* LCL_VAR int V10 loc6 d:2 N001 ( 3, 2) [000081] ------------ \--* LCL_VAR int V13 loc9 u:1 --------- ***** BB54, STMT00019(before) N008 ( 10, 9) [000089] -A-XG---R--- * ASG int N007 ( 4, 4) [000088] D--XG--N---- +--* IND int N006 ( 2, 2) [001115] -------N---- | \--* ADD byref N004 ( 1, 1) [000084] ------------ | +--* LCL_VAR ref V00 this u:1 N005 ( 1, 1) [001114] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] N003 ( 5, 4) [000087] ------------ \--* ADD int N001 ( 3, 2) [000085] ------------ +--* LCL_VAR int V13 loc9 u:1 (last use) N002 ( 1, 1) [000086] ------------ \--* CNS_INT int 1 N001 [000085] LCL_VAR V13 loc9 u:1 (last use) => N002 [000086] CNS_INT 1 => $c1 {IntCns 1} N003 [000087] ADD => N004 [000084] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N005 [001114] CNS_INT 56 field offset Fseq[_count] => $244 {LngCns: 56} N006 [001115] ADD => $290 {ADD($100, $244)} VNApplySelectors: VNForHandle(_count) is $59, fieldType is int VNForMapSelect($74f, $59):int returns $70e {$74f[$59]} VNForMapSelect($70e, $100):int returns $70f {$70e[$100]} VNForMapStore($70e, $100, $708):int returns $3c6 {$70e[$100 := $708]} VNApplySelectorsAssign: VNForHandle(_count) is $59, fieldType is int VNForMapStore($74f, $59, $3c6):int returns $3c7 {$74f[$59 := $3c6]} fgCurMemoryVN[GcHeap] assigned for StoreField at [000089] to VN: $3c7. N008 [000089] ASG => $VN.Void ***** BB54, STMT00019(after) N008 ( 10, 9) [000089] -A-XG---R--- * ASG int $VN.Void N007 ( 4, 4) [000088] D--XG--N---- +--* IND int $708 N006 ( 2, 2) [001115] -------N---- | \--* ADD byref $290 N004 ( 1, 1) [000084] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N005 ( 1, 1) [001114] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] $244 N003 ( 5, 4) [000087] ------------ \--* ADD int N001 ( 3, 2) [000085] ------------ +--* LCL_VAR int V13 loc9 u:1 (last use) N002 ( 1, 1) [000086] ------------ \--* CNS_INT int 1 $c1 --------- ***** BB54, STMT00020(before) N006 ( 4, 4) [000093] -A-XG---R--- * ASG ref N005 ( 1, 1) [000092] D------N---- +--* LCL_VAR ref V04 loc0 d:3 N004 ( 4, 4) [000091] ---XG------- \--* IND ref N003 ( 2, 2) [001117] -------N---- \--* ADD byref N001 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001116] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] N001 [000090] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N002 [001116] CNS_INT 16 field offset Fseq[_entries] => $241 {LngCns: 16} N003 [001117] ADD => $281 {ADD($100, $241)} VNApplySelectors: VNForHandle(_entries) is $45, fieldType is ref AX2: $45 != $59 ==> select([$3c7]store($74f, $59, $3c6), $45) ==> select($74f, $45). VNForMapSelect($3c7, $45):ref returns $75f {$74f[$45]} VNForMapSelect($75f, $100):ref returns $760 {$75f[$100]} N004 [000091] IND => N005 [000092] LCL_VAR V04 loc0 d:3 => N006 [000093] ASG => ***** BB54, STMT00020(after) N006 ( 4, 4) [000093] -A-XG---R--- * ASG ref N005 ( 1, 1) [000092] D------N---- +--* LCL_VAR ref V04 loc0 d:3 N004 ( 4, 4) [000091] ---XG------- \--* IND ref N003 ( 2, 2) [001117] -------N---- \--* ADD byref $281 N001 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001116] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] $241 finish(BB54). Succ(BB55). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#11) at start of BB45 is $471 {PhiMemoryDef($57, $470)} The SSA definition for GcHeap (#11) at start of BB45 is $471 {PhiMemoryDef($57, $470)} ***** BB45, STMT00035(before) N006 ( 8, 7) [000174] -A-XG---R--- * ASG int N005 ( 3, 2) [000173] D------N---- +--* LCL_VAR int V10 loc6 d:3 N004 ( 4, 4) [000172] ---XG------- \--* IND int N003 ( 2, 2) [001027] -------N---- \--* ADD byref N001 ( 1, 1) [000171] ------------ +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001026] ------------ \--* CNS_INT long 60 field offset Fseq[_freeList] N001 [000171] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N002 [001026] CNS_INT 60 field offset Fseq[_freeList] => $24d {LngCns: 60} N003 [001027] ADD => $295 {ADD($100, $24d)} VNApplySelectors: VNForHandle(_freeList) is $5d, fieldType is int VNForMapSelect($471, $5d):int returns $719 {$471[$5d]} VNForMapSelect($719, $100):int returns $71a {$719[$100]} N004 [000172] IND => N005 [000173] LCL_VAR V10 loc6 d:3 => N006 [000174] ASG => ***** BB45, STMT00035(after) N006 ( 8, 7) [000174] -A-XG---R--- * ASG int N005 ( 3, 2) [000173] D------N---- +--* LCL_VAR int V10 loc6 d:3 N004 ( 4, 4) [000172] ---XG------- \--* IND int N003 ( 2, 2) [001027] -------N---- \--* ADD byref $295 N001 ( 1, 1) [000171] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001026] ------------ \--* CNS_INT long 60 field offset Fseq[_freeList] $24d --------- ***** BB45, STMT00120(before) N034 ( 48, 47) [000688] -A-XG---R--- * ASG bool N033 ( 3, 2) [000687] D------N---- +--* LCL_VAR int V49 tmp35 d:1 N032 ( 44, 44) [000184] -A-XG------- \--* GE int N030 ( 39, 42) [000182] -A-XG------- +--* ADD int N028 ( 37, 40) [001050] -A-XG------- | +--* NEG int N027 ( 36, 39) [000181] *A-XG------- | | \--* IND int N026 ( 34, 37) [001029] -A-XG--N---- | | \--* ADD byref N024 ( 33, 36) [001044] -A-XG------- | | +--* COMMA byref N006 ( 4, 4) [001032] -A-XG---R--- | | | +--* ASG int N005 ( 1, 1) [001031] D------N---- | | | | +--* LCL_VAR int V62 tmp48 d:1 N004 ( 4, 4) [000178] ---XG------- | | | | \--* IND int N003 ( 2, 2) [001046] -------N---- | | | | \--* ADD byref N001 ( 1, 1) [000177] ------------ | | | | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001045] ------------ | | | | \--* CNS_INT long 60 field offset Fseq[_freeList] N023 ( 29, 32) [001043] ---XG------- | | | \--* COMMA byref N010 ( 8, 11) [001036] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [001033] ------------ | | | | +--* LCL_VAR int V62 tmp48 u:1 N009 ( 3, 3) [001035] ---X-------- | | | | \--* ARR_LENGTH int N008 ( 1, 1) [000176] ------------ | | | | \--* LCL_VAR ref V04 loc0 u:1 N022 ( 21, 21) [001049] ----G------- | | | \--* ADDR byref N021 ( 11, 11) [000179] a---G--N---- | | | \--* IND struct N020 ( 10, 10) [001042] -------N---- | | | \--* ADD byref N011 ( 1, 1) [001030] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N019 ( 9, 9) [001041] -------N---- | | | \--* ADD long N017 ( 8, 8) [001039] -------N---- | | | +--* LSH long N015 ( 7, 7) [001048] ------------ | | | | +--* MUL long N013 ( 2, 3) [001037] ------------ | | | | | +--* CAST long <- int N012 ( 1, 1) [001034] i----------- | | | | | | \--* LCL_VAR int V62 tmp48 u:1 (last use) N014 ( 1, 1) [001047] ------------ | | | | | \--* CNS_INT long 3 N016 ( 1, 1) [001038] -------N---- | | | | \--* CNS_INT long 3 N018 ( 1, 1) [001040] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] N025 ( 1, 1) [001028] ------------ | | \--* CNS_INT long 20 field offset Fseq[next] N029 ( 1, 1) [000175] ------------ | \--* CNS_INT int -3 N031 ( 1, 1) [000183] ------------ \--* CNS_INT int -1 N001 [000177] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N002 [001045] CNS_INT 60 field offset Fseq[_freeList] => $24d {LngCns: 60} N003 [001046] ADD => $295 {ADD($100, $24d)} VNApplySelectors: VNForHandle(_freeList) is $5d, fieldType is int VNForMapSelect($471, $5d):int returns $719 {$471[$5d]} VNForMapSelect($719, $100):int returns $71a {$719[$100]} N004 [000178] IND => N005 [001031] LCL_VAR V62 tmp48 d:1 => N006 [001032] ASG => N007 [001033] LCL_VAR V62 tmp48 u:1 => N008 [000176] LCL_VAR V04 loc0 u:1 => N009 [001035] ARR_LENGTH => N010 [001036] ARR_BOUNDS_CHECK_Rng => N011 [001030] LCL_VAR V04 loc0 u:1 => N012 [001034] LCL_VAR V62 tmp48 u:1 (last use) => VNForCastOper(long) is $d6 N013 [001037] CAST => N014 [001047] CNS_INT 3 => $24b {LngCns: 3} N015 [001048] MUL => N016 [001038] CNS_INT 3 => $24b {LngCns: 3} N017 [001039] LSH => N018 [001040] CNS_INT 16 Fseq[#FirstElem] => $241 {LngCns: 16} N019 [001041] ADD => N020 [001042] ADD => VNForHandle(arrElemType: Entry[__Canon,__Canon]) is $40 Relabeled IND_ARR_INDEX address node [001042] with l:$88: {PtrToArrElem($40, $2d3, $6cb, $0)} VNForMapSelect($471, $40):ref returns $773 {$471[$40]} VNForMapSelect($773, $2d3):ref returns $774 {$773[$2d3]} VNForMapSelect($774, $6cb):struct returns $503 {$774[$6cb]} hAtArrType $773 is MapSelect(curGcHeap($471), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $774 is MapSelect(hAtArrType($773), arr=$2d3). wholeElem $503 is MapSelect(hAtArrTypeAtArr($774), ind=$6cb). N021 [000179] IND => N022 [001049] ADDR => $88 {PtrToArrElem($40, $2d3, $6cb, $0)} N023 [001043] COMMA => N024 [001044] COMMA => N025 [001028] CNS_INT 20 field offset Fseq[next] => $24c {LngCns: 20} FieldSeq {next} is $46d N026 [001029] ADD => $29c {norm=$89 {PtrToArrElem($40, $2d3, $6cb, $46d)}, exc=$776( {NullPtrExc($100)}, {NullPtrExc($2d3)}, {IndexOutOfRangeExc($71a, $403)})} VNForMapSelect($471, $40):ref returns $773 {$471[$40]} VNForMapSelect($773, $2d3):ref returns $774 {$773[$2d3]} VNForMapSelect($774, $6cb):struct returns $503 {$774[$6cb]} hAtArrType $773 is MapSelect(curGcHeap($471), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $774 is MapSelect(hAtArrType($773), arr=$2d3). wholeElem $503 is MapSelect(hAtArrTypeAtArr($774), ind=$6cb). VNApplySelectors: VNForHandle(next) is $55, fieldType is int VNForMapSelect($503, $55):int returns $71e {$503[$55]} selectedElem is $71f after applying selectors. N027 [000181] IND => N028 [001050] NEG => N029 [000175] CNS_INT -3 => $e1 {IntCns -3} N030 [000182] ADD => N031 [000183] CNS_INT -1 => $c4 {IntCns -1} N032 [000184] GE => N033 [000687] LCL_VAR V49 tmp35 d:1 => N034 [000688] ASG => ***** BB45, STMT00120(after) N034 ( 48, 47) [000688] -A-XG---R--- * ASG bool N033 ( 3, 2) [000687] D------N---- +--* LCL_VAR int V49 tmp35 d:1 N032 ( 44, 44) [000184] -A-XG------- \--* GE int N030 ( 39, 42) [000182] -A-XG------- +--* ADD int N028 ( 37, 40) [001050] -A-XG------- | +--* NEG int N027 ( 36, 39) [000181] *A-XG------- | | \--* IND int N026 ( 34, 37) [001029] -A-XG--N---- | | \--* ADD byref $29c N024 ( 33, 36) [001044] -A-XG------- | | +--* COMMA byref N006 ( 4, 4) [001032] -A-XG---R--- | | | +--* ASG int N005 ( 1, 1) [001031] D------N---- | | | | +--* LCL_VAR int V62 tmp48 d:1 N004 ( 4, 4) [000178] ---XG------- | | | | \--* IND int N003 ( 2, 2) [001046] -------N---- | | | | \--* ADD byref $295 N001 ( 1, 1) [000177] ------------ | | | | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001045] ------------ | | | | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N023 ( 29, 32) [001043] ---XG------- | | | \--* COMMA byref N010 ( 8, 11) [001036] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [001033] ------------ | | | | +--* LCL_VAR int V62 tmp48 u:1 N009 ( 3, 3) [001035] ---X-------- | | | | \--* ARR_LENGTH int N008 ( 1, 1) [000176] ------------ | | | | \--* LCL_VAR ref V04 loc0 u:1 N022 ( 21, 21) [001049] ----G------- | | | \--* ADDR byref $88 N021 ( 11, 11) [000179] a---G--N---- | | | \--* IND struct N020 ( 10, 10) [001042] -------N---- | | | \--* ADD byref $88 N011 ( 1, 1) [001030] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N019 ( 9, 9) [001041] -------N---- | | | \--* ADD long N017 ( 8, 8) [001039] -------N---- | | | +--* LSH long N015 ( 7, 7) [001048] ------------ | | | | +--* MUL long N013 ( 2, 3) [001037] ------------ | | | | | +--* CAST long <- int N012 ( 1, 1) [001034] i----------- | | | | | | \--* LCL_VAR int V62 tmp48 u:1 (last use) N014 ( 1, 1) [001047] ------------ | | | | | \--* CNS_INT long 3 $24b N016 ( 1, 1) [001038] -------N---- | | | | \--* CNS_INT long 3 $24b N018 ( 1, 1) [001040] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N025 ( 1, 1) [001028] ------------ | | \--* CNS_INT long 20 field offset Fseq[next] $24c N029 ( 1, 1) [000175] ------------ | \--* CNS_INT int -3 $e1 N031 ( 1, 1) [000183] ------------ \--* CNS_INT int -1 $c4 --------- ***** BB45, STMT00123(before) N004 ( 8, 15) [000698] -A--G---R--- * ASG ref N003 ( 3, 2) [000697] D------N---- +--* LCL_VAR ref V50 tmp36 d:1 N002 ( 4, 12) [000684] #---G------- \--* IND ref N001 ( 2, 10) [000683] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] N001 [000683] CNS_INT(h) 0xD1FFAB1E [ICON_STR_HDL] => $43 {Hnd const: 0x00000000D1FFAB1E} N002 [000684] IND => $105 {NonNullIndirect($43)} N003 [000697] LCL_VAR V50 tmp36 d:1 => $105 {NonNullIndirect($43)} N004 [000698] ASG => $105 {NonNullIndirect($43)} ***** BB45, STMT00123(after) N004 ( 8, 15) [000698] -A--G---R--- * ASG ref $105 N003 ( 3, 2) [000697] D------N---- +--* LCL_VAR ref V50 tmp36 d:1 $105 N002 ( 4, 12) [000684] #---G------- \--* IND ref $105 N001 ( 2, 10) [000683] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 --------- ***** BB45, STMT00121(before) N004 ( 7, 6) [000693] ------------ * JTRUE void N003 ( 5, 4) [000692] J------N---- \--* NE int N001 ( 3, 2) [000690] ------------ +--* LCL_VAR int V49 tmp35 u:1 (last use) N002 ( 1, 1) [000691] ------------ \--* CNS_INT int 0 N001 [000690] LCL_VAR V49 tmp35 u:1 (last use) => N002 [000691] CNS_INT 0 => $c0 {IntCns 0} N003 [000692] NE => ***** BB45, STMT00121(after) N004 ( 7, 6) [000693] ------------ * JTRUE void N003 ( 5, 4) [000692] J------N---- \--* NE int N001 ( 3, 2) [000690] ------------ +--* LCL_VAR int V49 tmp35 u:1 (last use) N002 ( 1, 1) [000691] ------------ \--* CNS_INT int 0 $c0 finish(BB45). Succ(BB46). Not yet completed. All preds complete, adding to allDone. Succ(BB47). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#11) at start of BB46 is $471 {PhiMemoryDef($57, $470)} The SSA definition for GcHeap (#11) at start of BB46 is $471 {PhiMemoryDef($57, $470)} ***** BB46, STMT00122(before) N006 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail N004 ( 4, 12) [001052] #---G------- arg0 in rcx +--* IND ref N003 ( 2, 10) [001051] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" N005 ( 3, 2) [000695] ------------ arg1 in rdx \--* LCL_VAR ref V50 tmp36 u:1 (last use) N001 [001053] ARGPLACE => $23a {23a} N002 [001054] ARGPLACE => $23b {23b} N003 [001051] CNS_INT(h) 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" => $5e {Hnd const: 0x00000000D1FFAB1E} N004 [001052] IND => $114 {NonNullIndirect($5e)} N005 [000695] LCL_VAR V50 tmp36 u:1 (last use) => $105 {NonNullIndirect($43)} VN of ARGPLACE tree [001053] updated to $114 {NonNullIndirect($5e)} VN of ARGPLACE tree [001054] updated to $105 {NonNullIndirect($43)} fgCurMemoryVN[GcHeap] assigned for CALL at [000696] to VN: $23c. N006 [000696] CALL => $VN.Void ***** BB46, STMT00122(after) N006 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N004 ( 4, 12) [001052] #---G------- arg0 in rcx +--* IND ref $114 N003 ( 2, 10) [001051] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" $5e N005 ( 3, 2) [000695] ------------ arg1 in rdx \--* LCL_VAR ref V50 tmp36 u:1 (last use) $105 finish(BB46). Succ(BB47). Not yet completed. All preds complete, adding to allDone. Building phi application: $ca = SSA# 24. Building phi application: $e0 = SSA# 11. Building phi application: $777 = phi($e0, $ca). The SSA definition for GcHeap (#22) at start of BB47 is $778 {PhiMemoryDef($5f, $777)} ***** BB47, STMT00037(before) N035 ( 44, 47) [000200] -A-XG------- * ASG int N004 ( 4, 4) [000199] D--XG--N---- +--* IND int N003 ( 2, 2) [001056] -------N---- | \--* ADD byref N001 ( 1, 1) [000190] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001055] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] N034 ( 39, 42) [000198] -A-XG------- \--* ADD int N032 ( 37, 40) [001079] -A-XG------- +--* NEG int N031 ( 36, 39) [000197] *A-XG------- | \--* IND int N030 ( 34, 37) [001058] -A-XG--N---- | \--* ADD byref N028 ( 33, 36) [001073] -A-XG------- | +--* COMMA byref N010 ( 4, 4) [001061] -A-XG---R--- | | +--* ASG int N009 ( 1, 1) [001060] D------N---- | | | +--* LCL_VAR int V63 tmp49 d:1 N008 ( 4, 4) [000194] ---XG------- | | | \--* IND int N007 ( 2, 2) [001075] -------N---- | | | \--* ADD byref N005 ( 1, 1) [000193] ------------ | | | +--* LCL_VAR ref V00 this u:1 N006 ( 1, 1) [001074] ------------ | | | \--* CNS_INT long 60 field offset Fseq[_freeList] N027 ( 29, 32) [001072] ---XG------- | | \--* COMMA byref N014 ( 8, 11) [001065] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N011 ( 1, 1) [001062] ------------ | | | +--* LCL_VAR int V63 tmp49 u:1 N013 ( 3, 3) [001064] ---X-------- | | | \--* ARR_LENGTH int N012 ( 1, 1) [000192] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N026 ( 21, 21) [001078] ----G------- | | \--* ADDR byref N025 ( 11, 11) [000195] a---G--N---- | | \--* IND struct N024 ( 10, 10) [001071] -------N---- | | \--* ADD byref N015 ( 1, 1) [001059] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N023 ( 9, 9) [001070] -------N---- | | \--* ADD long N021 ( 8, 8) [001068] -------N---- | | +--* LSH long N019 ( 7, 7) [001077] ------------ | | | +--* MUL long N017 ( 2, 3) [001066] ------------ | | | | +--* CAST long <- int N016 ( 1, 1) [001063] i----------- | | | | | \--* LCL_VAR int V63 tmp49 u:1 (last use) N018 ( 1, 1) [001076] ------------ | | | | \--* CNS_INT long 3 N020 ( 1, 1) [001067] -------N---- | | | \--* CNS_INT long 3 N022 ( 1, 1) [001069] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N029 ( 1, 1) [001057] ------------ | \--* CNS_INT long 20 field offset Fseq[next] N033 ( 1, 1) [000191] ------------ \--* CNS_INT int -3 N001 [000190] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N002 [001055] CNS_INT 60 field offset Fseq[_freeList] => $24d {LngCns: 60} N003 [001056] ADD => $295 {ADD($100, $24d)} N005 [000193] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N006 [001074] CNS_INT 60 field offset Fseq[_freeList] => $24d {LngCns: 60} N007 [001075] ADD => $295 {ADD($100, $24d)} VNApplySelectors: VNForHandle(_freeList) is $5d, fieldType is int VNForMapSelect($778, $5d):int returns $72a {$778[$5d]} VNForMapSelect($72a, $100):int returns $72b {$72a[$100]} N008 [000194] IND => N009 [001060] LCL_VAR V63 tmp49 d:1 => N010 [001061] ASG => N011 [001062] LCL_VAR V63 tmp49 u:1 => N012 [000192] LCL_VAR V04 loc0 u:1 => N013 [001064] ARR_LENGTH => N014 [001065] ARR_BOUNDS_CHECK_Rng => N015 [001059] LCL_VAR V04 loc0 u:1 => N016 [001063] LCL_VAR V63 tmp49 u:1 (last use) => VNForCastOper(long) is $d6 N017 [001066] CAST => N018 [001076] CNS_INT 3 => $24b {LngCns: 3} N019 [001077] MUL => N020 [001067] CNS_INT 3 => $24b {LngCns: 3} N021 [001068] LSH => N022 [001069] CNS_INT 16 Fseq[#FirstElem] => $241 {LngCns: 16} N023 [001070] ADD => N024 [001071] ADD => VNForHandle(arrElemType: Entry[__Canon,__Canon]) is $40 Relabeled IND_ARR_INDEX address node [001071] with l:$8a: {PtrToArrElem($40, $2d3, $6d4, $0)} VNForMapSelect($778, $40):ref returns $7c2 {$778[$40]} VNForMapSelect($7c2, $2d3):ref returns $7c3 {$7c2[$2d3]} VNForMapSelect($7c3, $6d4):struct returns $504 {$7c3[$6d4]} hAtArrType $7c2 is MapSelect(curGcHeap($778), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $7c3 is MapSelect(hAtArrType($7c2), arr=$2d3). wholeElem $504 is MapSelect(hAtArrTypeAtArr($7c3), ind=$6d4). N025 [000195] IND => N026 [001078] ADDR => $8a {PtrToArrElem($40, $2d3, $6d4, $0)} N027 [001072] COMMA => N028 [001073] COMMA => N029 [001057] CNS_INT 20 field offset Fseq[next] => $24c {LngCns: 20} FieldSeq {next} is $46d N030 [001058] ADD => $2a3 {norm=$8b {PtrToArrElem($40, $2d3, $6d4, $46d)}, exc=$7c5( {NullPtrExc($100)}, {NullPtrExc($2d3)}, {IndexOutOfRangeExc($72b, $403)})} VNForMapSelect($778, $40):ref returns $7c2 {$778[$40]} VNForMapSelect($7c2, $2d3):ref returns $7c3 {$7c2[$2d3]} VNForMapSelect($7c3, $6d4):struct returns $504 {$7c3[$6d4]} hAtArrType $7c2 is MapSelect(curGcHeap($778), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $7c3 is MapSelect(hAtArrType($7c2), arr=$2d3). wholeElem $504 is MapSelect(hAtArrTypeAtArr($7c3), ind=$6d4). VNApplySelectors: VNForHandle(next) is $55, fieldType is int VNForMapSelect($504, $55):int returns $72e {$504[$55]} selectedElem is $72f after applying selectors. N031 [000197] IND => N032 [001079] NEG => N033 [000191] CNS_INT -3 => $e1 {IntCns -3} N034 [000198] ADD => VNApplySelectors: VNForHandle(_freeList) is $5d, fieldType is int VNForMapSelect($778, $5d):int returns $72a {$778[$5d]} VNForMapSelect($72a, $100):int returns $72b {$72a[$100]} VNForMapStore($72a, $100, $732):int returns $3c8 {$72a[$100 := $732]} VNApplySelectorsAssign: VNForHandle(_freeList) is $5d, fieldType is int VNForMapStore($778, $5d, $3c8):int returns $3c9 {$778[$5d := $3c8]} fgCurMemoryVN[GcHeap] assigned for StoreField at [000200] to VN: $3c9. N035 [000200] ASG => $VN.Void ***** BB47, STMT00037(after) N035 ( 44, 47) [000200] -A-XG------- * ASG int $VN.Void N004 ( 4, 4) [000199] D--XG--N---- +--* IND int $732 N003 ( 2, 2) [001056] -------N---- | \--* ADD byref $295 N001 ( 1, 1) [000190] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001055] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N034 ( 39, 42) [000198] -A-XG------- \--* ADD int N032 ( 37, 40) [001079] -A-XG------- +--* NEG int N031 ( 36, 39) [000197] *A-XG------- | \--* IND int N030 ( 34, 37) [001058] -A-XG--N---- | \--* ADD byref $2a3 N028 ( 33, 36) [001073] -A-XG------- | +--* COMMA byref N010 ( 4, 4) [001061] -A-XG---R--- | | +--* ASG int N009 ( 1, 1) [001060] D------N---- | | | +--* LCL_VAR int V63 tmp49 d:1 N008 ( 4, 4) [000194] ---XG------- | | | \--* IND int N007 ( 2, 2) [001075] -------N---- | | | \--* ADD byref $295 N005 ( 1, 1) [000193] ------------ | | | +--* LCL_VAR ref V00 this u:1 $100 N006 ( 1, 1) [001074] ------------ | | | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N027 ( 29, 32) [001072] ---XG------- | | \--* COMMA byref N014 ( 8, 11) [001065] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N011 ( 1, 1) [001062] ------------ | | | +--* LCL_VAR int V63 tmp49 u:1 N013 ( 3, 3) [001064] ---X-------- | | | \--* ARR_LENGTH int N012 ( 1, 1) [000192] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N026 ( 21, 21) [001078] ----G------- | | \--* ADDR byref $8a N025 ( 11, 11) [000195] a---G--N---- | | \--* IND struct N024 ( 10, 10) [001071] -------N---- | | \--* ADD byref $8a N015 ( 1, 1) [001059] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N023 ( 9, 9) [001070] -------N---- | | \--* ADD long N021 ( 8, 8) [001068] -------N---- | | +--* LSH long N019 ( 7, 7) [001077] ------------ | | | +--* MUL long N017 ( 2, 3) [001066] ------------ | | | | +--* CAST long <- int N016 ( 1, 1) [001063] i----------- | | | | | \--* LCL_VAR int V63 tmp49 u:1 (last use) N018 ( 1, 1) [001076] ------------ | | | | \--* CNS_INT long 3 $24b N020 ( 1, 1) [001067] -------N---- | | | \--* CNS_INT long 3 $24b N022 ( 1, 1) [001069] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N029 ( 1, 1) [001057] ------------ | \--* CNS_INT long 20 field offset Fseq[next] $24c N033 ( 1, 1) [000191] ------------ \--* CNS_INT int -3 $e1 --------- ***** BB47, STMT00038(before) N011 ( 11, 11) [000207] -A-XG---R--- * ASG int N010 ( 4, 4) [000206] D--XG--N---- +--* IND int N009 ( 2, 2) [001081] -------N---- | \--* ADD byref N007 ( 1, 1) [000201] ------------ | +--* LCL_VAR ref V00 this u:1 N008 ( 1, 1) [001080] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] N006 ( 6, 6) [000205] ---XG------- \--* ADD int N004 ( 4, 4) [000203] ---XG------- +--* IND int N003 ( 2, 2) [001083] -------N---- | \--* ADD byref N001 ( 1, 1) [000202] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001082] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] N005 ( 1, 1) [000204] ------------ \--* CNS_INT int -1 N001 [000202] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N002 [001082] CNS_INT 64 field offset Fseq[_freeCount] => $245 {LngCns: 64} N003 [001083] ADD => $28f {ADD($100, $245)} VNApplySelectors: VNForHandle(_freeCount) is $58, fieldType is int AX2: $58 != $5d ==> select([$3c9]store($778, $5d, $3c8), $58) ==> select($778, $58). VNForMapSelect($3c9, $58):int returns $735 {$778[$58]} VNForMapSelect($735, $100):int returns $736 {$735[$100]} N004 [000203] IND => N005 [000204] CNS_INT -1 => $c4 {IntCns -1} N006 [000205] ADD => N007 [000201] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N008 [001080] CNS_INT 64 field offset Fseq[_freeCount] => $245 {LngCns: 64} N009 [001081] ADD => $28f {ADD($100, $245)} VNApplySelectors: VNForHandle(_freeCount) is $58, fieldType is int AX2: $58 != $5d ==> select([$3c9]store($778, $5d, $3c8), $58) ==> select($778, $58). VNForMapSelect($3c9, $58):int returns $735 {$778[$58]} VNForMapSelect($735, $100):int returns $736 {$735[$100]} VNForMapStore($735, $100, $73a):int returns $3ca {$735[$100 := $73a]} VNApplySelectorsAssign: VNForHandle(_freeCount) is $58, fieldType is int VNForMapStore($3c9, $58, $3ca):int returns $3cb {$3c9[$58 := $3ca]} fgCurMemoryVN[GcHeap] assigned for StoreField at [000207] to VN: $3cb. N011 [000207] ASG => $VN.Void ***** BB47, STMT00038(after) N011 ( 11, 11) [000207] -A-XG---R--- * ASG int $VN.Void N010 ( 4, 4) [000206] D--XG--N---- +--* IND int $73a N009 ( 2, 2) [001081] -------N---- | \--* ADD byref $28f N007 ( 1, 1) [000201] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001080] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N006 ( 6, 6) [000205] ---XG------- \--* ADD int N004 ( 4, 4) [000203] ---XG------- +--* IND int N003 ( 2, 2) [001083] -------N---- | \--* ADD byref $28f N001 ( 1, 1) [000202] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001082] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N005 ( 1, 1) [000204] ------------ \--* CNS_INT int -1 $c4 finish(BB47). Succ(BB55). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 8/2 to $781 {PhiDef($8, $2, $2a4)} . SSA PHI definition: set VN of local 4/2 to $684 {PhiDef($4, $2, $2a4)} . SSA PHI definition: set VN of local 10/1 to $3cc {PhiDef($a, $1, $309)} . Building phi application: $e2 = SSA# 23. Building phi application: $d3 = SSA# 16. Building phi application: $7c6 = phi($d3, $e2). The SSA definition for GcHeap (#12) at start of BB55 is $7c7 {PhiMemoryDef($60, $7c6)} ***** BB55, STMT00021(before) N019 ( 39, 38) [000099] -A-XG---R--- * ASG byref N018 ( 3, 2) [000098] D------N---- +--* LCL_VAR byref V11 loc7 d:1 N017 ( 35, 35) [001128] ---XG------- \--* COMMA byref N004 ( 10, 12) [001121] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 3, 2) [000095] ------------ | +--* LCL_VAR int V10 loc6 u:1 N003 ( 3, 3) [001120] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000094] ------------ | \--* LCL_VAR ref V04 loc0 u:2 N016 ( 25, 23) [001131] ----G------- \--* ADDR byref N015 ( 13, 12) [000096] a---G--N---- \--* IND struct N014 ( 12, 11) [001127] -------N---- \--* ADD byref N005 ( 1, 1) [001118] ------------ +--* LCL_VAR ref V04 loc0 u:2 N013 ( 11, 10) [001126] -------N---- \--* ADD long N011 ( 10, 9) [001124] -------N---- +--* LSH long N009 ( 9, 8) [001130] ------------ | +--* MUL long N007 ( 4, 4) [001122] ------------ | | +--* CAST long <- int N006 ( 3, 2) [001119] i----------- | | | \--* LCL_VAR int V10 loc6 u:1 N008 ( 1, 1) [001129] ------------ | | \--* CNS_INT long 3 N010 ( 1, 1) [001123] -------N---- | \--* CNS_INT long 3 N012 ( 1, 1) [001125] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] N001 [000095] LCL_VAR V10 loc6 u:1 => $3cc {PhiDef($a, $1, $309)} N002 [000094] LCL_VAR V04 loc0 u:2 => $684 {PhiDef($4, $2, $2a4)} N003 [001120] ARR_LENGTH => $73d {norm=$40a {ARR_LENGTH($684)}, exc=$7c8 {NullPtrExc($684)}} N004 [001121] ARR_BOUNDS_CHECK_Rng => $7cd {norm=$3 {3}, exc=$7cc( {NullPtrExc($684)}, {IndexOutOfRangeExc($3cc, $40a)})} N005 [001118] LCL_VAR V04 loc0 u:2 => $684 {PhiDef($4, $2, $2a4)} N006 [001119] LCL_VAR V10 loc6 u:1 => $3cc {PhiDef($a, $1, $309)} VNForCastOper(long) is $d6 N007 [001122] CAST => $6dc {Cast($3cc, $d6)} N008 [001129] CNS_INT 3 => $24b {LngCns: 3} N009 [001130] MUL => $6dd {MUL($24b, $6dc)} N010 [001123] CNS_INT 3 => $24b {LngCns: 3} N011 [001124] LSH => $6de {LSH($6dd, $24b)} N012 [001125] CNS_INT 16 Fseq[#FirstElem] => $241 {LngCns: 16} N013 [001126] ADD => $6df {ADD($241, $6de)} N014 [001127] ADD => $2a5 {ADD($684, $6df)} VNForHandle(arrElemType: Entry[__Canon,__Canon]) is $40 Relabeled IND_ARR_INDEX address node [001127] with l:$8c: {PtrToArrElem($40, $684, $6dc, $0)} AX2: $40 != $59 ==> select([$3c7]store($74f, $59, $3c6), $40) ==> select($74f, $40). AX2: $40 != $58 ==> select([$3cb]store($3c9, $58, $3ca), $40) ==> select($3c9, $40). AX2: $40 != $5d ==> select([$3c9]store($778, $5d, $3c8), $40) ==> select($778, $40). VNForMapSelect($7c7, $40):ref returns $7d4 {$7c7[$40]} VNForMapSelect($7d4, $684):ref returns $7d5 {$7d4[$684]} VNForMapSelect($7d5, $6dc):struct returns $505 {$7d5[$6dc]} hAtArrType $7d4 is MapSelect(curGcHeap($7c7), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $7d5 is MapSelect(hAtArrType($7d4), arr=$684). wholeElem $505 is MapSelect(hAtArrTypeAtArr($7d5), ind=$6dc). N015 [000096] IND => N016 [001131] ADDR => $8c {PtrToArrElem($40, $684, $6dc, $0)} N017 [001128] COMMA => $2a6 {norm=$8c {PtrToArrElem($40, $684, $6dc, $0)}, exc=$7cc( {NullPtrExc($684)}, {IndexOutOfRangeExc($3cc, $40a)})} N018 [000098] LCL_VAR V11 loc7 d:1 => $8c {PtrToArrElem($40, $684, $6dc, $0)} N019 [000099] ASG => $2a6 {norm=$8c {PtrToArrElem($40, $684, $6dc, $0)}, exc=$7cc( {NullPtrExc($684)}, {IndexOutOfRangeExc($3cc, $40a)})} ***** BB55, STMT00021(after) N019 ( 39, 38) [000099] -A-XG---R--- * ASG byref $2a6 N018 ( 3, 2) [000098] D------N---- +--* LCL_VAR byref V11 loc7 d:1 $8c N017 ( 35, 35) [001128] ---XG------- \--* COMMA byref $2a6 N004 ( 10, 12) [001121] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $7cd N001 ( 3, 2) [000095] ------------ | +--* LCL_VAR int V10 loc6 u:1 $3cc N003 ( 3, 3) [001120] ---X-------- | \--* ARR_LENGTH int $73d N002 ( 1, 1) [000094] ------------ | \--* LCL_VAR ref V04 loc0 u:2 $684 N016 ( 25, 23) [001131] ----G------- \--* ADDR byref $8c N015 ( 13, 12) [000096] a---G--N---- \--* IND struct N014 ( 12, 11) [001127] -------N---- \--* ADD byref $8c N005 ( 1, 1) [001118] ------------ +--* LCL_VAR ref V04 loc0 u:2 $684 N013 ( 11, 10) [001126] -------N---- \--* ADD long $6df N011 ( 10, 9) [001124] -------N---- +--* LSH long $6de N009 ( 9, 8) [001130] ------------ | +--* MUL long $6dd N007 ( 4, 4) [001122] ------------ | | +--* CAST long <- int $6dc N006 ( 3, 2) [001119] i----------- | | | \--* LCL_VAR int V10 loc6 u:1 $3cc N008 ( 1, 1) [001129] ------------ | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [001123] -------N---- | \--* CNS_INT long 3 $24b N012 ( 1, 1) [001125] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 --------- ***** BB55, STMT00022(before) N006 ( 8, 7) [000103] -A-XG------- * ASG int N004 ( 6, 5) [000102] *--XG--N---- +--* IND int N003 ( 4, 3) [001133] -------N---- | \--* ADD byref N001 ( 3, 2) [000100] ------------ | +--* LCL_VAR byref V11 loc7 u:1 N002 ( 1, 1) [001132] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] N005 ( 1, 1) [000101] ------------ \--* LCL_VAR int V06 loc2 u:1 (last use) N001 [000100] LCL_VAR V11 loc7 u:1 => $8c {PtrToArrElem($40, $684, $6dc, $0)} N002 [001132] CNS_INT 16 field offset Fseq[hashCode] => $241 {LngCns: 16} FieldSeq {hashCode} is $45c N003 [001133] ADD => $8d {PtrToArrElem($40, $684, $6dc, $45c)} N005 [000101] LCL_VAR V06 loc2 u:1 (last use) => $3c0 {PhiDef($f, $1, $309)} Tree [000103] assigns to an array element: VNForMapSelect($7c7, $40):ref returns $7d4 {$7c7[$40]} VNForMapSelect($7d4, $684):ref returns $7d5 {$7d4[$684]} VNForMapSelect($7d5, $6dc):struct returns $505 {$7d5[$6dc]} VNApplySelectorsAssign: VNForHandle(hashCode) is $50, fieldType is int VNForMapStore($505, $50, $3c0):int returns $3cd {$505[$50 := $3c0]} VNForMapStore($7d5, $6dc, $3cd):int returns $3ce {$7d5[$6dc := $3cd]} VNForMapStore($7d4, $684, $3ce):ref returns $685 {$7d4[$684 := $3ce]} hAtArrType $7d4 is MapSelect(curGcHeap($7c7), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $7d5 is MapSelect(hAtArrType($7d4), arr=$684) hAtArrTypeAtArrAtInx $505 is MapSelect(hAtArrTypeAtArr($7d5), inx=$6dc):struct newValAtInd $3cd is {$505[$50 := $3c0]} newValAtArr $3ce is {$7d5[$6dc := $3cd]} newValAtArrType $685 is {$7d4[$684 := $3ce]} VNForMapStore($7c7, $40, $685):ref returns $686 {$7c7[$40 := $685]} fgCurMemoryVN[GcHeap] assigned for ArrIndexAssign (case 1) at [000103] to VN: $686. N006 [000103] ASG => $VN.Void ***** BB55, STMT00022(after) N006 ( 8, 7) [000103] -A-XG------- * ASG int $VN.Void N004 ( 6, 5) [000102] *--XG--N---- +--* IND int $3c0 N003 ( 4, 3) [001133] -------N---- | \--* ADD byref $8d N001 ( 3, 2) [000100] ------------ | +--* LCL_VAR byref V11 loc7 u:1 $8c N002 ( 1, 1) [001132] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N005 ( 1, 1) [000101] ------------ \--* LCL_VAR int V06 loc2 u:1 (last use) $3c0 --------- ***** BB55, STMT00023(before) N009 ( 15, 12) [000110] -A-XG---R--- * ASG int N008 ( 6, 5) [000109] *--XG--N---- +--* IND int N007 ( 4, 3) [001135] -------N---- | \--* ADD byref N005 ( 3, 2) [000104] ------------ | +--* LCL_VAR byref V11 loc7 u:1 N006 ( 1, 1) [001134] ------------ | \--* CNS_INT long 20 field offset Fseq[next] N004 ( 8, 6) [000108] ---XG------- \--* ADD int N002 ( 6, 4) [000106] *--XG------- +--* IND int N001 ( 3, 2) [000105] ------------ | \--* LCL_VAR byref V08 loc4 u:2 N003 ( 1, 1) [000107] ------------ \--* CNS_INT int -1 N001 [000105] LCL_VAR V08 loc4 u:2 => $781 {PhiDef($8, $2, $2a4)} N002 [000106] IND => N003 [000107] CNS_INT -1 => $c4 {IntCns -1} N004 [000108] ADD => N005 [000104] LCL_VAR V11 loc7 u:1 => $8c {PtrToArrElem($40, $684, $6dc, $0)} N006 [001134] CNS_INT 20 field offset Fseq[next] => $24c {LngCns: 20} FieldSeq {next} is $46d N007 [001135] ADD => $8e {PtrToArrElem($40, $684, $6dc, $46d)} Tree [000110] assigns to an array element: AX1: select([$7c7]store($686, $40, $685), $40) ==> $685. VNForMapSelect($686, $40):ref returns $685 {$7d4[$684 := $3ce]} AX1: select([$7d4]store($685, $684, $3ce), $684) ==> $3ce. VNForMapSelect($685, $684):ref returns $3ce {$7d5[$6dc := $3cd]} AX1: select([$7d5]store($3ce, $6dc, $3cd), $6dc) ==> $3cd. VNForMapSelect($3ce, $6dc):struct returns $3cd {$505[$50 := $3c0]} VNApplySelectorsAssign: VNForHandle(next) is $55, fieldType is int VNForMapStore($3cd, $55, $801):int returns $3d0 {$3cd[$55 := $801]} VNForMapStore($3ce, $6dc, $3d0):int returns $3d1 {$3ce[$6dc := $3d0]} VNForMapStore($685, $684, $3d1):ref returns $687 {$685[$684 := $3d1]} hAtArrType $685 is MapSelect(curGcHeap($686), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $3ce is MapSelect(hAtArrType($685), arr=$684) hAtArrTypeAtArrAtInx $3cd is MapSelect(hAtArrTypeAtArr($3ce), inx=$6dc):struct newValAtInd $3d0 is {$3cd[$55 := $801]} newValAtArr $3d1 is {$3ce[$6dc := $3d0]} newValAtArrType $687 is {$685[$684 := $3d1]} VNForMapStore($686, $40, $687):ref returns $688 {$686[$40 := $687]} fgCurMemoryVN[GcHeap] assigned for ArrIndexAssign (case 1) at [000110] to VN: $688. N009 [000110] ASG => $VN.Void ***** BB55, STMT00023(after) N009 ( 15, 12) [000110] -A-XG---R--- * ASG int $VN.Void N008 ( 6, 5) [000109] *--XG--N---- +--* IND int N007 ( 4, 3) [001135] -------N---- | \--* ADD byref $8e N005 ( 3, 2) [000104] ------------ | +--* LCL_VAR byref V11 loc7 u:1 $8c N006 ( 1, 1) [001134] ------------ | \--* CNS_INT long 20 field offset Fseq[next] $24c N004 ( 8, 6) [000108] ---XG------- \--* ADD int N002 ( 6, 4) [000106] *--XG------- +--* IND int N001 ( 3, 2) [000105] ------------ | \--* LCL_VAR byref V08 loc4 u:2 $781 N003 ( 1, 1) [000107] ------------ \--* CNS_INT int -1 $c4 --------- ***** BB55, STMT00024(before) N004 ( 8, 6) [000114] -A-XG------- * ASG ref N002 ( 6, 4) [000113] *--XG--N---- +--* IND ref N001 ( 3, 2) [000111] ------------ | \--* LCL_VAR byref V11 loc7 u:1 Zero Fseq[key] N003 ( 1, 1) [000112] ------------ \--* LCL_VAR ref V01 arg1 u:1 (last use) FieldSeq {key} is $45d N001 [000111] LCL_VAR V11 loc7 u:1 => $8f {PtrToArrElem($40, $684, $6dc, $45d)} N003 [000112] LCL_VAR V01 arg1 u:1 (last use) => $101 {InitVal($c1)} Tree [000114] assigns to an array element: AX1: select([$686]store($688, $40, $687), $40) ==> $687. VNForMapSelect($688, $40):ref returns $687 {$685[$684 := $3d1]} AX1: select([$685]store($687, $684, $3d1), $684) ==> $3d1. VNForMapSelect($687, $684):ref returns $3d1 {$3ce[$6dc := $3d0]} AX1: select([$3ce]store($3d1, $6dc, $3d0), $6dc) ==> $3d0. VNForMapSelect($3d1, $6dc):struct returns $3d0 {$3cd[$55 := $801]} VNApplySelectorsAssign: VNForHandle(key) is $51, fieldType is ref VNForMapStore($3d0, $51, $101):ref returns $689 {$3d0[$51 := $101]} VNForMapStore($3d1, $6dc, $689):ref returns $68a {$3d1[$6dc := $689]} VNForMapStore($687, $684, $68a):ref returns $68b {$687[$684 := $68a]} hAtArrType $687 is MapSelect(curGcHeap($688), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $3d1 is MapSelect(hAtArrType($687), arr=$684) hAtArrTypeAtArrAtInx $3d0 is MapSelect(hAtArrTypeAtArr($3d1), inx=$6dc):struct newValAtInd $689 is {$3d0[$51 := $101]} newValAtArr $68a is {$3d1[$6dc := $689]} newValAtArrType $68b is {$687[$684 := $68a]} VNForMapStore($688, $40, $68b):ref returns $68c {$688[$40 := $68b]} fgCurMemoryVN[GcHeap] assigned for ArrIndexAssign (case 1) at [000114] to VN: $68c. N004 [000114] ASG => $VN.Void ***** BB55, STMT00024(after) N004 ( 8, 6) [000114] -A-XG------- * ASG ref $VN.Void N002 ( 6, 4) [000113] *--XG--N---- +--* IND ref $101 N001 ( 3, 2) [000111] ------------ | \--* LCL_VAR byref V11 loc7 u:1 Zero Fseq[key] $8f N003 ( 1, 1) [000112] ------------ \--* LCL_VAR ref V01 arg1 u:1 (last use) $101 --------- ***** BB55, STMT00025(before) N006 ( 8, 7) [000118] -A-XG------- * ASG ref N004 ( 6, 5) [000117] *--XG--N---- +--* IND ref N003 ( 4, 3) [001137] -------N---- | \--* ADD byref N001 ( 3, 2) [000115] ------------ | +--* LCL_VAR byref V11 loc7 u:1 (last use) N002 ( 1, 1) [001136] ------------ | \--* CNS_INT long 8 field offset Fseq[value] N005 ( 1, 1) [000116] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) N001 [000115] LCL_VAR V11 loc7 u:1 (last use) => $8c {PtrToArrElem($40, $684, $6dc, $0)} N002 [001136] CNS_INT 8 field offset Fseq[value] => $240 {LngCns: 8} FieldSeq {value} is $468 N003 [001137] ADD => $90 {PtrToArrElem($40, $684, $6dc, $468)} N005 [000116] LCL_VAR V02 arg2 u:1 (last use) => $102 {InitVal($c2)} Tree [000118] assigns to an array element: AX1: select([$688]store($68c, $40, $68b), $40) ==> $68b. VNForMapSelect($68c, $40):ref returns $68b {$687[$684 := $68a]} AX1: select([$687]store($68b, $684, $68a), $684) ==> $68a. VNForMapSelect($68b, $684):ref returns $68a {$3d1[$6dc := $689]} AX1: select([$3d1]store($68a, $6dc, $689), $6dc) ==> $689. VNForMapSelect($68a, $6dc):struct returns $689 {$3d0[$51 := $101]} VNApplySelectorsAssign: VNForHandle(value) is $53, fieldType is ref VNForMapStore($689, $53, $102):ref returns $68d {$689[$53 := $102]} VNForMapStore($68a, $6dc, $68d):ref returns $68e {$68a[$6dc := $68d]} VNForMapStore($68b, $684, $68e):ref returns $68f {$68b[$684 := $68e]} hAtArrType $68b is MapSelect(curGcHeap($68c), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $68a is MapSelect(hAtArrType($68b), arr=$684) hAtArrTypeAtArrAtInx $689 is MapSelect(hAtArrTypeAtArr($68a), inx=$6dc):struct newValAtInd $68d is {$689[$53 := $102]} newValAtArr $68e is {$68a[$6dc := $68d]} newValAtArrType $68f is {$68b[$684 := $68e]} VNForMapStore($68c, $40, $68f):ref returns $690 {$68c[$40 := $68f]} fgCurMemoryVN[GcHeap] assigned for ArrIndexAssign (case 1) at [000118] to VN: $690. N006 [000118] ASG => $VN.Void ***** BB55, STMT00025(after) N006 ( 8, 7) [000118] -A-XG------- * ASG ref $VN.Void N004 ( 6, 5) [000117] *--XG--N---- +--* IND ref $102 N003 ( 4, 3) [001137] -------N---- | \--* ADD byref $90 N001 ( 3, 2) [000115] ------------ | +--* LCL_VAR byref V11 loc7 u:1 (last use) $8c N002 ( 1, 1) [001136] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N005 ( 1, 1) [000116] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 --------- ***** BB55, STMT00026(before) N006 ( 12, 9) [000124] -A-XG---R--- * ASG int N005 ( 6, 4) [000123] *--X---N---- +--* IND int N004 ( 3, 2) [000119] ------------ | \--* LCL_VAR byref V08 loc4 u:2 (last use) N003 ( 5, 4) [000122] ------------ \--* ADD int N001 ( 3, 2) [000120] ------------ +--* LCL_VAR int V10 loc6 u:1 (last use) N002 ( 1, 1) [000121] ------------ \--* CNS_INT int 1 N001 [000120] LCL_VAR V10 loc6 u:1 (last use) => $3cc {PhiDef($a, $1, $309)} N002 [000121] CNS_INT 1 => $c1 {IntCns 1} N003 [000122] ADD => $804 {ADD($c1, $3cc)} N004 [000119] LCL_VAR V08 loc4 u:2 (last use) => $781 {PhiDef($8, $2, $2a4)} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000124] to VN: $23d. N006 [000124] ASG => $VN.Void ***** BB55, STMT00026(after) N006 ( 12, 9) [000124] -A-XG---R--- * ASG int $VN.Void N005 ( 6, 4) [000123] *--X---N---- +--* IND int $804 N004 ( 3, 2) [000119] ------------ | \--* LCL_VAR byref V08 loc4 u:2 (last use) $781 N003 ( 5, 4) [000122] ------------ \--* ADD int $804 N001 ( 3, 2) [000120] ------------ +--* LCL_VAR int V10 loc6 u:1 (last use) $3cc N002 ( 1, 1) [000121] ------------ \--* CNS_INT int 1 $c1 --------- ***** BB55, STMT00027(before) N011 ( 11, 11) [000131] -A-XG---R--- * ASG int N010 ( 4, 4) [000130] D--XG--N---- +--* IND int N009 ( 2, 2) [001139] -------N---- | \--* ADD byref N007 ( 1, 1) [000125] ------------ | +--* LCL_VAR ref V00 this u:1 N008 ( 1, 1) [001138] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] N006 ( 6, 6) [000129] ---XG------- \--* ADD int N004 ( 4, 4) [000127] ---XG------- +--* IND int N003 ( 2, 2) [001141] -------N---- | \--* ADD byref N001 ( 1, 1) [000126] ------------ | +--* LCL_VAR ref V00 this u:1 N002 ( 1, 1) [001140] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] N005 ( 1, 1) [000128] ------------ \--* CNS_INT int 1 N001 [000126] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N002 [001140] CNS_INT 68 field offset Fseq[_version] => $24e {LngCns: 68} N003 [001141] ADD => $2a7 {ADD($100, $24e)} VNApplySelectors: VNForHandle(_version) is $61, fieldType is int VNForMapSelect($23d, $61):int returns $805 {$23d[$61]} VNForMapSelect($805, $100):int returns $806 {$805[$100]} N004 [000127] IND => N005 [000128] CNS_INT 1 => $c1 {IntCns 1} N006 [000129] ADD => N007 [000125] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N008 [001138] CNS_INT 68 field offset Fseq[_version] => $24e {LngCns: 68} N009 [001139] ADD => $2a7 {ADD($100, $24e)} VNApplySelectors: VNForHandle(_version) is $61, fieldType is int VNForMapSelect($23d, $61):int returns $805 {$23d[$61]} VNForMapSelect($805, $100):int returns $806 {$805[$100]} VNForMapStore($805, $100, $80a):int returns $3d2 {$805[$100 := $80a]} VNApplySelectorsAssign: VNForHandle(_version) is $61, fieldType is int VNForMapStore($23d, $61, $3d2):int returns $3d3 {$23d[$61 := $3d2]} fgCurMemoryVN[GcHeap] assigned for StoreField at [000131] to VN: $3d3. N011 [000131] ASG => $VN.Void ***** BB55, STMT00027(after) N011 ( 11, 11) [000131] -A-XG---R--- * ASG int $VN.Void N010 ( 4, 4) [000130] D--XG--N---- +--* IND int $80a N009 ( 2, 2) [001139] -------N---- | \--* ADD byref $2a7 N007 ( 1, 1) [000125] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001138] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] $24e N006 ( 6, 6) [000129] ---XG------- \--* ADD int N004 ( 4, 4) [000127] ---XG------- +--* IND int N003 ( 2, 2) [001141] -------N---- | \--* ADD byref $2a7 N001 ( 1, 1) [000126] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001140] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] $24e N005 ( 1, 1) [000128] ------------ \--* CNS_INT int 1 $c1 --------- ***** BB55, STMT00028(before) N004 ( 5, 5) [000148] ------------ * JTRUE void N003 ( 3, 3) [000147] N------N-U-- \--* LE int N001 ( 1, 1) [000145] ------------ +--* LCL_VAR int V07 loc3 u:2 (last use) N002 ( 1, 1) [000146] ------------ \--* CNS_INT int 100 N001 [000145] LCL_VAR V07 loc3 u:2 (last use) => $3c5 {PhiDef($7, $2, $610)} N002 [000146] CNS_INT 100 => $e3 {IntCns 100} N003 [000147] LE => $80d {LE_UN($3c5, $e3)} ***** BB55, STMT00028(after) N004 ( 5, 5) [000148] ------------ * JTRUE void N003 ( 3, 3) [000147] N------N-U-- \--* LE int $80d N001 ( 1, 1) [000145] ------------ +--* LCL_VAR int V07 loc3 u:2 (last use) $3c5 N002 ( 1, 1) [000146] ------------ \--* CNS_INT int 100 $e3 finish(BB55). Succ(BB56). Not yet completed. All preds complete, adding to allDone. Succ(BB58). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#13) at start of BB56 is $3d3 {$23d[$61 := $3d2]} The SSA definition for GcHeap (#13) at start of BB56 is $3d3 {$23d[$61 := $3d2]} ***** BB56, STMT00030(before) N008 ( 21, 22) [000156] --C-G------- * JTRUE void N007 ( 19, 20) [000155] J-C-G--N---- \--* EQ int N005 ( 17, 18) [000153] --C-G------- +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS N003 ( 1, 1) [000151] ------------ arg1 in rdx | +--* LCL_VAR ref V05 loc1 u:1 (last use) N004 ( 2, 10) [000152] H------N---- arg0 in rcx | \--* CNS_INT(h) long 0xd1ffab1e class N006 ( 1, 1) [000154] ------------ \--* CNS_INT ref null N001 [001143] ARGPLACE => $39d {39d} N002 [001142] ARGPLACE => $23e {23e} N003 [000151] LCL_VAR V05 loc1 u:1 (last use) => N004 [000152] CNS_INT(h) 0xd1ffab1e class => $62 {Hnd const: 0x00000000D1FFAB1E} VN of ARGPLACE tree [001143] updated to $62 {Hnd const: 0x00000000D1FFAB1E} VN of ARGPLACE tree [001142] updated to N005 [000153] CALL help => N006 [000154] CNS_INT null => $VN.Null N007 [000155] EQ => ***** BB56, STMT00030(after) N008 ( 21, 22) [000156] --C-G------- * JTRUE void N007 ( 19, 20) [000155] J-C-G--N---- \--* EQ int N005 ( 17, 18) [000153] --C-G------- +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS N003 ( 1, 1) [000151] ------------ arg1 in rdx | +--* LCL_VAR ref V05 loc1 u:1 (last use) N004 ( 2, 10) [000152] H------N---- arg0 in rcx | \--* CNS_INT(h) long 0xd1ffab1e class $62 N006 ( 1, 1) [000154] ------------ \--* CNS_INT ref null $VN.Null finish(BB56). Succ(BB57). Not yet completed. All preds complete, adding to allDone. Succ(BB58). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#13) at start of BB57 is $3d3 {$23d[$61 := $3d2]} The SSA definition for GcHeap (#13) at start of BB57 is $3d3 {$23d[$61 := $3d2]} ***** BB57, STMT00031(before) N008 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize N005 ( 3, 3) [000159] ---X-------- arg1 in rdx +--* ARR_LENGTH int N004 ( 1, 1) [000158] ------------ | \--* LCL_VAR ref V04 loc0 u:2 (last use) N006 ( 1, 1) [000157] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 N007 ( 1, 1) [000160] ------------ arg2 in r8 \--* CNS_INT int 1 N001 [001145] ARGPLACE => $23f {23f} N002 [001144] ARGPLACE => $1ec {1ec} N003 [001146] ARGPLACE => $1ed {1ed} N004 [000158] LCL_VAR V04 loc0 u:2 (last use) => $684 {PhiDef($4, $2, $2a4)} N005 [000159] ARR_LENGTH => $73d {norm=$40a {ARR_LENGTH($684)}, exc=$7c8 {NullPtrExc($684)}} N006 [000157] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} N007 [000160] CNS_INT 1 => $c1 {IntCns 1} VN of ARGPLACE tree [001144] updated to $100 {InitVal($c0)} VN of ARGPLACE tree [001146] updated to $73d {norm=$40a {ARR_LENGTH($684)}, exc=$7c8 {NullPtrExc($684)}} fgCurMemoryVN[GcHeap] assigned for CALL at [000161] to VN: $840. N008 [000161] CALL => $VN.Void ***** BB57, STMT00031(after) N008 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void N005 ( 3, 3) [000159] ---X-------- arg1 in rdx +--* ARR_LENGTH int $73d N004 ( 1, 1) [000158] ------------ | \--* LCL_VAR ref V04 loc0 u:2 (last use) $684 N006 ( 1, 1) [000157] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N007 ( 1, 1) [000160] ------------ arg2 in r8 \--* CNS_INT int 1 $c1 finish(BB57). Succ(BB58). Not yet completed. Not all preds complete Adding to notallDone, if necessary... The SSA definition for ByrefExposed (#25) at start of BB33 is $46f {PhiMemoryDef($56, $46e)} The SSA definition for GcHeap (#25) at start of BB33 is $46f {PhiMemoryDef($56, $46e)} ***** BB33, STMT00039(before) N023 ( 36, 39) [000215] ---XG------- * JTRUE void N022 ( 34, 37) [000214] N--XG--N-U-- \--* NE int N020 ( 32, 35) [000212] *--XG------- +--* IND int N019 ( 30, 33) [000948] ---XG--N---- | \--* ADD byref N017 ( 29, 32) [000959] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000952] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000209] ------------ | | | +--* LCL_VAR int V09 loc5 u:2 N003 ( 3, 3) [000951] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000208] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000962] ----G------- | | \--* ADDR byref N015 ( 11, 11) [000210] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000958] -------N---- | | \--* ADD byref N005 ( 1, 1) [000949] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000957] -------N---- | | \--* ADD long N011 ( 8, 8) [000955] -------N---- | | +--* LSH long N009 ( 7, 7) [000961] ------------ | | | +--* MUL long N007 ( 2, 3) [000953] ------------ | | | | +--* CAST long <- int N006 ( 1, 1) [000950] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:2 N008 ( 1, 1) [000960] ------------ | | | | \--* CNS_INT long 3 N010 ( 1, 1) [000954] -------N---- | | | \--* CNS_INT long 3 N012 ( 1, 1) [000956] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000947] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] N021 ( 1, 1) [000213] ------------ \--* LCL_VAR int V06 loc2 u:1 N001 [000209] LCL_VAR V09 loc5 u:2 => $3c4 {PhiDef($9, $2, $60b)} N002 [000208] LCL_VAR V04 loc0 u:1 => N003 [000951] ARR_LENGTH => N004 [000952] ARR_BOUNDS_CHECK_Rng => N005 [000949] LCL_VAR V04 loc0 u:1 => N006 [000950] LCL_VAR V09 loc5 u:2 => $3c4 {PhiDef($9, $2, $60b)} VNForCastOper(long) is $d6 N007 [000953] CAST => $6e1 {Cast($3c4, $d6)} N008 [000960] CNS_INT 3 => $24b {LngCns: 3} N009 [000961] MUL => $6e2 {MUL($24b, $6e1)} N010 [000954] CNS_INT 3 => $24b {LngCns: 3} N011 [000955] LSH => $6e3 {LSH($6e2, $24b)} N012 [000956] CNS_INT 16 Fseq[#FirstElem] => $241 {LngCns: 16} N013 [000957] ADD => $6e4 {ADD($241, $6e3)} N014 [000958] ADD => VNForHandle(arrElemType: Entry[__Canon,__Canon]) is $40 Relabeled IND_ARR_INDEX address node [000958] with l:$91: {PtrToArrElem($40, $2d3, $6e1, $0)} VNForMapSelect($46f, $40):ref returns $772 {$46f[$40]} VNForMapSelect($772, $2d3):ref returns $7e1 {$772[$2d3]} VNForMapSelect($7e1, $6e1):struct returns $506 {$7e1[$6e1]} hAtArrType $772 is MapSelect(curGcHeap($46f), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $7e1 is MapSelect(hAtArrType($772), arr=$2d3). wholeElem $506 is MapSelect(hAtArrTypeAtArr($7e1), ind=$6e1). N015 [000210] IND => N016 [000962] ADDR => $91 {PtrToArrElem($40, $2d3, $6e1, $0)} N017 [000959] COMMA => N018 [000947] CNS_INT 16 field offset Fseq[hashCode] => $241 {LngCns: 16} FieldSeq {hashCode} is $45c N019 [000948] ADD => $2ac {norm=$92 {PtrToArrElem($40, $2d3, $6e1, $45c)}, exc=$7de( {NullPtrExc($2d3)}, {IndexOutOfRangeExc($3c4, $403)})} VNForMapSelect($46f, $40):ref returns $772 {$46f[$40]} VNForMapSelect($772, $2d3):ref returns $7e1 {$772[$2d3]} VNForMapSelect($7e1, $6e1):struct returns $506 {$7e1[$6e1]} hAtArrType $772 is MapSelect(curGcHeap($46f), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $7e1 is MapSelect(hAtArrType($772), arr=$2d3). wholeElem $506 is MapSelect(hAtArrTypeAtArr($7e1), ind=$6e1). VNApplySelectors: VNForHandle(hashCode) is $50, fieldType is int VNForMapSelect($506, $50):int returns $810 {$506[$50]} selectedElem is $811 after applying selectors. N020 [000212] IND => N021 [000213] LCL_VAR V06 loc2 u:1 => $3c0 {PhiDef($f, $1, $309)} N022 [000214] NE => ***** BB33, STMT00039(after) N023 ( 36, 39) [000215] ---XG------- * JTRUE void N022 ( 34, 37) [000214] N--XG--N-U-- \--* NE int N020 ( 32, 35) [000212] *--XG------- +--* IND int N019 ( 30, 33) [000948] ---XG--N---- | \--* ADD byref $2ac N017 ( 29, 32) [000959] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000952] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000209] ------------ | | | +--* LCL_VAR int V09 loc5 u:2 $3c4 N003 ( 3, 3) [000951] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000208] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000962] ----G------- | | \--* ADDR byref $91 N015 ( 11, 11) [000210] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000958] -------N---- | | \--* ADD byref $91 N005 ( 1, 1) [000949] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000957] -------N---- | | \--* ADD long $6e4 N011 ( 8, 8) [000955] -------N---- | | +--* LSH long $6e3 N009 ( 7, 7) [000961] ------------ | | | +--* MUL long $6e2 N007 ( 2, 3) [000953] ------------ | | | | +--* CAST long <- int $6e1 N006 ( 1, 1) [000950] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:2 $3c4 N008 ( 1, 1) [000960] ------------ | | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000954] -------N---- | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000956] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000947] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N021 ( 1, 1) [000213] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 finish(BB33). Succ(BB34). Not yet completed. All preds complete, adding to allDone. Succ(BB42). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#25) at start of BB34 is $46f {PhiMemoryDef($56, $46e)} The SSA definition for GcHeap (#25) at start of BB34 is $46f {PhiMemoryDef($56, $46e)} ***** BB34, STMT00045(before) N020 ( 32, 34) [000246] -A-XG---R--- * ASG ref N019 ( 1, 1) [000245] D------N---- +--* LCL_VAR ref V17 tmp3 d:1 N018 ( 32, 34) [000973] ---XG------- \--* COMMA ref N004 ( 8, 11) [000966] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000236] ------------ | +--* LCL_VAR int V09 loc5 u:2 N003 ( 3, 3) [000965] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000235] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N017 ( 24, 23) [000977] *---G------- \--* IND ref N016 ( 21, 21) [000976] ----G------- \--* ADDR byref Zero Fseq[key] N015 ( 11, 11) [000237] a---G--N---- \--* IND struct N014 ( 10, 10) [000972] -------N---- \--* ADD byref N005 ( 1, 1) [000963] ------------ +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000971] -------N---- \--* ADD long N011 ( 8, 8) [000969] -------N---- +--* LSH long N009 ( 7, 7) [000975] ------------ | +--* MUL long N007 ( 2, 3) [000967] ------------ | | +--* CAST long <- int N006 ( 1, 1) [000964] i----------- | | | \--* LCL_VAR int V09 loc5 u:2 N008 ( 1, 1) [000974] ------------ | | \--* CNS_INT long 3 N010 ( 1, 1) [000968] -------N---- | \--* CNS_INT long 3 N012 ( 1, 1) [000970] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] N001 [000236] LCL_VAR V09 loc5 u:2 => $3c4 {PhiDef($9, $2, $60b)} N002 [000235] LCL_VAR V04 loc0 u:1 => N003 [000965] ARR_LENGTH => N004 [000966] ARR_BOUNDS_CHECK_Rng => N005 [000963] LCL_VAR V04 loc0 u:1 => N006 [000964] LCL_VAR V09 loc5 u:2 => $3c4 {PhiDef($9, $2, $60b)} VNForCastOper(long) is $d6 N007 [000967] CAST => $6e1 {Cast($3c4, $d6)} N008 [000974] CNS_INT 3 => $24b {LngCns: 3} N009 [000975] MUL => $6e2 {MUL($24b, $6e1)} N010 [000968] CNS_INT 3 => $24b {LngCns: 3} N011 [000969] LSH => $6e3 {LSH($6e2, $24b)} N012 [000970] CNS_INT 16 Fseq[#FirstElem] => $241 {LngCns: 16} N013 [000971] ADD => $6e4 {ADD($241, $6e3)} N014 [000972] ADD => VNForHandle(arrElemType: Entry[__Canon,__Canon]) is $40 Relabeled IND_ARR_INDEX address node [000972] with l:$91: {PtrToArrElem($40, $2d3, $6e1, $0)} VNForMapSelect($46f, $40):ref returns $772 {$46f[$40]} VNForMapSelect($772, $2d3):ref returns $7e1 {$772[$2d3]} VNForMapSelect($7e1, $6e1):struct returns $506 {$7e1[$6e1]} hAtArrType $772 is MapSelect(curGcHeap($46f), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $7e1 is MapSelect(hAtArrType($772), arr=$2d3). wholeElem $506 is MapSelect(hAtArrTypeAtArr($7e1), ind=$6e1). N015 [000237] IND => FieldSeq {key} is $45d N016 [000976] ADDR => $93 {PtrToArrElem($40, $2d3, $6e1, $45d)} VNForMapSelect($46f, $40):ref returns $772 {$46f[$40]} VNForMapSelect($772, $2d3):ref returns $7e1 {$772[$2d3]} VNForMapSelect($7e1, $6e1):struct returns $506 {$7e1[$6e1]} hAtArrType $772 is MapSelect(curGcHeap($46f), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $7e1 is MapSelect(hAtArrType($772), arr=$2d3). wholeElem $506 is MapSelect(hAtArrTypeAtArr($7e1), ind=$6e1). VNApplySelectors: VNForHandle(key) is $51, fieldType is ref VNForMapSelect($506, $51):ref returns $7e2 {$506[$51]} selectedElem is $7e2 after applying selectors. N017 [000977] IND => N018 [000973] COMMA => N019 [000245] LCL_VAR V17 tmp3 d:1 => N020 [000246] ASG => ***** BB34, STMT00045(after) N020 ( 32, 34) [000246] -A-XG---R--- * ASG ref N019 ( 1, 1) [000245] D------N---- +--* LCL_VAR ref V17 tmp3 d:1 N018 ( 32, 34) [000973] ---XG------- \--* COMMA ref N004 ( 8, 11) [000966] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000236] ------------ | +--* LCL_VAR int V09 loc5 u:2 $3c4 N003 ( 3, 3) [000965] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000235] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N017 ( 24, 23) [000977] *---G------- \--* IND ref N016 ( 21, 21) [000976] ----G------- \--* ADDR byref Zero Fseq[key] $93 N015 ( 11, 11) [000237] a---G--N---- \--* IND struct N014 ( 10, 10) [000972] -------N---- \--* ADD byref $91 N005 ( 1, 1) [000963] ------------ +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000971] -------N---- \--* ADD long $6e4 N011 ( 8, 8) [000969] -------N---- +--* LSH long $6e3 N009 ( 7, 7) [000975] ------------ | +--* MUL long $6e2 N007 ( 2, 3) [000967] ------------ | | +--* CAST long <- int $6e1 N006 ( 1, 1) [000964] i----------- | | | \--* LCL_VAR int V09 loc5 u:2 $3c4 N008 ( 1, 1) [000974] ------------ | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000968] -------N---- | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000970] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 --------- ***** BB34, STMT00044(before) N004 ( 3, 3) [000244] -A-X----R--- * ASG long N003 ( 1, 1) [000243] D------N---- +--* LCL_VAR long V16 tmp2 d:1 N002 ( 3, 2) [000242] #--X-------- \--* IND long N001 ( 1, 1) [000241] !----------- \--* LCL_VAR ref V00 this u:1 N001 [000241] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} VNForMapSelect($2, $100):ref returns $2e7 {$VN.ReadOnlyHeap[$100]} VNForMapSelect($2, $100):ref returns $2e7 {$VN.ReadOnlyHeap[$100]} N002 [000242] IND => $2e8 {norm=$2e7 {$VN.ReadOnlyHeap[$100]}, exc=$2c2 {NullPtrExc($100)}} N003 [000243] LCL_VAR V16 tmp2 d:1 => $2e7 {$VN.ReadOnlyHeap[$100]} N004 [000244] ASG => $2e8 {norm=$2e7 {$VN.ReadOnlyHeap[$100]}, exc=$2c2 {NullPtrExc($100)}} ***** BB34, STMT00044(after) N004 ( 3, 3) [000244] -A-X----R--- * ASG long $2e8 N003 ( 1, 1) [000243] D------N---- +--* LCL_VAR long V16 tmp2 d:1 $2e7 N002 ( 3, 2) [000242] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000241] !----------- \--* LCL_VAR ref V00 this u:1 $100 --------- ***** BB34, STMT00158(before) N011 ( 14, 13) [001163] ------------ * JTRUE void N010 ( 12, 11) [000263] J------N---- \--* EQ int N008 ( 10, 9) [000259] n----------- +--* IND long N007 ( 8, 7) [000255] -------N---- | \--* ADD long N005 ( 7, 6) [000253] #----------- | +--* IND long N004 ( 4, 4) [000252] #----------- | | \--* IND long N003 ( 2, 2) [000251] -------N---- | | \--* ADD long N001 ( 1, 1) [000249] ------------ | | +--* LCL_VAR long V16 tmp2 u:1 N002 ( 1, 1) [000250] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000254] ------------ | \--* CNS_INT long 48 N009 ( 1, 1) [000262] ------------ \--* CNS_INT long 0 N001 [000249] LCL_VAR V16 tmp2 u:1 => $2e7 {$VN.ReadOnlyHeap[$100]} N002 [000250] CNS_INT 56 => $244 {LngCns: 56} N003 [000251] ADD => $306 {ADD($244, $2e7)} VNForMapSelect($2, $306):ref returns $2e9 {$VN.ReadOnlyHeap[$306]} VNForMapSelect($2, $306):ref returns $2e9 {$VN.ReadOnlyHeap[$306]} N004 [000252] IND => $2e9 {$VN.ReadOnlyHeap[$306]} VNForMapSelect($2, $2e9):ref returns $2ea {$VN.ReadOnlyHeap[$2e9]} VNForMapSelect($2, $2e9):ref returns $2ea {$VN.ReadOnlyHeap[$2e9]} N005 [000253] IND => $2ea {$VN.ReadOnlyHeap[$2e9]} N006 [000254] CNS_INT 48 => $246 {LngCns: 48} N007 [000255] ADD => $6e6 {ADD($246, $2ea)} N008 [000259] IND => N009 [000262] CNS_INT 0 => $243 {LngCns: 0} N010 [000263] EQ => ***** BB34, STMT00158(after) N011 ( 14, 13) [001163] ------------ * JTRUE void N010 ( 12, 11) [000263] J------N---- \--* EQ int N008 ( 10, 9) [000259] n----------- +--* IND long N007 ( 8, 7) [000255] -------N---- | \--* ADD long $6e6 N005 ( 7, 6) [000253] #----------- | +--* IND long $2ea N004 ( 4, 4) [000252] #----------- | | \--* IND long $2e9 N003 ( 2, 2) [000251] -------N---- | | \--* ADD long $306 N001 ( 1, 1) [000249] ------------ | | +--* LCL_VAR long V16 tmp2 u:1 $2e7 N002 ( 1, 1) [000250] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000254] ------------ | \--* CNS_INT long 48 $246 N009 ( 1, 1) [000262] ------------ \--* CNS_INT long 0 $243 finish(BB34). Succ(BB35). Not yet completed. All preds complete, adding to allDone. Succ(BB36). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#25) at start of BB36 is $46f {PhiMemoryDef($56, $46e)} The SSA definition for GcHeap (#25) at start of BB36 is $46f {PhiMemoryDef($56, $46e)} ***** BB36, STMT00160(before) N007 ( 17, 18) [001167] -AC-G---R--- * ASG long N006 ( 1, 1) [001166] D------N---- +--* LCL_VAR long V19 tmp5 d:2 N005 ( 17, 18) [000261] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 1, 1) [000248] ------?----- arg0 in rcx +--* LCL_VAR long V16 tmp2 u:1 (last use) N004 ( 2, 10) [000260] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr N001 [000978] ARGPLACE => $3a0 {3a0} N002 [000979] ARGPLACE => $3a1 {3a1} N003 [000248] LCL_VAR V16 tmp2 u:1 (last use) => $2e7 {$VN.ReadOnlyHeap[$100]} N004 [000260] CNS_INT(h) 0xd1ffab1e global ptr => $63 {Hnd const: 0x00000000D1FFAB1E} VN of ARGPLACE tree [000978] updated to $2e7 {$VN.ReadOnlyHeap[$100]} VN of ARGPLACE tree [000979] updated to $63 {Hnd const: 0x00000000D1FFAB1E} N005 [000261] CALL help => $6e7 {RuntimeHandleClass($2e7, $63)} N006 [001166] LCL_VAR V19 tmp5 d:2 => $6e7 {RuntimeHandleClass($2e7, $63)} N007 [001167] ASG => $6e7 {RuntimeHandleClass($2e7, $63)} ***** BB36, STMT00160(after) N007 ( 17, 18) [001167] -AC-G---R--- * ASG long $6e7 N006 ( 1, 1) [001166] D------N---- +--* LCL_VAR long V19 tmp5 d:2 $6e7 N005 ( 17, 18) [000261] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $6e7 N003 ( 1, 1) [000248] ------?----- arg0 in rcx +--* LCL_VAR long V16 tmp2 u:1 (last use) $2e7 N004 ( 2, 10) [000260] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $63 finish(BB36). Succ(BB37). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#25) at start of BB35 is $46f {PhiMemoryDef($56, $46e)} The SSA definition for GcHeap (#25) at start of BB35 is $46f {PhiMemoryDef($56, $46e)} ***** BB35, STMT00159(before) N010 ( 10, 9) [001165] -A------R--- * ASG long N009 ( 1, 1) [001164] D------N---- +--* LCL_VAR long V19 tmp5 d:3 N008 ( 10, 9) [000264] n-----?----- \--* IND long N007 ( 8, 7) [000265] ------?N---- \--* ADD long N005 ( 7, 6) [000266] #-----?----- +--* IND long N004 ( 4, 4) [000267] #-----?----- | \--* IND long N003 ( 2, 2) [000268] ------?N---- | \--* ADD long N001 ( 1, 1) [000269] ------?----- | +--* LCL_VAR long V16 tmp2 u:1 (last use) N002 ( 1, 1) [000270] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000271] ------?----- \--* CNS_INT long 48 N001 [000269] LCL_VAR V16 tmp2 u:1 (last use) => $2e7 {$VN.ReadOnlyHeap[$100]} N002 [000270] CNS_INT 56 => $244 {LngCns: 56} N003 [000268] ADD => $306 {ADD($244, $2e7)} VNForMapSelect($2, $306):ref returns $2e9 {$VN.ReadOnlyHeap[$306]} VNForMapSelect($2, $306):ref returns $2e9 {$VN.ReadOnlyHeap[$306]} N004 [000267] IND => $2e9 {$VN.ReadOnlyHeap[$306]} VNForMapSelect($2, $2e9):ref returns $2ea {$VN.ReadOnlyHeap[$2e9]} VNForMapSelect($2, $2e9):ref returns $2ea {$VN.ReadOnlyHeap[$2e9]} N005 [000266] IND => $2ea {$VN.ReadOnlyHeap[$2e9]} N006 [000271] CNS_INT 48 => $246 {LngCns: 48} N007 [000265] ADD => $6e6 {ADD($246, $2ea)} N008 [000264] IND => N009 [001164] LCL_VAR V19 tmp5 d:3 => N010 [001165] ASG => ***** BB35, STMT00159(after) N010 ( 10, 9) [001165] -A------R--- * ASG long N009 ( 1, 1) [001164] D------N---- +--* LCL_VAR long V19 tmp5 d:3 N008 ( 10, 9) [000264] n-----?----- \--* IND long N007 ( 8, 7) [000265] ------?N---- \--* ADD long $6e6 N005 ( 7, 6) [000266] #-----?----- +--* IND long $2ea N004 ( 4, 4) [000267] #-----?----- | \--* IND long $2e9 N003 ( 2, 2) [000268] ------?N---- | \--* ADD long $306 N001 ( 1, 1) [000269] ------?----- | +--* LCL_VAR long V16 tmp2 u:1 (last use) $2e7 N002 ( 1, 1) [000270] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000271] ------?----- \--* CNS_INT long 48 $246 finish(BB35). Succ(BB37). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 19/1 to $349 {PhiDef($13, $1, $309)} . The SSA definition for ByrefExposed (#25) at start of BB37 is $46f {PhiMemoryDef($56, $46e)} The SSA definition for GcHeap (#25) at start of BB37 is $46f {PhiMemoryDef($56, $46e)} ***** BB37, STMT00049(before) N013 ( 32, 18) [000283] --CXG------- * JTRUE void N012 ( 30, 16) [000282] J-CXG--N---- \--* EQ int N010 ( 28, 14) [000280] --CXG------- +--* CALL ind stub int N009 ( 1, 1) [000279] ------------ calli tgt | \--* LCL_VAR long V19 tmp5 u:1 (last use) N005 ( 1, 1) [000234] ------------ this in rcx | +--* LCL_VAR ref V05 loc1 u:1 N006 ( 1, 1) [000980] ------------ arg1 in r11 | +--* LCL_VAR long V19 tmp5 u:1 r11 REG r11 N007 ( 1, 1) [000247] ------------ arg2 in rdx | +--* LCL_VAR ref V17 tmp3 u:1 (last use) N008 ( 1, 1) [000258] ------------ arg3 in r8 | \--* LCL_VAR ref V01 arg1 u:1 N011 ( 1, 1) [000281] ------------ \--* CNS_INT int 0 N001 [000981] ARGPLACE => $843 {843} N002 [000982] ARGPLACE => $3a5 {3a5} N003 [000983] ARGPLACE => $844 {844} N004 [000984] ARGPLACE => $845 {845} N005 [000234] LCL_VAR V05 loc1 u:1 => N006 [000980] LCL_VAR V19 tmp5 u:1 r11 => $349 {PhiDef($13, $1, $309)} N007 [000247] LCL_VAR V17 tmp3 u:1 (last use) => N008 [000258] LCL_VAR V01 arg1 u:1 => $101 {InitVal($c1)} N009 [000279] LCL_VAR V19 tmp5 u:1 (last use) => $349 {PhiDef($13, $1, $309)} VN of ARGPLACE tree [000982] updated to VN of ARGPLACE tree [000983] updated to $349 {PhiDef($13, $1, $309)} VN of ARGPLACE tree [000984] updated to fgCurMemoryVN[GcHeap] assigned for CALL at [000280] to VN: $846. N010 [000280] CALL ind stub => $1ef {1ef} N011 [000281] CNS_INT 0 => $c0 {IntCns 0} N012 [000282] EQ => $817 {EQ($1ef, $c0)} ***** BB37, STMT00049(after) N013 ( 32, 18) [000283] --CXG------- * JTRUE void N012 ( 30, 16) [000282] J-CXG--N---- \--* EQ int $817 N010 ( 28, 14) [000280] --CXG------- +--* CALL ind stub int $1ef N009 ( 1, 1) [000279] ------------ calli tgt | \--* LCL_VAR long V19 tmp5 u:1 (last use) $349 N005 ( 1, 1) [000234] ------------ this in rcx | +--* LCL_VAR ref V05 loc1 u:1 N006 ( 1, 1) [000980] ------------ arg1 in r11 | +--* LCL_VAR long V19 tmp5 u:1 r11 REG r11 $349 N007 ( 1, 1) [000247] ------------ arg2 in rdx | +--* LCL_VAR ref V17 tmp3 u:1 (last use) N008 ( 1, 1) [000258] ------------ arg3 in r8 | \--* LCL_VAR ref V01 arg1 u:1 $101 N011 ( 1, 1) [000281] ------------ \--* CNS_INT int 0 $c0 finish(BB37). Succ(BB38). Not yet completed. All preds complete, adding to allDone. Succ(BB42). Not yet completed. All preds complete, adding to allDone. Building phi application: $e4 = SSA# 27. Building phi application: $dc = SSA# 25. Building phi application: $7e5 = phi($dc, $e4). The SSA definition for GcHeap (#26) at start of BB42 is $7e6 {PhiMemoryDef($64, $7e5)} ***** BB42, STMT00040(before) N022 ( 32, 35) [000222] -A-XG---R--- * ASG int N021 ( 1, 1) [000221] D------N---- +--* LCL_VAR int V09 loc5 d:3 N020 ( 32, 35) [000220] *--XG------- \--* IND int N019 ( 30, 33) [001009] ---XG--N---- \--* ADD byref N017 ( 29, 32) [001020] ---XG------- +--* COMMA byref N004 ( 8, 11) [001013] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000217] ------------ | | +--* LCL_VAR int V09 loc5 u:2 N003 ( 3, 3) [001012] ---X-------- | | \--* ARR_LENGTH int N002 ( 1, 1) [000216] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [001023] ----G------- | \--* ADDR byref N015 ( 11, 11) [000218] a---G--N---- | \--* IND struct N014 ( 10, 10) [001019] -------N---- | \--* ADD byref N005 ( 1, 1) [001010] ------------ | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [001018] -------N---- | \--* ADD long N011 ( 8, 8) [001016] -------N---- | +--* LSH long N009 ( 7, 7) [001022] ------------ | | +--* MUL long N007 ( 2, 3) [001014] ------------ | | | +--* CAST long <- int N006 ( 1, 1) [001011] i----------- | | | | \--* LCL_VAR int V09 loc5 u:2 (last use) N008 ( 1, 1) [001021] ------------ | | | \--* CNS_INT long 3 N010 ( 1, 1) [001015] -------N---- | | \--* CNS_INT long 3 N012 ( 1, 1) [001017] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [001008] ------------ \--* CNS_INT long 20 field offset Fseq[next] N001 [000217] LCL_VAR V09 loc5 u:2 => $3c4 {PhiDef($9, $2, $60b)} N002 [000216] LCL_VAR V04 loc0 u:1 => N003 [001012] ARR_LENGTH => N004 [001013] ARR_BOUNDS_CHECK_Rng => N005 [001010] LCL_VAR V04 loc0 u:1 => N006 [001011] LCL_VAR V09 loc5 u:2 (last use) => $3c4 {PhiDef($9, $2, $60b)} VNForCastOper(long) is $d6 N007 [001014] CAST => $6e1 {Cast($3c4, $d6)} N008 [001021] CNS_INT 3 => $24b {LngCns: 3} N009 [001022] MUL => $6e2 {MUL($24b, $6e1)} N010 [001015] CNS_INT 3 => $24b {LngCns: 3} N011 [001016] LSH => $6e3 {LSH($6e2, $24b)} N012 [001017] CNS_INT 16 Fseq[#FirstElem] => $241 {LngCns: 16} N013 [001018] ADD => $6e4 {ADD($241, $6e3)} N014 [001019] ADD => VNForHandle(arrElemType: Entry[__Canon,__Canon]) is $40 Relabeled IND_ARR_INDEX address node [001019] with l:$91: {PtrToArrElem($40, $2d3, $6e1, $0)} VNForMapSelect($7e6, $40):ref returns $7e8 {$7e6[$40]} VNForMapSelect($7e8, $2d3):ref returns $7e9 {$7e8[$2d3]} VNForMapSelect($7e9, $6e1):struct returns $507 {$7e9[$6e1]} hAtArrType $7e8 is MapSelect(curGcHeap($7e6), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $7e9 is MapSelect(hAtArrType($7e8), arr=$2d3). wholeElem $507 is MapSelect(hAtArrTypeAtArr($7e9), ind=$6e1). N015 [000218] IND => N016 [001023] ADDR => $91 {PtrToArrElem($40, $2d3, $6e1, $0)} N017 [001020] COMMA => N018 [001008] CNS_INT 20 field offset Fseq[next] => $24c {LngCns: 20} FieldSeq {next} is $46d N019 [001009] ADD => $2ad {norm=$94 {PtrToArrElem($40, $2d3, $6e1, $46d)}, exc=$7de( {NullPtrExc($2d3)}, {IndexOutOfRangeExc($3c4, $403)})} VNForMapSelect($7e6, $40):ref returns $7e8 {$7e6[$40]} VNForMapSelect($7e8, $2d3):ref returns $7e9 {$7e8[$2d3]} VNForMapSelect($7e9, $6e1):struct returns $507 {$7e9[$6e1]} hAtArrType $7e8 is MapSelect(curGcHeap($7e6), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $7e9 is MapSelect(hAtArrType($7e8), arr=$2d3). wholeElem $507 is MapSelect(hAtArrTypeAtArr($7e9), ind=$6e1). VNApplySelectors: VNForHandle(next) is $55, fieldType is int VNForMapSelect($507, $55):int returns $818 {$507[$55]} selectedElem is $819 after applying selectors. N020 [000220] IND => N021 [000221] LCL_VAR V09 loc5 d:3 => N022 [000222] ASG => ***** BB42, STMT00040(after) N022 ( 32, 35) [000222] -A-XG---R--- * ASG int N021 ( 1, 1) [000221] D------N---- +--* LCL_VAR int V09 loc5 d:3 N020 ( 32, 35) [000220] *--XG------- \--* IND int N019 ( 30, 33) [001009] ---XG--N---- \--* ADD byref $2ad N017 ( 29, 32) [001020] ---XG------- +--* COMMA byref N004 ( 8, 11) [001013] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000217] ------------ | | +--* LCL_VAR int V09 loc5 u:2 $3c4 N003 ( 3, 3) [001012] ---X-------- | | \--* ARR_LENGTH int N002 ( 1, 1) [000216] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [001023] ----G------- | \--* ADDR byref $91 N015 ( 11, 11) [000218] a---G--N---- | \--* IND struct N014 ( 10, 10) [001019] -------N---- | \--* ADD byref $91 N005 ( 1, 1) [001010] ------------ | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [001018] -------N---- | \--* ADD long $6e4 N011 ( 8, 8) [001016] -------N---- | +--* LSH long $6e3 N009 ( 7, 7) [001022] ------------ | | +--* MUL long $6e2 N007 ( 2, 3) [001014] ------------ | | | +--* CAST long <- int $6e1 N006 ( 1, 1) [001011] i----------- | | | | \--* LCL_VAR int V09 loc5 u:2 (last use) $3c4 N008 ( 1, 1) [001021] ------------ | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [001015] -------N---- | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [001017] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [001008] ------------ \--* CNS_INT long 20 field offset Fseq[next] $24c --------- ***** BB42, STMT00041(before) N005 ( 3, 3) [000227] -A------R--- * ASG int N004 ( 1, 1) [000226] D------N---- +--* LCL_VAR int V07 loc3 d:4 N003 ( 3, 3) [000225] ------------ \--* ADD int N001 ( 1, 1) [000223] ------------ +--* LCL_VAR int V07 loc3 u:3 (last use) N002 ( 1, 1) [000224] ------------ \--* CNS_INT int 1 N001 [000223] LCL_VAR V07 loc3 u:3 (last use) => $3c3 {PhiDef($7, $3, $60a)} N002 [000224] CNS_INT 1 => $c1 {IntCns 1} N003 [000225] ADD => $81a {ADD($c1, $3c3)} N004 [000226] LCL_VAR V07 loc3 d:4 => $81a {ADD($c1, $3c3)} N005 [000227] ASG => $81a {ADD($c1, $3c3)} ***** BB42, STMT00041(after) N005 ( 3, 3) [000227] -A------R--- * ASG int $81a N004 ( 1, 1) [000226] D------N---- +--* LCL_VAR int V07 loc3 d:4 $81a N003 ( 3, 3) [000225] ------------ \--* ADD int $81a N001 ( 1, 1) [000223] ------------ +--* LCL_VAR int V07 loc3 u:3 (last use) $3c3 N002 ( 1, 1) [000224] ------------ \--* CNS_INT int 1 $c1 --------- ***** BB42, STMT00042(before) N005 ( 7, 7) [000232] ---X-------- * JTRUE void N004 ( 5, 5) [000231] N--X---N-U-- \--* LT int N002 ( 3, 3) [000230] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000229] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000228] ------------ \--* LCL_VAR int V07 loc3 u:4 N001 [000229] LCL_VAR V04 loc0 u:1 => N002 [000230] ARR_LENGTH => N003 [000228] LCL_VAR V07 loc3 u:4 => $81a {ADD($c1, $3c3)} N004 [000231] LT => ***** BB42, STMT00042(after) N005 ( 7, 7) [000232] ---X-------- * JTRUE void N004 ( 5, 5) [000231] N--X---N-U-- \--* LT int N002 ( 3, 3) [000230] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000229] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000228] ------------ \--* LCL_VAR int V07 loc3 u:4 $81a finish(BB42). Succ(BB43). Not yet completed. All preds complete, adding to allDone. Succ(BB68). Not yet completed. All preds complete, adding to allDone. Building phi application: $d2 = SSA# 32. Building phi application: $db = SSA# 26. Building phi application: $7ea = phi($db, $d2). The SSA definition for GcHeap (#9) at start of BB68 is $7eb {PhiMemoryDef($65, $7ea)} ***** BB68, STMT00043(before) N001 ( 14, 5) [000233] --CXG------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported fgCurMemoryVN[GcHeap] assigned for CALL at [000233] to VN: $847. N001 [000233] CALL => $VN.Void ***** BB68, STMT00043(after) N001 ( 14, 5) [000233] --CXG------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported $VN.Void finish(BB68). The SSA definition for ByrefExposed (#26) at start of BB43 is $7e6 {PhiMemoryDef($64, $7e5)} The SSA definition for GcHeap (#26) at start of BB43 is $7e6 {PhiMemoryDef($64, $7e5)} finish(BB43). Succ(BB32). The SSA definition for ByrefExposed (#27) at start of BB38 is $846 {846} The SSA definition for GcHeap (#27) at start of BB38 is $846 {846} ***** BB38, STMT00050(before) N005 ( 7, 8) [000287] ------------ * JTRUE void N004 ( 5, 6) [000286] N------N-U-- \--* NE int N002 ( 3, 4) [000985] ------------ +--* CAST int <- ubyte <- int N001 ( 2, 2) [000284] ------------ | \--* LCL_VAR int V03 arg3 u:1 N003 ( 1, 1) [000285] ------------ \--* CNS_INT int 1 N001 [000284] LCL_VAR V03 arg3 u:1 => $140 {InitVal($c3)} VNForCastOper(ubyte) is $d8 N002 [000985] CAST => $1be {Cast($140, $d8)} N003 [000285] CNS_INT 1 => $c1 {IntCns 1} N004 [000286] NE => $1bf {NE($1be, $c1)} ***** BB38, STMT00050(after) N005 ( 7, 8) [000287] ------------ * JTRUE void N004 ( 5, 6) [000286] N------N-U-- \--* NE int $1bf N002 ( 3, 4) [000985] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000284] ------------ | \--* LCL_VAR int V03 arg3 u:1 $140 N003 ( 1, 1) [000285] ------------ \--* CNS_INT int 1 $c1 finish(BB38). Succ(BB39). Not yet completed. All preds complete, adding to allDone. Succ(BB40). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#27) at start of BB40 is $846 {846} The SSA definition for GcHeap (#27) at start of BB40 is $846 {846} ***** BB40, STMT00051(before) N005 ( 7, 8) [000291] ------------ * JTRUE void N004 ( 5, 6) [000290] N------N-U-- \--* EQ int N002 ( 3, 4) [001002] ------------ +--* CAST int <- ubyte <- int N001 ( 2, 2) [000288] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) N003 ( 1, 1) [000289] ------------ \--* CNS_INT int 2 N001 [000288] LCL_VAR V03 arg3 u:1 (last use) => $140 {InitVal($c3)} VNForCastOper(ubyte) is $d8 N002 [001002] CAST => $1be {Cast($140, $d8)} N003 [000289] CNS_INT 2 => $c2 {IntCns 2} N004 [000290] EQ => $600 {EQ($1be, $c2)} ***** BB40, STMT00051(after) N005 ( 7, 8) [000291] ------------ * JTRUE void N004 ( 5, 6) [000290] N------N-U-- \--* EQ int $600 N002 ( 3, 4) [001002] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000288] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) $140 N003 ( 1, 1) [000289] ------------ \--* CNS_INT int 2 $c2 finish(BB40). Succ(BB41). Not yet completed. All preds complete, adding to allDone. Succ(BB64). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#27) at start of BB64 is $846 {846} The SSA definition for GcHeap (#27) at start of BB64 is $846 {846} ***** BB64, STMT00053(before) N004 ( 7, 5) [000299] -A-X----R--- * ASG long N003 ( 3, 2) [000298] D------N---- +--* LCL_VAR long V21 tmp7 d:1 N002 ( 3, 2) [000297] #--X-------- \--* IND long N001 ( 1, 1) [000296] !----------- \--* LCL_VAR ref V00 this u:1 N001 [000296] LCL_VAR V00 this u:1 => $100 {InitVal($c0)} VNForMapSelect($2, $100):ref returns $2e7 {$VN.ReadOnlyHeap[$100]} VNForMapSelect($2, $100):ref returns $2e7 {$VN.ReadOnlyHeap[$100]} N002 [000297] IND => $2e8 {norm=$2e7 {$VN.ReadOnlyHeap[$100]}, exc=$2c2 {NullPtrExc($100)}} N003 [000298] LCL_VAR V21 tmp7 d:1 => $2e7 {$VN.ReadOnlyHeap[$100]} N004 [000299] ASG => $2e8 {norm=$2e7 {$VN.ReadOnlyHeap[$100]}, exc=$2c2 {NullPtrExc($100)}} ***** BB64, STMT00053(after) N004 ( 7, 5) [000299] -A-X----R--- * ASG long $2e8 N003 ( 3, 2) [000298] D------N---- +--* LCL_VAR long V21 tmp7 d:1 $2e7 N002 ( 3, 2) [000297] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000296] !----------- \--* LCL_VAR ref V00 this u:1 $100 --------- ***** BB64, STMT00161(before) N011 ( 16, 14) [001168] ------------ * JTRUE void N010 ( 14, 12) [000315] J------N---- \--* EQ int N008 ( 12, 10) [000311] n----------- +--* IND long N007 ( 10, 8) [000307] -------N---- | \--* ADD long N005 ( 9, 7) [000305] #----------- | +--* IND long N004 ( 6, 5) [000304] #----------- | | \--* IND long N003 ( 4, 3) [000303] -------N---- | | \--* ADD long N001 ( 3, 2) [000301] ------------ | | +--* LCL_VAR long V21 tmp7 u:1 N002 ( 1, 1) [000302] ------------ | | \--* CNS_INT long 56 N006 ( 1, 1) [000306] ------------ | \--* CNS_INT long 56 N009 ( 1, 1) [000314] ------------ \--* CNS_INT long 0 N001 [000301] LCL_VAR V21 tmp7 u:1 => $2e7 {$VN.ReadOnlyHeap[$100]} N002 [000302] CNS_INT 56 => $244 {LngCns: 56} N003 [000303] ADD => $306 {ADD($244, $2e7)} VNForMapSelect($2, $306):ref returns $2e9 {$VN.ReadOnlyHeap[$306]} VNForMapSelect($2, $306):ref returns $2e9 {$VN.ReadOnlyHeap[$306]} N004 [000304] IND => $2e9 {$VN.ReadOnlyHeap[$306]} VNForMapSelect($2, $2e9):ref returns $2ea {$VN.ReadOnlyHeap[$2e9]} VNForMapSelect($2, $2e9):ref returns $2ea {$VN.ReadOnlyHeap[$2e9]} N005 [000305] IND => $2ea {$VN.ReadOnlyHeap[$2e9]} N006 [000306] CNS_INT 56 => $244 {LngCns: 56} N007 [000307] ADD => $331 {ADD($244, $2ea)} N008 [000311] IND => N009 [000314] CNS_INT 0 => $243 {LngCns: 0} N010 [000315] EQ => ***** BB64, STMT00161(after) N011 ( 16, 14) [001168] ------------ * JTRUE void N010 ( 14, 12) [000315] J------N---- \--* EQ int N008 ( 12, 10) [000311] n----------- +--* IND long N007 ( 10, 8) [000307] -------N---- | \--* ADD long $331 N005 ( 9, 7) [000305] #----------- | +--* IND long $2ea N004 ( 6, 5) [000304] #----------- | | \--* IND long $2e9 N003 ( 4, 3) [000303] -------N---- | | \--* ADD long $306 N001 ( 3, 2) [000301] ------------ | | +--* LCL_VAR long V21 tmp7 u:1 $2e7 N002 ( 1, 1) [000302] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000306] ------------ | \--* CNS_INT long 56 $244 N009 ( 1, 1) [000314] ------------ \--* CNS_INT long 0 $243 finish(BB64). Succ(BB65). Not yet completed. All preds complete, adding to allDone. Succ(BB66). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#27) at start of BB66 is $846 {846} The SSA definition for GcHeap (#27) at start of BB66 is $846 {846} ***** BB66, STMT00163(before) N007 ( 23, 22) [001172] -AC-G---R--- * ASG long N006 ( 3, 2) [001171] D------N---- +--* LCL_VAR long V23 tmp9 d:2 N005 ( 19, 19) [000313] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS N003 ( 3, 2) [000300] ------?----- arg0 in rcx +--* LCL_VAR long V21 tmp7 u:1 (last use) N004 ( 2, 10) [000312] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr N001 [001003] ARGPLACE => $3a8 {3a8} N002 [001004] ARGPLACE => $3a9 {3a9} N003 [000300] LCL_VAR V21 tmp7 u:1 (last use) => $2e7 {$VN.ReadOnlyHeap[$100]} N004 [000312] CNS_INT(h) 0xd1ffab1e global ptr => $52 {Hnd const: 0x00000000D1FFAB1E} VN of ARGPLACE tree [001003] updated to $2e7 {$VN.ReadOnlyHeap[$100]} VN of ARGPLACE tree [001004] updated to $52 {Hnd const: 0x00000000D1FFAB1E} N005 [000313] CALL help => $332 {RuntimeHandleClass($2e7, $52)} N006 [001171] LCL_VAR V23 tmp9 d:2 => $332 {RuntimeHandleClass($2e7, $52)} N007 [001172] ASG => $332 {RuntimeHandleClass($2e7, $52)} ***** BB66, STMT00163(after) N007 ( 23, 22) [001172] -AC-G---R--- * ASG long $332 N006 ( 3, 2) [001171] D------N---- +--* LCL_VAR long V23 tmp9 d:2 $332 N005 ( 19, 19) [000313] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 N003 ( 3, 2) [000300] ------?----- arg0 in rcx +--* LCL_VAR long V21 tmp7 u:1 (last use) $2e7 N004 ( 2, 10) [000312] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $52 finish(BB66). Succ(BB67). Not yet completed. Not all preds complete Adding to notallDone, if necessary... Was necessary. The SSA definition for ByrefExposed (#27) at start of BB65 is $846 {846} The SSA definition for GcHeap (#27) at start of BB65 is $846 {846} ***** BB65, STMT00162(before) N010 ( 16, 13) [001170] -A------R--- * ASG long N009 ( 3, 2) [001169] D------N---- +--* LCL_VAR long V23 tmp9 d:3 N008 ( 12, 10) [000316] n-----?----- \--* IND long N007 ( 10, 8) [000317] ------?N---- \--* ADD long N005 ( 9, 7) [000318] #-----?----- +--* IND long N004 ( 6, 5) [000319] #-----?----- | \--* IND long N003 ( 4, 3) [000320] ------?N---- | \--* ADD long N001 ( 3, 2) [000321] ------?----- | +--* LCL_VAR long V21 tmp7 u:1 (last use) N002 ( 1, 1) [000322] ------?----- | \--* CNS_INT long 56 N006 ( 1, 1) [000323] ------?----- \--* CNS_INT long 56 N001 [000321] LCL_VAR V21 tmp7 u:1 (last use) => $2e7 {$VN.ReadOnlyHeap[$100]} N002 [000322] CNS_INT 56 => $244 {LngCns: 56} N003 [000320] ADD => $306 {ADD($244, $2e7)} VNForMapSelect($2, $306):ref returns $2e9 {$VN.ReadOnlyHeap[$306]} VNForMapSelect($2, $306):ref returns $2e9 {$VN.ReadOnlyHeap[$306]} N004 [000319] IND => $2e9 {$VN.ReadOnlyHeap[$306]} VNForMapSelect($2, $2e9):ref returns $2ea {$VN.ReadOnlyHeap[$2e9]} VNForMapSelect($2, $2e9):ref returns $2ea {$VN.ReadOnlyHeap[$2e9]} N005 [000318] IND => $2ea {$VN.ReadOnlyHeap[$2e9]} N006 [000323] CNS_INT 56 => $244 {LngCns: 56} N007 [000317] ADD => $331 {ADD($244, $2ea)} N008 [000316] IND => N009 [001169] LCL_VAR V23 tmp9 d:3 => N010 [001170] ASG => ***** BB65, STMT00162(after) N010 ( 16, 13) [001170] -A------R--- * ASG long N009 ( 3, 2) [001169] D------N---- +--* LCL_VAR long V23 tmp9 d:3 N008 ( 12, 10) [000316] n-----?----- \--* IND long N007 ( 10, 8) [000317] ------?N---- \--* ADD long $331 N005 ( 9, 7) [000318] #-----?----- +--* IND long $2ea N004 ( 6, 5) [000319] #-----?----- | \--* IND long $2e9 N003 ( 4, 3) [000320] ------?N---- | \--* ADD long $306 N001 ( 3, 2) [000321] ------?----- | +--* LCL_VAR long V21 tmp7 u:1 (last use) $2e7 N002 ( 1, 1) [000322] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000323] ------?----- \--* CNS_INT long 56 $244 finish(BB65). Succ(BB67). Not yet completed. All preds complete, adding to allDone. SSA PHI definition: set VN of local 23/1 to $34b {PhiDef($17, $1, $309)} . The SSA definition for ByrefExposed (#27) at start of BB67 is $846 {846} The SSA definition for GcHeap (#27) at start of BB67 is $846 {846} ***** BB67, STMT00056(before) N005 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException N003 ( 3, 2) [000328] ------------ arg0 in rcx +--* LCL_VAR long V23 tmp9 u:1 (last use) N004 ( 1, 1) [000310] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) N001 [001005] ARGPLACE => $3ad {3ad} N002 [001006] ARGPLACE => $848 {848} N003 [000328] LCL_VAR V23 tmp9 u:1 (last use) => $34b {PhiDef($17, $1, $309)} N004 [000310] LCL_VAR V01 arg1 u:1 (last use) => $101 {InitVal($c1)} VN of ARGPLACE tree [001005] updated to $34b {PhiDef($17, $1, $309)} VN of ARGPLACE tree [001006] updated to $101 {InitVal($c1)} fgCurMemoryVN[GcHeap] assigned for CALL at [000295] to VN: $849. N005 [000295] CALL => $VN.Void ***** BB67, STMT00056(after) N005 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void N003 ( 3, 2) [000328] ------------ arg0 in rcx +--* LCL_VAR long V23 tmp9 u:1 (last use) $34b N004 ( 1, 1) [000310] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) $101 finish(BB67). The SSA definition for ByrefExposed (#27) at start of BB41 is $846 {846} The SSA definition for GcHeap (#27) at start of BB41 is $846 {846} finish(BB41). Succ(BB31). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#8) at start of BB31 is $2fa {PhiMemoryDef($4d, $2f9)} The SSA definition for GcHeap (#8) at start of BB31 is $2fa {PhiMemoryDef($4d, $2f9)} ***** BB31, STMT00148(before) N002 ( 2, 2) [000811] ------------ * RETURN int N001 ( 1, 1) [000437] ------------ \--* CNS_INT int 0 N001 [000437] CNS_INT 0 => $c0 {IntCns 0} N002 [000811] RETURN => $1f3 {1f3} ***** BB31, STMT00148(after) N002 ( 2, 2) [000811] ------------ * RETURN int $1f3 N001 ( 1, 1) [000437] ------------ \--* CNS_INT int 0 $c0 finish(BB31). The SSA definition for ByrefExposed (#27) at start of BB39 is $846 {846} The SSA definition for GcHeap (#27) at start of BB39 is $846 {846} ***** BB39, STMT00057(before) N022 ( 34, 37) [000336] -A-XG------- * ASG ref N020 ( 32, 35) [000335] *--XG--N---- +--* IND ref N019 ( 30, 33) [000987] ---XG--N---- | \--* ADD byref N017 ( 29, 32) [000998] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000991] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000331] ------------ | | | +--* LCL_VAR int V09 loc5 u:2 N003 ( 3, 3) [000990] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000330] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [001001] ----G------- | | \--* ADDR byref N015 ( 11, 11) [000332] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000997] -------N---- | | \--* ADD byref N005 ( 1, 1) [000988] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 (last use) N013 ( 9, 9) [000996] -------N---- | | \--* ADD long N011 ( 8, 8) [000994] -------N---- | | +--* LSH long N009 ( 7, 7) [001000] ------------ | | | +--* MUL long N007 ( 2, 3) [000992] ------------ | | | | +--* CAST long <- int N006 ( 1, 1) [000989] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:2 (last use) N008 ( 1, 1) [000999] ------------ | | | | \--* CNS_INT long 3 N010 ( 1, 1) [000993] -------N---- | | | \--* CNS_INT long 3 N012 ( 1, 1) [000995] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] N018 ( 1, 1) [000986] ------------ | \--* CNS_INT long 8 field offset Fseq[value] N021 ( 1, 1) [000334] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) N001 [000331] LCL_VAR V09 loc5 u:2 => $3c4 {PhiDef($9, $2, $60b)} N002 [000330] LCL_VAR V04 loc0 u:1 => N003 [000990] ARR_LENGTH => N004 [000991] ARR_BOUNDS_CHECK_Rng => N005 [000988] LCL_VAR V04 loc0 u:1 (last use) => N006 [000989] LCL_VAR V09 loc5 u:2 (last use) => $3c4 {PhiDef($9, $2, $60b)} VNForCastOper(long) is $d6 N007 [000992] CAST => $6e1 {Cast($3c4, $d6)} N008 [000999] CNS_INT 3 => $24b {LngCns: 3} N009 [001000] MUL => $6e2 {MUL($24b, $6e1)} N010 [000993] CNS_INT 3 => $24b {LngCns: 3} N011 [000994] LSH => $6e3 {LSH($6e2, $24b)} N012 [000995] CNS_INT 16 Fseq[#FirstElem] => $241 {LngCns: 16} N013 [000996] ADD => $6e4 {ADD($241, $6e3)} N014 [000997] ADD => VNForHandle(arrElemType: Entry[__Canon,__Canon]) is $40 Relabeled IND_ARR_INDEX address node [000997] with l:$91: {PtrToArrElem($40, $2d3, $6e1, $0)} VNForMapSelect($846, $40):ref returns $7e7 {$846[$40]} VNForMapSelect($7e7, $2d3):ref returns $7ec {$7e7[$2d3]} VNForMapSelect($7ec, $6e1):struct returns $508 {$7ec[$6e1]} hAtArrType $7e7 is MapSelect(curGcHeap($846), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $7ec is MapSelect(hAtArrType($7e7), arr=$2d3). wholeElem $508 is MapSelect(hAtArrTypeAtArr($7ec), ind=$6e1). N015 [000332] IND => N016 [001001] ADDR => $91 {PtrToArrElem($40, $2d3, $6e1, $0)} N017 [000998] COMMA => N018 [000986] CNS_INT 8 field offset Fseq[value] => $240 {LngCns: 8} FieldSeq {value} is $468 N019 [000987] ADD => $2ae {norm=$95 {PtrToArrElem($40, $2d3, $6e1, $468)}, exc=$7de( {NullPtrExc($2d3)}, {IndexOutOfRangeExc($3c4, $403)})} N021 [000334] LCL_VAR V02 arg2 u:1 (last use) => $102 {InitVal($c2)} Tree [000336] assigns to an array element: VNForMapSelect($846, $40):ref returns $7e7 {$846[$40]} VNForMapSelect($7e7, $2d3):ref returns $7ec {$7e7[$2d3]} VNForMapSelect($7ec, $6e1):struct returns $508 {$7ec[$6e1]} VNApplySelectorsAssign: VNForHandle(value) is $53, fieldType is ref VNForMapStore($508, $53, $102):ref returns $691 {$508[$53 := $102]} VNForMapStore($7ec, $6e1, $691):ref returns $692 {$7ec[$6e1 := $691]} VNForMapStore($7e7, $2d3, $692):ref returns $693 {$7e7[$2d3 := $692]} hAtArrType $7e7 is MapSelect(curGcHeap($846), Entry[__Canon,__Canon][]). hAtArrTypeAtArr $7ec is MapSelect(hAtArrType($7e7), arr=$2d3) hAtArrTypeAtArrAtInx $508 is MapSelect(hAtArrTypeAtArr($7ec), inx=$6e1):struct newValAtInd $691 is {$508[$53 := $102]} newValAtArr $692 is {$7ec[$6e1 := $691]} newValAtArrType $693 is {$7e7[$2d3 := $692]} VNForMapStore($846, $40, $693):ref returns $694 {$846[$40 := $693]} fgCurMemoryVN[GcHeap] assigned for ArrIndexAssign (case 1) at [000336] to VN: $694. N022 [000336] ASG => $VN.Void ***** BB39, STMT00057(after) N022 ( 34, 37) [000336] -A-XG------- * ASG ref $VN.Void N020 ( 32, 35) [000335] *--XG--N---- +--* IND ref $102 N019 ( 30, 33) [000987] ---XG--N---- | \--* ADD byref $2ae N017 ( 29, 32) [000998] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000991] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000331] ------------ | | | +--* LCL_VAR int V09 loc5 u:2 $3c4 N003 ( 3, 3) [000990] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000330] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [001001] ----G------- | | \--* ADDR byref $91 N015 ( 11, 11) [000332] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000997] -------N---- | | \--* ADD byref $91 N005 ( 1, 1) [000988] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 (last use) N013 ( 9, 9) [000996] -------N---- | | \--* ADD long $6e4 N011 ( 8, 8) [000994] -------N---- | | +--* LSH long $6e3 N009 ( 7, 7) [001000] ------------ | | | +--* MUL long $6e2 N007 ( 2, 3) [000992] ------------ | | | | +--* CAST long <- int $6e1 N006 ( 1, 1) [000989] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:2 (last use) $3c4 N008 ( 1, 1) [000999] ------------ | | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000993] -------N---- | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000995] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000986] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N021 ( 1, 1) [000334] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 finish(BB39). Succ(BB58). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#8) at start of BB58 is $2fa {PhiMemoryDef($4d, $2f9)} The SSA definition for GcHeap (#8) at start of BB58 is $2fa {PhiMemoryDef($4d, $2f9)} ***** BB58, STMT00147(before) N002 ( 2, 2) [000810] ------------ * RETURN int N001 ( 1, 1) [000482] ------------ \--* CNS_INT int 1 N001 [000482] CNS_INT 1 => $c1 {IntCns 1} N002 [000810] RETURN => $1f4 {1f4} ***** BB58, STMT00147(after) N002 ( 2, 2) [000810] ------------ * RETURN int $1f4 N001 ( 1, 1) [000482] ------------ \--* CNS_INT int 1 $c1 finish(BB58). *************** Finishing PHASE Do value numbering *************** Starting PHASE Hoist loop code *************** In optHoistLoopCode() Blocks/Trees before phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal Loop1 gcsafe BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe BB36 [0108] 1 BB34 1 [???..???) i gcsafe BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen BB54 [0044] 2 BB48,BB53 0.50 [261..276) i BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} ***** BB01 STMT00000 (IL 0x000...0x006) N004 ( 5, 5) [000003] ------------ * JTRUE void N003 ( 3, 3) [000002] J------N---- \--* EQ int $180 N001 ( 1, 1) [000000] ------------ +--* LCL_VAR ref V01 arg1 u:1 $101 N002 ( 1, 1) [000001] ------------ \--* CNS_INT ref null $VN.Null ------------ BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00001 (IL 0x00E...0x014) N007 ( 8, 8) [000008] ---XG------- * JTRUE void N006 ( 6, 6) [000007] J--XG--N---- \--* NE int N004 ( 4, 4) [000005] ---XG------- +--* IND ref N003 ( 2, 2) [000814] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000004] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000813] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] $240 N005 ( 1, 1) [000006] ------------ \--* CNS_INT ref null $VN.Null ------------ BB03 [016..01E), preds={BB02} succs={BB04} ***** BB03 STMT00085 (IL ???... ???) N005 ( 16, 10) [000528] --CXG------- * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize $1c2 N003 ( 1, 1) [000526] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N004 ( 1, 1) [000527] ------------ arg1 in rdx \--* CNS_INT int 0 $c0 ------------ BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ***** BB04 STMT00088 (IL 0x01E... ???) N008 ( 9, 6) [000544] -A-XG---R--- * ASG bool N007 ( 1, 1) [000543] D------N---- +--* LCL_VAR int V33 tmp19 d:1 N006 ( 9, 6) [000012] N--XG------- \--* NE int N004 ( 4, 4) [000010] ---XG------- +--* IND ref N003 ( 2, 2) [000818] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000009] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000817] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] $240 N005 ( 1, 1) [000011] ------------ \--* CNS_INT ref null $VN.Null ***** BB04 STMT00091 (IL 0x01E... ???) N004 ( 4, 12) [000554] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000553] D------N---- +--* LCL_VAR ref V34 tmp20 d:1 $105 N002 ( 4, 12) [000538] #---G------- \--* IND ref $105 N001 ( 2, 10) [000537] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB04 STMT00092 (IL 0x01E... ???) N004 ( 4, 12) [000556] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000555] D------N---- +--* LCL_VAR ref V35 tmp21 d:1 $105 N002 ( 4, 12) [000540] #---G------- \--* IND ref $105 N001 ( 2, 10) [000539] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB04 STMT00089 (IL 0x01E... ???) N004 ( 5, 5) [000549] ------------ * JTRUE void N003 ( 3, 3) [000548] J------N---- \--* NE int N001 ( 1, 1) [000546] ------------ +--* LCL_VAR int V33 tmp19 u:1 (last use) N002 ( 1, 1) [000547] ------------ \--* CNS_INT int 0 $c0 ------------ BB05 [01E..01F), preds={BB04} succs={BB06} ***** BB05 STMT00090 (IL 0x01E... ???) N005 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 1, 1) [000550] ------------ arg0 in rcx +--* LCL_VAR ref V34 tmp20 u:1 (last use) $105 N004 ( 1, 1) [000551] ------------ arg1 in rdx \--* LCL_VAR ref V35 tmp21 u:1 (last use) $105 ------------ BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} ***** BB06 STMT00003 (IL 0x02C... ???) N006 ( 4, 4) [000018] -A-XG---R--- * ASG ref N005 ( 1, 1) [000017] D------N---- +--* LCL_VAR ref V04 loc0 d:1 N004 ( 4, 4) [000016] ---XG------- \--* IND ref N003 ( 2, 2) [000822] -------N---- \--* ADD byref $281 N001 ( 1, 1) [000015] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000821] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] $241 ***** BB06 STMT00094 (IL 0x033... ???) N005 ( 6, 3) [000566] -A------R--- * ASG bool N004 ( 1, 1) [000565] D------N---- +--* LCL_VAR int V36 tmp22 d:1 N003 ( 6, 3) [000021] N----------- \--* NE int N001 ( 1, 1) [000019] ------------ +--* LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000020] ------------ \--* CNS_INT ref null $VN.Null ***** BB06 STMT00097 (IL 0x033... ???) N004 ( 4, 12) [000576] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000575] D------N---- +--* LCL_VAR ref V37 tmp23 d:1 $105 N002 ( 4, 12) [000562] #---G------- \--* IND ref $105 N001 ( 2, 10) [000561] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB06 STMT00095 (IL 0x033... ???) N004 ( 5, 5) [000571] ------------ * JTRUE void N003 ( 3, 3) [000570] J------N---- \--* NE int N001 ( 1, 1) [000568] ------------ +--* LCL_VAR int V36 tmp22 u:1 (last use) N002 ( 1, 1) [000569] ------------ \--* CNS_INT int 0 $c0 ------------ BB07 [033..034), preds={BB06} succs={BB08} ***** BB07 STMT00096 (IL 0x033... ???) N006 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N004 ( 4, 12) [000824] #---G------- arg0 in rcx +--* IND ref $106 N003 ( 2, 10) [000823] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" $46 N005 ( 1, 1) [000573] ------------ arg1 in rdx \--* LCL_VAR ref V37 tmp23 u:1 (last use) $105 ------------ BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} ***** BB08 STMT00005 (IL 0x041... ???) N006 ( 4, 4) [000028] -A-XG---R--- * ASG ref N005 ( 1, 1) [000027] D------N---- +--* LCL_VAR ref V05 loc1 d:1 N004 ( 4, 4) [000026] ---XG------- \--* IND ref N003 ( 2, 2) [000828] -------N---- \--* ADD byref $282 N001 ( 1, 1) [000025] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000827] ------------ \--* CNS_INT long 24 field offset Fseq[_comparer] $242 ***** BB08 STMT00006 (IL 0x048...0x049) N004 ( 5, 5) [000032] ------------ * JTRUE void N003 ( 3, 3) [000031] J------N---- \--* EQ int N001 ( 1, 1) [000029] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000030] ------------ \--* CNS_INT ref null $VN.Null ------------ BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} ***** BB09 STMT00079 (IL 0x04B...0x052) N004 ( 3, 3) [000489] -A-X----R--- * ASG long $2e8 N003 ( 1, 1) [000488] D------N---- +--* LCL_VAR long V29 tmp15 d:1 $2e7 N002 ( 3, 2) [000487] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000486] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB09 STMT00149 (IL ???... ???) N011 ( 14, 13) [001148] ------------ * JTRUE void N010 ( 12, 11) [000505] J------N---- \--* EQ int N008 ( 10, 9) [000501] n----------- +--* IND long N007 ( 8, 7) [000497] -------N---- | \--* ADD long $307 N005 ( 7, 6) [000495] #----------- | +--* IND long $2ea N004 ( 4, 4) [000494] #----------- | | \--* IND long $2e9 N003 ( 2, 2) [000493] -------N---- | | \--* ADD long $306 N001 ( 1, 1) [000491] ------------ | | +--* LCL_VAR long V29 tmp15 u:1 $2e7 N002 ( 1, 1) [000492] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000496] ------------ | \--* CNS_INT long 64 $245 N009 ( 1, 1) [000504] ------------ \--* CNS_INT long 0 $243 ------------ BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} ***** BB10 STMT00150 (IL ???... ???) N010 ( 10, 9) [001150] -A------R--- * ASG long N009 ( 1, 1) [001149] D------N---- +--* LCL_VAR long V31 tmp17 d:3 N008 ( 10, 9) [000506] n-----?----- \--* IND long N007 ( 8, 7) [000507] ------?N---- \--* ADD long $307 N005 ( 7, 6) [000508] #-----?----- +--* IND long $2ea N004 ( 4, 4) [000509] #-----?----- | \--* IND long $2e9 N003 ( 2, 2) [000510] ------?N---- | \--* ADD long $306 N001 ( 1, 1) [000511] ------?----- | +--* LCL_VAR long V29 tmp15 u:1 (last use) $2e7 N002 ( 1, 1) [000512] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000513] ------?----- \--* CNS_INT long 64 $245 ------------ BB11 [???..???), preds={BB09} succs={BB12} ***** BB11 STMT00151 (IL ???... ???) N007 ( 17, 18) [001152] -AC-G---R--- * ASG long $308 N006 ( 1, 1) [001151] D------N---- +--* LCL_VAR long V31 tmp17 d:2 $308 N005 ( 17, 18) [000503] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $308 N003 ( 1, 1) [000490] ------?----- arg0 in rcx +--* LCL_VAR long V29 tmp15 u:1 (last use) $2e7 N004 ( 2, 10) [000502] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $49 ------------ BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} ***** BB12 STMT00178 (IL ???... ???) N005 ( 0, 0) [001217] -A------R--- * ASG long N004 ( 0, 0) [001215] D------N---- +--* LCL_VAR long V31 tmp17 d:1 N003 ( 0, 0) [001216] ------------ \--* PHI long N001 ( 0, 0) [001247] ------------ pred BB10 +--* PHI_ARG long V31 tmp17 u:3 N002 ( 0, 0) [001246] ------------ pred BB11 \--* PHI_ARG long V31 tmp17 u:2 $308 ***** BB12 STMT00083 (IL ???... ???) N010 ( 31, 15) [000524] -ACXG---R--- * ASG int $1c7 N009 ( 3, 2) [000523] D------N---- +--* LCL_VAR int V15 tmp1 d:3 $1c7 N008 ( 27, 12) [000522] --CXG------- \--* CALL ind stub int $1c7 N007 ( 1, 1) [000521] ------------ calli tgt \--* LCL_VAR long V31 tmp17 u:1 (last use) $342 N004 ( 1, 1) [000484] ------------ this in rcx +--* LCL_VAR ref V05 loc1 u:1 N005 ( 1, 1) [000831] ------------ arg1 in r11 +--* LCL_VAR long V31 tmp17 u:1 r11 REG r11 $342 N006 ( 1, 1) [000500] ------------ arg2 in rdx \--* LCL_VAR ref V01 arg1 u:1 $101 ------------ BB13 [054..061), preds={BB08} succs={BB14} ***** BB13 STMT00007 (IL 0x054...0x05C) N013 ( 34, 21) [000038] -ACXG---R--- * ASG int $1c5 N012 ( 3, 2) [000037] D------N---- +--* LCL_VAR int V15 tmp1 d:2 $1c5 N011 ( 30, 18) [000035] --CXG------- \--* CALLV vt-ind int System.Object.GetHashCode $1c5 N010 ( 9, 8) [000843] n--X-------- control expr \--* IND long N009 ( 7, 6) [000842] ---X---N---- \--* ADD long $303 N007 ( 6, 5) [000840] #--X-------- +--* IND long $2e6 N006 ( 4, 3) [000839] ---X---N---- | \--* ADD long $301 N004 ( 3, 2) [000837] #--X-------- | +--* IND long $2e4 N003 ( 1, 1) [000836] ------------ | | \--* LCL_VAR ref V01 arg1 u:1 $101 N005 ( 1, 1) [000838] ------------ | \--* CNS_INT int 72 $c9 N008 ( 1, 1) [000841] ------------ \--* CNS_INT int 24 $ca N002 ( 1, 1) [000033] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 $101 ------------ BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ***** BB14 STMT00177 (IL ???... ???) N005 ( 0, 0) [001214] -A------R--- * ASG int N004 ( 0, 0) [001212] D------N---- +--* LCL_VAR int V15 tmp1 d:1 N003 ( 0, 0) [001213] ------------ \--* PHI int N001 ( 0, 0) [001245] ------------ pred BB12 +--* PHI_ARG int V15 tmp1 u:3 $1c7 N002 ( 0, 0) [001244] ------------ pred BB13 \--* PHI_ARG int V15 tmp1 u:2 $1c5 ***** BB14 STMT00008 (IL ???...0x061) N003 ( 3, 3) [000042] -A------R--- * ASG int $3c0 N002 ( 1, 1) [000041] D------N---- +--* LCL_VAR int V06 loc2 d:1 $3c0 N001 ( 3, 2) [000040] ------------ \--* LCL_VAR int V15 tmp1 u:1 (last use) $3c0 ***** BB14 STMT00009 (IL 0x062...0x063) N003 ( 1, 3) [000045] -A------R--- * ASG int $c0 N002 ( 1, 1) [000044] D------N---- +--* LCL_VAR int V07 loc3 d:1 $c0 N001 ( 1, 1) [000043] ------------ \--* CNS_INT int 0 $c0 ***** BB14 STMT00098 (IL 0x064... ???) N006 ( 4, 4) [000580] -A-XG---R--- * ASG ref N005 ( 1, 1) [000579] D------N---- +--* LCL_VAR ref V39 tmp25 d:1 N004 ( 4, 4) [000578] ---XG------- \--* IND ref N003 ( 2, 2) [000845] -------N---- \--* ADD byref $280 N001 ( 1, 1) [000046] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000844] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] $240 ***** BB14 STMT00105 (IL 0x064... ???) N004 ( 3, 3) [000629] -A-X----R--- * ASG int N003 ( 1, 1) [000628] D------N---- +--* LCL_VAR int V40 tmp26 d:1 N002 ( 3, 3) [000583] ---X-------- \--* ARR_LENGTH int N001 ( 1, 1) [000582] ------------ \--* LCL_VAR ref V39 tmp25 u:1 ***** BB14 STMT00106 (IL 0x064... ???) N006 ( 4, 4) [000631] -A-XG---R--- * ASG long N005 ( 1, 1) [000630] D------N---- +--* LCL_VAR long V41 tmp27 d:1 N004 ( 4, 4) [000585] ---XG------- \--* IND long N003 ( 2, 2) [000847] -------N---- \--* ADD byref $283 N001 ( 1, 1) [000584] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000846] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 ***** BB14 STMT00108 (IL 0x064... ???) N005 ( 6, 6) [000642] -A------R--- * ASG bool N004 ( 1, 1) [000641] D------N---- +--* LCL_VAR int V43 tmp29 d:1 N003 ( 6, 6) [000599] N--------U-- \--* LE int N001 ( 1, 1) [000597] ------------ +--* LCL_VAR int V40 tmp26 u:1 N002 ( 1, 4) [000598] ------------ \--* CNS_INT int 0x7FFFFFFF $ce ***** BB14 STMT00111 (IL 0x064... ???) N004 ( 4, 12) [000652] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000651] D------N---- +--* LCL_VAR ref V44 tmp30 d:1 $105 N002 ( 4, 12) [000636] #---G------- \--* IND ref $105 N001 ( 2, 10) [000635] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB14 STMT00112 (IL 0x064... ???) N004 ( 4, 12) [000654] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000653] D------N---- +--* LCL_VAR ref V45 tmp31 d:1 $105 N002 ( 4, 12) [000638] #---G------- \--* IND ref $105 N001 ( 2, 10) [000637] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB14 STMT00109 (IL 0x064... ???) N004 ( 5, 5) [000647] ------------ * JTRUE void N003 ( 3, 3) [000646] J------N---- \--* NE int N001 ( 1, 1) [000644] ------------ +--* LCL_VAR int V43 tmp29 u:1 (last use) N002 ( 1, 1) [000645] ------------ \--* CNS_INT int 0 $c0 ------------ BB15 [064..065), preds={BB14} succs={BB16} ***** BB15 STMT00110 (IL 0x064... ???) N005 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 1, 1) [000648] ------------ arg0 in rcx +--* LCL_VAR ref V44 tmp30 u:1 (last use) $105 N004 ( 1, 1) [000649] ------------ arg1 in rdx \--* LCL_VAR ref V45 tmp31 u:1 (last use) $105 ------------ BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} ***** BB16 STMT00103 (IL 0x064... ???) N016 ( 20, 21) [000619] -A------R--- * ASG int N015 ( 1, 1) [000618] D------N---- +--* LCL_VAR int V42 tmp28 d:1 N014 ( 20, 21) [000617] ------------ \--* CAST int <- uint <- long N013 ( 19, 19) [000616] ------------ \--* RSZ long N011 ( 17, 17) [000614] ------------ +--* MUL long N008 ( 11, 11) [000611] ------------ | +--* ADD long N006 ( 9, 9) [000608] ------------ | | +--* RSZ long N004 ( 7, 7) [000606] ------------ | | | +--* MUL long N001 ( 1, 1) [000604] ------------ | | | | +--* LCL_VAR long V41 tmp27 u:1 (last use) N003 ( 2, 3) [000605] ---------U-- | | | | \--* CAST long <- ulong <- uint $310 N002 ( 1, 1) [000047] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 $3c0 N005 ( 1, 1) [000607] ------------ | | | \--* CNS_INT int 32 $d2 N007 ( 1, 1) [000610] ------------ | | \--* CNS_INT long 1 $247 N010 ( 2, 3) [000613] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000612] ------------ | \--* LCL_VAR int V40 tmp26 u:1 N012 ( 1, 1) [000615] ------------ \--* CNS_INT int 32 $d2 ***** BB16 STMT00114 (IL 0x064... ???) N007 ( 27, 7) [000665] -A-X----R--- * ASG bool N006 ( 1, 1) [000664] D------N---- +--* LCL_VAR int V46 tmp32 d:1 N005 ( 27, 7) [000624] ---X-------- \--* EQ int N003 ( 22, 5) [000623] ---X-------- +--* UMOD int N001 ( 1, 1) [000621] ------------ | +--* LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000622] ------------ | \--* LCL_VAR int V40 tmp26 u:1 (last use) N004 ( 1, 1) [000620] ------------ \--* LCL_VAR int V42 tmp28 u:1 ***** BB16 STMT00117 (IL 0x064... ???) N004 ( 4, 12) [000675] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000674] D------N---- +--* LCL_VAR ref V47 tmp33 d:1 $105 N002 ( 4, 12) [000659] #---G------- \--* IND ref $105 N001 ( 2, 10) [000658] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB16 STMT00118 (IL 0x064... ???) N004 ( 4, 12) [000677] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000676] D------N---- +--* LCL_VAR ref V48 tmp34 d:1 $105 N002 ( 4, 12) [000661] #---G------- \--* IND ref $105 N001 ( 2, 10) [000660] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB16 STMT00115 (IL 0x064... ???) N004 ( 5, 5) [000670] ------------ * JTRUE void N003 ( 3, 3) [000669] J------N---- \--* NE int N001 ( 1, 1) [000667] ------------ +--* LCL_VAR int V46 tmp32 u:1 (last use) N002 ( 1, 1) [000668] ------------ \--* CNS_INT int 0 $c0 ------------ BB17 [064..065), preds={BB16} succs={BB18} ***** BB17 STMT00116 (IL 0x064... ???) N005 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 1, 1) [000671] ------------ arg0 in rcx +--* LCL_VAR ref V47 tmp33 u:1 (last use) $105 N004 ( 1, 1) [000672] ------------ arg1 in rdx \--* LCL_VAR ref V48 tmp34 u:1 (last use) $105 ------------ BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} ***** BB18 STMT00100 (IL 0x064... ???) N017 ( 19, 24) [000591] -A-XG---R--- * ASG byref N016 ( 1, 1) [000590] D------N---- +--* LCL_VAR byref V38 tmp24 d:1 $81 N015 ( 19, 24) [000862] ---XG------- \--* COMMA byref N004 ( 8, 11) [000855] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000627] ------------ | +--* LCL_VAR int V42 tmp28 u:1 N003 ( 3, 3) [000854] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000581] ------------ | \--* LCL_VAR ref V39 tmp25 u:1 N014 ( 11, 13) [000863] ----G------- \--* ADDR byref $81 N013 ( 6, 7) [000588] a---G--N---- \--* IND int N012 ( 5, 6) [000861] -------N---- \--* ADD byref $81 N005 ( 1, 1) [000852] ------------ +--* LCL_VAR ref V39 tmp25 u:1 (last use) N011 ( 4, 5) [000860] -------N---- \--* ADD long N009 ( 3, 4) [000858] -------N---- +--* LSH long N007 ( 2, 3) [000856] ------------ | +--* CAST long <- int N006 ( 1, 1) [000853] i----------- | | \--* LCL_VAR int V42 tmp28 u:1 (last use) N008 ( 1, 1) [000857] -------N---- | \--* CNS_INT long 2 $248 N010 ( 1, 1) [000859] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB18 STMT00011 (IL ???... ???) N003 ( 5, 4) [000051] -A------R--- * ASG byref $81 N002 ( 3, 2) [000050] D------N---- +--* LCL_VAR byref V08 loc4 d:1 $81 N001 ( 1, 1) [000592] ------------ \--* LCL_VAR byref V38 tmp24 u:1 $81 ***** BB18 STMT00012 (IL 0x06D...0x072) N006 ( 5, 4) [000057] -A-XG---R--- * ASG int N005 ( 1, 1) [000056] D------N---- +--* LCL_VAR int V09 loc5 d:1 N004 ( 5, 4) [000055] ---XG------- \--* ADD int N002 ( 3, 2) [000053] *--XG------- +--* IND int N001 ( 1, 1) [000052] ------------ | \--* LCL_VAR byref V38 tmp24 u:1 (last use) $81 N003 ( 1, 1) [000054] ------------ \--* CNS_INT int -1 $c4 ***** BB18 STMT00013 (IL 0x074...0x075) N004 ( 5, 5) [000061] ------------ * JTRUE void N003 ( 3, 3) [000060] J------N---- \--* NE int N001 ( 1, 1) [000058] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000059] ------------ \--* CNS_INT ref null $VN.Null ------------ BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} ***** BB19 STMT00059 (IL 0x0FF...0x104) N004 ( 3, 3) [000356] -A-X----R--- * ASG long $2e8 N003 ( 1, 1) [000355] D------N---- +--* LCL_VAR long V24 tmp10 d:1 $2e7 N002 ( 3, 2) [000354] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000353] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB19 STMT00152 (IL ???... ???) N011 ( 14, 13) [001153] ------------ * JTRUE void N010 ( 12, 11) [000369] J------N---- \--* EQ int N008 ( 10, 9) [000365] n----------- +--* IND long N007 ( 8, 7) [000364] -------N---- | \--* ADD long $324 N005 ( 7, 6) [000362] #----------- | +--* IND long $2ea N004 ( 4, 4) [000361] #----------- | | \--* IND long $2e9 N003 ( 2, 2) [000360] -------N---- | | \--* ADD long $306 N001 ( 1, 1) [000358] ------------ | | +--* LCL_VAR long V24 tmp10 u:1 $2e7 N002 ( 1, 1) [000359] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000363] ------------ | \--* CNS_INT long 32 $24a N009 ( 1, 1) [000368] ------------ \--* CNS_INT long 0 $243 ------------ BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} ***** BB20 STMT00153 (IL ???... ???) N010 ( 14, 12) [001155] -A------R--- * ASG long N009 ( 3, 2) [001154] D------N---- +--* LCL_VAR long V25 tmp11 d:3 N008 ( 10, 9) [000370] n-----?----- \--* IND long N007 ( 8, 7) [000371] ------?N---- \--* ADD long $324 N005 ( 7, 6) [000372] #-----?----- +--* IND long $2ea N004 ( 4, 4) [000373] #-----?----- | \--* IND long $2e9 N003 ( 2, 2) [000374] ------?N---- | \--* ADD long $306 N001 ( 1, 1) [000375] ------?----- | +--* LCL_VAR long V24 tmp10 u:1 (last use) $2e7 N002 ( 1, 1) [000376] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000377] ------?----- \--* CNS_INT long 32 $24a ------------ BB21 [???..???), preds={BB19} succs={BB22} ***** BB21 STMT00154 (IL ???... ???) N007 ( 21, 21) [001157] -AC-G---R--- * ASG long $325 N006 ( 3, 2) [001156] D------N---- +--* LCL_VAR long V25 tmp11 d:2 $325 N005 ( 17, 18) [000367] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $325 N003 ( 1, 1) [000357] ------?----- arg0 in rcx +--* LCL_VAR long V24 tmp10 u:1 (last use) $2e7 N004 ( 2, 10) [000366] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $4f ------------ BB22 [???..106), preds={BB20,BB21} succs={BB23} ***** BB22 STMT00172 (IL ???... ???) N005 ( 0, 0) [001199] -A------R--- * ASG long N004 ( 0, 0) [001197] D------N---- +--* LCL_VAR long V25 tmp11 d:1 N003 ( 0, 0) [001198] ------------ \--* PHI long N001 ( 0, 0) [001243] ------------ pred BB20 +--* PHI_ARG long V25 tmp11 u:3 N002 ( 0, 0) [001242] ------------ pred BB21 \--* PHI_ARG long V25 tmp11 u:2 $325 ***** BB22 STMT00062 (IL ???... ???) N005 ( 17, 8) [000386] -ACXG---R--- * ASG ref $223 N004 ( 1, 1) [000385] D------N---- +--* LCL_VAR ref V12 loc8 d:1 $223 N003 ( 17, 8) [000352] --CXG------- \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default $223 N002 ( 3, 2) [000382] ------------ arg0 in rcx \--* LCL_VAR long V25 tmp11 u:1 (last use) $344 ------------ BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} ***** BB23 STMT00165 (IL ???... ???) N005 ( 0, 0) [001178] -A------R--- * ASG int N004 ( 0, 0) [001176] D------N---- +--* LCL_VAR int V07 loc3 d:5 N003 ( 0, 0) [001177] ------------ \--* PHI int N001 ( 0, 0) [001238] ------------ pred BB27 +--* PHI_ARG int V07 loc3 u:6 N002 ( 0, 0) [001235] ------------ pred BB22 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB23 STMT00164 (IL ???... ???) N005 ( 0, 0) [001175] -A------R--- * ASG int N004 ( 0, 0) [001173] D------N---- +--* LCL_VAR int V09 loc5 d:4 N003 ( 0, 0) [001174] ------------ \--* PHI int N001 ( 0, 0) [001239] ------------ pred BB27 +--* PHI_ARG int V09 loc5 u:5 N002 ( 0, 0) [001236] ------------ pred BB22 \--* PHI_ARG int V09 loc5 u:1 ***** BB23 STMT00063 (IL 0x106...0x10B) N005 ( 7, 7) [000391] ---X-------- * JTRUE void N004 ( 5, 5) [000390] N--X---N-U-- \--* LE int N002 ( 3, 3) [000389] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000388] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000387] ------------ \--* LCL_VAR int V09 loc5 u:4 $3c2 ------------ BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} ***** BB24 STMT00064 (IL 0x110...0x11E) N023 ( 36, 39) [000399] ---XG------- * JTRUE void N022 ( 34, 37) [000398] N--XG--N-U-- \--* NE int N020 ( 32, 35) [000396] *--XG------- +--* IND int N019 ( 30, 33) [000868] ---XG--N---- | \--* ADD byref $28c N017 ( 29, 32) [000879] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000872] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000393] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N003 ( 3, 3) [000871] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000392] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000882] ----G------- | | \--* ADDR byref $82 N015 ( 11, 11) [000394] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000878] -------N---- | | \--* ADD byref $82 N005 ( 1, 1) [000869] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000877] -------N---- | | \--* ADD long $329 N011 ( 8, 8) [000875] -------N---- | | +--* LSH long $328 N009 ( 7, 7) [000881] ------------ | | | +--* MUL long $327 N007 ( 2, 3) [000873] ------------ | | | | +--* CAST long <- int $326 N006 ( 1, 1) [000870] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 $3c2 N008 ( 1, 1) [000880] ------------ | | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000874] -------N---- | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000876] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000867] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N021 ( 1, 1) [000397] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 ------------ BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} ***** BB25 STMT00069 (IL 0x120...0x135) N035 ( 67, 59) [000428] --CXG------- * JTRUE void N034 ( 65, 57) [000427] J-CXG--N---- \--* NE int $1bd N032 ( 63, 55) [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals $581 N031 ( 9, 8) [000908] n--X-------- control expr | \--* IND long N030 ( 7, 6) [000907] ---X---N---- | \--* ADD long $32e N028 ( 6, 5) [000905] #--X-------- | +--* IND long $465 N027 ( 4, 3) [000904] ---X---N---- | | \--* ADD long $32c N025 ( 3, 2) [000902] #--X-------- | | +--* IND long $463 N024 ( 1, 1) [000901] ------------ | | | \--* LCL_VAR ref V12 loc8 u:1 $223 N026 ( 1, 1) [000903] ------------ | | \--* CNS_INT int 72 $c9 N029 ( 1, 1) [000906] ------------ | \--* CNS_INT int 32 $d2 N021 ( 32, 34) [000893] ---XG------- arg1 in rdx | +--* COMMA ref N007 ( 8, 11) [000886] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N004 ( 1, 1) [000420] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N006 ( 3, 3) [000885] ---X-------- | | | \--* ARR_LENGTH int N005 ( 1, 1) [000419] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N020 ( 24, 23) [000897] *---G------- | | \--* IND ref N019 ( 21, 21) [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] $84 N018 ( 11, 11) [000421] a---G--N---- | | \--* IND struct N017 ( 10, 10) [000892] -------N---- | | \--* ADD byref $82 N008 ( 1, 1) [000883] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N016 ( 9, 9) [000891] -------N---- | | \--* ADD long $329 N014 ( 8, 8) [000889] -------N---- | | +--* LSH long $328 N012 ( 7, 7) [000895] ------------ | | | +--* MUL long $327 N010 ( 2, 3) [000887] ------------ | | | | +--* CAST long <- int $326 N009 ( 1, 1) [000884] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 $3c2 N011 ( 1, 1) [000894] ------------ | | | | \--* CNS_INT long 3 $24b N013 ( 1, 1) [000888] -------N---- | | | \--* CNS_INT long 3 $24b N015 ( 1, 1) [000890] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N022 ( 1, 1) [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 u:1 $223 N023 ( 1, 1) [000424] ------------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 u:1 $101 N033 ( 1, 1) [000426] ------------ \--* CNS_INT int 0 $c0 ------------ BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} ***** BB26 STMT00065 (IL 0x157...0x164) N022 ( 32, 35) [000406] -A-XG---R--- * ASG int N021 ( 1, 1) [000405] D------N---- +--* LCL_VAR int V09 loc5 d:5 N020 ( 32, 35) [000404] *--XG------- \--* IND int N019 ( 30, 33) [000932] ---XG--N---- \--* ADD byref $28e N017 ( 29, 32) [000943] ---XG------- +--* COMMA byref N004 ( 8, 11) [000936] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000401] ------------ | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N003 ( 3, 3) [000935] ---X-------- | | \--* ARR_LENGTH int N002 ( 1, 1) [000400] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000946] ----G------- | \--* ADDR byref $82 N015 ( 11, 11) [000402] a---G--N---- | \--* IND struct N014 ( 10, 10) [000942] -------N---- | \--* ADD byref $82 N005 ( 1, 1) [000933] ------------ | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000941] -------N---- | \--* ADD long $329 N011 ( 8, 8) [000939] -------N---- | +--* LSH long $328 N009 ( 7, 7) [000945] ------------ | | +--* MUL long $327 N007 ( 2, 3) [000937] ------------ | | | +--* CAST long <- int $326 N006 ( 1, 1) [000934] i----------- | | | | \--* LCL_VAR int V09 loc5 u:4 (last use) $3c2 N008 ( 1, 1) [000944] ------------ | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000938] -------N---- | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000940] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000931] ------------ \--* CNS_INT long 20 field offset Fseq[next] $24c ***** BB26 STMT00066 (IL 0x166...0x169) N005 ( 3, 3) [000411] -A------R--- * ASG int $605 N004 ( 1, 1) [000410] D------N---- +--* LCL_VAR int V07 loc3 d:6 $605 N003 ( 3, 3) [000409] ------------ \--* ADD int $605 N001 ( 1, 1) [000407] ------------ +--* LCL_VAR int V07 loc3 u:5 (last use) $3c1 N002 ( 1, 1) [000408] ------------ \--* CNS_INT int 1 $c1 ***** BB26 STMT00067 (IL 0x16A...0x16E) N005 ( 7, 7) [000416] ---X-------- * JTRUE void N004 ( 5, 5) [000415] N--X---N-U-- \--* LT int N002 ( 3, 3) [000414] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000413] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000412] ------------ \--* LCL_VAR int V07 loc3 u:6 $605 ------------ BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} ------------ BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} ***** BB28 STMT00070 (IL 0x137...0x139) N005 ( 7, 8) [000432] ------------ * JTRUE void N004 ( 5, 6) [000431] N------N-U-- \--* NE int $1bf N002 ( 3, 4) [000909] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000429] ------------ | \--* LCL_VAR int V03 arg3 u:1 $140 N003 ( 1, 1) [000430] ------------ \--* CNS_INT int 1 $c1 ------------ BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} ***** BB29 STMT00077 (IL 0x13B...0x144) N022 ( 34, 37) [000481] -A-XG------- * ASG ref $VN.Void N020 ( 32, 35) [000480] *--XG--N---- +--* IND ref $102 N019 ( 30, 33) [000911] ---XG--N---- | \--* ADD byref $28d N017 ( 29, 32) [000922] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000915] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000476] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N003 ( 3, 3) [000914] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000475] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000925] ----G------- | | \--* ADDR byref $82 N015 ( 11, 11) [000477] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000921] -------N---- | | \--* ADD byref $82 N005 ( 1, 1) [000912] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 (last use) N013 ( 9, 9) [000920] -------N---- | | \--* ADD long $329 N011 ( 8, 8) [000918] -------N---- | | +--* LSH long $328 N009 ( 7, 7) [000924] ------------ | | | +--* MUL long $327 N007 ( 2, 3) [000916] ------------ | | | | +--* CAST long <- int $326 N006 ( 1, 1) [000913] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 (last use) $3c2 N008 ( 1, 1) [000923] ------------ | | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000917] -------N---- | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000919] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000910] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N021 ( 1, 1) [000479] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 ------------ BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} ***** BB30 STMT00071 (IL 0x14B...0x14D) N005 ( 7, 8) [000436] ------------ * JTRUE void N004 ( 5, 6) [000435] N------N-U-- \--* EQ int $600 N002 ( 3, 4) [000926] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000433] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) $140 N003 ( 1, 1) [000434] ------------ \--* CNS_INT int 2 $c2 ------------ BB31 [???..???) (return), preds={BB30,BB41} succs={} ***** BB31 STMT00148 (IL ???... ???) N002 ( 2, 2) [000811] ------------ * RETURN int $1f3 N001 ( 1, 1) [000437] ------------ \--* CNS_INT int 0 $c0 ------------ BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} ***** BB32 STMT00175 (IL ???... ???) N005 ( 0, 0) [001208] -A------R--- * ASG int N004 ( 0, 0) [001206] D------N---- +--* LCL_VAR int V07 loc3 d:3 N003 ( 0, 0) [001207] ------------ \--* PHI int N001 ( 0, 0) [001229] ------------ pred BB43 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [001218] ------------ pred BB18 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB32 STMT00174 (IL ???... ???) N005 ( 0, 0) [001205] -A------R--- * ASG int N004 ( 0, 0) [001203] D------N---- +--* LCL_VAR int V09 loc5 d:2 N003 ( 0, 0) [001204] ------------ \--* PHI int N001 ( 0, 0) [001230] ------------ pred BB43 +--* PHI_ARG int V09 loc5 u:3 N002 ( 0, 0) [001219] ------------ pred BB18 \--* PHI_ARG int V09 loc5 u:1 ***** BB32 STMT00014 (IL 0x177...0x17C) N005 ( 7, 7) [000066] ---X-------- * JTRUE void N004 ( 5, 5) [000065] N--X---N-U-- \--* LE int N002 ( 3, 3) [000064] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000063] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000062] ------------ \--* LCL_VAR int V09 loc5 u:2 $3c4 ------------ BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} ***** BB33 STMT00039 (IL 0x17E...0x18C) N023 ( 36, 39) [000215] ---XG------- * JTRUE void N022 ( 34, 37) [000214] N--XG--N-U-- \--* NE int N020 ( 32, 35) [000212] *--XG------- +--* IND int N019 ( 30, 33) [000948] ---XG--N---- | \--* ADD byref $2ac N017 ( 29, 32) [000959] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000952] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000209] ------------ | | | +--* LCL_VAR int V09 loc5 u:2 $3c4 N003 ( 3, 3) [000951] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000208] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000962] ----G------- | | \--* ADDR byref $91 N015 ( 11, 11) [000210] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000958] -------N---- | | \--* ADD byref $91 N005 ( 1, 1) [000949] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000957] -------N---- | | \--* ADD long $6e4 N011 ( 8, 8) [000955] -------N---- | | +--* LSH long $6e3 N009 ( 7, 7) [000961] ------------ | | | +--* MUL long $6e2 N007 ( 2, 3) [000953] ------------ | | | | +--* CAST long <- int $6e1 N006 ( 1, 1) [000950] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:2 $3c4 N008 ( 1, 1) [000960] ------------ | | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000954] -------N---- | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000956] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000947] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N021 ( 1, 1) [000213] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 ------------ BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} ***** BB34 STMT00045 (IL 0x18E...0x1A2) N020 ( 32, 34) [000246] -A-XG---R--- * ASG ref N019 ( 1, 1) [000245] D------N---- +--* LCL_VAR ref V17 tmp3 d:1 N018 ( 32, 34) [000973] ---XG------- \--* COMMA ref N004 ( 8, 11) [000966] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000236] ------------ | +--* LCL_VAR int V09 loc5 u:2 $3c4 N003 ( 3, 3) [000965] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000235] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N017 ( 24, 23) [000977] *---G------- \--* IND ref N016 ( 21, 21) [000976] ----G------- \--* ADDR byref Zero Fseq[key] $93 N015 ( 11, 11) [000237] a---G--N---- \--* IND struct N014 ( 10, 10) [000972] -------N---- \--* ADD byref $91 N005 ( 1, 1) [000963] ------------ +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000971] -------N---- \--* ADD long $6e4 N011 ( 8, 8) [000969] -------N---- +--* LSH long $6e3 N009 ( 7, 7) [000975] ------------ | +--* MUL long $6e2 N007 ( 2, 3) [000967] ------------ | | +--* CAST long <- int $6e1 N006 ( 1, 1) [000964] i----------- | | | \--* LCL_VAR int V09 loc5 u:2 $3c4 N008 ( 1, 1) [000974] ------------ | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000968] -------N---- | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000970] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB34 STMT00044 (IL 0x18E... ???) N004 ( 3, 3) [000244] -A-X----R--- * ASG long $2e8 N003 ( 1, 1) [000243] D------N---- +--* LCL_VAR long V16 tmp2 d:1 $2e7 N002 ( 3, 2) [000242] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000241] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB34 STMT00158 (IL ???... ???) N011 ( 14, 13) [001163] ------------ * JTRUE void N010 ( 12, 11) [000263] J------N---- \--* EQ int N008 ( 10, 9) [000259] n----------- +--* IND long N007 ( 8, 7) [000255] -------N---- | \--* ADD long $6e6 N005 ( 7, 6) [000253] #----------- | +--* IND long $2ea N004 ( 4, 4) [000252] #----------- | | \--* IND long $2e9 N003 ( 2, 2) [000251] -------N---- | | \--* ADD long $306 N001 ( 1, 1) [000249] ------------ | | +--* LCL_VAR long V16 tmp2 u:1 $2e7 N002 ( 1, 1) [000250] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000254] ------------ | \--* CNS_INT long 48 $246 N009 ( 1, 1) [000262] ------------ \--* CNS_INT long 0 $243 ------------ BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} ***** BB35 STMT00159 (IL ???... ???) N010 ( 10, 9) [001165] -A------R--- * ASG long N009 ( 1, 1) [001164] D------N---- +--* LCL_VAR long V19 tmp5 d:3 N008 ( 10, 9) [000264] n-----?----- \--* IND long N007 ( 8, 7) [000265] ------?N---- \--* ADD long $6e6 N005 ( 7, 6) [000266] #-----?----- +--* IND long $2ea N004 ( 4, 4) [000267] #-----?----- | \--* IND long $2e9 N003 ( 2, 2) [000268] ------?N---- | \--* ADD long $306 N001 ( 1, 1) [000269] ------?----- | +--* LCL_VAR long V16 tmp2 u:1 (last use) $2e7 N002 ( 1, 1) [000270] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000271] ------?----- \--* CNS_INT long 48 $246 ------------ BB36 [???..???), preds={BB34} succs={BB37} ***** BB36 STMT00160 (IL ???... ???) N007 ( 17, 18) [001167] -AC-G---R--- * ASG long $6e7 N006 ( 1, 1) [001166] D------N---- +--* LCL_VAR long V19 tmp5 d:2 $6e7 N005 ( 17, 18) [000261] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $6e7 N003 ( 1, 1) [000248] ------?----- arg0 in rcx +--* LCL_VAR long V16 tmp2 u:1 (last use) $2e7 N004 ( 2, 10) [000260] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $63 ------------ BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} ***** BB37 STMT00176 (IL ???... ???) N005 ( 0, 0) [001211] -A------R--- * ASG long N004 ( 0, 0) [001209] D------N---- +--* LCL_VAR long V19 tmp5 d:1 N003 ( 0, 0) [001210] ------------ \--* PHI long N001 ( 0, 0) [001234] ------------ pred BB35 +--* PHI_ARG long V19 tmp5 u:3 N002 ( 0, 0) [001233] ------------ pred BB36 \--* PHI_ARG long V19 tmp5 u:2 $6e7 ***** BB37 STMT00049 (IL ???... ???) N013 ( 32, 18) [000283] --CXG------- * JTRUE void N012 ( 30, 16) [000282] J-CXG--N---- \--* EQ int $817 N010 ( 28, 14) [000280] --CXG------- +--* CALL ind stub int $1ef N009 ( 1, 1) [000279] ------------ calli tgt | \--* LCL_VAR long V19 tmp5 u:1 (last use) $349 N005 ( 1, 1) [000234] ------------ this in rcx | +--* LCL_VAR ref V05 loc1 u:1 N006 ( 1, 1) [000980] ------------ arg1 in r11 | +--* LCL_VAR long V19 tmp5 u:1 r11 REG r11 $349 N007 ( 1, 1) [000247] ------------ arg2 in rdx | +--* LCL_VAR ref V17 tmp3 u:1 (last use) N008 ( 1, 1) [000258] ------------ arg3 in r8 | \--* LCL_VAR ref V01 arg1 u:1 $101 N011 ( 1, 1) [000281] ------------ \--* CNS_INT int 0 $c0 ------------ BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} ***** BB38 STMT00050 (IL 0x1A4...0x1A6) N005 ( 7, 8) [000287] ------------ * JTRUE void N004 ( 5, 6) [000286] N------N-U-- \--* NE int $1bf N002 ( 3, 4) [000985] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000284] ------------ | \--* LCL_VAR int V03 arg3 u:1 $140 N003 ( 1, 1) [000285] ------------ \--* CNS_INT int 1 $c1 ------------ BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} ***** BB39 STMT00057 (IL 0x1A8...0x1B1) N022 ( 34, 37) [000336] -A-XG------- * ASG ref $VN.Void N020 ( 32, 35) [000335] *--XG--N---- +--* IND ref $102 N019 ( 30, 33) [000987] ---XG--N---- | \--* ADD byref $2ae N017 ( 29, 32) [000998] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000991] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000331] ------------ | | | +--* LCL_VAR int V09 loc5 u:2 $3c4 N003 ( 3, 3) [000990] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000330] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [001001] ----G------- | | \--* ADDR byref $91 N015 ( 11, 11) [000332] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000997] -------N---- | | \--* ADD byref $91 N005 ( 1, 1) [000988] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 (last use) N013 ( 9, 9) [000996] -------N---- | | \--* ADD long $6e4 N011 ( 8, 8) [000994] -------N---- | | +--* LSH long $6e3 N009 ( 7, 7) [001000] ------------ | | | +--* MUL long $6e2 N007 ( 2, 3) [000992] ------------ | | | | +--* CAST long <- int $6e1 N006 ( 1, 1) [000989] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:2 (last use) $3c4 N008 ( 1, 1) [000999] ------------ | | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000993] -------N---- | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000995] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000986] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N021 ( 1, 1) [000334] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 ------------ BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} ***** BB40 STMT00051 (IL 0x1B8...0x1BA) N005 ( 7, 8) [000291] ------------ * JTRUE void N004 ( 5, 6) [000290] N------N-U-- \--* EQ int $600 N002 ( 3, 4) [001002] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000288] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) $140 N003 ( 1, 1) [000289] ------------ \--* CNS_INT int 2 $c2 ------------ BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} ------------ BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} ***** BB42 STMT00040 (IL 0x1C4...0x1D1) N022 ( 32, 35) [000222] -A-XG---R--- * ASG int N021 ( 1, 1) [000221] D------N---- +--* LCL_VAR int V09 loc5 d:3 N020 ( 32, 35) [000220] *--XG------- \--* IND int N019 ( 30, 33) [001009] ---XG--N---- \--* ADD byref $2ad N017 ( 29, 32) [001020] ---XG------- +--* COMMA byref N004 ( 8, 11) [001013] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000217] ------------ | | +--* LCL_VAR int V09 loc5 u:2 $3c4 N003 ( 3, 3) [001012] ---X-------- | | \--* ARR_LENGTH int N002 ( 1, 1) [000216] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [001023] ----G------- | \--* ADDR byref $91 N015 ( 11, 11) [000218] a---G--N---- | \--* IND struct N014 ( 10, 10) [001019] -------N---- | \--* ADD byref $91 N005 ( 1, 1) [001010] ------------ | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [001018] -------N---- | \--* ADD long $6e4 N011 ( 8, 8) [001016] -------N---- | +--* LSH long $6e3 N009 ( 7, 7) [001022] ------------ | | +--* MUL long $6e2 N007 ( 2, 3) [001014] ------------ | | | +--* CAST long <- int $6e1 N006 ( 1, 1) [001011] i----------- | | | | \--* LCL_VAR int V09 loc5 u:2 (last use) $3c4 N008 ( 1, 1) [001021] ------------ | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [001015] -------N---- | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [001017] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [001008] ------------ \--* CNS_INT long 20 field offset Fseq[next] $24c ***** BB42 STMT00041 (IL 0x1D3...0x1D6) N005 ( 3, 3) [000227] -A------R--- * ASG int $81a N004 ( 1, 1) [000226] D------N---- +--* LCL_VAR int V07 loc3 d:4 $81a N003 ( 3, 3) [000225] ------------ \--* ADD int $81a N001 ( 1, 1) [000223] ------------ +--* LCL_VAR int V07 loc3 u:3 (last use) $3c3 N002 ( 1, 1) [000224] ------------ \--* CNS_INT int 1 $c1 ***** BB42 STMT00042 (IL 0x1D7...0x1DB) N005 ( 7, 7) [000232] ---X-------- * JTRUE void N004 ( 5, 5) [000231] N--X---N-U-- \--* LT int N002 ( 3, 3) [000230] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000229] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000228] ------------ \--* LCL_VAR int V07 loc3 u:4 $81a ------------ BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} ------------ BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} ***** BB44 STMT00166 (IL ???... ???) N005 ( 0, 0) [001181] -A------R--- * ASG int N004 ( 0, 0) [001179] D------N---- +--* LCL_VAR int V07 loc3 d:2 N003 ( 0, 0) [001180] ------------ \--* PHI int N001 ( 0, 0) [001237] ------------ pred BB23 +--* PHI_ARG int V07 loc3 u:5 $3c1 N002 ( 0, 0) [001228] ------------ pred BB32 \--* PHI_ARG int V07 loc3 u:3 $3c3 ***** BB44 STMT00015 (IL 0x1E4...0x1EB) N007 ( 8, 8) [000071] ---XG------- * JTRUE void N006 ( 6, 6) [000070] J--XG--N---- \--* LE int N004 ( 4, 4) [000068] ---XG------- +--* IND int N003 ( 2, 2) [001025] -------N---- | \--* ADD byref $28f N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001024] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N005 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 $c0 ------------ BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} ***** BB45 STMT00035 (IL 0x1ED...0x1F3) N006 ( 8, 7) [000174] -A-XG---R--- * ASG int N005 ( 3, 2) [000173] D------N---- +--* LCL_VAR int V10 loc6 d:3 N004 ( 4, 4) [000172] ---XG------- \--* IND int N003 ( 2, 2) [001027] -------N---- \--* ADD byref $295 N001 ( 1, 1) [000171] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001026] ------------ \--* CNS_INT long 60 field offset Fseq[_freeList] $24d ***** BB45 STMT00120 (IL 0x1F5... ???) N034 ( 48, 47) [000688] -A-XG---R--- * ASG bool N033 ( 3, 2) [000687] D------N---- +--* LCL_VAR int V49 tmp35 d:1 N032 ( 44, 44) [000184] -A-XG------- \--* GE int N030 ( 39, 42) [000182] -A-XG------- +--* ADD int N028 ( 37, 40) [001050] -A-XG------- | +--* NEG int N027 ( 36, 39) [000181] *A-XG------- | | \--* IND int N026 ( 34, 37) [001029] -A-XG--N---- | | \--* ADD byref $29c N024 ( 33, 36) [001044] -A-XG------- | | +--* COMMA byref N006 ( 4, 4) [001032] -A-XG---R--- | | | +--* ASG int N005 ( 1, 1) [001031] D------N---- | | | | +--* LCL_VAR int V62 tmp48 d:1 N004 ( 4, 4) [000178] ---XG------- | | | | \--* IND int N003 ( 2, 2) [001046] -------N---- | | | | \--* ADD byref $295 N001 ( 1, 1) [000177] ------------ | | | | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001045] ------------ | | | | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N023 ( 29, 32) [001043] ---XG------- | | | \--* COMMA byref N010 ( 8, 11) [001036] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [001033] ------------ | | | | +--* LCL_VAR int V62 tmp48 u:1 N009 ( 3, 3) [001035] ---X-------- | | | | \--* ARR_LENGTH int N008 ( 1, 1) [000176] ------------ | | | | \--* LCL_VAR ref V04 loc0 u:1 N022 ( 21, 21) [001049] ----G------- | | | \--* ADDR byref $88 N021 ( 11, 11) [000179] a---G--N---- | | | \--* IND struct N020 ( 10, 10) [001042] -------N---- | | | \--* ADD byref $88 N011 ( 1, 1) [001030] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N019 ( 9, 9) [001041] -------N---- | | | \--* ADD long N017 ( 8, 8) [001039] -------N---- | | | +--* LSH long N015 ( 7, 7) [001048] ------------ | | | | +--* MUL long N013 ( 2, 3) [001037] ------------ | | | | | +--* CAST long <- int N012 ( 1, 1) [001034] i----------- | | | | | | \--* LCL_VAR int V62 tmp48 u:1 (last use) N014 ( 1, 1) [001047] ------------ | | | | | \--* CNS_INT long 3 $24b N016 ( 1, 1) [001038] -------N---- | | | | \--* CNS_INT long 3 $24b N018 ( 1, 1) [001040] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N025 ( 1, 1) [001028] ------------ | | \--* CNS_INT long 20 field offset Fseq[next] $24c N029 ( 1, 1) [000175] ------------ | \--* CNS_INT int -3 $e1 N031 ( 1, 1) [000183] ------------ \--* CNS_INT int -1 $c4 ***** BB45 STMT00123 (IL 0x1F5... ???) N004 ( 8, 15) [000698] -A--G---R--- * ASG ref $105 N003 ( 3, 2) [000697] D------N---- +--* LCL_VAR ref V50 tmp36 d:1 $105 N002 ( 4, 12) [000684] #---G------- \--* IND ref $105 N001 ( 2, 10) [000683] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB45 STMT00121 (IL 0x1F5... ???) N004 ( 7, 6) [000693] ------------ * JTRUE void N003 ( 5, 4) [000692] J------N---- \--* NE int N001 ( 3, 2) [000690] ------------ +--* LCL_VAR int V49 tmp35 u:1 (last use) N002 ( 1, 1) [000691] ------------ \--* CNS_INT int 0 $c0 ------------ BB46 [1F5..1F6), preds={BB45} succs={BB47} ***** BB46 STMT00122 (IL 0x1F5... ???) N006 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N004 ( 4, 12) [001052] #---G------- arg0 in rcx +--* IND ref $114 N003 ( 2, 10) [001051] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" $5e N005 ( 3, 2) [000695] ------------ arg1 in rdx \--* LCL_VAR ref V50 tmp36 u:1 (last use) $105 ------------ BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} ***** BB47 STMT00037 (IL 0x219... ???) N035 ( 44, 47) [000200] -A-XG------- * ASG int $VN.Void N004 ( 4, 4) [000199] D--XG--N---- +--* IND int $732 N003 ( 2, 2) [001056] -------N---- | \--* ADD byref $295 N001 ( 1, 1) [000190] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001055] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N034 ( 39, 42) [000198] -A-XG------- \--* ADD int N032 ( 37, 40) [001079] -A-XG------- +--* NEG int N031 ( 36, 39) [000197] *A-XG------- | \--* IND int N030 ( 34, 37) [001058] -A-XG--N---- | \--* ADD byref $2a3 N028 ( 33, 36) [001073] -A-XG------- | +--* COMMA byref N010 ( 4, 4) [001061] -A-XG---R--- | | +--* ASG int N009 ( 1, 1) [001060] D------N---- | | | +--* LCL_VAR int V63 tmp49 d:1 N008 ( 4, 4) [000194] ---XG------- | | | \--* IND int N007 ( 2, 2) [001075] -------N---- | | | \--* ADD byref $295 N005 ( 1, 1) [000193] ------------ | | | +--* LCL_VAR ref V00 this u:1 $100 N006 ( 1, 1) [001074] ------------ | | | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N027 ( 29, 32) [001072] ---XG------- | | \--* COMMA byref N014 ( 8, 11) [001065] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N011 ( 1, 1) [001062] ------------ | | | +--* LCL_VAR int V63 tmp49 u:1 N013 ( 3, 3) [001064] ---X-------- | | | \--* ARR_LENGTH int N012 ( 1, 1) [000192] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N026 ( 21, 21) [001078] ----G------- | | \--* ADDR byref $8a N025 ( 11, 11) [000195] a---G--N---- | | \--* IND struct N024 ( 10, 10) [001071] -------N---- | | \--* ADD byref $8a N015 ( 1, 1) [001059] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N023 ( 9, 9) [001070] -------N---- | | \--* ADD long N021 ( 8, 8) [001068] -------N---- | | +--* LSH long N019 ( 7, 7) [001077] ------------ | | | +--* MUL long N017 ( 2, 3) [001066] ------------ | | | | +--* CAST long <- int N016 ( 1, 1) [001063] i----------- | | | | | \--* LCL_VAR int V63 tmp49 u:1 (last use) N018 ( 1, 1) [001076] ------------ | | | | \--* CNS_INT long 3 $24b N020 ( 1, 1) [001067] -------N---- | | | \--* CNS_INT long 3 $24b N022 ( 1, 1) [001069] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N029 ( 1, 1) [001057] ------------ | \--* CNS_INT long 20 field offset Fseq[next] $24c N033 ( 1, 1) [000191] ------------ \--* CNS_INT int -3 $e1 ***** BB47 STMT00038 (IL 0x233...0x23C) N011 ( 11, 11) [000207] -A-XG---R--- * ASG int $VN.Void N010 ( 4, 4) [000206] D--XG--N---- +--* IND int $73a N009 ( 2, 2) [001081] -------N---- | \--* ADD byref $28f N007 ( 1, 1) [000201] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001080] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N006 ( 6, 6) [000205] ---XG------- \--* ADD int N004 ( 4, 4) [000203] ---XG------- +--* IND int N003 ( 2, 2) [001083] -------N---- | \--* ADD byref $28f N001 ( 1, 1) [000202] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001082] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N005 ( 1, 1) [000204] ------------ \--* CNS_INT int -1 $c4 ------------ BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} ***** BB48 STMT00016 (IL 0x243...0x249) N006 ( 8, 7) [000075] -A-XG---R--- * ASG int N005 ( 3, 2) [000074] D------N---- +--* LCL_VAR int V13 loc9 d:1 N004 ( 4, 4) [000073] ---XG------- \--* IND int N003 ( 2, 2) [001085] -------N---- \--* ADD byref $290 N001 ( 1, 1) [000072] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001084] ------------ \--* CNS_INT long 56 field offset Fseq[_count] $244 ***** BB48 STMT00017 (IL 0x24B...0x250) N005 ( 9, 8) [000080] ---X-------- * JTRUE void N004 ( 7, 6) [000079] N--X---N-U-- \--* NE int N002 ( 3, 3) [000078] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000077] ------------ | \--* LCL_VAR ref V04 loc0 u:1 (last use) N003 ( 3, 2) [000076] ------------ \--* LCL_VAR int V13 loc9 u:1 ------------ BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00125 (IL 0x252... ???) N014 ( 44, 26) [000705] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void N009 ( 22, 13) [001090] -ACXG---R-L- arg1 SETUP +--* ASG int $1d7 N008 ( 3, 2) [001089] D------N---- | +--* LCL_VAR int V64 tmp50 d:1 $1d7 N007 ( 18, 10) [000702] --CXG------- | \--* CALL int System.Collections.HashHelpers.ExpandPrime $1d7 N006 ( 4, 4) [000701] ---XG------- arg0 in rcx | \--* IND int N005 ( 2, 2) [001087] -------N---- | \--* ADD byref $290 N003 ( 1, 1) [000700] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N004 ( 1, 1) [001086] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] $244 N011 ( 3, 2) [001091] ------------ arg1 in rdx +--* LCL_VAR int V64 tmp50 u:1 (last use) $1d7 N012 ( 1, 1) [000163] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N013 ( 1, 1) [000704] ------------ arg2 in r8 \--* CNS_INT int 0 $c0 ***** BB49 STMT00126 (IL 0x258... ???) N006 ( 8, 7) [000711] -A-XG---R--- * ASG ref N005 ( 3, 2) [000710] D------N---- +--* LCL_VAR ref V52 tmp38 d:1 N004 ( 4, 4) [000709] ---XG------- \--* IND ref N003 ( 2, 2) [001095] -------N---- \--* ADD byref $280 N001 ( 1, 1) [000165] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001094] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] $240 ***** BB49 STMT00133 (IL 0x258... ???) N004 ( 5, 4) [000760] -A-X----R--- * ASG int N003 ( 1, 1) [000759] D------N---- +--* LCL_VAR int V53 tmp39 d:1 N002 ( 5, 4) [000714] ---X-------- \--* ARR_LENGTH int N001 ( 3, 2) [000713] ------------ \--* LCL_VAR ref V52 tmp38 u:1 ***** BB49 STMT00134 (IL 0x258... ???) N006 ( 8, 7) [000762] -A-XG---R--- * ASG long N005 ( 3, 2) [000761] D------N---- +--* LCL_VAR long V54 tmp40 d:1 N004 ( 4, 4) [000716] ---XG------- \--* IND long N003 ( 2, 2) [001097] -------N---- \--* ADD byref $283 N001 ( 1, 1) [000715] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001096] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 ***** BB49 STMT00136 (IL 0x258... ???) N005 ( 10, 9) [000773] -A------R--- * ASG bool N004 ( 3, 2) [000772] D------N---- +--* LCL_VAR int V56 tmp42 d:1 N003 ( 6, 6) [000730] N--------U-- \--* LE int N001 ( 1, 1) [000728] ------------ +--* LCL_VAR int V53 tmp39 u:1 N002 ( 1, 4) [000729] ------------ \--* CNS_INT int 0x7FFFFFFF $ce ***** BB49 STMT00139 (IL 0x258... ???) N004 ( 8, 15) [000783] -A--G---R--- * ASG ref $105 N003 ( 3, 2) [000782] D------N---- +--* LCL_VAR ref V57 tmp43 d:1 $105 N002 ( 4, 12) [000767] #---G------- \--* IND ref $105 N001 ( 2, 10) [000766] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB49 STMT00140 (IL 0x258... ???) N004 ( 8, 15) [000785] -A--G---R--- * ASG ref $105 N003 ( 3, 2) [000784] D------N---- +--* LCL_VAR ref V58 tmp44 d:1 $105 N002 ( 4, 12) [000769] #---G------- \--* IND ref $105 N001 ( 2, 10) [000768] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB49 STMT00137 (IL 0x258... ???) N004 ( 7, 6) [000778] ------------ * JTRUE void N003 ( 5, 4) [000777] J------N---- \--* NE int N001 ( 3, 2) [000775] ------------ +--* LCL_VAR int V56 tmp42 u:1 (last use) N002 ( 1, 1) [000776] ------------ \--* CNS_INT int 0 $c0 ------------ BB50 [258..259), preds={BB49} succs={BB51} ***** BB50 STMT00138 (IL 0x258... ???) N005 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 3, 2) [000779] ------------ arg0 in rcx +--* LCL_VAR ref V57 tmp43 u:1 (last use) $105 N004 ( 3, 2) [000780] ------------ arg1 in rdx \--* LCL_VAR ref V58 tmp44 u:1 (last use) $105 ------------ BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00131 (IL 0x258... ???) N016 ( 26, 25) [000750] -A------R--- * ASG int N015 ( 3, 2) [000749] D------N---- +--* LCL_VAR int V55 tmp41 d:1 N014 ( 22, 22) [000748] ------------ \--* CAST int <- uint <- long N013 ( 21, 20) [000747] ------------ \--* RSZ long N011 ( 19, 18) [000745] ------------ +--* MUL long N008 ( 13, 12) [000742] ------------ | +--* ADD long N006 ( 11, 10) [000739] ------------ | | +--* RSZ long N004 ( 9, 8) [000737] ------------ | | | +--* MUL long N001 ( 3, 2) [000735] ------------ | | | | +--* LCL_VAR long V54 tmp40 u:1 (last use) N003 ( 2, 3) [000736] ---------U-- | | | | \--* CAST long <- ulong <- uint $310 N002 ( 1, 1) [000166] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 $3c0 N005 ( 1, 1) [000738] ------------ | | | \--* CNS_INT int 32 $d2 N007 ( 1, 1) [000741] ------------ | | \--* CNS_INT long 1 $247 N010 ( 2, 3) [000744] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000743] ------------ | \--* LCL_VAR int V53 tmp39 u:1 N012 ( 1, 1) [000746] ------------ \--* CNS_INT int 32 $d2 ***** BB51 STMT00142 (IL 0x258... ???) N007 ( 33, 11) [000796] -A-X----R--- * ASG bool N006 ( 3, 2) [000795] D------N---- +--* LCL_VAR int V59 tmp45 d:1 N005 ( 29, 8) [000755] ---X-------- \--* EQ int N003 ( 22, 5) [000754] ---X-------- +--* UMOD int N001 ( 1, 1) [000752] ------------ | +--* LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000753] ------------ | \--* LCL_VAR int V53 tmp39 u:1 (last use) N004 ( 3, 2) [000751] ------------ \--* LCL_VAR int V55 tmp41 u:1 ***** BB51 STMT00145 (IL 0x258... ???) N004 ( 8, 15) [000806] -A--G---R--- * ASG ref $105 N003 ( 3, 2) [000805] D------N---- +--* LCL_VAR ref V60 tmp46 d:1 $105 N002 ( 4, 12) [000790] #---G------- \--* IND ref $105 N001 ( 2, 10) [000789] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB51 STMT00146 (IL 0x258... ???) N004 ( 8, 15) [000808] -A--G---R--- * ASG ref $105 N003 ( 3, 2) [000807] D------N---- +--* LCL_VAR ref V61 tmp47 d:1 $105 N002 ( 4, 12) [000792] #---G------- \--* IND ref $105 N001 ( 2, 10) [000791] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB51 STMT00143 (IL 0x258... ???) N004 ( 7, 6) [000801] ------------ * JTRUE void N003 ( 5, 4) [000800] J------N---- \--* NE int N001 ( 3, 2) [000798] ------------ +--* LCL_VAR int V59 tmp45 u:1 (last use) N002 ( 1, 1) [000799] ------------ \--* CNS_INT int 0 $c0 ------------ BB52 [258..259), preds={BB51} succs={BB53} ***** BB52 STMT00144 (IL 0x258... ???) N005 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 3, 2) [000802] ------------ arg0 in rcx +--* LCL_VAR ref V60 tmp46 u:1 (last use) $105 N004 ( 3, 2) [000803] ------------ arg1 in rdx \--* LCL_VAR ref V61 tmp47 u:1 (last use) $105 ------------ BB53 [258..259), preds={BB51,BB52} succs={BB54} ***** BB53 STMT00128 (IL 0x258... ???) N017 ( 35, 33) [000722] -A-XG---R--- * ASG byref N016 ( 3, 2) [000721] D------N---- +--* LCL_VAR byref V51 tmp37 d:1 $87 N015 ( 31, 30) [001112] ---XG------- \--* COMMA byref N004 ( 12, 13) [001105] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 3, 2) [000758] ------------ | +--* LCL_VAR int V55 tmp41 u:1 N003 ( 5, 4) [001104] ---X-------- | \--* ARR_LENGTH int N002 ( 3, 2) [000712] ------------ | \--* LCL_VAR ref V52 tmp38 u:1 N014 ( 19, 17) [001113] ----G------- \--* ADDR byref $87 N013 ( 10, 9) [000719] a---G--N---- \--* IND int N012 ( 9, 8) [001111] -------N---- \--* ADD byref $87 N005 ( 3, 2) [001102] ------------ +--* LCL_VAR ref V52 tmp38 u:1 (last use) N011 ( 6, 6) [001110] -------N---- \--* ADD long N009 ( 5, 5) [001108] -------N---- +--* LSH long N007 ( 4, 4) [001106] ------------ | +--* CAST long <- int N006 ( 3, 2) [001103] i----------- | | \--* LCL_VAR int V55 tmp41 u:1 (last use) N008 ( 1, 1) [001107] -------N---- | \--* CNS_INT long 2 $248 N010 ( 1, 1) [001109] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB53 STMT00034 (IL ???... ???) N003 ( 7, 5) [000170] -A------R--- * ASG byref $87 N002 ( 3, 2) [000169] D------N---- +--* LCL_VAR byref V08 loc4 d:4 $87 N001 ( 3, 2) [000723] ------------ \--* LCL_VAR byref V51 tmp37 u:1 (last use) $87 ------------ BB54 [261..276), preds={BB48,BB53} succs={BB55} ***** BB54 STMT00170 (IL ???... ???) N005 ( 0, 0) [001193] -A------R--- * ASG byref N004 ( 0, 0) [001191] D------N---- +--* LCL_VAR byref V08 loc4 d:3 N003 ( 0, 0) [001192] ------------ \--* PHI byref N001 ( 0, 0) [001224] ------------ pred BB53 +--* PHI_ARG byref V08 loc4 u:4 $87 N002 ( 0, 0) [001220] ------------ pred BB48 \--* PHI_ARG byref V08 loc4 u:1 $81 ***** BB54 STMT00018 (IL 0x261...0x263) N003 ( 7, 5) [000083] -A------R--- * ASG int N002 ( 3, 2) [000082] D------N---- +--* LCL_VAR int V10 loc6 d:2 N001 ( 3, 2) [000081] ------------ \--* LCL_VAR int V13 loc9 u:1 ***** BB54 STMT00019 (IL 0x265...0x26A) N008 ( 10, 9) [000089] -A-XG---R--- * ASG int $VN.Void N007 ( 4, 4) [000088] D--XG--N---- +--* IND int $708 N006 ( 2, 2) [001115] -------N---- | \--* ADD byref $290 N004 ( 1, 1) [000084] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N005 ( 1, 1) [001114] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] $244 N003 ( 5, 4) [000087] ------------ \--* ADD int N001 ( 3, 2) [000085] ------------ +--* LCL_VAR int V13 loc9 u:1 (last use) N002 ( 1, 1) [000086] ------------ \--* CNS_INT int 1 $c1 ***** BB54 STMT00020 (IL 0x26F...0x275) N006 ( 4, 4) [000093] -A-XG---R--- * ASG ref N005 ( 1, 1) [000092] D------N---- +--* LCL_VAR ref V04 loc0 d:3 N004 ( 4, 4) [000091] ---XG------- \--* IND ref N003 ( 2, 2) [001117] -------N---- \--* ADD byref $281 N001 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001116] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] $241 ------------ BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} ***** BB55 STMT00171 (IL ???... ???) N005 ( 0, 0) [001196] -A------R--- * ASG byref N004 ( 0, 0) [001194] D------N---- +--* LCL_VAR byref V08 loc4 d:2 N003 ( 0, 0) [001195] ------------ \--* PHI byref N001 ( 0, 0) [001225] ------------ pred BB47 +--* PHI_ARG byref V08 loc4 u:1 $81 N002 ( 0, 0) [001221] ------------ pred BB54 \--* PHI_ARG byref V08 loc4 u:3 $780 ***** BB55 STMT00169 (IL ???... ???) N005 ( 0, 0) [001190] -A------R--- * ASG ref N004 ( 0, 0) [001188] D------N---- +--* LCL_VAR ref V04 loc0 d:2 N003 ( 0, 0) [001189] ------------ \--* PHI ref N001 ( 0, 0) [001226] ------------ pred BB47 +--* PHI_ARG ref V04 loc0 u:1 N002 ( 0, 0) [001222] ------------ pred BB54 \--* PHI_ARG ref V04 loc0 u:3 ***** BB55 STMT00168 (IL ???... ???) N005 ( 0, 0) [001187] -A------R--- * ASG int N004 ( 0, 0) [001185] D------N---- +--* LCL_VAR int V10 loc6 d:1 N003 ( 0, 0) [001186] ------------ \--* PHI int N001 ( 0, 0) [001227] ------------ pred BB47 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [001223] ------------ pred BB54 \--* PHI_ARG int V10 loc6 u:2 ***** BB55 STMT00021 (IL 0x276...0x27E) N019 ( 39, 38) [000099] -A-XG---R--- * ASG byref $2a6 N018 ( 3, 2) [000098] D------N---- +--* LCL_VAR byref V11 loc7 d:1 $8c N017 ( 35, 35) [001128] ---XG------- \--* COMMA byref $2a6 N004 ( 10, 12) [001121] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $7cd N001 ( 3, 2) [000095] ------------ | +--* LCL_VAR int V10 loc6 u:1 $3cc N003 ( 3, 3) [001120] ---X-------- | \--* ARR_LENGTH int $73d N002 ( 1, 1) [000094] ------------ | \--* LCL_VAR ref V04 loc0 u:2 $684 N016 ( 25, 23) [001131] ----G------- \--* ADDR byref $8c N015 ( 13, 12) [000096] a---G--N---- \--* IND struct N014 ( 12, 11) [001127] -------N---- \--* ADD byref $8c N005 ( 1, 1) [001118] ------------ +--* LCL_VAR ref V04 loc0 u:2 $684 N013 ( 11, 10) [001126] -------N---- \--* ADD long $6df N011 ( 10, 9) [001124] -------N---- +--* LSH long $6de N009 ( 9, 8) [001130] ------------ | +--* MUL long $6dd N007 ( 4, 4) [001122] ------------ | | +--* CAST long <- int $6dc N006 ( 3, 2) [001119] i----------- | | | \--* LCL_VAR int V10 loc6 u:1 $3cc N008 ( 1, 1) [001129] ------------ | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [001123] -------N---- | \--* CNS_INT long 3 $24b N012 ( 1, 1) [001125] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB55 STMT00022 (IL 0x280...0x283) N006 ( 8, 7) [000103] -A-XG------- * ASG int $VN.Void N004 ( 6, 5) [000102] *--XG--N---- +--* IND int $3c0 N003 ( 4, 3) [001133] -------N---- | \--* ADD byref $8d N001 ( 3, 2) [000100] ------------ | +--* LCL_VAR byref V11 loc7 u:1 $8c N002 ( 1, 1) [001132] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N005 ( 1, 1) [000101] ------------ \--* LCL_VAR int V06 loc2 u:1 (last use) $3c0 ***** BB55 STMT00023 (IL 0x288...0x28F) N009 ( 15, 12) [000110] -A-XG---R--- * ASG int $VN.Void N008 ( 6, 5) [000109] *--XG--N---- +--* IND int N007 ( 4, 3) [001135] -------N---- | \--* ADD byref $8e N005 ( 3, 2) [000104] ------------ | +--* LCL_VAR byref V11 loc7 u:1 $8c N006 ( 1, 1) [001134] ------------ | \--* CNS_INT long 20 field offset Fseq[next] $24c N004 ( 8, 6) [000108] ---XG------- \--* ADD int N002 ( 6, 4) [000106] *--XG------- +--* IND int N001 ( 3, 2) [000105] ------------ | \--* LCL_VAR byref V08 loc4 u:2 $781 N003 ( 1, 1) [000107] ------------ \--* CNS_INT int -1 $c4 ***** BB55 STMT00024 (IL 0x294...0x297) N004 ( 8, 6) [000114] -A-XG------- * ASG ref $VN.Void N002 ( 6, 4) [000113] *--XG--N---- +--* IND ref $101 N001 ( 3, 2) [000111] ------------ | \--* LCL_VAR byref V11 loc7 u:1 Zero Fseq[key] $8f N003 ( 1, 1) [000112] ------------ \--* LCL_VAR ref V01 arg1 u:1 (last use) $101 ***** BB55 STMT00025 (IL 0x29C...0x29F) N006 ( 8, 7) [000118] -A-XG------- * ASG ref $VN.Void N004 ( 6, 5) [000117] *--XG--N---- +--* IND ref $102 N003 ( 4, 3) [001137] -------N---- | \--* ADD byref $90 N001 ( 3, 2) [000115] ------------ | +--* LCL_VAR byref V11 loc7 u:1 (last use) $8c N002 ( 1, 1) [001136] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N005 ( 1, 1) [000116] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 ***** BB55 STMT00026 (IL 0x2A4...0x2AA) N006 ( 12, 9) [000124] -A-XG---R--- * ASG int $VN.Void N005 ( 6, 4) [000123] *--X---N---- +--* IND int $804 N004 ( 3, 2) [000119] ------------ | \--* LCL_VAR byref V08 loc4 u:2 (last use) $781 N003 ( 5, 4) [000122] ------------ \--* ADD int $804 N001 ( 3, 2) [000120] ------------ +--* LCL_VAR int V10 loc6 u:1 (last use) $3cc N002 ( 1, 1) [000121] ------------ \--* CNS_INT int 1 $c1 ***** BB55 STMT00027 (IL 0x2AB...0x2B4) N011 ( 11, 11) [000131] -A-XG---R--- * ASG int $VN.Void N010 ( 4, 4) [000130] D--XG--N---- +--* IND int $80a N009 ( 2, 2) [001139] -------N---- | \--* ADD byref $2a7 N007 ( 1, 1) [000125] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001138] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] $24e N006 ( 6, 6) [000129] ---XG------- \--* ADD int N004 ( 4, 4) [000127] ---XG------- +--* IND int N003 ( 2, 2) [001141] -------N---- | \--* ADD byref $2a7 N001 ( 1, 1) [000126] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001140] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] $24e N005 ( 1, 1) [000128] ------------ \--* CNS_INT int 1 $c1 ***** BB55 STMT00028 (IL 0x2CA...0x2CD) N004 ( 5, 5) [000148] ------------ * JTRUE void N003 ( 3, 3) [000147] N------N-U-- \--* LE int $80d N001 ( 1, 1) [000145] ------------ +--* LCL_VAR int V07 loc3 u:2 (last use) $3c5 N002 ( 1, 1) [000146] ------------ \--* CNS_INT int 100 $e3 ------------ BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} ***** BB56 STMT00030 (IL 0x2CF...0x2D5) N008 ( 21, 22) [000156] --C-G------- * JTRUE void N007 ( 19, 20) [000155] J-C-G--N---- \--* EQ int N005 ( 17, 18) [000153] --C-G------- +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS N003 ( 1, 1) [000151] ------------ arg1 in rdx | +--* LCL_VAR ref V05 loc1 u:1 (last use) N004 ( 2, 10) [000152] H------N---- arg0 in rcx | \--* CNS_INT(h) long 0xd1ffab1e class $62 N006 ( 1, 1) [000154] ------------ \--* CNS_INT ref null $VN.Null ------------ BB57 [2D7..2E3), preds={BB56} succs={BB58} ***** BB57 STMT00031 (IL 0x2D7...0x2DC) N008 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void N005 ( 3, 3) [000159] ---X-------- arg1 in rdx +--* ARR_LENGTH int $73d N004 ( 1, 1) [000158] ------------ | \--* LCL_VAR ref V04 loc0 u:2 (last use) $684 N006 ( 1, 1) [000157] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N007 ( 1, 1) [000160] ------------ arg2 in r8 \--* CNS_INT int 1 $c1 ------------ BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} ***** BB58 STMT00147 (IL ???... ???) N002 ( 2, 2) [000810] ------------ * RETURN int $1f4 N001 ( 1, 1) [000482] ------------ \--* CNS_INT int 1 $c1 ------------ BB59 [008..00E) (throw), preds={BB01} succs={} ***** BB59 STMT00086 (IL 0x008...0x009) N003 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException $VN.Void N002 ( 1, 1) [000532] ------------ arg0 in rcx \--* CNS_INT int 4 $c5 ------------ BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} ***** BB60 STMT00073 (IL 0x14F...0x150) N004 ( 7, 5) [000444] -A-X----R--- * ASG long $2e8 N003 ( 3, 2) [000443] D------N---- +--* LCL_VAR long V26 tmp12 d:1 $2e7 N002 ( 3, 2) [000442] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000441] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB60 STMT00155 (IL ???... ???) N011 ( 16, 14) [001158] ------------ * JTRUE void N010 ( 14, 12) [000460] J------N---- \--* EQ int N008 ( 12, 10) [000456] n----------- +--* IND long N007 ( 10, 8) [000452] -------N---- | \--* ADD long $331 N005 ( 9, 7) [000450] #----------- | +--* IND long $2ea N004 ( 6, 5) [000449] #----------- | | \--* IND long $2e9 N003 ( 4, 3) [000448] -------N---- | | \--* ADD long $306 N001 ( 3, 2) [000446] ------------ | | +--* LCL_VAR long V26 tmp12 u:1 $2e7 N002 ( 1, 1) [000447] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000451] ------------ | \--* CNS_INT long 56 $244 N009 ( 1, 1) [000459] ------------ \--* CNS_INT long 0 $243 ------------ BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} ***** BB61 STMT00156 (IL ???... ???) N010 ( 16, 13) [001160] -A------R--- * ASG long N009 ( 3, 2) [001159] D------N---- +--* LCL_VAR long V28 tmp14 d:3 N008 ( 12, 10) [000461] n-----?----- \--* IND long N007 ( 10, 8) [000462] ------?N---- \--* ADD long $331 N005 ( 9, 7) [000463] #-----?----- +--* IND long $2ea N004 ( 6, 5) [000464] #-----?----- | \--* IND long $2e9 N003 ( 4, 3) [000465] ------?N---- | \--* ADD long $306 N001 ( 3, 2) [000466] ------?----- | +--* LCL_VAR long V26 tmp12 u:1 (last use) $2e7 N002 ( 1, 1) [000467] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000468] ------?----- \--* CNS_INT long 56 $244 ------------ BB62 [???..???), preds={BB60} succs={BB63} ***** BB62 STMT00157 (IL ???... ???) N007 ( 23, 22) [001162] -AC-G---R--- * ASG long $332 N006 ( 3, 2) [001161] D------N---- +--* LCL_VAR long V28 tmp14 d:2 $332 N005 ( 19, 19) [000458] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 N003 ( 3, 2) [000445] ------?----- arg0 in rcx +--* LCL_VAR long V26 tmp12 u:1 (last use) $2e7 N004 ( 2, 10) [000457] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $52 ------------ BB63 [???..157) (throw), preds={BB61,BB62} succs={} ***** BB63 STMT00167 (IL ???... ???) N005 ( 0, 0) [001184] -A------R--- * ASG long N004 ( 0, 0) [001182] D------N---- +--* LCL_VAR long V28 tmp14 d:1 N003 ( 0, 0) [001183] ------------ \--* PHI long N001 ( 0, 0) [001241] ------------ pred BB61 +--* PHI_ARG long V28 tmp14 u:3 N002 ( 0, 0) [001240] ------------ pred BB62 \--* PHI_ARG long V28 tmp14 u:2 $332 ***** BB63 STMT00076 (IL ???... ???) N005 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void N003 ( 3, 2) [000473] ------------ arg0 in rcx +--* LCL_VAR long V28 tmp14 u:1 (last use) $347 N004 ( 1, 1) [000455] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) $101 ------------ BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} ***** BB64 STMT00053 (IL 0x1BC...0x1BD) N004 ( 7, 5) [000299] -A-X----R--- * ASG long $2e8 N003 ( 3, 2) [000298] D------N---- +--* LCL_VAR long V21 tmp7 d:1 $2e7 N002 ( 3, 2) [000297] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000296] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB64 STMT00161 (IL ???... ???) N011 ( 16, 14) [001168] ------------ * JTRUE void N010 ( 14, 12) [000315] J------N---- \--* EQ int N008 ( 12, 10) [000311] n----------- +--* IND long N007 ( 10, 8) [000307] -------N---- | \--* ADD long $331 N005 ( 9, 7) [000305] #----------- | +--* IND long $2ea N004 ( 6, 5) [000304] #----------- | | \--* IND long $2e9 N003 ( 4, 3) [000303] -------N---- | | \--* ADD long $306 N001 ( 3, 2) [000301] ------------ | | +--* LCL_VAR long V21 tmp7 u:1 $2e7 N002 ( 1, 1) [000302] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000306] ------------ | \--* CNS_INT long 56 $244 N009 ( 1, 1) [000314] ------------ \--* CNS_INT long 0 $243 ------------ BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} ***** BB65 STMT00162 (IL ???... ???) N010 ( 16, 13) [001170] -A------R--- * ASG long N009 ( 3, 2) [001169] D------N---- +--* LCL_VAR long V23 tmp9 d:3 N008 ( 12, 10) [000316] n-----?----- \--* IND long N007 ( 10, 8) [000317] ------?N---- \--* ADD long $331 N005 ( 9, 7) [000318] #-----?----- +--* IND long $2ea N004 ( 6, 5) [000319] #-----?----- | \--* IND long $2e9 N003 ( 4, 3) [000320] ------?N---- | \--* ADD long $306 N001 ( 3, 2) [000321] ------?----- | +--* LCL_VAR long V21 tmp7 u:1 (last use) $2e7 N002 ( 1, 1) [000322] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000323] ------?----- \--* CNS_INT long 56 $244 ------------ BB66 [???..???), preds={BB64} succs={BB67} ***** BB66 STMT00163 (IL ???... ???) N007 ( 23, 22) [001172] -AC-G---R--- * ASG long $332 N006 ( 3, 2) [001171] D------N---- +--* LCL_VAR long V23 tmp9 d:2 $332 N005 ( 19, 19) [000313] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 N003 ( 3, 2) [000300] ------?----- arg0 in rcx +--* LCL_VAR long V21 tmp7 u:1 (last use) $2e7 N004 ( 2, 10) [000312] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $52 ------------ BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} ***** BB67 STMT00173 (IL ???... ???) N005 ( 0, 0) [001202] -A------R--- * ASG long N004 ( 0, 0) [001200] D------N---- +--* LCL_VAR long V23 tmp9 d:1 N003 ( 0, 0) [001201] ------------ \--* PHI long N001 ( 0, 0) [001232] ------------ pred BB65 +--* PHI_ARG long V23 tmp9 u:3 N002 ( 0, 0) [001231] ------------ pred BB66 \--* PHI_ARG long V23 tmp9 u:2 $332 ***** BB67 STMT00056 (IL ???... ???) N005 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void N003 ( 3, 2) [000328] ------------ arg0 in rcx +--* LCL_VAR long V23 tmp9 u:1 (last use) $34b N004 ( 1, 1) [000310] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) $101 ------------ BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} ***** BB68 STMT00043 (IL 0x1DD...0x1E2) N001 ( 14, 5) [000233] --CXG------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported $VN.Void ------------------------------------------------------------------------------------------------------------------- optHoistLoopCode for loop L00 : Loop body contains a call Loop has multiple exits USEDEF (6)={V04 V09 V07 V01 V06 V12} INOUT (11)={V04 V09 V07 V00 V01 V06 V05 V03 V02 V12 V08} LOOPVARS(6)={V04 V09 V07 V01 V06 V12} optHoistLoopBlocks BB23 (weight= 4 ) of loop L00 , firstBlock is true *************** Finishing PHASE Hoist loop code *************** Starting PHASE VN based copy prop *************** In optVnCopyProp() Copy Assertion for BB01 curSsaName stack: { } Copy Assertion for BB59 curSsaName stack: { 1-[000000]:V01 } Copy Assertion for BB02 curSsaName stack: { 1-[000000]:V01 } Copy Assertion for BB04 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 } Live vars: {V00 V01 V02 V03} => {V00 V01 V02 V03 V33} Live vars: {V00 V01 V02 V03 V33} => {V00 V01 V02 V03 V33 V34} Live vars: {V00 V01 V02 V03 V33 V34} => {V00 V01 V02 V03 V33 V34 V35} Live vars: {V00 V01 V02 V03 V33 V34 V35} => {V00 V01 V02 V03 V34 V35} Copy Assertion for BB06 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 } Live vars: {V00 V01 V02 V03} => {V00 V01 V02 V03 V04} Live vars: {V00 V01 V02 V03 V04} => {V00 V01 V02 V03 V04 V36} Live vars: {V00 V01 V02 V03 V04 V36} => {V00 V01 V02 V03 V04 V36 V37} Live vars: {V00 V01 V02 V03 V04 V36 V37} => {V00 V01 V02 V03 V04 V37} Copy Assertion for BB08 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 4-[000017]:V04 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 } Live vars: {V00 V01 V02 V03 V04} => {V00 V01 V02 V03 V04 V05} Copy Assertion for BB14 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 4-[000017]:V04 5-[000027]:V05 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 } Live vars: {V00 V01 V02 V03 V04 V05 V15} => {V00 V01 V02 V03 V04 V05} Live vars: {V00 V01 V02 V03 V04 V05} => {V00 V01 V02 V03 V04 V05 V06} Live vars: {V00 V01 V02 V03 V04 V05 V06} => {V00 V01 V02 V03 V04 V05 V06 V07} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07} => {V00 V01 V02 V03 V04 V05 V06 V07 V39} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V43} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V43} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V43 V44} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V43 V44} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V43 V44 V45} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V43 V44 V45} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V44 V45} Copy Assertion for BB16 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[000044]:V07 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V42} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V42} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V46} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V46} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V46 V47} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V46 V47} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V46 V47 V48} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V46 V47 V48} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V47 V48} Copy Assertion for BB18 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[000044]:V07 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42} => {V00 V01 V02 V03 V04 V05 V06 V07 V42} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V42} => {V00 V01 V02 V03 V04 V05 V06 V07} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07} => {V00 V01 V02 V03 V04 V05 V06 V07 V38} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V38} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V38} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V38} => {V00 V01 V02 V03 V04 V05 V06 V07 V08} VN based copy assertion for [000052] V38 @00000081 by [000050] V08 @00000081. N001 ( 1, 1) [000052] ------------ * LCL_VAR byref V38 tmp24 u:1 (last use) $81 copy propagated to: N001 ( 1, 1) [000052] ------------ * LCL_VAR byref V08 loc4 u:1 (last use) $81 Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09} Copy Assertion for BB68 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[000044]:V07 8-[000050]:V08 9-[000056]:V09 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Copy Assertion for BB58 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[000044]:V07 8-[000050]:V08 9-[000056]:V09 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Copy Assertion for BB44 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[000044]:V07 8-[000050]:V08 9-[000056]:V09 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Copy Assertion for BB55 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001179]:V07 8-[000050]:V08 9-[000056]:V09 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10} => {V00 V01 V02 V04 V05 V06 V07 V08 V10 V11} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10 V11} => {V00 V01 V02 V04 V05 V07 V08 V10 V11} Live vars: {V00 V01 V02 V04 V05 V07 V08 V10 V11} => {V00 V02 V04 V05 V07 V08 V10 V11} Live vars: {V00 V02 V04 V05 V07 V08 V10 V11} => {V00 V02 V04 V05 V07 V08 V10} Live vars: {V00 V02 V04 V05 V07 V08 V10} => {V00 V04 V05 V07 V08 V10} Live vars: {V00 V04 V05 V07 V08 V10} => {V00 V04 V05 V07 V08} Live vars: {V00 V04 V05 V07 V08} => {V00 V04 V05 V07} Live vars: {V00 V04 V05 V07} => {V00 V04 V05} Copy Assertion for BB56 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 4-[001188]:V04 5-[000027]:V05 6-[000041]:V06 7-[001179]:V07 8-[001194]:V08 9-[000056]:V09 10-[001185]:V10 11-[000098]:V11 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V04 V05} => {V00 V04} Copy Assertion for BB57 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 4-[001188]:V04 5-[000027]:V05 6-[000041]:V06 7-[001179]:V07 8-[001194]:V08 9-[000056]:V09 10-[001185]:V10 11-[000098]:V11 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V04} => {V00} Copy Assertion for BB48 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001179]:V07 8-[000050]:V08 9-[000056]:V09 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V02 V04 V05 V06 V07 V08} => {V00 V01 V02 V04 V05 V06 V07 V08 V13} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V13} => {V00 V01 V02 V05 V06 V07 V08 V13} Copy Assertion for BB54 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001179]:V07 8-[000050]:V08 9-[000056]:V09 13-[000074]:V13 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V02 V05 V06 V07 V08 V13} => {V00 V01 V02 V05 V06 V07 V08 V10 V13} Live vars: {V00 V01 V02 V05 V06 V07 V08 V10 V13} => {V00 V01 V02 V05 V06 V07 V08 V10} VN based copy assertion for [000085] V13 @000001D3 by [000082] V10 @000001D3. N001 ( 3, 2) [000085] ------------ * LCL_VAR int V13 loc9 u:1 (last use) copy propagated to: N001 ( 3, 2) [000085] ------------ * LCL_VAR int V10 loc6 u:2 (last use) Live vars: {V00 V01 V02 V05 V06 V07 V08 V10} => {V00 V01 V02 V04 V05 V06 V07 V08 V10} Copy Assertion for BB49 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001179]:V07 8-[000050]:V08 9-[000056]:V09 13-[000074]:V13 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V02 V05 V06 V07 V13} => {V00 V01 V02 V05 V06 V07 V13 V64} Live vars: {V00 V01 V02 V05 V06 V07 V13 V64} => {V00 V01 V02 V05 V06 V07 V13} Live vars: {V00 V01 V02 V05 V06 V07 V13} => {V00 V01 V02 V05 V06 V07 V13 V52} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52} => {V00 V01 V02 V05 V06 V07 V13 V52 V53} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V53} => {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54} => {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V56} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V56} => {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V56 V57} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V56 V57} => {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V56 V57 V58} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V56 V57 V58} => {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V57 V58} Copy Assertion for BB51 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 4-[000017]:V04 64-[001089]:V64 5-[000027]:V05 6-[000041]:V06 7-[001179]:V07 8-[000050]:V08 9-[000056]:V09 13-[000074]:V13 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 52-[000710]:V52 53-[000759]:V53 54-[000761]:V54 56-[000772]:V56 57-[000782]:V57 58-[000784]:V58 } Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54} => {V00 V01 V02 V05 V06 V07 V13 V52 V53} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V53} => {V00 V01 V02 V05 V06 V07 V13 V52 V53 V55} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V53 V55} => {V00 V01 V02 V05 V06 V07 V13 V52 V55} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V55} => {V00 V01 V02 V05 V06 V07 V13 V52 V55 V59} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V55 V59} => {V00 V01 V02 V05 V06 V07 V13 V52 V55 V59 V60} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V55 V59 V60} => {V00 V01 V02 V05 V06 V07 V13 V52 V55 V59 V60 V61} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V55 V59 V60 V61} => {V00 V01 V02 V05 V06 V07 V13 V52 V55 V60 V61} Copy Assertion for BB53 curSsaName stack: { 59-[000795]:V59 0-[000004]:V00 60-[000805]:V60 1-[000000]:V01 61-[000807]:V61 2-[000116]:V02 4-[000017]:V04 64-[001089]:V64 5-[000027]:V05 6-[000041]:V06 7-[001179]:V07 8-[000050]:V08 9-[000056]:V09 13-[000074]:V13 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 52-[000710]:V52 53-[000759]:V53 54-[000761]:V54 55-[000749]:V55 56-[000772]:V56 57-[000782]:V57 58-[000784]:V58 } Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V55} => {V00 V01 V02 V05 V06 V07 V13 V55} Live vars: {V00 V01 V02 V05 V06 V07 V13 V55} => {V00 V01 V02 V05 V06 V07 V13} Live vars: {V00 V01 V02 V05 V06 V07 V13} => {V00 V01 V02 V05 V06 V07 V13 V51} Live vars: {V00 V01 V02 V05 V06 V07 V13 V51} => {V00 V01 V02 V05 V06 V07 V13} Live vars: {V00 V01 V02 V05 V06 V07 V13} => {V00 V01 V02 V05 V06 V07 V08 V13} Copy Assertion for BB52 curSsaName stack: { 59-[000795]:V59 0-[000004]:V00 60-[000805]:V60 1-[000000]:V01 61-[000807]:V61 2-[000116]:V02 4-[000017]:V04 64-[001089]:V64 5-[000027]:V05 6-[000041]:V06 7-[001179]:V07 8-[000050]:V08 9-[000056]:V09 13-[000074]:V13 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 52-[000710]:V52 53-[000759]:V53 54-[000761]:V54 55-[000749]:V55 56-[000772]:V56 57-[000782]:V57 58-[000784]:V58 } Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V55 V60 V61} => {V00 V01 V02 V05 V06 V07 V13 V52 V55 V61} VN based copy assertion for [000802] V60 @00000105 by [000807] V61 @00000105. N003 ( 3, 2) [000802] ------------ * LCL_VAR ref V60 tmp46 u:1 (last use) $105 copy propagated to: N003 ( 3, 2) [000802] ------------ * LCL_VAR ref V61 tmp47 u:1 (last use) $105 Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V55 V61} => {V00 V01 V02 V05 V06 V07 V13 V52 V55} Copy Assertion for BB50 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 4-[000017]:V04 64-[001089]:V64 5-[000027]:V05 6-[000041]:V06 7-[001179]:V07 8-[000050]:V08 9-[000056]:V09 13-[000074]:V13 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 52-[000710]:V52 53-[000759]:V53 54-[000761]:V54 56-[000772]:V56 57-[000782]:V57 58-[000784]:V58 } Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V57 V58} => {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V58} VN based copy assertion for [000779] V57 @00000105 by [000784] V58 @00000105. N003 ( 3, 2) [000779] ------------ * LCL_VAR ref V57 tmp43 u:1 (last use) $105 copy propagated to: N003 ( 3, 2) [000779] ------------ * LCL_VAR ref V58 tmp44 u:1 (last use) $105 Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V58} => {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54} Copy Assertion for BB45 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001179]:V07 8-[000050]:V08 9-[000056]:V09 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V02 V04 V05 V06 V07 V08} => {V00 V01 V02 V04 V05 V06 V07 V08 V10} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10} => {V00 V01 V02 V04 V05 V06 V07 V08 V10 V62} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10 V62} => {V00 V01 V02 V04 V05 V06 V07 V08 V10} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10} => {V00 V01 V02 V04 V05 V06 V07 V08 V10 V49} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10 V49} => {V00 V01 V02 V04 V05 V06 V07 V08 V10 V49 V50} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10 V49 V50} => {V00 V01 V02 V04 V05 V06 V07 V08 V10 V50} Copy Assertion for BB47 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 62-[001031]:V62 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001179]:V07 8-[000050]:V08 9-[000056]:V09 10-[000173]:V10 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 49-[000687]:V49 50-[000697]:V50 } Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10} => {V00 V01 V02 V04 V05 V06 V07 V08 V10 V63} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10 V63} => {V00 V01 V02 V04 V05 V06 V07 V08 V10} Copy Assertion for BB46 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 62-[001031]:V62 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001179]:V07 8-[000050]:V08 9-[000056]:V09 10-[000173]:V10 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 49-[000687]:V49 50-[000697]:V50 } Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10 V50} => {V00 V01 V02 V04 V05 V06 V07 V08 V10} Copy Assertion for BB32 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[000044]:V07 8-[000050]:V08 9-[000056]:V09 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Copy Assertion for BB33 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001206]:V07 8-[000050]:V08 9-[001203]:V09 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Copy Assertion for BB42 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001206]:V07 8-[000050]:V08 9-[001203]:V09 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09} => {V00 V01 V02 V03 V04 V05 V06 V07 V08} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09} => {V00 V01 V02 V03 V04 V05 V06 V08 V09} Live vars: {V00 V01 V02 V03 V04 V05 V06 V08 V09} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09} Copy Assertion for BB43 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[000226]:V07 8-[000050]:V08 9-[000221]:V09 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Copy Assertion for BB34 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001206]:V07 8-[000050]:V08 9-[001203]:V09 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V17} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V16 V17} Copy Assertion for BB37 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001206]:V07 8-[000050]:V08 9-[001203]:V09 15-[001212]:V15 16-[000243]:V16 17-[000245]:V17 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V17 V19} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V19} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V19} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09} Copy Assertion for BB38 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001206]:V07 8-[000050]:V08 9-[001203]:V09 15-[001212]:V15 16-[000243]:V16 17-[000245]:V17 19-[001209]:V19 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Copy Assertion for BB40 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001206]:V07 8-[000050]:V08 9-[001203]:V09 15-[001212]:V15 16-[000243]:V16 17-[000245]:V17 19-[001209]:V19 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V03} => {V00 V01} Copy Assertion for BB64 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001206]:V07 8-[000050]:V08 9-[001203]:V09 15-[001212]:V15 16-[000243]:V16 17-[000245]:V17 19-[001209]:V19 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01} => {V00 V01 V21} Copy Assertion for BB67 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001206]:V07 8-[000050]:V08 9-[001203]:V09 15-[001212]:V15 16-[000243]:V16 17-[000245]:V17 19-[001209]:V19 21-[000298]:V21 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V23} => {V00 V01} Live vars: {V00 V01} => {V00} Copy Assertion for BB66 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001206]:V07 8-[000050]:V08 9-[001203]:V09 15-[001212]:V15 16-[000243]:V16 17-[000245]:V17 19-[001209]:V19 21-[000298]:V21 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V21} => {V00 V01} Live vars: {V00 V01} => {V00 V01 V23} Copy Assertion for BB65 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001206]:V07 8-[000050]:V08 9-[001203]:V09 15-[001212]:V15 16-[000243]:V16 17-[000245]:V17 19-[001209]:V19 21-[000298]:V21 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V21} => {V00 V01} Live vars: {V00 V01} => {V00 V01 V23} Copy Assertion for BB41 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001206]:V07 8-[000050]:V08 9-[001203]:V09 15-[001212]:V15 16-[000243]:V16 17-[000245]:V17 19-[001209]:V19 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Copy Assertion for BB39 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001206]:V07 8-[000050]:V08 9-[001203]:V09 15-[001212]:V15 16-[000243]:V16 17-[000245]:V17 19-[001209]:V19 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V02 V04 V09} => {V00 V02 V09} Live vars: {V00 V02 V09} => {V00 V02} Live vars: {V00 V02} => {V00} Copy Assertion for BB36 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001206]:V07 8-[000050]:V08 9-[001203]:V09 15-[001212]:V15 16-[000243]:V16 17-[000245]:V17 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V16 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V17} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V17 V19} Copy Assertion for BB35 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001206]:V07 8-[000050]:V08 9-[001203]:V09 15-[001212]:V15 16-[000243]:V16 17-[000245]:V17 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V16 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V17} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V17} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V17 V19} Copy Assertion for BB31 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[000044]:V07 8-[000050]:V08 9-[000056]:V09 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Copy Assertion for BB19 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[000044]:V07 8-[000050]:V08 9-[000056]:V09 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V24} Copy Assertion for BB22 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[000044]:V07 8-[000050]:V08 9-[000056]:V09 15-[001212]:V15 24-[000355]:V24 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V25} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12} Copy Assertion for BB23 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[000044]:V07 8-[000050]:V08 9-[000056]:V09 12-[000385]:V12 15-[001212]:V15 24-[000355]:V24 25-[001197]:V25 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Copy Assertion for BB24 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001176]:V07 8-[000050]:V08 9-[001173]:V09 12-[000385]:V12 15-[001212]:V15 24-[000355]:V24 25-[001197]:V25 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Copy Assertion for BB26 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001176]:V07 8-[000050]:V08 9-[001173]:V09 12-[000385]:V12 15-[001212]:V15 24-[000355]:V24 25-[001197]:V25 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12} => {V00 V01 V02 V03 V04 V05 V06 V08 V09 V12} Live vars: {V00 V01 V02 V03 V04 V05 V06 V08 V09 V12} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12} Copy Assertion for BB27 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[000410]:V07 8-[000050]:V08 9-[000405]:V09 12-[000385]:V12 15-[001212]:V15 24-[000355]:V24 25-[001197]:V25 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Copy Assertion for BB25 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001176]:V07 8-[000050]:V08 9-[001173]:V09 12-[000385]:V12 15-[001212]:V15 24-[000355]:V24 25-[001197]:V25 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Copy Assertion for BB28 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001176]:V07 8-[000050]:V08 9-[001173]:V09 12-[000385]:V12 15-[001212]:V15 24-[000355]:V24 25-[001197]:V25 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Copy Assertion for BB30 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001176]:V07 8-[000050]:V08 9-[001173]:V09 12-[000385]:V12 15-[001212]:V15 24-[000355]:V24 25-[001197]:V25 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V03} => {V00 V01} Copy Assertion for BB60 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001176]:V07 8-[000050]:V08 9-[001173]:V09 12-[000385]:V12 15-[001212]:V15 24-[000355]:V24 25-[001197]:V25 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01} => {V00 V01 V26} Copy Assertion for BB63 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001176]:V07 8-[000050]:V08 9-[001173]:V09 12-[000385]:V12 15-[001212]:V15 24-[000355]:V24 25-[001197]:V25 26-[000443]:V26 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V28} => {V00 V01} Live vars: {V00 V01} => {V00} Copy Assertion for BB62 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001176]:V07 8-[000050]:V08 9-[001173]:V09 12-[000385]:V12 15-[001212]:V15 24-[000355]:V24 25-[001197]:V25 26-[000443]:V26 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V26} => {V00 V01} Live vars: {V00 V01} => {V00 V01 V28} Copy Assertion for BB61 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001176]:V07 8-[000050]:V08 9-[001173]:V09 12-[000385]:V12 15-[001212]:V15 24-[000355]:V24 25-[001197]:V25 26-[000443]:V26 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V26} => {V00 V01} Live vars: {V00 V01} => {V00 V01 V28} Copy Assertion for BB29 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[001176]:V07 8-[000050]:V08 9-[001173]:V09 12-[000385]:V12 15-[001212]:V15 24-[000355]:V24 25-[001197]:V25 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V02 V04 V09} => {V00 V02 V09} Live vars: {V00 V02 V09} => {V00 V02} Live vars: {V00 V02} => {V00} Copy Assertion for BB21 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[000044]:V07 8-[000050]:V08 9-[000056]:V09 15-[001212]:V15 24-[000355]:V24 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V24} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V25} Copy Assertion for BB20 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[000044]:V07 8-[000050]:V08 9-[000056]:V09 15-[001212]:V15 24-[000355]:V24 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 38-[000590]:V38 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V24} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V25} Copy Assertion for BB17 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[000044]:V07 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 42-[000618]:V42 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 46-[000664]:V46 47-[000674]:V47 48-[000676]:V48 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V47 V48} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V48} VN based copy assertion for [000671] V47 @00000105 by [000676] V48 @00000105. N003 ( 1, 1) [000671] ------------ * LCL_VAR ref V47 tmp33 u:1 (last use) $105 copy propagated to: N003 ( 1, 1) [000671] ------------ * LCL_VAR ref V48 tmp34 u:1 (last use) $105 Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V48} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42} Copy Assertion for BB15 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 6-[000041]:V06 7-[000044]:V07 15-[001212]:V15 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 39-[000579]:V39 40-[000628]:V40 41-[000630]:V41 43-[000641]:V43 44-[000651]:V44 45-[000653]:V45 } Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V44 V45} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V45} VN based copy assertion for [000648] V44 @00000105 by [000653] V45 @00000105. N003 ( 1, 1) [000648] ------------ * LCL_VAR ref V44 tmp30 u:1 (last use) $105 copy propagated to: N003 ( 1, 1) [000648] ------------ * LCL_VAR ref V45 tmp31 u:1 (last use) $105 Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V45} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41} Copy Assertion for BB13 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 } Live vars: {V00 V01 V02 V03 V04 V05} => {V00 V01 V02 V03 V04 V05 V15} Copy Assertion for BB09 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 } Live vars: {V00 V01 V02 V03 V04 V05} => {V00 V01 V02 V03 V04 V05 V29} Copy Assertion for BB12 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 29-[000488]:V29 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 } Live vars: {V00 V01 V02 V03 V04 V05 V31} => {V00 V01 V02 V03 V04 V05} Live vars: {V00 V01 V02 V03 V04 V05} => {V00 V01 V02 V03 V04 V05 V15} Copy Assertion for BB11 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 29-[000488]:V29 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 } Live vars: {V00 V01 V02 V03 V04 V05 V29} => {V00 V01 V02 V03 V04 V05} Live vars: {V00 V01 V02 V03 V04 V05} => {V00 V01 V02 V03 V04 V05 V31} Copy Assertion for BB10 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 5-[000027]:V05 29-[000488]:V29 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 } Live vars: {V00 V01 V02 V03 V04 V05 V29} => {V00 V01 V02 V03 V04 V05} Live vars: {V00 V01 V02 V03 V04 V05} => {V00 V01 V02 V03 V04 V05 V31} Copy Assertion for BB07 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 4-[000017]:V04 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 36-[000565]:V36 37-[000575]:V37 } Live vars: {V00 V01 V02 V03 V04 V37} => {V00 V01 V02 V03 V04} Copy Assertion for BB05 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 33-[000543]:V33 34-[000553]:V34 35-[000555]:V35 } Live vars: {V00 V01 V02 V03 V34 V35} => {V00 V01 V02 V03 V35} VN based copy assertion for [000550] V34 @00000105 by [000555] V35 @00000105. N003 ( 1, 1) [000550] ------------ * LCL_VAR ref V34 tmp20 u:1 (last use) $105 copy propagated to: N003 ( 1, 1) [000550] ------------ * LCL_VAR ref V35 tmp21 u:1 (last use) $105 Live vars: {V00 V01 V02 V03 V35} => {V00 V01 V02 V03} Copy Assertion for BB03 curSsaName stack: { 0-[000004]:V00 1-[000000]:V01 2-[000116]:V02 3-[000284]:V03 } *************** Finishing PHASE VN based copy prop *************** Starting PHASE Redundant branch opts ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal Loop1 gcsafe BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe BB36 [0108] 1 BB34 1 [???..???) i gcsafe BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen BB54 [0044] 2 BB48,BB53 0.50 [261..276) i BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Redundant branch opts [no changes] *************** Starting PHASE Optimize Valnum CSEs *************** In optOptimizeCSEs() Blocks/Trees at start of optOptimizeCSE phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal Loop1 gcsafe BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe BB36 [0108] 1 BB34 1 [???..???) i gcsafe BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen BB54 [0044] 2 BB48,BB53 0.50 [261..276) i BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} ***** BB01 STMT00000 (IL 0x000...0x006) N004 ( 5, 5) [000003] ------------ * JTRUE void N003 ( 3, 3) [000002] J------N---- \--* EQ int $180 N001 ( 1, 1) [000000] ------------ +--* LCL_VAR ref V01 arg1 u:1 $101 N002 ( 1, 1) [000001] ------------ \--* CNS_INT ref null $VN.Null ------------ BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00001 (IL 0x00E...0x014) N007 ( 8, 8) [000008] ---XG------- * JTRUE void N006 ( 6, 6) [000007] J--XG--N---- \--* NE int N004 ( 4, 4) [000005] ---XG------- +--* IND ref N003 ( 2, 2) [000814] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000004] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000813] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] $240 N005 ( 1, 1) [000006] ------------ \--* CNS_INT ref null $VN.Null ------------ BB03 [016..01E), preds={BB02} succs={BB04} ***** BB03 STMT00085 (IL ???... ???) N005 ( 16, 10) [000528] --CXG------- * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize $1c2 N003 ( 1, 1) [000526] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N004 ( 1, 1) [000527] ------------ arg1 in rdx \--* CNS_INT int 0 $c0 ------------ BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ***** BB04 STMT00088 (IL 0x01E... ???) N008 ( 9, 6) [000544] -A-XG---R--- * ASG bool N007 ( 1, 1) [000543] D------N---- +--* LCL_VAR int V33 tmp19 d:1 N006 ( 9, 6) [000012] N--XG------- \--* NE int N004 ( 4, 4) [000010] ---XG------- +--* IND ref N003 ( 2, 2) [000818] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000009] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000817] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] $240 N005 ( 1, 1) [000011] ------------ \--* CNS_INT ref null $VN.Null ***** BB04 STMT00091 (IL 0x01E... ???) N004 ( 4, 12) [000554] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000553] D------N---- +--* LCL_VAR ref V34 tmp20 d:1 $105 N002 ( 4, 12) [000538] #---G------- \--* IND ref $105 N001 ( 2, 10) [000537] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB04 STMT00092 (IL 0x01E... ???) N004 ( 4, 12) [000556] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000555] D------N---- +--* LCL_VAR ref V35 tmp21 d:1 $105 N002 ( 4, 12) [000540] #---G------- \--* IND ref $105 N001 ( 2, 10) [000539] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB04 STMT00089 (IL 0x01E... ???) N004 ( 5, 5) [000549] ------------ * JTRUE void N003 ( 3, 3) [000548] J------N---- \--* NE int N001 ( 1, 1) [000546] ------------ +--* LCL_VAR int V33 tmp19 u:1 (last use) N002 ( 1, 1) [000547] ------------ \--* CNS_INT int 0 $c0 ------------ BB05 [01E..01F), preds={BB04} succs={BB06} ***** BB05 STMT00090 (IL 0x01E... ???) N005 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 1, 1) [000550] ------------ arg0 in rcx +--* LCL_VAR ref V35 tmp21 u:1 (last use) $105 N004 ( 1, 1) [000551] ------------ arg1 in rdx \--* LCL_VAR ref V35 tmp21 u:1 (last use) $105 ------------ BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} ***** BB06 STMT00003 (IL 0x02C... ???) N006 ( 4, 4) [000018] -A-XG---R--- * ASG ref N005 ( 1, 1) [000017] D------N---- +--* LCL_VAR ref V04 loc0 d:1 N004 ( 4, 4) [000016] ---XG------- \--* IND ref N003 ( 2, 2) [000822] -------N---- \--* ADD byref $281 N001 ( 1, 1) [000015] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000821] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] $241 ***** BB06 STMT00094 (IL 0x033... ???) N005 ( 6, 3) [000566] -A------R--- * ASG bool N004 ( 1, 1) [000565] D------N---- +--* LCL_VAR int V36 tmp22 d:1 N003 ( 6, 3) [000021] N----------- \--* NE int N001 ( 1, 1) [000019] ------------ +--* LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000020] ------------ \--* CNS_INT ref null $VN.Null ***** BB06 STMT00097 (IL 0x033... ???) N004 ( 4, 12) [000576] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000575] D------N---- +--* LCL_VAR ref V37 tmp23 d:1 $105 N002 ( 4, 12) [000562] #---G------- \--* IND ref $105 N001 ( 2, 10) [000561] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB06 STMT00095 (IL 0x033... ???) N004 ( 5, 5) [000571] ------------ * JTRUE void N003 ( 3, 3) [000570] J------N---- \--* NE int N001 ( 1, 1) [000568] ------------ +--* LCL_VAR int V36 tmp22 u:1 (last use) N002 ( 1, 1) [000569] ------------ \--* CNS_INT int 0 $c0 ------------ BB07 [033..034), preds={BB06} succs={BB08} ***** BB07 STMT00096 (IL 0x033... ???) N006 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N004 ( 4, 12) [000824] #---G------- arg0 in rcx +--* IND ref $106 N003 ( 2, 10) [000823] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" $46 N005 ( 1, 1) [000573] ------------ arg1 in rdx \--* LCL_VAR ref V37 tmp23 u:1 (last use) $105 ------------ BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} ***** BB08 STMT00005 (IL 0x041... ???) N006 ( 4, 4) [000028] -A-XG---R--- * ASG ref N005 ( 1, 1) [000027] D------N---- +--* LCL_VAR ref V05 loc1 d:1 N004 ( 4, 4) [000026] ---XG------- \--* IND ref N003 ( 2, 2) [000828] -------N---- \--* ADD byref $282 N001 ( 1, 1) [000025] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000827] ------------ \--* CNS_INT long 24 field offset Fseq[_comparer] $242 ***** BB08 STMT00006 (IL 0x048...0x049) N004 ( 5, 5) [000032] ------------ * JTRUE void N003 ( 3, 3) [000031] J------N---- \--* EQ int N001 ( 1, 1) [000029] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000030] ------------ \--* CNS_INT ref null $VN.Null ------------ BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} ***** BB09 STMT00079 (IL 0x04B...0x052) N004 ( 3, 3) [000489] -A-X----R--- * ASG long $2e8 N003 ( 1, 1) [000488] D------N---- +--* LCL_VAR long V29 tmp15 d:1 $2e7 N002 ( 3, 2) [000487] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000486] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB09 STMT00149 (IL ???... ???) N011 ( 14, 13) [001148] ------------ * JTRUE void N010 ( 12, 11) [000505] J------N---- \--* EQ int N008 ( 10, 9) [000501] n----------- +--* IND long N007 ( 8, 7) [000497] -------N---- | \--* ADD long $307 N005 ( 7, 6) [000495] #----------- | +--* IND long $2ea N004 ( 4, 4) [000494] #----------- | | \--* IND long $2e9 N003 ( 2, 2) [000493] -------N---- | | \--* ADD long $306 N001 ( 1, 1) [000491] ------------ | | +--* LCL_VAR long V29 tmp15 u:1 $2e7 N002 ( 1, 1) [000492] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000496] ------------ | \--* CNS_INT long 64 $245 N009 ( 1, 1) [000504] ------------ \--* CNS_INT long 0 $243 ------------ BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} ***** BB10 STMT00150 (IL ???... ???) N010 ( 10, 9) [001150] -A------R--- * ASG long N009 ( 1, 1) [001149] D------N---- +--* LCL_VAR long V31 tmp17 d:3 N008 ( 10, 9) [000506] n-----?----- \--* IND long N007 ( 8, 7) [000507] ------?N---- \--* ADD long $307 N005 ( 7, 6) [000508] #-----?----- +--* IND long $2ea N004 ( 4, 4) [000509] #-----?----- | \--* IND long $2e9 N003 ( 2, 2) [000510] ------?N---- | \--* ADD long $306 N001 ( 1, 1) [000511] ------?----- | +--* LCL_VAR long V29 tmp15 u:1 (last use) $2e7 N002 ( 1, 1) [000512] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000513] ------?----- \--* CNS_INT long 64 $245 ------------ BB11 [???..???), preds={BB09} succs={BB12} ***** BB11 STMT00151 (IL ???... ???) N007 ( 17, 18) [001152] -AC-G---R--- * ASG long $308 N006 ( 1, 1) [001151] D------N---- +--* LCL_VAR long V31 tmp17 d:2 $308 N005 ( 17, 18) [000503] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $308 N003 ( 1, 1) [000490] ------?----- arg0 in rcx +--* LCL_VAR long V29 tmp15 u:1 (last use) $2e7 N004 ( 2, 10) [000502] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $49 ------------ BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} ***** BB12 STMT00178 (IL ???... ???) N005 ( 0, 0) [001217] -A------R--- * ASG long N004 ( 0, 0) [001215] D------N---- +--* LCL_VAR long V31 tmp17 d:1 N003 ( 0, 0) [001216] ------------ \--* PHI long N001 ( 0, 0) [001247] ------------ pred BB10 +--* PHI_ARG long V31 tmp17 u:3 N002 ( 0, 0) [001246] ------------ pred BB11 \--* PHI_ARG long V31 tmp17 u:2 $308 ***** BB12 STMT00083 (IL ???... ???) N010 ( 31, 15) [000524] -ACXG---R--- * ASG int $1c7 N009 ( 3, 2) [000523] D------N---- +--* LCL_VAR int V15 tmp1 d:3 $1c7 N008 ( 27, 12) [000522] --CXG------- \--* CALL ind stub int $1c7 N007 ( 1, 1) [000521] ------------ calli tgt \--* LCL_VAR long V31 tmp17 u:1 (last use) $342 N004 ( 1, 1) [000484] ------------ this in rcx +--* LCL_VAR ref V05 loc1 u:1 N005 ( 1, 1) [000831] ------------ arg1 in r11 +--* LCL_VAR long V31 tmp17 u:1 r11 REG r11 $342 N006 ( 1, 1) [000500] ------------ arg2 in rdx \--* LCL_VAR ref V01 arg1 u:1 $101 ------------ BB13 [054..061), preds={BB08} succs={BB14} ***** BB13 STMT00007 (IL 0x054...0x05C) N013 ( 34, 21) [000038] -ACXG---R--- * ASG int $1c5 N012 ( 3, 2) [000037] D------N---- +--* LCL_VAR int V15 tmp1 d:2 $1c5 N011 ( 30, 18) [000035] --CXG------- \--* CALLV vt-ind int System.Object.GetHashCode $1c5 N010 ( 9, 8) [000843] n--X-------- control expr \--* IND long N009 ( 7, 6) [000842] ---X---N---- \--* ADD long $303 N007 ( 6, 5) [000840] #--X-------- +--* IND long $2e6 N006 ( 4, 3) [000839] ---X---N---- | \--* ADD long $301 N004 ( 3, 2) [000837] #--X-------- | +--* IND long $2e4 N003 ( 1, 1) [000836] ------------ | | \--* LCL_VAR ref V01 arg1 u:1 $101 N005 ( 1, 1) [000838] ------------ | \--* CNS_INT int 72 $c9 N008 ( 1, 1) [000841] ------------ \--* CNS_INT int 24 $ca N002 ( 1, 1) [000033] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 $101 ------------ BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ***** BB14 STMT00177 (IL ???... ???) N005 ( 0, 0) [001214] -A------R--- * ASG int N004 ( 0, 0) [001212] D------N---- +--* LCL_VAR int V15 tmp1 d:1 N003 ( 0, 0) [001213] ------------ \--* PHI int N001 ( 0, 0) [001245] ------------ pred BB12 +--* PHI_ARG int V15 tmp1 u:3 $1c7 N002 ( 0, 0) [001244] ------------ pred BB13 \--* PHI_ARG int V15 tmp1 u:2 $1c5 ***** BB14 STMT00008 (IL ???...0x061) N003 ( 3, 3) [000042] -A------R--- * ASG int $3c0 N002 ( 1, 1) [000041] D------N---- +--* LCL_VAR int V06 loc2 d:1 $3c0 N001 ( 3, 2) [000040] ------------ \--* LCL_VAR int V15 tmp1 u:1 (last use) $3c0 ***** BB14 STMT00009 (IL 0x062...0x063) N003 ( 1, 3) [000045] -A------R--- * ASG int $c0 N002 ( 1, 1) [000044] D------N---- +--* LCL_VAR int V07 loc3 d:1 $c0 N001 ( 1, 1) [000043] ------------ \--* CNS_INT int 0 $c0 ***** BB14 STMT00098 (IL 0x064... ???) N006 ( 4, 4) [000580] -A-XG---R--- * ASG ref N005 ( 1, 1) [000579] D------N---- +--* LCL_VAR ref V39 tmp25 d:1 N004 ( 4, 4) [000578] ---XG------- \--* IND ref N003 ( 2, 2) [000845] -------N---- \--* ADD byref $280 N001 ( 1, 1) [000046] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000844] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] $240 ***** BB14 STMT00105 (IL 0x064... ???) N004 ( 3, 3) [000629] -A-X----R--- * ASG int N003 ( 1, 1) [000628] D------N---- +--* LCL_VAR int V40 tmp26 d:1 N002 ( 3, 3) [000583] ---X-------- \--* ARR_LENGTH int N001 ( 1, 1) [000582] ------------ \--* LCL_VAR ref V39 tmp25 u:1 ***** BB14 STMT00106 (IL 0x064... ???) N006 ( 4, 4) [000631] -A-XG---R--- * ASG long N005 ( 1, 1) [000630] D------N---- +--* LCL_VAR long V41 tmp27 d:1 N004 ( 4, 4) [000585] ---XG------- \--* IND long N003 ( 2, 2) [000847] -------N---- \--* ADD byref $283 N001 ( 1, 1) [000584] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000846] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 ***** BB14 STMT00108 (IL 0x064... ???) N005 ( 6, 6) [000642] -A------R--- * ASG bool N004 ( 1, 1) [000641] D------N---- +--* LCL_VAR int V43 tmp29 d:1 N003 ( 6, 6) [000599] N--------U-- \--* LE int N001 ( 1, 1) [000597] ------------ +--* LCL_VAR int V40 tmp26 u:1 N002 ( 1, 4) [000598] ------------ \--* CNS_INT int 0x7FFFFFFF $ce ***** BB14 STMT00111 (IL 0x064... ???) N004 ( 4, 12) [000652] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000651] D------N---- +--* LCL_VAR ref V44 tmp30 d:1 $105 N002 ( 4, 12) [000636] #---G------- \--* IND ref $105 N001 ( 2, 10) [000635] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB14 STMT00112 (IL 0x064... ???) N004 ( 4, 12) [000654] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000653] D------N---- +--* LCL_VAR ref V45 tmp31 d:1 $105 N002 ( 4, 12) [000638] #---G------- \--* IND ref $105 N001 ( 2, 10) [000637] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB14 STMT00109 (IL 0x064... ???) N004 ( 5, 5) [000647] ------------ * JTRUE void N003 ( 3, 3) [000646] J------N---- \--* NE int N001 ( 1, 1) [000644] ------------ +--* LCL_VAR int V43 tmp29 u:1 (last use) N002 ( 1, 1) [000645] ------------ \--* CNS_INT int 0 $c0 ------------ BB15 [064..065), preds={BB14} succs={BB16} ***** BB15 STMT00110 (IL 0x064... ???) N005 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 1, 1) [000648] ------------ arg0 in rcx +--* LCL_VAR ref V45 tmp31 u:1 (last use) $105 N004 ( 1, 1) [000649] ------------ arg1 in rdx \--* LCL_VAR ref V45 tmp31 u:1 (last use) $105 ------------ BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} ***** BB16 STMT00103 (IL 0x064... ???) N016 ( 20, 21) [000619] -A------R--- * ASG int N015 ( 1, 1) [000618] D------N---- +--* LCL_VAR int V42 tmp28 d:1 N014 ( 20, 21) [000617] ------------ \--* CAST int <- uint <- long N013 ( 19, 19) [000616] ------------ \--* RSZ long N011 ( 17, 17) [000614] ------------ +--* MUL long N008 ( 11, 11) [000611] ------------ | +--* ADD long N006 ( 9, 9) [000608] ------------ | | +--* RSZ long N004 ( 7, 7) [000606] ------------ | | | +--* MUL long N001 ( 1, 1) [000604] ------------ | | | | +--* LCL_VAR long V41 tmp27 u:1 (last use) N003 ( 2, 3) [000605] ---------U-- | | | | \--* CAST long <- ulong <- uint $310 N002 ( 1, 1) [000047] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 $3c0 N005 ( 1, 1) [000607] ------------ | | | \--* CNS_INT int 32 $d2 N007 ( 1, 1) [000610] ------------ | | \--* CNS_INT long 1 $247 N010 ( 2, 3) [000613] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000612] ------------ | \--* LCL_VAR int V40 tmp26 u:1 N012 ( 1, 1) [000615] ------------ \--* CNS_INT int 32 $d2 ***** BB16 STMT00114 (IL 0x064... ???) N007 ( 27, 7) [000665] -A-X----R--- * ASG bool N006 ( 1, 1) [000664] D------N---- +--* LCL_VAR int V46 tmp32 d:1 N005 ( 27, 7) [000624] ---X-------- \--* EQ int N003 ( 22, 5) [000623] ---X-------- +--* UMOD int N001 ( 1, 1) [000621] ------------ | +--* LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000622] ------------ | \--* LCL_VAR int V40 tmp26 u:1 (last use) N004 ( 1, 1) [000620] ------------ \--* LCL_VAR int V42 tmp28 u:1 ***** BB16 STMT00117 (IL 0x064... ???) N004 ( 4, 12) [000675] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000674] D------N---- +--* LCL_VAR ref V47 tmp33 d:1 $105 N002 ( 4, 12) [000659] #---G------- \--* IND ref $105 N001 ( 2, 10) [000658] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB16 STMT00118 (IL 0x064... ???) N004 ( 4, 12) [000677] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000676] D------N---- +--* LCL_VAR ref V48 tmp34 d:1 $105 N002 ( 4, 12) [000661] #---G------- \--* IND ref $105 N001 ( 2, 10) [000660] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB16 STMT00115 (IL 0x064... ???) N004 ( 5, 5) [000670] ------------ * JTRUE void N003 ( 3, 3) [000669] J------N---- \--* NE int N001 ( 1, 1) [000667] ------------ +--* LCL_VAR int V46 tmp32 u:1 (last use) N002 ( 1, 1) [000668] ------------ \--* CNS_INT int 0 $c0 ------------ BB17 [064..065), preds={BB16} succs={BB18} ***** BB17 STMT00116 (IL 0x064... ???) N005 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 1, 1) [000671] ------------ arg0 in rcx +--* LCL_VAR ref V48 tmp34 u:1 (last use) $105 N004 ( 1, 1) [000672] ------------ arg1 in rdx \--* LCL_VAR ref V48 tmp34 u:1 (last use) $105 ------------ BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} ***** BB18 STMT00100 (IL 0x064... ???) N017 ( 19, 24) [000591] -A-XG---R--- * ASG byref N016 ( 1, 1) [000590] D------N---- +--* LCL_VAR byref V38 tmp24 d:1 $81 N015 ( 19, 24) [000862] ---XG------- \--* COMMA byref N004 ( 8, 11) [000855] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000627] ------------ | +--* LCL_VAR int V42 tmp28 u:1 N003 ( 3, 3) [000854] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000581] ------------ | \--* LCL_VAR ref V39 tmp25 u:1 N014 ( 11, 13) [000863] ----G------- \--* ADDR byref $81 N013 ( 6, 7) [000588] a---G--N---- \--* IND int N012 ( 5, 6) [000861] -------N---- \--* ADD byref $81 N005 ( 1, 1) [000852] ------------ +--* LCL_VAR ref V39 tmp25 u:1 (last use) N011 ( 4, 5) [000860] -------N---- \--* ADD long N009 ( 3, 4) [000858] -------N---- +--* LSH long N007 ( 2, 3) [000856] ------------ | +--* CAST long <- int N006 ( 1, 1) [000853] i----------- | | \--* LCL_VAR int V42 tmp28 u:1 (last use) N008 ( 1, 1) [000857] -------N---- | \--* CNS_INT long 2 $248 N010 ( 1, 1) [000859] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB18 STMT00011 (IL ???... ???) N003 ( 5, 4) [000051] -A------R--- * ASG byref $81 N002 ( 3, 2) [000050] D------N---- +--* LCL_VAR byref V08 loc4 d:1 $81 N001 ( 1, 1) [000592] ------------ \--* LCL_VAR byref V38 tmp24 u:1 $81 ***** BB18 STMT00012 (IL 0x06D...0x072) N006 ( 5, 4) [000057] -A-XG---R--- * ASG int N005 ( 1, 1) [000056] D------N---- +--* LCL_VAR int V09 loc5 d:1 N004 ( 5, 4) [000055] ---XG------- \--* ADD int N002 ( 3, 2) [000053] *--XG------- +--* IND int N001 ( 1, 1) [000052] ------------ | \--* LCL_VAR byref V08 loc4 u:1 (last use) $81 N003 ( 1, 1) [000054] ------------ \--* CNS_INT int -1 $c4 ***** BB18 STMT00013 (IL 0x074...0x075) N004 ( 5, 5) [000061] ------------ * JTRUE void N003 ( 3, 3) [000060] J------N---- \--* NE int N001 ( 1, 1) [000058] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000059] ------------ \--* CNS_INT ref null $VN.Null ------------ BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} ***** BB19 STMT00059 (IL 0x0FF...0x104) N004 ( 3, 3) [000356] -A-X----R--- * ASG long $2e8 N003 ( 1, 1) [000355] D------N---- +--* LCL_VAR long V24 tmp10 d:1 $2e7 N002 ( 3, 2) [000354] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000353] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB19 STMT00152 (IL ???... ???) N011 ( 14, 13) [001153] ------------ * JTRUE void N010 ( 12, 11) [000369] J------N---- \--* EQ int N008 ( 10, 9) [000365] n----------- +--* IND long N007 ( 8, 7) [000364] -------N---- | \--* ADD long $324 N005 ( 7, 6) [000362] #----------- | +--* IND long $2ea N004 ( 4, 4) [000361] #----------- | | \--* IND long $2e9 N003 ( 2, 2) [000360] -------N---- | | \--* ADD long $306 N001 ( 1, 1) [000358] ------------ | | +--* LCL_VAR long V24 tmp10 u:1 $2e7 N002 ( 1, 1) [000359] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000363] ------------ | \--* CNS_INT long 32 $24a N009 ( 1, 1) [000368] ------------ \--* CNS_INT long 0 $243 ------------ BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} ***** BB20 STMT00153 (IL ???... ???) N010 ( 14, 12) [001155] -A------R--- * ASG long N009 ( 3, 2) [001154] D------N---- +--* LCL_VAR long V25 tmp11 d:3 N008 ( 10, 9) [000370] n-----?----- \--* IND long N007 ( 8, 7) [000371] ------?N---- \--* ADD long $324 N005 ( 7, 6) [000372] #-----?----- +--* IND long $2ea N004 ( 4, 4) [000373] #-----?----- | \--* IND long $2e9 N003 ( 2, 2) [000374] ------?N---- | \--* ADD long $306 N001 ( 1, 1) [000375] ------?----- | +--* LCL_VAR long V24 tmp10 u:1 (last use) $2e7 N002 ( 1, 1) [000376] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000377] ------?----- \--* CNS_INT long 32 $24a ------------ BB21 [???..???), preds={BB19} succs={BB22} ***** BB21 STMT00154 (IL ???... ???) N007 ( 21, 21) [001157] -AC-G---R--- * ASG long $325 N006 ( 3, 2) [001156] D------N---- +--* LCL_VAR long V25 tmp11 d:2 $325 N005 ( 17, 18) [000367] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $325 N003 ( 1, 1) [000357] ------?----- arg0 in rcx +--* LCL_VAR long V24 tmp10 u:1 (last use) $2e7 N004 ( 2, 10) [000366] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $4f ------------ BB22 [???..106), preds={BB20,BB21} succs={BB23} ***** BB22 STMT00172 (IL ???... ???) N005 ( 0, 0) [001199] -A------R--- * ASG long N004 ( 0, 0) [001197] D------N---- +--* LCL_VAR long V25 tmp11 d:1 N003 ( 0, 0) [001198] ------------ \--* PHI long N001 ( 0, 0) [001243] ------------ pred BB20 +--* PHI_ARG long V25 tmp11 u:3 N002 ( 0, 0) [001242] ------------ pred BB21 \--* PHI_ARG long V25 tmp11 u:2 $325 ***** BB22 STMT00062 (IL ???... ???) N005 ( 17, 8) [000386] -ACXG---R--- * ASG ref $223 N004 ( 1, 1) [000385] D------N---- +--* LCL_VAR ref V12 loc8 d:1 $223 N003 ( 17, 8) [000352] --CXG------- \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default $223 N002 ( 3, 2) [000382] ------------ arg0 in rcx \--* LCL_VAR long V25 tmp11 u:1 (last use) $344 ------------ BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} ***** BB23 STMT00165 (IL ???... ???) N005 ( 0, 0) [001178] -A------R--- * ASG int N004 ( 0, 0) [001176] D------N---- +--* LCL_VAR int V07 loc3 d:5 N003 ( 0, 0) [001177] ------------ \--* PHI int N001 ( 0, 0) [001238] ------------ pred BB27 +--* PHI_ARG int V07 loc3 u:6 N002 ( 0, 0) [001235] ------------ pred BB22 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB23 STMT00164 (IL ???... ???) N005 ( 0, 0) [001175] -A------R--- * ASG int N004 ( 0, 0) [001173] D------N---- +--* LCL_VAR int V09 loc5 d:4 N003 ( 0, 0) [001174] ------------ \--* PHI int N001 ( 0, 0) [001239] ------------ pred BB27 +--* PHI_ARG int V09 loc5 u:5 N002 ( 0, 0) [001236] ------------ pred BB22 \--* PHI_ARG int V09 loc5 u:1 ***** BB23 STMT00063 (IL 0x106...0x10B) N005 ( 7, 7) [000391] ---X-------- * JTRUE void N004 ( 5, 5) [000390] N--X---N-U-- \--* LE int N002 ( 3, 3) [000389] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000388] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000387] ------------ \--* LCL_VAR int V09 loc5 u:4 $3c2 ------------ BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} ***** BB24 STMT00064 (IL 0x110...0x11E) N023 ( 36, 39) [000399] ---XG------- * JTRUE void N022 ( 34, 37) [000398] N--XG--N-U-- \--* NE int N020 ( 32, 35) [000396] *--XG------- +--* IND int N019 ( 30, 33) [000868] ---XG--N---- | \--* ADD byref $28c N017 ( 29, 32) [000879] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000872] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000393] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N003 ( 3, 3) [000871] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000392] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000882] ----G------- | | \--* ADDR byref $82 N015 ( 11, 11) [000394] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000878] -------N---- | | \--* ADD byref $82 N005 ( 1, 1) [000869] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000877] -------N---- | | \--* ADD long $329 N011 ( 8, 8) [000875] -------N---- | | +--* LSH long $328 N009 ( 7, 7) [000881] ------------ | | | +--* MUL long $327 N007 ( 2, 3) [000873] ------------ | | | | +--* CAST long <- int $326 N006 ( 1, 1) [000870] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 $3c2 N008 ( 1, 1) [000880] ------------ | | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000874] -------N---- | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000876] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000867] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N021 ( 1, 1) [000397] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 ------------ BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} ***** BB25 STMT00069 (IL 0x120...0x135) N035 ( 67, 59) [000428] --CXG------- * JTRUE void N034 ( 65, 57) [000427] J-CXG--N---- \--* NE int $1bd N032 ( 63, 55) [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals $581 N031 ( 9, 8) [000908] n--X-------- control expr | \--* IND long N030 ( 7, 6) [000907] ---X---N---- | \--* ADD long $32e N028 ( 6, 5) [000905] #--X-------- | +--* IND long $465 N027 ( 4, 3) [000904] ---X---N---- | | \--* ADD long $32c N025 ( 3, 2) [000902] #--X-------- | | +--* IND long $463 N024 ( 1, 1) [000901] ------------ | | | \--* LCL_VAR ref V12 loc8 u:1 $223 N026 ( 1, 1) [000903] ------------ | | \--* CNS_INT int 72 $c9 N029 ( 1, 1) [000906] ------------ | \--* CNS_INT int 32 $d2 N021 ( 32, 34) [000893] ---XG------- arg1 in rdx | +--* COMMA ref N007 ( 8, 11) [000886] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N004 ( 1, 1) [000420] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N006 ( 3, 3) [000885] ---X-------- | | | \--* ARR_LENGTH int N005 ( 1, 1) [000419] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N020 ( 24, 23) [000897] *---G------- | | \--* IND ref N019 ( 21, 21) [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] $84 N018 ( 11, 11) [000421] a---G--N---- | | \--* IND struct N017 ( 10, 10) [000892] -------N---- | | \--* ADD byref $82 N008 ( 1, 1) [000883] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N016 ( 9, 9) [000891] -------N---- | | \--* ADD long $329 N014 ( 8, 8) [000889] -------N---- | | +--* LSH long $328 N012 ( 7, 7) [000895] ------------ | | | +--* MUL long $327 N010 ( 2, 3) [000887] ------------ | | | | +--* CAST long <- int $326 N009 ( 1, 1) [000884] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 $3c2 N011 ( 1, 1) [000894] ------------ | | | | \--* CNS_INT long 3 $24b N013 ( 1, 1) [000888] -------N---- | | | \--* CNS_INT long 3 $24b N015 ( 1, 1) [000890] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N022 ( 1, 1) [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 u:1 $223 N023 ( 1, 1) [000424] ------------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 u:1 $101 N033 ( 1, 1) [000426] ------------ \--* CNS_INT int 0 $c0 ------------ BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} ***** BB26 STMT00065 (IL 0x157...0x164) N022 ( 32, 35) [000406] -A-XG---R--- * ASG int N021 ( 1, 1) [000405] D------N---- +--* LCL_VAR int V09 loc5 d:5 N020 ( 32, 35) [000404] *--XG------- \--* IND int N019 ( 30, 33) [000932] ---XG--N---- \--* ADD byref $28e N017 ( 29, 32) [000943] ---XG------- +--* COMMA byref N004 ( 8, 11) [000936] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000401] ------------ | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N003 ( 3, 3) [000935] ---X-------- | | \--* ARR_LENGTH int N002 ( 1, 1) [000400] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000946] ----G------- | \--* ADDR byref $82 N015 ( 11, 11) [000402] a---G--N---- | \--* IND struct N014 ( 10, 10) [000942] -------N---- | \--* ADD byref $82 N005 ( 1, 1) [000933] ------------ | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000941] -------N---- | \--* ADD long $329 N011 ( 8, 8) [000939] -------N---- | +--* LSH long $328 N009 ( 7, 7) [000945] ------------ | | +--* MUL long $327 N007 ( 2, 3) [000937] ------------ | | | +--* CAST long <- int $326 N006 ( 1, 1) [000934] i----------- | | | | \--* LCL_VAR int V09 loc5 u:4 (last use) $3c2 N008 ( 1, 1) [000944] ------------ | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000938] -------N---- | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000940] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000931] ------------ \--* CNS_INT long 20 field offset Fseq[next] $24c ***** BB26 STMT00066 (IL 0x166...0x169) N005 ( 3, 3) [000411] -A------R--- * ASG int $605 N004 ( 1, 1) [000410] D------N---- +--* LCL_VAR int V07 loc3 d:6 $605 N003 ( 3, 3) [000409] ------------ \--* ADD int $605 N001 ( 1, 1) [000407] ------------ +--* LCL_VAR int V07 loc3 u:5 (last use) $3c1 N002 ( 1, 1) [000408] ------------ \--* CNS_INT int 1 $c1 ***** BB26 STMT00067 (IL 0x16A...0x16E) N005 ( 7, 7) [000416] ---X-------- * JTRUE void N004 ( 5, 5) [000415] N--X---N-U-- \--* LT int N002 ( 3, 3) [000414] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000413] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000412] ------------ \--* LCL_VAR int V07 loc3 u:6 $605 ------------ BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} ------------ BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} ***** BB28 STMT00070 (IL 0x137...0x139) N005 ( 7, 8) [000432] ------------ * JTRUE void N004 ( 5, 6) [000431] N------N-U-- \--* NE int $1bf N002 ( 3, 4) [000909] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000429] ------------ | \--* LCL_VAR int V03 arg3 u:1 $140 N003 ( 1, 1) [000430] ------------ \--* CNS_INT int 1 $c1 ------------ BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} ***** BB29 STMT00077 (IL 0x13B...0x144) N022 ( 34, 37) [000481] -A-XG------- * ASG ref $VN.Void N020 ( 32, 35) [000480] *--XG--N---- +--* IND ref $102 N019 ( 30, 33) [000911] ---XG--N---- | \--* ADD byref $28d N017 ( 29, 32) [000922] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000915] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000476] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N003 ( 3, 3) [000914] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000475] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000925] ----G------- | | \--* ADDR byref $82 N015 ( 11, 11) [000477] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000921] -------N---- | | \--* ADD byref $82 N005 ( 1, 1) [000912] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 (last use) N013 ( 9, 9) [000920] -------N---- | | \--* ADD long $329 N011 ( 8, 8) [000918] -------N---- | | +--* LSH long $328 N009 ( 7, 7) [000924] ------------ | | | +--* MUL long $327 N007 ( 2, 3) [000916] ------------ | | | | +--* CAST long <- int $326 N006 ( 1, 1) [000913] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 (last use) $3c2 N008 ( 1, 1) [000923] ------------ | | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000917] -------N---- | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000919] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000910] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N021 ( 1, 1) [000479] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 ------------ BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} ***** BB30 STMT00071 (IL 0x14B...0x14D) N005 ( 7, 8) [000436] ------------ * JTRUE void N004 ( 5, 6) [000435] N------N-U-- \--* EQ int $600 N002 ( 3, 4) [000926] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000433] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) $140 N003 ( 1, 1) [000434] ------------ \--* CNS_INT int 2 $c2 ------------ BB31 [???..???) (return), preds={BB30,BB41} succs={} ***** BB31 STMT00148 (IL ???... ???) N002 ( 2, 2) [000811] ------------ * RETURN int $1f3 N001 ( 1, 1) [000437] ------------ \--* CNS_INT int 0 $c0 ------------ BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} ***** BB32 STMT00175 (IL ???... ???) N005 ( 0, 0) [001208] -A------R--- * ASG int N004 ( 0, 0) [001206] D------N---- +--* LCL_VAR int V07 loc3 d:3 N003 ( 0, 0) [001207] ------------ \--* PHI int N001 ( 0, 0) [001229] ------------ pred BB43 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [001218] ------------ pred BB18 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB32 STMT00174 (IL ???... ???) N005 ( 0, 0) [001205] -A------R--- * ASG int N004 ( 0, 0) [001203] D------N---- +--* LCL_VAR int V09 loc5 d:2 N003 ( 0, 0) [001204] ------------ \--* PHI int N001 ( 0, 0) [001230] ------------ pred BB43 +--* PHI_ARG int V09 loc5 u:3 N002 ( 0, 0) [001219] ------------ pred BB18 \--* PHI_ARG int V09 loc5 u:1 ***** BB32 STMT00014 (IL 0x177...0x17C) N005 ( 7, 7) [000066] ---X-------- * JTRUE void N004 ( 5, 5) [000065] N--X---N-U-- \--* LE int N002 ( 3, 3) [000064] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000063] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000062] ------------ \--* LCL_VAR int V09 loc5 u:2 $3c4 ------------ BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} ***** BB33 STMT00039 (IL 0x17E...0x18C) N023 ( 36, 39) [000215] ---XG------- * JTRUE void N022 ( 34, 37) [000214] N--XG--N-U-- \--* NE int N020 ( 32, 35) [000212] *--XG------- +--* IND int N019 ( 30, 33) [000948] ---XG--N---- | \--* ADD byref $2ac N017 ( 29, 32) [000959] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000952] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000209] ------------ | | | +--* LCL_VAR int V09 loc5 u:2 $3c4 N003 ( 3, 3) [000951] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000208] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000962] ----G------- | | \--* ADDR byref $91 N015 ( 11, 11) [000210] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000958] -------N---- | | \--* ADD byref $91 N005 ( 1, 1) [000949] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000957] -------N---- | | \--* ADD long $6e4 N011 ( 8, 8) [000955] -------N---- | | +--* LSH long $6e3 N009 ( 7, 7) [000961] ------------ | | | +--* MUL long $6e2 N007 ( 2, 3) [000953] ------------ | | | | +--* CAST long <- int $6e1 N006 ( 1, 1) [000950] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:2 $3c4 N008 ( 1, 1) [000960] ------------ | | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000954] -------N---- | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000956] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000947] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N021 ( 1, 1) [000213] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 ------------ BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} ***** BB34 STMT00045 (IL 0x18E...0x1A2) N020 ( 32, 34) [000246] -A-XG---R--- * ASG ref N019 ( 1, 1) [000245] D------N---- +--* LCL_VAR ref V17 tmp3 d:1 N018 ( 32, 34) [000973] ---XG------- \--* COMMA ref N004 ( 8, 11) [000966] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000236] ------------ | +--* LCL_VAR int V09 loc5 u:2 $3c4 N003 ( 3, 3) [000965] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000235] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N017 ( 24, 23) [000977] *---G------- \--* IND ref N016 ( 21, 21) [000976] ----G------- \--* ADDR byref Zero Fseq[key] $93 N015 ( 11, 11) [000237] a---G--N---- \--* IND struct N014 ( 10, 10) [000972] -------N---- \--* ADD byref $91 N005 ( 1, 1) [000963] ------------ +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000971] -------N---- \--* ADD long $6e4 N011 ( 8, 8) [000969] -------N---- +--* LSH long $6e3 N009 ( 7, 7) [000975] ------------ | +--* MUL long $6e2 N007 ( 2, 3) [000967] ------------ | | +--* CAST long <- int $6e1 N006 ( 1, 1) [000964] i----------- | | | \--* LCL_VAR int V09 loc5 u:2 $3c4 N008 ( 1, 1) [000974] ------------ | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000968] -------N---- | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000970] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB34 STMT00044 (IL 0x18E... ???) N004 ( 3, 3) [000244] -A-X----R--- * ASG long $2e8 N003 ( 1, 1) [000243] D------N---- +--* LCL_VAR long V16 tmp2 d:1 $2e7 N002 ( 3, 2) [000242] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000241] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB34 STMT00158 (IL ???... ???) N011 ( 14, 13) [001163] ------------ * JTRUE void N010 ( 12, 11) [000263] J------N---- \--* EQ int N008 ( 10, 9) [000259] n----------- +--* IND long N007 ( 8, 7) [000255] -------N---- | \--* ADD long $6e6 N005 ( 7, 6) [000253] #----------- | +--* IND long $2ea N004 ( 4, 4) [000252] #----------- | | \--* IND long $2e9 N003 ( 2, 2) [000251] -------N---- | | \--* ADD long $306 N001 ( 1, 1) [000249] ------------ | | +--* LCL_VAR long V16 tmp2 u:1 $2e7 N002 ( 1, 1) [000250] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000254] ------------ | \--* CNS_INT long 48 $246 N009 ( 1, 1) [000262] ------------ \--* CNS_INT long 0 $243 ------------ BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} ***** BB35 STMT00159 (IL ???... ???) N010 ( 10, 9) [001165] -A------R--- * ASG long N009 ( 1, 1) [001164] D------N---- +--* LCL_VAR long V19 tmp5 d:3 N008 ( 10, 9) [000264] n-----?----- \--* IND long N007 ( 8, 7) [000265] ------?N---- \--* ADD long $6e6 N005 ( 7, 6) [000266] #-----?----- +--* IND long $2ea N004 ( 4, 4) [000267] #-----?----- | \--* IND long $2e9 N003 ( 2, 2) [000268] ------?N---- | \--* ADD long $306 N001 ( 1, 1) [000269] ------?----- | +--* LCL_VAR long V16 tmp2 u:1 (last use) $2e7 N002 ( 1, 1) [000270] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000271] ------?----- \--* CNS_INT long 48 $246 ------------ BB36 [???..???), preds={BB34} succs={BB37} ***** BB36 STMT00160 (IL ???... ???) N007 ( 17, 18) [001167] -AC-G---R--- * ASG long $6e7 N006 ( 1, 1) [001166] D------N---- +--* LCL_VAR long V19 tmp5 d:2 $6e7 N005 ( 17, 18) [000261] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $6e7 N003 ( 1, 1) [000248] ------?----- arg0 in rcx +--* LCL_VAR long V16 tmp2 u:1 (last use) $2e7 N004 ( 2, 10) [000260] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $63 ------------ BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} ***** BB37 STMT00176 (IL ???... ???) N005 ( 0, 0) [001211] -A------R--- * ASG long N004 ( 0, 0) [001209] D------N---- +--* LCL_VAR long V19 tmp5 d:1 N003 ( 0, 0) [001210] ------------ \--* PHI long N001 ( 0, 0) [001234] ------------ pred BB35 +--* PHI_ARG long V19 tmp5 u:3 N002 ( 0, 0) [001233] ------------ pred BB36 \--* PHI_ARG long V19 tmp5 u:2 $6e7 ***** BB37 STMT00049 (IL ???... ???) N013 ( 32, 18) [000283] --CXG------- * JTRUE void N012 ( 30, 16) [000282] J-CXG--N---- \--* EQ int $817 N010 ( 28, 14) [000280] --CXG------- +--* CALL ind stub int $1ef N009 ( 1, 1) [000279] ------------ calli tgt | \--* LCL_VAR long V19 tmp5 u:1 (last use) $349 N005 ( 1, 1) [000234] ------------ this in rcx | +--* LCL_VAR ref V05 loc1 u:1 N006 ( 1, 1) [000980] ------------ arg1 in r11 | +--* LCL_VAR long V19 tmp5 u:1 r11 REG r11 $349 N007 ( 1, 1) [000247] ------------ arg2 in rdx | +--* LCL_VAR ref V17 tmp3 u:1 (last use) N008 ( 1, 1) [000258] ------------ arg3 in r8 | \--* LCL_VAR ref V01 arg1 u:1 $101 N011 ( 1, 1) [000281] ------------ \--* CNS_INT int 0 $c0 ------------ BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} ***** BB38 STMT00050 (IL 0x1A4...0x1A6) N005 ( 7, 8) [000287] ------------ * JTRUE void N004 ( 5, 6) [000286] N------N-U-- \--* NE int $1bf N002 ( 3, 4) [000985] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000284] ------------ | \--* LCL_VAR int V03 arg3 u:1 $140 N003 ( 1, 1) [000285] ------------ \--* CNS_INT int 1 $c1 ------------ BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} ***** BB39 STMT00057 (IL 0x1A8...0x1B1) N022 ( 34, 37) [000336] -A-XG------- * ASG ref $VN.Void N020 ( 32, 35) [000335] *--XG--N---- +--* IND ref $102 N019 ( 30, 33) [000987] ---XG--N---- | \--* ADD byref $2ae N017 ( 29, 32) [000998] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000991] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000331] ------------ | | | +--* LCL_VAR int V09 loc5 u:2 $3c4 N003 ( 3, 3) [000990] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000330] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [001001] ----G------- | | \--* ADDR byref $91 N015 ( 11, 11) [000332] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000997] -------N---- | | \--* ADD byref $91 N005 ( 1, 1) [000988] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 (last use) N013 ( 9, 9) [000996] -------N---- | | \--* ADD long $6e4 N011 ( 8, 8) [000994] -------N---- | | +--* LSH long $6e3 N009 ( 7, 7) [001000] ------------ | | | +--* MUL long $6e2 N007 ( 2, 3) [000992] ------------ | | | | +--* CAST long <- int $6e1 N006 ( 1, 1) [000989] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:2 (last use) $3c4 N008 ( 1, 1) [000999] ------------ | | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000993] -------N---- | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000995] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000986] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N021 ( 1, 1) [000334] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 ------------ BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} ***** BB40 STMT00051 (IL 0x1B8...0x1BA) N005 ( 7, 8) [000291] ------------ * JTRUE void N004 ( 5, 6) [000290] N------N-U-- \--* EQ int $600 N002 ( 3, 4) [001002] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000288] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) $140 N003 ( 1, 1) [000289] ------------ \--* CNS_INT int 2 $c2 ------------ BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} ------------ BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} ***** BB42 STMT00040 (IL 0x1C4...0x1D1) N022 ( 32, 35) [000222] -A-XG---R--- * ASG int N021 ( 1, 1) [000221] D------N---- +--* LCL_VAR int V09 loc5 d:3 N020 ( 32, 35) [000220] *--XG------- \--* IND int N019 ( 30, 33) [001009] ---XG--N---- \--* ADD byref $2ad N017 ( 29, 32) [001020] ---XG------- +--* COMMA byref N004 ( 8, 11) [001013] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000217] ------------ | | +--* LCL_VAR int V09 loc5 u:2 $3c4 N003 ( 3, 3) [001012] ---X-------- | | \--* ARR_LENGTH int N002 ( 1, 1) [000216] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [001023] ----G------- | \--* ADDR byref $91 N015 ( 11, 11) [000218] a---G--N---- | \--* IND struct N014 ( 10, 10) [001019] -------N---- | \--* ADD byref $91 N005 ( 1, 1) [001010] ------------ | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [001018] -------N---- | \--* ADD long $6e4 N011 ( 8, 8) [001016] -------N---- | +--* LSH long $6e3 N009 ( 7, 7) [001022] ------------ | | +--* MUL long $6e2 N007 ( 2, 3) [001014] ------------ | | | +--* CAST long <- int $6e1 N006 ( 1, 1) [001011] i----------- | | | | \--* LCL_VAR int V09 loc5 u:2 (last use) $3c4 N008 ( 1, 1) [001021] ------------ | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [001015] -------N---- | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [001017] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [001008] ------------ \--* CNS_INT long 20 field offset Fseq[next] $24c ***** BB42 STMT00041 (IL 0x1D3...0x1D6) N005 ( 3, 3) [000227] -A------R--- * ASG int $81a N004 ( 1, 1) [000226] D------N---- +--* LCL_VAR int V07 loc3 d:4 $81a N003 ( 3, 3) [000225] ------------ \--* ADD int $81a N001 ( 1, 1) [000223] ------------ +--* LCL_VAR int V07 loc3 u:3 (last use) $3c3 N002 ( 1, 1) [000224] ------------ \--* CNS_INT int 1 $c1 ***** BB42 STMT00042 (IL 0x1D7...0x1DB) N005 ( 7, 7) [000232] ---X-------- * JTRUE void N004 ( 5, 5) [000231] N--X---N-U-- \--* LT int N002 ( 3, 3) [000230] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000229] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000228] ------------ \--* LCL_VAR int V07 loc3 u:4 $81a ------------ BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} ------------ BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} ***** BB44 STMT00166 (IL ???... ???) N005 ( 0, 0) [001181] -A------R--- * ASG int N004 ( 0, 0) [001179] D------N---- +--* LCL_VAR int V07 loc3 d:2 N003 ( 0, 0) [001180] ------------ \--* PHI int N001 ( 0, 0) [001237] ------------ pred BB23 +--* PHI_ARG int V07 loc3 u:5 $3c1 N002 ( 0, 0) [001228] ------------ pred BB32 \--* PHI_ARG int V07 loc3 u:3 $3c3 ***** BB44 STMT00015 (IL 0x1E4...0x1EB) N007 ( 8, 8) [000071] ---XG------- * JTRUE void N006 ( 6, 6) [000070] J--XG--N---- \--* LE int N004 ( 4, 4) [000068] ---XG------- +--* IND int N003 ( 2, 2) [001025] -------N---- | \--* ADD byref $28f N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001024] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N005 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 $c0 ------------ BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} ***** BB45 STMT00035 (IL 0x1ED...0x1F3) N006 ( 8, 7) [000174] -A-XG---R--- * ASG int N005 ( 3, 2) [000173] D------N---- +--* LCL_VAR int V10 loc6 d:3 N004 ( 4, 4) [000172] ---XG------- \--* IND int N003 ( 2, 2) [001027] -------N---- \--* ADD byref $295 N001 ( 1, 1) [000171] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001026] ------------ \--* CNS_INT long 60 field offset Fseq[_freeList] $24d ***** BB45 STMT00120 (IL 0x1F5... ???) N034 ( 48, 47) [000688] -A-XG---R--- * ASG bool N033 ( 3, 2) [000687] D------N---- +--* LCL_VAR int V49 tmp35 d:1 N032 ( 44, 44) [000184] -A-XG------- \--* GE int N030 ( 39, 42) [000182] -A-XG------- +--* ADD int N028 ( 37, 40) [001050] -A-XG------- | +--* NEG int N027 ( 36, 39) [000181] *A-XG------- | | \--* IND int N026 ( 34, 37) [001029] -A-XG--N---- | | \--* ADD byref $29c N024 ( 33, 36) [001044] -A-XG------- | | +--* COMMA byref N006 ( 4, 4) [001032] -A-XG---R--- | | | +--* ASG int N005 ( 1, 1) [001031] D------N---- | | | | +--* LCL_VAR int V62 tmp48 d:1 N004 ( 4, 4) [000178] ---XG------- | | | | \--* IND int N003 ( 2, 2) [001046] -------N---- | | | | \--* ADD byref $295 N001 ( 1, 1) [000177] ------------ | | | | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001045] ------------ | | | | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N023 ( 29, 32) [001043] ---XG------- | | | \--* COMMA byref N010 ( 8, 11) [001036] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [001033] ------------ | | | | +--* LCL_VAR int V62 tmp48 u:1 N009 ( 3, 3) [001035] ---X-------- | | | | \--* ARR_LENGTH int N008 ( 1, 1) [000176] ------------ | | | | \--* LCL_VAR ref V04 loc0 u:1 N022 ( 21, 21) [001049] ----G------- | | | \--* ADDR byref $88 N021 ( 11, 11) [000179] a---G--N---- | | | \--* IND struct N020 ( 10, 10) [001042] -------N---- | | | \--* ADD byref $88 N011 ( 1, 1) [001030] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N019 ( 9, 9) [001041] -------N---- | | | \--* ADD long N017 ( 8, 8) [001039] -------N---- | | | +--* LSH long N015 ( 7, 7) [001048] ------------ | | | | +--* MUL long N013 ( 2, 3) [001037] ------------ | | | | | +--* CAST long <- int N012 ( 1, 1) [001034] i----------- | | | | | | \--* LCL_VAR int V62 tmp48 u:1 (last use) N014 ( 1, 1) [001047] ------------ | | | | | \--* CNS_INT long 3 $24b N016 ( 1, 1) [001038] -------N---- | | | | \--* CNS_INT long 3 $24b N018 ( 1, 1) [001040] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N025 ( 1, 1) [001028] ------------ | | \--* CNS_INT long 20 field offset Fseq[next] $24c N029 ( 1, 1) [000175] ------------ | \--* CNS_INT int -3 $e1 N031 ( 1, 1) [000183] ------------ \--* CNS_INT int -1 $c4 ***** BB45 STMT00123 (IL 0x1F5... ???) N004 ( 8, 15) [000698] -A--G---R--- * ASG ref $105 N003 ( 3, 2) [000697] D------N---- +--* LCL_VAR ref V50 tmp36 d:1 $105 N002 ( 4, 12) [000684] #---G------- \--* IND ref $105 N001 ( 2, 10) [000683] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB45 STMT00121 (IL 0x1F5... ???) N004 ( 7, 6) [000693] ------------ * JTRUE void N003 ( 5, 4) [000692] J------N---- \--* NE int N001 ( 3, 2) [000690] ------------ +--* LCL_VAR int V49 tmp35 u:1 (last use) N002 ( 1, 1) [000691] ------------ \--* CNS_INT int 0 $c0 ------------ BB46 [1F5..1F6), preds={BB45} succs={BB47} ***** BB46 STMT00122 (IL 0x1F5... ???) N006 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N004 ( 4, 12) [001052] #---G------- arg0 in rcx +--* IND ref $114 N003 ( 2, 10) [001051] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" $5e N005 ( 3, 2) [000695] ------------ arg1 in rdx \--* LCL_VAR ref V50 tmp36 u:1 (last use) $105 ------------ BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} ***** BB47 STMT00037 (IL 0x219... ???) N035 ( 44, 47) [000200] -A-XG------- * ASG int $VN.Void N004 ( 4, 4) [000199] D--XG--N---- +--* IND int $732 N003 ( 2, 2) [001056] -------N---- | \--* ADD byref $295 N001 ( 1, 1) [000190] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001055] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N034 ( 39, 42) [000198] -A-XG------- \--* ADD int N032 ( 37, 40) [001079] -A-XG------- +--* NEG int N031 ( 36, 39) [000197] *A-XG------- | \--* IND int N030 ( 34, 37) [001058] -A-XG--N---- | \--* ADD byref $2a3 N028 ( 33, 36) [001073] -A-XG------- | +--* COMMA byref N010 ( 4, 4) [001061] -A-XG---R--- | | +--* ASG int N009 ( 1, 1) [001060] D------N---- | | | +--* LCL_VAR int V63 tmp49 d:1 N008 ( 4, 4) [000194] ---XG------- | | | \--* IND int N007 ( 2, 2) [001075] -------N---- | | | \--* ADD byref $295 N005 ( 1, 1) [000193] ------------ | | | +--* LCL_VAR ref V00 this u:1 $100 N006 ( 1, 1) [001074] ------------ | | | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N027 ( 29, 32) [001072] ---XG------- | | \--* COMMA byref N014 ( 8, 11) [001065] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N011 ( 1, 1) [001062] ------------ | | | +--* LCL_VAR int V63 tmp49 u:1 N013 ( 3, 3) [001064] ---X-------- | | | \--* ARR_LENGTH int N012 ( 1, 1) [000192] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N026 ( 21, 21) [001078] ----G------- | | \--* ADDR byref $8a N025 ( 11, 11) [000195] a---G--N---- | | \--* IND struct N024 ( 10, 10) [001071] -------N---- | | \--* ADD byref $8a N015 ( 1, 1) [001059] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N023 ( 9, 9) [001070] -------N---- | | \--* ADD long N021 ( 8, 8) [001068] -------N---- | | +--* LSH long N019 ( 7, 7) [001077] ------------ | | | +--* MUL long N017 ( 2, 3) [001066] ------------ | | | | +--* CAST long <- int N016 ( 1, 1) [001063] i----------- | | | | | \--* LCL_VAR int V63 tmp49 u:1 (last use) N018 ( 1, 1) [001076] ------------ | | | | \--* CNS_INT long 3 $24b N020 ( 1, 1) [001067] -------N---- | | | \--* CNS_INT long 3 $24b N022 ( 1, 1) [001069] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N029 ( 1, 1) [001057] ------------ | \--* CNS_INT long 20 field offset Fseq[next] $24c N033 ( 1, 1) [000191] ------------ \--* CNS_INT int -3 $e1 ***** BB47 STMT00038 (IL 0x233...0x23C) N011 ( 11, 11) [000207] -A-XG---R--- * ASG int $VN.Void N010 ( 4, 4) [000206] D--XG--N---- +--* IND int $73a N009 ( 2, 2) [001081] -------N---- | \--* ADD byref $28f N007 ( 1, 1) [000201] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001080] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N006 ( 6, 6) [000205] ---XG------- \--* ADD int N004 ( 4, 4) [000203] ---XG------- +--* IND int N003 ( 2, 2) [001083] -------N---- | \--* ADD byref $28f N001 ( 1, 1) [000202] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001082] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N005 ( 1, 1) [000204] ------------ \--* CNS_INT int -1 $c4 ------------ BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} ***** BB48 STMT00016 (IL 0x243...0x249) N006 ( 8, 7) [000075] -A-XG---R--- * ASG int N005 ( 3, 2) [000074] D------N---- +--* LCL_VAR int V13 loc9 d:1 N004 ( 4, 4) [000073] ---XG------- \--* IND int N003 ( 2, 2) [001085] -------N---- \--* ADD byref $290 N001 ( 1, 1) [000072] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001084] ------------ \--* CNS_INT long 56 field offset Fseq[_count] $244 ***** BB48 STMT00017 (IL 0x24B...0x250) N005 ( 9, 8) [000080] ---X-------- * JTRUE void N004 ( 7, 6) [000079] N--X---N-U-- \--* NE int N002 ( 3, 3) [000078] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000077] ------------ | \--* LCL_VAR ref V04 loc0 u:1 (last use) N003 ( 3, 2) [000076] ------------ \--* LCL_VAR int V13 loc9 u:1 ------------ BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00125 (IL 0x252... ???) N014 ( 44, 26) [000705] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void N009 ( 22, 13) [001090] -ACXG---R-L- arg1 SETUP +--* ASG int $1d7 N008 ( 3, 2) [001089] D------N---- | +--* LCL_VAR int V64 tmp50 d:1 $1d7 N007 ( 18, 10) [000702] --CXG------- | \--* CALL int System.Collections.HashHelpers.ExpandPrime $1d7 N006 ( 4, 4) [000701] ---XG------- arg0 in rcx | \--* IND int N005 ( 2, 2) [001087] -------N---- | \--* ADD byref $290 N003 ( 1, 1) [000700] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N004 ( 1, 1) [001086] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] $244 N011 ( 3, 2) [001091] ------------ arg1 in rdx +--* LCL_VAR int V64 tmp50 u:1 (last use) $1d7 N012 ( 1, 1) [000163] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N013 ( 1, 1) [000704] ------------ arg2 in r8 \--* CNS_INT int 0 $c0 ***** BB49 STMT00126 (IL 0x258... ???) N006 ( 8, 7) [000711] -A-XG---R--- * ASG ref N005 ( 3, 2) [000710] D------N---- +--* LCL_VAR ref V52 tmp38 d:1 N004 ( 4, 4) [000709] ---XG------- \--* IND ref N003 ( 2, 2) [001095] -------N---- \--* ADD byref $280 N001 ( 1, 1) [000165] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001094] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] $240 ***** BB49 STMT00133 (IL 0x258... ???) N004 ( 5, 4) [000760] -A-X----R--- * ASG int N003 ( 1, 1) [000759] D------N---- +--* LCL_VAR int V53 tmp39 d:1 N002 ( 5, 4) [000714] ---X-------- \--* ARR_LENGTH int N001 ( 3, 2) [000713] ------------ \--* LCL_VAR ref V52 tmp38 u:1 ***** BB49 STMT00134 (IL 0x258... ???) N006 ( 8, 7) [000762] -A-XG---R--- * ASG long N005 ( 3, 2) [000761] D------N---- +--* LCL_VAR long V54 tmp40 d:1 N004 ( 4, 4) [000716] ---XG------- \--* IND long N003 ( 2, 2) [001097] -------N---- \--* ADD byref $283 N001 ( 1, 1) [000715] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001096] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 ***** BB49 STMT00136 (IL 0x258... ???) N005 ( 10, 9) [000773] -A------R--- * ASG bool N004 ( 3, 2) [000772] D------N---- +--* LCL_VAR int V56 tmp42 d:1 N003 ( 6, 6) [000730] N--------U-- \--* LE int N001 ( 1, 1) [000728] ------------ +--* LCL_VAR int V53 tmp39 u:1 N002 ( 1, 4) [000729] ------------ \--* CNS_INT int 0x7FFFFFFF $ce ***** BB49 STMT00139 (IL 0x258... ???) N004 ( 8, 15) [000783] -A--G---R--- * ASG ref $105 N003 ( 3, 2) [000782] D------N---- +--* LCL_VAR ref V57 tmp43 d:1 $105 N002 ( 4, 12) [000767] #---G------- \--* IND ref $105 N001 ( 2, 10) [000766] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB49 STMT00140 (IL 0x258... ???) N004 ( 8, 15) [000785] -A--G---R--- * ASG ref $105 N003 ( 3, 2) [000784] D------N---- +--* LCL_VAR ref V58 tmp44 d:1 $105 N002 ( 4, 12) [000769] #---G------- \--* IND ref $105 N001 ( 2, 10) [000768] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB49 STMT00137 (IL 0x258... ???) N004 ( 7, 6) [000778] ------------ * JTRUE void N003 ( 5, 4) [000777] J------N---- \--* NE int N001 ( 3, 2) [000775] ------------ +--* LCL_VAR int V56 tmp42 u:1 (last use) N002 ( 1, 1) [000776] ------------ \--* CNS_INT int 0 $c0 ------------ BB50 [258..259), preds={BB49} succs={BB51} ***** BB50 STMT00138 (IL 0x258... ???) N005 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 3, 2) [000779] ------------ arg0 in rcx +--* LCL_VAR ref V58 tmp44 u:1 (last use) $105 N004 ( 3, 2) [000780] ------------ arg1 in rdx \--* LCL_VAR ref V58 tmp44 u:1 (last use) $105 ------------ BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00131 (IL 0x258... ???) N016 ( 26, 25) [000750] -A------R--- * ASG int N015 ( 3, 2) [000749] D------N---- +--* LCL_VAR int V55 tmp41 d:1 N014 ( 22, 22) [000748] ------------ \--* CAST int <- uint <- long N013 ( 21, 20) [000747] ------------ \--* RSZ long N011 ( 19, 18) [000745] ------------ +--* MUL long N008 ( 13, 12) [000742] ------------ | +--* ADD long N006 ( 11, 10) [000739] ------------ | | +--* RSZ long N004 ( 9, 8) [000737] ------------ | | | +--* MUL long N001 ( 3, 2) [000735] ------------ | | | | +--* LCL_VAR long V54 tmp40 u:1 (last use) N003 ( 2, 3) [000736] ---------U-- | | | | \--* CAST long <- ulong <- uint $310 N002 ( 1, 1) [000166] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 $3c0 N005 ( 1, 1) [000738] ------------ | | | \--* CNS_INT int 32 $d2 N007 ( 1, 1) [000741] ------------ | | \--* CNS_INT long 1 $247 N010 ( 2, 3) [000744] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000743] ------------ | \--* LCL_VAR int V53 tmp39 u:1 N012 ( 1, 1) [000746] ------------ \--* CNS_INT int 32 $d2 ***** BB51 STMT00142 (IL 0x258... ???) N007 ( 33, 11) [000796] -A-X----R--- * ASG bool N006 ( 3, 2) [000795] D------N---- +--* LCL_VAR int V59 tmp45 d:1 N005 ( 29, 8) [000755] ---X-------- \--* EQ int N003 ( 22, 5) [000754] ---X-------- +--* UMOD int N001 ( 1, 1) [000752] ------------ | +--* LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000753] ------------ | \--* LCL_VAR int V53 tmp39 u:1 (last use) N004 ( 3, 2) [000751] ------------ \--* LCL_VAR int V55 tmp41 u:1 ***** BB51 STMT00145 (IL 0x258... ???) N004 ( 8, 15) [000806] -A--G---R--- * ASG ref $105 N003 ( 3, 2) [000805] D------N---- +--* LCL_VAR ref V60 tmp46 d:1 $105 N002 ( 4, 12) [000790] #---G------- \--* IND ref $105 N001 ( 2, 10) [000789] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB51 STMT00146 (IL 0x258... ???) N004 ( 8, 15) [000808] -A--G---R--- * ASG ref $105 N003 ( 3, 2) [000807] D------N---- +--* LCL_VAR ref V61 tmp47 d:1 $105 N002 ( 4, 12) [000792] #---G------- \--* IND ref $105 N001 ( 2, 10) [000791] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB51 STMT00143 (IL 0x258... ???) N004 ( 7, 6) [000801] ------------ * JTRUE void N003 ( 5, 4) [000800] J------N---- \--* NE int N001 ( 3, 2) [000798] ------------ +--* LCL_VAR int V59 tmp45 u:1 (last use) N002 ( 1, 1) [000799] ------------ \--* CNS_INT int 0 $c0 ------------ BB52 [258..259), preds={BB51} succs={BB53} ***** BB52 STMT00144 (IL 0x258... ???) N005 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 3, 2) [000802] ------------ arg0 in rcx +--* LCL_VAR ref V61 tmp47 u:1 (last use) $105 N004 ( 3, 2) [000803] ------------ arg1 in rdx \--* LCL_VAR ref V61 tmp47 u:1 (last use) $105 ------------ BB53 [258..259), preds={BB51,BB52} succs={BB54} ***** BB53 STMT00128 (IL 0x258... ???) N017 ( 35, 33) [000722] -A-XG---R--- * ASG byref N016 ( 3, 2) [000721] D------N---- +--* LCL_VAR byref V51 tmp37 d:1 $87 N015 ( 31, 30) [001112] ---XG------- \--* COMMA byref N004 ( 12, 13) [001105] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 3, 2) [000758] ------------ | +--* LCL_VAR int V55 tmp41 u:1 N003 ( 5, 4) [001104] ---X-------- | \--* ARR_LENGTH int N002 ( 3, 2) [000712] ------------ | \--* LCL_VAR ref V52 tmp38 u:1 N014 ( 19, 17) [001113] ----G------- \--* ADDR byref $87 N013 ( 10, 9) [000719] a---G--N---- \--* IND int N012 ( 9, 8) [001111] -------N---- \--* ADD byref $87 N005 ( 3, 2) [001102] ------------ +--* LCL_VAR ref V52 tmp38 u:1 (last use) N011 ( 6, 6) [001110] -------N---- \--* ADD long N009 ( 5, 5) [001108] -------N---- +--* LSH long N007 ( 4, 4) [001106] ------------ | +--* CAST long <- int N006 ( 3, 2) [001103] i----------- | | \--* LCL_VAR int V55 tmp41 u:1 (last use) N008 ( 1, 1) [001107] -------N---- | \--* CNS_INT long 2 $248 N010 ( 1, 1) [001109] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB53 STMT00034 (IL ???... ???) N003 ( 7, 5) [000170] -A------R--- * ASG byref $87 N002 ( 3, 2) [000169] D------N---- +--* LCL_VAR byref V08 loc4 d:4 $87 N001 ( 3, 2) [000723] ------------ \--* LCL_VAR byref V51 tmp37 u:1 (last use) $87 ------------ BB54 [261..276), preds={BB48,BB53} succs={BB55} ***** BB54 STMT00170 (IL ???... ???) N005 ( 0, 0) [001193] -A------R--- * ASG byref N004 ( 0, 0) [001191] D------N---- +--* LCL_VAR byref V08 loc4 d:3 N003 ( 0, 0) [001192] ------------ \--* PHI byref N001 ( 0, 0) [001224] ------------ pred BB53 +--* PHI_ARG byref V08 loc4 u:4 $87 N002 ( 0, 0) [001220] ------------ pred BB48 \--* PHI_ARG byref V08 loc4 u:1 $81 ***** BB54 STMT00018 (IL 0x261...0x263) N003 ( 7, 5) [000083] -A------R--- * ASG int N002 ( 3, 2) [000082] D------N---- +--* LCL_VAR int V10 loc6 d:2 N001 ( 3, 2) [000081] ------------ \--* LCL_VAR int V13 loc9 u:1 ***** BB54 STMT00019 (IL 0x265...0x26A) N008 ( 10, 9) [000089] -A-XG---R--- * ASG int $VN.Void N007 ( 4, 4) [000088] D--XG--N---- +--* IND int $708 N006 ( 2, 2) [001115] -------N---- | \--* ADD byref $290 N004 ( 1, 1) [000084] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N005 ( 1, 1) [001114] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] $244 N003 ( 5, 4) [000087] ------------ \--* ADD int N001 ( 3, 2) [000085] ------------ +--* LCL_VAR int V10 loc6 u:2 (last use) N002 ( 1, 1) [000086] ------------ \--* CNS_INT int 1 $c1 ***** BB54 STMT00020 (IL 0x26F...0x275) N006 ( 4, 4) [000093] -A-XG---R--- * ASG ref N005 ( 1, 1) [000092] D------N---- +--* LCL_VAR ref V04 loc0 d:3 N004 ( 4, 4) [000091] ---XG------- \--* IND ref N003 ( 2, 2) [001117] -------N---- \--* ADD byref $281 N001 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001116] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] $241 ------------ BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} ***** BB55 STMT00171 (IL ???... ???) N005 ( 0, 0) [001196] -A------R--- * ASG byref N004 ( 0, 0) [001194] D------N---- +--* LCL_VAR byref V08 loc4 d:2 N003 ( 0, 0) [001195] ------------ \--* PHI byref N001 ( 0, 0) [001225] ------------ pred BB47 +--* PHI_ARG byref V08 loc4 u:1 $81 N002 ( 0, 0) [001221] ------------ pred BB54 \--* PHI_ARG byref V08 loc4 u:3 $780 ***** BB55 STMT00169 (IL ???... ???) N005 ( 0, 0) [001190] -A------R--- * ASG ref N004 ( 0, 0) [001188] D------N---- +--* LCL_VAR ref V04 loc0 d:2 N003 ( 0, 0) [001189] ------------ \--* PHI ref N001 ( 0, 0) [001226] ------------ pred BB47 +--* PHI_ARG ref V04 loc0 u:1 N002 ( 0, 0) [001222] ------------ pred BB54 \--* PHI_ARG ref V04 loc0 u:3 ***** BB55 STMT00168 (IL ???... ???) N005 ( 0, 0) [001187] -A------R--- * ASG int N004 ( 0, 0) [001185] D------N---- +--* LCL_VAR int V10 loc6 d:1 N003 ( 0, 0) [001186] ------------ \--* PHI int N001 ( 0, 0) [001227] ------------ pred BB47 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [001223] ------------ pred BB54 \--* PHI_ARG int V10 loc6 u:2 ***** BB55 STMT00021 (IL 0x276...0x27E) N019 ( 39, 38) [000099] -A-XG---R--- * ASG byref $2a6 N018 ( 3, 2) [000098] D------N---- +--* LCL_VAR byref V11 loc7 d:1 $8c N017 ( 35, 35) [001128] ---XG------- \--* COMMA byref $2a6 N004 ( 10, 12) [001121] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $7cd N001 ( 3, 2) [000095] ------------ | +--* LCL_VAR int V10 loc6 u:1 $3cc N003 ( 3, 3) [001120] ---X-------- | \--* ARR_LENGTH int $73d N002 ( 1, 1) [000094] ------------ | \--* LCL_VAR ref V04 loc0 u:2 $684 N016 ( 25, 23) [001131] ----G------- \--* ADDR byref $8c N015 ( 13, 12) [000096] a---G--N---- \--* IND struct N014 ( 12, 11) [001127] -------N---- \--* ADD byref $8c N005 ( 1, 1) [001118] ------------ +--* LCL_VAR ref V04 loc0 u:2 $684 N013 ( 11, 10) [001126] -------N---- \--* ADD long $6df N011 ( 10, 9) [001124] -------N---- +--* LSH long $6de N009 ( 9, 8) [001130] ------------ | +--* MUL long $6dd N007 ( 4, 4) [001122] ------------ | | +--* CAST long <- int $6dc N006 ( 3, 2) [001119] i----------- | | | \--* LCL_VAR int V10 loc6 u:1 $3cc N008 ( 1, 1) [001129] ------------ | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [001123] -------N---- | \--* CNS_INT long 3 $24b N012 ( 1, 1) [001125] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB55 STMT00022 (IL 0x280...0x283) N006 ( 8, 7) [000103] -A-XG------- * ASG int $VN.Void N004 ( 6, 5) [000102] *--XG--N---- +--* IND int $3c0 N003 ( 4, 3) [001133] -------N---- | \--* ADD byref $8d N001 ( 3, 2) [000100] ------------ | +--* LCL_VAR byref V11 loc7 u:1 $8c N002 ( 1, 1) [001132] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N005 ( 1, 1) [000101] ------------ \--* LCL_VAR int V06 loc2 u:1 (last use) $3c0 ***** BB55 STMT00023 (IL 0x288...0x28F) N009 ( 15, 12) [000110] -A-XG---R--- * ASG int $VN.Void N008 ( 6, 5) [000109] *--XG--N---- +--* IND int N007 ( 4, 3) [001135] -------N---- | \--* ADD byref $8e N005 ( 3, 2) [000104] ------------ | +--* LCL_VAR byref V11 loc7 u:1 $8c N006 ( 1, 1) [001134] ------------ | \--* CNS_INT long 20 field offset Fseq[next] $24c N004 ( 8, 6) [000108] ---XG------- \--* ADD int N002 ( 6, 4) [000106] *--XG------- +--* IND int N001 ( 3, 2) [000105] ------------ | \--* LCL_VAR byref V08 loc4 u:2 $781 N003 ( 1, 1) [000107] ------------ \--* CNS_INT int -1 $c4 ***** BB55 STMT00024 (IL 0x294...0x297) N004 ( 8, 6) [000114] -A-XG------- * ASG ref $VN.Void N002 ( 6, 4) [000113] *--XG--N---- +--* IND ref $101 N001 ( 3, 2) [000111] ------------ | \--* LCL_VAR byref V11 loc7 u:1 Zero Fseq[key] $8f N003 ( 1, 1) [000112] ------------ \--* LCL_VAR ref V01 arg1 u:1 (last use) $101 ***** BB55 STMT00025 (IL 0x29C...0x29F) N006 ( 8, 7) [000118] -A-XG------- * ASG ref $VN.Void N004 ( 6, 5) [000117] *--XG--N---- +--* IND ref $102 N003 ( 4, 3) [001137] -------N---- | \--* ADD byref $90 N001 ( 3, 2) [000115] ------------ | +--* LCL_VAR byref V11 loc7 u:1 (last use) $8c N002 ( 1, 1) [001136] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N005 ( 1, 1) [000116] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 ***** BB55 STMT00026 (IL 0x2A4...0x2AA) N006 ( 12, 9) [000124] -A-XG---R--- * ASG int $VN.Void N005 ( 6, 4) [000123] *--X---N---- +--* IND int $804 N004 ( 3, 2) [000119] ------------ | \--* LCL_VAR byref V08 loc4 u:2 (last use) $781 N003 ( 5, 4) [000122] ------------ \--* ADD int $804 N001 ( 3, 2) [000120] ------------ +--* LCL_VAR int V10 loc6 u:1 (last use) $3cc N002 ( 1, 1) [000121] ------------ \--* CNS_INT int 1 $c1 ***** BB55 STMT00027 (IL 0x2AB...0x2B4) N011 ( 11, 11) [000131] -A-XG---R--- * ASG int $VN.Void N010 ( 4, 4) [000130] D--XG--N---- +--* IND int $80a N009 ( 2, 2) [001139] -------N---- | \--* ADD byref $2a7 N007 ( 1, 1) [000125] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001138] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] $24e N006 ( 6, 6) [000129] ---XG------- \--* ADD int N004 ( 4, 4) [000127] ---XG------- +--* IND int N003 ( 2, 2) [001141] -------N---- | \--* ADD byref $2a7 N001 ( 1, 1) [000126] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001140] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] $24e N005 ( 1, 1) [000128] ------------ \--* CNS_INT int 1 $c1 ***** BB55 STMT00028 (IL 0x2CA...0x2CD) N004 ( 5, 5) [000148] ------------ * JTRUE void N003 ( 3, 3) [000147] N------N-U-- \--* LE int $80d N001 ( 1, 1) [000145] ------------ +--* LCL_VAR int V07 loc3 u:2 (last use) $3c5 N002 ( 1, 1) [000146] ------------ \--* CNS_INT int 100 $e3 ------------ BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} ***** BB56 STMT00030 (IL 0x2CF...0x2D5) N008 ( 21, 22) [000156] --C-G------- * JTRUE void N007 ( 19, 20) [000155] J-C-G--N---- \--* EQ int N005 ( 17, 18) [000153] --C-G------- +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS N003 ( 1, 1) [000151] ------------ arg1 in rdx | +--* LCL_VAR ref V05 loc1 u:1 (last use) N004 ( 2, 10) [000152] H------N---- arg0 in rcx | \--* CNS_INT(h) long 0xd1ffab1e class $62 N006 ( 1, 1) [000154] ------------ \--* CNS_INT ref null $VN.Null ------------ BB57 [2D7..2E3), preds={BB56} succs={BB58} ***** BB57 STMT00031 (IL 0x2D7...0x2DC) N008 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void N005 ( 3, 3) [000159] ---X-------- arg1 in rdx +--* ARR_LENGTH int $73d N004 ( 1, 1) [000158] ------------ | \--* LCL_VAR ref V04 loc0 u:2 (last use) $684 N006 ( 1, 1) [000157] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N007 ( 1, 1) [000160] ------------ arg2 in r8 \--* CNS_INT int 1 $c1 ------------ BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} ***** BB58 STMT00147 (IL ???... ???) N002 ( 2, 2) [000810] ------------ * RETURN int $1f4 N001 ( 1, 1) [000482] ------------ \--* CNS_INT int 1 $c1 ------------ BB59 [008..00E) (throw), preds={BB01} succs={} ***** BB59 STMT00086 (IL 0x008...0x009) N003 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException $VN.Void N002 ( 1, 1) [000532] ------------ arg0 in rcx \--* CNS_INT int 4 $c5 ------------ BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} ***** BB60 STMT00073 (IL 0x14F...0x150) N004 ( 7, 5) [000444] -A-X----R--- * ASG long $2e8 N003 ( 3, 2) [000443] D------N---- +--* LCL_VAR long V26 tmp12 d:1 $2e7 N002 ( 3, 2) [000442] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000441] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB60 STMT00155 (IL ???... ???) N011 ( 16, 14) [001158] ------------ * JTRUE void N010 ( 14, 12) [000460] J------N---- \--* EQ int N008 ( 12, 10) [000456] n----------- +--* IND long N007 ( 10, 8) [000452] -------N---- | \--* ADD long $331 N005 ( 9, 7) [000450] #----------- | +--* IND long $2ea N004 ( 6, 5) [000449] #----------- | | \--* IND long $2e9 N003 ( 4, 3) [000448] -------N---- | | \--* ADD long $306 N001 ( 3, 2) [000446] ------------ | | +--* LCL_VAR long V26 tmp12 u:1 $2e7 N002 ( 1, 1) [000447] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000451] ------------ | \--* CNS_INT long 56 $244 N009 ( 1, 1) [000459] ------------ \--* CNS_INT long 0 $243 ------------ BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} ***** BB61 STMT00156 (IL ???... ???) N010 ( 16, 13) [001160] -A------R--- * ASG long N009 ( 3, 2) [001159] D------N---- +--* LCL_VAR long V28 tmp14 d:3 N008 ( 12, 10) [000461] n-----?----- \--* IND long N007 ( 10, 8) [000462] ------?N---- \--* ADD long $331 N005 ( 9, 7) [000463] #-----?----- +--* IND long $2ea N004 ( 6, 5) [000464] #-----?----- | \--* IND long $2e9 N003 ( 4, 3) [000465] ------?N---- | \--* ADD long $306 N001 ( 3, 2) [000466] ------?----- | +--* LCL_VAR long V26 tmp12 u:1 (last use) $2e7 N002 ( 1, 1) [000467] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000468] ------?----- \--* CNS_INT long 56 $244 ------------ BB62 [???..???), preds={BB60} succs={BB63} ***** BB62 STMT00157 (IL ???... ???) N007 ( 23, 22) [001162] -AC-G---R--- * ASG long $332 N006 ( 3, 2) [001161] D------N---- +--* LCL_VAR long V28 tmp14 d:2 $332 N005 ( 19, 19) [000458] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 N003 ( 3, 2) [000445] ------?----- arg0 in rcx +--* LCL_VAR long V26 tmp12 u:1 (last use) $2e7 N004 ( 2, 10) [000457] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $52 ------------ BB63 [???..157) (throw), preds={BB61,BB62} succs={} ***** BB63 STMT00167 (IL ???... ???) N005 ( 0, 0) [001184] -A------R--- * ASG long N004 ( 0, 0) [001182] D------N---- +--* LCL_VAR long V28 tmp14 d:1 N003 ( 0, 0) [001183] ------------ \--* PHI long N001 ( 0, 0) [001241] ------------ pred BB61 +--* PHI_ARG long V28 tmp14 u:3 N002 ( 0, 0) [001240] ------------ pred BB62 \--* PHI_ARG long V28 tmp14 u:2 $332 ***** BB63 STMT00076 (IL ???... ???) N005 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void N003 ( 3, 2) [000473] ------------ arg0 in rcx +--* LCL_VAR long V28 tmp14 u:1 (last use) $347 N004 ( 1, 1) [000455] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) $101 ------------ BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} ***** BB64 STMT00053 (IL 0x1BC...0x1BD) N004 ( 7, 5) [000299] -A-X----R--- * ASG long $2e8 N003 ( 3, 2) [000298] D------N---- +--* LCL_VAR long V21 tmp7 d:1 $2e7 N002 ( 3, 2) [000297] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000296] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB64 STMT00161 (IL ???... ???) N011 ( 16, 14) [001168] ------------ * JTRUE void N010 ( 14, 12) [000315] J------N---- \--* EQ int N008 ( 12, 10) [000311] n----------- +--* IND long N007 ( 10, 8) [000307] -------N---- | \--* ADD long $331 N005 ( 9, 7) [000305] #----------- | +--* IND long $2ea N004 ( 6, 5) [000304] #----------- | | \--* IND long $2e9 N003 ( 4, 3) [000303] -------N---- | | \--* ADD long $306 N001 ( 3, 2) [000301] ------------ | | +--* LCL_VAR long V21 tmp7 u:1 $2e7 N002 ( 1, 1) [000302] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000306] ------------ | \--* CNS_INT long 56 $244 N009 ( 1, 1) [000314] ------------ \--* CNS_INT long 0 $243 ------------ BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} ***** BB65 STMT00162 (IL ???... ???) N010 ( 16, 13) [001170] -A------R--- * ASG long N009 ( 3, 2) [001169] D------N---- +--* LCL_VAR long V23 tmp9 d:3 N008 ( 12, 10) [000316] n-----?----- \--* IND long N007 ( 10, 8) [000317] ------?N---- \--* ADD long $331 N005 ( 9, 7) [000318] #-----?----- +--* IND long $2ea N004 ( 6, 5) [000319] #-----?----- | \--* IND long $2e9 N003 ( 4, 3) [000320] ------?N---- | \--* ADD long $306 N001 ( 3, 2) [000321] ------?----- | +--* LCL_VAR long V21 tmp7 u:1 (last use) $2e7 N002 ( 1, 1) [000322] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000323] ------?----- \--* CNS_INT long 56 $244 ------------ BB66 [???..???), preds={BB64} succs={BB67} ***** BB66 STMT00163 (IL ???... ???) N007 ( 23, 22) [001172] -AC-G---R--- * ASG long $332 N006 ( 3, 2) [001171] D------N---- +--* LCL_VAR long V23 tmp9 d:2 $332 N005 ( 19, 19) [000313] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 N003 ( 3, 2) [000300] ------?----- arg0 in rcx +--* LCL_VAR long V21 tmp7 u:1 (last use) $2e7 N004 ( 2, 10) [000312] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $52 ------------ BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} ***** BB67 STMT00173 (IL ???... ???) N005 ( 0, 0) [001202] -A------R--- * ASG long N004 ( 0, 0) [001200] D------N---- +--* LCL_VAR long V23 tmp9 d:1 N003 ( 0, 0) [001201] ------------ \--* PHI long N001 ( 0, 0) [001232] ------------ pred BB65 +--* PHI_ARG long V23 tmp9 u:3 N002 ( 0, 0) [001231] ------------ pred BB66 \--* PHI_ARG long V23 tmp9 u:2 $332 ***** BB67 STMT00056 (IL ???... ???) N005 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void N003 ( 3, 2) [000328] ------------ arg0 in rcx +--* LCL_VAR long V23 tmp9 u:1 (last use) $34b N004 ( 1, 1) [000310] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) $101 ------------ BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} ***** BB68 STMT00043 (IL 0x1DD...0x1E2) N001 ( 14, 5) [000233] --CXG------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In optOptimizeValnumCSEs() CSE candidate #01, key=$105 in BB04, [cost= 4, size=12]: N002 ( 4, 12) CSE #01 (use)[000540] #---G------- * IND ref $105 N001 ( 2, 10) [000539] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 CSE candidate #02, key=$2e9 in BB10, [cost= 4, size= 4]: N004 ( 4, 4) CSE #02 (use)[000509] #-----?----- * IND long $2e9 N003 ( 2, 2) [000510] ------?N---- \--* ADD long $306 N001 ( 1, 1) [000511] ------?----- +--* LCL_VAR long V29 tmp15 u:1 (last use) $2e7 N002 ( 1, 1) [000512] ------?----- \--* CNS_INT long 56 $244 CSE candidate #03, key=$2ea in BB10, [cost= 7, size= 6]: N005 ( 7, 6) CSE #03 (use)[000508] #-----?----- * IND long $2ea N004 ( 4, 4) CSE #02 (use)[000509] #-----?----- \--* IND long $2e9 N003 ( 2, 2) [000510] ------?N---- \--* ADD long $306 N001 ( 1, 1) [000511] ------?----- +--* LCL_VAR long V29 tmp15 u:1 (last use) $2e7 N002 ( 1, 1) [000512] ------?----- \--* CNS_INT long 56 $244 CSE candidate #04, key=$341 in BB10, [cost=10, size= 9]: N008 ( 10, 9) CSE #04 (use)[000506] n-----?----- * IND long N007 ( 8, 7) [000507] ------?N---- \--* ADD long $307 N005 ( 7, 6) CSE #03 (use)[000508] #-----?----- +--* IND long $2ea N004 ( 4, 4) CSE #02 (use)[000509] #-----?----- | \--* IND long $2e9 N003 ( 2, 2) [000510] ------?N---- | \--* ADD long $306 N001 ( 1, 1) [000511] ------?----- | +--* LCL_VAR long V29 tmp15 u:1 (last use) $2e7 N002 ( 1, 1) [000512] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000513] ------?----- \--* CNS_INT long 64 $245 CSE candidate #05, key=$401 in BB18, [cost= 3, size= 3]: N003 ( 3, 3) CSE #05 (use)[000854] ---X-------- * ARR_LENGTH int N002 ( 1, 1) [000581] ------------ \--* LCL_VAR ref V39 tmp25 u:1 CSE candidate #06, key=$2e7 in BB19, [cost= 3, size= 2]: N002 ( 3, 2) CSE #06 (use)[000354] #--X-------- * IND long $2e8 N001 ( 1, 1) [000353] !----------- \--* LCL_VAR ref V00 this u:1 $100 CSE candidate #07, key=$343 in BB20, [cost=10, size= 9]: N008 ( 10, 9) CSE #07 (use)[000370] n-----?----- * IND long N007 ( 8, 7) [000371] ------?N---- \--* ADD long $324 N005 ( 7, 6) CSE #03 (use)[000372] #-----?----- +--* IND long $2ea N004 ( 4, 4) CSE #02 (use)[000373] #-----?----- | \--* IND long $2e9 N003 ( 2, 2) [000374] ------?N---- | \--* ADD long $306 N001 ( 1, 1) [000375] ------?----- | +--* LCL_VAR long V24 tmp10 u:1 (last use) $2e7 N002 ( 1, 1) [000376] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000377] ------?----- \--* CNS_INT long 32 $24a CSE candidate #08, key=$403 in BB24, [cost= 3, size= 3]: N003 ( 3, 3) CSE #08 (use)[000871] ---X-------- * ARR_LENGTH int N002 ( 1, 1) [000392] ------------ \--* LCL_VAR ref V04 loc0 u:1 CSE candidate #09, key=$326 in BB25, [cost= 2, size= 3]: N010 ( 2, 3) CSE #09 (use)[000887] ------------ * CAST long <- int $326 N009 ( 1, 1) [000884] i----------- \--* LCL_VAR int V09 loc5 u:4 $3c2 CSE candidate #10, key=$327 in BB25, [cost= 7, size= 7]: N012 ( 7, 7) CSE #10 (use)[000895] ------------ * MUL long $327 N010 ( 2, 3) CSE #09 (use)[000887] ------------ +--* CAST long <- int $326 N009 ( 1, 1) [000884] i----------- | \--* LCL_VAR int V09 loc5 u:4 $3c2 N011 ( 1, 1) [000894] ------------ \--* CNS_INT long 3 $24b CSE candidate #11, key=$28b in BB26, [cost=29, size=32]: N017 ( 29, 32) CSE #11 (use)[000943] ---XG------- * COMMA byref N004 ( 8, 11) [000936] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000401] ------------ | +--* LCL_VAR int V09 loc5 u:4 $3c2 N003 ( 3, 3) CSE #08 (use)[000935] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000400] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000946] ----G------- \--* ADDR byref $82 N015 ( 11, 11) [000402] a---G--N---- \--* IND struct N014 ( 10, 10) [000942] -------N---- \--* ADD byref $82 N005 ( 1, 1) [000933] ------------ +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000941] -------N---- \--* ADD long $329 N011 ( 8, 8) [000939] -------N---- +--* LSH long $328 N009 ( 7, 7) CSE #10 (use)[000945] ------------ | +--* MUL long $327 N007 ( 2, 3) CSE #09 (use)[000937] ------------ | | +--* CAST long <- int $326 N006 ( 1, 1) [000934] i----------- | | | \--* LCL_VAR int V09 loc5 u:4 (last use) $3c2 N008 ( 1, 1) [000944] ------------ | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000938] -------N---- | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000940] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 CSE candidate #12, key=$1be in BB30, [cost= 3, size= 4]: N002 ( 3, 4) CSE #12 (use)[000926] ------------ * CAST int <- ubyte <- int $1be N001 ( 2, 2) [000433] ------------ \--* LCL_VAR int V03 arg3 u:1 (last use) $140 CSE candidate #13, key=$6e1 in BB34, [cost= 2, size= 3]: N007 ( 2, 3) CSE #13 (use)[000967] ------------ * CAST long <- int $6e1 N006 ( 1, 1) [000964] i----------- \--* LCL_VAR int V09 loc5 u:2 $3c4 CSE candidate #14, key=$6e2 in BB34, [cost= 7, size= 7]: N009 ( 7, 7) CSE #14 (use)[000975] ------------ * MUL long $6e2 N007 ( 2, 3) CSE #13 (use)[000967] ------------ +--* CAST long <- int $6e1 N006 ( 1, 1) [000964] i----------- | \--* LCL_VAR int V09 loc5 u:2 $3c4 N008 ( 1, 1) [000974] ------------ \--* CNS_INT long 3 $24b CSE candidate #15, key=$348 in BB35, [cost=10, size= 9]: N008 ( 10, 9) CSE #15 (use)[000264] n-----?----- * IND long N007 ( 8, 7) [000265] ------?N---- \--* ADD long $6e6 N005 ( 7, 6) CSE #03 (use)[000266] #-----?----- +--* IND long $2ea N004 ( 4, 4) CSE #02 (use)[000267] #-----?----- | \--* IND long $2e9 N003 ( 2, 2) [000268] ------?N---- | \--* ADD long $306 N001 ( 1, 1) [000269] ------?----- | +--* LCL_VAR long V16 tmp2 u:1 (last use) $2e7 N002 ( 1, 1) [000270] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000271] ------?----- \--* CNS_INT long 48 $246 CSE candidate #16, key=$2ab in BB39, [cost=29, size=32]: N017 ( 29, 32) CSE #16 (use)[000998] ---XG------- * COMMA byref N004 ( 8, 11) [000991] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000331] ------------ | +--* LCL_VAR int V09 loc5 u:2 $3c4 N003 ( 3, 3) CSE #08 (use)[000990] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000330] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [001001] ----G------- \--* ADDR byref $91 N015 ( 11, 11) [000332] a---G--N---- \--* IND struct N014 ( 10, 10) [000997] -------N---- \--* ADD byref $91 N005 ( 1, 1) [000988] ------------ +--* LCL_VAR ref V04 loc0 u:1 (last use) N013 ( 9, 9) [000996] -------N---- \--* ADD long $6e4 N011 ( 8, 8) [000994] -------N---- +--* LSH long $6e3 N009 ( 7, 7) CSE #14 (use)[001000] ------------ | +--* MUL long $6e2 N007 ( 2, 3) CSE #13 (use)[000992] ------------ | | +--* CAST long <- int $6e1 N006 ( 1, 1) [000989] i----------- | | | \--* LCL_VAR int V09 loc5 u:2 (last use) $3c4 N008 ( 1, 1) [000999] ------------ | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000993] -------N---- | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000995] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 CSE candidate #17, key=$71a in BB45, [cost= 4, size= 4]: N004 ( 4, 4) CSE #17 (use)[000178] ---XG------- * IND int N003 ( 2, 2) [001046] -------N---- \--* ADD byref $295 N001 ( 1, 1) [000177] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001045] ------------ \--* CNS_INT long 60 field offset Fseq[_freeList] $24d CSE candidate #18, key=$62c in BB49, [cost= 4, size= 4]: N006 ( 4, 4) CSE #18 (use)[000701] ---XG------- * IND int N005 ( 2, 2) [001087] -------N---- \--* ADD byref $290 N003 ( 1, 1) [000700] ------------ +--* LCL_VAR ref V00 this u:1 $100 N004 ( 1, 1) [001086] ------------ \--* CNS_INT long 56 field offset Fseq[_count] $244 CSE candidate #19, key=$310 in BB51, [cost= 2, size= 3]: N003 ( 2, 3) CSE #19 (use)[000736] ---------U-- * CAST long <- ulong <- uint $310 N002 ( 1, 1) [000166] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 CSE candidate #20, key=$405 in BB53, [cost= 5, size= 4]: N003 ( 5, 4) CSE #20 (use)[001104] ---X-------- * ARR_LENGTH int N002 ( 3, 2) [000712] ------------ \--* LCL_VAR ref V52 tmp38 u:1 CSE candidate #21, key=$40a in BB57, [cost= 3, size= 3]: N005 ( 3, 3) CSE #21 (use)[000159] ---X-------- * ARR_LENGTH int $73d N004 ( 1, 1) [000158] ------------ \--* LCL_VAR ref V04 loc0 u:2 (last use) $684 CSE candidate #22, key=$346 in BB61, [cost=12, size=10]: N008 ( 12, 10) CSE #22 (use)[000461] n-----?----- * IND long N007 ( 10, 8) [000462] ------?N---- \--* ADD long $331 N005 ( 9, 7) CSE #03 (use)[000463] #-----?----- +--* IND long $2ea N004 ( 6, 5) CSE #02 (use)[000464] #-----?----- | \--* IND long $2e9 N003 ( 4, 3) [000465] ------?N---- | \--* ADD long $306 N001 ( 3, 2) [000466] ------?----- | +--* LCL_VAR long V26 tmp12 u:1 (last use) $2e7 N002 ( 1, 1) [000467] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000468] ------?----- \--* CNS_INT long 56 $244 CSE candidate #23, key=$34a in BB65, [cost=12, size=10]: N008 ( 12, 10) CSE #23 (use)[000316] n-----?----- * IND long N007 ( 10, 8) [000317] ------?N---- \--* ADD long $331 N005 ( 9, 7) CSE #03 (use)[000318] #-----?----- +--* IND long $2ea N004 ( 6, 5) CSE #02 (use)[000319] #-----?----- | \--* IND long $2e9 N003 ( 4, 3) [000320] ------?N---- | \--* ADD long $306 N001 ( 3, 2) [000321] ------?----- | +--* LCL_VAR long V21 tmp7 u:1 (last use) $2e7 N002 ( 1, 1) [000322] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000323] ------?----- \--* CNS_INT long 56 $244 CSE candidate #24, key=$332 in BB66, [cost=19, size=19]: N005 ( 19, 19) CSE #24 (use)[000313] --C-G-?----- * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 N003 ( 3, 2) [000300] ------?----- arg0 in rcx +--* LCL_VAR long V21 tmp7 u:1 (last use) $2e7 N004 ( 2, 10) [000312] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $52 Blocks that generate CSE def/uses BB04 cseGen = 0000000000000003 BB06 cseGen = 0000000000000003 BB09 cseGen = 0000000000000CFC BB10 cseGen = 00000000000000FC BB14 cseGen = 0000000000000303 BB16 cseGen = 0000003000000003 BB18 cseGen = 0000000000000300 BB19 cseGen = 0000000000003C3C BB20 cseGen = 000000000000303C BB23 cseGen = 000000000000C000 BB24 cseGen = 00000000003FC000 BB25 cseGen = 0000000000054000 BB26 cseGen = 00000000003FC000 BB28 cseGen = 0000000000C00000 BB29 cseGen = 00000000003FC000 BB30 cseGen = 0000000000C00000 BB32 cseGen = 000000000000C000 BB33 cseGen = 00000000CF00C000 BB34 cseGen = 000000003F00CC3C BB35 cseGen = 000000003000003C BB38 cseGen = 0000000000C00000 BB39 cseGen = 00000000CF00C000 BB40 cseGen = 0000000000C00000 BB42 cseGen = 00000000CF00C000 BB45 cseGen = 000000030000C003 BB47 cseGen = 000000000000C000 BB48 cseGen = 0000000C0000C000 BB49 cseGen = 000000C400000003 BB51 cseGen = 0000003000000003 BB53 cseGen = 000000C000000000 BB55 cseGen = 0000030000000000 BB57 cseGen = 0000010000000000 BB60 cseGen = 00000C0000000C3C BB61 cseGen = 00000C000000003C BB62 cseGen = 0000C00000000000 BB64 cseGen = 0000300000000C3C BB65 cseGen = 000030000000003C BB66 cseGen = 0000C00000000000 Performing DataFlow for ValnumCSE's StartMerge BB01 :: cseOut = 0001FFFFFFFFFFFF EndMerge BB01 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB02 :: cseOut = 0001FFFFFFFFFFFF Merge BB02 and BB01 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000000000000000 EndMerge BB02 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB59 :: cseOut = 0001FFFFFFFFFFFF Merge BB59 and BB01 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000000000000000 EndMerge BB59 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB03 :: cseOut = 0001FFFFFFFFFFFF Merge BB03 and BB02 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000000000000000 EndMerge BB03 :: cseIn = 0000000000000000 :: cseGen = 0000000000000000 => cseOut = 0000000000000000 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB04 :: cseOut = 0001FFFFFFFFFFFF Merge BB04 and BB02 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000000000000000 Merge BB04 and BB03 :: cseIn = 0000000000000000 :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000000000000000 EndMerge BB04 :: cseIn = 0000000000000000 :: cseGen = 0000000000000003 => cseOut = 0000000000000003 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB04 :: cseOut = 0000000000000003 Merge BB04 and BB02 :: cseIn = 0000000000000000 :: cseOut = 0000000000000003 => cseIn = 0000000000000000 Merge BB04 and BB03 :: cseIn = 0000000000000000 :: cseOut = 0000000000000003 => cseIn = 0000000000000000 EndMerge BB04 :: cseIn = 0000000000000000 :: cseGen = 0000000000000003 => cseOut = 0000000000000003 != preMerge = 0000000000000003, => false StartMerge BB05 :: cseOut = 0001FFFFFFFFFFFF Merge BB05 and BB04 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000000000000003 EndMerge BB05 :: cseIn = 0000000000000003 -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB06 :: cseOut = 0001FFFFFFFFFFFF Merge BB06 and BB04 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000000000000003 Merge BB06 and BB05 :: cseIn = 0000000000000003 :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000000000000001 EndMerge BB06 :: cseIn = 0000000000000001 :: cseGen = 0000000000000003 => cseOut = 0000000000000003 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB06 :: cseOut = 0000000000000003 Merge BB06 and BB04 :: cseIn = 0000000000000001 :: cseOut = 0000000000000003 => cseIn = 0000000000000001 Merge BB06 and BB05 :: cseIn = 0000000000000001 :: cseOut = 0000000000000003 => cseIn = 0000000000000001 EndMerge BB06 :: cseIn = 0000000000000001 :: cseGen = 0000000000000003 => cseOut = 0000000000000003 != preMerge = 0000000000000003, => false StartMerge BB07 :: cseOut = 0001FFFFFFFFFFFF Merge BB07 and BB06 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000000000000003 EndMerge BB07 :: cseIn = 0000000000000003 -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB08 :: cseOut = 0001FFFFFFFFFFFF Merge BB08 and BB06 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000000000000003 Merge BB08 and BB07 :: cseIn = 0000000000000003 :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000000000000001 EndMerge BB08 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB08 :: cseOut = 0000000000000001 Merge BB08 and BB06 :: cseIn = 0000000000000001 :: cseOut = 0000000000000001 => cseIn = 0000000000000001 Merge BB08 and BB07 :: cseIn = 0000000000000001 :: cseOut = 0000000000000001 => cseIn = 0000000000000001 EndMerge BB08 :: cseIn = 0000000000000001 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 0000000000000001, => false StartMerge BB09 :: cseOut = 0001FFFFFFFFFFFF Merge BB09 and BB08 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000000000000001 EndMerge BB09 :: cseIn = 0000000000000001 -- cseKill = 0000555555555555 :: cseGen = 0000000000000CFC => cseOut = 0000000000000CFD != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB13 :: cseOut = 0001FFFFFFFFFFFF Merge BB13 and BB08 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000000000000001 EndMerge BB13 :: cseIn = 0000000000000001 -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000000000000001 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB10 :: cseOut = 0001FFFFFFFFFFFF Merge BB10 and BB09 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000000000000CFD EndMerge BB10 :: cseIn = 0000000000000CFD :: cseGen = 00000000000000FC => cseOut = 0000000000000CFD != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB11 :: cseOut = 0001FFFFFFFFFFFF Merge BB11 and BB09 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000000000000CFD EndMerge BB11 :: cseIn = 0000000000000CFD :: cseGen = 0000000000000000 => cseOut = 0000000000000CFD != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB14 :: cseOut = 0001FFFFFFFFFFFF Merge BB14 and BB12 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0001FFFFFFFFFFFF Merge BB14 and BB13 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000000000000001 EndMerge BB14 :: cseIn = 0000000000000001 :: cseGen = 0000000000000303 => cseOut = 0000000000000303 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB12 :: cseOut = 0001FFFFFFFFFFFF Merge BB12 and BB10 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000000000000CFD Merge BB12 and BB11 :: cseIn = 0000000000000CFD :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000000000000CFD EndMerge BB12 :: cseIn = 0000000000000CFD -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000000000000455 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB12 :: cseOut = 0000000000000455 Merge BB12 and BB10 :: cseIn = 0000000000000CFD :: cseOut = 0000000000000455 => cseIn = 0000000000000CFD Merge BB12 and BB11 :: cseIn = 0000000000000CFD :: cseOut = 0000000000000455 => cseIn = 0000000000000CFD EndMerge BB12 :: cseIn = 0000000000000CFD -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000000000000455 != preMerge = 0000000000000455, => false StartMerge BB15 :: cseOut = 0001FFFFFFFFFFFF Merge BB15 and BB14 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000000000000303 EndMerge BB15 :: cseIn = 0000000000000303 -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000000000000101 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB16 :: cseOut = 0001FFFFFFFFFFFF Merge BB16 and BB14 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000000000000303 Merge BB16 and BB15 :: cseIn = 0000000000000303 :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000000000000101 EndMerge BB16 :: cseIn = 0000000000000101 :: cseGen = 0000003000000003 => cseOut = 0000003000000103 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB14 :: cseOut = 0000000000000303 Merge BB14 and BB12 :: cseIn = 0000000000000001 :: cseOut = 0000000000000303 => cseIn = 0000000000000001 Merge BB14 and BB13 :: cseIn = 0000000000000001 :: cseOut = 0000000000000303 => cseIn = 0000000000000001 EndMerge BB14 :: cseIn = 0000000000000001 :: cseGen = 0000000000000303 => cseOut = 0000000000000303 != preMerge = 0000000000000303, => false StartMerge BB16 :: cseOut = 0000003000000103 Merge BB16 and BB14 :: cseIn = 0000000000000101 :: cseOut = 0000003000000103 => cseIn = 0000000000000101 Merge BB16 and BB15 :: cseIn = 0000000000000101 :: cseOut = 0000003000000103 => cseIn = 0000000000000101 EndMerge BB16 :: cseIn = 0000000000000101 :: cseGen = 0000003000000003 => cseOut = 0000003000000103 != preMerge = 0000003000000103, => false StartMerge BB17 :: cseOut = 0001FFFFFFFFFFFF Merge BB17 and BB16 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000003000000103 EndMerge BB17 :: cseIn = 0000003000000103 -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000001000000101 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB18 :: cseOut = 0001FFFFFFFFFFFF Merge BB18 and BB16 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000003000000103 Merge BB18 and BB17 :: cseIn = 0000003000000103 :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001000000101 EndMerge BB18 :: cseIn = 0000001000000101 :: cseGen = 0000000000000300 => cseOut = 0000001000000301 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB18 :: cseOut = 0000001000000301 Merge BB18 and BB16 :: cseIn = 0000001000000101 :: cseOut = 0000001000000301 => cseIn = 0000001000000101 Merge BB18 and BB17 :: cseIn = 0000001000000101 :: cseOut = 0000001000000301 => cseIn = 0000001000000101 EndMerge BB18 :: cseIn = 0000001000000101 :: cseGen = 0000000000000300 => cseOut = 0000001000000301 != preMerge = 0000001000000301, => false StartMerge BB19 :: cseOut = 0001FFFFFFFFFFFF Merge BB19 and BB18 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001000000301 EndMerge BB19 :: cseIn = 0000001000000301 -- cseKill = 0000555555555555 :: cseGen = 0000000000003C3C => cseOut = 0000001000003D3D != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB32 :: cseOut = 0001FFFFFFFFFFFF Merge BB32 and BB18 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001000000301 Merge BB32 and BB43 :: cseIn = 0000001000000301 :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001000000301 EndMerge BB32 :: cseIn = 0000001000000301 :: cseGen = 000000000000C000 => cseOut = 000000100000C301 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB20 :: cseOut = 0001FFFFFFFFFFFF Merge BB20 and BB19 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001000003D3D EndMerge BB20 :: cseIn = 0000001000003D3D :: cseGen = 000000000000303C => cseOut = 0000001000003D3D != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB21 :: cseOut = 0001FFFFFFFFFFFF Merge BB21 and BB19 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001000003D3D EndMerge BB21 :: cseIn = 0000001000003D3D :: cseGen = 0000000000000000 => cseOut = 0000001000003D3D != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB33 :: cseOut = 0001FFFFFFFFFFFF Merge BB33 and BB32 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 000000100000C301 EndMerge BB33 :: cseIn = 000000100000C301 :: cseGen = 00000000CF00C000 => cseOut = 00000010CF00C301 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB44 :: cseOut = 0001FFFFFFFFFFFF Merge BB44 and BB23 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0001FFFFFFFFFFFF Merge BB44 and BB32 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 000000100000C301 EndMerge BB44 :: cseIn = 000000100000C301 :: cseGen = 0000000000000000 => cseOut = 000000100000C301 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB22 :: cseOut = 0001FFFFFFFFFFFF Merge BB22 and BB20 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001000003D3D Merge BB22 and BB21 :: cseIn = 0000001000003D3D :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001000003D3D EndMerge BB22 :: cseIn = 0000001000003D3D -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000001000001515 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB22 :: cseOut = 0000001000001515 Merge BB22 and BB20 :: cseIn = 0000001000003D3D :: cseOut = 0000001000001515 => cseIn = 0000001000003D3D Merge BB22 and BB21 :: cseIn = 0000001000003D3D :: cseOut = 0000001000001515 => cseIn = 0000001000003D3D EndMerge BB22 :: cseIn = 0000001000003D3D -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000001000001515 != preMerge = 0000001000001515, => false StartMerge BB34 :: cseOut = 0001FFFFFFFFFFFF Merge BB34 and BB33 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 00000010CF00C301 EndMerge BB34 :: cseIn = 00000010CF00C301 -- cseKill = 0000555555555555 :: cseGen = 000000003F00CC3C => cseOut = 000000107F00CD3D != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB42 :: cseOut = 0001FFFFFFFFFFFF Merge BB42 and BB33 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 00000010CF00C301 Merge BB42 and BB37 :: cseIn = 00000010CF00C301 :: cseOut = 0001FFFFFFFFFFFF => cseIn = 00000010CF00C301 EndMerge BB42 :: cseIn = 00000010CF00C301 :: cseGen = 00000000CF00C000 => cseOut = 00000010CF00C301 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB45 :: cseOut = 0001FFFFFFFFFFFF Merge BB45 and BB44 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 000000100000C301 EndMerge BB45 :: cseIn = 000000100000C301 :: cseGen = 000000030000C003 => cseOut = 000000130000C303 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB48 :: cseOut = 0001FFFFFFFFFFFF Merge BB48 and BB44 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 000000100000C301 EndMerge BB48 :: cseIn = 000000100000C301 :: cseGen = 0000000C0000C000 => cseOut = 0000001C0000C301 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB23 :: cseOut = 0001FFFFFFFFFFFF Merge BB23 and BB22 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001000001515 Merge BB23 and BB27 :: cseIn = 0000001000001515 :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001000001515 EndMerge BB23 :: cseIn = 0000001000001515 :: cseGen = 000000000000C000 => cseOut = 000000100000D515 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB35 :: cseOut = 0001FFFFFFFFFFFF Merge BB35 and BB34 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 000000107F00CD3D EndMerge BB35 :: cseIn = 000000107F00CD3D :: cseGen = 000000003000003C => cseOut = 000000107F00CD3D != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB36 :: cseOut = 0001FFFFFFFFFFFF Merge BB36 and BB34 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 000000107F00CD3D EndMerge BB36 :: cseIn = 000000107F00CD3D :: cseGen = 0000000000000000 => cseOut = 000000107F00CD3D != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB43 :: cseOut = 0001FFFFFFFFFFFF Merge BB43 and BB42 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 00000010CF00C301 EndMerge BB43 :: cseIn = 00000010CF00C301 :: cseGen = 0000000000000000 => cseOut = 00000010CF00C301 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB68 :: cseOut = 0001FFFFFFFFFFFF Merge BB68 and BB26 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0001FFFFFFFFFFFF Merge BB68 and BB42 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 00000010CF00C301 EndMerge BB68 :: cseIn = 00000010CF00C301 -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000001045004101 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB46 :: cseOut = 0001FFFFFFFFFFFF Merge BB46 and BB45 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 000000130000C303 EndMerge BB46 :: cseIn = 000000130000C303 -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000001100004101 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB47 :: cseOut = 0001FFFFFFFFFFFF Merge BB47 and BB45 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 000000130000C303 Merge BB47 and BB46 :: cseIn = 000000130000C303 :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001100004101 EndMerge BB47 :: cseIn = 0000001100004101 :: cseGen = 000000000000C000 => cseOut = 000000110000C101 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB49 :: cseOut = 0001FFFFFFFFFFFF Merge BB49 and BB48 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001C0000C301 EndMerge BB49 :: cseIn = 0000001C0000C301 -- cseKill = 0000555555555555 :: cseGen = 000000C400000003 => cseOut = 000000D400004103 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB54 :: cseOut = 0001FFFFFFFFFFFF Merge BB54 and BB48 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001C0000C301 Merge BB54 and BB53 :: cseIn = 0000001C0000C301 :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001C0000C301 EndMerge BB54 :: cseIn = 0000001C0000C301 :: cseGen = 0000000000000000 => cseOut = 0000001C0000C301 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB24 :: cseOut = 0001FFFFFFFFFFFF Merge BB24 and BB23 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 000000100000D515 EndMerge BB24 :: cseIn = 000000100000D515 :: cseGen = 00000000003FC000 => cseOut = 00000010003FD515 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB44 :: cseOut = 000000100000C301 Merge BB44 and BB23 :: cseIn = 000000100000C301 :: cseOut = 000000100000C301 => cseIn = 000000100000C101 Merge BB44 and BB32 :: cseIn = 000000100000C101 :: cseOut = 000000100000C301 => cseIn = 000000100000C101 EndMerge BB44 :: cseIn = 000000100000C101 :: cseGen = 0000000000000000 => cseOut = 000000100000C101 != preMerge = 000000100000C301, => true StartMerge BB37 :: cseOut = 0001FFFFFFFFFFFF Merge BB37 and BB35 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 000000107F00CD3D Merge BB37 and BB36 :: cseIn = 000000107F00CD3D :: cseOut = 0001FFFFFFFFFFFF => cseIn = 000000107F00CD3D EndMerge BB37 :: cseIn = 000000107F00CD3D -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000001055004515 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB37 :: cseOut = 0000001055004515 Merge BB37 and BB35 :: cseIn = 000000107F00CD3D :: cseOut = 0000001055004515 => cseIn = 000000107F00CD3D Merge BB37 and BB36 :: cseIn = 000000107F00CD3D :: cseOut = 0000001055004515 => cseIn = 000000107F00CD3D EndMerge BB37 :: cseIn = 000000107F00CD3D -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000001055004515 != preMerge = 0000001055004515, => false StartMerge BB32 :: cseOut = 000000100000C301 Merge BB32 and BB18 :: cseIn = 0000001000000301 :: cseOut = 000000100000C301 => cseIn = 0000001000000301 Merge BB32 and BB43 :: cseIn = 0000001000000301 :: cseOut = 000000100000C301 => cseIn = 0000001000000301 EndMerge BB32 :: cseIn = 0000001000000301 :: cseGen = 000000000000C000 => cseOut = 000000100000C301 != preMerge = 000000100000C301, => false StartMerge BB47 :: cseOut = 000000110000C101 Merge BB47 and BB45 :: cseIn = 0000001100004101 :: cseOut = 000000110000C101 => cseIn = 0000001100004101 Merge BB47 and BB46 :: cseIn = 0000001100004101 :: cseOut = 000000110000C101 => cseIn = 0000001100004101 EndMerge BB47 :: cseIn = 0000001100004101 :: cseGen = 000000000000C000 => cseOut = 000000110000C101 != preMerge = 000000110000C101, => false StartMerge BB55 :: cseOut = 0001FFFFFFFFFFFF Merge BB55 and BB47 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 000000110000C101 Merge BB55 and BB54 :: cseIn = 000000110000C101 :: cseOut = 0001FFFFFFFFFFFF => cseIn = 000000100000C101 EndMerge BB55 :: cseIn = 000000100000C101 :: cseGen = 0000030000000000 => cseOut = 000003100000C101 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB50 :: cseOut = 0001FFFFFFFFFFFF Merge BB50 and BB49 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 000000D400004103 EndMerge BB50 :: cseIn = 000000D400004103 -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000005400004101 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB51 :: cseOut = 0001FFFFFFFFFFFF Merge BB51 and BB49 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 000000D400004103 Merge BB51 and BB50 :: cseIn = 000000D400004103 :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000005400004101 EndMerge BB51 :: cseIn = 0000005400004101 :: cseGen = 0000003000000003 => cseOut = 0000007400004103 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB55 :: cseOut = 000003100000C101 Merge BB55 and BB47 :: cseIn = 000000100000C101 :: cseOut = 000003100000C101 => cseIn = 000000100000C101 Merge BB55 and BB54 :: cseIn = 000000100000C101 :: cseOut = 000003100000C101 => cseIn = 000000100000C101 EndMerge BB55 :: cseIn = 000000100000C101 :: cseGen = 0000030000000000 => cseOut = 000003100000C101 != preMerge = 000003100000C101, => false StartMerge BB25 :: cseOut = 0001FFFFFFFFFFFF Merge BB25 and BB24 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 00000010003FD515 EndMerge BB25 :: cseIn = 00000010003FD515 -- cseKill = 0000555555555555 :: cseGen = 0000000000054000 => cseOut = 0000001000155515 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB26 :: cseOut = 0001FFFFFFFFFFFF Merge BB26 and BB24 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 00000010003FD515 Merge BB26 and BB25 :: cseIn = 00000010003FD515 :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001000155515 EndMerge BB26 :: cseIn = 0000001000155515 :: cseGen = 00000000003FC000 => cseOut = 00000010003FD515 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB45 :: cseOut = 000000130000C303 Merge BB45 and BB44 :: cseIn = 000000100000C301 :: cseOut = 000000130000C303 => cseIn = 000000100000C101 EndMerge BB45 :: cseIn = 000000100000C101 :: cseGen = 000000030000C003 => cseOut = 000000130000C103 != preMerge = 000000130000C303, => true StartMerge BB48 :: cseOut = 0000001C0000C301 Merge BB48 and BB44 :: cseIn = 000000100000C301 :: cseOut = 0000001C0000C301 => cseIn = 000000100000C101 EndMerge BB48 :: cseIn = 000000100000C101 :: cseGen = 0000000C0000C000 => cseOut = 0000001C0000C101 != preMerge = 0000001C0000C301, => true StartMerge BB38 :: cseOut = 0001FFFFFFFFFFFF Merge BB38 and BB37 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001055004515 EndMerge BB38 :: cseIn = 0000001055004515 :: cseGen = 0000000000C00000 => cseOut = 0000001055C04515 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB42 :: cseOut = 00000010CF00C301 Merge BB42 and BB33 :: cseIn = 00000010CF00C301 :: cseOut = 00000010CF00C301 => cseIn = 00000010CF00C301 Merge BB42 and BB37 :: cseIn = 00000010CF00C301 :: cseOut = 00000010CF00C301 => cseIn = 0000001045004101 EndMerge BB42 :: cseIn = 0000001045004101 :: cseGen = 00000000CF00C000 => cseOut = 00000010CF00C101 != preMerge = 00000010CF00C301, => true StartMerge BB56 :: cseOut = 0001FFFFFFFFFFFF Merge BB56 and BB55 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 000003100000C101 EndMerge BB56 :: cseIn = 000003100000C101 -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000011000004101 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB58 :: cseOut = 0001FFFFFFFFFFFF Merge BB58 and BB29 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0001FFFFFFFFFFFF Merge BB58 and BB39 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0001FFFFFFFFFFFF Merge BB58 and BB55 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 000003100000C101 Merge BB58 and BB56 :: cseIn = 000003100000C101 :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000011000004101 Merge BB58 and BB57 :: cseIn = 0000011000004101 :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000011000004101 EndMerge BB58 :: cseIn = 0000011000004101 :: cseGen = 0000000000000000 => cseOut = 0000011000004101 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB51 :: cseOut = 0000007400004103 Merge BB51 and BB49 :: cseIn = 0000005400004101 :: cseOut = 0000007400004103 => cseIn = 0000005400004101 Merge BB51 and BB50 :: cseIn = 0000005400004101 :: cseOut = 0000007400004103 => cseIn = 0000005400004101 EndMerge BB51 :: cseIn = 0000005400004101 :: cseGen = 0000003000000003 => cseOut = 0000007400004103 != preMerge = 0000007400004103, => false StartMerge BB52 :: cseOut = 0001FFFFFFFFFFFF Merge BB52 and BB51 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000007400004103 EndMerge BB52 :: cseIn = 0000007400004103 -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000005400004101 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB53 :: cseOut = 0001FFFFFFFFFFFF Merge BB53 and BB51 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000007400004103 Merge BB53 and BB52 :: cseIn = 0000007400004103 :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000005400004101 EndMerge BB53 :: cseIn = 0000005400004101 :: cseGen = 000000C000000000 => cseOut = 000000D400004101 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB26 :: cseOut = 00000010003FD515 Merge BB26 and BB24 :: cseIn = 0000001000155515 :: cseOut = 00000010003FD515 => cseIn = 0000001000155515 Merge BB26 and BB25 :: cseIn = 0000001000155515 :: cseOut = 00000010003FD515 => cseIn = 0000001000155515 EndMerge BB26 :: cseIn = 0000001000155515 :: cseGen = 00000000003FC000 => cseOut = 00000010003FD515 != preMerge = 00000010003FD515, => false StartMerge BB28 :: cseOut = 0001FFFFFFFFFFFF Merge BB28 and BB25 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001000155515 EndMerge BB28 :: cseIn = 0000001000155515 :: cseGen = 0000000000C00000 => cseOut = 0000001000D55515 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB27 :: cseOut = 0001FFFFFFFFFFFF Merge BB27 and BB26 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 00000010003FD515 EndMerge BB27 :: cseIn = 00000010003FD515 :: cseGen = 0000000000000000 => cseOut = 00000010003FD515 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB68 :: cseOut = 0000001045004101 Merge BB68 and BB26 :: cseIn = 00000010CF00C301 :: cseOut = 0000001045004101 => cseIn = 000000100000C101 Merge BB68 and BB42 :: cseIn = 000000100000C101 :: cseOut = 0000001045004101 => cseIn = 000000100000C101 EndMerge BB68 :: cseIn = 000000100000C101 -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000001000004101 != preMerge = 0000001045004101, => true StartMerge BB46 :: cseOut = 0000001100004101 Merge BB46 and BB45 :: cseIn = 000000130000C303 :: cseOut = 0000001100004101 => cseIn = 000000130000C103 EndMerge BB46 :: cseIn = 000000130000C103 -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000001100004101 != preMerge = 0000001100004101, => false StartMerge BB47 :: cseOut = 000000110000C101 Merge BB47 and BB45 :: cseIn = 0000001100004101 :: cseOut = 000000110000C101 => cseIn = 0000001100004101 Merge BB47 and BB46 :: cseIn = 0000001100004101 :: cseOut = 000000110000C101 => cseIn = 0000001100004101 EndMerge BB47 :: cseIn = 0000001100004101 :: cseGen = 000000000000C000 => cseOut = 000000110000C101 != preMerge = 000000110000C101, => false StartMerge BB49 :: cseOut = 000000D400004103 Merge BB49 and BB48 :: cseIn = 0000001C0000C301 :: cseOut = 000000D400004103 => cseIn = 0000001C0000C101 EndMerge BB49 :: cseIn = 0000001C0000C101 -- cseKill = 0000555555555555 :: cseGen = 000000C400000003 => cseOut = 000000D400004103 != preMerge = 000000D400004103, => false StartMerge BB54 :: cseOut = 0000001C0000C301 Merge BB54 and BB48 :: cseIn = 0000001C0000C301 :: cseOut = 0000001C0000C301 => cseIn = 0000001C0000C101 Merge BB54 and BB53 :: cseIn = 0000001C0000C101 :: cseOut = 0000001C0000C301 => cseIn = 0000001400004101 EndMerge BB54 :: cseIn = 0000001400004101 :: cseGen = 0000000000000000 => cseOut = 0000001400004101 != preMerge = 0000001C0000C301, => true StartMerge BB39 :: cseOut = 0001FFFFFFFFFFFF Merge BB39 and BB38 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001055C04515 EndMerge BB39 :: cseIn = 0000001055C04515 :: cseGen = 00000000CF00C000 => cseOut = 00000010DFC0C515 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB40 :: cseOut = 0001FFFFFFFFFFFF Merge BB40 and BB38 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001055C04515 EndMerge BB40 :: cseIn = 0000001055C04515 :: cseGen = 0000000000C00000 => cseOut = 0000001055C04515 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB43 :: cseOut = 00000010CF00C301 Merge BB43 and BB42 :: cseIn = 00000010CF00C301 :: cseOut = 00000010CF00C301 => cseIn = 00000010CF00C101 EndMerge BB43 :: cseIn = 00000010CF00C101 :: cseGen = 0000000000000000 => cseOut = 00000010CF00C101 != preMerge = 00000010CF00C301, => true StartMerge BB68 :: cseOut = 0000001000004101 Merge BB68 and BB26 :: cseIn = 000000100000C101 :: cseOut = 0000001000004101 => cseIn = 000000100000C101 Merge BB68 and BB42 :: cseIn = 000000100000C101 :: cseOut = 0000001000004101 => cseIn = 000000100000C101 EndMerge BB68 :: cseIn = 000000100000C101 -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000001000004101 != preMerge = 0000001000004101, => false StartMerge BB57 :: cseOut = 0001FFFFFFFFFFFF Merge BB57 and BB56 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000011000004101 EndMerge BB57 :: cseIn = 0000011000004101 -- cseKill = 0000555555555555 :: cseGen = 0000010000000000 => cseOut = 0000011000004101 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB58 :: cseOut = 0000011000004101 Merge BB58 and BB29 :: cseIn = 0000011000004101 :: cseOut = 0000011000004101 => cseIn = 0000011000004101 Merge BB58 and BB39 :: cseIn = 0000011000004101 :: cseOut = 0000011000004101 => cseIn = 0000001000004101 Merge BB58 and BB55 :: cseIn = 0000001000004101 :: cseOut = 0000011000004101 => cseIn = 0000001000004101 Merge BB58 and BB56 :: cseIn = 0000001000004101 :: cseOut = 0000011000004101 => cseIn = 0000001000004101 Merge BB58 and BB57 :: cseIn = 0000001000004101 :: cseOut = 0000011000004101 => cseIn = 0000001000004101 EndMerge BB58 :: cseIn = 0000001000004101 :: cseGen = 0000000000000000 => cseOut = 0000001000004101 != preMerge = 0000011000004101, => true StartMerge BB53 :: cseOut = 000000D400004101 Merge BB53 and BB51 :: cseIn = 0000005400004101 :: cseOut = 000000D400004101 => cseIn = 0000005400004101 Merge BB53 and BB52 :: cseIn = 0000005400004101 :: cseOut = 000000D400004101 => cseIn = 0000005400004101 EndMerge BB53 :: cseIn = 0000005400004101 :: cseGen = 000000C000000000 => cseOut = 000000D400004101 != preMerge = 000000D400004101, => false StartMerge BB54 :: cseOut = 0000001400004101 Merge BB54 and BB48 :: cseIn = 0000001400004101 :: cseOut = 0000001400004101 => cseIn = 0000001400004101 Merge BB54 and BB53 :: cseIn = 0000001400004101 :: cseOut = 0000001400004101 => cseIn = 0000001400004101 EndMerge BB54 :: cseIn = 0000001400004101 :: cseGen = 0000000000000000 => cseOut = 0000001400004101 != preMerge = 0000001400004101, => false StartMerge BB29 :: cseOut = 0001FFFFFFFFFFFF Merge BB29 and BB28 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001000D55515 EndMerge BB29 :: cseIn = 0000001000D55515 :: cseGen = 00000000003FC000 => cseOut = 0000001000FFD515 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB30 :: cseOut = 0001FFFFFFFFFFFF Merge BB30 and BB28 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001000D55515 EndMerge BB30 :: cseIn = 0000001000D55515 :: cseGen = 0000000000C00000 => cseOut = 0000001000D55515 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB23 :: cseOut = 000000100000D515 Merge BB23 and BB22 :: cseIn = 0000001000001515 :: cseOut = 000000100000D515 => cseIn = 0000001000001515 Merge BB23 and BB27 :: cseIn = 0000001000001515 :: cseOut = 000000100000D515 => cseIn = 0000001000001515 EndMerge BB23 :: cseIn = 0000001000001515 :: cseGen = 000000000000C000 => cseOut = 000000100000D515 != preMerge = 000000100000D515, => false StartMerge BB55 :: cseOut = 000003100000C101 Merge BB55 and BB47 :: cseIn = 000000100000C101 :: cseOut = 000003100000C101 => cseIn = 000000100000C101 Merge BB55 and BB54 :: cseIn = 000000100000C101 :: cseOut = 000003100000C101 => cseIn = 0000001000004101 EndMerge BB55 :: cseIn = 0000001000004101 :: cseGen = 0000030000000000 => cseOut = 0000031000004101 != preMerge = 000003100000C101, => true StartMerge BB58 :: cseOut = 0000001000004101 Merge BB58 and BB29 :: cseIn = 0000001000004101 :: cseOut = 0000001000004101 => cseIn = 0000001000004101 Merge BB58 and BB39 :: cseIn = 0000001000004101 :: cseOut = 0000001000004101 => cseIn = 0000001000004101 Merge BB58 and BB55 :: cseIn = 0000001000004101 :: cseOut = 0000001000004101 => cseIn = 0000001000004101 Merge BB58 and BB56 :: cseIn = 0000001000004101 :: cseOut = 0000001000004101 => cseIn = 0000001000004101 Merge BB58 and BB57 :: cseIn = 0000001000004101 :: cseOut = 0000001000004101 => cseIn = 0000001000004101 EndMerge BB58 :: cseIn = 0000001000004101 :: cseGen = 0000000000000000 => cseOut = 0000001000004101 != preMerge = 0000001000004101, => false StartMerge BB41 :: cseOut = 0001FFFFFFFFFFFF Merge BB41 and BB40 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001055C04515 EndMerge BB41 :: cseIn = 0000001055C04515 :: cseGen = 0000000000000000 => cseOut = 0000001055C04515 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB64 :: cseOut = 0001FFFFFFFFFFFF Merge BB64 and BB40 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001055C04515 EndMerge BB64 :: cseIn = 0000001055C04515 -- cseKill = 0000555555555555 :: cseGen = 0000300000000C3C => cseOut = 0000301055404D3D != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB32 :: cseOut = 000000100000C301 Merge BB32 and BB18 :: cseIn = 0000001000000301 :: cseOut = 000000100000C301 => cseIn = 0000001000000301 Merge BB32 and BB43 :: cseIn = 0000001000000301 :: cseOut = 000000100000C301 => cseIn = 0000001000000101 EndMerge BB32 :: cseIn = 0000001000000101 :: cseGen = 000000000000C000 => cseOut = 000000100000C101 != preMerge = 000000100000C301, => true StartMerge BB58 :: cseOut = 0000001000004101 Merge BB58 and BB29 :: cseIn = 0000001000004101 :: cseOut = 0000001000004101 => cseIn = 0000001000004101 Merge BB58 and BB39 :: cseIn = 0000001000004101 :: cseOut = 0000001000004101 => cseIn = 0000001000004101 Merge BB58 and BB55 :: cseIn = 0000001000004101 :: cseOut = 0000001000004101 => cseIn = 0000001000004101 Merge BB58 and BB56 :: cseIn = 0000001000004101 :: cseOut = 0000001000004101 => cseIn = 0000001000004101 Merge BB58 and BB57 :: cseIn = 0000001000004101 :: cseOut = 0000001000004101 => cseIn = 0000001000004101 EndMerge BB58 :: cseIn = 0000001000004101 :: cseGen = 0000000000000000 => cseOut = 0000001000004101 != preMerge = 0000001000004101, => false StartMerge BB58 :: cseOut = 0000001000004101 Merge BB58 and BB29 :: cseIn = 0000001000004101 :: cseOut = 0000001000004101 => cseIn = 0000001000004101 Merge BB58 and BB39 :: cseIn = 0000001000004101 :: cseOut = 0000001000004101 => cseIn = 0000001000004101 Merge BB58 and BB55 :: cseIn = 0000001000004101 :: cseOut = 0000001000004101 => cseIn = 0000001000004101 Merge BB58 and BB56 :: cseIn = 0000001000004101 :: cseOut = 0000001000004101 => cseIn = 0000001000004101 Merge BB58 and BB57 :: cseIn = 0000001000004101 :: cseOut = 0000001000004101 => cseIn = 0000001000004101 EndMerge BB58 :: cseIn = 0000001000004101 :: cseGen = 0000000000000000 => cseOut = 0000001000004101 != preMerge = 0000001000004101, => false StartMerge BB31 :: cseOut = 0001FFFFFFFFFFFF Merge BB31 and BB30 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001000D55515 Merge BB31 and BB41 :: cseIn = 0000001000D55515 :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001000C04515 EndMerge BB31 :: cseIn = 0000001000C04515 :: cseGen = 0000000000000000 => cseOut = 0000001000C04515 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB60 :: cseOut = 0001FFFFFFFFFFFF Merge BB60 and BB30 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000001000D55515 EndMerge BB60 :: cseIn = 0000001000D55515 -- cseKill = 0000555555555555 :: cseGen = 00000C0000000C3C => cseOut = 00000C1000555D3D != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB56 :: cseOut = 0000011000004101 Merge BB56 and BB55 :: cseIn = 000003100000C101 :: cseOut = 0000011000004101 => cseIn = 0000031000004101 EndMerge BB56 :: cseIn = 0000031000004101 -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000011000004101 != preMerge = 0000011000004101, => false StartMerge BB58 :: cseOut = 0000001000004101 Merge BB58 and BB29 :: cseIn = 0000001000004101 :: cseOut = 0000001000004101 => cseIn = 0000001000004101 Merge BB58 and BB39 :: cseIn = 0000001000004101 :: cseOut = 0000001000004101 => cseIn = 0000001000004101 Merge BB58 and BB55 :: cseIn = 0000001000004101 :: cseOut = 0000001000004101 => cseIn = 0000001000004101 Merge BB58 and BB56 :: cseIn = 0000001000004101 :: cseOut = 0000001000004101 => cseIn = 0000001000004101 Merge BB58 and BB57 :: cseIn = 0000001000004101 :: cseOut = 0000001000004101 => cseIn = 0000001000004101 EndMerge BB58 :: cseIn = 0000001000004101 :: cseGen = 0000000000000000 => cseOut = 0000001000004101 != preMerge = 0000001000004101, => false StartMerge BB31 :: cseOut = 0000001000C04515 Merge BB31 and BB30 :: cseIn = 0000001000C04515 :: cseOut = 0000001000C04515 => cseIn = 0000001000C04515 Merge BB31 and BB41 :: cseIn = 0000001000C04515 :: cseOut = 0000001000C04515 => cseIn = 0000001000C04515 EndMerge BB31 :: cseIn = 0000001000C04515 :: cseGen = 0000000000000000 => cseOut = 0000001000C04515 != preMerge = 0000001000C04515, => false StartMerge BB65 :: cseOut = 0001FFFFFFFFFFFF Merge BB65 and BB64 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000301055404D3D EndMerge BB65 :: cseIn = 0000301055404D3D :: cseGen = 000030000000003C => cseOut = 0000301055404D3D != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB66 :: cseOut = 0001FFFFFFFFFFFF Merge BB66 and BB64 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000301055404D3D EndMerge BB66 :: cseIn = 0000301055404D3D :: cseGen = 0000C00000000000 => cseOut = 0000F01055404D3D != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB33 :: cseOut = 00000010CF00C301 Merge BB33 and BB32 :: cseIn = 000000100000C301 :: cseOut = 00000010CF00C301 => cseIn = 000000100000C101 EndMerge BB33 :: cseIn = 000000100000C101 :: cseGen = 00000000CF00C000 => cseOut = 00000010CF00C101 != preMerge = 00000010CF00C301, => true StartMerge BB44 :: cseOut = 000000100000C101 Merge BB44 and BB23 :: cseIn = 000000100000C101 :: cseOut = 000000100000C101 => cseIn = 000000100000C101 Merge BB44 and BB32 :: cseIn = 000000100000C101 :: cseOut = 000000100000C101 => cseIn = 000000100000C101 EndMerge BB44 :: cseIn = 000000100000C101 :: cseGen = 0000000000000000 => cseOut = 000000100000C101 != preMerge = 000000100000C101, => false StartMerge BB61 :: cseOut = 0001FFFFFFFFFFFF Merge BB61 and BB60 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 00000C1000555D3D EndMerge BB61 :: cseIn = 00000C1000555D3D :: cseGen = 00000C000000003C => cseOut = 00000C1000555D3D != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB62 :: cseOut = 0001FFFFFFFFFFFF Merge BB62 and BB60 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 00000C1000555D3D EndMerge BB62 :: cseIn = 00000C1000555D3D :: cseGen = 0000C00000000000 => cseOut = 0000CC1000555D3D != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB67 :: cseOut = 0001FFFFFFFFFFFF Merge BB67 and BB65 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000301055404D3D Merge BB67 and BB66 :: cseIn = 0000301055404D3D :: cseOut = 0001FFFFFFFFFFFF => cseIn = 0000301055404D3D EndMerge BB67 :: cseIn = 0000301055404D3D -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000101055404515 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB67 :: cseOut = 0000101055404515 Merge BB67 and BB65 :: cseIn = 0000301055404D3D :: cseOut = 0000101055404515 => cseIn = 0000301055404D3D Merge BB67 and BB66 :: cseIn = 0000301055404D3D :: cseOut = 0000101055404515 => cseIn = 0000301055404D3D EndMerge BB67 :: cseIn = 0000301055404D3D -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000101055404515 != preMerge = 0000101055404515, => false StartMerge BB34 :: cseOut = 000000107F00CD3D Merge BB34 and BB33 :: cseIn = 00000010CF00C301 :: cseOut = 000000107F00CD3D => cseIn = 00000010CF00C101 EndMerge BB34 :: cseIn = 00000010CF00C101 -- cseKill = 0000555555555555 :: cseGen = 000000003F00CC3C => cseOut = 000000107F00CD3D != preMerge = 000000107F00CD3D, => false StartMerge BB42 :: cseOut = 00000010CF00C101 Merge BB42 and BB33 :: cseIn = 0000001045004101 :: cseOut = 00000010CF00C101 => cseIn = 0000001045004101 Merge BB42 and BB37 :: cseIn = 0000001045004101 :: cseOut = 00000010CF00C101 => cseIn = 0000001045004101 EndMerge BB42 :: cseIn = 0000001045004101 :: cseGen = 00000000CF00C000 => cseOut = 00000010CF00C101 != preMerge = 00000010CF00C101, => false StartMerge BB63 :: cseOut = 0001FFFFFFFFFFFF Merge BB63 and BB61 :: cseIn = 0001FFFFFFFFFFFF :: cseOut = 0001FFFFFFFFFFFF => cseIn = 00000C1000555D3D Merge BB63 and BB62 :: cseIn = 00000C1000555D3D :: cseOut = 0001FFFFFFFFFFFF => cseIn = 00000C1000555D3D EndMerge BB63 :: cseIn = 00000C1000555D3D -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000041000555515 != preMerge = 0001FFFFFFFFFFFF, => true StartMerge BB63 :: cseOut = 0000041000555515 Merge BB63 and BB61 :: cseIn = 00000C1000555D3D :: cseOut = 0000041000555515 => cseIn = 00000C1000555D3D Merge BB63 and BB62 :: cseIn = 00000C1000555D3D :: cseOut = 0000041000555515 => cseIn = 00000C1000555D3D EndMerge BB63 :: cseIn = 00000C1000555D3D -- cseKill = 0000555555555555 :: cseGen = 0000000000000000 => cseOut = 0000041000555515 != preMerge = 0000041000555515, => false After performing DataFlow for ValnumCSE's BB01 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB02 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB03 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB04 cseIn = 0000000000000000, cseGen = 0000000000000003, cseOut = 0000000000000003 BB05 cseIn = 0000000000000003, cseGen = 0000000000000000, cseOut = 0000000000000001 BB06 cseIn = 0000000000000001, cseGen = 0000000000000003, cseOut = 0000000000000003 BB07 cseIn = 0000000000000003, cseGen = 0000000000000000, cseOut = 0000000000000001 BB08 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB09 cseIn = 0000000000000001, cseGen = 0000000000000CFC, cseOut = 0000000000000CFD BB10 cseIn = 0000000000000CFD, cseGen = 00000000000000FC, cseOut = 0000000000000CFD BB11 cseIn = 0000000000000CFD, cseGen = 0000000000000000, cseOut = 0000000000000CFD BB12 cseIn = 0000000000000CFD, cseGen = 0000000000000000, cseOut = 0000000000000455 BB13 cseIn = 0000000000000001, cseGen = 0000000000000000, cseOut = 0000000000000001 BB14 cseIn = 0000000000000001, cseGen = 0000000000000303, cseOut = 0000000000000303 BB15 cseIn = 0000000000000303, cseGen = 0000000000000000, cseOut = 0000000000000101 BB16 cseIn = 0000000000000101, cseGen = 0000003000000003, cseOut = 0000003000000103 BB17 cseIn = 0000003000000103, cseGen = 0000000000000000, cseOut = 0000001000000101 BB18 cseIn = 0000001000000101, cseGen = 0000000000000300, cseOut = 0000001000000301 BB19 cseIn = 0000001000000301, cseGen = 0000000000003C3C, cseOut = 0000001000003D3D BB20 cseIn = 0000001000003D3D, cseGen = 000000000000303C, cseOut = 0000001000003D3D BB21 cseIn = 0000001000003D3D, cseGen = 0000000000000000, cseOut = 0000001000003D3D BB22 cseIn = 0000001000003D3D, cseGen = 0000000000000000, cseOut = 0000001000001515 BB23 cseIn = 0000001000001515, cseGen = 000000000000C000, cseOut = 000000100000D515 BB24 cseIn = 000000100000D515, cseGen = 00000000003FC000, cseOut = 00000010003FD515 BB25 cseIn = 00000010003FD515, cseGen = 0000000000054000, cseOut = 0000001000155515 BB26 cseIn = 0000001000155515, cseGen = 00000000003FC000, cseOut = 00000010003FD515 BB27 cseIn = 00000010003FD515, cseGen = 0000000000000000, cseOut = 00000010003FD515 BB28 cseIn = 0000001000155515, cseGen = 0000000000C00000, cseOut = 0000001000D55515 BB29 cseIn = 0000001000D55515, cseGen = 00000000003FC000, cseOut = 0000001000FFD515 BB30 cseIn = 0000001000D55515, cseGen = 0000000000C00000, cseOut = 0000001000D55515 BB31 cseIn = 0000001000C04515, cseGen = 0000000000000000, cseOut = 0000001000C04515 BB32 cseIn = 0000001000000101, cseGen = 000000000000C000, cseOut = 000000100000C101 BB33 cseIn = 000000100000C101, cseGen = 00000000CF00C000, cseOut = 00000010CF00C101 BB34 cseIn = 00000010CF00C101, cseGen = 000000003F00CC3C, cseOut = 000000107F00CD3D BB35 cseIn = 000000107F00CD3D, cseGen = 000000003000003C, cseOut = 000000107F00CD3D BB36 cseIn = 000000107F00CD3D, cseGen = 0000000000000000, cseOut = 000000107F00CD3D BB37 cseIn = 000000107F00CD3D, cseGen = 0000000000000000, cseOut = 0000001055004515 BB38 cseIn = 0000001055004515, cseGen = 0000000000C00000, cseOut = 0000001055C04515 BB39 cseIn = 0000001055C04515, cseGen = 00000000CF00C000, cseOut = 00000010DFC0C515 BB40 cseIn = 0000001055C04515, cseGen = 0000000000C00000, cseOut = 0000001055C04515 BB41 cseIn = 0000001055C04515, cseGen = 0000000000000000, cseOut = 0000001055C04515 BB42 cseIn = 0000001045004101, cseGen = 00000000CF00C000, cseOut = 00000010CF00C101 BB43 cseIn = 00000010CF00C101, cseGen = 0000000000000000, cseOut = 00000010CF00C101 BB44 cseIn = 000000100000C101, cseGen = 0000000000000000, cseOut = 000000100000C101 BB45 cseIn = 000000100000C101, cseGen = 000000030000C003, cseOut = 000000130000C103 BB46 cseIn = 000000130000C103, cseGen = 0000000000000000, cseOut = 0000001100004101 BB47 cseIn = 0000001100004101, cseGen = 000000000000C000, cseOut = 000000110000C101 BB48 cseIn = 000000100000C101, cseGen = 0000000C0000C000, cseOut = 0000001C0000C101 BB49 cseIn = 0000001C0000C101, cseGen = 000000C400000003, cseOut = 000000D400004103 BB50 cseIn = 000000D400004103, cseGen = 0000000000000000, cseOut = 0000005400004101 BB51 cseIn = 0000005400004101, cseGen = 0000003000000003, cseOut = 0000007400004103 BB52 cseIn = 0000007400004103, cseGen = 0000000000000000, cseOut = 0000005400004101 BB53 cseIn = 0000005400004101, cseGen = 000000C000000000, cseOut = 000000D400004101 BB54 cseIn = 0000001400004101, cseGen = 0000000000000000, cseOut = 0000001400004101 BB55 cseIn = 0000001000004101, cseGen = 0000030000000000, cseOut = 0000031000004101 BB56 cseIn = 0000031000004101, cseGen = 0000000000000000, cseOut = 0000011000004101 BB57 cseIn = 0000011000004101, cseGen = 0000010000000000, cseOut = 0000011000004101 BB58 cseIn = 0000001000004101, cseGen = 0000000000000000, cseOut = 0000001000004101 BB59 cseIn = 0000000000000000, cseGen = 0000000000000000, cseOut = 0000000000000000 BB60 cseIn = 0000001000D55515, cseGen = 00000C0000000C3C, cseOut = 00000C1000555D3D BB61 cseIn = 00000C1000555D3D, cseGen = 00000C000000003C, cseOut = 00000C1000555D3D BB62 cseIn = 00000C1000555D3D, cseGen = 0000C00000000000, cseOut = 0000CC1000555D3D BB63 cseIn = 00000C1000555D3D, cseGen = 0000000000000000, cseOut = 0000041000555515 BB64 cseIn = 0000001055C04515, cseGen = 0000300000000C3C, cseOut = 0000301055404D3D BB65 cseIn = 0000301055404D3D, cseGen = 000030000000003C, cseOut = 0000301055404D3D BB66 cseIn = 0000301055404D3D, cseGen = 0000C00000000000, cseOut = 0000F01055404D3D BB67 cseIn = 0000301055404D3D, cseGen = 0000000000000000, cseOut = 0000101055404515 BB68 cseIn = 000000100000C101, cseGen = 0000000000000000, cseOut = 0000001000004101 Labeling the CSEs with Use/Def information BB04 [000538] Def of CSE #01 [weight=1 ] BB04 [000540] Use of CSE #01 [weight=1 ] BB06 [000562] Use of CSE #01 [weight=1 ] *** Now Live Across Call *** BB09 [000487] Def of CSE #06 [weight=0.50] BB09 [000494] Def of CSE #02 [weight=0.50] BB09 [000495] Def of CSE #03 [weight=0.50] BB09 [000501] Def of CSE #04 [weight=0.50] BB10 [000509] Use of CSE #02 [weight=0.25] BB10 [000508] Use of CSE #03 [weight=0.25] BB10 [000506] Use of CSE #04 [weight=0.25] BB14 [000583] Def of CSE #05 [weight=1 ] BB14 [000636] Use of CSE #01 [weight=1 ] BB14 [000638] Use of CSE #01 [weight=1 ] BB16 [000605] Def of CSE #19 [weight=1 ] BB16 [000659] Use of CSE #01 [weight=1 ] BB16 [000661] Use of CSE #01 [weight=1 ] BB18 [000854] Use of CSE #05 [weight=1 ] *** Now Live Across Call *** BB19 [000354] Def of CSE #06 [weight=0.50] BB19 [000361] Def of CSE #02 [weight=0.50] BB19 [000362] Def of CSE #03 [weight=0.50] BB19 [000365] Def of CSE #07 [weight=0.50] BB20 [000373] Use of CSE #02 [weight=0.25] BB20 [000372] Use of CSE #03 [weight=0.25] BB20 [000370] Use of CSE #07 [weight=0.25] BB23 [000389] Def of CSE #08 [weight=4 ] BB24 [000871] Use of CSE #08 [weight=4 ] BB24 [000873] Def of CSE #09 [weight=4 ] BB24 [000881] Def of CSE #10 [weight=4 ] BB24 [000879] Def of CSE #11 [weight=4 ] BB25 [000885] Use of CSE #08 [weight=2 ] BB25 [000887] Use of CSE #09 [weight=2 ] BB25 [000895] Use of CSE #10 [weight=2 ] BB26 [000935] Use of CSE #08 [weight=4 ] *** Now Live Across Call *** BB26 [000937] Use of CSE #09 [weight=4 ] *** Now Live Across Call *** BB26 [000945] Use of CSE #10 [weight=4 ] *** Now Live Across Call *** BB26 [000943] Use of CSE #11 [weight=4 ] *** Now Live Across Call *** BB26 [000414] Use of CSE #08 [weight=4 ] BB28 [000909] Def of CSE #12 [weight=0.50] BB29 [000914] Use of CSE #08 [weight=0.50] BB29 [000916] Use of CSE #09 [weight=0.50] BB29 [000924] Use of CSE #10 [weight=0.50] BB29 [000922] Use of CSE #11 [weight=0.50] BB30 [000926] Use of CSE #12 [weight=0.50] BB32 [000064] Def of CSE #08 [weight=4 ] BB33 [000951] Use of CSE #08 [weight=4 ] BB33 [000953] Def of CSE #13 [weight=4 ] BB33 [000961] Def of CSE #14 [weight=4 ] BB33 [000959] Def of CSE #16 [weight=4 ] BB34 [000965] Use of CSE #08 [weight=2 ] BB34 [000967] Use of CSE #13 [weight=2 ] BB34 [000975] Use of CSE #14 [weight=2 ] BB34 [000242] Def of CSE #06 [weight=2 ] BB34 [000252] Def of CSE #02 [weight=2 ] BB34 [000253] Def of CSE #03 [weight=2 ] BB34 [000259] Def of CSE #15 [weight=2 ] BB35 [000267] Use of CSE #02 [weight=1 ] BB35 [000266] Use of CSE #03 [weight=1 ] BB35 [000264] Use of CSE #15 [weight=1 ] BB38 [000985] Def of CSE #12 [weight=0.50] BB39 [000990] Use of CSE #08 [weight=0.50] BB39 [000992] Use of CSE #13 [weight=0.50] *** Now Live Across Call *** BB39 [001000] Use of CSE #14 [weight=0.50] *** Now Live Across Call *** BB39 [000998] Use of CSE #16 [weight=0.50] *** Now Live Across Call *** BB40 [001002] Use of CSE #12 [weight=0.50] BB42 [001012] Use of CSE #08 [weight=4 ] BB42 [001014] Use of CSE #13 [weight=4 ] BB42 [001022] Use of CSE #14 [weight=4 ] BB42 [001020] Use of CSE #16 [weight=4 ] BB42 [000230] Use of CSE #08 [weight=4 ] BB45 [000172] Def of CSE #17 [weight=0.50] BB45 [000178] Use of CSE #17 [weight=0.50] BB45 [001035] Use of CSE #08 [weight=0.50] BB45 [000684] Use of CSE #01 [weight=0.50] BB47 [001064] Use of CSE #08 [weight=0.50] BB48 [000073] Def of CSE #18 [weight=0.50] BB48 [000078] Use of CSE #08 [weight=0.50] BB49 [000701] Use of CSE #18 [weight=0.50] BB49 [000714] Def of CSE #20 [weight=0.50] BB49 [000767] Use of CSE #01 [weight=0.50] BB49 [000769] Use of CSE #01 [weight=0.50] BB51 [000736] Use of CSE #19 [weight=0.50] *** Now Live Across Call *** BB51 [000790] Use of CSE #01 [weight=0.50] BB51 [000792] Use of CSE #01 [weight=0.50] BB53 [001104] Use of CSE #20 [weight=0.50] *** Now Live Across Call *** BB55 [001120] Def of CSE #21 [weight=0.50] BB57 [000159] Use of CSE #21 [weight=0.50] *** Now Live Across Call *** BB60 [000442] Use of CSE #06 [weight=0 ] *** Now Live Across Call *** BB60 [000449] Use of CSE #02 [weight=0 ] *** Now Live Across Call *** BB60 [000450] Use of CSE #03 [weight=0 ] *** Now Live Across Call *** BB60 [000456] Def of CSE #22 [weight=0 ] BB61 [000464] Use of CSE #02 [weight=0 ] BB61 [000463] Use of CSE #03 [weight=0 ] BB61 [000461] Use of CSE #22 [weight=0 ] BB62 [000458] Def of CSE #24 [weight=0 ] BB64 [000297] Use of CSE #06 [weight=0 ] BB64 [000304] Use of CSE #02 [weight=0 ] BB64 [000305] Use of CSE #03 [weight=0 ] BB64 [000311] Def of CSE #23 [weight=0 ] BB65 [000319] Use of CSE #02 [weight=0 ] BB65 [000318] Use of CSE #03 [weight=0 ] BB65 [000316] Use of CSE #23 [weight=0 ] BB66 [000313] Def of CSE #24 [weight=0 ] ************ Trees at start of optValnumCSE_Heuristic() ------------ BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} ***** BB01 STMT00000 (IL 0x000...0x006) N004 ( 5, 5) [000003] ------------ * JTRUE void N003 ( 3, 3) [000002] J------N---- \--* EQ int $180 N001 ( 1, 1) [000000] ------------ +--* LCL_VAR ref V01 arg1 u:1 $101 N002 ( 1, 1) [000001] ------------ \--* CNS_INT ref null $VN.Null ------------ BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00001 (IL 0x00E...0x014) N007 ( 8, 8) [000008] ---XG------- * JTRUE void N006 ( 6, 6) [000007] J--XG--N---- \--* NE int N004 ( 4, 4) [000005] ---XG------- +--* IND ref N003 ( 2, 2) [000814] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000004] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000813] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] $240 N005 ( 1, 1) [000006] ------------ \--* CNS_INT ref null $VN.Null ------------ BB03 [016..01E), preds={BB02} succs={BB04} ***** BB03 STMT00085 (IL ???... ???) N005 ( 16, 10) [000528] --CXG------- * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize $1c2 N003 ( 1, 1) [000526] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N004 ( 1, 1) [000527] ------------ arg1 in rdx \--* CNS_INT int 0 $c0 ------------ BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ***** BB04 STMT00088 (IL 0x01E... ???) N008 ( 9, 6) [000544] -A-XG---R--- * ASG bool N007 ( 1, 1) [000543] D------N---- +--* LCL_VAR int V33 tmp19 d:1 N006 ( 9, 6) [000012] N--XG------- \--* NE int N004 ( 4, 4) [000010] ---XG------- +--* IND ref N003 ( 2, 2) [000818] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000009] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000817] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] $240 N005 ( 1, 1) [000011] ------------ \--* CNS_INT ref null $VN.Null ***** BB04 STMT00091 (IL 0x01E... ???) N004 ( 4, 12) [000554] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000553] D------N---- +--* LCL_VAR ref V34 tmp20 d:1 $105 N002 ( 4, 12) CSE #01 (def)[000538] #---G------- \--* IND ref $105 N001 ( 2, 10) [000537] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB04 STMT00092 (IL 0x01E... ???) N004 ( 4, 12) [000556] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000555] D------N---- +--* LCL_VAR ref V35 tmp21 d:1 $105 N002 ( 4, 12) CSE #01 (use)[000540] #---G------- \--* IND ref $105 N001 ( 2, 10) [000539] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB04 STMT00089 (IL 0x01E... ???) N004 ( 5, 5) [000549] ------------ * JTRUE void N003 ( 3, 3) [000548] J------N---- \--* NE int N001 ( 1, 1) [000546] ------------ +--* LCL_VAR int V33 tmp19 u:1 (last use) N002 ( 1, 1) [000547] ------------ \--* CNS_INT int 0 $c0 ------------ BB05 [01E..01F), preds={BB04} succs={BB06} ***** BB05 STMT00090 (IL 0x01E... ???) N005 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 1, 1) [000550] ------------ arg0 in rcx +--* LCL_VAR ref V35 tmp21 u:1 (last use) $105 N004 ( 1, 1) [000551] ------------ arg1 in rdx \--* LCL_VAR ref V35 tmp21 u:1 (last use) $105 ------------ BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} ***** BB06 STMT00003 (IL 0x02C... ???) N006 ( 4, 4) [000018] -A-XG---R--- * ASG ref N005 ( 1, 1) [000017] D------N---- +--* LCL_VAR ref V04 loc0 d:1 N004 ( 4, 4) [000016] ---XG------- \--* IND ref N003 ( 2, 2) [000822] -------N---- \--* ADD byref $281 N001 ( 1, 1) [000015] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000821] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] $241 ***** BB06 STMT00094 (IL 0x033... ???) N005 ( 6, 3) [000566] -A------R--- * ASG bool N004 ( 1, 1) [000565] D------N---- +--* LCL_VAR int V36 tmp22 d:1 N003 ( 6, 3) [000021] N----------- \--* NE int N001 ( 1, 1) [000019] ------------ +--* LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000020] ------------ \--* CNS_INT ref null $VN.Null ***** BB06 STMT00097 (IL 0x033... ???) N004 ( 4, 12) [000576] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000575] D------N---- +--* LCL_VAR ref V37 tmp23 d:1 $105 N002 ( 4, 12) CSE #01 (use)[000562] #---G------- \--* IND ref $105 N001 ( 2, 10) [000561] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB06 STMT00095 (IL 0x033... ???) N004 ( 5, 5) [000571] ------------ * JTRUE void N003 ( 3, 3) [000570] J------N---- \--* NE int N001 ( 1, 1) [000568] ------------ +--* LCL_VAR int V36 tmp22 u:1 (last use) N002 ( 1, 1) [000569] ------------ \--* CNS_INT int 0 $c0 ------------ BB07 [033..034), preds={BB06} succs={BB08} ***** BB07 STMT00096 (IL 0x033... ???) N006 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N004 ( 4, 12) [000824] #---G------- arg0 in rcx +--* IND ref $106 N003 ( 2, 10) [000823] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" $46 N005 ( 1, 1) [000573] ------------ arg1 in rdx \--* LCL_VAR ref V37 tmp23 u:1 (last use) $105 ------------ BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} ***** BB08 STMT00005 (IL 0x041... ???) N006 ( 4, 4) [000028] -A-XG---R--- * ASG ref N005 ( 1, 1) [000027] D------N---- +--* LCL_VAR ref V05 loc1 d:1 N004 ( 4, 4) [000026] ---XG------- \--* IND ref N003 ( 2, 2) [000828] -------N---- \--* ADD byref $282 N001 ( 1, 1) [000025] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000827] ------------ \--* CNS_INT long 24 field offset Fseq[_comparer] $242 ***** BB08 STMT00006 (IL 0x048...0x049) N004 ( 5, 5) [000032] ------------ * JTRUE void N003 ( 3, 3) [000031] J------N---- \--* EQ int N001 ( 1, 1) [000029] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000030] ------------ \--* CNS_INT ref null $VN.Null ------------ BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} ***** BB09 STMT00079 (IL 0x04B...0x052) N004 ( 3, 3) [000489] -A-X----R--- * ASG long $2e8 N003 ( 1, 1) [000488] D------N---- +--* LCL_VAR long V29 tmp15 d:1 $2e7 N002 ( 3, 2) CSE #06 (def)[000487] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000486] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB09 STMT00149 (IL ???... ???) N011 ( 14, 13) [001148] ------------ * JTRUE void N010 ( 12, 11) [000505] J------N---- \--* EQ int N008 ( 10, 9) CSE #04 (def)[000501] n----------- +--* IND long N007 ( 8, 7) [000497] -------N---- | \--* ADD long $307 N005 ( 7, 6) CSE #03 (def)[000495] #----------- | +--* IND long $2ea N004 ( 4, 4) CSE #02 (def)[000494] #----------- | | \--* IND long $2e9 N003 ( 2, 2) [000493] -------N---- | | \--* ADD long $306 N001 ( 1, 1) [000491] ------------ | | +--* LCL_VAR long V29 tmp15 u:1 $2e7 N002 ( 1, 1) [000492] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000496] ------------ | \--* CNS_INT long 64 $245 N009 ( 1, 1) [000504] ------------ \--* CNS_INT long 0 $243 ------------ BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} ***** BB10 STMT00150 (IL ???... ???) N010 ( 10, 9) [001150] -A------R--- * ASG long N009 ( 1, 1) [001149] D------N---- +--* LCL_VAR long V31 tmp17 d:3 N008 ( 10, 9) CSE #04 (use)[000506] n-----?----- \--* IND long N007 ( 8, 7) [000507] ------?N---- \--* ADD long $307 N005 ( 7, 6) CSE #03 (use)[000508] #-----?----- +--* IND long $2ea N004 ( 4, 4) CSE #02 (use)[000509] #-----?----- | \--* IND long $2e9 N003 ( 2, 2) [000510] ------?N---- | \--* ADD long $306 N001 ( 1, 1) [000511] ------?----- | +--* LCL_VAR long V29 tmp15 u:1 (last use) $2e7 N002 ( 1, 1) [000512] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000513] ------?----- \--* CNS_INT long 64 $245 ------------ BB11 [???..???), preds={BB09} succs={BB12} ***** BB11 STMT00151 (IL ???... ???) N007 ( 17, 18) [001152] -AC-G---R--- * ASG long $308 N006 ( 1, 1) [001151] D------N---- +--* LCL_VAR long V31 tmp17 d:2 $308 N005 ( 17, 18) [000503] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $308 N003 ( 1, 1) [000490] ------?----- arg0 in rcx +--* LCL_VAR long V29 tmp15 u:1 (last use) $2e7 N004 ( 2, 10) [000502] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $49 ------------ BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} ***** BB12 STMT00178 (IL ???... ???) N005 ( 0, 0) [001217] -A------R--- * ASG long N004 ( 0, 0) [001215] D------N---- +--* LCL_VAR long V31 tmp17 d:1 N003 ( 0, 0) [001216] ------------ \--* PHI long N001 ( 0, 0) [001247] ------------ pred BB10 +--* PHI_ARG long V31 tmp17 u:3 N002 ( 0, 0) [001246] ------------ pred BB11 \--* PHI_ARG long V31 tmp17 u:2 $308 ***** BB12 STMT00083 (IL ???... ???) N010 ( 31, 15) [000524] -ACXG---R--- * ASG int $1c7 N009 ( 3, 2) [000523] D------N---- +--* LCL_VAR int V15 tmp1 d:3 $1c7 N008 ( 27, 12) [000522] --CXG------- \--* CALL ind stub int $1c7 N007 ( 1, 1) [000521] ------------ calli tgt \--* LCL_VAR long V31 tmp17 u:1 (last use) $342 N004 ( 1, 1) [000484] ------------ this in rcx +--* LCL_VAR ref V05 loc1 u:1 N005 ( 1, 1) [000831] ------------ arg1 in r11 +--* LCL_VAR long V31 tmp17 u:1 r11 REG r11 $342 N006 ( 1, 1) [000500] ------------ arg2 in rdx \--* LCL_VAR ref V01 arg1 u:1 $101 ------------ BB13 [054..061), preds={BB08} succs={BB14} ***** BB13 STMT00007 (IL 0x054...0x05C) N013 ( 34, 21) [000038] -ACXG---R--- * ASG int $1c5 N012 ( 3, 2) [000037] D------N---- +--* LCL_VAR int V15 tmp1 d:2 $1c5 N011 ( 30, 18) [000035] --CXG------- \--* CALLV vt-ind int System.Object.GetHashCode $1c5 N010 ( 9, 8) [000843] n--X-------- control expr \--* IND long N009 ( 7, 6) [000842] ---X---N---- \--* ADD long $303 N007 ( 6, 5) [000840] #--X-------- +--* IND long $2e6 N006 ( 4, 3) [000839] ---X---N---- | \--* ADD long $301 N004 ( 3, 2) [000837] #--X-------- | +--* IND long $2e4 N003 ( 1, 1) [000836] ------------ | | \--* LCL_VAR ref V01 arg1 u:1 $101 N005 ( 1, 1) [000838] ------------ | \--* CNS_INT int 72 $c9 N008 ( 1, 1) [000841] ------------ \--* CNS_INT int 24 $ca N002 ( 1, 1) [000033] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 $101 ------------ BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ***** BB14 STMT00177 (IL ???... ???) N005 ( 0, 0) [001214] -A------R--- * ASG int N004 ( 0, 0) [001212] D------N---- +--* LCL_VAR int V15 tmp1 d:1 N003 ( 0, 0) [001213] ------------ \--* PHI int N001 ( 0, 0) [001245] ------------ pred BB12 +--* PHI_ARG int V15 tmp1 u:3 $1c7 N002 ( 0, 0) [001244] ------------ pred BB13 \--* PHI_ARG int V15 tmp1 u:2 $1c5 ***** BB14 STMT00008 (IL ???...0x061) N003 ( 3, 3) [000042] -A------R--- * ASG int $3c0 N002 ( 1, 1) [000041] D------N---- +--* LCL_VAR int V06 loc2 d:1 $3c0 N001 ( 3, 2) [000040] ------------ \--* LCL_VAR int V15 tmp1 u:1 (last use) $3c0 ***** BB14 STMT00009 (IL 0x062...0x063) N003 ( 1, 3) [000045] -A------R--- * ASG int $c0 N002 ( 1, 1) [000044] D------N---- +--* LCL_VAR int V07 loc3 d:1 $c0 N001 ( 1, 1) [000043] ------------ \--* CNS_INT int 0 $c0 ***** BB14 STMT00098 (IL 0x064... ???) N006 ( 4, 4) [000580] -A-XG---R--- * ASG ref N005 ( 1, 1) [000579] D------N---- +--* LCL_VAR ref V39 tmp25 d:1 N004 ( 4, 4) [000578] ---XG------- \--* IND ref N003 ( 2, 2) [000845] -------N---- \--* ADD byref $280 N001 ( 1, 1) [000046] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000844] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] $240 ***** BB14 STMT00105 (IL 0x064... ???) N004 ( 3, 3) [000629] -A-X----R--- * ASG int N003 ( 1, 1) [000628] D------N---- +--* LCL_VAR int V40 tmp26 d:1 N002 ( 3, 3) CSE #05 (def)[000583] ---X-------- \--* ARR_LENGTH int N001 ( 1, 1) [000582] ------------ \--* LCL_VAR ref V39 tmp25 u:1 ***** BB14 STMT00106 (IL 0x064... ???) N006 ( 4, 4) [000631] -A-XG---R--- * ASG long N005 ( 1, 1) [000630] D------N---- +--* LCL_VAR long V41 tmp27 d:1 N004 ( 4, 4) [000585] ---XG------- \--* IND long N003 ( 2, 2) [000847] -------N---- \--* ADD byref $283 N001 ( 1, 1) [000584] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000846] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 ***** BB14 STMT00108 (IL 0x064... ???) N005 ( 6, 6) [000642] -A------R--- * ASG bool N004 ( 1, 1) [000641] D------N---- +--* LCL_VAR int V43 tmp29 d:1 N003 ( 6, 6) [000599] N--------U-- \--* LE int N001 ( 1, 1) [000597] ------------ +--* LCL_VAR int V40 tmp26 u:1 N002 ( 1, 4) [000598] ------------ \--* CNS_INT int 0x7FFFFFFF $ce ***** BB14 STMT00111 (IL 0x064... ???) N004 ( 4, 12) [000652] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000651] D------N---- +--* LCL_VAR ref V44 tmp30 d:1 $105 N002 ( 4, 12) CSE #01 (use)[000636] #---G------- \--* IND ref $105 N001 ( 2, 10) [000635] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB14 STMT00112 (IL 0x064... ???) N004 ( 4, 12) [000654] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000653] D------N---- +--* LCL_VAR ref V45 tmp31 d:1 $105 N002 ( 4, 12) CSE #01 (use)[000638] #---G------- \--* IND ref $105 N001 ( 2, 10) [000637] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB14 STMT00109 (IL 0x064... ???) N004 ( 5, 5) [000647] ------------ * JTRUE void N003 ( 3, 3) [000646] J------N---- \--* NE int N001 ( 1, 1) [000644] ------------ +--* LCL_VAR int V43 tmp29 u:1 (last use) N002 ( 1, 1) [000645] ------------ \--* CNS_INT int 0 $c0 ------------ BB15 [064..065), preds={BB14} succs={BB16} ***** BB15 STMT00110 (IL 0x064... ???) N005 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 1, 1) [000648] ------------ arg0 in rcx +--* LCL_VAR ref V45 tmp31 u:1 (last use) $105 N004 ( 1, 1) [000649] ------------ arg1 in rdx \--* LCL_VAR ref V45 tmp31 u:1 (last use) $105 ------------ BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} ***** BB16 STMT00103 (IL 0x064... ???) N016 ( 20, 21) [000619] -A------R--- * ASG int N015 ( 1, 1) [000618] D------N---- +--* LCL_VAR int V42 tmp28 d:1 N014 ( 20, 21) [000617] ------------ \--* CAST int <- uint <- long N013 ( 19, 19) [000616] ------------ \--* RSZ long N011 ( 17, 17) [000614] ------------ +--* MUL long N008 ( 11, 11) [000611] ------------ | +--* ADD long N006 ( 9, 9) [000608] ------------ | | +--* RSZ long N004 ( 7, 7) [000606] ------------ | | | +--* MUL long N001 ( 1, 1) [000604] ------------ | | | | +--* LCL_VAR long V41 tmp27 u:1 (last use) N003 ( 2, 3) CSE #19 (def)[000605] ---------U-- | | | | \--* CAST long <- ulong <- uint $310 N002 ( 1, 1) [000047] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 $3c0 N005 ( 1, 1) [000607] ------------ | | | \--* CNS_INT int 32 $d2 N007 ( 1, 1) [000610] ------------ | | \--* CNS_INT long 1 $247 N010 ( 2, 3) [000613] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000612] ------------ | \--* LCL_VAR int V40 tmp26 u:1 N012 ( 1, 1) [000615] ------------ \--* CNS_INT int 32 $d2 ***** BB16 STMT00114 (IL 0x064... ???) N007 ( 27, 7) [000665] -A-X----R--- * ASG bool N006 ( 1, 1) [000664] D------N---- +--* LCL_VAR int V46 tmp32 d:1 N005 ( 27, 7) [000624] ---X-------- \--* EQ int N003 ( 22, 5) [000623] ---X-------- +--* UMOD int N001 ( 1, 1) [000621] ------------ | +--* LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000622] ------------ | \--* LCL_VAR int V40 tmp26 u:1 (last use) N004 ( 1, 1) [000620] ------------ \--* LCL_VAR int V42 tmp28 u:1 ***** BB16 STMT00117 (IL 0x064... ???) N004 ( 4, 12) [000675] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000674] D------N---- +--* LCL_VAR ref V47 tmp33 d:1 $105 N002 ( 4, 12) CSE #01 (use)[000659] #---G------- \--* IND ref $105 N001 ( 2, 10) [000658] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB16 STMT00118 (IL 0x064... ???) N004 ( 4, 12) [000677] -A--G---R--- * ASG ref $105 N003 ( 1, 1) [000676] D------N---- +--* LCL_VAR ref V48 tmp34 d:1 $105 N002 ( 4, 12) CSE #01 (use)[000661] #---G------- \--* IND ref $105 N001 ( 2, 10) [000660] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB16 STMT00115 (IL 0x064... ???) N004 ( 5, 5) [000670] ------------ * JTRUE void N003 ( 3, 3) [000669] J------N---- \--* NE int N001 ( 1, 1) [000667] ------------ +--* LCL_VAR int V46 tmp32 u:1 (last use) N002 ( 1, 1) [000668] ------------ \--* CNS_INT int 0 $c0 ------------ BB17 [064..065), preds={BB16} succs={BB18} ***** BB17 STMT00116 (IL 0x064... ???) N005 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 1, 1) [000671] ------------ arg0 in rcx +--* LCL_VAR ref V48 tmp34 u:1 (last use) $105 N004 ( 1, 1) [000672] ------------ arg1 in rdx \--* LCL_VAR ref V48 tmp34 u:1 (last use) $105 ------------ BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} ***** BB18 STMT00100 (IL 0x064... ???) N017 ( 19, 24) [000591] -A-XG---R--- * ASG byref N016 ( 1, 1) [000590] D------N---- +--* LCL_VAR byref V38 tmp24 d:1 $81 N015 ( 19, 24) [000862] ---XG------- \--* COMMA byref N004 ( 8, 11) [000855] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000627] ------------ | +--* LCL_VAR int V42 tmp28 u:1 N003 ( 3, 3) CSE #05 (use)[000854] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000581] ------------ | \--* LCL_VAR ref V39 tmp25 u:1 N014 ( 11, 13) [000863] ----G------- \--* ADDR byref $81 N013 ( 6, 7) [000588] a---G--N---- \--* IND int N012 ( 5, 6) [000861] -------N---- \--* ADD byref $81 N005 ( 1, 1) [000852] ------------ +--* LCL_VAR ref V39 tmp25 u:1 (last use) N011 ( 4, 5) [000860] -------N---- \--* ADD long N009 ( 3, 4) [000858] -------N---- +--* LSH long N007 ( 2, 3) [000856] ------------ | +--* CAST long <- int N006 ( 1, 1) [000853] i----------- | | \--* LCL_VAR int V42 tmp28 u:1 (last use) N008 ( 1, 1) [000857] -------N---- | \--* CNS_INT long 2 $248 N010 ( 1, 1) [000859] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB18 STMT00011 (IL ???... ???) N003 ( 5, 4) [000051] -A------R--- * ASG byref $81 N002 ( 3, 2) [000050] D------N---- +--* LCL_VAR byref V08 loc4 d:1 $81 N001 ( 1, 1) [000592] ------------ \--* LCL_VAR byref V38 tmp24 u:1 $81 ***** BB18 STMT00012 (IL 0x06D...0x072) N006 ( 5, 4) [000057] -A-XG---R--- * ASG int N005 ( 1, 1) [000056] D------N---- +--* LCL_VAR int V09 loc5 d:1 N004 ( 5, 4) [000055] ---XG------- \--* ADD int N002 ( 3, 2) [000053] *--XG------- +--* IND int N001 ( 1, 1) [000052] ------------ | \--* LCL_VAR byref V08 loc4 u:1 (last use) $81 N003 ( 1, 1) [000054] ------------ \--* CNS_INT int -1 $c4 ***** BB18 STMT00013 (IL 0x074...0x075) N004 ( 5, 5) [000061] ------------ * JTRUE void N003 ( 3, 3) [000060] J------N---- \--* NE int N001 ( 1, 1) [000058] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000059] ------------ \--* CNS_INT ref null $VN.Null ------------ BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} ***** BB19 STMT00059 (IL 0x0FF...0x104) N004 ( 3, 3) [000356] -A-X----R--- * ASG long $2e8 N003 ( 1, 1) [000355] D------N---- +--* LCL_VAR long V24 tmp10 d:1 $2e7 N002 ( 3, 2) CSE #06 (def)[000354] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000353] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB19 STMT00152 (IL ???... ???) N011 ( 14, 13) [001153] ------------ * JTRUE void N010 ( 12, 11) [000369] J------N---- \--* EQ int N008 ( 10, 9) CSE #07 (def)[000365] n----------- +--* IND long N007 ( 8, 7) [000364] -------N---- | \--* ADD long $324 N005 ( 7, 6) CSE #03 (def)[000362] #----------- | +--* IND long $2ea N004 ( 4, 4) CSE #02 (def)[000361] #----------- | | \--* IND long $2e9 N003 ( 2, 2) [000360] -------N---- | | \--* ADD long $306 N001 ( 1, 1) [000358] ------------ | | +--* LCL_VAR long V24 tmp10 u:1 $2e7 N002 ( 1, 1) [000359] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000363] ------------ | \--* CNS_INT long 32 $24a N009 ( 1, 1) [000368] ------------ \--* CNS_INT long 0 $243 ------------ BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} ***** BB20 STMT00153 (IL ???... ???) N010 ( 14, 12) [001155] -A------R--- * ASG long N009 ( 3, 2) [001154] D------N---- +--* LCL_VAR long V25 tmp11 d:3 N008 ( 10, 9) CSE #07 (use)[000370] n-----?----- \--* IND long N007 ( 8, 7) [000371] ------?N---- \--* ADD long $324 N005 ( 7, 6) CSE #03 (use)[000372] #-----?----- +--* IND long $2ea N004 ( 4, 4) CSE #02 (use)[000373] #-----?----- | \--* IND long $2e9 N003 ( 2, 2) [000374] ------?N---- | \--* ADD long $306 N001 ( 1, 1) [000375] ------?----- | +--* LCL_VAR long V24 tmp10 u:1 (last use) $2e7 N002 ( 1, 1) [000376] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000377] ------?----- \--* CNS_INT long 32 $24a ------------ BB21 [???..???), preds={BB19} succs={BB22} ***** BB21 STMT00154 (IL ???... ???) N007 ( 21, 21) [001157] -AC-G---R--- * ASG long $325 N006 ( 3, 2) [001156] D------N---- +--* LCL_VAR long V25 tmp11 d:2 $325 N005 ( 17, 18) [000367] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $325 N003 ( 1, 1) [000357] ------?----- arg0 in rcx +--* LCL_VAR long V24 tmp10 u:1 (last use) $2e7 N004 ( 2, 10) [000366] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $4f ------------ BB22 [???..106), preds={BB20,BB21} succs={BB23} ***** BB22 STMT00172 (IL ???... ???) N005 ( 0, 0) [001199] -A------R--- * ASG long N004 ( 0, 0) [001197] D------N---- +--* LCL_VAR long V25 tmp11 d:1 N003 ( 0, 0) [001198] ------------ \--* PHI long N001 ( 0, 0) [001243] ------------ pred BB20 +--* PHI_ARG long V25 tmp11 u:3 N002 ( 0, 0) [001242] ------------ pred BB21 \--* PHI_ARG long V25 tmp11 u:2 $325 ***** BB22 STMT00062 (IL ???... ???) N005 ( 17, 8) [000386] -ACXG---R--- * ASG ref $223 N004 ( 1, 1) [000385] D------N---- +--* LCL_VAR ref V12 loc8 d:1 $223 N003 ( 17, 8) [000352] --CXG------- \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default $223 N002 ( 3, 2) [000382] ------------ arg0 in rcx \--* LCL_VAR long V25 tmp11 u:1 (last use) $344 ------------ BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} ***** BB23 STMT00165 (IL ???... ???) N005 ( 0, 0) [001178] -A------R--- * ASG int N004 ( 0, 0) [001176] D------N---- +--* LCL_VAR int V07 loc3 d:5 N003 ( 0, 0) [001177] ------------ \--* PHI int N001 ( 0, 0) [001238] ------------ pred BB27 +--* PHI_ARG int V07 loc3 u:6 N002 ( 0, 0) [001235] ------------ pred BB22 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB23 STMT00164 (IL ???... ???) N005 ( 0, 0) [001175] -A------R--- * ASG int N004 ( 0, 0) [001173] D------N---- +--* LCL_VAR int V09 loc5 d:4 N003 ( 0, 0) [001174] ------------ \--* PHI int N001 ( 0, 0) [001239] ------------ pred BB27 +--* PHI_ARG int V09 loc5 u:5 N002 ( 0, 0) [001236] ------------ pred BB22 \--* PHI_ARG int V09 loc5 u:1 ***** BB23 STMT00063 (IL 0x106...0x10B) N005 ( 7, 7) [000391] ---X-------- * JTRUE void N004 ( 5, 5) [000390] N--X---N-U-- \--* LE int N002 ( 3, 3) CSE #08 (def)[000389] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000388] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000387] ------------ \--* LCL_VAR int V09 loc5 u:4 $3c2 ------------ BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} ***** BB24 STMT00064 (IL 0x110...0x11E) N023 ( 36, 39) [000399] ---XG------- * JTRUE void N022 ( 34, 37) [000398] N--XG--N-U-- \--* NE int N020 ( 32, 35) [000396] *--XG------- +--* IND int N019 ( 30, 33) [000868] ---XG--N---- | \--* ADD byref $28c N017 ( 29, 32) CSE #11 (def)[000879] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000872] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000393] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N003 ( 3, 3) CSE #08 (use)[000871] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000392] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000882] ----G------- | | \--* ADDR byref $82 N015 ( 11, 11) [000394] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000878] -------N---- | | \--* ADD byref $82 N005 ( 1, 1) [000869] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000877] -------N---- | | \--* ADD long $329 N011 ( 8, 8) [000875] -------N---- | | +--* LSH long $328 N009 ( 7, 7) CSE #10 (def)[000881] ------------ | | | +--* MUL long $327 N007 ( 2, 3) CSE #09 (def)[000873] ------------ | | | | +--* CAST long <- int $326 N006 ( 1, 1) [000870] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 $3c2 N008 ( 1, 1) [000880] ------------ | | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000874] -------N---- | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000876] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000867] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N021 ( 1, 1) [000397] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 ------------ BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} ***** BB25 STMT00069 (IL 0x120...0x135) N035 ( 67, 59) [000428] --CXG------- * JTRUE void N034 ( 65, 57) [000427] J-CXG--N---- \--* NE int $1bd N032 ( 63, 55) [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals $581 N031 ( 9, 8) [000908] n--X-------- control expr | \--* IND long N030 ( 7, 6) [000907] ---X---N---- | \--* ADD long $32e N028 ( 6, 5) [000905] #--X-------- | +--* IND long $465 N027 ( 4, 3) [000904] ---X---N---- | | \--* ADD long $32c N025 ( 3, 2) [000902] #--X-------- | | +--* IND long $463 N024 ( 1, 1) [000901] ------------ | | | \--* LCL_VAR ref V12 loc8 u:1 $223 N026 ( 1, 1) [000903] ------------ | | \--* CNS_INT int 72 $c9 N029 ( 1, 1) [000906] ------------ | \--* CNS_INT int 32 $d2 N021 ( 32, 34) [000893] ---XG------- arg1 in rdx | +--* COMMA ref N007 ( 8, 11) [000886] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N004 ( 1, 1) [000420] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N006 ( 3, 3) CSE #08 (use)[000885] ---X-------- | | | \--* ARR_LENGTH int N005 ( 1, 1) [000419] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N020 ( 24, 23) [000897] *---G------- | | \--* IND ref N019 ( 21, 21) [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] $84 N018 ( 11, 11) [000421] a---G--N---- | | \--* IND struct N017 ( 10, 10) [000892] -------N---- | | \--* ADD byref $82 N008 ( 1, 1) [000883] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N016 ( 9, 9) [000891] -------N---- | | \--* ADD long $329 N014 ( 8, 8) [000889] -------N---- | | +--* LSH long $328 N012 ( 7, 7) CSE #10 (use)[000895] ------------ | | | +--* MUL long $327 N010 ( 2, 3) CSE #09 (use)[000887] ------------ | | | | +--* CAST long <- int $326 N009 ( 1, 1) [000884] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 $3c2 N011 ( 1, 1) [000894] ------------ | | | | \--* CNS_INT long 3 $24b N013 ( 1, 1) [000888] -------N---- | | | \--* CNS_INT long 3 $24b N015 ( 1, 1) [000890] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N022 ( 1, 1) [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 u:1 $223 N023 ( 1, 1) [000424] ------------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 u:1 $101 N033 ( 1, 1) [000426] ------------ \--* CNS_INT int 0 $c0 ------------ BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} ***** BB26 STMT00065 (IL 0x157...0x164) N022 ( 32, 35) [000406] -A-XG---R--- * ASG int N021 ( 1, 1) [000405] D------N---- +--* LCL_VAR int V09 loc5 d:5 N020 ( 32, 35) [000404] *--XG------- \--* IND int N019 ( 30, 33) [000932] ---XG--N---- \--* ADD byref $28e N017 ( 29, 32) CSE #11 (use)[000943] ---XG------- +--* COMMA byref N004 ( 8, 11) [000936] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000401] ------------ | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N003 ( 3, 3) CSE #08 (use)[000935] ---X-------- | | \--* ARR_LENGTH int N002 ( 1, 1) [000400] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000946] ----G------- | \--* ADDR byref $82 N015 ( 11, 11) [000402] a---G--N---- | \--* IND struct N014 ( 10, 10) [000942] -------N---- | \--* ADD byref $82 N005 ( 1, 1) [000933] ------------ | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000941] -------N---- | \--* ADD long $329 N011 ( 8, 8) [000939] -------N---- | +--* LSH long $328 N009 ( 7, 7) CSE #10 (use)[000945] ------------ | | +--* MUL long $327 N007 ( 2, 3) CSE #09 (use)[000937] ------------ | | | +--* CAST long <- int $326 N006 ( 1, 1) [000934] i----------- | | | | \--* LCL_VAR int V09 loc5 u:4 (last use) $3c2 N008 ( 1, 1) [000944] ------------ | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000938] -------N---- | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000940] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000931] ------------ \--* CNS_INT long 20 field offset Fseq[next] $24c ***** BB26 STMT00066 (IL 0x166...0x169) N005 ( 3, 3) [000411] -A------R--- * ASG int $605 N004 ( 1, 1) [000410] D------N---- +--* LCL_VAR int V07 loc3 d:6 $605 N003 ( 3, 3) [000409] ------------ \--* ADD int $605 N001 ( 1, 1) [000407] ------------ +--* LCL_VAR int V07 loc3 u:5 (last use) $3c1 N002 ( 1, 1) [000408] ------------ \--* CNS_INT int 1 $c1 ***** BB26 STMT00067 (IL 0x16A...0x16E) N005 ( 7, 7) [000416] ---X-------- * JTRUE void N004 ( 5, 5) [000415] N--X---N-U-- \--* LT int N002 ( 3, 3) CSE #08 (use)[000414] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000413] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000412] ------------ \--* LCL_VAR int V07 loc3 u:6 $605 ------------ BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} ------------ BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} ***** BB28 STMT00070 (IL 0x137...0x139) N005 ( 7, 8) [000432] ------------ * JTRUE void N004 ( 5, 6) [000431] N------N-U-- \--* NE int $1bf N002 ( 3, 4) CSE #12 (def)[000909] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000429] ------------ | \--* LCL_VAR int V03 arg3 u:1 $140 N003 ( 1, 1) [000430] ------------ \--* CNS_INT int 1 $c1 ------------ BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} ***** BB29 STMT00077 (IL 0x13B...0x144) N022 ( 34, 37) [000481] -A-XG------- * ASG ref $VN.Void N020 ( 32, 35) [000480] *--XG--N---- +--* IND ref $102 N019 ( 30, 33) [000911] ---XG--N---- | \--* ADD byref $28d N017 ( 29, 32) CSE #11 (use)[000922] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000915] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000476] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N003 ( 3, 3) CSE #08 (use)[000914] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000475] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000925] ----G------- | | \--* ADDR byref $82 N015 ( 11, 11) [000477] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000921] -------N---- | | \--* ADD byref $82 N005 ( 1, 1) [000912] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 (last use) N013 ( 9, 9) [000920] -------N---- | | \--* ADD long $329 N011 ( 8, 8) [000918] -------N---- | | +--* LSH long $328 N009 ( 7, 7) CSE #10 (use)[000924] ------------ | | | +--* MUL long $327 N007 ( 2, 3) CSE #09 (use)[000916] ------------ | | | | +--* CAST long <- int $326 N006 ( 1, 1) [000913] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:4 (last use) $3c2 N008 ( 1, 1) [000923] ------------ | | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000917] -------N---- | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000919] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000910] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N021 ( 1, 1) [000479] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 ------------ BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} ***** BB30 STMT00071 (IL 0x14B...0x14D) N005 ( 7, 8) [000436] ------------ * JTRUE void N004 ( 5, 6) [000435] N------N-U-- \--* EQ int $600 N002 ( 3, 4) CSE #12 (use)[000926] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000433] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) $140 N003 ( 1, 1) [000434] ------------ \--* CNS_INT int 2 $c2 ------------ BB31 [???..???) (return), preds={BB30,BB41} succs={} ***** BB31 STMT00148 (IL ???... ???) N002 ( 2, 2) [000811] ------------ * RETURN int $1f3 N001 ( 1, 1) [000437] ------------ \--* CNS_INT int 0 $c0 ------------ BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} ***** BB32 STMT00175 (IL ???... ???) N005 ( 0, 0) [001208] -A------R--- * ASG int N004 ( 0, 0) [001206] D------N---- +--* LCL_VAR int V07 loc3 d:3 N003 ( 0, 0) [001207] ------------ \--* PHI int N001 ( 0, 0) [001229] ------------ pred BB43 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [001218] ------------ pred BB18 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB32 STMT00174 (IL ???... ???) N005 ( 0, 0) [001205] -A------R--- * ASG int N004 ( 0, 0) [001203] D------N---- +--* LCL_VAR int V09 loc5 d:2 N003 ( 0, 0) [001204] ------------ \--* PHI int N001 ( 0, 0) [001230] ------------ pred BB43 +--* PHI_ARG int V09 loc5 u:3 N002 ( 0, 0) [001219] ------------ pred BB18 \--* PHI_ARG int V09 loc5 u:1 ***** BB32 STMT00014 (IL 0x177...0x17C) N005 ( 7, 7) [000066] ---X-------- * JTRUE void N004 ( 5, 5) [000065] N--X---N-U-- \--* LE int N002 ( 3, 3) CSE #08 (def)[000064] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000063] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000062] ------------ \--* LCL_VAR int V09 loc5 u:2 $3c4 ------------ BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} ***** BB33 STMT00039 (IL 0x17E...0x18C) N023 ( 36, 39) [000215] ---XG------- * JTRUE void N022 ( 34, 37) [000214] N--XG--N-U-- \--* NE int N020 ( 32, 35) [000212] *--XG------- +--* IND int N019 ( 30, 33) [000948] ---XG--N---- | \--* ADD byref $2ac N017 ( 29, 32) CSE #16 (def)[000959] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000952] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000209] ------------ | | | +--* LCL_VAR int V09 loc5 u:2 $3c4 N003 ( 3, 3) CSE #08 (use)[000951] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000208] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000962] ----G------- | | \--* ADDR byref $91 N015 ( 11, 11) [000210] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000958] -------N---- | | \--* ADD byref $91 N005 ( 1, 1) [000949] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000957] -------N---- | | \--* ADD long $6e4 N011 ( 8, 8) [000955] -------N---- | | +--* LSH long $6e3 N009 ( 7, 7) CSE #14 (def)[000961] ------------ | | | +--* MUL long $6e2 N007 ( 2, 3) CSE #13 (def)[000953] ------------ | | | | +--* CAST long <- int $6e1 N006 ( 1, 1) [000950] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:2 $3c4 N008 ( 1, 1) [000960] ------------ | | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000954] -------N---- | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000956] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000947] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N021 ( 1, 1) [000213] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 ------------ BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} ***** BB34 STMT00045 (IL 0x18E...0x1A2) N020 ( 32, 34) [000246] -A-XG---R--- * ASG ref N019 ( 1, 1) [000245] D------N---- +--* LCL_VAR ref V17 tmp3 d:1 N018 ( 32, 34) [000973] ---XG------- \--* COMMA ref N004 ( 8, 11) [000966] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000236] ------------ | +--* LCL_VAR int V09 loc5 u:2 $3c4 N003 ( 3, 3) CSE #08 (use)[000965] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000235] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N017 ( 24, 23) [000977] *---G------- \--* IND ref N016 ( 21, 21) [000976] ----G------- \--* ADDR byref Zero Fseq[key] $93 N015 ( 11, 11) [000237] a---G--N---- \--* IND struct N014 ( 10, 10) [000972] -------N---- \--* ADD byref $91 N005 ( 1, 1) [000963] ------------ +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000971] -------N---- \--* ADD long $6e4 N011 ( 8, 8) [000969] -------N---- +--* LSH long $6e3 N009 ( 7, 7) CSE #14 (use)[000975] ------------ | +--* MUL long $6e2 N007 ( 2, 3) CSE #13 (use)[000967] ------------ | | +--* CAST long <- int $6e1 N006 ( 1, 1) [000964] i----------- | | | \--* LCL_VAR int V09 loc5 u:2 $3c4 N008 ( 1, 1) [000974] ------------ | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000968] -------N---- | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000970] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB34 STMT00044 (IL 0x18E... ???) N004 ( 3, 3) [000244] -A-X----R--- * ASG long $2e8 N003 ( 1, 1) [000243] D------N---- +--* LCL_VAR long V16 tmp2 d:1 $2e7 N002 ( 3, 2) CSE #06 (def)[000242] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000241] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB34 STMT00158 (IL ???... ???) N011 ( 14, 13) [001163] ------------ * JTRUE void N010 ( 12, 11) [000263] J------N---- \--* EQ int N008 ( 10, 9) CSE #15 (def)[000259] n----------- +--* IND long N007 ( 8, 7) [000255] -------N---- | \--* ADD long $6e6 N005 ( 7, 6) CSE #03 (def)[000253] #----------- | +--* IND long $2ea N004 ( 4, 4) CSE #02 (def)[000252] #----------- | | \--* IND long $2e9 N003 ( 2, 2) [000251] -------N---- | | \--* ADD long $306 N001 ( 1, 1) [000249] ------------ | | +--* LCL_VAR long V16 tmp2 u:1 $2e7 N002 ( 1, 1) [000250] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000254] ------------ | \--* CNS_INT long 48 $246 N009 ( 1, 1) [000262] ------------ \--* CNS_INT long 0 $243 ------------ BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} ***** BB35 STMT00159 (IL ???... ???) N010 ( 10, 9) [001165] -A------R--- * ASG long N009 ( 1, 1) [001164] D------N---- +--* LCL_VAR long V19 tmp5 d:3 N008 ( 10, 9) CSE #15 (use)[000264] n-----?----- \--* IND long N007 ( 8, 7) [000265] ------?N---- \--* ADD long $6e6 N005 ( 7, 6) CSE #03 (use)[000266] #-----?----- +--* IND long $2ea N004 ( 4, 4) CSE #02 (use)[000267] #-----?----- | \--* IND long $2e9 N003 ( 2, 2) [000268] ------?N---- | \--* ADD long $306 N001 ( 1, 1) [000269] ------?----- | +--* LCL_VAR long V16 tmp2 u:1 (last use) $2e7 N002 ( 1, 1) [000270] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000271] ------?----- \--* CNS_INT long 48 $246 ------------ BB36 [???..???), preds={BB34} succs={BB37} ***** BB36 STMT00160 (IL ???... ???) N007 ( 17, 18) [001167] -AC-G---R--- * ASG long $6e7 N006 ( 1, 1) [001166] D------N---- +--* LCL_VAR long V19 tmp5 d:2 $6e7 N005 ( 17, 18) [000261] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $6e7 N003 ( 1, 1) [000248] ------?----- arg0 in rcx +--* LCL_VAR long V16 tmp2 u:1 (last use) $2e7 N004 ( 2, 10) [000260] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $63 ------------ BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} ***** BB37 STMT00176 (IL ???... ???) N005 ( 0, 0) [001211] -A------R--- * ASG long N004 ( 0, 0) [001209] D------N---- +--* LCL_VAR long V19 tmp5 d:1 N003 ( 0, 0) [001210] ------------ \--* PHI long N001 ( 0, 0) [001234] ------------ pred BB35 +--* PHI_ARG long V19 tmp5 u:3 N002 ( 0, 0) [001233] ------------ pred BB36 \--* PHI_ARG long V19 tmp5 u:2 $6e7 ***** BB37 STMT00049 (IL ???... ???) N013 ( 32, 18) [000283] --CXG------- * JTRUE void N012 ( 30, 16) [000282] J-CXG--N---- \--* EQ int $817 N010 ( 28, 14) [000280] --CXG------- +--* CALL ind stub int $1ef N009 ( 1, 1) [000279] ------------ calli tgt | \--* LCL_VAR long V19 tmp5 u:1 (last use) $349 N005 ( 1, 1) [000234] ------------ this in rcx | +--* LCL_VAR ref V05 loc1 u:1 N006 ( 1, 1) [000980] ------------ arg1 in r11 | +--* LCL_VAR long V19 tmp5 u:1 r11 REG r11 $349 N007 ( 1, 1) [000247] ------------ arg2 in rdx | +--* LCL_VAR ref V17 tmp3 u:1 (last use) N008 ( 1, 1) [000258] ------------ arg3 in r8 | \--* LCL_VAR ref V01 arg1 u:1 $101 N011 ( 1, 1) [000281] ------------ \--* CNS_INT int 0 $c0 ------------ BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} ***** BB38 STMT00050 (IL 0x1A4...0x1A6) N005 ( 7, 8) [000287] ------------ * JTRUE void N004 ( 5, 6) [000286] N------N-U-- \--* NE int $1bf N002 ( 3, 4) CSE #12 (def)[000985] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000284] ------------ | \--* LCL_VAR int V03 arg3 u:1 $140 N003 ( 1, 1) [000285] ------------ \--* CNS_INT int 1 $c1 ------------ BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} ***** BB39 STMT00057 (IL 0x1A8...0x1B1) N022 ( 34, 37) [000336] -A-XG------- * ASG ref $VN.Void N020 ( 32, 35) [000335] *--XG--N---- +--* IND ref $102 N019 ( 30, 33) [000987] ---XG--N---- | \--* ADD byref $2ae N017 ( 29, 32) CSE #16 (use)[000998] ---XG------- | +--* COMMA byref N004 ( 8, 11) [000991] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000331] ------------ | | | +--* LCL_VAR int V09 loc5 u:2 $3c4 N003 ( 3, 3) CSE #08 (use)[000990] ---X-------- | | | \--* ARR_LENGTH int N002 ( 1, 1) [000330] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [001001] ----G------- | | \--* ADDR byref $91 N015 ( 11, 11) [000332] a---G--N---- | | \--* IND struct N014 ( 10, 10) [000997] -------N---- | | \--* ADD byref $91 N005 ( 1, 1) [000988] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 (last use) N013 ( 9, 9) [000996] -------N---- | | \--* ADD long $6e4 N011 ( 8, 8) [000994] -------N---- | | +--* LSH long $6e3 N009 ( 7, 7) CSE #14 (use)[001000] ------------ | | | +--* MUL long $6e2 N007 ( 2, 3) CSE #13 (use)[000992] ------------ | | | | +--* CAST long <- int $6e1 N006 ( 1, 1) [000989] i----------- | | | | | \--* LCL_VAR int V09 loc5 u:2 (last use) $3c4 N008 ( 1, 1) [000999] ------------ | | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000993] -------N---- | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000995] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000986] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N021 ( 1, 1) [000334] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 ------------ BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} ***** BB40 STMT00051 (IL 0x1B8...0x1BA) N005 ( 7, 8) [000291] ------------ * JTRUE void N004 ( 5, 6) [000290] N------N-U-- \--* EQ int $600 N002 ( 3, 4) CSE #12 (use)[001002] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000288] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) $140 N003 ( 1, 1) [000289] ------------ \--* CNS_INT int 2 $c2 ------------ BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} ------------ BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} ***** BB42 STMT00040 (IL 0x1C4...0x1D1) N022 ( 32, 35) [000222] -A-XG---R--- * ASG int N021 ( 1, 1) [000221] D------N---- +--* LCL_VAR int V09 loc5 d:3 N020 ( 32, 35) [000220] *--XG------- \--* IND int N019 ( 30, 33) [001009] ---XG--N---- \--* ADD byref $2ad N017 ( 29, 32) CSE #16 (use)[001020] ---XG------- +--* COMMA byref N004 ( 8, 11) [001013] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000217] ------------ | | +--* LCL_VAR int V09 loc5 u:2 $3c4 N003 ( 3, 3) CSE #08 (use)[001012] ---X-------- | | \--* ARR_LENGTH int N002 ( 1, 1) [000216] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [001023] ----G------- | \--* ADDR byref $91 N015 ( 11, 11) [000218] a---G--N---- | \--* IND struct N014 ( 10, 10) [001019] -------N---- | \--* ADD byref $91 N005 ( 1, 1) [001010] ------------ | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [001018] -------N---- | \--* ADD long $6e4 N011 ( 8, 8) [001016] -------N---- | +--* LSH long $6e3 N009 ( 7, 7) CSE #14 (use)[001022] ------------ | | +--* MUL long $6e2 N007 ( 2, 3) CSE #13 (use)[001014] ------------ | | | +--* CAST long <- int $6e1 N006 ( 1, 1) [001011] i----------- | | | | \--* LCL_VAR int V09 loc5 u:2 (last use) $3c4 N008 ( 1, 1) [001021] ------------ | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [001015] -------N---- | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [001017] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [001008] ------------ \--* CNS_INT long 20 field offset Fseq[next] $24c ***** BB42 STMT00041 (IL 0x1D3...0x1D6) N005 ( 3, 3) [000227] -A------R--- * ASG int $81a N004 ( 1, 1) [000226] D------N---- +--* LCL_VAR int V07 loc3 d:4 $81a N003 ( 3, 3) [000225] ------------ \--* ADD int $81a N001 ( 1, 1) [000223] ------------ +--* LCL_VAR int V07 loc3 u:3 (last use) $3c3 N002 ( 1, 1) [000224] ------------ \--* CNS_INT int 1 $c1 ***** BB42 STMT00042 (IL 0x1D7...0x1DB) N005 ( 7, 7) [000232] ---X-------- * JTRUE void N004 ( 5, 5) [000231] N--X---N-U-- \--* LT int N002 ( 3, 3) CSE #08 (use)[000230] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000229] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N003 ( 1, 1) [000228] ------------ \--* LCL_VAR int V07 loc3 u:4 $81a ------------ BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} ------------ BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} ***** BB44 STMT00166 (IL ???... ???) N005 ( 0, 0) [001181] -A------R--- * ASG int N004 ( 0, 0) [001179] D------N---- +--* LCL_VAR int V07 loc3 d:2 N003 ( 0, 0) [001180] ------------ \--* PHI int N001 ( 0, 0) [001237] ------------ pred BB23 +--* PHI_ARG int V07 loc3 u:5 $3c1 N002 ( 0, 0) [001228] ------------ pred BB32 \--* PHI_ARG int V07 loc3 u:3 $3c3 ***** BB44 STMT00015 (IL 0x1E4...0x1EB) N007 ( 8, 8) [000071] ---XG------- * JTRUE void N006 ( 6, 6) [000070] J--XG--N---- \--* LE int N004 ( 4, 4) [000068] ---XG------- +--* IND int N003 ( 2, 2) [001025] -------N---- | \--* ADD byref $28f N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001024] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N005 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 $c0 ------------ BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} ***** BB45 STMT00035 (IL 0x1ED...0x1F3) N006 ( 8, 7) [000174] -A-XG---R--- * ASG int N005 ( 3, 2) [000173] D------N---- +--* LCL_VAR int V10 loc6 d:3 N004 ( 4, 4) CSE #17 (def)[000172] ---XG------- \--* IND int N003 ( 2, 2) [001027] -------N---- \--* ADD byref $295 N001 ( 1, 1) [000171] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001026] ------------ \--* CNS_INT long 60 field offset Fseq[_freeList] $24d ***** BB45 STMT00120 (IL 0x1F5... ???) N034 ( 48, 47) [000688] -A-XG---R--- * ASG bool N033 ( 3, 2) [000687] D------N---- +--* LCL_VAR int V49 tmp35 d:1 N032 ( 44, 44) [000184] -A-XG------- \--* GE int N030 ( 39, 42) [000182] -A-XG------- +--* ADD int N028 ( 37, 40) [001050] -A-XG------- | +--* NEG int N027 ( 36, 39) [000181] *A-XG------- | | \--* IND int N026 ( 34, 37) [001029] -A-XG--N---- | | \--* ADD byref $29c N024 ( 33, 36) [001044] -A-XG------- | | +--* COMMA byref N006 ( 4, 4) [001032] -A-XG---R--- | | | +--* ASG int N005 ( 1, 1) [001031] D------N---- | | | | +--* LCL_VAR int V62 tmp48 d:1 N004 ( 4, 4) CSE #17 (use)[000178] ---XG------- | | | | \--* IND int N003 ( 2, 2) [001046] -------N---- | | | | \--* ADD byref $295 N001 ( 1, 1) [000177] ------------ | | | | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001045] ------------ | | | | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N023 ( 29, 32) [001043] ---XG------- | | | \--* COMMA byref N010 ( 8, 11) [001036] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [001033] ------------ | | | | +--* LCL_VAR int V62 tmp48 u:1 N009 ( 3, 3) CSE #08 (use)[001035] ---X-------- | | | | \--* ARR_LENGTH int N008 ( 1, 1) [000176] ------------ | | | | \--* LCL_VAR ref V04 loc0 u:1 N022 ( 21, 21) [001049] ----G------- | | | \--* ADDR byref $88 N021 ( 11, 11) [000179] a---G--N---- | | | \--* IND struct N020 ( 10, 10) [001042] -------N---- | | | \--* ADD byref $88 N011 ( 1, 1) [001030] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N019 ( 9, 9) [001041] -------N---- | | | \--* ADD long N017 ( 8, 8) [001039] -------N---- | | | +--* LSH long N015 ( 7, 7) [001048] ------------ | | | | +--* MUL long N013 ( 2, 3) [001037] ------------ | | | | | +--* CAST long <- int N012 ( 1, 1) [001034] i----------- | | | | | | \--* LCL_VAR int V62 tmp48 u:1 (last use) N014 ( 1, 1) [001047] ------------ | | | | | \--* CNS_INT long 3 $24b N016 ( 1, 1) [001038] -------N---- | | | | \--* CNS_INT long 3 $24b N018 ( 1, 1) [001040] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N025 ( 1, 1) [001028] ------------ | | \--* CNS_INT long 20 field offset Fseq[next] $24c N029 ( 1, 1) [000175] ------------ | \--* CNS_INT int -3 $e1 N031 ( 1, 1) [000183] ------------ \--* CNS_INT int -1 $c4 ***** BB45 STMT00123 (IL 0x1F5... ???) N004 ( 8, 15) [000698] -A--G---R--- * ASG ref $105 N003 ( 3, 2) [000697] D------N---- +--* LCL_VAR ref V50 tmp36 d:1 $105 N002 ( 4, 12) CSE #01 (use)[000684] #---G------- \--* IND ref $105 N001 ( 2, 10) [000683] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB45 STMT00121 (IL 0x1F5... ???) N004 ( 7, 6) [000693] ------------ * JTRUE void N003 ( 5, 4) [000692] J------N---- \--* NE int N001 ( 3, 2) [000690] ------------ +--* LCL_VAR int V49 tmp35 u:1 (last use) N002 ( 1, 1) [000691] ------------ \--* CNS_INT int 0 $c0 ------------ BB46 [1F5..1F6), preds={BB45} succs={BB47} ***** BB46 STMT00122 (IL 0x1F5... ???) N006 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N004 ( 4, 12) [001052] #---G------- arg0 in rcx +--* IND ref $114 N003 ( 2, 10) [001051] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" $5e N005 ( 3, 2) [000695] ------------ arg1 in rdx \--* LCL_VAR ref V50 tmp36 u:1 (last use) $105 ------------ BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} ***** BB47 STMT00037 (IL 0x219... ???) N035 ( 44, 47) [000200] -A-XG------- * ASG int $VN.Void N004 ( 4, 4) [000199] D--XG--N---- +--* IND int $732 N003 ( 2, 2) [001056] -------N---- | \--* ADD byref $295 N001 ( 1, 1) [000190] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001055] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N034 ( 39, 42) [000198] -A-XG------- \--* ADD int N032 ( 37, 40) [001079] -A-XG------- +--* NEG int N031 ( 36, 39) [000197] *A-XG------- | \--* IND int N030 ( 34, 37) [001058] -A-XG--N---- | \--* ADD byref $2a3 N028 ( 33, 36) [001073] -A-XG------- | +--* COMMA byref N010 ( 4, 4) [001061] -A-XG---R--- | | +--* ASG int N009 ( 1, 1) [001060] D------N---- | | | +--* LCL_VAR int V63 tmp49 d:1 N008 ( 4, 4) [000194] ---XG------- | | | \--* IND int N007 ( 2, 2) [001075] -------N---- | | | \--* ADD byref $295 N005 ( 1, 1) [000193] ------------ | | | +--* LCL_VAR ref V00 this u:1 $100 N006 ( 1, 1) [001074] ------------ | | | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N027 ( 29, 32) [001072] ---XG------- | | \--* COMMA byref N014 ( 8, 11) [001065] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N011 ( 1, 1) [001062] ------------ | | | +--* LCL_VAR int V63 tmp49 u:1 N013 ( 3, 3) CSE #08 (use)[001064] ---X-------- | | | \--* ARR_LENGTH int N012 ( 1, 1) [000192] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N026 ( 21, 21) [001078] ----G------- | | \--* ADDR byref $8a N025 ( 11, 11) [000195] a---G--N---- | | \--* IND struct N024 ( 10, 10) [001071] -------N---- | | \--* ADD byref $8a N015 ( 1, 1) [001059] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N023 ( 9, 9) [001070] -------N---- | | \--* ADD long N021 ( 8, 8) [001068] -------N---- | | +--* LSH long N019 ( 7, 7) [001077] ------------ | | | +--* MUL long N017 ( 2, 3) [001066] ------------ | | | | +--* CAST long <- int N016 ( 1, 1) [001063] i----------- | | | | | \--* LCL_VAR int V63 tmp49 u:1 (last use) N018 ( 1, 1) [001076] ------------ | | | | \--* CNS_INT long 3 $24b N020 ( 1, 1) [001067] -------N---- | | | \--* CNS_INT long 3 $24b N022 ( 1, 1) [001069] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N029 ( 1, 1) [001057] ------------ | \--* CNS_INT long 20 field offset Fseq[next] $24c N033 ( 1, 1) [000191] ------------ \--* CNS_INT int -3 $e1 ***** BB47 STMT00038 (IL 0x233...0x23C) N011 ( 11, 11) [000207] -A-XG---R--- * ASG int $VN.Void N010 ( 4, 4) [000206] D--XG--N---- +--* IND int $73a N009 ( 2, 2) [001081] -------N---- | \--* ADD byref $28f N007 ( 1, 1) [000201] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001080] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N006 ( 6, 6) [000205] ---XG------- \--* ADD int N004 ( 4, 4) [000203] ---XG------- +--* IND int N003 ( 2, 2) [001083] -------N---- | \--* ADD byref $28f N001 ( 1, 1) [000202] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001082] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N005 ( 1, 1) [000204] ------------ \--* CNS_INT int -1 $c4 ------------ BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} ***** BB48 STMT00016 (IL 0x243...0x249) N006 ( 8, 7) [000075] -A-XG---R--- * ASG int N005 ( 3, 2) [000074] D------N---- +--* LCL_VAR int V13 loc9 d:1 N004 ( 4, 4) CSE #18 (def)[000073] ---XG------- \--* IND int N003 ( 2, 2) [001085] -------N---- \--* ADD byref $290 N001 ( 1, 1) [000072] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001084] ------------ \--* CNS_INT long 56 field offset Fseq[_count] $244 ***** BB48 STMT00017 (IL 0x24B...0x250) N005 ( 9, 8) [000080] ---X-------- * JTRUE void N004 ( 7, 6) [000079] N--X---N-U-- \--* NE int N002 ( 3, 3) CSE #08 (use)[000078] ---X-------- +--* ARR_LENGTH int N001 ( 1, 1) [000077] ------------ | \--* LCL_VAR ref V04 loc0 u:1 (last use) N003 ( 3, 2) [000076] ------------ \--* LCL_VAR int V13 loc9 u:1 ------------ BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00125 (IL 0x252... ???) N014 ( 44, 26) [000705] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void N009 ( 22, 13) [001090] -ACXG---R-L- arg1 SETUP +--* ASG int $1d7 N008 ( 3, 2) [001089] D------N---- | +--* LCL_VAR int V64 tmp50 d:1 $1d7 N007 ( 18, 10) [000702] --CXG------- | \--* CALL int System.Collections.HashHelpers.ExpandPrime $1d7 N006 ( 4, 4) CSE #18 (use)[000701] ---XG------- arg0 in rcx | \--* IND int N005 ( 2, 2) [001087] -------N---- | \--* ADD byref $290 N003 ( 1, 1) [000700] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N004 ( 1, 1) [001086] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] $244 N011 ( 3, 2) [001091] ------------ arg1 in rdx +--* LCL_VAR int V64 tmp50 u:1 (last use) $1d7 N012 ( 1, 1) [000163] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N013 ( 1, 1) [000704] ------------ arg2 in r8 \--* CNS_INT int 0 $c0 ***** BB49 STMT00126 (IL 0x258... ???) N006 ( 8, 7) [000711] -A-XG---R--- * ASG ref N005 ( 3, 2) [000710] D------N---- +--* LCL_VAR ref V52 tmp38 d:1 N004 ( 4, 4) [000709] ---XG------- \--* IND ref N003 ( 2, 2) [001095] -------N---- \--* ADD byref $280 N001 ( 1, 1) [000165] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001094] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] $240 ***** BB49 STMT00133 (IL 0x258... ???) N004 ( 5, 4) [000760] -A-X----R--- * ASG int N003 ( 1, 1) [000759] D------N---- +--* LCL_VAR int V53 tmp39 d:1 N002 ( 5, 4) CSE #20 (def)[000714] ---X-------- \--* ARR_LENGTH int N001 ( 3, 2) [000713] ------------ \--* LCL_VAR ref V52 tmp38 u:1 ***** BB49 STMT00134 (IL 0x258... ???) N006 ( 8, 7) [000762] -A-XG---R--- * ASG long N005 ( 3, 2) [000761] D------N---- +--* LCL_VAR long V54 tmp40 d:1 N004 ( 4, 4) [000716] ---XG------- \--* IND long N003 ( 2, 2) [001097] -------N---- \--* ADD byref $283 N001 ( 1, 1) [000715] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001096] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 ***** BB49 STMT00136 (IL 0x258... ???) N005 ( 10, 9) [000773] -A------R--- * ASG bool N004 ( 3, 2) [000772] D------N---- +--* LCL_VAR int V56 tmp42 d:1 N003 ( 6, 6) [000730] N--------U-- \--* LE int N001 ( 1, 1) [000728] ------------ +--* LCL_VAR int V53 tmp39 u:1 N002 ( 1, 4) [000729] ------------ \--* CNS_INT int 0x7FFFFFFF $ce ***** BB49 STMT00139 (IL 0x258... ???) N004 ( 8, 15) [000783] -A--G---R--- * ASG ref $105 N003 ( 3, 2) [000782] D------N---- +--* LCL_VAR ref V57 tmp43 d:1 $105 N002 ( 4, 12) CSE #01 (use)[000767] #---G------- \--* IND ref $105 N001 ( 2, 10) [000766] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB49 STMT00140 (IL 0x258... ???) N004 ( 8, 15) [000785] -A--G---R--- * ASG ref $105 N003 ( 3, 2) [000784] D------N---- +--* LCL_VAR ref V58 tmp44 d:1 $105 N002 ( 4, 12) CSE #01 (use)[000769] #---G------- \--* IND ref $105 N001 ( 2, 10) [000768] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB49 STMT00137 (IL 0x258... ???) N004 ( 7, 6) [000778] ------------ * JTRUE void N003 ( 5, 4) [000777] J------N---- \--* NE int N001 ( 3, 2) [000775] ------------ +--* LCL_VAR int V56 tmp42 u:1 (last use) N002 ( 1, 1) [000776] ------------ \--* CNS_INT int 0 $c0 ------------ BB50 [258..259), preds={BB49} succs={BB51} ***** BB50 STMT00138 (IL 0x258... ???) N005 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 3, 2) [000779] ------------ arg0 in rcx +--* LCL_VAR ref V58 tmp44 u:1 (last use) $105 N004 ( 3, 2) [000780] ------------ arg1 in rdx \--* LCL_VAR ref V58 tmp44 u:1 (last use) $105 ------------ BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00131 (IL 0x258... ???) N016 ( 26, 25) [000750] -A------R--- * ASG int N015 ( 3, 2) [000749] D------N---- +--* LCL_VAR int V55 tmp41 d:1 N014 ( 22, 22) [000748] ------------ \--* CAST int <- uint <- long N013 ( 21, 20) [000747] ------------ \--* RSZ long N011 ( 19, 18) [000745] ------------ +--* MUL long N008 ( 13, 12) [000742] ------------ | +--* ADD long N006 ( 11, 10) [000739] ------------ | | +--* RSZ long N004 ( 9, 8) [000737] ------------ | | | +--* MUL long N001 ( 3, 2) [000735] ------------ | | | | +--* LCL_VAR long V54 tmp40 u:1 (last use) N003 ( 2, 3) CSE #19 (use)[000736] ---------U-- | | | | \--* CAST long <- ulong <- uint $310 N002 ( 1, 1) [000166] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 $3c0 N005 ( 1, 1) [000738] ------------ | | | \--* CNS_INT int 32 $d2 N007 ( 1, 1) [000741] ------------ | | \--* CNS_INT long 1 $247 N010 ( 2, 3) [000744] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000743] ------------ | \--* LCL_VAR int V53 tmp39 u:1 N012 ( 1, 1) [000746] ------------ \--* CNS_INT int 32 $d2 ***** BB51 STMT00142 (IL 0x258... ???) N007 ( 33, 11) [000796] -A-X----R--- * ASG bool N006 ( 3, 2) [000795] D------N---- +--* LCL_VAR int V59 tmp45 d:1 N005 ( 29, 8) [000755] ---X-------- \--* EQ int N003 ( 22, 5) [000754] ---X-------- +--* UMOD int N001 ( 1, 1) [000752] ------------ | +--* LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000753] ------------ | \--* LCL_VAR int V53 tmp39 u:1 (last use) N004 ( 3, 2) [000751] ------------ \--* LCL_VAR int V55 tmp41 u:1 ***** BB51 STMT00145 (IL 0x258... ???) N004 ( 8, 15) [000806] -A--G---R--- * ASG ref $105 N003 ( 3, 2) [000805] D------N---- +--* LCL_VAR ref V60 tmp46 d:1 $105 N002 ( 4, 12) CSE #01 (use)[000790] #---G------- \--* IND ref $105 N001 ( 2, 10) [000789] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB51 STMT00146 (IL 0x258... ???) N004 ( 8, 15) [000808] -A--G---R--- * ASG ref $105 N003 ( 3, 2) [000807] D------N---- +--* LCL_VAR ref V61 tmp47 d:1 $105 N002 ( 4, 12) CSE #01 (use)[000792] #---G------- \--* IND ref $105 N001 ( 2, 10) [000791] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 ***** BB51 STMT00143 (IL 0x258... ???) N004 ( 7, 6) [000801] ------------ * JTRUE void N003 ( 5, 4) [000800] J------N---- \--* NE int N001 ( 3, 2) [000798] ------------ +--* LCL_VAR int V59 tmp45 u:1 (last use) N002 ( 1, 1) [000799] ------------ \--* CNS_INT int 0 $c0 ------------ BB52 [258..259), preds={BB51} succs={BB53} ***** BB52 STMT00144 (IL 0x258... ???) N005 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 3, 2) [000802] ------------ arg0 in rcx +--* LCL_VAR ref V61 tmp47 u:1 (last use) $105 N004 ( 3, 2) [000803] ------------ arg1 in rdx \--* LCL_VAR ref V61 tmp47 u:1 (last use) $105 ------------ BB53 [258..259), preds={BB51,BB52} succs={BB54} ***** BB53 STMT00128 (IL 0x258... ???) N017 ( 35, 33) [000722] -A-XG---R--- * ASG byref N016 ( 3, 2) [000721] D------N---- +--* LCL_VAR byref V51 tmp37 d:1 $87 N015 ( 31, 30) [001112] ---XG------- \--* COMMA byref N004 ( 12, 13) [001105] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 3, 2) [000758] ------------ | +--* LCL_VAR int V55 tmp41 u:1 N003 ( 5, 4) CSE #20 (use)[001104] ---X-------- | \--* ARR_LENGTH int N002 ( 3, 2) [000712] ------------ | \--* LCL_VAR ref V52 tmp38 u:1 N014 ( 19, 17) [001113] ----G------- \--* ADDR byref $87 N013 ( 10, 9) [000719] a---G--N---- \--* IND int N012 ( 9, 8) [001111] -------N---- \--* ADD byref $87 N005 ( 3, 2) [001102] ------------ +--* LCL_VAR ref V52 tmp38 u:1 (last use) N011 ( 6, 6) [001110] -------N---- \--* ADD long N009 ( 5, 5) [001108] -------N---- +--* LSH long N007 ( 4, 4) [001106] ------------ | +--* CAST long <- int N006 ( 3, 2) [001103] i----------- | | \--* LCL_VAR int V55 tmp41 u:1 (last use) N008 ( 1, 1) [001107] -------N---- | \--* CNS_INT long 2 $248 N010 ( 1, 1) [001109] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB53 STMT00034 (IL ???... ???) N003 ( 7, 5) [000170] -A------R--- * ASG byref $87 N002 ( 3, 2) [000169] D------N---- +--* LCL_VAR byref V08 loc4 d:4 $87 N001 ( 3, 2) [000723] ------------ \--* LCL_VAR byref V51 tmp37 u:1 (last use) $87 ------------ BB54 [261..276), preds={BB48,BB53} succs={BB55} ***** BB54 STMT00170 (IL ???... ???) N005 ( 0, 0) [001193] -A------R--- * ASG byref N004 ( 0, 0) [001191] D------N---- +--* LCL_VAR byref V08 loc4 d:3 N003 ( 0, 0) [001192] ------------ \--* PHI byref N001 ( 0, 0) [001224] ------------ pred BB53 +--* PHI_ARG byref V08 loc4 u:4 $87 N002 ( 0, 0) [001220] ------------ pred BB48 \--* PHI_ARG byref V08 loc4 u:1 $81 ***** BB54 STMT00018 (IL 0x261...0x263) N003 ( 7, 5) [000083] -A------R--- * ASG int N002 ( 3, 2) [000082] D------N---- +--* LCL_VAR int V10 loc6 d:2 N001 ( 3, 2) [000081] ------------ \--* LCL_VAR int V13 loc9 u:1 ***** BB54 STMT00019 (IL 0x265...0x26A) N008 ( 10, 9) [000089] -A-XG---R--- * ASG int $VN.Void N007 ( 4, 4) [000088] D--XG--N---- +--* IND int $708 N006 ( 2, 2) [001115] -------N---- | \--* ADD byref $290 N004 ( 1, 1) [000084] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N005 ( 1, 1) [001114] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] $244 N003 ( 5, 4) [000087] ------------ \--* ADD int N001 ( 3, 2) [000085] ------------ +--* LCL_VAR int V10 loc6 u:2 (last use) N002 ( 1, 1) [000086] ------------ \--* CNS_INT int 1 $c1 ***** BB54 STMT00020 (IL 0x26F...0x275) N006 ( 4, 4) [000093] -A-XG---R--- * ASG ref N005 ( 1, 1) [000092] D------N---- +--* LCL_VAR ref V04 loc0 d:3 N004 ( 4, 4) [000091] ---XG------- \--* IND ref N003 ( 2, 2) [001117] -------N---- \--* ADD byref $281 N001 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001116] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] $241 ------------ BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} ***** BB55 STMT00171 (IL ???... ???) N005 ( 0, 0) [001196] -A------R--- * ASG byref N004 ( 0, 0) [001194] D------N---- +--* LCL_VAR byref V08 loc4 d:2 N003 ( 0, 0) [001195] ------------ \--* PHI byref N001 ( 0, 0) [001225] ------------ pred BB47 +--* PHI_ARG byref V08 loc4 u:1 $81 N002 ( 0, 0) [001221] ------------ pred BB54 \--* PHI_ARG byref V08 loc4 u:3 $780 ***** BB55 STMT00169 (IL ???... ???) N005 ( 0, 0) [001190] -A------R--- * ASG ref N004 ( 0, 0) [001188] D------N---- +--* LCL_VAR ref V04 loc0 d:2 N003 ( 0, 0) [001189] ------------ \--* PHI ref N001 ( 0, 0) [001226] ------------ pred BB47 +--* PHI_ARG ref V04 loc0 u:1 N002 ( 0, 0) [001222] ------------ pred BB54 \--* PHI_ARG ref V04 loc0 u:3 ***** BB55 STMT00168 (IL ???... ???) N005 ( 0, 0) [001187] -A------R--- * ASG int N004 ( 0, 0) [001185] D------N---- +--* LCL_VAR int V10 loc6 d:1 N003 ( 0, 0) [001186] ------------ \--* PHI int N001 ( 0, 0) [001227] ------------ pred BB47 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [001223] ------------ pred BB54 \--* PHI_ARG int V10 loc6 u:2 ***** BB55 STMT00021 (IL 0x276...0x27E) N019 ( 39, 38) [000099] -A-XG---R--- * ASG byref $2a6 N018 ( 3, 2) [000098] D------N---- +--* LCL_VAR byref V11 loc7 d:1 $8c N017 ( 35, 35) [001128] ---XG------- \--* COMMA byref $2a6 N004 ( 10, 12) [001121] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $7cd N001 ( 3, 2) [000095] ------------ | +--* LCL_VAR int V10 loc6 u:1 $3cc N003 ( 3, 3) CSE #21 (def)[001120] ---X-------- | \--* ARR_LENGTH int $73d N002 ( 1, 1) [000094] ------------ | \--* LCL_VAR ref V04 loc0 u:2 $684 N016 ( 25, 23) [001131] ----G------- \--* ADDR byref $8c N015 ( 13, 12) [000096] a---G--N---- \--* IND struct N014 ( 12, 11) [001127] -------N---- \--* ADD byref $8c N005 ( 1, 1) [001118] ------------ +--* LCL_VAR ref V04 loc0 u:2 $684 N013 ( 11, 10) [001126] -------N---- \--* ADD long $6df N011 ( 10, 9) [001124] -------N---- +--* LSH long $6de N009 ( 9, 8) [001130] ------------ | +--* MUL long $6dd N007 ( 4, 4) [001122] ------------ | | +--* CAST long <- int $6dc N006 ( 3, 2) [001119] i----------- | | | \--* LCL_VAR int V10 loc6 u:1 $3cc N008 ( 1, 1) [001129] ------------ | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [001123] -------N---- | \--* CNS_INT long 3 $24b N012 ( 1, 1) [001125] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB55 STMT00022 (IL 0x280...0x283) N006 ( 8, 7) [000103] -A-XG------- * ASG int $VN.Void N004 ( 6, 5) [000102] *--XG--N---- +--* IND int $3c0 N003 ( 4, 3) [001133] -------N---- | \--* ADD byref $8d N001 ( 3, 2) [000100] ------------ | +--* LCL_VAR byref V11 loc7 u:1 $8c N002 ( 1, 1) [001132] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N005 ( 1, 1) [000101] ------------ \--* LCL_VAR int V06 loc2 u:1 (last use) $3c0 ***** BB55 STMT00023 (IL 0x288...0x28F) N009 ( 15, 12) [000110] -A-XG---R--- * ASG int $VN.Void N008 ( 6, 5) [000109] *--XG--N---- +--* IND int N007 ( 4, 3) [001135] -------N---- | \--* ADD byref $8e N005 ( 3, 2) [000104] ------------ | +--* LCL_VAR byref V11 loc7 u:1 $8c N006 ( 1, 1) [001134] ------------ | \--* CNS_INT long 20 field offset Fseq[next] $24c N004 ( 8, 6) [000108] ---XG------- \--* ADD int N002 ( 6, 4) [000106] *--XG------- +--* IND int N001 ( 3, 2) [000105] ------------ | \--* LCL_VAR byref V08 loc4 u:2 $781 N003 ( 1, 1) [000107] ------------ \--* CNS_INT int -1 $c4 ***** BB55 STMT00024 (IL 0x294...0x297) N004 ( 8, 6) [000114] -A-XG------- * ASG ref $VN.Void N002 ( 6, 4) [000113] *--XG--N---- +--* IND ref $101 N001 ( 3, 2) [000111] ------------ | \--* LCL_VAR byref V11 loc7 u:1 Zero Fseq[key] $8f N003 ( 1, 1) [000112] ------------ \--* LCL_VAR ref V01 arg1 u:1 (last use) $101 ***** BB55 STMT00025 (IL 0x29C...0x29F) N006 ( 8, 7) [000118] -A-XG------- * ASG ref $VN.Void N004 ( 6, 5) [000117] *--XG--N---- +--* IND ref $102 N003 ( 4, 3) [001137] -------N---- | \--* ADD byref $90 N001 ( 3, 2) [000115] ------------ | +--* LCL_VAR byref V11 loc7 u:1 (last use) $8c N002 ( 1, 1) [001136] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N005 ( 1, 1) [000116] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 ***** BB55 STMT00026 (IL 0x2A4...0x2AA) N006 ( 12, 9) [000124] -A-XG---R--- * ASG int $VN.Void N005 ( 6, 4) [000123] *--X---N---- +--* IND int $804 N004 ( 3, 2) [000119] ------------ | \--* LCL_VAR byref V08 loc4 u:2 (last use) $781 N003 ( 5, 4) [000122] ------------ \--* ADD int $804 N001 ( 3, 2) [000120] ------------ +--* LCL_VAR int V10 loc6 u:1 (last use) $3cc N002 ( 1, 1) [000121] ------------ \--* CNS_INT int 1 $c1 ***** BB55 STMT00027 (IL 0x2AB...0x2B4) N011 ( 11, 11) [000131] -A-XG---R--- * ASG int $VN.Void N010 ( 4, 4) [000130] D--XG--N---- +--* IND int $80a N009 ( 2, 2) [001139] -------N---- | \--* ADD byref $2a7 N007 ( 1, 1) [000125] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001138] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] $24e N006 ( 6, 6) [000129] ---XG------- \--* ADD int N004 ( 4, 4) [000127] ---XG------- +--* IND int N003 ( 2, 2) [001141] -------N---- | \--* ADD byref $2a7 N001 ( 1, 1) [000126] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001140] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] $24e N005 ( 1, 1) [000128] ------------ \--* CNS_INT int 1 $c1 ***** BB55 STMT00028 (IL 0x2CA...0x2CD) N004 ( 5, 5) [000148] ------------ * JTRUE void N003 ( 3, 3) [000147] N------N-U-- \--* LE int $80d N001 ( 1, 1) [000145] ------------ +--* LCL_VAR int V07 loc3 u:2 (last use) $3c5 N002 ( 1, 1) [000146] ------------ \--* CNS_INT int 100 $e3 ------------ BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} ***** BB56 STMT00030 (IL 0x2CF...0x2D5) N008 ( 21, 22) [000156] --C-G------- * JTRUE void N007 ( 19, 20) [000155] J-C-G--N---- \--* EQ int N005 ( 17, 18) [000153] --C-G------- +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS N003 ( 1, 1) [000151] ------------ arg1 in rdx | +--* LCL_VAR ref V05 loc1 u:1 (last use) N004 ( 2, 10) [000152] H------N---- arg0 in rcx | \--* CNS_INT(h) long 0xd1ffab1e class $62 N006 ( 1, 1) [000154] ------------ \--* CNS_INT ref null $VN.Null ------------ BB57 [2D7..2E3), preds={BB56} succs={BB58} ***** BB57 STMT00031 (IL 0x2D7...0x2DC) N008 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void N005 ( 3, 3) CSE #21 (use)[000159] ---X-------- arg1 in rdx +--* ARR_LENGTH int $73d N004 ( 1, 1) [000158] ------------ | \--* LCL_VAR ref V04 loc0 u:2 (last use) $684 N006 ( 1, 1) [000157] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N007 ( 1, 1) [000160] ------------ arg2 in r8 \--* CNS_INT int 1 $c1 ------------ BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} ***** BB58 STMT00147 (IL ???... ???) N002 ( 2, 2) [000810] ------------ * RETURN int $1f4 N001 ( 1, 1) [000482] ------------ \--* CNS_INT int 1 $c1 ------------ BB59 [008..00E) (throw), preds={BB01} succs={} ***** BB59 STMT00086 (IL 0x008...0x009) N003 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException $VN.Void N002 ( 1, 1) [000532] ------------ arg0 in rcx \--* CNS_INT int 4 $c5 ------------ BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} ***** BB60 STMT00073 (IL 0x14F...0x150) N004 ( 7, 5) [000444] -A-X----R--- * ASG long $2e8 N003 ( 3, 2) [000443] D------N---- +--* LCL_VAR long V26 tmp12 d:1 $2e7 N002 ( 3, 2) CSE #06 (use)[000442] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000441] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB60 STMT00155 (IL ???... ???) N011 ( 16, 14) [001158] ------------ * JTRUE void N010 ( 14, 12) [000460] J------N---- \--* EQ int N008 ( 12, 10) CSE #22 (def)[000456] n----------- +--* IND long N007 ( 10, 8) [000452] -------N---- | \--* ADD long $331 N005 ( 9, 7) CSE #03 (use)[000450] #----------- | +--* IND long $2ea N004 ( 6, 5) CSE #02 (use)[000449] #----------- | | \--* IND long $2e9 N003 ( 4, 3) [000448] -------N---- | | \--* ADD long $306 N001 ( 3, 2) [000446] ------------ | | +--* LCL_VAR long V26 tmp12 u:1 $2e7 N002 ( 1, 1) [000447] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000451] ------------ | \--* CNS_INT long 56 $244 N009 ( 1, 1) [000459] ------------ \--* CNS_INT long 0 $243 ------------ BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} ***** BB61 STMT00156 (IL ???... ???) N010 ( 16, 13) [001160] -A------R--- * ASG long N009 ( 3, 2) [001159] D------N---- +--* LCL_VAR long V28 tmp14 d:3 N008 ( 12, 10) CSE #22 (use)[000461] n-----?----- \--* IND long N007 ( 10, 8) [000462] ------?N---- \--* ADD long $331 N005 ( 9, 7) CSE #03 (use)[000463] #-----?----- +--* IND long $2ea N004 ( 6, 5) CSE #02 (use)[000464] #-----?----- | \--* IND long $2e9 N003 ( 4, 3) [000465] ------?N---- | \--* ADD long $306 N001 ( 3, 2) [000466] ------?----- | +--* LCL_VAR long V26 tmp12 u:1 (last use) $2e7 N002 ( 1, 1) [000467] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000468] ------?----- \--* CNS_INT long 56 $244 ------------ BB62 [???..???), preds={BB60} succs={BB63} ***** BB62 STMT00157 (IL ???... ???) N007 ( 23, 22) [001162] -AC-G---R--- * ASG long $332 N006 ( 3, 2) [001161] D------N---- +--* LCL_VAR long V28 tmp14 d:2 $332 N005 ( 19, 19) CSE #24 (def)[000458] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 N003 ( 3, 2) [000445] ------?----- arg0 in rcx +--* LCL_VAR long V26 tmp12 u:1 (last use) $2e7 N004 ( 2, 10) [000457] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $52 ------------ BB63 [???..157) (throw), preds={BB61,BB62} succs={} ***** BB63 STMT00167 (IL ???... ???) N005 ( 0, 0) [001184] -A------R--- * ASG long N004 ( 0, 0) [001182] D------N---- +--* LCL_VAR long V28 tmp14 d:1 N003 ( 0, 0) [001183] ------------ \--* PHI long N001 ( 0, 0) [001241] ------------ pred BB61 +--* PHI_ARG long V28 tmp14 u:3 N002 ( 0, 0) [001240] ------------ pred BB62 \--* PHI_ARG long V28 tmp14 u:2 $332 ***** BB63 STMT00076 (IL ???... ???) N005 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void N003 ( 3, 2) [000473] ------------ arg0 in rcx +--* LCL_VAR long V28 tmp14 u:1 (last use) $347 N004 ( 1, 1) [000455] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) $101 ------------ BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} ***** BB64 STMT00053 (IL 0x1BC...0x1BD) N004 ( 7, 5) [000299] -A-X----R--- * ASG long $2e8 N003 ( 3, 2) [000298] D------N---- +--* LCL_VAR long V21 tmp7 d:1 $2e7 N002 ( 3, 2) CSE #06 (use)[000297] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000296] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB64 STMT00161 (IL ???... ???) N011 ( 16, 14) [001168] ------------ * JTRUE void N010 ( 14, 12) [000315] J------N---- \--* EQ int N008 ( 12, 10) CSE #23 (def)[000311] n----------- +--* IND long N007 ( 10, 8) [000307] -------N---- | \--* ADD long $331 N005 ( 9, 7) CSE #03 (use)[000305] #----------- | +--* IND long $2ea N004 ( 6, 5) CSE #02 (use)[000304] #----------- | | \--* IND long $2e9 N003 ( 4, 3) [000303] -------N---- | | \--* ADD long $306 N001 ( 3, 2) [000301] ------------ | | +--* LCL_VAR long V21 tmp7 u:1 $2e7 N002 ( 1, 1) [000302] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000306] ------------ | \--* CNS_INT long 56 $244 N009 ( 1, 1) [000314] ------------ \--* CNS_INT long 0 $243 ------------ BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} ***** BB65 STMT00162 (IL ???... ???) N010 ( 16, 13) [001170] -A------R--- * ASG long N009 ( 3, 2) [001169] D------N---- +--* LCL_VAR long V23 tmp9 d:3 N008 ( 12, 10) CSE #23 (use)[000316] n-----?----- \--* IND long N007 ( 10, 8) [000317] ------?N---- \--* ADD long $331 N005 ( 9, 7) CSE #03 (use)[000318] #-----?----- +--* IND long $2ea N004 ( 6, 5) CSE #02 (use)[000319] #-----?----- | \--* IND long $2e9 N003 ( 4, 3) [000320] ------?N---- | \--* ADD long $306 N001 ( 3, 2) [000321] ------?----- | +--* LCL_VAR long V21 tmp7 u:1 (last use) $2e7 N002 ( 1, 1) [000322] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000323] ------?----- \--* CNS_INT long 56 $244 ------------ BB66 [???..???), preds={BB64} succs={BB67} ***** BB66 STMT00163 (IL ???... ???) N007 ( 23, 22) [001172] -AC-G---R--- * ASG long $332 N006 ( 3, 2) [001171] D------N---- +--* LCL_VAR long V23 tmp9 d:2 $332 N005 ( 19, 19) CSE #24 (def)[000313] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 N003 ( 3, 2) [000300] ------?----- arg0 in rcx +--* LCL_VAR long V21 tmp7 u:1 (last use) $2e7 N004 ( 2, 10) [000312] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $52 ------------ BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} ***** BB67 STMT00173 (IL ???... ???) N005 ( 0, 0) [001202] -A------R--- * ASG long N004 ( 0, 0) [001200] D------N---- +--* LCL_VAR long V23 tmp9 d:1 N003 ( 0, 0) [001201] ------------ \--* PHI long N001 ( 0, 0) [001232] ------------ pred BB65 +--* PHI_ARG long V23 tmp9 u:3 N002 ( 0, 0) [001231] ------------ pred BB66 \--* PHI_ARG long V23 tmp9 u:2 $332 ***** BB67 STMT00056 (IL ???... ???) N005 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void N003 ( 3, 2) [000328] ------------ arg0 in rcx +--* LCL_VAR long V23 tmp9 u:1 (last use) $34b N004 ( 1, 1) [000310] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) $101 ------------ BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} ***** BB68 STMT00043 (IL 0x1DD...0x1E2) N001 ( 14, 5) [000233] --CXG------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported $VN.Void ------------------------------------------------------------------------------------------------------------------- Aggressive CSE Promotion cutoff is 450.000000 Moderate CSE Promotion cutoff is 300.000000 enregCount is 64 Framesize estimate is 0x0088 We have a large frame Sorted CSE candidates: CSE #11, {$28b, $457} useCnt=2: [def=400.000000, use=450.000000, cost= 29, call] :: N017 ( 29, 32) CSE #11 (def)[000879] ---XG------- * COMMA byref CSE #16, {$2ab, $7de} useCnt=2: [def=400.000000, use=450.000000, cost= 29, call] :: N017 ( 29, 32) CSE #16 (def)[000959] ---XG------- * COMMA byref CSE #24, {$332, $4 } useCnt=0: [def=0.000000, use=0.000000, cost= 19 ] :: N005 ( 19, 19) CSE #24 (def)[000458] --C-G-?----- * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 CSE #22, {$346, $4 } useCnt=1: [def=0.000000, use=0.000000, cost= 12 ] :: N008 ( 12, 10) CSE #22 (def)[000456] n----------- * IND long CSE #23, {$34a, $4 } useCnt=1: [def=0.000000, use=0.000000, cost= 12 ] :: N008 ( 12, 10) CSE #23 (def)[000311] n----------- * IND long CSE #15, {$348, $4 } useCnt=1: [def=200.000000, use=100.000000, cost= 10 ] :: N008 ( 10, 9) CSE #15 (def)[000259] n----------- * IND long CSE #04, {$341, $4 } useCnt=1: [def=50.000000, use=25.000000, cost= 10 ] :: N008 ( 10, 9) CSE #04 (def)[000501] n----------- * IND long CSE #07, {$343, $4 } useCnt=1: [def=50.000000, use=25.000000, cost= 10 ] :: N008 ( 10, 9) CSE #07 (def)[000365] n----------- * IND long CSE #10, {$327, $4 } useCnt=3: [def=400.000000, use=650.000000, cost= 7, call] :: N009 ( 7, 7) CSE #10 (def)[000881] ------------ * MUL long $327 CSE #14, {$6e2, $4 } useCnt=3: [def=400.000000, use=650.000000, cost= 7, call] :: N009 ( 7, 7) CSE #14 (def)[000961] ------------ * MUL long $6e2 CSE #03, {$2ea, $4 } useCnt=7: [def=300.000000, use=150.000000, cost= 7, call] :: N005 ( 7, 6) CSE #03 (def)[000495] #----------- * IND long $2ea CSE #20, {$405, $477} useCnt=1: [def=50.000000, use=50.000000, cost= 5, call] :: N002 ( 5, 4) CSE #20 (def)[000714] ---X-------- * ARR_LENGTH int CSE #01, {$105, $4 } useCnt=11: [def=100.000000, use=850.000000, cost= 4, call] :: N002 ( 4, 12) CSE #01 (def)[000538] #---G------- * IND ref $105 CSE #02, {$2e9, $4 } useCnt=7: [def=300.000000, use=150.000000, cost= 4, call] :: N004 ( 4, 4) CSE #02 (def)[000494] #----------- * IND long $2e9 CSE #17, {$71a, $2c2} useCnt=1: [def=50.000000, use=50.000000, cost= 4 ] :: N004 ( 4, 4) CSE #17 (def)[000172] ---XG------- * IND int CSE #18, {$62c, $2c2} useCnt=1: [def=50.000000, use=50.000000, cost= 4 ] :: N004 ( 4, 4) CSE #18 (def)[000073] ---XG------- * IND int CSE #08, {$403, $44f} useCnt=13: [def=800.000000, use=3050.000000, cost= 3, call] :: N002 ( 3, 3) CSE #08 (def)[000389] ---X-------- * ARR_LENGTH int CSE #05, {$401, $2f4} useCnt=1: [def=100.000000, use=100.000000, cost= 3, call] :: N002 ( 3, 3) CSE #05 (def)[000583] ---X-------- * ARR_LENGTH int CSE #12, {$1be, $4 } useCnt=2: [def=100.000000, use=100.000000, cost= 3 ] :: N002 ( 3, 4) CSE #12 (def)[000909] ------------ * CAST int <- ubyte <- int $1be CSE #21, {$40a, $7c8} useCnt=1: [def=50.000000, use=50.000000, cost= 3, call] :: N003 ( 3, 3) CSE #21 (def)[001120] ---X-------- * ARR_LENGTH int $73d CSE #06, {$2e7, $2c2} useCnt=2: [def=300.000000, use=0.000000, cost= 3, call] :: N002 ( 3, 2) CSE #06 (def)[000487] #--X-------- * IND long $2e8 CSE #09, {$326, $4 } useCnt=3: [def=400.000000, use=650.000000, cost= 2, call] :: N007 ( 2, 3) CSE #09 (def)[000873] ------------ * CAST long <- int $326 CSE #13, {$6e1, $4 } useCnt=3: [def=400.000000, use=650.000000, cost= 2, call] :: N007 ( 2, 3) CSE #13 (def)[000953] ------------ * CAST long <- int $6e1 CSE #19, {$310, $4 } useCnt=1: [def=100.000000, use=50.000000, cost= 2, call] :: N003 ( 2, 3) CSE #19 (def)[000605] ---------U-- * CAST long <- ulong <- uint $310 Considering CSE #11 {$28b, $457} [def=400.000000, use=450.000000, cost= 29, call] CSE Expression : N017 ( 29, 32) CSE #11 (def)[000879] ---XG------- * COMMA byref N004 ( 8, 11) [000872] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000393] ------------ | +--* LCL_VAR int V09 loc5 u:4 $3c2 N003 ( 3, 3) CSE #08 (use)[000871] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000392] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000882] ----G------- \--* ADDR byref $82 N015 ( 11, 11) [000394] a---G--N---- \--* IND struct N014 ( 10, 10) [000878] -------N---- \--* ADD byref $82 N005 ( 1, 1) [000869] ------------ +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000877] -------N---- \--* ADD long $329 N011 ( 8, 8) [000875] -------N---- +--* LSH long $328 N009 ( 7, 7) CSE #10 (def)[000881] ------------ | +--* MUL long $327 N007 ( 2, 3) CSE #09 (def)[000873] ------------ | | +--* CAST long <- int $326 N006 ( 1, 1) [000870] i----------- | | | \--* LCL_VAR int V09 loc5 u:4 $3c2 N008 ( 1, 1) [000880] ------------ | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000874] -------N---- | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000876] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 Aggressive CSE Promotion (1250.000000 >= 450.000000) cseRefCnt=1250.000000, aggressiveRefCnt=450.000000, moderateRefCnt=300.000000 defCnt=400.000000, useCnt=450.000000, cost=29, size=32, LiveAcrossCall def_cost=1, use_cost=1, extra_no_cost=124, extra_yes_cost=0 CSE cost savings check (13174.000000 >= 850.000000) passes Promoting CSE: lvaGrabTemp returning 65 (V65 rat0) (a long lifetime temp) called for CSE - aggressive. CSE #11 is single-def, so associated CSE temp V65 will be in SSA New refCnts for V65: refCnt = 2, refCntWtd = 8 New refCnts for V65: refCnt = 3, refCntWtd = 12 New refCnts for V65: refCnt = 4, refCntWtd = 12.50 CSE #11 def at [000879] replaced in BB24 with def of V65 optValnumCSE morphed tree: N027 ( 37, 40) [000399] -A-XG------- * JTRUE void N026 ( 35, 38) [000398] NA-XG--N-U-- \--* NE int N024 ( 33, 36) [000396] *A-XG------- +--* IND int N023 ( 31, 34) [000868] -A-XG--N---- | \--* ADD byref $28c N021 ( 30, 33) [001251] -A-XG------- | +--* COMMA byref N019 ( 29, 32) [001249] -A-XG---R--- | | +--* ASG byref $VN.Void N018 ( 1, 1) [001248] D------N---- | | | +--* LCL_VAR byref V65 cse0 d:1 N017 ( 29, 32) [000879] ---XG------- | | | \--* COMMA byref N004 ( 8, 11) [000872] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000393] ------------ | | | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N003 ( 3, 3) CSE #08 (use)[000871] ---X-------- | | | | \--* ARR_LENGTH int N002 ( 1, 1) [000392] ------------ | | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000882] ----G------- | | | \--* ADDR byref $82 N015 ( 11, 11) [000394] a---G--N---- | | | \--* IND struct N014 ( 10, 10) [000878] -------N---- | | | \--* ADD byref $82 N005 ( 1, 1) [000869] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000877] -------N---- | | | \--* ADD long $329 N011 ( 8, 8) [000875] -------N---- | | | +--* LSH long $328 N009 ( 7, 7) CSE #10 (def)[000881] ------------ | | | | +--* MUL long $327 N007 ( 2, 3) CSE #09 (def)[000873] ------------ | | | | | +--* CAST long <- int $326 N006 ( 1, 1) [000870] i----------- | | | | | | \--* LCL_VAR int V09 loc5 u:4 $3c2 N008 ( 1, 1) [000880] ------------ | | | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000874] -------N---- | | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000876] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N020 ( 1, 1) [001250] ------------ | | \--* LCL_VAR byref V65 cse0 u:1 N022 ( 1, 1) [000867] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N025 ( 1, 1) [000397] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 Working on the replacement of the CSE #11 use at [000943] in BB26 Unmark CSE use #08 at [000935]: 13 -> 12 Unmark CSE use #10 at [000945]: 3 -> 2 Unmark CSE use #09 at [000937]: 3 -> 2 optValnumCSE morphed tree: N006 ( 4, 4) [000406] -A-XG---R--- * ASG int N005 ( 1, 1) [000405] D------N---- +--* LCL_VAR int V09 loc5 d:5 N004 ( 4, 4) [000404] *--XG------- \--* IND int N003 ( 2, 2) [000932] ----G--N---- \--* ADD byref $28e N001 ( 1, 1) [001252] ------------ +--* LCL_VAR byref V65 cse0 u:1 $82 N002 ( 1, 1) [000931] ------------ \--* CNS_INT long 20 field offset Fseq[next] $24c Working on the replacement of the CSE #11 use at [000922] in BB29 Unmark CSE use #08 at [000914]: 12 -> 11 Unmark CSE use #10 at [000924]: 2 -> 1 Unmark CSE use #09 at [000916]: 2 -> 1 optValnumCSE morphed tree: N006 ( 6, 6) [000481] -A-XG------- * ASG ref $VN.Void N004 ( 4, 4) [000480] *--XG--N---- +--* IND ref $102 N003 ( 2, 2) [000911] ----G--N---- | \--* ADD byref $28d N001 ( 1, 1) [001253] ------------ | +--* LCL_VAR byref V65 cse0 u:1 $82 N002 ( 1, 1) [000910] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N005 ( 1, 1) [000479] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 Considering CSE #16 {$2ab, $7de} [def=400.000000, use=450.000000, cost= 29, call] CSE Expression : N017 ( 29, 32) CSE #16 (def)[000959] ---XG------- * COMMA byref N004 ( 8, 11) [000952] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000209] ------------ | +--* LCL_VAR int V09 loc5 u:2 $3c4 N003 ( 3, 3) CSE #08 (use)[000951] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000208] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000962] ----G------- \--* ADDR byref $91 N015 ( 11, 11) [000210] a---G--N---- \--* IND struct N014 ( 10, 10) [000958] -------N---- \--* ADD byref $91 N005 ( 1, 1) [000949] ------------ +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000957] -------N---- \--* ADD long $6e4 N011 ( 8, 8) [000955] -------N---- +--* LSH long $6e3 N009 ( 7, 7) CSE #14 (def)[000961] ------------ | +--* MUL long $6e2 N007 ( 2, 3) CSE #13 (def)[000953] ------------ | | +--* CAST long <- int $6e1 N006 ( 1, 1) [000950] i----------- | | | \--* LCL_VAR int V09 loc5 u:2 $3c4 N008 ( 1, 1) [000960] ------------ | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000954] -------N---- | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000956] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 Aggressive CSE Promotion (1250.000000 >= 550.000000) cseRefCnt=1250.000000, aggressiveRefCnt=550.000000, moderateRefCnt=350.000000 defCnt=400.000000, useCnt=450.000000, cost=29, size=32, LiveAcrossCall def_cost=1, use_cost=1, extra_no_cost=124, extra_yes_cost=0 CSE cost savings check (13174.000000 >= 850.000000) passes Promoting CSE: lvaGrabTemp returning 66 (V66 rat0) (a long lifetime temp) called for CSE - aggressive. CSE #16 is single-def, so associated CSE temp V66 will be in SSA New refCnts for V66: refCnt = 2, refCntWtd = 8 New refCnts for V66: refCnt = 3, refCntWtd = 8.50 New refCnts for V66: refCnt = 4, refCntWtd = 12.50 CSE #16 def at [000959] replaced in BB33 with def of V66 optValnumCSE morphed tree: N027 ( 37, 40) [000215] -A-XG------- * JTRUE void N026 ( 35, 38) [000214] NA-XG--N-U-- \--* NE int N024 ( 33, 36) [000212] *A-XG------- +--* IND int N023 ( 31, 34) [000948] -A-XG--N---- | \--* ADD byref $2ac N021 ( 30, 33) [001257] -A-XG------- | +--* COMMA byref N019 ( 29, 32) [001255] -A-XG---R--- | | +--* ASG byref $VN.Void N018 ( 1, 1) [001254] D------N---- | | | +--* LCL_VAR byref V66 cse1 d:1 N017 ( 29, 32) [000959] ---XG------- | | | \--* COMMA byref N004 ( 8, 11) [000952] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000209] ------------ | | | | +--* LCL_VAR int V09 loc5 u:2 $3c4 N003 ( 3, 3) CSE #08 (use)[000951] ---X-------- | | | | \--* ARR_LENGTH int N002 ( 1, 1) [000208] ------------ | | | | \--* LCL_VAR ref V04 loc0 u:1 N016 ( 21, 21) [000962] ----G------- | | | \--* ADDR byref $91 N015 ( 11, 11) [000210] a---G--N---- | | | \--* IND struct N014 ( 10, 10) [000958] -------N---- | | | \--* ADD byref $91 N005 ( 1, 1) [000949] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 9, 9) [000957] -------N---- | | | \--* ADD long $6e4 N011 ( 8, 8) [000955] -------N---- | | | +--* LSH long $6e3 N009 ( 7, 7) CSE #14 (def)[000961] ------------ | | | | +--* MUL long $6e2 N007 ( 2, 3) CSE #13 (def)[000953] ------------ | | | | | +--* CAST long <- int $6e1 N006 ( 1, 1) [000950] i----------- | | | | | | \--* LCL_VAR int V09 loc5 u:2 $3c4 N008 ( 1, 1) [000960] ------------ | | | | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [000954] -------N---- | | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000956] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N020 ( 1, 1) [001256] ------------ | | \--* LCL_VAR byref V66 cse1 u:1 N022 ( 1, 1) [000947] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N025 ( 1, 1) [000213] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 Working on the replacement of the CSE #16 use at [000998] in BB39 Unmark CSE use #08 at [000990]: 11 -> 10 Unmark CSE use #14 at [001000]: 3 -> 2 Unmark CSE use #13 at [000992]: 3 -> 2 optValnumCSE morphed tree: N006 ( 6, 6) [000336] -A-XG------- * ASG ref $VN.Void N004 ( 4, 4) [000335] *--XG--N---- +--* IND ref $102 N003 ( 2, 2) [000987] ----G--N---- | \--* ADD byref $2ae N001 ( 1, 1) [001258] ------------ | +--* LCL_VAR byref V66 cse1 u:1 $91 N002 ( 1, 1) [000986] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N005 ( 1, 1) [000334] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 Working on the replacement of the CSE #16 use at [001020] in BB42 Unmark CSE use #08 at [001012]: 10 -> 9 Unmark CSE use #14 at [001022]: 2 -> 1 Unmark CSE use #13 at [001014]: 2 -> 1 optValnumCSE morphed tree: N006 ( 4, 4) [000222] -A-XG---R--- * ASG int N005 ( 1, 1) [000221] D------N---- +--* LCL_VAR int V09 loc5 d:3 N004 ( 4, 4) [000220] *--XG------- \--* IND int N003 ( 2, 2) [001009] ----G--N---- \--* ADD byref $2ad N001 ( 1, 1) [001259] ------------ +--* LCL_VAR byref V66 cse1 u:1 $91 N002 ( 1, 1) [001008] ------------ \--* CNS_INT long 20 field offset Fseq[next] $24c Skipped CSE #24 because use count is 0 Skipped CSE #22 because use count is 0 Skipped CSE #23 because use count is 0 Considering CSE #15 {$348, $4 } [def=200.000000, use=100.000000, cost= 10 ] CSE Expression : N008 ( 10, 9) CSE #15 (def)[000259] n----------- * IND long N007 ( 8, 7) [000255] -------N---- \--* ADD long $6e6 N005 ( 7, 6) CSE #03 (def)[000253] #----------- +--* IND long $2ea N004 ( 4, 4) CSE #02 (def)[000252] #----------- | \--* IND long $2e9 N003 ( 2, 2) [000251] -------N---- | \--* ADD long $306 N001 ( 1, 1) [000249] ------------ | +--* LCL_VAR long V16 tmp2 u:1 $2e7 N002 ( 1, 1) [000250] ------------ | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000254] ------------ \--* CNS_INT long 48 $246 Moderate CSE Promotion (CSE never live at call) (500.000000 >= 400.000000) cseRefCnt=500.000000, aggressiveRefCnt=650.000000, moderateRefCnt=400.000000 defCnt=200.000000, useCnt=100.000000, cost=10, size=9 def_cost=2, use_cost=1, extra_no_cost=16, extra_yes_cost=0 CSE cost savings check (1016.000000 >= 500.000000) passes Promoting CSE: lvaGrabTemp returning 67 (V67 rat0) (a long lifetime temp) called for CSE - moderate. CSE #15 is single-def, so associated CSE temp V67 will be in SSA New refCnts for V67: refCnt = 2, refCntWtd = 4 New refCnts for V67: refCnt = 3, refCntWtd = 5 CSE #15 def at [000259] replaced in BB34 with def of V67 optValnumCSE morphed tree: N015 ( 15, 14) [001163] -A---------- * JTRUE void N014 ( 13, 12) [000263] JA-----N---- \--* EQ int N012 ( 11, 10) [001263] -A---------- +--* COMMA long N010 ( 10, 9) [001261] -A------R--- | +--* ASG long $VN.Void N009 ( 1, 1) [001260] D------N---- | | +--* LCL_VAR long V67 cse2 d:1 N008 ( 10, 9) [000259] n----------- | | \--* IND long N007 ( 8, 7) [000255] -------N---- | | \--* ADD long $6e6 N005 ( 7, 6) CSE #03 (def)[000253] #----------- | | +--* IND long $2ea N004 ( 4, 4) CSE #02 (def)[000252] #----------- | | | \--* IND long $2e9 N003 ( 2, 2) [000251] -------N---- | | | \--* ADD long $306 N001 ( 1, 1) [000249] ------------ | | | +--* LCL_VAR long V16 tmp2 u:1 $2e7 N002 ( 1, 1) [000250] ------------ | | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000254] ------------ | | \--* CNS_INT long 48 $246 N011 ( 1, 1) [001262] ------------ | \--* LCL_VAR long V67 cse2 u:1 N013 ( 1, 1) [000262] ------------ \--* CNS_INT long 0 $243 Working on the replacement of the CSE #15 use at [000264] in BB35 Unmark CSE use #03 at [000266]: 7 -> 6 Unmark CSE use #02 at [000267]: 7 -> 6 optValnumCSE morphed tree: N003 ( 1, 3) [001165] -A------R--- * ASG long N002 ( 1, 1) [001164] D------N---- +--* LCL_VAR long V19 tmp5 d:3 N001 ( 1, 1) [001264] ------------ \--* LCL_VAR long V67 cse2 u:1 Considering CSE #04 {$341, $4 } [def=50.000000, use=25.000000, cost= 10 ] CSE Expression : N008 ( 10, 9) CSE #04 (def)[000501] n----------- * IND long N007 ( 8, 7) [000497] -------N---- \--* ADD long $307 N005 ( 7, 6) CSE #03 (def)[000495] #----------- +--* IND long $2ea N004 ( 4, 4) CSE #02 (def)[000494] #----------- | \--* IND long $2e9 N003 ( 2, 2) [000493] -------N---- | \--* ADD long $306 N001 ( 1, 1) [000491] ------------ | +--* LCL_VAR long V29 tmp15 u:1 $2e7 N002 ( 1, 1) [000492] ------------ | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000496] ------------ \--* CNS_INT long 64 $245 Conservative CSE Promotion (not enregisterable) (125.000000 < 400.000000) cseRefCnt=125.000000, aggressiveRefCnt=650.000000, moderateRefCnt=400.000000 defCnt=50.000000, useCnt=25.000000, cost=10, size=9 def_cost=2, use_cost=2, extra_no_cost=14, extra_yes_cost=0 CSE cost savings check (264.000000 >= 150.000000) passes Promoting CSE: lvaGrabTemp returning 68 (V68 rat0) (a long lifetime temp) called for CSE - conservative. CSE #04 is single-def, so associated CSE temp V68 will be in SSA New refCnts for V68: refCnt = 2, refCntWtd = 1 New refCnts for V68: refCnt = 3, refCntWtd = 1.25 CSE #04 def at [000501] replaced in BB09 with def of V68 optValnumCSE morphed tree: N015 ( 21, 18) [001148] -A---------- * JTRUE void N014 ( 19, 16) [000505] JA-----N---- \--* EQ int N012 ( 17, 14) [001268] -A---------- +--* COMMA long N010 ( 14, 12) [001266] -A------R--- | +--* ASG long $VN.Void N009 ( 3, 2) [001265] D------N---- | | +--* LCL_VAR long V68 cse3 d:1 N008 ( 10, 9) [000501] n----------- | | \--* IND long N007 ( 8, 7) [000497] -------N---- | | \--* ADD long $307 N005 ( 7, 6) CSE #03 (def)[000495] #----------- | | +--* IND long $2ea N004 ( 4, 4) CSE #02 (def)[000494] #----------- | | | \--* IND long $2e9 N003 ( 2, 2) [000493] -------N---- | | | \--* ADD long $306 N001 ( 1, 1) [000491] ------------ | | | +--* LCL_VAR long V29 tmp15 u:1 $2e7 N002 ( 1, 1) [000492] ------------ | | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000496] ------------ | | \--* CNS_INT long 64 $245 N011 ( 3, 2) [001267] ------------ | \--* LCL_VAR long V68 cse3 u:1 N013 ( 1, 1) [000504] ------------ \--* CNS_INT long 0 $243 Working on the replacement of the CSE #04 use at [000506] in BB10 Unmark CSE use #03 at [000508]: 6 -> 5 Unmark CSE use #02 at [000509]: 6 -> 5 optValnumCSE morphed tree: N003 ( 3, 3) [001150] -A------R--- * ASG long N002 ( 1, 1) [001149] D------N---- +--* LCL_VAR long V31 tmp17 d:3 N001 ( 3, 2) [001269] ------------ \--* LCL_VAR long V68 cse3 u:1 Considering CSE #07 {$343, $4 } [def=50.000000, use=25.000000, cost= 10 ] CSE Expression : N008 ( 10, 9) CSE #07 (def)[000365] n----------- * IND long N007 ( 8, 7) [000364] -------N---- \--* ADD long $324 N005 ( 7, 6) CSE #03 (def)[000362] #----------- +--* IND long $2ea N004 ( 4, 4) CSE #02 (def)[000361] #----------- | \--* IND long $2e9 N003 ( 2, 2) [000360] -------N---- | \--* ADD long $306 N001 ( 1, 1) [000358] ------------ | +--* LCL_VAR long V24 tmp10 u:1 $2e7 N002 ( 1, 1) [000359] ------------ | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000363] ------------ \--* CNS_INT long 32 $24a Conservative CSE Promotion (not enregisterable) (125.000000 < 400.000000) cseRefCnt=125.000000, aggressiveRefCnt=650.000000, moderateRefCnt=400.000000 defCnt=50.000000, useCnt=25.000000, cost=10, size=9 def_cost=2, use_cost=2, extra_no_cost=14, extra_yes_cost=0 CSE cost savings check (264.000000 >= 150.000000) passes Promoting CSE: lvaGrabTemp returning 69 (V69 rat0) (a long lifetime temp) called for CSE - conservative. CSE #07 is single-def, so associated CSE temp V69 will be in SSA New refCnts for V69: refCnt = 2, refCntWtd = 1 New refCnts for V69: refCnt = 3, refCntWtd = 1.25 CSE #07 def at [000365] replaced in BB19 with def of V69 optValnumCSE morphed tree: N015 ( 21, 18) [001153] -A---------- * JTRUE void N014 ( 19, 16) [000369] JA-----N---- \--* EQ int N012 ( 17, 14) [001273] -A---------- +--* COMMA long N010 ( 14, 12) [001271] -A------R--- | +--* ASG long $VN.Void N009 ( 3, 2) [001270] D------N---- | | +--* LCL_VAR long V69 cse4 d:1 N008 ( 10, 9) [000365] n----------- | | \--* IND long N007 ( 8, 7) [000364] -------N---- | | \--* ADD long $324 N005 ( 7, 6) CSE #03 (def)[000362] #----------- | | +--* IND long $2ea N004 ( 4, 4) CSE #02 (def)[000361] #----------- | | | \--* IND long $2e9 N003 ( 2, 2) [000360] -------N---- | | | \--* ADD long $306 N001 ( 1, 1) [000358] ------------ | | | +--* LCL_VAR long V24 tmp10 u:1 $2e7 N002 ( 1, 1) [000359] ------------ | | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000363] ------------ | | \--* CNS_INT long 32 $24a N011 ( 3, 2) [001272] ------------ | \--* LCL_VAR long V69 cse4 u:1 N013 ( 1, 1) [000368] ------------ \--* CNS_INT long 0 $243 Working on the replacement of the CSE #07 use at [000370] in BB20 Unmark CSE use #03 at [000372]: 5 -> 4 Unmark CSE use #02 at [000373]: 5 -> 4 optValnumCSE morphed tree: N003 ( 7, 5) [001155] -A------R--- * ASG long N002 ( 3, 2) [001154] D------N---- +--* LCL_VAR long V25 tmp11 d:3 N001 ( 3, 2) [001274] ------------ \--* LCL_VAR long V69 cse4 u:1 Considering CSE #10 {$327, $4 } [def=400.000000, use=200.000000, cost= 7, call] CSE Expression : N009 ( 7, 7) CSE #10 (def)[000881] ------------ * MUL long $327 N007 ( 2, 3) CSE #09 (def)[000873] ------------ +--* CAST long <- int $326 N006 ( 1, 1) [000870] i----------- | \--* LCL_VAR int V09 loc5 u:4 $3c2 N008 ( 1, 1) [000880] ------------ \--* CNS_INT long 3 $24b Aggressive CSE Promotion (1000.000000 >= 650.000000) cseRefCnt=1000.000000, aggressiveRefCnt=650.000000, moderateRefCnt=400.000000 defCnt=400.000000, useCnt=200.000000, cost=7, size=7, LiveAcrossCall def_cost=1, use_cost=1, extra_no_cost=12, extra_yes_cost=0 CSE cost savings check (1412.000000 >= 600.000000) passes Promoting CSE: lvaGrabTemp returning 70 (V70 rat0) (a long lifetime temp) called for CSE - aggressive. CSE #10 is single-def, so associated CSE temp V70 will be in SSA New refCnts for V70: refCnt = 2, refCntWtd = 8 New refCnts for V70: refCnt = 3, refCntWtd = 10 CSE #10 def at [000881] replaced in BB24 with def of V70 optValnumCSE morphed tree: N031 ( 39, 42) [000399] -A-XG------- * JTRUE void N030 ( 37, 40) [000398] NA-XG--N-U-- \--* NE int N028 ( 35, 38) [000396] *A-XG------- +--* IND int N027 ( 33, 36) [000868] -A-XG--N---- | \--* ADD byref $28c N025 ( 32, 35) [001251] -A-XG------- | +--* COMMA byref N023 ( 31, 34) [001249] -A-XG---R--- | | +--* ASG byref $VN.Void N022 ( 1, 1) [001248] D------N---- | | | +--* LCL_VAR byref V65 cse0 d:1 N021 ( 31, 34) [000879] -A-XG------- | | | \--* COMMA byref N004 ( 8, 11) [000872] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000393] ------------ | | | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N003 ( 3, 3) CSE #08 (use)[000871] ---X-------- | | | | \--* ARR_LENGTH int N002 ( 1, 1) [000392] ------------ | | | | \--* LCL_VAR ref V04 loc0 u:1 N020 ( 23, 23) [000882] -A--G------- | | | \--* ADDR byref $82 N019 ( 12, 12) [000394] aA--G--N---- | | | \--* IND struct N018 ( 11, 11) [000878] -A-----N---- | | | \--* ADD byref $82 N005 ( 1, 1) [000869] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N017 ( 10, 10) [000877] -A-----N---- | | | \--* ADD long $329 N015 ( 9, 9) [000875] -A-----N---- | | | +--* LSH long $328 N013 ( 8, 8) [001278] -A---------- | | | | +--* COMMA long $327 N011 ( 7, 7) [001276] -A------R--- | | | | | +--* ASG long $VN.Void N010 ( 1, 1) [001275] D------N---- | | | | | | +--* LCL_VAR long V70 cse5 d:1 $327 N009 ( 7, 7) [000881] ------------ | | | | | | \--* MUL long $327 N007 ( 2, 3) CSE #09 (def)[000873] ------------ | | | | | | +--* CAST long <- int $326 N006 ( 1, 1) [000870] i----------- | | | | | | | \--* LCL_VAR int V09 loc5 u:4 $3c2 N008 ( 1, 1) [000880] ------------ | | | | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [001277] ------------ | | | | | \--* LCL_VAR long V70 cse5 u:1 $327 N014 ( 1, 1) [000874] -------N---- | | | | \--* CNS_INT long 3 $24b N016 ( 1, 1) [000876] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N024 ( 1, 1) [001250] ------------ | | \--* LCL_VAR byref V65 cse0 u:1 N026 ( 1, 1) [000867] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N029 ( 1, 1) [000397] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 Working on the replacement of the CSE #10 use at [000895] in BB25 Unmark CSE use #09 at [000887]: 1 -> 0 ReMorphing args for 425.CALL: argSlots=3, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 ArgTable for 425.CALL after fgMorphArgs: fgArgTabEntry[arg 1 893.COMMA ref (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 0 418.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=1, processed] fgArgTabEntry[arg 2 424.LCL_VAR ref (By ref), 1 reg: r8, byteAlignment=8, lateArgInx=2, processed] optValnumCSE morphed tree: N032 ( 55, 47) [000428] --CXG------- * JTRUE void N031 ( 53, 45) [000427] J-CXG--N---- \--* NE int $1bd N029 ( 51, 43) [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals $581 N028 ( 9, 8) [000908] n--X-------- control expr | \--* IND long N027 ( 7, 6) [000907] ---X---N---- | \--* ADD long $32e N025 ( 6, 5) [000905] #--X-------- | +--* IND long $465 N024 ( 4, 3) [000904] ---X---N---- | | \--* ADD long $32c N022 ( 3, 2) [000902] #--X-------- | | +--* IND long $463 N021 ( 1, 1) [000901] ------------ | | | \--* LCL_VAR ref V12 loc8 u:1 $223 N023 ( 1, 1) [000903] ------------ | | \--* CNS_INT int 72 $c9 N026 ( 1, 1) [000906] ------------ | \--* CNS_INT int 32 $d2 N018 ( 20, 22) [000893] ---XG------- arg1 in rdx | +--* COMMA ref N007 ( 8, 11) [000886] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N004 ( 1, 1) [000420] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N006 ( 3, 3) CSE #08 (use)[000885] ---X-------- | | | \--* ARR_LENGTH int N005 ( 1, 1) [000419] ------------ | | | \--* LCL_VAR ref V04 loc0 u:1 N017 ( 12, 11) [000897] *---G------- | | \--* IND ref N016 ( 9, 9) [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] $84 N015 ( 5, 5) [000421] a---G--N---- | | \--* IND struct N014 ( 4, 4) [000892] -------N---- | | \--* ADD byref $82 N008 ( 1, 1) [000883] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 3, 3) [000891] -------N---- | | \--* ADD long $329 N011 ( 2, 2) [000889] -------N---- | | +--* LSH long $328 N009 ( 1, 1) [001279] ------------ | | | +--* LCL_VAR long V70 cse5 u:1 $327 N010 ( 1, 1) [000888] -------N---- | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000890] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N019 ( 1, 1) [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 u:1 $223 N020 ( 1, 1) [000424] ------------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 u:1 $101 N030 ( 1, 1) [000426] ------------ \--* CNS_INT int 0 $c0 Considering CSE #14 {$6e2, $4 } [def=400.000000, use=200.000000, cost= 7, call] CSE Expression : N009 ( 7, 7) CSE #14 (def)[000961] ------------ * MUL long $6e2 N007 ( 2, 3) CSE #13 (def)[000953] ------------ +--* CAST long <- int $6e1 N006 ( 1, 1) [000950] i----------- | \--* LCL_VAR int V09 loc5 u:2 $3c4 N008 ( 1, 1) [000960] ------------ \--* CNS_INT long 3 $24b Aggressive CSE Promotion (1000.000000 >= 750.000000) cseRefCnt=1000.000000, aggressiveRefCnt=750.000000, moderateRefCnt=450.000000 defCnt=400.000000, useCnt=200.000000, cost=7, size=7, LiveAcrossCall def_cost=1, use_cost=1, extra_no_cost=12, extra_yes_cost=0 CSE cost savings check (1412.000000 >= 600.000000) passes Promoting CSE: lvaGrabTemp returning 71 (V71 rat0) (a long lifetime temp) called for CSE - aggressive. CSE #14 is single-def, so associated CSE temp V71 will be in SSA New refCnts for V71: refCnt = 2, refCntWtd = 8 New refCnts for V71: refCnt = 3, refCntWtd = 10 CSE #14 def at [000961] replaced in BB33 with def of V71 optValnumCSE morphed tree: N031 ( 39, 42) [000215] -A-XG------- * JTRUE void N030 ( 37, 40) [000214] NA-XG--N-U-- \--* NE int N028 ( 35, 38) [000212] *A-XG------- +--* IND int N027 ( 33, 36) [000948] -A-XG--N---- | \--* ADD byref $2ac N025 ( 32, 35) [001257] -A-XG------- | +--* COMMA byref N023 ( 31, 34) [001255] -A-XG---R--- | | +--* ASG byref $VN.Void N022 ( 1, 1) [001254] D------N---- | | | +--* LCL_VAR byref V66 cse1 d:1 N021 ( 31, 34) [000959] -A-XG------- | | | \--* COMMA byref N004 ( 8, 11) [000952] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000209] ------------ | | | | +--* LCL_VAR int V09 loc5 u:2 $3c4 N003 ( 3, 3) CSE #08 (use)[000951] ---X-------- | | | | \--* ARR_LENGTH int N002 ( 1, 1) [000208] ------------ | | | | \--* LCL_VAR ref V04 loc0 u:1 N020 ( 23, 23) [000962] -A--G------- | | | \--* ADDR byref $91 N019 ( 12, 12) [000210] aA--G--N---- | | | \--* IND struct N018 ( 11, 11) [000958] -A-----N---- | | | \--* ADD byref $91 N005 ( 1, 1) [000949] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N017 ( 10, 10) [000957] -A-----N---- | | | \--* ADD long $6e4 N015 ( 9, 9) [000955] -A-----N---- | | | +--* LSH long $6e3 N013 ( 8, 8) [001283] -A---------- | | | | +--* COMMA long $6e2 N011 ( 7, 7) [001281] -A------R--- | | | | | +--* ASG long $VN.Void N010 ( 1, 1) [001280] D------N---- | | | | | | +--* LCL_VAR long V71 cse6 d:1 $6e2 N009 ( 7, 7) [000961] ------------ | | | | | | \--* MUL long $6e2 N007 ( 2, 3) CSE #13 (def)[000953] ------------ | | | | | | +--* CAST long <- int $6e1 N006 ( 1, 1) [000950] i----------- | | | | | | | \--* LCL_VAR int V09 loc5 u:2 $3c4 N008 ( 1, 1) [000960] ------------ | | | | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [001282] ------------ | | | | | \--* LCL_VAR long V71 cse6 u:1 $6e2 N014 ( 1, 1) [000954] -------N---- | | | | \--* CNS_INT long 3 $24b N016 ( 1, 1) [000956] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N024 ( 1, 1) [001256] ------------ | | \--* LCL_VAR byref V66 cse1 u:1 N026 ( 1, 1) [000947] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N029 ( 1, 1) [000213] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 Working on the replacement of the CSE #14 use at [000975] in BB34 Unmark CSE use #13 at [000967]: 1 -> 0 optValnumCSE morphed tree: N017 ( 20, 22) [000246] -A-XG---R--- * ASG ref N016 ( 1, 1) [000245] D------N---- +--* LCL_VAR ref V17 tmp3 d:1 N015 ( 20, 22) [000973] ---XG------- \--* COMMA ref N004 ( 8, 11) [000966] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000236] ------------ | +--* LCL_VAR int V09 loc5 u:2 $3c4 N003 ( 3, 3) CSE #08 (use)[000965] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000235] ------------ | \--* LCL_VAR ref V04 loc0 u:1 N014 ( 12, 11) [000977] *---G------- \--* IND ref N013 ( 9, 9) [000976] ----G------- \--* ADDR byref Zero Fseq[key] $93 N012 ( 5, 5) [000237] a---G--N---- \--* IND struct N011 ( 4, 4) [000972] -------N---- \--* ADD byref $91 N005 ( 1, 1) [000963] ------------ +--* LCL_VAR ref V04 loc0 u:1 N010 ( 3, 3) [000971] -------N---- \--* ADD long $6e4 N008 ( 2, 2) [000969] -------N---- +--* LSH long $6e3 N006 ( 1, 1) [001284] ------------ | +--* LCL_VAR long V71 cse6 u:1 $6e2 N007 ( 1, 1) [000968] -------N---- | \--* CNS_INT long 3 $24b N009 ( 1, 1) [000970] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 Skipped CSE #03 because use count is 0 Considering CSE #20 {$405, $477} [def=50.000000, use=50.000000, cost= 5, call] CSE Expression : N002 ( 5, 4) CSE #20 (def)[000714] ---X-------- * ARR_LENGTH int N001 ( 3, 2) [000713] ------------ \--* LCL_VAR ref V52 tmp38 u:1 Conservative CSE Promotion (150.000000 < 500.000000) cseRefCnt=150.000000, aggressiveRefCnt=850.000000, moderateRefCnt=500.000000 defCnt=50.000000, useCnt=50.000000, cost=5, size=4, LiveAcrossCall def_cost=2, use_cost=3, extra_no_cost=2, extra_yes_cost=0 CSE cost savings check (252.000000 >= 250.000000) passes Promoting CSE: lvaGrabTemp returning 72 (V72 rat0) (a long lifetime temp) called for CSE - conservative. CSE #20 is single-def, so associated CSE temp V72 will be in SSA New refCnts for V72: refCnt = 2, refCntWtd = 1 New refCnts for V72: refCnt = 3, refCntWtd = 1.50 CSE #20 def at [000714] replaced in BB49 with def of V72 optValnumCSE morphed tree: N008 ( 12, 9) [000760] -A-X----R--- * ASG int N007 ( 1, 1) [000759] D------N---- +--* LCL_VAR int V53 tmp39 d:1 N006 ( 12, 9) [001288] -A-X-------- \--* COMMA int N004 ( 9, 7) [001286] -A-X----R--- +--* ASG int $VN.Void N003 ( 3, 2) [001285] D------N---- | +--* LCL_VAR int V72 cse7 d:1 N002 ( 5, 4) [000714] ---X-------- | \--* ARR_LENGTH int N001 ( 3, 2) [000713] ------------ | \--* LCL_VAR ref V52 tmp38 u:1 N005 ( 3, 2) [001287] ------------ \--* LCL_VAR int V72 cse7 u:1 Working on the replacement of the CSE #20 use at [001104] in BB53 optValnumCSE morphed tree: N016 ( 33, 31) [000722] -A-XG---R--- * ASG byref N015 ( 3, 2) [000721] D------N---- +--* LCL_VAR byref V51 tmp37 d:1 $87 N014 ( 29, 28) [001112] ---XG------- \--* COMMA byref N003 ( 10, 11) [001105] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 3, 2) [000758] ------------ | +--* LCL_VAR int V55 tmp41 u:1 N002 ( 3, 2) [001289] ------------ | \--* LCL_VAR int V72 cse7 u:1 N013 ( 19, 17) [001113] ----G------- \--* ADDR byref $87 N012 ( 10, 9) [000719] a---G--N---- \--* IND int N011 ( 9, 8) [001111] -------N---- \--* ADD byref $87 N004 ( 3, 2) [001102] ------------ +--* LCL_VAR ref V52 tmp38 u:1 (last use) N010 ( 6, 6) [001110] -------N---- \--* ADD long N008 ( 5, 5) [001108] -------N---- +--* LSH long N006 ( 4, 4) [001106] ------------ | +--* CAST long <- int N005 ( 3, 2) [001103] i----------- | | \--* LCL_VAR int V55 tmp41 u:1 (last use) N007 ( 1, 1) [001107] -------N---- | \--* CNS_INT long 2 $248 N009 ( 1, 1) [001109] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 Considering CSE #01 {$105, $4 } [def=100.000000, use=850.000000, cost= 4, call] CSE Expression : N002 ( 4, 12) CSE #01 (def)[000538] #---G------- * IND ref $105 N001 ( 2, 10) [000537] H----------- \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 Aggressive CSE Promotion (1050.000000 >= 850.000000) cseRefCnt=1050.000000, aggressiveRefCnt=850.000000, moderateRefCnt=500.000000 defCnt=100.000000, useCnt=850.000000, cost=4, size=12, LiveAcrossCall def_cost=1, use_cost=1, extra_no_cost=242, extra_yes_cost=0 CSE cost savings check (3642.000000 >= 950.000000) passes Promoting CSE: lvaGrabTemp returning 73 (V73 rat0) (a long lifetime temp) called for CSE - aggressive. CSE #01 is single-def, so associated CSE temp V73 will be in SSA New refCnts for V73: refCnt = 2, refCntWtd = 2 New refCnts for V73: refCnt = 3, refCntWtd = 3 New refCnts for V73: refCnt = 4, refCntWtd = 4 New refCnts for V73: refCnt = 5, refCntWtd = 5 New refCnts for V73: refCnt = 6, refCntWtd = 6 New refCnts for V73: refCnt = 7, refCntWtd = 7 New refCnts for V73: refCnt = 8, refCntWtd = 8 New refCnts for V73: refCnt = 9, refCntWtd = 8.50 New refCnts for V73: refCnt = 10, refCntWtd = 9 New refCnts for V73: refCnt = 11, refCntWtd = 9.50 New refCnts for V73: refCnt = 12, refCntWtd = 10 New refCnts for V73: refCnt = 13, refCntWtd = 10.50 CSE #01 def at [000538] replaced in BB04 with def of V73 optValnumCSE morphed tree: N008 ( 5, 13) [000554] -A--G---R--- * ASG ref $105 N007 ( 1, 1) [000553] D------N---- +--* LCL_VAR ref V34 tmp20 d:1 $105 N006 ( 5, 13) [001293] -A--G------- \--* COMMA ref $105 N004 ( 4, 12) [001291] -A--G---R--- +--* ASG ref $VN.Void N003 ( 1, 1) [001290] D------N---- | +--* LCL_VAR ref V73 cse8 d:1 $105 N002 ( 4, 12) [000538] #---G------- | \--* IND ref $105 N001 ( 2, 10) [000537] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 N005 ( 1, 1) [001292] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 Working on the replacement of the CSE #01 use at [000540] in BB04 optValnumCSE morphed tree: N003 ( 1, 3) [000556] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000555] D------N---- +--* LCL_VAR ref V35 tmp21 d:1 $105 N001 ( 1, 1) [001294] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 Working on the replacement of the CSE #01 use at [000562] in BB06 optValnumCSE morphed tree: N003 ( 1, 3) [000576] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000575] D------N---- +--* LCL_VAR ref V37 tmp23 d:1 $105 N001 ( 1, 1) [001295] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 Working on the replacement of the CSE #01 use at [000636] in BB14 optValnumCSE morphed tree: N003 ( 1, 3) [000652] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000651] D------N---- +--* LCL_VAR ref V44 tmp30 d:1 $105 N001 ( 1, 1) [001296] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 Working on the replacement of the CSE #01 use at [000638] in BB14 optValnumCSE morphed tree: N003 ( 1, 3) [000654] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000653] D------N---- +--* LCL_VAR ref V45 tmp31 d:1 $105 N001 ( 1, 1) [001297] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 Working on the replacement of the CSE #01 use at [000659] in BB16 optValnumCSE morphed tree: N003 ( 1, 3) [000675] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000674] D------N---- +--* LCL_VAR ref V47 tmp33 d:1 $105 N001 ( 1, 1) [001298] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 Working on the replacement of the CSE #01 use at [000661] in BB16 optValnumCSE morphed tree: N003 ( 1, 3) [000677] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000676] D------N---- +--* LCL_VAR ref V48 tmp34 d:1 $105 N001 ( 1, 1) [001299] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 Working on the replacement of the CSE #01 use at [000684] in BB45 optValnumCSE morphed tree: N003 ( 5, 4) [000698] -A--G---R--- * ASG ref $105 N002 ( 3, 2) [000697] D------N---- +--* LCL_VAR ref V50 tmp36 d:1 $105 N001 ( 1, 1) [001300] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 Working on the replacement of the CSE #01 use at [000767] in BB49 optValnumCSE morphed tree: N003 ( 5, 4) [000783] -A--G---R--- * ASG ref $105 N002 ( 3, 2) [000782] D------N---- +--* LCL_VAR ref V57 tmp43 d:1 $105 N001 ( 1, 1) [001301] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 Working on the replacement of the CSE #01 use at [000769] in BB49 optValnumCSE morphed tree: N003 ( 5, 4) [000785] -A--G---R--- * ASG ref $105 N002 ( 3, 2) [000784] D------N---- +--* LCL_VAR ref V58 tmp44 d:1 $105 N001 ( 1, 1) [001302] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 Working on the replacement of the CSE #01 use at [000790] in BB51 optValnumCSE morphed tree: N003 ( 5, 4) [000806] -A--G---R--- * ASG ref $105 N002 ( 3, 2) [000805] D------N---- +--* LCL_VAR ref V60 tmp46 d:1 $105 N001 ( 1, 1) [001303] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 Working on the replacement of the CSE #01 use at [000792] in BB51 optValnumCSE morphed tree: N003 ( 5, 4) [000808] -A--G---R--- * ASG ref $105 N002 ( 3, 2) [000807] D------N---- +--* LCL_VAR ref V61 tmp47 d:1 $105 N001 ( 1, 1) [001304] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 Skipped CSE #02 because use count is 0 Considering CSE #17 {$71a, $2c2} [def=50.000000, use=50.000000, cost= 4 ] CSE Expression : N004 ( 4, 4) CSE #17 (def)[000172] ---XG------- * IND int N003 ( 2, 2) [001027] -------N---- \--* ADD byref $295 N001 ( 1, 1) [000171] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001026] ------------ \--* CNS_INT long 60 field offset Fseq[_freeList] $24d Conservative CSE Promotion (not enregisterable) (150.000000 < 550.000000) cseRefCnt=150.000000, aggressiveRefCnt=950.000000, moderateRefCnt=550.000000 defCnt=50.000000, useCnt=50.000000, cost=4, size=4 def_cost=2, use_cost=2, extra_no_cost=4, extra_yes_cost=0 CSE cost savings check (204.000000 >= 200.000000) passes Promoting CSE: lvaGrabTemp returning 74 (V74 rat0) (a long lifetime temp) called for CSE - conservative. CSE #17 is single-def, so associated CSE temp V74 will be in SSA New refCnts for V74: refCnt = 2, refCntWtd = 1 New refCnts for V74: refCnt = 3, refCntWtd = 1.50 CSE #17 def at [000172] replaced in BB45 with def of V74 optValnumCSE morphed tree: N010 ( 15, 12) [000174] -A-XG---R--- * ASG int N009 ( 3, 2) [000173] D------N---- +--* LCL_VAR int V10 loc6 d:3 N008 ( 11, 9) [001308] -A-XG------- \--* COMMA int N006 ( 8, 7) [001306] -A-XG---R--- +--* ASG int $VN.Void N005 ( 3, 2) [001305] D------N---- | +--* LCL_VAR int V74 cse9 d:1 N004 ( 4, 4) [000172] ---XG------- | \--* IND int N003 ( 2, 2) [001027] -------N---- | \--* ADD byref $295 N001 ( 1, 1) [000171] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001026] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N007 ( 3, 2) [001307] ------------ \--* LCL_VAR int V74 cse9 u:1 Working on the replacement of the CSE #17 use at [000178] in BB45 optValnumCSE morphed tree: N031 ( 47, 46) [000688] -A-XG---R--- * ASG bool N030 ( 3, 2) [000687] D------N---- +--* LCL_VAR int V49 tmp35 d:1 N029 ( 43, 43) [000184] -A-XG------- \--* GE int N027 ( 38, 41) [000182] -A-XG------- +--* ADD int N025 ( 36, 39) [001050] -A-XG------- | +--* NEG int N024 ( 35, 38) [000181] *A-XG------- | | \--* IND int N023 ( 33, 36) [001029] -A-XG--N---- | | \--* ADD byref $29c N021 ( 32, 35) [001044] -A-XG------- | | +--* COMMA byref N003 ( 3, 3) [001032] -A--G---R--- | | | +--* ASG int N002 ( 1, 1) [001031] D------N---- | | | | +--* LCL_VAR int V62 tmp48 d:1 N001 ( 3, 2) [001309] ------------ | | | | \--* LCL_VAR int V74 cse9 u:1 N020 ( 29, 32) [001043] ---XG------- | | | \--* COMMA byref N007 ( 8, 11) [001036] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N004 ( 1, 1) [001033] ------------ | | | | +--* LCL_VAR int V62 tmp48 u:1 N006 ( 3, 3) CSE #08 (use)[001035] ---X-------- | | | | \--* ARR_LENGTH int N005 ( 1, 1) [000176] ------------ | | | | \--* LCL_VAR ref V04 loc0 u:1 N019 ( 21, 21) [001049] ----G------- | | | \--* ADDR byref $88 N018 ( 11, 11) [000179] a---G--N---- | | | \--* IND struct N017 ( 10, 10) [001042] -------N---- | | | \--* ADD byref $88 N008 ( 1, 1) [001030] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N016 ( 9, 9) [001041] -------N---- | | | \--* ADD long N014 ( 8, 8) [001039] -------N---- | | | +--* LSH long N012 ( 7, 7) [001048] ------------ | | | | +--* MUL long N010 ( 2, 3) [001037] ------------ | | | | | +--* CAST long <- int N009 ( 1, 1) [001034] i----------- | | | | | | \--* LCL_VAR int V62 tmp48 u:1 (last use) N011 ( 1, 1) [001047] ------------ | | | | | \--* CNS_INT long 3 $24b N013 ( 1, 1) [001038] -------N---- | | | | \--* CNS_INT long 3 $24b N015 ( 1, 1) [001040] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N022 ( 1, 1) [001028] ------------ | | \--* CNS_INT long 20 field offset Fseq[next] $24c N026 ( 1, 1) [000175] ------------ | \--* CNS_INT int -3 $e1 N028 ( 1, 1) [000183] ------------ \--* CNS_INT int -1 $c4 Considering CSE #18 {$62c, $2c2} [def=50.000000, use=50.000000, cost= 4 ] CSE Expression : N004 ( 4, 4) CSE #18 (def)[000073] ---XG------- * IND int N003 ( 2, 2) [001085] -------N---- \--* ADD byref $290 N001 ( 1, 1) [000072] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001084] ------------ \--* CNS_INT long 56 field offset Fseq[_count] $244 Conservative CSE Promotion (not enregisterable) (150.000000 < 550.000000) cseRefCnt=150.000000, aggressiveRefCnt=950.000000, moderateRefCnt=550.000000 defCnt=50.000000, useCnt=50.000000, cost=4, size=4 def_cost=2, use_cost=2, extra_no_cost=4, extra_yes_cost=0 CSE cost savings check (204.000000 >= 200.000000) passes Promoting CSE: lvaGrabTemp returning 75 (V75 rat0) (a long lifetime temp) called for CSE - conservative. CSE #18 is single-def, so associated CSE temp V75 will be in SSA New refCnts for V75: refCnt = 2, refCntWtd = 1 New refCnts for V75: refCnt = 3, refCntWtd = 1.50 CSE #18 def at [000073] replaced in BB48 with def of V75 optValnumCSE morphed tree: N010 ( 15, 12) [000075] -A-XG---R--- * ASG int N009 ( 3, 2) [000074] D------N---- +--* LCL_VAR int V13 loc9 d:1 N008 ( 11, 9) [001313] -A-XG------- \--* COMMA int N006 ( 8, 7) [001311] -A-XG---R--- +--* ASG int $VN.Void N005 ( 3, 2) [001310] D------N---- | +--* LCL_VAR int V75 cse10 d:1 N004 ( 4, 4) [000073] ---XG------- | \--* IND int N003 ( 2, 2) [001085] -------N---- | \--* ADD byref $290 N001 ( 1, 1) [000072] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001084] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] $244 N007 ( 3, 2) [001312] ------------ \--* LCL_VAR int V75 cse10 u:1 Working on the replacement of the CSE #18 use at [000701] in BB49 ReMorphing args for 705.CALL: ReMorphing args for 702.CALL: argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 ArgTable for 702.CALL after fgMorphArgs: fgArgTabEntry[arg 0 1314.LCL_VAR int (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] argSlots=3, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 ArgTable for 705.CALL after fgMorphArgs: fgArgTabEntry[arg 1 1091.LCL_VAR int (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=0, tmpNum=V64, isTmp, processed] fgArgTabEntry[arg 0 163.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=1, processed] fgArgTabEntry[arg 2 704.CNS_INT int (By ref), 1 reg: r8, byteAlignment=8, lateArgInx=2, processed] optValnumCSE morphed tree: N011 ( 43, 24) [000705] -ACXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void N006 ( 21, 11) [001090] -ACXG---R-L- arg1 SETUP +--* ASG int $1d7 N005 ( 3, 2) [001089] D------N---- | +--* LCL_VAR int V64 tmp50 d:1 $1d7 N004 ( 17, 8) [000702] --CXG------- | \--* CALL int System.Collections.HashHelpers.ExpandPrime $1d7 N003 ( 3, 2) [001314] ------------ arg0 in rcx | \--* LCL_VAR int V75 cse10 u:1 N008 ( 3, 2) [001091] ------------ arg1 in rdx +--* LCL_VAR int V64 tmp50 u:1 (last use) $1d7 N009 ( 1, 1) [000163] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N010 ( 1, 1) [000704] ------------ arg2 in r8 \--* CNS_INT int 0 $c0 Considering CSE #08 {$403, $44f} [def=800.000000, use=2150.000000, cost= 3, call] CSE Expression : N002 ( 3, 3) CSE #08 (def)[000389] ---X-------- * ARR_LENGTH int N001 ( 1, 1) [000388] ------------ \--* LCL_VAR ref V04 loc0 u:1 Aggressive CSE Promotion (3750.000000 >= 950.000000) cseRefCnt=3750.000000, aggressiveRefCnt=950.000000, moderateRefCnt=550.000000 defCnt=800.000000, useCnt=2150.000000, cost=3, size=3, LiveAcrossCall def_cost=1, use_cost=1, extra_no_cost=36, extra_yes_cost=0 CSE cost savings check (6486.000000 >= 2950.000000) passes Promoting CSE: lvaGrabTemp returning 76 (V76 rat0) (a long lifetime temp) called for CSE - aggressive. New refCnts for V76: refCnt = 2, refCntWtd = 8 New refCnts for V76: refCnt = 3, refCntWtd = 12 New refCnts for V76: refCnt = 4, refCntWtd = 14 New refCnts for V76: refCnt = 5, refCntWtd = 18 New refCnts for V76: refCnt = 6, refCntWtd = 22 New refCnts for V76: refCnt = 7, refCntWtd = 26 New refCnts for V76: refCnt = 8, refCntWtd = 30 New refCnts for V76: refCnt = 9, refCntWtd = 32 New refCnts for V76: refCnt = 10, refCntWtd = 36 New refCnts for V76: refCnt = 11, refCntWtd = 36.50 New refCnts for V76: refCnt = 12, refCntWtd = 37 New refCnts for V76: refCnt = 13, refCntWtd = 37.50 CSE #08 def at [000389] replaced in BB23 with def of V76 optValnumCSE morphed tree: N009 ( 8, 8) [000391] -A-X-------- * JTRUE void N008 ( 6, 6) [000390] NA-X---N-U-- \--* LE int N006 ( 4, 4) [001318] -A-X-------- +--* COMMA int N004 ( 3, 3) [001316] -A-X----R--- | +--* ASG int $VN.Void N003 ( 1, 1) [001315] D------N---- | | +--* LCL_VAR int V76 cse11 N002 ( 3, 3) [000389] ---X-------- | | \--* ARR_LENGTH int N001 ( 1, 1) [000388] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N005 ( 1, 1) [001317] ------------ | \--* LCL_VAR int V76 cse11 N007 ( 1, 1) [000387] ------------ \--* LCL_VAR int V09 loc5 u:4 $3c2 Working on the replacement of the CSE #08 use at [000871] in BB24 optValnumCSE morphed tree: N030 ( 37, 40) [000399] -A-XG------- * JTRUE void N029 ( 35, 38) [000398] NA-XG--N-U-- \--* NE int N027 ( 33, 36) [000396] *A-XG------- +--* IND int N026 ( 31, 34) [000868] -A-XG--N---- | \--* ADD byref $28c N024 ( 30, 33) [001251] -A-XG------- | +--* COMMA byref N022 ( 29, 32) [001249] -A-XG---R--- | | +--* ASG byref $VN.Void N021 ( 1, 1) [001248] D------N---- | | | +--* LCL_VAR byref V65 cse0 d:1 N020 ( 29, 32) [000879] -A-XG------- | | | \--* COMMA byref N003 ( 6, 9) [000872] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000393] ------------ | | | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N002 ( 1, 1) [001319] ------------ | | | | \--* LCL_VAR int V76 cse11 N019 ( 23, 23) [000882] -A--G------- | | | \--* ADDR byref $82 N018 ( 12, 12) [000394] aA--G--N---- | | | \--* IND struct N017 ( 11, 11) [000878] -A-----N---- | | | \--* ADD byref $82 N004 ( 1, 1) [000869] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N016 ( 10, 10) [000877] -A-----N---- | | | \--* ADD long $329 N014 ( 9, 9) [000875] -A-----N---- | | | +--* LSH long $328 N012 ( 8, 8) [001278] -A---------- | | | | +--* COMMA long $327 N010 ( 7, 7) [001276] -A------R--- | | | | | +--* ASG long $VN.Void N009 ( 1, 1) [001275] D------N---- | | | | | | +--* LCL_VAR long V70 cse5 d:1 $327 N008 ( 7, 7) [000881] ------------ | | | | | | \--* MUL long $327 N006 ( 2, 3) CSE #09 (def)[000873] ------------ | | | | | | +--* CAST long <- int $326 N005 ( 1, 1) [000870] i----------- | | | | | | | \--* LCL_VAR int V09 loc5 u:4 $3c2 N007 ( 1, 1) [000880] ------------ | | | | | | \--* CNS_INT long 3 $24b N011 ( 1, 1) [001277] ------------ | | | | | \--* LCL_VAR long V70 cse5 u:1 $327 N013 ( 1, 1) [000874] -------N---- | | | | \--* CNS_INT long 3 $24b N015 ( 1, 1) [000876] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N023 ( 1, 1) [001250] ------------ | | \--* LCL_VAR byref V65 cse0 u:1 N025 ( 1, 1) [000867] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N028 ( 1, 1) [000397] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 Working on the replacement of the CSE #08 use at [000885] in BB25 ReMorphing args for 425.CALL: argSlots=3, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 ArgTable for 425.CALL after fgMorphArgs: fgArgTabEntry[arg 1 893.COMMA ref (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 0 418.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=1, processed] fgArgTabEntry[arg 2 424.LCL_VAR ref (By ref), 1 reg: r8, byteAlignment=8, lateArgInx=2, processed] optValnumCSE morphed tree: N031 ( 53, 45) [000428] --CXG------- * JTRUE void N030 ( 51, 43) [000427] J-CXG--N---- \--* NE int $1bd N028 ( 49, 41) [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals $581 N027 ( 9, 8) [000908] n--X-------- control expr | \--* IND long N026 ( 7, 6) [000907] ---X---N---- | \--* ADD long $32e N024 ( 6, 5) [000905] #--X-------- | +--* IND long $465 N023 ( 4, 3) [000904] ---X---N---- | | \--* ADD long $32c N021 ( 3, 2) [000902] #--X-------- | | +--* IND long $463 N020 ( 1, 1) [000901] ------------ | | | \--* LCL_VAR ref V12 loc8 u:1 $223 N022 ( 1, 1) [000903] ------------ | | \--* CNS_INT int 72 $c9 N025 ( 1, 1) [000906] ------------ | \--* CNS_INT int 32 $d2 N017 ( 18, 20) [000893] ---XG------- arg1 in rdx | +--* COMMA ref N006 ( 6, 9) [000886] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N004 ( 1, 1) [000420] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N005 ( 1, 1) [001320] ------------ | | | \--* LCL_VAR int V76 cse11 N016 ( 12, 11) [000897] *---G------- | | \--* IND ref N015 ( 9, 9) [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] $84 N014 ( 5, 5) [000421] a---G--N---- | | \--* IND struct N013 ( 4, 4) [000892] -------N---- | | \--* ADD byref $82 N007 ( 1, 1) [000883] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N012 ( 3, 3) [000891] -------N---- | | \--* ADD long $329 N010 ( 2, 2) [000889] -------N---- | | +--* LSH long $328 N008 ( 1, 1) [001279] ------------ | | | +--* LCL_VAR long V70 cse5 u:1 $327 N009 ( 1, 1) [000888] -------N---- | | | \--* CNS_INT long 3 $24b N011 ( 1, 1) [000890] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 u:1 $223 N019 ( 1, 1) [000424] ------------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 u:1 $101 N029 ( 1, 1) [000426] ------------ \--* CNS_INT int 0 $c0 Working on the replacement of the CSE #08 use at [000414] in BB26 optValnumCSE morphed tree: N004 ( 5, 5) [000416] ------------ * JTRUE void N003 ( 3, 3) [000415] N------N-U-- \--* LT int N001 ( 1, 1) [001321] ------------ +--* LCL_VAR int V76 cse11 N002 ( 1, 1) [000412] ------------ \--* LCL_VAR int V07 loc3 u:6 $605 CSE #08 def at [000064] replaced in BB32 with def of V76 optValnumCSE morphed tree: N009 ( 8, 8) [000066] -A-X-------- * JTRUE void N008 ( 6, 6) [000065] NA-X---N-U-- \--* LE int N006 ( 4, 4) [001325] -A-X-------- +--* COMMA int N004 ( 3, 3) [001323] -A-X----R--- | +--* ASG int $VN.Void N003 ( 1, 1) [001322] D------N---- | | +--* LCL_VAR int V76 cse11 N002 ( 3, 3) [000064] ---X-------- | | \--* ARR_LENGTH int N001 ( 1, 1) [000063] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N005 ( 1, 1) [001324] ------------ | \--* LCL_VAR int V76 cse11 N007 ( 1, 1) [000062] ------------ \--* LCL_VAR int V09 loc5 u:2 $3c4 Working on the replacement of the CSE #08 use at [000951] in BB33 optValnumCSE morphed tree: N030 ( 37, 40) [000215] -A-XG------- * JTRUE void N029 ( 35, 38) [000214] NA-XG--N-U-- \--* NE int N027 ( 33, 36) [000212] *A-XG------- +--* IND int N026 ( 31, 34) [000948] -A-XG--N---- | \--* ADD byref $2ac N024 ( 30, 33) [001257] -A-XG------- | +--* COMMA byref N022 ( 29, 32) [001255] -A-XG---R--- | | +--* ASG byref $VN.Void N021 ( 1, 1) [001254] D------N---- | | | +--* LCL_VAR byref V66 cse1 d:1 N020 ( 29, 32) [000959] -A-XG------- | | | \--* COMMA byref N003 ( 6, 9) [000952] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000209] ------------ | | | | +--* LCL_VAR int V09 loc5 u:2 $3c4 N002 ( 1, 1) [001326] ------------ | | | | \--* LCL_VAR int V76 cse11 N019 ( 23, 23) [000962] -A--G------- | | | \--* ADDR byref $91 N018 ( 12, 12) [000210] aA--G--N---- | | | \--* IND struct N017 ( 11, 11) [000958] -A-----N---- | | | \--* ADD byref $91 N004 ( 1, 1) [000949] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N016 ( 10, 10) [000957] -A-----N---- | | | \--* ADD long $6e4 N014 ( 9, 9) [000955] -A-----N---- | | | +--* LSH long $6e3 N012 ( 8, 8) [001283] -A---------- | | | | +--* COMMA long $6e2 N010 ( 7, 7) [001281] -A------R--- | | | | | +--* ASG long $VN.Void N009 ( 1, 1) [001280] D------N---- | | | | | | +--* LCL_VAR long V71 cse6 d:1 $6e2 N008 ( 7, 7) [000961] ------------ | | | | | | \--* MUL long $6e2 N006 ( 2, 3) CSE #13 (def)[000953] ------------ | | | | | | +--* CAST long <- int $6e1 N005 ( 1, 1) [000950] i----------- | | | | | | | \--* LCL_VAR int V09 loc5 u:2 $3c4 N007 ( 1, 1) [000960] ------------ | | | | | | \--* CNS_INT long 3 $24b N011 ( 1, 1) [001282] ------------ | | | | | \--* LCL_VAR long V71 cse6 u:1 $6e2 N013 ( 1, 1) [000954] -------N---- | | | | \--* CNS_INT long 3 $24b N015 ( 1, 1) [000956] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N023 ( 1, 1) [001256] ------------ | | \--* LCL_VAR byref V66 cse1 u:1 N025 ( 1, 1) [000947] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N028 ( 1, 1) [000213] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 Working on the replacement of the CSE #08 use at [000965] in BB34 optValnumCSE morphed tree: N016 ( 18, 20) [000246] -A-XG---R--- * ASG ref N015 ( 1, 1) [000245] D------N---- +--* LCL_VAR ref V17 tmp3 d:1 N014 ( 18, 20) [000973] ---XG------- \--* COMMA ref N003 ( 6, 9) [000966] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000236] ------------ | +--* LCL_VAR int V09 loc5 u:2 $3c4 N002 ( 1, 1) [001327] ------------ | \--* LCL_VAR int V76 cse11 N013 ( 12, 11) [000977] *---G------- \--* IND ref N012 ( 9, 9) [000976] ----G------- \--* ADDR byref Zero Fseq[key] $93 N011 ( 5, 5) [000237] a---G--N---- \--* IND struct N010 ( 4, 4) [000972] -------N---- \--* ADD byref $91 N004 ( 1, 1) [000963] ------------ +--* LCL_VAR ref V04 loc0 u:1 N009 ( 3, 3) [000971] -------N---- \--* ADD long $6e4 N007 ( 2, 2) [000969] -------N---- +--* LSH long $6e3 N005 ( 1, 1) [001284] ------------ | +--* LCL_VAR long V71 cse6 u:1 $6e2 N006 ( 1, 1) [000968] -------N---- | \--* CNS_INT long 3 $24b N008 ( 1, 1) [000970] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 Working on the replacement of the CSE #08 use at [000230] in BB42 optValnumCSE morphed tree: N004 ( 5, 5) [000232] ------------ * JTRUE void N003 ( 3, 3) [000231] N------N-U-- \--* LT int N001 ( 1, 1) [001328] ------------ +--* LCL_VAR int V76 cse11 N002 ( 1, 1) [000228] ------------ \--* LCL_VAR int V07 loc3 u:4 $81a Working on the replacement of the CSE #08 use at [001035] in BB45 optValnumCSE morphed tree: N030 ( 45, 44) [000688] -A-XG---R--- * ASG bool N029 ( 3, 2) [000687] D------N---- +--* LCL_VAR int V49 tmp35 d:1 N028 ( 41, 41) [000184] -A-XG------- \--* GE int N026 ( 36, 39) [000182] -A-XG------- +--* ADD int N024 ( 34, 37) [001050] -A-XG------- | +--* NEG int N023 ( 33, 36) [000181] *A-XG------- | | \--* IND int N022 ( 31, 34) [001029] -A-XG--N---- | | \--* ADD byref $29c N020 ( 30, 33) [001044] -A-XG------- | | +--* COMMA byref N003 ( 3, 3) [001032] -A--G---R--- | | | +--* ASG int N002 ( 1, 1) [001031] D------N---- | | | | +--* LCL_VAR int V62 tmp48 d:1 N001 ( 3, 2) [001309] ------------ | | | | \--* LCL_VAR int V74 cse9 u:1 N019 ( 27, 30) [001043] ---XG------- | | | \--* COMMA byref N006 ( 6, 9) [001036] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N004 ( 1, 1) [001033] ------------ | | | | +--* LCL_VAR int V62 tmp48 u:1 N005 ( 1, 1) [001329] ------------ | | | | \--* LCL_VAR int V76 cse11 N018 ( 21, 21) [001049] ----G------- | | | \--* ADDR byref $88 N017 ( 11, 11) [000179] a---G--N---- | | | \--* IND struct N016 ( 10, 10) [001042] -------N---- | | | \--* ADD byref $88 N007 ( 1, 1) [001030] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N015 ( 9, 9) [001041] -------N---- | | | \--* ADD long N013 ( 8, 8) [001039] -------N---- | | | +--* LSH long N011 ( 7, 7) [001048] ------------ | | | | +--* MUL long N009 ( 2, 3) [001037] ------------ | | | | | +--* CAST long <- int N008 ( 1, 1) [001034] i----------- | | | | | | \--* LCL_VAR int V62 tmp48 u:1 (last use) N010 ( 1, 1) [001047] ------------ | | | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [001038] -------N---- | | | | \--* CNS_INT long 3 $24b N014 ( 1, 1) [001040] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N021 ( 1, 1) [001028] ------------ | | \--* CNS_INT long 20 field offset Fseq[next] $24c N025 ( 1, 1) [000175] ------------ | \--* CNS_INT int -3 $e1 N027 ( 1, 1) [000183] ------------ \--* CNS_INT int -1 $c4 Working on the replacement of the CSE #08 use at [001064] in BB47 optValnumCSE morphed tree: N034 ( 42, 45) [000200] -A-XG------- * ASG int $VN.Void N004 ( 4, 4) [000199] D--XG--N---- +--* IND int $732 N003 ( 2, 2) [001056] -------N---- | \--* ADD byref $295 N001 ( 1, 1) [000190] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001055] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N033 ( 37, 40) [000198] -A-XG------- \--* ADD int N031 ( 35, 38) [001079] -A-XG------- +--* NEG int N030 ( 34, 37) [000197] *A-XG------- | \--* IND int N029 ( 32, 35) [001058] -A-XG--N---- | \--* ADD byref $2a3 N027 ( 31, 34) [001073] -A-XG------- | +--* COMMA byref N010 ( 4, 4) [001061] -A-XG---R--- | | +--* ASG int N009 ( 1, 1) [001060] D------N---- | | | +--* LCL_VAR int V63 tmp49 d:1 N008 ( 4, 4) [000194] ---XG------- | | | \--* IND int N007 ( 2, 2) [001075] -------N---- | | | \--* ADD byref $295 N005 ( 1, 1) [000193] ------------ | | | +--* LCL_VAR ref V00 this u:1 $100 N006 ( 1, 1) [001074] ------------ | | | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N026 ( 27, 30) [001072] ---XG------- | | \--* COMMA byref N013 ( 6, 9) [001065] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N011 ( 1, 1) [001062] ------------ | | | +--* LCL_VAR int V63 tmp49 u:1 N012 ( 1, 1) [001330] ------------ | | | \--* LCL_VAR int V76 cse11 N025 ( 21, 21) [001078] ----G------- | | \--* ADDR byref $8a N024 ( 11, 11) [000195] a---G--N---- | | \--* IND struct N023 ( 10, 10) [001071] -------N---- | | \--* ADD byref $8a N014 ( 1, 1) [001059] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N022 ( 9, 9) [001070] -------N---- | | \--* ADD long N020 ( 8, 8) [001068] -------N---- | | +--* LSH long N018 ( 7, 7) [001077] ------------ | | | +--* MUL long N016 ( 2, 3) [001066] ------------ | | | | +--* CAST long <- int N015 ( 1, 1) [001063] i----------- | | | | | \--* LCL_VAR int V63 tmp49 u:1 (last use) N017 ( 1, 1) [001076] ------------ | | | | \--* CNS_INT long 3 $24b N019 ( 1, 1) [001067] -------N---- | | | \--* CNS_INT long 3 $24b N021 ( 1, 1) [001069] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N028 ( 1, 1) [001057] ------------ | \--* CNS_INT long 20 field offset Fseq[next] $24c N032 ( 1, 1) [000191] ------------ \--* CNS_INT int -3 $e1 Working on the replacement of the CSE #08 use at [000078] in BB48 optValnumCSE morphed tree: N004 ( 7, 6) [000080] ------------ * JTRUE void N003 ( 5, 4) [000079] N------N-U-- \--* NE int N001 ( 1, 1) [001331] ------------ +--* LCL_VAR int V76 cse11 N002 ( 3, 2) [000076] ------------ \--* LCL_VAR int V13 loc9 u:1 Considering CSE #05 {$401, $2f4} [def=100.000000, use=100.000000, cost= 3, call] CSE Expression : N002 ( 3, 3) CSE #05 (def)[000583] ---X-------- * ARR_LENGTH int N001 ( 1, 1) [000582] ------------ \--* LCL_VAR ref V39 tmp25 u:1 Conservative CSE Promotion (300.000000 < 600.000000) cseRefCnt=300.000000, aggressiveRefCnt=1050.000000, moderateRefCnt=600.000000 defCnt=100.000000, useCnt=100.000000, cost=3, size=3, LiveAcrossCall def_cost=2, use_cost=3, extra_no_cost=0, extra_yes_cost=0 CSE cost savings check (300.000000 >= 500.000000) fails Did Not promote this CSE Considering CSE #12 {$1be, $4 } [def=100.000000, use=100.000000, cost= 3 ] CSE Expression : N002 ( 3, 4) CSE #12 (def)[000909] ------------ * CAST int <- ubyte <- int $1be N001 ( 2, 2) [000429] ------------ \--* LCL_VAR int V03 arg3 u:1 $140 Conservative CSE Promotion (not enregisterable) (300.000000 < 600.000000) cseRefCnt=300.000000, aggressiveRefCnt=1050.000000, moderateRefCnt=600.000000 defCnt=100.000000, useCnt=100.000000, cost=3, size=4 def_cost=2, use_cost=2, extra_no_cost=8, extra_yes_cost=0 CSE cost savings check (308.000000 >= 400.000000) fails Did Not promote this CSE Considering CSE #21 {$40a, $7c8} [def=50.000000, use=50.000000, cost= 3, call] CSE Expression : N003 ( 3, 3) CSE #21 (def)[001120] ---X-------- * ARR_LENGTH int $73d N002 ( 1, 1) [000094] ------------ \--* LCL_VAR ref V04 loc0 u:2 $684 Conservative CSE Promotion (150.000000 < 600.000000) cseRefCnt=150.000000, aggressiveRefCnt=1050.000000, moderateRefCnt=600.000000 defCnt=50.000000, useCnt=50.000000, cost=3, size=3, LiveAcrossCall def_cost=2, use_cost=3, extra_no_cost=0, extra_yes_cost=0 CSE cost savings check (150.000000 >= 250.000000) fails Did Not promote this CSE Skipped CSE #06 because use count is 0 Skipped CSE #09 because use count is 0 Skipped CSE #13 because use count is 0 Considering CSE #19 {$310, $4 } [def=100.000000, use=50.000000, cost= 2, call] CSE Expression : N003 ( 2, 3) CSE #19 (def)[000605] ---------U-- * CAST long <- ulong <- uint $310 N002 ( 1, 1) [000047] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 Conservative CSE Promotion (250.000000 < 600.000000) cseRefCnt=250.000000, aggressiveRefCnt=1050.000000, moderateRefCnt=600.000000 defCnt=100.000000, useCnt=50.000000, cost=2, size=3, LiveAcrossCall def_cost=2, use_cost=3, extra_no_cost=0, extra_yes_cost=0 CSE cost savings check (100.000000 >= 350.000000) fails Did Not promote this CSE *************** Finishing PHASE Optimize Valnum CSEs *************** Starting PHASE Assertion prop *************** In optAssertionPropMain() Blocks/Trees at start of phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal Loop1 gcsafe BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe BB36 [0108] 1 BB34 1 [???..???) i gcsafe BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen BB54 [0044] 2 BB48,BB53 0.50 [261..276) i BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} ***** BB01 STMT00000 (IL 0x000...0x006) N004 ( 5, 5) [000003] ------------ * JTRUE void N003 ( 3, 3) [000002] J------N---- \--* EQ int $180 N001 ( 1, 1) [000000] ------------ +--* LCL_VAR ref V01 arg1 u:1 $101 N002 ( 1, 1) [000001] ------------ \--* CNS_INT ref null $VN.Null ------------ BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00001 (IL 0x00E...0x014) N007 ( 8, 8) [000008] ---XG------- * JTRUE void N006 ( 6, 6) [000007] J--XG--N---- \--* NE int N004 ( 4, 4) [000005] ---XG------- +--* IND ref N003 ( 2, 2) [000814] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000004] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000813] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] $240 N005 ( 1, 1) [000006] ------------ \--* CNS_INT ref null $VN.Null ------------ BB03 [016..01E), preds={BB02} succs={BB04} ***** BB03 STMT00085 (IL ???... ???) N005 ( 16, 10) [000528] --CXG------- * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize $1c2 N003 ( 1, 1) [000526] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N004 ( 1, 1) [000527] ------------ arg1 in rdx \--* CNS_INT int 0 $c0 ------------ BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ***** BB04 STMT00088 (IL 0x01E... ???) N008 ( 9, 6) [000544] -A-XG---R--- * ASG bool N007 ( 1, 1) [000543] D------N---- +--* LCL_VAR int V33 tmp19 d:1 N006 ( 9, 6) [000012] N--XG------- \--* NE int N004 ( 4, 4) [000010] ---XG------- +--* IND ref N003 ( 2, 2) [000818] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000009] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000817] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] $240 N005 ( 1, 1) [000011] ------------ \--* CNS_INT ref null $VN.Null ***** BB04 STMT00091 (IL 0x01E... ???) N008 ( 5, 13) [000554] -A--G---R--- * ASG ref $105 N007 ( 1, 1) [000553] D------N---- +--* LCL_VAR ref V34 tmp20 d:1 $105 N006 ( 5, 13) [001293] -A--G------- \--* COMMA ref $105 N004 ( 4, 12) [001291] -A--G---R--- +--* ASG ref $VN.Void N003 ( 1, 1) [001290] D------N---- | +--* LCL_VAR ref V73 cse8 d:1 $105 N002 ( 4, 12) [000538] #---G------- | \--* IND ref $105 N001 ( 2, 10) [000537] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 N005 ( 1, 1) [001292] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB04 STMT00092 (IL 0x01E... ???) N003 ( 1, 3) [000556] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000555] D------N---- +--* LCL_VAR ref V35 tmp21 d:1 $105 N001 ( 1, 1) [001294] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB04 STMT00089 (IL 0x01E... ???) N004 ( 5, 5) [000549] ------------ * JTRUE void N003 ( 3, 3) [000548] J------N---- \--* NE int N001 ( 1, 1) [000546] ------------ +--* LCL_VAR int V33 tmp19 u:1 (last use) N002 ( 1, 1) [000547] ------------ \--* CNS_INT int 0 $c0 ------------ BB05 [01E..01F), preds={BB04} succs={BB06} ***** BB05 STMT00090 (IL 0x01E... ???) N005 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 1, 1) [000550] ------------ arg0 in rcx +--* LCL_VAR ref V35 tmp21 u:1 (last use) $105 N004 ( 1, 1) [000551] ------------ arg1 in rdx \--* LCL_VAR ref V35 tmp21 u:1 (last use) $105 ------------ BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} ***** BB06 STMT00003 (IL 0x02C... ???) N006 ( 4, 4) [000018] -A-XG---R--- * ASG ref N005 ( 1, 1) [000017] D------N---- +--* LCL_VAR ref V04 loc0 d:1 N004 ( 4, 4) [000016] ---XG------- \--* IND ref N003 ( 2, 2) [000822] -------N---- \--* ADD byref $281 N001 ( 1, 1) [000015] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000821] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] $241 ***** BB06 STMT00094 (IL 0x033... ???) N005 ( 6, 3) [000566] -A------R--- * ASG bool N004 ( 1, 1) [000565] D------N---- +--* LCL_VAR int V36 tmp22 d:1 N003 ( 6, 3) [000021] N----------- \--* NE int N001 ( 1, 1) [000019] ------------ +--* LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000020] ------------ \--* CNS_INT ref null $VN.Null ***** BB06 STMT00097 (IL 0x033... ???) N003 ( 1, 3) [000576] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000575] D------N---- +--* LCL_VAR ref V37 tmp23 d:1 $105 N001 ( 1, 1) [001295] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB06 STMT00095 (IL 0x033... ???) N004 ( 5, 5) [000571] ------------ * JTRUE void N003 ( 3, 3) [000570] J------N---- \--* NE int N001 ( 1, 1) [000568] ------------ +--* LCL_VAR int V36 tmp22 u:1 (last use) N002 ( 1, 1) [000569] ------------ \--* CNS_INT int 0 $c0 ------------ BB07 [033..034), preds={BB06} succs={BB08} ***** BB07 STMT00096 (IL 0x033... ???) N006 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N004 ( 4, 12) [000824] #---G------- arg0 in rcx +--* IND ref $106 N003 ( 2, 10) [000823] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" $46 N005 ( 1, 1) [000573] ------------ arg1 in rdx \--* LCL_VAR ref V37 tmp23 u:1 (last use) $105 ------------ BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} ***** BB08 STMT00005 (IL 0x041... ???) N006 ( 4, 4) [000028] -A-XG---R--- * ASG ref N005 ( 1, 1) [000027] D------N---- +--* LCL_VAR ref V05 loc1 d:1 N004 ( 4, 4) [000026] ---XG------- \--* IND ref N003 ( 2, 2) [000828] -------N---- \--* ADD byref $282 N001 ( 1, 1) [000025] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000827] ------------ \--* CNS_INT long 24 field offset Fseq[_comparer] $242 ***** BB08 STMT00006 (IL 0x048...0x049) N004 ( 5, 5) [000032] ------------ * JTRUE void N003 ( 3, 3) [000031] J------N---- \--* EQ int N001 ( 1, 1) [000029] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000030] ------------ \--* CNS_INT ref null $VN.Null ------------ BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} ***** BB09 STMT00079 (IL 0x04B...0x052) N004 ( 3, 3) [000489] -A-X----R--- * ASG long $2e8 N003 ( 1, 1) [000488] D------N---- +--* LCL_VAR long V29 tmp15 d:1 $2e7 N002 ( 3, 2) [000487] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000486] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB09 STMT00149 (IL ???... ???) N015 ( 21, 18) [001148] -A---------- * JTRUE void N014 ( 19, 16) [000505] JA-----N---- \--* EQ int N012 ( 17, 14) [001268] -A---------- +--* COMMA long N010 ( 14, 12) [001266] -A------R--- | +--* ASG long $VN.Void N009 ( 3, 2) [001265] D------N---- | | +--* LCL_VAR long V68 cse3 d:1 N008 ( 10, 9) [000501] n----------- | | \--* IND long N007 ( 8, 7) [000497] -------N---- | | \--* ADD long $307 N005 ( 7, 6) [000495] #----------- | | +--* IND long $2ea N004 ( 4, 4) [000494] #----------- | | | \--* IND long $2e9 N003 ( 2, 2) [000493] -------N---- | | | \--* ADD long $306 N001 ( 1, 1) [000491] ------------ | | | +--* LCL_VAR long V29 tmp15 u:1 $2e7 N002 ( 1, 1) [000492] ------------ | | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000496] ------------ | | \--* CNS_INT long 64 $245 N011 ( 3, 2) [001267] ------------ | \--* LCL_VAR long V68 cse3 u:1 N013 ( 1, 1) [000504] ------------ \--* CNS_INT long 0 $243 ------------ BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} ***** BB10 STMT00150 (IL ???... ???) N003 ( 3, 3) [001150] -A------R--- * ASG long N002 ( 1, 1) [001149] D------N---- +--* LCL_VAR long V31 tmp17 d:3 N001 ( 3, 2) [001269] ------------ \--* LCL_VAR long V68 cse3 u:1 ------------ BB11 [???..???), preds={BB09} succs={BB12} ***** BB11 STMT00151 (IL ???... ???) N007 ( 17, 18) [001152] -AC-G---R--- * ASG long $308 N006 ( 1, 1) [001151] D------N---- +--* LCL_VAR long V31 tmp17 d:2 $308 N005 ( 17, 18) [000503] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $308 N003 ( 1, 1) [000490] ------?----- arg0 in rcx +--* LCL_VAR long V29 tmp15 u:1 (last use) $2e7 N004 ( 2, 10) [000502] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $49 ------------ BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} ***** BB12 STMT00178 (IL ???... ???) N005 ( 0, 0) [001217] -A------R--- * ASG long N004 ( 0, 0) [001215] D------N---- +--* LCL_VAR long V31 tmp17 d:1 N003 ( 0, 0) [001216] ------------ \--* PHI long N001 ( 0, 0) [001247] ------------ pred BB10 +--* PHI_ARG long V31 tmp17 u:3 N002 ( 0, 0) [001246] ------------ pred BB11 \--* PHI_ARG long V31 tmp17 u:2 $308 ***** BB12 STMT00083 (IL ???... ???) N010 ( 31, 15) [000524] -ACXG---R--- * ASG int $1c7 N009 ( 3, 2) [000523] D------N---- +--* LCL_VAR int V15 tmp1 d:3 $1c7 N008 ( 27, 12) [000522] --CXG------- \--* CALL ind stub int $1c7 N007 ( 1, 1) [000521] ------------ calli tgt \--* LCL_VAR long V31 tmp17 u:1 (last use) $342 N004 ( 1, 1) [000484] ------------ this in rcx +--* LCL_VAR ref V05 loc1 u:1 N005 ( 1, 1) [000831] ------------ arg1 in r11 +--* LCL_VAR long V31 tmp17 u:1 r11 REG r11 $342 N006 ( 1, 1) [000500] ------------ arg2 in rdx \--* LCL_VAR ref V01 arg1 u:1 $101 ------------ BB13 [054..061), preds={BB08} succs={BB14} ***** BB13 STMT00007 (IL 0x054...0x05C) N013 ( 34, 21) [000038] -ACXG---R--- * ASG int $1c5 N012 ( 3, 2) [000037] D------N---- +--* LCL_VAR int V15 tmp1 d:2 $1c5 N011 ( 30, 18) [000035] --CXG------- \--* CALLV vt-ind int System.Object.GetHashCode $1c5 N010 ( 9, 8) [000843] n--X-------- control expr \--* IND long N009 ( 7, 6) [000842] ---X---N---- \--* ADD long $303 N007 ( 6, 5) [000840] #--X-------- +--* IND long $2e6 N006 ( 4, 3) [000839] ---X---N---- | \--* ADD long $301 N004 ( 3, 2) [000837] #--X-------- | +--* IND long $2e4 N003 ( 1, 1) [000836] ------------ | | \--* LCL_VAR ref V01 arg1 u:1 $101 N005 ( 1, 1) [000838] ------------ | \--* CNS_INT int 72 $c9 N008 ( 1, 1) [000841] ------------ \--* CNS_INT int 24 $ca N002 ( 1, 1) [000033] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 $101 ------------ BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ***** BB14 STMT00177 (IL ???... ???) N005 ( 0, 0) [001214] -A------R--- * ASG int N004 ( 0, 0) [001212] D------N---- +--* LCL_VAR int V15 tmp1 d:1 N003 ( 0, 0) [001213] ------------ \--* PHI int N001 ( 0, 0) [001245] ------------ pred BB12 +--* PHI_ARG int V15 tmp1 u:3 $1c7 N002 ( 0, 0) [001244] ------------ pred BB13 \--* PHI_ARG int V15 tmp1 u:2 $1c5 ***** BB14 STMT00008 (IL ???...0x061) N003 ( 3, 3) [000042] -A------R--- * ASG int $3c0 N002 ( 1, 1) [000041] D------N---- +--* LCL_VAR int V06 loc2 d:1 $3c0 N001 ( 3, 2) [000040] ------------ \--* LCL_VAR int V15 tmp1 u:1 (last use) $3c0 ***** BB14 STMT00009 (IL 0x062...0x063) N003 ( 1, 3) [000045] -A------R--- * ASG int $c0 N002 ( 1, 1) [000044] D------N---- +--* LCL_VAR int V07 loc3 d:1 $c0 N001 ( 1, 1) [000043] ------------ \--* CNS_INT int 0 $c0 ***** BB14 STMT00098 (IL 0x064... ???) N006 ( 4, 4) [000580] -A-XG---R--- * ASG ref N005 ( 1, 1) [000579] D------N---- +--* LCL_VAR ref V39 tmp25 d:1 N004 ( 4, 4) [000578] ---XG------- \--* IND ref N003 ( 2, 2) [000845] -------N---- \--* ADD byref $280 N001 ( 1, 1) [000046] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000844] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] $240 ***** BB14 STMT00105 (IL 0x064... ???) N004 ( 3, 3) [000629] -A-X----R--- * ASG int N003 ( 1, 1) [000628] D------N---- +--* LCL_VAR int V40 tmp26 d:1 N002 ( 3, 3) [000583] ---X-------- \--* ARR_LENGTH int N001 ( 1, 1) [000582] ------------ \--* LCL_VAR ref V39 tmp25 u:1 ***** BB14 STMT00106 (IL 0x064... ???) N006 ( 4, 4) [000631] -A-XG---R--- * ASG long N005 ( 1, 1) [000630] D------N---- +--* LCL_VAR long V41 tmp27 d:1 N004 ( 4, 4) [000585] ---XG------- \--* IND long N003 ( 2, 2) [000847] -------N---- \--* ADD byref $283 N001 ( 1, 1) [000584] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000846] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 ***** BB14 STMT00108 (IL 0x064... ???) N005 ( 6, 6) [000642] -A------R--- * ASG bool N004 ( 1, 1) [000641] D------N---- +--* LCL_VAR int V43 tmp29 d:1 N003 ( 6, 6) [000599] N--------U-- \--* LE int N001 ( 1, 1) [000597] ------------ +--* LCL_VAR int V40 tmp26 u:1 N002 ( 1, 4) [000598] ------------ \--* CNS_INT int 0x7FFFFFFF $ce ***** BB14 STMT00111 (IL 0x064... ???) N003 ( 1, 3) [000652] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000651] D------N---- +--* LCL_VAR ref V44 tmp30 d:1 $105 N001 ( 1, 1) [001296] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB14 STMT00112 (IL 0x064... ???) N003 ( 1, 3) [000654] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000653] D------N---- +--* LCL_VAR ref V45 tmp31 d:1 $105 N001 ( 1, 1) [001297] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB14 STMT00109 (IL 0x064... ???) N004 ( 5, 5) [000647] ------------ * JTRUE void N003 ( 3, 3) [000646] J------N---- \--* NE int N001 ( 1, 1) [000644] ------------ +--* LCL_VAR int V43 tmp29 u:1 (last use) N002 ( 1, 1) [000645] ------------ \--* CNS_INT int 0 $c0 ------------ BB15 [064..065), preds={BB14} succs={BB16} ***** BB15 STMT00110 (IL 0x064... ???) N005 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 1, 1) [000648] ------------ arg0 in rcx +--* LCL_VAR ref V45 tmp31 u:1 (last use) $105 N004 ( 1, 1) [000649] ------------ arg1 in rdx \--* LCL_VAR ref V45 tmp31 u:1 (last use) $105 ------------ BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} ***** BB16 STMT00103 (IL 0x064... ???) N016 ( 20, 21) [000619] -A------R--- * ASG int N015 ( 1, 1) [000618] D------N---- +--* LCL_VAR int V42 tmp28 d:1 N014 ( 20, 21) [000617] ------------ \--* CAST int <- uint <- long N013 ( 19, 19) [000616] ------------ \--* RSZ long N011 ( 17, 17) [000614] ------------ +--* MUL long N008 ( 11, 11) [000611] ------------ | +--* ADD long N006 ( 9, 9) [000608] ------------ | | +--* RSZ long N004 ( 7, 7) [000606] ------------ | | | +--* MUL long N001 ( 1, 1) [000604] ------------ | | | | +--* LCL_VAR long V41 tmp27 u:1 (last use) N003 ( 2, 3) [000605] ---------U-- | | | | \--* CAST long <- ulong <- uint $310 N002 ( 1, 1) [000047] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 $3c0 N005 ( 1, 1) [000607] ------------ | | | \--* CNS_INT int 32 $d2 N007 ( 1, 1) [000610] ------------ | | \--* CNS_INT long 1 $247 N010 ( 2, 3) [000613] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000612] ------------ | \--* LCL_VAR int V40 tmp26 u:1 N012 ( 1, 1) [000615] ------------ \--* CNS_INT int 32 $d2 ***** BB16 STMT00114 (IL 0x064... ???) N007 ( 27, 7) [000665] -A-X----R--- * ASG bool N006 ( 1, 1) [000664] D------N---- +--* LCL_VAR int V46 tmp32 d:1 N005 ( 27, 7) [000624] ---X-------- \--* EQ int N003 ( 22, 5) [000623] ---X-------- +--* UMOD int N001 ( 1, 1) [000621] ------------ | +--* LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000622] ------------ | \--* LCL_VAR int V40 tmp26 u:1 (last use) N004 ( 1, 1) [000620] ------------ \--* LCL_VAR int V42 tmp28 u:1 ***** BB16 STMT00117 (IL 0x064... ???) N003 ( 1, 3) [000675] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000674] D------N---- +--* LCL_VAR ref V47 tmp33 d:1 $105 N001 ( 1, 1) [001298] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB16 STMT00118 (IL 0x064... ???) N003 ( 1, 3) [000677] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000676] D------N---- +--* LCL_VAR ref V48 tmp34 d:1 $105 N001 ( 1, 1) [001299] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB16 STMT00115 (IL 0x064... ???) N004 ( 5, 5) [000670] ------------ * JTRUE void N003 ( 3, 3) [000669] J------N---- \--* NE int N001 ( 1, 1) [000667] ------------ +--* LCL_VAR int V46 tmp32 u:1 (last use) N002 ( 1, 1) [000668] ------------ \--* CNS_INT int 0 $c0 ------------ BB17 [064..065), preds={BB16} succs={BB18} ***** BB17 STMT00116 (IL 0x064... ???) N005 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 1, 1) [000671] ------------ arg0 in rcx +--* LCL_VAR ref V48 tmp34 u:1 (last use) $105 N004 ( 1, 1) [000672] ------------ arg1 in rdx \--* LCL_VAR ref V48 tmp34 u:1 (last use) $105 ------------ BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} ***** BB18 STMT00100 (IL 0x064... ???) N017 ( 19, 24) [000591] -A-XG---R--- * ASG byref N016 ( 1, 1) [000590] D------N---- +--* LCL_VAR byref V38 tmp24 d:1 $81 N015 ( 19, 24) [000862] ---XG------- \--* COMMA byref N004 ( 8, 11) [000855] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000627] ------------ | +--* LCL_VAR int V42 tmp28 u:1 N003 ( 3, 3) [000854] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000581] ------------ | \--* LCL_VAR ref V39 tmp25 u:1 N014 ( 11, 13) [000863] ----G------- \--* ADDR byref $81 N013 ( 6, 7) [000588] a---G--N---- \--* IND int N012 ( 5, 6) [000861] -------N---- \--* ADD byref $81 N005 ( 1, 1) [000852] ------------ +--* LCL_VAR ref V39 tmp25 u:1 (last use) N011 ( 4, 5) [000860] -------N---- \--* ADD long N009 ( 3, 4) [000858] -------N---- +--* LSH long N007 ( 2, 3) [000856] ------------ | +--* CAST long <- int N006 ( 1, 1) [000853] i----------- | | \--* LCL_VAR int V42 tmp28 u:1 (last use) N008 ( 1, 1) [000857] -------N---- | \--* CNS_INT long 2 $248 N010 ( 1, 1) [000859] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB18 STMT00011 (IL ???... ???) N003 ( 5, 4) [000051] -A------R--- * ASG byref $81 N002 ( 3, 2) [000050] D------N---- +--* LCL_VAR byref V08 loc4 d:1 $81 N001 ( 1, 1) [000592] ------------ \--* LCL_VAR byref V38 tmp24 u:1 $81 ***** BB18 STMT00012 (IL 0x06D...0x072) N006 ( 5, 4) [000057] -A-XG---R--- * ASG int N005 ( 1, 1) [000056] D------N---- +--* LCL_VAR int V09 loc5 d:1 N004 ( 5, 4) [000055] ---XG------- \--* ADD int N002 ( 3, 2) [000053] *--XG------- +--* IND int N001 ( 1, 1) [000052] ------------ | \--* LCL_VAR byref V08 loc4 u:1 (last use) $81 N003 ( 1, 1) [000054] ------------ \--* CNS_INT int -1 $c4 ***** BB18 STMT00013 (IL 0x074...0x075) N004 ( 5, 5) [000061] ------------ * JTRUE void N003 ( 3, 3) [000060] J------N---- \--* NE int N001 ( 1, 1) [000058] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000059] ------------ \--* CNS_INT ref null $VN.Null ------------ BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} ***** BB19 STMT00059 (IL 0x0FF...0x104) N004 ( 3, 3) [000356] -A-X----R--- * ASG long $2e8 N003 ( 1, 1) [000355] D------N---- +--* LCL_VAR long V24 tmp10 d:1 $2e7 N002 ( 3, 2) [000354] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000353] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB19 STMT00152 (IL ???... ???) N015 ( 21, 18) [001153] -A---------- * JTRUE void N014 ( 19, 16) [000369] JA-----N---- \--* EQ int N012 ( 17, 14) [001273] -A---------- +--* COMMA long N010 ( 14, 12) [001271] -A------R--- | +--* ASG long $VN.Void N009 ( 3, 2) [001270] D------N---- | | +--* LCL_VAR long V69 cse4 d:1 N008 ( 10, 9) [000365] n----------- | | \--* IND long N007 ( 8, 7) [000364] -------N---- | | \--* ADD long $324 N005 ( 7, 6) [000362] #----------- | | +--* IND long $2ea N004 ( 4, 4) [000361] #----------- | | | \--* IND long $2e9 N003 ( 2, 2) [000360] -------N---- | | | \--* ADD long $306 N001 ( 1, 1) [000358] ------------ | | | +--* LCL_VAR long V24 tmp10 u:1 $2e7 N002 ( 1, 1) [000359] ------------ | | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000363] ------------ | | \--* CNS_INT long 32 $24a N011 ( 3, 2) [001272] ------------ | \--* LCL_VAR long V69 cse4 u:1 N013 ( 1, 1) [000368] ------------ \--* CNS_INT long 0 $243 ------------ BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} ***** BB20 STMT00153 (IL ???... ???) N003 ( 7, 5) [001155] -A------R--- * ASG long N002 ( 3, 2) [001154] D------N---- +--* LCL_VAR long V25 tmp11 d:3 N001 ( 3, 2) [001274] ------------ \--* LCL_VAR long V69 cse4 u:1 ------------ BB21 [???..???), preds={BB19} succs={BB22} ***** BB21 STMT00154 (IL ???... ???) N007 ( 21, 21) [001157] -AC-G---R--- * ASG long $325 N006 ( 3, 2) [001156] D------N---- +--* LCL_VAR long V25 tmp11 d:2 $325 N005 ( 17, 18) [000367] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $325 N003 ( 1, 1) [000357] ------?----- arg0 in rcx +--* LCL_VAR long V24 tmp10 u:1 (last use) $2e7 N004 ( 2, 10) [000366] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $4f ------------ BB22 [???..106), preds={BB20,BB21} succs={BB23} ***** BB22 STMT00172 (IL ???... ???) N005 ( 0, 0) [001199] -A------R--- * ASG long N004 ( 0, 0) [001197] D------N---- +--* LCL_VAR long V25 tmp11 d:1 N003 ( 0, 0) [001198] ------------ \--* PHI long N001 ( 0, 0) [001243] ------------ pred BB20 +--* PHI_ARG long V25 tmp11 u:3 N002 ( 0, 0) [001242] ------------ pred BB21 \--* PHI_ARG long V25 tmp11 u:2 $325 ***** BB22 STMT00062 (IL ???... ???) N005 ( 17, 8) [000386] -ACXG---R--- * ASG ref $223 N004 ( 1, 1) [000385] D------N---- +--* LCL_VAR ref V12 loc8 d:1 $223 N003 ( 17, 8) [000352] --CXG------- \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default $223 N002 ( 3, 2) [000382] ------------ arg0 in rcx \--* LCL_VAR long V25 tmp11 u:1 (last use) $344 ------------ BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} ***** BB23 STMT00165 (IL ???... ???) N005 ( 0, 0) [001178] -A------R--- * ASG int N004 ( 0, 0) [001176] D------N---- +--* LCL_VAR int V07 loc3 d:5 N003 ( 0, 0) [001177] ------------ \--* PHI int N001 ( 0, 0) [001238] ------------ pred BB27 +--* PHI_ARG int V07 loc3 u:6 N002 ( 0, 0) [001235] ------------ pred BB22 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB23 STMT00164 (IL ???... ???) N005 ( 0, 0) [001175] -A------R--- * ASG int N004 ( 0, 0) [001173] D------N---- +--* LCL_VAR int V09 loc5 d:4 N003 ( 0, 0) [001174] ------------ \--* PHI int N001 ( 0, 0) [001239] ------------ pred BB27 +--* PHI_ARG int V09 loc5 u:5 N002 ( 0, 0) [001236] ------------ pred BB22 \--* PHI_ARG int V09 loc5 u:1 ***** BB23 STMT00063 (IL 0x106...0x10B) N009 ( 8, 8) [000391] -A-X-------- * JTRUE void N008 ( 6, 6) [000390] NA-X---N-U-- \--* LE int N006 ( 4, 4) [001318] -A-X-------- +--* COMMA int N004 ( 3, 3) [001316] -A-X----R--- | +--* ASG int $VN.Void N003 ( 1, 1) [001315] D------N---- | | +--* LCL_VAR int V76 cse11 N002 ( 3, 3) [000389] ---X-------- | | \--* ARR_LENGTH int N001 ( 1, 1) [000388] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N005 ( 1, 1) [001317] ------------ | \--* LCL_VAR int V76 cse11 N007 ( 1, 1) [000387] ------------ \--* LCL_VAR int V09 loc5 u:4 $3c2 ------------ BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} ***** BB24 STMT00064 (IL 0x110...0x11E) N030 ( 37, 40) [000399] -A-XG------- * JTRUE void N029 ( 35, 38) [000398] NA-XG--N-U-- \--* NE int N027 ( 33, 36) [000396] *A-XG------- +--* IND int N026 ( 31, 34) [000868] -A-XG--N---- | \--* ADD byref $28c N024 ( 30, 33) [001251] -A-XG------- | +--* COMMA byref N022 ( 29, 32) [001249] -A-XG---R--- | | +--* ASG byref $VN.Void N021 ( 1, 1) [001248] D------N---- | | | +--* LCL_VAR byref V65 cse0 d:1 N020 ( 29, 32) [000879] -A-XG------- | | | \--* COMMA byref N003 ( 6, 9) [000872] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000393] ------------ | | | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N002 ( 1, 1) [001319] ------------ | | | | \--* LCL_VAR int V76 cse11 N019 ( 23, 23) [000882] -A--G------- | | | \--* ADDR byref $82 N018 ( 12, 12) [000394] aA--G--N---- | | | \--* IND struct N017 ( 11, 11) [000878] -A-----N---- | | | \--* ADD byref $82 N004 ( 1, 1) [000869] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N016 ( 10, 10) [000877] -A-----N---- | | | \--* ADD long $329 N014 ( 9, 9) [000875] -A-----N---- | | | +--* LSH long $328 N012 ( 8, 8) [001278] -A---------- | | | | +--* COMMA long $327 N010 ( 7, 7) [001276] -A------R--- | | | | | +--* ASG long $VN.Void N009 ( 1, 1) [001275] D------N---- | | | | | | +--* LCL_VAR long V70 cse5 d:1 $327 N008 ( 7, 7) [000881] ------------ | | | | | | \--* MUL long $327 N006 ( 2, 3) [000873] ------------ | | | | | | +--* CAST long <- int $326 N005 ( 1, 1) [000870] i----------- | | | | | | | \--* LCL_VAR int V09 loc5 u:4 $3c2 N007 ( 1, 1) [000880] ------------ | | | | | | \--* CNS_INT long 3 $24b N011 ( 1, 1) [001277] ------------ | | | | | \--* LCL_VAR long V70 cse5 u:1 $327 N013 ( 1, 1) [000874] -------N---- | | | | \--* CNS_INT long 3 $24b N015 ( 1, 1) [000876] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N023 ( 1, 1) [001250] ------------ | | \--* LCL_VAR byref V65 cse0 u:1 N025 ( 1, 1) [000867] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N028 ( 1, 1) [000397] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 ------------ BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} ***** BB25 STMT00069 (IL 0x120...0x135) N031 ( 53, 45) [000428] --CXG------- * JTRUE void N030 ( 51, 43) [000427] J-CXG--N---- \--* NE int $1bd N028 ( 49, 41) [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals $581 N027 ( 9, 8) [000908] n--X-------- control expr | \--* IND long N026 ( 7, 6) [000907] ---X---N---- | \--* ADD long $32e N024 ( 6, 5) [000905] #--X-------- | +--* IND long $465 N023 ( 4, 3) [000904] ---X---N---- | | \--* ADD long $32c N021 ( 3, 2) [000902] #--X-------- | | +--* IND long $463 N020 ( 1, 1) [000901] ------------ | | | \--* LCL_VAR ref V12 loc8 u:1 $223 N022 ( 1, 1) [000903] ------------ | | \--* CNS_INT int 72 $c9 N025 ( 1, 1) [000906] ------------ | \--* CNS_INT int 32 $d2 N017 ( 18, 20) [000893] ---XG------- arg1 in rdx | +--* COMMA ref N006 ( 6, 9) [000886] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N004 ( 1, 1) [000420] ------------ | | | +--* LCL_VAR int V09 loc5 u:4 $3c2 N005 ( 1, 1) [001320] ------------ | | | \--* LCL_VAR int V76 cse11 N016 ( 12, 11) [000897] *---G------- | | \--* IND ref N015 ( 9, 9) [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] $84 N014 ( 5, 5) [000421] a---G--N---- | | \--* IND struct N013 ( 4, 4) [000892] -------N---- | | \--* ADD byref $82 N007 ( 1, 1) [000883] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N012 ( 3, 3) [000891] -------N---- | | \--* ADD long $329 N010 ( 2, 2) [000889] -------N---- | | +--* LSH long $328 N008 ( 1, 1) [001279] ------------ | | | +--* LCL_VAR long V70 cse5 u:1 $327 N009 ( 1, 1) [000888] -------N---- | | | \--* CNS_INT long 3 $24b N011 ( 1, 1) [000890] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N018 ( 1, 1) [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 u:1 $223 N019 ( 1, 1) [000424] ------------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 u:1 $101 N029 ( 1, 1) [000426] ------------ \--* CNS_INT int 0 $c0 ------------ BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} ***** BB26 STMT00065 (IL 0x157...0x164) N006 ( 4, 4) [000406] -A-XG---R--- * ASG int N005 ( 1, 1) [000405] D------N---- +--* LCL_VAR int V09 loc5 d:5 N004 ( 4, 4) [000404] *--XG------- \--* IND int N003 ( 2, 2) [000932] ----G--N---- \--* ADD byref $28e N001 ( 1, 1) [001252] ------------ +--* LCL_VAR byref V65 cse0 u:1 $82 N002 ( 1, 1) [000931] ------------ \--* CNS_INT long 20 field offset Fseq[next] $24c ***** BB26 STMT00066 (IL 0x166...0x169) N005 ( 3, 3) [000411] -A------R--- * ASG int $605 N004 ( 1, 1) [000410] D------N---- +--* LCL_VAR int V07 loc3 d:6 $605 N003 ( 3, 3) [000409] ------------ \--* ADD int $605 N001 ( 1, 1) [000407] ------------ +--* LCL_VAR int V07 loc3 u:5 (last use) $3c1 N002 ( 1, 1) [000408] ------------ \--* CNS_INT int 1 $c1 ***** BB26 STMT00067 (IL 0x16A...0x16E) N004 ( 5, 5) [000416] ------------ * JTRUE void N003 ( 3, 3) [000415] N------N-U-- \--* LT int N001 ( 1, 1) [001321] ------------ +--* LCL_VAR int V76 cse11 N002 ( 1, 1) [000412] ------------ \--* LCL_VAR int V07 loc3 u:6 $605 ------------ BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} ------------ BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} ***** BB28 STMT00070 (IL 0x137...0x139) N005 ( 7, 8) [000432] ------------ * JTRUE void N004 ( 5, 6) [000431] N------N-U-- \--* NE int $1bf N002 ( 3, 4) [000909] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000429] ------------ | \--* LCL_VAR int V03 arg3 u:1 $140 N003 ( 1, 1) [000430] ------------ \--* CNS_INT int 1 $c1 ------------ BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} ***** BB29 STMT00077 (IL 0x13B...0x144) N006 ( 6, 6) [000481] -A-XG------- * ASG ref $VN.Void N004 ( 4, 4) [000480] *--XG--N---- +--* IND ref $102 N003 ( 2, 2) [000911] ----G--N---- | \--* ADD byref $28d N001 ( 1, 1) [001253] ------------ | +--* LCL_VAR byref V65 cse0 u:1 $82 N002 ( 1, 1) [000910] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N005 ( 1, 1) [000479] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 ------------ BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} ***** BB30 STMT00071 (IL 0x14B...0x14D) N005 ( 7, 8) [000436] ------------ * JTRUE void N004 ( 5, 6) [000435] N------N-U-- \--* EQ int $600 N002 ( 3, 4) [000926] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000433] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) $140 N003 ( 1, 1) [000434] ------------ \--* CNS_INT int 2 $c2 ------------ BB31 [???..???) (return), preds={BB30,BB41} succs={} ***** BB31 STMT00148 (IL ???... ???) N002 ( 2, 2) [000811] ------------ * RETURN int $1f3 N001 ( 1, 1) [000437] ------------ \--* CNS_INT int 0 $c0 ------------ BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} ***** BB32 STMT00175 (IL ???... ???) N005 ( 0, 0) [001208] -A------R--- * ASG int N004 ( 0, 0) [001206] D------N---- +--* LCL_VAR int V07 loc3 d:3 N003 ( 0, 0) [001207] ------------ \--* PHI int N001 ( 0, 0) [001229] ------------ pred BB43 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [001218] ------------ pred BB18 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB32 STMT00174 (IL ???... ???) N005 ( 0, 0) [001205] -A------R--- * ASG int N004 ( 0, 0) [001203] D------N---- +--* LCL_VAR int V09 loc5 d:2 N003 ( 0, 0) [001204] ------------ \--* PHI int N001 ( 0, 0) [001230] ------------ pred BB43 +--* PHI_ARG int V09 loc5 u:3 N002 ( 0, 0) [001219] ------------ pred BB18 \--* PHI_ARG int V09 loc5 u:1 ***** BB32 STMT00014 (IL 0x177...0x17C) N009 ( 8, 8) [000066] -A-X-------- * JTRUE void N008 ( 6, 6) [000065] NA-X---N-U-- \--* LE int N006 ( 4, 4) [001325] -A-X-------- +--* COMMA int N004 ( 3, 3) [001323] -A-X----R--- | +--* ASG int $VN.Void N003 ( 1, 1) [001322] D------N---- | | +--* LCL_VAR int V76 cse11 N002 ( 3, 3) [000064] ---X-------- | | \--* ARR_LENGTH int N001 ( 1, 1) [000063] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N005 ( 1, 1) [001324] ------------ | \--* LCL_VAR int V76 cse11 N007 ( 1, 1) [000062] ------------ \--* LCL_VAR int V09 loc5 u:2 $3c4 ------------ BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} ***** BB33 STMT00039 (IL 0x17E...0x18C) N030 ( 37, 40) [000215] -A-XG------- * JTRUE void N029 ( 35, 38) [000214] NA-XG--N-U-- \--* NE int N027 ( 33, 36) [000212] *A-XG------- +--* IND int N026 ( 31, 34) [000948] -A-XG--N---- | \--* ADD byref $2ac N024 ( 30, 33) [001257] -A-XG------- | +--* COMMA byref N022 ( 29, 32) [001255] -A-XG---R--- | | +--* ASG byref $VN.Void N021 ( 1, 1) [001254] D------N---- | | | +--* LCL_VAR byref V66 cse1 d:1 N020 ( 29, 32) [000959] -A-XG------- | | | \--* COMMA byref N003 ( 6, 9) [000952] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000209] ------------ | | | | +--* LCL_VAR int V09 loc5 u:2 $3c4 N002 ( 1, 1) [001326] ------------ | | | | \--* LCL_VAR int V76 cse11 N019 ( 23, 23) [000962] -A--G------- | | | \--* ADDR byref $91 N018 ( 12, 12) [000210] aA--G--N---- | | | \--* IND struct N017 ( 11, 11) [000958] -A-----N---- | | | \--* ADD byref $91 N004 ( 1, 1) [000949] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N016 ( 10, 10) [000957] -A-----N---- | | | \--* ADD long $6e4 N014 ( 9, 9) [000955] -A-----N---- | | | +--* LSH long $6e3 N012 ( 8, 8) [001283] -A---------- | | | | +--* COMMA long $6e2 N010 ( 7, 7) [001281] -A------R--- | | | | | +--* ASG long $VN.Void N009 ( 1, 1) [001280] D------N---- | | | | | | +--* LCL_VAR long V71 cse6 d:1 $6e2 N008 ( 7, 7) [000961] ------------ | | | | | | \--* MUL long $6e2 N006 ( 2, 3) [000953] ------------ | | | | | | +--* CAST long <- int $6e1 N005 ( 1, 1) [000950] i----------- | | | | | | | \--* LCL_VAR int V09 loc5 u:2 $3c4 N007 ( 1, 1) [000960] ------------ | | | | | | \--* CNS_INT long 3 $24b N011 ( 1, 1) [001282] ------------ | | | | | \--* LCL_VAR long V71 cse6 u:1 $6e2 N013 ( 1, 1) [000954] -------N---- | | | | \--* CNS_INT long 3 $24b N015 ( 1, 1) [000956] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N023 ( 1, 1) [001256] ------------ | | \--* LCL_VAR byref V66 cse1 u:1 N025 ( 1, 1) [000947] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N028 ( 1, 1) [000213] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 ------------ BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} ***** BB34 STMT00045 (IL 0x18E...0x1A2) N016 ( 18, 20) [000246] -A-XG---R--- * ASG ref N015 ( 1, 1) [000245] D------N---- +--* LCL_VAR ref V17 tmp3 d:1 N014 ( 18, 20) [000973] ---XG------- \--* COMMA ref N003 ( 6, 9) [000966] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000236] ------------ | +--* LCL_VAR int V09 loc5 u:2 $3c4 N002 ( 1, 1) [001327] ------------ | \--* LCL_VAR int V76 cse11 N013 ( 12, 11) [000977] *---G------- \--* IND ref N012 ( 9, 9) [000976] ----G------- \--* ADDR byref Zero Fseq[key] $93 N011 ( 5, 5) [000237] a---G--N---- \--* IND struct N010 ( 4, 4) [000972] -------N---- \--* ADD byref $91 N004 ( 1, 1) [000963] ------------ +--* LCL_VAR ref V04 loc0 u:1 N009 ( 3, 3) [000971] -------N---- \--* ADD long $6e4 N007 ( 2, 2) [000969] -------N---- +--* LSH long $6e3 N005 ( 1, 1) [001284] ------------ | +--* LCL_VAR long V71 cse6 u:1 $6e2 N006 ( 1, 1) [000968] -------N---- | \--* CNS_INT long 3 $24b N008 ( 1, 1) [000970] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB34 STMT00044 (IL 0x18E... ???) N004 ( 3, 3) [000244] -A-X----R--- * ASG long $2e8 N003 ( 1, 1) [000243] D------N---- +--* LCL_VAR long V16 tmp2 d:1 $2e7 N002 ( 3, 2) [000242] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000241] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB34 STMT00158 (IL ???... ???) N015 ( 15, 14) [001163] -A---------- * JTRUE void N014 ( 13, 12) [000263] JA-----N---- \--* EQ int N012 ( 11, 10) [001263] -A---------- +--* COMMA long N010 ( 10, 9) [001261] -A------R--- | +--* ASG long $VN.Void N009 ( 1, 1) [001260] D------N---- | | +--* LCL_VAR long V67 cse2 d:1 N008 ( 10, 9) [000259] n----------- | | \--* IND long N007 ( 8, 7) [000255] -------N---- | | \--* ADD long $6e6 N005 ( 7, 6) [000253] #----------- | | +--* IND long $2ea N004 ( 4, 4) [000252] #----------- | | | \--* IND long $2e9 N003 ( 2, 2) [000251] -------N---- | | | \--* ADD long $306 N001 ( 1, 1) [000249] ------------ | | | +--* LCL_VAR long V16 tmp2 u:1 $2e7 N002 ( 1, 1) [000250] ------------ | | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000254] ------------ | | \--* CNS_INT long 48 $246 N011 ( 1, 1) [001262] ------------ | \--* LCL_VAR long V67 cse2 u:1 N013 ( 1, 1) [000262] ------------ \--* CNS_INT long 0 $243 ------------ BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} ***** BB35 STMT00159 (IL ???... ???) N003 ( 1, 3) [001165] -A------R--- * ASG long N002 ( 1, 1) [001164] D------N---- +--* LCL_VAR long V19 tmp5 d:3 N001 ( 1, 1) [001264] ------------ \--* LCL_VAR long V67 cse2 u:1 ------------ BB36 [???..???), preds={BB34} succs={BB37} ***** BB36 STMT00160 (IL ???... ???) N007 ( 17, 18) [001167] -AC-G---R--- * ASG long $6e7 N006 ( 1, 1) [001166] D------N---- +--* LCL_VAR long V19 tmp5 d:2 $6e7 N005 ( 17, 18) [000261] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $6e7 N003 ( 1, 1) [000248] ------?----- arg0 in rcx +--* LCL_VAR long V16 tmp2 u:1 (last use) $2e7 N004 ( 2, 10) [000260] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $63 ------------ BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} ***** BB37 STMT00176 (IL ???... ???) N005 ( 0, 0) [001211] -A------R--- * ASG long N004 ( 0, 0) [001209] D------N---- +--* LCL_VAR long V19 tmp5 d:1 N003 ( 0, 0) [001210] ------------ \--* PHI long N001 ( 0, 0) [001234] ------------ pred BB35 +--* PHI_ARG long V19 tmp5 u:3 N002 ( 0, 0) [001233] ------------ pred BB36 \--* PHI_ARG long V19 tmp5 u:2 $6e7 ***** BB37 STMT00049 (IL ???... ???) N013 ( 32, 18) [000283] --CXG------- * JTRUE void N012 ( 30, 16) [000282] J-CXG--N---- \--* EQ int $817 N010 ( 28, 14) [000280] --CXG------- +--* CALL ind stub int $1ef N009 ( 1, 1) [000279] ------------ calli tgt | \--* LCL_VAR long V19 tmp5 u:1 (last use) $349 N005 ( 1, 1) [000234] ------------ this in rcx | +--* LCL_VAR ref V05 loc1 u:1 N006 ( 1, 1) [000980] ------------ arg1 in r11 | +--* LCL_VAR long V19 tmp5 u:1 r11 REG r11 $349 N007 ( 1, 1) [000247] ------------ arg2 in rdx | +--* LCL_VAR ref V17 tmp3 u:1 (last use) N008 ( 1, 1) [000258] ------------ arg3 in r8 | \--* LCL_VAR ref V01 arg1 u:1 $101 N011 ( 1, 1) [000281] ------------ \--* CNS_INT int 0 $c0 ------------ BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} ***** BB38 STMT00050 (IL 0x1A4...0x1A6) N005 ( 7, 8) [000287] ------------ * JTRUE void N004 ( 5, 6) [000286] N------N-U-- \--* NE int $1bf N002 ( 3, 4) [000985] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000284] ------------ | \--* LCL_VAR int V03 arg3 u:1 $140 N003 ( 1, 1) [000285] ------------ \--* CNS_INT int 1 $c1 ------------ BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} ***** BB39 STMT00057 (IL 0x1A8...0x1B1) N006 ( 6, 6) [000336] -A-XG------- * ASG ref $VN.Void N004 ( 4, 4) [000335] *--XG--N---- +--* IND ref $102 N003 ( 2, 2) [000987] ----G--N---- | \--* ADD byref $2ae N001 ( 1, 1) [001258] ------------ | +--* LCL_VAR byref V66 cse1 u:1 $91 N002 ( 1, 1) [000986] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N005 ( 1, 1) [000334] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 ------------ BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} ***** BB40 STMT00051 (IL 0x1B8...0x1BA) N005 ( 7, 8) [000291] ------------ * JTRUE void N004 ( 5, 6) [000290] N------N-U-- \--* EQ int $600 N002 ( 3, 4) [001002] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000288] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) $140 N003 ( 1, 1) [000289] ------------ \--* CNS_INT int 2 $c2 ------------ BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} ------------ BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} ***** BB42 STMT00040 (IL 0x1C4...0x1D1) N006 ( 4, 4) [000222] -A-XG---R--- * ASG int N005 ( 1, 1) [000221] D------N---- +--* LCL_VAR int V09 loc5 d:3 N004 ( 4, 4) [000220] *--XG------- \--* IND int N003 ( 2, 2) [001009] ----G--N---- \--* ADD byref $2ad N001 ( 1, 1) [001259] ------------ +--* LCL_VAR byref V66 cse1 u:1 $91 N002 ( 1, 1) [001008] ------------ \--* CNS_INT long 20 field offset Fseq[next] $24c ***** BB42 STMT00041 (IL 0x1D3...0x1D6) N005 ( 3, 3) [000227] -A------R--- * ASG int $81a N004 ( 1, 1) [000226] D------N---- +--* LCL_VAR int V07 loc3 d:4 $81a N003 ( 3, 3) [000225] ------------ \--* ADD int $81a N001 ( 1, 1) [000223] ------------ +--* LCL_VAR int V07 loc3 u:3 (last use) $3c3 N002 ( 1, 1) [000224] ------------ \--* CNS_INT int 1 $c1 ***** BB42 STMT00042 (IL 0x1D7...0x1DB) N004 ( 5, 5) [000232] ------------ * JTRUE void N003 ( 3, 3) [000231] N------N-U-- \--* LT int N001 ( 1, 1) [001328] ------------ +--* LCL_VAR int V76 cse11 N002 ( 1, 1) [000228] ------------ \--* LCL_VAR int V07 loc3 u:4 $81a ------------ BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} ------------ BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} ***** BB44 STMT00166 (IL ???... ???) N005 ( 0, 0) [001181] -A------R--- * ASG int N004 ( 0, 0) [001179] D------N---- +--* LCL_VAR int V07 loc3 d:2 N003 ( 0, 0) [001180] ------------ \--* PHI int N001 ( 0, 0) [001237] ------------ pred BB23 +--* PHI_ARG int V07 loc3 u:5 $3c1 N002 ( 0, 0) [001228] ------------ pred BB32 \--* PHI_ARG int V07 loc3 u:3 $3c3 ***** BB44 STMT00015 (IL 0x1E4...0x1EB) N007 ( 8, 8) [000071] ---XG------- * JTRUE void N006 ( 6, 6) [000070] J--XG--N---- \--* LE int N004 ( 4, 4) [000068] ---XG------- +--* IND int N003 ( 2, 2) [001025] -------N---- | \--* ADD byref $28f N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001024] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N005 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 $c0 ------------ BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} ***** BB45 STMT00035 (IL 0x1ED...0x1F3) N010 ( 15, 12) [000174] -A-XG---R--- * ASG int N009 ( 3, 2) [000173] D------N---- +--* LCL_VAR int V10 loc6 d:3 N008 ( 11, 9) [001308] -A-XG------- \--* COMMA int N006 ( 8, 7) [001306] -A-XG---R--- +--* ASG int $VN.Void N005 ( 3, 2) [001305] D------N---- | +--* LCL_VAR int V74 cse9 d:1 N004 ( 4, 4) [000172] ---XG------- | \--* IND int N003 ( 2, 2) [001027] -------N---- | \--* ADD byref $295 N001 ( 1, 1) [000171] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001026] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N007 ( 3, 2) [001307] ------------ \--* LCL_VAR int V74 cse9 u:1 ***** BB45 STMT00120 (IL 0x1F5... ???) N030 ( 45, 44) [000688] -A-XG---R--- * ASG bool N029 ( 3, 2) [000687] D------N---- +--* LCL_VAR int V49 tmp35 d:1 N028 ( 41, 41) [000184] -A-XG------- \--* GE int N026 ( 36, 39) [000182] -A-XG------- +--* ADD int N024 ( 34, 37) [001050] -A-XG------- | +--* NEG int N023 ( 33, 36) [000181] *A-XG------- | | \--* IND int N022 ( 31, 34) [001029] -A-XG--N---- | | \--* ADD byref $29c N020 ( 30, 33) [001044] -A-XG------- | | +--* COMMA byref N003 ( 3, 3) [001032] -A--G---R--- | | | +--* ASG int N002 ( 1, 1) [001031] D------N---- | | | | +--* LCL_VAR int V62 tmp48 d:1 N001 ( 3, 2) [001309] ------------ | | | | \--* LCL_VAR int V74 cse9 u:1 N019 ( 27, 30) [001043] ---XG------- | | | \--* COMMA byref N006 ( 6, 9) [001036] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N004 ( 1, 1) [001033] ------------ | | | | +--* LCL_VAR int V62 tmp48 u:1 N005 ( 1, 1) [001329] ------------ | | | | \--* LCL_VAR int V76 cse11 N018 ( 21, 21) [001049] ----G------- | | | \--* ADDR byref $88 N017 ( 11, 11) [000179] a---G--N---- | | | \--* IND struct N016 ( 10, 10) [001042] -------N---- | | | \--* ADD byref $88 N007 ( 1, 1) [001030] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N015 ( 9, 9) [001041] -------N---- | | | \--* ADD long N013 ( 8, 8) [001039] -------N---- | | | +--* LSH long N011 ( 7, 7) [001048] ------------ | | | | +--* MUL long N009 ( 2, 3) [001037] ------------ | | | | | +--* CAST long <- int N008 ( 1, 1) [001034] i----------- | | | | | | \--* LCL_VAR int V62 tmp48 u:1 (last use) N010 ( 1, 1) [001047] ------------ | | | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [001038] -------N---- | | | | \--* CNS_INT long 3 $24b N014 ( 1, 1) [001040] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N021 ( 1, 1) [001028] ------------ | | \--* CNS_INT long 20 field offset Fseq[next] $24c N025 ( 1, 1) [000175] ------------ | \--* CNS_INT int -3 $e1 N027 ( 1, 1) [000183] ------------ \--* CNS_INT int -1 $c4 ***** BB45 STMT00123 (IL 0x1F5... ???) N003 ( 5, 4) [000698] -A--G---R--- * ASG ref $105 N002 ( 3, 2) [000697] D------N---- +--* LCL_VAR ref V50 tmp36 d:1 $105 N001 ( 1, 1) [001300] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB45 STMT00121 (IL 0x1F5... ???) N004 ( 7, 6) [000693] ------------ * JTRUE void N003 ( 5, 4) [000692] J------N---- \--* NE int N001 ( 3, 2) [000690] ------------ +--* LCL_VAR int V49 tmp35 u:1 (last use) N002 ( 1, 1) [000691] ------------ \--* CNS_INT int 0 $c0 ------------ BB46 [1F5..1F6), preds={BB45} succs={BB47} ***** BB46 STMT00122 (IL 0x1F5... ???) N006 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N004 ( 4, 12) [001052] #---G------- arg0 in rcx +--* IND ref $114 N003 ( 2, 10) [001051] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" $5e N005 ( 3, 2) [000695] ------------ arg1 in rdx \--* LCL_VAR ref V50 tmp36 u:1 (last use) $105 ------------ BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} ***** BB47 STMT00037 (IL 0x219... ???) N034 ( 42, 45) [000200] -A-XG------- * ASG int $VN.Void N004 ( 4, 4) [000199] D--XG--N---- +--* IND int $732 N003 ( 2, 2) [001056] -------N---- | \--* ADD byref $295 N001 ( 1, 1) [000190] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001055] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N033 ( 37, 40) [000198] -A-XG------- \--* ADD int N031 ( 35, 38) [001079] -A-XG------- +--* NEG int N030 ( 34, 37) [000197] *A-XG------- | \--* IND int N029 ( 32, 35) [001058] -A-XG--N---- | \--* ADD byref $2a3 N027 ( 31, 34) [001073] -A-XG------- | +--* COMMA byref N010 ( 4, 4) [001061] -A-XG---R--- | | +--* ASG int N009 ( 1, 1) [001060] D------N---- | | | +--* LCL_VAR int V63 tmp49 d:1 N008 ( 4, 4) [000194] ---XG------- | | | \--* IND int N007 ( 2, 2) [001075] -------N---- | | | \--* ADD byref $295 N005 ( 1, 1) [000193] ------------ | | | +--* LCL_VAR ref V00 this u:1 $100 N006 ( 1, 1) [001074] ------------ | | | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N026 ( 27, 30) [001072] ---XG------- | | \--* COMMA byref N013 ( 6, 9) [001065] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N011 ( 1, 1) [001062] ------------ | | | +--* LCL_VAR int V63 tmp49 u:1 N012 ( 1, 1) [001330] ------------ | | | \--* LCL_VAR int V76 cse11 N025 ( 21, 21) [001078] ----G------- | | \--* ADDR byref $8a N024 ( 11, 11) [000195] a---G--N---- | | \--* IND struct N023 ( 10, 10) [001071] -------N---- | | \--* ADD byref $8a N014 ( 1, 1) [001059] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N022 ( 9, 9) [001070] -------N---- | | \--* ADD long N020 ( 8, 8) [001068] -------N---- | | +--* LSH long N018 ( 7, 7) [001077] ------------ | | | +--* MUL long N016 ( 2, 3) [001066] ------------ | | | | +--* CAST long <- int N015 ( 1, 1) [001063] i----------- | | | | | \--* LCL_VAR int V63 tmp49 u:1 (last use) N017 ( 1, 1) [001076] ------------ | | | | \--* CNS_INT long 3 $24b N019 ( 1, 1) [001067] -------N---- | | | \--* CNS_INT long 3 $24b N021 ( 1, 1) [001069] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N028 ( 1, 1) [001057] ------------ | \--* CNS_INT long 20 field offset Fseq[next] $24c N032 ( 1, 1) [000191] ------------ \--* CNS_INT int -3 $e1 ***** BB47 STMT00038 (IL 0x233...0x23C) N011 ( 11, 11) [000207] -A-XG---R--- * ASG int $VN.Void N010 ( 4, 4) [000206] D--XG--N---- +--* IND int $73a N009 ( 2, 2) [001081] -------N---- | \--* ADD byref $28f N007 ( 1, 1) [000201] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001080] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N006 ( 6, 6) [000205] ---XG------- \--* ADD int N004 ( 4, 4) [000203] ---XG------- +--* IND int N003 ( 2, 2) [001083] -------N---- | \--* ADD byref $28f N001 ( 1, 1) [000202] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001082] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N005 ( 1, 1) [000204] ------------ \--* CNS_INT int -1 $c4 ------------ BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} ***** BB48 STMT00016 (IL 0x243...0x249) N010 ( 15, 12) [000075] -A-XG---R--- * ASG int N009 ( 3, 2) [000074] D------N---- +--* LCL_VAR int V13 loc9 d:1 N008 ( 11, 9) [001313] -A-XG------- \--* COMMA int N006 ( 8, 7) [001311] -A-XG---R--- +--* ASG int $VN.Void N005 ( 3, 2) [001310] D------N---- | +--* LCL_VAR int V75 cse10 d:1 N004 ( 4, 4) [000073] ---XG------- | \--* IND int N003 ( 2, 2) [001085] -------N---- | \--* ADD byref $290 N001 ( 1, 1) [000072] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001084] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] $244 N007 ( 3, 2) [001312] ------------ \--* LCL_VAR int V75 cse10 u:1 ***** BB48 STMT00017 (IL 0x24B...0x250) N004 ( 7, 6) [000080] ------------ * JTRUE void N003 ( 5, 4) [000079] N------N-U-- \--* NE int N001 ( 1, 1) [001331] ------------ +--* LCL_VAR int V76 cse11 N002 ( 3, 2) [000076] ------------ \--* LCL_VAR int V13 loc9 u:1 ------------ BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00125 (IL 0x252... ???) N011 ( 43, 24) [000705] -ACXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void N006 ( 21, 11) [001090] -ACXG---R-L- arg1 SETUP +--* ASG int $1d7 N005 ( 3, 2) [001089] D------N---- | +--* LCL_VAR int V64 tmp50 d:1 $1d7 N004 ( 17, 8) [000702] --CXG------- | \--* CALL int System.Collections.HashHelpers.ExpandPrime $1d7 N003 ( 3, 2) [001314] ------------ arg0 in rcx | \--* LCL_VAR int V75 cse10 u:1 N008 ( 3, 2) [001091] ------------ arg1 in rdx +--* LCL_VAR int V64 tmp50 u:1 (last use) $1d7 N009 ( 1, 1) [000163] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N010 ( 1, 1) [000704] ------------ arg2 in r8 \--* CNS_INT int 0 $c0 ***** BB49 STMT00126 (IL 0x258... ???) N006 ( 8, 7) [000711] -A-XG---R--- * ASG ref N005 ( 3, 2) [000710] D------N---- +--* LCL_VAR ref V52 tmp38 d:1 N004 ( 4, 4) [000709] ---XG------- \--* IND ref N003 ( 2, 2) [001095] -------N---- \--* ADD byref $280 N001 ( 1, 1) [000165] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001094] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] $240 ***** BB49 STMT00133 (IL 0x258... ???) N008 ( 12, 9) [000760] -A-X----R--- * ASG int N007 ( 1, 1) [000759] D------N---- +--* LCL_VAR int V53 tmp39 d:1 N006 ( 12, 9) [001288] -A-X-------- \--* COMMA int N004 ( 9, 7) [001286] -A-X----R--- +--* ASG int $VN.Void N003 ( 3, 2) [001285] D------N---- | +--* LCL_VAR int V72 cse7 d:1 N002 ( 5, 4) [000714] ---X-------- | \--* ARR_LENGTH int N001 ( 3, 2) [000713] ------------ | \--* LCL_VAR ref V52 tmp38 u:1 N005 ( 3, 2) [001287] ------------ \--* LCL_VAR int V72 cse7 u:1 ***** BB49 STMT00134 (IL 0x258... ???) N006 ( 8, 7) [000762] -A-XG---R--- * ASG long N005 ( 3, 2) [000761] D------N---- +--* LCL_VAR long V54 tmp40 d:1 N004 ( 4, 4) [000716] ---XG------- \--* IND long N003 ( 2, 2) [001097] -------N---- \--* ADD byref $283 N001 ( 1, 1) [000715] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001096] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 ***** BB49 STMT00136 (IL 0x258... ???) N005 ( 10, 9) [000773] -A------R--- * ASG bool N004 ( 3, 2) [000772] D------N---- +--* LCL_VAR int V56 tmp42 d:1 N003 ( 6, 6) [000730] N--------U-- \--* LE int N001 ( 1, 1) [000728] ------------ +--* LCL_VAR int V53 tmp39 u:1 N002 ( 1, 4) [000729] ------------ \--* CNS_INT int 0x7FFFFFFF $ce ***** BB49 STMT00139 (IL 0x258... ???) N003 ( 5, 4) [000783] -A--G---R--- * ASG ref $105 N002 ( 3, 2) [000782] D------N---- +--* LCL_VAR ref V57 tmp43 d:1 $105 N001 ( 1, 1) [001301] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB49 STMT00140 (IL 0x258... ???) N003 ( 5, 4) [000785] -A--G---R--- * ASG ref $105 N002 ( 3, 2) [000784] D------N---- +--* LCL_VAR ref V58 tmp44 d:1 $105 N001 ( 1, 1) [001302] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB49 STMT00137 (IL 0x258... ???) N004 ( 7, 6) [000778] ------------ * JTRUE void N003 ( 5, 4) [000777] J------N---- \--* NE int N001 ( 3, 2) [000775] ------------ +--* LCL_VAR int V56 tmp42 u:1 (last use) N002 ( 1, 1) [000776] ------------ \--* CNS_INT int 0 $c0 ------------ BB50 [258..259), preds={BB49} succs={BB51} ***** BB50 STMT00138 (IL 0x258... ???) N005 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 3, 2) [000779] ------------ arg0 in rcx +--* LCL_VAR ref V58 tmp44 u:1 (last use) $105 N004 ( 3, 2) [000780] ------------ arg1 in rdx \--* LCL_VAR ref V58 tmp44 u:1 (last use) $105 ------------ BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00131 (IL 0x258... ???) N016 ( 26, 25) [000750] -A------R--- * ASG int N015 ( 3, 2) [000749] D------N---- +--* LCL_VAR int V55 tmp41 d:1 N014 ( 22, 22) [000748] ------------ \--* CAST int <- uint <- long N013 ( 21, 20) [000747] ------------ \--* RSZ long N011 ( 19, 18) [000745] ------------ +--* MUL long N008 ( 13, 12) [000742] ------------ | +--* ADD long N006 ( 11, 10) [000739] ------------ | | +--* RSZ long N004 ( 9, 8) [000737] ------------ | | | +--* MUL long N001 ( 3, 2) [000735] ------------ | | | | +--* LCL_VAR long V54 tmp40 u:1 (last use) N003 ( 2, 3) [000736] ---------U-- | | | | \--* CAST long <- ulong <- uint $310 N002 ( 1, 1) [000166] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 $3c0 N005 ( 1, 1) [000738] ------------ | | | \--* CNS_INT int 32 $d2 N007 ( 1, 1) [000741] ------------ | | \--* CNS_INT long 1 $247 N010 ( 2, 3) [000744] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000743] ------------ | \--* LCL_VAR int V53 tmp39 u:1 N012 ( 1, 1) [000746] ------------ \--* CNS_INT int 32 $d2 ***** BB51 STMT00142 (IL 0x258... ???) N007 ( 33, 11) [000796] -A-X----R--- * ASG bool N006 ( 3, 2) [000795] D------N---- +--* LCL_VAR int V59 tmp45 d:1 N005 ( 29, 8) [000755] ---X-------- \--* EQ int N003 ( 22, 5) [000754] ---X-------- +--* UMOD int N001 ( 1, 1) [000752] ------------ | +--* LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000753] ------------ | \--* LCL_VAR int V53 tmp39 u:1 (last use) N004 ( 3, 2) [000751] ------------ \--* LCL_VAR int V55 tmp41 u:1 ***** BB51 STMT00145 (IL 0x258... ???) N003 ( 5, 4) [000806] -A--G---R--- * ASG ref $105 N002 ( 3, 2) [000805] D------N---- +--* LCL_VAR ref V60 tmp46 d:1 $105 N001 ( 1, 1) [001303] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB51 STMT00146 (IL 0x258... ???) N003 ( 5, 4) [000808] -A--G---R--- * ASG ref $105 N002 ( 3, 2) [000807] D------N---- +--* LCL_VAR ref V61 tmp47 d:1 $105 N001 ( 1, 1) [001304] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB51 STMT00143 (IL 0x258... ???) N004 ( 7, 6) [000801] ------------ * JTRUE void N003 ( 5, 4) [000800] J------N---- \--* NE int N001 ( 3, 2) [000798] ------------ +--* LCL_VAR int V59 tmp45 u:1 (last use) N002 ( 1, 1) [000799] ------------ \--* CNS_INT int 0 $c0 ------------ BB52 [258..259), preds={BB51} succs={BB53} ***** BB52 STMT00144 (IL 0x258... ???) N005 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 3, 2) [000802] ------------ arg0 in rcx +--* LCL_VAR ref V61 tmp47 u:1 (last use) $105 N004 ( 3, 2) [000803] ------------ arg1 in rdx \--* LCL_VAR ref V61 tmp47 u:1 (last use) $105 ------------ BB53 [258..259), preds={BB51,BB52} succs={BB54} ***** BB53 STMT00128 (IL 0x258... ???) N016 ( 33, 31) [000722] -A-XG---R--- * ASG byref N015 ( 3, 2) [000721] D------N---- +--* LCL_VAR byref V51 tmp37 d:1 $87 N014 ( 29, 28) [001112] ---XG------- \--* COMMA byref N003 ( 10, 11) [001105] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 3, 2) [000758] ------------ | +--* LCL_VAR int V55 tmp41 u:1 N002 ( 3, 2) [001289] ------------ | \--* LCL_VAR int V72 cse7 u:1 N013 ( 19, 17) [001113] ----G------- \--* ADDR byref $87 N012 ( 10, 9) [000719] a---G--N---- \--* IND int N011 ( 9, 8) [001111] -------N---- \--* ADD byref $87 N004 ( 3, 2) [001102] ------------ +--* LCL_VAR ref V52 tmp38 u:1 (last use) N010 ( 6, 6) [001110] -------N---- \--* ADD long N008 ( 5, 5) [001108] -------N---- +--* LSH long N006 ( 4, 4) [001106] ------------ | +--* CAST long <- int N005 ( 3, 2) [001103] i----------- | | \--* LCL_VAR int V55 tmp41 u:1 (last use) N007 ( 1, 1) [001107] -------N---- | \--* CNS_INT long 2 $248 N009 ( 1, 1) [001109] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB53 STMT00034 (IL ???... ???) N003 ( 7, 5) [000170] -A------R--- * ASG byref $87 N002 ( 3, 2) [000169] D------N---- +--* LCL_VAR byref V08 loc4 d:4 $87 N001 ( 3, 2) [000723] ------------ \--* LCL_VAR byref V51 tmp37 u:1 (last use) $87 ------------ BB54 [261..276), preds={BB48,BB53} succs={BB55} ***** BB54 STMT00170 (IL ???... ???) N005 ( 0, 0) [001193] -A------R--- * ASG byref N004 ( 0, 0) [001191] D------N---- +--* LCL_VAR byref V08 loc4 d:3 N003 ( 0, 0) [001192] ------------ \--* PHI byref N001 ( 0, 0) [001224] ------------ pred BB53 +--* PHI_ARG byref V08 loc4 u:4 $87 N002 ( 0, 0) [001220] ------------ pred BB48 \--* PHI_ARG byref V08 loc4 u:1 $81 ***** BB54 STMT00018 (IL 0x261...0x263) N003 ( 7, 5) [000083] -A------R--- * ASG int N002 ( 3, 2) [000082] D------N---- +--* LCL_VAR int V10 loc6 d:2 N001 ( 3, 2) [000081] ------------ \--* LCL_VAR int V13 loc9 u:1 ***** BB54 STMT00019 (IL 0x265...0x26A) N008 ( 10, 9) [000089] -A-XG---R--- * ASG int $VN.Void N007 ( 4, 4) [000088] D--XG--N---- +--* IND int $708 N006 ( 2, 2) [001115] -------N---- | \--* ADD byref $290 N004 ( 1, 1) [000084] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N005 ( 1, 1) [001114] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] $244 N003 ( 5, 4) [000087] ------------ \--* ADD int N001 ( 3, 2) [000085] ------------ +--* LCL_VAR int V10 loc6 u:2 (last use) N002 ( 1, 1) [000086] ------------ \--* CNS_INT int 1 $c1 ***** BB54 STMT00020 (IL 0x26F...0x275) N006 ( 4, 4) [000093] -A-XG---R--- * ASG ref N005 ( 1, 1) [000092] D------N---- +--* LCL_VAR ref V04 loc0 d:3 N004 ( 4, 4) [000091] ---XG------- \--* IND ref N003 ( 2, 2) [001117] -------N---- \--* ADD byref $281 N001 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001116] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] $241 ------------ BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} ***** BB55 STMT00171 (IL ???... ???) N005 ( 0, 0) [001196] -A------R--- * ASG byref N004 ( 0, 0) [001194] D------N---- +--* LCL_VAR byref V08 loc4 d:2 N003 ( 0, 0) [001195] ------------ \--* PHI byref N001 ( 0, 0) [001225] ------------ pred BB47 +--* PHI_ARG byref V08 loc4 u:1 $81 N002 ( 0, 0) [001221] ------------ pred BB54 \--* PHI_ARG byref V08 loc4 u:3 $780 ***** BB55 STMT00169 (IL ???... ???) N005 ( 0, 0) [001190] -A------R--- * ASG ref N004 ( 0, 0) [001188] D------N---- +--* LCL_VAR ref V04 loc0 d:2 N003 ( 0, 0) [001189] ------------ \--* PHI ref N001 ( 0, 0) [001226] ------------ pred BB47 +--* PHI_ARG ref V04 loc0 u:1 N002 ( 0, 0) [001222] ------------ pred BB54 \--* PHI_ARG ref V04 loc0 u:3 ***** BB55 STMT00168 (IL ???... ???) N005 ( 0, 0) [001187] -A------R--- * ASG int N004 ( 0, 0) [001185] D------N---- +--* LCL_VAR int V10 loc6 d:1 N003 ( 0, 0) [001186] ------------ \--* PHI int N001 ( 0, 0) [001227] ------------ pred BB47 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [001223] ------------ pred BB54 \--* PHI_ARG int V10 loc6 u:2 ***** BB55 STMT00021 (IL 0x276...0x27E) N019 ( 39, 38) [000099] -A-XG---R--- * ASG byref $2a6 N018 ( 3, 2) [000098] D------N---- +--* LCL_VAR byref V11 loc7 d:1 $8c N017 ( 35, 35) [001128] ---XG------- \--* COMMA byref $2a6 N004 ( 10, 12) [001121] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $7cd N001 ( 3, 2) [000095] ------------ | +--* LCL_VAR int V10 loc6 u:1 $3cc N003 ( 3, 3) [001120] ---X-------- | \--* ARR_LENGTH int $73d N002 ( 1, 1) [000094] ------------ | \--* LCL_VAR ref V04 loc0 u:2 $684 N016 ( 25, 23) [001131] ----G------- \--* ADDR byref $8c N015 ( 13, 12) [000096] a---G--N---- \--* IND struct N014 ( 12, 11) [001127] -------N---- \--* ADD byref $8c N005 ( 1, 1) [001118] ------------ +--* LCL_VAR ref V04 loc0 u:2 $684 N013 ( 11, 10) [001126] -------N---- \--* ADD long $6df N011 ( 10, 9) [001124] -------N---- +--* LSH long $6de N009 ( 9, 8) [001130] ------------ | +--* MUL long $6dd N007 ( 4, 4) [001122] ------------ | | +--* CAST long <- int $6dc N006 ( 3, 2) [001119] i----------- | | | \--* LCL_VAR int V10 loc6 u:1 $3cc N008 ( 1, 1) [001129] ------------ | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [001123] -------N---- | \--* CNS_INT long 3 $24b N012 ( 1, 1) [001125] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB55 STMT00022 (IL 0x280...0x283) N006 ( 8, 7) [000103] -A-XG------- * ASG int $VN.Void N004 ( 6, 5) [000102] *--XG--N---- +--* IND int $3c0 N003 ( 4, 3) [001133] -------N---- | \--* ADD byref $8d N001 ( 3, 2) [000100] ------------ | +--* LCL_VAR byref V11 loc7 u:1 $8c N002 ( 1, 1) [001132] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N005 ( 1, 1) [000101] ------------ \--* LCL_VAR int V06 loc2 u:1 (last use) $3c0 ***** BB55 STMT00023 (IL 0x288...0x28F) N009 ( 15, 12) [000110] -A-XG---R--- * ASG int $VN.Void N008 ( 6, 5) [000109] *--XG--N---- +--* IND int N007 ( 4, 3) [001135] -------N---- | \--* ADD byref $8e N005 ( 3, 2) [000104] ------------ | +--* LCL_VAR byref V11 loc7 u:1 $8c N006 ( 1, 1) [001134] ------------ | \--* CNS_INT long 20 field offset Fseq[next] $24c N004 ( 8, 6) [000108] ---XG------- \--* ADD int N002 ( 6, 4) [000106] *--XG------- +--* IND int N001 ( 3, 2) [000105] ------------ | \--* LCL_VAR byref V08 loc4 u:2 $781 N003 ( 1, 1) [000107] ------------ \--* CNS_INT int -1 $c4 ***** BB55 STMT00024 (IL 0x294...0x297) N004 ( 8, 6) [000114] -A-XG------- * ASG ref $VN.Void N002 ( 6, 4) [000113] *--XG--N---- +--* IND ref $101 N001 ( 3, 2) [000111] ------------ | \--* LCL_VAR byref V11 loc7 u:1 Zero Fseq[key] $8f N003 ( 1, 1) [000112] ------------ \--* LCL_VAR ref V01 arg1 u:1 (last use) $101 ***** BB55 STMT00025 (IL 0x29C...0x29F) N006 ( 8, 7) [000118] -A-XG------- * ASG ref $VN.Void N004 ( 6, 5) [000117] *--XG--N---- +--* IND ref $102 N003 ( 4, 3) [001137] -------N---- | \--* ADD byref $90 N001 ( 3, 2) [000115] ------------ | +--* LCL_VAR byref V11 loc7 u:1 (last use) $8c N002 ( 1, 1) [001136] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N005 ( 1, 1) [000116] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 ***** BB55 STMT00026 (IL 0x2A4...0x2AA) N006 ( 12, 9) [000124] -A-XG---R--- * ASG int $VN.Void N005 ( 6, 4) [000123] *--X---N---- +--* IND int $804 N004 ( 3, 2) [000119] ------------ | \--* LCL_VAR byref V08 loc4 u:2 (last use) $781 N003 ( 5, 4) [000122] ------------ \--* ADD int $804 N001 ( 3, 2) [000120] ------------ +--* LCL_VAR int V10 loc6 u:1 (last use) $3cc N002 ( 1, 1) [000121] ------------ \--* CNS_INT int 1 $c1 ***** BB55 STMT00027 (IL 0x2AB...0x2B4) N011 ( 11, 11) [000131] -A-XG---R--- * ASG int $VN.Void N010 ( 4, 4) [000130] D--XG--N---- +--* IND int $80a N009 ( 2, 2) [001139] -------N---- | \--* ADD byref $2a7 N007 ( 1, 1) [000125] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001138] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] $24e N006 ( 6, 6) [000129] ---XG------- \--* ADD int N004 ( 4, 4) [000127] ---XG------- +--* IND int N003 ( 2, 2) [001141] -------N---- | \--* ADD byref $2a7 N001 ( 1, 1) [000126] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001140] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] $24e N005 ( 1, 1) [000128] ------------ \--* CNS_INT int 1 $c1 ***** BB55 STMT00028 (IL 0x2CA...0x2CD) N004 ( 5, 5) [000148] ------------ * JTRUE void N003 ( 3, 3) [000147] N------N-U-- \--* LE int $80d N001 ( 1, 1) [000145] ------------ +--* LCL_VAR int V07 loc3 u:2 (last use) $3c5 N002 ( 1, 1) [000146] ------------ \--* CNS_INT int 100 $e3 ------------ BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} ***** BB56 STMT00030 (IL 0x2CF...0x2D5) N008 ( 21, 22) [000156] --C-G------- * JTRUE void N007 ( 19, 20) [000155] J-C-G--N---- \--* EQ int N005 ( 17, 18) [000153] --C-G------- +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS N003 ( 1, 1) [000151] ------------ arg1 in rdx | +--* LCL_VAR ref V05 loc1 u:1 (last use) N004 ( 2, 10) [000152] H------N---- arg0 in rcx | \--* CNS_INT(h) long 0xd1ffab1e class $62 N006 ( 1, 1) [000154] ------------ \--* CNS_INT ref null $VN.Null ------------ BB57 [2D7..2E3), preds={BB56} succs={BB58} ***** BB57 STMT00031 (IL 0x2D7...0x2DC) N008 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void N005 ( 3, 3) [000159] ---X-------- arg1 in rdx +--* ARR_LENGTH int $73d N004 ( 1, 1) [000158] ------------ | \--* LCL_VAR ref V04 loc0 u:2 (last use) $684 N006 ( 1, 1) [000157] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N007 ( 1, 1) [000160] ------------ arg2 in r8 \--* CNS_INT int 1 $c1 ------------ BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} ***** BB58 STMT00147 (IL ???... ???) N002 ( 2, 2) [000810] ------------ * RETURN int $1f4 N001 ( 1, 1) [000482] ------------ \--* CNS_INT int 1 $c1 ------------ BB59 [008..00E) (throw), preds={BB01} succs={} ***** BB59 STMT00086 (IL 0x008...0x009) N003 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException $VN.Void N002 ( 1, 1) [000532] ------------ arg0 in rcx \--* CNS_INT int 4 $c5 ------------ BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} ***** BB60 STMT00073 (IL 0x14F...0x150) N004 ( 7, 5) [000444] -A-X----R--- * ASG long $2e8 N003 ( 3, 2) [000443] D------N---- +--* LCL_VAR long V26 tmp12 d:1 $2e7 N002 ( 3, 2) [000442] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000441] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB60 STMT00155 (IL ???... ???) N011 ( 16, 14) [001158] ------------ * JTRUE void N010 ( 14, 12) [000460] J------N---- \--* EQ int N008 ( 12, 10) [000456] n----------- +--* IND long N007 ( 10, 8) [000452] -------N---- | \--* ADD long $331 N005 ( 9, 7) [000450] #----------- | +--* IND long $2ea N004 ( 6, 5) [000449] #----------- | | \--* IND long $2e9 N003 ( 4, 3) [000448] -------N---- | | \--* ADD long $306 N001 ( 3, 2) [000446] ------------ | | +--* LCL_VAR long V26 tmp12 u:1 $2e7 N002 ( 1, 1) [000447] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000451] ------------ | \--* CNS_INT long 56 $244 N009 ( 1, 1) [000459] ------------ \--* CNS_INT long 0 $243 ------------ BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} ***** BB61 STMT00156 (IL ???... ???) N010 ( 16, 13) [001160] -A------R--- * ASG long N009 ( 3, 2) [001159] D------N---- +--* LCL_VAR long V28 tmp14 d:3 N008 ( 12, 10) [000461] n-----?----- \--* IND long N007 ( 10, 8) [000462] ------?N---- \--* ADD long $331 N005 ( 9, 7) [000463] #-----?----- +--* IND long $2ea N004 ( 6, 5) [000464] #-----?----- | \--* IND long $2e9 N003 ( 4, 3) [000465] ------?N---- | \--* ADD long $306 N001 ( 3, 2) [000466] ------?----- | +--* LCL_VAR long V26 tmp12 u:1 (last use) $2e7 N002 ( 1, 1) [000467] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000468] ------?----- \--* CNS_INT long 56 $244 ------------ BB62 [???..???), preds={BB60} succs={BB63} ***** BB62 STMT00157 (IL ???... ???) N007 ( 23, 22) [001162] -AC-G---R--- * ASG long $332 N006 ( 3, 2) [001161] D------N---- +--* LCL_VAR long V28 tmp14 d:2 $332 N005 ( 19, 19) [000458] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 N003 ( 3, 2) [000445] ------?----- arg0 in rcx +--* LCL_VAR long V26 tmp12 u:1 (last use) $2e7 N004 ( 2, 10) [000457] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $52 ------------ BB63 [???..157) (throw), preds={BB61,BB62} succs={} ***** BB63 STMT00167 (IL ???... ???) N005 ( 0, 0) [001184] -A------R--- * ASG long N004 ( 0, 0) [001182] D------N---- +--* LCL_VAR long V28 tmp14 d:1 N003 ( 0, 0) [001183] ------------ \--* PHI long N001 ( 0, 0) [001241] ------------ pred BB61 +--* PHI_ARG long V28 tmp14 u:3 N002 ( 0, 0) [001240] ------------ pred BB62 \--* PHI_ARG long V28 tmp14 u:2 $332 ***** BB63 STMT00076 (IL ???... ???) N005 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void N003 ( 3, 2) [000473] ------------ arg0 in rcx +--* LCL_VAR long V28 tmp14 u:1 (last use) $347 N004 ( 1, 1) [000455] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) $101 ------------ BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} ***** BB64 STMT00053 (IL 0x1BC...0x1BD) N004 ( 7, 5) [000299] -A-X----R--- * ASG long $2e8 N003 ( 3, 2) [000298] D------N---- +--* LCL_VAR long V21 tmp7 d:1 $2e7 N002 ( 3, 2) [000297] #--X-------- \--* IND long $2e8 N001 ( 1, 1) [000296] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB64 STMT00161 (IL ???... ???) N011 ( 16, 14) [001168] ------------ * JTRUE void N010 ( 14, 12) [000315] J------N---- \--* EQ int N008 ( 12, 10) [000311] n----------- +--* IND long N007 ( 10, 8) [000307] -------N---- | \--* ADD long $331 N005 ( 9, 7) [000305] #----------- | +--* IND long $2ea N004 ( 6, 5) [000304] #----------- | | \--* IND long $2e9 N003 ( 4, 3) [000303] -------N---- | | \--* ADD long $306 N001 ( 3, 2) [000301] ------------ | | +--* LCL_VAR long V21 tmp7 u:1 $2e7 N002 ( 1, 1) [000302] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000306] ------------ | \--* CNS_INT long 56 $244 N009 ( 1, 1) [000314] ------------ \--* CNS_INT long 0 $243 ------------ BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} ***** BB65 STMT00162 (IL ???... ???) N010 ( 16, 13) [001170] -A------R--- * ASG long N009 ( 3, 2) [001169] D------N---- +--* LCL_VAR long V23 tmp9 d:3 N008 ( 12, 10) [000316] n-----?----- \--* IND long N007 ( 10, 8) [000317] ------?N---- \--* ADD long $331 N005 ( 9, 7) [000318] #-----?----- +--* IND long $2ea N004 ( 6, 5) [000319] #-----?----- | \--* IND long $2e9 N003 ( 4, 3) [000320] ------?N---- | \--* ADD long $306 N001 ( 3, 2) [000321] ------?----- | +--* LCL_VAR long V21 tmp7 u:1 (last use) $2e7 N002 ( 1, 1) [000322] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000323] ------?----- \--* CNS_INT long 56 $244 ------------ BB66 [???..???), preds={BB64} succs={BB67} ***** BB66 STMT00163 (IL ???... ???) N007 ( 23, 22) [001172] -AC-G---R--- * ASG long $332 N006 ( 3, 2) [001171] D------N---- +--* LCL_VAR long V23 tmp9 d:2 $332 N005 ( 19, 19) [000313] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 N003 ( 3, 2) [000300] ------?----- arg0 in rcx +--* LCL_VAR long V21 tmp7 u:1 (last use) $2e7 N004 ( 2, 10) [000312] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $52 ------------ BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} ***** BB67 STMT00173 (IL ???... ???) N005 ( 0, 0) [001202] -A------R--- * ASG long N004 ( 0, 0) [001200] D------N---- +--* LCL_VAR long V23 tmp9 d:1 N003 ( 0, 0) [001201] ------------ \--* PHI long N001 ( 0, 0) [001232] ------------ pred BB65 +--* PHI_ARG long V23 tmp9 u:3 N002 ( 0, 0) [001231] ------------ pred BB66 \--* PHI_ARG long V23 tmp9 u:2 $332 ***** BB67 STMT00056 (IL ???... ???) N005 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void N003 ( 3, 2) [000328] ------------ arg0 in rcx +--* LCL_VAR long V23 tmp9 u:1 (last use) $34b N004 ( 1, 1) [000310] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) $101 ------------ BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} ***** BB68 STMT00043 (IL 0x1DD...0x1E2) N001 ( 14, 5) [000233] --CXG------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported $VN.Void ------------------------------------------------------------------------------------------------------------------- GenTreeNode creates assertion: N004 ( 5, 5) [000003] ------------ * JTRUE void In BB01 New Global Constant Assertion: (257, 0) ($101,$0) V01.01 == null index=#01, mask=00000000000000000000000000000001 GenTreeNode creates assertion: N004 ( 5, 5) [000003] ------------ * JTRUE void In BB01 New Global Constant Assertion: (257, 0) ($101,$0) V01.01 != null index=#02, mask=00000000000000000000000000000002 GenTreeNode creates assertion: N004 ( 4, 4) [000005] ---XG------- * IND ref In BB02 New Global Constant Assertion: (256, 0) ($100,$0) V00.01 != null index=#03, mask=00000000000000000000000000000004 GenTreeNode creates assertion: N004 ( 5, 5) [000549] ------------ * JTRUE void In BB04 New Global Constant Assertion: (389, 192) ($185,$c0) V33.01 != 0 index=#04, mask=00000000000000000000000000000008 GenTreeNode creates assertion: N004 ( 5, 5) [000549] ------------ * JTRUE void In BB04 New Global Constant Assertion: (389, 192) ($185,$c0) V33.01 == 0 index=#05, mask=00000000000000000000000000000010 GenTreeNode creates assertion: N004 ( 5, 5) [000571] ------------ * JTRUE void In BB06 New Global Constant Assertion: (395, 192) ($18b,$c0) V36.01 != 0 index=#06, mask=00000000000000000000000000000020 GenTreeNode creates assertion: N004 ( 5, 5) [000571] ------------ * JTRUE void In BB06 New Global Constant Assertion: (395, 192) ($18b,$c0) V36.01 == 0 index=#07, mask=00000000000000000000000000000040 GenTreeNode creates assertion: N004 ( 5, 5) [000032] ------------ * JTRUE void In BB08 New Global Constant Assertion: (528, 0) ($210,$0) V05.01 == null index=#08, mask=00000000000000000000000000000080 GenTreeNode creates assertion: N004 ( 5, 5) [000032] ------------ * JTRUE void In BB08 New Global Constant Assertion: (528, 0) ($210,$0) V05.01 != null index=#09, mask=00000000000000000000000000000100 GenTreeNode creates assertion: N008 ( 27, 12) [000522] --CXG------- * CALL ind stub int $1c7 In BB12 New Global Constant Assertion: (528, 0) ($210,$0) V05.01 != null index=#10, mask=00000000000000000000000000000200 GenTreeNode creates assertion: N004 ( 3, 2) [000837] #--X-------- * IND long $2e4 In BB13 New Global Constant Assertion: (257, 0) ($101,$0) V01.01 != null index=#11, mask=00000000000000000000000000000400 GenTreeNode creates assertion: N002 ( 3, 3) [000583] ---X-------- * ARR_LENGTH int In BB14 New Global Constant Assertion: (535, 0) ($217,$0) V39.01 != null index=#12, mask=00000000000000000000000000000800 GenTreeNode creates assertion: N004 ( 5, 5) [000647] ------------ * JTRUE void In BB14 New Global Constant Assertion: (405, 192) ($195,$c0) V43.01 != 0 index=#13, mask=00000000000000000000000000001000 GenTreeNode creates assertion: N004 ( 5, 5) [000647] ------------ * JTRUE void In BB14 New Global Constant Assertion: (405, 192) ($195,$c0) V43.01 == 0 index=#14, mask=00000000000000000000000000002000 GenTreeNode creates assertion: N004 ( 5, 5) [000670] ------------ * JTRUE void In BB16 New Global Constant Assertion: (415, 192) ($19f,$c0) V46.01 != 0 index=#15, mask=00000000000000000000000000004000 GenTreeNode creates assertion: N004 ( 5, 5) [000670] ------------ * JTRUE void In BB16 New Global Constant Assertion: (415, 192) ($19f,$c0) V46.01 == 0 index=#16, mask=00000000000000000000000000008000 GenTreeNode creates assertion: N004 ( 8, 11) [000855] ---X-------- * ARR_BOUNDS_CHECK_Rng void In BB18 New Global ArrBnds Assertion: (0, 0) ($0,$0) [idx: {Cast($31b, $d3)};len: {ARR_LENGTH($217)}] in range index=#17, mask=00000000000000000000000000010000 GenTreeNode creates assertion: N002 ( 3, 2) [000053] *--XG------- * IND int In BB18 New Global Constant Assertion: (129, 0) ($81,$0) Value_Number {PtrToArrElem($4e, $2f0, $31e, $0)} is not 0 index=#18, mask=00000000000000000000000000020000 GenTreeNode creates assertion: N002 ( 3, 3) [000389] ---X-------- * ARR_LENGTH int In BB23 New Global Constant Assertion: (522, 0) ($20a,$0) V04.01 != null index=#19, mask=00000000000000000000000000040000 GenTreeNode creates assertion: N009 ( 8, 8) [000391] -A-X-------- * JTRUE void In BB23 New Global ArrBnds Assertion: (436, -1) ($1b4,$ffffffff) [idx: {PhiDef($9, $4, $1b1)};len: {ARR_LENGTH($20a)}] in range index=#20, mask=00000000000000000000000000080000 GenTreeNode creates assertion: N021 ( 3, 2) [000902] #--X-------- * IND long $463 In BB25 New Global Constant Assertion: (547, 0) ($223,$0) V12.01 != null index=#21, mask=00000000000000000000000000100000 GenTreeNode creates assertion: N004 ( 4, 4) [000404] *--XG------- * IND int In BB26 New Global Constant Assertion: (130, 0) ($82,$0) Value_Number {PtrToArrElem($40, $2d3, $326, $0)} is not 0 index=#22, mask=00000000000000000000000000200000 GenTreeNode creates assertion: N002 ( 3, 4) [000909] ------------ * CAST int <- ubyte <- int $1be In BB28 New Global Subrange Assertion: (320, 0) ($140,$0) V03.01 in [0..255] index=#23, mask=00000000000000000000000000400000 GenTreeNode creates assertion: N009 ( 8, 8) [000066] -A-X-------- * JTRUE void In BB32 New Global ArrBnds Assertion: (1548, -1) ($60c,$ffffffff) [idx: {PhiDef($9, $2, $60b)};len: {ARR_LENGTH($20a)}] in range index=#24, mask=00000000000000000000000000800000 GenTreeNode creates assertion: N004 ( 4, 4) [000335] *--XG--N---- * IND ref $102 In BB39 New Global Constant Assertion: (145, 0) ($91,$0) Value_Number {PtrToArrElem($40, $2d3, $6e1, $0)} is not 0 index=#25, mask=00000000000000000000000001000000 GenTreeNode creates assertion: N007 ( 8, 8) [000071] ---XG------- * JTRUE void In BB44 New Global Constant Assertion: (1566, 192) ($61e,$c0) Const_Loop_Bnd {LE($1d2, $c0)} is not {IntCns 0} index=#26, mask=00000000000000000000000002000000 GenTreeNode creates assertion: N007 ( 8, 8) [000071] ---XG------- * JTRUE void In BB44 New Global Constant Assertion: (1566, 192) ($61e,$c0) Const_Loop_Bnd {LE($1d2, $c0)} is {IntCns 0} index=#27, mask=00000000000000000000000004000000 GenTreeNode creates assertion: N006 ( 6, 9) [001036] ---X-------- * ARR_BOUNDS_CHECK_Rng void In BB45 New Global ArrBnds Assertion: (0, 0) ($0,$0) [idx: {1e2};len: {ARR_LENGTH($20a)}] in range index=#28, mask=00000000000000000000000008000000 GenTreeNode creates assertion: N004 ( 7, 6) [000693] ------------ * JTRUE void In BB45 New Global Constant Assertion: (1828, 192) ($724,$c0) Const_Loop_Bnd {GE($721, $c4)} is not {IntCns 0} index=#29, mask=00000000000000000000000010000000 GenTreeNode creates assertion: N004 ( 7, 6) [000693] ------------ * JTRUE void In BB45 New Global Constant Assertion: (1828, 192) ($724,$c0) Const_Loop_Bnd {GE($721, $c4)} is {IntCns 0} index=#30, mask=00000000000000000000000020000000 GenTreeNode creates assertion: N013 ( 6, 9) [001065] ---X-------- * ARR_BOUNDS_CHECK_Rng void In BB47 New Global ArrBnds Assertion: (0, 0) ($0,$0) [idx: {1e6};len: {ARR_LENGTH($20a)}] in range index=#31, mask=00000000000000000000000040000000 GenTreeNode creates assertion: N002 ( 5, 4) [000714] ---X-------- * ARR_LENGTH int In BB49 New Global Constant Assertion: (555, 0) ($22b,$0) V52.01 != null index=#32, mask=00000000000000000000000080000000 GenTreeNode creates assertion: N004 ( 7, 6) [000778] ------------ * JTRUE void In BB49 New Global Constant Assertion: (1590, 192) ($636,$c0) V56.01 != 0 index=#33, mask=00000000000000000000000100000000 GenTreeNode creates assertion: N004 ( 7, 6) [000778] ------------ * JTRUE void In BB49 New Global Constant Assertion: (1590, 192) ($636,$c0) V56.01 == 0 index=#34, mask=00000000000000000000000200000000 GenTreeNode creates assertion: N004 ( 7, 6) [000801] ------------ * JTRUE void In BB51 New Global Constant Assertion: (1792, 192) ($700,$c0) V59.01 != 0 index=#35, mask=00000000000000000000000400000000 GenTreeNode creates assertion: N004 ( 7, 6) [000801] ------------ * JTRUE void In BB51 New Global Constant Assertion: (1792, 192) ($700,$c0) V59.01 == 0 index=#36, mask=00000000000000000000000800000000 GenTreeNode creates assertion: N003 ( 10, 11) [001105] ---X-------- * ARR_BOUNDS_CHECK_Rng void In BB53 New Global ArrBnds Assertion: (0, 0) ($0,$0) [idx: {Cast($6c1, $d3)};len: {ARR_LENGTH($22b)}] in range index=#37, mask=00000000000000000000001000000000 GenTreeNode creates assertion: N003 ( 3, 3) [001120] ---X-------- * ARR_LENGTH int $73d In BB55 New Global Constant Assertion: (1668, 0) ($684,$0) V04.02 != null index=#38, mask=00000000000000000000002000000000 GenTreeNode creates assertion: N004 ( 10, 12) [001121] ---X-------- * ARR_BOUNDS_CHECK_Rng void $7cd In BB55 New Global ArrBnds Assertion: (0, 0) ($0,$0) [idx: {PhiDef($a, $1, $309)};len: {ARR_LENGTH($684)}] in range index=#39, mask=00000000000000000000004000000000 GenTreeNode creates assertion: N004 ( 6, 5) [000102] *--XG--N---- * IND int $3c0 In BB55 New Global Constant Assertion: (140, 0) ($8c,$0) Value_Number {PtrToArrElem($40, $684, $6dc, $0)} is not 0 index=#40, mask=00000000000000000000008000000000 GenTreeNode creates assertion: N002 ( 6, 4) [000106] *--XG------- * IND int In BB55 New Global Constant Assertion: (1921, 0) ($781,$0) Value_Number {PhiDef($8, $2, $2a4)} is not 0 index=#41, mask=00000000000000000000010000000000 GenTreeNode creates assertion: N002 ( 6, 4) [000113] *--XG--N---- * IND ref $101 In BB55 New Global Constant Assertion: (143, 0) ($8f,$0) Value_Number {PtrToArrElem($40, $684, $6dc, $45d)} is not 0 index=#42, mask=00000000000000000000020000000000 GenTreeNode creates assertion: N008 ( 21, 22) [000156] --C-G------- * JTRUE void In BB56 New Global Subtype Assertion: (528, 98) ($210,$62) V05.01 is not MT(D1FFAB1E) index=#43, mask=00000000000000000000040000000000 GenTreeNode creates assertion: N008 ( 21, 22) [000156] --C-G------- * JTRUE void In BB56 New Global Subtype Assertion: (528, 98) ($210,$62) V05.01 is MT(D1FFAB1E) index=#44, mask=00000000000000000000080000000000 BB01 valueGen = 00000000000000000000000000000002 => BB59 valueGen = 00000000000000000000000000000001, BB02 valueGen = 00000000000000000000000000000004 => BB04 valueGen = 00000000000000000000000000000004, BB03 valueGen = 00000000000000000000000000000000 BB04 valueGen = 00000000000000000000000000000014 => BB06 valueGen = 0000000000000000000000000000000C, BB05 valueGen = 00000000000000000000000000000000 BB06 valueGen = 00000000000000000000000000000044 => BB08 valueGen = 00000000000000000000000000000024, BB07 valueGen = 00000000000000000000000000000000 BB08 valueGen = 00000000000000000000000000000104 => BB13 valueGen = 00000000000000000000000000000084, BB09 valueGen = 00000000000000000000000000000004 => BB11 valueGen = 00000000000000000000000000000004, BB10 valueGen = 00000000000000000000000000000000 BB11 valueGen = 00000000000000000000000000000000 BB12 valueGen = 00000000000000000000000000000200 BB13 valueGen = 00000000000000000000000000000400 BB14 valueGen = 00000000000000000000000000002804 => BB16 valueGen = 00000000000000000000000000001804, BB15 valueGen = 00000000000000000000000000000000 BB16 valueGen = 00000000000000000000000000008000 => BB18 valueGen = 00000000000000000000000000004000, BB17 valueGen = 00000000000000000000000000000000 BB18 valueGen = 00000000000000000000000000030880 => BB32 valueGen = 00000000000000000000000000030900, BB19 valueGen = 00000000000000000000000000000004 => BB21 valueGen = 00000000000000000000000000000004, BB20 valueGen = 00000000000000000000000000000000 BB21 valueGen = 00000000000000000000000000000000 BB22 valueGen = 00000000000000000000000000000000 BB23 valueGen = 000000000000000000000000000C0000 => BB44 valueGen = 00000000000000000000000000040000, BB24 valueGen = 00000000000000000000000000080000 => BB26 valueGen = 00000000000000000000000000080000, BB25 valueGen = 00000000000000000000000000180000 => BB28 valueGen = 00000000000000000000000000180000, BB26 valueGen = 00000000000000000000000000200000 => BB68 valueGen = 00000000000000000000000000200000, BB27 valueGen = 00000000000000000000000000000000 BB28 valueGen = 00000000000000000000000000000000 => BB30 valueGen = 00000000000000000000000000000000, BB29 valueGen = 00000000000000000000000000200000 BB30 valueGen = 00000000000000000000000000000000 => BB60 valueGen = 00000000000000000000000000000000, BB31 valueGen = 00000000000000000000000000000000 BB32 valueGen = 00000000000000000000000000840000 => BB44 valueGen = 00000000000000000000000000040000, BB33 valueGen = 00000000000000000000000000800000 => BB42 valueGen = 00000000000000000000000000800000, BB34 valueGen = 00000000000000000000000000800004 => BB36 valueGen = 00000000000000000000000000800004, BB35 valueGen = 00000000000000000000000000000000 BB36 valueGen = 00000000000000000000000000000000 BB37 valueGen = 00000000000000000000000000000200 => BB42 valueGen = 00000000000000000000000000000200, BB38 valueGen = 00000000000000000000000000000000 => BB40 valueGen = 00000000000000000000000000000000, BB39 valueGen = 00000000000000000000000001000000 BB40 valueGen = 00000000000000000000000000000000 => BB64 valueGen = 00000000000000000000000000000000, BB41 valueGen = 00000000000000000000000000000000 BB42 valueGen = 00000000000000000000000001000000 => BB68 valueGen = 00000000000000000000000001000000, BB43 valueGen = 00000000000000000000000000000000 BB44 valueGen = 00000000000000000000000004000004 => BB48 valueGen = 00000000000000000000000002000004, BB45 valueGen = 00000000000000000000000028000004 => BB47 valueGen = 00000000000000000000000018000004, BB46 valueGen = 00000000000000000000000000000000 BB47 valueGen = 00000000000000000000000040000004 BB48 valueGen = 00000000000000000000000000000004 => BB54 valueGen = 00000000000000000000000000000004, BB49 valueGen = 00000000000000000000000280000004 => BB51 valueGen = 00000000000000000000000180000004, BB50 valueGen = 00000000000000000000000000000000 BB51 valueGen = 00000000000000000000000800000000 => BB53 valueGen = 00000000000000000000000400000000, BB52 valueGen = 00000000000000000000000000000000 BB53 valueGen = 00000000000000000000001000000000 BB54 valueGen = 00000000000000000000000000000004 BB55 valueGen = 0000000000000000000003E000000004 => BB58 valueGen = 0000000000000000000003E000000004, BB56 valueGen = 00000000000000000000080000000000 => BB58 valueGen = 00000000000000000000040000000000, BB57 valueGen = 00000000000000000000002000000000 BB58 valueGen = 00000000000000000000000000000000 BB59 valueGen = 00000000000000000000000000000000 BB60 valueGen = 00000000000000000000000000000004 => BB62 valueGen = 00000000000000000000000000000004, BB61 valueGen = 00000000000000000000000000000000 BB62 valueGen = 00000000000000000000000000000000 BB63 valueGen = 00000000000000000000000000000000 BB64 valueGen = 00000000000000000000000000000004 => BB66 valueGen = 00000000000000000000000000000004, BB65 valueGen = 00000000000000000000000000000000 BB66 valueGen = 00000000000000000000000000000000 BB67 valueGen = 00000000000000000000000000000000 BB68 valueGen = 00000000000000000000000000000000 AssertionPropCallback::StartMerge: BB01 in -> 00000000000000000000000000000000 AssertionPropCallback::EndMerge : BB01 in -> 00000000000000000000000000000000 AssertionPropCallback::Changed : BB01 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000000002; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000000001; AssertionPropCallback::StartMerge: BB02 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB02 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB01 out -> 00000000000000000000000000000002 AssertionPropCallback::EndMerge : BB02 in -> 00000000000000000000000000000002 AssertionPropCallback::Changed : BB02 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000000006; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000000006; AssertionPropCallback::StartMerge: BB59 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB59 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB01 out -> 00000000000000000000000000000001 AssertionPropCallback::EndMerge : BB59 in -> 00000000000000000000000000000001 AssertionPropCallback::Changed : BB59 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000000001; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000000001; AssertionPropCallback::StartMerge: BB03 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB03 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB02 out -> 00000000000000000000000000000006 AssertionPropCallback::EndMerge : BB03 in -> 00000000000000000000000000000006 AssertionPropCallback::Changed : BB03 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000000006; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000000006; AssertionPropCallback::StartMerge: BB04 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB04 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB02 out -> 00000000000000000000000000000006 AssertionPropCallback::Merge : BB04 in -> 00000000000000000000000000000006, predBlock BB03 out -> 00000000000000000000000000000006 AssertionPropCallback::EndMerge : BB04 in -> 00000000000000000000000000000006 AssertionPropCallback::Changed : BB04 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000000016; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 0000000000000000000000000000000E; AssertionPropCallback::StartMerge: BB04 in -> 00000000000000000000000000000006 AssertionPropCallback::Merge : BB04 in -> 00000000000000000000000000000006, predBlock BB02 out -> 00000000000000000000000000000006 AssertionPropCallback::Merge : BB04 in -> 00000000000000000000000000000006, predBlock BB03 out -> 00000000000000000000000000000006 AssertionPropCallback::EndMerge : BB04 in -> 00000000000000000000000000000006 AssertionPropCallback::Unchanged : BB04 out -> 00000000000000000000000000000016; jumpDest out -> 0000000000000000000000000000000E AssertionPropCallback::StartMerge: BB05 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB05 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB04 out -> 00000000000000000000000000000016 AssertionPropCallback::EndMerge : BB05 in -> 00000000000000000000000000000016 AssertionPropCallback::Changed : BB05 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000000016; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000000016; AssertionPropCallback::StartMerge: BB06 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB06 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB04 out -> 0000000000000000000000000000000E AssertionPropCallback::Merge : BB06 in -> 0000000000000000000000000000000E, predBlock BB05 out -> 00000000000000000000000000000016 AssertionPropCallback::EndMerge : BB06 in -> 00000000000000000000000000000006 AssertionPropCallback::Changed : BB06 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000000046; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000000026; AssertionPropCallback::StartMerge: BB06 in -> 00000000000000000000000000000006 AssertionPropCallback::Merge : BB06 in -> 00000000000000000000000000000006, predBlock BB04 out -> 0000000000000000000000000000000E AssertionPropCallback::Merge : BB06 in -> 00000000000000000000000000000006, predBlock BB05 out -> 00000000000000000000000000000016 AssertionPropCallback::EndMerge : BB06 in -> 00000000000000000000000000000006 AssertionPropCallback::Unchanged : BB06 out -> 00000000000000000000000000000046; jumpDest out -> 00000000000000000000000000000026 AssertionPropCallback::StartMerge: BB07 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB07 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB06 out -> 00000000000000000000000000000046 AssertionPropCallback::EndMerge : BB07 in -> 00000000000000000000000000000046 AssertionPropCallback::Changed : BB07 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000000046; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000000046; AssertionPropCallback::StartMerge: BB08 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB08 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB06 out -> 00000000000000000000000000000026 AssertionPropCallback::Merge : BB08 in -> 00000000000000000000000000000026, predBlock BB07 out -> 00000000000000000000000000000046 AssertionPropCallback::EndMerge : BB08 in -> 00000000000000000000000000000006 AssertionPropCallback::Changed : BB08 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000000106; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000000086; AssertionPropCallback::StartMerge: BB08 in -> 00000000000000000000000000000006 AssertionPropCallback::Merge : BB08 in -> 00000000000000000000000000000006, predBlock BB06 out -> 00000000000000000000000000000026 AssertionPropCallback::Merge : BB08 in -> 00000000000000000000000000000006, predBlock BB07 out -> 00000000000000000000000000000046 AssertionPropCallback::EndMerge : BB08 in -> 00000000000000000000000000000006 AssertionPropCallback::Unchanged : BB08 out -> 00000000000000000000000000000106; jumpDest out -> 00000000000000000000000000000086 AssertionPropCallback::StartMerge: BB09 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB09 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB08 out -> 00000000000000000000000000000106 AssertionPropCallback::EndMerge : BB09 in -> 00000000000000000000000000000106 AssertionPropCallback::Changed : BB09 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000000106; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000000106; AssertionPropCallback::StartMerge: BB13 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB13 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB08 out -> 00000000000000000000000000000086 AssertionPropCallback::EndMerge : BB13 in -> 00000000000000000000000000000086 AssertionPropCallback::Changed : BB13 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000000486; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000000086; AssertionPropCallback::StartMerge: BB10 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB10 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB09 out -> 00000000000000000000000000000106 AssertionPropCallback::EndMerge : BB10 in -> 00000000000000000000000000000106 AssertionPropCallback::Changed : BB10 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000000106; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000000106; AssertionPropCallback::StartMerge: BB11 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB11 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB09 out -> 00000000000000000000000000000106 AssertionPropCallback::EndMerge : BB11 in -> 00000000000000000000000000000106 AssertionPropCallback::Changed : BB11 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000000106; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000000106; AssertionPropCallback::StartMerge: BB14 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB14 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB12 out -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB14 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB13 out -> 00000000000000000000000000000486 AssertionPropCallback::EndMerge : BB14 in -> 00000000000000000000000000000486 AssertionPropCallback::Changed : BB14 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000002C86; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000001C86; AssertionPropCallback::StartMerge: BB12 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB12 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB10 out -> 00000000000000000000000000000106 AssertionPropCallback::Merge : BB12 in -> 00000000000000000000000000000106, predBlock BB11 out -> 00000000000000000000000000000106 AssertionPropCallback::EndMerge : BB12 in -> 00000000000000000000000000000106 AssertionPropCallback::Changed : BB12 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000000306; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000000106; AssertionPropCallback::StartMerge: BB12 in -> 00000000000000000000000000000106 AssertionPropCallback::Merge : BB12 in -> 00000000000000000000000000000106, predBlock BB10 out -> 00000000000000000000000000000106 AssertionPropCallback::Merge : BB12 in -> 00000000000000000000000000000106, predBlock BB11 out -> 00000000000000000000000000000106 AssertionPropCallback::EndMerge : BB12 in -> 00000000000000000000000000000106 AssertionPropCallback::Unchanged : BB12 out -> 00000000000000000000000000000306; jumpDest out -> 00000000000000000000000000000106 AssertionPropCallback::StartMerge: BB15 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB15 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB14 out -> 00000000000000000000000000002C86 AssertionPropCallback::EndMerge : BB15 in -> 00000000000000000000000000002C86 AssertionPropCallback::Changed : BB15 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000002C86; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000002C86; AssertionPropCallback::StartMerge: BB16 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB16 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB14 out -> 00000000000000000000000000001C86 AssertionPropCallback::Merge : BB16 in -> 00000000000000000000000000001C86, predBlock BB15 out -> 00000000000000000000000000002C86 AssertionPropCallback::EndMerge : BB16 in -> 00000000000000000000000000000C86 AssertionPropCallback::Changed : BB16 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000008C86; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000004C86; AssertionPropCallback::StartMerge: BB14 in -> 00000000000000000000000000000486 AssertionPropCallback::Merge : BB14 in -> 00000000000000000000000000000486, predBlock BB12 out -> 00000000000000000000000000000306 AssertionPropCallback::Merge : BB14 in -> 00000000000000000000000000000006, predBlock BB13 out -> 00000000000000000000000000000486 AssertionPropCallback::EndMerge : BB14 in -> 00000000000000000000000000000006 AssertionPropCallback::Changed : BB14 before out -> 00000000000000000000000000002C86; after out -> 00000000000000000000000000002806; jumpDest before out -> 00000000000000000000000000001C86; jumpDest after out -> 00000000000000000000000000001806; AssertionPropCallback::StartMerge: BB16 in -> 00000000000000000000000000000C86 AssertionPropCallback::Merge : BB16 in -> 00000000000000000000000000000C86, predBlock BB14 out -> 00000000000000000000000000001806 AssertionPropCallback::Merge : BB16 in -> 00000000000000000000000000000806, predBlock BB15 out -> 00000000000000000000000000002C86 AssertionPropCallback::EndMerge : BB16 in -> 00000000000000000000000000000806 AssertionPropCallback::Changed : BB16 before out -> 00000000000000000000000000008C86; after out -> 00000000000000000000000000008806; jumpDest before out -> 00000000000000000000000000004C86; jumpDest after out -> 00000000000000000000000000004806; AssertionPropCallback::StartMerge: BB17 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB17 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB16 out -> 00000000000000000000000000008806 AssertionPropCallback::EndMerge : BB17 in -> 00000000000000000000000000008806 AssertionPropCallback::Changed : BB17 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000008806; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000008806; AssertionPropCallback::StartMerge: BB18 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB18 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB16 out -> 00000000000000000000000000004806 AssertionPropCallback::Merge : BB18 in -> 00000000000000000000000000004806, predBlock BB17 out -> 00000000000000000000000000008806 AssertionPropCallback::EndMerge : BB18 in -> 00000000000000000000000000000806 AssertionPropCallback::Changed : BB18 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000030886; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000030906; AssertionPropCallback::StartMerge: BB15 in -> 00000000000000000000000000002C86 AssertionPropCallback::Merge : BB15 in -> 00000000000000000000000000002C86, predBlock BB14 out -> 00000000000000000000000000002806 AssertionPropCallback::EndMerge : BB15 in -> 00000000000000000000000000002806 AssertionPropCallback::Changed : BB15 before out -> 00000000000000000000000000002C86; after out -> 00000000000000000000000000002806; jumpDest before out -> 00000000000000000000000000002C86; jumpDest after out -> 00000000000000000000000000002806; AssertionPropCallback::StartMerge: BB16 in -> 00000000000000000000000000000806 AssertionPropCallback::Merge : BB16 in -> 00000000000000000000000000000806, predBlock BB14 out -> 00000000000000000000000000001806 AssertionPropCallback::Merge : BB16 in -> 00000000000000000000000000000806, predBlock BB15 out -> 00000000000000000000000000002806 AssertionPropCallback::EndMerge : BB16 in -> 00000000000000000000000000000806 AssertionPropCallback::Unchanged : BB16 out -> 00000000000000000000000000008806; jumpDest out -> 00000000000000000000000000004806 AssertionPropCallback::StartMerge: BB17 in -> 00000000000000000000000000008806 AssertionPropCallback::Merge : BB17 in -> 00000000000000000000000000008806, predBlock BB16 out -> 00000000000000000000000000008806 AssertionPropCallback::EndMerge : BB17 in -> 00000000000000000000000000008806 AssertionPropCallback::Unchanged : BB17 out -> 00000000000000000000000000008806; jumpDest out -> 00000000000000000000000000008806 AssertionPropCallback::StartMerge: BB18 in -> 00000000000000000000000000000806 AssertionPropCallback::Merge : BB18 in -> 00000000000000000000000000000806, predBlock BB16 out -> 00000000000000000000000000004806 AssertionPropCallback::Merge : BB18 in -> 00000000000000000000000000000806, predBlock BB17 out -> 00000000000000000000000000008806 AssertionPropCallback::EndMerge : BB18 in -> 00000000000000000000000000000806 AssertionPropCallback::Unchanged : BB18 out -> 00000000000000000000000000030886; jumpDest out -> 00000000000000000000000000030906 AssertionPropCallback::StartMerge: BB18 in -> 00000000000000000000000000000806 AssertionPropCallback::Merge : BB18 in -> 00000000000000000000000000000806, predBlock BB16 out -> 00000000000000000000000000004806 AssertionPropCallback::Merge : BB18 in -> 00000000000000000000000000000806, predBlock BB17 out -> 00000000000000000000000000008806 AssertionPropCallback::EndMerge : BB18 in -> 00000000000000000000000000000806 AssertionPropCallback::Unchanged : BB18 out -> 00000000000000000000000000030886; jumpDest out -> 00000000000000000000000000030906 AssertionPropCallback::StartMerge: BB19 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB19 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB18 out -> 00000000000000000000000000030886 AssertionPropCallback::EndMerge : BB19 in -> 00000000000000000000000000030886 AssertionPropCallback::Changed : BB19 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000030886; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000030886; AssertionPropCallback::StartMerge: BB32 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB32 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB18 out -> 00000000000000000000000000030906 AssertionPropCallback::Merge : BB32 in -> 00000000000000000000000000030906, predBlock BB43 out -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::EndMerge : BB32 in -> 00000000000000000000000000030906 AssertionPropCallback::Changed : BB32 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000870906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000070906; AssertionPropCallback::StartMerge: BB16 in -> 00000000000000000000000000000806 AssertionPropCallback::Merge : BB16 in -> 00000000000000000000000000000806, predBlock BB14 out -> 00000000000000000000000000001806 AssertionPropCallback::Merge : BB16 in -> 00000000000000000000000000000806, predBlock BB15 out -> 00000000000000000000000000002806 AssertionPropCallback::EndMerge : BB16 in -> 00000000000000000000000000000806 AssertionPropCallback::Unchanged : BB16 out -> 00000000000000000000000000008806; jumpDest out -> 00000000000000000000000000004806 AssertionPropCallback::StartMerge: BB20 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB20 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB19 out -> 00000000000000000000000000030886 AssertionPropCallback::EndMerge : BB20 in -> 00000000000000000000000000030886 AssertionPropCallback::Changed : BB20 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000030886; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000030886; AssertionPropCallback::StartMerge: BB21 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB21 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB19 out -> 00000000000000000000000000030886 AssertionPropCallback::EndMerge : BB21 in -> 00000000000000000000000000030886 AssertionPropCallback::Changed : BB21 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000030886; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000030886; AssertionPropCallback::StartMerge: BB33 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB33 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB32 out -> 00000000000000000000000000870906 AssertionPropCallback::EndMerge : BB33 in -> 00000000000000000000000000870906 AssertionPropCallback::Changed : BB33 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000870906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000870906; AssertionPropCallback::StartMerge: BB44 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB44 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB23 out -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB44 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB32 out -> 00000000000000000000000000070906 AssertionPropCallback::EndMerge : BB44 in -> 00000000000000000000000000070906 AssertionPropCallback::Changed : BB44 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000004070906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000002070906; AssertionPropCallback::StartMerge: BB22 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB22 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB20 out -> 00000000000000000000000000030886 AssertionPropCallback::Merge : BB22 in -> 00000000000000000000000000030886, predBlock BB21 out -> 00000000000000000000000000030886 AssertionPropCallback::EndMerge : BB22 in -> 00000000000000000000000000030886 AssertionPropCallback::Changed : BB22 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000030886; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000030886; AssertionPropCallback::StartMerge: BB22 in -> 00000000000000000000000000030886 AssertionPropCallback::Merge : BB22 in -> 00000000000000000000000000030886, predBlock BB20 out -> 00000000000000000000000000030886 AssertionPropCallback::Merge : BB22 in -> 00000000000000000000000000030886, predBlock BB21 out -> 00000000000000000000000000030886 AssertionPropCallback::EndMerge : BB22 in -> 00000000000000000000000000030886 AssertionPropCallback::Unchanged : BB22 out -> 00000000000000000000000000030886; jumpDest out -> 00000000000000000000000000030886 AssertionPropCallback::StartMerge: BB34 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB34 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB33 out -> 00000000000000000000000000870906 AssertionPropCallback::EndMerge : BB34 in -> 00000000000000000000000000870906 AssertionPropCallback::Changed : BB34 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000870906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000870906; AssertionPropCallback::StartMerge: BB42 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB42 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB33 out -> 00000000000000000000000000870906 AssertionPropCallback::Merge : BB42 in -> 00000000000000000000000000870906, predBlock BB37 out -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::EndMerge : BB42 in -> 00000000000000000000000000870906 AssertionPropCallback::Changed : BB42 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000001870906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000001870906; AssertionPropCallback::StartMerge: BB45 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB45 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB44 out -> 00000000000000000000000004070906 AssertionPropCallback::EndMerge : BB45 in -> 00000000000000000000000004070906 AssertionPropCallback::Changed : BB45 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 0000000000000000000000002C070906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 0000000000000000000000001C070906; AssertionPropCallback::StartMerge: BB48 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB48 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB44 out -> 00000000000000000000000002070906 AssertionPropCallback::EndMerge : BB48 in -> 00000000000000000000000002070906 AssertionPropCallback::Changed : BB48 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000002070906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000002070906; AssertionPropCallback::StartMerge: BB23 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB23 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB22 out -> 00000000000000000000000000030886 AssertionPropCallback::Merge : BB23 in -> 00000000000000000000000000030886, predBlock BB27 out -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::EndMerge : BB23 in -> 00000000000000000000000000030886 AssertionPropCallback::Changed : BB23 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 000000000000000000000000000F0886; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000070886; AssertionPropCallback::StartMerge: BB35 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB35 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB34 out -> 00000000000000000000000000870906 AssertionPropCallback::EndMerge : BB35 in -> 00000000000000000000000000870906 AssertionPropCallback::Changed : BB35 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000870906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000870906; AssertionPropCallback::StartMerge: BB36 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB36 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB34 out -> 00000000000000000000000000870906 AssertionPropCallback::EndMerge : BB36 in -> 00000000000000000000000000870906 AssertionPropCallback::Changed : BB36 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000870906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000870906; AssertionPropCallback::StartMerge: BB43 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB43 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB42 out -> 00000000000000000000000001870906 AssertionPropCallback::EndMerge : BB43 in -> 00000000000000000000000001870906 AssertionPropCallback::Changed : BB43 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000001870906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000001870906; AssertionPropCallback::StartMerge: BB68 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB68 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB26 out -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB68 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB42 out -> 00000000000000000000000001870906 AssertionPropCallback::EndMerge : BB68 in -> 00000000000000000000000001870906 AssertionPropCallback::Changed : BB68 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000001870906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000001870906; AssertionPropCallback::StartMerge: BB46 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB46 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB45 out -> 0000000000000000000000002C070906 AssertionPropCallback::EndMerge : BB46 in -> 0000000000000000000000002C070906 AssertionPropCallback::Changed : BB46 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 0000000000000000000000002C070906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 0000000000000000000000002C070906; AssertionPropCallback::StartMerge: BB47 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB47 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB45 out -> 0000000000000000000000001C070906 AssertionPropCallback::Merge : BB47 in -> 0000000000000000000000001C070906, predBlock BB46 out -> 0000000000000000000000002C070906 AssertionPropCallback::EndMerge : BB47 in -> 0000000000000000000000000C070906 AssertionPropCallback::Changed : BB47 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 0000000000000000000000004C070906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 0000000000000000000000000C070906; AssertionPropCallback::StartMerge: BB49 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB49 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB48 out -> 00000000000000000000000002070906 AssertionPropCallback::EndMerge : BB49 in -> 00000000000000000000000002070906 AssertionPropCallback::Changed : BB49 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000282070906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000182070906; AssertionPropCallback::StartMerge: BB54 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB54 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB48 out -> 00000000000000000000000002070906 AssertionPropCallback::Merge : BB54 in -> 00000000000000000000000002070906, predBlock BB53 out -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::EndMerge : BB54 in -> 00000000000000000000000002070906 AssertionPropCallback::Changed : BB54 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000002070906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000002070906; AssertionPropCallback::StartMerge: BB24 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB24 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB23 out -> 000000000000000000000000000F0886 AssertionPropCallback::EndMerge : BB24 in -> 000000000000000000000000000F0886 AssertionPropCallback::Changed : BB24 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 000000000000000000000000000F0886; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 000000000000000000000000000F0886; AssertionPropCallback::StartMerge: BB44 in -> 00000000000000000000000000070906 AssertionPropCallback::Merge : BB44 in -> 00000000000000000000000000070906, predBlock BB23 out -> 00000000000000000000000000070886 AssertionPropCallback::Merge : BB44 in -> 00000000000000000000000000070806, predBlock BB32 out -> 00000000000000000000000000070906 AssertionPropCallback::EndMerge : BB44 in -> 00000000000000000000000000070806 AssertionPropCallback::Changed : BB44 before out -> 00000000000000000000000004070906; after out -> 00000000000000000000000004070806; jumpDest before out -> 00000000000000000000000002070906; jumpDest after out -> 00000000000000000000000002070806; AssertionPropCallback::StartMerge: BB37 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB37 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB35 out -> 00000000000000000000000000870906 AssertionPropCallback::Merge : BB37 in -> 00000000000000000000000000870906, predBlock BB36 out -> 00000000000000000000000000870906 AssertionPropCallback::EndMerge : BB37 in -> 00000000000000000000000000870906 AssertionPropCallback::Changed : BB37 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000870B06; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000870B06; AssertionPropCallback::StartMerge: BB37 in -> 00000000000000000000000000870906 AssertionPropCallback::Merge : BB37 in -> 00000000000000000000000000870906, predBlock BB35 out -> 00000000000000000000000000870906 AssertionPropCallback::Merge : BB37 in -> 00000000000000000000000000870906, predBlock BB36 out -> 00000000000000000000000000870906 AssertionPropCallback::EndMerge : BB37 in -> 00000000000000000000000000870906 AssertionPropCallback::Unchanged : BB37 out -> 00000000000000000000000000870B06; jumpDest out -> 00000000000000000000000000870B06 AssertionPropCallback::StartMerge: BB32 in -> 00000000000000000000000000030906 AssertionPropCallback::Merge : BB32 in -> 00000000000000000000000000030906, predBlock BB18 out -> 00000000000000000000000000030906 AssertionPropCallback::Merge : BB32 in -> 00000000000000000000000000030906, predBlock BB43 out -> 00000000000000000000000001870906 AssertionPropCallback::EndMerge : BB32 in -> 00000000000000000000000000030906 AssertionPropCallback::Unchanged : BB32 out -> 00000000000000000000000000870906; jumpDest out -> 00000000000000000000000000070906 AssertionPropCallback::StartMerge: BB47 in -> 0000000000000000000000000C070906 AssertionPropCallback::Merge : BB47 in -> 0000000000000000000000000C070906, predBlock BB45 out -> 0000000000000000000000001C070906 AssertionPropCallback::Merge : BB47 in -> 0000000000000000000000000C070906, predBlock BB46 out -> 0000000000000000000000002C070906 AssertionPropCallback::EndMerge : BB47 in -> 0000000000000000000000000C070906 AssertionPropCallback::Unchanged : BB47 out -> 0000000000000000000000004C070906; jumpDest out -> 0000000000000000000000000C070906 AssertionPropCallback::StartMerge: BB55 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB55 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB47 out -> 0000000000000000000000004C070906 AssertionPropCallback::Merge : BB55 in -> 0000000000000000000000004C070906, predBlock BB54 out -> 00000000000000000000000002070906 AssertionPropCallback::EndMerge : BB55 in -> 00000000000000000000000000070906 AssertionPropCallback::Changed : BB55 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 0000000000000000000003E000070906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 0000000000000000000003E000070906; AssertionPropCallback::StartMerge: BB50 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB50 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB49 out -> 00000000000000000000000282070906 AssertionPropCallback::EndMerge : BB50 in -> 00000000000000000000000282070906 AssertionPropCallback::Changed : BB50 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000282070906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000282070906; AssertionPropCallback::StartMerge: BB51 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB51 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB49 out -> 00000000000000000000000182070906 AssertionPropCallback::Merge : BB51 in -> 00000000000000000000000182070906, predBlock BB50 out -> 00000000000000000000000282070906 AssertionPropCallback::EndMerge : BB51 in -> 00000000000000000000000082070906 AssertionPropCallback::Changed : BB51 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000882070906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000482070906; AssertionPropCallback::StartMerge: BB55 in -> 00000000000000000000000000070906 AssertionPropCallback::Merge : BB55 in -> 00000000000000000000000000070906, predBlock BB47 out -> 0000000000000000000000004C070906 AssertionPropCallback::Merge : BB55 in -> 00000000000000000000000000070906, predBlock BB54 out -> 00000000000000000000000002070906 AssertionPropCallback::EndMerge : BB55 in -> 00000000000000000000000000070906 AssertionPropCallback::Unchanged : BB55 out -> 0000000000000000000003E000070906; jumpDest out -> 0000000000000000000003E000070906 AssertionPropCallback::StartMerge: BB25 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB25 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB24 out -> 000000000000000000000000000F0886 AssertionPropCallback::EndMerge : BB25 in -> 000000000000000000000000000F0886 AssertionPropCallback::Changed : BB25 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 000000000000000000000000001F0886; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 000000000000000000000000001F0886; AssertionPropCallback::StartMerge: BB26 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB26 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB24 out -> 000000000000000000000000000F0886 AssertionPropCallback::Merge : BB26 in -> 000000000000000000000000000F0886, predBlock BB25 out -> 000000000000000000000000001F0886 AssertionPropCallback::EndMerge : BB26 in -> 000000000000000000000000000F0886 AssertionPropCallback::Changed : BB26 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 000000000000000000000000002F0886; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 000000000000000000000000002F0886; AssertionPropCallback::StartMerge: BB45 in -> 00000000000000000000000004070906 AssertionPropCallback::Merge : BB45 in -> 00000000000000000000000004070906, predBlock BB44 out -> 00000000000000000000000004070806 AssertionPropCallback::EndMerge : BB45 in -> 00000000000000000000000004070806 AssertionPropCallback::Changed : BB45 before out -> 0000000000000000000000002C070906; after out -> 0000000000000000000000002C070806; jumpDest before out -> 0000000000000000000000001C070906; jumpDest after out -> 0000000000000000000000001C070806; AssertionPropCallback::StartMerge: BB48 in -> 00000000000000000000000002070906 AssertionPropCallback::Merge : BB48 in -> 00000000000000000000000002070906, predBlock BB44 out -> 00000000000000000000000002070806 AssertionPropCallback::EndMerge : BB48 in -> 00000000000000000000000002070806 AssertionPropCallback::Changed : BB48 before out -> 00000000000000000000000002070906; after out -> 00000000000000000000000002070806; jumpDest before out -> 00000000000000000000000002070906; jumpDest after out -> 00000000000000000000000002070806; AssertionPropCallback::StartMerge: BB38 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB38 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB37 out -> 00000000000000000000000000870B06 AssertionPropCallback::EndMerge : BB38 in -> 00000000000000000000000000870B06 AssertionPropCallback::Changed : BB38 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000870B06; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000870B06; AssertionPropCallback::StartMerge: BB42 in -> 00000000000000000000000000870906 AssertionPropCallback::Merge : BB42 in -> 00000000000000000000000000870906, predBlock BB33 out -> 00000000000000000000000000870906 AssertionPropCallback::Merge : BB42 in -> 00000000000000000000000000870906, predBlock BB37 out -> 00000000000000000000000000870B06 AssertionPropCallback::EndMerge : BB42 in -> 00000000000000000000000000870906 AssertionPropCallback::Unchanged : BB42 out -> 00000000000000000000000001870906; jumpDest out -> 00000000000000000000000001870906 AssertionPropCallback::StartMerge: BB56 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB56 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB55 out -> 0000000000000000000003E000070906 AssertionPropCallback::EndMerge : BB56 in -> 0000000000000000000003E000070906 AssertionPropCallback::Changed : BB56 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 000000000000000000000BE000070906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 0000000000000000000007E000070906; AssertionPropCallback::StartMerge: BB58 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB58 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB29 out -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB58 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB39 out -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB58 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB55 out -> 0000000000000000000003E000070906 AssertionPropCallback::Merge : BB58 in -> 0000000000000000000003E000070906, predBlock BB56 out -> 0000000000000000000007E000070906 AssertionPropCallback::Merge : BB58 in -> 0000000000000000000003E000070906, predBlock BB57 out -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::EndMerge : BB58 in -> 0000000000000000000003E000070906 AssertionPropCallback::Changed : BB58 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 0000000000000000000003E000070906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 0000000000000000000003E000070906; AssertionPropCallback::StartMerge: BB51 in -> 00000000000000000000000082070906 AssertionPropCallback::Merge : BB51 in -> 00000000000000000000000082070906, predBlock BB49 out -> 00000000000000000000000182070906 AssertionPropCallback::Merge : BB51 in -> 00000000000000000000000082070906, predBlock BB50 out -> 00000000000000000000000282070906 AssertionPropCallback::EndMerge : BB51 in -> 00000000000000000000000082070906 AssertionPropCallback::Unchanged : BB51 out -> 00000000000000000000000882070906; jumpDest out -> 00000000000000000000000482070906 AssertionPropCallback::StartMerge: BB52 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB52 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB51 out -> 00000000000000000000000882070906 AssertionPropCallback::EndMerge : BB52 in -> 00000000000000000000000882070906 AssertionPropCallback::Changed : BB52 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000882070906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000882070906; AssertionPropCallback::StartMerge: BB53 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB53 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB51 out -> 00000000000000000000000482070906 AssertionPropCallback::Merge : BB53 in -> 00000000000000000000000482070906, predBlock BB52 out -> 00000000000000000000000882070906 AssertionPropCallback::EndMerge : BB53 in -> 00000000000000000000000082070906 AssertionPropCallback::Changed : BB53 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000001082070906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000082070906; AssertionPropCallback::StartMerge: BB26 in -> 000000000000000000000000000F0886 AssertionPropCallback::Merge : BB26 in -> 000000000000000000000000000F0886, predBlock BB24 out -> 000000000000000000000000000F0886 AssertionPropCallback::Merge : BB26 in -> 000000000000000000000000000F0886, predBlock BB25 out -> 000000000000000000000000001F0886 AssertionPropCallback::EndMerge : BB26 in -> 000000000000000000000000000F0886 AssertionPropCallback::Unchanged : BB26 out -> 000000000000000000000000002F0886; jumpDest out -> 000000000000000000000000002F0886 AssertionPropCallback::StartMerge: BB28 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB28 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB25 out -> 000000000000000000000000001F0886 AssertionPropCallback::EndMerge : BB28 in -> 000000000000000000000000001F0886 AssertionPropCallback::Changed : BB28 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 000000000000000000000000001F0886; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 000000000000000000000000001F0886; AssertionPropCallback::StartMerge: BB27 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB27 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB26 out -> 000000000000000000000000002F0886 AssertionPropCallback::EndMerge : BB27 in -> 000000000000000000000000002F0886 AssertionPropCallback::Changed : BB27 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 000000000000000000000000002F0886; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 000000000000000000000000002F0886; AssertionPropCallback::StartMerge: BB68 in -> 00000000000000000000000001870906 AssertionPropCallback::Merge : BB68 in -> 00000000000000000000000001870906, predBlock BB26 out -> 000000000000000000000000002F0886 AssertionPropCallback::Merge : BB68 in -> 00000000000000000000000000070806, predBlock BB42 out -> 00000000000000000000000001870906 AssertionPropCallback::EndMerge : BB68 in -> 00000000000000000000000000070806 AssertionPropCallback::Changed : BB68 before out -> 00000000000000000000000001870906; after out -> 00000000000000000000000000070806; jumpDest before out -> 00000000000000000000000001870906; jumpDest after out -> 00000000000000000000000000070806; AssertionPropCallback::StartMerge: BB46 in -> 0000000000000000000000002C070906 AssertionPropCallback::Merge : BB46 in -> 0000000000000000000000002C070906, predBlock BB45 out -> 0000000000000000000000002C070806 AssertionPropCallback::EndMerge : BB46 in -> 0000000000000000000000002C070806 AssertionPropCallback::Changed : BB46 before out -> 0000000000000000000000002C070906; after out -> 0000000000000000000000002C070806; jumpDest before out -> 0000000000000000000000002C070906; jumpDest after out -> 0000000000000000000000002C070806; AssertionPropCallback::StartMerge: BB47 in -> 0000000000000000000000000C070906 AssertionPropCallback::Merge : BB47 in -> 0000000000000000000000000C070906, predBlock BB45 out -> 0000000000000000000000001C070806 AssertionPropCallback::Merge : BB47 in -> 0000000000000000000000000C070806, predBlock BB46 out -> 0000000000000000000000002C070806 AssertionPropCallback::EndMerge : BB47 in -> 0000000000000000000000000C070806 AssertionPropCallback::Changed : BB47 before out -> 0000000000000000000000004C070906; after out -> 0000000000000000000000004C070806; jumpDest before out -> 0000000000000000000000000C070906; jumpDest after out -> 0000000000000000000000000C070806; AssertionPropCallback::StartMerge: BB49 in -> 00000000000000000000000002070906 AssertionPropCallback::Merge : BB49 in -> 00000000000000000000000002070906, predBlock BB48 out -> 00000000000000000000000002070806 AssertionPropCallback::EndMerge : BB49 in -> 00000000000000000000000002070806 AssertionPropCallback::Changed : BB49 before out -> 00000000000000000000000282070906; after out -> 00000000000000000000000282070806; jumpDest before out -> 00000000000000000000000182070906; jumpDest after out -> 00000000000000000000000182070806; AssertionPropCallback::StartMerge: BB54 in -> 00000000000000000000000002070906 AssertionPropCallback::Merge : BB54 in -> 00000000000000000000000002070906, predBlock BB48 out -> 00000000000000000000000002070806 AssertionPropCallback::Merge : BB54 in -> 00000000000000000000000002070806, predBlock BB53 out -> 00000000000000000000001082070906 AssertionPropCallback::EndMerge : BB54 in -> 00000000000000000000000002070806 AssertionPropCallback::Changed : BB54 before out -> 00000000000000000000000002070906; after out -> 00000000000000000000000002070806; jumpDest before out -> 00000000000000000000000002070906; jumpDest after out -> 00000000000000000000000002070806; AssertionPropCallback::StartMerge: BB39 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB39 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB38 out -> 00000000000000000000000000870B06 AssertionPropCallback::EndMerge : BB39 in -> 00000000000000000000000000870B06 AssertionPropCallback::Changed : BB39 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000001870B06; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000870B06; AssertionPropCallback::StartMerge: BB40 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB40 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB38 out -> 00000000000000000000000000870B06 AssertionPropCallback::EndMerge : BB40 in -> 00000000000000000000000000870B06 AssertionPropCallback::Changed : BB40 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000870B06; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000870B06; AssertionPropCallback::StartMerge: BB57 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB57 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB56 out -> 000000000000000000000BE000070906 AssertionPropCallback::EndMerge : BB57 in -> 000000000000000000000BE000070906 AssertionPropCallback::Changed : BB57 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 000000000000000000000BE000070906; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 000000000000000000000BE000070906; AssertionPropCallback::StartMerge: BB58 in -> 0000000000000000000003E000070906 AssertionPropCallback::Merge : BB58 in -> 0000000000000000000003E000070906, predBlock BB29 out -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB58 in -> 0000000000000000000003E000070906, predBlock BB39 out -> 00000000000000000000000001870B06 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070906, predBlock BB55 out -> 0000000000000000000003E000070906 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070906, predBlock BB56 out -> 0000000000000000000007E000070906 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070906, predBlock BB57 out -> 000000000000000000000BE000070906 AssertionPropCallback::EndMerge : BB58 in -> 00000000000000000000000000070906 AssertionPropCallback::Changed : BB58 before out -> 0000000000000000000003E000070906; after out -> 00000000000000000000000000070906; jumpDest before out -> 0000000000000000000003E000070906; jumpDest after out -> 00000000000000000000000000070906; AssertionPropCallback::StartMerge: BB53 in -> 00000000000000000000000082070906 AssertionPropCallback::Merge : BB53 in -> 00000000000000000000000082070906, predBlock BB51 out -> 00000000000000000000000482070906 AssertionPropCallback::Merge : BB53 in -> 00000000000000000000000082070906, predBlock BB52 out -> 00000000000000000000000882070906 AssertionPropCallback::EndMerge : BB53 in -> 00000000000000000000000082070906 AssertionPropCallback::Unchanged : BB53 out -> 00000000000000000000001082070906; jumpDest out -> 00000000000000000000000082070906 AssertionPropCallback::StartMerge: BB54 in -> 00000000000000000000000002070806 AssertionPropCallback::Merge : BB54 in -> 00000000000000000000000002070806, predBlock BB48 out -> 00000000000000000000000002070806 AssertionPropCallback::Merge : BB54 in -> 00000000000000000000000002070806, predBlock BB53 out -> 00000000000000000000001082070906 AssertionPropCallback::EndMerge : BB54 in -> 00000000000000000000000002070806 AssertionPropCallback::Unchanged : BB54 out -> 00000000000000000000000002070806; jumpDest out -> 00000000000000000000000002070806 AssertionPropCallback::StartMerge: BB29 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB29 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB28 out -> 000000000000000000000000001F0886 AssertionPropCallback::EndMerge : BB29 in -> 000000000000000000000000001F0886 AssertionPropCallback::Changed : BB29 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 000000000000000000000000003F0886; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 000000000000000000000000001F0886; AssertionPropCallback::StartMerge: BB30 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB30 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB28 out -> 000000000000000000000000001F0886 AssertionPropCallback::EndMerge : BB30 in -> 000000000000000000000000001F0886 AssertionPropCallback::Changed : BB30 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 000000000000000000000000001F0886; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 000000000000000000000000001F0886; AssertionPropCallback::StartMerge: BB23 in -> 00000000000000000000000000030886 AssertionPropCallback::Merge : BB23 in -> 00000000000000000000000000030886, predBlock BB22 out -> 00000000000000000000000000030886 AssertionPropCallback::Merge : BB23 in -> 00000000000000000000000000030886, predBlock BB27 out -> 000000000000000000000000002F0886 AssertionPropCallback::EndMerge : BB23 in -> 00000000000000000000000000030886 AssertionPropCallback::Unchanged : BB23 out -> 000000000000000000000000000F0886; jumpDest out -> 00000000000000000000000000070886 AssertionPropCallback::StartMerge: BB47 in -> 0000000000000000000000000C070806 AssertionPropCallback::Merge : BB47 in -> 0000000000000000000000000C070806, predBlock BB45 out -> 0000000000000000000000001C070806 AssertionPropCallback::Merge : BB47 in -> 0000000000000000000000000C070806, predBlock BB46 out -> 0000000000000000000000002C070806 AssertionPropCallback::EndMerge : BB47 in -> 0000000000000000000000000C070806 AssertionPropCallback::Unchanged : BB47 out -> 0000000000000000000000004C070806; jumpDest out -> 0000000000000000000000000C070806 AssertionPropCallback::StartMerge: BB55 in -> 00000000000000000000000000070906 AssertionPropCallback::Merge : BB55 in -> 00000000000000000000000000070906, predBlock BB47 out -> 0000000000000000000000004C070806 AssertionPropCallback::Merge : BB55 in -> 00000000000000000000000000070806, predBlock BB54 out -> 00000000000000000000000002070806 AssertionPropCallback::EndMerge : BB55 in -> 00000000000000000000000000070806 AssertionPropCallback::Changed : BB55 before out -> 0000000000000000000003E000070906; after out -> 0000000000000000000003E000070806; jumpDest before out -> 0000000000000000000003E000070906; jumpDest after out -> 0000000000000000000003E000070806; AssertionPropCallback::StartMerge: BB50 in -> 00000000000000000000000282070906 AssertionPropCallback::Merge : BB50 in -> 00000000000000000000000282070906, predBlock BB49 out -> 00000000000000000000000282070806 AssertionPropCallback::EndMerge : BB50 in -> 00000000000000000000000282070806 AssertionPropCallback::Changed : BB50 before out -> 00000000000000000000000282070906; after out -> 00000000000000000000000282070806; jumpDest before out -> 00000000000000000000000282070906; jumpDest after out -> 00000000000000000000000282070806; AssertionPropCallback::StartMerge: BB51 in -> 00000000000000000000000082070906 AssertionPropCallback::Merge : BB51 in -> 00000000000000000000000082070906, predBlock BB49 out -> 00000000000000000000000182070806 AssertionPropCallback::Merge : BB51 in -> 00000000000000000000000082070806, predBlock BB50 out -> 00000000000000000000000282070806 AssertionPropCallback::EndMerge : BB51 in -> 00000000000000000000000082070806 AssertionPropCallback::Changed : BB51 before out -> 00000000000000000000000882070906; after out -> 00000000000000000000000882070806; jumpDest before out -> 00000000000000000000000482070906; jumpDest after out -> 00000000000000000000000482070806; AssertionPropCallback::StartMerge: BB55 in -> 00000000000000000000000000070806 AssertionPropCallback::Merge : BB55 in -> 00000000000000000000000000070806, predBlock BB47 out -> 0000000000000000000000004C070806 AssertionPropCallback::Merge : BB55 in -> 00000000000000000000000000070806, predBlock BB54 out -> 00000000000000000000000002070806 AssertionPropCallback::EndMerge : BB55 in -> 00000000000000000000000000070806 AssertionPropCallback::Unchanged : BB55 out -> 0000000000000000000003E000070806; jumpDest out -> 0000000000000000000003E000070806 AssertionPropCallback::StartMerge: BB58 in -> 00000000000000000000000000070906 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070906, predBlock BB29 out -> 000000000000000000000000003F0886 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB39 out -> 00000000000000000000000001870B06 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB55 out -> 0000000000000000000003E000070806 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB56 out -> 0000000000000000000007E000070906 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB57 out -> 000000000000000000000BE000070906 AssertionPropCallback::EndMerge : BB58 in -> 00000000000000000000000000070806 AssertionPropCallback::Changed : BB58 before out -> 00000000000000000000000000070906; after out -> 00000000000000000000000000070806; jumpDest before out -> 00000000000000000000000000070906; jumpDest after out -> 00000000000000000000000000070806; AssertionPropCallback::StartMerge: BB41 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB41 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB40 out -> 00000000000000000000000000870B06 AssertionPropCallback::EndMerge : BB41 in -> 00000000000000000000000000870B06 AssertionPropCallback::Changed : BB41 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000870B06; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000870B06; AssertionPropCallback::StartMerge: BB64 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB64 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB40 out -> 00000000000000000000000000870B06 AssertionPropCallback::EndMerge : BB64 in -> 00000000000000000000000000870B06 AssertionPropCallback::Changed : BB64 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000870B06; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000870B06; AssertionPropCallback::StartMerge: BB58 in -> 00000000000000000000000000070806 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB29 out -> 000000000000000000000000003F0886 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB39 out -> 00000000000000000000000001870B06 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB55 out -> 0000000000000000000003E000070806 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB56 out -> 0000000000000000000007E000070906 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB57 out -> 000000000000000000000BE000070906 AssertionPropCallback::EndMerge : BB58 in -> 00000000000000000000000000070806 AssertionPropCallback::Unchanged : BB58 out -> 00000000000000000000000000070806; jumpDest out -> 00000000000000000000000000070806 AssertionPropCallback::StartMerge: BB58 in -> 00000000000000000000000000070806 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB29 out -> 000000000000000000000000003F0886 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB39 out -> 00000000000000000000000001870B06 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB55 out -> 0000000000000000000003E000070806 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB56 out -> 0000000000000000000007E000070906 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB57 out -> 000000000000000000000BE000070906 AssertionPropCallback::EndMerge : BB58 in -> 00000000000000000000000000070806 AssertionPropCallback::Unchanged : BB58 out -> 00000000000000000000000000070806; jumpDest out -> 00000000000000000000000000070806 AssertionPropCallback::StartMerge: BB31 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB31 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB30 out -> 000000000000000000000000001F0886 AssertionPropCallback::Merge : BB31 in -> 000000000000000000000000001F0886, predBlock BB41 out -> 00000000000000000000000000870B06 AssertionPropCallback::EndMerge : BB31 in -> 00000000000000000000000000070806 AssertionPropCallback::Changed : BB31 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000070806; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000070806; AssertionPropCallback::StartMerge: BB60 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB60 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB30 out -> 000000000000000000000000001F0886 AssertionPropCallback::EndMerge : BB60 in -> 000000000000000000000000001F0886 AssertionPropCallback::Changed : BB60 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 000000000000000000000000001F0886; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 000000000000000000000000001F0886; AssertionPropCallback::StartMerge: BB56 in -> 0000000000000000000003E000070906 AssertionPropCallback::Merge : BB56 in -> 0000000000000000000003E000070906, predBlock BB55 out -> 0000000000000000000003E000070806 AssertionPropCallback::EndMerge : BB56 in -> 0000000000000000000003E000070806 AssertionPropCallback::Changed : BB56 before out -> 000000000000000000000BE000070906; after out -> 000000000000000000000BE000070806; jumpDest before out -> 0000000000000000000007E000070906; jumpDest after out -> 0000000000000000000007E000070806; AssertionPropCallback::StartMerge: BB58 in -> 00000000000000000000000000070806 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB29 out -> 000000000000000000000000003F0886 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB39 out -> 00000000000000000000000001870B06 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB55 out -> 0000000000000000000003E000070806 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB56 out -> 0000000000000000000007E000070806 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB57 out -> 000000000000000000000BE000070906 AssertionPropCallback::EndMerge : BB58 in -> 00000000000000000000000000070806 AssertionPropCallback::Unchanged : BB58 out -> 00000000000000000000000000070806; jumpDest out -> 00000000000000000000000000070806 AssertionPropCallback::StartMerge: BB51 in -> 00000000000000000000000082070806 AssertionPropCallback::Merge : BB51 in -> 00000000000000000000000082070806, predBlock BB49 out -> 00000000000000000000000182070806 AssertionPropCallback::Merge : BB51 in -> 00000000000000000000000082070806, predBlock BB50 out -> 00000000000000000000000282070806 AssertionPropCallback::EndMerge : BB51 in -> 00000000000000000000000082070806 AssertionPropCallback::Unchanged : BB51 out -> 00000000000000000000000882070806; jumpDest out -> 00000000000000000000000482070806 AssertionPropCallback::StartMerge: BB52 in -> 00000000000000000000000882070906 AssertionPropCallback::Merge : BB52 in -> 00000000000000000000000882070906, predBlock BB51 out -> 00000000000000000000000882070806 AssertionPropCallback::EndMerge : BB52 in -> 00000000000000000000000882070806 AssertionPropCallback::Changed : BB52 before out -> 00000000000000000000000882070906; after out -> 00000000000000000000000882070806; jumpDest before out -> 00000000000000000000000882070906; jumpDest after out -> 00000000000000000000000882070806; AssertionPropCallback::StartMerge: BB53 in -> 00000000000000000000000082070906 AssertionPropCallback::Merge : BB53 in -> 00000000000000000000000082070906, predBlock BB51 out -> 00000000000000000000000482070806 AssertionPropCallback::Merge : BB53 in -> 00000000000000000000000082070806, predBlock BB52 out -> 00000000000000000000000882070806 AssertionPropCallback::EndMerge : BB53 in -> 00000000000000000000000082070806 AssertionPropCallback::Changed : BB53 before out -> 00000000000000000000001082070906; after out -> 00000000000000000000001082070806; jumpDest before out -> 00000000000000000000000082070906; jumpDest after out -> 00000000000000000000000082070806; AssertionPropCallback::StartMerge: BB31 in -> 00000000000000000000000000070806 AssertionPropCallback::Merge : BB31 in -> 00000000000000000000000000070806, predBlock BB30 out -> 000000000000000000000000001F0886 AssertionPropCallback::Merge : BB31 in -> 00000000000000000000000000070806, predBlock BB41 out -> 00000000000000000000000000870B06 AssertionPropCallback::EndMerge : BB31 in -> 00000000000000000000000000070806 AssertionPropCallback::Unchanged : BB31 out -> 00000000000000000000000000070806; jumpDest out -> 00000000000000000000000000070806 AssertionPropCallback::StartMerge: BB65 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB65 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB64 out -> 00000000000000000000000000870B06 AssertionPropCallback::EndMerge : BB65 in -> 00000000000000000000000000870B06 AssertionPropCallback::Changed : BB65 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000870B06; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000870B06; AssertionPropCallback::StartMerge: BB66 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB66 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB64 out -> 00000000000000000000000000870B06 AssertionPropCallback::EndMerge : BB66 in -> 00000000000000000000000000870B06 AssertionPropCallback::Changed : BB66 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000870B06; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000870B06; AssertionPropCallback::StartMerge: BB61 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB61 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB60 out -> 000000000000000000000000001F0886 AssertionPropCallback::EndMerge : BB61 in -> 000000000000000000000000001F0886 AssertionPropCallback::Changed : BB61 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 000000000000000000000000001F0886; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 000000000000000000000000001F0886; AssertionPropCallback::StartMerge: BB62 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB62 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB60 out -> 000000000000000000000000001F0886 AssertionPropCallback::EndMerge : BB62 in -> 000000000000000000000000001F0886 AssertionPropCallback::Changed : BB62 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 000000000000000000000000001F0886; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 000000000000000000000000001F0886; AssertionPropCallback::StartMerge: BB57 in -> 000000000000000000000BE000070906 AssertionPropCallback::Merge : BB57 in -> 000000000000000000000BE000070906, predBlock BB56 out -> 000000000000000000000BE000070806 AssertionPropCallback::EndMerge : BB57 in -> 000000000000000000000BE000070806 AssertionPropCallback::Changed : BB57 before out -> 000000000000000000000BE000070906; after out -> 000000000000000000000BE000070806; jumpDest before out -> 000000000000000000000BE000070906; jumpDest after out -> 000000000000000000000BE000070806; AssertionPropCallback::StartMerge: BB58 in -> 00000000000000000000000000070806 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB29 out -> 000000000000000000000000003F0886 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB39 out -> 00000000000000000000000001870B06 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB55 out -> 0000000000000000000003E000070806 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB56 out -> 0000000000000000000007E000070806 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB57 out -> 000000000000000000000BE000070806 AssertionPropCallback::EndMerge : BB58 in -> 00000000000000000000000000070806 AssertionPropCallback::Unchanged : BB58 out -> 00000000000000000000000000070806; jumpDest out -> 00000000000000000000000000070806 AssertionPropCallback::StartMerge: BB53 in -> 00000000000000000000000082070806 AssertionPropCallback::Merge : BB53 in -> 00000000000000000000000082070806, predBlock BB51 out -> 00000000000000000000000482070806 AssertionPropCallback::Merge : BB53 in -> 00000000000000000000000082070806, predBlock BB52 out -> 00000000000000000000000882070806 AssertionPropCallback::EndMerge : BB53 in -> 00000000000000000000000082070806 AssertionPropCallback::Unchanged : BB53 out -> 00000000000000000000001082070806; jumpDest out -> 00000000000000000000000082070806 AssertionPropCallback::StartMerge: BB54 in -> 00000000000000000000000002070806 AssertionPropCallback::Merge : BB54 in -> 00000000000000000000000002070806, predBlock BB48 out -> 00000000000000000000000002070806 AssertionPropCallback::Merge : BB54 in -> 00000000000000000000000002070806, predBlock BB53 out -> 00000000000000000000001082070806 AssertionPropCallback::EndMerge : BB54 in -> 00000000000000000000000002070806 AssertionPropCallback::Unchanged : BB54 out -> 00000000000000000000000002070806; jumpDest out -> 00000000000000000000000002070806 AssertionPropCallback::StartMerge: BB67 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB67 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB65 out -> 00000000000000000000000000870B06 AssertionPropCallback::Merge : BB67 in -> 00000000000000000000000000870B06, predBlock BB66 out -> 00000000000000000000000000870B06 AssertionPropCallback::EndMerge : BB67 in -> 00000000000000000000000000870B06 AssertionPropCallback::Changed : BB67 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 00000000000000000000000000870B06; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 00000000000000000000000000870B06; AssertionPropCallback::StartMerge: BB67 in -> 00000000000000000000000000870B06 AssertionPropCallback::Merge : BB67 in -> 00000000000000000000000000870B06, predBlock BB65 out -> 00000000000000000000000000870B06 AssertionPropCallback::Merge : BB67 in -> 00000000000000000000000000870B06, predBlock BB66 out -> 00000000000000000000000000870B06 AssertionPropCallback::EndMerge : BB67 in -> 00000000000000000000000000870B06 AssertionPropCallback::Unchanged : BB67 out -> 00000000000000000000000000870B06; jumpDest out -> 00000000000000000000000000870B06 AssertionPropCallback::StartMerge: BB63 in -> 000000000000000000000FFFFFFFFFFF AssertionPropCallback::Merge : BB63 in -> 000000000000000000000FFFFFFFFFFF, predBlock BB61 out -> 000000000000000000000000001F0886 AssertionPropCallback::Merge : BB63 in -> 000000000000000000000000001F0886, predBlock BB62 out -> 000000000000000000000000001F0886 AssertionPropCallback::EndMerge : BB63 in -> 000000000000000000000000001F0886 AssertionPropCallback::Changed : BB63 before out -> 000000000000000000000FFFFFFFFFFF; after out -> 000000000000000000000000001F0886; jumpDest before out -> 000000000000000000000FFFFFFFFFFF; jumpDest after out -> 000000000000000000000000001F0886; AssertionPropCallback::StartMerge: BB63 in -> 000000000000000000000000001F0886 AssertionPropCallback::Merge : BB63 in -> 000000000000000000000000001F0886, predBlock BB61 out -> 000000000000000000000000001F0886 AssertionPropCallback::Merge : BB63 in -> 000000000000000000000000001F0886, predBlock BB62 out -> 000000000000000000000000001F0886 AssertionPropCallback::EndMerge : BB63 in -> 000000000000000000000000001F0886 AssertionPropCallback::Unchanged : BB63 out -> 000000000000000000000000001F0886; jumpDest out -> 000000000000000000000000001F0886 AssertionPropCallback::StartMerge: BB58 in -> 00000000000000000000000000070806 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB29 out -> 000000000000000000000000003F0886 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB39 out -> 00000000000000000000000001870B06 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB55 out -> 0000000000000000000003E000070806 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB56 out -> 0000000000000000000007E000070806 AssertionPropCallback::Merge : BB58 in -> 00000000000000000000000000070806, predBlock BB57 out -> 000000000000000000000BE000070806 AssertionPropCallback::EndMerge : BB58 in -> 00000000000000000000000000070806 AssertionPropCallback::Unchanged : BB58 out -> 00000000000000000000000000070806; jumpDest out -> 00000000000000000000000000070806 Compiler::optImpliedByTypeOfAssertions: Subtype Assertion #44, implies assertion #09 BB01 valueIn = 00000000000000000000000000000000 valueOut = 00000000000000000000000000000002 => BB59 valueOut= 00000000000000000000000000000001 BB02 valueIn = 00000000000000000000000000000002 valueOut = 00000000000000000000000000000006 => BB04 valueOut= 00000000000000000000000000000006 BB03 valueIn = 00000000000000000000000000000006 valueOut = 00000000000000000000000000000006 BB04 valueIn = 00000000000000000000000000000006 valueOut = 00000000000000000000000000000016 => BB06 valueOut= 0000000000000000000000000000000E BB05 valueIn = 00000000000000000000000000000016 valueOut = 00000000000000000000000000000016 BB06 valueIn = 00000000000000000000000000000006 valueOut = 00000000000000000000000000000046 => BB08 valueOut= 00000000000000000000000000000026 BB07 valueIn = 00000000000000000000000000000046 valueOut = 00000000000000000000000000000046 BB08 valueIn = 00000000000000000000000000000006 valueOut = 00000000000000000000000000000106 => BB13 valueOut= 00000000000000000000000000000086 BB09 valueIn = 00000000000000000000000000000106 valueOut = 00000000000000000000000000000106 => BB11 valueOut= 00000000000000000000000000000106 BB10 valueIn = 00000000000000000000000000000106 valueOut = 00000000000000000000000000000106 BB11 valueIn = 00000000000000000000000000000106 valueOut = 00000000000000000000000000000106 BB12 valueIn = 00000000000000000000000000000106 valueOut = 00000000000000000000000000000306 BB13 valueIn = 00000000000000000000000000000086 valueOut = 00000000000000000000000000000486 BB14 valueIn = 00000000000000000000000000000006 valueOut = 00000000000000000000000000002806 => BB16 valueOut= 00000000000000000000000000001806 BB15 valueIn = 00000000000000000000000000002806 valueOut = 00000000000000000000000000002806 BB16 valueIn = 00000000000000000000000000000806 valueOut = 00000000000000000000000000008806 => BB18 valueOut= 00000000000000000000000000004806 BB17 valueIn = 00000000000000000000000000008806 valueOut = 00000000000000000000000000008806 BB18 valueIn = 00000000000000000000000000000806 valueOut = 00000000000000000000000000030886 => BB32 valueOut= 00000000000000000000000000030906 BB19 valueIn = 00000000000000000000000000030886 valueOut = 00000000000000000000000000030886 => BB21 valueOut= 00000000000000000000000000030886 BB20 valueIn = 00000000000000000000000000030886 valueOut = 00000000000000000000000000030886 BB21 valueIn = 00000000000000000000000000030886 valueOut = 00000000000000000000000000030886 BB22 valueIn = 00000000000000000000000000030886 valueOut = 00000000000000000000000000030886 BB23 valueIn = 00000000000000000000000000030886 valueOut = 000000000000000000000000000F0886 => BB44 valueOut= 00000000000000000000000000070886 BB24 valueIn = 000000000000000000000000000F0886 valueOut = 000000000000000000000000000F0886 => BB26 valueOut= 000000000000000000000000000F0886 BB25 valueIn = 000000000000000000000000000F0886 valueOut = 000000000000000000000000001F0886 => BB28 valueOut= 000000000000000000000000001F0886 BB26 valueIn = 000000000000000000000000000F0886 valueOut = 000000000000000000000000002F0886 => BB68 valueOut= 000000000000000000000000002F0886 BB27 valueIn = 000000000000000000000000002F0886 valueOut = 000000000000000000000000002F0886 BB28 valueIn = 000000000000000000000000001F0886 valueOut = 000000000000000000000000001F0886 => BB30 valueOut= 000000000000000000000000001F0886 BB29 valueIn = 000000000000000000000000001F0886 valueOut = 000000000000000000000000003F0886 BB30 valueIn = 000000000000000000000000001F0886 valueOut = 000000000000000000000000001F0886 => BB60 valueOut= 000000000000000000000000001F0886 BB31 valueIn = 00000000000000000000000000070806 valueOut = 00000000000000000000000000070806 BB32 valueIn = 00000000000000000000000000030906 valueOut = 00000000000000000000000000870906 => BB44 valueOut= 00000000000000000000000000070906 BB33 valueIn = 00000000000000000000000000870906 valueOut = 00000000000000000000000000870906 => BB42 valueOut= 00000000000000000000000000870906 BB34 valueIn = 00000000000000000000000000870906 valueOut = 00000000000000000000000000870906 => BB36 valueOut= 00000000000000000000000000870906 BB35 valueIn = 00000000000000000000000000870906 valueOut = 00000000000000000000000000870906 BB36 valueIn = 00000000000000000000000000870906 valueOut = 00000000000000000000000000870906 BB37 valueIn = 00000000000000000000000000870906 valueOut = 00000000000000000000000000870B06 => BB42 valueOut= 00000000000000000000000000870B06 BB38 valueIn = 00000000000000000000000000870B06 valueOut = 00000000000000000000000000870B06 => BB40 valueOut= 00000000000000000000000000870B06 BB39 valueIn = 00000000000000000000000000870B06 valueOut = 00000000000000000000000001870B06 BB40 valueIn = 00000000000000000000000000870B06 valueOut = 00000000000000000000000000870B06 => BB64 valueOut= 00000000000000000000000000870B06 BB41 valueIn = 00000000000000000000000000870B06 valueOut = 00000000000000000000000000870B06 BB42 valueIn = 00000000000000000000000000870906 valueOut = 00000000000000000000000001870906 => BB68 valueOut= 00000000000000000000000001870906 BB43 valueIn = 00000000000000000000000001870906 valueOut = 00000000000000000000000001870906 BB44 valueIn = 00000000000000000000000000070806 valueOut = 00000000000000000000000004070806 => BB48 valueOut= 00000000000000000000000002070806 BB45 valueIn = 00000000000000000000000004070806 valueOut = 0000000000000000000000002C070806 => BB47 valueOut= 0000000000000000000000001C070806 BB46 valueIn = 0000000000000000000000002C070806 valueOut = 0000000000000000000000002C070806 BB47 valueIn = 0000000000000000000000000C070806 valueOut = 0000000000000000000000004C070806 BB48 valueIn = 00000000000000000000000002070806 valueOut = 00000000000000000000000002070806 => BB54 valueOut= 00000000000000000000000002070806 BB49 valueIn = 00000000000000000000000002070806 valueOut = 00000000000000000000000282070806 => BB51 valueOut= 00000000000000000000000182070806 BB50 valueIn = 00000000000000000000000282070806 valueOut = 00000000000000000000000282070806 BB51 valueIn = 00000000000000000000000082070806 valueOut = 00000000000000000000000882070806 => BB53 valueOut= 00000000000000000000000482070806 BB52 valueIn = 00000000000000000000000882070806 valueOut = 00000000000000000000000882070806 BB53 valueIn = 00000000000000000000000082070806 valueOut = 00000000000000000000001082070806 BB54 valueIn = 00000000000000000000000002070806 valueOut = 00000000000000000000000002070806 BB55 valueIn = 00000000000000000000000000070806 valueOut = 0000000000000000000003E000070806 => BB58 valueOut= 0000000000000000000003E000070806 BB56 valueIn = 0000000000000000000003E000070806 valueOut = 000000000000000000000BE000070806 => BB58 valueOut= 0000000000000000000007E000070806 BB57 valueIn = 000000000000000000000BE000070906 valueOut = 000000000000000000000BE000070806 BB58 valueIn = 00000000000000000000000000070806 valueOut = 00000000000000000000000000070806 BB59 valueIn = 00000000000000000000000000000001 valueOut = 00000000000000000000000000000001 BB60 valueIn = 000000000000000000000000001F0886 valueOut = 000000000000000000000000001F0886 => BB62 valueOut= 000000000000000000000000001F0886 BB61 valueIn = 000000000000000000000000001F0886 valueOut = 000000000000000000000000001F0886 BB62 valueIn = 000000000000000000000000001F0886 valueOut = 000000000000000000000000001F0886 BB63 valueIn = 000000000000000000000000001F0886 valueOut = 000000000000000000000000001F0886 BB64 valueIn = 00000000000000000000000000870B06 valueOut = 00000000000000000000000000870B06 => BB66 valueOut= 00000000000000000000000000870B06 BB65 valueIn = 00000000000000000000000000870B06 valueOut = 00000000000000000000000000870B06 BB66 valueIn = 00000000000000000000000000870B06 valueOut = 00000000000000000000000000870B06 BB67 valueIn = 00000000000000000000000000870B06 valueOut = 00000000000000000000000000870B06 BB68 valueIn = 00000000000000000000000000070806 valueOut = 00000000000000000000000000070806 Propagating 00000000000000000000000000000000 assertions for BB01, stmt STMT00000, tree [000000], tree -> 0 Propagating 00000000000000000000000000000000 assertions for BB01, stmt STMT00000, tree [000001], tree -> 0 Propagating 00000000000000000000000000000000 assertions for BB01, stmt STMT00000, tree [000002], tree -> 0 Propagating 00000000000000000000000000000000 assertions for BB01, stmt STMT00000, tree [000003], tree -> 1 Propagating 00000000000000000000000000000002 assertions for BB02, stmt STMT00001, tree [000004], tree -> 0 Propagating 00000000000000000000000000000002 assertions for BB02, stmt STMT00001, tree [000813], tree -> 0 Propagating 00000000000000000000000000000002 assertions for BB02, stmt STMT00001, tree [000814], tree -> 0 Propagating 00000000000000000000000000000002 assertions for BB02, stmt STMT00001, tree [000005], tree -> 3 Propagating 00000000000000000000000000000006 assertions for BB02, stmt STMT00001, tree [000006], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB02, stmt STMT00001, tree [000007], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB02, stmt STMT00001, tree [000008], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB03, stmt STMT00085, tree [000815], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB03, stmt STMT00085, tree [000816], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB03, stmt STMT00085, tree [000526], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB03, stmt STMT00085, tree [000527], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB03, stmt STMT00085, tree [000528], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00088, tree [000009], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00088, tree [000817], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00088, tree [000818], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00088, tree [000010], tree -> 3 VN based non-null prop in BB04: N004 ( 4, 4) [000010] ---XG------- * IND ref Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00088, tree [000011], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00088, tree [000012], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00088, tree [000543], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00088, tree [000544], tree -> 0 Re-morphing this stmt: STMT00088 (IL 0x01E... ???) N008 ( 9, 6) [000544] -A-XG---R--- * ASG bool N007 ( 1, 1) [000543] D------N---- +--* LCL_VAR int V33 tmp19 d:1 N006 ( 9, 6) [000012] N--XG------- \--* NE int N004 ( 4, 4) [000010] n---GO------ +--* IND ref N003 ( 2, 2) [000818] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000009] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000817] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] $240 N005 ( 1, 1) [000011] ------------ \--* CNS_INT ref null $VN.Null optAssertionPropMain morphed tree: N008 ( 9, 6) [000544] -A--GO--R--- * ASG bool N007 ( 1, 1) [000543] D------N---- +--* LCL_VAR int V33 tmp19 d:1 N006 ( 9, 6) [000012] N---GO------ \--* NE int N004 ( 4, 4) [000010] n---GO------ +--* IND ref N003 ( 2, 2) [000818] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000009] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000817] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] $240 N005 ( 1, 1) [000011] ------------ \--* CNS_INT ref null $VN.Null Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00091, tree [000537], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00091, tree [000538], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00091, tree [001290], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00091, tree [001291], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00091, tree [001292], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00091, tree [001293], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00091, tree [000553], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00091, tree [000554], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00092, tree [001294], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00092, tree [000555], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00092, tree [000556], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00089, tree [000546], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00089, tree [000547], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00089, tree [000548], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB04, stmt STMT00089, tree [000549], tree -> 4 Propagating 00000000000000000000000000000016 assertions for BB05, stmt STMT00090, tree [000819], tree -> 0 Propagating 00000000000000000000000000000016 assertions for BB05, stmt STMT00090, tree [000820], tree -> 0 Propagating 00000000000000000000000000000016 assertions for BB05, stmt STMT00090, tree [000550], tree -> 0 Propagating 00000000000000000000000000000016 assertions for BB05, stmt STMT00090, tree [000551], tree -> 0 Propagating 00000000000000000000000000000016 assertions for BB05, stmt STMT00090, tree [000552], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB06, stmt STMT00003, tree [000015], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB06, stmt STMT00003, tree [000821], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB06, stmt STMT00003, tree [000822], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB06, stmt STMT00003, tree [000016], tree -> 3 VN based non-null prop in BB06: N004 ( 4, 4) [000016] ---XG------- * IND ref Propagating 00000000000000000000000000000006 assertions for BB06, stmt STMT00003, tree [000017], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB06, stmt STMT00003, tree [000018], tree -> 0 Re-morphing this stmt: STMT00003 (IL 0x02C... ???) N006 ( 4, 4) [000018] -A-XG---R--- * ASG ref N005 ( 1, 1) [000017] D------N---- +--* LCL_VAR ref V04 loc0 d:1 N004 ( 4, 4) [000016] n---GO------ \--* IND ref N003 ( 2, 2) [000822] -------N---- \--* ADD byref $281 N001 ( 1, 1) [000015] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000821] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] $241 optAssertionPropMain morphed tree: N006 ( 4, 4) [000018] -A--GO--R--- * ASG ref N005 ( 1, 1) [000017] D------N---- +--* LCL_VAR ref V04 loc0 d:1 N004 ( 4, 4) [000016] n---GO------ \--* IND ref N003 ( 2, 2) [000822] -------N---- \--* ADD byref $281 N001 ( 1, 1) [000015] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000821] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] $241 Propagating 00000000000000000000000000000006 assertions for BB06, stmt STMT00094, tree [000019], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB06, stmt STMT00094, tree [000020], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB06, stmt STMT00094, tree [000021], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB06, stmt STMT00094, tree [000565], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB06, stmt STMT00094, tree [000566], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB06, stmt STMT00097, tree [001295], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB06, stmt STMT00097, tree [000575], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB06, stmt STMT00097, tree [000576], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB06, stmt STMT00095, tree [000568], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB06, stmt STMT00095, tree [000569], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB06, stmt STMT00095, tree [000570], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB06, stmt STMT00095, tree [000571], tree -> 6 Propagating 00000000000000000000000000000046 assertions for BB07, stmt STMT00096, tree [000825], tree -> 0 Propagating 00000000000000000000000000000046 assertions for BB07, stmt STMT00096, tree [000826], tree -> 0 Propagating 00000000000000000000000000000046 assertions for BB07, stmt STMT00096, tree [000823], tree -> 0 Propagating 00000000000000000000000000000046 assertions for BB07, stmt STMT00096, tree [000824], tree -> 0 Propagating 00000000000000000000000000000046 assertions for BB07, stmt STMT00096, tree [000573], tree -> 0 Propagating 00000000000000000000000000000046 assertions for BB07, stmt STMT00096, tree [000574], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB08, stmt STMT00005, tree [000025], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB08, stmt STMT00005, tree [000827], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB08, stmt STMT00005, tree [000828], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB08, stmt STMT00005, tree [000026], tree -> 3 VN based non-null prop in BB08: N004 ( 4, 4) [000026] ---XG------- * IND ref Propagating 00000000000000000000000000000006 assertions for BB08, stmt STMT00005, tree [000027], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB08, stmt STMT00005, tree [000028], tree -> 0 Re-morphing this stmt: STMT00005 (IL 0x041... ???) N006 ( 4, 4) [000028] -A-XG---R--- * ASG ref N005 ( 1, 1) [000027] D------N---- +--* LCL_VAR ref V05 loc1 d:1 N004 ( 4, 4) [000026] n---GO------ \--* IND ref N003 ( 2, 2) [000828] -------N---- \--* ADD byref $282 N001 ( 1, 1) [000025] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000827] ------------ \--* CNS_INT long 24 field offset Fseq[_comparer] $242 optAssertionPropMain morphed tree: N006 ( 4, 4) [000028] -A--GO--R--- * ASG ref N005 ( 1, 1) [000027] D------N---- +--* LCL_VAR ref V05 loc1 d:1 N004 ( 4, 4) [000026] n---GO------ \--* IND ref N003 ( 2, 2) [000828] -------N---- \--* ADD byref $282 N001 ( 1, 1) [000025] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000827] ------------ \--* CNS_INT long 24 field offset Fseq[_comparer] $242 Propagating 00000000000000000000000000000006 assertions for BB08, stmt STMT00006, tree [000029], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB08, stmt STMT00006, tree [000030], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB08, stmt STMT00006, tree [000031], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB08, stmt STMT00006, tree [000032], tree -> 8 Propagating 00000000000000000000000000000106 assertions for BB09, stmt STMT00079, tree [000486], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB09, stmt STMT00079, tree [000487], tree -> 3 VN based non-null prop in BB09: N002 ( 3, 2) [000487] #--X-------- * IND long $2e8 Propagating 00000000000000000000000000000106 assertions for BB09, stmt STMT00079, tree [000488], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB09, stmt STMT00079, tree [000489], tree -> 0 Re-morphing this stmt: STMT00079 (IL 0x04B...0x052) N004 ( 3, 3) [000489] -A-X----R--- * ASG long $2e8 N003 ( 1, 1) [000488] D------N---- +--* LCL_VAR long V29 tmp15 d:1 $2e7 N002 ( 3, 2) [000487] #----O------ \--* IND long $2e8 N001 ( 1, 1) [000486] !----------- \--* LCL_VAR ref V00 this u:1 $100 optAssertionPropMain morphed tree: N004 ( 3, 3) [000489] -A---O--R--- * ASG long $2e8 N003 ( 1, 1) [000488] D------N---- +--* LCL_VAR long V29 tmp15 d:1 $2e7 N002 ( 3, 2) [000487] #----O------ \--* IND long $2e8 N001 ( 1, 1) [000486] !----------- \--* LCL_VAR ref V00 this u:1 $100 Propagating 00000000000000000000000000000106 assertions for BB09, stmt STMT00149, tree [000491], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB09, stmt STMT00149, tree [000492], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB09, stmt STMT00149, tree [000493], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB09, stmt STMT00149, tree [000494], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB09, stmt STMT00149, tree [000495], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB09, stmt STMT00149, tree [000496], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB09, stmt STMT00149, tree [000497], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB09, stmt STMT00149, tree [000501], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB09, stmt STMT00149, tree [001265], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB09, stmt STMT00149, tree [001266], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB09, stmt STMT00149, tree [001267], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB09, stmt STMT00149, tree [001268], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB09, stmt STMT00149, tree [000504], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB09, stmt STMT00149, tree [000505], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB09, stmt STMT00149, tree [001148], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB10, stmt STMT00150, tree [001269], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB10, stmt STMT00150, tree [001149], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB10, stmt STMT00150, tree [001150], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB11, stmt STMT00151, tree [000829], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB11, stmt STMT00151, tree [000830], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB11, stmt STMT00151, tree [000490], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB11, stmt STMT00151, tree [000502], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB11, stmt STMT00151, tree [000503], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB11, stmt STMT00151, tree [001151], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB11, stmt STMT00151, tree [001152], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB12, stmt STMT00083, tree [000832], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB12, stmt STMT00083, tree [000833], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB12, stmt STMT00083, tree [000834], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB12, stmt STMT00083, tree [000484], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB12, stmt STMT00083, tree [000831], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB12, stmt STMT00083, tree [000500], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB12, stmt STMT00083, tree [000521], tree -> 0 Propagating 00000000000000000000000000000106 assertions for BB12, stmt STMT00083, tree [000522], tree -> 10 Propagating 00000000000000000000000000000306 assertions for BB12, stmt STMT00083, tree [000523], tree -> 0 Propagating 00000000000000000000000000000306 assertions for BB12, stmt STMT00083, tree [000524], tree -> 0 Propagating 00000000000000000000000000000086 assertions for BB13, stmt STMT00007, tree [000835], tree -> 0 Propagating 00000000000000000000000000000086 assertions for BB13, stmt STMT00007, tree [000033], tree -> 0 Propagating 00000000000000000000000000000086 assertions for BB13, stmt STMT00007, tree [000836], tree -> 0 Propagating 00000000000000000000000000000086 assertions for BB13, stmt STMT00007, tree [000837], tree -> 11 VN based non-null prop in BB13: N004 ( 3, 2) [000837] #--X-------- * IND long $2e4 Propagating 00000000000000000000000000000486 assertions for BB13, stmt STMT00007, tree [000838], tree -> 0 Propagating 00000000000000000000000000000486 assertions for BB13, stmt STMT00007, tree [000839], tree -> 0 Propagating 00000000000000000000000000000486 assertions for BB13, stmt STMT00007, tree [000840], tree -> 0 Propagating 00000000000000000000000000000486 assertions for BB13, stmt STMT00007, tree [000841], tree -> 0 Propagating 00000000000000000000000000000486 assertions for BB13, stmt STMT00007, tree [000842], tree -> 0 Propagating 00000000000000000000000000000486 assertions for BB13, stmt STMT00007, tree [000843], tree -> 0 Propagating 00000000000000000000000000000486 assertions for BB13, stmt STMT00007, tree [000035], tree -> 11 Propagating 00000000000000000000000000000486 assertions for BB13, stmt STMT00007, tree [000037], tree -> 0 Propagating 00000000000000000000000000000486 assertions for BB13, stmt STMT00007, tree [000038], tree -> 0 Re-morphing this stmt: STMT00007 (IL 0x054...0x05C) N013 ( 34, 21) [000038] -ACXG---R--- * ASG int $1c5 N012 ( 3, 2) [000037] D------N---- +--* LCL_VAR int V15 tmp1 d:2 $1c5 N011 ( 30, 18) [000035] --CXG------- \--* CALLV vt-ind int System.Object.GetHashCode $1c5 N010 ( 9, 8) [000843] n--X-------- control expr \--* IND long N009 ( 7, 6) [000842] ---X---N---- \--* ADD long $303 N007 ( 6, 5) [000840] #--X-------- +--* IND long $2e6 N006 ( 4, 3) [000839] ---X---N---- | \--* ADD long $301 N004 ( 3, 2) [000837] #----O------ | +--* IND long $2e4 N003 ( 1, 1) [000836] ------------ | | \--* LCL_VAR ref V01 arg1 u:1 $101 N005 ( 1, 1) [000838] ------------ | \--* CNS_INT int 72 $c9 N008 ( 1, 1) [000841] ------------ \--* CNS_INT int 24 $ca N002 ( 1, 1) [000033] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 $101 ReMorphing args for 35.CALL: argSlots=1, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 ArgTable for 35.CALL after fgMorphArgs: fgArgTabEntry[arg 0 33.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=0, processed] optAssertionPropMain morphed tree: N013 ( 34, 21) [000038] -ACXGO--R--- * ASG int $1c5 N012 ( 3, 2) [000037] D------N---- +--* LCL_VAR int V15 tmp1 d:2 $1c5 N011 ( 30, 18) [000035] --CXGO------ \--* CALLV vt-ind int System.Object.GetHashCode $1c5 N010 ( 9, 8) [000843] n----O------ control expr \--* IND long N009 ( 7, 6) [000842] -----O-N---- \--* ADD long $303 N007 ( 6, 5) [000840] #----O------ +--* IND long $2e6 N006 ( 4, 3) [000839] -----O-N---- | \--* ADD long $301 N004 ( 3, 2) [000837] #----O------ | +--* IND long $2e4 N003 ( 1, 1) [000836] ------------ | | \--* LCL_VAR ref V01 arg1 u:1 $101 N005 ( 1, 1) [000838] ------------ | \--* CNS_INT int 72 $c9 N008 ( 1, 1) [000841] ------------ \--* CNS_INT int 24 $ca N002 ( 1, 1) [000033] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 $101 Propagating 00000000000000000000000000000006 assertions for BB14, stmt STMT00008, tree [000040], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB14, stmt STMT00008, tree [000041], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB14, stmt STMT00008, tree [000042], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB14, stmt STMT00009, tree [000043], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB14, stmt STMT00009, tree [000044], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB14, stmt STMT00009, tree [000045], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB14, stmt STMT00098, tree [000046], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB14, stmt STMT00098, tree [000844], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB14, stmt STMT00098, tree [000845], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB14, stmt STMT00098, tree [000578], tree -> 3 VN based non-null prop in BB14: N004 ( 4, 4) [000578] ---XG------- * IND ref Propagating 00000000000000000000000000000006 assertions for BB14, stmt STMT00098, tree [000579], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB14, stmt STMT00098, tree [000580], tree -> 0 Re-morphing this stmt: STMT00098 (IL 0x064... ???) N006 ( 4, 4) [000580] -A-XG---R--- * ASG ref N005 ( 1, 1) [000579] D------N---- +--* LCL_VAR ref V39 tmp25 d:1 N004 ( 4, 4) [000578] n---GO------ \--* IND ref N003 ( 2, 2) [000845] -------N---- \--* ADD byref $280 N001 ( 1, 1) [000046] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000844] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] $240 optAssertionPropMain morphed tree: N006 ( 4, 4) [000580] -A--GO--R--- * ASG ref N005 ( 1, 1) [000579] D------N---- +--* LCL_VAR ref V39 tmp25 d:1 N004 ( 4, 4) [000578] n---GO------ \--* IND ref N003 ( 2, 2) [000845] -------N---- \--* ADD byref $280 N001 ( 1, 1) [000046] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000844] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] $240 Propagating 00000000000000000000000000000006 assertions for BB14, stmt STMT00105, tree [000582], tree -> 0 Propagating 00000000000000000000000000000006 assertions for BB14, stmt STMT00105, tree [000583], tree -> 12 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00105, tree [000628], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00105, tree [000629], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00106, tree [000584], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00106, tree [000846], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00106, tree [000847], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00106, tree [000585], tree -> 3 VN based non-null prop in BB14: N004 ( 4, 4) [000585] ---XG------- * IND long Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00106, tree [000630], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00106, tree [000631], tree -> 0 Re-morphing this stmt: STMT00106 (IL 0x064... ???) N006 ( 4, 4) [000631] -A-XG---R--- * ASG long N005 ( 1, 1) [000630] D------N---- +--* LCL_VAR long V41 tmp27 d:1 N004 ( 4, 4) [000585] n---GO------ \--* IND long N003 ( 2, 2) [000847] -------N---- \--* ADD byref $283 N001 ( 1, 1) [000584] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000846] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 optAssertionPropMain morphed tree: N006 ( 4, 4) [000631] -A--GO--R--- * ASG long N005 ( 1, 1) [000630] D------N---- +--* LCL_VAR long V41 tmp27 d:1 N004 ( 4, 4) [000585] n---GO------ \--* IND long N003 ( 2, 2) [000847] -------N---- \--* ADD byref $283 N001 ( 1, 1) [000584] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000846] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00108, tree [000597], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00108, tree [000598], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00108, tree [000599], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00108, tree [000641], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00108, tree [000642], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00111, tree [001296], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00111, tree [000651], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00111, tree [000652], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00112, tree [001297], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00112, tree [000653], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00112, tree [000654], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00109, tree [000644], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00109, tree [000645], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00109, tree [000646], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB14, stmt STMT00109, tree [000647], tree -> 13 Propagating 00000000000000000000000000002806 assertions for BB15, stmt STMT00110, tree [000848], tree -> 0 Propagating 00000000000000000000000000002806 assertions for BB15, stmt STMT00110, tree [000849], tree -> 0 Propagating 00000000000000000000000000002806 assertions for BB15, stmt STMT00110, tree [000648], tree -> 0 Propagating 00000000000000000000000000002806 assertions for BB15, stmt STMT00110, tree [000649], tree -> 0 Propagating 00000000000000000000000000002806 assertions for BB15, stmt STMT00110, tree [000650], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00103, tree [000604], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00103, tree [000047], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00103, tree [000605], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00103, tree [000606], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00103, tree [000607], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00103, tree [000608], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00103, tree [000610], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00103, tree [000611], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00103, tree [000612], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00103, tree [000613], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00103, tree [000614], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00103, tree [000615], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00103, tree [000616], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00103, tree [000617], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00103, tree [000618], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00103, tree [000619], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00114, tree [000621], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00114, tree [000622], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00114, tree [000623], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00114, tree [000620], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00114, tree [000624], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00114, tree [000664], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00114, tree [000665], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00117, tree [001298], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00117, tree [000674], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00117, tree [000675], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00118, tree [001299], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00118, tree [000676], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00118, tree [000677], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00115, tree [000667], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00115, tree [000668], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00115, tree [000669], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB16, stmt STMT00115, tree [000670], tree -> 15 Propagating 00000000000000000000000000008806 assertions for BB17, stmt STMT00116, tree [000850], tree -> 0 Propagating 00000000000000000000000000008806 assertions for BB17, stmt STMT00116, tree [000851], tree -> 0 Propagating 00000000000000000000000000008806 assertions for BB17, stmt STMT00116, tree [000671], tree -> 0 Propagating 00000000000000000000000000008806 assertions for BB17, stmt STMT00116, tree [000672], tree -> 0 Propagating 00000000000000000000000000008806 assertions for BB17, stmt STMT00116, tree [000673], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB18, stmt STMT00100, tree [000627], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB18, stmt STMT00100, tree [000581], tree -> 0 Propagating 00000000000000000000000000000806 assertions for BB18, stmt STMT00100, tree [000854], tree -> 12 Propagating 00000000000000000000000000000806 assertions for BB18, stmt STMT00100, tree [000855], tree -> 17 Propagating 00000000000000000000000000010806 assertions for BB18, stmt STMT00100, tree [000852], tree -> 0 Propagating 00000000000000000000000000010806 assertions for BB18, stmt STMT00100, tree [000853], tree -> 0 Propagating 00000000000000000000000000010806 assertions for BB18, stmt STMT00100, tree [000856], tree -> 0 Propagating 00000000000000000000000000010806 assertions for BB18, stmt STMT00100, tree [000857], tree -> 0 Propagating 00000000000000000000000000010806 assertions for BB18, stmt STMT00100, tree [000858], tree -> 0 Propagating 00000000000000000000000000010806 assertions for BB18, stmt STMT00100, tree [000859], tree -> 0 Propagating 00000000000000000000000000010806 assertions for BB18, stmt STMT00100, tree [000860], tree -> 0 Propagating 00000000000000000000000000010806 assertions for BB18, stmt STMT00100, tree [000861], tree -> 0 Propagating 00000000000000000000000000010806 assertions for BB18, stmt STMT00100, tree [000588], tree -> 0 Propagating 00000000000000000000000000010806 assertions for BB18, stmt STMT00100, tree [000863], tree -> 0 Propagating 00000000000000000000000000010806 assertions for BB18, stmt STMT00100, tree [000862], tree -> 0 Propagating 00000000000000000000000000010806 assertions for BB18, stmt STMT00100, tree [000590], tree -> 0 Propagating 00000000000000000000000000010806 assertions for BB18, stmt STMT00100, tree [000591], tree -> 0 Propagating 00000000000000000000000000010806 assertions for BB18, stmt STMT00011, tree [000592], tree -> 0 Propagating 00000000000000000000000000010806 assertions for BB18, stmt STMT00011, tree [000050], tree -> 0 Propagating 00000000000000000000000000010806 assertions for BB18, stmt STMT00011, tree [000051], tree -> 0 Propagating 00000000000000000000000000010806 assertions for BB18, stmt STMT00012, tree [000052], tree -> 0 Propagating 00000000000000000000000000010806 assertions for BB18, stmt STMT00012, tree [000053], tree -> 18 Propagating 00000000000000000000000000030806 assertions for BB18, stmt STMT00012, tree [000054], tree -> 0 Propagating 00000000000000000000000000030806 assertions for BB18, stmt STMT00012, tree [000055], tree -> 0 Propagating 00000000000000000000000000030806 assertions for BB18, stmt STMT00012, tree [000056], tree -> 0 Propagating 00000000000000000000000000030806 assertions for BB18, stmt STMT00012, tree [000057], tree -> 0 Propagating 00000000000000000000000000030806 assertions for BB18, stmt STMT00013, tree [000058], tree -> 0 Propagating 00000000000000000000000000030806 assertions for BB18, stmt STMT00013, tree [000059], tree -> 0 Propagating 00000000000000000000000000030806 assertions for BB18, stmt STMT00013, tree [000060], tree -> 0 Propagating 00000000000000000000000000030806 assertions for BB18, stmt STMT00013, tree [000061], tree -> 9 Propagating 00000000000000000000000000030886 assertions for BB19, stmt STMT00059, tree [000353], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB19, stmt STMT00059, tree [000354], tree -> 3 VN based non-null prop in BB19: N002 ( 3, 2) [000354] #--X-------- * IND long $2e8 Propagating 00000000000000000000000000030886 assertions for BB19, stmt STMT00059, tree [000355], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB19, stmt STMT00059, tree [000356], tree -> 0 Re-morphing this stmt: STMT00059 (IL 0x0FF...0x104) N004 ( 3, 3) [000356] -A-X----R--- * ASG long $2e8 N003 ( 1, 1) [000355] D------N---- +--* LCL_VAR long V24 tmp10 d:1 $2e7 N002 ( 3, 2) [000354] #----O------ \--* IND long $2e8 N001 ( 1, 1) [000353] !----------- \--* LCL_VAR ref V00 this u:1 $100 optAssertionPropMain morphed tree: N004 ( 3, 3) [000356] -A---O--R--- * ASG long $2e8 N003 ( 1, 1) [000355] D------N---- +--* LCL_VAR long V24 tmp10 d:1 $2e7 N002 ( 3, 2) [000354] #----O------ \--* IND long $2e8 N001 ( 1, 1) [000353] !----------- \--* LCL_VAR ref V00 this u:1 $100 Propagating 00000000000000000000000000030886 assertions for BB19, stmt STMT00152, tree [000358], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB19, stmt STMT00152, tree [000359], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB19, stmt STMT00152, tree [000360], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB19, stmt STMT00152, tree [000361], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB19, stmt STMT00152, tree [000362], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB19, stmt STMT00152, tree [000363], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB19, stmt STMT00152, tree [000364], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB19, stmt STMT00152, tree [000365], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB19, stmt STMT00152, tree [001270], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB19, stmt STMT00152, tree [001271], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB19, stmt STMT00152, tree [001272], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB19, stmt STMT00152, tree [001273], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB19, stmt STMT00152, tree [000368], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB19, stmt STMT00152, tree [000369], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB19, stmt STMT00152, tree [001153], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB20, stmt STMT00153, tree [001274], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB20, stmt STMT00153, tree [001154], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB20, stmt STMT00153, tree [001155], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB21, stmt STMT00154, tree [000864], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB21, stmt STMT00154, tree [000865], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB21, stmt STMT00154, tree [000357], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB21, stmt STMT00154, tree [000366], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB21, stmt STMT00154, tree [000367], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB21, stmt STMT00154, tree [001156], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB21, stmt STMT00154, tree [001157], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB22, stmt STMT00062, tree [000866], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB22, stmt STMT00062, tree [000382], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB22, stmt STMT00062, tree [000352], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB22, stmt STMT00062, tree [000385], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB22, stmt STMT00062, tree [000386], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB23, stmt STMT00063, tree [000388], tree -> 0 Propagating 00000000000000000000000000030886 assertions for BB23, stmt STMT00063, tree [000389], tree -> 19 Propagating 00000000000000000000000000070886 assertions for BB23, stmt STMT00063, tree [001315], tree -> 0 Propagating 00000000000000000000000000070886 assertions for BB23, stmt STMT00063, tree [001316], tree -> 0 Propagating 00000000000000000000000000070886 assertions for BB23, stmt STMT00063, tree [001317], tree -> 0 Propagating 00000000000000000000000000070886 assertions for BB23, stmt STMT00063, tree [001318], tree -> 0 Propagating 00000000000000000000000000070886 assertions for BB23, stmt STMT00063, tree [000387], tree -> 0 Propagating 00000000000000000000000000070886 assertions for BB23, stmt STMT00063, tree [000390], tree -> 0 Propagating 00000000000000000000000000070886 assertions for BB23, stmt STMT00063, tree [000391], tree -> 20 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [000393], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [001319], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [000872], tree -> 20 VN based redundant (a[i] followed by a[i]) bounds check assertion prop for index #20 in BB24: N003 ( 6, 9) [000872] ---X-------- * ARR_BOUNDS_CHECK_Rng void Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [000869], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [000870], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [000873], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [000880], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [000881], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [001275], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [001276], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [001277], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [001278], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [000874], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [000875], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [000876], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [000877], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [000878], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [000394], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [000882], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [000879], tree -> 0 Before optRemoveRangeCheck: N020 ( 29, 32) [000879] -A-XG------- * COMMA byref N003 ( 6, 9) [000872] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000393] ------------ | +--* LCL_VAR int V09 loc5 u:4 $3c2 N002 ( 1, 1) [001319] ------------ | \--* LCL_VAR int V76 cse11 N019 ( 23, 23) [000882] -A--G------- \--* ADDR byref $82 N018 ( 12, 12) [000394] aA--G--N---- \--* IND struct N017 ( 11, 11) [000878] -A-----N---- \--* ADD byref $82 N004 ( 1, 1) [000869] ------------ +--* LCL_VAR ref V04 loc0 u:1 N016 ( 10, 10) [000877] -A-----N---- \--* ADD long $329 N014 ( 9, 9) [000875] -A-----N---- +--* LSH long $328 N012 ( 8, 8) [001278] -A---------- | +--* COMMA long $327 N010 ( 7, 7) [001276] -A------R--- | | +--* ASG long $VN.Void N009 ( 1, 1) [001275] D------N---- | | | +--* LCL_VAR long V70 cse5 d:1 $327 N008 ( 7, 7) [000881] ------------ | | | \--* MUL long $327 N006 ( 2, 3) [000873] ------------ | | | +--* CAST long <- int $326 N005 ( 1, 1) [000870] i----------- | | | | \--* LCL_VAR int V09 loc5 u:4 $3c2 N007 ( 1, 1) [000880] ------------ | | | \--* CNS_INT long 3 $24b N011 ( 1, 1) [001277] ------------ | | \--* LCL_VAR long V70 cse5 u:1 $327 N013 ( 1, 1) [000874] -------N---- | \--* CNS_INT long 3 $24b N015 ( 1, 1) [000876] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 After optRemoveRangeCheck: N018 ( 23, 23) [000879] -A--G--N---- * COMMA byref N001 ( 0, 0) [000872] ------------ +--* NOP void N017 ( 23, 23) [000882] -A--G------- \--* ADDR byref $82 N016 ( 12, 12) [000394] aA--G--N---- \--* IND struct N015 ( 11, 11) [000878] -A-----N---- \--* ADD byref $82 N002 ( 1, 1) [000869] ------------ +--* LCL_VAR ref V04 loc0 u:1 N014 ( 10, 10) [000877] -A-----N---- \--* ADD long $329 N012 ( 9, 9) [000875] -A-----N---- +--* LSH long $328 N010 ( 8, 8) [001278] -A---------- | +--* COMMA long $327 N008 ( 7, 7) [001276] -A------R--- | | +--* ASG long $VN.Void N007 ( 1, 1) [001275] D------N---- | | | +--* LCL_VAR long V70 cse5 d:1 $327 N006 ( 7, 7) [000881] ------------ | | | \--* MUL long $327 N004 ( 2, 3) [000873] ------------ | | | +--* CAST long <- int $326 N003 ( 1, 1) [000870] i----------- | | | | \--* LCL_VAR int V09 loc5 u:4 $3c2 N005 ( 1, 1) [000880] ------------ | | | \--* CNS_INT long 3 $24b N009 ( 1, 1) [001277] ------------ | | \--* LCL_VAR long V70 cse5 u:1 $327 N011 ( 1, 1) [000874] -------N---- | \--* CNS_INT long 3 $24b N013 ( 1, 1) [000876] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [001248], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [001249], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [001250], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [001251], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [000867], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [000868], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [000396], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [000397], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [000398], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB24, stmt STMT00064, tree [000399], tree -> 0 Re-morphing this stmt: STMT00064 (IL 0x110...0x11E) N028 ( 31, 31) [000399] -A-XG------- * JTRUE void N027 ( 29, 29) [000398] NA-XG--N-U-- \--* NE int N025 ( 27, 27) [000396] *A-XG------- +--* IND int N024 ( 25, 25) [000868] -A--G--N---- | \--* ADD byref $28c N022 ( 24, 24) [001251] -A--G------- | +--* COMMA byref N020 ( 23, 23) [001249] -A--G---R--- | | +--* ASG byref $VN.Void N019 ( 1, 1) [001248] D------N---- | | | +--* LCL_VAR byref V65 cse0 d:1 N018 ( 23, 23) [000879] -A--G--N---- | | | \--* COMMA byref N001 ( 0, 0) [000872] ------------ | | | +--* NOP void N017 ( 23, 23) [000882] -A--G------- | | | \--* ADDR byref $82 N016 ( 12, 12) [000394] aA--G--N---- | | | \--* IND struct N015 ( 11, 11) [000878] -A-----N---- | | | \--* ADD byref $82 N002 ( 1, 1) [000869] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N014 ( 10, 10) [000877] -A-----N---- | | | \--* ADD long $329 N012 ( 9, 9) [000875] -A-----N---- | | | +--* LSH long $328 N010 ( 8, 8) [001278] -A---------- | | | | +--* COMMA long $327 N008 ( 7, 7) [001276] -A------R--- | | | | | +--* ASG long $VN.Void N007 ( 1, 1) [001275] D------N---- | | | | | | +--* LCL_VAR long V70 cse5 d:1 $327 N006 ( 7, 7) [000881] ------------ | | | | | | \--* MUL long $327 N004 ( 2, 3) [000873] ------------ | | | | | | +--* CAST long <- int $326 N003 ( 1, 1) [000870] i----------- | | | | | | | \--* LCL_VAR int V09 loc5 u:4 $3c2 N005 ( 1, 1) [000880] ------------ | | | | | | \--* CNS_INT long 3 $24b N009 ( 1, 1) [001277] ------------ | | | | | \--* LCL_VAR long V70 cse5 u:1 $327 N011 ( 1, 1) [000874] -------N---- | | | | \--* CNS_INT long 3 $24b N013 ( 1, 1) [000876] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N021 ( 1, 1) [001250] ------------ | | \--* LCL_VAR byref V65 cse0 u:1 N023 ( 1, 1) [000867] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N026 ( 1, 1) [000397] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 optAssertionPropMain morphed tree: N026 ( 31, 31) [000399] -A-XG------- * JTRUE void N025 ( 29, 29) [000398] NA-XG--N-U-- \--* NE int N023 ( 27, 27) [000396] *A-XG------- +--* IND int N022 ( 25, 25) [000868] -A--G--N---- | \--* ADD byref $28c N020 ( 24, 24) [001251] -A--G------- | +--* COMMA byref N018 ( 23, 23) [001249] -A--G---R--- | | +--* ASG byref $VN.Void N017 ( 1, 1) [001248] D------N---- | | | +--* LCL_VAR byref V65 cse0 d:1 N016 ( 23, 23) [000882] -A--G--N---- | | | \--* ADDR byref $82 N015 ( 12, 12) [000394] aA--G--N---- | | | \--* IND struct N014 ( 11, 11) [000878] -A-----N---- | | | \--* ADD byref $82 N001 ( 1, 1) [000869] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 10, 10) [000877] -A-----N---- | | | \--* ADD long $329 N011 ( 9, 9) [000875] -A-----N---- | | | +--* LSH long $328 N009 ( 8, 8) [001278] -A---------- | | | | +--* COMMA long $327 N007 ( 7, 7) [001276] -A------R--- | | | | | +--* ASG long $VN.Void N006 ( 1, 1) [001275] D------N---- | | | | | | +--* LCL_VAR long V70 cse5 d:1 $327 N005 ( 7, 7) [000881] ------------ | | | | | | \--* MUL long $327 N003 ( 2, 3) [000873] ------------ | | | | | | +--* CAST long <- int $326 N002 ( 1, 1) [000870] i----------- | | | | | | | \--* LCL_VAR int V09 loc5 u:4 $3c2 N004 ( 1, 1) [000880] ------------ | | | | | | \--* CNS_INT long 3 $24b N008 ( 1, 1) [001277] ------------ | | | | | \--* LCL_VAR long V70 cse5 u:1 $327 N010 ( 1, 1) [000874] -------N---- | | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000876] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N019 ( 1, 1) [001250] ------------ | | \--* LCL_VAR byref V65 cse0 u:1 N021 ( 1, 1) [000867] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N024 ( 1, 1) [000397] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 Propagating 000000000000000000000000000F0886 assertions for BB25, stmt STMT00069, tree [000899], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB25, stmt STMT00069, tree [000898], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB25, stmt STMT00069, tree [000900], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB25, stmt STMT00069, tree [000420], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB25, stmt STMT00069, tree [001320], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB25, stmt STMT00069, tree [000886], tree -> 20 VN based redundant (a[i] followed by a[i]) bounds check assertion prop for index #20 in BB25: N006 ( 6, 9) [000886] ---X-------- * ARR_BOUNDS_CHECK_Rng void Propagating 000000000000000000000000000F0886 assertions for BB25, stmt STMT00069, tree [000883], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB25, stmt STMT00069, tree [001279], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB25, stmt STMT00069, tree [000888], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB25, stmt STMT00069, tree [000889], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB25, stmt STMT00069, tree [000890], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB25, stmt STMT00069, tree [000891], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB25, stmt STMT00069, tree [000892], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB25, stmt STMT00069, tree [000421], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB25, stmt STMT00069, tree [000896], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB25, stmt STMT00069, tree [000897], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB25, stmt STMT00069, tree [000893], tree -> 0 Before optRemoveRangeCheck: N017 ( 18, 20) [000893] ---XG------- * COMMA ref N006 ( 6, 9) [000886] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N004 ( 1, 1) [000420] ------------ | +--* LCL_VAR int V09 loc5 u:4 $3c2 N005 ( 1, 1) [001320] ------------ | \--* LCL_VAR int V76 cse11 N016 ( 12, 11) [000897] *---G------- \--* IND ref N015 ( 9, 9) [000896] ----G------- \--* ADDR byref Zero Fseq[key] $84 N014 ( 5, 5) [000421] a---G--N---- \--* IND struct N013 ( 4, 4) [000892] -------N---- \--* ADD byref $82 N007 ( 1, 1) [000883] ------------ +--* LCL_VAR ref V04 loc0 u:1 N012 ( 3, 3) [000891] -------N---- \--* ADD long $329 N010 ( 2, 2) [000889] -------N---- +--* LSH long $328 N008 ( 1, 1) [001279] ------------ | +--* LCL_VAR long V70 cse5 u:1 $327 N009 ( 1, 1) [000888] -------N---- | \--* CNS_INT long 3 $24b N011 ( 1, 1) [000890] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 After optRemoveRangeCheck: N015 ( 12, 11) [000893] ----G--N---- * COMMA ref N004 ( 0, 0) [000886] ------------ +--* NOP void N014 ( 12, 11) [000897] *---G------- \--* IND ref N013 ( 9, 9) [000896] ----G------- \--* ADDR byref Zero Fseq[key] $84 N012 ( 5, 5) [000421] a---G--N---- \--* IND struct N011 ( 4, 4) [000892] -------N---- \--* ADD byref $82 N005 ( 1, 1) [000883] ------------ +--* LCL_VAR ref V04 loc0 u:1 N010 ( 3, 3) [000891] -------N---- \--* ADD long $329 N008 ( 2, 2) [000889] -------N---- +--* LSH long $328 N006 ( 1, 1) [001279] ------------ | +--* LCL_VAR long V70 cse5 u:1 $327 N007 ( 1, 1) [000888] -------N---- | \--* CNS_INT long 3 $24b N009 ( 1, 1) [000890] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 Propagating 000000000000000000000000000F0886 assertions for BB25, stmt STMT00069, tree [000418], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB25, stmt STMT00069, tree [000424], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB25, stmt STMT00069, tree [000901], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB25, stmt STMT00069, tree [000902], tree -> 21 Propagating 000000000000000000000000001F0886 assertions for BB25, stmt STMT00069, tree [000903], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB25, stmt STMT00069, tree [000904], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB25, stmt STMT00069, tree [000905], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB25, stmt STMT00069, tree [000906], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB25, stmt STMT00069, tree [000907], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB25, stmt STMT00069, tree [000908], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB25, stmt STMT00069, tree [000425], tree -> 21 Propagating 000000000000000000000000001F0886 assertions for BB25, stmt STMT00069, tree [000426], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB25, stmt STMT00069, tree [000427], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB25, stmt STMT00069, tree [000428], tree -> 0 Re-morphing this stmt: STMT00069 (IL 0x120...0x135) N029 ( 47, 36) [000428] --CXG------- * JTRUE void N028 ( 45, 34) [000427] J-CXG--N---- \--* NE int $1bd N026 ( 43, 32) [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals $581 N025 ( 9, 8) [000908] n--X-------- control expr | \--* IND long N024 ( 7, 6) [000907] ---X---N---- | \--* ADD long $32e N022 ( 6, 5) [000905] #--X-------- | +--* IND long $465 N021 ( 4, 3) [000904] ---X---N---- | | \--* ADD long $32c N019 ( 3, 2) [000902] #--X-------- | | +--* IND long $463 N018 ( 1, 1) [000901] ------------ | | | \--* LCL_VAR ref V12 loc8 u:1 $223 N020 ( 1, 1) [000903] ------------ | | \--* CNS_INT int 72 $c9 N023 ( 1, 1) [000906] ------------ | \--* CNS_INT int 32 $d2 N015 ( 12, 11) [000893] ----G--N---- arg1 in rdx | +--* COMMA ref N004 ( 0, 0) [000886] ------------ | | +--* NOP void N014 ( 12, 11) [000897] *---G------- | | \--* IND ref N013 ( 9, 9) [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] $84 N012 ( 5, 5) [000421] a---G--N---- | | \--* IND struct N011 ( 4, 4) [000892] -------N---- | | \--* ADD byref $82 N005 ( 1, 1) [000883] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N010 ( 3, 3) [000891] -------N---- | | \--* ADD long $329 N008 ( 2, 2) [000889] -------N---- | | +--* LSH long $328 N006 ( 1, 1) [001279] ------------ | | | +--* LCL_VAR long V70 cse5 u:1 $327 N007 ( 1, 1) [000888] -------N---- | | | \--* CNS_INT long 3 $24b N009 ( 1, 1) [000890] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N016 ( 1, 1) [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 u:1 $223 N017 ( 1, 1) [000424] ------------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 u:1 $101 N027 ( 1, 1) [000426] ------------ \--* CNS_INT int 0 $c0 ReMorphing args for 425.CALL: argSlots=3, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 ArgTable for 425.CALL after fgMorphArgs: fgArgTabEntry[arg 1 897.IND ref (By ref), 1 reg: rdx, byteAlignment=8, lateArgInx=0, processed] fgArgTabEntry[arg 0 418.LCL_VAR ref (By ref), 1 reg: rcx, byteAlignment=8, lateArgInx=1, processed] fgArgTabEntry[arg 2 424.LCL_VAR ref (By ref), 1 reg: r8, byteAlignment=8, lateArgInx=2, processed] optAssertionPropMain morphed tree: N027 ( 47, 36) [000428] --CXG------- * JTRUE void N026 ( 45, 34) [000427] J-CXG--N---- \--* NE int $1bd N024 ( 43, 32) [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals $581 N023 ( 9, 8) [000908] n--X-------- control expr | \--* IND long N022 ( 7, 6) [000907] ---X---N---- | \--* ADD long $32e N020 ( 6, 5) [000905] #--X-------- | +--* IND long $465 N019 ( 4, 3) [000904] ---X---N---- | | \--* ADD long $32c N017 ( 3, 2) [000902] #--X-------- | | +--* IND long $463 N016 ( 1, 1) [000901] ------------ | | | \--* LCL_VAR ref V12 loc8 u:1 $223 N018 ( 1, 1) [000903] ------------ | | \--* CNS_INT int 72 $c9 N021 ( 1, 1) [000906] ------------ | \--* CNS_INT int 32 $d2 N013 ( 12, 11) [000897] *---G--N---- arg1 in rdx | +--* IND ref N012 ( 9, 9) [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] $84 N011 ( 5, 5) [000421] a---G--N---- | | \--* IND struct N010 ( 4, 4) [000892] -------N---- | | \--* ADD byref $82 N004 ( 1, 1) [000883] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N009 ( 3, 3) [000891] -------N---- | | \--* ADD long $329 N007 ( 2, 2) [000889] -------N---- | | +--* LSH long $328 N005 ( 1, 1) [001279] ------------ | | | +--* LCL_VAR long V70 cse5 u:1 $327 N006 ( 1, 1) [000888] -------N---- | | | \--* CNS_INT long 3 $24b N008 ( 1, 1) [000890] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N014 ( 1, 1) [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 u:1 $223 N015 ( 1, 1) [000424] ------------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 u:1 $101 N025 ( 1, 1) [000426] ------------ \--* CNS_INT int 0 $c0 Propagating 000000000000000000000000000F0886 assertions for BB26, stmt STMT00065, tree [001252], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB26, stmt STMT00065, tree [000931], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB26, stmt STMT00065, tree [000932], tree -> 0 Propagating 000000000000000000000000000F0886 assertions for BB26, stmt STMT00065, tree [000404], tree -> 22 Propagating 000000000000000000000000002F0886 assertions for BB26, stmt STMT00065, tree [000405], tree -> 0 Propagating 000000000000000000000000002F0886 assertions for BB26, stmt STMT00065, tree [000406], tree -> 0 Propagating 000000000000000000000000002F0886 assertions for BB26, stmt STMT00066, tree [000407], tree -> 0 Propagating 000000000000000000000000002F0886 assertions for BB26, stmt STMT00066, tree [000408], tree -> 0 Propagating 000000000000000000000000002F0886 assertions for BB26, stmt STMT00066, tree [000409], tree -> 0 Propagating 000000000000000000000000002F0886 assertions for BB26, stmt STMT00066, tree [000410], tree -> 0 Propagating 000000000000000000000000002F0886 assertions for BB26, stmt STMT00066, tree [000411], tree -> 0 Propagating 000000000000000000000000002F0886 assertions for BB26, stmt STMT00067, tree [001321], tree -> 0 Propagating 000000000000000000000000002F0886 assertions for BB26, stmt STMT00067, tree [000412], tree -> 0 Propagating 000000000000000000000000002F0886 assertions for BB26, stmt STMT00067, tree [000415], tree -> 0 Propagating 000000000000000000000000002F0886 assertions for BB26, stmt STMT00067, tree [000416], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB28, stmt STMT00070, tree [000429], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB28, stmt STMT00070, tree [000909], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB28, stmt STMT00070, tree [000430], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB28, stmt STMT00070, tree [000431], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB28, stmt STMT00070, tree [000432], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB29, stmt STMT00077, tree [001253], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB29, stmt STMT00077, tree [000910], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB29, stmt STMT00077, tree [000911], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB29, stmt STMT00077, tree [000480], tree -> 22 Propagating 000000000000000000000000003F0886 assertions for BB29, stmt STMT00077, tree [000479], tree -> 0 Propagating 000000000000000000000000003F0886 assertions for BB29, stmt STMT00077, tree [000481], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB30, stmt STMT00071, tree [000433], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB30, stmt STMT00071, tree [000926], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB30, stmt STMT00071, tree [000434], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB30, stmt STMT00071, tree [000435], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB30, stmt STMT00071, tree [000436], tree -> 0 Propagating 00000000000000000000000000070806 assertions for BB31, stmt STMT00148, tree [000437], tree -> 0 Propagating 00000000000000000000000000070806 assertions for BB31, stmt STMT00148, tree [000811], tree -> 0 Propagating 00000000000000000000000000030906 assertions for BB32, stmt STMT00014, tree [000063], tree -> 0 Propagating 00000000000000000000000000030906 assertions for BB32, stmt STMT00014, tree [000064], tree -> 19 Propagating 00000000000000000000000000070906 assertions for BB32, stmt STMT00014, tree [001322], tree -> 0 Propagating 00000000000000000000000000070906 assertions for BB32, stmt STMT00014, tree [001323], tree -> 0 Propagating 00000000000000000000000000070906 assertions for BB32, stmt STMT00014, tree [001324], tree -> 0 Propagating 00000000000000000000000000070906 assertions for BB32, stmt STMT00014, tree [001325], tree -> 0 Propagating 00000000000000000000000000070906 assertions for BB32, stmt STMT00014, tree [000062], tree -> 0 Propagating 00000000000000000000000000070906 assertions for BB32, stmt STMT00014, tree [000065], tree -> 0 Propagating 00000000000000000000000000070906 assertions for BB32, stmt STMT00014, tree [000066], tree -> 24 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [000209], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [001326], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [000952], tree -> 24 VN based redundant (a[i] followed by a[i]) bounds check assertion prop for index #24 in BB33: N003 ( 6, 9) [000952] ---X-------- * ARR_BOUNDS_CHECK_Rng void Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [000949], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [000950], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [000953], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [000960], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [000961], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [001280], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [001281], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [001282], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [001283], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [000954], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [000955], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [000956], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [000957], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [000958], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [000210], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [000962], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [000959], tree -> 0 Before optRemoveRangeCheck: N020 ( 29, 32) [000959] -A-XG------- * COMMA byref N003 ( 6, 9) [000952] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000209] ------------ | +--* LCL_VAR int V09 loc5 u:2 $3c4 N002 ( 1, 1) [001326] ------------ | \--* LCL_VAR int V76 cse11 N019 ( 23, 23) [000962] -A--G------- \--* ADDR byref $91 N018 ( 12, 12) [000210] aA--G--N---- \--* IND struct N017 ( 11, 11) [000958] -A-----N---- \--* ADD byref $91 N004 ( 1, 1) [000949] ------------ +--* LCL_VAR ref V04 loc0 u:1 N016 ( 10, 10) [000957] -A-----N---- \--* ADD long $6e4 N014 ( 9, 9) [000955] -A-----N---- +--* LSH long $6e3 N012 ( 8, 8) [001283] -A---------- | +--* COMMA long $6e2 N010 ( 7, 7) [001281] -A------R--- | | +--* ASG long $VN.Void N009 ( 1, 1) [001280] D------N---- | | | +--* LCL_VAR long V71 cse6 d:1 $6e2 N008 ( 7, 7) [000961] ------------ | | | \--* MUL long $6e2 N006 ( 2, 3) [000953] ------------ | | | +--* CAST long <- int $6e1 N005 ( 1, 1) [000950] i----------- | | | | \--* LCL_VAR int V09 loc5 u:2 $3c4 N007 ( 1, 1) [000960] ------------ | | | \--* CNS_INT long 3 $24b N011 ( 1, 1) [001282] ------------ | | \--* LCL_VAR long V71 cse6 u:1 $6e2 N013 ( 1, 1) [000954] -------N---- | \--* CNS_INT long 3 $24b N015 ( 1, 1) [000956] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 After optRemoveRangeCheck: N018 ( 23, 23) [000959] -A--G--N---- * COMMA byref N001 ( 0, 0) [000952] ------------ +--* NOP void N017 ( 23, 23) [000962] -A--G------- \--* ADDR byref $91 N016 ( 12, 12) [000210] aA--G--N---- \--* IND struct N015 ( 11, 11) [000958] -A-----N---- \--* ADD byref $91 N002 ( 1, 1) [000949] ------------ +--* LCL_VAR ref V04 loc0 u:1 N014 ( 10, 10) [000957] -A-----N---- \--* ADD long $6e4 N012 ( 9, 9) [000955] -A-----N---- +--* LSH long $6e3 N010 ( 8, 8) [001283] -A---------- | +--* COMMA long $6e2 N008 ( 7, 7) [001281] -A------R--- | | +--* ASG long $VN.Void N007 ( 1, 1) [001280] D------N---- | | | +--* LCL_VAR long V71 cse6 d:1 $6e2 N006 ( 7, 7) [000961] ------------ | | | \--* MUL long $6e2 N004 ( 2, 3) [000953] ------------ | | | +--* CAST long <- int $6e1 N003 ( 1, 1) [000950] i----------- | | | | \--* LCL_VAR int V09 loc5 u:2 $3c4 N005 ( 1, 1) [000960] ------------ | | | \--* CNS_INT long 3 $24b N009 ( 1, 1) [001282] ------------ | | \--* LCL_VAR long V71 cse6 u:1 $6e2 N011 ( 1, 1) [000954] -------N---- | \--* CNS_INT long 3 $24b N013 ( 1, 1) [000956] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [001254], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [001255], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [001256], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [001257], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [000947], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [000948], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [000212], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [000213], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [000214], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB33, stmt STMT00039, tree [000215], tree -> 0 Re-morphing this stmt: STMT00039 (IL 0x17E...0x18C) N028 ( 31, 31) [000215] -A-XG------- * JTRUE void N027 ( 29, 29) [000214] NA-XG--N-U-- \--* NE int N025 ( 27, 27) [000212] *A-XG------- +--* IND int N024 ( 25, 25) [000948] -A--G--N---- | \--* ADD byref $2ac N022 ( 24, 24) [001257] -A--G------- | +--* COMMA byref N020 ( 23, 23) [001255] -A--G---R--- | | +--* ASG byref $VN.Void N019 ( 1, 1) [001254] D------N---- | | | +--* LCL_VAR byref V66 cse1 d:1 N018 ( 23, 23) [000959] -A--G--N---- | | | \--* COMMA byref N001 ( 0, 0) [000952] ------------ | | | +--* NOP void N017 ( 23, 23) [000962] -A--G------- | | | \--* ADDR byref $91 N016 ( 12, 12) [000210] aA--G--N---- | | | \--* IND struct N015 ( 11, 11) [000958] -A-----N---- | | | \--* ADD byref $91 N002 ( 1, 1) [000949] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N014 ( 10, 10) [000957] -A-----N---- | | | \--* ADD long $6e4 N012 ( 9, 9) [000955] -A-----N---- | | | +--* LSH long $6e3 N010 ( 8, 8) [001283] -A---------- | | | | +--* COMMA long $6e2 N008 ( 7, 7) [001281] -A------R--- | | | | | +--* ASG long $VN.Void N007 ( 1, 1) [001280] D------N---- | | | | | | +--* LCL_VAR long V71 cse6 d:1 $6e2 N006 ( 7, 7) [000961] ------------ | | | | | | \--* MUL long $6e2 N004 ( 2, 3) [000953] ------------ | | | | | | +--* CAST long <- int $6e1 N003 ( 1, 1) [000950] i----------- | | | | | | | \--* LCL_VAR int V09 loc5 u:2 $3c4 N005 ( 1, 1) [000960] ------------ | | | | | | \--* CNS_INT long 3 $24b N009 ( 1, 1) [001282] ------------ | | | | | \--* LCL_VAR long V71 cse6 u:1 $6e2 N011 ( 1, 1) [000954] -------N---- | | | | \--* CNS_INT long 3 $24b N013 ( 1, 1) [000956] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N021 ( 1, 1) [001256] ------------ | | \--* LCL_VAR byref V66 cse1 u:1 N023 ( 1, 1) [000947] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N026 ( 1, 1) [000213] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 optAssertionPropMain morphed tree: N026 ( 31, 31) [000215] -A-XG------- * JTRUE void N025 ( 29, 29) [000214] NA-XG--N-U-- \--* NE int N023 ( 27, 27) [000212] *A-XG------- +--* IND int N022 ( 25, 25) [000948] -A--G--N---- | \--* ADD byref $2ac N020 ( 24, 24) [001257] -A--G------- | +--* COMMA byref N018 ( 23, 23) [001255] -A--G---R--- | | +--* ASG byref $VN.Void N017 ( 1, 1) [001254] D------N---- | | | +--* LCL_VAR byref V66 cse1 d:1 N016 ( 23, 23) [000962] -A--G--N---- | | | \--* ADDR byref $91 N015 ( 12, 12) [000210] aA--G--N---- | | | \--* IND struct N014 ( 11, 11) [000958] -A-----N---- | | | \--* ADD byref $91 N001 ( 1, 1) [000949] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 10, 10) [000957] -A-----N---- | | | \--* ADD long $6e4 N011 ( 9, 9) [000955] -A-----N---- | | | +--* LSH long $6e3 N009 ( 8, 8) [001283] -A---------- | | | | +--* COMMA long $6e2 N007 ( 7, 7) [001281] -A------R--- | | | | | +--* ASG long $VN.Void N006 ( 1, 1) [001280] D------N---- | | | | | | +--* LCL_VAR long V71 cse6 d:1 $6e2 N005 ( 7, 7) [000961] ------------ | | | | | | \--* MUL long $6e2 N003 ( 2, 3) [000953] ------------ | | | | | | +--* CAST long <- int $6e1 N002 ( 1, 1) [000950] i----------- | | | | | | | \--* LCL_VAR int V09 loc5 u:2 $3c4 N004 ( 1, 1) [000960] ------------ | | | | | | \--* CNS_INT long 3 $24b N008 ( 1, 1) [001282] ------------ | | | | | \--* LCL_VAR long V71 cse6 u:1 $6e2 N010 ( 1, 1) [000954] -------N---- | | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000956] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N019 ( 1, 1) [001256] ------------ | | \--* LCL_VAR byref V66 cse1 u:1 N021 ( 1, 1) [000947] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N024 ( 1, 1) [000213] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00045, tree [000236], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00045, tree [001327], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00045, tree [000966], tree -> 24 VN based redundant (a[i] followed by a[i]) bounds check assertion prop for index #24 in BB34: N003 ( 6, 9) [000966] ---X-------- * ARR_BOUNDS_CHECK_Rng void Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00045, tree [000963], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00045, tree [001284], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00045, tree [000968], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00045, tree [000969], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00045, tree [000970], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00045, tree [000971], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00045, tree [000972], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00045, tree [000237], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00045, tree [000976], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00045, tree [000977], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00045, tree [000973], tree -> 0 Before optRemoveRangeCheck: N014 ( 18, 20) [000973] ---XG------- * COMMA ref N003 ( 6, 9) [000966] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000236] ------------ | +--* LCL_VAR int V09 loc5 u:2 $3c4 N002 ( 1, 1) [001327] ------------ | \--* LCL_VAR int V76 cse11 N013 ( 12, 11) [000977] *---G------- \--* IND ref N012 ( 9, 9) [000976] ----G------- \--* ADDR byref Zero Fseq[key] $93 N011 ( 5, 5) [000237] a---G--N---- \--* IND struct N010 ( 4, 4) [000972] -------N---- \--* ADD byref $91 N004 ( 1, 1) [000963] ------------ +--* LCL_VAR ref V04 loc0 u:1 N009 ( 3, 3) [000971] -------N---- \--* ADD long $6e4 N007 ( 2, 2) [000969] -------N---- +--* LSH long $6e3 N005 ( 1, 1) [001284] ------------ | +--* LCL_VAR long V71 cse6 u:1 $6e2 N006 ( 1, 1) [000968] -------N---- | \--* CNS_INT long 3 $24b N008 ( 1, 1) [000970] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 After optRemoveRangeCheck: N012 ( 12, 11) [000973] ----G--N---- * COMMA ref N001 ( 0, 0) [000966] ------------ +--* NOP void N011 ( 12, 11) [000977] *---G------- \--* IND ref N010 ( 9, 9) [000976] ----G------- \--* ADDR byref Zero Fseq[key] $93 N009 ( 5, 5) [000237] a---G--N---- \--* IND struct N008 ( 4, 4) [000972] -------N---- \--* ADD byref $91 N002 ( 1, 1) [000963] ------------ +--* LCL_VAR ref V04 loc0 u:1 N007 ( 3, 3) [000971] -------N---- \--* ADD long $6e4 N005 ( 2, 2) [000969] -------N---- +--* LSH long $6e3 N003 ( 1, 1) [001284] ------------ | +--* LCL_VAR long V71 cse6 u:1 $6e2 N004 ( 1, 1) [000968] -------N---- | \--* CNS_INT long 3 $24b N006 ( 1, 1) [000970] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00045, tree [000245], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00045, tree [000246], tree -> 0 Re-morphing this stmt: STMT00045 (IL 0x18E...0x1A2) N014 ( 12, 11) [000246] -A--G---R--- * ASG ref N013 ( 1, 1) [000245] D------N---- +--* LCL_VAR ref V17 tmp3 d:1 N012 ( 12, 11) [000973] ----G--N---- \--* COMMA ref N001 ( 0, 0) [000966] ------------ +--* NOP void N011 ( 12, 11) [000977] *---G------- \--* IND ref N010 ( 9, 9) [000976] ----G------- \--* ADDR byref Zero Fseq[key] $93 N009 ( 5, 5) [000237] a---G--N---- \--* IND struct N008 ( 4, 4) [000972] -------N---- \--* ADD byref $91 N002 ( 1, 1) [000963] ------------ +--* LCL_VAR ref V04 loc0 u:1 N007 ( 3, 3) [000971] -------N---- \--* ADD long $6e4 N005 ( 2, 2) [000969] -------N---- +--* LSH long $6e3 N003 ( 1, 1) [001284] ------------ | +--* LCL_VAR long V71 cse6 u:1 $6e2 N004 ( 1, 1) [000968] -------N---- | \--* CNS_INT long 3 $24b N006 ( 1, 1) [000970] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 optAssertionPropMain morphed tree: N012 ( 12, 11) [000246] -A--G---R--- * ASG ref N011 ( 1, 1) [000245] D------N---- +--* LCL_VAR ref V17 tmp3 d:1 N010 ( 12, 11) [000977] *---G--N---- \--* IND ref N009 ( 9, 9) [000976] ----G------- \--* ADDR byref Zero Fseq[key] $93 N008 ( 5, 5) [000237] a---G--N---- \--* IND struct N007 ( 4, 4) [000972] -------N---- \--* ADD byref $91 N001 ( 1, 1) [000963] ------------ +--* LCL_VAR ref V04 loc0 u:1 N006 ( 3, 3) [000971] -------N---- \--* ADD long $6e4 N004 ( 2, 2) [000969] -------N---- +--* LSH long $6e3 N002 ( 1, 1) [001284] ------------ | +--* LCL_VAR long V71 cse6 u:1 $6e2 N003 ( 1, 1) [000968] -------N---- | \--* CNS_INT long 3 $24b N005 ( 1, 1) [000970] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00044, tree [000241], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00044, tree [000242], tree -> 3 VN based non-null prop in BB34: N002 ( 3, 2) [000242] #--X-------- * IND long $2e8 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00044, tree [000243], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00044, tree [000244], tree -> 0 Re-morphing this stmt: STMT00044 (IL 0x18E... ???) N004 ( 3, 3) [000244] -A-X----R--- * ASG long $2e8 N003 ( 1, 1) [000243] D------N---- +--* LCL_VAR long V16 tmp2 d:1 $2e7 N002 ( 3, 2) [000242] #----O------ \--* IND long $2e8 N001 ( 1, 1) [000241] !----------- \--* LCL_VAR ref V00 this u:1 $100 optAssertionPropMain morphed tree: N004 ( 3, 3) [000244] -A---O--R--- * ASG long $2e8 N003 ( 1, 1) [000243] D------N---- +--* LCL_VAR long V16 tmp2 d:1 $2e7 N002 ( 3, 2) [000242] #----O------ \--* IND long $2e8 N001 ( 1, 1) [000241] !----------- \--* LCL_VAR ref V00 this u:1 $100 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00158, tree [000249], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00158, tree [000250], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00158, tree [000251], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00158, tree [000252], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00158, tree [000253], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00158, tree [000254], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00158, tree [000255], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00158, tree [000259], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00158, tree [001260], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00158, tree [001261], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00158, tree [001262], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00158, tree [001263], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00158, tree [000262], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00158, tree [000263], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB34, stmt STMT00158, tree [001163], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB35, stmt STMT00159, tree [001264], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB35, stmt STMT00159, tree [001164], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB35, stmt STMT00159, tree [001165], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB36, stmt STMT00160, tree [000978], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB36, stmt STMT00160, tree [000979], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB36, stmt STMT00160, tree [000248], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB36, stmt STMT00160, tree [000260], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB36, stmt STMT00160, tree [000261], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB36, stmt STMT00160, tree [001166], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB36, stmt STMT00160, tree [001167], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB37, stmt STMT00049, tree [000981], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB37, stmt STMT00049, tree [000982], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB37, stmt STMT00049, tree [000983], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB37, stmt STMT00049, tree [000984], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB37, stmt STMT00049, tree [000234], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB37, stmt STMT00049, tree [000980], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB37, stmt STMT00049, tree [000247], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB37, stmt STMT00049, tree [000258], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB37, stmt STMT00049, tree [000279], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB37, stmt STMT00049, tree [000280], tree -> 10 Propagating 00000000000000000000000000870B06 assertions for BB37, stmt STMT00049, tree [000281], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB37, stmt STMT00049, tree [000282], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB37, stmt STMT00049, tree [000283], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB38, stmt STMT00050, tree [000284], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB38, stmt STMT00050, tree [000985], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB38, stmt STMT00050, tree [000285], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB38, stmt STMT00050, tree [000286], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB38, stmt STMT00050, tree [000287], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB39, stmt STMT00057, tree [001258], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB39, stmt STMT00057, tree [000986], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB39, stmt STMT00057, tree [000987], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB39, stmt STMT00057, tree [000335], tree -> 25 Propagating 00000000000000000000000001870B06 assertions for BB39, stmt STMT00057, tree [000334], tree -> 0 Propagating 00000000000000000000000001870B06 assertions for BB39, stmt STMT00057, tree [000336], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB40, stmt STMT00051, tree [000288], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB40, stmt STMT00051, tree [001002], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB40, stmt STMT00051, tree [000289], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB40, stmt STMT00051, tree [000290], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB40, stmt STMT00051, tree [000291], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB42, stmt STMT00040, tree [001259], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB42, stmt STMT00040, tree [001008], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB42, stmt STMT00040, tree [001009], tree -> 0 Propagating 00000000000000000000000000870906 assertions for BB42, stmt STMT00040, tree [000220], tree -> 25 Propagating 00000000000000000000000001870906 assertions for BB42, stmt STMT00040, tree [000221], tree -> 0 Propagating 00000000000000000000000001870906 assertions for BB42, stmt STMT00040, tree [000222], tree -> 0 Propagating 00000000000000000000000001870906 assertions for BB42, stmt STMT00041, tree [000223], tree -> 0 Propagating 00000000000000000000000001870906 assertions for BB42, stmt STMT00041, tree [000224], tree -> 0 Propagating 00000000000000000000000001870906 assertions for BB42, stmt STMT00041, tree [000225], tree -> 0 Propagating 00000000000000000000000001870906 assertions for BB42, stmt STMT00041, tree [000226], tree -> 0 Propagating 00000000000000000000000001870906 assertions for BB42, stmt STMT00041, tree [000227], tree -> 0 Propagating 00000000000000000000000001870906 assertions for BB42, stmt STMT00042, tree [001328], tree -> 0 Propagating 00000000000000000000000001870906 assertions for BB42, stmt STMT00042, tree [000228], tree -> 0 Propagating 00000000000000000000000001870906 assertions for BB42, stmt STMT00042, tree [000231], tree -> 0 Propagating 00000000000000000000000001870906 assertions for BB42, stmt STMT00042, tree [000232], tree -> 0 Propagating 00000000000000000000000000070806 assertions for BB44, stmt STMT00015, tree [000067], tree -> 0 Propagating 00000000000000000000000000070806 assertions for BB44, stmt STMT00015, tree [001024], tree -> 0 Propagating 00000000000000000000000000070806 assertions for BB44, stmt STMT00015, tree [001025], tree -> 0 Propagating 00000000000000000000000000070806 assertions for BB44, stmt STMT00015, tree [000068], tree -> 3 VN based non-null prop in BB44: N004 ( 4, 4) [000068] ---XG------- * IND int Propagating 00000000000000000000000000070806 assertions for BB44, stmt STMT00015, tree [000069], tree -> 0 Propagating 00000000000000000000000000070806 assertions for BB44, stmt STMT00015, tree [000070], tree -> 0 Propagating 00000000000000000000000000070806 assertions for BB44, stmt STMT00015, tree [000071], tree -> 26 Re-morphing this stmt: STMT00015 (IL 0x1E4...0x1EB) N007 ( 8, 8) [000071] ---XG------- * JTRUE void N006 ( 6, 6) [000070] J--XG--N---- \--* LE int N004 ( 4, 4) [000068] n---GO------ +--* IND int N003 ( 2, 2) [001025] -------N---- | \--* ADD byref $28f N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001024] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N005 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 $c0 optAssertionPropMain morphed tree: N007 ( 8, 8) [000071] ----GO------ * JTRUE void N006 ( 6, 6) [000070] J---GO-N---- \--* LE int N004 ( 4, 4) [000068] n---GO------ +--* IND int N003 ( 2, 2) [001025] -------N---- | \--* ADD byref $28f N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001024] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N005 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 $c0 Propagating 00000000000000000000000004070806 assertions for BB45, stmt STMT00035, tree [000171], tree -> 0 Propagating 00000000000000000000000004070806 assertions for BB45, stmt STMT00035, tree [001026], tree -> 0 Propagating 00000000000000000000000004070806 assertions for BB45, stmt STMT00035, tree [001027], tree -> 0 Propagating 00000000000000000000000004070806 assertions for BB45, stmt STMT00035, tree [000172], tree -> 3 VN based non-null prop in BB45: N004 ( 4, 4) [000172] ---XG------- * IND int Propagating 00000000000000000000000004070806 assertions for BB45, stmt STMT00035, tree [001305], tree -> 0 Propagating 00000000000000000000000004070806 assertions for BB45, stmt STMT00035, tree [001306], tree -> 0 Propagating 00000000000000000000000004070806 assertions for BB45, stmt STMT00035, tree [001307], tree -> 0 Propagating 00000000000000000000000004070806 assertions for BB45, stmt STMT00035, tree [001308], tree -> 0 Propagating 00000000000000000000000004070806 assertions for BB45, stmt STMT00035, tree [000173], tree -> 0 Propagating 00000000000000000000000004070806 assertions for BB45, stmt STMT00035, tree [000174], tree -> 0 Re-morphing this stmt: STMT00035 (IL 0x1ED...0x1F3) N010 ( 15, 12) [000174] -A-XG---R--- * ASG int N009 ( 3, 2) [000173] D------N---- +--* LCL_VAR int V10 loc6 d:3 N008 ( 11, 9) [001308] -A-XG------- \--* COMMA int N006 ( 8, 7) [001306] -A-XG---R--- +--* ASG int $VN.Void N005 ( 3, 2) [001305] D------N---- | +--* LCL_VAR int V74 cse9 d:1 N004 ( 4, 4) [000172] n---GO------ | \--* IND int N003 ( 2, 2) [001027] -------N---- | \--* ADD byref $295 N001 ( 1, 1) [000171] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001026] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N007 ( 3, 2) [001307] ------------ \--* LCL_VAR int V74 cse9 u:1 optAssertionPropMain morphed tree: N010 ( 15, 12) [000174] -A--GO--R--- * ASG int N009 ( 3, 2) [000173] D------N---- +--* LCL_VAR int V10 loc6 d:3 N008 ( 11, 9) [001308] -A--GO------ \--* COMMA int N006 ( 8, 7) [001306] -A--GO--R--- +--* ASG int $VN.Void N005 ( 3, 2) [001305] D------N---- | +--* LCL_VAR int V74 cse9 d:1 N004 ( 4, 4) [000172] n---GO------ | \--* IND int N003 ( 2, 2) [001027] -------N---- | \--* ADD byref $295 N001 ( 1, 1) [000171] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001026] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N007 ( 3, 2) [001307] ------------ \--* LCL_VAR int V74 cse9 u:1 Propagating 00000000000000000000000004070806 assertions for BB45, stmt STMT00120, tree [001309], tree -> 0 Propagating 00000000000000000000000004070806 assertions for BB45, stmt STMT00120, tree [001031], tree -> 0 Propagating 00000000000000000000000004070806 assertions for BB45, stmt STMT00120, tree [001032], tree -> 0 Propagating 00000000000000000000000004070806 assertions for BB45, stmt STMT00120, tree [001033], tree -> 0 Propagating 00000000000000000000000004070806 assertions for BB45, stmt STMT00120, tree [001329], tree -> 0 Propagating 00000000000000000000000004070806 assertions for BB45, stmt STMT00120, tree [001036], tree -> 28 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [001030], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [001034], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [001037], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [001047], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [001048], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [001038], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [001039], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [001040], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [001041], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [001042], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [000179], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [001049], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [001043], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [001044], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [001028], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [001029], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [000181], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [001050], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [000175], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [000182], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [000183], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [000184], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [000687], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00120, tree [000688], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00123, tree [001300], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00123, tree [000697], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00123, tree [000698], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00121, tree [000690], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00121, tree [000691], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00121, tree [000692], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB45, stmt STMT00121, tree [000693], tree -> 29 Propagating 0000000000000000000000002C070806 assertions for BB46, stmt STMT00122, tree [001053], tree -> 0 Propagating 0000000000000000000000002C070806 assertions for BB46, stmt STMT00122, tree [001054], tree -> 0 Propagating 0000000000000000000000002C070806 assertions for BB46, stmt STMT00122, tree [001051], tree -> 0 Propagating 0000000000000000000000002C070806 assertions for BB46, stmt STMT00122, tree [001052], tree -> 0 Propagating 0000000000000000000000002C070806 assertions for BB46, stmt STMT00122, tree [000695], tree -> 0 Propagating 0000000000000000000000002C070806 assertions for BB46, stmt STMT00122, tree [000696], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB47, stmt STMT00037, tree [000190], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB47, stmt STMT00037, tree [001055], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB47, stmt STMT00037, tree [001056], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB47, stmt STMT00037, tree [000199], tree -> 3 VN based non-null prop in BB47: N004 ( 4, 4) [000199] D--XG--N---- * IND int $732 Propagating 0000000000000000000000000C070806 assertions for BB47, stmt STMT00037, tree [000193], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB47, stmt STMT00037, tree [001074], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB47, stmt STMT00037, tree [001075], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB47, stmt STMT00037, tree [000194], tree -> 3 VN based non-null prop in BB47: N008 ( 4, 4) [000194] ---XG------- * IND int Propagating 0000000000000000000000000C070806 assertions for BB47, stmt STMT00037, tree [001060], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB47, stmt STMT00037, tree [001061], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB47, stmt STMT00037, tree [001062], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB47, stmt STMT00037, tree [001330], tree -> 0 Propagating 0000000000000000000000000C070806 assertions for BB47, stmt STMT00037, tree [001065], tree -> 31 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00037, tree [001059], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00037, tree [001063], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00037, tree [001066], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00037, tree [001076], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00037, tree [001077], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00037, tree [001067], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00037, tree [001068], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00037, tree [001069], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00037, tree [001070], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00037, tree [001071], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00037, tree [000195], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00037, tree [001078], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00037, tree [001072], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00037, tree [001073], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00037, tree [001057], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00037, tree [001058], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00037, tree [000197], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00037, tree [001079], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00037, tree [000191], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00037, tree [000198], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00037, tree [000200], tree -> 0 Re-morphing this stmt: STMT00037 (IL 0x219... ???) N034 ( 42, 45) [000200] -A-XG------- * ASG int $VN.Void N004 ( 4, 4) [000199] n---GO-N---- +--* IND int $732 N003 ( 2, 2) [001056] -------N---- | \--* ADD byref $295 N001 ( 1, 1) [000190] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001055] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N033 ( 37, 40) [000198] -A-XG------- \--* ADD int N031 ( 35, 38) [001079] -A-XG------- +--* NEG int N030 ( 34, 37) [000197] *A-XG------- | \--* IND int N029 ( 32, 35) [001058] -A-XG--N---- | \--* ADD byref $2a3 N027 ( 31, 34) [001073] -A-XG------- | +--* COMMA byref N010 ( 4, 4) [001061] -A-XG---R--- | | +--* ASG int N009 ( 1, 1) [001060] D------N---- | | | +--* LCL_VAR int V63 tmp49 d:1 N008 ( 4, 4) [000194] n---GO------ | | | \--* IND int N007 ( 2, 2) [001075] -------N---- | | | \--* ADD byref $295 N005 ( 1, 1) [000193] ------------ | | | +--* LCL_VAR ref V00 this u:1 $100 N006 ( 1, 1) [001074] ------------ | | | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N026 ( 27, 30) [001072] ---XG------- | | \--* COMMA byref N013 ( 6, 9) [001065] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N011 ( 1, 1) [001062] ------------ | | | +--* LCL_VAR int V63 tmp49 u:1 N012 ( 1, 1) [001330] ------------ | | | \--* LCL_VAR int V76 cse11 N025 ( 21, 21) [001078] ----G------- | | \--* ADDR byref $8a N024 ( 11, 11) [000195] a---G--N---- | | \--* IND struct N023 ( 10, 10) [001071] -------N---- | | \--* ADD byref $8a N014 ( 1, 1) [001059] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N022 ( 9, 9) [001070] -------N---- | | \--* ADD long N020 ( 8, 8) [001068] -------N---- | | +--* LSH long N018 ( 7, 7) [001077] ------------ | | | +--* MUL long N016 ( 2, 3) [001066] ------------ | | | | +--* CAST long <- int N015 ( 1, 1) [001063] i----------- | | | | | \--* LCL_VAR int V63 tmp49 u:1 (last use) N017 ( 1, 1) [001076] ------------ | | | | \--* CNS_INT long 3 $24b N019 ( 1, 1) [001067] -------N---- | | | \--* CNS_INT long 3 $24b N021 ( 1, 1) [001069] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N028 ( 1, 1) [001057] ------------ | \--* CNS_INT long 20 field offset Fseq[next] $24c N032 ( 1, 1) [000191] ------------ \--* CNS_INT int -3 $e1 optAssertionPropMain morphed tree: N034 ( 42, 45) [000200] -A-XGO------ * ASG int $VN.Void N004 ( 4, 4) [000199] n---GO-N---- +--* IND int $732 N003 ( 2, 2) [001056] -------N---- | \--* ADD byref $295 N001 ( 1, 1) [000190] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001055] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N033 ( 37, 40) [000198] -A-XGO------ \--* ADD int N031 ( 35, 38) [001079] -A-XGO------ +--* NEG int N030 ( 34, 37) [000197] *A-XGO------ | \--* IND int N029 ( 32, 35) [001058] -A-XGO-N---- | \--* ADD byref $2a3 N027 ( 31, 34) [001073] -A-XGO------ | +--* COMMA byref N010 ( 4, 4) [001061] -A--GO--R--- | | +--* ASG int N009 ( 1, 1) [001060] D------N---- | | | +--* LCL_VAR int V63 tmp49 d:1 N008 ( 4, 4) [000194] n---GO------ | | | \--* IND int N007 ( 2, 2) [001075] -------N---- | | | \--* ADD byref $295 N005 ( 1, 1) [000193] ------------ | | | +--* LCL_VAR ref V00 this u:1 $100 N006 ( 1, 1) [001074] ------------ | | | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N026 ( 27, 30) [001072] ---XG------- | | \--* COMMA byref N013 ( 6, 9) [001065] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N011 ( 1, 1) [001062] ------------ | | | +--* LCL_VAR int V63 tmp49 u:1 N012 ( 1, 1) [001330] ------------ | | | \--* LCL_VAR int V76 cse11 N025 ( 21, 21) [001078] ----G------- | | \--* ADDR byref $8a N024 ( 11, 11) [000195] a---G--N---- | | \--* IND struct N023 ( 10, 10) [001071] -------N---- | | \--* ADD byref $8a N014 ( 1, 1) [001059] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N022 ( 9, 9) [001070] -------N---- | | \--* ADD long N020 ( 8, 8) [001068] -------N---- | | +--* LSH long N018 ( 7, 7) [001077] ------------ | | | +--* MUL long N016 ( 2, 3) [001066] ------------ | | | | +--* CAST long <- int N015 ( 1, 1) [001063] i----------- | | | | | \--* LCL_VAR int V63 tmp49 u:1 (last use) N017 ( 1, 1) [001076] ------------ | | | | \--* CNS_INT long 3 $24b N019 ( 1, 1) [001067] -------N---- | | | \--* CNS_INT long 3 $24b N021 ( 1, 1) [001069] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N028 ( 1, 1) [001057] ------------ | \--* CNS_INT long 20 field offset Fseq[next] $24c N032 ( 1, 1) [000191] ------------ \--* CNS_INT int -3 $e1 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00038, tree [000202], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00038, tree [001082], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00038, tree [001083], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00038, tree [000203], tree -> 3 VN based non-null prop in BB47: N004 ( 4, 4) [000203] ---XG------- * IND int Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00038, tree [000204], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00038, tree [000205], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00038, tree [000201], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00038, tree [001080], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00038, tree [001081], tree -> 0 Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00038, tree [000206], tree -> 3 VN based non-null prop in BB47: N010 ( 4, 4) [000206] D--XG--N---- * IND int $73a Propagating 0000000000000000000000004C070806 assertions for BB47, stmt STMT00038, tree [000207], tree -> 0 Re-morphing this stmt: STMT00038 (IL 0x233...0x23C) N011 ( 11, 11) [000207] -A-XG---R--- * ASG int $VN.Void N010 ( 4, 4) [000206] n---GO-N---- +--* IND int $73a N009 ( 2, 2) [001081] -------N---- | \--* ADD byref $28f N007 ( 1, 1) [000201] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001080] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N006 ( 6, 6) [000205] ---XG------- \--* ADD int N004 ( 4, 4) [000203] n---GO------ +--* IND int N003 ( 2, 2) [001083] -------N---- | \--* ADD byref $28f N001 ( 1, 1) [000202] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001082] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N005 ( 1, 1) [000204] ------------ \--* CNS_INT int -1 $c4 optAssertionPropMain morphed tree: N011 ( 11, 11) [000207] -A--GO--R--- * ASG int $VN.Void N010 ( 4, 4) [000206] n---GO-N---- +--* IND int $73a N009 ( 2, 2) [001081] -------N---- | \--* ADD byref $28f N007 ( 1, 1) [000201] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001080] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N006 ( 6, 6) [000205] ----GO------ \--* ADD int N004 ( 4, 4) [000203] n---GO------ +--* IND int N003 ( 2, 2) [001083] -------N---- | \--* ADD byref $28f N001 ( 1, 1) [000202] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001082] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N005 ( 1, 1) [000204] ------------ \--* CNS_INT int -1 $c4 Propagating 00000000000000000000000002070806 assertions for BB48, stmt STMT00016, tree [000072], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB48, stmt STMT00016, tree [001084], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB48, stmt STMT00016, tree [001085], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB48, stmt STMT00016, tree [000073], tree -> 3 VN based non-null prop in BB48: N004 ( 4, 4) [000073] ---XG------- * IND int Propagating 00000000000000000000000002070806 assertions for BB48, stmt STMT00016, tree [001310], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB48, stmt STMT00016, tree [001311], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB48, stmt STMT00016, tree [001312], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB48, stmt STMT00016, tree [001313], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB48, stmt STMT00016, tree [000074], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB48, stmt STMT00016, tree [000075], tree -> 0 Re-morphing this stmt: STMT00016 (IL 0x243...0x249) N010 ( 15, 12) [000075] -A-XG---R--- * ASG int N009 ( 3, 2) [000074] D------N---- +--* LCL_VAR int V13 loc9 d:1 N008 ( 11, 9) [001313] -A-XG------- \--* COMMA int N006 ( 8, 7) [001311] -A-XG---R--- +--* ASG int $VN.Void N005 ( 3, 2) [001310] D------N---- | +--* LCL_VAR int V75 cse10 d:1 N004 ( 4, 4) [000073] n---GO------ | \--* IND int N003 ( 2, 2) [001085] -------N---- | \--* ADD byref $290 N001 ( 1, 1) [000072] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001084] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] $244 N007 ( 3, 2) [001312] ------------ \--* LCL_VAR int V75 cse10 u:1 optAssertionPropMain morphed tree: N010 ( 15, 12) [000075] -A--GO--R--- * ASG int N009 ( 3, 2) [000074] D------N---- +--* LCL_VAR int V13 loc9 d:1 N008 ( 11, 9) [001313] -A--GO------ \--* COMMA int N006 ( 8, 7) [001311] -A--GO--R--- +--* ASG int $VN.Void N005 ( 3, 2) [001310] D------N---- | +--* LCL_VAR int V75 cse10 d:1 N004 ( 4, 4) [000073] n---GO------ | \--* IND int N003 ( 2, 2) [001085] -------N---- | \--* ADD byref $290 N001 ( 1, 1) [000072] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001084] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] $244 N007 ( 3, 2) [001312] ------------ \--* LCL_VAR int V75 cse10 u:1 Propagating 00000000000000000000000002070806 assertions for BB48, stmt STMT00017, tree [001331], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB48, stmt STMT00017, tree [000076], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB48, stmt STMT00017, tree [000079], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB48, stmt STMT00017, tree [000080], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB49, stmt STMT00125, tree [001092], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB49, stmt STMT00125, tree [001088], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB49, stmt STMT00125, tree [001314], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB49, stmt STMT00125, tree [000702], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB49, stmt STMT00125, tree [001089], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB49, stmt STMT00125, tree [001090], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB49, stmt STMT00125, tree [001093], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB49, stmt STMT00125, tree [001091], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB49, stmt STMT00125, tree [000163], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB49, stmt STMT00125, tree [000704], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB49, stmt STMT00125, tree [000705], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB49, stmt STMT00126, tree [000165], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB49, stmt STMT00126, tree [001094], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB49, stmt STMT00126, tree [001095], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB49, stmt STMT00126, tree [000709], tree -> 3 VN based non-null prop in BB49: N004 ( 4, 4) [000709] ---XG------- * IND ref Propagating 00000000000000000000000002070806 assertions for BB49, stmt STMT00126, tree [000710], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB49, stmt STMT00126, tree [000711], tree -> 0 Re-morphing this stmt: STMT00126 (IL 0x258... ???) N006 ( 8, 7) [000711] -A-XG---R--- * ASG ref N005 ( 3, 2) [000710] D------N---- +--* LCL_VAR ref V52 tmp38 d:1 N004 ( 4, 4) [000709] n---GO------ \--* IND ref N003 ( 2, 2) [001095] -------N---- \--* ADD byref $280 N001 ( 1, 1) [000165] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001094] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] $240 optAssertionPropMain morphed tree: N006 ( 8, 7) [000711] -A--GO--R--- * ASG ref N005 ( 3, 2) [000710] D------N---- +--* LCL_VAR ref V52 tmp38 d:1 N004 ( 4, 4) [000709] n---GO------ \--* IND ref N003 ( 2, 2) [001095] -------N---- \--* ADD byref $280 N001 ( 1, 1) [000165] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001094] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] $240 Propagating 00000000000000000000000002070806 assertions for BB49, stmt STMT00133, tree [000713], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB49, stmt STMT00133, tree [000714], tree -> 32 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00133, tree [001285], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00133, tree [001286], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00133, tree [001287], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00133, tree [001288], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00133, tree [000759], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00133, tree [000760], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00134, tree [000715], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00134, tree [001096], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00134, tree [001097], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00134, tree [000716], tree -> 3 VN based non-null prop in BB49: N004 ( 4, 4) [000716] ---XG------- * IND long Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00134, tree [000761], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00134, tree [000762], tree -> 0 Re-morphing this stmt: STMT00134 (IL 0x258... ???) N006 ( 8, 7) [000762] -A-XG---R--- * ASG long N005 ( 3, 2) [000761] D------N---- +--* LCL_VAR long V54 tmp40 d:1 N004 ( 4, 4) [000716] n---GO------ \--* IND long N003 ( 2, 2) [001097] -------N---- \--* ADD byref $283 N001 ( 1, 1) [000715] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001096] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 optAssertionPropMain morphed tree: N006 ( 8, 7) [000762] -A--GO--R--- * ASG long N005 ( 3, 2) [000761] D------N---- +--* LCL_VAR long V54 tmp40 d:1 N004 ( 4, 4) [000716] n---GO------ \--* IND long N003 ( 2, 2) [001097] -------N---- \--* ADD byref $283 N001 ( 1, 1) [000715] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001096] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00136, tree [000728], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00136, tree [000729], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00136, tree [000730], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00136, tree [000772], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00136, tree [000773], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00139, tree [001301], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00139, tree [000782], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00139, tree [000783], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00140, tree [001302], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00140, tree [000784], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00140, tree [000785], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00137, tree [000775], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00137, tree [000776], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00137, tree [000777], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB49, stmt STMT00137, tree [000778], tree -> 33 Propagating 00000000000000000000000282070806 assertions for BB50, stmt STMT00138, tree [001098], tree -> 0 Propagating 00000000000000000000000282070806 assertions for BB50, stmt STMT00138, tree [001099], tree -> 0 Propagating 00000000000000000000000282070806 assertions for BB50, stmt STMT00138, tree [000779], tree -> 0 Propagating 00000000000000000000000282070806 assertions for BB50, stmt STMT00138, tree [000780], tree -> 0 Propagating 00000000000000000000000282070806 assertions for BB50, stmt STMT00138, tree [000781], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00131, tree [000735], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00131, tree [000166], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00131, tree [000736], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00131, tree [000737], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00131, tree [000738], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00131, tree [000739], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00131, tree [000741], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00131, tree [000742], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00131, tree [000743], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00131, tree [000744], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00131, tree [000745], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00131, tree [000746], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00131, tree [000747], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00131, tree [000748], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00131, tree [000749], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00131, tree [000750], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00142, tree [000752], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00142, tree [000753], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00142, tree [000754], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00142, tree [000751], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00142, tree [000755], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00142, tree [000795], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00142, tree [000796], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00145, tree [001303], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00145, tree [000805], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00145, tree [000806], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00146, tree [001304], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00146, tree [000807], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00146, tree [000808], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00143, tree [000798], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00143, tree [000799], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00143, tree [000800], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB51, stmt STMT00143, tree [000801], tree -> 35 Propagating 00000000000000000000000882070806 assertions for BB52, stmt STMT00144, tree [001100], tree -> 0 Propagating 00000000000000000000000882070806 assertions for BB52, stmt STMT00144, tree [001101], tree -> 0 Propagating 00000000000000000000000882070806 assertions for BB52, stmt STMT00144, tree [000802], tree -> 0 Propagating 00000000000000000000000882070806 assertions for BB52, stmt STMT00144, tree [000803], tree -> 0 Propagating 00000000000000000000000882070806 assertions for BB52, stmt STMT00144, tree [000804], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB53, stmt STMT00128, tree [000758], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB53, stmt STMT00128, tree [001289], tree -> 0 Propagating 00000000000000000000000082070806 assertions for BB53, stmt STMT00128, tree [001105], tree -> 37 Propagating 00000000000000000000001082070806 assertions for BB53, stmt STMT00128, tree [001102], tree -> 0 Propagating 00000000000000000000001082070806 assertions for BB53, stmt STMT00128, tree [001103], tree -> 0 Propagating 00000000000000000000001082070806 assertions for BB53, stmt STMT00128, tree [001106], tree -> 0 Propagating 00000000000000000000001082070806 assertions for BB53, stmt STMT00128, tree [001107], tree -> 0 Propagating 00000000000000000000001082070806 assertions for BB53, stmt STMT00128, tree [001108], tree -> 0 Propagating 00000000000000000000001082070806 assertions for BB53, stmt STMT00128, tree [001109], tree -> 0 Propagating 00000000000000000000001082070806 assertions for BB53, stmt STMT00128, tree [001110], tree -> 0 Propagating 00000000000000000000001082070806 assertions for BB53, stmt STMT00128, tree [001111], tree -> 0 Propagating 00000000000000000000001082070806 assertions for BB53, stmt STMT00128, tree [000719], tree -> 0 Propagating 00000000000000000000001082070806 assertions for BB53, stmt STMT00128, tree [001113], tree -> 0 Propagating 00000000000000000000001082070806 assertions for BB53, stmt STMT00128, tree [001112], tree -> 0 Propagating 00000000000000000000001082070806 assertions for BB53, stmt STMT00128, tree [000721], tree -> 0 Propagating 00000000000000000000001082070806 assertions for BB53, stmt STMT00128, tree [000722], tree -> 0 Propagating 00000000000000000000001082070806 assertions for BB53, stmt STMT00034, tree [000723], tree -> 0 Propagating 00000000000000000000001082070806 assertions for BB53, stmt STMT00034, tree [000169], tree -> 0 Propagating 00000000000000000000001082070806 assertions for BB53, stmt STMT00034, tree [000170], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB54, stmt STMT00018, tree [000081], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB54, stmt STMT00018, tree [000082], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB54, stmt STMT00018, tree [000083], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB54, stmt STMT00019, tree [000085], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB54, stmt STMT00019, tree [000086], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB54, stmt STMT00019, tree [000087], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB54, stmt STMT00019, tree [000084], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB54, stmt STMT00019, tree [001114], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB54, stmt STMT00019, tree [001115], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB54, stmt STMT00019, tree [000088], tree -> 3 VN based non-null prop in BB54: N007 ( 4, 4) [000088] D--XG--N---- * IND int $708 Propagating 00000000000000000000000002070806 assertions for BB54, stmt STMT00019, tree [000089], tree -> 0 Re-morphing this stmt: STMT00019 (IL 0x265...0x26A) N008 ( 10, 9) [000089] -A-XG---R--- * ASG int $VN.Void N007 ( 4, 4) [000088] n---GO-N---- +--* IND int $708 N006 ( 2, 2) [001115] -------N---- | \--* ADD byref $290 N004 ( 1, 1) [000084] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N005 ( 1, 1) [001114] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] $244 N003 ( 5, 4) [000087] ------------ \--* ADD int N001 ( 3, 2) [000085] ------------ +--* LCL_VAR int V10 loc6 u:2 (last use) N002 ( 1, 1) [000086] ------------ \--* CNS_INT int 1 $c1 optAssertionPropMain morphed tree: N008 ( 10, 9) [000089] -A--GO--R--- * ASG int $VN.Void N007 ( 4, 4) [000088] n---GO-N---- +--* IND int $708 N006 ( 2, 2) [001115] -------N---- | \--* ADD byref $290 N004 ( 1, 1) [000084] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N005 ( 1, 1) [001114] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] $244 N003 ( 5, 4) [000087] ------------ \--* ADD int N001 ( 3, 2) [000085] ------------ +--* LCL_VAR int V10 loc6 u:2 (last use) N002 ( 1, 1) [000086] ------------ \--* CNS_INT int 1 $c1 Propagating 00000000000000000000000002070806 assertions for BB54, stmt STMT00020, tree [000090], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB54, stmt STMT00020, tree [001116], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB54, stmt STMT00020, tree [001117], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB54, stmt STMT00020, tree [000091], tree -> 3 VN based non-null prop in BB54: N004 ( 4, 4) [000091] ---XG------- * IND ref Propagating 00000000000000000000000002070806 assertions for BB54, stmt STMT00020, tree [000092], tree -> 0 Propagating 00000000000000000000000002070806 assertions for BB54, stmt STMT00020, tree [000093], tree -> 0 Re-morphing this stmt: STMT00020 (IL 0x26F...0x275) N006 ( 4, 4) [000093] -A-XG---R--- * ASG ref N005 ( 1, 1) [000092] D------N---- +--* LCL_VAR ref V04 loc0 d:3 N004 ( 4, 4) [000091] n---GO------ \--* IND ref N003 ( 2, 2) [001117] -------N---- \--* ADD byref $281 N001 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001116] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] $241 optAssertionPropMain morphed tree: N006 ( 4, 4) [000093] -A--GO--R--- * ASG ref N005 ( 1, 1) [000092] D------N---- +--* LCL_VAR ref V04 loc0 d:3 N004 ( 4, 4) [000091] n---GO------ \--* IND ref N003 ( 2, 2) [001117] -------N---- \--* ADD byref $281 N001 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001116] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] $241 Propagating 00000000000000000000000000070806 assertions for BB55, stmt STMT00021, tree [000095], tree -> 0 Propagating 00000000000000000000000000070806 assertions for BB55, stmt STMT00021, tree [000094], tree -> 0 Propagating 00000000000000000000000000070806 assertions for BB55, stmt STMT00021, tree [001120], tree -> 38 Propagating 00000000000000000000002000070806 assertions for BB55, stmt STMT00021, tree [001121], tree -> 39 Propagating 00000000000000000000006000070806 assertions for BB55, stmt STMT00021, tree [001118], tree -> 0 Propagating 00000000000000000000006000070806 assertions for BB55, stmt STMT00021, tree [001119], tree -> 0 Propagating 00000000000000000000006000070806 assertions for BB55, stmt STMT00021, tree [001122], tree -> 0 Propagating 00000000000000000000006000070806 assertions for BB55, stmt STMT00021, tree [001129], tree -> 0 Propagating 00000000000000000000006000070806 assertions for BB55, stmt STMT00021, tree [001130], tree -> 0 Propagating 00000000000000000000006000070806 assertions for BB55, stmt STMT00021, tree [001123], tree -> 0 Propagating 00000000000000000000006000070806 assertions for BB55, stmt STMT00021, tree [001124], tree -> 0 Propagating 00000000000000000000006000070806 assertions for BB55, stmt STMT00021, tree [001125], tree -> 0 Propagating 00000000000000000000006000070806 assertions for BB55, stmt STMT00021, tree [001126], tree -> 0 Propagating 00000000000000000000006000070806 assertions for BB55, stmt STMT00021, tree [001127], tree -> 0 Propagating 00000000000000000000006000070806 assertions for BB55, stmt STMT00021, tree [000096], tree -> 0 Propagating 00000000000000000000006000070806 assertions for BB55, stmt STMT00021, tree [001131], tree -> 0 Propagating 00000000000000000000006000070806 assertions for BB55, stmt STMT00021, tree [001128], tree -> 0 Propagating 00000000000000000000006000070806 assertions for BB55, stmt STMT00021, tree [000098], tree -> 0 Propagating 00000000000000000000006000070806 assertions for BB55, stmt STMT00021, tree [000099], tree -> 0 Propagating 00000000000000000000006000070806 assertions for BB55, stmt STMT00022, tree [000100], tree -> 0 Propagating 00000000000000000000006000070806 assertions for BB55, stmt STMT00022, tree [001132], tree -> 0 Propagating 00000000000000000000006000070806 assertions for BB55, stmt STMT00022, tree [001133], tree -> 0 Propagating 00000000000000000000006000070806 assertions for BB55, stmt STMT00022, tree [000102], tree -> 40 Propagating 0000000000000000000000E000070806 assertions for BB55, stmt STMT00022, tree [000101], tree -> 0 Propagating 0000000000000000000000E000070806 assertions for BB55, stmt STMT00022, tree [000103], tree -> 0 Propagating 0000000000000000000000E000070806 assertions for BB55, stmt STMT00023, tree [000105], tree -> 0 Propagating 0000000000000000000000E000070806 assertions for BB55, stmt STMT00023, tree [000106], tree -> 41 Propagating 0000000000000000000001E000070806 assertions for BB55, stmt STMT00023, tree [000107], tree -> 0 Propagating 0000000000000000000001E000070806 assertions for BB55, stmt STMT00023, tree [000108], tree -> 0 Propagating 0000000000000000000001E000070806 assertions for BB55, stmt STMT00023, tree [000104], tree -> 0 Propagating 0000000000000000000001E000070806 assertions for BB55, stmt STMT00023, tree [001134], tree -> 0 Propagating 0000000000000000000001E000070806 assertions for BB55, stmt STMT00023, tree [001135], tree -> 0 Propagating 0000000000000000000001E000070806 assertions for BB55, stmt STMT00023, tree [000109], tree -> 40 VN based non-null prop in BB55: N008 ( 6, 5) [000109] *--XG--N---- * IND int Propagating 0000000000000000000001E000070806 assertions for BB55, stmt STMT00023, tree [000110], tree -> 0 Re-morphing this stmt: STMT00023 (IL 0x288...0x28F) N009 ( 15, 12) [000110] -A-XG---R--- * ASG int $VN.Void N008 ( 6, 5) [000109] *---GO-N---- +--* IND int N007 ( 4, 3) [001135] -------N---- | \--* ADD byref $8e N005 ( 3, 2) [000104] ------------ | +--* LCL_VAR byref V11 loc7 u:1 $8c N006 ( 1, 1) [001134] ------------ | \--* CNS_INT long 20 field offset Fseq[next] $24c N004 ( 8, 6) [000108] ---XG------- \--* ADD int N002 ( 6, 4) [000106] *--XG------- +--* IND int N001 ( 3, 2) [000105] ------------ | \--* LCL_VAR byref V08 loc4 u:2 $781 N003 ( 1, 1) [000107] ------------ \--* CNS_INT int -1 $c4 optAssertionPropMain morphed tree: N009 ( 15, 12) [000110] -A-XGO--R--- * ASG int $VN.Void N008 ( 6, 5) [000109] *---GO-N---- +--* IND int N007 ( 4, 3) [001135] -------N---- | \--* ADD byref $8e N005 ( 3, 2) [000104] ------------ | +--* LCL_VAR byref V11 loc7 u:1 $8c N006 ( 1, 1) [001134] ------------ | \--* CNS_INT long 20 field offset Fseq[next] $24c N004 ( 8, 6) [000108] ---XG------- \--* ADD int N002 ( 6, 4) [000106] *--XG------- +--* IND int N001 ( 3, 2) [000105] ------------ | \--* LCL_VAR byref V08 loc4 u:2 $781 N003 ( 1, 1) [000107] ------------ \--* CNS_INT int -1 $c4 Propagating 0000000000000000000001E000070806 assertions for BB55, stmt STMT00024, tree [000111], tree -> 0 Propagating 0000000000000000000001E000070806 assertions for BB55, stmt STMT00024, tree [000113], tree -> 42 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00024, tree [000112], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00024, tree [000114], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00025, tree [000115], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00025, tree [001136], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00025, tree [001137], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00025, tree [000117], tree -> 40 VN based non-null prop in BB55: N004 ( 6, 5) [000117] *--XG--N---- * IND ref $102 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00025, tree [000116], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00025, tree [000118], tree -> 0 Re-morphing this stmt: STMT00025 (IL 0x29C...0x29F) N006 ( 8, 7) [000118] -A-XG------- * ASG ref $VN.Void N004 ( 6, 5) [000117] *---GO-N---- +--* IND ref $102 N003 ( 4, 3) [001137] -------N---- | \--* ADD byref $90 N001 ( 3, 2) [000115] ------------ | +--* LCL_VAR byref V11 loc7 u:1 (last use) $8c N002 ( 1, 1) [001136] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N005 ( 1, 1) [000116] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 optAssertionPropMain morphed tree: N006 ( 8, 7) [000118] -A--GO------ * ASG ref $VN.Void N004 ( 6, 5) [000117] *---GO-N---- +--* IND ref $102 N003 ( 4, 3) [001137] -------N---- | \--* ADD byref $90 N001 ( 3, 2) [000115] ------------ | +--* LCL_VAR byref V11 loc7 u:1 (last use) $8c N002 ( 1, 1) [001136] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N005 ( 1, 1) [000116] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00026, tree [000120], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00026, tree [000121], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00026, tree [000122], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00026, tree [000119], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00026, tree [000123], tree -> 41 VN based non-null prop in BB55: N005 ( 6, 4) [000123] *--X---N---- * IND int $804 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00026, tree [000124], tree -> 0 Re-morphing this stmt: STMT00026 (IL 0x2A4...0x2AA) N006 ( 12, 9) [000124] -A-XG---R--- * ASG int $VN.Void N005 ( 6, 4) [000123] *----O-N---- +--* IND int $804 N004 ( 3, 2) [000119] ------------ | \--* LCL_VAR byref V08 loc4 u:2 (last use) $781 N003 ( 5, 4) [000122] ------------ \--* ADD int $804 N001 ( 3, 2) [000120] ------------ +--* LCL_VAR int V10 loc6 u:1 (last use) $3cc N002 ( 1, 1) [000121] ------------ \--* CNS_INT int 1 $c1 optAssertionPropMain morphed tree: N006 ( 12, 9) [000124] -A--GO--R--- * ASG int $VN.Void N005 ( 6, 4) [000123] *----O-N---- +--* IND int $804 N004 ( 3, 2) [000119] ------------ | \--* LCL_VAR byref V08 loc4 u:2 (last use) $781 N003 ( 5, 4) [000122] ------------ \--* ADD int $804 N001 ( 3, 2) [000120] ------------ +--* LCL_VAR int V10 loc6 u:1 (last use) $3cc N002 ( 1, 1) [000121] ------------ \--* CNS_INT int 1 $c1 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00027, tree [000126], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00027, tree [001140], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00027, tree [001141], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00027, tree [000127], tree -> 3 VN based non-null prop in BB55: N004 ( 4, 4) [000127] ---XG------- * IND int Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00027, tree [000128], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00027, tree [000129], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00027, tree [000125], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00027, tree [001138], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00027, tree [001139], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00027, tree [000130], tree -> 3 VN based non-null prop in BB55: N010 ( 4, 4) [000130] D--XG--N---- * IND int $80a Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00027, tree [000131], tree -> 0 Re-morphing this stmt: STMT00027 (IL 0x2AB...0x2B4) N011 ( 11, 11) [000131] -A-XG---R--- * ASG int $VN.Void N010 ( 4, 4) [000130] n---GO-N---- +--* IND int $80a N009 ( 2, 2) [001139] -------N---- | \--* ADD byref $2a7 N007 ( 1, 1) [000125] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001138] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] $24e N006 ( 6, 6) [000129] ---XG------- \--* ADD int N004 ( 4, 4) [000127] n---GO------ +--* IND int N003 ( 2, 2) [001141] -------N---- | \--* ADD byref $2a7 N001 ( 1, 1) [000126] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001140] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] $24e N005 ( 1, 1) [000128] ------------ \--* CNS_INT int 1 $c1 optAssertionPropMain morphed tree: N011 ( 11, 11) [000131] -A--GO--R--- * ASG int $VN.Void N010 ( 4, 4) [000130] n---GO-N---- +--* IND int $80a N009 ( 2, 2) [001139] -------N---- | \--* ADD byref $2a7 N007 ( 1, 1) [000125] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001138] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] $24e N006 ( 6, 6) [000129] ----GO------ \--* ADD int N004 ( 4, 4) [000127] n---GO------ +--* IND int N003 ( 2, 2) [001141] -------N---- | \--* ADD byref $2a7 N001 ( 1, 1) [000126] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001140] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] $24e N005 ( 1, 1) [000128] ------------ \--* CNS_INT int 1 $c1 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00028, tree [000145], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00028, tree [000146], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00028, tree [000147], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB55, stmt STMT00028, tree [000148], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB56, stmt STMT00030, tree [001143], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB56, stmt STMT00030, tree [001142], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB56, stmt STMT00030, tree [000151], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB56, stmt STMT00030, tree [000152], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB56, stmt STMT00030, tree [000153], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB56, stmt STMT00030, tree [000154], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB56, stmt STMT00030, tree [000155], tree -> 0 Propagating 0000000000000000000003E000070806 assertions for BB56, stmt STMT00030, tree [000156], tree -> 43 Propagating 000000000000000000000BE000070906 assertions for BB57, stmt STMT00031, tree [001145], tree -> 0 Propagating 000000000000000000000BE000070906 assertions for BB57, stmt STMT00031, tree [001144], tree -> 0 Propagating 000000000000000000000BE000070906 assertions for BB57, stmt STMT00031, tree [001146], tree -> 0 Propagating 000000000000000000000BE000070906 assertions for BB57, stmt STMT00031, tree [000158], tree -> 0 Propagating 000000000000000000000BE000070906 assertions for BB57, stmt STMT00031, tree [000159], tree -> 38 Propagating 000000000000000000000BE000070906 assertions for BB57, stmt STMT00031, tree [000157], tree -> 0 Propagating 000000000000000000000BE000070906 assertions for BB57, stmt STMT00031, tree [000160], tree -> 0 Propagating 000000000000000000000BE000070906 assertions for BB57, stmt STMT00031, tree [000161], tree -> 0 Propagating 00000000000000000000000000070806 assertions for BB58, stmt STMT00147, tree [000482], tree -> 0 Propagating 00000000000000000000000000070806 assertions for BB58, stmt STMT00147, tree [000810], tree -> 0 Propagating 00000000000000000000000000000001 assertions for BB59, stmt STMT00086, tree [000812], tree -> 0 Propagating 00000000000000000000000000000001 assertions for BB59, stmt STMT00086, tree [000532], tree -> 0 Propagating 00000000000000000000000000000001 assertions for BB59, stmt STMT00086, tree [000533], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB60, stmt STMT00073, tree [000441], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB60, stmt STMT00073, tree [000442], tree -> 3 VN based non-null prop in BB60: N002 ( 3, 2) [000442] #--X-------- * IND long $2e8 Propagating 000000000000000000000000001F0886 assertions for BB60, stmt STMT00073, tree [000443], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB60, stmt STMT00073, tree [000444], tree -> 0 Re-morphing this stmt: STMT00073 (IL 0x14F...0x150) N004 ( 7, 5) [000444] -A-X----R--- * ASG long $2e8 N003 ( 3, 2) [000443] D------N---- +--* LCL_VAR long V26 tmp12 d:1 $2e7 N002 ( 3, 2) [000442] #----O------ \--* IND long $2e8 N001 ( 1, 1) [000441] !----------- \--* LCL_VAR ref V00 this u:1 $100 optAssertionPropMain morphed tree: N004 ( 7, 5) [000444] -A---O--R--- * ASG long $2e8 N003 ( 3, 2) [000443] D------N---- +--* LCL_VAR long V26 tmp12 d:1 $2e7 N002 ( 3, 2) [000442] #----O------ \--* IND long $2e8 N001 ( 1, 1) [000441] !----------- \--* LCL_VAR ref V00 this u:1 $100 Propagating 000000000000000000000000001F0886 assertions for BB60, stmt STMT00155, tree [000446], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB60, stmt STMT00155, tree [000447], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB60, stmt STMT00155, tree [000448], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB60, stmt STMT00155, tree [000449], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB60, stmt STMT00155, tree [000450], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB60, stmt STMT00155, tree [000451], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB60, stmt STMT00155, tree [000452], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB60, stmt STMT00155, tree [000456], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB60, stmt STMT00155, tree [000459], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB60, stmt STMT00155, tree [000460], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB60, stmt STMT00155, tree [001158], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB61, stmt STMT00156, tree [000466], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB61, stmt STMT00156, tree [000467], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB61, stmt STMT00156, tree [000465], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB61, stmt STMT00156, tree [000464], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB61, stmt STMT00156, tree [000463], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB61, stmt STMT00156, tree [000468], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB61, stmt STMT00156, tree [000462], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB61, stmt STMT00156, tree [000461], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB61, stmt STMT00156, tree [001159], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB61, stmt STMT00156, tree [001160], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB62, stmt STMT00157, tree [000927], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB62, stmt STMT00157, tree [000928], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB62, stmt STMT00157, tree [000445], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB62, stmt STMT00157, tree [000457], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB62, stmt STMT00157, tree [000458], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB62, stmt STMT00157, tree [001161], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB62, stmt STMT00157, tree [001162], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB63, stmt STMT00076, tree [000929], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB63, stmt STMT00076, tree [000930], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB63, stmt STMT00076, tree [000473], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB63, stmt STMT00076, tree [000455], tree -> 0 Propagating 000000000000000000000000001F0886 assertions for BB63, stmt STMT00076, tree [000440], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB64, stmt STMT00053, tree [000296], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB64, stmt STMT00053, tree [000297], tree -> 3 VN based non-null prop in BB64: N002 ( 3, 2) [000297] #--X-------- * IND long $2e8 Propagating 00000000000000000000000000870B06 assertions for BB64, stmt STMT00053, tree [000298], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB64, stmt STMT00053, tree [000299], tree -> 0 Re-morphing this stmt: STMT00053 (IL 0x1BC...0x1BD) N004 ( 7, 5) [000299] -A-X----R--- * ASG long $2e8 N003 ( 3, 2) [000298] D------N---- +--* LCL_VAR long V21 tmp7 d:1 $2e7 N002 ( 3, 2) [000297] #----O------ \--* IND long $2e8 N001 ( 1, 1) [000296] !----------- \--* LCL_VAR ref V00 this u:1 $100 optAssertionPropMain morphed tree: N004 ( 7, 5) [000299] -A---O--R--- * ASG long $2e8 N003 ( 3, 2) [000298] D------N---- +--* LCL_VAR long V21 tmp7 d:1 $2e7 N002 ( 3, 2) [000297] #----O------ \--* IND long $2e8 N001 ( 1, 1) [000296] !----------- \--* LCL_VAR ref V00 this u:1 $100 Propagating 00000000000000000000000000870B06 assertions for BB64, stmt STMT00161, tree [000301], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB64, stmt STMT00161, tree [000302], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB64, stmt STMT00161, tree [000303], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB64, stmt STMT00161, tree [000304], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB64, stmt STMT00161, tree [000305], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB64, stmt STMT00161, tree [000306], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB64, stmt STMT00161, tree [000307], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB64, stmt STMT00161, tree [000311], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB64, stmt STMT00161, tree [000314], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB64, stmt STMT00161, tree [000315], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB64, stmt STMT00161, tree [001168], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB65, stmt STMT00162, tree [000321], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB65, stmt STMT00162, tree [000322], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB65, stmt STMT00162, tree [000320], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB65, stmt STMT00162, tree [000319], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB65, stmt STMT00162, tree [000318], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB65, stmt STMT00162, tree [000323], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB65, stmt STMT00162, tree [000317], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB65, stmt STMT00162, tree [000316], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB65, stmt STMT00162, tree [001169], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB65, stmt STMT00162, tree [001170], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB66, stmt STMT00163, tree [001003], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB66, stmt STMT00163, tree [001004], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB66, stmt STMT00163, tree [000300], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB66, stmt STMT00163, tree [000312], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB66, stmt STMT00163, tree [000313], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB66, stmt STMT00163, tree [001171], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB66, stmt STMT00163, tree [001172], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB67, stmt STMT00056, tree [001005], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB67, stmt STMT00056, tree [001006], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB67, stmt STMT00056, tree [000328], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB67, stmt STMT00056, tree [000310], tree -> 0 Propagating 00000000000000000000000000870B06 assertions for BB67, stmt STMT00056, tree [000295], tree -> 0 Propagating 00000000000000000000000000070806 assertions for BB68, stmt STMT00043, tree [000233], tree -> 0 *************** In fgDebugCheckBBlist *************** Finishing PHASE Assertion prop *************** Starting PHASE Optimize index checks *************** In OptimizeRangeChecks() Blocks/trees before phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal Loop1 gcsafe BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe BB36 [0108] 1 BB34 1 [???..???) i gcsafe BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen BB54 [0044] 2 BB48,BB53 0.50 [261..276) i BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} ***** BB01 STMT00000 (IL 0x000...0x006) N004 ( 5, 5) [000003] ------------ * JTRUE void N003 ( 3, 3) [000002] J------N---- \--* EQ int $180 N001 ( 1, 1) [000000] ------------ +--* LCL_VAR ref V01 arg1 u:1 $101 N002 ( 1, 1) [000001] ------------ \--* CNS_INT ref null $VN.Null ------------ BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00001 (IL 0x00E...0x014) N007 ( 8, 8) [000008] ---XG------- * JTRUE void N006 ( 6, 6) [000007] J--XG--N---- \--* NE int N004 ( 4, 4) [000005] ---XG------- +--* IND ref N003 ( 2, 2) [000814] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000004] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000813] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] $240 N005 ( 1, 1) [000006] ------------ \--* CNS_INT ref null $VN.Null ------------ BB03 [016..01E), preds={BB02} succs={BB04} ***** BB03 STMT00085 (IL ???... ???) N005 ( 16, 10) [000528] --CXG------- * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize $1c2 N003 ( 1, 1) [000526] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N004 ( 1, 1) [000527] ------------ arg1 in rdx \--* CNS_INT int 0 $c0 ------------ BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ***** BB04 STMT00088 (IL 0x01E... ???) N008 ( 9, 6) [000544] -A--GO--R--- * ASG bool N007 ( 1, 1) [000543] D------N---- +--* LCL_VAR int V33 tmp19 d:1 N006 ( 9, 6) [000012] N---GO------ \--* NE int N004 ( 4, 4) [000010] n---GO------ +--* IND ref N003 ( 2, 2) [000818] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000009] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000817] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] $240 N005 ( 1, 1) [000011] ------------ \--* CNS_INT ref null $VN.Null ***** BB04 STMT00091 (IL 0x01E... ???) N008 ( 5, 13) [000554] -A--G---R--- * ASG ref $105 N007 ( 1, 1) [000553] D------N---- +--* LCL_VAR ref V34 tmp20 d:1 $105 N006 ( 5, 13) [001293] -A--G------- \--* COMMA ref $105 N004 ( 4, 12) [001291] -A--G---R--- +--* ASG ref $VN.Void N003 ( 1, 1) [001290] D------N---- | +--* LCL_VAR ref V73 cse8 d:1 $105 N002 ( 4, 12) [000538] #---G------- | \--* IND ref $105 N001 ( 2, 10) [000537] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 N005 ( 1, 1) [001292] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB04 STMT00092 (IL 0x01E... ???) N003 ( 1, 3) [000556] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000555] D------N---- +--* LCL_VAR ref V35 tmp21 d:1 $105 N001 ( 1, 1) [001294] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB04 STMT00089 (IL 0x01E... ???) N004 ( 5, 5) [000549] ------------ * JTRUE void N003 ( 3, 3) [000548] J------N---- \--* NE int N001 ( 1, 1) [000546] ------------ +--* LCL_VAR int V33 tmp19 u:1 (last use) N002 ( 1, 1) [000547] ------------ \--* CNS_INT int 0 $c0 ------------ BB05 [01E..01F), preds={BB04} succs={BB06} ***** BB05 STMT00090 (IL 0x01E... ???) N005 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 1, 1) [000550] ------------ arg0 in rcx +--* LCL_VAR ref V35 tmp21 u:1 (last use) $105 N004 ( 1, 1) [000551] ------------ arg1 in rdx \--* LCL_VAR ref V35 tmp21 u:1 (last use) $105 ------------ BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} ***** BB06 STMT00003 (IL 0x02C... ???) N006 ( 4, 4) [000018] -A--GO--R--- * ASG ref N005 ( 1, 1) [000017] D------N---- +--* LCL_VAR ref V04 loc0 d:1 N004 ( 4, 4) [000016] n---GO------ \--* IND ref N003 ( 2, 2) [000822] -------N---- \--* ADD byref $281 N001 ( 1, 1) [000015] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000821] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] $241 ***** BB06 STMT00094 (IL 0x033... ???) N005 ( 6, 3) [000566] -A------R--- * ASG bool N004 ( 1, 1) [000565] D------N---- +--* LCL_VAR int V36 tmp22 d:1 N003 ( 6, 3) [000021] N----------- \--* NE int N001 ( 1, 1) [000019] ------------ +--* LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000020] ------------ \--* CNS_INT ref null $VN.Null ***** BB06 STMT00097 (IL 0x033... ???) N003 ( 1, 3) [000576] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000575] D------N---- +--* LCL_VAR ref V37 tmp23 d:1 $105 N001 ( 1, 1) [001295] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB06 STMT00095 (IL 0x033... ???) N004 ( 5, 5) [000571] ------------ * JTRUE void N003 ( 3, 3) [000570] J------N---- \--* NE int N001 ( 1, 1) [000568] ------------ +--* LCL_VAR int V36 tmp22 u:1 (last use) N002 ( 1, 1) [000569] ------------ \--* CNS_INT int 0 $c0 ------------ BB07 [033..034), preds={BB06} succs={BB08} ***** BB07 STMT00096 (IL 0x033... ???) N006 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N004 ( 4, 12) [000824] #---G------- arg0 in rcx +--* IND ref $106 N003 ( 2, 10) [000823] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" $46 N005 ( 1, 1) [000573] ------------ arg1 in rdx \--* LCL_VAR ref V37 tmp23 u:1 (last use) $105 ------------ BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} ***** BB08 STMT00005 (IL 0x041... ???) N006 ( 4, 4) [000028] -A--GO--R--- * ASG ref N005 ( 1, 1) [000027] D------N---- +--* LCL_VAR ref V05 loc1 d:1 N004 ( 4, 4) [000026] n---GO------ \--* IND ref N003 ( 2, 2) [000828] -------N---- \--* ADD byref $282 N001 ( 1, 1) [000025] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000827] ------------ \--* CNS_INT long 24 field offset Fseq[_comparer] $242 ***** BB08 STMT00006 (IL 0x048...0x049) N004 ( 5, 5) [000032] ------------ * JTRUE void N003 ( 3, 3) [000031] J------N---- \--* EQ int N001 ( 1, 1) [000029] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000030] ------------ \--* CNS_INT ref null $VN.Null ------------ BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} ***** BB09 STMT00079 (IL 0x04B...0x052) N004 ( 3, 3) [000489] -A---O--R--- * ASG long $2e8 N003 ( 1, 1) [000488] D------N---- +--* LCL_VAR long V29 tmp15 d:1 $2e7 N002 ( 3, 2) [000487] #----O------ \--* IND long $2e8 N001 ( 1, 1) [000486] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB09 STMT00149 (IL ???... ???) N015 ( 21, 18) [001148] -A---------- * JTRUE void N014 ( 19, 16) [000505] JA-----N---- \--* EQ int N012 ( 17, 14) [001268] -A---------- +--* COMMA long N010 ( 14, 12) [001266] -A------R--- | +--* ASG long $VN.Void N009 ( 3, 2) [001265] D------N---- | | +--* LCL_VAR long V68 cse3 d:1 N008 ( 10, 9) [000501] n----------- | | \--* IND long N007 ( 8, 7) [000497] -------N---- | | \--* ADD long $307 N005 ( 7, 6) [000495] #----------- | | +--* IND long $2ea N004 ( 4, 4) [000494] #----------- | | | \--* IND long $2e9 N003 ( 2, 2) [000493] -------N---- | | | \--* ADD long $306 N001 ( 1, 1) [000491] ------------ | | | +--* LCL_VAR long V29 tmp15 u:1 $2e7 N002 ( 1, 1) [000492] ------------ | | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000496] ------------ | | \--* CNS_INT long 64 $245 N011 ( 3, 2) [001267] ------------ | \--* LCL_VAR long V68 cse3 u:1 N013 ( 1, 1) [000504] ------------ \--* CNS_INT long 0 $243 ------------ BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} ***** BB10 STMT00150 (IL ???... ???) N003 ( 3, 3) [001150] -A------R--- * ASG long N002 ( 1, 1) [001149] D------N---- +--* LCL_VAR long V31 tmp17 d:3 N001 ( 3, 2) [001269] ------------ \--* LCL_VAR long V68 cse3 u:1 ------------ BB11 [???..???), preds={BB09} succs={BB12} ***** BB11 STMT00151 (IL ???... ???) N007 ( 17, 18) [001152] -AC-G---R--- * ASG long $308 N006 ( 1, 1) [001151] D------N---- +--* LCL_VAR long V31 tmp17 d:2 $308 N005 ( 17, 18) [000503] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $308 N003 ( 1, 1) [000490] ------?----- arg0 in rcx +--* LCL_VAR long V29 tmp15 u:1 (last use) $2e7 N004 ( 2, 10) [000502] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $49 ------------ BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} ***** BB12 STMT00178 (IL ???... ???) N005 ( 0, 0) [001217] -A------R--- * ASG long N004 ( 0, 0) [001215] D------N---- +--* LCL_VAR long V31 tmp17 d:1 N003 ( 0, 0) [001216] ------------ \--* PHI long N001 ( 0, 0) [001247] ------------ pred BB10 +--* PHI_ARG long V31 tmp17 u:3 N002 ( 0, 0) [001246] ------------ pred BB11 \--* PHI_ARG long V31 tmp17 u:2 $308 ***** BB12 STMT00083 (IL ???... ???) N010 ( 31, 15) [000524] -ACXG---R--- * ASG int $1c7 N009 ( 3, 2) [000523] D------N---- +--* LCL_VAR int V15 tmp1 d:3 $1c7 N008 ( 27, 12) [000522] --CXG------- \--* CALL ind stub int $1c7 N007 ( 1, 1) [000521] ------------ calli tgt \--* LCL_VAR long V31 tmp17 u:1 (last use) $342 N004 ( 1, 1) [000484] ------------ this in rcx +--* LCL_VAR ref V05 loc1 u:1 N005 ( 1, 1) [000831] ------------ arg1 in r11 +--* LCL_VAR long V31 tmp17 u:1 r11 REG r11 $342 N006 ( 1, 1) [000500] ------------ arg2 in rdx \--* LCL_VAR ref V01 arg1 u:1 $101 ------------ BB13 [054..061), preds={BB08} succs={BB14} ***** BB13 STMT00007 (IL 0x054...0x05C) N013 ( 34, 21) [000038] -ACXGO--R--- * ASG int $1c5 N012 ( 3, 2) [000037] D------N---- +--* LCL_VAR int V15 tmp1 d:2 $1c5 N011 ( 30, 18) [000035] --CXGO------ \--* CALLV vt-ind int System.Object.GetHashCode $1c5 N010 ( 9, 8) [000843] n----O------ control expr \--* IND long N009 ( 7, 6) [000842] -----O-N---- \--* ADD long $303 N007 ( 6, 5) [000840] #----O------ +--* IND long $2e6 N006 ( 4, 3) [000839] -----O-N---- | \--* ADD long $301 N004 ( 3, 2) [000837] #----O------ | +--* IND long $2e4 N003 ( 1, 1) [000836] ------------ | | \--* LCL_VAR ref V01 arg1 u:1 $101 N005 ( 1, 1) [000838] ------------ | \--* CNS_INT int 72 $c9 N008 ( 1, 1) [000841] ------------ \--* CNS_INT int 24 $ca N002 ( 1, 1) [000033] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 $101 ------------ BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ***** BB14 STMT00177 (IL ???... ???) N005 ( 0, 0) [001214] -A------R--- * ASG int N004 ( 0, 0) [001212] D------N---- +--* LCL_VAR int V15 tmp1 d:1 N003 ( 0, 0) [001213] ------------ \--* PHI int N001 ( 0, 0) [001245] ------------ pred BB12 +--* PHI_ARG int V15 tmp1 u:3 $1c7 N002 ( 0, 0) [001244] ------------ pred BB13 \--* PHI_ARG int V15 tmp1 u:2 $1c5 ***** BB14 STMT00008 (IL ???...0x061) N003 ( 3, 3) [000042] -A------R--- * ASG int $3c0 N002 ( 1, 1) [000041] D------N---- +--* LCL_VAR int V06 loc2 d:1 $3c0 N001 ( 3, 2) [000040] ------------ \--* LCL_VAR int V15 tmp1 u:1 (last use) $3c0 ***** BB14 STMT00009 (IL 0x062...0x063) N003 ( 1, 3) [000045] -A------R--- * ASG int $c0 N002 ( 1, 1) [000044] D------N---- +--* LCL_VAR int V07 loc3 d:1 $c0 N001 ( 1, 1) [000043] ------------ \--* CNS_INT int 0 $c0 ***** BB14 STMT00098 (IL 0x064... ???) N006 ( 4, 4) [000580] -A--GO--R--- * ASG ref N005 ( 1, 1) [000579] D------N---- +--* LCL_VAR ref V39 tmp25 d:1 N004 ( 4, 4) [000578] n---GO------ \--* IND ref N003 ( 2, 2) [000845] -------N---- \--* ADD byref $280 N001 ( 1, 1) [000046] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000844] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] $240 ***** BB14 STMT00105 (IL 0x064... ???) N004 ( 3, 3) [000629] -A-X----R--- * ASG int N003 ( 1, 1) [000628] D------N---- +--* LCL_VAR int V40 tmp26 d:1 N002 ( 3, 3) [000583] ---X-------- \--* ARR_LENGTH int N001 ( 1, 1) [000582] ------------ \--* LCL_VAR ref V39 tmp25 u:1 ***** BB14 STMT00106 (IL 0x064... ???) N006 ( 4, 4) [000631] -A--GO--R--- * ASG long N005 ( 1, 1) [000630] D------N---- +--* LCL_VAR long V41 tmp27 d:1 N004 ( 4, 4) [000585] n---GO------ \--* IND long N003 ( 2, 2) [000847] -------N---- \--* ADD byref $283 N001 ( 1, 1) [000584] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000846] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 ***** BB14 STMT00108 (IL 0x064... ???) N005 ( 6, 6) [000642] -A------R--- * ASG bool N004 ( 1, 1) [000641] D------N---- +--* LCL_VAR int V43 tmp29 d:1 N003 ( 6, 6) [000599] N--------U-- \--* LE int N001 ( 1, 1) [000597] ------------ +--* LCL_VAR int V40 tmp26 u:1 N002 ( 1, 4) [000598] ------------ \--* CNS_INT int 0x7FFFFFFF $ce ***** BB14 STMT00111 (IL 0x064... ???) N003 ( 1, 3) [000652] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000651] D------N---- +--* LCL_VAR ref V44 tmp30 d:1 $105 N001 ( 1, 1) [001296] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB14 STMT00112 (IL 0x064... ???) N003 ( 1, 3) [000654] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000653] D------N---- +--* LCL_VAR ref V45 tmp31 d:1 $105 N001 ( 1, 1) [001297] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB14 STMT00109 (IL 0x064... ???) N004 ( 5, 5) [000647] ------------ * JTRUE void N003 ( 3, 3) [000646] J------N---- \--* NE int N001 ( 1, 1) [000644] ------------ +--* LCL_VAR int V43 tmp29 u:1 (last use) N002 ( 1, 1) [000645] ------------ \--* CNS_INT int 0 $c0 ------------ BB15 [064..065), preds={BB14} succs={BB16} ***** BB15 STMT00110 (IL 0x064... ???) N005 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 1, 1) [000648] ------------ arg0 in rcx +--* LCL_VAR ref V45 tmp31 u:1 (last use) $105 N004 ( 1, 1) [000649] ------------ arg1 in rdx \--* LCL_VAR ref V45 tmp31 u:1 (last use) $105 ------------ BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} ***** BB16 STMT00103 (IL 0x064... ???) N016 ( 20, 21) [000619] -A------R--- * ASG int N015 ( 1, 1) [000618] D------N---- +--* LCL_VAR int V42 tmp28 d:1 N014 ( 20, 21) [000617] ------------ \--* CAST int <- uint <- long N013 ( 19, 19) [000616] ------------ \--* RSZ long N011 ( 17, 17) [000614] ------------ +--* MUL long N008 ( 11, 11) [000611] ------------ | +--* ADD long N006 ( 9, 9) [000608] ------------ | | +--* RSZ long N004 ( 7, 7) [000606] ------------ | | | +--* MUL long N001 ( 1, 1) [000604] ------------ | | | | +--* LCL_VAR long V41 tmp27 u:1 (last use) N003 ( 2, 3) [000605] ---------U-- | | | | \--* CAST long <- ulong <- uint $310 N002 ( 1, 1) [000047] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 $3c0 N005 ( 1, 1) [000607] ------------ | | | \--* CNS_INT int 32 $d2 N007 ( 1, 1) [000610] ------------ | | \--* CNS_INT long 1 $247 N010 ( 2, 3) [000613] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000612] ------------ | \--* LCL_VAR int V40 tmp26 u:1 N012 ( 1, 1) [000615] ------------ \--* CNS_INT int 32 $d2 ***** BB16 STMT00114 (IL 0x064... ???) N007 ( 27, 7) [000665] -A-X----R--- * ASG bool N006 ( 1, 1) [000664] D------N---- +--* LCL_VAR int V46 tmp32 d:1 N005 ( 27, 7) [000624] ---X-------- \--* EQ int N003 ( 22, 5) [000623] ---X-------- +--* UMOD int N001 ( 1, 1) [000621] ------------ | +--* LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000622] ------------ | \--* LCL_VAR int V40 tmp26 u:1 (last use) N004 ( 1, 1) [000620] ------------ \--* LCL_VAR int V42 tmp28 u:1 ***** BB16 STMT00117 (IL 0x064... ???) N003 ( 1, 3) [000675] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000674] D------N---- +--* LCL_VAR ref V47 tmp33 d:1 $105 N001 ( 1, 1) [001298] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB16 STMT00118 (IL 0x064... ???) N003 ( 1, 3) [000677] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000676] D------N---- +--* LCL_VAR ref V48 tmp34 d:1 $105 N001 ( 1, 1) [001299] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB16 STMT00115 (IL 0x064... ???) N004 ( 5, 5) [000670] ------------ * JTRUE void N003 ( 3, 3) [000669] J------N---- \--* NE int N001 ( 1, 1) [000667] ------------ +--* LCL_VAR int V46 tmp32 u:1 (last use) N002 ( 1, 1) [000668] ------------ \--* CNS_INT int 0 $c0 ------------ BB17 [064..065), preds={BB16} succs={BB18} ***** BB17 STMT00116 (IL 0x064... ???) N005 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 1, 1) [000671] ------------ arg0 in rcx +--* LCL_VAR ref V48 tmp34 u:1 (last use) $105 N004 ( 1, 1) [000672] ------------ arg1 in rdx \--* LCL_VAR ref V48 tmp34 u:1 (last use) $105 ------------ BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} ***** BB18 STMT00100 (IL 0x064... ???) N017 ( 19, 24) [000591] -A-XG---R--- * ASG byref N016 ( 1, 1) [000590] D------N---- +--* LCL_VAR byref V38 tmp24 d:1 $81 N015 ( 19, 24) [000862] ---XG------- \--* COMMA byref N004 ( 8, 11) [000855] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000627] ------------ | +--* LCL_VAR int V42 tmp28 u:1 N003 ( 3, 3) [000854] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000581] ------------ | \--* LCL_VAR ref V39 tmp25 u:1 N014 ( 11, 13) [000863] ----G------- \--* ADDR byref $81 N013 ( 6, 7) [000588] a---G--N---- \--* IND int N012 ( 5, 6) [000861] -------N---- \--* ADD byref $81 N005 ( 1, 1) [000852] ------------ +--* LCL_VAR ref V39 tmp25 u:1 (last use) N011 ( 4, 5) [000860] -------N---- \--* ADD long N009 ( 3, 4) [000858] -------N---- +--* LSH long N007 ( 2, 3) [000856] ------------ | +--* CAST long <- int N006 ( 1, 1) [000853] i----------- | | \--* LCL_VAR int V42 tmp28 u:1 (last use) N008 ( 1, 1) [000857] -------N---- | \--* CNS_INT long 2 $248 N010 ( 1, 1) [000859] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB18 STMT00011 (IL ???... ???) N003 ( 5, 4) [000051] -A------R--- * ASG byref $81 N002 ( 3, 2) [000050] D------N---- +--* LCL_VAR byref V08 loc4 d:1 $81 N001 ( 1, 1) [000592] ------------ \--* LCL_VAR byref V38 tmp24 u:1 $81 ***** BB18 STMT00012 (IL 0x06D...0x072) N006 ( 5, 4) [000057] -A-XG---R--- * ASG int N005 ( 1, 1) [000056] D------N---- +--* LCL_VAR int V09 loc5 d:1 N004 ( 5, 4) [000055] ---XG------- \--* ADD int N002 ( 3, 2) [000053] *--XG------- +--* IND int N001 ( 1, 1) [000052] ------------ | \--* LCL_VAR byref V08 loc4 u:1 (last use) $81 N003 ( 1, 1) [000054] ------------ \--* CNS_INT int -1 $c4 ***** BB18 STMT00013 (IL 0x074...0x075) N004 ( 5, 5) [000061] ------------ * JTRUE void N003 ( 3, 3) [000060] J------N---- \--* NE int N001 ( 1, 1) [000058] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000059] ------------ \--* CNS_INT ref null $VN.Null ------------ BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} ***** BB19 STMT00059 (IL 0x0FF...0x104) N004 ( 3, 3) [000356] -A---O--R--- * ASG long $2e8 N003 ( 1, 1) [000355] D------N---- +--* LCL_VAR long V24 tmp10 d:1 $2e7 N002 ( 3, 2) [000354] #----O------ \--* IND long $2e8 N001 ( 1, 1) [000353] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB19 STMT00152 (IL ???... ???) N015 ( 21, 18) [001153] -A---------- * JTRUE void N014 ( 19, 16) [000369] JA-----N---- \--* EQ int N012 ( 17, 14) [001273] -A---------- +--* COMMA long N010 ( 14, 12) [001271] -A------R--- | +--* ASG long $VN.Void N009 ( 3, 2) [001270] D------N---- | | +--* LCL_VAR long V69 cse4 d:1 N008 ( 10, 9) [000365] n----------- | | \--* IND long N007 ( 8, 7) [000364] -------N---- | | \--* ADD long $324 N005 ( 7, 6) [000362] #----------- | | +--* IND long $2ea N004 ( 4, 4) [000361] #----------- | | | \--* IND long $2e9 N003 ( 2, 2) [000360] -------N---- | | | \--* ADD long $306 N001 ( 1, 1) [000358] ------------ | | | +--* LCL_VAR long V24 tmp10 u:1 $2e7 N002 ( 1, 1) [000359] ------------ | | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000363] ------------ | | \--* CNS_INT long 32 $24a N011 ( 3, 2) [001272] ------------ | \--* LCL_VAR long V69 cse4 u:1 N013 ( 1, 1) [000368] ------------ \--* CNS_INT long 0 $243 ------------ BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} ***** BB20 STMT00153 (IL ???... ???) N003 ( 7, 5) [001155] -A------R--- * ASG long N002 ( 3, 2) [001154] D------N---- +--* LCL_VAR long V25 tmp11 d:3 N001 ( 3, 2) [001274] ------------ \--* LCL_VAR long V69 cse4 u:1 ------------ BB21 [???..???), preds={BB19} succs={BB22} ***** BB21 STMT00154 (IL ???... ???) N007 ( 21, 21) [001157] -AC-G---R--- * ASG long $325 N006 ( 3, 2) [001156] D------N---- +--* LCL_VAR long V25 tmp11 d:2 $325 N005 ( 17, 18) [000367] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $325 N003 ( 1, 1) [000357] ------?----- arg0 in rcx +--* LCL_VAR long V24 tmp10 u:1 (last use) $2e7 N004 ( 2, 10) [000366] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $4f ------------ BB22 [???..106), preds={BB20,BB21} succs={BB23} ***** BB22 STMT00172 (IL ???... ???) N005 ( 0, 0) [001199] -A------R--- * ASG long N004 ( 0, 0) [001197] D------N---- +--* LCL_VAR long V25 tmp11 d:1 N003 ( 0, 0) [001198] ------------ \--* PHI long N001 ( 0, 0) [001243] ------------ pred BB20 +--* PHI_ARG long V25 tmp11 u:3 N002 ( 0, 0) [001242] ------------ pred BB21 \--* PHI_ARG long V25 tmp11 u:2 $325 ***** BB22 STMT00062 (IL ???... ???) N005 ( 17, 8) [000386] -ACXG---R--- * ASG ref $223 N004 ( 1, 1) [000385] D------N---- +--* LCL_VAR ref V12 loc8 d:1 $223 N003 ( 17, 8) [000352] --CXG------- \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default $223 N002 ( 3, 2) [000382] ------------ arg0 in rcx \--* LCL_VAR long V25 tmp11 u:1 (last use) $344 ------------ BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} ***** BB23 STMT00165 (IL ???... ???) N005 ( 0, 0) [001178] -A------R--- * ASG int N004 ( 0, 0) [001176] D------N---- +--* LCL_VAR int V07 loc3 d:5 N003 ( 0, 0) [001177] ------------ \--* PHI int N001 ( 0, 0) [001238] ------------ pred BB27 +--* PHI_ARG int V07 loc3 u:6 N002 ( 0, 0) [001235] ------------ pred BB22 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB23 STMT00164 (IL ???... ???) N005 ( 0, 0) [001175] -A------R--- * ASG int N004 ( 0, 0) [001173] D------N---- +--* LCL_VAR int V09 loc5 d:4 N003 ( 0, 0) [001174] ------------ \--* PHI int N001 ( 0, 0) [001239] ------------ pred BB27 +--* PHI_ARG int V09 loc5 u:5 N002 ( 0, 0) [001236] ------------ pred BB22 \--* PHI_ARG int V09 loc5 u:1 ***** BB23 STMT00063 (IL 0x106...0x10B) N009 ( 8, 8) [000391] -A-X-------- * JTRUE void N008 ( 6, 6) [000390] NA-X---N-U-- \--* LE int N006 ( 4, 4) [001318] -A-X-------- +--* COMMA int N004 ( 3, 3) [001316] -A-X----R--- | +--* ASG int $VN.Void N003 ( 1, 1) [001315] D------N---- | | +--* LCL_VAR int V76 cse11 N002 ( 3, 3) [000389] ---X-------- | | \--* ARR_LENGTH int N001 ( 1, 1) [000388] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N005 ( 1, 1) [001317] ------------ | \--* LCL_VAR int V76 cse11 N007 ( 1, 1) [000387] ------------ \--* LCL_VAR int V09 loc5 u:4 $3c2 ------------ BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} ***** BB24 STMT00064 (IL 0x110...0x11E) N026 ( 31, 31) [000399] -A-XG------- * JTRUE void N025 ( 29, 29) [000398] NA-XG--N-U-- \--* NE int N023 ( 27, 27) [000396] *A-XG------- +--* IND int N022 ( 25, 25) [000868] -A--G--N---- | \--* ADD byref $28c N020 ( 24, 24) [001251] -A--G------- | +--* COMMA byref N018 ( 23, 23) [001249] -A--G---R--- | | +--* ASG byref $VN.Void N017 ( 1, 1) [001248] D------N---- | | | +--* LCL_VAR byref V65 cse0 d:1 N016 ( 23, 23) [000882] -A--G--N---- | | | \--* ADDR byref $82 N015 ( 12, 12) [000394] aA--G--N---- | | | \--* IND struct N014 ( 11, 11) [000878] -A-----N---- | | | \--* ADD byref $82 N001 ( 1, 1) [000869] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 10, 10) [000877] -A-----N---- | | | \--* ADD long $329 N011 ( 9, 9) [000875] -A-----N---- | | | +--* LSH long $328 N009 ( 8, 8) [001278] -A---------- | | | | +--* COMMA long $327 N007 ( 7, 7) [001276] -A------R--- | | | | | +--* ASG long $VN.Void N006 ( 1, 1) [001275] D------N---- | | | | | | +--* LCL_VAR long V70 cse5 d:1 $327 N005 ( 7, 7) [000881] ------------ | | | | | | \--* MUL long $327 N003 ( 2, 3) [000873] ------------ | | | | | | +--* CAST long <- int $326 N002 ( 1, 1) [000870] i----------- | | | | | | | \--* LCL_VAR int V09 loc5 u:4 $3c2 N004 ( 1, 1) [000880] ------------ | | | | | | \--* CNS_INT long 3 $24b N008 ( 1, 1) [001277] ------------ | | | | | \--* LCL_VAR long V70 cse5 u:1 $327 N010 ( 1, 1) [000874] -------N---- | | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000876] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N019 ( 1, 1) [001250] ------------ | | \--* LCL_VAR byref V65 cse0 u:1 N021 ( 1, 1) [000867] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N024 ( 1, 1) [000397] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 ------------ BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} ***** BB25 STMT00069 (IL 0x120...0x135) N027 ( 47, 36) [000428] --CXG------- * JTRUE void N026 ( 45, 34) [000427] J-CXG--N---- \--* NE int $1bd N024 ( 43, 32) [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals $581 N023 ( 9, 8) [000908] n--X-------- control expr | \--* IND long N022 ( 7, 6) [000907] ---X---N---- | \--* ADD long $32e N020 ( 6, 5) [000905] #--X-------- | +--* IND long $465 N019 ( 4, 3) [000904] ---X---N---- | | \--* ADD long $32c N017 ( 3, 2) [000902] #--X-------- | | +--* IND long $463 N016 ( 1, 1) [000901] ------------ | | | \--* LCL_VAR ref V12 loc8 u:1 $223 N018 ( 1, 1) [000903] ------------ | | \--* CNS_INT int 72 $c9 N021 ( 1, 1) [000906] ------------ | \--* CNS_INT int 32 $d2 N013 ( 12, 11) [000897] *---G--N---- arg1 in rdx | +--* IND ref N012 ( 9, 9) [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] $84 N011 ( 5, 5) [000421] a---G--N---- | | \--* IND struct N010 ( 4, 4) [000892] -------N---- | | \--* ADD byref $82 N004 ( 1, 1) [000883] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N009 ( 3, 3) [000891] -------N---- | | \--* ADD long $329 N007 ( 2, 2) [000889] -------N---- | | +--* LSH long $328 N005 ( 1, 1) [001279] ------------ | | | +--* LCL_VAR long V70 cse5 u:1 $327 N006 ( 1, 1) [000888] -------N---- | | | \--* CNS_INT long 3 $24b N008 ( 1, 1) [000890] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N014 ( 1, 1) [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 u:1 $223 N015 ( 1, 1) [000424] ------------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 u:1 $101 N025 ( 1, 1) [000426] ------------ \--* CNS_INT int 0 $c0 ------------ BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} ***** BB26 STMT00065 (IL 0x157...0x164) N006 ( 4, 4) [000406] -A-XG---R--- * ASG int N005 ( 1, 1) [000405] D------N---- +--* LCL_VAR int V09 loc5 d:5 N004 ( 4, 4) [000404] *--XG------- \--* IND int N003 ( 2, 2) [000932] ----G--N---- \--* ADD byref $28e N001 ( 1, 1) [001252] ------------ +--* LCL_VAR byref V65 cse0 u:1 $82 N002 ( 1, 1) [000931] ------------ \--* CNS_INT long 20 field offset Fseq[next] $24c ***** BB26 STMT00066 (IL 0x166...0x169) N005 ( 3, 3) [000411] -A------R--- * ASG int $605 N004 ( 1, 1) [000410] D------N---- +--* LCL_VAR int V07 loc3 d:6 $605 N003 ( 3, 3) [000409] ------------ \--* ADD int $605 N001 ( 1, 1) [000407] ------------ +--* LCL_VAR int V07 loc3 u:5 (last use) $3c1 N002 ( 1, 1) [000408] ------------ \--* CNS_INT int 1 $c1 ***** BB26 STMT00067 (IL 0x16A...0x16E) N004 ( 5, 5) [000416] ------------ * JTRUE void N003 ( 3, 3) [000415] N------N-U-- \--* LT int N001 ( 1, 1) [001321] ------------ +--* LCL_VAR int V76 cse11 N002 ( 1, 1) [000412] ------------ \--* LCL_VAR int V07 loc3 u:6 $605 ------------ BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} ------------ BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} ***** BB28 STMT00070 (IL 0x137...0x139) N005 ( 7, 8) [000432] ------------ * JTRUE void N004 ( 5, 6) [000431] N------N-U-- \--* NE int $1bf N002 ( 3, 4) [000909] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000429] ------------ | \--* LCL_VAR int V03 arg3 u:1 $140 N003 ( 1, 1) [000430] ------------ \--* CNS_INT int 1 $c1 ------------ BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} ***** BB29 STMT00077 (IL 0x13B...0x144) N006 ( 6, 6) [000481] -A-XG------- * ASG ref $VN.Void N004 ( 4, 4) [000480] *--XG--N---- +--* IND ref $102 N003 ( 2, 2) [000911] ----G--N---- | \--* ADD byref $28d N001 ( 1, 1) [001253] ------------ | +--* LCL_VAR byref V65 cse0 u:1 $82 N002 ( 1, 1) [000910] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N005 ( 1, 1) [000479] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 ------------ BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} ***** BB30 STMT00071 (IL 0x14B...0x14D) N005 ( 7, 8) [000436] ------------ * JTRUE void N004 ( 5, 6) [000435] N------N-U-- \--* EQ int $600 N002 ( 3, 4) [000926] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000433] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) $140 N003 ( 1, 1) [000434] ------------ \--* CNS_INT int 2 $c2 ------------ BB31 [???..???) (return), preds={BB30,BB41} succs={} ***** BB31 STMT00148 (IL ???... ???) N002 ( 2, 2) [000811] ------------ * RETURN int $1f3 N001 ( 1, 1) [000437] ------------ \--* CNS_INT int 0 $c0 ------------ BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} ***** BB32 STMT00175 (IL ???... ???) N005 ( 0, 0) [001208] -A------R--- * ASG int N004 ( 0, 0) [001206] D------N---- +--* LCL_VAR int V07 loc3 d:3 N003 ( 0, 0) [001207] ------------ \--* PHI int N001 ( 0, 0) [001229] ------------ pred BB43 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [001218] ------------ pred BB18 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB32 STMT00174 (IL ???... ???) N005 ( 0, 0) [001205] -A------R--- * ASG int N004 ( 0, 0) [001203] D------N---- +--* LCL_VAR int V09 loc5 d:2 N003 ( 0, 0) [001204] ------------ \--* PHI int N001 ( 0, 0) [001230] ------------ pred BB43 +--* PHI_ARG int V09 loc5 u:3 N002 ( 0, 0) [001219] ------------ pred BB18 \--* PHI_ARG int V09 loc5 u:1 ***** BB32 STMT00014 (IL 0x177...0x17C) N009 ( 8, 8) [000066] -A-X-------- * JTRUE void N008 ( 6, 6) [000065] NA-X---N-U-- \--* LE int N006 ( 4, 4) [001325] -A-X-------- +--* COMMA int N004 ( 3, 3) [001323] -A-X----R--- | +--* ASG int $VN.Void N003 ( 1, 1) [001322] D------N---- | | +--* LCL_VAR int V76 cse11 N002 ( 3, 3) [000064] ---X-------- | | \--* ARR_LENGTH int N001 ( 1, 1) [000063] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N005 ( 1, 1) [001324] ------------ | \--* LCL_VAR int V76 cse11 N007 ( 1, 1) [000062] ------------ \--* LCL_VAR int V09 loc5 u:2 $3c4 ------------ BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} ***** BB33 STMT00039 (IL 0x17E...0x18C) N026 ( 31, 31) [000215] -A-XG------- * JTRUE void N025 ( 29, 29) [000214] NA-XG--N-U-- \--* NE int N023 ( 27, 27) [000212] *A-XG------- +--* IND int N022 ( 25, 25) [000948] -A--G--N---- | \--* ADD byref $2ac N020 ( 24, 24) [001257] -A--G------- | +--* COMMA byref N018 ( 23, 23) [001255] -A--G---R--- | | +--* ASG byref $VN.Void N017 ( 1, 1) [001254] D------N---- | | | +--* LCL_VAR byref V66 cse1 d:1 N016 ( 23, 23) [000962] -A--G--N---- | | | \--* ADDR byref $91 N015 ( 12, 12) [000210] aA--G--N---- | | | \--* IND struct N014 ( 11, 11) [000958] -A-----N---- | | | \--* ADD byref $91 N001 ( 1, 1) [000949] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 10, 10) [000957] -A-----N---- | | | \--* ADD long $6e4 N011 ( 9, 9) [000955] -A-----N---- | | | +--* LSH long $6e3 N009 ( 8, 8) [001283] -A---------- | | | | +--* COMMA long $6e2 N007 ( 7, 7) [001281] -A------R--- | | | | | +--* ASG long $VN.Void N006 ( 1, 1) [001280] D------N---- | | | | | | +--* LCL_VAR long V71 cse6 d:1 $6e2 N005 ( 7, 7) [000961] ------------ | | | | | | \--* MUL long $6e2 N003 ( 2, 3) [000953] ------------ | | | | | | +--* CAST long <- int $6e1 N002 ( 1, 1) [000950] i----------- | | | | | | | \--* LCL_VAR int V09 loc5 u:2 $3c4 N004 ( 1, 1) [000960] ------------ | | | | | | \--* CNS_INT long 3 $24b N008 ( 1, 1) [001282] ------------ | | | | | \--* LCL_VAR long V71 cse6 u:1 $6e2 N010 ( 1, 1) [000954] -------N---- | | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000956] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N019 ( 1, 1) [001256] ------------ | | \--* LCL_VAR byref V66 cse1 u:1 N021 ( 1, 1) [000947] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N024 ( 1, 1) [000213] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 ------------ BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} ***** BB34 STMT00045 (IL 0x18E...0x1A2) N012 ( 12, 11) [000246] -A--G---R--- * ASG ref N011 ( 1, 1) [000245] D------N---- +--* LCL_VAR ref V17 tmp3 d:1 N010 ( 12, 11) [000977] *---G--N---- \--* IND ref N009 ( 9, 9) [000976] ----G------- \--* ADDR byref Zero Fseq[key] $93 N008 ( 5, 5) [000237] a---G--N---- \--* IND struct N007 ( 4, 4) [000972] -------N---- \--* ADD byref $91 N001 ( 1, 1) [000963] ------------ +--* LCL_VAR ref V04 loc0 u:1 N006 ( 3, 3) [000971] -------N---- \--* ADD long $6e4 N004 ( 2, 2) [000969] -------N---- +--* LSH long $6e3 N002 ( 1, 1) [001284] ------------ | +--* LCL_VAR long V71 cse6 u:1 $6e2 N003 ( 1, 1) [000968] -------N---- | \--* CNS_INT long 3 $24b N005 ( 1, 1) [000970] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB34 STMT00044 (IL 0x18E... ???) N004 ( 3, 3) [000244] -A---O--R--- * ASG long $2e8 N003 ( 1, 1) [000243] D------N---- +--* LCL_VAR long V16 tmp2 d:1 $2e7 N002 ( 3, 2) [000242] #----O------ \--* IND long $2e8 N001 ( 1, 1) [000241] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB34 STMT00158 (IL ???... ???) N015 ( 15, 14) [001163] -A---------- * JTRUE void N014 ( 13, 12) [000263] JA-----N---- \--* EQ int N012 ( 11, 10) [001263] -A---------- +--* COMMA long N010 ( 10, 9) [001261] -A------R--- | +--* ASG long $VN.Void N009 ( 1, 1) [001260] D------N---- | | +--* LCL_VAR long V67 cse2 d:1 N008 ( 10, 9) [000259] n----------- | | \--* IND long N007 ( 8, 7) [000255] -------N---- | | \--* ADD long $6e6 N005 ( 7, 6) [000253] #----------- | | +--* IND long $2ea N004 ( 4, 4) [000252] #----------- | | | \--* IND long $2e9 N003 ( 2, 2) [000251] -------N---- | | | \--* ADD long $306 N001 ( 1, 1) [000249] ------------ | | | +--* LCL_VAR long V16 tmp2 u:1 $2e7 N002 ( 1, 1) [000250] ------------ | | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000254] ------------ | | \--* CNS_INT long 48 $246 N011 ( 1, 1) [001262] ------------ | \--* LCL_VAR long V67 cse2 u:1 N013 ( 1, 1) [000262] ------------ \--* CNS_INT long 0 $243 ------------ BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} ***** BB35 STMT00159 (IL ???... ???) N003 ( 1, 3) [001165] -A------R--- * ASG long N002 ( 1, 1) [001164] D------N---- +--* LCL_VAR long V19 tmp5 d:3 N001 ( 1, 1) [001264] ------------ \--* LCL_VAR long V67 cse2 u:1 ------------ BB36 [???..???), preds={BB34} succs={BB37} ***** BB36 STMT00160 (IL ???... ???) N007 ( 17, 18) [001167] -AC-G---R--- * ASG long $6e7 N006 ( 1, 1) [001166] D------N---- +--* LCL_VAR long V19 tmp5 d:2 $6e7 N005 ( 17, 18) [000261] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $6e7 N003 ( 1, 1) [000248] ------?----- arg0 in rcx +--* LCL_VAR long V16 tmp2 u:1 (last use) $2e7 N004 ( 2, 10) [000260] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $63 ------------ BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} ***** BB37 STMT00176 (IL ???... ???) N005 ( 0, 0) [001211] -A------R--- * ASG long N004 ( 0, 0) [001209] D------N---- +--* LCL_VAR long V19 tmp5 d:1 N003 ( 0, 0) [001210] ------------ \--* PHI long N001 ( 0, 0) [001234] ------------ pred BB35 +--* PHI_ARG long V19 tmp5 u:3 N002 ( 0, 0) [001233] ------------ pred BB36 \--* PHI_ARG long V19 tmp5 u:2 $6e7 ***** BB37 STMT00049 (IL ???... ???) N013 ( 32, 18) [000283] --CXG------- * JTRUE void N012 ( 30, 16) [000282] J-CXG--N---- \--* EQ int $817 N010 ( 28, 14) [000280] --CXG------- +--* CALL ind stub int $1ef N009 ( 1, 1) [000279] ------------ calli tgt | \--* LCL_VAR long V19 tmp5 u:1 (last use) $349 N005 ( 1, 1) [000234] ------------ this in rcx | +--* LCL_VAR ref V05 loc1 u:1 N006 ( 1, 1) [000980] ------------ arg1 in r11 | +--* LCL_VAR long V19 tmp5 u:1 r11 REG r11 $349 N007 ( 1, 1) [000247] ------------ arg2 in rdx | +--* LCL_VAR ref V17 tmp3 u:1 (last use) N008 ( 1, 1) [000258] ------------ arg3 in r8 | \--* LCL_VAR ref V01 arg1 u:1 $101 N011 ( 1, 1) [000281] ------------ \--* CNS_INT int 0 $c0 ------------ BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} ***** BB38 STMT00050 (IL 0x1A4...0x1A6) N005 ( 7, 8) [000287] ------------ * JTRUE void N004 ( 5, 6) [000286] N------N-U-- \--* NE int $1bf N002 ( 3, 4) [000985] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000284] ------------ | \--* LCL_VAR int V03 arg3 u:1 $140 N003 ( 1, 1) [000285] ------------ \--* CNS_INT int 1 $c1 ------------ BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} ***** BB39 STMT00057 (IL 0x1A8...0x1B1) N006 ( 6, 6) [000336] -A-XG------- * ASG ref $VN.Void N004 ( 4, 4) [000335] *--XG--N---- +--* IND ref $102 N003 ( 2, 2) [000987] ----G--N---- | \--* ADD byref $2ae N001 ( 1, 1) [001258] ------------ | +--* LCL_VAR byref V66 cse1 u:1 $91 N002 ( 1, 1) [000986] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N005 ( 1, 1) [000334] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 ------------ BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} ***** BB40 STMT00051 (IL 0x1B8...0x1BA) N005 ( 7, 8) [000291] ------------ * JTRUE void N004 ( 5, 6) [000290] N------N-U-- \--* EQ int $600 N002 ( 3, 4) [001002] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000288] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) $140 N003 ( 1, 1) [000289] ------------ \--* CNS_INT int 2 $c2 ------------ BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} ------------ BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} ***** BB42 STMT00040 (IL 0x1C4...0x1D1) N006 ( 4, 4) [000222] -A-XG---R--- * ASG int N005 ( 1, 1) [000221] D------N---- +--* LCL_VAR int V09 loc5 d:3 N004 ( 4, 4) [000220] *--XG------- \--* IND int N003 ( 2, 2) [001009] ----G--N---- \--* ADD byref $2ad N001 ( 1, 1) [001259] ------------ +--* LCL_VAR byref V66 cse1 u:1 $91 N002 ( 1, 1) [001008] ------------ \--* CNS_INT long 20 field offset Fseq[next] $24c ***** BB42 STMT00041 (IL 0x1D3...0x1D6) N005 ( 3, 3) [000227] -A------R--- * ASG int $81a N004 ( 1, 1) [000226] D------N---- +--* LCL_VAR int V07 loc3 d:4 $81a N003 ( 3, 3) [000225] ------------ \--* ADD int $81a N001 ( 1, 1) [000223] ------------ +--* LCL_VAR int V07 loc3 u:3 (last use) $3c3 N002 ( 1, 1) [000224] ------------ \--* CNS_INT int 1 $c1 ***** BB42 STMT00042 (IL 0x1D7...0x1DB) N004 ( 5, 5) [000232] ------------ * JTRUE void N003 ( 3, 3) [000231] N------N-U-- \--* LT int N001 ( 1, 1) [001328] ------------ +--* LCL_VAR int V76 cse11 N002 ( 1, 1) [000228] ------------ \--* LCL_VAR int V07 loc3 u:4 $81a ------------ BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} ------------ BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} ***** BB44 STMT00166 (IL ???... ???) N005 ( 0, 0) [001181] -A------R--- * ASG int N004 ( 0, 0) [001179] D------N---- +--* LCL_VAR int V07 loc3 d:2 N003 ( 0, 0) [001180] ------------ \--* PHI int N001 ( 0, 0) [001237] ------------ pred BB23 +--* PHI_ARG int V07 loc3 u:5 $3c1 N002 ( 0, 0) [001228] ------------ pred BB32 \--* PHI_ARG int V07 loc3 u:3 $3c3 ***** BB44 STMT00015 (IL 0x1E4...0x1EB) N007 ( 8, 8) [000071] ----GO------ * JTRUE void N006 ( 6, 6) [000070] J---GO-N---- \--* LE int N004 ( 4, 4) [000068] n---GO------ +--* IND int N003 ( 2, 2) [001025] -------N---- | \--* ADD byref $28f N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001024] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N005 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 $c0 ------------ BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} ***** BB45 STMT00035 (IL 0x1ED...0x1F3) N010 ( 15, 12) [000174] -A--GO--R--- * ASG int N009 ( 3, 2) [000173] D------N---- +--* LCL_VAR int V10 loc6 d:3 N008 ( 11, 9) [001308] -A--GO------ \--* COMMA int N006 ( 8, 7) [001306] -A--GO--R--- +--* ASG int $VN.Void N005 ( 3, 2) [001305] D------N---- | +--* LCL_VAR int V74 cse9 d:1 N004 ( 4, 4) [000172] n---GO------ | \--* IND int N003 ( 2, 2) [001027] -------N---- | \--* ADD byref $295 N001 ( 1, 1) [000171] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001026] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N007 ( 3, 2) [001307] ------------ \--* LCL_VAR int V74 cse9 u:1 ***** BB45 STMT00120 (IL 0x1F5... ???) N030 ( 45, 44) [000688] -A-XG---R--- * ASG bool N029 ( 3, 2) [000687] D------N---- +--* LCL_VAR int V49 tmp35 d:1 N028 ( 41, 41) [000184] -A-XG------- \--* GE int N026 ( 36, 39) [000182] -A-XG------- +--* ADD int N024 ( 34, 37) [001050] -A-XG------- | +--* NEG int N023 ( 33, 36) [000181] *A-XG------- | | \--* IND int N022 ( 31, 34) [001029] -A-XG--N---- | | \--* ADD byref $29c N020 ( 30, 33) [001044] -A-XG------- | | +--* COMMA byref N003 ( 3, 3) [001032] -A--G---R--- | | | +--* ASG int N002 ( 1, 1) [001031] D------N---- | | | | +--* LCL_VAR int V62 tmp48 d:1 N001 ( 3, 2) [001309] ------------ | | | | \--* LCL_VAR int V74 cse9 u:1 N019 ( 27, 30) [001043] ---XG------- | | | \--* COMMA byref N006 ( 6, 9) [001036] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N004 ( 1, 1) [001033] ------------ | | | | +--* LCL_VAR int V62 tmp48 u:1 N005 ( 1, 1) [001329] ------------ | | | | \--* LCL_VAR int V76 cse11 N018 ( 21, 21) [001049] ----G------- | | | \--* ADDR byref $88 N017 ( 11, 11) [000179] a---G--N---- | | | \--* IND struct N016 ( 10, 10) [001042] -------N---- | | | \--* ADD byref $88 N007 ( 1, 1) [001030] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N015 ( 9, 9) [001041] -------N---- | | | \--* ADD long N013 ( 8, 8) [001039] -------N---- | | | +--* LSH long N011 ( 7, 7) [001048] ------------ | | | | +--* MUL long N009 ( 2, 3) [001037] ------------ | | | | | +--* CAST long <- int N008 ( 1, 1) [001034] i----------- | | | | | | \--* LCL_VAR int V62 tmp48 u:1 (last use) N010 ( 1, 1) [001047] ------------ | | | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [001038] -------N---- | | | | \--* CNS_INT long 3 $24b N014 ( 1, 1) [001040] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N021 ( 1, 1) [001028] ------------ | | \--* CNS_INT long 20 field offset Fseq[next] $24c N025 ( 1, 1) [000175] ------------ | \--* CNS_INT int -3 $e1 N027 ( 1, 1) [000183] ------------ \--* CNS_INT int -1 $c4 ***** BB45 STMT00123 (IL 0x1F5... ???) N003 ( 5, 4) [000698] -A--G---R--- * ASG ref $105 N002 ( 3, 2) [000697] D------N---- +--* LCL_VAR ref V50 tmp36 d:1 $105 N001 ( 1, 1) [001300] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB45 STMT00121 (IL 0x1F5... ???) N004 ( 7, 6) [000693] ------------ * JTRUE void N003 ( 5, 4) [000692] J------N---- \--* NE int N001 ( 3, 2) [000690] ------------ +--* LCL_VAR int V49 tmp35 u:1 (last use) N002 ( 1, 1) [000691] ------------ \--* CNS_INT int 0 $c0 ------------ BB46 [1F5..1F6), preds={BB45} succs={BB47} ***** BB46 STMT00122 (IL 0x1F5... ???) N006 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N004 ( 4, 12) [001052] #---G------- arg0 in rcx +--* IND ref $114 N003 ( 2, 10) [001051] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" $5e N005 ( 3, 2) [000695] ------------ arg1 in rdx \--* LCL_VAR ref V50 tmp36 u:1 (last use) $105 ------------ BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} ***** BB47 STMT00037 (IL 0x219... ???) N034 ( 42, 45) [000200] -A-XGO------ * ASG int $VN.Void N004 ( 4, 4) [000199] n---GO-N---- +--* IND int $732 N003 ( 2, 2) [001056] -------N---- | \--* ADD byref $295 N001 ( 1, 1) [000190] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001055] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N033 ( 37, 40) [000198] -A-XGO------ \--* ADD int N031 ( 35, 38) [001079] -A-XGO------ +--* NEG int N030 ( 34, 37) [000197] *A-XGO------ | \--* IND int N029 ( 32, 35) [001058] -A-XGO-N---- | \--* ADD byref $2a3 N027 ( 31, 34) [001073] -A-XGO------ | +--* COMMA byref N010 ( 4, 4) [001061] -A--GO--R--- | | +--* ASG int N009 ( 1, 1) [001060] D------N---- | | | +--* LCL_VAR int V63 tmp49 d:1 N008 ( 4, 4) [000194] n---GO------ | | | \--* IND int N007 ( 2, 2) [001075] -------N---- | | | \--* ADD byref $295 N005 ( 1, 1) [000193] ------------ | | | +--* LCL_VAR ref V00 this u:1 $100 N006 ( 1, 1) [001074] ------------ | | | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N026 ( 27, 30) [001072] ---XG------- | | \--* COMMA byref N013 ( 6, 9) [001065] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N011 ( 1, 1) [001062] ------------ | | | +--* LCL_VAR int V63 tmp49 u:1 N012 ( 1, 1) [001330] ------------ | | | \--* LCL_VAR int V76 cse11 N025 ( 21, 21) [001078] ----G------- | | \--* ADDR byref $8a N024 ( 11, 11) [000195] a---G--N---- | | \--* IND struct N023 ( 10, 10) [001071] -------N---- | | \--* ADD byref $8a N014 ( 1, 1) [001059] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N022 ( 9, 9) [001070] -------N---- | | \--* ADD long N020 ( 8, 8) [001068] -------N---- | | +--* LSH long N018 ( 7, 7) [001077] ------------ | | | +--* MUL long N016 ( 2, 3) [001066] ------------ | | | | +--* CAST long <- int N015 ( 1, 1) [001063] i----------- | | | | | \--* LCL_VAR int V63 tmp49 u:1 (last use) N017 ( 1, 1) [001076] ------------ | | | | \--* CNS_INT long 3 $24b N019 ( 1, 1) [001067] -------N---- | | | \--* CNS_INT long 3 $24b N021 ( 1, 1) [001069] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N028 ( 1, 1) [001057] ------------ | \--* CNS_INT long 20 field offset Fseq[next] $24c N032 ( 1, 1) [000191] ------------ \--* CNS_INT int -3 $e1 ***** BB47 STMT00038 (IL 0x233...0x23C) N011 ( 11, 11) [000207] -A--GO--R--- * ASG int $VN.Void N010 ( 4, 4) [000206] n---GO-N---- +--* IND int $73a N009 ( 2, 2) [001081] -------N---- | \--* ADD byref $28f N007 ( 1, 1) [000201] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001080] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N006 ( 6, 6) [000205] ----GO------ \--* ADD int N004 ( 4, 4) [000203] n---GO------ +--* IND int N003 ( 2, 2) [001083] -------N---- | \--* ADD byref $28f N001 ( 1, 1) [000202] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001082] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N005 ( 1, 1) [000204] ------------ \--* CNS_INT int -1 $c4 ------------ BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} ***** BB48 STMT00016 (IL 0x243...0x249) N010 ( 15, 12) [000075] -A--GO--R--- * ASG int N009 ( 3, 2) [000074] D------N---- +--* LCL_VAR int V13 loc9 d:1 N008 ( 11, 9) [001313] -A--GO------ \--* COMMA int N006 ( 8, 7) [001311] -A--GO--R--- +--* ASG int $VN.Void N005 ( 3, 2) [001310] D------N---- | +--* LCL_VAR int V75 cse10 d:1 N004 ( 4, 4) [000073] n---GO------ | \--* IND int N003 ( 2, 2) [001085] -------N---- | \--* ADD byref $290 N001 ( 1, 1) [000072] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001084] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] $244 N007 ( 3, 2) [001312] ------------ \--* LCL_VAR int V75 cse10 u:1 ***** BB48 STMT00017 (IL 0x24B...0x250) N004 ( 7, 6) [000080] ------------ * JTRUE void N003 ( 5, 4) [000079] N------N-U-- \--* NE int N001 ( 1, 1) [001331] ------------ +--* LCL_VAR int V76 cse11 N002 ( 3, 2) [000076] ------------ \--* LCL_VAR int V13 loc9 u:1 ------------ BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00125 (IL 0x252... ???) N011 ( 43, 24) [000705] -ACXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void N006 ( 21, 11) [001090] -ACXG---R-L- arg1 SETUP +--* ASG int $1d7 N005 ( 3, 2) [001089] D------N---- | +--* LCL_VAR int V64 tmp50 d:1 $1d7 N004 ( 17, 8) [000702] --CXG------- | \--* CALL int System.Collections.HashHelpers.ExpandPrime $1d7 N003 ( 3, 2) [001314] ------------ arg0 in rcx | \--* LCL_VAR int V75 cse10 u:1 N008 ( 3, 2) [001091] ------------ arg1 in rdx +--* LCL_VAR int V64 tmp50 u:1 (last use) $1d7 N009 ( 1, 1) [000163] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N010 ( 1, 1) [000704] ------------ arg2 in r8 \--* CNS_INT int 0 $c0 ***** BB49 STMT00126 (IL 0x258... ???) N006 ( 8, 7) [000711] -A--GO--R--- * ASG ref N005 ( 3, 2) [000710] D------N---- +--* LCL_VAR ref V52 tmp38 d:1 N004 ( 4, 4) [000709] n---GO------ \--* IND ref N003 ( 2, 2) [001095] -------N---- \--* ADD byref $280 N001 ( 1, 1) [000165] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001094] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] $240 ***** BB49 STMT00133 (IL 0x258... ???) N008 ( 12, 9) [000760] -A-X----R--- * ASG int N007 ( 1, 1) [000759] D------N---- +--* LCL_VAR int V53 tmp39 d:1 N006 ( 12, 9) [001288] -A-X-------- \--* COMMA int N004 ( 9, 7) [001286] -A-X----R--- +--* ASG int $VN.Void N003 ( 3, 2) [001285] D------N---- | +--* LCL_VAR int V72 cse7 d:1 N002 ( 5, 4) [000714] ---X-------- | \--* ARR_LENGTH int N001 ( 3, 2) [000713] ------------ | \--* LCL_VAR ref V52 tmp38 u:1 N005 ( 3, 2) [001287] ------------ \--* LCL_VAR int V72 cse7 u:1 ***** BB49 STMT00134 (IL 0x258... ???) N006 ( 8, 7) [000762] -A--GO--R--- * ASG long N005 ( 3, 2) [000761] D------N---- +--* LCL_VAR long V54 tmp40 d:1 N004 ( 4, 4) [000716] n---GO------ \--* IND long N003 ( 2, 2) [001097] -------N---- \--* ADD byref $283 N001 ( 1, 1) [000715] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001096] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 ***** BB49 STMT00136 (IL 0x258... ???) N005 ( 10, 9) [000773] -A------R--- * ASG bool N004 ( 3, 2) [000772] D------N---- +--* LCL_VAR int V56 tmp42 d:1 N003 ( 6, 6) [000730] N--------U-- \--* LE int N001 ( 1, 1) [000728] ------------ +--* LCL_VAR int V53 tmp39 u:1 N002 ( 1, 4) [000729] ------------ \--* CNS_INT int 0x7FFFFFFF $ce ***** BB49 STMT00139 (IL 0x258... ???) N003 ( 5, 4) [000783] -A--G---R--- * ASG ref $105 N002 ( 3, 2) [000782] D------N---- +--* LCL_VAR ref V57 tmp43 d:1 $105 N001 ( 1, 1) [001301] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB49 STMT00140 (IL 0x258... ???) N003 ( 5, 4) [000785] -A--G---R--- * ASG ref $105 N002 ( 3, 2) [000784] D------N---- +--* LCL_VAR ref V58 tmp44 d:1 $105 N001 ( 1, 1) [001302] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB49 STMT00137 (IL 0x258... ???) N004 ( 7, 6) [000778] ------------ * JTRUE void N003 ( 5, 4) [000777] J------N---- \--* NE int N001 ( 3, 2) [000775] ------------ +--* LCL_VAR int V56 tmp42 u:1 (last use) N002 ( 1, 1) [000776] ------------ \--* CNS_INT int 0 $c0 ------------ BB50 [258..259), preds={BB49} succs={BB51} ***** BB50 STMT00138 (IL 0x258... ???) N005 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 3, 2) [000779] ------------ arg0 in rcx +--* LCL_VAR ref V58 tmp44 u:1 (last use) $105 N004 ( 3, 2) [000780] ------------ arg1 in rdx \--* LCL_VAR ref V58 tmp44 u:1 (last use) $105 ------------ BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00131 (IL 0x258... ???) N016 ( 26, 25) [000750] -A------R--- * ASG int N015 ( 3, 2) [000749] D------N---- +--* LCL_VAR int V55 tmp41 d:1 N014 ( 22, 22) [000748] ------------ \--* CAST int <- uint <- long N013 ( 21, 20) [000747] ------------ \--* RSZ long N011 ( 19, 18) [000745] ------------ +--* MUL long N008 ( 13, 12) [000742] ------------ | +--* ADD long N006 ( 11, 10) [000739] ------------ | | +--* RSZ long N004 ( 9, 8) [000737] ------------ | | | +--* MUL long N001 ( 3, 2) [000735] ------------ | | | | +--* LCL_VAR long V54 tmp40 u:1 (last use) N003 ( 2, 3) [000736] ---------U-- | | | | \--* CAST long <- ulong <- uint $310 N002 ( 1, 1) [000166] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 $3c0 N005 ( 1, 1) [000738] ------------ | | | \--* CNS_INT int 32 $d2 N007 ( 1, 1) [000741] ------------ | | \--* CNS_INT long 1 $247 N010 ( 2, 3) [000744] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000743] ------------ | \--* LCL_VAR int V53 tmp39 u:1 N012 ( 1, 1) [000746] ------------ \--* CNS_INT int 32 $d2 ***** BB51 STMT00142 (IL 0x258... ???) N007 ( 33, 11) [000796] -A-X----R--- * ASG bool N006 ( 3, 2) [000795] D------N---- +--* LCL_VAR int V59 tmp45 d:1 N005 ( 29, 8) [000755] ---X-------- \--* EQ int N003 ( 22, 5) [000754] ---X-------- +--* UMOD int N001 ( 1, 1) [000752] ------------ | +--* LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000753] ------------ | \--* LCL_VAR int V53 tmp39 u:1 (last use) N004 ( 3, 2) [000751] ------------ \--* LCL_VAR int V55 tmp41 u:1 ***** BB51 STMT00145 (IL 0x258... ???) N003 ( 5, 4) [000806] -A--G---R--- * ASG ref $105 N002 ( 3, 2) [000805] D------N---- +--* LCL_VAR ref V60 tmp46 d:1 $105 N001 ( 1, 1) [001303] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB51 STMT00146 (IL 0x258... ???) N003 ( 5, 4) [000808] -A--G---R--- * ASG ref $105 N002 ( 3, 2) [000807] D------N---- +--* LCL_VAR ref V61 tmp47 d:1 $105 N001 ( 1, 1) [001304] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB51 STMT00143 (IL 0x258... ???) N004 ( 7, 6) [000801] ------------ * JTRUE void N003 ( 5, 4) [000800] J------N---- \--* NE int N001 ( 3, 2) [000798] ------------ +--* LCL_VAR int V59 tmp45 u:1 (last use) N002 ( 1, 1) [000799] ------------ \--* CNS_INT int 0 $c0 ------------ BB52 [258..259), preds={BB51} succs={BB53} ***** BB52 STMT00144 (IL 0x258... ???) N005 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 3, 2) [000802] ------------ arg0 in rcx +--* LCL_VAR ref V61 tmp47 u:1 (last use) $105 N004 ( 3, 2) [000803] ------------ arg1 in rdx \--* LCL_VAR ref V61 tmp47 u:1 (last use) $105 ------------ BB53 [258..259), preds={BB51,BB52} succs={BB54} ***** BB53 STMT00128 (IL 0x258... ???) N016 ( 33, 31) [000722] -A-XG---R--- * ASG byref N015 ( 3, 2) [000721] D------N---- +--* LCL_VAR byref V51 tmp37 d:1 $87 N014 ( 29, 28) [001112] ---XG------- \--* COMMA byref N003 ( 10, 11) [001105] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 3, 2) [000758] ------------ | +--* LCL_VAR int V55 tmp41 u:1 N002 ( 3, 2) [001289] ------------ | \--* LCL_VAR int V72 cse7 u:1 N013 ( 19, 17) [001113] ----G------- \--* ADDR byref $87 N012 ( 10, 9) [000719] a---G--N---- \--* IND int N011 ( 9, 8) [001111] -------N---- \--* ADD byref $87 N004 ( 3, 2) [001102] ------------ +--* LCL_VAR ref V52 tmp38 u:1 (last use) N010 ( 6, 6) [001110] -------N---- \--* ADD long N008 ( 5, 5) [001108] -------N---- +--* LSH long N006 ( 4, 4) [001106] ------------ | +--* CAST long <- int N005 ( 3, 2) [001103] i----------- | | \--* LCL_VAR int V55 tmp41 u:1 (last use) N007 ( 1, 1) [001107] -------N---- | \--* CNS_INT long 2 $248 N009 ( 1, 1) [001109] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB53 STMT00034 (IL ???... ???) N003 ( 7, 5) [000170] -A------R--- * ASG byref $87 N002 ( 3, 2) [000169] D------N---- +--* LCL_VAR byref V08 loc4 d:4 $87 N001 ( 3, 2) [000723] ------------ \--* LCL_VAR byref V51 tmp37 u:1 (last use) $87 ------------ BB54 [261..276), preds={BB48,BB53} succs={BB55} ***** BB54 STMT00170 (IL ???... ???) N005 ( 0, 0) [001193] -A------R--- * ASG byref N004 ( 0, 0) [001191] D------N---- +--* LCL_VAR byref V08 loc4 d:3 N003 ( 0, 0) [001192] ------------ \--* PHI byref N001 ( 0, 0) [001224] ------------ pred BB53 +--* PHI_ARG byref V08 loc4 u:4 $87 N002 ( 0, 0) [001220] ------------ pred BB48 \--* PHI_ARG byref V08 loc4 u:1 $81 ***** BB54 STMT00018 (IL 0x261...0x263) N003 ( 7, 5) [000083] -A------R--- * ASG int N002 ( 3, 2) [000082] D------N---- +--* LCL_VAR int V10 loc6 d:2 N001 ( 3, 2) [000081] ------------ \--* LCL_VAR int V13 loc9 u:1 ***** BB54 STMT00019 (IL 0x265...0x26A) N008 ( 10, 9) [000089] -A--GO--R--- * ASG int $VN.Void N007 ( 4, 4) [000088] n---GO-N---- +--* IND int $708 N006 ( 2, 2) [001115] -------N---- | \--* ADD byref $290 N004 ( 1, 1) [000084] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N005 ( 1, 1) [001114] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] $244 N003 ( 5, 4) [000087] ------------ \--* ADD int N001 ( 3, 2) [000085] ------------ +--* LCL_VAR int V10 loc6 u:2 (last use) N002 ( 1, 1) [000086] ------------ \--* CNS_INT int 1 $c1 ***** BB54 STMT00020 (IL 0x26F...0x275) N006 ( 4, 4) [000093] -A--GO--R--- * ASG ref N005 ( 1, 1) [000092] D------N---- +--* LCL_VAR ref V04 loc0 d:3 N004 ( 4, 4) [000091] n---GO------ \--* IND ref N003 ( 2, 2) [001117] -------N---- \--* ADD byref $281 N001 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001116] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] $241 ------------ BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} ***** BB55 STMT00171 (IL ???... ???) N005 ( 0, 0) [001196] -A------R--- * ASG byref N004 ( 0, 0) [001194] D------N---- +--* LCL_VAR byref V08 loc4 d:2 N003 ( 0, 0) [001195] ------------ \--* PHI byref N001 ( 0, 0) [001225] ------------ pred BB47 +--* PHI_ARG byref V08 loc4 u:1 $81 N002 ( 0, 0) [001221] ------------ pred BB54 \--* PHI_ARG byref V08 loc4 u:3 $780 ***** BB55 STMT00169 (IL ???... ???) N005 ( 0, 0) [001190] -A------R--- * ASG ref N004 ( 0, 0) [001188] D------N---- +--* LCL_VAR ref V04 loc0 d:2 N003 ( 0, 0) [001189] ------------ \--* PHI ref N001 ( 0, 0) [001226] ------------ pred BB47 +--* PHI_ARG ref V04 loc0 u:1 N002 ( 0, 0) [001222] ------------ pred BB54 \--* PHI_ARG ref V04 loc0 u:3 ***** BB55 STMT00168 (IL ???... ???) N005 ( 0, 0) [001187] -A------R--- * ASG int N004 ( 0, 0) [001185] D------N---- +--* LCL_VAR int V10 loc6 d:1 N003 ( 0, 0) [001186] ------------ \--* PHI int N001 ( 0, 0) [001227] ------------ pred BB47 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [001223] ------------ pred BB54 \--* PHI_ARG int V10 loc6 u:2 ***** BB55 STMT00021 (IL 0x276...0x27E) N019 ( 39, 38) [000099] -A-XG---R--- * ASG byref $2a6 N018 ( 3, 2) [000098] D------N---- +--* LCL_VAR byref V11 loc7 d:1 $8c N017 ( 35, 35) [001128] ---XG------- \--* COMMA byref $2a6 N004 ( 10, 12) [001121] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $7cd N001 ( 3, 2) [000095] ------------ | +--* LCL_VAR int V10 loc6 u:1 $3cc N003 ( 3, 3) [001120] ---X-------- | \--* ARR_LENGTH int $73d N002 ( 1, 1) [000094] ------------ | \--* LCL_VAR ref V04 loc0 u:2 $684 N016 ( 25, 23) [001131] ----G------- \--* ADDR byref $8c N015 ( 13, 12) [000096] a---G--N---- \--* IND struct N014 ( 12, 11) [001127] -------N---- \--* ADD byref $8c N005 ( 1, 1) [001118] ------------ +--* LCL_VAR ref V04 loc0 u:2 $684 N013 ( 11, 10) [001126] -------N---- \--* ADD long $6df N011 ( 10, 9) [001124] -------N---- +--* LSH long $6de N009 ( 9, 8) [001130] ------------ | +--* MUL long $6dd N007 ( 4, 4) [001122] ------------ | | +--* CAST long <- int $6dc N006 ( 3, 2) [001119] i----------- | | | \--* LCL_VAR int V10 loc6 u:1 $3cc N008 ( 1, 1) [001129] ------------ | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [001123] -------N---- | \--* CNS_INT long 3 $24b N012 ( 1, 1) [001125] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB55 STMT00022 (IL 0x280...0x283) N006 ( 8, 7) [000103] -A-XG------- * ASG int $VN.Void N004 ( 6, 5) [000102] *--XG--N---- +--* IND int $3c0 N003 ( 4, 3) [001133] -------N---- | \--* ADD byref $8d N001 ( 3, 2) [000100] ------------ | +--* LCL_VAR byref V11 loc7 u:1 $8c N002 ( 1, 1) [001132] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N005 ( 1, 1) [000101] ------------ \--* LCL_VAR int V06 loc2 u:1 (last use) $3c0 ***** BB55 STMT00023 (IL 0x288...0x28F) N009 ( 15, 12) [000110] -A-XGO--R--- * ASG int $VN.Void N008 ( 6, 5) [000109] *---GO-N---- +--* IND int N007 ( 4, 3) [001135] -------N---- | \--* ADD byref $8e N005 ( 3, 2) [000104] ------------ | +--* LCL_VAR byref V11 loc7 u:1 $8c N006 ( 1, 1) [001134] ------------ | \--* CNS_INT long 20 field offset Fseq[next] $24c N004 ( 8, 6) [000108] ---XG------- \--* ADD int N002 ( 6, 4) [000106] *--XG------- +--* IND int N001 ( 3, 2) [000105] ------------ | \--* LCL_VAR byref V08 loc4 u:2 $781 N003 ( 1, 1) [000107] ------------ \--* CNS_INT int -1 $c4 ***** BB55 STMT00024 (IL 0x294...0x297) N004 ( 8, 6) [000114] -A-XG------- * ASG ref $VN.Void N002 ( 6, 4) [000113] *--XG--N---- +--* IND ref $101 N001 ( 3, 2) [000111] ------------ | \--* LCL_VAR byref V11 loc7 u:1 Zero Fseq[key] $8f N003 ( 1, 1) [000112] ------------ \--* LCL_VAR ref V01 arg1 u:1 (last use) $101 ***** BB55 STMT00025 (IL 0x29C...0x29F) N006 ( 8, 7) [000118] -A--GO------ * ASG ref $VN.Void N004 ( 6, 5) [000117] *---GO-N---- +--* IND ref $102 N003 ( 4, 3) [001137] -------N---- | \--* ADD byref $90 N001 ( 3, 2) [000115] ------------ | +--* LCL_VAR byref V11 loc7 u:1 (last use) $8c N002 ( 1, 1) [001136] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N005 ( 1, 1) [000116] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 ***** BB55 STMT00026 (IL 0x2A4...0x2AA) N006 ( 12, 9) [000124] -A--GO--R--- * ASG int $VN.Void N005 ( 6, 4) [000123] *----O-N---- +--* IND int $804 N004 ( 3, 2) [000119] ------------ | \--* LCL_VAR byref V08 loc4 u:2 (last use) $781 N003 ( 5, 4) [000122] ------------ \--* ADD int $804 N001 ( 3, 2) [000120] ------------ +--* LCL_VAR int V10 loc6 u:1 (last use) $3cc N002 ( 1, 1) [000121] ------------ \--* CNS_INT int 1 $c1 ***** BB55 STMT00027 (IL 0x2AB...0x2B4) N011 ( 11, 11) [000131] -A--GO--R--- * ASG int $VN.Void N010 ( 4, 4) [000130] n---GO-N---- +--* IND int $80a N009 ( 2, 2) [001139] -------N---- | \--* ADD byref $2a7 N007 ( 1, 1) [000125] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001138] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] $24e N006 ( 6, 6) [000129] ----GO------ \--* ADD int N004 ( 4, 4) [000127] n---GO------ +--* IND int N003 ( 2, 2) [001141] -------N---- | \--* ADD byref $2a7 N001 ( 1, 1) [000126] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001140] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] $24e N005 ( 1, 1) [000128] ------------ \--* CNS_INT int 1 $c1 ***** BB55 STMT00028 (IL 0x2CA...0x2CD) N004 ( 5, 5) [000148] ------------ * JTRUE void N003 ( 3, 3) [000147] N------N-U-- \--* LE int $80d N001 ( 1, 1) [000145] ------------ +--* LCL_VAR int V07 loc3 u:2 (last use) $3c5 N002 ( 1, 1) [000146] ------------ \--* CNS_INT int 100 $e3 ------------ BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} ***** BB56 STMT00030 (IL 0x2CF...0x2D5) N008 ( 21, 22) [000156] --C-G------- * JTRUE void N007 ( 19, 20) [000155] J-C-G--N---- \--* EQ int N005 ( 17, 18) [000153] --C-G------- +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS N003 ( 1, 1) [000151] ------------ arg1 in rdx | +--* LCL_VAR ref V05 loc1 u:1 (last use) N004 ( 2, 10) [000152] H------N---- arg0 in rcx | \--* CNS_INT(h) long 0xd1ffab1e class $62 N006 ( 1, 1) [000154] ------------ \--* CNS_INT ref null $VN.Null ------------ BB57 [2D7..2E3), preds={BB56} succs={BB58} ***** BB57 STMT00031 (IL 0x2D7...0x2DC) N008 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void N005 ( 3, 3) [000159] ---X-------- arg1 in rdx +--* ARR_LENGTH int $73d N004 ( 1, 1) [000158] ------------ | \--* LCL_VAR ref V04 loc0 u:2 (last use) $684 N006 ( 1, 1) [000157] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N007 ( 1, 1) [000160] ------------ arg2 in r8 \--* CNS_INT int 1 $c1 ------------ BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} ***** BB58 STMT00147 (IL ???... ???) N002 ( 2, 2) [000810] ------------ * RETURN int $1f4 N001 ( 1, 1) [000482] ------------ \--* CNS_INT int 1 $c1 ------------ BB59 [008..00E) (throw), preds={BB01} succs={} ***** BB59 STMT00086 (IL 0x008...0x009) N003 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException $VN.Void N002 ( 1, 1) [000532] ------------ arg0 in rcx \--* CNS_INT int 4 $c5 ------------ BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} ***** BB60 STMT00073 (IL 0x14F...0x150) N004 ( 7, 5) [000444] -A---O--R--- * ASG long $2e8 N003 ( 3, 2) [000443] D------N---- +--* LCL_VAR long V26 tmp12 d:1 $2e7 N002 ( 3, 2) [000442] #----O------ \--* IND long $2e8 N001 ( 1, 1) [000441] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB60 STMT00155 (IL ???... ???) N011 ( 16, 14) [001158] ------------ * JTRUE void N010 ( 14, 12) [000460] J------N---- \--* EQ int N008 ( 12, 10) [000456] n----------- +--* IND long N007 ( 10, 8) [000452] -------N---- | \--* ADD long $331 N005 ( 9, 7) [000450] #----------- | +--* IND long $2ea N004 ( 6, 5) [000449] #----------- | | \--* IND long $2e9 N003 ( 4, 3) [000448] -------N---- | | \--* ADD long $306 N001 ( 3, 2) [000446] ------------ | | +--* LCL_VAR long V26 tmp12 u:1 $2e7 N002 ( 1, 1) [000447] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000451] ------------ | \--* CNS_INT long 56 $244 N009 ( 1, 1) [000459] ------------ \--* CNS_INT long 0 $243 ------------ BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} ***** BB61 STMT00156 (IL ???... ???) N010 ( 16, 13) [001160] -A------R--- * ASG long N009 ( 3, 2) [001159] D------N---- +--* LCL_VAR long V28 tmp14 d:3 N008 ( 12, 10) [000461] n-----?----- \--* IND long N007 ( 10, 8) [000462] ------?N---- \--* ADD long $331 N005 ( 9, 7) [000463] #-----?----- +--* IND long $2ea N004 ( 6, 5) [000464] #-----?----- | \--* IND long $2e9 N003 ( 4, 3) [000465] ------?N---- | \--* ADD long $306 N001 ( 3, 2) [000466] ------?----- | +--* LCL_VAR long V26 tmp12 u:1 (last use) $2e7 N002 ( 1, 1) [000467] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000468] ------?----- \--* CNS_INT long 56 $244 ------------ BB62 [???..???), preds={BB60} succs={BB63} ***** BB62 STMT00157 (IL ???... ???) N007 ( 23, 22) [001162] -AC-G---R--- * ASG long $332 N006 ( 3, 2) [001161] D------N---- +--* LCL_VAR long V28 tmp14 d:2 $332 N005 ( 19, 19) [000458] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 N003 ( 3, 2) [000445] ------?----- arg0 in rcx +--* LCL_VAR long V26 tmp12 u:1 (last use) $2e7 N004 ( 2, 10) [000457] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $52 ------------ BB63 [???..157) (throw), preds={BB61,BB62} succs={} ***** BB63 STMT00167 (IL ???... ???) N005 ( 0, 0) [001184] -A------R--- * ASG long N004 ( 0, 0) [001182] D------N---- +--* LCL_VAR long V28 tmp14 d:1 N003 ( 0, 0) [001183] ------------ \--* PHI long N001 ( 0, 0) [001241] ------------ pred BB61 +--* PHI_ARG long V28 tmp14 u:3 N002 ( 0, 0) [001240] ------------ pred BB62 \--* PHI_ARG long V28 tmp14 u:2 $332 ***** BB63 STMT00076 (IL ???... ???) N005 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void N003 ( 3, 2) [000473] ------------ arg0 in rcx +--* LCL_VAR long V28 tmp14 u:1 (last use) $347 N004 ( 1, 1) [000455] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) $101 ------------ BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} ***** BB64 STMT00053 (IL 0x1BC...0x1BD) N004 ( 7, 5) [000299] -A---O--R--- * ASG long $2e8 N003 ( 3, 2) [000298] D------N---- +--* LCL_VAR long V21 tmp7 d:1 $2e7 N002 ( 3, 2) [000297] #----O------ \--* IND long $2e8 N001 ( 1, 1) [000296] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB64 STMT00161 (IL ???... ???) N011 ( 16, 14) [001168] ------------ * JTRUE void N010 ( 14, 12) [000315] J------N---- \--* EQ int N008 ( 12, 10) [000311] n----------- +--* IND long N007 ( 10, 8) [000307] -------N---- | \--* ADD long $331 N005 ( 9, 7) [000305] #----------- | +--* IND long $2ea N004 ( 6, 5) [000304] #----------- | | \--* IND long $2e9 N003 ( 4, 3) [000303] -------N---- | | \--* ADD long $306 N001 ( 3, 2) [000301] ------------ | | +--* LCL_VAR long V21 tmp7 u:1 $2e7 N002 ( 1, 1) [000302] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000306] ------------ | \--* CNS_INT long 56 $244 N009 ( 1, 1) [000314] ------------ \--* CNS_INT long 0 $243 ------------ BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} ***** BB65 STMT00162 (IL ???... ???) N010 ( 16, 13) [001170] -A------R--- * ASG long N009 ( 3, 2) [001169] D------N---- +--* LCL_VAR long V23 tmp9 d:3 N008 ( 12, 10) [000316] n-----?----- \--* IND long N007 ( 10, 8) [000317] ------?N---- \--* ADD long $331 N005 ( 9, 7) [000318] #-----?----- +--* IND long $2ea N004 ( 6, 5) [000319] #-----?----- | \--* IND long $2e9 N003 ( 4, 3) [000320] ------?N---- | \--* ADD long $306 N001 ( 3, 2) [000321] ------?----- | +--* LCL_VAR long V21 tmp7 u:1 (last use) $2e7 N002 ( 1, 1) [000322] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000323] ------?----- \--* CNS_INT long 56 $244 ------------ BB66 [???..???), preds={BB64} succs={BB67} ***** BB66 STMT00163 (IL ???... ???) N007 ( 23, 22) [001172] -AC-G---R--- * ASG long $332 N006 ( 3, 2) [001171] D------N---- +--* LCL_VAR long V23 tmp9 d:2 $332 N005 ( 19, 19) [000313] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 N003 ( 3, 2) [000300] ------?----- arg0 in rcx +--* LCL_VAR long V21 tmp7 u:1 (last use) $2e7 N004 ( 2, 10) [000312] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $52 ------------ BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} ***** BB67 STMT00173 (IL ???... ???) N005 ( 0, 0) [001202] -A------R--- * ASG long N004 ( 0, 0) [001200] D------N---- +--* LCL_VAR long V23 tmp9 d:1 N003 ( 0, 0) [001201] ------------ \--* PHI long N001 ( 0, 0) [001232] ------------ pred BB65 +--* PHI_ARG long V23 tmp9 u:3 N002 ( 0, 0) [001231] ------------ pred BB66 \--* PHI_ARG long V23 tmp9 u:2 $332 ***** BB67 STMT00056 (IL ???... ???) N005 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void N003 ( 3, 2) [000328] ------------ arg0 in rcx +--* LCL_VAR long V23 tmp9 u:1 (last use) $34b N004 ( 1, 1) [000310] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) $101 ------------ BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} ***** BB68 STMT00043 (IL 0x1DD...0x1E2) N001 ( 14, 5) [000233] --CXG------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported $VN.Void ------------------------------------------------------------------------------------------------------------------- Looking for array size assertions for: $400 ArrSize for lengthVN:400 = 0 [RangeCheck::GetRange] BB18N001 ( 1, 1) [000627] ------------ * LCL_VAR int V42 tmp28 u:1 { ---------------------------------------------------- N016 ( 20, 21) [000619] -A------R--- * ASG int N015 ( 1, 1) [000618] D------N---- +--* LCL_VAR int V42 tmp28 d:1 N014 ( 20, 21) [000617] ------------ \--* CAST int <- uint <- long N013 ( 19, 19) [000616] ------------ \--* RSZ long N011 ( 17, 17) [000614] ------------ +--* MUL long N008 ( 11, 11) [000611] ------------ | +--* ADD long N006 ( 9, 9) [000608] ------------ | | +--* RSZ long N004 ( 7, 7) [000606] ------------ | | | +--* MUL long N001 ( 1, 1) [000604] ------------ | | | | +--* LCL_VAR long V41 tmp27 u:1 (last use) N003 ( 2, 3) [000605] ---------U-- | | | | \--* CAST long <- ulong <- uint $310 N002 ( 1, 1) [000047] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 $3c0 N005 ( 1, 1) [000607] ------------ | | | \--* CNS_INT int 32 $d2 N007 ( 1, 1) [000610] ------------ | | \--* CNS_INT long 1 $247 N010 ( 2, 3) [000613] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000612] ------------ | \--* LCL_VAR int V40 tmp26 u:1 N012 ( 1, 1) [000615] ------------ \--* CNS_INT int 32 $d2 ---------------------------------------------------- [RangeCheck::GetRange] BB16N014 ( 20, 21) [000617] ------------ * CAST int <- uint <- long N013 ( 19, 19) [000616] ------------ \--* RSZ long N011 ( 17, 17) [000614] ------------ +--* MUL long N008 ( 11, 11) [000611] ------------ | +--* ADD long N006 ( 9, 9) [000608] ------------ | | +--* RSZ long N004 ( 7, 7) [000606] ------------ | | | +--* MUL long N001 ( 1, 1) [000604] ------------ | | | | +--* LCL_VAR long V41 tmp27 u:1 (last use) N003 ( 2, 3) [000605] ---------U-- | | | | \--* CAST long <- ulong <- uint $310 N002 ( 1, 1) [000047] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 $3c0 N005 ( 1, 1) [000607] ------------ | | | \--* CNS_INT int 32 $d2 N007 ( 1, 1) [000610] ------------ | | \--* CNS_INT long 1 $247 N010 ( 2, 3) [000613] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000612] ------------ | \--* LCL_VAR int V40 tmp26 u:1 N012 ( 1, 1) [000615] ------------ \--* CNS_INT int 32 $d2 { Computed Range [000617] => } Merge assertions from BB18:00000000000000000000000000000806 for assignment about [000618] done merging Merging assertions from pred edges of BB18 for op [000627] $199 Computed Range [000627] => } Looking for array size assertions for: $402 ArrSize for lengthVN:402 = 0 [RangeCheck::GetRange] BB45N004 ( 1, 1) [001033] ------------ * LCL_VAR int V62 tmp48 u:1 { ---------------------------------------------------- N003 ( 3, 3) [001032] -A--G---R--- * ASG int N002 ( 1, 1) [001031] D------N---- +--* LCL_VAR int V62 tmp48 d:1 N001 ( 3, 2) [001309] ------------ \--* LCL_VAR int V74 cse9 u:1 ---------------------------------------------------- [RangeCheck::GetRange] BB45N001 ( 3, 2) [001309] ------------ * LCL_VAR int V74 cse9 u:1 { ---------------------------------------------------- N006 ( 8, 7) [001306] -A--GO--R--- * ASG int $VN.Void N005 ( 3, 2) [001305] D------N---- +--* LCL_VAR int V74 cse9 d:1 N004 ( 4, 4) [000172] n---GO------ \--* IND int N003 ( 2, 2) [001027] -------N---- \--* ADD byref $295 N001 ( 1, 1) [000171] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001026] ------------ \--* CNS_INT long 60 field offset Fseq[_freeList] $24d ---------------------------------------------------- [RangeCheck::GetRange] BB45N004 ( 4, 4) [000172] n---GO------ * IND int N003 ( 2, 2) [001027] -------N---- \--* ADD byref $295 N001 ( 1, 1) [000171] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001026] ------------ \--* CNS_INT long 60 field offset Fseq[_freeList] $24d { Computed Range [000172] => } Merge assertions from BB45:00000000000000000000000004070806 for assignment about [001305] done merging Merging assertions from pred edges of BB45 for op [001309] $1e0 Computed Range [001309] => } Merge assertions from BB45:00000000000000000000000004070806 for assignment about [001031] done merging Merging assertions from pred edges of BB45 for op [001033] $1e2 Computed Range [001033] => } Looking for array size assertions for: $402 ArrSize for lengthVN:402 = 0 [RangeCheck::GetRange] BB47N011 ( 1, 1) [001062] ------------ * LCL_VAR int V63 tmp49 u:1 { ---------------------------------------------------- N010 ( 4, 4) [001061] -A--GO--R--- * ASG int N009 ( 1, 1) [001060] D------N---- +--* LCL_VAR int V63 tmp49 d:1 N008 ( 4, 4) [000194] n---GO------ \--* IND int N007 ( 2, 2) [001075] -------N---- \--* ADD byref $295 N005 ( 1, 1) [000193] ------------ +--* LCL_VAR ref V00 this u:1 $100 N006 ( 1, 1) [001074] ------------ \--* CNS_INT long 60 field offset Fseq[_freeList] $24d ---------------------------------------------------- [RangeCheck::GetRange] BB47N008 ( 4, 4) [000194] n---GO------ * IND int N007 ( 2, 2) [001075] -------N---- \--* ADD byref $295 N005 ( 1, 1) [000193] ------------ +--* LCL_VAR ref V00 this u:1 $100 N006 ( 1, 1) [001074] ------------ \--* CNS_INT long 60 field offset Fseq[_freeList] $24d { Computed Range [000194] => } Merge assertions from BB47:0000000000000000000000000C070806 for assignment about [001060] done merging Merging assertions from pred edges of BB47 for op [001062] $1e6 Computed Range [001062] => } Looking for array size assertions for: $404 ArrSize for lengthVN:404 = 0 [RangeCheck::GetRange] BB53N001 ( 3, 2) [000758] ------------ * LCL_VAR int V55 tmp41 u:1 { ---------------------------------------------------- N016 ( 26, 25) [000750] -A------R--- * ASG int N015 ( 3, 2) [000749] D------N---- +--* LCL_VAR int V55 tmp41 d:1 N014 ( 22, 22) [000748] ------------ \--* CAST int <- uint <- long N013 ( 21, 20) [000747] ------------ \--* RSZ long N011 ( 19, 18) [000745] ------------ +--* MUL long N008 ( 13, 12) [000742] ------------ | +--* ADD long N006 ( 11, 10) [000739] ------------ | | +--* RSZ long N004 ( 9, 8) [000737] ------------ | | | +--* MUL long N001 ( 3, 2) [000735] ------------ | | | | +--* LCL_VAR long V54 tmp40 u:1 (last use) N003 ( 2, 3) [000736] ---------U-- | | | | \--* CAST long <- ulong <- uint $310 N002 ( 1, 1) [000166] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 $3c0 N005 ( 1, 1) [000738] ------------ | | | \--* CNS_INT int 32 $d2 N007 ( 1, 1) [000741] ------------ | | \--* CNS_INT long 1 $247 N010 ( 2, 3) [000744] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000743] ------------ | \--* LCL_VAR int V53 tmp39 u:1 N012 ( 1, 1) [000746] ------------ \--* CNS_INT int 32 $d2 ---------------------------------------------------- [RangeCheck::GetRange] BB51N014 ( 22, 22) [000748] ------------ * CAST int <- uint <- long N013 ( 21, 20) [000747] ------------ \--* RSZ long N011 ( 19, 18) [000745] ------------ +--* MUL long N008 ( 13, 12) [000742] ------------ | +--* ADD long N006 ( 11, 10) [000739] ------------ | | +--* RSZ long N004 ( 9, 8) [000737] ------------ | | | +--* MUL long N001 ( 3, 2) [000735] ------------ | | | | +--* LCL_VAR long V54 tmp40 u:1 (last use) N003 ( 2, 3) [000736] ---------U-- | | | | \--* CAST long <- ulong <- uint $310 N002 ( 1, 1) [000166] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 $3c0 N005 ( 1, 1) [000738] ------------ | | | \--* CNS_INT int 32 $d2 N007 ( 1, 1) [000741] ------------ | | \--* CNS_INT long 1 $247 N010 ( 2, 3) [000744] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000743] ------------ | \--* LCL_VAR int V53 tmp39 u:1 N012 ( 1, 1) [000746] ------------ \--* CNS_INT int 32 $d2 { Computed Range [000748] => } Merge assertions from BB53:00000000000000000000000082070806 for assignment about [000749] done merging Merging assertions from pred edges of BB53 for op [000758] $63a Computed Range [000758] => } Looking for array size assertions for: $40a ArrSize for lengthVN:40A = 0 [RangeCheck::GetRange] BB55N001 ( 3, 2) [000095] ------------ * LCL_VAR int V10 loc6 u:1 $3cc { ---------------------------------------------------- N005 ( 0, 0) [001187] -A------R--- * ASG int N004 ( 0, 0) [001185] D------N---- +--* LCL_VAR int V10 loc6 d:1 N003 ( 0, 0) [001186] ------------ \--* PHI int N001 ( 0, 0) [001227] ------------ pred BB47 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [001223] ------------ pred BB54 \--* PHI_ARG int V10 loc6 u:2 ---------------------------------------------------- [RangeCheck::GetRange] BB55N003 ( 0, 0) [001186] ------------ * PHI int N001 ( 0, 0) [001227] ------------ pred BB47 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [001223] ------------ pred BB54 \--* PHI_ARG int V10 loc6 u:2 { [RangeCheck::GetRange] BB55N001 ( 0, 0) [001227] ------------ * PHI_ARG int V10 loc6 u:3 { ---------------------------------------------------- N010 ( 15, 12) [000174] -A--GO--R--- * ASG int N009 ( 3, 2) [000173] D------N---- +--* LCL_VAR int V10 loc6 d:3 N008 ( 11, 9) [001308] -A--GO------ \--* COMMA int N006 ( 8, 7) [001306] -A--GO--R--- +--* ASG int $VN.Void N005 ( 3, 2) [001305] D------N---- | +--* LCL_VAR int V74 cse9 d:1 N004 ( 4, 4) [000172] n---GO------ | \--* IND int N003 ( 2, 2) [001027] -------N---- | \--* ADD byref $295 N001 ( 1, 1) [000171] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001026] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N007 ( 3, 2) [001307] ------------ \--* LCL_VAR int V74 cse9 u:1 ---------------------------------------------------- [RangeCheck::GetRange] BB45N008 ( 11, 9) [001308] -A--GO------ * COMMA int N006 ( 8, 7) [001306] -A--GO--R--- +--* ASG int $VN.Void N005 ( 3, 2) [001305] D------N---- | +--* LCL_VAR int V74 cse9 d:1 N004 ( 4, 4) [000172] n---GO------ | \--* IND int N003 ( 2, 2) [001027] -------N---- | \--* ADD byref $295 N001 ( 1, 1) [000171] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001026] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N007 ( 3, 2) [001307] ------------ \--* LCL_VAR int V74 cse9 u:1 { [RangeCheck::GetRange] BB45N007 ( 3, 2) [001307] ------------ * LCL_VAR int V74 cse9 u:1 { ---------------------------------------------------- N006 ( 8, 7) [001306] -A--GO--R--- * ASG int $VN.Void N005 ( 3, 2) [001305] D------N---- +--* LCL_VAR int V74 cse9 d:1 N004 ( 4, 4) [000172] n---GO------ \--* IND int N003 ( 2, 2) [001027] -------N---- \--* ADD byref $295 N001 ( 1, 1) [000171] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001026] ------------ \--* CNS_INT long 60 field offset Fseq[_freeList] $24d ---------------------------------------------------- [RangeCheck::GetRange] BB45N004 ( 4, 4) [000172] n---GO------ * IND int N003 ( 2, 2) [001027] -------N---- \--* ADD byref $295 N001 ( 1, 1) [000171] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001026] ------------ \--* CNS_INT long 60 field offset Fseq[_freeList] $24d { Computed Range [000172] => } Merge assertions from BB45:00000000000000000000000004070806 for assignment about [001305] done merging Merging assertions from pred edges of BB45 for op [001307] $1e0 Computed Range [001307] => } Computed Range [001308] => } Merge assertions from BB55:00000000000000000000000000070806 for assignment about [000173] done merging Merging assertions from pred edges of BB55 for op [001227] $1e0 Merge assertions from pred BB47 JTrue edge: 0000000000000000000000000C070806 Computed Range [001227] => } Merging assertions from pred edges of BB55 for op [001227] $1e0 Merge assertions from pred BB47 JTrue edge: 0000000000000000000000000C070806 Merging ranges : [RangeCheck::GetRange] BB55N002 ( 0, 0) [001223] ------------ * PHI_ARG int V10 loc6 u:2 { ---------------------------------------------------- N003 ( 7, 5) [000083] -A------R--- * ASG int N002 ( 3, 2) [000082] D------N---- +--* LCL_VAR int V10 loc6 d:2 N001 ( 3, 2) [000081] ------------ \--* LCL_VAR int V13 loc9 u:1 ---------------------------------------------------- [RangeCheck::GetRange] BB54N001 ( 3, 2) [000081] ------------ * LCL_VAR int V13 loc9 u:1 { ---------------------------------------------------- N010 ( 15, 12) [000075] -A--GO--R--- * ASG int N009 ( 3, 2) [000074] D------N---- +--* LCL_VAR int V13 loc9 d:1 N008 ( 11, 9) [001313] -A--GO------ \--* COMMA int N006 ( 8, 7) [001311] -A--GO--R--- +--* ASG int $VN.Void N005 ( 3, 2) [001310] D------N---- | +--* LCL_VAR int V75 cse10 d:1 N004 ( 4, 4) [000073] n---GO------ | \--* IND int N003 ( 2, 2) [001085] -------N---- | \--* ADD byref $290 N001 ( 1, 1) [000072] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001084] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] $244 N007 ( 3, 2) [001312] ------------ \--* LCL_VAR int V75 cse10 u:1 ---------------------------------------------------- [RangeCheck::GetRange] BB48N008 ( 11, 9) [001313] -A--GO------ * COMMA int N006 ( 8, 7) [001311] -A--GO--R--- +--* ASG int $VN.Void N005 ( 3, 2) [001310] D------N---- | +--* LCL_VAR int V75 cse10 d:1 N004 ( 4, 4) [000073] n---GO------ | \--* IND int N003 ( 2, 2) [001085] -------N---- | \--* ADD byref $290 N001 ( 1, 1) [000072] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001084] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] $244 N007 ( 3, 2) [001312] ------------ \--* LCL_VAR int V75 cse10 u:1 { [RangeCheck::GetRange] BB48N007 ( 3, 2) [001312] ------------ * LCL_VAR int V75 cse10 u:1 { ---------------------------------------------------- N006 ( 8, 7) [001311] -A--GO--R--- * ASG int $VN.Void N005 ( 3, 2) [001310] D------N---- +--* LCL_VAR int V75 cse10 d:1 N004 ( 4, 4) [000073] n---GO------ \--* IND int N003 ( 2, 2) [001085] -------N---- \--* ADD byref $290 N001 ( 1, 1) [000072] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001084] ------------ \--* CNS_INT long 56 field offset Fseq[_count] $244 ---------------------------------------------------- [RangeCheck::GetRange] BB48N004 ( 4, 4) [000073] n---GO------ * IND int N003 ( 2, 2) [001085] -------N---- \--* ADD byref $290 N001 ( 1, 1) [000072] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001084] ------------ \--* CNS_INT long 56 field offset Fseq[_count] $244 { Computed Range [000073] => } Merge assertions from BB48:00000000000000000000000002070806 for assignment about [001310] done merging Merging assertions from pred edges of BB48 for op [001312] $1d3 Computed Range [001312] => } Computed Range [001313] => } Merge assertions from BB54:00000000000000000000000002070806 for assignment about [000074] done merging Merging assertions from pred edges of BB54 for op [000081] $1d3 Computed Range [000081] => } Merge assertions from BB55:00000000000000000000000000070806 for assignment about [000082] done merging Merging assertions from pred edges of BB55 for op [001223] $1d3 Merge assertions from pred BB54 edge: 00000000000000000000000002070806 Computed Range [001223] => } Merging assertions from pred edges of BB55 for op [001223] $1d3 Merge assertions from pred BB54 edge: 00000000000000000000000002070806 Merging ranges : Computed Range [001186] => } Merge assertions from BB55:00000000000000000000000000070806 for assignment about [001185] done merging Merging assertions from pred edges of BB55 for op [000095] $3cc Computed Range [000095] => } *************** Finishing PHASE Optimize index checks *************** Starting PHASE Insert GC Polls *************** Finishing PHASE Insert GC Polls [no changes] *************** Starting PHASE Determine first cold block *************** In fgDetermineFirstColdBlock() No procedure splitting will be done for this method *************** Finishing PHASE Determine first cold block Trees before Rationalize IR ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal Loop1 gcsafe BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe BB36 [0108] 1 BB34 1 [???..???) i gcsafe BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen BB54 [0044] 2 BB48,BB53 0.50 [261..276) i BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} ***** BB01 STMT00000 (IL 0x000...0x006) N004 ( 5, 5) [000003] ------------ * JTRUE void N003 ( 3, 3) [000002] J------N---- \--* EQ int $180 N001 ( 1, 1) [000000] ------------ +--* LCL_VAR ref V01 arg1 u:1 $101 N002 ( 1, 1) [000001] ------------ \--* CNS_INT ref null $VN.Null ------------ BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ***** BB02 STMT00001 (IL 0x00E...0x014) N007 ( 8, 8) [000008] ---XG------- * JTRUE void N006 ( 6, 6) [000007] J--XG--N---- \--* NE int N004 ( 4, 4) [000005] ---XG------- +--* IND ref N003 ( 2, 2) [000814] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000004] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000813] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] $240 N005 ( 1, 1) [000006] ------------ \--* CNS_INT ref null $VN.Null ------------ BB03 [016..01E), preds={BB02} succs={BB04} ***** BB03 STMT00085 (IL ???... ???) N005 ( 16, 10) [000528] --CXG------- * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize $1c2 N003 ( 1, 1) [000526] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N004 ( 1, 1) [000527] ------------ arg1 in rdx \--* CNS_INT int 0 $c0 ------------ BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ***** BB04 STMT00088 (IL 0x01E... ???) N008 ( 9, 6) [000544] -A--GO--R--- * ASG bool N007 ( 1, 1) [000543] D------N---- +--* LCL_VAR int V33 tmp19 d:1 N006 ( 9, 6) [000012] N---GO------ \--* NE int N004 ( 4, 4) [000010] n---GO------ +--* IND ref N003 ( 2, 2) [000818] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000009] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000817] ------------ | \--* CNS_INT long 8 field offset Fseq[_buckets] $240 N005 ( 1, 1) [000011] ------------ \--* CNS_INT ref null $VN.Null ***** BB04 STMT00091 (IL 0x01E... ???) N008 ( 5, 13) [000554] -A--G---R--- * ASG ref $105 N007 ( 1, 1) [000553] D------N---- +--* LCL_VAR ref V34 tmp20 d:1 $105 N006 ( 5, 13) [001293] -A--G------- \--* COMMA ref $105 N004 ( 4, 12) [001291] -A--G---R--- +--* ASG ref $VN.Void N003 ( 1, 1) [001290] D------N---- | +--* LCL_VAR ref V73 cse8 d:1 $105 N002 ( 4, 12) [000538] #---G------- | \--* IND ref $105 N001 ( 2, 10) [000537] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 N005 ( 1, 1) [001292] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB04 STMT00092 (IL 0x01E... ???) N003 ( 1, 3) [000556] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000555] D------N---- +--* LCL_VAR ref V35 tmp21 d:1 $105 N001 ( 1, 1) [001294] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB04 STMT00089 (IL 0x01E... ???) N004 ( 5, 5) [000549] ------------ * JTRUE void N003 ( 3, 3) [000548] J------N---- \--* NE int N001 ( 1, 1) [000546] ------------ +--* LCL_VAR int V33 tmp19 u:1 (last use) N002 ( 1, 1) [000547] ------------ \--* CNS_INT int 0 $c0 ------------ BB05 [01E..01F), preds={BB04} succs={BB06} ***** BB05 STMT00090 (IL 0x01E... ???) N005 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 1, 1) [000550] ------------ arg0 in rcx +--* LCL_VAR ref V35 tmp21 u:1 (last use) $105 N004 ( 1, 1) [000551] ------------ arg1 in rdx \--* LCL_VAR ref V35 tmp21 u:1 (last use) $105 ------------ BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} ***** BB06 STMT00003 (IL 0x02C... ???) N006 ( 4, 4) [000018] -A--GO--R--- * ASG ref N005 ( 1, 1) [000017] D------N---- +--* LCL_VAR ref V04 loc0 d:1 N004 ( 4, 4) [000016] n---GO------ \--* IND ref N003 ( 2, 2) [000822] -------N---- \--* ADD byref $281 N001 ( 1, 1) [000015] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000821] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] $241 ***** BB06 STMT00094 (IL 0x033... ???) N005 ( 6, 3) [000566] -A------R--- * ASG bool N004 ( 1, 1) [000565] D------N---- +--* LCL_VAR int V36 tmp22 d:1 N003 ( 6, 3) [000021] N----------- \--* NE int N001 ( 1, 1) [000019] ------------ +--* LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000020] ------------ \--* CNS_INT ref null $VN.Null ***** BB06 STMT00097 (IL 0x033... ???) N003 ( 1, 3) [000576] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000575] D------N---- +--* LCL_VAR ref V37 tmp23 d:1 $105 N001 ( 1, 1) [001295] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB06 STMT00095 (IL 0x033... ???) N004 ( 5, 5) [000571] ------------ * JTRUE void N003 ( 3, 3) [000570] J------N---- \--* NE int N001 ( 1, 1) [000568] ------------ +--* LCL_VAR int V36 tmp22 u:1 (last use) N002 ( 1, 1) [000569] ------------ \--* CNS_INT int 0 $c0 ------------ BB07 [033..034), preds={BB06} succs={BB08} ***** BB07 STMT00096 (IL 0x033... ???) N006 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N004 ( 4, 12) [000824] #---G------- arg0 in rcx +--* IND ref $106 N003 ( 2, 10) [000823] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" $46 N005 ( 1, 1) [000573] ------------ arg1 in rdx \--* LCL_VAR ref V37 tmp23 u:1 (last use) $105 ------------ BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} ***** BB08 STMT00005 (IL 0x041... ???) N006 ( 4, 4) [000028] -A--GO--R--- * ASG ref N005 ( 1, 1) [000027] D------N---- +--* LCL_VAR ref V05 loc1 d:1 N004 ( 4, 4) [000026] n---GO------ \--* IND ref N003 ( 2, 2) [000828] -------N---- \--* ADD byref $282 N001 ( 1, 1) [000025] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000827] ------------ \--* CNS_INT long 24 field offset Fseq[_comparer] $242 ***** BB08 STMT00006 (IL 0x048...0x049) N004 ( 5, 5) [000032] ------------ * JTRUE void N003 ( 3, 3) [000031] J------N---- \--* EQ int N001 ( 1, 1) [000029] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000030] ------------ \--* CNS_INT ref null $VN.Null ------------ BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} ***** BB09 STMT00079 (IL 0x04B...0x052) N004 ( 3, 3) [000489] -A---O--R--- * ASG long $2e8 N003 ( 1, 1) [000488] D------N---- +--* LCL_VAR long V29 tmp15 d:1 $2e7 N002 ( 3, 2) [000487] #----O------ \--* IND long $2e8 N001 ( 1, 1) [000486] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB09 STMT00149 (IL ???... ???) N015 ( 21, 18) [001148] -A---------- * JTRUE void N014 ( 19, 16) [000505] JA-----N---- \--* EQ int N012 ( 17, 14) [001268] -A---------- +--* COMMA long N010 ( 14, 12) [001266] -A------R--- | +--* ASG long $VN.Void N009 ( 3, 2) [001265] D------N---- | | +--* LCL_VAR long V68 cse3 d:1 N008 ( 10, 9) [000501] n----------- | | \--* IND long N007 ( 8, 7) [000497] -------N---- | | \--* ADD long $307 N005 ( 7, 6) [000495] #----------- | | +--* IND long $2ea N004 ( 4, 4) [000494] #----------- | | | \--* IND long $2e9 N003 ( 2, 2) [000493] -------N---- | | | \--* ADD long $306 N001 ( 1, 1) [000491] ------------ | | | +--* LCL_VAR long V29 tmp15 u:1 $2e7 N002 ( 1, 1) [000492] ------------ | | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000496] ------------ | | \--* CNS_INT long 64 $245 N011 ( 3, 2) [001267] ------------ | \--* LCL_VAR long V68 cse3 u:1 N013 ( 1, 1) [000504] ------------ \--* CNS_INT long 0 $243 ------------ BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} ***** BB10 STMT00150 (IL ???... ???) N003 ( 3, 3) [001150] -A------R--- * ASG long N002 ( 1, 1) [001149] D------N---- +--* LCL_VAR long V31 tmp17 d:3 N001 ( 3, 2) [001269] ------------ \--* LCL_VAR long V68 cse3 u:1 ------------ BB11 [???..???), preds={BB09} succs={BB12} ***** BB11 STMT00151 (IL ???... ???) N007 ( 17, 18) [001152] -AC-G---R--- * ASG long $308 N006 ( 1, 1) [001151] D------N---- +--* LCL_VAR long V31 tmp17 d:2 $308 N005 ( 17, 18) [000503] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $308 N003 ( 1, 1) [000490] ------?----- arg0 in rcx +--* LCL_VAR long V29 tmp15 u:1 (last use) $2e7 N004 ( 2, 10) [000502] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $49 ------------ BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} ***** BB12 STMT00178 (IL ???... ???) N005 ( 0, 0) [001217] -A------R--- * ASG long N004 ( 0, 0) [001215] D------N---- +--* LCL_VAR long V31 tmp17 d:1 N003 ( 0, 0) [001216] ------------ \--* PHI long N001 ( 0, 0) [001247] ------------ pred BB10 +--* PHI_ARG long V31 tmp17 u:3 N002 ( 0, 0) [001246] ------------ pred BB11 \--* PHI_ARG long V31 tmp17 u:2 $308 ***** BB12 STMT00083 (IL ???... ???) N010 ( 31, 15) [000524] -ACXG---R--- * ASG int $1c7 N009 ( 3, 2) [000523] D------N---- +--* LCL_VAR int V15 tmp1 d:3 $1c7 N008 ( 27, 12) [000522] --CXG------- \--* CALL ind stub int $1c7 N007 ( 1, 1) [000521] ------------ calli tgt \--* LCL_VAR long V31 tmp17 u:1 (last use) $342 N004 ( 1, 1) [000484] ------------ this in rcx +--* LCL_VAR ref V05 loc1 u:1 N005 ( 1, 1) [000831] ------------ arg1 in r11 +--* LCL_VAR long V31 tmp17 u:1 r11 REG r11 $342 N006 ( 1, 1) [000500] ------------ arg2 in rdx \--* LCL_VAR ref V01 arg1 u:1 $101 ------------ BB13 [054..061), preds={BB08} succs={BB14} ***** BB13 STMT00007 (IL 0x054...0x05C) N013 ( 34, 21) [000038] -ACXGO--R--- * ASG int $1c5 N012 ( 3, 2) [000037] D------N---- +--* LCL_VAR int V15 tmp1 d:2 $1c5 N011 ( 30, 18) [000035] --CXGO------ \--* CALLV vt-ind int System.Object.GetHashCode $1c5 N010 ( 9, 8) [000843] n----O------ control expr \--* IND long N009 ( 7, 6) [000842] -----O-N---- \--* ADD long $303 N007 ( 6, 5) [000840] #----O------ +--* IND long $2e6 N006 ( 4, 3) [000839] -----O-N---- | \--* ADD long $301 N004 ( 3, 2) [000837] #----O------ | +--* IND long $2e4 N003 ( 1, 1) [000836] ------------ | | \--* LCL_VAR ref V01 arg1 u:1 $101 N005 ( 1, 1) [000838] ------------ | \--* CNS_INT int 72 $c9 N008 ( 1, 1) [000841] ------------ \--* CNS_INT int 24 $ca N002 ( 1, 1) [000033] ------------ this in rcx \--* LCL_VAR ref V01 arg1 u:1 $101 ------------ BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ***** BB14 STMT00177 (IL ???... ???) N005 ( 0, 0) [001214] -A------R--- * ASG int N004 ( 0, 0) [001212] D------N---- +--* LCL_VAR int V15 tmp1 d:1 N003 ( 0, 0) [001213] ------------ \--* PHI int N001 ( 0, 0) [001245] ------------ pred BB12 +--* PHI_ARG int V15 tmp1 u:3 $1c7 N002 ( 0, 0) [001244] ------------ pred BB13 \--* PHI_ARG int V15 tmp1 u:2 $1c5 ***** BB14 STMT00008 (IL ???...0x061) N003 ( 3, 3) [000042] -A------R--- * ASG int $3c0 N002 ( 1, 1) [000041] D------N---- +--* LCL_VAR int V06 loc2 d:1 $3c0 N001 ( 3, 2) [000040] ------------ \--* LCL_VAR int V15 tmp1 u:1 (last use) $3c0 ***** BB14 STMT00009 (IL 0x062...0x063) N003 ( 1, 3) [000045] -A------R--- * ASG int $c0 N002 ( 1, 1) [000044] D------N---- +--* LCL_VAR int V07 loc3 d:1 $c0 N001 ( 1, 1) [000043] ------------ \--* CNS_INT int 0 $c0 ***** BB14 STMT00098 (IL 0x064... ???) N006 ( 4, 4) [000580] -A--GO--R--- * ASG ref N005 ( 1, 1) [000579] D------N---- +--* LCL_VAR ref V39 tmp25 d:1 N004 ( 4, 4) [000578] n---GO------ \--* IND ref N003 ( 2, 2) [000845] -------N---- \--* ADD byref $280 N001 ( 1, 1) [000046] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000844] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] $240 ***** BB14 STMT00105 (IL 0x064... ???) N004 ( 3, 3) [000629] -A-X----R--- * ASG int N003 ( 1, 1) [000628] D------N---- +--* LCL_VAR int V40 tmp26 d:1 N002 ( 3, 3) [000583] ---X-------- \--* ARR_LENGTH int N001 ( 1, 1) [000582] ------------ \--* LCL_VAR ref V39 tmp25 u:1 ***** BB14 STMT00106 (IL 0x064... ???) N006 ( 4, 4) [000631] -A--GO--R--- * ASG long N005 ( 1, 1) [000630] D------N---- +--* LCL_VAR long V41 tmp27 d:1 N004 ( 4, 4) [000585] n---GO------ \--* IND long N003 ( 2, 2) [000847] -------N---- \--* ADD byref $283 N001 ( 1, 1) [000584] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000846] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 ***** BB14 STMT00108 (IL 0x064... ???) N005 ( 6, 6) [000642] -A------R--- * ASG bool N004 ( 1, 1) [000641] D------N---- +--* LCL_VAR int V43 tmp29 d:1 N003 ( 6, 6) [000599] N--------U-- \--* LE int N001 ( 1, 1) [000597] ------------ +--* LCL_VAR int V40 tmp26 u:1 N002 ( 1, 4) [000598] ------------ \--* CNS_INT int 0x7FFFFFFF $ce ***** BB14 STMT00111 (IL 0x064... ???) N003 ( 1, 3) [000652] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000651] D------N---- +--* LCL_VAR ref V44 tmp30 d:1 $105 N001 ( 1, 1) [001296] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB14 STMT00112 (IL 0x064... ???) N003 ( 1, 3) [000654] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000653] D------N---- +--* LCL_VAR ref V45 tmp31 d:1 $105 N001 ( 1, 1) [001297] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB14 STMT00109 (IL 0x064... ???) N004 ( 5, 5) [000647] ------------ * JTRUE void N003 ( 3, 3) [000646] J------N---- \--* NE int N001 ( 1, 1) [000644] ------------ +--* LCL_VAR int V43 tmp29 u:1 (last use) N002 ( 1, 1) [000645] ------------ \--* CNS_INT int 0 $c0 ------------ BB15 [064..065), preds={BB14} succs={BB16} ***** BB15 STMT00110 (IL 0x064... ???) N005 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 1, 1) [000648] ------------ arg0 in rcx +--* LCL_VAR ref V45 tmp31 u:1 (last use) $105 N004 ( 1, 1) [000649] ------------ arg1 in rdx \--* LCL_VAR ref V45 tmp31 u:1 (last use) $105 ------------ BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} ***** BB16 STMT00103 (IL 0x064... ???) N016 ( 20, 21) [000619] -A------R--- * ASG int N015 ( 1, 1) [000618] D------N---- +--* LCL_VAR int V42 tmp28 d:1 N014 ( 20, 21) [000617] ------------ \--* CAST int <- uint <- long N013 ( 19, 19) [000616] ------------ \--* RSZ long N011 ( 17, 17) [000614] ------------ +--* MUL long N008 ( 11, 11) [000611] ------------ | +--* ADD long N006 ( 9, 9) [000608] ------------ | | +--* RSZ long N004 ( 7, 7) [000606] ------------ | | | +--* MUL long N001 ( 1, 1) [000604] ------------ | | | | +--* LCL_VAR long V41 tmp27 u:1 (last use) N003 ( 2, 3) [000605] ---------U-- | | | | \--* CAST long <- ulong <- uint $310 N002 ( 1, 1) [000047] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 $3c0 N005 ( 1, 1) [000607] ------------ | | | \--* CNS_INT int 32 $d2 N007 ( 1, 1) [000610] ------------ | | \--* CNS_INT long 1 $247 N010 ( 2, 3) [000613] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000612] ------------ | \--* LCL_VAR int V40 tmp26 u:1 N012 ( 1, 1) [000615] ------------ \--* CNS_INT int 32 $d2 ***** BB16 STMT00114 (IL 0x064... ???) N007 ( 27, 7) [000665] -A-X----R--- * ASG bool N006 ( 1, 1) [000664] D------N---- +--* LCL_VAR int V46 tmp32 d:1 N005 ( 27, 7) [000624] ---X-------- \--* EQ int N003 ( 22, 5) [000623] ---X-------- +--* UMOD int N001 ( 1, 1) [000621] ------------ | +--* LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000622] ------------ | \--* LCL_VAR int V40 tmp26 u:1 (last use) N004 ( 1, 1) [000620] ------------ \--* LCL_VAR int V42 tmp28 u:1 ***** BB16 STMT00117 (IL 0x064... ???) N003 ( 1, 3) [000675] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000674] D------N---- +--* LCL_VAR ref V47 tmp33 d:1 $105 N001 ( 1, 1) [001298] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB16 STMT00118 (IL 0x064... ???) N003 ( 1, 3) [000677] -A--G---R--- * ASG ref $105 N002 ( 1, 1) [000676] D------N---- +--* LCL_VAR ref V48 tmp34 d:1 $105 N001 ( 1, 1) [001299] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB16 STMT00115 (IL 0x064... ???) N004 ( 5, 5) [000670] ------------ * JTRUE void N003 ( 3, 3) [000669] J------N---- \--* NE int N001 ( 1, 1) [000667] ------------ +--* LCL_VAR int V46 tmp32 u:1 (last use) N002 ( 1, 1) [000668] ------------ \--* CNS_INT int 0 $c0 ------------ BB17 [064..065), preds={BB16} succs={BB18} ***** BB17 STMT00116 (IL 0x064... ???) N005 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 1, 1) [000671] ------------ arg0 in rcx +--* LCL_VAR ref V48 tmp34 u:1 (last use) $105 N004 ( 1, 1) [000672] ------------ arg1 in rdx \--* LCL_VAR ref V48 tmp34 u:1 (last use) $105 ------------ BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} ***** BB18 STMT00100 (IL 0x064... ???) N017 ( 19, 24) [000591] -A-XG---R--- * ASG byref N016 ( 1, 1) [000590] D------N---- +--* LCL_VAR byref V38 tmp24 d:1 $81 N015 ( 19, 24) [000862] ---XG------- \--* COMMA byref N004 ( 8, 11) [000855] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 1, 1) [000627] ------------ | +--* LCL_VAR int V42 tmp28 u:1 N003 ( 3, 3) [000854] ---X-------- | \--* ARR_LENGTH int N002 ( 1, 1) [000581] ------------ | \--* LCL_VAR ref V39 tmp25 u:1 N014 ( 11, 13) [000863] ----G------- \--* ADDR byref $81 N013 ( 6, 7) [000588] a---G--N---- \--* IND int N012 ( 5, 6) [000861] -------N---- \--* ADD byref $81 N005 ( 1, 1) [000852] ------------ +--* LCL_VAR ref V39 tmp25 u:1 (last use) N011 ( 4, 5) [000860] -------N---- \--* ADD long N009 ( 3, 4) [000858] -------N---- +--* LSH long N007 ( 2, 3) [000856] ------------ | +--* CAST long <- int N006 ( 1, 1) [000853] i----------- | | \--* LCL_VAR int V42 tmp28 u:1 (last use) N008 ( 1, 1) [000857] -------N---- | \--* CNS_INT long 2 $248 N010 ( 1, 1) [000859] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB18 STMT00011 (IL ???... ???) N003 ( 5, 4) [000051] -A------R--- * ASG byref $81 N002 ( 3, 2) [000050] D------N---- +--* LCL_VAR byref V08 loc4 d:1 $81 N001 ( 1, 1) [000592] ------------ \--* LCL_VAR byref V38 tmp24 u:1 $81 ***** BB18 STMT00012 (IL 0x06D...0x072) N006 ( 5, 4) [000057] -A-XG---R--- * ASG int N005 ( 1, 1) [000056] D------N---- +--* LCL_VAR int V09 loc5 d:1 N004 ( 5, 4) [000055] ---XG------- \--* ADD int N002 ( 3, 2) [000053] *--XG------- +--* IND int N001 ( 1, 1) [000052] ------------ | \--* LCL_VAR byref V08 loc4 u:1 (last use) $81 N003 ( 1, 1) [000054] ------------ \--* CNS_INT int -1 $c4 ***** BB18 STMT00013 (IL 0x074...0x075) N004 ( 5, 5) [000061] ------------ * JTRUE void N003 ( 3, 3) [000060] J------N---- \--* NE int N001 ( 1, 1) [000058] ------------ +--* LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000059] ------------ \--* CNS_INT ref null $VN.Null ------------ BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} ***** BB19 STMT00059 (IL 0x0FF...0x104) N004 ( 3, 3) [000356] -A---O--R--- * ASG long $2e8 N003 ( 1, 1) [000355] D------N---- +--* LCL_VAR long V24 tmp10 d:1 $2e7 N002 ( 3, 2) [000354] #----O------ \--* IND long $2e8 N001 ( 1, 1) [000353] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB19 STMT00152 (IL ???... ???) N015 ( 21, 18) [001153] -A---------- * JTRUE void N014 ( 19, 16) [000369] JA-----N---- \--* EQ int N012 ( 17, 14) [001273] -A---------- +--* COMMA long N010 ( 14, 12) [001271] -A------R--- | +--* ASG long $VN.Void N009 ( 3, 2) [001270] D------N---- | | +--* LCL_VAR long V69 cse4 d:1 N008 ( 10, 9) [000365] n----------- | | \--* IND long N007 ( 8, 7) [000364] -------N---- | | \--* ADD long $324 N005 ( 7, 6) [000362] #----------- | | +--* IND long $2ea N004 ( 4, 4) [000361] #----------- | | | \--* IND long $2e9 N003 ( 2, 2) [000360] -------N---- | | | \--* ADD long $306 N001 ( 1, 1) [000358] ------------ | | | +--* LCL_VAR long V24 tmp10 u:1 $2e7 N002 ( 1, 1) [000359] ------------ | | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000363] ------------ | | \--* CNS_INT long 32 $24a N011 ( 3, 2) [001272] ------------ | \--* LCL_VAR long V69 cse4 u:1 N013 ( 1, 1) [000368] ------------ \--* CNS_INT long 0 $243 ------------ BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} ***** BB20 STMT00153 (IL ???... ???) N003 ( 7, 5) [001155] -A------R--- * ASG long N002 ( 3, 2) [001154] D------N---- +--* LCL_VAR long V25 tmp11 d:3 N001 ( 3, 2) [001274] ------------ \--* LCL_VAR long V69 cse4 u:1 ------------ BB21 [???..???), preds={BB19} succs={BB22} ***** BB21 STMT00154 (IL ???... ???) N007 ( 21, 21) [001157] -AC-G---R--- * ASG long $325 N006 ( 3, 2) [001156] D------N---- +--* LCL_VAR long V25 tmp11 d:2 $325 N005 ( 17, 18) [000367] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $325 N003 ( 1, 1) [000357] ------?----- arg0 in rcx +--* LCL_VAR long V24 tmp10 u:1 (last use) $2e7 N004 ( 2, 10) [000366] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $4f ------------ BB22 [???..106), preds={BB20,BB21} succs={BB23} ***** BB22 STMT00172 (IL ???... ???) N005 ( 0, 0) [001199] -A------R--- * ASG long N004 ( 0, 0) [001197] D------N---- +--* LCL_VAR long V25 tmp11 d:1 N003 ( 0, 0) [001198] ------------ \--* PHI long N001 ( 0, 0) [001243] ------------ pred BB20 +--* PHI_ARG long V25 tmp11 u:3 N002 ( 0, 0) [001242] ------------ pred BB21 \--* PHI_ARG long V25 tmp11 u:2 $325 ***** BB22 STMT00062 (IL ???... ???) N005 ( 17, 8) [000386] -ACXG---R--- * ASG ref $223 N004 ( 1, 1) [000385] D------N---- +--* LCL_VAR ref V12 loc8 d:1 $223 N003 ( 17, 8) [000352] --CXG------- \--* CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default $223 N002 ( 3, 2) [000382] ------------ arg0 in rcx \--* LCL_VAR long V25 tmp11 u:1 (last use) $344 ------------ BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} ***** BB23 STMT00165 (IL ???... ???) N005 ( 0, 0) [001178] -A------R--- * ASG int N004 ( 0, 0) [001176] D------N---- +--* LCL_VAR int V07 loc3 d:5 N003 ( 0, 0) [001177] ------------ \--* PHI int N001 ( 0, 0) [001238] ------------ pred BB27 +--* PHI_ARG int V07 loc3 u:6 N002 ( 0, 0) [001235] ------------ pred BB22 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB23 STMT00164 (IL ???... ???) N005 ( 0, 0) [001175] -A------R--- * ASG int N004 ( 0, 0) [001173] D------N---- +--* LCL_VAR int V09 loc5 d:4 N003 ( 0, 0) [001174] ------------ \--* PHI int N001 ( 0, 0) [001239] ------------ pred BB27 +--* PHI_ARG int V09 loc5 u:5 N002 ( 0, 0) [001236] ------------ pred BB22 \--* PHI_ARG int V09 loc5 u:1 ***** BB23 STMT00063 (IL 0x106...0x10B) N009 ( 8, 8) [000391] -A-X-------- * JTRUE void N008 ( 6, 6) [000390] NA-X---N-U-- \--* LE int N006 ( 4, 4) [001318] -A-X-------- +--* COMMA int N004 ( 3, 3) [001316] -A-X----R--- | +--* ASG int $VN.Void N003 ( 1, 1) [001315] D------N---- | | +--* LCL_VAR int V76 cse11 N002 ( 3, 3) [000389] ---X-------- | | \--* ARR_LENGTH int N001 ( 1, 1) [000388] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N005 ( 1, 1) [001317] ------------ | \--* LCL_VAR int V76 cse11 N007 ( 1, 1) [000387] ------------ \--* LCL_VAR int V09 loc5 u:4 $3c2 ------------ BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} ***** BB24 STMT00064 (IL 0x110...0x11E) N026 ( 31, 31) [000399] -A-XG------- * JTRUE void N025 ( 29, 29) [000398] NA-XG--N-U-- \--* NE int N023 ( 27, 27) [000396] *A-XG------- +--* IND int N022 ( 25, 25) [000868] -A--G--N---- | \--* ADD byref $28c N020 ( 24, 24) [001251] -A--G------- | +--* COMMA byref N018 ( 23, 23) [001249] -A--G---R--- | | +--* ASG byref $VN.Void N017 ( 1, 1) [001248] D------N---- | | | +--* LCL_VAR byref V65 cse0 d:1 N016 ( 23, 23) [000882] -A--G--N---- | | | \--* ADDR byref $82 N015 ( 12, 12) [000394] aA--G--N---- | | | \--* IND struct N014 ( 11, 11) [000878] -A-----N---- | | | \--* ADD byref $82 N001 ( 1, 1) [000869] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 10, 10) [000877] -A-----N---- | | | \--* ADD long $329 N011 ( 9, 9) [000875] -A-----N---- | | | +--* LSH long $328 N009 ( 8, 8) [001278] -A---------- | | | | +--* COMMA long $327 N007 ( 7, 7) [001276] -A------R--- | | | | | +--* ASG long $VN.Void N006 ( 1, 1) [001275] D------N---- | | | | | | +--* LCL_VAR long V70 cse5 d:1 $327 N005 ( 7, 7) [000881] ------------ | | | | | | \--* MUL long $327 N003 ( 2, 3) [000873] ------------ | | | | | | +--* CAST long <- int $326 N002 ( 1, 1) [000870] i----------- | | | | | | | \--* LCL_VAR int V09 loc5 u:4 $3c2 N004 ( 1, 1) [000880] ------------ | | | | | | \--* CNS_INT long 3 $24b N008 ( 1, 1) [001277] ------------ | | | | | \--* LCL_VAR long V70 cse5 u:1 $327 N010 ( 1, 1) [000874] -------N---- | | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000876] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N019 ( 1, 1) [001250] ------------ | | \--* LCL_VAR byref V65 cse0 u:1 N021 ( 1, 1) [000867] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N024 ( 1, 1) [000397] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 ------------ BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} ***** BB25 STMT00069 (IL 0x120...0x135) N027 ( 47, 36) [000428] --CXG------- * JTRUE void N026 ( 45, 34) [000427] J-CXG--N---- \--* NE int $1bd N024 ( 43, 32) [000425] --CXG------- +--* CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals $581 N023 ( 9, 8) [000908] n--X-------- control expr | \--* IND long N022 ( 7, 6) [000907] ---X---N---- | \--* ADD long $32e N020 ( 6, 5) [000905] #--X-------- | +--* IND long $465 N019 ( 4, 3) [000904] ---X---N---- | | \--* ADD long $32c N017 ( 3, 2) [000902] #--X-------- | | +--* IND long $463 N016 ( 1, 1) [000901] ------------ | | | \--* LCL_VAR ref V12 loc8 u:1 $223 N018 ( 1, 1) [000903] ------------ | | \--* CNS_INT int 72 $c9 N021 ( 1, 1) [000906] ------------ | \--* CNS_INT int 32 $d2 N013 ( 12, 11) [000897] *---G--N---- arg1 in rdx | +--* IND ref N012 ( 9, 9) [000896] ----G------- | | \--* ADDR byref Zero Fseq[key] $84 N011 ( 5, 5) [000421] a---G--N---- | | \--* IND struct N010 ( 4, 4) [000892] -------N---- | | \--* ADD byref $82 N004 ( 1, 1) [000883] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N009 ( 3, 3) [000891] -------N---- | | \--* ADD long $329 N007 ( 2, 2) [000889] -------N---- | | +--* LSH long $328 N005 ( 1, 1) [001279] ------------ | | | +--* LCL_VAR long V70 cse5 u:1 $327 N006 ( 1, 1) [000888] -------N---- | | | \--* CNS_INT long 3 $24b N008 ( 1, 1) [000890] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N014 ( 1, 1) [000418] ------------ this in rcx | +--* LCL_VAR ref V12 loc8 u:1 $223 N015 ( 1, 1) [000424] ------------ arg2 in r8 | \--* LCL_VAR ref V01 arg1 u:1 $101 N025 ( 1, 1) [000426] ------------ \--* CNS_INT int 0 $c0 ------------ BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} ***** BB26 STMT00065 (IL 0x157...0x164) N006 ( 4, 4) [000406] -A-XG---R--- * ASG int N005 ( 1, 1) [000405] D------N---- +--* LCL_VAR int V09 loc5 d:5 N004 ( 4, 4) [000404] *--XG------- \--* IND int N003 ( 2, 2) [000932] ----G--N---- \--* ADD byref $28e N001 ( 1, 1) [001252] ------------ +--* LCL_VAR byref V65 cse0 u:1 $82 N002 ( 1, 1) [000931] ------------ \--* CNS_INT long 20 field offset Fseq[next] $24c ***** BB26 STMT00066 (IL 0x166...0x169) N005 ( 3, 3) [000411] -A------R--- * ASG int $605 N004 ( 1, 1) [000410] D------N---- +--* LCL_VAR int V07 loc3 d:6 $605 N003 ( 3, 3) [000409] ------------ \--* ADD int $605 N001 ( 1, 1) [000407] ------------ +--* LCL_VAR int V07 loc3 u:5 (last use) $3c1 N002 ( 1, 1) [000408] ------------ \--* CNS_INT int 1 $c1 ***** BB26 STMT00067 (IL 0x16A...0x16E) N004 ( 5, 5) [000416] ------------ * JTRUE void N003 ( 3, 3) [000415] N------N-U-- \--* LT int N001 ( 1, 1) [001321] ------------ +--* LCL_VAR int V76 cse11 N002 ( 1, 1) [000412] ------------ \--* LCL_VAR int V07 loc3 u:6 $605 ------------ BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} ------------ BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} ***** BB28 STMT00070 (IL 0x137...0x139) N005 ( 7, 8) [000432] ------------ * JTRUE void N004 ( 5, 6) [000431] N------N-U-- \--* NE int $1bf N002 ( 3, 4) [000909] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000429] ------------ | \--* LCL_VAR int V03 arg3 u:1 $140 N003 ( 1, 1) [000430] ------------ \--* CNS_INT int 1 $c1 ------------ BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} ***** BB29 STMT00077 (IL 0x13B...0x144) N006 ( 6, 6) [000481] -A-XG------- * ASG ref $VN.Void N004 ( 4, 4) [000480] *--XG--N---- +--* IND ref $102 N003 ( 2, 2) [000911] ----G--N---- | \--* ADD byref $28d N001 ( 1, 1) [001253] ------------ | +--* LCL_VAR byref V65 cse0 u:1 $82 N002 ( 1, 1) [000910] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N005 ( 1, 1) [000479] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 ------------ BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} ***** BB30 STMT00071 (IL 0x14B...0x14D) N005 ( 7, 8) [000436] ------------ * JTRUE void N004 ( 5, 6) [000435] N------N-U-- \--* EQ int $600 N002 ( 3, 4) [000926] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000433] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) $140 N003 ( 1, 1) [000434] ------------ \--* CNS_INT int 2 $c2 ------------ BB31 [???..???) (return), preds={BB30,BB41} succs={} ***** BB31 STMT00148 (IL ???... ???) N002 ( 2, 2) [000811] ------------ * RETURN int $1f3 N001 ( 1, 1) [000437] ------------ \--* CNS_INT int 0 $c0 ------------ BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} ***** BB32 STMT00175 (IL ???... ???) N005 ( 0, 0) [001208] -A------R--- * ASG int N004 ( 0, 0) [001206] D------N---- +--* LCL_VAR int V07 loc3 d:3 N003 ( 0, 0) [001207] ------------ \--* PHI int N001 ( 0, 0) [001229] ------------ pred BB43 +--* PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [001218] ------------ pred BB18 \--* PHI_ARG int V07 loc3 u:1 $c0 ***** BB32 STMT00174 (IL ???... ???) N005 ( 0, 0) [001205] -A------R--- * ASG int N004 ( 0, 0) [001203] D------N---- +--* LCL_VAR int V09 loc5 d:2 N003 ( 0, 0) [001204] ------------ \--* PHI int N001 ( 0, 0) [001230] ------------ pred BB43 +--* PHI_ARG int V09 loc5 u:3 N002 ( 0, 0) [001219] ------------ pred BB18 \--* PHI_ARG int V09 loc5 u:1 ***** BB32 STMT00014 (IL 0x177...0x17C) N009 ( 8, 8) [000066] -A-X-------- * JTRUE void N008 ( 6, 6) [000065] NA-X---N-U-- \--* LE int N006 ( 4, 4) [001325] -A-X-------- +--* COMMA int N004 ( 3, 3) [001323] -A-X----R--- | +--* ASG int $VN.Void N003 ( 1, 1) [001322] D------N---- | | +--* LCL_VAR int V76 cse11 N002 ( 3, 3) [000064] ---X-------- | | \--* ARR_LENGTH int N001 ( 1, 1) [000063] ------------ | | \--* LCL_VAR ref V04 loc0 u:1 N005 ( 1, 1) [001324] ------------ | \--* LCL_VAR int V76 cse11 N007 ( 1, 1) [000062] ------------ \--* LCL_VAR int V09 loc5 u:2 $3c4 ------------ BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} ***** BB33 STMT00039 (IL 0x17E...0x18C) N026 ( 31, 31) [000215] -A-XG------- * JTRUE void N025 ( 29, 29) [000214] NA-XG--N-U-- \--* NE int N023 ( 27, 27) [000212] *A-XG------- +--* IND int N022 ( 25, 25) [000948] -A--G--N---- | \--* ADD byref $2ac N020 ( 24, 24) [001257] -A--G------- | +--* COMMA byref N018 ( 23, 23) [001255] -A--G---R--- | | +--* ASG byref $VN.Void N017 ( 1, 1) [001254] D------N---- | | | +--* LCL_VAR byref V66 cse1 d:1 N016 ( 23, 23) [000962] -A--G--N---- | | | \--* ADDR byref $91 N015 ( 12, 12) [000210] aA--G--N---- | | | \--* IND struct N014 ( 11, 11) [000958] -A-----N---- | | | \--* ADD byref $91 N001 ( 1, 1) [000949] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N013 ( 10, 10) [000957] -A-----N---- | | | \--* ADD long $6e4 N011 ( 9, 9) [000955] -A-----N---- | | | +--* LSH long $6e3 N009 ( 8, 8) [001283] -A---------- | | | | +--* COMMA long $6e2 N007 ( 7, 7) [001281] -A------R--- | | | | | +--* ASG long $VN.Void N006 ( 1, 1) [001280] D------N---- | | | | | | +--* LCL_VAR long V71 cse6 d:1 $6e2 N005 ( 7, 7) [000961] ------------ | | | | | | \--* MUL long $6e2 N003 ( 2, 3) [000953] ------------ | | | | | | +--* CAST long <- int $6e1 N002 ( 1, 1) [000950] i----------- | | | | | | | \--* LCL_VAR int V09 loc5 u:2 $3c4 N004 ( 1, 1) [000960] ------------ | | | | | | \--* CNS_INT long 3 $24b N008 ( 1, 1) [001282] ------------ | | | | | \--* LCL_VAR long V71 cse6 u:1 $6e2 N010 ( 1, 1) [000954] -------N---- | | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [000956] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N019 ( 1, 1) [001256] ------------ | | \--* LCL_VAR byref V66 cse1 u:1 N021 ( 1, 1) [000947] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N024 ( 1, 1) [000213] ------------ \--* LCL_VAR int V06 loc2 u:1 $3c0 ------------ BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} ***** BB34 STMT00045 (IL 0x18E...0x1A2) N012 ( 12, 11) [000246] -A--G---R--- * ASG ref N011 ( 1, 1) [000245] D------N---- +--* LCL_VAR ref V17 tmp3 d:1 N010 ( 12, 11) [000977] *---G--N---- \--* IND ref N009 ( 9, 9) [000976] ----G------- \--* ADDR byref Zero Fseq[key] $93 N008 ( 5, 5) [000237] a---G--N---- \--* IND struct N007 ( 4, 4) [000972] -------N---- \--* ADD byref $91 N001 ( 1, 1) [000963] ------------ +--* LCL_VAR ref V04 loc0 u:1 N006 ( 3, 3) [000971] -------N---- \--* ADD long $6e4 N004 ( 2, 2) [000969] -------N---- +--* LSH long $6e3 N002 ( 1, 1) [001284] ------------ | +--* LCL_VAR long V71 cse6 u:1 $6e2 N003 ( 1, 1) [000968] -------N---- | \--* CNS_INT long 3 $24b N005 ( 1, 1) [000970] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB34 STMT00044 (IL 0x18E... ???) N004 ( 3, 3) [000244] -A---O--R--- * ASG long $2e8 N003 ( 1, 1) [000243] D------N---- +--* LCL_VAR long V16 tmp2 d:1 $2e7 N002 ( 3, 2) [000242] #----O------ \--* IND long $2e8 N001 ( 1, 1) [000241] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB34 STMT00158 (IL ???... ???) N015 ( 15, 14) [001163] -A---------- * JTRUE void N014 ( 13, 12) [000263] JA-----N---- \--* EQ int N012 ( 11, 10) [001263] -A---------- +--* COMMA long N010 ( 10, 9) [001261] -A------R--- | +--* ASG long $VN.Void N009 ( 1, 1) [001260] D------N---- | | +--* LCL_VAR long V67 cse2 d:1 N008 ( 10, 9) [000259] n----------- | | \--* IND long N007 ( 8, 7) [000255] -------N---- | | \--* ADD long $6e6 N005 ( 7, 6) [000253] #----------- | | +--* IND long $2ea N004 ( 4, 4) [000252] #----------- | | | \--* IND long $2e9 N003 ( 2, 2) [000251] -------N---- | | | \--* ADD long $306 N001 ( 1, 1) [000249] ------------ | | | +--* LCL_VAR long V16 tmp2 u:1 $2e7 N002 ( 1, 1) [000250] ------------ | | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000254] ------------ | | \--* CNS_INT long 48 $246 N011 ( 1, 1) [001262] ------------ | \--* LCL_VAR long V67 cse2 u:1 N013 ( 1, 1) [000262] ------------ \--* CNS_INT long 0 $243 ------------ BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} ***** BB35 STMT00159 (IL ???... ???) N003 ( 1, 3) [001165] -A------R--- * ASG long N002 ( 1, 1) [001164] D------N---- +--* LCL_VAR long V19 tmp5 d:3 N001 ( 1, 1) [001264] ------------ \--* LCL_VAR long V67 cse2 u:1 ------------ BB36 [???..???), preds={BB34} succs={BB37} ***** BB36 STMT00160 (IL ???... ???) N007 ( 17, 18) [001167] -AC-G---R--- * ASG long $6e7 N006 ( 1, 1) [001166] D------N---- +--* LCL_VAR long V19 tmp5 d:2 $6e7 N005 ( 17, 18) [000261] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $6e7 N003 ( 1, 1) [000248] ------?----- arg0 in rcx +--* LCL_VAR long V16 tmp2 u:1 (last use) $2e7 N004 ( 2, 10) [000260] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $63 ------------ BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} ***** BB37 STMT00176 (IL ???... ???) N005 ( 0, 0) [001211] -A------R--- * ASG long N004 ( 0, 0) [001209] D------N---- +--* LCL_VAR long V19 tmp5 d:1 N003 ( 0, 0) [001210] ------------ \--* PHI long N001 ( 0, 0) [001234] ------------ pred BB35 +--* PHI_ARG long V19 tmp5 u:3 N002 ( 0, 0) [001233] ------------ pred BB36 \--* PHI_ARG long V19 tmp5 u:2 $6e7 ***** BB37 STMT00049 (IL ???... ???) N013 ( 32, 18) [000283] --CXG------- * JTRUE void N012 ( 30, 16) [000282] J-CXG--N---- \--* EQ int $817 N010 ( 28, 14) [000280] --CXG------- +--* CALL ind stub int $1ef N009 ( 1, 1) [000279] ------------ calli tgt | \--* LCL_VAR long V19 tmp5 u:1 (last use) $349 N005 ( 1, 1) [000234] ------------ this in rcx | +--* LCL_VAR ref V05 loc1 u:1 N006 ( 1, 1) [000980] ------------ arg1 in r11 | +--* LCL_VAR long V19 tmp5 u:1 r11 REG r11 $349 N007 ( 1, 1) [000247] ------------ arg2 in rdx | +--* LCL_VAR ref V17 tmp3 u:1 (last use) N008 ( 1, 1) [000258] ------------ arg3 in r8 | \--* LCL_VAR ref V01 arg1 u:1 $101 N011 ( 1, 1) [000281] ------------ \--* CNS_INT int 0 $c0 ------------ BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} ***** BB38 STMT00050 (IL 0x1A4...0x1A6) N005 ( 7, 8) [000287] ------------ * JTRUE void N004 ( 5, 6) [000286] N------N-U-- \--* NE int $1bf N002 ( 3, 4) [000985] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000284] ------------ | \--* LCL_VAR int V03 arg3 u:1 $140 N003 ( 1, 1) [000285] ------------ \--* CNS_INT int 1 $c1 ------------ BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} ***** BB39 STMT00057 (IL 0x1A8...0x1B1) N006 ( 6, 6) [000336] -A-XG------- * ASG ref $VN.Void N004 ( 4, 4) [000335] *--XG--N---- +--* IND ref $102 N003 ( 2, 2) [000987] ----G--N---- | \--* ADD byref $2ae N001 ( 1, 1) [001258] ------------ | +--* LCL_VAR byref V66 cse1 u:1 $91 N002 ( 1, 1) [000986] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N005 ( 1, 1) [000334] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 ------------ BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} ***** BB40 STMT00051 (IL 0x1B8...0x1BA) N005 ( 7, 8) [000291] ------------ * JTRUE void N004 ( 5, 6) [000290] N------N-U-- \--* EQ int $600 N002 ( 3, 4) [001002] ------------ +--* CAST int <- ubyte <- int $1be N001 ( 2, 2) [000288] ------------ | \--* LCL_VAR int V03 arg3 u:1 (last use) $140 N003 ( 1, 1) [000289] ------------ \--* CNS_INT int 2 $c2 ------------ BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} ------------ BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} ***** BB42 STMT00040 (IL 0x1C4...0x1D1) N006 ( 4, 4) [000222] -A-XG---R--- * ASG int N005 ( 1, 1) [000221] D------N---- +--* LCL_VAR int V09 loc5 d:3 N004 ( 4, 4) [000220] *--XG------- \--* IND int N003 ( 2, 2) [001009] ----G--N---- \--* ADD byref $2ad N001 ( 1, 1) [001259] ------------ +--* LCL_VAR byref V66 cse1 u:1 $91 N002 ( 1, 1) [001008] ------------ \--* CNS_INT long 20 field offset Fseq[next] $24c ***** BB42 STMT00041 (IL 0x1D3...0x1D6) N005 ( 3, 3) [000227] -A------R--- * ASG int $81a N004 ( 1, 1) [000226] D------N---- +--* LCL_VAR int V07 loc3 d:4 $81a N003 ( 3, 3) [000225] ------------ \--* ADD int $81a N001 ( 1, 1) [000223] ------------ +--* LCL_VAR int V07 loc3 u:3 (last use) $3c3 N002 ( 1, 1) [000224] ------------ \--* CNS_INT int 1 $c1 ***** BB42 STMT00042 (IL 0x1D7...0x1DB) N004 ( 5, 5) [000232] ------------ * JTRUE void N003 ( 3, 3) [000231] N------N-U-- \--* LT int N001 ( 1, 1) [001328] ------------ +--* LCL_VAR int V76 cse11 N002 ( 1, 1) [000228] ------------ \--* LCL_VAR int V07 loc3 u:4 $81a ------------ BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} ------------ BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} ***** BB44 STMT00166 (IL ???... ???) N005 ( 0, 0) [001181] -A------R--- * ASG int N004 ( 0, 0) [001179] D------N---- +--* LCL_VAR int V07 loc3 d:2 N003 ( 0, 0) [001180] ------------ \--* PHI int N001 ( 0, 0) [001237] ------------ pred BB23 +--* PHI_ARG int V07 loc3 u:5 $3c1 N002 ( 0, 0) [001228] ------------ pred BB32 \--* PHI_ARG int V07 loc3 u:3 $3c3 ***** BB44 STMT00015 (IL 0x1E4...0x1EB) N007 ( 8, 8) [000071] ----GO------ * JTRUE void N006 ( 6, 6) [000070] J---GO-N---- \--* LE int N004 ( 4, 4) [000068] n---GO------ +--* IND int N003 ( 2, 2) [001025] -------N---- | \--* ADD byref $28f N001 ( 1, 1) [000067] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001024] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N005 ( 1, 1) [000069] ------------ \--* CNS_INT int 0 $c0 ------------ BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} ***** BB45 STMT00035 (IL 0x1ED...0x1F3) N010 ( 15, 12) [000174] -A--GO--R--- * ASG int N009 ( 3, 2) [000173] D------N---- +--* LCL_VAR int V10 loc6 d:3 N008 ( 11, 9) [001308] -A--GO------ \--* COMMA int N006 ( 8, 7) [001306] -A--GO--R--- +--* ASG int $VN.Void N005 ( 3, 2) [001305] D------N---- | +--* LCL_VAR int V74 cse9 d:1 N004 ( 4, 4) [000172] n---GO------ | \--* IND int N003 ( 2, 2) [001027] -------N---- | \--* ADD byref $295 N001 ( 1, 1) [000171] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001026] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N007 ( 3, 2) [001307] ------------ \--* LCL_VAR int V74 cse9 u:1 ***** BB45 STMT00120 (IL 0x1F5... ???) N030 ( 45, 44) [000688] -A-XG---R--- * ASG bool N029 ( 3, 2) [000687] D------N---- +--* LCL_VAR int V49 tmp35 d:1 N028 ( 41, 41) [000184] -A-XG------- \--* GE int N026 ( 36, 39) [000182] -A-XG------- +--* ADD int N024 ( 34, 37) [001050] -A-XG------- | +--* NEG int N023 ( 33, 36) [000181] *A-XG------- | | \--* IND int N022 ( 31, 34) [001029] -A-XG--N---- | | \--* ADD byref $29c N020 ( 30, 33) [001044] -A-XG------- | | +--* COMMA byref N003 ( 3, 3) [001032] -A--G---R--- | | | +--* ASG int N002 ( 1, 1) [001031] D------N---- | | | | +--* LCL_VAR int V62 tmp48 d:1 N001 ( 3, 2) [001309] ------------ | | | | \--* LCL_VAR int V74 cse9 u:1 N019 ( 27, 30) [001043] ---XG------- | | | \--* COMMA byref N006 ( 6, 9) [001036] ---X-------- | | | +--* ARR_BOUNDS_CHECK_Rng void N004 ( 1, 1) [001033] ------------ | | | | +--* LCL_VAR int V62 tmp48 u:1 N005 ( 1, 1) [001329] ------------ | | | | \--* LCL_VAR int V76 cse11 N018 ( 21, 21) [001049] ----G------- | | | \--* ADDR byref $88 N017 ( 11, 11) [000179] a---G--N---- | | | \--* IND struct N016 ( 10, 10) [001042] -------N---- | | | \--* ADD byref $88 N007 ( 1, 1) [001030] ------------ | | | +--* LCL_VAR ref V04 loc0 u:1 N015 ( 9, 9) [001041] -------N---- | | | \--* ADD long N013 ( 8, 8) [001039] -------N---- | | | +--* LSH long N011 ( 7, 7) [001048] ------------ | | | | +--* MUL long N009 ( 2, 3) [001037] ------------ | | | | | +--* CAST long <- int N008 ( 1, 1) [001034] i----------- | | | | | | \--* LCL_VAR int V62 tmp48 u:1 (last use) N010 ( 1, 1) [001047] ------------ | | | | | \--* CNS_INT long 3 $24b N012 ( 1, 1) [001038] -------N---- | | | | \--* CNS_INT long 3 $24b N014 ( 1, 1) [001040] ------------ | | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N021 ( 1, 1) [001028] ------------ | | \--* CNS_INT long 20 field offset Fseq[next] $24c N025 ( 1, 1) [000175] ------------ | \--* CNS_INT int -3 $e1 N027 ( 1, 1) [000183] ------------ \--* CNS_INT int -1 $c4 ***** BB45 STMT00123 (IL 0x1F5... ???) N003 ( 5, 4) [000698] -A--G---R--- * ASG ref $105 N002 ( 3, 2) [000697] D------N---- +--* LCL_VAR ref V50 tmp36 d:1 $105 N001 ( 1, 1) [001300] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB45 STMT00121 (IL 0x1F5... ???) N004 ( 7, 6) [000693] ------------ * JTRUE void N003 ( 5, 4) [000692] J------N---- \--* NE int N001 ( 3, 2) [000690] ------------ +--* LCL_VAR int V49 tmp35 u:1 (last use) N002 ( 1, 1) [000691] ------------ \--* CNS_INT int 0 $c0 ------------ BB46 [1F5..1F6), preds={BB45} succs={BB47} ***** BB46 STMT00122 (IL 0x1F5... ???) N006 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N004 ( 4, 12) [001052] #---G------- arg0 in rcx +--* IND ref $114 N003 ( 2, 10) [001051] H----------- | \--* CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" $5e N005 ( 3, 2) [000695] ------------ arg1 in rdx \--* LCL_VAR ref V50 tmp36 u:1 (last use) $105 ------------ BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} ***** BB47 STMT00037 (IL 0x219... ???) N034 ( 42, 45) [000200] -A-XGO------ * ASG int $VN.Void N004 ( 4, 4) [000199] n---GO-N---- +--* IND int $732 N003 ( 2, 2) [001056] -------N---- | \--* ADD byref $295 N001 ( 1, 1) [000190] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001055] ------------ | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N033 ( 37, 40) [000198] -A-XGO------ \--* ADD int N031 ( 35, 38) [001079] -A-XGO------ +--* NEG int N030 ( 34, 37) [000197] *A-XGO------ | \--* IND int N029 ( 32, 35) [001058] -A-XGO-N---- | \--* ADD byref $2a3 N027 ( 31, 34) [001073] -A-XGO------ | +--* COMMA byref N010 ( 4, 4) [001061] -A--GO--R--- | | +--* ASG int N009 ( 1, 1) [001060] D------N---- | | | +--* LCL_VAR int V63 tmp49 d:1 N008 ( 4, 4) [000194] n---GO------ | | | \--* IND int N007 ( 2, 2) [001075] -------N---- | | | \--* ADD byref $295 N005 ( 1, 1) [000193] ------------ | | | +--* LCL_VAR ref V00 this u:1 $100 N006 ( 1, 1) [001074] ------------ | | | \--* CNS_INT long 60 field offset Fseq[_freeList] $24d N026 ( 27, 30) [001072] ---XG------- | | \--* COMMA byref N013 ( 6, 9) [001065] ---X-------- | | +--* ARR_BOUNDS_CHECK_Rng void N011 ( 1, 1) [001062] ------------ | | | +--* LCL_VAR int V63 tmp49 u:1 N012 ( 1, 1) [001330] ------------ | | | \--* LCL_VAR int V76 cse11 N025 ( 21, 21) [001078] ----G------- | | \--* ADDR byref $8a N024 ( 11, 11) [000195] a---G--N---- | | \--* IND struct N023 ( 10, 10) [001071] -------N---- | | \--* ADD byref $8a N014 ( 1, 1) [001059] ------------ | | +--* LCL_VAR ref V04 loc0 u:1 N022 ( 9, 9) [001070] -------N---- | | \--* ADD long N020 ( 8, 8) [001068] -------N---- | | +--* LSH long N018 ( 7, 7) [001077] ------------ | | | +--* MUL long N016 ( 2, 3) [001066] ------------ | | | | +--* CAST long <- int N015 ( 1, 1) [001063] i----------- | | | | | \--* LCL_VAR int V63 tmp49 u:1 (last use) N017 ( 1, 1) [001076] ------------ | | | | \--* CNS_INT long 3 $24b N019 ( 1, 1) [001067] -------N---- | | | \--* CNS_INT long 3 $24b N021 ( 1, 1) [001069] ------------ | | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N028 ( 1, 1) [001057] ------------ | \--* CNS_INT long 20 field offset Fseq[next] $24c N032 ( 1, 1) [000191] ------------ \--* CNS_INT int -3 $e1 ***** BB47 STMT00038 (IL 0x233...0x23C) N011 ( 11, 11) [000207] -A--GO--R--- * ASG int $VN.Void N010 ( 4, 4) [000206] n---GO-N---- +--* IND int $73a N009 ( 2, 2) [001081] -------N---- | \--* ADD byref $28f N007 ( 1, 1) [000201] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001080] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N006 ( 6, 6) [000205] ----GO------ \--* ADD int N004 ( 4, 4) [000203] n---GO------ +--* IND int N003 ( 2, 2) [001083] -------N---- | \--* ADD byref $28f N001 ( 1, 1) [000202] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001082] ------------ | \--* CNS_INT long 64 field offset Fseq[_freeCount] $245 N005 ( 1, 1) [000204] ------------ \--* CNS_INT int -1 $c4 ------------ BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} ***** BB48 STMT00016 (IL 0x243...0x249) N010 ( 15, 12) [000075] -A--GO--R--- * ASG int N009 ( 3, 2) [000074] D------N---- +--* LCL_VAR int V13 loc9 d:1 N008 ( 11, 9) [001313] -A--GO------ \--* COMMA int N006 ( 8, 7) [001311] -A--GO--R--- +--* ASG int $VN.Void N005 ( 3, 2) [001310] D------N---- | +--* LCL_VAR int V75 cse10 d:1 N004 ( 4, 4) [000073] n---GO------ | \--* IND int N003 ( 2, 2) [001085] -------N---- | \--* ADD byref $290 N001 ( 1, 1) [000072] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001084] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] $244 N007 ( 3, 2) [001312] ------------ \--* LCL_VAR int V75 cse10 u:1 ***** BB48 STMT00017 (IL 0x24B...0x250) N004 ( 7, 6) [000080] ------------ * JTRUE void N003 ( 5, 4) [000079] N------N-U-- \--* NE int N001 ( 1, 1) [001331] ------------ +--* LCL_VAR int V76 cse11 N002 ( 3, 2) [000076] ------------ \--* LCL_VAR int V13 loc9 u:1 ------------ BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ***** BB49 STMT00125 (IL 0x252... ???) N011 ( 43, 24) [000705] -ACXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void N006 ( 21, 11) [001090] -ACXG---R-L- arg1 SETUP +--* ASG int $1d7 N005 ( 3, 2) [001089] D------N---- | +--* LCL_VAR int V64 tmp50 d:1 $1d7 N004 ( 17, 8) [000702] --CXG------- | \--* CALL int System.Collections.HashHelpers.ExpandPrime $1d7 N003 ( 3, 2) [001314] ------------ arg0 in rcx | \--* LCL_VAR int V75 cse10 u:1 N008 ( 3, 2) [001091] ------------ arg1 in rdx +--* LCL_VAR int V64 tmp50 u:1 (last use) $1d7 N009 ( 1, 1) [000163] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N010 ( 1, 1) [000704] ------------ arg2 in r8 \--* CNS_INT int 0 $c0 ***** BB49 STMT00126 (IL 0x258... ???) N006 ( 8, 7) [000711] -A--GO--R--- * ASG ref N005 ( 3, 2) [000710] D------N---- +--* LCL_VAR ref V52 tmp38 d:1 N004 ( 4, 4) [000709] n---GO------ \--* IND ref N003 ( 2, 2) [001095] -------N---- \--* ADD byref $280 N001 ( 1, 1) [000165] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001094] ------------ \--* CNS_INT long 8 field offset Fseq[_buckets] $240 ***** BB49 STMT00133 (IL 0x258... ???) N008 ( 12, 9) [000760] -A-X----R--- * ASG int N007 ( 1, 1) [000759] D------N---- +--* LCL_VAR int V53 tmp39 d:1 N006 ( 12, 9) [001288] -A-X-------- \--* COMMA int N004 ( 9, 7) [001286] -A-X----R--- +--* ASG int $VN.Void N003 ( 3, 2) [001285] D------N---- | +--* LCL_VAR int V72 cse7 d:1 N002 ( 5, 4) [000714] ---X-------- | \--* ARR_LENGTH int N001 ( 3, 2) [000713] ------------ | \--* LCL_VAR ref V52 tmp38 u:1 N005 ( 3, 2) [001287] ------------ \--* LCL_VAR int V72 cse7 u:1 ***** BB49 STMT00134 (IL 0x258... ???) N006 ( 8, 7) [000762] -A--GO--R--- * ASG long N005 ( 3, 2) [000761] D------N---- +--* LCL_VAR long V54 tmp40 d:1 N004 ( 4, 4) [000716] n---GO------ \--* IND long N003 ( 2, 2) [001097] -------N---- \--* ADD byref $283 N001 ( 1, 1) [000715] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001096] ------------ \--* CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 ***** BB49 STMT00136 (IL 0x258... ???) N005 ( 10, 9) [000773] -A------R--- * ASG bool N004 ( 3, 2) [000772] D------N---- +--* LCL_VAR int V56 tmp42 d:1 N003 ( 6, 6) [000730] N--------U-- \--* LE int N001 ( 1, 1) [000728] ------------ +--* LCL_VAR int V53 tmp39 u:1 N002 ( 1, 4) [000729] ------------ \--* CNS_INT int 0x7FFFFFFF $ce ***** BB49 STMT00139 (IL 0x258... ???) N003 ( 5, 4) [000783] -A--G---R--- * ASG ref $105 N002 ( 3, 2) [000782] D------N---- +--* LCL_VAR ref V57 tmp43 d:1 $105 N001 ( 1, 1) [001301] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB49 STMT00140 (IL 0x258... ???) N003 ( 5, 4) [000785] -A--G---R--- * ASG ref $105 N002 ( 3, 2) [000784] D------N---- +--* LCL_VAR ref V58 tmp44 d:1 $105 N001 ( 1, 1) [001302] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB49 STMT00137 (IL 0x258... ???) N004 ( 7, 6) [000778] ------------ * JTRUE void N003 ( 5, 4) [000777] J------N---- \--* NE int N001 ( 3, 2) [000775] ------------ +--* LCL_VAR int V56 tmp42 u:1 (last use) N002 ( 1, 1) [000776] ------------ \--* CNS_INT int 0 $c0 ------------ BB50 [258..259), preds={BB49} succs={BB51} ***** BB50 STMT00138 (IL 0x258... ???) N005 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 3, 2) [000779] ------------ arg0 in rcx +--* LCL_VAR ref V58 tmp44 u:1 (last use) $105 N004 ( 3, 2) [000780] ------------ arg1 in rdx \--* LCL_VAR ref V58 tmp44 u:1 (last use) $105 ------------ BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} ***** BB51 STMT00131 (IL 0x258... ???) N016 ( 26, 25) [000750] -A------R--- * ASG int N015 ( 3, 2) [000749] D------N---- +--* LCL_VAR int V55 tmp41 d:1 N014 ( 22, 22) [000748] ------------ \--* CAST int <- uint <- long N013 ( 21, 20) [000747] ------------ \--* RSZ long N011 ( 19, 18) [000745] ------------ +--* MUL long N008 ( 13, 12) [000742] ------------ | +--* ADD long N006 ( 11, 10) [000739] ------------ | | +--* RSZ long N004 ( 9, 8) [000737] ------------ | | | +--* MUL long N001 ( 3, 2) [000735] ------------ | | | | +--* LCL_VAR long V54 tmp40 u:1 (last use) N003 ( 2, 3) [000736] ---------U-- | | | | \--* CAST long <- ulong <- uint $310 N002 ( 1, 1) [000166] ------------ | | | | \--* LCL_VAR int V06 loc2 u:1 $3c0 N005 ( 1, 1) [000738] ------------ | | | \--* CNS_INT int 32 $d2 N007 ( 1, 1) [000741] ------------ | | \--* CNS_INT long 1 $247 N010 ( 2, 3) [000744] ---------U-- | \--* CAST long <- ulong <- uint N009 ( 1, 1) [000743] ------------ | \--* LCL_VAR int V53 tmp39 u:1 N012 ( 1, 1) [000746] ------------ \--* CNS_INT int 32 $d2 ***** BB51 STMT00142 (IL 0x258... ???) N007 ( 33, 11) [000796] -A-X----R--- * ASG bool N006 ( 3, 2) [000795] D------N---- +--* LCL_VAR int V59 tmp45 d:1 N005 ( 29, 8) [000755] ---X-------- \--* EQ int N003 ( 22, 5) [000754] ---X-------- +--* UMOD int N001 ( 1, 1) [000752] ------------ | +--* LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000753] ------------ | \--* LCL_VAR int V53 tmp39 u:1 (last use) N004 ( 3, 2) [000751] ------------ \--* LCL_VAR int V55 tmp41 u:1 ***** BB51 STMT00145 (IL 0x258... ???) N003 ( 5, 4) [000806] -A--G---R--- * ASG ref $105 N002 ( 3, 2) [000805] D------N---- +--* LCL_VAR ref V60 tmp46 d:1 $105 N001 ( 1, 1) [001303] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB51 STMT00146 (IL 0x258... ???) N003 ( 5, 4) [000808] -A--G---R--- * ASG ref $105 N002 ( 3, 2) [000807] D------N---- +--* LCL_VAR ref V61 tmp47 d:1 $105 N001 ( 1, 1) [001304] ------------ \--* LCL_VAR ref V73 cse8 u:1 $105 ***** BB51 STMT00143 (IL 0x258... ???) N004 ( 7, 6) [000801] ------------ * JTRUE void N003 ( 5, 4) [000800] J------N---- \--* NE int N001 ( 3, 2) [000798] ------------ +--* LCL_VAR int V59 tmp45 u:1 (last use) N002 ( 1, 1) [000799] ------------ \--* CNS_INT int 0 $c0 ------------ BB52 [258..259), preds={BB51} succs={BB53} ***** BB52 STMT00144 (IL 0x258... ???) N005 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void N003 ( 3, 2) [000802] ------------ arg0 in rcx +--* LCL_VAR ref V61 tmp47 u:1 (last use) $105 N004 ( 3, 2) [000803] ------------ arg1 in rdx \--* LCL_VAR ref V61 tmp47 u:1 (last use) $105 ------------ BB53 [258..259), preds={BB51,BB52} succs={BB54} ***** BB53 STMT00128 (IL 0x258... ???) N016 ( 33, 31) [000722] -A-XG---R--- * ASG byref N015 ( 3, 2) [000721] D------N---- +--* LCL_VAR byref V51 tmp37 d:1 $87 N014 ( 29, 28) [001112] ---XG------- \--* COMMA byref N003 ( 10, 11) [001105] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void N001 ( 3, 2) [000758] ------------ | +--* LCL_VAR int V55 tmp41 u:1 N002 ( 3, 2) [001289] ------------ | \--* LCL_VAR int V72 cse7 u:1 N013 ( 19, 17) [001113] ----G------- \--* ADDR byref $87 N012 ( 10, 9) [000719] a---G--N---- \--* IND int N011 ( 9, 8) [001111] -------N---- \--* ADD byref $87 N004 ( 3, 2) [001102] ------------ +--* LCL_VAR ref V52 tmp38 u:1 (last use) N010 ( 6, 6) [001110] -------N---- \--* ADD long N008 ( 5, 5) [001108] -------N---- +--* LSH long N006 ( 4, 4) [001106] ------------ | +--* CAST long <- int N005 ( 3, 2) [001103] i----------- | | \--* LCL_VAR int V55 tmp41 u:1 (last use) N007 ( 1, 1) [001107] -------N---- | \--* CNS_INT long 2 $248 N009 ( 1, 1) [001109] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB53 STMT00034 (IL ???... ???) N003 ( 7, 5) [000170] -A------R--- * ASG byref $87 N002 ( 3, 2) [000169] D------N---- +--* LCL_VAR byref V08 loc4 d:4 $87 N001 ( 3, 2) [000723] ------------ \--* LCL_VAR byref V51 tmp37 u:1 (last use) $87 ------------ BB54 [261..276), preds={BB48,BB53} succs={BB55} ***** BB54 STMT00170 (IL ???... ???) N005 ( 0, 0) [001193] -A------R--- * ASG byref N004 ( 0, 0) [001191] D------N---- +--* LCL_VAR byref V08 loc4 d:3 N003 ( 0, 0) [001192] ------------ \--* PHI byref N001 ( 0, 0) [001224] ------------ pred BB53 +--* PHI_ARG byref V08 loc4 u:4 $87 N002 ( 0, 0) [001220] ------------ pred BB48 \--* PHI_ARG byref V08 loc4 u:1 $81 ***** BB54 STMT00018 (IL 0x261...0x263) N003 ( 7, 5) [000083] -A------R--- * ASG int N002 ( 3, 2) [000082] D------N---- +--* LCL_VAR int V10 loc6 d:2 N001 ( 3, 2) [000081] ------------ \--* LCL_VAR int V13 loc9 u:1 ***** BB54 STMT00019 (IL 0x265...0x26A) N008 ( 10, 9) [000089] -A--GO--R--- * ASG int $VN.Void N007 ( 4, 4) [000088] n---GO-N---- +--* IND int $708 N006 ( 2, 2) [001115] -------N---- | \--* ADD byref $290 N004 ( 1, 1) [000084] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N005 ( 1, 1) [001114] ------------ | \--* CNS_INT long 56 field offset Fseq[_count] $244 N003 ( 5, 4) [000087] ------------ \--* ADD int N001 ( 3, 2) [000085] ------------ +--* LCL_VAR int V10 loc6 u:2 (last use) N002 ( 1, 1) [000086] ------------ \--* CNS_INT int 1 $c1 ***** BB54 STMT00020 (IL 0x26F...0x275) N006 ( 4, 4) [000093] -A--GO--R--- * ASG ref N005 ( 1, 1) [000092] D------N---- +--* LCL_VAR ref V04 loc0 d:3 N004 ( 4, 4) [000091] n---GO------ \--* IND ref N003 ( 2, 2) [001117] -------N---- \--* ADD byref $281 N001 ( 1, 1) [000090] ------------ +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001116] ------------ \--* CNS_INT long 16 field offset Fseq[_entries] $241 ------------ BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} ***** BB55 STMT00171 (IL ???... ???) N005 ( 0, 0) [001196] -A------R--- * ASG byref N004 ( 0, 0) [001194] D------N---- +--* LCL_VAR byref V08 loc4 d:2 N003 ( 0, 0) [001195] ------------ \--* PHI byref N001 ( 0, 0) [001225] ------------ pred BB47 +--* PHI_ARG byref V08 loc4 u:1 $81 N002 ( 0, 0) [001221] ------------ pred BB54 \--* PHI_ARG byref V08 loc4 u:3 $780 ***** BB55 STMT00169 (IL ???... ???) N005 ( 0, 0) [001190] -A------R--- * ASG ref N004 ( 0, 0) [001188] D------N---- +--* LCL_VAR ref V04 loc0 d:2 N003 ( 0, 0) [001189] ------------ \--* PHI ref N001 ( 0, 0) [001226] ------------ pred BB47 +--* PHI_ARG ref V04 loc0 u:1 N002 ( 0, 0) [001222] ------------ pred BB54 \--* PHI_ARG ref V04 loc0 u:3 ***** BB55 STMT00168 (IL ???... ???) N005 ( 0, 0) [001187] -A------R--- * ASG int N004 ( 0, 0) [001185] D------N---- +--* LCL_VAR int V10 loc6 d:1 N003 ( 0, 0) [001186] ------------ \--* PHI int N001 ( 0, 0) [001227] ------------ pred BB47 +--* PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [001223] ------------ pred BB54 \--* PHI_ARG int V10 loc6 u:2 ***** BB55 STMT00021 (IL 0x276...0x27E) N019 ( 39, 38) [000099] -A-XG---R--- * ASG byref $2a6 N018 ( 3, 2) [000098] D------N---- +--* LCL_VAR byref V11 loc7 d:1 $8c N017 ( 35, 35) [001128] ---XG------- \--* COMMA byref $2a6 N004 ( 10, 12) [001121] ---X-------- +--* ARR_BOUNDS_CHECK_Rng void $7cd N001 ( 3, 2) [000095] ------------ | +--* LCL_VAR int V10 loc6 u:1 $3cc N003 ( 3, 3) [001120] ---X-------- | \--* ARR_LENGTH int $73d N002 ( 1, 1) [000094] ------------ | \--* LCL_VAR ref V04 loc0 u:2 $684 N016 ( 25, 23) [001131] ----G------- \--* ADDR byref $8c N015 ( 13, 12) [000096] a---G--N---- \--* IND struct N014 ( 12, 11) [001127] -------N---- \--* ADD byref $8c N005 ( 1, 1) [001118] ------------ +--* LCL_VAR ref V04 loc0 u:2 $684 N013 ( 11, 10) [001126] -------N---- \--* ADD long $6df N011 ( 10, 9) [001124] -------N---- +--* LSH long $6de N009 ( 9, 8) [001130] ------------ | +--* MUL long $6dd N007 ( 4, 4) [001122] ------------ | | +--* CAST long <- int $6dc N006 ( 3, 2) [001119] i----------- | | | \--* LCL_VAR int V10 loc6 u:1 $3cc N008 ( 1, 1) [001129] ------------ | | \--* CNS_INT long 3 $24b N010 ( 1, 1) [001123] -------N---- | \--* CNS_INT long 3 $24b N012 ( 1, 1) [001125] ------------ \--* CNS_INT long 16 Fseq[#FirstElem] $241 ***** BB55 STMT00022 (IL 0x280...0x283) N006 ( 8, 7) [000103] -A-XG------- * ASG int $VN.Void N004 ( 6, 5) [000102] *--XG--N---- +--* IND int $3c0 N003 ( 4, 3) [001133] -------N---- | \--* ADD byref $8d N001 ( 3, 2) [000100] ------------ | +--* LCL_VAR byref V11 loc7 u:1 $8c N002 ( 1, 1) [001132] ------------ | \--* CNS_INT long 16 field offset Fseq[hashCode] $241 N005 ( 1, 1) [000101] ------------ \--* LCL_VAR int V06 loc2 u:1 (last use) $3c0 ***** BB55 STMT00023 (IL 0x288...0x28F) N009 ( 15, 12) [000110] -A-XGO--R--- * ASG int $VN.Void N008 ( 6, 5) [000109] *---GO-N---- +--* IND int N007 ( 4, 3) [001135] -------N---- | \--* ADD byref $8e N005 ( 3, 2) [000104] ------------ | +--* LCL_VAR byref V11 loc7 u:1 $8c N006 ( 1, 1) [001134] ------------ | \--* CNS_INT long 20 field offset Fseq[next] $24c N004 ( 8, 6) [000108] ---XG------- \--* ADD int N002 ( 6, 4) [000106] *--XG------- +--* IND int N001 ( 3, 2) [000105] ------------ | \--* LCL_VAR byref V08 loc4 u:2 $781 N003 ( 1, 1) [000107] ------------ \--* CNS_INT int -1 $c4 ***** BB55 STMT00024 (IL 0x294...0x297) N004 ( 8, 6) [000114] -A-XG------- * ASG ref $VN.Void N002 ( 6, 4) [000113] *--XG--N---- +--* IND ref $101 N001 ( 3, 2) [000111] ------------ | \--* LCL_VAR byref V11 loc7 u:1 Zero Fseq[key] $8f N003 ( 1, 1) [000112] ------------ \--* LCL_VAR ref V01 arg1 u:1 (last use) $101 ***** BB55 STMT00025 (IL 0x29C...0x29F) N006 ( 8, 7) [000118] -A--GO------ * ASG ref $VN.Void N004 ( 6, 5) [000117] *---GO-N---- +--* IND ref $102 N003 ( 4, 3) [001137] -------N---- | \--* ADD byref $90 N001 ( 3, 2) [000115] ------------ | +--* LCL_VAR byref V11 loc7 u:1 (last use) $8c N002 ( 1, 1) [001136] ------------ | \--* CNS_INT long 8 field offset Fseq[value] $240 N005 ( 1, 1) [000116] ------------ \--* LCL_VAR ref V02 arg2 u:1 (last use) $102 ***** BB55 STMT00026 (IL 0x2A4...0x2AA) N006 ( 12, 9) [000124] -A--GO--R--- * ASG int $VN.Void N005 ( 6, 4) [000123] *----O-N---- +--* IND int $804 N004 ( 3, 2) [000119] ------------ | \--* LCL_VAR byref V08 loc4 u:2 (last use) $781 N003 ( 5, 4) [000122] ------------ \--* ADD int $804 N001 ( 3, 2) [000120] ------------ +--* LCL_VAR int V10 loc6 u:1 (last use) $3cc N002 ( 1, 1) [000121] ------------ \--* CNS_INT int 1 $c1 ***** BB55 STMT00027 (IL 0x2AB...0x2B4) N011 ( 11, 11) [000131] -A--GO--R--- * ASG int $VN.Void N010 ( 4, 4) [000130] n---GO-N---- +--* IND int $80a N009 ( 2, 2) [001139] -------N---- | \--* ADD byref $2a7 N007 ( 1, 1) [000125] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001138] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] $24e N006 ( 6, 6) [000129] ----GO------ \--* ADD int N004 ( 4, 4) [000127] n---GO------ +--* IND int N003 ( 2, 2) [001141] -------N---- | \--* ADD byref $2a7 N001 ( 1, 1) [000126] ------------ | +--* LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001140] ------------ | \--* CNS_INT long 68 field offset Fseq[_version] $24e N005 ( 1, 1) [000128] ------------ \--* CNS_INT int 1 $c1 ***** BB55 STMT00028 (IL 0x2CA...0x2CD) N004 ( 5, 5) [000148] ------------ * JTRUE void N003 ( 3, 3) [000147] N------N-U-- \--* LE int $80d N001 ( 1, 1) [000145] ------------ +--* LCL_VAR int V07 loc3 u:2 (last use) $3c5 N002 ( 1, 1) [000146] ------------ \--* CNS_INT int 100 $e3 ------------ BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} ***** BB56 STMT00030 (IL 0x2CF...0x2D5) N008 ( 21, 22) [000156] --C-G------- * JTRUE void N007 ( 19, 20) [000155] J-C-G--N---- \--* EQ int N005 ( 17, 18) [000153] --C-G------- +--* CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS N003 ( 1, 1) [000151] ------------ arg1 in rdx | +--* LCL_VAR ref V05 loc1 u:1 (last use) N004 ( 2, 10) [000152] H------N---- arg0 in rcx | \--* CNS_INT(h) long 0xd1ffab1e class $62 N006 ( 1, 1) [000154] ------------ \--* CNS_INT ref null $VN.Null ------------ BB57 [2D7..2E3), preds={BB56} succs={BB58} ***** BB57 STMT00031 (IL 0x2D7...0x2DC) N008 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void N005 ( 3, 3) [000159] ---X-------- arg1 in rdx +--* ARR_LENGTH int $73d N004 ( 1, 1) [000158] ------------ | \--* LCL_VAR ref V04 loc0 u:2 (last use) $684 N006 ( 1, 1) [000157] ------------ this in rcx +--* LCL_VAR ref V00 this u:1 $100 N007 ( 1, 1) [000160] ------------ arg2 in r8 \--* CNS_INT int 1 $c1 ------------ BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} ***** BB58 STMT00147 (IL ???... ???) N002 ( 2, 2) [000810] ------------ * RETURN int $1f4 N001 ( 1, 1) [000482] ------------ \--* CNS_INT int 1 $c1 ------------ BB59 [008..00E) (throw), preds={BB01} succs={} ***** BB59 STMT00086 (IL 0x008...0x009) N003 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException $VN.Void N002 ( 1, 1) [000532] ------------ arg0 in rcx \--* CNS_INT int 4 $c5 ------------ BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} ***** BB60 STMT00073 (IL 0x14F...0x150) N004 ( 7, 5) [000444] -A---O--R--- * ASG long $2e8 N003 ( 3, 2) [000443] D------N---- +--* LCL_VAR long V26 tmp12 d:1 $2e7 N002 ( 3, 2) [000442] #----O------ \--* IND long $2e8 N001 ( 1, 1) [000441] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB60 STMT00155 (IL ???... ???) N011 ( 16, 14) [001158] ------------ * JTRUE void N010 ( 14, 12) [000460] J------N---- \--* EQ int N008 ( 12, 10) [000456] n----------- +--* IND long N007 ( 10, 8) [000452] -------N---- | \--* ADD long $331 N005 ( 9, 7) [000450] #----------- | +--* IND long $2ea N004 ( 6, 5) [000449] #----------- | | \--* IND long $2e9 N003 ( 4, 3) [000448] -------N---- | | \--* ADD long $306 N001 ( 3, 2) [000446] ------------ | | +--* LCL_VAR long V26 tmp12 u:1 $2e7 N002 ( 1, 1) [000447] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000451] ------------ | \--* CNS_INT long 56 $244 N009 ( 1, 1) [000459] ------------ \--* CNS_INT long 0 $243 ------------ BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} ***** BB61 STMT00156 (IL ???... ???) N010 ( 16, 13) [001160] -A------R--- * ASG long N009 ( 3, 2) [001159] D------N---- +--* LCL_VAR long V28 tmp14 d:3 N008 ( 12, 10) [000461] n-----?----- \--* IND long N007 ( 10, 8) [000462] ------?N---- \--* ADD long $331 N005 ( 9, 7) [000463] #-----?----- +--* IND long $2ea N004 ( 6, 5) [000464] #-----?----- | \--* IND long $2e9 N003 ( 4, 3) [000465] ------?N---- | \--* ADD long $306 N001 ( 3, 2) [000466] ------?----- | +--* LCL_VAR long V26 tmp12 u:1 (last use) $2e7 N002 ( 1, 1) [000467] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000468] ------?----- \--* CNS_INT long 56 $244 ------------ BB62 [???..???), preds={BB60} succs={BB63} ***** BB62 STMT00157 (IL ???... ???) N007 ( 23, 22) [001162] -AC-G---R--- * ASG long $332 N006 ( 3, 2) [001161] D------N---- +--* LCL_VAR long V28 tmp14 d:2 $332 N005 ( 19, 19) [000458] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 N003 ( 3, 2) [000445] ------?----- arg0 in rcx +--* LCL_VAR long V26 tmp12 u:1 (last use) $2e7 N004 ( 2, 10) [000457] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $52 ------------ BB63 [???..157) (throw), preds={BB61,BB62} succs={} ***** BB63 STMT00167 (IL ???... ???) N005 ( 0, 0) [001184] -A------R--- * ASG long N004 ( 0, 0) [001182] D------N---- +--* LCL_VAR long V28 tmp14 d:1 N003 ( 0, 0) [001183] ------------ \--* PHI long N001 ( 0, 0) [001241] ------------ pred BB61 +--* PHI_ARG long V28 tmp14 u:3 N002 ( 0, 0) [001240] ------------ pred BB62 \--* PHI_ARG long V28 tmp14 u:2 $332 ***** BB63 STMT00076 (IL ???... ???) N005 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void N003 ( 3, 2) [000473] ------------ arg0 in rcx +--* LCL_VAR long V28 tmp14 u:1 (last use) $347 N004 ( 1, 1) [000455] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) $101 ------------ BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} ***** BB64 STMT00053 (IL 0x1BC...0x1BD) N004 ( 7, 5) [000299] -A---O--R--- * ASG long $2e8 N003 ( 3, 2) [000298] D------N---- +--* LCL_VAR long V21 tmp7 d:1 $2e7 N002 ( 3, 2) [000297] #----O------ \--* IND long $2e8 N001 ( 1, 1) [000296] !----------- \--* LCL_VAR ref V00 this u:1 $100 ***** BB64 STMT00161 (IL ???... ???) N011 ( 16, 14) [001168] ------------ * JTRUE void N010 ( 14, 12) [000315] J------N---- \--* EQ int N008 ( 12, 10) [000311] n----------- +--* IND long N007 ( 10, 8) [000307] -------N---- | \--* ADD long $331 N005 ( 9, 7) [000305] #----------- | +--* IND long $2ea N004 ( 6, 5) [000304] #----------- | | \--* IND long $2e9 N003 ( 4, 3) [000303] -------N---- | | \--* ADD long $306 N001 ( 3, 2) [000301] ------------ | | +--* LCL_VAR long V21 tmp7 u:1 $2e7 N002 ( 1, 1) [000302] ------------ | | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000306] ------------ | \--* CNS_INT long 56 $244 N009 ( 1, 1) [000314] ------------ \--* CNS_INT long 0 $243 ------------ BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} ***** BB65 STMT00162 (IL ???... ???) N010 ( 16, 13) [001170] -A------R--- * ASG long N009 ( 3, 2) [001169] D------N---- +--* LCL_VAR long V23 tmp9 d:3 N008 ( 12, 10) [000316] n-----?----- \--* IND long N007 ( 10, 8) [000317] ------?N---- \--* ADD long $331 N005 ( 9, 7) [000318] #-----?----- +--* IND long $2ea N004 ( 6, 5) [000319] #-----?----- | \--* IND long $2e9 N003 ( 4, 3) [000320] ------?N---- | \--* ADD long $306 N001 ( 3, 2) [000321] ------?----- | +--* LCL_VAR long V21 tmp7 u:1 (last use) $2e7 N002 ( 1, 1) [000322] ------?----- | \--* CNS_INT long 56 $244 N006 ( 1, 1) [000323] ------?----- \--* CNS_INT long 56 $244 ------------ BB66 [???..???), preds={BB64} succs={BB67} ***** BB66 STMT00163 (IL ???... ???) N007 ( 23, 22) [001172] -AC-G---R--- * ASG long $332 N006 ( 3, 2) [001171] D------N---- +--* LCL_VAR long V23 tmp9 d:2 $332 N005 ( 19, 19) [000313] --C-G-?----- \--* CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 N003 ( 3, 2) [000300] ------?----- arg0 in rcx +--* LCL_VAR long V21 tmp7 u:1 (last use) $2e7 N004 ( 2, 10) [000312] H-----?----- arg1 in rdx \--* CNS_INT(h) long 0xd1ffab1e global ptr $52 ------------ BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} ***** BB67 STMT00173 (IL ???... ???) N005 ( 0, 0) [001202] -A------R--- * ASG long N004 ( 0, 0) [001200] D------N---- +--* LCL_VAR long V23 tmp9 d:1 N003 ( 0, 0) [001201] ------------ \--* PHI long N001 ( 0, 0) [001232] ------------ pred BB65 +--* PHI_ARG long V23 tmp9 u:3 N002 ( 0, 0) [001231] ------------ pred BB66 \--* PHI_ARG long V23 tmp9 u:2 $332 ***** BB67 STMT00056 (IL ???... ???) N005 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void N003 ( 3, 2) [000328] ------------ arg0 in rcx +--* LCL_VAR long V23 tmp9 u:1 (last use) $34b N004 ( 1, 1) [000310] ------------ arg1 in rdx \--* LCL_VAR ref V01 arg1 u:1 (last use) $101 ------------ BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} ***** BB68 STMT00043 (IL 0x1DD...0x1E2) N001 ( 14, 5) [000233] --CXG------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Rationalize IR rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N008 ( 9, 6) [000544] DA--GO------ * STORE_LCL_VAR int V33 tmp19 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 4, 12) [001291] DA--G------- * STORE_LCL_VAR ref V73 cse8 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N008 ( 5, 13) [000554] DA--G------- * STORE_LCL_VAR ref V34 tmp20 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000556] DA--G------- * STORE_LCL_VAR ref V35 tmp21 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 4) [000018] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 6, 3) [000566] DA---------- * STORE_LCL_VAR int V36 tmp22 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000576] DA--G------- * STORE_LCL_VAR ref V37 tmp23 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 4) [000028] DA--GO------ * STORE_LCL_VAR ref V05 loc1 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 3, 3) [000489] DA---O------ * STORE_LCL_VAR long V29 tmp15 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N010 ( 14, 12) [001266] DA---------- * STORE_LCL_VAR long V68 cse3 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 3, 3) [001150] DA---------- * STORE_LCL_VAR long V31 tmp17 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 17, 18) [001152] DAC-G------- * STORE_LCL_VAR long V31 tmp17 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [001217] DA---------- * STORE_LCL_VAR long V31 tmp17 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N010 ( 31, 15) [000524] DACXG------- * STORE_LCL_VAR int V15 tmp1 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N013 ( 34, 21) [000038] DACXGO------ * STORE_LCL_VAR int V15 tmp1 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [001214] DA---------- * STORE_LCL_VAR int V15 tmp1 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 3, 3) [000042] DA---------- * STORE_LCL_VAR int V06 loc2 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000045] DA---------- * STORE_LCL_VAR int V07 loc3 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 4) [000580] DA--GO------ * STORE_LCL_VAR ref V39 tmp25 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 3, 3) [000629] DA-X-------- * STORE_LCL_VAR int V40 tmp26 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 4) [000631] DA--GO------ * STORE_LCL_VAR long V41 tmp27 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 6, 6) [000642] DA---------- * STORE_LCL_VAR int V43 tmp29 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000652] DA--G------- * STORE_LCL_VAR ref V44 tmp30 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000654] DA--G------- * STORE_LCL_VAR ref V45 tmp31 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N016 ( 20, 21) [000619] DA---------- * STORE_LCL_VAR int V42 tmp28 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 27, 7) [000665] DA-X-------- * STORE_LCL_VAR int V46 tmp32 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000675] DA--G------- * STORE_LCL_VAR ref V47 tmp33 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [000677] DA--G------- * STORE_LCL_VAR ref V48 tmp34 d:1 Rewriting GT_ADDR(GT_IND(X)) to X: N005 ( 1, 1) [000852] ------------ t852 = LCL_VAR ref V39 tmp25 u:1 (last use) N006 ( 1, 1) [000853] ------------ t853 = LCL_VAR int V42 tmp28 u:1 (last use) /--* t853 int N007 ( 2, 3) [000856] ------------ t856 = * CAST long <- int N008 ( 1, 1) [000857] -------N---- t857 = CNS_INT long 2 $248 /--* t856 long +--* t857 long N009 ( 3, 4) [000858] -------N---- t858 = * LSH long N010 ( 1, 1) [000859] ------------ t859 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t858 long +--* t859 long N011 ( 4, 5) [000860] -------N---- t860 = * ADD long /--* t852 ref +--* t860 long N012 ( 5, 6) [000861] -------N---- t861 = * ADD byref $81 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N017 ( 19, 24) [000591] DA-XG------- * STORE_LCL_VAR byref V38 tmp24 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000051] DA---------- * STORE_LCL_VAR byref V08 loc4 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 5, 4) [000057] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 3, 3) [000356] DA---O------ * STORE_LCL_VAR long V24 tmp10 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N010 ( 14, 12) [001271] DA---------- * STORE_LCL_VAR long V69 cse4 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [001155] DA---------- * STORE_LCL_VAR long V25 tmp11 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 21, 21) [001157] DAC-G------- * STORE_LCL_VAR long V25 tmp11 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [001199] DA---------- * STORE_LCL_VAR long V25 tmp11 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 17, 8) [000386] DACXG------- * STORE_LCL_VAR ref V12 loc8 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [001178] DA---------- * STORE_LCL_VAR int V07 loc3 d:5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [001175] DA---------- * STORE_LCL_VAR int V09 loc5 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 3, 3) [001316] DA-X-------- * STORE_LCL_VAR int V76 cse11 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 7, 7) [001276] DA---------- * STORE_LCL_VAR long V70 cse5 d:1 Rewriting GT_ADDR(GT_IND(X)) to X: N001 ( 1, 1) [000869] ------------ t869 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000870] ------------ t870 = LCL_VAR int V09 loc5 u:4 $3c2 /--* t870 int N003 ( 2, 3) [000873] ------------ t873 = * CAST long <- int $326 N004 ( 1, 1) [000880] ------------ t880 = CNS_INT long 3 $24b /--* t873 long +--* t880 long N005 ( 7, 7) [000881] ------------ t881 = * MUL long $327 /--* t881 long N007 ( 7, 7) [001276] DA---------- * STORE_LCL_VAR long V70 cse5 d:1 N008 ( 1, 1) [001277] ------------ t1277 = LCL_VAR long V70 cse5 u:1 $327 N010 ( 1, 1) [000874] -------N---- t874 = CNS_INT long 3 $24b /--* t1277 long +--* t874 long N011 ( 9, 9) [000875] -------N---- t875 = * LSH long $328 N012 ( 1, 1) [000876] ------------ t876 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t875 long +--* t876 long N013 ( 10, 10) [000877] -------N---- t877 = * ADD long $329 /--* t869 ref +--* t877 long N014 ( 11, 11) [000878] -------N---- t878 = * ADD byref $82 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N018 ( 23, 23) [001249] DA--G------- * STORE_LCL_VAR byref V65 cse0 d:1 Rewriting GT_ADDR(GT_IND(X)) to X: N004 ( 1, 1) [000883] ------------ t883 = LCL_VAR ref V04 loc0 u:1 N005 ( 1, 1) [001279] ------------ t1279 = LCL_VAR long V70 cse5 u:1 $327 N006 ( 1, 1) [000888] -------N---- t888 = CNS_INT long 3 $24b /--* t1279 long +--* t888 long N007 ( 2, 2) [000889] -------N---- t889 = * LSH long $328 N008 ( 1, 1) [000890] ------------ t890 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t889 long +--* t890 long N009 ( 3, 3) [000891] -------N---- t891 = * ADD long $329 /--* t883 ref +--* t891 long N010 ( 4, 4) [000892] -------N---- t892 = * ADD byref $82 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 4) [000406] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:5 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 3) [000411] DA---------- * STORE_LCL_VAR int V07 loc3 d:6 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [001208] DA---------- * STORE_LCL_VAR int V07 loc3 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [001205] DA---------- * STORE_LCL_VAR int V09 loc5 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 3, 3) [001323] DA-X-------- * STORE_LCL_VAR int V76 cse11 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 7, 7) [001281] DA---------- * STORE_LCL_VAR long V71 cse6 d:1 Rewriting GT_ADDR(GT_IND(X)) to X: N001 ( 1, 1) [000949] ------------ t949 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000950] ------------ t950 = LCL_VAR int V09 loc5 u:2 $3c4 /--* t950 int N003 ( 2, 3) [000953] ------------ t953 = * CAST long <- int $6e1 N004 ( 1, 1) [000960] ------------ t960 = CNS_INT long 3 $24b /--* t953 long +--* t960 long N005 ( 7, 7) [000961] ------------ t961 = * MUL long $6e2 /--* t961 long N007 ( 7, 7) [001281] DA---------- * STORE_LCL_VAR long V71 cse6 d:1 N008 ( 1, 1) [001282] ------------ t1282 = LCL_VAR long V71 cse6 u:1 $6e2 N010 ( 1, 1) [000954] -------N---- t954 = CNS_INT long 3 $24b /--* t1282 long +--* t954 long N011 ( 9, 9) [000955] -------N---- t955 = * LSH long $6e3 N012 ( 1, 1) [000956] ------------ t956 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t955 long +--* t956 long N013 ( 10, 10) [000957] -------N---- t957 = * ADD long $6e4 /--* t949 ref +--* t957 long N014 ( 11, 11) [000958] -------N---- t958 = * ADD byref $91 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N018 ( 23, 23) [001255] DA--G------- * STORE_LCL_VAR byref V66 cse1 d:1 Rewriting GT_ADDR(GT_IND(X)) to X: N001 ( 1, 1) [000963] ------------ t963 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [001284] ------------ t1284 = LCL_VAR long V71 cse6 u:1 $6e2 N003 ( 1, 1) [000968] -------N---- t968 = CNS_INT long 3 $24b /--* t1284 long +--* t968 long N004 ( 2, 2) [000969] -------N---- t969 = * LSH long $6e3 N005 ( 1, 1) [000970] ------------ t970 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t969 long +--* t970 long N006 ( 3, 3) [000971] -------N---- t971 = * ADD long $6e4 /--* t963 ref +--* t971 long N007 ( 4, 4) [000972] -------N---- t972 = * ADD byref $91 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N012 ( 12, 11) [000246] DA--G------- * STORE_LCL_VAR ref V17 tmp3 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 3, 3) [000244] DA---O------ * STORE_LCL_VAR long V16 tmp2 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N010 ( 10, 9) [001261] DA---------- * STORE_LCL_VAR long V67 cse2 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 1, 3) [001165] DA---------- * STORE_LCL_VAR long V19 tmp5 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 17, 18) [001167] DAC-G------- * STORE_LCL_VAR long V19 tmp5 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [001211] DA---------- * STORE_LCL_VAR long V19 tmp5 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 4) [000222] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 3, 3) [000227] DA---------- * STORE_LCL_VAR int V07 loc3 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [001181] DA---------- * STORE_LCL_VAR int V07 loc3 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 8, 7) [001306] DA--GO------ * STORE_LCL_VAR int V74 cse9 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N010 ( 15, 12) [000174] DA--GO------ * STORE_LCL_VAR int V10 loc6 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 3, 3) [001032] DA--G------- * STORE_LCL_VAR int V62 tmp48 d:1 Rewriting GT_ADDR(GT_IND(X)) to X: N007 ( 1, 1) [001030] ------------ t1030 = LCL_VAR ref V04 loc0 u:1 N008 ( 1, 1) [001034] ------------ t1034 = LCL_VAR int V62 tmp48 u:1 (last use) /--* t1034 int N009 ( 2, 3) [001037] ------------ t1037 = * CAST long <- int N010 ( 1, 1) [001047] ------------ t1047 = CNS_INT long 3 $24b /--* t1037 long +--* t1047 long N011 ( 7, 7) [001048] ------------ t1048 = * MUL long N012 ( 1, 1) [001038] -------N---- t1038 = CNS_INT long 3 $24b /--* t1048 long +--* t1038 long N013 ( 8, 8) [001039] -------N---- t1039 = * LSH long N014 ( 1, 1) [001040] ------------ t1040 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t1039 long +--* t1040 long N015 ( 9, 9) [001041] -------N---- t1041 = * ADD long /--* t1030 ref +--* t1041 long N016 ( 10, 10) [001042] -------N---- t1042 = * ADD byref $88 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N030 ( 45, 44) [000688] DA-XG------- * STORE_LCL_VAR int V49 tmp35 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000698] DA--G------- * STORE_LCL_VAR ref V50 tmp36 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N010 ( 4, 4) [001061] DA--GO------ * STORE_LCL_VAR int V63 tmp49 d:1 Rewriting GT_ADDR(GT_IND(X)) to X: N014 ( 1, 1) [001059] ------------ t1059 = LCL_VAR ref V04 loc0 u:1 N015 ( 1, 1) [001063] ------------ t1063 = LCL_VAR int V63 tmp49 u:1 (last use) /--* t1063 int N016 ( 2, 3) [001066] ------------ t1066 = * CAST long <- int N017 ( 1, 1) [001076] ------------ t1076 = CNS_INT long 3 $24b /--* t1066 long +--* t1076 long N018 ( 7, 7) [001077] ------------ t1077 = * MUL long N019 ( 1, 1) [001067] -------N---- t1067 = CNS_INT long 3 $24b /--* t1077 long +--* t1067 long N020 ( 8, 8) [001068] -------N---- t1068 = * LSH long N021 ( 1, 1) [001069] ------------ t1069 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t1068 long +--* t1069 long N022 ( 9, 9) [001070] -------N---- t1070 = * ADD long /--* t1059 ref +--* t1070 long N023 ( 10, 10) [001071] -------N---- t1071 = * ADD byref $8a rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 8, 7) [001311] DA--GO------ * STORE_LCL_VAR int V75 cse10 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N010 ( 15, 12) [000075] DA--GO------ * STORE_LCL_VAR int V13 loc9 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 21, 11) [001090] DACXG-----L- * STORE_LCL_VAR int V64 tmp50 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 8, 7) [000711] DA--GO------ * STORE_LCL_VAR ref V52 tmp38 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 9, 7) [001286] DA-X-------- * STORE_LCL_VAR int V72 cse7 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N008 ( 12, 9) [000760] DA-X-------- * STORE_LCL_VAR int V53 tmp39 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 8, 7) [000762] DA--GO------ * STORE_LCL_VAR long V54 tmp40 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 10, 9) [000773] DA---------- * STORE_LCL_VAR int V56 tmp42 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000783] DA--G------- * STORE_LCL_VAR ref V57 tmp43 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000785] DA--G------- * STORE_LCL_VAR ref V58 tmp44 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N016 ( 26, 25) [000750] DA---------- * STORE_LCL_VAR int V55 tmp41 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 33, 11) [000796] DA-X-------- * STORE_LCL_VAR int V59 tmp45 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000806] DA--G------- * STORE_LCL_VAR ref V60 tmp46 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000808] DA--G------- * STORE_LCL_VAR ref V61 tmp47 d:1 Rewriting GT_ADDR(GT_IND(X)) to X: N004 ( 3, 2) [001102] ------------ t1102 = LCL_VAR ref V52 tmp38 u:1 (last use) N005 ( 3, 2) [001103] ------------ t1103 = LCL_VAR int V55 tmp41 u:1 (last use) /--* t1103 int N006 ( 4, 4) [001106] ------------ t1106 = * CAST long <- int N007 ( 1, 1) [001107] -------N---- t1107 = CNS_INT long 2 $248 /--* t1106 long +--* t1107 long N008 ( 5, 5) [001108] -------N---- t1108 = * LSH long N009 ( 1, 1) [001109] ------------ t1109 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t1108 long +--* t1109 long N010 ( 6, 6) [001110] -------N---- t1110 = * ADD long /--* t1102 ref +--* t1110 long N011 ( 9, 8) [001111] -------N---- t1111 = * ADD byref $87 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N016 ( 33, 31) [000722] DA-XG------- * STORE_LCL_VAR byref V51 tmp37 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000170] DA---------- * STORE_LCL_VAR byref V08 loc4 d:4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [001193] DA---------- * STORE_LCL_VAR byref V08 loc4 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 7, 5) [000083] DA---------- * STORE_LCL_VAR int V10 loc6 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 4) [000093] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [001196] DA---------- * STORE_LCL_VAR byref V08 loc4 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [001190] DA---------- * STORE_LCL_VAR ref V04 loc0 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [001187] DA---------- * STORE_LCL_VAR int V10 loc6 d:1 Rewriting GT_ADDR(GT_IND(X)) to X: N005 ( 1, 1) [001118] ------------ t1118 = LCL_VAR ref V04 loc0 u:2 $684 N006 ( 3, 2) [001119] ------------ t1119 = LCL_VAR int V10 loc6 u:1 $3cc /--* t1119 int N007 ( 4, 4) [001122] ------------ t1122 = * CAST long <- int $6dc N008 ( 1, 1) [001129] ------------ t1129 = CNS_INT long 3 $24b /--* t1122 long +--* t1129 long N009 ( 9, 8) [001130] ------------ t1130 = * MUL long $6dd N010 ( 1, 1) [001123] -------N---- t1123 = CNS_INT long 3 $24b /--* t1130 long +--* t1123 long N011 ( 10, 9) [001124] -------N---- t1124 = * LSH long $6de N012 ( 1, 1) [001125] ------------ t1125 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t1124 long +--* t1125 long N013 ( 11, 10) [001126] -------N---- t1126 = * ADD long $6df /--* t1118 ref +--* t1126 long N014 ( 12, 11) [001127] -------N---- t1127 = * ADD byref $8c rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N019 ( 39, 38) [000099] DA-XG------- * STORE_LCL_VAR byref V11 loc7 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 7, 5) [000444] DA---O------ * STORE_LCL_VAR long V26 tmp12 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N010 ( 16, 13) [001160] DA---------- * STORE_LCL_VAR long V28 tmp14 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 23, 22) [001162] DAC-G------- * STORE_LCL_VAR long V28 tmp14 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [001184] DA---------- * STORE_LCL_VAR long V28 tmp14 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 7, 5) [000299] DA---O------ * STORE_LCL_VAR long V21 tmp7 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N010 ( 16, 13) [001170] DA---------- * STORE_LCL_VAR long V23 tmp9 d:3 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N007 ( 23, 22) [001172] DAC-G------- * STORE_LCL_VAR long V23 tmp9 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 0, 0) [001202] DA---------- * STORE_LCL_VAR long V23 tmp9 d:1 *************** Finishing PHASE Rationalize IR Trees after Rationalize IR ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i LIR BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i LIR BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe LIR BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i LIR BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe LIR BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i LIR BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe LIR BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i LIR BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe LIR BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe LIR BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe LIR BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe LIR BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe LIR BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen LIR BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe LIR BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen LIR BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe LIR BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen LIR BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe LIR BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe LIR BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe LIR BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe LIR BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target LIR BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd LIR BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd LIR BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd LIR BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal LIR BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd LIR BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen LIR BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd LIR BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal Loop1 gcsafe LIR BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target LIR BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd LIR BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd LIR BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe LIR BB36 [0108] 1 BB34 1 [???..???) i gcsafe LIR BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd LIR BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd LIR BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen LIR BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd LIR BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe LIR BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd LIR BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal LIR BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i LIR BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen LIR BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe LIR BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen LIR BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen LIR BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen LIR BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe LIR BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen LIR BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe LIR BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen LIR BB54 [0044] 2 BB48,BB53 0.50 [261..276) i LIR BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen LIR BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall LIR BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen LIR BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal LIR BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe LIR BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd LIR BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe LIR BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe LIR BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd LIR BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd LIR BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe LIR BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe LIR BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd LIR BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} [001332] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V01 arg1 u:1 $101 N002 ( 1, 1) [000001] ------------ t1 = CNS_INT ref null $VN.Null /--* t0 ref +--* t1 ref N003 ( 3, 3) [000002] J------N---- t2 = * EQ int $180 /--* t2 int N004 ( 5, 5) [000003] ------------ * JTRUE void ------------ BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} [001333] ------------ IL_OFFSET void IL offset: 0xe N001 ( 1, 1) [000004] ------------ t4 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000813] ------------ t813 = CNS_INT long 8 field offset Fseq[_buckets] $240 /--* t4 ref +--* t813 long N003 ( 2, 2) [000814] -------N---- t814 = * ADD byref $280 /--* t814 byref N004 ( 4, 4) [000005] ---XG------- t5 = * IND ref N005 ( 1, 1) [000006] ------------ t6 = CNS_INT ref null $VN.Null /--* t5 ref +--* t6 ref N006 ( 6, 6) [000007] J--XG--N---- t7 = * NE int /--* t7 int N007 ( 8, 8) [000008] ---XG------- * JTRUE void ------------ BB03 [016..01E), preds={BB02} succs={BB04} N003 ( 1, 1) [000526] ------------ t526 = LCL_VAR ref V00 this u:1 $100 N004 ( 1, 1) [000527] ------------ t527 = CNS_INT int 0 $c0 /--* t526 ref this in rcx +--* t527 int arg1 in rdx N005 ( 16, 10) [000528] --CXG------- t528 = * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize $1c2 ------------ BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} [001334] ------------ IL_OFFSET void IL offset: 0x1e N001 ( 1, 1) [000009] ------------ t9 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000817] ------------ t817 = CNS_INT long 8 field offset Fseq[_buckets] $240 /--* t9 ref +--* t817 long N003 ( 2, 2) [000818] -------N---- t818 = * ADD byref $280 /--* t818 byref N004 ( 4, 4) [000010] n---GO------ t10 = * IND ref N005 ( 1, 1) [000011] ------------ t11 = CNS_INT ref null $VN.Null /--* t10 ref +--* t11 ref N006 ( 9, 6) [000012] N---GO------ t12 = * NE int /--* t12 int N008 ( 9, 6) [000544] DA--GO------ * STORE_LCL_VAR int V33 tmp19 d:1 [001335] ------------ IL_OFFSET void IL offset: 0x1e N001 ( 2, 10) [000537] H----------- t537 = CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 /--* t537 long N002 ( 4, 12) [000538] #---G------- t538 = * IND ref $105 /--* t538 ref N004 ( 4, 12) [001291] DA--G------- * STORE_LCL_VAR ref V73 cse8 d:1 N005 ( 1, 1) [001292] ------------ t1292 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1292 ref N008 ( 5, 13) [000554] DA--G------- * STORE_LCL_VAR ref V34 tmp20 d:1 [001336] ------------ IL_OFFSET void IL offset: 0x1e N001 ( 1, 1) [001294] ------------ t1294 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1294 ref N003 ( 1, 3) [000556] DA--G------- * STORE_LCL_VAR ref V35 tmp21 d:1 [001337] ------------ IL_OFFSET void IL offset: 0x1e N001 ( 1, 1) [000546] ------------ t546 = LCL_VAR int V33 tmp19 u:1 (last use) N002 ( 1, 1) [000547] ------------ t547 = CNS_INT int 0 $c0 /--* t546 int +--* t547 int N003 ( 3, 3) [000548] J------N---- t548 = * NE int /--* t548 int N004 ( 5, 5) [000549] ------------ * JTRUE void ------------ BB05 [01E..01F), preds={BB04} succs={BB06} [001338] ------------ IL_OFFSET void IL offset: 0x1e N003 ( 1, 1) [000550] ------------ t550 = LCL_VAR ref V35 tmp21 u:1 (last use) $105 N004 ( 1, 1) [000551] ------------ t551 = LCL_VAR ref V35 tmp21 u:1 (last use) $105 /--* t550 ref arg0 in rcx +--* t551 ref arg1 in rdx N005 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} [001339] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 1) [000015] ------------ t15 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000821] ------------ t821 = CNS_INT long 16 field offset Fseq[_entries] $241 /--* t15 ref +--* t821 long N003 ( 2, 2) [000822] -------N---- t822 = * ADD byref $281 /--* t822 byref N004 ( 4, 4) [000016] n---GO------ t16 = * IND ref /--* t16 ref N006 ( 4, 4) [000018] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:1 [001340] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 1, 1) [000019] ------------ t19 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000020] ------------ t20 = CNS_INT ref null $VN.Null /--* t19 ref +--* t20 ref N003 ( 6, 3) [000021] N----------- t21 = * NE int /--* t21 int N005 ( 6, 3) [000566] DA---------- * STORE_LCL_VAR int V36 tmp22 d:1 [001341] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 1, 1) [001295] ------------ t1295 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1295 ref N003 ( 1, 3) [000576] DA--G------- * STORE_LCL_VAR ref V37 tmp23 d:1 [001342] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 1, 1) [000568] ------------ t568 = LCL_VAR int V36 tmp22 u:1 (last use) N002 ( 1, 1) [000569] ------------ t569 = CNS_INT int 0 $c0 /--* t568 int +--* t569 int N003 ( 3, 3) [000570] J------N---- t570 = * NE int /--* t570 int N004 ( 5, 5) [000571] ------------ * JTRUE void ------------ BB07 [033..034), preds={BB06} succs={BB08} [001343] ------------ IL_OFFSET void IL offset: 0x33 N003 ( 2, 10) [000823] H----------- t823 = CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" $46 /--* t823 long N004 ( 4, 12) [000824] #---G------- t824 = * IND ref $106 N005 ( 1, 1) [000573] ------------ t573 = LCL_VAR ref V37 tmp23 u:1 (last use) $105 /--* t824 ref arg0 in rcx +--* t573 ref arg1 in rdx N006 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} [001344] ------------ IL_OFFSET void IL offset: 0x41 N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000827] ------------ t827 = CNS_INT long 24 field offset Fseq[_comparer] $242 /--* t25 ref +--* t827 long N003 ( 2, 2) [000828] -------N---- t828 = * ADD byref $282 /--* t828 byref N004 ( 4, 4) [000026] n---GO------ t26 = * IND ref /--* t26 ref N006 ( 4, 4) [000028] DA--GO------ * STORE_LCL_VAR ref V05 loc1 d:1 [001345] ------------ IL_OFFSET void IL offset: 0x48 N001 ( 1, 1) [000029] ------------ t29 = LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000030] ------------ t30 = CNS_INT ref null $VN.Null /--* t29 ref +--* t30 ref N003 ( 3, 3) [000031] J------N---- t31 = * EQ int /--* t31 int N004 ( 5, 5) [000032] ------------ * JTRUE void ------------ BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} [001346] ------------ IL_OFFSET void IL offset: 0x4b N001 ( 1, 1) [000486] !----------- t486 = LCL_VAR ref V00 this u:1 $100 /--* t486 ref N002 ( 3, 2) [000487] #----O------ t487 = * IND long $2e8 /--* t487 long N004 ( 3, 3) [000489] DA---O------ * STORE_LCL_VAR long V29 tmp15 d:1 N001 ( 1, 1) [000491] ------------ t491 = LCL_VAR long V29 tmp15 u:1 $2e7 N002 ( 1, 1) [000492] ------------ t492 = CNS_INT long 56 $244 /--* t491 long +--* t492 long N003 ( 2, 2) [000493] -------N---- t493 = * ADD long $306 /--* t493 long N004 ( 4, 4) [000494] #----------- t494 = * IND long $2e9 /--* t494 long N005 ( 7, 6) [000495] #----------- t495 = * IND long $2ea N006 ( 1, 1) [000496] ------------ t496 = CNS_INT long 64 $245 /--* t495 long +--* t496 long N007 ( 8, 7) [000497] -------N---- t497 = * ADD long $307 /--* t497 long N008 ( 10, 9) [000501] n----------- t501 = * IND long /--* t501 long N010 ( 14, 12) [001266] DA---------- * STORE_LCL_VAR long V68 cse3 d:1 N011 ( 3, 2) [001267] ------------ t1267 = LCL_VAR long V68 cse3 u:1 N013 ( 1, 1) [000504] ------------ t504 = CNS_INT long 0 $243 /--* t1267 long +--* t504 long N014 ( 19, 16) [000505] J------N---- t505 = * EQ int /--* t505 int N015 ( 21, 18) [001148] ------------ * JTRUE void ------------ BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} N001 ( 3, 2) [001269] ------------ t1269 = LCL_VAR long V68 cse3 u:1 /--* t1269 long N003 ( 3, 3) [001150] DA---------- * STORE_LCL_VAR long V31 tmp17 d:3 ------------ BB11 [???..???), preds={BB09} succs={BB12} N003 ( 1, 1) [000490] ------?----- t490 = LCL_VAR long V29 tmp15 u:1 (last use) $2e7 N004 ( 2, 10) [000502] H-----?----- t502 = CNS_INT(h) long 0xd1ffab1e global ptr $49 /--* t490 long arg0 in rcx +--* t502 long arg1 in rdx N005 ( 17, 18) [000503] --C-G-?----- t503 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $308 /--* t503 long N007 ( 17, 18) [001152] DA--G------- * STORE_LCL_VAR long V31 tmp17 d:2 ------------ BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} N001 ( 0, 0) [001247] ------------ t1247 = PHI_ARG long V31 tmp17 u:3 N002 ( 0, 0) [001246] ------------ t1246 = PHI_ARG long V31 tmp17 u:2 $308 /--* t1247 long +--* t1246 long N003 ( 0, 0) [001216] ------------ t1216 = * PHI long /--* t1216 long N005 ( 0, 0) [001217] DA---------- * STORE_LCL_VAR long V31 tmp17 d:1 N004 ( 1, 1) [000484] ------------ t484 = LCL_VAR ref V05 loc1 u:1 N005 ( 1, 1) [000831] ------------ t831 = LCL_VAR long V31 tmp17 u:1 r11 REG r11 $342 N006 ( 1, 1) [000500] ------------ t500 = LCL_VAR ref V01 arg1 u:1 $101 N007 ( 1, 1) [000521] ------------ t521 = LCL_VAR long V31 tmp17 u:1 (last use) $342 /--* t484 ref this in rcx +--* t831 long arg1 in r11 +--* t500 ref arg2 in rdx +--* t521 long calli tgt N008 ( 27, 12) [000522] --CXG------- t522 = * CALL ind stub int $1c7 /--* t522 int N010 ( 31, 15) [000524] DA-XG------- * STORE_LCL_VAR int V15 tmp1 d:3 ------------ BB13 [054..061), preds={BB08} succs={BB14} [001347] ------------ IL_OFFSET void IL offset: 0x54 N002 ( 1, 1) [000033] ------------ t33 = LCL_VAR ref V01 arg1 u:1 $101 N003 ( 1, 1) [000836] ------------ t836 = LCL_VAR ref V01 arg1 u:1 $101 /--* t836 ref N004 ( 3, 2) [000837] #----O------ t837 = * IND long $2e4 N005 ( 1, 1) [000838] ------------ t838 = CNS_INT int 72 $c9 /--* t837 long +--* t838 int N006 ( 4, 3) [000839] -----O-N---- t839 = * ADD long $301 /--* t839 long N007 ( 6, 5) [000840] #----O------ t840 = * IND long $2e6 N008 ( 1, 1) [000841] ------------ t841 = CNS_INT int 24 $ca /--* t840 long +--* t841 int N009 ( 7, 6) [000842] -----O-N---- t842 = * ADD long $303 /--* t842 long N010 ( 9, 8) [000843] n----O------ t843 = * IND long /--* t33 ref this in rcx +--* t843 long control expr N011 ( 30, 18) [000035] --CXGO------ t35 = * CALLV vt-ind int System.Object.GetHashCode $1c5 /--* t35 int N013 ( 34, 21) [000038] DA-XGO------ * STORE_LCL_VAR int V15 tmp1 d:2 ------------ BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} N001 ( 0, 0) [001245] ------------ t1245 = PHI_ARG int V15 tmp1 u:3 $1c7 N002 ( 0, 0) [001244] ------------ t1244 = PHI_ARG int V15 tmp1 u:2 $1c5 /--* t1245 int +--* t1244 int N003 ( 0, 0) [001213] ------------ t1213 = * PHI int /--* t1213 int N005 ( 0, 0) [001214] DA---------- * STORE_LCL_VAR int V15 tmp1 d:1 N001 ( 3, 2) [000040] ------------ t40 = LCL_VAR int V15 tmp1 u:1 (last use) $3c0 /--* t40 int N003 ( 3, 3) [000042] DA---------- * STORE_LCL_VAR int V06 loc2 d:1 [001348] ------------ IL_OFFSET void IL offset: 0x62 N001 ( 1, 1) [000043] ------------ t43 = CNS_INT int 0 $c0 /--* t43 int N003 ( 1, 3) [000045] DA---------- * STORE_LCL_VAR int V07 loc3 d:1 [001349] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000046] ------------ t46 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000844] ------------ t844 = CNS_INT long 8 field offset Fseq[_buckets] $240 /--* t46 ref +--* t844 long N003 ( 2, 2) [000845] -------N---- t845 = * ADD byref $280 /--* t845 byref N004 ( 4, 4) [000578] n---GO------ t578 = * IND ref /--* t578 ref N006 ( 4, 4) [000580] DA--GO------ * STORE_LCL_VAR ref V39 tmp25 d:1 [001350] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000582] ------------ t582 = LCL_VAR ref V39 tmp25 u:1 /--* t582 ref N002 ( 3, 3) [000583] ---X-------- t583 = * ARR_LENGTH int /--* t583 int N004 ( 3, 3) [000629] DA-X-------- * STORE_LCL_VAR int V40 tmp26 d:1 [001351] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000584] ------------ t584 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000846] ------------ t846 = CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 /--* t584 ref +--* t846 long N003 ( 2, 2) [000847] -------N---- t847 = * ADD byref $283 /--* t847 byref N004 ( 4, 4) [000585] n---GO------ t585 = * IND long /--* t585 long N006 ( 4, 4) [000631] DA--GO------ * STORE_LCL_VAR long V41 tmp27 d:1 [001352] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000597] ------------ t597 = LCL_VAR int V40 tmp26 u:1 N002 ( 1, 4) [000598] ------------ t598 = CNS_INT int 0x7FFFFFFF $ce /--* t597 int +--* t598 int N003 ( 6, 6) [000599] N--------U-- t599 = * LE int /--* t599 int N005 ( 6, 6) [000642] DA---------- * STORE_LCL_VAR int V43 tmp29 d:1 [001353] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [001296] ------------ t1296 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1296 ref N003 ( 1, 3) [000652] DA--G------- * STORE_LCL_VAR ref V44 tmp30 d:1 [001354] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [001297] ------------ t1297 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1297 ref N003 ( 1, 3) [000654] DA--G------- * STORE_LCL_VAR ref V45 tmp31 d:1 [001355] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000644] ------------ t644 = LCL_VAR int V43 tmp29 u:1 (last use) N002 ( 1, 1) [000645] ------------ t645 = CNS_INT int 0 $c0 /--* t644 int +--* t645 int N003 ( 3, 3) [000646] J------N---- t646 = * NE int /--* t646 int N004 ( 5, 5) [000647] ------------ * JTRUE void ------------ BB15 [064..065), preds={BB14} succs={BB16} [001356] ------------ IL_OFFSET void IL offset: 0x64 N003 ( 1, 1) [000648] ------------ t648 = LCL_VAR ref V45 tmp31 u:1 (last use) $105 N004 ( 1, 1) [000649] ------------ t649 = LCL_VAR ref V45 tmp31 u:1 (last use) $105 /--* t648 ref arg0 in rcx +--* t649 ref arg1 in rdx N005 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} [001357] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000604] ------------ t604 = LCL_VAR long V41 tmp27 u:1 (last use) N002 ( 1, 1) [000047] ------------ t47 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t47 int N003 ( 2, 3) [000605] ---------U-- t605 = * CAST long <- ulong <- uint $310 /--* t604 long +--* t605 long N004 ( 7, 7) [000606] ------------ t606 = * MUL long N005 ( 1, 1) [000607] ------------ t607 = CNS_INT int 32 $d2 /--* t606 long +--* t607 int N006 ( 9, 9) [000608] ------------ t608 = * RSZ long N007 ( 1, 1) [000610] ------------ t610 = CNS_INT long 1 $247 /--* t608 long +--* t610 long N008 ( 11, 11) [000611] ------------ t611 = * ADD long N009 ( 1, 1) [000612] ------------ t612 = LCL_VAR int V40 tmp26 u:1 /--* t612 int N010 ( 2, 3) [000613] ---------U-- t613 = * CAST long <- ulong <- uint /--* t611 long +--* t613 long N011 ( 17, 17) [000614] ------------ t614 = * MUL long N012 ( 1, 1) [000615] ------------ t615 = CNS_INT int 32 $d2 /--* t614 long +--* t615 int N013 ( 19, 19) [000616] ------------ t616 = * RSZ long /--* t616 long N014 ( 20, 21) [000617] ------------ t617 = * CAST int <- uint <- long /--* t617 int N016 ( 20, 21) [000619] DA---------- * STORE_LCL_VAR int V42 tmp28 d:1 [001358] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000621] ------------ t621 = LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000622] ------------ t622 = LCL_VAR int V40 tmp26 u:1 (last use) /--* t621 int +--* t622 int N003 ( 22, 5) [000623] ---X-------- t623 = * UMOD int N004 ( 1, 1) [000620] ------------ t620 = LCL_VAR int V42 tmp28 u:1 /--* t623 int +--* t620 int N005 ( 27, 7) [000624] ---X-------- t624 = * EQ int /--* t624 int N007 ( 27, 7) [000665] DA-X-------- * STORE_LCL_VAR int V46 tmp32 d:1 [001359] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [001298] ------------ t1298 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1298 ref N003 ( 1, 3) [000675] DA--G------- * STORE_LCL_VAR ref V47 tmp33 d:1 [001360] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [001299] ------------ t1299 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1299 ref N003 ( 1, 3) [000677] DA--G------- * STORE_LCL_VAR ref V48 tmp34 d:1 [001361] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000667] ------------ t667 = LCL_VAR int V46 tmp32 u:1 (last use) N002 ( 1, 1) [000668] ------------ t668 = CNS_INT int 0 $c0 /--* t667 int +--* t668 int N003 ( 3, 3) [000669] J------N---- t669 = * NE int /--* t669 int N004 ( 5, 5) [000670] ------------ * JTRUE void ------------ BB17 [064..065), preds={BB16} succs={BB18} [001362] ------------ IL_OFFSET void IL offset: 0x64 N003 ( 1, 1) [000671] ------------ t671 = LCL_VAR ref V48 tmp34 u:1 (last use) $105 N004 ( 1, 1) [000672] ------------ t672 = LCL_VAR ref V48 tmp34 u:1 (last use) $105 /--* t671 ref arg0 in rcx +--* t672 ref arg1 in rdx N005 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} [001363] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000627] ------------ t627 = LCL_VAR int V42 tmp28 u:1 N002 ( 1, 1) [000581] ------------ t581 = LCL_VAR ref V39 tmp25 u:1 /--* t581 ref N003 ( 3, 3) [000854] ---X-------- t854 = * ARR_LENGTH int /--* t627 int +--* t854 int N004 ( 8, 11) [000855] ---X-------- * ARR_BOUNDS_CHECK_Rng void N005 ( 1, 1) [000852] ------------ t852 = LCL_VAR ref V39 tmp25 u:1 (last use) N006 ( 1, 1) [000853] ------------ t853 = LCL_VAR int V42 tmp28 u:1 (last use) /--* t853 int N007 ( 2, 3) [000856] ------------ t856 = * CAST long <- int N008 ( 1, 1) [000857] -------N---- t857 = CNS_INT long 2 $248 /--* t856 long +--* t857 long N009 ( 3, 4) [000858] -------N---- t858 = * LSH long N010 ( 1, 1) [000859] ------------ t859 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t858 long +--* t859 long N011 ( 4, 5) [000860] -------N---- t860 = * ADD long /--* t852 ref +--* t860 long N012 ( 5, 6) [000861] -------N---- t861 = * ADD byref $81 /--* t861 byref N017 ( 19, 24) [000591] DA-XG------- * STORE_LCL_VAR byref V38 tmp24 d:1 N001 ( 1, 1) [000592] ------------ t592 = LCL_VAR byref V38 tmp24 u:1 $81 /--* t592 byref N003 ( 5, 4) [000051] DA---------- * STORE_LCL_VAR byref V08 loc4 d:1 [001364] ------------ IL_OFFSET void IL offset: 0x6d N001 ( 1, 1) [000052] ------------ t52 = LCL_VAR byref V08 loc4 u:1 (last use) $81 /--* t52 byref N002 ( 3, 2) [000053] *--XG------- t53 = * IND int N003 ( 1, 1) [000054] ------------ t54 = CNS_INT int -1 $c4 /--* t53 int +--* t54 int N004 ( 5, 4) [000055] ---XG------- t55 = * ADD int /--* t55 int N006 ( 5, 4) [000057] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:1 [001365] ------------ IL_OFFSET void IL offset: 0x74 N001 ( 1, 1) [000058] ------------ t58 = LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000059] ------------ t59 = CNS_INT ref null $VN.Null /--* t58 ref +--* t59 ref N003 ( 3, 3) [000060] J------N---- t60 = * NE int /--* t60 int N004 ( 5, 5) [000061] ------------ * JTRUE void ------------ BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} [001366] ------------ IL_OFFSET void IL offset: 0xff N001 ( 1, 1) [000353] !----------- t353 = LCL_VAR ref V00 this u:1 $100 /--* t353 ref N002 ( 3, 2) [000354] #----O------ t354 = * IND long $2e8 /--* t354 long N004 ( 3, 3) [000356] DA---O------ * STORE_LCL_VAR long V24 tmp10 d:1 N001 ( 1, 1) [000358] ------------ t358 = LCL_VAR long V24 tmp10 u:1 $2e7 N002 ( 1, 1) [000359] ------------ t359 = CNS_INT long 56 $244 /--* t358 long +--* t359 long N003 ( 2, 2) [000360] -------N---- t360 = * ADD long $306 /--* t360 long N004 ( 4, 4) [000361] #----------- t361 = * IND long $2e9 /--* t361 long N005 ( 7, 6) [000362] #----------- t362 = * IND long $2ea N006 ( 1, 1) [000363] ------------ t363 = CNS_INT long 32 $24a /--* t362 long +--* t363 long N007 ( 8, 7) [000364] -------N---- t364 = * ADD long $324 /--* t364 long N008 ( 10, 9) [000365] n----------- t365 = * IND long /--* t365 long N010 ( 14, 12) [001271] DA---------- * STORE_LCL_VAR long V69 cse4 d:1 N011 ( 3, 2) [001272] ------------ t1272 = LCL_VAR long V69 cse4 u:1 N013 ( 1, 1) [000368] ------------ t368 = CNS_INT long 0 $243 /--* t1272 long +--* t368 long N014 ( 19, 16) [000369] J------N---- t369 = * EQ int /--* t369 int N015 ( 21, 18) [001153] ------------ * JTRUE void ------------ BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} N001 ( 3, 2) [001274] ------------ t1274 = LCL_VAR long V69 cse4 u:1 /--* t1274 long N003 ( 7, 5) [001155] DA---------- * STORE_LCL_VAR long V25 tmp11 d:3 ------------ BB21 [???..???), preds={BB19} succs={BB22} N003 ( 1, 1) [000357] ------?----- t357 = LCL_VAR long V24 tmp10 u:1 (last use) $2e7 N004 ( 2, 10) [000366] H-----?----- t366 = CNS_INT(h) long 0xd1ffab1e global ptr $4f /--* t357 long arg0 in rcx +--* t366 long arg1 in rdx N005 ( 17, 18) [000367] --C-G-?----- t367 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $325 /--* t367 long N007 ( 21, 21) [001157] DA--G------- * STORE_LCL_VAR long V25 tmp11 d:2 ------------ BB22 [???..106), preds={BB20,BB21} succs={BB23} N001 ( 0, 0) [001243] ------------ t1243 = PHI_ARG long V25 tmp11 u:3 N002 ( 0, 0) [001242] ------------ t1242 = PHI_ARG long V25 tmp11 u:2 $325 /--* t1243 long +--* t1242 long N003 ( 0, 0) [001198] ------------ t1198 = * PHI long /--* t1198 long N005 ( 0, 0) [001199] DA---------- * STORE_LCL_VAR long V25 tmp11 d:1 N002 ( 3, 2) [000382] ------------ t382 = LCL_VAR long V25 tmp11 u:1 (last use) $344 /--* t382 long arg0 in rcx N003 ( 17, 8) [000352] --CXG------- t352 = * CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default $223 /--* t352 ref N005 ( 17, 8) [000386] DA-XG------- * STORE_LCL_VAR ref V12 loc8 d:1 ------------ BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} N001 ( 0, 0) [001238] ------------ t1238 = PHI_ARG int V07 loc3 u:6 N002 ( 0, 0) [001235] ------------ t1235 = PHI_ARG int V07 loc3 u:1 $c0 /--* t1238 int +--* t1235 int N003 ( 0, 0) [001177] ------------ t1177 = * PHI int /--* t1177 int N005 ( 0, 0) [001178] DA---------- * STORE_LCL_VAR int V07 loc3 d:5 N001 ( 0, 0) [001239] ------------ t1239 = PHI_ARG int V09 loc5 u:5 N002 ( 0, 0) [001236] ------------ t1236 = PHI_ARG int V09 loc5 u:1 /--* t1239 int +--* t1236 int N003 ( 0, 0) [001174] ------------ t1174 = * PHI int /--* t1174 int N005 ( 0, 0) [001175] DA---------- * STORE_LCL_VAR int V09 loc5 d:4 [001367] ------------ IL_OFFSET void IL offset: 0x106 N001 ( 1, 1) [000388] ------------ t388 = LCL_VAR ref V04 loc0 u:1 /--* t388 ref N002 ( 3, 3) [000389] ---X-------- t389 = * ARR_LENGTH int /--* t389 int N004 ( 3, 3) [001316] DA-X-------- * STORE_LCL_VAR int V76 cse11 N005 ( 1, 1) [001317] ------------ t1317 = LCL_VAR int V76 cse11 N007 ( 1, 1) [000387] ------------ t387 = LCL_VAR int V09 loc5 u:4 $3c2 /--* t1317 int +--* t387 int N008 ( 6, 6) [000390] N--X---N-U-- t390 = * LE int /--* t390 int N009 ( 8, 8) [000391] ---X-------- * JTRUE void ------------ BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} [001368] ------------ IL_OFFSET void IL offset: 0x110 N001 ( 1, 1) [000869] ------------ t869 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000870] ------------ t870 = LCL_VAR int V09 loc5 u:4 $3c2 /--* t870 int N003 ( 2, 3) [000873] ------------ t873 = * CAST long <- int $326 N004 ( 1, 1) [000880] ------------ t880 = CNS_INT long 3 $24b /--* t873 long +--* t880 long N005 ( 7, 7) [000881] ------------ t881 = * MUL long $327 /--* t881 long N007 ( 7, 7) [001276] DA---------- * STORE_LCL_VAR long V70 cse5 d:1 N008 ( 1, 1) [001277] ------------ t1277 = LCL_VAR long V70 cse5 u:1 $327 N010 ( 1, 1) [000874] -------N---- t874 = CNS_INT long 3 $24b /--* t1277 long +--* t874 long N011 ( 9, 9) [000875] -------N---- t875 = * LSH long $328 N012 ( 1, 1) [000876] ------------ t876 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t875 long +--* t876 long N013 ( 10, 10) [000877] -------N---- t877 = * ADD long $329 /--* t869 ref +--* t877 long N014 ( 11, 11) [000878] -------N---- t878 = * ADD byref $82 /--* t878 byref N018 ( 23, 23) [001249] DA--G------- * STORE_LCL_VAR byref V65 cse0 d:1 N019 ( 1, 1) [001250] ------------ t1250 = LCL_VAR byref V65 cse0 u:1 N021 ( 1, 1) [000867] ------------ t867 = CNS_INT long 16 field offset Fseq[hashCode] $241 /--* t1250 byref +--* t867 long N022 ( 25, 25) [000868] ----G--N---- t868 = * ADD byref $28c /--* t868 byref N023 ( 27, 27) [000396] *--XG------- t396 = * IND int N024 ( 1, 1) [000397] ------------ t397 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t396 int +--* t397 int N025 ( 29, 29) [000398] N--XG--N-U-- t398 = * NE int /--* t398 int N026 ( 31, 31) [000399] ---XG------- * JTRUE void ------------ BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} [001369] ------------ IL_OFFSET void IL offset: 0x120 N004 ( 1, 1) [000883] ------------ t883 = LCL_VAR ref V04 loc0 u:1 N005 ( 1, 1) [001279] ------------ t1279 = LCL_VAR long V70 cse5 u:1 $327 N006 ( 1, 1) [000888] -------N---- t888 = CNS_INT long 3 $24b /--* t1279 long +--* t888 long N007 ( 2, 2) [000889] -------N---- t889 = * LSH long $328 N008 ( 1, 1) [000890] ------------ t890 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t889 long +--* t890 long N009 ( 3, 3) [000891] -------N---- t891 = * ADD long $329 /--* t883 ref +--* t891 long N010 ( 4, 4) [000892] -------N---- t892 = * ADD byref $82 /--* t892 byref N013 ( 12, 11) [000897] *---G--N---- t897 = * IND ref N014 ( 1, 1) [000418] ------------ t418 = LCL_VAR ref V12 loc8 u:1 $223 N015 ( 1, 1) [000424] ------------ t424 = LCL_VAR ref V01 arg1 u:1 $101 N016 ( 1, 1) [000901] ------------ t901 = LCL_VAR ref V12 loc8 u:1 $223 /--* t901 ref N017 ( 3, 2) [000902] #--X-------- t902 = * IND long $463 N018 ( 1, 1) [000903] ------------ t903 = CNS_INT int 72 $c9 /--* t902 long +--* t903 int N019 ( 4, 3) [000904] ---X---N---- t904 = * ADD long $32c /--* t904 long N020 ( 6, 5) [000905] #--X-------- t905 = * IND long $465 N021 ( 1, 1) [000906] ------------ t906 = CNS_INT int 32 $d2 /--* t905 long +--* t906 int N022 ( 7, 6) [000907] ---X---N---- t907 = * ADD long $32e /--* t907 long N023 ( 9, 8) [000908] n--X-------- t908 = * IND long /--* t897 ref arg1 in rdx +--* t418 ref this in rcx +--* t424 ref arg2 in r8 +--* t908 long control expr N024 ( 43, 32) [000425] --CXG------- t425 = * CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals $581 N025 ( 1, 1) [000426] ------------ t426 = CNS_INT int 0 $c0 /--* t425 int +--* t426 int N026 ( 45, 34) [000427] J--XG--N---- t427 = * NE int $1bd /--* t427 int N027 ( 47, 36) [000428] ---XG------- * JTRUE void ------------ BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} [001370] ------------ IL_OFFSET void IL offset: 0x157 N001 ( 1, 1) [001252] ------------ t1252 = LCL_VAR byref V65 cse0 u:1 $82 N002 ( 1, 1) [000931] ------------ t931 = CNS_INT long 20 field offset Fseq[next] $24c /--* t1252 byref +--* t931 long N003 ( 2, 2) [000932] ----G--N---- t932 = * ADD byref $28e /--* t932 byref N004 ( 4, 4) [000404] *--XG------- t404 = * IND int /--* t404 int N006 ( 4, 4) [000406] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:5 [001371] ------------ IL_OFFSET void IL offset: 0x166 N001 ( 1, 1) [000407] ------------ t407 = LCL_VAR int V07 loc3 u:5 (last use) $3c1 N002 ( 1, 1) [000408] ------------ t408 = CNS_INT int 1 $c1 /--* t407 int +--* t408 int N003 ( 3, 3) [000409] ------------ t409 = * ADD int $605 /--* t409 int N005 ( 3, 3) [000411] DA---------- * STORE_LCL_VAR int V07 loc3 d:6 [001372] ------------ IL_OFFSET void IL offset: 0x16a N001 ( 1, 1) [001321] ------------ t1321 = LCL_VAR int V76 cse11 N002 ( 1, 1) [000412] ------------ t412 = LCL_VAR int V07 loc3 u:6 $605 /--* t1321 int +--* t412 int N003 ( 3, 3) [000415] N------N-U-- t415 = * LT int /--* t415 int N004 ( 5, 5) [000416] ------------ * JTRUE void ------------ BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} ------------ BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} [001373] ------------ IL_OFFSET void IL offset: 0x137 N001 ( 2, 2) [000429] ------------ t429 = LCL_VAR int V03 arg3 u:1 $140 /--* t429 int N002 ( 3, 4) [000909] ------------ t909 = * CAST int <- ubyte <- int $1be N003 ( 1, 1) [000430] ------------ t430 = CNS_INT int 1 $c1 /--* t909 int +--* t430 int N004 ( 5, 6) [000431] N------N-U-- t431 = * NE int $1bf /--* t431 int N005 ( 7, 8) [000432] ------------ * JTRUE void ------------ BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} [001374] ------------ IL_OFFSET void IL offset: 0x13b N001 ( 1, 1) [001253] ------------ t1253 = LCL_VAR byref V65 cse0 u:1 $82 N002 ( 1, 1) [000910] ------------ t910 = CNS_INT long 8 field offset Fseq[value] $240 /--* t1253 byref +--* t910 long N003 ( 2, 2) [000911] ----G--N---- t911 = * ADD byref $28d N005 ( 1, 1) [000479] ------------ t479 = LCL_VAR ref V02 arg2 u:1 (last use) $102 /--* t911 byref +--* t479 ref [001375] -A-XG------- * STOREIND ref ------------ BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} [001376] ------------ IL_OFFSET void IL offset: 0x14b N001 ( 2, 2) [000433] ------------ t433 = LCL_VAR int V03 arg3 u:1 (last use) $140 /--* t433 int N002 ( 3, 4) [000926] ------------ t926 = * CAST int <- ubyte <- int $1be N003 ( 1, 1) [000434] ------------ t434 = CNS_INT int 2 $c2 /--* t926 int +--* t434 int N004 ( 5, 6) [000435] N------N-U-- t435 = * EQ int $600 /--* t435 int N005 ( 7, 8) [000436] ------------ * JTRUE void ------------ BB31 [???..???) (return), preds={BB30,BB41} succs={} N001 ( 1, 1) [000437] ------------ t437 = CNS_INT int 0 $c0 /--* t437 int N002 ( 2, 2) [000811] ------------ * RETURN int $1f3 ------------ BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} N001 ( 0, 0) [001229] ------------ t1229 = PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [001218] ------------ t1218 = PHI_ARG int V07 loc3 u:1 $c0 /--* t1229 int +--* t1218 int N003 ( 0, 0) [001207] ------------ t1207 = * PHI int /--* t1207 int N005 ( 0, 0) [001208] DA---------- * STORE_LCL_VAR int V07 loc3 d:3 N001 ( 0, 0) [001230] ------------ t1230 = PHI_ARG int V09 loc5 u:3 N002 ( 0, 0) [001219] ------------ t1219 = PHI_ARG int V09 loc5 u:1 /--* t1230 int +--* t1219 int N003 ( 0, 0) [001204] ------------ t1204 = * PHI int /--* t1204 int N005 ( 0, 0) [001205] DA---------- * STORE_LCL_VAR int V09 loc5 d:2 [001377] ------------ IL_OFFSET void IL offset: 0x177 N001 ( 1, 1) [000063] ------------ t63 = LCL_VAR ref V04 loc0 u:1 /--* t63 ref N002 ( 3, 3) [000064] ---X-------- t64 = * ARR_LENGTH int /--* t64 int N004 ( 3, 3) [001323] DA-X-------- * STORE_LCL_VAR int V76 cse11 N005 ( 1, 1) [001324] ------------ t1324 = LCL_VAR int V76 cse11 N007 ( 1, 1) [000062] ------------ t62 = LCL_VAR int V09 loc5 u:2 $3c4 /--* t1324 int +--* t62 int N008 ( 6, 6) [000065] N--X---N-U-- t65 = * LE int /--* t65 int N009 ( 8, 8) [000066] ---X-------- * JTRUE void ------------ BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} [001378] ------------ IL_OFFSET void IL offset: 0x17e N001 ( 1, 1) [000949] ------------ t949 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000950] ------------ t950 = LCL_VAR int V09 loc5 u:2 $3c4 /--* t950 int N003 ( 2, 3) [000953] ------------ t953 = * CAST long <- int $6e1 N004 ( 1, 1) [000960] ------------ t960 = CNS_INT long 3 $24b /--* t953 long +--* t960 long N005 ( 7, 7) [000961] ------------ t961 = * MUL long $6e2 /--* t961 long N007 ( 7, 7) [001281] DA---------- * STORE_LCL_VAR long V71 cse6 d:1 N008 ( 1, 1) [001282] ------------ t1282 = LCL_VAR long V71 cse6 u:1 $6e2 N010 ( 1, 1) [000954] -------N---- t954 = CNS_INT long 3 $24b /--* t1282 long +--* t954 long N011 ( 9, 9) [000955] -------N---- t955 = * LSH long $6e3 N012 ( 1, 1) [000956] ------------ t956 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t955 long +--* t956 long N013 ( 10, 10) [000957] -------N---- t957 = * ADD long $6e4 /--* t949 ref +--* t957 long N014 ( 11, 11) [000958] -------N---- t958 = * ADD byref $91 /--* t958 byref N018 ( 23, 23) [001255] DA--G------- * STORE_LCL_VAR byref V66 cse1 d:1 N019 ( 1, 1) [001256] ------------ t1256 = LCL_VAR byref V66 cse1 u:1 N021 ( 1, 1) [000947] ------------ t947 = CNS_INT long 16 field offset Fseq[hashCode] $241 /--* t1256 byref +--* t947 long N022 ( 25, 25) [000948] ----G--N---- t948 = * ADD byref $2ac /--* t948 byref N023 ( 27, 27) [000212] *--XG------- t212 = * IND int N024 ( 1, 1) [000213] ------------ t213 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t212 int +--* t213 int N025 ( 29, 29) [000214] N--XG--N-U-- t214 = * NE int /--* t214 int N026 ( 31, 31) [000215] ---XG------- * JTRUE void ------------ BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} [001379] ------------ IL_OFFSET void IL offset: 0x18e N001 ( 1, 1) [000963] ------------ t963 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [001284] ------------ t1284 = LCL_VAR long V71 cse6 u:1 $6e2 N003 ( 1, 1) [000968] -------N---- t968 = CNS_INT long 3 $24b /--* t1284 long +--* t968 long N004 ( 2, 2) [000969] -------N---- t969 = * LSH long $6e3 N005 ( 1, 1) [000970] ------------ t970 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t969 long +--* t970 long N006 ( 3, 3) [000971] -------N---- t971 = * ADD long $6e4 /--* t963 ref +--* t971 long N007 ( 4, 4) [000972] -------N---- t972 = * ADD byref $91 /--* t972 byref N010 ( 12, 11) [000977] *---G--N---- t977 = * IND ref /--* t977 ref N012 ( 12, 11) [000246] DA--G------- * STORE_LCL_VAR ref V17 tmp3 d:1 [001380] ------------ IL_OFFSET void IL offset: 0x18e N001 ( 1, 1) [000241] !----------- t241 = LCL_VAR ref V00 this u:1 $100 /--* t241 ref N002 ( 3, 2) [000242] #----O------ t242 = * IND long $2e8 /--* t242 long N004 ( 3, 3) [000244] DA---O------ * STORE_LCL_VAR long V16 tmp2 d:1 N001 ( 1, 1) [000249] ------------ t249 = LCL_VAR long V16 tmp2 u:1 $2e7 N002 ( 1, 1) [000250] ------------ t250 = CNS_INT long 56 $244 /--* t249 long +--* t250 long N003 ( 2, 2) [000251] -------N---- t251 = * ADD long $306 /--* t251 long N004 ( 4, 4) [000252] #----------- t252 = * IND long $2e9 /--* t252 long N005 ( 7, 6) [000253] #----------- t253 = * IND long $2ea N006 ( 1, 1) [000254] ------------ t254 = CNS_INT long 48 $246 /--* t253 long +--* t254 long N007 ( 8, 7) [000255] -------N---- t255 = * ADD long $6e6 /--* t255 long N008 ( 10, 9) [000259] n----------- t259 = * IND long /--* t259 long N010 ( 10, 9) [001261] DA---------- * STORE_LCL_VAR long V67 cse2 d:1 N011 ( 1, 1) [001262] ------------ t1262 = LCL_VAR long V67 cse2 u:1 N013 ( 1, 1) [000262] ------------ t262 = CNS_INT long 0 $243 /--* t1262 long +--* t262 long N014 ( 13, 12) [000263] J------N---- t263 = * EQ int /--* t263 int N015 ( 15, 14) [001163] ------------ * JTRUE void ------------ BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} N001 ( 1, 1) [001264] ------------ t1264 = LCL_VAR long V67 cse2 u:1 /--* t1264 long N003 ( 1, 3) [001165] DA---------- * STORE_LCL_VAR long V19 tmp5 d:3 ------------ BB36 [???..???), preds={BB34} succs={BB37} N003 ( 1, 1) [000248] ------?----- t248 = LCL_VAR long V16 tmp2 u:1 (last use) $2e7 N004 ( 2, 10) [000260] H-----?----- t260 = CNS_INT(h) long 0xd1ffab1e global ptr $63 /--* t248 long arg0 in rcx +--* t260 long arg1 in rdx N005 ( 17, 18) [000261] --C-G-?----- t261 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $6e7 /--* t261 long N007 ( 17, 18) [001167] DA--G------- * STORE_LCL_VAR long V19 tmp5 d:2 ------------ BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} N001 ( 0, 0) [001234] ------------ t1234 = PHI_ARG long V19 tmp5 u:3 N002 ( 0, 0) [001233] ------------ t1233 = PHI_ARG long V19 tmp5 u:2 $6e7 /--* t1234 long +--* t1233 long N003 ( 0, 0) [001210] ------------ t1210 = * PHI long /--* t1210 long N005 ( 0, 0) [001211] DA---------- * STORE_LCL_VAR long V19 tmp5 d:1 N005 ( 1, 1) [000234] ------------ t234 = LCL_VAR ref V05 loc1 u:1 N006 ( 1, 1) [000980] ------------ t980 = LCL_VAR long V19 tmp5 u:1 r11 REG r11 $349 N007 ( 1, 1) [000247] ------------ t247 = LCL_VAR ref V17 tmp3 u:1 (last use) N008 ( 1, 1) [000258] ------------ t258 = LCL_VAR ref V01 arg1 u:1 $101 N009 ( 1, 1) [000279] ------------ t279 = LCL_VAR long V19 tmp5 u:1 (last use) $349 /--* t234 ref this in rcx +--* t980 long arg1 in r11 +--* t247 ref arg2 in rdx +--* t258 ref arg3 in r8 +--* t279 long calli tgt N010 ( 28, 14) [000280] --CXG------- t280 = * CALL ind stub int $1ef N011 ( 1, 1) [000281] ------------ t281 = CNS_INT int 0 $c0 /--* t280 int +--* t281 int N012 ( 30, 16) [000282] J--XG--N---- t282 = * EQ int $817 /--* t282 int N013 ( 32, 18) [000283] ---XG------- * JTRUE void ------------ BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} [001381] ------------ IL_OFFSET void IL offset: 0x1a4 N001 ( 2, 2) [000284] ------------ t284 = LCL_VAR int V03 arg3 u:1 $140 /--* t284 int N002 ( 3, 4) [000985] ------------ t985 = * CAST int <- ubyte <- int $1be N003 ( 1, 1) [000285] ------------ t285 = CNS_INT int 1 $c1 /--* t985 int +--* t285 int N004 ( 5, 6) [000286] N------N-U-- t286 = * NE int $1bf /--* t286 int N005 ( 7, 8) [000287] ------------ * JTRUE void ------------ BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} [001382] ------------ IL_OFFSET void IL offset: 0x1a8 N001 ( 1, 1) [001258] ------------ t1258 = LCL_VAR byref V66 cse1 u:1 $91 N002 ( 1, 1) [000986] ------------ t986 = CNS_INT long 8 field offset Fseq[value] $240 /--* t1258 byref +--* t986 long N003 ( 2, 2) [000987] ----G--N---- t987 = * ADD byref $2ae N005 ( 1, 1) [000334] ------------ t334 = LCL_VAR ref V02 arg2 u:1 (last use) $102 /--* t987 byref +--* t334 ref [001383] -A-XG------- * STOREIND ref ------------ BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} [001384] ------------ IL_OFFSET void IL offset: 0x1b8 N001 ( 2, 2) [000288] ------------ t288 = LCL_VAR int V03 arg3 u:1 (last use) $140 /--* t288 int N002 ( 3, 4) [001002] ------------ t1002 = * CAST int <- ubyte <- int $1be N003 ( 1, 1) [000289] ------------ t289 = CNS_INT int 2 $c2 /--* t1002 int +--* t289 int N004 ( 5, 6) [000290] N------N-U-- t290 = * EQ int $600 /--* t290 int N005 ( 7, 8) [000291] ------------ * JTRUE void ------------ BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} ------------ BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} [001385] ------------ IL_OFFSET void IL offset: 0x1c4 N001 ( 1, 1) [001259] ------------ t1259 = LCL_VAR byref V66 cse1 u:1 $91 N002 ( 1, 1) [001008] ------------ t1008 = CNS_INT long 20 field offset Fseq[next] $24c /--* t1259 byref +--* t1008 long N003 ( 2, 2) [001009] ----G--N---- t1009 = * ADD byref $2ad /--* t1009 byref N004 ( 4, 4) [000220] *--XG------- t220 = * IND int /--* t220 int N006 ( 4, 4) [000222] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:3 [001386] ------------ IL_OFFSET void IL offset: 0x1d3 N001 ( 1, 1) [000223] ------------ t223 = LCL_VAR int V07 loc3 u:3 (last use) $3c3 N002 ( 1, 1) [000224] ------------ t224 = CNS_INT int 1 $c1 /--* t223 int +--* t224 int N003 ( 3, 3) [000225] ------------ t225 = * ADD int $81a /--* t225 int N005 ( 3, 3) [000227] DA---------- * STORE_LCL_VAR int V07 loc3 d:4 [001387] ------------ IL_OFFSET void IL offset: 0x1d7 N001 ( 1, 1) [001328] ------------ t1328 = LCL_VAR int V76 cse11 N002 ( 1, 1) [000228] ------------ t228 = LCL_VAR int V07 loc3 u:4 $81a /--* t1328 int +--* t228 int N003 ( 3, 3) [000231] N------N-U-- t231 = * LT int /--* t231 int N004 ( 5, 5) [000232] ------------ * JTRUE void ------------ BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} ------------ BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} N001 ( 0, 0) [001237] ------------ t1237 = PHI_ARG int V07 loc3 u:5 $3c1 N002 ( 0, 0) [001228] ------------ t1228 = PHI_ARG int V07 loc3 u:3 $3c3 /--* t1237 int +--* t1228 int N003 ( 0, 0) [001180] ------------ t1180 = * PHI int /--* t1180 int N005 ( 0, 0) [001181] DA---------- * STORE_LCL_VAR int V07 loc3 d:2 [001388] ------------ IL_OFFSET void IL offset: 0x1e4 N001 ( 1, 1) [000067] ------------ t67 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001024] ------------ t1024 = CNS_INT long 64 field offset Fseq[_freeCount] $245 /--* t67 ref +--* t1024 long N003 ( 2, 2) [001025] -------N---- t1025 = * ADD byref $28f /--* t1025 byref N004 ( 4, 4) [000068] n---GO------ t68 = * IND int N005 ( 1, 1) [000069] ------------ t69 = CNS_INT int 0 $c0 /--* t68 int +--* t69 int N006 ( 6, 6) [000070] J---GO-N---- t70 = * LE int /--* t70 int N007 ( 8, 8) [000071] ----GO------ * JTRUE void ------------ BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} [001389] ------------ IL_OFFSET void IL offset: 0x1ed N001 ( 1, 1) [000171] ------------ t171 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001026] ------------ t1026 = CNS_INT long 60 field offset Fseq[_freeList] $24d /--* t171 ref +--* t1026 long N003 ( 2, 2) [001027] -------N---- t1027 = * ADD byref $295 /--* t1027 byref N004 ( 4, 4) [000172] n---GO------ t172 = * IND int /--* t172 int N006 ( 8, 7) [001306] DA--GO------ * STORE_LCL_VAR int V74 cse9 d:1 N007 ( 3, 2) [001307] ------------ t1307 = LCL_VAR int V74 cse9 u:1 /--* t1307 int N010 ( 15, 12) [000174] DA--GO------ * STORE_LCL_VAR int V10 loc6 d:3 [001390] ------------ IL_OFFSET void IL offset: 0x1f5 N001 ( 3, 2) [001309] ------------ t1309 = LCL_VAR int V74 cse9 u:1 /--* t1309 int N003 ( 3, 3) [001032] DA--G------- * STORE_LCL_VAR int V62 tmp48 d:1 N004 ( 1, 1) [001033] ------------ t1033 = LCL_VAR int V62 tmp48 u:1 N005 ( 1, 1) [001329] ------------ t1329 = LCL_VAR int V76 cse11 /--* t1033 int +--* t1329 int N006 ( 6, 9) [001036] ---X-------- * ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [001030] ------------ t1030 = LCL_VAR ref V04 loc0 u:1 N008 ( 1, 1) [001034] ------------ t1034 = LCL_VAR int V62 tmp48 u:1 (last use) /--* t1034 int N009 ( 2, 3) [001037] ------------ t1037 = * CAST long <- int N010 ( 1, 1) [001047] ------------ t1047 = CNS_INT long 3 $24b /--* t1037 long +--* t1047 long N011 ( 7, 7) [001048] ------------ t1048 = * MUL long N012 ( 1, 1) [001038] -------N---- t1038 = CNS_INT long 3 $24b /--* t1048 long +--* t1038 long N013 ( 8, 8) [001039] -------N---- t1039 = * LSH long N014 ( 1, 1) [001040] ------------ t1040 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t1039 long +--* t1040 long N015 ( 9, 9) [001041] -------N---- t1041 = * ADD long /--* t1030 ref +--* t1041 long N016 ( 10, 10) [001042] -------N---- t1042 = * ADD byref $88 N021 ( 1, 1) [001028] ------------ t1028 = CNS_INT long 20 field offset Fseq[next] $24c /--* t1042 byref +--* t1028 long N022 ( 31, 34) [001029] ---XG--N---- t1029 = * ADD byref $29c /--* t1029 byref N023 ( 33, 36) [000181] *--XG------- t181 = * IND int /--* t181 int N024 ( 34, 37) [001050] ---XG------- t1050 = * NEG int N025 ( 1, 1) [000175] ------------ t175 = CNS_INT int -3 $e1 /--* t1050 int +--* t175 int N026 ( 36, 39) [000182] ---XG------- t182 = * ADD int N027 ( 1, 1) [000183] ------------ t183 = CNS_INT int -1 $c4 /--* t182 int +--* t183 int N028 ( 41, 41) [000184] ---XG------- t184 = * GE int /--* t184 int N030 ( 45, 44) [000688] DA-XG------- * STORE_LCL_VAR int V49 tmp35 d:1 [001391] ------------ IL_OFFSET void IL offset: 0x1f5 N001 ( 1, 1) [001300] ------------ t1300 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1300 ref N003 ( 5, 4) [000698] DA--G------- * STORE_LCL_VAR ref V50 tmp36 d:1 [001392] ------------ IL_OFFSET void IL offset: 0x1f5 N001 ( 3, 2) [000690] ------------ t690 = LCL_VAR int V49 tmp35 u:1 (last use) N002 ( 1, 1) [000691] ------------ t691 = CNS_INT int 0 $c0 /--* t690 int +--* t691 int N003 ( 5, 4) [000692] J------N---- t692 = * NE int /--* t692 int N004 ( 7, 6) [000693] ------------ * JTRUE void ------------ BB46 [1F5..1F6), preds={BB45} succs={BB47} [001393] ------------ IL_OFFSET void IL offset: 0x1f5 N003 ( 2, 10) [001051] H----------- t1051 = CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" $5e /--* t1051 long N004 ( 4, 12) [001052] #---G------- t1052 = * IND ref $114 N005 ( 3, 2) [000695] ------------ t695 = LCL_VAR ref V50 tmp36 u:1 (last use) $105 /--* t1052 ref arg0 in rcx +--* t695 ref arg1 in rdx N006 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} [001394] ------------ IL_OFFSET void IL offset: 0x219 N001 ( 1, 1) [000190] ------------ t190 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001055] ------------ t1055 = CNS_INT long 60 field offset Fseq[_freeList] $24d /--* t190 ref +--* t1055 long N003 ( 2, 2) [001056] -------N---- t1056 = * ADD byref $295 N005 ( 1, 1) [000193] ------------ t193 = LCL_VAR ref V00 this u:1 $100 N006 ( 1, 1) [001074] ------------ t1074 = CNS_INT long 60 field offset Fseq[_freeList] $24d /--* t193 ref +--* t1074 long N007 ( 2, 2) [001075] -------N---- t1075 = * ADD byref $295 /--* t1075 byref N008 ( 4, 4) [000194] n---GO------ t194 = * IND int /--* t194 int N010 ( 4, 4) [001061] DA--GO------ * STORE_LCL_VAR int V63 tmp49 d:1 N011 ( 1, 1) [001062] ------------ t1062 = LCL_VAR int V63 tmp49 u:1 N012 ( 1, 1) [001330] ------------ t1330 = LCL_VAR int V76 cse11 /--* t1062 int +--* t1330 int N013 ( 6, 9) [001065] ---X-------- * ARR_BOUNDS_CHECK_Rng void N014 ( 1, 1) [001059] ------------ t1059 = LCL_VAR ref V04 loc0 u:1 N015 ( 1, 1) [001063] ------------ t1063 = LCL_VAR int V63 tmp49 u:1 (last use) /--* t1063 int N016 ( 2, 3) [001066] ------------ t1066 = * CAST long <- int N017 ( 1, 1) [001076] ------------ t1076 = CNS_INT long 3 $24b /--* t1066 long +--* t1076 long N018 ( 7, 7) [001077] ------------ t1077 = * MUL long N019 ( 1, 1) [001067] -------N---- t1067 = CNS_INT long 3 $24b /--* t1077 long +--* t1067 long N020 ( 8, 8) [001068] -------N---- t1068 = * LSH long N021 ( 1, 1) [001069] ------------ t1069 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t1068 long +--* t1069 long N022 ( 9, 9) [001070] -------N---- t1070 = * ADD long /--* t1059 ref +--* t1070 long N023 ( 10, 10) [001071] -------N---- t1071 = * ADD byref $8a N028 ( 1, 1) [001057] ------------ t1057 = CNS_INT long 20 field offset Fseq[next] $24c /--* t1071 byref +--* t1057 long N029 ( 32, 35) [001058] ---XGO-N---- t1058 = * ADD byref $2a3 /--* t1058 byref N030 ( 34, 37) [000197] *--XGO------ t197 = * IND int /--* t197 int N031 ( 35, 38) [001079] ---XGO------ t1079 = * NEG int N032 ( 1, 1) [000191] ------------ t191 = CNS_INT int -3 $e1 /--* t1079 int +--* t191 int N033 ( 37, 40) [000198] ---XGO------ t198 = * ADD int /--* t1056 byref +--* t198 int [001395] -A-XGO------ * STOREIND int [001396] ------------ IL_OFFSET void IL offset: 0x233 N001 ( 1, 1) [000202] ------------ t202 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001082] ------------ t1082 = CNS_INT long 64 field offset Fseq[_freeCount] $245 /--* t202 ref +--* t1082 long N003 ( 2, 2) [001083] -------N---- t1083 = * ADD byref $28f /--* t1083 byref N004 ( 4, 4) [000203] n---GO------ t203 = * IND int N005 ( 1, 1) [000204] ------------ t204 = CNS_INT int -1 $c4 /--* t203 int +--* t204 int N006 ( 6, 6) [000205] ----GO------ t205 = * ADD int N007 ( 1, 1) [000201] ------------ t201 = LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001080] ------------ t1080 = CNS_INT long 64 field offset Fseq[_freeCount] $245 /--* t201 ref +--* t1080 long N009 ( 2, 2) [001081] -------N---- t1081 = * ADD byref $28f /--* t1081 byref +--* t205 int [001397] -A--GO------ * STOREIND int ------------ BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} [001398] ------------ IL_OFFSET void IL offset: 0x243 N001 ( 1, 1) [000072] ------------ t72 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001084] ------------ t1084 = CNS_INT long 56 field offset Fseq[_count] $244 /--* t72 ref +--* t1084 long N003 ( 2, 2) [001085] -------N---- t1085 = * ADD byref $290 /--* t1085 byref N004 ( 4, 4) [000073] n---GO------ t73 = * IND int /--* t73 int N006 ( 8, 7) [001311] DA--GO------ * STORE_LCL_VAR int V75 cse10 d:1 N007 ( 3, 2) [001312] ------------ t1312 = LCL_VAR int V75 cse10 u:1 /--* t1312 int N010 ( 15, 12) [000075] DA--GO------ * STORE_LCL_VAR int V13 loc9 d:1 [001399] ------------ IL_OFFSET void IL offset: 0x24b N001 ( 1, 1) [001331] ------------ t1331 = LCL_VAR int V76 cse11 N002 ( 3, 2) [000076] ------------ t76 = LCL_VAR int V13 loc9 u:1 /--* t1331 int +--* t76 int N003 ( 5, 4) [000079] N------N-U-- t79 = * NE int /--* t79 int N004 ( 7, 6) [000080] ------------ * JTRUE void ------------ BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} [001400] ------------ IL_OFFSET void IL offset: 0x252 N003 ( 3, 2) [001314] ------------ t1314 = LCL_VAR int V75 cse10 u:1 /--* t1314 int arg0 in rcx N004 ( 17, 8) [000702] --CXG------- t702 = * CALL int System.Collections.HashHelpers.ExpandPrime $1d7 /--* t702 int N006 ( 21, 11) [001090] DA-XG-----L- * STORE_LCL_VAR int V64 tmp50 d:1 N008 ( 3, 2) [001091] ------------ t1091 = LCL_VAR int V64 tmp50 u:1 (last use) $1d7 N009 ( 1, 1) [000163] ------------ t163 = LCL_VAR ref V00 this u:1 $100 N010 ( 1, 1) [000704] ------------ t704 = CNS_INT int 0 $c0 /--* t1091 int arg1 in rdx +--* t163 ref this in rcx +--* t704 int arg2 in r8 N011 ( 43, 24) [000705] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void [001401] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [000165] ------------ t165 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001094] ------------ t1094 = CNS_INT long 8 field offset Fseq[_buckets] $240 /--* t165 ref +--* t1094 long N003 ( 2, 2) [001095] -------N---- t1095 = * ADD byref $280 /--* t1095 byref N004 ( 4, 4) [000709] n---GO------ t709 = * IND ref /--* t709 ref N006 ( 8, 7) [000711] DA--GO------ * STORE_LCL_VAR ref V52 tmp38 d:1 [001402] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000713] ------------ t713 = LCL_VAR ref V52 tmp38 u:1 /--* t713 ref N002 ( 5, 4) [000714] ---X-------- t714 = * ARR_LENGTH int /--* t714 int N004 ( 9, 7) [001286] DA-X-------- * STORE_LCL_VAR int V72 cse7 d:1 N005 ( 3, 2) [001287] ------------ t1287 = LCL_VAR int V72 cse7 u:1 /--* t1287 int N008 ( 12, 9) [000760] DA-X-------- * STORE_LCL_VAR int V53 tmp39 d:1 [001403] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [000715] ------------ t715 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001096] ------------ t1096 = CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 /--* t715 ref +--* t1096 long N003 ( 2, 2) [001097] -------N---- t1097 = * ADD byref $283 /--* t1097 byref N004 ( 4, 4) [000716] n---GO------ t716 = * IND long /--* t716 long N006 ( 8, 7) [000762] DA--GO------ * STORE_LCL_VAR long V54 tmp40 d:1 [001404] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [000728] ------------ t728 = LCL_VAR int V53 tmp39 u:1 N002 ( 1, 4) [000729] ------------ t729 = CNS_INT int 0x7FFFFFFF $ce /--* t728 int +--* t729 int N003 ( 6, 6) [000730] N--------U-- t730 = * LE int /--* t730 int N005 ( 10, 9) [000773] DA---------- * STORE_LCL_VAR int V56 tmp42 d:1 [001405] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [001301] ------------ t1301 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1301 ref N003 ( 5, 4) [000783] DA--G------- * STORE_LCL_VAR ref V57 tmp43 d:1 [001406] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [001302] ------------ t1302 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1302 ref N003 ( 5, 4) [000785] DA--G------- * STORE_LCL_VAR ref V58 tmp44 d:1 [001407] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000775] ------------ t775 = LCL_VAR int V56 tmp42 u:1 (last use) N002 ( 1, 1) [000776] ------------ t776 = CNS_INT int 0 $c0 /--* t775 int +--* t776 int N003 ( 5, 4) [000777] J------N---- t777 = * NE int /--* t777 int N004 ( 7, 6) [000778] ------------ * JTRUE void ------------ BB50 [258..259), preds={BB49} succs={BB51} [001408] ------------ IL_OFFSET void IL offset: 0x258 N003 ( 3, 2) [000779] ------------ t779 = LCL_VAR ref V58 tmp44 u:1 (last use) $105 N004 ( 3, 2) [000780] ------------ t780 = LCL_VAR ref V58 tmp44 u:1 (last use) $105 /--* t779 ref arg0 in rcx +--* t780 ref arg1 in rdx N005 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} [001409] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000735] ------------ t735 = LCL_VAR long V54 tmp40 u:1 (last use) N002 ( 1, 1) [000166] ------------ t166 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t166 int N003 ( 2, 3) [000736] ---------U-- t736 = * CAST long <- ulong <- uint $310 /--* t735 long +--* t736 long N004 ( 9, 8) [000737] ------------ t737 = * MUL long N005 ( 1, 1) [000738] ------------ t738 = CNS_INT int 32 $d2 /--* t737 long +--* t738 int N006 ( 11, 10) [000739] ------------ t739 = * RSZ long N007 ( 1, 1) [000741] ------------ t741 = CNS_INT long 1 $247 /--* t739 long +--* t741 long N008 ( 13, 12) [000742] ------------ t742 = * ADD long N009 ( 1, 1) [000743] ------------ t743 = LCL_VAR int V53 tmp39 u:1 /--* t743 int N010 ( 2, 3) [000744] ---------U-- t744 = * CAST long <- ulong <- uint /--* t742 long +--* t744 long N011 ( 19, 18) [000745] ------------ t745 = * MUL long N012 ( 1, 1) [000746] ------------ t746 = CNS_INT int 32 $d2 /--* t745 long +--* t746 int N013 ( 21, 20) [000747] ------------ t747 = * RSZ long /--* t747 long N014 ( 22, 22) [000748] ------------ t748 = * CAST int <- uint <- long /--* t748 int N016 ( 26, 25) [000750] DA---------- * STORE_LCL_VAR int V55 tmp41 d:1 [001410] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [000752] ------------ t752 = LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000753] ------------ t753 = LCL_VAR int V53 tmp39 u:1 (last use) /--* t752 int +--* t753 int N003 ( 22, 5) [000754] ---X-------- t754 = * UMOD int N004 ( 3, 2) [000751] ------------ t751 = LCL_VAR int V55 tmp41 u:1 /--* t754 int +--* t751 int N005 ( 29, 8) [000755] ---X-------- t755 = * EQ int /--* t755 int N007 ( 33, 11) [000796] DA-X-------- * STORE_LCL_VAR int V59 tmp45 d:1 [001411] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [001303] ------------ t1303 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1303 ref N003 ( 5, 4) [000806] DA--G------- * STORE_LCL_VAR ref V60 tmp46 d:1 [001412] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [001304] ------------ t1304 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1304 ref N003 ( 5, 4) [000808] DA--G------- * STORE_LCL_VAR ref V61 tmp47 d:1 [001413] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000798] ------------ t798 = LCL_VAR int V59 tmp45 u:1 (last use) N002 ( 1, 1) [000799] ------------ t799 = CNS_INT int 0 $c0 /--* t798 int +--* t799 int N003 ( 5, 4) [000800] J------N---- t800 = * NE int /--* t800 int N004 ( 7, 6) [000801] ------------ * JTRUE void ------------ BB52 [258..259), preds={BB51} succs={BB53} [001414] ------------ IL_OFFSET void IL offset: 0x258 N003 ( 3, 2) [000802] ------------ t802 = LCL_VAR ref V61 tmp47 u:1 (last use) $105 N004 ( 3, 2) [000803] ------------ t803 = LCL_VAR ref V61 tmp47 u:1 (last use) $105 /--* t802 ref arg0 in rcx +--* t803 ref arg1 in rdx N005 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB53 [258..259), preds={BB51,BB52} succs={BB54} [001415] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000758] ------------ t758 = LCL_VAR int V55 tmp41 u:1 N002 ( 3, 2) [001289] ------------ t1289 = LCL_VAR int V72 cse7 u:1 /--* t758 int +--* t1289 int N003 ( 10, 11) [001105] ---X-------- * ARR_BOUNDS_CHECK_Rng void N004 ( 3, 2) [001102] ------------ t1102 = LCL_VAR ref V52 tmp38 u:1 (last use) N005 ( 3, 2) [001103] ------------ t1103 = LCL_VAR int V55 tmp41 u:1 (last use) /--* t1103 int N006 ( 4, 4) [001106] ------------ t1106 = * CAST long <- int N007 ( 1, 1) [001107] -------N---- t1107 = CNS_INT long 2 $248 /--* t1106 long +--* t1107 long N008 ( 5, 5) [001108] -------N---- t1108 = * LSH long N009 ( 1, 1) [001109] ------------ t1109 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t1108 long +--* t1109 long N010 ( 6, 6) [001110] -------N---- t1110 = * ADD long /--* t1102 ref +--* t1110 long N011 ( 9, 8) [001111] -------N---- t1111 = * ADD byref $87 /--* t1111 byref N016 ( 33, 31) [000722] DA-XG------- * STORE_LCL_VAR byref V51 tmp37 d:1 N001 ( 3, 2) [000723] ------------ t723 = LCL_VAR byref V51 tmp37 u:1 (last use) $87 /--* t723 byref N003 ( 7, 5) [000170] DA---------- * STORE_LCL_VAR byref V08 loc4 d:4 ------------ BB54 [261..276), preds={BB48,BB53} succs={BB55} N001 ( 0, 0) [001224] ------------ t1224 = PHI_ARG byref V08 loc4 u:4 $87 N002 ( 0, 0) [001220] ------------ t1220 = PHI_ARG byref V08 loc4 u:1 $81 /--* t1224 byref +--* t1220 byref N003 ( 0, 0) [001192] ------------ t1192 = * PHI byref /--* t1192 byref N005 ( 0, 0) [001193] DA---------- * STORE_LCL_VAR byref V08 loc4 d:3 [001416] ------------ IL_OFFSET void IL offset: 0x261 N001 ( 3, 2) [000081] ------------ t81 = LCL_VAR int V13 loc9 u:1 /--* t81 int N003 ( 7, 5) [000083] DA---------- * STORE_LCL_VAR int V10 loc6 d:2 [001417] ------------ IL_OFFSET void IL offset: 0x265 N001 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V10 loc6 u:2 (last use) N002 ( 1, 1) [000086] ------------ t86 = CNS_INT int 1 $c1 /--* t85 int +--* t86 int N003 ( 5, 4) [000087] ------------ t87 = * ADD int N004 ( 1, 1) [000084] ------------ t84 = LCL_VAR ref V00 this u:1 $100 N005 ( 1, 1) [001114] ------------ t1114 = CNS_INT long 56 field offset Fseq[_count] $244 /--* t84 ref +--* t1114 long N006 ( 2, 2) [001115] -------N---- t1115 = * ADD byref $290 /--* t1115 byref +--* t87 int [001418] -A--GO------ * STOREIND int [001419] ------------ IL_OFFSET void IL offset: 0x26f N001 ( 1, 1) [000090] ------------ t90 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001116] ------------ t1116 = CNS_INT long 16 field offset Fseq[_entries] $241 /--* t90 ref +--* t1116 long N003 ( 2, 2) [001117] -------N---- t1117 = * ADD byref $281 /--* t1117 byref N004 ( 4, 4) [000091] n---GO------ t91 = * IND ref /--* t91 ref N006 ( 4, 4) [000093] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:3 ------------ BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} N001 ( 0, 0) [001225] ------------ t1225 = PHI_ARG byref V08 loc4 u:1 $81 N002 ( 0, 0) [001221] ------------ t1221 = PHI_ARG byref V08 loc4 u:3 $780 /--* t1225 byref +--* t1221 byref N003 ( 0, 0) [001195] ------------ t1195 = * PHI byref /--* t1195 byref N005 ( 0, 0) [001196] DA---------- * STORE_LCL_VAR byref V08 loc4 d:2 N001 ( 0, 0) [001226] ------------ t1226 = PHI_ARG ref V04 loc0 u:1 N002 ( 0, 0) [001222] ------------ t1222 = PHI_ARG ref V04 loc0 u:3 /--* t1226 ref +--* t1222 ref N003 ( 0, 0) [001189] ------------ t1189 = * PHI ref /--* t1189 ref N005 ( 0, 0) [001190] DA---------- * STORE_LCL_VAR ref V04 loc0 d:2 N001 ( 0, 0) [001227] ------------ t1227 = PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [001223] ------------ t1223 = PHI_ARG int V10 loc6 u:2 /--* t1227 int +--* t1223 int N003 ( 0, 0) [001186] ------------ t1186 = * PHI int /--* t1186 int N005 ( 0, 0) [001187] DA---------- * STORE_LCL_VAR int V10 loc6 d:1 [001420] ------------ IL_OFFSET void IL offset: 0x276 N001 ( 3, 2) [000095] ------------ t95 = LCL_VAR int V10 loc6 u:1 $3cc N002 ( 1, 1) [000094] ------------ t94 = LCL_VAR ref V04 loc0 u:2 $684 /--* t94 ref N003 ( 3, 3) [001120] ---X-------- t1120 = * ARR_LENGTH int $73d /--* t95 int +--* t1120 int N004 ( 10, 12) [001121] ---X-------- * ARR_BOUNDS_CHECK_Rng void $7cd N005 ( 1, 1) [001118] ------------ t1118 = LCL_VAR ref V04 loc0 u:2 $684 N006 ( 3, 2) [001119] ------------ t1119 = LCL_VAR int V10 loc6 u:1 $3cc /--* t1119 int N007 ( 4, 4) [001122] ------------ t1122 = * CAST long <- int $6dc N008 ( 1, 1) [001129] ------------ t1129 = CNS_INT long 3 $24b /--* t1122 long +--* t1129 long N009 ( 9, 8) [001130] ------------ t1130 = * MUL long $6dd N010 ( 1, 1) [001123] -------N---- t1123 = CNS_INT long 3 $24b /--* t1130 long +--* t1123 long N011 ( 10, 9) [001124] -------N---- t1124 = * LSH long $6de N012 ( 1, 1) [001125] ------------ t1125 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t1124 long +--* t1125 long N013 ( 11, 10) [001126] -------N---- t1126 = * ADD long $6df /--* t1118 ref +--* t1126 long N014 ( 12, 11) [001127] -------N---- t1127 = * ADD byref $8c /--* t1127 byref N019 ( 39, 38) [000099] DA-XG------- * STORE_LCL_VAR byref V11 loc7 d:1 [001421] ------------ IL_OFFSET void IL offset: 0x280 N001 ( 3, 2) [000100] ------------ t100 = LCL_VAR byref V11 loc7 u:1 $8c N002 ( 1, 1) [001132] ------------ t1132 = CNS_INT long 16 field offset Fseq[hashCode] $241 /--* t100 byref +--* t1132 long N003 ( 4, 3) [001133] -------N---- t1133 = * ADD byref $8d N005 ( 1, 1) [000101] ------------ t101 = LCL_VAR int V06 loc2 u:1 (last use) $3c0 /--* t1133 byref +--* t101 int [001422] -A-XG------- * STOREIND int [001423] ------------ IL_OFFSET void IL offset: 0x288 N001 ( 3, 2) [000105] ------------ t105 = LCL_VAR byref V08 loc4 u:2 $781 /--* t105 byref N002 ( 6, 4) [000106] *--XG------- t106 = * IND int N003 ( 1, 1) [000107] ------------ t107 = CNS_INT int -1 $c4 /--* t106 int +--* t107 int N004 ( 8, 6) [000108] ---XG------- t108 = * ADD int N005 ( 3, 2) [000104] ------------ t104 = LCL_VAR byref V11 loc7 u:1 $8c N006 ( 1, 1) [001134] ------------ t1134 = CNS_INT long 20 field offset Fseq[next] $24c /--* t104 byref +--* t1134 long N007 ( 4, 3) [001135] -------N---- t1135 = * ADD byref $8e /--* t1135 byref +--* t108 int [001424] -A-XGO------ * STOREIND int [001425] ------------ IL_OFFSET void IL offset: 0x294 N001 ( 3, 2) [000111] ------------ t111 = LCL_VAR byref V11 loc7 u:1 Zero Fseq[key] $8f N003 ( 1, 1) [000112] ------------ t112 = LCL_VAR ref V01 arg1 u:1 (last use) $101 /--* t111 byref +--* t112 ref [001426] -A-XG------- * STOREIND ref [001427] ------------ IL_OFFSET void IL offset: 0x29c N001 ( 3, 2) [000115] ------------ t115 = LCL_VAR byref V11 loc7 u:1 (last use) $8c N002 ( 1, 1) [001136] ------------ t1136 = CNS_INT long 8 field offset Fseq[value] $240 /--* t115 byref +--* t1136 long N003 ( 4, 3) [001137] -------N---- t1137 = * ADD byref $90 N005 ( 1, 1) [000116] ------------ t116 = LCL_VAR ref V02 arg2 u:1 (last use) $102 /--* t1137 byref +--* t116 ref [001428] -A--GO------ * STOREIND ref [001429] ------------ IL_OFFSET void IL offset: 0x2a4 N001 ( 3, 2) [000120] ------------ t120 = LCL_VAR int V10 loc6 u:1 (last use) $3cc N002 ( 1, 1) [000121] ------------ t121 = CNS_INT int 1 $c1 /--* t120 int +--* t121 int N003 ( 5, 4) [000122] ------------ t122 = * ADD int $804 N004 ( 3, 2) [000119] ------------ t119 = LCL_VAR byref V08 loc4 u:2 (last use) $781 /--* t119 byref +--* t122 int [001430] -A--GO------ * STOREIND int [001431] ------------ IL_OFFSET void IL offset: 0x2ab N001 ( 1, 1) [000126] ------------ t126 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001140] ------------ t1140 = CNS_INT long 68 field offset Fseq[_version] $24e /--* t126 ref +--* t1140 long N003 ( 2, 2) [001141] -------N---- t1141 = * ADD byref $2a7 /--* t1141 byref N004 ( 4, 4) [000127] n---GO------ t127 = * IND int N005 ( 1, 1) [000128] ------------ t128 = CNS_INT int 1 $c1 /--* t127 int +--* t128 int N006 ( 6, 6) [000129] ----GO------ t129 = * ADD int N007 ( 1, 1) [000125] ------------ t125 = LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001138] ------------ t1138 = CNS_INT long 68 field offset Fseq[_version] $24e /--* t125 ref +--* t1138 long N009 ( 2, 2) [001139] -------N---- t1139 = * ADD byref $2a7 /--* t1139 byref +--* t129 int [001432] -A--GO------ * STOREIND int [001433] ------------ IL_OFFSET void IL offset: 0x2ca N001 ( 1, 1) [000145] ------------ t145 = LCL_VAR int V07 loc3 u:2 (last use) $3c5 N002 ( 1, 1) [000146] ------------ t146 = CNS_INT int 100 $e3 /--* t145 int +--* t146 int N003 ( 3, 3) [000147] N------N-U-- t147 = * LE int $80d /--* t147 int N004 ( 5, 5) [000148] ------------ * JTRUE void ------------ BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} [001434] ------------ IL_OFFSET void IL offset: 0x2cf N003 ( 1, 1) [000151] ------------ t151 = LCL_VAR ref V05 loc1 u:1 (last use) N004 ( 2, 10) [000152] H------N---- t152 = CNS_INT(h) long 0xd1ffab1e class $62 /--* t151 ref arg1 in rdx +--* t152 long arg0 in rcx N005 ( 17, 18) [000153] --C-G------- t153 = * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS N006 ( 1, 1) [000154] ------------ t154 = CNS_INT ref null $VN.Null /--* t153 ref +--* t154 ref N007 ( 19, 20) [000155] J---G--N---- t155 = * EQ int /--* t155 int N008 ( 21, 22) [000156] ----G------- * JTRUE void ------------ BB57 [2D7..2E3), preds={BB56} succs={BB58} [001435] ------------ IL_OFFSET void IL offset: 0x2d7 N004 ( 1, 1) [000158] ------------ t158 = LCL_VAR ref V04 loc0 u:2 (last use) $684 /--* t158 ref N005 ( 3, 3) [000159] ---X-------- t159 = * ARR_LENGTH int $73d N006 ( 1, 1) [000157] ------------ t157 = LCL_VAR ref V00 this u:1 $100 N007 ( 1, 1) [000160] ------------ t160 = CNS_INT int 1 $c1 /--* t159 int arg1 in rdx +--* t157 ref this in rcx +--* t160 int arg2 in r8 N008 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void ------------ BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} N001 ( 1, 1) [000482] ------------ t482 = CNS_INT int 1 $c1 /--* t482 int N002 ( 2, 2) [000810] ------------ * RETURN int $1f4 ------------ BB59 [008..00E) (throw), preds={BB01} succs={} [001436] ------------ IL_OFFSET void IL offset: 0x8 N002 ( 1, 1) [000532] ------------ t532 = CNS_INT int 4 $c5 /--* t532 int arg0 in rcx N003 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException $VN.Void ------------ BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} [001437] ------------ IL_OFFSET void IL offset: 0x14f N001 ( 1, 1) [000441] !----------- t441 = LCL_VAR ref V00 this u:1 $100 /--* t441 ref N002 ( 3, 2) [000442] #----O------ t442 = * IND long $2e8 /--* t442 long N004 ( 7, 5) [000444] DA---O------ * STORE_LCL_VAR long V26 tmp12 d:1 N001 ( 3, 2) [000446] ------------ t446 = LCL_VAR long V26 tmp12 u:1 $2e7 N002 ( 1, 1) [000447] ------------ t447 = CNS_INT long 56 $244 /--* t446 long +--* t447 long N003 ( 4, 3) [000448] -------N---- t448 = * ADD long $306 /--* t448 long N004 ( 6, 5) [000449] #----------- t449 = * IND long $2e9 /--* t449 long N005 ( 9, 7) [000450] #----------- t450 = * IND long $2ea N006 ( 1, 1) [000451] ------------ t451 = CNS_INT long 56 $244 /--* t450 long +--* t451 long N007 ( 10, 8) [000452] -------N---- t452 = * ADD long $331 /--* t452 long N008 ( 12, 10) [000456] n----------- t456 = * IND long N009 ( 1, 1) [000459] ------------ t459 = CNS_INT long 0 $243 /--* t456 long +--* t459 long N010 ( 14, 12) [000460] J------N---- t460 = * EQ int /--* t460 int N011 ( 16, 14) [001158] ------------ * JTRUE void ------------ BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} N001 ( 3, 2) [000466] ------?----- t466 = LCL_VAR long V26 tmp12 u:1 (last use) $2e7 N002 ( 1, 1) [000467] ------?----- t467 = CNS_INT long 56 $244 /--* t466 long +--* t467 long N003 ( 4, 3) [000465] ------?N---- t465 = * ADD long $306 /--* t465 long N004 ( 6, 5) [000464] #-----?----- t464 = * IND long $2e9 /--* t464 long N005 ( 9, 7) [000463] #-----?----- t463 = * IND long $2ea N006 ( 1, 1) [000468] ------?----- t468 = CNS_INT long 56 $244 /--* t463 long +--* t468 long N007 ( 10, 8) [000462] ------?N---- t462 = * ADD long $331 /--* t462 long N008 ( 12, 10) [000461] n-----?----- t461 = * IND long /--* t461 long N010 ( 16, 13) [001160] DA---------- * STORE_LCL_VAR long V28 tmp14 d:3 ------------ BB62 [???..???), preds={BB60} succs={BB63} N003 ( 3, 2) [000445] ------?----- t445 = LCL_VAR long V26 tmp12 u:1 (last use) $2e7 N004 ( 2, 10) [000457] H-----?----- t457 = CNS_INT(h) long 0xd1ffab1e global ptr $52 /--* t445 long arg0 in rcx +--* t457 long arg1 in rdx N005 ( 19, 19) [000458] --C-G-?----- t458 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 /--* t458 long N007 ( 23, 22) [001162] DA--G------- * STORE_LCL_VAR long V28 tmp14 d:2 ------------ BB63 [???..157) (throw), preds={BB61,BB62} succs={} N001 ( 0, 0) [001241] ------------ t1241 = PHI_ARG long V28 tmp14 u:3 N002 ( 0, 0) [001240] ------------ t1240 = PHI_ARG long V28 tmp14 u:2 $332 /--* t1241 long +--* t1240 long N003 ( 0, 0) [001183] ------------ t1183 = * PHI long /--* t1183 long N005 ( 0, 0) [001184] DA---------- * STORE_LCL_VAR long V28 tmp14 d:1 N003 ( 3, 2) [000473] ------------ t473 = LCL_VAR long V28 tmp14 u:1 (last use) $347 N004 ( 1, 1) [000455] ------------ t455 = LCL_VAR ref V01 arg1 u:1 (last use) $101 /--* t473 long arg0 in rcx +--* t455 ref arg1 in rdx N005 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void ------------ BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} [001438] ------------ IL_OFFSET void IL offset: 0x1bc N001 ( 1, 1) [000296] !----------- t296 = LCL_VAR ref V00 this u:1 $100 /--* t296 ref N002 ( 3, 2) [000297] #----O------ t297 = * IND long $2e8 /--* t297 long N004 ( 7, 5) [000299] DA---O------ * STORE_LCL_VAR long V21 tmp7 d:1 N001 ( 3, 2) [000301] ------------ t301 = LCL_VAR long V21 tmp7 u:1 $2e7 N002 ( 1, 1) [000302] ------------ t302 = CNS_INT long 56 $244 /--* t301 long +--* t302 long N003 ( 4, 3) [000303] -------N---- t303 = * ADD long $306 /--* t303 long N004 ( 6, 5) [000304] #----------- t304 = * IND long $2e9 /--* t304 long N005 ( 9, 7) [000305] #----------- t305 = * IND long $2ea N006 ( 1, 1) [000306] ------------ t306 = CNS_INT long 56 $244 /--* t305 long +--* t306 long N007 ( 10, 8) [000307] -------N---- t307 = * ADD long $331 /--* t307 long N008 ( 12, 10) [000311] n----------- t311 = * IND long N009 ( 1, 1) [000314] ------------ t314 = CNS_INT long 0 $243 /--* t311 long +--* t314 long N010 ( 14, 12) [000315] J------N---- t315 = * EQ int /--* t315 int N011 ( 16, 14) [001168] ------------ * JTRUE void ------------ BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} N001 ( 3, 2) [000321] ------?----- t321 = LCL_VAR long V21 tmp7 u:1 (last use) $2e7 N002 ( 1, 1) [000322] ------?----- t322 = CNS_INT long 56 $244 /--* t321 long +--* t322 long N003 ( 4, 3) [000320] ------?N---- t320 = * ADD long $306 /--* t320 long N004 ( 6, 5) [000319] #-----?----- t319 = * IND long $2e9 /--* t319 long N005 ( 9, 7) [000318] #-----?----- t318 = * IND long $2ea N006 ( 1, 1) [000323] ------?----- t323 = CNS_INT long 56 $244 /--* t318 long +--* t323 long N007 ( 10, 8) [000317] ------?N---- t317 = * ADD long $331 /--* t317 long N008 ( 12, 10) [000316] n-----?----- t316 = * IND long /--* t316 long N010 ( 16, 13) [001170] DA---------- * STORE_LCL_VAR long V23 tmp9 d:3 ------------ BB66 [???..???), preds={BB64} succs={BB67} N003 ( 3, 2) [000300] ------?----- t300 = LCL_VAR long V21 tmp7 u:1 (last use) $2e7 N004 ( 2, 10) [000312] H-----?----- t312 = CNS_INT(h) long 0xd1ffab1e global ptr $52 /--* t300 long arg0 in rcx +--* t312 long arg1 in rdx N005 ( 19, 19) [000313] --C-G-?----- t313 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 /--* t313 long N007 ( 23, 22) [001172] DA--G------- * STORE_LCL_VAR long V23 tmp9 d:2 ------------ BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} N001 ( 0, 0) [001232] ------------ t1232 = PHI_ARG long V23 tmp9 u:3 N002 ( 0, 0) [001231] ------------ t1231 = PHI_ARG long V23 tmp9 u:2 $332 /--* t1232 long +--* t1231 long N003 ( 0, 0) [001201] ------------ t1201 = * PHI long /--* t1201 long N005 ( 0, 0) [001202] DA---------- * STORE_LCL_VAR long V23 tmp9 d:1 N003 ( 3, 2) [000328] ------------ t328 = LCL_VAR long V23 tmp9 u:1 (last use) $34b N004 ( 1, 1) [000310] ------------ t310 = LCL_VAR ref V01 arg1 u:1 (last use) $101 /--* t328 long arg0 in rcx +--* t310 ref arg1 in rdx N005 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void ------------ BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} [001439] ------------ IL_OFFSET void IL offset: 0x1dd N001 ( 14, 5) [000233] --CXG------- CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Do 'simple' lowering Bumping outgoingArgSpaceSize to 32 for call [000528] outgoingArgSpaceSize 32 sufficient for call [000552], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000574], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000503], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000522], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000035], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000650], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000673], which needs 32 *** Computing fgRngChkTarget for block BB18 fgNewBBinRegion(jumpKind=3, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=true, insertAtEnd=true): inserting after BB68 New Basic Block BB69 [0117] created. fgAddCodeRef - Add BB in non-EH region for RNGCHK_FAIL, new block BB69 [0117] Initializing arg info for 1444.CALL: ArgTable for 1444.CALL after fgInitArgInfo: Morphing args for 1444.CALL: argSlots=0, preallocatedArgCount=4, nextSlotNum=4, nextSlotByteOffset=32, outgoingArgSpaceSize=32 ArgTable for 1444.CALL after fgMorphArgs: outgoingArgSpaceSize 32 sufficient for call [000367], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000352], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000425], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000261], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000280], which needs 32 *** Computing fgRngChkTarget for block BB45 outgoingArgSpaceSize 32 sufficient for call [000696], which needs 32 *** Computing fgRngChkTarget for block BB47 outgoingArgSpaceSize 32 sufficient for call [000702], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000705], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000781], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000804], which needs 32 *** Computing fgRngChkTarget for block BB53 *** Computing fgRngChkTarget for block BB55 outgoingArgSpaceSize 32 sufficient for call [000153], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000161], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000533], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000458], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000440], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000313], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000295], which needs 32 outgoingArgSpaceSize 32 sufficient for call [000233], which needs 32 outgoingArgSpaceSize 32 sufficient for call [001444], which needs 32 After fgSimpleLowering() added some RngChk throw blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i LIR BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i LIR BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe LIR BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i LIR BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe LIR BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i LIR BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe LIR BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i LIR BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe LIR BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe LIR BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe LIR BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe LIR BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe LIR BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen LIR BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe LIR BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen LIR BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe LIR BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen LIR BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe LIR BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe LIR BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe LIR BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe LIR BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target LIR BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd LIR BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd LIR BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd LIR BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal LIR BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd LIR BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen LIR BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd LIR BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal Loop1 gcsafe LIR BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target LIR BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd LIR BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd LIR BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe LIR BB36 [0108] 1 BB34 1 [???..???) i gcsafe LIR BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd LIR BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd LIR BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen LIR BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd LIR BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe LIR BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd LIR BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal LIR BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i LIR BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen LIR BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe LIR BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen LIR BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen LIR BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen LIR BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe LIR BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen LIR BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe LIR BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen LIR BB54 [0044] 2 BB48,BB53 0.50 [261..276) i LIR BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen LIR BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall LIR BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen LIR BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal LIR BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe LIR BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd LIR BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe LIR BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe LIR BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd LIR BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd LIR BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe LIR BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe LIR BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd LIR BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd LIR BB69 [0117] 0 0 [???..???) (throw ) keep i internal rare LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** Finishing PHASE Do 'simple' lowering *************** In fgDebugCheckBBlist Trees before Lowering nodeinfo ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i LIR BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i LIR BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe LIR BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i LIR BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe LIR BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i LIR BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe LIR BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i LIR BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe LIR BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe LIR BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe LIR BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe LIR BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe LIR BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen LIR BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe LIR BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen LIR BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe LIR BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen LIR BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe LIR BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe LIR BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe LIR BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe LIR BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target LIR BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd LIR BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd LIR BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd LIR BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal LIR BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd LIR BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen LIR BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd LIR BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal Loop1 gcsafe LIR BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target LIR BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd LIR BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd LIR BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe LIR BB36 [0108] 1 BB34 1 [???..???) i gcsafe LIR BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd LIR BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd LIR BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen LIR BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd LIR BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe LIR BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd LIR BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal LIR BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i LIR BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen LIR BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe LIR BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen LIR BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen LIR BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen LIR BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe LIR BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen LIR BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe LIR BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen LIR BB54 [0044] 2 BB48,BB53 0.50 [261..276) i LIR BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen LIR BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall LIR BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen LIR BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal LIR BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe LIR BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd LIR BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe LIR BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe LIR BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd LIR BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd LIR BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe LIR BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe LIR BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd LIR BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd LIR BB69 [0117] 0 0 [???..???) (throw ) keep i internal rare LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} [001332] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V01 arg1 u:1 $101 N002 ( 1, 1) [000001] ------------ t1 = CNS_INT ref null $VN.Null /--* t0 ref +--* t1 ref N003 ( 3, 3) [000002] J------N---- t2 = * EQ int $180 /--* t2 int N004 ( 5, 5) [000003] ------------ * JTRUE void ------------ BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} [001333] ------------ IL_OFFSET void IL offset: 0xe N001 ( 1, 1) [000004] ------------ t4 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000813] ------------ t813 = CNS_INT long 8 field offset Fseq[_buckets] $240 /--* t4 ref +--* t813 long N003 ( 2, 2) [000814] -------N---- t814 = * ADD byref $280 /--* t814 byref N004 ( 4, 4) [000005] ---XG------- t5 = * IND ref N005 ( 1, 1) [000006] ------------ t6 = CNS_INT ref null $VN.Null /--* t5 ref +--* t6 ref N006 ( 6, 6) [000007] J--XG--N---- t7 = * NE int /--* t7 int N007 ( 8, 8) [000008] ---XG------- * JTRUE void ------------ BB03 [016..01E), preds={BB02} succs={BB04} N003 ( 1, 1) [000526] ------------ t526 = LCL_VAR ref V00 this u:1 $100 N004 ( 1, 1) [000527] ------------ t527 = CNS_INT int 0 $c0 /--* t526 ref this in rcx +--* t527 int arg1 in rdx N005 ( 16, 10) [000528] --CXG------- t528 = * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize $1c2 ------------ BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} [001334] ------------ IL_OFFSET void IL offset: 0x1e N001 ( 1, 1) [000009] ------------ t9 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000817] ------------ t817 = CNS_INT long 8 field offset Fseq[_buckets] $240 /--* t9 ref +--* t817 long N003 ( 2, 2) [000818] -------N---- t818 = * ADD byref $280 /--* t818 byref N004 ( 4, 4) [000010] n---GO------ t10 = * IND ref N005 ( 1, 1) [000011] ------------ t11 = CNS_INT ref null $VN.Null /--* t10 ref +--* t11 ref N006 ( 9, 6) [000012] N---GO------ t12 = * NE int /--* t12 int N008 ( 9, 6) [000544] DA--GO------ * STORE_LCL_VAR int V33 tmp19 d:1 [001335] ------------ IL_OFFSET void IL offset: 0x1e N001 ( 2, 10) [000537] H----------- t537 = CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 /--* t537 long N002 ( 4, 12) [000538] #---G------- t538 = * IND ref $105 /--* t538 ref N004 ( 4, 12) [001291] DA--G------- * STORE_LCL_VAR ref V73 cse8 d:1 N005 ( 1, 1) [001292] ------------ t1292 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1292 ref N008 ( 5, 13) [000554] DA--G------- * STORE_LCL_VAR ref V34 tmp20 d:1 [001336] ------------ IL_OFFSET void IL offset: 0x1e N001 ( 1, 1) [001294] ------------ t1294 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1294 ref N003 ( 1, 3) [000556] DA--G------- * STORE_LCL_VAR ref V35 tmp21 d:1 [001337] ------------ IL_OFFSET void IL offset: 0x1e N001 ( 1, 1) [000546] ------------ t546 = LCL_VAR int V33 tmp19 u:1 (last use) N002 ( 1, 1) [000547] ------------ t547 = CNS_INT int 0 $c0 /--* t546 int +--* t547 int N003 ( 3, 3) [000548] J------N---- t548 = * NE int /--* t548 int N004 ( 5, 5) [000549] ------------ * JTRUE void ------------ BB05 [01E..01F), preds={BB04} succs={BB06} [001338] ------------ IL_OFFSET void IL offset: 0x1e N003 ( 1, 1) [000550] ------------ t550 = LCL_VAR ref V35 tmp21 u:1 (last use) $105 N004 ( 1, 1) [000551] ------------ t551 = LCL_VAR ref V35 tmp21 u:1 (last use) $105 /--* t550 ref arg0 in rcx +--* t551 ref arg1 in rdx N005 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} [001339] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 1) [000015] ------------ t15 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000821] ------------ t821 = CNS_INT long 16 field offset Fseq[_entries] $241 /--* t15 ref +--* t821 long N003 ( 2, 2) [000822] -------N---- t822 = * ADD byref $281 /--* t822 byref N004 ( 4, 4) [000016] n---GO------ t16 = * IND ref /--* t16 ref N006 ( 4, 4) [000018] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:1 [001340] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 1, 1) [000019] ------------ t19 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000020] ------------ t20 = CNS_INT ref null $VN.Null /--* t19 ref +--* t20 ref N003 ( 6, 3) [000021] N----------- t21 = * NE int /--* t21 int N005 ( 6, 3) [000566] DA---------- * STORE_LCL_VAR int V36 tmp22 d:1 [001341] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 1, 1) [001295] ------------ t1295 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1295 ref N003 ( 1, 3) [000576] DA--G------- * STORE_LCL_VAR ref V37 tmp23 d:1 [001342] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 1, 1) [000568] ------------ t568 = LCL_VAR int V36 tmp22 u:1 (last use) N002 ( 1, 1) [000569] ------------ t569 = CNS_INT int 0 $c0 /--* t568 int +--* t569 int N003 ( 3, 3) [000570] J------N---- t570 = * NE int /--* t570 int N004 ( 5, 5) [000571] ------------ * JTRUE void ------------ BB07 [033..034), preds={BB06} succs={BB08} [001343] ------------ IL_OFFSET void IL offset: 0x33 N003 ( 2, 10) [000823] H----------- t823 = CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" $46 /--* t823 long N004 ( 4, 12) [000824] #---G------- t824 = * IND ref $106 N005 ( 1, 1) [000573] ------------ t573 = LCL_VAR ref V37 tmp23 u:1 (last use) $105 /--* t824 ref arg0 in rcx +--* t573 ref arg1 in rdx N006 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} [001344] ------------ IL_OFFSET void IL offset: 0x41 N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000827] ------------ t827 = CNS_INT long 24 field offset Fseq[_comparer] $242 /--* t25 ref +--* t827 long N003 ( 2, 2) [000828] -------N---- t828 = * ADD byref $282 /--* t828 byref N004 ( 4, 4) [000026] n---GO------ t26 = * IND ref /--* t26 ref N006 ( 4, 4) [000028] DA--GO------ * STORE_LCL_VAR ref V05 loc1 d:1 [001345] ------------ IL_OFFSET void IL offset: 0x48 N001 ( 1, 1) [000029] ------------ t29 = LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000030] ------------ t30 = CNS_INT ref null $VN.Null /--* t29 ref +--* t30 ref N003 ( 3, 3) [000031] J------N---- t31 = * EQ int /--* t31 int N004 ( 5, 5) [000032] ------------ * JTRUE void ------------ BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} [001346] ------------ IL_OFFSET void IL offset: 0x4b N001 ( 1, 1) [000486] !----------- t486 = LCL_VAR ref V00 this u:1 $100 /--* t486 ref N002 ( 3, 2) [000487] #----O------ t487 = * IND long $2e8 /--* t487 long N004 ( 3, 3) [000489] DA---O------ * STORE_LCL_VAR long V29 tmp15 d:1 N001 ( 1, 1) [000491] ------------ t491 = LCL_VAR long V29 tmp15 u:1 $2e7 N002 ( 1, 1) [000492] ------------ t492 = CNS_INT long 56 $244 /--* t491 long +--* t492 long N003 ( 2, 2) [000493] -------N---- t493 = * ADD long $306 /--* t493 long N004 ( 4, 4) [000494] #----------- t494 = * IND long $2e9 /--* t494 long N005 ( 7, 6) [000495] #----------- t495 = * IND long $2ea N006 ( 1, 1) [000496] ------------ t496 = CNS_INT long 64 $245 /--* t495 long +--* t496 long N007 ( 8, 7) [000497] -------N---- t497 = * ADD long $307 /--* t497 long N008 ( 10, 9) [000501] n----------- t501 = * IND long /--* t501 long N010 ( 14, 12) [001266] DA---------- * STORE_LCL_VAR long V68 cse3 d:1 N011 ( 3, 2) [001267] ------------ t1267 = LCL_VAR long V68 cse3 u:1 N013 ( 1, 1) [000504] ------------ t504 = CNS_INT long 0 $243 /--* t1267 long +--* t504 long N014 ( 19, 16) [000505] J------N---- t505 = * EQ int /--* t505 int N015 ( 21, 18) [001148] ------------ * JTRUE void ------------ BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} N001 ( 3, 2) [001269] ------------ t1269 = LCL_VAR long V68 cse3 u:1 /--* t1269 long N003 ( 3, 3) [001150] DA---------- * STORE_LCL_VAR long V31 tmp17 d:3 ------------ BB11 [???..???), preds={BB09} succs={BB12} N003 ( 1, 1) [000490] ------?----- t490 = LCL_VAR long V29 tmp15 u:1 (last use) $2e7 N004 ( 2, 10) [000502] H-----?----- t502 = CNS_INT(h) long 0xd1ffab1e global ptr $49 /--* t490 long arg0 in rcx +--* t502 long arg1 in rdx N005 ( 17, 18) [000503] --C-G-?----- t503 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $308 /--* t503 long N007 ( 17, 18) [001152] DA--G------- * STORE_LCL_VAR long V31 tmp17 d:2 ------------ BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} N001 ( 0, 0) [001247] ------------ t1247 = PHI_ARG long V31 tmp17 u:3 N002 ( 0, 0) [001246] ------------ t1246 = PHI_ARG long V31 tmp17 u:2 $308 /--* t1247 long +--* t1246 long N003 ( 0, 0) [001216] ------------ t1216 = * PHI long /--* t1216 long N005 ( 0, 0) [001217] DA---------- * STORE_LCL_VAR long V31 tmp17 d:1 N004 ( 1, 1) [000484] ------------ t484 = LCL_VAR ref V05 loc1 u:1 N005 ( 1, 1) [000831] ------------ t831 = LCL_VAR long V31 tmp17 u:1 r11 REG r11 $342 N006 ( 1, 1) [000500] ------------ t500 = LCL_VAR ref V01 arg1 u:1 $101 N007 ( 1, 1) [000521] ------------ t521 = LCL_VAR long V31 tmp17 u:1 (last use) $342 /--* t484 ref this in rcx +--* t831 long arg1 in r11 +--* t500 ref arg2 in rdx +--* t521 long calli tgt N008 ( 27, 12) [000522] --CXG------- t522 = * CALL ind stub int $1c7 /--* t522 int N010 ( 31, 15) [000524] DA-XG------- * STORE_LCL_VAR int V15 tmp1 d:3 ------------ BB13 [054..061), preds={BB08} succs={BB14} [001347] ------------ IL_OFFSET void IL offset: 0x54 N002 ( 1, 1) [000033] ------------ t33 = LCL_VAR ref V01 arg1 u:1 $101 N003 ( 1, 1) [000836] ------------ t836 = LCL_VAR ref V01 arg1 u:1 $101 /--* t836 ref N004 ( 3, 2) [000837] #----O------ t837 = * IND long $2e4 N005 ( 1, 1) [000838] ------------ t838 = CNS_INT int 72 $c9 /--* t837 long +--* t838 int N006 ( 4, 3) [000839] -----O-N---- t839 = * ADD long $301 /--* t839 long N007 ( 6, 5) [000840] #----O------ t840 = * IND long $2e6 N008 ( 1, 1) [000841] ------------ t841 = CNS_INT int 24 $ca /--* t840 long +--* t841 int N009 ( 7, 6) [000842] -----O-N---- t842 = * ADD long $303 /--* t842 long N010 ( 9, 8) [000843] n----O------ t843 = * IND long /--* t33 ref this in rcx +--* t843 long control expr N011 ( 30, 18) [000035] --CXGO------ t35 = * CALLV vt-ind int System.Object.GetHashCode $1c5 /--* t35 int N013 ( 34, 21) [000038] DA-XGO------ * STORE_LCL_VAR int V15 tmp1 d:2 ------------ BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} N001 ( 0, 0) [001245] ------------ t1245 = PHI_ARG int V15 tmp1 u:3 $1c7 N002 ( 0, 0) [001244] ------------ t1244 = PHI_ARG int V15 tmp1 u:2 $1c5 /--* t1245 int +--* t1244 int N003 ( 0, 0) [001213] ------------ t1213 = * PHI int /--* t1213 int N005 ( 0, 0) [001214] DA---------- * STORE_LCL_VAR int V15 tmp1 d:1 N001 ( 3, 2) [000040] ------------ t40 = LCL_VAR int V15 tmp1 u:1 (last use) $3c0 /--* t40 int N003 ( 3, 3) [000042] DA---------- * STORE_LCL_VAR int V06 loc2 d:1 [001348] ------------ IL_OFFSET void IL offset: 0x62 N001 ( 1, 1) [000043] ------------ t43 = CNS_INT int 0 $c0 /--* t43 int N003 ( 1, 3) [000045] DA---------- * STORE_LCL_VAR int V07 loc3 d:1 [001349] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000046] ------------ t46 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000844] ------------ t844 = CNS_INT long 8 field offset Fseq[_buckets] $240 /--* t46 ref +--* t844 long N003 ( 2, 2) [000845] -------N---- t845 = * ADD byref $280 /--* t845 byref N004 ( 4, 4) [000578] n---GO------ t578 = * IND ref /--* t578 ref N006 ( 4, 4) [000580] DA--GO------ * STORE_LCL_VAR ref V39 tmp25 d:1 [001350] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000582] ------------ t582 = LCL_VAR ref V39 tmp25 u:1 [001440] ------------ t1440 = CNS_INT long 8 /--* t582 ref +--* t1440 long [001441] ------------ t1441 = * ADD ref /--* t1441 ref N002 ( 3, 3) [000583] ---X-------- t583 = * IND int /--* t583 int N004 ( 3, 3) [000629] DA-X-------- * STORE_LCL_VAR int V40 tmp26 d:1 [001351] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000584] ------------ t584 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [000846] ------------ t846 = CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 /--* t584 ref +--* t846 long N003 ( 2, 2) [000847] -------N---- t847 = * ADD byref $283 /--* t847 byref N004 ( 4, 4) [000585] n---GO------ t585 = * IND long /--* t585 long N006 ( 4, 4) [000631] DA--GO------ * STORE_LCL_VAR long V41 tmp27 d:1 [001352] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000597] ------------ t597 = LCL_VAR int V40 tmp26 u:1 N002 ( 1, 4) [000598] ------------ t598 = CNS_INT int 0x7FFFFFFF $ce /--* t597 int +--* t598 int N003 ( 6, 6) [000599] N--------U-- t599 = * LE int /--* t599 int N005 ( 6, 6) [000642] DA---------- * STORE_LCL_VAR int V43 tmp29 d:1 [001353] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [001296] ------------ t1296 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1296 ref N003 ( 1, 3) [000652] DA--G------- * STORE_LCL_VAR ref V44 tmp30 d:1 [001354] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [001297] ------------ t1297 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1297 ref N003 ( 1, 3) [000654] DA--G------- * STORE_LCL_VAR ref V45 tmp31 d:1 [001355] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000644] ------------ t644 = LCL_VAR int V43 tmp29 u:1 (last use) N002 ( 1, 1) [000645] ------------ t645 = CNS_INT int 0 $c0 /--* t644 int +--* t645 int N003 ( 3, 3) [000646] J------N---- t646 = * NE int /--* t646 int N004 ( 5, 5) [000647] ------------ * JTRUE void ------------ BB15 [064..065), preds={BB14} succs={BB16} [001356] ------------ IL_OFFSET void IL offset: 0x64 N003 ( 1, 1) [000648] ------------ t648 = LCL_VAR ref V45 tmp31 u:1 (last use) $105 N004 ( 1, 1) [000649] ------------ t649 = LCL_VAR ref V45 tmp31 u:1 (last use) $105 /--* t648 ref arg0 in rcx +--* t649 ref arg1 in rdx N005 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} [001357] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000604] ------------ t604 = LCL_VAR long V41 tmp27 u:1 (last use) N002 ( 1, 1) [000047] ------------ t47 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t47 int N003 ( 2, 3) [000605] ---------U-- t605 = * CAST long <- ulong <- uint $310 /--* t604 long +--* t605 long N004 ( 7, 7) [000606] ------------ t606 = * MUL long N005 ( 1, 1) [000607] ------------ t607 = CNS_INT int 32 $d2 /--* t606 long +--* t607 int N006 ( 9, 9) [000608] ------------ t608 = * RSZ long N007 ( 1, 1) [000610] ------------ t610 = CNS_INT long 1 $247 /--* t608 long +--* t610 long N008 ( 11, 11) [000611] ------------ t611 = * ADD long N009 ( 1, 1) [000612] ------------ t612 = LCL_VAR int V40 tmp26 u:1 /--* t612 int N010 ( 2, 3) [000613] ---------U-- t613 = * CAST long <- ulong <- uint /--* t611 long +--* t613 long N011 ( 17, 17) [000614] ------------ t614 = * MUL long N012 ( 1, 1) [000615] ------------ t615 = CNS_INT int 32 $d2 /--* t614 long +--* t615 int N013 ( 19, 19) [000616] ------------ t616 = * RSZ long /--* t616 long N014 ( 20, 21) [000617] ------------ t617 = * CAST int <- uint <- long /--* t617 int N016 ( 20, 21) [000619] DA---------- * STORE_LCL_VAR int V42 tmp28 d:1 [001358] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000621] ------------ t621 = LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000622] ------------ t622 = LCL_VAR int V40 tmp26 u:1 (last use) /--* t621 int +--* t622 int N003 ( 22, 5) [000623] ---X-------- t623 = * UMOD int N004 ( 1, 1) [000620] ------------ t620 = LCL_VAR int V42 tmp28 u:1 /--* t623 int +--* t620 int N005 ( 27, 7) [000624] ---X-------- t624 = * EQ int /--* t624 int N007 ( 27, 7) [000665] DA-X-------- * STORE_LCL_VAR int V46 tmp32 d:1 [001359] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [001298] ------------ t1298 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1298 ref N003 ( 1, 3) [000675] DA--G------- * STORE_LCL_VAR ref V47 tmp33 d:1 [001360] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [001299] ------------ t1299 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1299 ref N003 ( 1, 3) [000677] DA--G------- * STORE_LCL_VAR ref V48 tmp34 d:1 [001361] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000667] ------------ t667 = LCL_VAR int V46 tmp32 u:1 (last use) N002 ( 1, 1) [000668] ------------ t668 = CNS_INT int 0 $c0 /--* t667 int +--* t668 int N003 ( 3, 3) [000669] J------N---- t669 = * NE int /--* t669 int N004 ( 5, 5) [000670] ------------ * JTRUE void ------------ BB17 [064..065), preds={BB16} succs={BB18} [001362] ------------ IL_OFFSET void IL offset: 0x64 N003 ( 1, 1) [000671] ------------ t671 = LCL_VAR ref V48 tmp34 u:1 (last use) $105 N004 ( 1, 1) [000672] ------------ t672 = LCL_VAR ref V48 tmp34 u:1 (last use) $105 /--* t671 ref arg0 in rcx +--* t672 ref arg1 in rdx N005 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} [001363] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000627] ------------ t627 = LCL_VAR int V42 tmp28 u:1 N002 ( 1, 1) [000581] ------------ t581 = LCL_VAR ref V39 tmp25 u:1 [001442] ------------ t1442 = CNS_INT long 8 /--* t581 ref +--* t1442 long [001443] ------------ t1443 = * ADD ref /--* t1443 ref N003 ( 3, 3) [000854] ---X-------- t854 = * IND int /--* t627 int +--* t854 int N004 ( 8, 11) [000855] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void N005 ( 1, 1) [000852] ------------ t852 = LCL_VAR ref V39 tmp25 u:1 (last use) N006 ( 1, 1) [000853] ------------ t853 = LCL_VAR int V42 tmp28 u:1 (last use) /--* t853 int N007 ( 2, 3) [000856] ------------ t856 = * CAST long <- int N008 ( 1, 1) [000857] -------N---- t857 = CNS_INT long 2 $248 /--* t856 long +--* t857 long N009 ( 3, 4) [000858] -------N---- t858 = * LSH long N010 ( 1, 1) [000859] ------------ t859 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t858 long +--* t859 long N011 ( 4, 5) [000860] -------N---- t860 = * ADD long /--* t852 ref +--* t860 long N012 ( 5, 6) [000861] -------N---- t861 = * ADD byref $81 /--* t861 byref N017 ( 19, 24) [000591] DA-XG------- * STORE_LCL_VAR byref V38 tmp24 d:1 N001 ( 1, 1) [000592] ------------ t592 = LCL_VAR byref V38 tmp24 u:1 $81 /--* t592 byref N003 ( 5, 4) [000051] DA---------- * STORE_LCL_VAR byref V08 loc4 d:1 [001364] ------------ IL_OFFSET void IL offset: 0x6d N001 ( 1, 1) [000052] ------------ t52 = LCL_VAR byref V08 loc4 u:1 (last use) $81 /--* t52 byref N002 ( 3, 2) [000053] *--XG------- t53 = * IND int N003 ( 1, 1) [000054] ------------ t54 = CNS_INT int -1 $c4 /--* t53 int +--* t54 int N004 ( 5, 4) [000055] ---XG------- t55 = * ADD int /--* t55 int N006 ( 5, 4) [000057] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:1 [001365] ------------ IL_OFFSET void IL offset: 0x74 N001 ( 1, 1) [000058] ------------ t58 = LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000059] ------------ t59 = CNS_INT ref null $VN.Null /--* t58 ref +--* t59 ref N003 ( 3, 3) [000060] J------N---- t60 = * NE int /--* t60 int N004 ( 5, 5) [000061] ------------ * JTRUE void ------------ BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} [001366] ------------ IL_OFFSET void IL offset: 0xff N001 ( 1, 1) [000353] !----------- t353 = LCL_VAR ref V00 this u:1 $100 /--* t353 ref N002 ( 3, 2) [000354] #----O------ t354 = * IND long $2e8 /--* t354 long N004 ( 3, 3) [000356] DA---O------ * STORE_LCL_VAR long V24 tmp10 d:1 N001 ( 1, 1) [000358] ------------ t358 = LCL_VAR long V24 tmp10 u:1 $2e7 N002 ( 1, 1) [000359] ------------ t359 = CNS_INT long 56 $244 /--* t358 long +--* t359 long N003 ( 2, 2) [000360] -------N---- t360 = * ADD long $306 /--* t360 long N004 ( 4, 4) [000361] #----------- t361 = * IND long $2e9 /--* t361 long N005 ( 7, 6) [000362] #----------- t362 = * IND long $2ea N006 ( 1, 1) [000363] ------------ t363 = CNS_INT long 32 $24a /--* t362 long +--* t363 long N007 ( 8, 7) [000364] -------N---- t364 = * ADD long $324 /--* t364 long N008 ( 10, 9) [000365] n----------- t365 = * IND long /--* t365 long N010 ( 14, 12) [001271] DA---------- * STORE_LCL_VAR long V69 cse4 d:1 N011 ( 3, 2) [001272] ------------ t1272 = LCL_VAR long V69 cse4 u:1 N013 ( 1, 1) [000368] ------------ t368 = CNS_INT long 0 $243 /--* t1272 long +--* t368 long N014 ( 19, 16) [000369] J------N---- t369 = * EQ int /--* t369 int N015 ( 21, 18) [001153] ------------ * JTRUE void ------------ BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} N001 ( 3, 2) [001274] ------------ t1274 = LCL_VAR long V69 cse4 u:1 /--* t1274 long N003 ( 7, 5) [001155] DA---------- * STORE_LCL_VAR long V25 tmp11 d:3 ------------ BB21 [???..???), preds={BB19} succs={BB22} N003 ( 1, 1) [000357] ------?----- t357 = LCL_VAR long V24 tmp10 u:1 (last use) $2e7 N004 ( 2, 10) [000366] H-----?----- t366 = CNS_INT(h) long 0xd1ffab1e global ptr $4f /--* t357 long arg0 in rcx +--* t366 long arg1 in rdx N005 ( 17, 18) [000367] --C-G-?----- t367 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $325 /--* t367 long N007 ( 21, 21) [001157] DA--G------- * STORE_LCL_VAR long V25 tmp11 d:2 ------------ BB22 [???..106), preds={BB20,BB21} succs={BB23} N001 ( 0, 0) [001243] ------------ t1243 = PHI_ARG long V25 tmp11 u:3 N002 ( 0, 0) [001242] ------------ t1242 = PHI_ARG long V25 tmp11 u:2 $325 /--* t1243 long +--* t1242 long N003 ( 0, 0) [001198] ------------ t1198 = * PHI long /--* t1198 long N005 ( 0, 0) [001199] DA---------- * STORE_LCL_VAR long V25 tmp11 d:1 N002 ( 3, 2) [000382] ------------ t382 = LCL_VAR long V25 tmp11 u:1 (last use) $344 /--* t382 long arg0 in rcx N003 ( 17, 8) [000352] --CXG------- t352 = * CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default $223 /--* t352 ref N005 ( 17, 8) [000386] DA-XG------- * STORE_LCL_VAR ref V12 loc8 d:1 ------------ BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} N001 ( 0, 0) [001238] ------------ t1238 = PHI_ARG int V07 loc3 u:6 N002 ( 0, 0) [001235] ------------ t1235 = PHI_ARG int V07 loc3 u:1 $c0 /--* t1238 int +--* t1235 int N003 ( 0, 0) [001177] ------------ t1177 = * PHI int /--* t1177 int N005 ( 0, 0) [001178] DA---------- * STORE_LCL_VAR int V07 loc3 d:5 N001 ( 0, 0) [001239] ------------ t1239 = PHI_ARG int V09 loc5 u:5 N002 ( 0, 0) [001236] ------------ t1236 = PHI_ARG int V09 loc5 u:1 /--* t1239 int +--* t1236 int N003 ( 0, 0) [001174] ------------ t1174 = * PHI int /--* t1174 int N005 ( 0, 0) [001175] DA---------- * STORE_LCL_VAR int V09 loc5 d:4 [001367] ------------ IL_OFFSET void IL offset: 0x106 N001 ( 1, 1) [000388] ------------ t388 = LCL_VAR ref V04 loc0 u:1 [001445] ------------ t1445 = CNS_INT long 8 /--* t388 ref +--* t1445 long [001446] ------------ t1446 = * ADD ref /--* t1446 ref N002 ( 3, 3) [000389] ---X-------- t389 = * IND int /--* t389 int N004 ( 3, 3) [001316] DA-X-------- * STORE_LCL_VAR int V76 cse11 N005 ( 1, 1) [001317] ------------ t1317 = LCL_VAR int V76 cse11 N007 ( 1, 1) [000387] ------------ t387 = LCL_VAR int V09 loc5 u:4 $3c2 /--* t1317 int +--* t387 int N008 ( 6, 6) [000390] N--X---N-U-- t390 = * LE int /--* t390 int N009 ( 8, 8) [000391] ---X-------- * JTRUE void ------------ BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} [001368] ------------ IL_OFFSET void IL offset: 0x110 N001 ( 1, 1) [000869] ------------ t869 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000870] ------------ t870 = LCL_VAR int V09 loc5 u:4 $3c2 /--* t870 int N003 ( 2, 3) [000873] ------------ t873 = * CAST long <- int $326 N004 ( 1, 1) [000880] ------------ t880 = CNS_INT long 3 $24b /--* t873 long +--* t880 long N005 ( 7, 7) [000881] ------------ t881 = * MUL long $327 /--* t881 long N007 ( 7, 7) [001276] DA---------- * STORE_LCL_VAR long V70 cse5 d:1 N008 ( 1, 1) [001277] ------------ t1277 = LCL_VAR long V70 cse5 u:1 $327 N010 ( 1, 1) [000874] -------N---- t874 = CNS_INT long 3 $24b /--* t1277 long +--* t874 long N011 ( 9, 9) [000875] -------N---- t875 = * LSH long $328 N012 ( 1, 1) [000876] ------------ t876 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t875 long +--* t876 long N013 ( 10, 10) [000877] -------N---- t877 = * ADD long $329 /--* t869 ref +--* t877 long N014 ( 11, 11) [000878] -------N---- t878 = * ADD byref $82 /--* t878 byref N018 ( 23, 23) [001249] DA--G------- * STORE_LCL_VAR byref V65 cse0 d:1 N019 ( 1, 1) [001250] ------------ t1250 = LCL_VAR byref V65 cse0 u:1 N021 ( 1, 1) [000867] ------------ t867 = CNS_INT long 16 field offset Fseq[hashCode] $241 /--* t1250 byref +--* t867 long N022 ( 25, 25) [000868] ----G--N---- t868 = * ADD byref $28c /--* t868 byref N023 ( 27, 27) [000396] *--XG------- t396 = * IND int N024 ( 1, 1) [000397] ------------ t397 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t396 int +--* t397 int N025 ( 29, 29) [000398] N--XG--N-U-- t398 = * NE int /--* t398 int N026 ( 31, 31) [000399] ---XG------- * JTRUE void ------------ BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} [001369] ------------ IL_OFFSET void IL offset: 0x120 N004 ( 1, 1) [000883] ------------ t883 = LCL_VAR ref V04 loc0 u:1 N005 ( 1, 1) [001279] ------------ t1279 = LCL_VAR long V70 cse5 u:1 $327 N006 ( 1, 1) [000888] -------N---- t888 = CNS_INT long 3 $24b /--* t1279 long +--* t888 long N007 ( 2, 2) [000889] -------N---- t889 = * LSH long $328 N008 ( 1, 1) [000890] ------------ t890 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t889 long +--* t890 long N009 ( 3, 3) [000891] -------N---- t891 = * ADD long $329 /--* t883 ref +--* t891 long N010 ( 4, 4) [000892] -------N---- t892 = * ADD byref $82 /--* t892 byref N013 ( 12, 11) [000897] *---G--N---- t897 = * IND ref N014 ( 1, 1) [000418] ------------ t418 = LCL_VAR ref V12 loc8 u:1 $223 N015 ( 1, 1) [000424] ------------ t424 = LCL_VAR ref V01 arg1 u:1 $101 N016 ( 1, 1) [000901] ------------ t901 = LCL_VAR ref V12 loc8 u:1 $223 /--* t901 ref N017 ( 3, 2) [000902] #--X-------- t902 = * IND long $463 N018 ( 1, 1) [000903] ------------ t903 = CNS_INT int 72 $c9 /--* t902 long +--* t903 int N019 ( 4, 3) [000904] ---X---N---- t904 = * ADD long $32c /--* t904 long N020 ( 6, 5) [000905] #--X-------- t905 = * IND long $465 N021 ( 1, 1) [000906] ------------ t906 = CNS_INT int 32 $d2 /--* t905 long +--* t906 int N022 ( 7, 6) [000907] ---X---N---- t907 = * ADD long $32e /--* t907 long N023 ( 9, 8) [000908] n--X-------- t908 = * IND long /--* t897 ref arg1 in rdx +--* t418 ref this in rcx +--* t424 ref arg2 in r8 +--* t908 long control expr N024 ( 43, 32) [000425] --CXG------- t425 = * CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals $581 N025 ( 1, 1) [000426] ------------ t426 = CNS_INT int 0 $c0 /--* t425 int +--* t426 int N026 ( 45, 34) [000427] J--XG--N---- t427 = * NE int $1bd /--* t427 int N027 ( 47, 36) [000428] ---XG------- * JTRUE void ------------ BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} [001370] ------------ IL_OFFSET void IL offset: 0x157 N001 ( 1, 1) [001252] ------------ t1252 = LCL_VAR byref V65 cse0 u:1 $82 N002 ( 1, 1) [000931] ------------ t931 = CNS_INT long 20 field offset Fseq[next] $24c /--* t1252 byref +--* t931 long N003 ( 2, 2) [000932] ----G--N---- t932 = * ADD byref $28e /--* t932 byref N004 ( 4, 4) [000404] *--XG------- t404 = * IND int /--* t404 int N006 ( 4, 4) [000406] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:5 [001371] ------------ IL_OFFSET void IL offset: 0x166 N001 ( 1, 1) [000407] ------------ t407 = LCL_VAR int V07 loc3 u:5 (last use) $3c1 N002 ( 1, 1) [000408] ------------ t408 = CNS_INT int 1 $c1 /--* t407 int +--* t408 int N003 ( 3, 3) [000409] ------------ t409 = * ADD int $605 /--* t409 int N005 ( 3, 3) [000411] DA---------- * STORE_LCL_VAR int V07 loc3 d:6 [001372] ------------ IL_OFFSET void IL offset: 0x16a N001 ( 1, 1) [001321] ------------ t1321 = LCL_VAR int V76 cse11 N002 ( 1, 1) [000412] ------------ t412 = LCL_VAR int V07 loc3 u:6 $605 /--* t1321 int +--* t412 int N003 ( 3, 3) [000415] N------N-U-- t415 = * LT int /--* t415 int N004 ( 5, 5) [000416] ------------ * JTRUE void ------------ BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} ------------ BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} [001373] ------------ IL_OFFSET void IL offset: 0x137 N001 ( 2, 2) [000429] ------------ t429 = LCL_VAR int V03 arg3 u:1 $140 /--* t429 int N002 ( 3, 4) [000909] ------------ t909 = * CAST int <- ubyte <- int $1be N003 ( 1, 1) [000430] ------------ t430 = CNS_INT int 1 $c1 /--* t909 int +--* t430 int N004 ( 5, 6) [000431] N------N-U-- t431 = * NE int $1bf /--* t431 int N005 ( 7, 8) [000432] ------------ * JTRUE void ------------ BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} [001374] ------------ IL_OFFSET void IL offset: 0x13b N001 ( 1, 1) [001253] ------------ t1253 = LCL_VAR byref V65 cse0 u:1 $82 N002 ( 1, 1) [000910] ------------ t910 = CNS_INT long 8 field offset Fseq[value] $240 /--* t1253 byref +--* t910 long N003 ( 2, 2) [000911] ----G--N---- t911 = * ADD byref $28d N005 ( 1, 1) [000479] ------------ t479 = LCL_VAR ref V02 arg2 u:1 (last use) $102 /--* t911 byref +--* t479 ref [001375] -A-XG------- * STOREIND ref ------------ BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} [001376] ------------ IL_OFFSET void IL offset: 0x14b N001 ( 2, 2) [000433] ------------ t433 = LCL_VAR int V03 arg3 u:1 (last use) $140 /--* t433 int N002 ( 3, 4) [000926] ------------ t926 = * CAST int <- ubyte <- int $1be N003 ( 1, 1) [000434] ------------ t434 = CNS_INT int 2 $c2 /--* t926 int +--* t434 int N004 ( 5, 6) [000435] N------N-U-- t435 = * EQ int $600 /--* t435 int N005 ( 7, 8) [000436] ------------ * JTRUE void ------------ BB31 [???..???) (return), preds={BB30,BB41} succs={} N001 ( 1, 1) [000437] ------------ t437 = CNS_INT int 0 $c0 /--* t437 int N002 ( 2, 2) [000811] ------------ * RETURN int $1f3 ------------ BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} N001 ( 0, 0) [001229] ------------ t1229 = PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [001218] ------------ t1218 = PHI_ARG int V07 loc3 u:1 $c0 /--* t1229 int +--* t1218 int N003 ( 0, 0) [001207] ------------ t1207 = * PHI int /--* t1207 int N005 ( 0, 0) [001208] DA---------- * STORE_LCL_VAR int V07 loc3 d:3 N001 ( 0, 0) [001230] ------------ t1230 = PHI_ARG int V09 loc5 u:3 N002 ( 0, 0) [001219] ------------ t1219 = PHI_ARG int V09 loc5 u:1 /--* t1230 int +--* t1219 int N003 ( 0, 0) [001204] ------------ t1204 = * PHI int /--* t1204 int N005 ( 0, 0) [001205] DA---------- * STORE_LCL_VAR int V09 loc5 d:2 [001377] ------------ IL_OFFSET void IL offset: 0x177 N001 ( 1, 1) [000063] ------------ t63 = LCL_VAR ref V04 loc0 u:1 [001447] ------------ t1447 = CNS_INT long 8 /--* t63 ref +--* t1447 long [001448] ------------ t1448 = * ADD ref /--* t1448 ref N002 ( 3, 3) [000064] ---X-------- t64 = * IND int /--* t64 int N004 ( 3, 3) [001323] DA-X-------- * STORE_LCL_VAR int V76 cse11 N005 ( 1, 1) [001324] ------------ t1324 = LCL_VAR int V76 cse11 N007 ( 1, 1) [000062] ------------ t62 = LCL_VAR int V09 loc5 u:2 $3c4 /--* t1324 int +--* t62 int N008 ( 6, 6) [000065] N--X---N-U-- t65 = * LE int /--* t65 int N009 ( 8, 8) [000066] ---X-------- * JTRUE void ------------ BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} [001378] ------------ IL_OFFSET void IL offset: 0x17e N001 ( 1, 1) [000949] ------------ t949 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000950] ------------ t950 = LCL_VAR int V09 loc5 u:2 $3c4 /--* t950 int N003 ( 2, 3) [000953] ------------ t953 = * CAST long <- int $6e1 N004 ( 1, 1) [000960] ------------ t960 = CNS_INT long 3 $24b /--* t953 long +--* t960 long N005 ( 7, 7) [000961] ------------ t961 = * MUL long $6e2 /--* t961 long N007 ( 7, 7) [001281] DA---------- * STORE_LCL_VAR long V71 cse6 d:1 N008 ( 1, 1) [001282] ------------ t1282 = LCL_VAR long V71 cse6 u:1 $6e2 N010 ( 1, 1) [000954] -------N---- t954 = CNS_INT long 3 $24b /--* t1282 long +--* t954 long N011 ( 9, 9) [000955] -------N---- t955 = * LSH long $6e3 N012 ( 1, 1) [000956] ------------ t956 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t955 long +--* t956 long N013 ( 10, 10) [000957] -------N---- t957 = * ADD long $6e4 /--* t949 ref +--* t957 long N014 ( 11, 11) [000958] -------N---- t958 = * ADD byref $91 /--* t958 byref N018 ( 23, 23) [001255] DA--G------- * STORE_LCL_VAR byref V66 cse1 d:1 N019 ( 1, 1) [001256] ------------ t1256 = LCL_VAR byref V66 cse1 u:1 N021 ( 1, 1) [000947] ------------ t947 = CNS_INT long 16 field offset Fseq[hashCode] $241 /--* t1256 byref +--* t947 long N022 ( 25, 25) [000948] ----G--N---- t948 = * ADD byref $2ac /--* t948 byref N023 ( 27, 27) [000212] *--XG------- t212 = * IND int N024 ( 1, 1) [000213] ------------ t213 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t212 int +--* t213 int N025 ( 29, 29) [000214] N--XG--N-U-- t214 = * NE int /--* t214 int N026 ( 31, 31) [000215] ---XG------- * JTRUE void ------------ BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} [001379] ------------ IL_OFFSET void IL offset: 0x18e N001 ( 1, 1) [000963] ------------ t963 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [001284] ------------ t1284 = LCL_VAR long V71 cse6 u:1 $6e2 N003 ( 1, 1) [000968] -------N---- t968 = CNS_INT long 3 $24b /--* t1284 long +--* t968 long N004 ( 2, 2) [000969] -------N---- t969 = * LSH long $6e3 N005 ( 1, 1) [000970] ------------ t970 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t969 long +--* t970 long N006 ( 3, 3) [000971] -------N---- t971 = * ADD long $6e4 /--* t963 ref +--* t971 long N007 ( 4, 4) [000972] -------N---- t972 = * ADD byref $91 /--* t972 byref N010 ( 12, 11) [000977] *---G--N---- t977 = * IND ref /--* t977 ref N012 ( 12, 11) [000246] DA--G------- * STORE_LCL_VAR ref V17 tmp3 d:1 [001380] ------------ IL_OFFSET void IL offset: 0x18e N001 ( 1, 1) [000241] !----------- t241 = LCL_VAR ref V00 this u:1 $100 /--* t241 ref N002 ( 3, 2) [000242] #----O------ t242 = * IND long $2e8 /--* t242 long N004 ( 3, 3) [000244] DA---O------ * STORE_LCL_VAR long V16 tmp2 d:1 N001 ( 1, 1) [000249] ------------ t249 = LCL_VAR long V16 tmp2 u:1 $2e7 N002 ( 1, 1) [000250] ------------ t250 = CNS_INT long 56 $244 /--* t249 long +--* t250 long N003 ( 2, 2) [000251] -------N---- t251 = * ADD long $306 /--* t251 long N004 ( 4, 4) [000252] #----------- t252 = * IND long $2e9 /--* t252 long N005 ( 7, 6) [000253] #----------- t253 = * IND long $2ea N006 ( 1, 1) [000254] ------------ t254 = CNS_INT long 48 $246 /--* t253 long +--* t254 long N007 ( 8, 7) [000255] -------N---- t255 = * ADD long $6e6 /--* t255 long N008 ( 10, 9) [000259] n----------- t259 = * IND long /--* t259 long N010 ( 10, 9) [001261] DA---------- * STORE_LCL_VAR long V67 cse2 d:1 N011 ( 1, 1) [001262] ------------ t1262 = LCL_VAR long V67 cse2 u:1 N013 ( 1, 1) [000262] ------------ t262 = CNS_INT long 0 $243 /--* t1262 long +--* t262 long N014 ( 13, 12) [000263] J------N---- t263 = * EQ int /--* t263 int N015 ( 15, 14) [001163] ------------ * JTRUE void ------------ BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} N001 ( 1, 1) [001264] ------------ t1264 = LCL_VAR long V67 cse2 u:1 /--* t1264 long N003 ( 1, 3) [001165] DA---------- * STORE_LCL_VAR long V19 tmp5 d:3 ------------ BB36 [???..???), preds={BB34} succs={BB37} N003 ( 1, 1) [000248] ------?----- t248 = LCL_VAR long V16 tmp2 u:1 (last use) $2e7 N004 ( 2, 10) [000260] H-----?----- t260 = CNS_INT(h) long 0xd1ffab1e global ptr $63 /--* t248 long arg0 in rcx +--* t260 long arg1 in rdx N005 ( 17, 18) [000261] --C-G-?----- t261 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $6e7 /--* t261 long N007 ( 17, 18) [001167] DA--G------- * STORE_LCL_VAR long V19 tmp5 d:2 ------------ BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} N001 ( 0, 0) [001234] ------------ t1234 = PHI_ARG long V19 tmp5 u:3 N002 ( 0, 0) [001233] ------------ t1233 = PHI_ARG long V19 tmp5 u:2 $6e7 /--* t1234 long +--* t1233 long N003 ( 0, 0) [001210] ------------ t1210 = * PHI long /--* t1210 long N005 ( 0, 0) [001211] DA---------- * STORE_LCL_VAR long V19 tmp5 d:1 N005 ( 1, 1) [000234] ------------ t234 = LCL_VAR ref V05 loc1 u:1 N006 ( 1, 1) [000980] ------------ t980 = LCL_VAR long V19 tmp5 u:1 r11 REG r11 $349 N007 ( 1, 1) [000247] ------------ t247 = LCL_VAR ref V17 tmp3 u:1 (last use) N008 ( 1, 1) [000258] ------------ t258 = LCL_VAR ref V01 arg1 u:1 $101 N009 ( 1, 1) [000279] ------------ t279 = LCL_VAR long V19 tmp5 u:1 (last use) $349 /--* t234 ref this in rcx +--* t980 long arg1 in r11 +--* t247 ref arg2 in rdx +--* t258 ref arg3 in r8 +--* t279 long calli tgt N010 ( 28, 14) [000280] --CXG------- t280 = * CALL ind stub int $1ef N011 ( 1, 1) [000281] ------------ t281 = CNS_INT int 0 $c0 /--* t280 int +--* t281 int N012 ( 30, 16) [000282] J--XG--N---- t282 = * EQ int $817 /--* t282 int N013 ( 32, 18) [000283] ---XG------- * JTRUE void ------------ BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} [001381] ------------ IL_OFFSET void IL offset: 0x1a4 N001 ( 2, 2) [000284] ------------ t284 = LCL_VAR int V03 arg3 u:1 $140 /--* t284 int N002 ( 3, 4) [000985] ------------ t985 = * CAST int <- ubyte <- int $1be N003 ( 1, 1) [000285] ------------ t285 = CNS_INT int 1 $c1 /--* t985 int +--* t285 int N004 ( 5, 6) [000286] N------N-U-- t286 = * NE int $1bf /--* t286 int N005 ( 7, 8) [000287] ------------ * JTRUE void ------------ BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} [001382] ------------ IL_OFFSET void IL offset: 0x1a8 N001 ( 1, 1) [001258] ------------ t1258 = LCL_VAR byref V66 cse1 u:1 $91 N002 ( 1, 1) [000986] ------------ t986 = CNS_INT long 8 field offset Fseq[value] $240 /--* t1258 byref +--* t986 long N003 ( 2, 2) [000987] ----G--N---- t987 = * ADD byref $2ae N005 ( 1, 1) [000334] ------------ t334 = LCL_VAR ref V02 arg2 u:1 (last use) $102 /--* t987 byref +--* t334 ref [001383] -A-XG------- * STOREIND ref ------------ BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} [001384] ------------ IL_OFFSET void IL offset: 0x1b8 N001 ( 2, 2) [000288] ------------ t288 = LCL_VAR int V03 arg3 u:1 (last use) $140 /--* t288 int N002 ( 3, 4) [001002] ------------ t1002 = * CAST int <- ubyte <- int $1be N003 ( 1, 1) [000289] ------------ t289 = CNS_INT int 2 $c2 /--* t1002 int +--* t289 int N004 ( 5, 6) [000290] N------N-U-- t290 = * EQ int $600 /--* t290 int N005 ( 7, 8) [000291] ------------ * JTRUE void ------------ BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} ------------ BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} [001385] ------------ IL_OFFSET void IL offset: 0x1c4 N001 ( 1, 1) [001259] ------------ t1259 = LCL_VAR byref V66 cse1 u:1 $91 N002 ( 1, 1) [001008] ------------ t1008 = CNS_INT long 20 field offset Fseq[next] $24c /--* t1259 byref +--* t1008 long N003 ( 2, 2) [001009] ----G--N---- t1009 = * ADD byref $2ad /--* t1009 byref N004 ( 4, 4) [000220] *--XG------- t220 = * IND int /--* t220 int N006 ( 4, 4) [000222] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:3 [001386] ------------ IL_OFFSET void IL offset: 0x1d3 N001 ( 1, 1) [000223] ------------ t223 = LCL_VAR int V07 loc3 u:3 (last use) $3c3 N002 ( 1, 1) [000224] ------------ t224 = CNS_INT int 1 $c1 /--* t223 int +--* t224 int N003 ( 3, 3) [000225] ------------ t225 = * ADD int $81a /--* t225 int N005 ( 3, 3) [000227] DA---------- * STORE_LCL_VAR int V07 loc3 d:4 [001387] ------------ IL_OFFSET void IL offset: 0x1d7 N001 ( 1, 1) [001328] ------------ t1328 = LCL_VAR int V76 cse11 N002 ( 1, 1) [000228] ------------ t228 = LCL_VAR int V07 loc3 u:4 $81a /--* t1328 int +--* t228 int N003 ( 3, 3) [000231] N------N-U-- t231 = * LT int /--* t231 int N004 ( 5, 5) [000232] ------------ * JTRUE void ------------ BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} ------------ BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} N001 ( 0, 0) [001237] ------------ t1237 = PHI_ARG int V07 loc3 u:5 $3c1 N002 ( 0, 0) [001228] ------------ t1228 = PHI_ARG int V07 loc3 u:3 $3c3 /--* t1237 int +--* t1228 int N003 ( 0, 0) [001180] ------------ t1180 = * PHI int /--* t1180 int N005 ( 0, 0) [001181] DA---------- * STORE_LCL_VAR int V07 loc3 d:2 [001388] ------------ IL_OFFSET void IL offset: 0x1e4 N001 ( 1, 1) [000067] ------------ t67 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001024] ------------ t1024 = CNS_INT long 64 field offset Fseq[_freeCount] $245 /--* t67 ref +--* t1024 long N003 ( 2, 2) [001025] -------N---- t1025 = * ADD byref $28f /--* t1025 byref N004 ( 4, 4) [000068] n---GO------ t68 = * IND int N005 ( 1, 1) [000069] ------------ t69 = CNS_INT int 0 $c0 /--* t68 int +--* t69 int N006 ( 6, 6) [000070] J---GO-N---- t70 = * LE int /--* t70 int N007 ( 8, 8) [000071] ----GO------ * JTRUE void ------------ BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} [001389] ------------ IL_OFFSET void IL offset: 0x1ed N001 ( 1, 1) [000171] ------------ t171 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001026] ------------ t1026 = CNS_INT long 60 field offset Fseq[_freeList] $24d /--* t171 ref +--* t1026 long N003 ( 2, 2) [001027] -------N---- t1027 = * ADD byref $295 /--* t1027 byref N004 ( 4, 4) [000172] n---GO------ t172 = * IND int /--* t172 int N006 ( 8, 7) [001306] DA--GO------ * STORE_LCL_VAR int V74 cse9 d:1 N007 ( 3, 2) [001307] ------------ t1307 = LCL_VAR int V74 cse9 u:1 /--* t1307 int N010 ( 15, 12) [000174] DA--GO------ * STORE_LCL_VAR int V10 loc6 d:3 [001390] ------------ IL_OFFSET void IL offset: 0x1f5 N001 ( 3, 2) [001309] ------------ t1309 = LCL_VAR int V74 cse9 u:1 /--* t1309 int N003 ( 3, 3) [001032] DA--G------- * STORE_LCL_VAR int V62 tmp48 d:1 N004 ( 1, 1) [001033] ------------ t1033 = LCL_VAR int V62 tmp48 u:1 N005 ( 1, 1) [001329] ------------ t1329 = LCL_VAR int V76 cse11 /--* t1033 int +--* t1329 int N006 ( 6, 9) [001036] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void N007 ( 1, 1) [001030] ------------ t1030 = LCL_VAR ref V04 loc0 u:1 N008 ( 1, 1) [001034] ------------ t1034 = LCL_VAR int V62 tmp48 u:1 (last use) /--* t1034 int N009 ( 2, 3) [001037] ------------ t1037 = * CAST long <- int N010 ( 1, 1) [001047] ------------ t1047 = CNS_INT long 3 $24b /--* t1037 long +--* t1047 long N011 ( 7, 7) [001048] ------------ t1048 = * MUL long N012 ( 1, 1) [001038] -------N---- t1038 = CNS_INT long 3 $24b /--* t1048 long +--* t1038 long N013 ( 8, 8) [001039] -------N---- t1039 = * LSH long N014 ( 1, 1) [001040] ------------ t1040 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t1039 long +--* t1040 long N015 ( 9, 9) [001041] -------N---- t1041 = * ADD long /--* t1030 ref +--* t1041 long N016 ( 10, 10) [001042] -------N---- t1042 = * ADD byref $88 N021 ( 1, 1) [001028] ------------ t1028 = CNS_INT long 20 field offset Fseq[next] $24c /--* t1042 byref +--* t1028 long N022 ( 31, 34) [001029] ---XG--N---- t1029 = * ADD byref $29c /--* t1029 byref N023 ( 33, 36) [000181] *--XG------- t181 = * IND int /--* t181 int N024 ( 34, 37) [001050] ---XG------- t1050 = * NEG int N025 ( 1, 1) [000175] ------------ t175 = CNS_INT int -3 $e1 /--* t1050 int +--* t175 int N026 ( 36, 39) [000182] ---XG------- t182 = * ADD int N027 ( 1, 1) [000183] ------------ t183 = CNS_INT int -1 $c4 /--* t182 int +--* t183 int N028 ( 41, 41) [000184] ---XG------- t184 = * GE int /--* t184 int N030 ( 45, 44) [000688] DA-XG------- * STORE_LCL_VAR int V49 tmp35 d:1 [001391] ------------ IL_OFFSET void IL offset: 0x1f5 N001 ( 1, 1) [001300] ------------ t1300 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1300 ref N003 ( 5, 4) [000698] DA--G------- * STORE_LCL_VAR ref V50 tmp36 d:1 [001392] ------------ IL_OFFSET void IL offset: 0x1f5 N001 ( 3, 2) [000690] ------------ t690 = LCL_VAR int V49 tmp35 u:1 (last use) N002 ( 1, 1) [000691] ------------ t691 = CNS_INT int 0 $c0 /--* t690 int +--* t691 int N003 ( 5, 4) [000692] J------N---- t692 = * NE int /--* t692 int N004 ( 7, 6) [000693] ------------ * JTRUE void ------------ BB46 [1F5..1F6), preds={BB45} succs={BB47} [001393] ------------ IL_OFFSET void IL offset: 0x1f5 N003 ( 2, 10) [001051] H----------- t1051 = CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" $5e /--* t1051 long N004 ( 4, 12) [001052] #---G------- t1052 = * IND ref $114 N005 ( 3, 2) [000695] ------------ t695 = LCL_VAR ref V50 tmp36 u:1 (last use) $105 /--* t1052 ref arg0 in rcx +--* t695 ref arg1 in rdx N006 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} [001394] ------------ IL_OFFSET void IL offset: 0x219 N001 ( 1, 1) [000190] ------------ t190 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001055] ------------ t1055 = CNS_INT long 60 field offset Fseq[_freeList] $24d /--* t190 ref +--* t1055 long N003 ( 2, 2) [001056] -------N---- t1056 = * ADD byref $295 N005 ( 1, 1) [000193] ------------ t193 = LCL_VAR ref V00 this u:1 $100 N006 ( 1, 1) [001074] ------------ t1074 = CNS_INT long 60 field offset Fseq[_freeList] $24d /--* t193 ref +--* t1074 long N007 ( 2, 2) [001075] -------N---- t1075 = * ADD byref $295 /--* t1075 byref N008 ( 4, 4) [000194] n---GO------ t194 = * IND int /--* t194 int N010 ( 4, 4) [001061] DA--GO------ * STORE_LCL_VAR int V63 tmp49 d:1 N011 ( 1, 1) [001062] ------------ t1062 = LCL_VAR int V63 tmp49 u:1 N012 ( 1, 1) [001330] ------------ t1330 = LCL_VAR int V76 cse11 /--* t1062 int +--* t1330 int N013 ( 6, 9) [001065] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void N014 ( 1, 1) [001059] ------------ t1059 = LCL_VAR ref V04 loc0 u:1 N015 ( 1, 1) [001063] ------------ t1063 = LCL_VAR int V63 tmp49 u:1 (last use) /--* t1063 int N016 ( 2, 3) [001066] ------------ t1066 = * CAST long <- int N017 ( 1, 1) [001076] ------------ t1076 = CNS_INT long 3 $24b /--* t1066 long +--* t1076 long N018 ( 7, 7) [001077] ------------ t1077 = * MUL long N019 ( 1, 1) [001067] -------N---- t1067 = CNS_INT long 3 $24b /--* t1077 long +--* t1067 long N020 ( 8, 8) [001068] -------N---- t1068 = * LSH long N021 ( 1, 1) [001069] ------------ t1069 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t1068 long +--* t1069 long N022 ( 9, 9) [001070] -------N---- t1070 = * ADD long /--* t1059 ref +--* t1070 long N023 ( 10, 10) [001071] -------N---- t1071 = * ADD byref $8a N028 ( 1, 1) [001057] ------------ t1057 = CNS_INT long 20 field offset Fseq[next] $24c /--* t1071 byref +--* t1057 long N029 ( 32, 35) [001058] ---XGO-N---- t1058 = * ADD byref $2a3 /--* t1058 byref N030 ( 34, 37) [000197] *--XGO------ t197 = * IND int /--* t197 int N031 ( 35, 38) [001079] ---XGO------ t1079 = * NEG int N032 ( 1, 1) [000191] ------------ t191 = CNS_INT int -3 $e1 /--* t1079 int +--* t191 int N033 ( 37, 40) [000198] ---XGO------ t198 = * ADD int /--* t1056 byref +--* t198 int [001395] -A-XGO------ * STOREIND int [001396] ------------ IL_OFFSET void IL offset: 0x233 N001 ( 1, 1) [000202] ------------ t202 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001082] ------------ t1082 = CNS_INT long 64 field offset Fseq[_freeCount] $245 /--* t202 ref +--* t1082 long N003 ( 2, 2) [001083] -------N---- t1083 = * ADD byref $28f /--* t1083 byref N004 ( 4, 4) [000203] n---GO------ t203 = * IND int N005 ( 1, 1) [000204] ------------ t204 = CNS_INT int -1 $c4 /--* t203 int +--* t204 int N006 ( 6, 6) [000205] ----GO------ t205 = * ADD int N007 ( 1, 1) [000201] ------------ t201 = LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001080] ------------ t1080 = CNS_INT long 64 field offset Fseq[_freeCount] $245 /--* t201 ref +--* t1080 long N009 ( 2, 2) [001081] -------N---- t1081 = * ADD byref $28f /--* t1081 byref +--* t205 int [001397] -A--GO------ * STOREIND int ------------ BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} [001398] ------------ IL_OFFSET void IL offset: 0x243 N001 ( 1, 1) [000072] ------------ t72 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001084] ------------ t1084 = CNS_INT long 56 field offset Fseq[_count] $244 /--* t72 ref +--* t1084 long N003 ( 2, 2) [001085] -------N---- t1085 = * ADD byref $290 /--* t1085 byref N004 ( 4, 4) [000073] n---GO------ t73 = * IND int /--* t73 int N006 ( 8, 7) [001311] DA--GO------ * STORE_LCL_VAR int V75 cse10 d:1 N007 ( 3, 2) [001312] ------------ t1312 = LCL_VAR int V75 cse10 u:1 /--* t1312 int N010 ( 15, 12) [000075] DA--GO------ * STORE_LCL_VAR int V13 loc9 d:1 [001399] ------------ IL_OFFSET void IL offset: 0x24b N001 ( 1, 1) [001331] ------------ t1331 = LCL_VAR int V76 cse11 N002 ( 3, 2) [000076] ------------ t76 = LCL_VAR int V13 loc9 u:1 /--* t1331 int +--* t76 int N003 ( 5, 4) [000079] N------N-U-- t79 = * NE int /--* t79 int N004 ( 7, 6) [000080] ------------ * JTRUE void ------------ BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} [001400] ------------ IL_OFFSET void IL offset: 0x252 N003 ( 3, 2) [001314] ------------ t1314 = LCL_VAR int V75 cse10 u:1 /--* t1314 int arg0 in rcx N004 ( 17, 8) [000702] --CXG------- t702 = * CALL int System.Collections.HashHelpers.ExpandPrime $1d7 /--* t702 int N006 ( 21, 11) [001090] DA-XG-----L- * STORE_LCL_VAR int V64 tmp50 d:1 N008 ( 3, 2) [001091] ------------ t1091 = LCL_VAR int V64 tmp50 u:1 (last use) $1d7 N009 ( 1, 1) [000163] ------------ t163 = LCL_VAR ref V00 this u:1 $100 N010 ( 1, 1) [000704] ------------ t704 = CNS_INT int 0 $c0 /--* t1091 int arg1 in rdx +--* t163 ref this in rcx +--* t704 int arg2 in r8 N011 ( 43, 24) [000705] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void [001401] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [000165] ------------ t165 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001094] ------------ t1094 = CNS_INT long 8 field offset Fseq[_buckets] $240 /--* t165 ref +--* t1094 long N003 ( 2, 2) [001095] -------N---- t1095 = * ADD byref $280 /--* t1095 byref N004 ( 4, 4) [000709] n---GO------ t709 = * IND ref /--* t709 ref N006 ( 8, 7) [000711] DA--GO------ * STORE_LCL_VAR ref V52 tmp38 d:1 [001402] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000713] ------------ t713 = LCL_VAR ref V52 tmp38 u:1 [001449] ------------ t1449 = CNS_INT long 8 /--* t713 ref +--* t1449 long [001450] ------------ t1450 = * ADD ref /--* t1450 ref N002 ( 5, 4) [000714] ---X-------- t714 = * IND int /--* t714 int N004 ( 9, 7) [001286] DA-X-------- * STORE_LCL_VAR int V72 cse7 d:1 N005 ( 3, 2) [001287] ------------ t1287 = LCL_VAR int V72 cse7 u:1 /--* t1287 int N008 ( 12, 9) [000760] DA-X-------- * STORE_LCL_VAR int V53 tmp39 d:1 [001403] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [000715] ------------ t715 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001096] ------------ t1096 = CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 /--* t715 ref +--* t1096 long N003 ( 2, 2) [001097] -------N---- t1097 = * ADD byref $283 /--* t1097 byref N004 ( 4, 4) [000716] n---GO------ t716 = * IND long /--* t716 long N006 ( 8, 7) [000762] DA--GO------ * STORE_LCL_VAR long V54 tmp40 d:1 [001404] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [000728] ------------ t728 = LCL_VAR int V53 tmp39 u:1 N002 ( 1, 4) [000729] ------------ t729 = CNS_INT int 0x7FFFFFFF $ce /--* t728 int +--* t729 int N003 ( 6, 6) [000730] N--------U-- t730 = * LE int /--* t730 int N005 ( 10, 9) [000773] DA---------- * STORE_LCL_VAR int V56 tmp42 d:1 [001405] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [001301] ------------ t1301 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1301 ref N003 ( 5, 4) [000783] DA--G------- * STORE_LCL_VAR ref V57 tmp43 d:1 [001406] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [001302] ------------ t1302 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1302 ref N003 ( 5, 4) [000785] DA--G------- * STORE_LCL_VAR ref V58 tmp44 d:1 [001407] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000775] ------------ t775 = LCL_VAR int V56 tmp42 u:1 (last use) N002 ( 1, 1) [000776] ------------ t776 = CNS_INT int 0 $c0 /--* t775 int +--* t776 int N003 ( 5, 4) [000777] J------N---- t777 = * NE int /--* t777 int N004 ( 7, 6) [000778] ------------ * JTRUE void ------------ BB50 [258..259), preds={BB49} succs={BB51} [001408] ------------ IL_OFFSET void IL offset: 0x258 N003 ( 3, 2) [000779] ------------ t779 = LCL_VAR ref V58 tmp44 u:1 (last use) $105 N004 ( 3, 2) [000780] ------------ t780 = LCL_VAR ref V58 tmp44 u:1 (last use) $105 /--* t779 ref arg0 in rcx +--* t780 ref arg1 in rdx N005 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} [001409] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000735] ------------ t735 = LCL_VAR long V54 tmp40 u:1 (last use) N002 ( 1, 1) [000166] ------------ t166 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t166 int N003 ( 2, 3) [000736] ---------U-- t736 = * CAST long <- ulong <- uint $310 /--* t735 long +--* t736 long N004 ( 9, 8) [000737] ------------ t737 = * MUL long N005 ( 1, 1) [000738] ------------ t738 = CNS_INT int 32 $d2 /--* t737 long +--* t738 int N006 ( 11, 10) [000739] ------------ t739 = * RSZ long N007 ( 1, 1) [000741] ------------ t741 = CNS_INT long 1 $247 /--* t739 long +--* t741 long N008 ( 13, 12) [000742] ------------ t742 = * ADD long N009 ( 1, 1) [000743] ------------ t743 = LCL_VAR int V53 tmp39 u:1 /--* t743 int N010 ( 2, 3) [000744] ---------U-- t744 = * CAST long <- ulong <- uint /--* t742 long +--* t744 long N011 ( 19, 18) [000745] ------------ t745 = * MUL long N012 ( 1, 1) [000746] ------------ t746 = CNS_INT int 32 $d2 /--* t745 long +--* t746 int N013 ( 21, 20) [000747] ------------ t747 = * RSZ long /--* t747 long N014 ( 22, 22) [000748] ------------ t748 = * CAST int <- uint <- long /--* t748 int N016 ( 26, 25) [000750] DA---------- * STORE_LCL_VAR int V55 tmp41 d:1 [001410] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [000752] ------------ t752 = LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000753] ------------ t753 = LCL_VAR int V53 tmp39 u:1 (last use) /--* t752 int +--* t753 int N003 ( 22, 5) [000754] ---X-------- t754 = * UMOD int N004 ( 3, 2) [000751] ------------ t751 = LCL_VAR int V55 tmp41 u:1 /--* t754 int +--* t751 int N005 ( 29, 8) [000755] ---X-------- t755 = * EQ int /--* t755 int N007 ( 33, 11) [000796] DA-X-------- * STORE_LCL_VAR int V59 tmp45 d:1 [001411] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [001303] ------------ t1303 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1303 ref N003 ( 5, 4) [000806] DA--G------- * STORE_LCL_VAR ref V60 tmp46 d:1 [001412] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [001304] ------------ t1304 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1304 ref N003 ( 5, 4) [000808] DA--G------- * STORE_LCL_VAR ref V61 tmp47 d:1 [001413] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000798] ------------ t798 = LCL_VAR int V59 tmp45 u:1 (last use) N002 ( 1, 1) [000799] ------------ t799 = CNS_INT int 0 $c0 /--* t798 int +--* t799 int N003 ( 5, 4) [000800] J------N---- t800 = * NE int /--* t800 int N004 ( 7, 6) [000801] ------------ * JTRUE void ------------ BB52 [258..259), preds={BB51} succs={BB53} [001414] ------------ IL_OFFSET void IL offset: 0x258 N003 ( 3, 2) [000802] ------------ t802 = LCL_VAR ref V61 tmp47 u:1 (last use) $105 N004 ( 3, 2) [000803] ------------ t803 = LCL_VAR ref V61 tmp47 u:1 (last use) $105 /--* t802 ref arg0 in rcx +--* t803 ref arg1 in rdx N005 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB53 [258..259), preds={BB51,BB52} succs={BB54} [001415] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000758] ------------ t758 = LCL_VAR int V55 tmp41 u:1 N002 ( 3, 2) [001289] ------------ t1289 = LCL_VAR int V72 cse7 u:1 /--* t758 int +--* t1289 int N003 ( 10, 11) [001105] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void N004 ( 3, 2) [001102] ------------ t1102 = LCL_VAR ref V52 tmp38 u:1 (last use) N005 ( 3, 2) [001103] ------------ t1103 = LCL_VAR int V55 tmp41 u:1 (last use) /--* t1103 int N006 ( 4, 4) [001106] ------------ t1106 = * CAST long <- int N007 ( 1, 1) [001107] -------N---- t1107 = CNS_INT long 2 $248 /--* t1106 long +--* t1107 long N008 ( 5, 5) [001108] -------N---- t1108 = * LSH long N009 ( 1, 1) [001109] ------------ t1109 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t1108 long +--* t1109 long N010 ( 6, 6) [001110] -------N---- t1110 = * ADD long /--* t1102 ref +--* t1110 long N011 ( 9, 8) [001111] -------N---- t1111 = * ADD byref $87 /--* t1111 byref N016 ( 33, 31) [000722] DA-XG------- * STORE_LCL_VAR byref V51 tmp37 d:1 N001 ( 3, 2) [000723] ------------ t723 = LCL_VAR byref V51 tmp37 u:1 (last use) $87 /--* t723 byref N003 ( 7, 5) [000170] DA---------- * STORE_LCL_VAR byref V08 loc4 d:4 ------------ BB54 [261..276), preds={BB48,BB53} succs={BB55} N001 ( 0, 0) [001224] ------------ t1224 = PHI_ARG byref V08 loc4 u:4 $87 N002 ( 0, 0) [001220] ------------ t1220 = PHI_ARG byref V08 loc4 u:1 $81 /--* t1224 byref +--* t1220 byref N003 ( 0, 0) [001192] ------------ t1192 = * PHI byref /--* t1192 byref N005 ( 0, 0) [001193] DA---------- * STORE_LCL_VAR byref V08 loc4 d:3 [001416] ------------ IL_OFFSET void IL offset: 0x261 N001 ( 3, 2) [000081] ------------ t81 = LCL_VAR int V13 loc9 u:1 /--* t81 int N003 ( 7, 5) [000083] DA---------- * STORE_LCL_VAR int V10 loc6 d:2 [001417] ------------ IL_OFFSET void IL offset: 0x265 N001 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V10 loc6 u:2 (last use) N002 ( 1, 1) [000086] ------------ t86 = CNS_INT int 1 $c1 /--* t85 int +--* t86 int N003 ( 5, 4) [000087] ------------ t87 = * ADD int N004 ( 1, 1) [000084] ------------ t84 = LCL_VAR ref V00 this u:1 $100 N005 ( 1, 1) [001114] ------------ t1114 = CNS_INT long 56 field offset Fseq[_count] $244 /--* t84 ref +--* t1114 long N006 ( 2, 2) [001115] -------N---- t1115 = * ADD byref $290 /--* t1115 byref +--* t87 int [001418] -A--GO------ * STOREIND int [001419] ------------ IL_OFFSET void IL offset: 0x26f N001 ( 1, 1) [000090] ------------ t90 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001116] ------------ t1116 = CNS_INT long 16 field offset Fseq[_entries] $241 /--* t90 ref +--* t1116 long N003 ( 2, 2) [001117] -------N---- t1117 = * ADD byref $281 /--* t1117 byref N004 ( 4, 4) [000091] n---GO------ t91 = * IND ref /--* t91 ref N006 ( 4, 4) [000093] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:3 ------------ BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} N001 ( 0, 0) [001225] ------------ t1225 = PHI_ARG byref V08 loc4 u:1 $81 N002 ( 0, 0) [001221] ------------ t1221 = PHI_ARG byref V08 loc4 u:3 $780 /--* t1225 byref +--* t1221 byref N003 ( 0, 0) [001195] ------------ t1195 = * PHI byref /--* t1195 byref N005 ( 0, 0) [001196] DA---------- * STORE_LCL_VAR byref V08 loc4 d:2 N001 ( 0, 0) [001226] ------------ t1226 = PHI_ARG ref V04 loc0 u:1 N002 ( 0, 0) [001222] ------------ t1222 = PHI_ARG ref V04 loc0 u:3 /--* t1226 ref +--* t1222 ref N003 ( 0, 0) [001189] ------------ t1189 = * PHI ref /--* t1189 ref N005 ( 0, 0) [001190] DA---------- * STORE_LCL_VAR ref V04 loc0 d:2 N001 ( 0, 0) [001227] ------------ t1227 = PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [001223] ------------ t1223 = PHI_ARG int V10 loc6 u:2 /--* t1227 int +--* t1223 int N003 ( 0, 0) [001186] ------------ t1186 = * PHI int /--* t1186 int N005 ( 0, 0) [001187] DA---------- * STORE_LCL_VAR int V10 loc6 d:1 [001420] ------------ IL_OFFSET void IL offset: 0x276 N001 ( 3, 2) [000095] ------------ t95 = LCL_VAR int V10 loc6 u:1 $3cc N002 ( 1, 1) [000094] ------------ t94 = LCL_VAR ref V04 loc0 u:2 $684 [001451] ------------ t1451 = CNS_INT long 8 /--* t94 ref +--* t1451 long [001452] ------------ t1452 = * ADD ref /--* t1452 ref N003 ( 3, 3) [001120] ---X-------- t1120 = * IND int $73d /--* t95 int +--* t1120 int N004 ( 10, 12) [001121] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void $7cd N005 ( 1, 1) [001118] ------------ t1118 = LCL_VAR ref V04 loc0 u:2 $684 N006 ( 3, 2) [001119] ------------ t1119 = LCL_VAR int V10 loc6 u:1 $3cc /--* t1119 int N007 ( 4, 4) [001122] ------------ t1122 = * CAST long <- int $6dc N008 ( 1, 1) [001129] ------------ t1129 = CNS_INT long 3 $24b /--* t1122 long +--* t1129 long N009 ( 9, 8) [001130] ------------ t1130 = * MUL long $6dd N010 ( 1, 1) [001123] -------N---- t1123 = CNS_INT long 3 $24b /--* t1130 long +--* t1123 long N011 ( 10, 9) [001124] -------N---- t1124 = * LSH long $6de N012 ( 1, 1) [001125] ------------ t1125 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t1124 long +--* t1125 long N013 ( 11, 10) [001126] -------N---- t1126 = * ADD long $6df /--* t1118 ref +--* t1126 long N014 ( 12, 11) [001127] -------N---- t1127 = * ADD byref $8c /--* t1127 byref N019 ( 39, 38) [000099] DA-XG------- * STORE_LCL_VAR byref V11 loc7 d:1 [001421] ------------ IL_OFFSET void IL offset: 0x280 N001 ( 3, 2) [000100] ------------ t100 = LCL_VAR byref V11 loc7 u:1 $8c N002 ( 1, 1) [001132] ------------ t1132 = CNS_INT long 16 field offset Fseq[hashCode] $241 /--* t100 byref +--* t1132 long N003 ( 4, 3) [001133] -------N---- t1133 = * ADD byref $8d N005 ( 1, 1) [000101] ------------ t101 = LCL_VAR int V06 loc2 u:1 (last use) $3c0 /--* t1133 byref +--* t101 int [001422] -A-XG------- * STOREIND int [001423] ------------ IL_OFFSET void IL offset: 0x288 N001 ( 3, 2) [000105] ------------ t105 = LCL_VAR byref V08 loc4 u:2 $781 /--* t105 byref N002 ( 6, 4) [000106] *--XG------- t106 = * IND int N003 ( 1, 1) [000107] ------------ t107 = CNS_INT int -1 $c4 /--* t106 int +--* t107 int N004 ( 8, 6) [000108] ---XG------- t108 = * ADD int N005 ( 3, 2) [000104] ------------ t104 = LCL_VAR byref V11 loc7 u:1 $8c N006 ( 1, 1) [001134] ------------ t1134 = CNS_INT long 20 field offset Fseq[next] $24c /--* t104 byref +--* t1134 long N007 ( 4, 3) [001135] -------N---- t1135 = * ADD byref $8e /--* t1135 byref +--* t108 int [001424] -A-XGO------ * STOREIND int [001425] ------------ IL_OFFSET void IL offset: 0x294 N001 ( 3, 2) [000111] ------------ t111 = LCL_VAR byref V11 loc7 u:1 Zero Fseq[key] $8f N003 ( 1, 1) [000112] ------------ t112 = LCL_VAR ref V01 arg1 u:1 (last use) $101 /--* t111 byref +--* t112 ref [001426] -A-XG------- * STOREIND ref [001427] ------------ IL_OFFSET void IL offset: 0x29c N001 ( 3, 2) [000115] ------------ t115 = LCL_VAR byref V11 loc7 u:1 (last use) $8c N002 ( 1, 1) [001136] ------------ t1136 = CNS_INT long 8 field offset Fseq[value] $240 /--* t115 byref +--* t1136 long N003 ( 4, 3) [001137] -------N---- t1137 = * ADD byref $90 N005 ( 1, 1) [000116] ------------ t116 = LCL_VAR ref V02 arg2 u:1 (last use) $102 /--* t1137 byref +--* t116 ref [001428] -A--GO------ * STOREIND ref [001429] ------------ IL_OFFSET void IL offset: 0x2a4 N001 ( 3, 2) [000120] ------------ t120 = LCL_VAR int V10 loc6 u:1 (last use) $3cc N002 ( 1, 1) [000121] ------------ t121 = CNS_INT int 1 $c1 /--* t120 int +--* t121 int N003 ( 5, 4) [000122] ------------ t122 = * ADD int $804 N004 ( 3, 2) [000119] ------------ t119 = LCL_VAR byref V08 loc4 u:2 (last use) $781 /--* t119 byref +--* t122 int [001430] -A--GO------ * STOREIND int [001431] ------------ IL_OFFSET void IL offset: 0x2ab N001 ( 1, 1) [000126] ------------ t126 = LCL_VAR ref V00 this u:1 $100 N002 ( 1, 1) [001140] ------------ t1140 = CNS_INT long 68 field offset Fseq[_version] $24e /--* t126 ref +--* t1140 long N003 ( 2, 2) [001141] -------N---- t1141 = * ADD byref $2a7 /--* t1141 byref N004 ( 4, 4) [000127] n---GO------ t127 = * IND int N005 ( 1, 1) [000128] ------------ t128 = CNS_INT int 1 $c1 /--* t127 int +--* t128 int N006 ( 6, 6) [000129] ----GO------ t129 = * ADD int N007 ( 1, 1) [000125] ------------ t125 = LCL_VAR ref V00 this u:1 $100 N008 ( 1, 1) [001138] ------------ t1138 = CNS_INT long 68 field offset Fseq[_version] $24e /--* t125 ref +--* t1138 long N009 ( 2, 2) [001139] -------N---- t1139 = * ADD byref $2a7 /--* t1139 byref +--* t129 int [001432] -A--GO------ * STOREIND int [001433] ------------ IL_OFFSET void IL offset: 0x2ca N001 ( 1, 1) [000145] ------------ t145 = LCL_VAR int V07 loc3 u:2 (last use) $3c5 N002 ( 1, 1) [000146] ------------ t146 = CNS_INT int 100 $e3 /--* t145 int +--* t146 int N003 ( 3, 3) [000147] N------N-U-- t147 = * LE int $80d /--* t147 int N004 ( 5, 5) [000148] ------------ * JTRUE void ------------ BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} [001434] ------------ IL_OFFSET void IL offset: 0x2cf N003 ( 1, 1) [000151] ------------ t151 = LCL_VAR ref V05 loc1 u:1 (last use) N004 ( 2, 10) [000152] H------N---- t152 = CNS_INT(h) long 0xd1ffab1e class $62 /--* t151 ref arg1 in rdx +--* t152 long arg0 in rcx N005 ( 17, 18) [000153] --C-G------- t153 = * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS N006 ( 1, 1) [000154] ------------ t154 = CNS_INT ref null $VN.Null /--* t153 ref +--* t154 ref N007 ( 19, 20) [000155] J---G--N---- t155 = * EQ int /--* t155 int N008 ( 21, 22) [000156] ----G------- * JTRUE void ------------ BB57 [2D7..2E3), preds={BB56} succs={BB58} [001435] ------------ IL_OFFSET void IL offset: 0x2d7 N004 ( 1, 1) [000158] ------------ t158 = LCL_VAR ref V04 loc0 u:2 (last use) $684 [001453] ------------ t1453 = CNS_INT long 8 /--* t158 ref +--* t1453 long [001454] ------------ t1454 = * ADD ref /--* t1454 ref N005 ( 3, 3) [000159] ---X-------- t159 = * IND int $73d N006 ( 1, 1) [000157] ------------ t157 = LCL_VAR ref V00 this u:1 $100 N007 ( 1, 1) [000160] ------------ t160 = CNS_INT int 1 $c1 /--* t159 int arg1 in rdx +--* t157 ref this in rcx +--* t160 int arg2 in r8 N008 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void ------------ BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} N001 ( 1, 1) [000482] ------------ t482 = CNS_INT int 1 $c1 /--* t482 int N002 ( 2, 2) [000810] ------------ * RETURN int $1f4 ------------ BB59 [008..00E) (throw), preds={BB01} succs={} [001436] ------------ IL_OFFSET void IL offset: 0x8 N002 ( 1, 1) [000532] ------------ t532 = CNS_INT int 4 $c5 /--* t532 int arg0 in rcx N003 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException $VN.Void ------------ BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} [001437] ------------ IL_OFFSET void IL offset: 0x14f N001 ( 1, 1) [000441] !----------- t441 = LCL_VAR ref V00 this u:1 $100 /--* t441 ref N002 ( 3, 2) [000442] #----O------ t442 = * IND long $2e8 /--* t442 long N004 ( 7, 5) [000444] DA---O------ * STORE_LCL_VAR long V26 tmp12 d:1 N001 ( 3, 2) [000446] ------------ t446 = LCL_VAR long V26 tmp12 u:1 $2e7 N002 ( 1, 1) [000447] ------------ t447 = CNS_INT long 56 $244 /--* t446 long +--* t447 long N003 ( 4, 3) [000448] -------N---- t448 = * ADD long $306 /--* t448 long N004 ( 6, 5) [000449] #----------- t449 = * IND long $2e9 /--* t449 long N005 ( 9, 7) [000450] #----------- t450 = * IND long $2ea N006 ( 1, 1) [000451] ------------ t451 = CNS_INT long 56 $244 /--* t450 long +--* t451 long N007 ( 10, 8) [000452] -------N---- t452 = * ADD long $331 /--* t452 long N008 ( 12, 10) [000456] n----------- t456 = * IND long N009 ( 1, 1) [000459] ------------ t459 = CNS_INT long 0 $243 /--* t456 long +--* t459 long N010 ( 14, 12) [000460] J------N---- t460 = * EQ int /--* t460 int N011 ( 16, 14) [001158] ------------ * JTRUE void ------------ BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} N001 ( 3, 2) [000466] ------?----- t466 = LCL_VAR long V26 tmp12 u:1 (last use) $2e7 N002 ( 1, 1) [000467] ------?----- t467 = CNS_INT long 56 $244 /--* t466 long +--* t467 long N003 ( 4, 3) [000465] ------?N---- t465 = * ADD long $306 /--* t465 long N004 ( 6, 5) [000464] #-----?----- t464 = * IND long $2e9 /--* t464 long N005 ( 9, 7) [000463] #-----?----- t463 = * IND long $2ea N006 ( 1, 1) [000468] ------?----- t468 = CNS_INT long 56 $244 /--* t463 long +--* t468 long N007 ( 10, 8) [000462] ------?N---- t462 = * ADD long $331 /--* t462 long N008 ( 12, 10) [000461] n-----?----- t461 = * IND long /--* t461 long N010 ( 16, 13) [001160] DA---------- * STORE_LCL_VAR long V28 tmp14 d:3 ------------ BB62 [???..???), preds={BB60} succs={BB63} N003 ( 3, 2) [000445] ------?----- t445 = LCL_VAR long V26 tmp12 u:1 (last use) $2e7 N004 ( 2, 10) [000457] H-----?----- t457 = CNS_INT(h) long 0xd1ffab1e global ptr $52 /--* t445 long arg0 in rcx +--* t457 long arg1 in rdx N005 ( 19, 19) [000458] --C-G-?----- t458 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 /--* t458 long N007 ( 23, 22) [001162] DA--G------- * STORE_LCL_VAR long V28 tmp14 d:2 ------------ BB63 [???..157) (throw), preds={BB61,BB62} succs={} N001 ( 0, 0) [001241] ------------ t1241 = PHI_ARG long V28 tmp14 u:3 N002 ( 0, 0) [001240] ------------ t1240 = PHI_ARG long V28 tmp14 u:2 $332 /--* t1241 long +--* t1240 long N003 ( 0, 0) [001183] ------------ t1183 = * PHI long /--* t1183 long N005 ( 0, 0) [001184] DA---------- * STORE_LCL_VAR long V28 tmp14 d:1 N003 ( 3, 2) [000473] ------------ t473 = LCL_VAR long V28 tmp14 u:1 (last use) $347 N004 ( 1, 1) [000455] ------------ t455 = LCL_VAR ref V01 arg1 u:1 (last use) $101 /--* t473 long arg0 in rcx +--* t455 ref arg1 in rdx N005 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void ------------ BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} [001438] ------------ IL_OFFSET void IL offset: 0x1bc N001 ( 1, 1) [000296] !----------- t296 = LCL_VAR ref V00 this u:1 $100 /--* t296 ref N002 ( 3, 2) [000297] #----O------ t297 = * IND long $2e8 /--* t297 long N004 ( 7, 5) [000299] DA---O------ * STORE_LCL_VAR long V21 tmp7 d:1 N001 ( 3, 2) [000301] ------------ t301 = LCL_VAR long V21 tmp7 u:1 $2e7 N002 ( 1, 1) [000302] ------------ t302 = CNS_INT long 56 $244 /--* t301 long +--* t302 long N003 ( 4, 3) [000303] -------N---- t303 = * ADD long $306 /--* t303 long N004 ( 6, 5) [000304] #----------- t304 = * IND long $2e9 /--* t304 long N005 ( 9, 7) [000305] #----------- t305 = * IND long $2ea N006 ( 1, 1) [000306] ------------ t306 = CNS_INT long 56 $244 /--* t305 long +--* t306 long N007 ( 10, 8) [000307] -------N---- t307 = * ADD long $331 /--* t307 long N008 ( 12, 10) [000311] n----------- t311 = * IND long N009 ( 1, 1) [000314] ------------ t314 = CNS_INT long 0 $243 /--* t311 long +--* t314 long N010 ( 14, 12) [000315] J------N---- t315 = * EQ int /--* t315 int N011 ( 16, 14) [001168] ------------ * JTRUE void ------------ BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} N001 ( 3, 2) [000321] ------?----- t321 = LCL_VAR long V21 tmp7 u:1 (last use) $2e7 N002 ( 1, 1) [000322] ------?----- t322 = CNS_INT long 56 $244 /--* t321 long +--* t322 long N003 ( 4, 3) [000320] ------?N---- t320 = * ADD long $306 /--* t320 long N004 ( 6, 5) [000319] #-----?----- t319 = * IND long $2e9 /--* t319 long N005 ( 9, 7) [000318] #-----?----- t318 = * IND long $2ea N006 ( 1, 1) [000323] ------?----- t323 = CNS_INT long 56 $244 /--* t318 long +--* t323 long N007 ( 10, 8) [000317] ------?N---- t317 = * ADD long $331 /--* t317 long N008 ( 12, 10) [000316] n-----?----- t316 = * IND long /--* t316 long N010 ( 16, 13) [001170] DA---------- * STORE_LCL_VAR long V23 tmp9 d:3 ------------ BB66 [???..???), preds={BB64} succs={BB67} N003 ( 3, 2) [000300] ------?----- t300 = LCL_VAR long V21 tmp7 u:1 (last use) $2e7 N004 ( 2, 10) [000312] H-----?----- t312 = CNS_INT(h) long 0xd1ffab1e global ptr $52 /--* t300 long arg0 in rcx +--* t312 long arg1 in rdx N005 ( 19, 19) [000313] --C-G-?----- t313 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 /--* t313 long N007 ( 23, 22) [001172] DA--G------- * STORE_LCL_VAR long V23 tmp9 d:2 ------------ BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} N001 ( 0, 0) [001232] ------------ t1232 = PHI_ARG long V23 tmp9 u:3 N002 ( 0, 0) [001231] ------------ t1231 = PHI_ARG long V23 tmp9 u:2 $332 /--* t1232 long +--* t1231 long N003 ( 0, 0) [001201] ------------ t1201 = * PHI long /--* t1201 long N005 ( 0, 0) [001202] DA---------- * STORE_LCL_VAR long V23 tmp9 d:1 N003 ( 3, 2) [000328] ------------ t328 = LCL_VAR long V23 tmp9 u:1 (last use) $34b N004 ( 1, 1) [000310] ------------ t310 = LCL_VAR ref V01 arg1 u:1 (last use) $101 /--* t328 long arg0 in rcx +--* t310 ref arg1 in rdx N005 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void ------------ BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} [001439] ------------ IL_OFFSET void IL offset: 0x1dd N001 ( 14, 5) [000233] --CXG------- CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported $VN.Void ------------ BB69 [???..???) (throw), preds={} succs={} N001 ( 14, 5) [001444] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Lowering nodeinfo Addressing mode: Base N001 ( 1, 1) [000004] ------------ * LCL_VAR ref V00 this u:1 $100 + 8 Removing unused node: N002 ( 1, 1) [000813] -c---------- * CNS_INT long 8 field offset Fseq[_buckets] $240 New addressing mode node: N003 ( 2, 2) [000814] ------------ * LEA(b+8) byref lowering call (before): N003 ( 1, 1) [000526] ------------ t526 = LCL_VAR ref V00 this u:1 $100 N004 ( 1, 1) [000527] ------------ t527 = CNS_INT int 0 $c0 /--* t526 ref this in rcx +--* t527 int arg1 in rdx N005 ( 16, 10) [000528] --CXG------- t528 = * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize $1c2 objp: ====== lowering arg : N001 ( 0, 0) [000815] ----------L- * ARGPLACE ref $202 args: ====== lowering arg : N002 ( 0, 0) [000816] ----------L- * ARGPLACE int $100 late: ====== lowering arg : N003 ( 1, 1) [000526] ------------ * LCL_VAR ref V00 this u:1 $100 new node is : [001455] ------------ * PUTARG_REG ref REG rcx lowering arg : N004 ( 1, 1) [000527] ------------ * CNS_INT int 0 $c0 new node is : [001456] ------------ * PUTARG_REG int REG rdx lowering call (after): N003 ( 1, 1) [000526] ------------ t526 = LCL_VAR ref V00 this u:1 $100 /--* t526 ref [001455] ------------ t1455 = * PUTARG_REG ref REG rcx N004 ( 1, 1) [000527] ------------ t527 = CNS_INT int 0 $c0 /--* t527 int [001456] ------------ t1456 = * PUTARG_REG int REG rdx /--* t1455 ref this in rcx +--* t1456 int arg1 in rdx N005 ( 16, 10) [000528] --CXG------- t528 = * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize $1c2 Addressing mode: Base N001 ( 1, 1) [000009] ------------ * LCL_VAR ref V00 this u:1 $100 + 8 Removing unused node: N002 ( 1, 1) [000817] -c---------- * CNS_INT long 8 field offset Fseq[_buckets] $240 New addressing mode node: N003 ( 2, 2) [000818] ------------ * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000009] ------------ t9 = LCL_VAR ref V00 this u:1 $100 /--* t9 ref N003 ( 2, 2) [000818] -c---------- t818 = * LEA(b+8) byref /--* t818 byref N004 ( 4, 4) [000010] nc--GO------ t10 = * IND ref N005 ( 1, 1) [000011] -c---------- t11 = CNS_INT ref null $VN.Null /--* t10 ref +--* t11 ref N006 ( 9, 6) [000012] N---GO------ t12 = * NE int /--* t12 int N008 ( 9, 6) [000544] DA--GO------ * STORE_LCL_VAR int V33 tmp19 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000009] ------------ t9 = LCL_VAR ref V00 this u:1 $100 /--* t9 ref N003 ( 2, 2) [000818] -c---------- t818 = * LEA(b+8) byref /--* t818 byref N004 ( 4, 4) [000010] nc--GO------ t10 = * IND ref N005 ( 1, 1) [000011] -c---------- t11 = CNS_INT ref null $VN.Null /--* t10 ref +--* t11 ref N006 ( 9, 6) [000012] N---GO------ t12 = * NE int /--* t12 int N008 ( 9, 6) [000544] DA--GO------ * STORE_LCL_VAR int V33 tmp19 d:1 lowering store lcl var/field (before): N001 ( 2, 10) [000537] H----------- t537 = CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 /--* t537 long N002 ( 4, 12) [000538] #---G------- t538 = * IND ref $105 /--* t538 ref N004 ( 4, 12) [001291] DA--G------- * STORE_LCL_VAR ref V73 cse8 d:1 lowering store lcl var/field (after): N001 ( 2, 10) [000537] H----------- t537 = CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 /--* t537 long N002 ( 4, 12) [000538] #---G------- t538 = * IND ref $105 /--* t538 ref N004 ( 4, 12) [001291] DA--G------- * STORE_LCL_VAR ref V73 cse8 d:1 lowering store lcl var/field (before): N005 ( 1, 1) [001292] ------------ t1292 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1292 ref N008 ( 5, 13) [000554] DA--G------- * STORE_LCL_VAR ref V34 tmp20 d:1 lowering store lcl var/field (after): N005 ( 1, 1) [001292] ------------ t1292 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1292 ref N008 ( 5, 13) [000554] DA--G------- * STORE_LCL_VAR ref V34 tmp20 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [001294] ------------ t1294 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1294 ref N003 ( 1, 3) [000556] DA--G------- * STORE_LCL_VAR ref V35 tmp21 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [001294] ------------ t1294 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1294 ref N003 ( 1, 3) [000556] DA--G------- * STORE_LCL_VAR ref V35 tmp21 d:1 lowering call (before): N003 ( 1, 1) [000550] ------------ t550 = LCL_VAR ref V35 tmp21 u:1 (last use) $105 N004 ( 1, 1) [000551] ------------ t551 = LCL_VAR ref V35 tmp21 u:1 (last use) $105 /--* t550 ref arg0 in rcx +--* t551 ref arg1 in rdx N005 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000819] ----------L- * ARGPLACE ref $105 lowering arg : N002 ( 0, 0) [000820] ----------L- * ARGPLACE ref $105 late: ====== lowering arg : N003 ( 1, 1) [000550] ------------ * LCL_VAR ref V35 tmp21 u:1 (last use) $105 new node is : [001457] ------------ * PUTARG_REG ref REG rcx lowering arg : N004 ( 1, 1) [000551] ------------ * LCL_VAR ref V35 tmp21 u:1 (last use) $105 new node is : [001458] ------------ * PUTARG_REG ref REG rdx lowering call (after): N003 ( 1, 1) [000550] ------------ t550 = LCL_VAR ref V35 tmp21 u:1 (last use) $105 /--* t550 ref [001457] ------------ t1457 = * PUTARG_REG ref REG rcx N004 ( 1, 1) [000551] ------------ t551 = LCL_VAR ref V35 tmp21 u:1 (last use) $105 /--* t551 ref [001458] ------------ t1458 = * PUTARG_REG ref REG rdx /--* t1457 ref arg0 in rcx +--* t1458 ref arg1 in rdx N005 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void Addressing mode: Base N001 ( 1, 1) [000015] ------------ * LCL_VAR ref V00 this u:1 $100 + 16 Removing unused node: N002 ( 1, 1) [000821] -c---------- * CNS_INT long 16 field offset Fseq[_entries] $241 New addressing mode node: N003 ( 2, 2) [000822] ------------ * LEA(b+16) byref lowering store lcl var/field (before): N001 ( 1, 1) [000015] ------------ t15 = LCL_VAR ref V00 this u:1 $100 /--* t15 ref N003 ( 2, 2) [000822] -c---------- t822 = * LEA(b+16) byref /--* t822 byref N004 ( 4, 4) [000016] n---GO------ t16 = * IND ref /--* t16 ref N006 ( 4, 4) [000018] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000015] ------------ t15 = LCL_VAR ref V00 this u:1 $100 /--* t15 ref N003 ( 2, 2) [000822] -c---------- t822 = * LEA(b+16) byref /--* t822 byref N004 ( 4, 4) [000016] n---GO------ t16 = * IND ref /--* t16 ref N006 ( 4, 4) [000018] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000019] ------------ t19 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000020] -c---------- t20 = CNS_INT ref null $VN.Null /--* t19 ref +--* t20 ref N003 ( 6, 3) [000021] N----------- t21 = * NE int /--* t21 int N005 ( 6, 3) [000566] DA---------- * STORE_LCL_VAR int V36 tmp22 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000019] ------------ t19 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000020] -c---------- t20 = CNS_INT ref null $VN.Null /--* t19 ref +--* t20 ref N003 ( 6, 3) [000021] N----------- t21 = * NE int /--* t21 int N005 ( 6, 3) [000566] DA---------- * STORE_LCL_VAR int V36 tmp22 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [001295] ------------ t1295 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1295 ref N003 ( 1, 3) [000576] DA--G------- * STORE_LCL_VAR ref V37 tmp23 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [001295] ------------ t1295 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1295 ref N003 ( 1, 3) [000576] DA--G------- * STORE_LCL_VAR ref V37 tmp23 d:1 lowering call (before): N003 ( 2, 10) [000823] H----------- t823 = CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" $46 /--* t823 long N004 ( 4, 12) [000824] #---G------- t824 = * IND ref $106 N005 ( 1, 1) [000573] ------------ t573 = LCL_VAR ref V37 tmp23 u:1 (last use) $105 /--* t824 ref arg0 in rcx +--* t573 ref arg1 in rdx N006 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000825] ----------L- * ARGPLACE ref $106 lowering arg : N002 ( 0, 0) [000826] ----------L- * ARGPLACE ref $105 late: ====== lowering arg : N004 ( 4, 12) [000824] #---G------- * IND ref $106 new node is : [001459] ----G------- * PUTARG_REG ref REG rcx lowering arg : N005 ( 1, 1) [000573] ------------ * LCL_VAR ref V37 tmp23 u:1 (last use) $105 new node is : [001460] ------------ * PUTARG_REG ref REG rdx lowering call (after): N003 ( 2, 10) [000823] H----------- t823 = CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" $46 /--* t823 long N004 ( 4, 12) [000824] #---G------- t824 = * IND ref $106 /--* t824 ref [001459] ----G------- t1459 = * PUTARG_REG ref REG rcx N005 ( 1, 1) [000573] ------------ t573 = LCL_VAR ref V37 tmp23 u:1 (last use) $105 /--* t573 ref [001460] ------------ t1460 = * PUTARG_REG ref REG rdx /--* t1459 ref arg0 in rcx +--* t1460 ref arg1 in rdx N006 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void Addressing mode: Base N001 ( 1, 1) [000025] ------------ * LCL_VAR ref V00 this u:1 $100 + 24 Removing unused node: N002 ( 1, 1) [000827] -c---------- * CNS_INT long 24 field offset Fseq[_comparer] $242 New addressing mode node: N003 ( 2, 2) [000828] ------------ * LEA(b+24) byref lowering store lcl var/field (before): N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR ref V00 this u:1 $100 /--* t25 ref N003 ( 2, 2) [000828] -c---------- t828 = * LEA(b+24) byref /--* t828 byref N004 ( 4, 4) [000026] n---GO------ t26 = * IND ref /--* t26 ref N006 ( 4, 4) [000028] DA--GO------ * STORE_LCL_VAR ref V05 loc1 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR ref V00 this u:1 $100 /--* t25 ref N003 ( 2, 2) [000828] -c---------- t828 = * LEA(b+24) byref /--* t828 byref N004 ( 4, 4) [000026] n---GO------ t26 = * IND ref /--* t26 ref N006 ( 4, 4) [000028] DA--GO------ * STORE_LCL_VAR ref V05 loc1 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000486] !----------- t486 = LCL_VAR ref V00 this u:1 $100 /--* t486 ref N002 ( 3, 2) [000487] #----O------ t487 = * IND long $2e8 /--* t487 long N004 ( 3, 3) [000489] DA---O------ * STORE_LCL_VAR long V29 tmp15 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000486] !----------- t486 = LCL_VAR ref V00 this u:1 $100 /--* t486 ref N002 ( 3, 2) [000487] #----O------ t487 = * IND long $2e8 /--* t487 long N004 ( 3, 3) [000489] DA---O------ * STORE_LCL_VAR long V29 tmp15 d:1 Addressing mode: Base N001 ( 1, 1) [000491] ------------ * LCL_VAR long V29 tmp15 u:1 $2e7 + 56 Removing unused node: N002 ( 1, 1) [000492] -c---------- * CNS_INT long 56 $244 New addressing mode node: N003 ( 2, 2) [000493] ------------ * LEA(b+56) long Addressing mode: Base N005 ( 7, 6) [000495] #----------- * IND long $2ea + 64 Removing unused node: N006 ( 1, 1) [000496] -c---------- * CNS_INT long 64 $245 New addressing mode node: N007 ( 8, 7) [000497] ------------ * LEA(b+64) long lowering store lcl var/field (before): N001 ( 1, 1) [000491] ------------ t491 = LCL_VAR long V29 tmp15 u:1 $2e7 /--* t491 long N003 ( 2, 2) [000493] -c---------- t493 = * LEA(b+56) long /--* t493 long N004 ( 4, 4) [000494] #----------- t494 = * IND long $2e9 /--* t494 long N005 ( 7, 6) [000495] #----------- t495 = * IND long $2ea /--* t495 long N007 ( 8, 7) [000497] -c---------- t497 = * LEA(b+64) long /--* t497 long N008 ( 10, 9) [000501] n----------- t501 = * IND long /--* t501 long N010 ( 14, 12) [001266] DA---------- * STORE_LCL_VAR long V68 cse3 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000491] ------------ t491 = LCL_VAR long V29 tmp15 u:1 $2e7 /--* t491 long N003 ( 2, 2) [000493] -c---------- t493 = * LEA(b+56) long /--* t493 long N004 ( 4, 4) [000494] #----------- t494 = * IND long $2e9 /--* t494 long N005 ( 7, 6) [000495] #----------- t495 = * IND long $2ea /--* t495 long N007 ( 8, 7) [000497] -c---------- t497 = * LEA(b+64) long /--* t497 long N008 ( 10, 9) [000501] n----------- t501 = * IND long /--* t501 long N010 ( 14, 12) [001266] DA---------- * STORE_LCL_VAR long V68 cse3 d:1 lowering store lcl var/field (before): N001 ( 3, 2) [001269] ------------ t1269 = LCL_VAR long V68 cse3 u:1 /--* t1269 long N003 ( 3, 3) [001150] DA---------- * STORE_LCL_VAR long V31 tmp17 d:3 lowering store lcl var/field (after): N001 ( 3, 2) [001269] ------------ t1269 = LCL_VAR long V68 cse3 u:1 /--* t1269 long N003 ( 3, 3) [001150] DA---------- * STORE_LCL_VAR long V31 tmp17 d:3 lowering call (before): N003 ( 1, 1) [000490] ------?----- t490 = LCL_VAR long V29 tmp15 u:1 (last use) $2e7 N004 ( 2, 10) [000502] H-----?----- t502 = CNS_INT(h) long 0xd1ffab1e global ptr $49 /--* t490 long arg0 in rcx +--* t502 long arg1 in rdx N005 ( 17, 18) [000503] --C-G-?----- t503 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $308 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000829] ------?---L- * ARGPLACE long $2e7 lowering arg : N002 ( 0, 0) [000830] ------?---L- * ARGPLACE long $49 late: ====== lowering arg : N003 ( 1, 1) [000490] ------?----- * LCL_VAR long V29 tmp15 u:1 (last use) $2e7 new node is : [001461] ------------ * PUTARG_REG long REG rcx lowering arg : N004 ( 2, 10) [000502] H-----?----- * CNS_INT(h) long 0xd1ffab1e global ptr $49 new node is : [001462] ------------ * PUTARG_REG long REG rdx lowering call (after): N003 ( 1, 1) [000490] ------?----- t490 = LCL_VAR long V29 tmp15 u:1 (last use) $2e7 /--* t490 long [001461] ------------ t1461 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000502] H-----?----- t502 = CNS_INT(h) long 0xd1ffab1e global ptr $49 /--* t502 long [001462] ------------ t1462 = * PUTARG_REG long REG rdx /--* t1461 long arg0 in rcx +--* t1462 long arg1 in rdx N005 ( 17, 18) [000503] --C-G-?----- t503 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $308 lowering store lcl var/field (before): N003 ( 1, 1) [000490] ------?----- t490 = LCL_VAR long V29 tmp15 u:1 (last use) $2e7 /--* t490 long [001461] ------------ t1461 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000502] H-----?----- t502 = CNS_INT(h) long 0xd1ffab1e global ptr $49 /--* t502 long [001462] ------------ t1462 = * PUTARG_REG long REG rdx /--* t1461 long arg0 in rcx +--* t1462 long arg1 in rdx N005 ( 17, 18) [000503] --C-G-?----- t503 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $308 /--* t503 long N007 ( 17, 18) [001152] DA--G------- * STORE_LCL_VAR long V31 tmp17 d:2 lowering store lcl var/field (after): N003 ( 1, 1) [000490] ------?----- t490 = LCL_VAR long V29 tmp15 u:1 (last use) $2e7 /--* t490 long [001461] ------------ t1461 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000502] H-----?----- t502 = CNS_INT(h) long 0xd1ffab1e global ptr $49 /--* t502 long [001462] ------------ t1462 = * PUTARG_REG long REG rdx /--* t1461 long arg0 in rcx +--* t1462 long arg1 in rdx N005 ( 17, 18) [000503] --C-G-?----- t503 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $308 /--* t503 long N007 ( 17, 18) [001152] DA--G------- * STORE_LCL_VAR long V31 tmp17 d:2 lowering store lcl var/field (before): N001 ( 0, 0) [001247] ------------ t1247 = PHI_ARG long V31 tmp17 u:3 N002 ( 0, 0) [001246] ------------ t1246 = PHI_ARG long V31 tmp17 u:2 $308 /--* t1247 long +--* t1246 long N003 ( 0, 0) [001216] ------------ t1216 = * PHI long /--* t1216 long N005 ( 0, 0) [001217] DA---------- * STORE_LCL_VAR long V31 tmp17 d:1 lowering store lcl var/field (after): N001 ( 0, 0) [001247] ------------ t1247 = PHI_ARG long V31 tmp17 u:3 N002 ( 0, 0) [001246] ------------ t1246 = PHI_ARG long V31 tmp17 u:2 $308 /--* t1247 long +--* t1246 long N003 ( 0, 0) [001216] ------------ t1216 = * PHI long /--* t1216 long N005 ( 0, 0) [001217] DA---------- * STORE_LCL_VAR long V31 tmp17 d:1 lowering call (before): N004 ( 1, 1) [000484] ------------ t484 = LCL_VAR ref V05 loc1 u:1 N005 ( 1, 1) [000831] ------------ t831 = LCL_VAR long V31 tmp17 u:1 r11 REG r11 $342 N006 ( 1, 1) [000500] ------------ t500 = LCL_VAR ref V01 arg1 u:1 $101 N007 ( 1, 1) [000521] ------------ t521 = LCL_VAR long V31 tmp17 u:1 (last use) $342 /--* t484 ref this in rcx +--* t831 long arg1 in r11 +--* t500 ref arg2 in rdx +--* t521 long calli tgt N008 ( 27, 12) [000522] --CXG------- t522 = * CALL ind stub int $1c7 objp: ====== lowering arg : N001 ( 0, 0) [000832] ----------L- * ARGPLACE ref $214 args: ====== lowering arg : N002 ( 0, 0) [000833] ----------L- * ARGPLACE long lowering arg : N003 ( 0, 0) [000834] ----------L- * ARGPLACE ref $342 late: ====== lowering arg : N004 ( 1, 1) [000484] ------------ * LCL_VAR ref V05 loc1 u:1 new node is : [001463] ------------ * PUTARG_REG ref REG rcx lowering arg : N005 ( 1, 1) [000831] ------------ * LCL_VAR long V31 tmp17 u:1 r11 REG r11 $342 new node is : [001464] ------------ * PUTARG_REG long REG r11 lowering arg : N006 ( 1, 1) [000500] ------------ * LCL_VAR ref V01 arg1 u:1 $101 new node is : [001465] ------------ * PUTARG_REG ref REG rdx lowering call (after): N004 ( 1, 1) [000484] ------------ t484 = LCL_VAR ref V05 loc1 u:1 /--* t484 ref [001463] ------------ t1463 = * PUTARG_REG ref REG rcx N005 ( 1, 1) [000831] ------------ t831 = LCL_VAR long V31 tmp17 u:1 r11 REG r11 $342 /--* t831 long [001464] ------------ t1464 = * PUTARG_REG long REG r11 N006 ( 1, 1) [000500] ------------ t500 = LCL_VAR ref V01 arg1 u:1 $101 /--* t500 ref [001465] ------------ t1465 = * PUTARG_REG ref REG rdx N007 ( 1, 1) [000521] ------------ t521 = LCL_VAR long V31 tmp17 u:1 (last use) $342 /--* t521 long [001466] Dc---------- t1466 = * IND long REG NA /--* t1463 ref this in rcx +--* t1464 long arg1 in r11 +--* t1465 ref arg2 in rdx +--* t1466 long calli tgt N008 ( 27, 12) [000522] --CXG------- t522 = * CALL ind stub int $1c7 lowering store lcl var/field (before): N004 ( 1, 1) [000484] ------------ t484 = LCL_VAR ref V05 loc1 u:1 /--* t484 ref [001463] ------------ t1463 = * PUTARG_REG ref REG rcx N005 ( 1, 1) [000831] ------------ t831 = LCL_VAR long V31 tmp17 u:1 r11 REG r11 $342 /--* t831 long [001464] ------------ t1464 = * PUTARG_REG long REG r11 N006 ( 1, 1) [000500] ------------ t500 = LCL_VAR ref V01 arg1 u:1 $101 /--* t500 ref [001465] ------------ t1465 = * PUTARG_REG ref REG rdx N007 ( 1, 1) [000521] ------------ t521 = LCL_VAR long V31 tmp17 u:1 (last use) $342 /--* t521 long [001466] Dc---------- t1466 = * IND long REG NA /--* t1463 ref this in rcx +--* t1464 long arg1 in r11 +--* t1465 ref arg2 in rdx +--* t1466 long calli tgt N008 ( 27, 12) [000522] --CXG------- t522 = * CALL ind stub int $1c7 /--* t522 int N010 ( 31, 15) [000524] DA-XG------- * STORE_LCL_VAR int V15 tmp1 d:3 lowering store lcl var/field (after): N004 ( 1, 1) [000484] ------------ t484 = LCL_VAR ref V05 loc1 u:1 /--* t484 ref [001463] ------------ t1463 = * PUTARG_REG ref REG rcx N005 ( 1, 1) [000831] ------------ t831 = LCL_VAR long V31 tmp17 u:1 r11 REG r11 $342 /--* t831 long [001464] ------------ t1464 = * PUTARG_REG long REG r11 N006 ( 1, 1) [000500] ------------ t500 = LCL_VAR ref V01 arg1 u:1 $101 /--* t500 ref [001465] ------------ t1465 = * PUTARG_REG ref REG rdx N007 ( 1, 1) [000521] ------------ t521 = LCL_VAR long V31 tmp17 u:1 (last use) $342 /--* t521 long [001466] Dc---------- t1466 = * IND long REG NA /--* t1463 ref this in rcx +--* t1464 long arg1 in r11 +--* t1465 ref arg2 in rdx +--* t1466 long calli tgt N008 ( 27, 12) [000522] --CXG------- t522 = * CALL ind stub int $1c7 /--* t522 int N010 ( 31, 15) [000524] DA-XG------- * STORE_LCL_VAR int V15 tmp1 d:3 Addressing mode: Base N004 ( 3, 2) [000837] #----O------ * IND long $2e4 + 72 Removing unused node: N005 ( 1, 1) [000838] -c---------- * CNS_INT int 72 $c9 New addressing mode node: N006 ( 4, 3) [000839] ------------ * LEA(b+72) long Addressing mode: Base N007 ( 6, 5) [000840] #----O------ * IND long $2e6 + 24 Removing unused node: N008 ( 1, 1) [000841] -c---------- * CNS_INT int 24 $ca New addressing mode node: N009 ( 7, 6) [000842] ------------ * LEA(b+24) long lowering call (before): N002 ( 1, 1) [000033] ------------ t33 = LCL_VAR ref V01 arg1 u:1 $101 N003 ( 1, 1) [000836] ------------ t836 = LCL_VAR ref V01 arg1 u:1 $101 /--* t836 ref N004 ( 3, 2) [000837] #----O------ t837 = * IND long $2e4 /--* t837 long N006 ( 4, 3) [000839] -c---------- t839 = * LEA(b+72) long /--* t839 long N007 ( 6, 5) [000840] #----O------ t840 = * IND long $2e6 /--* t840 long N009 ( 7, 6) [000842] -c---------- t842 = * LEA(b+24) long /--* t842 long N010 ( 9, 8) [000843] n----O------ t843 = * IND long /--* t33 ref this in rcx +--* t843 long control expr N011 ( 30, 18) [000035] --CXGO------ t35 = * CALLV vt-ind int System.Object.GetHashCode $1c5 objp: ====== lowering arg : N001 ( 0, 0) [000835] ----------L- * ARGPLACE ref $212 args: ====== late: ====== lowering arg : N002 ( 1, 1) [000033] ------------ * LCL_VAR ref V01 arg1 u:1 $101 new node is : [001467] ------------ * PUTARG_REG ref REG rcx lowering call (after): N002 ( 1, 1) [000033] ------------ t33 = LCL_VAR ref V01 arg1 u:1 $101 /--* t33 ref [001467] ------------ t1467 = * PUTARG_REG ref REG rcx N003 ( 1, 1) [000836] ------------ t836 = LCL_VAR ref V01 arg1 u:1 $101 /--* t836 ref N004 ( 3, 2) [000837] #----O------ t837 = * IND long $2e4 /--* t837 long N006 ( 4, 3) [000839] -c---------- t839 = * LEA(b+72) long /--* t839 long N007 ( 6, 5) [000840] #----O------ t840 = * IND long $2e6 /--* t840 long N009 ( 7, 6) [000842] -c---------- t842 = * LEA(b+24) long /--* t842 long N010 ( 9, 8) [000843] nc---O------ t843 = * IND long REG NA /--* t1467 ref this in rcx +--* t843 long control expr N011 ( 30, 18) [000035] --CXGO------ t35 = * CALLV vt-ind int System.Object.GetHashCode $1c5 lowering store lcl var/field (before): N002 ( 1, 1) [000033] ------------ t33 = LCL_VAR ref V01 arg1 u:1 $101 /--* t33 ref [001467] ------------ t1467 = * PUTARG_REG ref REG rcx N003 ( 1, 1) [000836] ------------ t836 = LCL_VAR ref V01 arg1 u:1 $101 /--* t836 ref N004 ( 3, 2) [000837] #----O------ t837 = * IND long $2e4 /--* t837 long N006 ( 4, 3) [000839] -c---------- t839 = * LEA(b+72) long /--* t839 long N007 ( 6, 5) [000840] #----O------ t840 = * IND long $2e6 /--* t840 long N009 ( 7, 6) [000842] -c---------- t842 = * LEA(b+24) long /--* t842 long N010 ( 9, 8) [000843] nc---O------ t843 = * IND long REG NA /--* t1467 ref this in rcx +--* t843 long control expr N011 ( 30, 18) [000035] --CXGO------ t35 = * CALLV vt-ind int System.Object.GetHashCode $1c5 /--* t35 int N013 ( 34, 21) [000038] DA-XGO------ * STORE_LCL_VAR int V15 tmp1 d:2 lowering store lcl var/field (after): N002 ( 1, 1) [000033] ------------ t33 = LCL_VAR ref V01 arg1 u:1 $101 /--* t33 ref [001467] ------------ t1467 = * PUTARG_REG ref REG rcx N003 ( 1, 1) [000836] ------------ t836 = LCL_VAR ref V01 arg1 u:1 $101 /--* t836 ref N004 ( 3, 2) [000837] #----O------ t837 = * IND long $2e4 /--* t837 long N006 ( 4, 3) [000839] -c---------- t839 = * LEA(b+72) long /--* t839 long N007 ( 6, 5) [000840] #----O------ t840 = * IND long $2e6 /--* t840 long N009 ( 7, 6) [000842] -c---------- t842 = * LEA(b+24) long /--* t842 long N010 ( 9, 8) [000843] nc---O------ t843 = * IND long REG NA /--* t1467 ref this in rcx +--* t843 long control expr N011 ( 30, 18) [000035] --CXGO------ t35 = * CALLV vt-ind int System.Object.GetHashCode $1c5 /--* t35 int N013 ( 34, 21) [000038] DA-XGO------ * STORE_LCL_VAR int V15 tmp1 d:2 lowering store lcl var/field (before): N001 ( 0, 0) [001245] ------------ t1245 = PHI_ARG int V15 tmp1 u:3 $1c7 N002 ( 0, 0) [001244] ------------ t1244 = PHI_ARG int V15 tmp1 u:2 $1c5 /--* t1245 int +--* t1244 int N003 ( 0, 0) [001213] ------------ t1213 = * PHI int /--* t1213 int N005 ( 0, 0) [001214] DA---------- * STORE_LCL_VAR int V15 tmp1 d:1 lowering store lcl var/field (after): N001 ( 0, 0) [001245] ------------ t1245 = PHI_ARG int V15 tmp1 u:3 $1c7 N002 ( 0, 0) [001244] ------------ t1244 = PHI_ARG int V15 tmp1 u:2 $1c5 /--* t1245 int +--* t1244 int N003 ( 0, 0) [001213] ------------ t1213 = * PHI int /--* t1213 int N005 ( 0, 0) [001214] DA---------- * STORE_LCL_VAR int V15 tmp1 d:1 lowering store lcl var/field (before): N001 ( 3, 2) [000040] ------------ t40 = LCL_VAR int V15 tmp1 u:1 (last use) $3c0 /--* t40 int N003 ( 3, 3) [000042] DA---------- * STORE_LCL_VAR int V06 loc2 d:1 lowering store lcl var/field (after): N001 ( 3, 2) [000040] ------------ t40 = LCL_VAR int V15 tmp1 u:1 (last use) $3c0 /--* t40 int N003 ( 3, 3) [000042] DA---------- * STORE_LCL_VAR int V06 loc2 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000043] ------------ t43 = CNS_INT int 0 $c0 /--* t43 int N003 ( 1, 3) [000045] DA---------- * STORE_LCL_VAR int V07 loc3 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000043] ------------ t43 = CNS_INT int 0 $c0 /--* t43 int N003 ( 1, 3) [000045] DA---------- * STORE_LCL_VAR int V07 loc3 d:1 Addressing mode: Base N001 ( 1, 1) [000046] ------------ * LCL_VAR ref V00 this u:1 $100 + 8 Removing unused node: N002 ( 1, 1) [000844] -c---------- * CNS_INT long 8 field offset Fseq[_buckets] $240 New addressing mode node: N003 ( 2, 2) [000845] ------------ * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000046] ------------ t46 = LCL_VAR ref V00 this u:1 $100 /--* t46 ref N003 ( 2, 2) [000845] -c---------- t845 = * LEA(b+8) byref /--* t845 byref N004 ( 4, 4) [000578] n---GO------ t578 = * IND ref /--* t578 ref N006 ( 4, 4) [000580] DA--GO------ * STORE_LCL_VAR ref V39 tmp25 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000046] ------------ t46 = LCL_VAR ref V00 this u:1 $100 /--* t46 ref N003 ( 2, 2) [000845] -c---------- t845 = * LEA(b+8) byref /--* t845 byref N004 ( 4, 4) [000578] n---GO------ t578 = * IND ref /--* t578 ref N006 ( 4, 4) [000580] DA--GO------ * STORE_LCL_VAR ref V39 tmp25 d:1 Addressing mode: Base N001 ( 1, 1) [000582] ------------ * LCL_VAR ref V39 tmp25 u:1 + 8 Removing unused node: [001440] -c---------- * CNS_INT long 8 New addressing mode node: [001441] ------------ * LEA(b+8) ref lowering store lcl var/field (before): N001 ( 1, 1) [000582] ------------ t582 = LCL_VAR ref V39 tmp25 u:1 /--* t582 ref [001441] -c---------- t1441 = * LEA(b+8) ref /--* t1441 ref N002 ( 3, 3) [000583] ---X-------- t583 = * IND int /--* t583 int N004 ( 3, 3) [000629] DA-X-------- * STORE_LCL_VAR int V40 tmp26 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000582] ------------ t582 = LCL_VAR ref V39 tmp25 u:1 /--* t582 ref [001441] -c---------- t1441 = * LEA(b+8) ref /--* t1441 ref N002 ( 3, 3) [000583] ---X-------- t583 = * IND int /--* t583 int N004 ( 3, 3) [000629] DA-X-------- * STORE_LCL_VAR int V40 tmp26 d:1 Addressing mode: Base N001 ( 1, 1) [000584] ------------ * LCL_VAR ref V00 this u:1 $100 + 48 Removing unused node: N002 ( 1, 1) [000846] -c---------- * CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 New addressing mode node: N003 ( 2, 2) [000847] ------------ * LEA(b+48) byref lowering store lcl var/field (before): N001 ( 1, 1) [000584] ------------ t584 = LCL_VAR ref V00 this u:1 $100 /--* t584 ref N003 ( 2, 2) [000847] -c---------- t847 = * LEA(b+48) byref /--* t847 byref N004 ( 4, 4) [000585] n---GO------ t585 = * IND long /--* t585 long N006 ( 4, 4) [000631] DA--GO------ * STORE_LCL_VAR long V41 tmp27 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000584] ------------ t584 = LCL_VAR ref V00 this u:1 $100 /--* t584 ref N003 ( 2, 2) [000847] -c---------- t847 = * LEA(b+48) byref /--* t847 byref N004 ( 4, 4) [000585] n---GO------ t585 = * IND long /--* t585 long N006 ( 4, 4) [000631] DA--GO------ * STORE_LCL_VAR long V41 tmp27 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000597] ------------ t597 = LCL_VAR int V40 tmp26 u:1 N002 ( 1, 4) [000598] -c---------- t598 = CNS_INT int 0x7FFFFFFF $ce /--* t597 int +--* t598 int N003 ( 6, 6) [000599] N--------U-- t599 = * LE int /--* t599 int N005 ( 6, 6) [000642] DA---------- * STORE_LCL_VAR int V43 tmp29 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000597] ------------ t597 = LCL_VAR int V40 tmp26 u:1 N002 ( 1, 4) [000598] -c---------- t598 = CNS_INT int 0x7FFFFFFF $ce /--* t597 int +--* t598 int N003 ( 6, 6) [000599] N--------U-- t599 = * LE int /--* t599 int N005 ( 6, 6) [000642] DA---------- * STORE_LCL_VAR int V43 tmp29 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [001296] ------------ t1296 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1296 ref N003 ( 1, 3) [000652] DA--G------- * STORE_LCL_VAR ref V44 tmp30 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [001296] ------------ t1296 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1296 ref N003 ( 1, 3) [000652] DA--G------- * STORE_LCL_VAR ref V44 tmp30 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [001297] ------------ t1297 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1297 ref N003 ( 1, 3) [000654] DA--G------- * STORE_LCL_VAR ref V45 tmp31 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [001297] ------------ t1297 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1297 ref N003 ( 1, 3) [000654] DA--G------- * STORE_LCL_VAR ref V45 tmp31 d:1 lowering call (before): N003 ( 1, 1) [000648] ------------ t648 = LCL_VAR ref V45 tmp31 u:1 (last use) $105 N004 ( 1, 1) [000649] ------------ t649 = LCL_VAR ref V45 tmp31 u:1 (last use) $105 /--* t648 ref arg0 in rcx +--* t649 ref arg1 in rdx N005 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000848] ----------L- * ARGPLACE ref $105 lowering arg : N002 ( 0, 0) [000849] ----------L- * ARGPLACE ref $105 late: ====== lowering arg : N003 ( 1, 1) [000648] ------------ * LCL_VAR ref V45 tmp31 u:1 (last use) $105 new node is : [001468] ------------ * PUTARG_REG ref REG rcx lowering arg : N004 ( 1, 1) [000649] ------------ * LCL_VAR ref V45 tmp31 u:1 (last use) $105 new node is : [001469] ------------ * PUTARG_REG ref REG rdx lowering call (after): N003 ( 1, 1) [000648] ------------ t648 = LCL_VAR ref V45 tmp31 u:1 (last use) $105 /--* t648 ref [001468] ------------ t1468 = * PUTARG_REG ref REG rcx N004 ( 1, 1) [000649] ------------ t649 = LCL_VAR ref V45 tmp31 u:1 (last use) $105 /--* t649 ref [001469] ------------ t1469 = * PUTARG_REG ref REG rdx /--* t1468 ref arg0 in rcx +--* t1469 ref arg1 in rdx N005 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void lowering store lcl var/field (before): N001 ( 1, 1) [000604] ------------ t604 = LCL_VAR long V41 tmp27 u:1 (last use) N002 ( 1, 1) [000047] ------------ t47 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t47 int N003 ( 2, 3) [000605] ---------U-- t605 = * CAST long <- ulong <- uint $310 /--* t604 long +--* t605 long N004 ( 7, 7) [000606] ------------ t606 = * MUL long N005 ( 1, 1) [000607] -c---------- t607 = CNS_INT int 32 $d2 /--* t606 long +--* t607 int N006 ( 9, 9) [000608] ------------ t608 = * RSZ long N007 ( 1, 1) [000610] -c---------- t610 = CNS_INT long 1 $247 /--* t608 long +--* t610 long N008 ( 11, 11) [000611] ------------ t611 = * ADD long N009 ( 1, 1) [000612] ------------ t612 = LCL_VAR int V40 tmp26 u:1 /--* t612 int N010 ( 2, 3) [000613] ---------U-- t613 = * CAST long <- ulong <- uint /--* t611 long +--* t613 long N011 ( 17, 17) [000614] ------------ t614 = * MUL long N012 ( 1, 1) [000615] -c---------- t615 = CNS_INT int 32 $d2 /--* t614 long +--* t615 int N013 ( 19, 19) [000616] ------------ t616 = * RSZ long /--* t616 long N014 ( 20, 21) [000617] ------------ t617 = * CAST int <- uint <- long /--* t617 int N016 ( 20, 21) [000619] DA---------- * STORE_LCL_VAR int V42 tmp28 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000604] ------------ t604 = LCL_VAR long V41 tmp27 u:1 (last use) N002 ( 1, 1) [000047] ------------ t47 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t47 int N003 ( 2, 3) [000605] ---------U-- t605 = * CAST long <- ulong <- uint $310 /--* t604 long +--* t605 long N004 ( 7, 7) [000606] ------------ t606 = * MUL long N005 ( 1, 1) [000607] -c---------- t607 = CNS_INT int 32 $d2 /--* t606 long +--* t607 int N006 ( 9, 9) [000608] ------------ t608 = * RSZ long N007 ( 1, 1) [000610] -c---------- t610 = CNS_INT long 1 $247 /--* t608 long +--* t610 long N008 ( 11, 11) [000611] ------------ t611 = * ADD long N009 ( 1, 1) [000612] ------------ t612 = LCL_VAR int V40 tmp26 u:1 /--* t612 int N010 ( 2, 3) [000613] ---------U-- t613 = * CAST long <- ulong <- uint /--* t611 long +--* t613 long N011 ( 17, 17) [000614] ------------ t614 = * MUL long N012 ( 1, 1) [000615] -c---------- t615 = CNS_INT int 32 $d2 /--* t614 long +--* t615 int N013 ( 19, 19) [000616] ------------ t616 = * RSZ long /--* t616 long N014 ( 20, 21) [000617] ------------ t617 = * CAST int <- uint <- long /--* t617 int N016 ( 20, 21) [000619] DA---------- * STORE_LCL_VAR int V42 tmp28 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000621] ------------ t621 = LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000622] ------------ t622 = LCL_VAR int V40 tmp26 u:1 (last use) /--* t621 int +--* t622 int N003 ( 22, 5) [000623] ---X-------- t623 = * UMOD int N004 ( 1, 1) [000620] ------------ t620 = LCL_VAR int V42 tmp28 u:1 /--* t623 int +--* t620 int N005 ( 27, 7) [000624] ---X-------- t624 = * EQ int /--* t624 int N007 ( 27, 7) [000665] DA-X-------- * STORE_LCL_VAR int V46 tmp32 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000621] ------------ t621 = LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000622] ------------ t622 = LCL_VAR int V40 tmp26 u:1 (last use) /--* t621 int +--* t622 int N003 ( 22, 5) [000623] ---X-------- t623 = * UMOD int N004 ( 1, 1) [000620] ------------ t620 = LCL_VAR int V42 tmp28 u:1 /--* t623 int +--* t620 int N005 ( 27, 7) [000624] ---X-------- t624 = * EQ int /--* t624 int N007 ( 27, 7) [000665] DA-X-------- * STORE_LCL_VAR int V46 tmp32 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [001298] ------------ t1298 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1298 ref N003 ( 1, 3) [000675] DA--G------- * STORE_LCL_VAR ref V47 tmp33 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [001298] ------------ t1298 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1298 ref N003 ( 1, 3) [000675] DA--G------- * STORE_LCL_VAR ref V47 tmp33 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [001299] ------------ t1299 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1299 ref N003 ( 1, 3) [000677] DA--G------- * STORE_LCL_VAR ref V48 tmp34 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [001299] ------------ t1299 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1299 ref N003 ( 1, 3) [000677] DA--G------- * STORE_LCL_VAR ref V48 tmp34 d:1 lowering call (before): N003 ( 1, 1) [000671] ------------ t671 = LCL_VAR ref V48 tmp34 u:1 (last use) $105 N004 ( 1, 1) [000672] ------------ t672 = LCL_VAR ref V48 tmp34 u:1 (last use) $105 /--* t671 ref arg0 in rcx +--* t672 ref arg1 in rdx N005 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000850] ----------L- * ARGPLACE ref $105 lowering arg : N002 ( 0, 0) [000851] ----------L- * ARGPLACE ref $105 late: ====== lowering arg : N003 ( 1, 1) [000671] ------------ * LCL_VAR ref V48 tmp34 u:1 (last use) $105 new node is : [001470] ------------ * PUTARG_REG ref REG rcx lowering arg : N004 ( 1, 1) [000672] ------------ * LCL_VAR ref V48 tmp34 u:1 (last use) $105 new node is : [001471] ------------ * PUTARG_REG ref REG rdx lowering call (after): N003 ( 1, 1) [000671] ------------ t671 = LCL_VAR ref V48 tmp34 u:1 (last use) $105 /--* t671 ref [001470] ------------ t1470 = * PUTARG_REG ref REG rcx N004 ( 1, 1) [000672] ------------ t672 = LCL_VAR ref V48 tmp34 u:1 (last use) $105 /--* t672 ref [001471] ------------ t1471 = * PUTARG_REG ref REG rdx /--* t1470 ref arg0 in rcx +--* t1471 ref arg1 in rdx N005 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void Addressing mode: Base N002 ( 1, 1) [000581] ------------ * LCL_VAR ref V39 tmp25 u:1 + 8 Removing unused node: [001442] -c---------- * CNS_INT long 8 New addressing mode node: [001443] ------------ * LEA(b+8) ref Addressing mode: Base N005 ( 1, 1) [000852] ------------ * LCL_VAR ref V39 tmp25 u:1 (last use) + Index * 4 + 16 N007 ( 2, 3) [000856] ------------ * CAST long <- int Removing unused node: N011 ( 4, 5) [000860] -------N---- * ADD long Removing unused node: N010 ( 1, 1) [000859] -c---------- * CNS_INT long 16 Fseq[#FirstElem] $241 Removing unused node: N009 ( 3, 4) [000858] -------N---- * LSH long Removing unused node: N008 ( 1, 1) [000857] -c-----N---- * CNS_INT long 2 $248 New addressing mode node: N012 ( 5, 6) [000861] -------N---- * LEA(b+(i*4)+16) byref lowering store lcl var/field (before): N005 ( 1, 1) [000852] ------------ t852 = LCL_VAR ref V39 tmp25 u:1 (last use) N006 ( 1, 1) [000853] ------------ t853 = LCL_VAR int V42 tmp28 u:1 (last use) /--* t853 int N007 ( 2, 3) [000856] ------------ t856 = * CAST long <- int /--* t852 ref +--* t856 long N012 ( 5, 6) [000861] -------N---- t861 = * LEA(b+(i*4)+16) byref /--* t861 byref N017 ( 19, 24) [000591] DA-XG------- * STORE_LCL_VAR byref V38 tmp24 d:1 lowering store lcl var/field (after): N005 ( 1, 1) [000852] ------------ t852 = LCL_VAR ref V39 tmp25 u:1 (last use) N006 ( 1, 1) [000853] ------------ t853 = LCL_VAR int V42 tmp28 u:1 (last use) /--* t853 int N007 ( 2, 3) [000856] ------------ t856 = * CAST long <- int /--* t852 ref +--* t856 long N012 ( 5, 6) [000861] -------N---- t861 = * LEA(b+(i*4)+16) byref /--* t861 byref N017 ( 19, 24) [000591] DA-XG------- * STORE_LCL_VAR byref V38 tmp24 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000592] ------------ t592 = LCL_VAR byref V38 tmp24 u:1 $81 /--* t592 byref N003 ( 5, 4) [000051] DA---------- * STORE_LCL_VAR byref V08 loc4 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000592] ------------ t592 = LCL_VAR byref V38 tmp24 u:1 $81 /--* t592 byref N003 ( 5, 4) [000051] DA---------- * STORE_LCL_VAR byref V08 loc4 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000052] ------------ t52 = LCL_VAR byref V08 loc4 u:1 (last use) $81 /--* t52 byref N002 ( 3, 2) [000053] *--XG------- t53 = * IND int N003 ( 1, 1) [000054] -c---------- t54 = CNS_INT int -1 $c4 /--* t53 int +--* t54 int N004 ( 5, 4) [000055] ---XG------- t55 = * ADD int /--* t55 int N006 ( 5, 4) [000057] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000052] ------------ t52 = LCL_VAR byref V08 loc4 u:1 (last use) $81 /--* t52 byref N002 ( 3, 2) [000053] *--XG------- t53 = * IND int N003 ( 1, 1) [000054] -c---------- t54 = CNS_INT int -1 $c4 /--* t53 int +--* t54 int N004 ( 5, 4) [000055] ---XG------- t55 = * ADD int /--* t55 int N006 ( 5, 4) [000057] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000353] !----------- t353 = LCL_VAR ref V00 this u:1 $100 /--* t353 ref N002 ( 3, 2) [000354] #----O------ t354 = * IND long $2e8 /--* t354 long N004 ( 3, 3) [000356] DA---O------ * STORE_LCL_VAR long V24 tmp10 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000353] !----------- t353 = LCL_VAR ref V00 this u:1 $100 /--* t353 ref N002 ( 3, 2) [000354] #----O------ t354 = * IND long $2e8 /--* t354 long N004 ( 3, 3) [000356] DA---O------ * STORE_LCL_VAR long V24 tmp10 d:1 Addressing mode: Base N001 ( 1, 1) [000358] ------------ * LCL_VAR long V24 tmp10 u:1 $2e7 + 56 Removing unused node: N002 ( 1, 1) [000359] -c---------- * CNS_INT long 56 $244 New addressing mode node: N003 ( 2, 2) [000360] ------------ * LEA(b+56) long Addressing mode: Base N005 ( 7, 6) [000362] #----------- * IND long $2ea + 32 Removing unused node: N006 ( 1, 1) [000363] -c---------- * CNS_INT long 32 $24a New addressing mode node: N007 ( 8, 7) [000364] ------------ * LEA(b+32) long lowering store lcl var/field (before): N001 ( 1, 1) [000358] ------------ t358 = LCL_VAR long V24 tmp10 u:1 $2e7 /--* t358 long N003 ( 2, 2) [000360] -c---------- t360 = * LEA(b+56) long /--* t360 long N004 ( 4, 4) [000361] #----------- t361 = * IND long $2e9 /--* t361 long N005 ( 7, 6) [000362] #----------- t362 = * IND long $2ea /--* t362 long N007 ( 8, 7) [000364] -c---------- t364 = * LEA(b+32) long /--* t364 long N008 ( 10, 9) [000365] n----------- t365 = * IND long /--* t365 long N010 ( 14, 12) [001271] DA---------- * STORE_LCL_VAR long V69 cse4 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000358] ------------ t358 = LCL_VAR long V24 tmp10 u:1 $2e7 /--* t358 long N003 ( 2, 2) [000360] -c---------- t360 = * LEA(b+56) long /--* t360 long N004 ( 4, 4) [000361] #----------- t361 = * IND long $2e9 /--* t361 long N005 ( 7, 6) [000362] #----------- t362 = * IND long $2ea /--* t362 long N007 ( 8, 7) [000364] -c---------- t364 = * LEA(b+32) long /--* t364 long N008 ( 10, 9) [000365] n----------- t365 = * IND long /--* t365 long N010 ( 14, 12) [001271] DA---------- * STORE_LCL_VAR long V69 cse4 d:1 lowering store lcl var/field (before): N001 ( 3, 2) [001274] ------------ t1274 = LCL_VAR long V69 cse4 u:1 /--* t1274 long N003 ( 7, 5) [001155] DA---------- * STORE_LCL_VAR long V25 tmp11 d:3 lowering store lcl var/field (after): N001 ( 3, 2) [001274] ------------ t1274 = LCL_VAR long V69 cse4 u:1 /--* t1274 long N003 ( 7, 5) [001155] DA---------- * STORE_LCL_VAR long V25 tmp11 d:3 lowering call (before): N003 ( 1, 1) [000357] ------?----- t357 = LCL_VAR long V24 tmp10 u:1 (last use) $2e7 N004 ( 2, 10) [000366] H-----?----- t366 = CNS_INT(h) long 0xd1ffab1e global ptr $4f /--* t357 long arg0 in rcx +--* t366 long arg1 in rdx N005 ( 17, 18) [000367] --C-G-?----- t367 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $325 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000864] ------?---L- * ARGPLACE long $2e7 lowering arg : N002 ( 0, 0) [000865] ------?---L- * ARGPLACE long $4f late: ====== lowering arg : N003 ( 1, 1) [000357] ------?----- * LCL_VAR long V24 tmp10 u:1 (last use) $2e7 new node is : [001472] ------------ * PUTARG_REG long REG rcx lowering arg : N004 ( 2, 10) [000366] H-----?----- * CNS_INT(h) long 0xd1ffab1e global ptr $4f new node is : [001473] ------------ * PUTARG_REG long REG rdx lowering call (after): N003 ( 1, 1) [000357] ------?----- t357 = LCL_VAR long V24 tmp10 u:1 (last use) $2e7 /--* t357 long [001472] ------------ t1472 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000366] H-----?----- t366 = CNS_INT(h) long 0xd1ffab1e global ptr $4f /--* t366 long [001473] ------------ t1473 = * PUTARG_REG long REG rdx /--* t1472 long arg0 in rcx +--* t1473 long arg1 in rdx N005 ( 17, 18) [000367] --C-G-?----- t367 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $325 lowering store lcl var/field (before): N003 ( 1, 1) [000357] ------?----- t357 = LCL_VAR long V24 tmp10 u:1 (last use) $2e7 /--* t357 long [001472] ------------ t1472 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000366] H-----?----- t366 = CNS_INT(h) long 0xd1ffab1e global ptr $4f /--* t366 long [001473] ------------ t1473 = * PUTARG_REG long REG rdx /--* t1472 long arg0 in rcx +--* t1473 long arg1 in rdx N005 ( 17, 18) [000367] --C-G-?----- t367 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $325 /--* t367 long N007 ( 21, 21) [001157] DA--G------- * STORE_LCL_VAR long V25 tmp11 d:2 lowering store lcl var/field (after): N003 ( 1, 1) [000357] ------?----- t357 = LCL_VAR long V24 tmp10 u:1 (last use) $2e7 /--* t357 long [001472] ------------ t1472 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000366] H-----?----- t366 = CNS_INT(h) long 0xd1ffab1e global ptr $4f /--* t366 long [001473] ------------ t1473 = * PUTARG_REG long REG rdx /--* t1472 long arg0 in rcx +--* t1473 long arg1 in rdx N005 ( 17, 18) [000367] --C-G-?----- t367 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $325 /--* t367 long N007 ( 21, 21) [001157] DA--G------- * STORE_LCL_VAR long V25 tmp11 d:2 lowering store lcl var/field (before): N001 ( 0, 0) [001243] ------------ t1243 = PHI_ARG long V25 tmp11 u:3 N002 ( 0, 0) [001242] ------------ t1242 = PHI_ARG long V25 tmp11 u:2 $325 /--* t1243 long +--* t1242 long N003 ( 0, 0) [001198] ------------ t1198 = * PHI long /--* t1198 long N005 ( 0, 0) [001199] DA---------- * STORE_LCL_VAR long V25 tmp11 d:1 lowering store lcl var/field (after): N001 ( 0, 0) [001243] ------------ t1243 = PHI_ARG long V25 tmp11 u:3 N002 ( 0, 0) [001242] ------------ t1242 = PHI_ARG long V25 tmp11 u:2 $325 /--* t1243 long +--* t1242 long N003 ( 0, 0) [001198] ------------ t1198 = * PHI long /--* t1198 long N005 ( 0, 0) [001199] DA---------- * STORE_LCL_VAR long V25 tmp11 d:1 lowering call (before): N002 ( 3, 2) [000382] ------------ t382 = LCL_VAR long V25 tmp11 u:1 (last use) $344 /--* t382 long arg0 in rcx N003 ( 17, 8) [000352] --CXG------- t352 = * CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default $223 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000866] ----------L- * ARGPLACE long $344 late: ====== lowering arg : N002 ( 3, 2) [000382] ------------ * LCL_VAR long V25 tmp11 u:1 (last use) $344 new node is : [001474] ------------ * PUTARG_REG long REG rcx lowering call (after): N002 ( 3, 2) [000382] ------------ t382 = LCL_VAR long V25 tmp11 u:1 (last use) $344 /--* t382 long [001474] ------------ t1474 = * PUTARG_REG long REG rcx /--* t1474 long arg0 in rcx N003 ( 17, 8) [000352] --CXG------- t352 = * CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default $223 lowering store lcl var/field (before): N002 ( 3, 2) [000382] ------------ t382 = LCL_VAR long V25 tmp11 u:1 (last use) $344 /--* t382 long [001474] ------------ t1474 = * PUTARG_REG long REG rcx /--* t1474 long arg0 in rcx N003 ( 17, 8) [000352] --CXG------- t352 = * CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default $223 /--* t352 ref N005 ( 17, 8) [000386] DA-XG------- * STORE_LCL_VAR ref V12 loc8 d:1 lowering store lcl var/field (after): N002 ( 3, 2) [000382] ------------ t382 = LCL_VAR long V25 tmp11 u:1 (last use) $344 /--* t382 long [001474] ------------ t1474 = * PUTARG_REG long REG rcx /--* t1474 long arg0 in rcx N003 ( 17, 8) [000352] --CXG------- t352 = * CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default $223 /--* t352 ref N005 ( 17, 8) [000386] DA-XG------- * STORE_LCL_VAR ref V12 loc8 d:1 lowering store lcl var/field (before): N001 ( 0, 0) [001238] ------------ t1238 = PHI_ARG int V07 loc3 u:6 N002 ( 0, 0) [001235] ------------ t1235 = PHI_ARG int V07 loc3 u:1 $c0 /--* t1238 int +--* t1235 int N003 ( 0, 0) [001177] ------------ t1177 = * PHI int /--* t1177 int N005 ( 0, 0) [001178] DA---------- * STORE_LCL_VAR int V07 loc3 d:5 lowering store lcl var/field (after): N001 ( 0, 0) [001238] ------------ t1238 = PHI_ARG int V07 loc3 u:6 N002 ( 0, 0) [001235] ------------ t1235 = PHI_ARG int V07 loc3 u:1 $c0 /--* t1238 int +--* t1235 int N003 ( 0, 0) [001177] ------------ t1177 = * PHI int /--* t1177 int N005 ( 0, 0) [001178] DA---------- * STORE_LCL_VAR int V07 loc3 d:5 lowering store lcl var/field (before): N001 ( 0, 0) [001239] ------------ t1239 = PHI_ARG int V09 loc5 u:5 N002 ( 0, 0) [001236] ------------ t1236 = PHI_ARG int V09 loc5 u:1 /--* t1239 int +--* t1236 int N003 ( 0, 0) [001174] ------------ t1174 = * PHI int /--* t1174 int N005 ( 0, 0) [001175] DA---------- * STORE_LCL_VAR int V09 loc5 d:4 lowering store lcl var/field (after): N001 ( 0, 0) [001239] ------------ t1239 = PHI_ARG int V09 loc5 u:5 N002 ( 0, 0) [001236] ------------ t1236 = PHI_ARG int V09 loc5 u:1 /--* t1239 int +--* t1236 int N003 ( 0, 0) [001174] ------------ t1174 = * PHI int /--* t1174 int N005 ( 0, 0) [001175] DA---------- * STORE_LCL_VAR int V09 loc5 d:4 Addressing mode: Base N001 ( 1, 1) [000388] ------------ * LCL_VAR ref V04 loc0 u:1 + 8 Removing unused node: [001445] -c---------- * CNS_INT long 8 New addressing mode node: [001446] ------------ * LEA(b+8) ref lowering store lcl var/field (before): N001 ( 1, 1) [000388] ------------ t388 = LCL_VAR ref V04 loc0 u:1 /--* t388 ref [001446] -c---------- t1446 = * LEA(b+8) ref /--* t1446 ref N002 ( 3, 3) [000389] ---X-------- t389 = * IND int /--* t389 int N004 ( 3, 3) [001316] DA-X-------- * STORE_LCL_VAR int V76 cse11 lowering store lcl var/field (after): N001 ( 1, 1) [000388] ------------ t388 = LCL_VAR ref V04 loc0 u:1 /--* t388 ref [001446] -c---------- t1446 = * LEA(b+8) ref /--* t1446 ref N002 ( 3, 3) [000389] ---X-------- t389 = * IND int /--* t389 int N004 ( 3, 3) [001316] DA-X-------- * STORE_LCL_VAR int V76 cse11 lowering store lcl var/field (before): N002 ( 1, 1) [000870] ------------ t870 = LCL_VAR int V09 loc5 u:4 $3c2 /--* t870 int N003 ( 2, 3) [000873] ------------ t873 = * CAST long <- int $326 N004 ( 1, 1) [000880] -c---------- t880 = CNS_INT long 3 $24b /--* t873 long +--* t880 long N005 ( 7, 7) [000881] ------------ t881 = * MUL long $327 /--* t881 long N007 ( 7, 7) [001276] DA---------- * STORE_LCL_VAR long V70 cse5 d:1 lowering store lcl var/field (after): N002 ( 1, 1) [000870] ------------ t870 = LCL_VAR int V09 loc5 u:4 $3c2 /--* t870 int N003 ( 2, 3) [000873] ------------ t873 = * CAST long <- int $326 N004 ( 1, 1) [000880] -c---------- t880 = CNS_INT long 3 $24b /--* t873 long +--* t880 long N005 ( 7, 7) [000881] ------------ t881 = * MUL long $327 /--* t881 long N007 ( 7, 7) [001276] DA---------- * STORE_LCL_VAR long V70 cse5 d:1 Addressing mode: Base N001 ( 1, 1) [000869] ------------ * LCL_VAR ref V04 loc0 u:1 + Index * 8 + 16 N008 ( 1, 1) [001277] ------------ * LCL_VAR long V70 cse5 u:1 $327 Removing unused node: N013 ( 10, 10) [000877] -------N---- * ADD long $329 Removing unused node: N012 ( 1, 1) [000876] -c---------- * CNS_INT long 16 Fseq[#FirstElem] $241 Removing unused node: N011 ( 9, 9) [000875] -------N---- * LSH long $328 Removing unused node: N010 ( 1, 1) [000874] -c-----N---- * CNS_INT long 3 $24b New addressing mode node: N014 ( 11, 11) [000878] -------N---- * LEA(b+(i*8)+16) byref lowering store lcl var/field (before): N001 ( 1, 1) [000869] ------------ t869 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000870] ------------ t870 = LCL_VAR int V09 loc5 u:4 $3c2 /--* t870 int N003 ( 2, 3) [000873] ------------ t873 = * CAST long <- int $326 N004 ( 1, 1) [000880] -c---------- t880 = CNS_INT long 3 $24b /--* t873 long +--* t880 long N005 ( 7, 7) [000881] ------------ t881 = * MUL long $327 /--* t881 long N007 ( 7, 7) [001276] DA---------- * STORE_LCL_VAR long V70 cse5 d:1 N008 ( 1, 1) [001277] ------------ t1277 = LCL_VAR long V70 cse5 u:1 $327 /--* t869 ref +--* t1277 long N014 ( 11, 11) [000878] -------N---- t878 = * LEA(b+(i*8)+16) byref /--* t878 byref N018 ( 23, 23) [001249] DA--G------- * STORE_LCL_VAR byref V65 cse0 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000869] ------------ t869 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000870] ------------ t870 = LCL_VAR int V09 loc5 u:4 $3c2 /--* t870 int N003 ( 2, 3) [000873] ------------ t873 = * CAST long <- int $326 N004 ( 1, 1) [000880] -c---------- t880 = CNS_INT long 3 $24b /--* t873 long +--* t880 long N005 ( 7, 7) [000881] ------------ t881 = * MUL long $327 /--* t881 long N007 ( 7, 7) [001276] DA---------- * STORE_LCL_VAR long V70 cse5 d:1 N008 ( 1, 1) [001277] ------------ t1277 = LCL_VAR long V70 cse5 u:1 $327 /--* t869 ref +--* t1277 long N014 ( 11, 11) [000878] -------N---- t878 = * LEA(b+(i*8)+16) byref /--* t878 byref N018 ( 23, 23) [001249] DA--G------- * STORE_LCL_VAR byref V65 cse0 d:1 Addressing mode: Base N019 ( 1, 1) [001250] ------------ * LCL_VAR byref V65 cse0 u:1 + 16 Removing unused node: N021 ( 1, 1) [000867] -c---------- * CNS_INT long 16 field offset Fseq[hashCode] $241 New addressing mode node: N022 ( 25, 25) [000868] ------------ * LEA(b+16) byref Addressing mode: Base N004 ( 1, 1) [000883] ------------ * LCL_VAR ref V04 loc0 u:1 + Index * 8 + 16 N005 ( 1, 1) [001279] ------------ * LCL_VAR long V70 cse5 u:1 $327 Removing unused node: N009 ( 3, 3) [000891] -------N---- * ADD long $329 Removing unused node: N008 ( 1, 1) [000890] -c---------- * CNS_INT long 16 Fseq[#FirstElem] $241 Removing unused node: N007 ( 2, 2) [000889] -------N---- * LSH long $328 Removing unused node: N006 ( 1, 1) [000888] -c-----N---- * CNS_INT long 3 $24b New addressing mode node: N010 ( 4, 4) [000892] ------------ * LEA(b+(i*8)+16) byref Addressing mode: Base N017 ( 3, 2) [000902] #--X-------- * IND long $463 + 72 Removing unused node: N018 ( 1, 1) [000903] -c---------- * CNS_INT int 72 $c9 New addressing mode node: N019 ( 4, 3) [000904] ------------ * LEA(b+72) long Addressing mode: Base N020 ( 6, 5) [000905] #--X-------- * IND long $465 + 32 Removing unused node: N021 ( 1, 1) [000906] -c---------- * CNS_INT int 32 $d2 New addressing mode node: N022 ( 7, 6) [000907] ------------ * LEA(b+32) long lowering call (before): N004 ( 1, 1) [000883] ------------ t883 = LCL_VAR ref V04 loc0 u:1 N005 ( 1, 1) [001279] ------------ t1279 = LCL_VAR long V70 cse5 u:1 $327 /--* t883 ref +--* t1279 long N010 ( 4, 4) [000892] -c---------- t892 = * LEA(b+(i*8)+16) byref /--* t892 byref N013 ( 12, 11) [000897] *---G--N---- t897 = * IND ref N014 ( 1, 1) [000418] ------------ t418 = LCL_VAR ref V12 loc8 u:1 $223 N015 ( 1, 1) [000424] ------------ t424 = LCL_VAR ref V01 arg1 u:1 $101 N016 ( 1, 1) [000901] ------------ t901 = LCL_VAR ref V12 loc8 u:1 $223 /--* t901 ref N017 ( 3, 2) [000902] #--X-------- t902 = * IND long $463 /--* t902 long N019 ( 4, 3) [000904] -c---------- t904 = * LEA(b+72) long /--* t904 long N020 ( 6, 5) [000905] #--X-------- t905 = * IND long $465 /--* t905 long N022 ( 7, 6) [000907] -c---------- t907 = * LEA(b+32) long /--* t907 long N023 ( 9, 8) [000908] n--X-------- t908 = * IND long /--* t897 ref arg1 in rdx +--* t418 ref this in rcx +--* t424 ref arg2 in r8 +--* t908 long control expr N024 ( 43, 32) [000425] --CXG------- t425 = * CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals $581 objp: ====== lowering arg : N001 ( 0, 0) [000899] ----------L- * ARGPLACE ref $4c1 args: ====== lowering arg : N002 ( 0, 0) [000898] ----------L- * ARGPLACE ref $223 lowering arg : N003 ( 0, 0) [000900] ----------L- * ARGPLACE ref late: ====== lowering arg : N013 ( 12, 11) [000897] *---G--N---- * IND ref new node is : [001475] ----G------- * PUTARG_REG ref REG rdx lowering arg : N014 ( 1, 1) [000418] ------------ * LCL_VAR ref V12 loc8 u:1 $223 new node is : [001476] ------------ * PUTARG_REG ref REG rcx lowering arg : N015 ( 1, 1) [000424] ------------ * LCL_VAR ref V01 arg1 u:1 $101 new node is : [001477] ------------ * PUTARG_REG ref REG r8 lowering call (after): N004 ( 1, 1) [000883] ------------ t883 = LCL_VAR ref V04 loc0 u:1 N005 ( 1, 1) [001279] ------------ t1279 = LCL_VAR long V70 cse5 u:1 $327 /--* t883 ref +--* t1279 long N010 ( 4, 4) [000892] -c---------- t892 = * LEA(b+(i*8)+16) byref /--* t892 byref N013 ( 12, 11) [000897] *---G--N---- t897 = * IND ref /--* t897 ref [001475] ----G------- t1475 = * PUTARG_REG ref REG rdx N014 ( 1, 1) [000418] ------------ t418 = LCL_VAR ref V12 loc8 u:1 $223 /--* t418 ref [001476] ------------ t1476 = * PUTARG_REG ref REG rcx N015 ( 1, 1) [000424] ------------ t424 = LCL_VAR ref V01 arg1 u:1 $101 /--* t424 ref [001477] ------------ t1477 = * PUTARG_REG ref REG r8 N016 ( 1, 1) [000901] ------------ t901 = LCL_VAR ref V12 loc8 u:1 $223 /--* t901 ref N017 ( 3, 2) [000902] #--X-------- t902 = * IND long $463 /--* t902 long N019 ( 4, 3) [000904] -c---------- t904 = * LEA(b+72) long /--* t904 long N020 ( 6, 5) [000905] #--X-------- t905 = * IND long $465 /--* t905 long N022 ( 7, 6) [000907] -c---------- t907 = * LEA(b+32) long /--* t907 long N023 ( 9, 8) [000908] nc-X-------- t908 = * IND long REG NA /--* t1475 ref arg1 in rdx +--* t1476 ref this in rcx +--* t1477 ref arg2 in r8 +--* t908 long control expr N024 ( 43, 32) [000425] --CXG------- t425 = * CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals $581 Addressing mode: Base N001 ( 1, 1) [001252] ------------ * LCL_VAR byref V65 cse0 u:1 $82 + 20 Removing unused node: N002 ( 1, 1) [000931] -c---------- * CNS_INT long 20 field offset Fseq[next] $24c New addressing mode node: N003 ( 2, 2) [000932] ------------ * LEA(b+20) byref lowering store lcl var/field (before): N001 ( 1, 1) [001252] ------------ t1252 = LCL_VAR byref V65 cse0 u:1 $82 /--* t1252 byref N003 ( 2, 2) [000932] -c---------- t932 = * LEA(b+20) byref /--* t932 byref N004 ( 4, 4) [000404] *--XG------- t404 = * IND int /--* t404 int N006 ( 4, 4) [000406] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:5 lowering store lcl var/field (after): N001 ( 1, 1) [001252] ------------ t1252 = LCL_VAR byref V65 cse0 u:1 $82 /--* t1252 byref N003 ( 2, 2) [000932] -c---------- t932 = * LEA(b+20) byref /--* t932 byref N004 ( 4, 4) [000404] *--XG------- t404 = * IND int /--* t404 int N006 ( 4, 4) [000406] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:5 lowering store lcl var/field (before): N001 ( 1, 1) [000407] ------------ t407 = LCL_VAR int V07 loc3 u:5 (last use) $3c1 N002 ( 1, 1) [000408] -c---------- t408 = CNS_INT int 1 $c1 /--* t407 int +--* t408 int N003 ( 3, 3) [000409] ------------ t409 = * ADD int $605 /--* t409 int N005 ( 3, 3) [000411] DA---------- * STORE_LCL_VAR int V07 loc3 d:6 lowering store lcl var/field (after): N001 ( 1, 1) [000407] ------------ t407 = LCL_VAR int V07 loc3 u:5 (last use) $3c1 N002 ( 1, 1) [000408] -c---------- t408 = CNS_INT int 1 $c1 /--* t407 int +--* t408 int N003 ( 3, 3) [000409] ------------ t409 = * ADD int $605 /--* t409 int N005 ( 3, 3) [000411] DA---------- * STORE_LCL_VAR int V07 loc3 d:6 Addressing mode: Base N001 ( 1, 1) [001253] ------------ * LCL_VAR byref V65 cse0 u:1 $82 + 8 Removing unused node: N002 ( 1, 1) [000910] -c---------- * CNS_INT long 8 field offset Fseq[value] $240 New addressing mode node: N003 ( 2, 2) [000911] ------------ * LEA(b+8) byref lowering GT_RETURN N002 ( 2, 2) [000811] ------------ * RETURN int $1f3 ============lowering store lcl var/field (before): N001 ( 0, 0) [001229] ------------ t1229 = PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [001218] ------------ t1218 = PHI_ARG int V07 loc3 u:1 $c0 /--* t1229 int +--* t1218 int N003 ( 0, 0) [001207] ------------ t1207 = * PHI int /--* t1207 int N005 ( 0, 0) [001208] DA---------- * STORE_LCL_VAR int V07 loc3 d:3 lowering store lcl var/field (after): N001 ( 0, 0) [001229] ------------ t1229 = PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [001218] ------------ t1218 = PHI_ARG int V07 loc3 u:1 $c0 /--* t1229 int +--* t1218 int N003 ( 0, 0) [001207] ------------ t1207 = * PHI int /--* t1207 int N005 ( 0, 0) [001208] DA---------- * STORE_LCL_VAR int V07 loc3 d:3 lowering store lcl var/field (before): N001 ( 0, 0) [001230] ------------ t1230 = PHI_ARG int V09 loc5 u:3 N002 ( 0, 0) [001219] ------------ t1219 = PHI_ARG int V09 loc5 u:1 /--* t1230 int +--* t1219 int N003 ( 0, 0) [001204] ------------ t1204 = * PHI int /--* t1204 int N005 ( 0, 0) [001205] DA---------- * STORE_LCL_VAR int V09 loc5 d:2 lowering store lcl var/field (after): N001 ( 0, 0) [001230] ------------ t1230 = PHI_ARG int V09 loc5 u:3 N002 ( 0, 0) [001219] ------------ t1219 = PHI_ARG int V09 loc5 u:1 /--* t1230 int +--* t1219 int N003 ( 0, 0) [001204] ------------ t1204 = * PHI int /--* t1204 int N005 ( 0, 0) [001205] DA---------- * STORE_LCL_VAR int V09 loc5 d:2 Addressing mode: Base N001 ( 1, 1) [000063] ------------ * LCL_VAR ref V04 loc0 u:1 + 8 Removing unused node: [001447] -c---------- * CNS_INT long 8 New addressing mode node: [001448] ------------ * LEA(b+8) ref lowering store lcl var/field (before): N001 ( 1, 1) [000063] ------------ t63 = LCL_VAR ref V04 loc0 u:1 /--* t63 ref [001448] -c---------- t1448 = * LEA(b+8) ref /--* t1448 ref N002 ( 3, 3) [000064] ---X-------- t64 = * IND int /--* t64 int N004 ( 3, 3) [001323] DA-X-------- * STORE_LCL_VAR int V76 cse11 lowering store lcl var/field (after): N001 ( 1, 1) [000063] ------------ t63 = LCL_VAR ref V04 loc0 u:1 /--* t63 ref [001448] -c---------- t1448 = * LEA(b+8) ref /--* t1448 ref N002 ( 3, 3) [000064] ---X-------- t64 = * IND int /--* t64 int N004 ( 3, 3) [001323] DA-X-------- * STORE_LCL_VAR int V76 cse11 lowering store lcl var/field (before): N002 ( 1, 1) [000950] ------------ t950 = LCL_VAR int V09 loc5 u:2 $3c4 /--* t950 int N003 ( 2, 3) [000953] ------------ t953 = * CAST long <- int $6e1 N004 ( 1, 1) [000960] -c---------- t960 = CNS_INT long 3 $24b /--* t953 long +--* t960 long N005 ( 7, 7) [000961] ------------ t961 = * MUL long $6e2 /--* t961 long N007 ( 7, 7) [001281] DA---------- * STORE_LCL_VAR long V71 cse6 d:1 lowering store lcl var/field (after): N002 ( 1, 1) [000950] ------------ t950 = LCL_VAR int V09 loc5 u:2 $3c4 /--* t950 int N003 ( 2, 3) [000953] ------------ t953 = * CAST long <- int $6e1 N004 ( 1, 1) [000960] -c---------- t960 = CNS_INT long 3 $24b /--* t953 long +--* t960 long N005 ( 7, 7) [000961] ------------ t961 = * MUL long $6e2 /--* t961 long N007 ( 7, 7) [001281] DA---------- * STORE_LCL_VAR long V71 cse6 d:1 Addressing mode: Base N001 ( 1, 1) [000949] ------------ * LCL_VAR ref V04 loc0 u:1 + Index * 8 + 16 N008 ( 1, 1) [001282] ------------ * LCL_VAR long V71 cse6 u:1 $6e2 Removing unused node: N013 ( 10, 10) [000957] -------N---- * ADD long $6e4 Removing unused node: N012 ( 1, 1) [000956] -c---------- * CNS_INT long 16 Fseq[#FirstElem] $241 Removing unused node: N011 ( 9, 9) [000955] -------N---- * LSH long $6e3 Removing unused node: N010 ( 1, 1) [000954] -c-----N---- * CNS_INT long 3 $24b New addressing mode node: N014 ( 11, 11) [000958] -------N---- * LEA(b+(i*8)+16) byref lowering store lcl var/field (before): N001 ( 1, 1) [000949] ------------ t949 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000950] ------------ t950 = LCL_VAR int V09 loc5 u:2 $3c4 /--* t950 int N003 ( 2, 3) [000953] ------------ t953 = * CAST long <- int $6e1 N004 ( 1, 1) [000960] -c---------- t960 = CNS_INT long 3 $24b /--* t953 long +--* t960 long N005 ( 7, 7) [000961] ------------ t961 = * MUL long $6e2 /--* t961 long N007 ( 7, 7) [001281] DA---------- * STORE_LCL_VAR long V71 cse6 d:1 N008 ( 1, 1) [001282] ------------ t1282 = LCL_VAR long V71 cse6 u:1 $6e2 /--* t949 ref +--* t1282 long N014 ( 11, 11) [000958] -------N---- t958 = * LEA(b+(i*8)+16) byref /--* t958 byref N018 ( 23, 23) [001255] DA--G------- * STORE_LCL_VAR byref V66 cse1 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000949] ------------ t949 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000950] ------------ t950 = LCL_VAR int V09 loc5 u:2 $3c4 /--* t950 int N003 ( 2, 3) [000953] ------------ t953 = * CAST long <- int $6e1 N004 ( 1, 1) [000960] -c---------- t960 = CNS_INT long 3 $24b /--* t953 long +--* t960 long N005 ( 7, 7) [000961] ------------ t961 = * MUL long $6e2 /--* t961 long N007 ( 7, 7) [001281] DA---------- * STORE_LCL_VAR long V71 cse6 d:1 N008 ( 1, 1) [001282] ------------ t1282 = LCL_VAR long V71 cse6 u:1 $6e2 /--* t949 ref +--* t1282 long N014 ( 11, 11) [000958] -------N---- t958 = * LEA(b+(i*8)+16) byref /--* t958 byref N018 ( 23, 23) [001255] DA--G------- * STORE_LCL_VAR byref V66 cse1 d:1 Addressing mode: Base N019 ( 1, 1) [001256] ------------ * LCL_VAR byref V66 cse1 u:1 + 16 Removing unused node: N021 ( 1, 1) [000947] -c---------- * CNS_INT long 16 field offset Fseq[hashCode] $241 New addressing mode node: N022 ( 25, 25) [000948] ------------ * LEA(b+16) byref Addressing mode: Base N001 ( 1, 1) [000963] ------------ * LCL_VAR ref V04 loc0 u:1 + Index * 8 + 16 N002 ( 1, 1) [001284] ------------ * LCL_VAR long V71 cse6 u:1 $6e2 Removing unused node: N006 ( 3, 3) [000971] -------N---- * ADD long $6e4 Removing unused node: N005 ( 1, 1) [000970] -c---------- * CNS_INT long 16 Fseq[#FirstElem] $241 Removing unused node: N004 ( 2, 2) [000969] -------N---- * LSH long $6e3 Removing unused node: N003 ( 1, 1) [000968] -c-----N---- * CNS_INT long 3 $24b New addressing mode node: N007 ( 4, 4) [000972] ------------ * LEA(b+(i*8)+16) byref lowering store lcl var/field (before): N001 ( 1, 1) [000963] ------------ t963 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [001284] ------------ t1284 = LCL_VAR long V71 cse6 u:1 $6e2 /--* t963 ref +--* t1284 long N007 ( 4, 4) [000972] -c---------- t972 = * LEA(b+(i*8)+16) byref /--* t972 byref N010 ( 12, 11) [000977] *---G--N---- t977 = * IND ref /--* t977 ref N012 ( 12, 11) [000246] DA--G------- * STORE_LCL_VAR ref V17 tmp3 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000963] ------------ t963 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [001284] ------------ t1284 = LCL_VAR long V71 cse6 u:1 $6e2 /--* t963 ref +--* t1284 long N007 ( 4, 4) [000972] -c---------- t972 = * LEA(b+(i*8)+16) byref /--* t972 byref N010 ( 12, 11) [000977] *---G--N---- t977 = * IND ref /--* t977 ref N012 ( 12, 11) [000246] DA--G------- * STORE_LCL_VAR ref V17 tmp3 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000241] !----------- t241 = LCL_VAR ref V00 this u:1 $100 /--* t241 ref N002 ( 3, 2) [000242] #----O------ t242 = * IND long $2e8 /--* t242 long N004 ( 3, 3) [000244] DA---O------ * STORE_LCL_VAR long V16 tmp2 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000241] !----------- t241 = LCL_VAR ref V00 this u:1 $100 /--* t241 ref N002 ( 3, 2) [000242] #----O------ t242 = * IND long $2e8 /--* t242 long N004 ( 3, 3) [000244] DA---O------ * STORE_LCL_VAR long V16 tmp2 d:1 Addressing mode: Base N001 ( 1, 1) [000249] ------------ * LCL_VAR long V16 tmp2 u:1 $2e7 + 56 Removing unused node: N002 ( 1, 1) [000250] -c---------- * CNS_INT long 56 $244 New addressing mode node: N003 ( 2, 2) [000251] ------------ * LEA(b+56) long Addressing mode: Base N005 ( 7, 6) [000253] #----------- * IND long $2ea + 48 Removing unused node: N006 ( 1, 1) [000254] -c---------- * CNS_INT long 48 $246 New addressing mode node: N007 ( 8, 7) [000255] ------------ * LEA(b+48) long lowering store lcl var/field (before): N001 ( 1, 1) [000249] ------------ t249 = LCL_VAR long V16 tmp2 u:1 $2e7 /--* t249 long N003 ( 2, 2) [000251] -c---------- t251 = * LEA(b+56) long /--* t251 long N004 ( 4, 4) [000252] #----------- t252 = * IND long $2e9 /--* t252 long N005 ( 7, 6) [000253] #----------- t253 = * IND long $2ea /--* t253 long N007 ( 8, 7) [000255] -c---------- t255 = * LEA(b+48) long /--* t255 long N008 ( 10, 9) [000259] n----------- t259 = * IND long /--* t259 long N010 ( 10, 9) [001261] DA---------- * STORE_LCL_VAR long V67 cse2 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000249] ------------ t249 = LCL_VAR long V16 tmp2 u:1 $2e7 /--* t249 long N003 ( 2, 2) [000251] -c---------- t251 = * LEA(b+56) long /--* t251 long N004 ( 4, 4) [000252] #----------- t252 = * IND long $2e9 /--* t252 long N005 ( 7, 6) [000253] #----------- t253 = * IND long $2ea /--* t253 long N007 ( 8, 7) [000255] -c---------- t255 = * LEA(b+48) long /--* t255 long N008 ( 10, 9) [000259] n----------- t259 = * IND long /--* t259 long N010 ( 10, 9) [001261] DA---------- * STORE_LCL_VAR long V67 cse2 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [001264] ------------ t1264 = LCL_VAR long V67 cse2 u:1 /--* t1264 long N003 ( 1, 3) [001165] DA---------- * STORE_LCL_VAR long V19 tmp5 d:3 lowering store lcl var/field (after): N001 ( 1, 1) [001264] ------------ t1264 = LCL_VAR long V67 cse2 u:1 /--* t1264 long N003 ( 1, 3) [001165] DA---------- * STORE_LCL_VAR long V19 tmp5 d:3 lowering call (before): N003 ( 1, 1) [000248] ------?----- t248 = LCL_VAR long V16 tmp2 u:1 (last use) $2e7 N004 ( 2, 10) [000260] H-----?----- t260 = CNS_INT(h) long 0xd1ffab1e global ptr $63 /--* t248 long arg0 in rcx +--* t260 long arg1 in rdx N005 ( 17, 18) [000261] --C-G-?----- t261 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $6e7 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000978] ------?---L- * ARGPLACE long $2e7 lowering arg : N002 ( 0, 0) [000979] ------?---L- * ARGPLACE long $63 late: ====== lowering arg : N003 ( 1, 1) [000248] ------?----- * LCL_VAR long V16 tmp2 u:1 (last use) $2e7 new node is : [001478] ------------ * PUTARG_REG long REG rcx lowering arg : N004 ( 2, 10) [000260] H-----?----- * CNS_INT(h) long 0xd1ffab1e global ptr $63 new node is : [001479] ------------ * PUTARG_REG long REG rdx lowering call (after): N003 ( 1, 1) [000248] ------?----- t248 = LCL_VAR long V16 tmp2 u:1 (last use) $2e7 /--* t248 long [001478] ------------ t1478 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000260] H-----?----- t260 = CNS_INT(h) long 0xd1ffab1e global ptr $63 /--* t260 long [001479] ------------ t1479 = * PUTARG_REG long REG rdx /--* t1478 long arg0 in rcx +--* t1479 long arg1 in rdx N005 ( 17, 18) [000261] --C-G-?----- t261 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $6e7 lowering store lcl var/field (before): N003 ( 1, 1) [000248] ------?----- t248 = LCL_VAR long V16 tmp2 u:1 (last use) $2e7 /--* t248 long [001478] ------------ t1478 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000260] H-----?----- t260 = CNS_INT(h) long 0xd1ffab1e global ptr $63 /--* t260 long [001479] ------------ t1479 = * PUTARG_REG long REG rdx /--* t1478 long arg0 in rcx +--* t1479 long arg1 in rdx N005 ( 17, 18) [000261] --C-G-?----- t261 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $6e7 /--* t261 long N007 ( 17, 18) [001167] DA--G------- * STORE_LCL_VAR long V19 tmp5 d:2 lowering store lcl var/field (after): N003 ( 1, 1) [000248] ------?----- t248 = LCL_VAR long V16 tmp2 u:1 (last use) $2e7 /--* t248 long [001478] ------------ t1478 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000260] H-----?----- t260 = CNS_INT(h) long 0xd1ffab1e global ptr $63 /--* t260 long [001479] ------------ t1479 = * PUTARG_REG long REG rdx /--* t1478 long arg0 in rcx +--* t1479 long arg1 in rdx N005 ( 17, 18) [000261] --C-G-?----- t261 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $6e7 /--* t261 long N007 ( 17, 18) [001167] DA--G------- * STORE_LCL_VAR long V19 tmp5 d:2 lowering store lcl var/field (before): N001 ( 0, 0) [001234] ------------ t1234 = PHI_ARG long V19 tmp5 u:3 N002 ( 0, 0) [001233] ------------ t1233 = PHI_ARG long V19 tmp5 u:2 $6e7 /--* t1234 long +--* t1233 long N003 ( 0, 0) [001210] ------------ t1210 = * PHI long /--* t1210 long N005 ( 0, 0) [001211] DA---------- * STORE_LCL_VAR long V19 tmp5 d:1 lowering store lcl var/field (after): N001 ( 0, 0) [001234] ------------ t1234 = PHI_ARG long V19 tmp5 u:3 N002 ( 0, 0) [001233] ------------ t1233 = PHI_ARG long V19 tmp5 u:2 $6e7 /--* t1234 long +--* t1233 long N003 ( 0, 0) [001210] ------------ t1210 = * PHI long /--* t1210 long N005 ( 0, 0) [001211] DA---------- * STORE_LCL_VAR long V19 tmp5 d:1 lowering call (before): N005 ( 1, 1) [000234] ------------ t234 = LCL_VAR ref V05 loc1 u:1 N006 ( 1, 1) [000980] ------------ t980 = LCL_VAR long V19 tmp5 u:1 r11 REG r11 $349 N007 ( 1, 1) [000247] ------------ t247 = LCL_VAR ref V17 tmp3 u:1 (last use) N008 ( 1, 1) [000258] ------------ t258 = LCL_VAR ref V01 arg1 u:1 $101 N009 ( 1, 1) [000279] ------------ t279 = LCL_VAR long V19 tmp5 u:1 (last use) $349 /--* t234 ref this in rcx +--* t980 long arg1 in r11 +--* t247 ref arg2 in rdx +--* t258 ref arg3 in r8 +--* t279 long calli tgt N010 ( 28, 14) [000280] --CXG------- t280 = * CALL ind stub int $1ef objp: ====== lowering arg : N001 ( 0, 0) [000981] ----------L- * ARGPLACE ref $843 args: ====== lowering arg : N002 ( 0, 0) [000982] ----------L- * ARGPLACE long lowering arg : N003 ( 0, 0) [000983] ----------L- * ARGPLACE ref $349 lowering arg : N004 ( 0, 0) [000984] ----------L- * ARGPLACE ref late: ====== lowering arg : N005 ( 1, 1) [000234] ------------ * LCL_VAR ref V05 loc1 u:1 new node is : [001480] ------------ * PUTARG_REG ref REG rcx lowering arg : N006 ( 1, 1) [000980] ------------ * LCL_VAR long V19 tmp5 u:1 r11 REG r11 $349 new node is : [001481] ------------ * PUTARG_REG long REG r11 lowering arg : N007 ( 1, 1) [000247] ------------ * LCL_VAR ref V17 tmp3 u:1 (last use) new node is : [001482] ------------ * PUTARG_REG ref REG rdx lowering arg : N008 ( 1, 1) [000258] ------------ * LCL_VAR ref V01 arg1 u:1 $101 new node is : [001483] ------------ * PUTARG_REG ref REG r8 lowering call (after): N005 ( 1, 1) [000234] ------------ t234 = LCL_VAR ref V05 loc1 u:1 /--* t234 ref [001480] ------------ t1480 = * PUTARG_REG ref REG rcx N006 ( 1, 1) [000980] ------------ t980 = LCL_VAR long V19 tmp5 u:1 r11 REG r11 $349 /--* t980 long [001481] ------------ t1481 = * PUTARG_REG long REG r11 N007 ( 1, 1) [000247] ------------ t247 = LCL_VAR ref V17 tmp3 u:1 (last use) /--* t247 ref [001482] ------------ t1482 = * PUTARG_REG ref REG rdx N008 ( 1, 1) [000258] ------------ t258 = LCL_VAR ref V01 arg1 u:1 $101 /--* t258 ref [001483] ------------ t1483 = * PUTARG_REG ref REG r8 N009 ( 1, 1) [000279] ------------ t279 = LCL_VAR long V19 tmp5 u:1 (last use) $349 /--* t279 long [001484] Dc---------- t1484 = * IND long REG NA /--* t1480 ref this in rcx +--* t1481 long arg1 in r11 +--* t1482 ref arg2 in rdx +--* t1483 ref arg3 in r8 +--* t1484 long calli tgt N010 ( 28, 14) [000280] --CXG------- t280 = * CALL ind stub int $1ef Addressing mode: Base N001 ( 1, 1) [001258] ------------ * LCL_VAR byref V66 cse1 u:1 $91 + 8 Removing unused node: N002 ( 1, 1) [000986] -c---------- * CNS_INT long 8 field offset Fseq[value] $240 New addressing mode node: N003 ( 2, 2) [000987] ------------ * LEA(b+8) byref Addressing mode: Base N001 ( 1, 1) [001259] ------------ * LCL_VAR byref V66 cse1 u:1 $91 + 20 Removing unused node: N002 ( 1, 1) [001008] -c---------- * CNS_INT long 20 field offset Fseq[next] $24c New addressing mode node: N003 ( 2, 2) [001009] ------------ * LEA(b+20) byref lowering store lcl var/field (before): N001 ( 1, 1) [001259] ------------ t1259 = LCL_VAR byref V66 cse1 u:1 $91 /--* t1259 byref N003 ( 2, 2) [001009] -c---------- t1009 = * LEA(b+20) byref /--* t1009 byref N004 ( 4, 4) [000220] *--XG------- t220 = * IND int /--* t220 int N006 ( 4, 4) [000222] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:3 lowering store lcl var/field (after): N001 ( 1, 1) [001259] ------------ t1259 = LCL_VAR byref V66 cse1 u:1 $91 /--* t1259 byref N003 ( 2, 2) [001009] -c---------- t1009 = * LEA(b+20) byref /--* t1009 byref N004 ( 4, 4) [000220] *--XG------- t220 = * IND int /--* t220 int N006 ( 4, 4) [000222] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:3 lowering store lcl var/field (before): N001 ( 1, 1) [000223] ------------ t223 = LCL_VAR int V07 loc3 u:3 (last use) $3c3 N002 ( 1, 1) [000224] -c---------- t224 = CNS_INT int 1 $c1 /--* t223 int +--* t224 int N003 ( 3, 3) [000225] ------------ t225 = * ADD int $81a /--* t225 int N005 ( 3, 3) [000227] DA---------- * STORE_LCL_VAR int V07 loc3 d:4 lowering store lcl var/field (after): N001 ( 1, 1) [000223] ------------ t223 = LCL_VAR int V07 loc3 u:3 (last use) $3c3 N002 ( 1, 1) [000224] -c---------- t224 = CNS_INT int 1 $c1 /--* t223 int +--* t224 int N003 ( 3, 3) [000225] ------------ t225 = * ADD int $81a /--* t225 int N005 ( 3, 3) [000227] DA---------- * STORE_LCL_VAR int V07 loc3 d:4 lowering store lcl var/field (before): N001 ( 0, 0) [001237] ------------ t1237 = PHI_ARG int V07 loc3 u:5 $3c1 N002 ( 0, 0) [001228] ------------ t1228 = PHI_ARG int V07 loc3 u:3 $3c3 /--* t1237 int +--* t1228 int N003 ( 0, 0) [001180] ------------ t1180 = * PHI int /--* t1180 int N005 ( 0, 0) [001181] DA---------- * STORE_LCL_VAR int V07 loc3 d:2 lowering store lcl var/field (after): N001 ( 0, 0) [001237] ------------ t1237 = PHI_ARG int V07 loc3 u:5 $3c1 N002 ( 0, 0) [001228] ------------ t1228 = PHI_ARG int V07 loc3 u:3 $3c3 /--* t1237 int +--* t1228 int N003 ( 0, 0) [001180] ------------ t1180 = * PHI int /--* t1180 int N005 ( 0, 0) [001181] DA---------- * STORE_LCL_VAR int V07 loc3 d:2 Addressing mode: Base N001 ( 1, 1) [000067] ------------ * LCL_VAR ref V00 this u:1 $100 + 64 Removing unused node: N002 ( 1, 1) [001024] -c---------- * CNS_INT long 64 field offset Fseq[_freeCount] $245 New addressing mode node: N003 ( 2, 2) [001025] ------------ * LEA(b+64) byref Addressing mode: Base N001 ( 1, 1) [000171] ------------ * LCL_VAR ref V00 this u:1 $100 + 60 Removing unused node: N002 ( 1, 1) [001026] -c---------- * CNS_INT long 60 field offset Fseq[_freeList] $24d New addressing mode node: N003 ( 2, 2) [001027] ------------ * LEA(b+60) byref lowering store lcl var/field (before): N001 ( 1, 1) [000171] ------------ t171 = LCL_VAR ref V00 this u:1 $100 /--* t171 ref N003 ( 2, 2) [001027] -c---------- t1027 = * LEA(b+60) byref /--* t1027 byref N004 ( 4, 4) [000172] n---GO------ t172 = * IND int /--* t172 int N006 ( 8, 7) [001306] DA--GO------ * STORE_LCL_VAR int V74 cse9 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000171] ------------ t171 = LCL_VAR ref V00 this u:1 $100 /--* t171 ref N003 ( 2, 2) [001027] -c---------- t1027 = * LEA(b+60) byref /--* t1027 byref N004 ( 4, 4) [000172] n---GO------ t172 = * IND int /--* t172 int N006 ( 8, 7) [001306] DA--GO------ * STORE_LCL_VAR int V74 cse9 d:1 lowering store lcl var/field (before): N007 ( 3, 2) [001307] ------------ t1307 = LCL_VAR int V74 cse9 u:1 /--* t1307 int N010 ( 15, 12) [000174] DA--GO------ * STORE_LCL_VAR int V10 loc6 d:3 lowering store lcl var/field (after): N007 ( 3, 2) [001307] ------------ t1307 = LCL_VAR int V74 cse9 u:1 /--* t1307 int N010 ( 15, 12) [000174] DA--GO------ * STORE_LCL_VAR int V10 loc6 d:3 lowering store lcl var/field (before): N001 ( 3, 2) [001309] ------------ t1309 = LCL_VAR int V74 cse9 u:1 /--* t1309 int N003 ( 3, 3) [001032] DA--G------- * STORE_LCL_VAR int V62 tmp48 d:1 lowering store lcl var/field (after): N001 ( 3, 2) [001309] ------------ t1309 = LCL_VAR int V74 cse9 u:1 /--* t1309 int N003 ( 3, 3) [001032] DA--G------- * STORE_LCL_VAR int V62 tmp48 d:1 Addressing mode: Base N007 ( 1, 1) [001030] ------------ * LCL_VAR ref V04 loc0 u:1 + Index * 8 + 36 N011 ( 7, 7) [001048] ------------ * MUL long Removing unused node: N021 ( 1, 1) [001028] -c---------- * CNS_INT long 20 field offset Fseq[next] $24c Removing unused node: N016 ( 10, 10) [001042] -------N---- * ADD byref $88 Removing unused node: N015 ( 9, 9) [001041] -------N---- * ADD long Removing unused node: N014 ( 1, 1) [001040] -c---------- * CNS_INT long 16 Fseq[#FirstElem] $241 Removing unused node: N013 ( 8, 8) [001039] -------N---- * LSH long Removing unused node: N012 ( 1, 1) [001038] -c-----N---- * CNS_INT long 3 $24b New addressing mode node: N022 ( 31, 34) [001029] ------------ * LEA(b+(i*8)+36) byref lowering store lcl var/field (before): N007 ( 1, 1) [001030] ------------ t1030 = LCL_VAR ref V04 loc0 u:1 N008 ( 1, 1) [001034] ------------ t1034 = LCL_VAR int V62 tmp48 u:1 (last use) /--* t1034 int N009 ( 2, 3) [001037] ------------ t1037 = * CAST long <- int N010 ( 1, 1) [001047] -c---------- t1047 = CNS_INT long 3 $24b /--* t1037 long +--* t1047 long N011 ( 7, 7) [001048] ------------ t1048 = * MUL long /--* t1030 ref +--* t1048 long N022 ( 31, 34) [001029] -c---------- t1029 = * LEA(b+(i*8)+36) byref /--* t1029 byref N023 ( 33, 36) [000181] *--XG------- t181 = * IND int /--* t181 int N024 ( 34, 37) [001050] ---XG------- t1050 = * NEG int N025 ( 1, 1) [000175] -c---------- t175 = CNS_INT int -3 $e1 /--* t1050 int +--* t175 int N026 ( 36, 39) [000182] ---XG------- t182 = * ADD int N027 ( 1, 1) [000183] -c---------- t183 = CNS_INT int -1 $c4 /--* t182 int +--* t183 int N028 ( 41, 41) [000184] ---XG------- t184 = * GE int /--* t184 int N030 ( 45, 44) [000688] DA-XG------- * STORE_LCL_VAR int V49 tmp35 d:1 lowering store lcl var/field (after): N007 ( 1, 1) [001030] ------------ t1030 = LCL_VAR ref V04 loc0 u:1 N008 ( 1, 1) [001034] ------------ t1034 = LCL_VAR int V62 tmp48 u:1 (last use) /--* t1034 int N009 ( 2, 3) [001037] ------------ t1037 = * CAST long <- int N010 ( 1, 1) [001047] -c---------- t1047 = CNS_INT long 3 $24b /--* t1037 long +--* t1047 long N011 ( 7, 7) [001048] ------------ t1048 = * MUL long /--* t1030 ref +--* t1048 long N022 ( 31, 34) [001029] -c---------- t1029 = * LEA(b+(i*8)+36) byref /--* t1029 byref N023 ( 33, 36) [000181] *--XG------- t181 = * IND int /--* t181 int N024 ( 34, 37) [001050] ---XG------- t1050 = * NEG int N025 ( 1, 1) [000175] -c---------- t175 = CNS_INT int -3 $e1 /--* t1050 int +--* t175 int N026 ( 36, 39) [000182] ---XG------- t182 = * ADD int N027 ( 1, 1) [000183] -c---------- t183 = CNS_INT int -1 $c4 /--* t182 int +--* t183 int N028 ( 41, 41) [000184] ---XG------- t184 = * GE int /--* t184 int N030 ( 45, 44) [000688] DA-XG------- * STORE_LCL_VAR int V49 tmp35 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [001300] ------------ t1300 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1300 ref N003 ( 5, 4) [000698] DA--G------- * STORE_LCL_VAR ref V50 tmp36 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [001300] ------------ t1300 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1300 ref N003 ( 5, 4) [000698] DA--G------- * STORE_LCL_VAR ref V50 tmp36 d:1 lowering call (before): N003 ( 2, 10) [001051] H----------- t1051 = CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" $5e /--* t1051 long N004 ( 4, 12) [001052] #---G------- t1052 = * IND ref $114 N005 ( 3, 2) [000695] ------------ t695 = LCL_VAR ref V50 tmp36 u:1 (last use) $105 /--* t1052 ref arg0 in rcx +--* t695 ref arg1 in rdx N006 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [001053] ----------L- * ARGPLACE ref $114 lowering arg : N002 ( 0, 0) [001054] ----------L- * ARGPLACE ref $105 late: ====== lowering arg : N004 ( 4, 12) [001052] #---G------- * IND ref $114 new node is : [001485] ----G------- * PUTARG_REG ref REG rcx lowering arg : N005 ( 3, 2) [000695] ------------ * LCL_VAR ref V50 tmp36 u:1 (last use) $105 new node is : [001486] ------------ * PUTARG_REG ref REG rdx lowering call (after): N003 ( 2, 10) [001051] H----------- t1051 = CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" $5e /--* t1051 long N004 ( 4, 12) [001052] #---G------- t1052 = * IND ref $114 /--* t1052 ref [001485] ----G------- t1485 = * PUTARG_REG ref REG rcx N005 ( 3, 2) [000695] ------------ t695 = LCL_VAR ref V50 tmp36 u:1 (last use) $105 /--* t695 ref [001486] ------------ t1486 = * PUTARG_REG ref REG rdx /--* t1485 ref arg0 in rcx +--* t1486 ref arg1 in rdx N006 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void Addressing mode: Base N005 ( 1, 1) [000193] ------------ * LCL_VAR ref V00 this u:1 $100 + 60 Removing unused node: N006 ( 1, 1) [001074] -c---------- * CNS_INT long 60 field offset Fseq[_freeList] $24d New addressing mode node: N007 ( 2, 2) [001075] ------------ * LEA(b+60) byref lowering store lcl var/field (before): N005 ( 1, 1) [000193] ------------ t193 = LCL_VAR ref V00 this u:1 $100 /--* t193 ref N007 ( 2, 2) [001075] -c---------- t1075 = * LEA(b+60) byref /--* t1075 byref N008 ( 4, 4) [000194] n---GO------ t194 = * IND int /--* t194 int N010 ( 4, 4) [001061] DA--GO------ * STORE_LCL_VAR int V63 tmp49 d:1 lowering store lcl var/field (after): N005 ( 1, 1) [000193] ------------ t193 = LCL_VAR ref V00 this u:1 $100 /--* t193 ref N007 ( 2, 2) [001075] -c---------- t1075 = * LEA(b+60) byref /--* t1075 byref N008 ( 4, 4) [000194] n---GO------ t194 = * IND int /--* t194 int N010 ( 4, 4) [001061] DA--GO------ * STORE_LCL_VAR int V63 tmp49 d:1 Addressing mode: Base N014 ( 1, 1) [001059] ------------ * LCL_VAR ref V04 loc0 u:1 + Index * 8 + 36 N018 ( 7, 7) [001077] ------------ * MUL long Removing unused node: N028 ( 1, 1) [001057] -c---------- * CNS_INT long 20 field offset Fseq[next] $24c Removing unused node: N023 ( 10, 10) [001071] -------N---- * ADD byref $8a Removing unused node: N022 ( 9, 9) [001070] -------N---- * ADD long Removing unused node: N021 ( 1, 1) [001069] -c---------- * CNS_INT long 16 Fseq[#FirstElem] $241 Removing unused node: N020 ( 8, 8) [001068] -------N---- * LSH long Removing unused node: N019 ( 1, 1) [001067] -c-----N---- * CNS_INT long 3 $24b New addressing mode node: N029 ( 32, 35) [001058] ------------ * LEA(b+(i*8)+36) byref Addressing mode: Base N001 ( 1, 1) [000190] ------------ * LCL_VAR ref V00 this u:1 $100 + 60 Removing unused node: N002 ( 1, 1) [001055] -c---------- * CNS_INT long 60 field offset Fseq[_freeList] $24d New addressing mode node: N003 ( 2, 2) [001056] ------------ * LEA(b+60) byref Lower of StoreInd didn't mark the node as self contained for reason: address mode is not supported N001 ( 1, 1) [000190] ------------ t190 = LCL_VAR ref V00 this u:1 $100 /--* t190 ref N003 ( 2, 2) [001056] ------------ t1056 = * LEA(b+60) byref N005 ( 1, 1) [000193] ------------ t193 = LCL_VAR ref V00 this u:1 $100 /--* t193 ref N007 ( 2, 2) [001075] -c---------- t1075 = * LEA(b+60) byref /--* t1075 byref N008 ( 4, 4) [000194] n---GO------ t194 = * IND int /--* t194 int N010 ( 4, 4) [001061] DA--GO------ * STORE_LCL_VAR int V63 tmp49 d:1 N011 ( 1, 1) [001062] ------------ t1062 = LCL_VAR int V63 tmp49 u:1 N012 ( 1, 1) [001330] ------------ t1330 = LCL_VAR int V76 cse11 /--* t1062 int +--* t1330 int N013 ( 6, 9) [001065] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void N014 ( 1, 1) [001059] ------------ t1059 = LCL_VAR ref V04 loc0 u:1 N015 ( 1, 1) [001063] ------------ t1063 = LCL_VAR int V63 tmp49 u:1 (last use) /--* t1063 int N016 ( 2, 3) [001066] ------------ t1066 = * CAST long <- int N017 ( 1, 1) [001076] -c---------- t1076 = CNS_INT long 3 $24b /--* t1066 long +--* t1076 long N018 ( 7, 7) [001077] ------------ t1077 = * MUL long /--* t1059 ref +--* t1077 long N029 ( 32, 35) [001058] -c---------- t1058 = * LEA(b+(i*8)+36) byref /--* t1058 byref N030 ( 34, 37) [000197] *--XGO------ t197 = * IND int /--* t197 int N031 ( 35, 38) [001079] ---XGO------ t1079 = * NEG int N032 ( 1, 1) [000191] -c---------- t191 = CNS_INT int -3 $e1 /--* t1079 int +--* t191 int N033 ( 37, 40) [000198] ---XGO------ t198 = * ADD int /--* t1056 byref +--* t198 int [001395] -A-XGO------ * STOREIND int Addressing mode: Base N001 ( 1, 1) [000202] ------------ * LCL_VAR ref V00 this u:1 $100 + 64 Removing unused node: N002 ( 1, 1) [001082] -c---------- * CNS_INT long 64 field offset Fseq[_freeCount] $245 New addressing mode node: N003 ( 2, 2) [001083] ------------ * LEA(b+64) byref Addressing mode: Base N007 ( 1, 1) [000201] ------------ * LCL_VAR ref V00 this u:1 $100 + 64 Removing unused node: N008 ( 1, 1) [001080] -c---------- * CNS_INT long 64 field offset Fseq[_freeCount] $245 New addressing mode node: N009 ( 2, 2) [001081] ------------ * LEA(b+64) byref Lower succesfully detected an assignment of the form: *addrMode BinOp= source N001 ( 1, 1) [000202] ------------ t202 = LCL_VAR ref V00 this u:1 $100 /--* t202 ref N003 ( 2, 2) [001083] -c---------- t1083 = * LEA(b+64) byref /--* t1083 byref N004 ( 4, 4) [000203] n---GO------ t203 = * IND int N005 ( 1, 1) [000204] -c---------- t204 = CNS_INT int -1 $c4 /--* t203 int +--* t204 int N006 ( 6, 6) [000205] ----GO------ t205 = * ADD int N007 ( 1, 1) [000201] ------------ t201 = LCL_VAR ref V00 this u:1 $100 /--* t201 ref N009 ( 2, 2) [001081] ------------ t1081 = * LEA(b+64) byref /--* t1081 byref +--* t205 int [001397] -A--GO------ * STOREIND int Addressing mode: Base N001 ( 1, 1) [000072] ------------ * LCL_VAR ref V00 this u:1 $100 + 56 Removing unused node: N002 ( 1, 1) [001084] -c---------- * CNS_INT long 56 field offset Fseq[_count] $244 New addressing mode node: N003 ( 2, 2) [001085] ------------ * LEA(b+56) byref lowering store lcl var/field (before): N001 ( 1, 1) [000072] ------------ t72 = LCL_VAR ref V00 this u:1 $100 /--* t72 ref N003 ( 2, 2) [001085] -c---------- t1085 = * LEA(b+56) byref /--* t1085 byref N004 ( 4, 4) [000073] n---GO------ t73 = * IND int /--* t73 int N006 ( 8, 7) [001311] DA--GO------ * STORE_LCL_VAR int V75 cse10 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000072] ------------ t72 = LCL_VAR ref V00 this u:1 $100 /--* t72 ref N003 ( 2, 2) [001085] -c---------- t1085 = * LEA(b+56) byref /--* t1085 byref N004 ( 4, 4) [000073] n---GO------ t73 = * IND int /--* t73 int N006 ( 8, 7) [001311] DA--GO------ * STORE_LCL_VAR int V75 cse10 d:1 lowering store lcl var/field (before): N007 ( 3, 2) [001312] ------------ t1312 = LCL_VAR int V75 cse10 u:1 /--* t1312 int N010 ( 15, 12) [000075] DA--GO------ * STORE_LCL_VAR int V13 loc9 d:1 lowering store lcl var/field (after): N007 ( 3, 2) [001312] ------------ t1312 = LCL_VAR int V75 cse10 u:1 /--* t1312 int N010 ( 15, 12) [000075] DA--GO------ * STORE_LCL_VAR int V13 loc9 d:1 lowering call (before): N003 ( 3, 2) [001314] ------------ t1314 = LCL_VAR int V75 cse10 u:1 /--* t1314 int arg0 in rcx N004 ( 17, 8) [000702] --CXG------- t702 = * CALL int System.Collections.HashHelpers.ExpandPrime $1d7 objp: ====== args: ====== lowering arg : N002 ( 0, 0) [001088] ----------L- * ARGPLACE int late: ====== lowering arg : N003 ( 3, 2) [001314] ------------ * LCL_VAR int V75 cse10 u:1 new node is : [001487] ------------ * PUTARG_REG int REG rcx lowering call (after): N003 ( 3, 2) [001314] ------------ t1314 = LCL_VAR int V75 cse10 u:1 /--* t1314 int [001487] ------------ t1487 = * PUTARG_REG int REG rcx /--* t1487 int arg0 in rcx N004 ( 17, 8) [000702] --CXG------- t702 = * CALL int System.Collections.HashHelpers.ExpandPrime $1d7 lowering store lcl var/field (before): N003 ( 3, 2) [001314] ------------ t1314 = LCL_VAR int V75 cse10 u:1 /--* t1314 int [001487] ------------ t1487 = * PUTARG_REG int REG rcx /--* t1487 int arg0 in rcx N004 ( 17, 8) [000702] --CXG------- t702 = * CALL int System.Collections.HashHelpers.ExpandPrime $1d7 /--* t702 int N006 ( 21, 11) [001090] DA-XG-----L- * STORE_LCL_VAR int V64 tmp50 d:1 lowering store lcl var/field (after): N003 ( 3, 2) [001314] ------------ t1314 = LCL_VAR int V75 cse10 u:1 /--* t1314 int [001487] ------------ t1487 = * PUTARG_REG int REG rcx /--* t1487 int arg0 in rcx N004 ( 17, 8) [000702] --CXG------- t702 = * CALL int System.Collections.HashHelpers.ExpandPrime $1d7 /--* t702 int N006 ( 21, 11) [001090] DA-XG-----L- * STORE_LCL_VAR int V64 tmp50 d:1 lowering call (before): N003 ( 3, 2) [001314] ------------ t1314 = LCL_VAR int V75 cse10 u:1 /--* t1314 int [001487] ------------ t1487 = * PUTARG_REG int REG rcx /--* t1487 int arg0 in rcx N004 ( 17, 8) [000702] --CXG------- t702 = * CALL int System.Collections.HashHelpers.ExpandPrime $1d7 /--* t702 int N006 ( 21, 11) [001090] DA-XG-----L- * STORE_LCL_VAR int V64 tmp50 d:1 N008 ( 3, 2) [001091] ------------ t1091 = LCL_VAR int V64 tmp50 u:1 (last use) $1d7 N009 ( 1, 1) [000163] ------------ t163 = LCL_VAR ref V00 this u:1 $100 N010 ( 1, 1) [000704] ------------ t704 = CNS_INT int 0 $c0 /--* t1091 int arg1 in rdx +--* t163 ref this in rcx +--* t704 int arg2 in r8 N011 ( 43, 24) [000705] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void objp: ====== lowering arg : N001 ( 0, 0) [001092] ----------L- * ARGPLACE ref $228 args: ====== lowering arg : N006 ( 21, 11) [001090] DA-XG-----L- * STORE_LCL_VAR int V64 tmp50 d:1 lowering arg : N007 ( 0, 0) [001093] ----------L- * ARGPLACE int $1d7 late: ====== lowering arg : N008 ( 3, 2) [001091] ------------ * LCL_VAR int V64 tmp50 u:1 (last use) $1d7 new node is : [001488] ------------ * PUTARG_REG int REG rdx lowering arg : N009 ( 1, 1) [000163] ------------ * LCL_VAR ref V00 this u:1 $100 new node is : [001489] ------------ * PUTARG_REG ref REG rcx lowering arg : N010 ( 1, 1) [000704] ------------ * CNS_INT int 0 $c0 new node is : [001490] ------------ * PUTARG_REG int REG r8 lowering call (after): N003 ( 3, 2) [001314] ------------ t1314 = LCL_VAR int V75 cse10 u:1 /--* t1314 int [001487] ------------ t1487 = * PUTARG_REG int REG rcx /--* t1487 int arg0 in rcx N004 ( 17, 8) [000702] --CXG------- t702 = * CALL int System.Collections.HashHelpers.ExpandPrime $1d7 /--* t702 int N006 ( 21, 11) [001090] DA-XG-----L- * STORE_LCL_VAR int V64 tmp50 d:1 N008 ( 3, 2) [001091] ------------ t1091 = LCL_VAR int V64 tmp50 u:1 (last use) $1d7 /--* t1091 int [001488] ------------ t1488 = * PUTARG_REG int REG rdx N009 ( 1, 1) [000163] ------------ t163 = LCL_VAR ref V00 this u:1 $100 /--* t163 ref [001489] ------------ t1489 = * PUTARG_REG ref REG rcx N010 ( 1, 1) [000704] ------------ t704 = CNS_INT int 0 $c0 /--* t704 int [001490] ------------ t1490 = * PUTARG_REG int REG r8 /--* t1488 int arg1 in rdx +--* t1489 ref this in rcx +--* t1490 int arg2 in r8 N011 ( 43, 24) [000705] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void Addressing mode: Base N001 ( 1, 1) [000165] ------------ * LCL_VAR ref V00 this u:1 $100 + 8 Removing unused node: N002 ( 1, 1) [001094] -c---------- * CNS_INT long 8 field offset Fseq[_buckets] $240 New addressing mode node: N003 ( 2, 2) [001095] ------------ * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000165] ------------ t165 = LCL_VAR ref V00 this u:1 $100 /--* t165 ref N003 ( 2, 2) [001095] -c---------- t1095 = * LEA(b+8) byref /--* t1095 byref N004 ( 4, 4) [000709] n---GO------ t709 = * IND ref /--* t709 ref N006 ( 8, 7) [000711] DA--GO------ * STORE_LCL_VAR ref V52 tmp38 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000165] ------------ t165 = LCL_VAR ref V00 this u:1 $100 /--* t165 ref N003 ( 2, 2) [001095] -c---------- t1095 = * LEA(b+8) byref /--* t1095 byref N004 ( 4, 4) [000709] n---GO------ t709 = * IND ref /--* t709 ref N006 ( 8, 7) [000711] DA--GO------ * STORE_LCL_VAR ref V52 tmp38 d:1 Addressing mode: Base N001 ( 3, 2) [000713] ------------ * LCL_VAR ref V52 tmp38 u:1 + 8 Removing unused node: [001449] -c---------- * CNS_INT long 8 New addressing mode node: [001450] ------------ * LEA(b+8) ref lowering store lcl var/field (before): N001 ( 3, 2) [000713] ------------ t713 = LCL_VAR ref V52 tmp38 u:1 /--* t713 ref [001450] -c---------- t1450 = * LEA(b+8) ref /--* t1450 ref N002 ( 5, 4) [000714] ---X-------- t714 = * IND int /--* t714 int N004 ( 9, 7) [001286] DA-X-------- * STORE_LCL_VAR int V72 cse7 d:1 lowering store lcl var/field (after): N001 ( 3, 2) [000713] ------------ t713 = LCL_VAR ref V52 tmp38 u:1 /--* t713 ref [001450] -c---------- t1450 = * LEA(b+8) ref /--* t1450 ref N002 ( 5, 4) [000714] ---X-------- t714 = * IND int /--* t714 int N004 ( 9, 7) [001286] DA-X-------- * STORE_LCL_VAR int V72 cse7 d:1 lowering store lcl var/field (before): N005 ( 3, 2) [001287] ------------ t1287 = LCL_VAR int V72 cse7 u:1 /--* t1287 int N008 ( 12, 9) [000760] DA-X-------- * STORE_LCL_VAR int V53 tmp39 d:1 lowering store lcl var/field (after): N005 ( 3, 2) [001287] ------------ t1287 = LCL_VAR int V72 cse7 u:1 /--* t1287 int N008 ( 12, 9) [000760] DA-X-------- * STORE_LCL_VAR int V53 tmp39 d:1 Addressing mode: Base N001 ( 1, 1) [000715] ------------ * LCL_VAR ref V00 this u:1 $100 + 48 Removing unused node: N002 ( 1, 1) [001096] -c---------- * CNS_INT long 48 field offset Fseq[_fastModMultiplier] $246 New addressing mode node: N003 ( 2, 2) [001097] ------------ * LEA(b+48) byref lowering store lcl var/field (before): N001 ( 1, 1) [000715] ------------ t715 = LCL_VAR ref V00 this u:1 $100 /--* t715 ref N003 ( 2, 2) [001097] -c---------- t1097 = * LEA(b+48) byref /--* t1097 byref N004 ( 4, 4) [000716] n---GO------ t716 = * IND long /--* t716 long N006 ( 8, 7) [000762] DA--GO------ * STORE_LCL_VAR long V54 tmp40 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000715] ------------ t715 = LCL_VAR ref V00 this u:1 $100 /--* t715 ref N003 ( 2, 2) [001097] -c---------- t1097 = * LEA(b+48) byref /--* t1097 byref N004 ( 4, 4) [000716] n---GO------ t716 = * IND long /--* t716 long N006 ( 8, 7) [000762] DA--GO------ * STORE_LCL_VAR long V54 tmp40 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000728] ------------ t728 = LCL_VAR int V53 tmp39 u:1 N002 ( 1, 4) [000729] -c---------- t729 = CNS_INT int 0x7FFFFFFF $ce /--* t728 int +--* t729 int N003 ( 6, 6) [000730] N--------U-- t730 = * LE int /--* t730 int N005 ( 10, 9) [000773] DA---------- * STORE_LCL_VAR int V56 tmp42 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000728] ------------ t728 = LCL_VAR int V53 tmp39 u:1 N002 ( 1, 4) [000729] -c---------- t729 = CNS_INT int 0x7FFFFFFF $ce /--* t728 int +--* t729 int N003 ( 6, 6) [000730] N--------U-- t730 = * LE int /--* t730 int N005 ( 10, 9) [000773] DA---------- * STORE_LCL_VAR int V56 tmp42 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [001301] ------------ t1301 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1301 ref N003 ( 5, 4) [000783] DA--G------- * STORE_LCL_VAR ref V57 tmp43 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [001301] ------------ t1301 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1301 ref N003 ( 5, 4) [000783] DA--G------- * STORE_LCL_VAR ref V57 tmp43 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [001302] ------------ t1302 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1302 ref N003 ( 5, 4) [000785] DA--G------- * STORE_LCL_VAR ref V58 tmp44 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [001302] ------------ t1302 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1302 ref N003 ( 5, 4) [000785] DA--G------- * STORE_LCL_VAR ref V58 tmp44 d:1 lowering call (before): N003 ( 3, 2) [000779] ------------ t779 = LCL_VAR ref V58 tmp44 u:1 (last use) $105 N004 ( 3, 2) [000780] ------------ t780 = LCL_VAR ref V58 tmp44 u:1 (last use) $105 /--* t779 ref arg0 in rcx +--* t780 ref arg1 in rdx N005 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [001098] ----------L- * ARGPLACE ref $105 lowering arg : N002 ( 0, 0) [001099] ----------L- * ARGPLACE ref $105 late: ====== lowering arg : N003 ( 3, 2) [000779] ------------ * LCL_VAR ref V58 tmp44 u:1 (last use) $105 new node is : [001491] ------------ * PUTARG_REG ref REG rcx lowering arg : N004 ( 3, 2) [000780] ------------ * LCL_VAR ref V58 tmp44 u:1 (last use) $105 new node is : [001492] ------------ * PUTARG_REG ref REG rdx lowering call (after): N003 ( 3, 2) [000779] ------------ t779 = LCL_VAR ref V58 tmp44 u:1 (last use) $105 /--* t779 ref [001491] ------------ t1491 = * PUTARG_REG ref REG rcx N004 ( 3, 2) [000780] ------------ t780 = LCL_VAR ref V58 tmp44 u:1 (last use) $105 /--* t780 ref [001492] ------------ t1492 = * PUTARG_REG ref REG rdx /--* t1491 ref arg0 in rcx +--* t1492 ref arg1 in rdx N005 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void lowering store lcl var/field (before): N001 ( 3, 2) [000735] ------------ t735 = LCL_VAR long V54 tmp40 u:1 (last use) N002 ( 1, 1) [000166] ------------ t166 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t166 int N003 ( 2, 3) [000736] ---------U-- t736 = * CAST long <- ulong <- uint $310 /--* t735 long +--* t736 long N004 ( 9, 8) [000737] ------------ t737 = * MUL long N005 ( 1, 1) [000738] -c---------- t738 = CNS_INT int 32 $d2 /--* t737 long +--* t738 int N006 ( 11, 10) [000739] ------------ t739 = * RSZ long N007 ( 1, 1) [000741] -c---------- t741 = CNS_INT long 1 $247 /--* t739 long +--* t741 long N008 ( 13, 12) [000742] ------------ t742 = * ADD long N009 ( 1, 1) [000743] ------------ t743 = LCL_VAR int V53 tmp39 u:1 /--* t743 int N010 ( 2, 3) [000744] ---------U-- t744 = * CAST long <- ulong <- uint /--* t742 long +--* t744 long N011 ( 19, 18) [000745] ------------ t745 = * MUL long N012 ( 1, 1) [000746] -c---------- t746 = CNS_INT int 32 $d2 /--* t745 long +--* t746 int N013 ( 21, 20) [000747] ------------ t747 = * RSZ long /--* t747 long N014 ( 22, 22) [000748] ------------ t748 = * CAST int <- uint <- long /--* t748 int N016 ( 26, 25) [000750] DA---------- * STORE_LCL_VAR int V55 tmp41 d:1 lowering store lcl var/field (after): N001 ( 3, 2) [000735] ------------ t735 = LCL_VAR long V54 tmp40 u:1 (last use) N002 ( 1, 1) [000166] ------------ t166 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t166 int N003 ( 2, 3) [000736] ---------U-- t736 = * CAST long <- ulong <- uint $310 /--* t735 long +--* t736 long N004 ( 9, 8) [000737] ------------ t737 = * MUL long N005 ( 1, 1) [000738] -c---------- t738 = CNS_INT int 32 $d2 /--* t737 long +--* t738 int N006 ( 11, 10) [000739] ------------ t739 = * RSZ long N007 ( 1, 1) [000741] -c---------- t741 = CNS_INT long 1 $247 /--* t739 long +--* t741 long N008 ( 13, 12) [000742] ------------ t742 = * ADD long N009 ( 1, 1) [000743] ------------ t743 = LCL_VAR int V53 tmp39 u:1 /--* t743 int N010 ( 2, 3) [000744] ---------U-- t744 = * CAST long <- ulong <- uint /--* t742 long +--* t744 long N011 ( 19, 18) [000745] ------------ t745 = * MUL long N012 ( 1, 1) [000746] -c---------- t746 = CNS_INT int 32 $d2 /--* t745 long +--* t746 int N013 ( 21, 20) [000747] ------------ t747 = * RSZ long /--* t747 long N014 ( 22, 22) [000748] ------------ t748 = * CAST int <- uint <- long /--* t748 int N016 ( 26, 25) [000750] DA---------- * STORE_LCL_VAR int V55 tmp41 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000752] ------------ t752 = LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000753] ------------ t753 = LCL_VAR int V53 tmp39 u:1 (last use) /--* t752 int +--* t753 int N003 ( 22, 5) [000754] ---X-------- t754 = * UMOD int N004 ( 3, 2) [000751] ------------ t751 = LCL_VAR int V55 tmp41 u:1 /--* t754 int +--* t751 int N005 ( 29, 8) [000755] ---X-------- t755 = * EQ int /--* t755 int N007 ( 33, 11) [000796] DA-X-------- * STORE_LCL_VAR int V59 tmp45 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000752] ------------ t752 = LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000753] ------------ t753 = LCL_VAR int V53 tmp39 u:1 (last use) /--* t752 int +--* t753 int N003 ( 22, 5) [000754] ---X-------- t754 = * UMOD int N004 ( 3, 2) [000751] ------------ t751 = LCL_VAR int V55 tmp41 u:1 /--* t754 int +--* t751 int N005 ( 29, 8) [000755] ---X-------- t755 = * EQ int /--* t755 int N007 ( 33, 11) [000796] DA-X-------- * STORE_LCL_VAR int V59 tmp45 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [001303] ------------ t1303 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1303 ref N003 ( 5, 4) [000806] DA--G------- * STORE_LCL_VAR ref V60 tmp46 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [001303] ------------ t1303 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1303 ref N003 ( 5, 4) [000806] DA--G------- * STORE_LCL_VAR ref V60 tmp46 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [001304] ------------ t1304 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1304 ref N003 ( 5, 4) [000808] DA--G------- * STORE_LCL_VAR ref V61 tmp47 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [001304] ------------ t1304 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1304 ref N003 ( 5, 4) [000808] DA--G------- * STORE_LCL_VAR ref V61 tmp47 d:1 lowering call (before): N003 ( 3, 2) [000802] ------------ t802 = LCL_VAR ref V61 tmp47 u:1 (last use) $105 N004 ( 3, 2) [000803] ------------ t803 = LCL_VAR ref V61 tmp47 u:1 (last use) $105 /--* t802 ref arg0 in rcx +--* t803 ref arg1 in rdx N005 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [001100] ----------L- * ARGPLACE ref $105 lowering arg : N002 ( 0, 0) [001101] ----------L- * ARGPLACE ref $105 late: ====== lowering arg : N003 ( 3, 2) [000802] ------------ * LCL_VAR ref V61 tmp47 u:1 (last use) $105 new node is : [001493] ------------ * PUTARG_REG ref REG rcx lowering arg : N004 ( 3, 2) [000803] ------------ * LCL_VAR ref V61 tmp47 u:1 (last use) $105 new node is : [001494] ------------ * PUTARG_REG ref REG rdx lowering call (after): N003 ( 3, 2) [000802] ------------ t802 = LCL_VAR ref V61 tmp47 u:1 (last use) $105 /--* t802 ref [001493] ------------ t1493 = * PUTARG_REG ref REG rcx N004 ( 3, 2) [000803] ------------ t803 = LCL_VAR ref V61 tmp47 u:1 (last use) $105 /--* t803 ref [001494] ------------ t1494 = * PUTARG_REG ref REG rdx /--* t1493 ref arg0 in rcx +--* t1494 ref arg1 in rdx N005 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void Addressing mode: Base N004 ( 3, 2) [001102] ------------ * LCL_VAR ref V52 tmp38 u:1 (last use) + Index * 4 + 16 N006 ( 4, 4) [001106] ------------ * CAST long <- int Removing unused node: N010 ( 6, 6) [001110] -------N---- * ADD long Removing unused node: N009 ( 1, 1) [001109] -c---------- * CNS_INT long 16 Fseq[#FirstElem] $241 Removing unused node: N008 ( 5, 5) [001108] -------N---- * LSH long Removing unused node: N007 ( 1, 1) [001107] -c-----N---- * CNS_INT long 2 $248 New addressing mode node: N011 ( 9, 8) [001111] -------N---- * LEA(b+(i*4)+16) byref lowering store lcl var/field (before): N004 ( 3, 2) [001102] ------------ t1102 = LCL_VAR ref V52 tmp38 u:1 (last use) N005 ( 3, 2) [001103] ------------ t1103 = LCL_VAR int V55 tmp41 u:1 (last use) /--* t1103 int N006 ( 4, 4) [001106] ------------ t1106 = * CAST long <- int /--* t1102 ref +--* t1106 long N011 ( 9, 8) [001111] -------N---- t1111 = * LEA(b+(i*4)+16) byref /--* t1111 byref N016 ( 33, 31) [000722] DA-XG------- * STORE_LCL_VAR byref V51 tmp37 d:1 lowering store lcl var/field (after): N004 ( 3, 2) [001102] ------------ t1102 = LCL_VAR ref V52 tmp38 u:1 (last use) N005 ( 3, 2) [001103] ------------ t1103 = LCL_VAR int V55 tmp41 u:1 (last use) /--* t1103 int N006 ( 4, 4) [001106] ------------ t1106 = * CAST long <- int /--* t1102 ref +--* t1106 long N011 ( 9, 8) [001111] -------N---- t1111 = * LEA(b+(i*4)+16) byref /--* t1111 byref N016 ( 33, 31) [000722] DA-XG------- * STORE_LCL_VAR byref V51 tmp37 d:1 lowering store lcl var/field (before): N001 ( 3, 2) [000723] ------------ t723 = LCL_VAR byref V51 tmp37 u:1 (last use) $87 /--* t723 byref N003 ( 7, 5) [000170] DA---------- * STORE_LCL_VAR byref V08 loc4 d:4 lowering store lcl var/field (after): N001 ( 3, 2) [000723] ------------ t723 = LCL_VAR byref V51 tmp37 u:1 (last use) $87 /--* t723 byref N003 ( 7, 5) [000170] DA---------- * STORE_LCL_VAR byref V08 loc4 d:4 lowering store lcl var/field (before): N001 ( 0, 0) [001224] ------------ t1224 = PHI_ARG byref V08 loc4 u:4 $87 N002 ( 0, 0) [001220] ------------ t1220 = PHI_ARG byref V08 loc4 u:1 $81 /--* t1224 byref +--* t1220 byref N003 ( 0, 0) [001192] ------------ t1192 = * PHI byref /--* t1192 byref N005 ( 0, 0) [001193] DA---------- * STORE_LCL_VAR byref V08 loc4 d:3 lowering store lcl var/field (after): N001 ( 0, 0) [001224] ------------ t1224 = PHI_ARG byref V08 loc4 u:4 $87 N002 ( 0, 0) [001220] ------------ t1220 = PHI_ARG byref V08 loc4 u:1 $81 /--* t1224 byref +--* t1220 byref N003 ( 0, 0) [001192] ------------ t1192 = * PHI byref /--* t1192 byref N005 ( 0, 0) [001193] DA---------- * STORE_LCL_VAR byref V08 loc4 d:3 lowering store lcl var/field (before): N001 ( 3, 2) [000081] ------------ t81 = LCL_VAR int V13 loc9 u:1 /--* t81 int N003 ( 7, 5) [000083] DA---------- * STORE_LCL_VAR int V10 loc6 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000081] ------------ t81 = LCL_VAR int V13 loc9 u:1 /--* t81 int N003 ( 7, 5) [000083] DA---------- * STORE_LCL_VAR int V10 loc6 d:2 Addressing mode: Base N004 ( 1, 1) [000084] ------------ * LCL_VAR ref V00 this u:1 $100 + 56 Removing unused node: N005 ( 1, 1) [001114] -c---------- * CNS_INT long 56 field offset Fseq[_count] $244 New addressing mode node: N006 ( 2, 2) [001115] ------------ * LEA(b+56) byref Lower of StoreInd didn't mark the node as self contained for reason: address mode is not supported N001 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V10 loc6 u:2 (last use) N002 ( 1, 1) [000086] -c---------- t86 = CNS_INT int 1 $c1 /--* t85 int +--* t86 int N003 ( 5, 4) [000087] ------------ t87 = * ADD int N004 ( 1, 1) [000084] ------------ t84 = LCL_VAR ref V00 this u:1 $100 /--* t84 ref N006 ( 2, 2) [001115] ------------ t1115 = * LEA(b+56) byref /--* t1115 byref +--* t87 int [001418] -A--GO------ * STOREIND int Addressing mode: Base N001 ( 1, 1) [000090] ------------ * LCL_VAR ref V00 this u:1 $100 + 16 Removing unused node: N002 ( 1, 1) [001116] -c---------- * CNS_INT long 16 field offset Fseq[_entries] $241 New addressing mode node: N003 ( 2, 2) [001117] ------------ * LEA(b+16) byref lowering store lcl var/field (before): N001 ( 1, 1) [000090] ------------ t90 = LCL_VAR ref V00 this u:1 $100 /--* t90 ref N003 ( 2, 2) [001117] -c---------- t1117 = * LEA(b+16) byref /--* t1117 byref N004 ( 4, 4) [000091] n---GO------ t91 = * IND ref /--* t91 ref N006 ( 4, 4) [000093] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:3 lowering store lcl var/field (after): N001 ( 1, 1) [000090] ------------ t90 = LCL_VAR ref V00 this u:1 $100 /--* t90 ref N003 ( 2, 2) [001117] -c---------- t1117 = * LEA(b+16) byref /--* t1117 byref N004 ( 4, 4) [000091] n---GO------ t91 = * IND ref /--* t91 ref N006 ( 4, 4) [000093] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:3 lowering store lcl var/field (before): N001 ( 0, 0) [001225] ------------ t1225 = PHI_ARG byref V08 loc4 u:1 $81 N002 ( 0, 0) [001221] ------------ t1221 = PHI_ARG byref V08 loc4 u:3 $780 /--* t1225 byref +--* t1221 byref N003 ( 0, 0) [001195] ------------ t1195 = * PHI byref /--* t1195 byref N005 ( 0, 0) [001196] DA---------- * STORE_LCL_VAR byref V08 loc4 d:2 lowering store lcl var/field (after): N001 ( 0, 0) [001225] ------------ t1225 = PHI_ARG byref V08 loc4 u:1 $81 N002 ( 0, 0) [001221] ------------ t1221 = PHI_ARG byref V08 loc4 u:3 $780 /--* t1225 byref +--* t1221 byref N003 ( 0, 0) [001195] ------------ t1195 = * PHI byref /--* t1195 byref N005 ( 0, 0) [001196] DA---------- * STORE_LCL_VAR byref V08 loc4 d:2 lowering store lcl var/field (before): N001 ( 0, 0) [001226] ------------ t1226 = PHI_ARG ref V04 loc0 u:1 N002 ( 0, 0) [001222] ------------ t1222 = PHI_ARG ref V04 loc0 u:3 /--* t1226 ref +--* t1222 ref N003 ( 0, 0) [001189] ------------ t1189 = * PHI ref /--* t1189 ref N005 ( 0, 0) [001190] DA---------- * STORE_LCL_VAR ref V04 loc0 d:2 lowering store lcl var/field (after): N001 ( 0, 0) [001226] ------------ t1226 = PHI_ARG ref V04 loc0 u:1 N002 ( 0, 0) [001222] ------------ t1222 = PHI_ARG ref V04 loc0 u:3 /--* t1226 ref +--* t1222 ref N003 ( 0, 0) [001189] ------------ t1189 = * PHI ref /--* t1189 ref N005 ( 0, 0) [001190] DA---------- * STORE_LCL_VAR ref V04 loc0 d:2 lowering store lcl var/field (before): N001 ( 0, 0) [001227] ------------ t1227 = PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [001223] ------------ t1223 = PHI_ARG int V10 loc6 u:2 /--* t1227 int +--* t1223 int N003 ( 0, 0) [001186] ------------ t1186 = * PHI int /--* t1186 int N005 ( 0, 0) [001187] DA---------- * STORE_LCL_VAR int V10 loc6 d:1 lowering store lcl var/field (after): N001 ( 0, 0) [001227] ------------ t1227 = PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [001223] ------------ t1223 = PHI_ARG int V10 loc6 u:2 /--* t1227 int +--* t1223 int N003 ( 0, 0) [001186] ------------ t1186 = * PHI int /--* t1186 int N005 ( 0, 0) [001187] DA---------- * STORE_LCL_VAR int V10 loc6 d:1 Addressing mode: Base N002 ( 1, 1) [000094] ------------ * LCL_VAR ref V04 loc0 u:2 $684 + 8 Removing unused node: [001451] -c---------- * CNS_INT long 8 New addressing mode node: [001452] ------------ * LEA(b+8) ref Addressing mode: Base N005 ( 1, 1) [001118] ------------ * LCL_VAR ref V04 loc0 u:2 $684 + Index * 8 + 16 N009 ( 9, 8) [001130] ------------ * MUL long $6dd Removing unused node: N013 ( 11, 10) [001126] -------N---- * ADD long $6df Removing unused node: N012 ( 1, 1) [001125] -c---------- * CNS_INT long 16 Fseq[#FirstElem] $241 Removing unused node: N011 ( 10, 9) [001124] -------N---- * LSH long $6de Removing unused node: N010 ( 1, 1) [001123] -c-----N---- * CNS_INT long 3 $24b New addressing mode node: N014 ( 12, 11) [001127] -------N---- * LEA(b+(i*8)+16) byref lowering store lcl var/field (before): N005 ( 1, 1) [001118] ------------ t1118 = LCL_VAR ref V04 loc0 u:2 $684 N006 ( 3, 2) [001119] ------------ t1119 = LCL_VAR int V10 loc6 u:1 $3cc /--* t1119 int N007 ( 4, 4) [001122] ------------ t1122 = * CAST long <- int $6dc N008 ( 1, 1) [001129] -c---------- t1129 = CNS_INT long 3 $24b /--* t1122 long +--* t1129 long N009 ( 9, 8) [001130] ------------ t1130 = * MUL long $6dd /--* t1118 ref +--* t1130 long N014 ( 12, 11) [001127] -------N---- t1127 = * LEA(b+(i*8)+16) byref /--* t1127 byref N019 ( 39, 38) [000099] DA-XG------- * STORE_LCL_VAR byref V11 loc7 d:1 lowering store lcl var/field (after): N005 ( 1, 1) [001118] ------------ t1118 = LCL_VAR ref V04 loc0 u:2 $684 N006 ( 3, 2) [001119] ------------ t1119 = LCL_VAR int V10 loc6 u:1 $3cc /--* t1119 int N007 ( 4, 4) [001122] ------------ t1122 = * CAST long <- int $6dc N008 ( 1, 1) [001129] -c---------- t1129 = CNS_INT long 3 $24b /--* t1122 long +--* t1129 long N009 ( 9, 8) [001130] ------------ t1130 = * MUL long $6dd /--* t1118 ref +--* t1130 long N014 ( 12, 11) [001127] -------N---- t1127 = * LEA(b+(i*8)+16) byref /--* t1127 byref N019 ( 39, 38) [000099] DA-XG------- * STORE_LCL_VAR byref V11 loc7 d:1 Addressing mode: Base N001 ( 3, 2) [000100] ------------ * LCL_VAR byref V11 loc7 u:1 $8c + 16 Removing unused node: N002 ( 1, 1) [001132] -c---------- * CNS_INT long 16 field offset Fseq[hashCode] $241 New addressing mode node: N003 ( 4, 3) [001133] ------------ * LEA(b+16) byref Lower of StoreInd didn't mark the node as self contained for reason: oper is not supported N001 ( 3, 2) [000100] ------------ t100 = LCL_VAR byref V11 loc7 u:1 $8c /--* t100 byref N003 ( 4, 3) [001133] ------------ t1133 = * LEA(b+16) byref N005 ( 1, 1) [000101] ------------ t101 = LCL_VAR int V06 loc2 u:1 (last use) $3c0 /--* t1133 byref +--* t101 int [001422] -A-XG------- * STOREIND int Addressing mode: Base N005 ( 3, 2) [000104] ------------ * LCL_VAR byref V11 loc7 u:1 $8c + 20 Removing unused node: N006 ( 1, 1) [001134] -c---------- * CNS_INT long 20 field offset Fseq[next] $24c New addressing mode node: N007 ( 4, 3) [001135] ------------ * LEA(b+20) byref Lower of StoreInd didn't mark the node as self contained for reason: address mode is not supported N001 ( 3, 2) [000105] ------------ t105 = LCL_VAR byref V08 loc4 u:2 $781 /--* t105 byref N002 ( 6, 4) [000106] *--XG------- t106 = * IND int N003 ( 1, 1) [000107] -c---------- t107 = CNS_INT int -1 $c4 /--* t106 int +--* t107 int N004 ( 8, 6) [000108] ---XG------- t108 = * ADD int N005 ( 3, 2) [000104] ------------ t104 = LCL_VAR byref V11 loc7 u:1 $8c /--* t104 byref N007 ( 4, 3) [001135] ------------ t1135 = * LEA(b+20) byref /--* t1135 byref +--* t108 int [001424] -A-XGO------ * STOREIND int Addressing mode: Base N001 ( 3, 2) [000115] ------------ * LCL_VAR byref V11 loc7 u:1 (last use) $8c + 8 Removing unused node: N002 ( 1, 1) [001136] -c---------- * CNS_INT long 8 field offset Fseq[value] $240 New addressing mode node: N003 ( 4, 3) [001137] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: address mode is not supported N001 ( 3, 2) [000120] ------------ t120 = LCL_VAR int V10 loc6 u:1 (last use) $3cc N002 ( 1, 1) [000121] -c---------- t121 = CNS_INT int 1 $c1 /--* t120 int +--* t121 int N003 ( 5, 4) [000122] ------------ t122 = * ADD int $804 N004 ( 3, 2) [000119] ------------ t119 = LCL_VAR byref V08 loc4 u:2 (last use) $781 /--* t119 byref +--* t122 int [001430] -A--GO------ * STOREIND int Addressing mode: Base N001 ( 1, 1) [000126] ------------ * LCL_VAR ref V00 this u:1 $100 + 68 Removing unused node: N002 ( 1, 1) [001140] -c---------- * CNS_INT long 68 field offset Fseq[_version] $24e New addressing mode node: N003 ( 2, 2) [001141] ------------ * LEA(b+68) byref Addressing mode: Base N007 ( 1, 1) [000125] ------------ * LCL_VAR ref V00 this u:1 $100 + 68 Removing unused node: N008 ( 1, 1) [001138] -c---------- * CNS_INT long 68 field offset Fseq[_version] $24e New addressing mode node: N009 ( 2, 2) [001139] ------------ * LEA(b+68) byref Lower succesfully detected an assignment of the form: *addrMode BinOp= source N001 ( 1, 1) [000126] ------------ t126 = LCL_VAR ref V00 this u:1 $100 /--* t126 ref N003 ( 2, 2) [001141] -c---------- t1141 = * LEA(b+68) byref /--* t1141 byref N004 ( 4, 4) [000127] n---GO------ t127 = * IND int N005 ( 1, 1) [000128] -c---------- t128 = CNS_INT int 1 $c1 /--* t127 int +--* t128 int N006 ( 6, 6) [000129] ----GO------ t129 = * ADD int N007 ( 1, 1) [000125] ------------ t125 = LCL_VAR ref V00 this u:1 $100 /--* t125 ref N009 ( 2, 2) [001139] ------------ t1139 = * LEA(b+68) byref /--* t1139 byref +--* t129 int [001432] -A--GO------ * STOREIND int lowering call (before): N003 ( 1, 1) [000151] ------------ t151 = LCL_VAR ref V05 loc1 u:1 (last use) N004 ( 2, 10) [000152] H------N---- t152 = CNS_INT(h) long 0xd1ffab1e class $62 /--* t151 ref arg1 in rdx +--* t152 long arg0 in rcx N005 ( 17, 18) [000153] --C-G------- t153 = * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS objp: ====== args: ====== lowering arg : N001 ( 0, 0) [001143] ----------L- * ARGPLACE long $62 lowering arg : N002 ( 0, 0) [001142] ----------L- * ARGPLACE ref late: ====== lowering arg : N003 ( 1, 1) [000151] ------------ * LCL_VAR ref V05 loc1 u:1 (last use) new node is : [001495] ------------ * PUTARG_REG ref REG rdx lowering arg : N004 ( 2, 10) [000152] H------N---- * CNS_INT(h) long 0xd1ffab1e class $62 new node is : [001496] ------------ * PUTARG_REG long REG rcx lowering call (after): N003 ( 1, 1) [000151] ------------ t151 = LCL_VAR ref V05 loc1 u:1 (last use) /--* t151 ref [001495] ------------ t1495 = * PUTARG_REG ref REG rdx N004 ( 2, 10) [000152] H------N---- t152 = CNS_INT(h) long 0xd1ffab1e class $62 /--* t152 long [001496] ------------ t1496 = * PUTARG_REG long REG rcx /--* t1495 ref arg1 in rdx +--* t1496 long arg0 in rcx N005 ( 17, 18) [000153] --C-G------- t153 = * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS Addressing mode: Base N004 ( 1, 1) [000158] ------------ * LCL_VAR ref V04 loc0 u:2 (last use) $684 + 8 Removing unused node: [001453] -c---------- * CNS_INT long 8 New addressing mode node: [001454] ------------ * LEA(b+8) ref lowering call (before): N004 ( 1, 1) [000158] ------------ t158 = LCL_VAR ref V04 loc0 u:2 (last use) $684 /--* t158 ref [001454] -c---------- t1454 = * LEA(b+8) ref /--* t1454 ref N005 ( 3, 3) [000159] ---X-------- t159 = * IND int $73d N006 ( 1, 1) [000157] ------------ t157 = LCL_VAR ref V00 this u:1 $100 N007 ( 1, 1) [000160] ------------ t160 = CNS_INT int 1 $c1 /--* t159 int arg1 in rdx +--* t157 ref this in rcx +--* t160 int arg2 in r8 N008 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void objp: ====== lowering arg : N001 ( 0, 0) [001145] ----------L- * ARGPLACE ref $23f args: ====== lowering arg : N002 ( 0, 0) [001144] ----------L- * ARGPLACE int $100 lowering arg : N003 ( 0, 0) [001146] ----------L- * ARGPLACE int $73d late: ====== lowering arg : N005 ( 3, 3) [000159] ---X-------- * IND int $73d new node is : [001497] ---X-------- * PUTARG_REG int REG rdx lowering arg : N006 ( 1, 1) [000157] ------------ * LCL_VAR ref V00 this u:1 $100 new node is : [001498] ------------ * PUTARG_REG ref REG rcx lowering arg : N007 ( 1, 1) [000160] ------------ * CNS_INT int 1 $c1 new node is : [001499] ------------ * PUTARG_REG int REG r8 lowering call (after): N004 ( 1, 1) [000158] ------------ t158 = LCL_VAR ref V04 loc0 u:2 (last use) $684 /--* t158 ref [001454] -c---------- t1454 = * LEA(b+8) ref /--* t1454 ref N005 ( 3, 3) [000159] ---X-------- t159 = * IND int $73d /--* t159 int [001497] ---X-------- t1497 = * PUTARG_REG int REG rdx N006 ( 1, 1) [000157] ------------ t157 = LCL_VAR ref V00 this u:1 $100 /--* t157 ref [001498] ------------ t1498 = * PUTARG_REG ref REG rcx N007 ( 1, 1) [000160] ------------ t160 = CNS_INT int 1 $c1 /--* t160 int [001499] ------------ t1499 = * PUTARG_REG int REG r8 /--* t1497 int arg1 in rdx +--* t1498 ref this in rcx +--* t1499 int arg2 in r8 N008 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void lowering GT_RETURN N002 ( 2, 2) [000810] ------------ * RETURN int $1f4 ============lowering call (before): N002 ( 1, 1) [000532] ------------ t532 = CNS_INT int 4 $c5 /--* t532 int arg0 in rcx N003 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException $VN.Void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000812] ----------L- * ARGPLACE int $c5 late: ====== lowering arg : N002 ( 1, 1) [000532] ------------ * CNS_INT int 4 $c5 new node is : [001500] ------------ * PUTARG_REG int REG rcx lowering call (after): N002 ( 1, 1) [000532] ------------ t532 = CNS_INT int 4 $c5 /--* t532 int [001500] ------------ t1500 = * PUTARG_REG int REG rcx /--* t1500 int arg0 in rcx N003 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException $VN.Void lowering store lcl var/field (before): N001 ( 1, 1) [000441] !----------- t441 = LCL_VAR ref V00 this u:1 $100 /--* t441 ref N002 ( 3, 2) [000442] #----O------ t442 = * IND long $2e8 /--* t442 long N004 ( 7, 5) [000444] DA---O------ * STORE_LCL_VAR long V26 tmp12 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000441] !----------- t441 = LCL_VAR ref V00 this u:1 $100 /--* t441 ref N002 ( 3, 2) [000442] #----O------ t442 = * IND long $2e8 /--* t442 long N004 ( 7, 5) [000444] DA---O------ * STORE_LCL_VAR long V26 tmp12 d:1 Addressing mode: Base N001 ( 3, 2) [000446] ------------ * LCL_VAR long V26 tmp12 u:1 $2e7 + 56 Removing unused node: N002 ( 1, 1) [000447] -c---------- * CNS_INT long 56 $244 New addressing mode node: N003 ( 4, 3) [000448] ------------ * LEA(b+56) long Addressing mode: Base N005 ( 9, 7) [000450] #----------- * IND long $2ea + 56 Removing unused node: N006 ( 1, 1) [000451] -c---------- * CNS_INT long 56 $244 New addressing mode node: N007 ( 10, 8) [000452] ------------ * LEA(b+56) long Addressing mode: Base N001 ( 3, 2) [000466] ------?----- * LCL_VAR long V26 tmp12 u:1 (last use) $2e7 + 56 Removing unused node: N002 ( 1, 1) [000467] -c----?----- * CNS_INT long 56 $244 New addressing mode node: N003 ( 4, 3) [000465] ------?----- * LEA(b+56) long Addressing mode: Base N005 ( 9, 7) [000463] #-----?----- * IND long $2ea + 56 Removing unused node: N006 ( 1, 1) [000468] -c----?----- * CNS_INT long 56 $244 New addressing mode node: N007 ( 10, 8) [000462] ------?----- * LEA(b+56) long lowering store lcl var/field (before): N001 ( 3, 2) [000466] ------?----- t466 = LCL_VAR long V26 tmp12 u:1 (last use) $2e7 /--* t466 long N003 ( 4, 3) [000465] -c----?----- t465 = * LEA(b+56) long /--* t465 long N004 ( 6, 5) [000464] #-----?----- t464 = * IND long $2e9 /--* t464 long N005 ( 9, 7) [000463] #-----?----- t463 = * IND long $2ea /--* t463 long N007 ( 10, 8) [000462] -c----?----- t462 = * LEA(b+56) long /--* t462 long N008 ( 12, 10) [000461] n-----?----- t461 = * IND long /--* t461 long N010 ( 16, 13) [001160] DA---------- * STORE_LCL_VAR long V28 tmp14 d:3 lowering store lcl var/field (after): N001 ( 3, 2) [000466] ------?----- t466 = LCL_VAR long V26 tmp12 u:1 (last use) $2e7 /--* t466 long N003 ( 4, 3) [000465] -c----?----- t465 = * LEA(b+56) long /--* t465 long N004 ( 6, 5) [000464] #-----?----- t464 = * IND long $2e9 /--* t464 long N005 ( 9, 7) [000463] #-----?----- t463 = * IND long $2ea /--* t463 long N007 ( 10, 8) [000462] -c----?----- t462 = * LEA(b+56) long /--* t462 long N008 ( 12, 10) [000461] n-----?----- t461 = * IND long /--* t461 long N010 ( 16, 13) [001160] DA---------- * STORE_LCL_VAR long V28 tmp14 d:3 lowering call (before): N003 ( 3, 2) [000445] ------?----- t445 = LCL_VAR long V26 tmp12 u:1 (last use) $2e7 N004 ( 2, 10) [000457] H-----?----- t457 = CNS_INT(h) long 0xd1ffab1e global ptr $52 /--* t445 long arg0 in rcx +--* t457 long arg1 in rdx N005 ( 19, 19) [000458] --C-G-?----- t458 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000927] ------?---L- * ARGPLACE long $2e7 lowering arg : N002 ( 0, 0) [000928] ------?---L- * ARGPLACE long $52 late: ====== lowering arg : N003 ( 3, 2) [000445] ------?----- * LCL_VAR long V26 tmp12 u:1 (last use) $2e7 new node is : [001501] ------------ * PUTARG_REG long REG rcx lowering arg : N004 ( 2, 10) [000457] H-----?----- * CNS_INT(h) long 0xd1ffab1e global ptr $52 new node is : [001502] ------------ * PUTARG_REG long REG rdx lowering call (after): N003 ( 3, 2) [000445] ------?----- t445 = LCL_VAR long V26 tmp12 u:1 (last use) $2e7 /--* t445 long [001501] ------------ t1501 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000457] H-----?----- t457 = CNS_INT(h) long 0xd1ffab1e global ptr $52 /--* t457 long [001502] ------------ t1502 = * PUTARG_REG long REG rdx /--* t1501 long arg0 in rcx +--* t1502 long arg1 in rdx N005 ( 19, 19) [000458] --C-G-?----- t458 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 lowering store lcl var/field (before): N003 ( 3, 2) [000445] ------?----- t445 = LCL_VAR long V26 tmp12 u:1 (last use) $2e7 /--* t445 long [001501] ------------ t1501 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000457] H-----?----- t457 = CNS_INT(h) long 0xd1ffab1e global ptr $52 /--* t457 long [001502] ------------ t1502 = * PUTARG_REG long REG rdx /--* t1501 long arg0 in rcx +--* t1502 long arg1 in rdx N005 ( 19, 19) [000458] --C-G-?----- t458 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 /--* t458 long N007 ( 23, 22) [001162] DA--G------- * STORE_LCL_VAR long V28 tmp14 d:2 lowering store lcl var/field (after): N003 ( 3, 2) [000445] ------?----- t445 = LCL_VAR long V26 tmp12 u:1 (last use) $2e7 /--* t445 long [001501] ------------ t1501 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000457] H-----?----- t457 = CNS_INT(h) long 0xd1ffab1e global ptr $52 /--* t457 long [001502] ------------ t1502 = * PUTARG_REG long REG rdx /--* t1501 long arg0 in rcx +--* t1502 long arg1 in rdx N005 ( 19, 19) [000458] --C-G-?----- t458 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 /--* t458 long N007 ( 23, 22) [001162] DA--G------- * STORE_LCL_VAR long V28 tmp14 d:2 lowering store lcl var/field (before): N001 ( 0, 0) [001241] ------------ t1241 = PHI_ARG long V28 tmp14 u:3 N002 ( 0, 0) [001240] ------------ t1240 = PHI_ARG long V28 tmp14 u:2 $332 /--* t1241 long +--* t1240 long N003 ( 0, 0) [001183] ------------ t1183 = * PHI long /--* t1183 long N005 ( 0, 0) [001184] DA---------- * STORE_LCL_VAR long V28 tmp14 d:1 lowering store lcl var/field (after): N001 ( 0, 0) [001241] ------------ t1241 = PHI_ARG long V28 tmp14 u:3 N002 ( 0, 0) [001240] ------------ t1240 = PHI_ARG long V28 tmp14 u:2 $332 /--* t1241 long +--* t1240 long N003 ( 0, 0) [001183] ------------ t1183 = * PHI long /--* t1183 long N005 ( 0, 0) [001184] DA---------- * STORE_LCL_VAR long V28 tmp14 d:1 lowering call (before): N003 ( 3, 2) [000473] ------------ t473 = LCL_VAR long V28 tmp14 u:1 (last use) $347 N004 ( 1, 1) [000455] ------------ t455 = LCL_VAR ref V01 arg1 u:1 (last use) $101 /--* t473 long arg0 in rcx +--* t455 ref arg1 in rdx N005 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000929] ----------L- * ARGPLACE long $347 lowering arg : N002 ( 0, 0) [000930] ----------L- * ARGPLACE ref $101 late: ====== lowering arg : N003 ( 3, 2) [000473] ------------ * LCL_VAR long V28 tmp14 u:1 (last use) $347 new node is : [001503] ------------ * PUTARG_REG long REG rcx lowering arg : N004 ( 1, 1) [000455] ------------ * LCL_VAR ref V01 arg1 u:1 (last use) $101 new node is : [001504] ------------ * PUTARG_REG ref REG rdx lowering call (after): N003 ( 3, 2) [000473] ------------ t473 = LCL_VAR long V28 tmp14 u:1 (last use) $347 /--* t473 long [001503] ------------ t1503 = * PUTARG_REG long REG rcx N004 ( 1, 1) [000455] ------------ t455 = LCL_VAR ref V01 arg1 u:1 (last use) $101 /--* t455 ref [001504] ------------ t1504 = * PUTARG_REG ref REG rdx /--* t1503 long arg0 in rcx +--* t1504 ref arg1 in rdx N005 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void lowering store lcl var/field (before): N001 ( 1, 1) [000296] !----------- t296 = LCL_VAR ref V00 this u:1 $100 /--* t296 ref N002 ( 3, 2) [000297] #----O------ t297 = * IND long $2e8 /--* t297 long N004 ( 7, 5) [000299] DA---O------ * STORE_LCL_VAR long V21 tmp7 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000296] !----------- t296 = LCL_VAR ref V00 this u:1 $100 /--* t296 ref N002 ( 3, 2) [000297] #----O------ t297 = * IND long $2e8 /--* t297 long N004 ( 7, 5) [000299] DA---O------ * STORE_LCL_VAR long V21 tmp7 d:1 Addressing mode: Base N001 ( 3, 2) [000301] ------------ * LCL_VAR long V21 tmp7 u:1 $2e7 + 56 Removing unused node: N002 ( 1, 1) [000302] -c---------- * CNS_INT long 56 $244 New addressing mode node: N003 ( 4, 3) [000303] ------------ * LEA(b+56) long Addressing mode: Base N005 ( 9, 7) [000305] #----------- * IND long $2ea + 56 Removing unused node: N006 ( 1, 1) [000306] -c---------- * CNS_INT long 56 $244 New addressing mode node: N007 ( 10, 8) [000307] ------------ * LEA(b+56) long Addressing mode: Base N001 ( 3, 2) [000321] ------?----- * LCL_VAR long V21 tmp7 u:1 (last use) $2e7 + 56 Removing unused node: N002 ( 1, 1) [000322] -c----?----- * CNS_INT long 56 $244 New addressing mode node: N003 ( 4, 3) [000320] ------?----- * LEA(b+56) long Addressing mode: Base N005 ( 9, 7) [000318] #-----?----- * IND long $2ea + 56 Removing unused node: N006 ( 1, 1) [000323] -c----?----- * CNS_INT long 56 $244 New addressing mode node: N007 ( 10, 8) [000317] ------?----- * LEA(b+56) long lowering store lcl var/field (before): N001 ( 3, 2) [000321] ------?----- t321 = LCL_VAR long V21 tmp7 u:1 (last use) $2e7 /--* t321 long N003 ( 4, 3) [000320] -c----?----- t320 = * LEA(b+56) long /--* t320 long N004 ( 6, 5) [000319] #-----?----- t319 = * IND long $2e9 /--* t319 long N005 ( 9, 7) [000318] #-----?----- t318 = * IND long $2ea /--* t318 long N007 ( 10, 8) [000317] -c----?----- t317 = * LEA(b+56) long /--* t317 long N008 ( 12, 10) [000316] n-----?----- t316 = * IND long /--* t316 long N010 ( 16, 13) [001170] DA---------- * STORE_LCL_VAR long V23 tmp9 d:3 lowering store lcl var/field (after): N001 ( 3, 2) [000321] ------?----- t321 = LCL_VAR long V21 tmp7 u:1 (last use) $2e7 /--* t321 long N003 ( 4, 3) [000320] -c----?----- t320 = * LEA(b+56) long /--* t320 long N004 ( 6, 5) [000319] #-----?----- t319 = * IND long $2e9 /--* t319 long N005 ( 9, 7) [000318] #-----?----- t318 = * IND long $2ea /--* t318 long N007 ( 10, 8) [000317] -c----?----- t317 = * LEA(b+56) long /--* t317 long N008 ( 12, 10) [000316] n-----?----- t316 = * IND long /--* t316 long N010 ( 16, 13) [001170] DA---------- * STORE_LCL_VAR long V23 tmp9 d:3 lowering call (before): N003 ( 3, 2) [000300] ------?----- t300 = LCL_VAR long V21 tmp7 u:1 (last use) $2e7 N004 ( 2, 10) [000312] H-----?----- t312 = CNS_INT(h) long 0xd1ffab1e global ptr $52 /--* t300 long arg0 in rcx +--* t312 long arg1 in rdx N005 ( 19, 19) [000313] --C-G-?----- t313 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [001003] ------?---L- * ARGPLACE long $2e7 lowering arg : N002 ( 0, 0) [001004] ------?---L- * ARGPLACE long $52 late: ====== lowering arg : N003 ( 3, 2) [000300] ------?----- * LCL_VAR long V21 tmp7 u:1 (last use) $2e7 new node is : [001505] ------------ * PUTARG_REG long REG rcx lowering arg : N004 ( 2, 10) [000312] H-----?----- * CNS_INT(h) long 0xd1ffab1e global ptr $52 new node is : [001506] ------------ * PUTARG_REG long REG rdx lowering call (after): N003 ( 3, 2) [000300] ------?----- t300 = LCL_VAR long V21 tmp7 u:1 (last use) $2e7 /--* t300 long [001505] ------------ t1505 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000312] H-----?----- t312 = CNS_INT(h) long 0xd1ffab1e global ptr $52 /--* t312 long [001506] ------------ t1506 = * PUTARG_REG long REG rdx /--* t1505 long arg0 in rcx +--* t1506 long arg1 in rdx N005 ( 19, 19) [000313] --C-G-?----- t313 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 lowering store lcl var/field (before): N003 ( 3, 2) [000300] ------?----- t300 = LCL_VAR long V21 tmp7 u:1 (last use) $2e7 /--* t300 long [001505] ------------ t1505 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000312] H-----?----- t312 = CNS_INT(h) long 0xd1ffab1e global ptr $52 /--* t312 long [001506] ------------ t1506 = * PUTARG_REG long REG rdx /--* t1505 long arg0 in rcx +--* t1506 long arg1 in rdx N005 ( 19, 19) [000313] --C-G-?----- t313 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 /--* t313 long N007 ( 23, 22) [001172] DA--G------- * STORE_LCL_VAR long V23 tmp9 d:2 lowering store lcl var/field (after): N003 ( 3, 2) [000300] ------?----- t300 = LCL_VAR long V21 tmp7 u:1 (last use) $2e7 /--* t300 long [001505] ------------ t1505 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000312] H-----?----- t312 = CNS_INT(h) long 0xd1ffab1e global ptr $52 /--* t312 long [001506] ------------ t1506 = * PUTARG_REG long REG rdx /--* t1505 long arg0 in rcx +--* t1506 long arg1 in rdx N005 ( 19, 19) [000313] --C-G-?----- t313 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 /--* t313 long N007 ( 23, 22) [001172] DA--G------- * STORE_LCL_VAR long V23 tmp9 d:2 lowering store lcl var/field (before): N001 ( 0, 0) [001232] ------------ t1232 = PHI_ARG long V23 tmp9 u:3 N002 ( 0, 0) [001231] ------------ t1231 = PHI_ARG long V23 tmp9 u:2 $332 /--* t1232 long +--* t1231 long N003 ( 0, 0) [001201] ------------ t1201 = * PHI long /--* t1201 long N005 ( 0, 0) [001202] DA---------- * STORE_LCL_VAR long V23 tmp9 d:1 lowering store lcl var/field (after): N001 ( 0, 0) [001232] ------------ t1232 = PHI_ARG long V23 tmp9 u:3 N002 ( 0, 0) [001231] ------------ t1231 = PHI_ARG long V23 tmp9 u:2 $332 /--* t1232 long +--* t1231 long N003 ( 0, 0) [001201] ------------ t1201 = * PHI long /--* t1201 long N005 ( 0, 0) [001202] DA---------- * STORE_LCL_VAR long V23 tmp9 d:1 lowering call (before): N003 ( 3, 2) [000328] ------------ t328 = LCL_VAR long V23 tmp9 u:1 (last use) $34b N004 ( 1, 1) [000310] ------------ t310 = LCL_VAR ref V01 arg1 u:1 (last use) $101 /--* t328 long arg0 in rcx +--* t310 ref arg1 in rdx N005 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [001005] ----------L- * ARGPLACE long $34b lowering arg : N002 ( 0, 0) [001006] ----------L- * ARGPLACE ref $101 late: ====== lowering arg : N003 ( 3, 2) [000328] ------------ * LCL_VAR long V23 tmp9 u:1 (last use) $34b new node is : [001507] ------------ * PUTARG_REG long REG rcx lowering arg : N004 ( 1, 1) [000310] ------------ * LCL_VAR ref V01 arg1 u:1 (last use) $101 new node is : [001508] ------------ * PUTARG_REG ref REG rdx lowering call (after): N003 ( 3, 2) [000328] ------------ t328 = LCL_VAR long V23 tmp9 u:1 (last use) $34b /--* t328 long [001507] ------------ t1507 = * PUTARG_REG long REG rcx N004 ( 1, 1) [000310] ------------ t310 = LCL_VAR ref V01 arg1 u:1 (last use) $101 /--* t310 ref [001508] ------------ t1508 = * PUTARG_REG ref REG rdx /--* t1507 long arg0 in rcx +--* t1508 ref arg1 in rdx N005 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void lowering call (before): N001 ( 14, 5) [000233] --CXG------- CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported $VN.Void objp: ====== args: ====== late: ====== lowering call (after): N001 ( 14, 5) [000233] --CXG------- CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported $VN.Void lowering call (before): N001 ( 14, 5) [001444] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL objp: ====== args: ====== late: ====== lowering call (after): N001 ( 14, 5) [001444] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL Lower has completed modifying nodes. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i LIR BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i LIR BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe LIR BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i LIR BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe LIR BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i LIR BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe LIR BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i LIR BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe LIR BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe LIR BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe LIR BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe LIR BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe LIR BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen LIR BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe LIR BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen LIR BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe LIR BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen LIR BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe LIR BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe LIR BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe LIR BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe LIR BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target LIR BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd LIR BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd LIR BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd LIR BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal LIR BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd LIR BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen LIR BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd LIR BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal Loop1 gcsafe LIR BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target LIR BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd LIR BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd LIR BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe LIR BB36 [0108] 1 BB34 1 [???..???) i gcsafe LIR BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd LIR BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd LIR BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen LIR BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd LIR BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe LIR BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd LIR BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal LIR BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i LIR BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen LIR BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe LIR BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen LIR BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen LIR BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen LIR BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe LIR BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen LIR BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe LIR BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen LIR BB54 [0044] 2 BB48,BB53 0.50 [261..276) i LIR BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen LIR BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall LIR BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen LIR BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal LIR BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe LIR BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd LIR BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe LIR BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe LIR BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd LIR BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd LIR BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe LIR BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe LIR BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd LIR BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd LIR BB69 [0117] 0 0 [???..???) (throw ) keep i internal rare LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} [001332] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V01 arg1 u:1 $101 N002 ( 1, 1) [000001] -c---------- t1 = CNS_INT ref null $VN.Null /--* t0 ref +--* t1 ref N003 ( 3, 3) [000002] J------N---- * EQ void $180 N004 ( 5, 5) [000003] ------------ * JTRUE void ------------ BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} [001333] ------------ IL_OFFSET void IL offset: 0xe N001 ( 1, 1) [000004] ------------ t4 = LCL_VAR ref V00 this u:1 $100 /--* t4 ref N003 ( 2, 2) [000814] -c---------- t814 = * LEA(b+8) byref /--* t814 byref N004 ( 4, 4) [000005] -c-XG------- t5 = * IND ref N005 ( 1, 1) [000006] -c---------- t6 = CNS_INT ref null $VN.Null /--* t5 ref +--* t6 ref N006 ( 6, 6) [000007] J--XG--N---- * NE void N007 ( 8, 8) [000008] ---XG------- * JTRUE void ------------ BB03 [016..01E), preds={BB02} succs={BB04} N003 ( 1, 1) [000526] ------------ t526 = LCL_VAR ref V00 this u:1 $100 /--* t526 ref [001455] ------------ t1455 = * PUTARG_REG ref REG rcx N004 ( 1, 1) [000527] ------------ t527 = CNS_INT int 0 $c0 /--* t527 int [001456] ------------ t1456 = * PUTARG_REG int REG rdx /--* t1455 ref this in rcx +--* t1456 int arg1 in rdx N005 ( 16, 10) [000528] --CXG------- t528 = * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize $1c2 ------------ BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} [001334] ------------ IL_OFFSET void IL offset: 0x1e N001 ( 1, 1) [000009] ------------ t9 = LCL_VAR ref V00 this u:1 $100 /--* t9 ref N003 ( 2, 2) [000818] -c---------- t818 = * LEA(b+8) byref /--* t818 byref N004 ( 4, 4) [000010] nc--GO------ t10 = * IND ref N005 ( 1, 1) [000011] -c---------- t11 = CNS_INT ref null $VN.Null /--* t10 ref +--* t11 ref N006 ( 9, 6) [000012] N---GO------ t12 = * NE int /--* t12 int N008 ( 9, 6) [000544] DA--GO------ * STORE_LCL_VAR int V33 tmp19 d:1 [001335] ------------ IL_OFFSET void IL offset: 0x1e N001 ( 2, 10) [000537] H----------- t537 = CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 /--* t537 long N002 ( 4, 12) [000538] #---G------- t538 = * IND ref $105 /--* t538 ref N004 ( 4, 12) [001291] DA--G------- * STORE_LCL_VAR ref V73 cse8 d:1 N005 ( 1, 1) [001292] ------------ t1292 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1292 ref N008 ( 5, 13) [000554] DA--G------- * STORE_LCL_VAR ref V34 tmp20 d:1 [001336] ------------ IL_OFFSET void IL offset: 0x1e N001 ( 1, 1) [001294] ------------ t1294 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1294 ref N003 ( 1, 3) [000556] DA--G------- * STORE_LCL_VAR ref V35 tmp21 d:1 [001337] ------------ IL_OFFSET void IL offset: 0x1e N001 ( 1, 1) [000546] ------------ t546 = LCL_VAR int V33 tmp19 u:1 (last use) N002 ( 1, 1) [000547] -c---------- t547 = CNS_INT int 0 $c0 /--* t546 int +--* t547 int N003 ( 3, 3) [000548] J------N---- * NE void N004 ( 5, 5) [000549] ------------ * JTRUE void ------------ BB05 [01E..01F), preds={BB04} succs={BB06} [001338] ------------ IL_OFFSET void IL offset: 0x1e N003 ( 1, 1) [000550] ------------ t550 = LCL_VAR ref V35 tmp21 u:1 (last use) $105 /--* t550 ref [001457] ------------ t1457 = * PUTARG_REG ref REG rcx N004 ( 1, 1) [000551] ------------ t551 = LCL_VAR ref V35 tmp21 u:1 (last use) $105 /--* t551 ref [001458] ------------ t1458 = * PUTARG_REG ref REG rdx /--* t1457 ref arg0 in rcx +--* t1458 ref arg1 in rdx N005 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} [001339] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 1) [000015] ------------ t15 = LCL_VAR ref V00 this u:1 $100 /--* t15 ref N003 ( 2, 2) [000822] -c---------- t822 = * LEA(b+16) byref /--* t822 byref N004 ( 4, 4) [000016] n---GO------ t16 = * IND ref /--* t16 ref N006 ( 4, 4) [000018] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:1 [001340] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 1, 1) [000019] ------------ t19 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000020] -c---------- t20 = CNS_INT ref null $VN.Null /--* t19 ref +--* t20 ref N003 ( 6, 3) [000021] N----------- t21 = * NE int /--* t21 int N005 ( 6, 3) [000566] DA---------- * STORE_LCL_VAR int V36 tmp22 d:1 [001341] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 1, 1) [001295] ------------ t1295 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1295 ref N003 ( 1, 3) [000576] DA--G------- * STORE_LCL_VAR ref V37 tmp23 d:1 [001342] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 1, 1) [000568] ------------ t568 = LCL_VAR int V36 tmp22 u:1 (last use) N002 ( 1, 1) [000569] -c---------- t569 = CNS_INT int 0 $c0 /--* t568 int +--* t569 int N003 ( 3, 3) [000570] J------N---- * NE void N004 ( 5, 5) [000571] ------------ * JTRUE void ------------ BB07 [033..034), preds={BB06} succs={BB08} [001343] ------------ IL_OFFSET void IL offset: 0x33 N003 ( 2, 10) [000823] H----------- t823 = CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" $46 /--* t823 long N004 ( 4, 12) [000824] #---G------- t824 = * IND ref $106 /--* t824 ref [001459] ----G------- t1459 = * PUTARG_REG ref REG rcx N005 ( 1, 1) [000573] ------------ t573 = LCL_VAR ref V37 tmp23 u:1 (last use) $105 /--* t573 ref [001460] ------------ t1460 = * PUTARG_REG ref REG rdx /--* t1459 ref arg0 in rcx +--* t1460 ref arg1 in rdx N006 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} [001344] ------------ IL_OFFSET void IL offset: 0x41 N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR ref V00 this u:1 $100 /--* t25 ref N003 ( 2, 2) [000828] -c---------- t828 = * LEA(b+24) byref /--* t828 byref N004 ( 4, 4) [000026] n---GO------ t26 = * IND ref /--* t26 ref N006 ( 4, 4) [000028] DA--GO------ * STORE_LCL_VAR ref V05 loc1 d:1 [001345] ------------ IL_OFFSET void IL offset: 0x48 N001 ( 1, 1) [000029] ------------ t29 = LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000030] -c---------- t30 = CNS_INT ref null $VN.Null /--* t29 ref +--* t30 ref N003 ( 3, 3) [000031] J------N---- * EQ void N004 ( 5, 5) [000032] ------------ * JTRUE void ------------ BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} [001346] ------------ IL_OFFSET void IL offset: 0x4b N001 ( 1, 1) [000486] !----------- t486 = LCL_VAR ref V00 this u:1 $100 /--* t486 ref N002 ( 3, 2) [000487] #----O------ t487 = * IND long $2e8 /--* t487 long N004 ( 3, 3) [000489] DA---O------ * STORE_LCL_VAR long V29 tmp15 d:1 N001 ( 1, 1) [000491] ------------ t491 = LCL_VAR long V29 tmp15 u:1 $2e7 /--* t491 long N003 ( 2, 2) [000493] -c---------- t493 = * LEA(b+56) long /--* t493 long N004 ( 4, 4) [000494] #----------- t494 = * IND long $2e9 /--* t494 long N005 ( 7, 6) [000495] #----------- t495 = * IND long $2ea /--* t495 long N007 ( 8, 7) [000497] -c---------- t497 = * LEA(b+64) long /--* t497 long N008 ( 10, 9) [000501] n----------- t501 = * IND long /--* t501 long N010 ( 14, 12) [001266] DA---------- * STORE_LCL_VAR long V68 cse3 d:1 N011 ( 3, 2) [001267] ------------ t1267 = LCL_VAR long V68 cse3 u:1 N013 ( 1, 1) [000504] -c---------- t504 = CNS_INT long 0 $243 /--* t1267 long +--* t504 long N014 ( 19, 16) [000505] J------N---- * EQ void N015 ( 21, 18) [001148] ------------ * JTRUE void ------------ BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} N001 ( 3, 2) [001269] ------------ t1269 = LCL_VAR long V68 cse3 u:1 /--* t1269 long N003 ( 3, 3) [001150] DA---------- * STORE_LCL_VAR long V31 tmp17 d:3 ------------ BB11 [???..???), preds={BB09} succs={BB12} N003 ( 1, 1) [000490] ------?----- t490 = LCL_VAR long V29 tmp15 u:1 (last use) $2e7 /--* t490 long [001461] ------------ t1461 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000502] H-----?----- t502 = CNS_INT(h) long 0xd1ffab1e global ptr $49 /--* t502 long [001462] ------------ t1462 = * PUTARG_REG long REG rdx /--* t1461 long arg0 in rcx +--* t1462 long arg1 in rdx N005 ( 17, 18) [000503] --C-G-?----- t503 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $308 /--* t503 long N007 ( 17, 18) [001152] DA--G------- * STORE_LCL_VAR long V31 tmp17 d:2 ------------ BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} N001 ( 0, 0) [001247] ------------ t1247 = PHI_ARG long V31 tmp17 u:3 N002 ( 0, 0) [001246] ------------ t1246 = PHI_ARG long V31 tmp17 u:2 $308 /--* t1247 long +--* t1246 long N003 ( 0, 0) [001216] ------------ t1216 = * PHI long /--* t1216 long N005 ( 0, 0) [001217] DA---------- * STORE_LCL_VAR long V31 tmp17 d:1 N004 ( 1, 1) [000484] ------------ t484 = LCL_VAR ref V05 loc1 u:1 /--* t484 ref [001463] ------------ t1463 = * PUTARG_REG ref REG rcx N005 ( 1, 1) [000831] ------------ t831 = LCL_VAR long V31 tmp17 u:1 r11 REG r11 $342 /--* t831 long [001464] ------------ t1464 = * PUTARG_REG long REG r11 N006 ( 1, 1) [000500] ------------ t500 = LCL_VAR ref V01 arg1 u:1 $101 /--* t500 ref [001465] ------------ t1465 = * PUTARG_REG ref REG rdx N007 ( 1, 1) [000521] ------------ t521 = LCL_VAR long V31 tmp17 u:1 (last use) $342 /--* t521 long [001466] Dc---------- t1466 = * IND long REG NA /--* t1463 ref this in rcx +--* t1464 long arg1 in r11 +--* t1465 ref arg2 in rdx +--* t1466 long calli tgt N008 ( 27, 12) [000522] --CXG------- t522 = * CALL ind stub int $1c7 /--* t522 int N010 ( 31, 15) [000524] DA-XG------- * STORE_LCL_VAR int V15 tmp1 d:3 ------------ BB13 [054..061), preds={BB08} succs={BB14} [001347] ------------ IL_OFFSET void IL offset: 0x54 N002 ( 1, 1) [000033] ------------ t33 = LCL_VAR ref V01 arg1 u:1 $101 /--* t33 ref [001467] ------------ t1467 = * PUTARG_REG ref REG rcx N003 ( 1, 1) [000836] ------------ t836 = LCL_VAR ref V01 arg1 u:1 $101 /--* t836 ref N004 ( 3, 2) [000837] #----O------ t837 = * IND long $2e4 /--* t837 long N006 ( 4, 3) [000839] -c---------- t839 = * LEA(b+72) long /--* t839 long N007 ( 6, 5) [000840] #----O------ t840 = * IND long $2e6 /--* t840 long N009 ( 7, 6) [000842] -c---------- t842 = * LEA(b+24) long /--* t842 long N010 ( 9, 8) [000843] nc---O------ t843 = * IND long REG NA /--* t1467 ref this in rcx +--* t843 long control expr N011 ( 30, 18) [000035] --CXGO------ t35 = * CALLV vt-ind int System.Object.GetHashCode $1c5 /--* t35 int N013 ( 34, 21) [000038] DA-XGO------ * STORE_LCL_VAR int V15 tmp1 d:2 ------------ BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} N001 ( 0, 0) [001245] ------------ t1245 = PHI_ARG int V15 tmp1 u:3 $1c7 N002 ( 0, 0) [001244] ------------ t1244 = PHI_ARG int V15 tmp1 u:2 $1c5 /--* t1245 int +--* t1244 int N003 ( 0, 0) [001213] ------------ t1213 = * PHI int /--* t1213 int N005 ( 0, 0) [001214] DA---------- * STORE_LCL_VAR int V15 tmp1 d:1 N001 ( 3, 2) [000040] ------------ t40 = LCL_VAR int V15 tmp1 u:1 (last use) $3c0 /--* t40 int N003 ( 3, 3) [000042] DA---------- * STORE_LCL_VAR int V06 loc2 d:1 [001348] ------------ IL_OFFSET void IL offset: 0x62 N001 ( 1, 1) [000043] ------------ t43 = CNS_INT int 0 $c0 /--* t43 int N003 ( 1, 3) [000045] DA---------- * STORE_LCL_VAR int V07 loc3 d:1 [001349] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000046] ------------ t46 = LCL_VAR ref V00 this u:1 $100 /--* t46 ref N003 ( 2, 2) [000845] -c---------- t845 = * LEA(b+8) byref /--* t845 byref N004 ( 4, 4) [000578] n---GO------ t578 = * IND ref /--* t578 ref N006 ( 4, 4) [000580] DA--GO------ * STORE_LCL_VAR ref V39 tmp25 d:1 [001350] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000582] ------------ t582 = LCL_VAR ref V39 tmp25 u:1 /--* t582 ref [001441] -c---------- t1441 = * LEA(b+8) ref /--* t1441 ref N002 ( 3, 3) [000583] ---X-------- t583 = * IND int /--* t583 int N004 ( 3, 3) [000629] DA-X-------- * STORE_LCL_VAR int V40 tmp26 d:1 [001351] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000584] ------------ t584 = LCL_VAR ref V00 this u:1 $100 /--* t584 ref N003 ( 2, 2) [000847] -c---------- t847 = * LEA(b+48) byref /--* t847 byref N004 ( 4, 4) [000585] n---GO------ t585 = * IND long /--* t585 long N006 ( 4, 4) [000631] DA--GO------ * STORE_LCL_VAR long V41 tmp27 d:1 [001352] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000597] ------------ t597 = LCL_VAR int V40 tmp26 u:1 N002 ( 1, 4) [000598] -c---------- t598 = CNS_INT int 0x7FFFFFFF $ce /--* t597 int +--* t598 int N003 ( 6, 6) [000599] N--------U-- t599 = * LE int /--* t599 int N005 ( 6, 6) [000642] DA---------- * STORE_LCL_VAR int V43 tmp29 d:1 [001353] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [001296] ------------ t1296 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1296 ref N003 ( 1, 3) [000652] DA--G------- * STORE_LCL_VAR ref V44 tmp30 d:1 [001354] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [001297] ------------ t1297 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1297 ref N003 ( 1, 3) [000654] DA--G------- * STORE_LCL_VAR ref V45 tmp31 d:1 [001355] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000644] ------------ t644 = LCL_VAR int V43 tmp29 u:1 (last use) N002 ( 1, 1) [000645] -c---------- t645 = CNS_INT int 0 $c0 /--* t644 int +--* t645 int N003 ( 3, 3) [000646] J------N---- * NE void N004 ( 5, 5) [000647] ------------ * JTRUE void ------------ BB15 [064..065), preds={BB14} succs={BB16} [001356] ------------ IL_OFFSET void IL offset: 0x64 N003 ( 1, 1) [000648] ------------ t648 = LCL_VAR ref V45 tmp31 u:1 (last use) $105 /--* t648 ref [001468] ------------ t1468 = * PUTARG_REG ref REG rcx N004 ( 1, 1) [000649] ------------ t649 = LCL_VAR ref V45 tmp31 u:1 (last use) $105 /--* t649 ref [001469] ------------ t1469 = * PUTARG_REG ref REG rdx /--* t1468 ref arg0 in rcx +--* t1469 ref arg1 in rdx N005 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} [001357] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000604] ------------ t604 = LCL_VAR long V41 tmp27 u:1 (last use) N002 ( 1, 1) [000047] ------------ t47 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t47 int N003 ( 2, 3) [000605] ---------U-- t605 = * CAST long <- ulong <- uint $310 /--* t604 long +--* t605 long N004 ( 7, 7) [000606] ------------ t606 = * MUL long N005 ( 1, 1) [000607] -c---------- t607 = CNS_INT int 32 $d2 /--* t606 long +--* t607 int N006 ( 9, 9) [000608] ------------ t608 = * RSZ long N007 ( 1, 1) [000610] -c---------- t610 = CNS_INT long 1 $247 /--* t608 long +--* t610 long N008 ( 11, 11) [000611] ------------ t611 = * ADD long N009 ( 1, 1) [000612] ------------ t612 = LCL_VAR int V40 tmp26 u:1 /--* t612 int N010 ( 2, 3) [000613] ---------U-- t613 = * CAST long <- ulong <- uint /--* t611 long +--* t613 long N011 ( 17, 17) [000614] ------------ t614 = * MUL long N012 ( 1, 1) [000615] -c---------- t615 = CNS_INT int 32 $d2 /--* t614 long +--* t615 int N013 ( 19, 19) [000616] ------------ t616 = * RSZ long /--* t616 long N014 ( 20, 21) [000617] ------------ t617 = * CAST int <- uint <- long /--* t617 int N016 ( 20, 21) [000619] DA---------- * STORE_LCL_VAR int V42 tmp28 d:1 [001358] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000621] ------------ t621 = LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000622] ------------ t622 = LCL_VAR int V40 tmp26 u:1 (last use) /--* t621 int +--* t622 int N003 ( 22, 5) [000623] ---X-------- t623 = * UMOD int N004 ( 1, 1) [000620] ------------ t620 = LCL_VAR int V42 tmp28 u:1 /--* t623 int +--* t620 int N005 ( 27, 7) [000624] ---X-------- t624 = * EQ int /--* t624 int N007 ( 27, 7) [000665] DA-X-------- * STORE_LCL_VAR int V46 tmp32 d:1 [001359] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [001298] ------------ t1298 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1298 ref N003 ( 1, 3) [000675] DA--G------- * STORE_LCL_VAR ref V47 tmp33 d:1 [001360] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [001299] ------------ t1299 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1299 ref N003 ( 1, 3) [000677] DA--G------- * STORE_LCL_VAR ref V48 tmp34 d:1 [001361] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000667] ------------ t667 = LCL_VAR int V46 tmp32 u:1 (last use) N002 ( 1, 1) [000668] -c---------- t668 = CNS_INT int 0 $c0 /--* t667 int +--* t668 int N003 ( 3, 3) [000669] J------N---- * NE void N004 ( 5, 5) [000670] ------------ * JTRUE void ------------ BB17 [064..065), preds={BB16} succs={BB18} [001362] ------------ IL_OFFSET void IL offset: 0x64 N003 ( 1, 1) [000671] ------------ t671 = LCL_VAR ref V48 tmp34 u:1 (last use) $105 /--* t671 ref [001470] ------------ t1470 = * PUTARG_REG ref REG rcx N004 ( 1, 1) [000672] ------------ t672 = LCL_VAR ref V48 tmp34 u:1 (last use) $105 /--* t672 ref [001471] ------------ t1471 = * PUTARG_REG ref REG rdx /--* t1470 ref arg0 in rcx +--* t1471 ref arg1 in rdx N005 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} [001363] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000627] ------------ t627 = LCL_VAR int V42 tmp28 u:1 N002 ( 1, 1) [000581] ------------ t581 = LCL_VAR ref V39 tmp25 u:1 /--* t581 ref [001443] -c---------- t1443 = * LEA(b+8) ref /--* t1443 ref N003 ( 3, 3) [000854] -c-X-------- t854 = * IND int /--* t627 int +--* t854 int N004 ( 8, 11) [000855] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void N005 ( 1, 1) [000852] ------------ t852 = LCL_VAR ref V39 tmp25 u:1 (last use) N006 ( 1, 1) [000853] ------------ t853 = LCL_VAR int V42 tmp28 u:1 (last use) /--* t853 int N007 ( 2, 3) [000856] ------------ t856 = * CAST long <- int /--* t852 ref +--* t856 long N012 ( 5, 6) [000861] -------N---- t861 = * LEA(b+(i*4)+16) byref /--* t861 byref N017 ( 19, 24) [000591] DA-XG------- * STORE_LCL_VAR byref V38 tmp24 d:1 N001 ( 1, 1) [000592] ------------ t592 = LCL_VAR byref V38 tmp24 u:1 $81 /--* t592 byref N003 ( 5, 4) [000051] DA---------- * STORE_LCL_VAR byref V08 loc4 d:1 [001364] ------------ IL_OFFSET void IL offset: 0x6d N001 ( 1, 1) [000052] ------------ t52 = LCL_VAR byref V08 loc4 u:1 (last use) $81 /--* t52 byref N002 ( 3, 2) [000053] *--XG------- t53 = * IND int N003 ( 1, 1) [000054] -c---------- t54 = CNS_INT int -1 $c4 /--* t53 int +--* t54 int N004 ( 5, 4) [000055] ---XG------- t55 = * ADD int /--* t55 int N006 ( 5, 4) [000057] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:1 [001365] ------------ IL_OFFSET void IL offset: 0x74 N001 ( 1, 1) [000058] ------------ t58 = LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000059] -c---------- t59 = CNS_INT ref null $VN.Null /--* t58 ref +--* t59 ref N003 ( 3, 3) [000060] J------N---- * NE void N004 ( 5, 5) [000061] ------------ * JTRUE void ------------ BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} [001366] ------------ IL_OFFSET void IL offset: 0xff N001 ( 1, 1) [000353] !----------- t353 = LCL_VAR ref V00 this u:1 $100 /--* t353 ref N002 ( 3, 2) [000354] #----O------ t354 = * IND long $2e8 /--* t354 long N004 ( 3, 3) [000356] DA---O------ * STORE_LCL_VAR long V24 tmp10 d:1 N001 ( 1, 1) [000358] ------------ t358 = LCL_VAR long V24 tmp10 u:1 $2e7 /--* t358 long N003 ( 2, 2) [000360] -c---------- t360 = * LEA(b+56) long /--* t360 long N004 ( 4, 4) [000361] #----------- t361 = * IND long $2e9 /--* t361 long N005 ( 7, 6) [000362] #----------- t362 = * IND long $2ea /--* t362 long N007 ( 8, 7) [000364] -c---------- t364 = * LEA(b+32) long /--* t364 long N008 ( 10, 9) [000365] n----------- t365 = * IND long /--* t365 long N010 ( 14, 12) [001271] DA---------- * STORE_LCL_VAR long V69 cse4 d:1 N011 ( 3, 2) [001272] ------------ t1272 = LCL_VAR long V69 cse4 u:1 N013 ( 1, 1) [000368] -c---------- t368 = CNS_INT long 0 $243 /--* t1272 long +--* t368 long N014 ( 19, 16) [000369] J------N---- * EQ void N015 ( 21, 18) [001153] ------------ * JTRUE void ------------ BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} N001 ( 3, 2) [001274] ------------ t1274 = LCL_VAR long V69 cse4 u:1 /--* t1274 long N003 ( 7, 5) [001155] DA---------- * STORE_LCL_VAR long V25 tmp11 d:3 ------------ BB21 [???..???), preds={BB19} succs={BB22} N003 ( 1, 1) [000357] ------?----- t357 = LCL_VAR long V24 tmp10 u:1 (last use) $2e7 /--* t357 long [001472] ------------ t1472 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000366] H-----?----- t366 = CNS_INT(h) long 0xd1ffab1e global ptr $4f /--* t366 long [001473] ------------ t1473 = * PUTARG_REG long REG rdx /--* t1472 long arg0 in rcx +--* t1473 long arg1 in rdx N005 ( 17, 18) [000367] --C-G-?----- t367 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $325 /--* t367 long N007 ( 21, 21) [001157] DA--G------- * STORE_LCL_VAR long V25 tmp11 d:2 ------------ BB22 [???..106), preds={BB20,BB21} succs={BB23} N001 ( 0, 0) [001243] ------------ t1243 = PHI_ARG long V25 tmp11 u:3 N002 ( 0, 0) [001242] ------------ t1242 = PHI_ARG long V25 tmp11 u:2 $325 /--* t1243 long +--* t1242 long N003 ( 0, 0) [001198] ------------ t1198 = * PHI long /--* t1198 long N005 ( 0, 0) [001199] DA---------- * STORE_LCL_VAR long V25 tmp11 d:1 N002 ( 3, 2) [000382] ------------ t382 = LCL_VAR long V25 tmp11 u:1 (last use) $344 /--* t382 long [001474] ------------ t1474 = * PUTARG_REG long REG rcx /--* t1474 long arg0 in rcx N003 ( 17, 8) [000352] --CXG------- t352 = * CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default $223 /--* t352 ref N005 ( 17, 8) [000386] DA-XG------- * STORE_LCL_VAR ref V12 loc8 d:1 ------------ BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} N001 ( 0, 0) [001238] ------------ t1238 = PHI_ARG int V07 loc3 u:6 N002 ( 0, 0) [001235] ------------ t1235 = PHI_ARG int V07 loc3 u:1 $c0 /--* t1238 int +--* t1235 int N003 ( 0, 0) [001177] ------------ t1177 = * PHI int /--* t1177 int N005 ( 0, 0) [001178] DA---------- * STORE_LCL_VAR int V07 loc3 d:5 N001 ( 0, 0) [001239] ------------ t1239 = PHI_ARG int V09 loc5 u:5 N002 ( 0, 0) [001236] ------------ t1236 = PHI_ARG int V09 loc5 u:1 /--* t1239 int +--* t1236 int N003 ( 0, 0) [001174] ------------ t1174 = * PHI int /--* t1174 int N005 ( 0, 0) [001175] DA---------- * STORE_LCL_VAR int V09 loc5 d:4 [001367] ------------ IL_OFFSET void IL offset: 0x106 N001 ( 1, 1) [000388] ------------ t388 = LCL_VAR ref V04 loc0 u:1 /--* t388 ref [001446] -c---------- t1446 = * LEA(b+8) ref /--* t1446 ref N002 ( 3, 3) [000389] ---X-------- t389 = * IND int /--* t389 int N004 ( 3, 3) [001316] DA-X-------- * STORE_LCL_VAR int V76 cse11 N005 ( 1, 1) [001317] ------------ t1317 = LCL_VAR int V76 cse11 N007 ( 1, 1) [000387] ------------ t387 = LCL_VAR int V09 loc5 u:4 $3c2 /--* t1317 int +--* t387 int N008 ( 6, 6) [000390] N--X---N-U-- * LE void N009 ( 8, 8) [000391] ---X-------- * JTRUE void ------------ BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} [001368] ------------ IL_OFFSET void IL offset: 0x110 N001 ( 1, 1) [000869] ------------ t869 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000870] ------------ t870 = LCL_VAR int V09 loc5 u:4 $3c2 /--* t870 int N003 ( 2, 3) [000873] ------------ t873 = * CAST long <- int $326 N004 ( 1, 1) [000880] -c---------- t880 = CNS_INT long 3 $24b /--* t873 long +--* t880 long N005 ( 7, 7) [000881] ------------ t881 = * MUL long $327 /--* t881 long N007 ( 7, 7) [001276] DA---------- * STORE_LCL_VAR long V70 cse5 d:1 N008 ( 1, 1) [001277] ------------ t1277 = LCL_VAR long V70 cse5 u:1 $327 /--* t869 ref +--* t1277 long N014 ( 11, 11) [000878] -------N---- t878 = * LEA(b+(i*8)+16) byref /--* t878 byref N018 ( 23, 23) [001249] DA--G------- * STORE_LCL_VAR byref V65 cse0 d:1 N019 ( 1, 1) [001250] ------------ t1250 = LCL_VAR byref V65 cse0 u:1 /--* t1250 byref N022 ( 25, 25) [000868] -c---------- t868 = * LEA(b+16) byref /--* t868 byref N023 ( 27, 27) [000396] *c-XG------- t396 = * IND int N024 ( 1, 1) [000397] ------------ t397 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t396 int +--* t397 int N025 ( 29, 29) [000398] N--XG--N-U-- * NE void N026 ( 31, 31) [000399] ---XG------- * JTRUE void ------------ BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} [001369] ------------ IL_OFFSET void IL offset: 0x120 N004 ( 1, 1) [000883] ------------ t883 = LCL_VAR ref V04 loc0 u:1 N005 ( 1, 1) [001279] ------------ t1279 = LCL_VAR long V70 cse5 u:1 $327 /--* t883 ref +--* t1279 long N010 ( 4, 4) [000892] -c---------- t892 = * LEA(b+(i*8)+16) byref /--* t892 byref N013 ( 12, 11) [000897] *---G--N---- t897 = * IND ref /--* t897 ref [001475] ----G------- t1475 = * PUTARG_REG ref REG rdx N014 ( 1, 1) [000418] ------------ t418 = LCL_VAR ref V12 loc8 u:1 $223 /--* t418 ref [001476] ------------ t1476 = * PUTARG_REG ref REG rcx N015 ( 1, 1) [000424] ------------ t424 = LCL_VAR ref V01 arg1 u:1 $101 /--* t424 ref [001477] ------------ t1477 = * PUTARG_REG ref REG r8 N016 ( 1, 1) [000901] ------------ t901 = LCL_VAR ref V12 loc8 u:1 $223 /--* t901 ref N017 ( 3, 2) [000902] #--X-------- t902 = * IND long $463 /--* t902 long N019 ( 4, 3) [000904] -c---------- t904 = * LEA(b+72) long /--* t904 long N020 ( 6, 5) [000905] #--X-------- t905 = * IND long $465 /--* t905 long N022 ( 7, 6) [000907] -c---------- t907 = * LEA(b+32) long /--* t907 long N023 ( 9, 8) [000908] nc-X-------- t908 = * IND long REG NA /--* t1475 ref arg1 in rdx +--* t1476 ref this in rcx +--* t1477 ref arg2 in r8 +--* t908 long control expr N024 ( 43, 32) [000425] --CXG------- t425 = * CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals $581 N025 ( 1, 1) [000426] -c---------- t426 = CNS_INT int 0 $c0 /--* t425 int +--* t426 int N026 ( 45, 34) [000427] J--XG--N---- * NE void $1bd N027 ( 47, 36) [000428] ---XG------- * JTRUE void ------------ BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} [001370] ------------ IL_OFFSET void IL offset: 0x157 N001 ( 1, 1) [001252] ------------ t1252 = LCL_VAR byref V65 cse0 u:1 $82 /--* t1252 byref N003 ( 2, 2) [000932] -c---------- t932 = * LEA(b+20) byref /--* t932 byref N004 ( 4, 4) [000404] *--XG------- t404 = * IND int /--* t404 int N006 ( 4, 4) [000406] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:5 [001371] ------------ IL_OFFSET void IL offset: 0x166 N001 ( 1, 1) [000407] ------------ t407 = LCL_VAR int V07 loc3 u:5 (last use) $3c1 N002 ( 1, 1) [000408] -c---------- t408 = CNS_INT int 1 $c1 /--* t407 int +--* t408 int N003 ( 3, 3) [000409] ------------ t409 = * ADD int $605 /--* t409 int N005 ( 3, 3) [000411] DA---------- * STORE_LCL_VAR int V07 loc3 d:6 [001372] ------------ IL_OFFSET void IL offset: 0x16a N001 ( 1, 1) [001321] ------------ t1321 = LCL_VAR int V76 cse11 N002 ( 1, 1) [000412] ------------ t412 = LCL_VAR int V07 loc3 u:6 $605 /--* t1321 int +--* t412 int N003 ( 3, 3) [000415] N------N-U-- * LT void N004 ( 5, 5) [000416] ------------ * JTRUE void ------------ BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} ------------ BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} [001373] ------------ IL_OFFSET void IL offset: 0x137 N001 ( 2, 2) [000429] ------------ t429 = LCL_VAR ubyte V03 arg3 u:1 $140 N003 ( 1, 1) [000430] -c---------- t430 = CNS_INT ubyte 1 $c1 /--* t429 ubyte +--* t430 ubyte N004 ( 5, 6) [000431] N------N-U-- * NE void $1bf N005 ( 7, 8) [000432] ------------ * JTRUE void ------------ BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} [001374] ------------ IL_OFFSET void IL offset: 0x13b N001 ( 1, 1) [001253] ------------ t1253 = LCL_VAR byref V65 cse0 u:1 $82 /--* t1253 byref N003 ( 2, 2) [000911] ------------ t911 = * LEA(b+8) byref N005 ( 1, 1) [000479] ------------ t479 = LCL_VAR ref V02 arg2 u:1 (last use) $102 /--* t911 byref +--* t479 ref [001375] -A-XG------- * STOREIND ref ------------ BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} [001376] ------------ IL_OFFSET void IL offset: 0x14b N001 ( 2, 2) [000433] ------------ t433 = LCL_VAR ubyte V03 arg3 u:1 (last use) $140 N003 ( 1, 1) [000434] -c---------- t434 = CNS_INT ubyte 2 $c2 /--* t433 ubyte +--* t434 ubyte N004 ( 5, 6) [000435] N------N-U-- * EQ void $600 N005 ( 7, 8) [000436] ------------ * JTRUE void ------------ BB31 [???..???) (return), preds={BB30,BB41} succs={} N001 ( 1, 1) [000437] ------------ t437 = CNS_INT int 0 $c0 /--* t437 int N002 ( 2, 2) [000811] ------------ * RETURN int $1f3 ------------ BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} N001 ( 0, 0) [001229] ------------ t1229 = PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [001218] ------------ t1218 = PHI_ARG int V07 loc3 u:1 $c0 /--* t1229 int +--* t1218 int N003 ( 0, 0) [001207] ------------ t1207 = * PHI int /--* t1207 int N005 ( 0, 0) [001208] DA---------- * STORE_LCL_VAR int V07 loc3 d:3 N001 ( 0, 0) [001230] ------------ t1230 = PHI_ARG int V09 loc5 u:3 N002 ( 0, 0) [001219] ------------ t1219 = PHI_ARG int V09 loc5 u:1 /--* t1230 int +--* t1219 int N003 ( 0, 0) [001204] ------------ t1204 = * PHI int /--* t1204 int N005 ( 0, 0) [001205] DA---------- * STORE_LCL_VAR int V09 loc5 d:2 [001377] ------------ IL_OFFSET void IL offset: 0x177 N001 ( 1, 1) [000063] ------------ t63 = LCL_VAR ref V04 loc0 u:1 /--* t63 ref [001448] -c---------- t1448 = * LEA(b+8) ref /--* t1448 ref N002 ( 3, 3) [000064] ---X-------- t64 = * IND int /--* t64 int N004 ( 3, 3) [001323] DA-X-------- * STORE_LCL_VAR int V76 cse11 N005 ( 1, 1) [001324] ------------ t1324 = LCL_VAR int V76 cse11 N007 ( 1, 1) [000062] ------------ t62 = LCL_VAR int V09 loc5 u:2 $3c4 /--* t1324 int +--* t62 int N008 ( 6, 6) [000065] N--X---N-U-- * LE void N009 ( 8, 8) [000066] ---X-------- * JTRUE void ------------ BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} [001378] ------------ IL_OFFSET void IL offset: 0x17e N001 ( 1, 1) [000949] ------------ t949 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000950] ------------ t950 = LCL_VAR int V09 loc5 u:2 $3c4 /--* t950 int N003 ( 2, 3) [000953] ------------ t953 = * CAST long <- int $6e1 N004 ( 1, 1) [000960] -c---------- t960 = CNS_INT long 3 $24b /--* t953 long +--* t960 long N005 ( 7, 7) [000961] ------------ t961 = * MUL long $6e2 /--* t961 long N007 ( 7, 7) [001281] DA---------- * STORE_LCL_VAR long V71 cse6 d:1 N008 ( 1, 1) [001282] ------------ t1282 = LCL_VAR long V71 cse6 u:1 $6e2 /--* t949 ref +--* t1282 long N014 ( 11, 11) [000958] -------N---- t958 = * LEA(b+(i*8)+16) byref /--* t958 byref N018 ( 23, 23) [001255] DA--G------- * STORE_LCL_VAR byref V66 cse1 d:1 N019 ( 1, 1) [001256] ------------ t1256 = LCL_VAR byref V66 cse1 u:1 /--* t1256 byref N022 ( 25, 25) [000948] -c---------- t948 = * LEA(b+16) byref /--* t948 byref N023 ( 27, 27) [000212] *c-XG------- t212 = * IND int N024 ( 1, 1) [000213] ------------ t213 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t212 int +--* t213 int N025 ( 29, 29) [000214] N--XG--N-U-- * NE void N026 ( 31, 31) [000215] ---XG------- * JTRUE void ------------ BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} [001379] ------------ IL_OFFSET void IL offset: 0x18e N001 ( 1, 1) [000963] ------------ t963 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [001284] ------------ t1284 = LCL_VAR long V71 cse6 u:1 $6e2 /--* t963 ref +--* t1284 long N007 ( 4, 4) [000972] -c---------- t972 = * LEA(b+(i*8)+16) byref /--* t972 byref N010 ( 12, 11) [000977] *---G--N---- t977 = * IND ref /--* t977 ref N012 ( 12, 11) [000246] DA--G------- * STORE_LCL_VAR ref V17 tmp3 d:1 [001380] ------------ IL_OFFSET void IL offset: 0x18e N001 ( 1, 1) [000241] !----------- t241 = LCL_VAR ref V00 this u:1 $100 /--* t241 ref N002 ( 3, 2) [000242] #----O------ t242 = * IND long $2e8 /--* t242 long N004 ( 3, 3) [000244] DA---O------ * STORE_LCL_VAR long V16 tmp2 d:1 N001 ( 1, 1) [000249] ------------ t249 = LCL_VAR long V16 tmp2 u:1 $2e7 /--* t249 long N003 ( 2, 2) [000251] -c---------- t251 = * LEA(b+56) long /--* t251 long N004 ( 4, 4) [000252] #----------- t252 = * IND long $2e9 /--* t252 long N005 ( 7, 6) [000253] #----------- t253 = * IND long $2ea /--* t253 long N007 ( 8, 7) [000255] -c---------- t255 = * LEA(b+48) long /--* t255 long N008 ( 10, 9) [000259] n----------- t259 = * IND long /--* t259 long N010 ( 10, 9) [001261] DA---------- * STORE_LCL_VAR long V67 cse2 d:1 N011 ( 1, 1) [001262] ------------ t1262 = LCL_VAR long V67 cse2 u:1 N013 ( 1, 1) [000262] -c---------- t262 = CNS_INT long 0 $243 /--* t1262 long +--* t262 long N014 ( 13, 12) [000263] J------N---- * EQ void N015 ( 15, 14) [001163] ------------ * JTRUE void ------------ BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} N001 ( 1, 1) [001264] ------------ t1264 = LCL_VAR long V67 cse2 u:1 /--* t1264 long N003 ( 1, 3) [001165] DA---------- * STORE_LCL_VAR long V19 tmp5 d:3 ------------ BB36 [???..???), preds={BB34} succs={BB37} N003 ( 1, 1) [000248] ------?----- t248 = LCL_VAR long V16 tmp2 u:1 (last use) $2e7 /--* t248 long [001478] ------------ t1478 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000260] H-----?----- t260 = CNS_INT(h) long 0xd1ffab1e global ptr $63 /--* t260 long [001479] ------------ t1479 = * PUTARG_REG long REG rdx /--* t1478 long arg0 in rcx +--* t1479 long arg1 in rdx N005 ( 17, 18) [000261] --C-G-?----- t261 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $6e7 /--* t261 long N007 ( 17, 18) [001167] DA--G------- * STORE_LCL_VAR long V19 tmp5 d:2 ------------ BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} N001 ( 0, 0) [001234] ------------ t1234 = PHI_ARG long V19 tmp5 u:3 N002 ( 0, 0) [001233] ------------ t1233 = PHI_ARG long V19 tmp5 u:2 $6e7 /--* t1234 long +--* t1233 long N003 ( 0, 0) [001210] ------------ t1210 = * PHI long /--* t1210 long N005 ( 0, 0) [001211] DA---------- * STORE_LCL_VAR long V19 tmp5 d:1 N005 ( 1, 1) [000234] ------------ t234 = LCL_VAR ref V05 loc1 u:1 /--* t234 ref [001480] ------------ t1480 = * PUTARG_REG ref REG rcx N006 ( 1, 1) [000980] ------------ t980 = LCL_VAR long V19 tmp5 u:1 r11 REG r11 $349 /--* t980 long [001481] ------------ t1481 = * PUTARG_REG long REG r11 N007 ( 1, 1) [000247] ------------ t247 = LCL_VAR ref V17 tmp3 u:1 (last use) /--* t247 ref [001482] ------------ t1482 = * PUTARG_REG ref REG rdx N008 ( 1, 1) [000258] ------------ t258 = LCL_VAR ref V01 arg1 u:1 $101 /--* t258 ref [001483] ------------ t1483 = * PUTARG_REG ref REG r8 N009 ( 1, 1) [000279] ------------ t279 = LCL_VAR long V19 tmp5 u:1 (last use) $349 /--* t279 long [001484] Dc---------- t1484 = * IND long REG NA /--* t1480 ref this in rcx +--* t1481 long arg1 in r11 +--* t1482 ref arg2 in rdx +--* t1483 ref arg3 in r8 +--* t1484 long calli tgt N010 ( 28, 14) [000280] --CXG------- t280 = * CALL ind stub int $1ef N011 ( 1, 1) [000281] -c---------- t281 = CNS_INT int 0 $c0 /--* t280 int +--* t281 int N012 ( 30, 16) [000282] J--XG--N---- * EQ void $817 N013 ( 32, 18) [000283] ---XG------- * JTRUE void ------------ BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} [001381] ------------ IL_OFFSET void IL offset: 0x1a4 N001 ( 2, 2) [000284] ------------ t284 = LCL_VAR ubyte V03 arg3 u:1 $140 N003 ( 1, 1) [000285] -c---------- t285 = CNS_INT ubyte 1 $c1 /--* t284 ubyte +--* t285 ubyte N004 ( 5, 6) [000286] N------N-U-- * NE void $1bf N005 ( 7, 8) [000287] ------------ * JTRUE void ------------ BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} [001382] ------------ IL_OFFSET void IL offset: 0x1a8 N001 ( 1, 1) [001258] ------------ t1258 = LCL_VAR byref V66 cse1 u:1 $91 /--* t1258 byref N003 ( 2, 2) [000987] ------------ t987 = * LEA(b+8) byref N005 ( 1, 1) [000334] ------------ t334 = LCL_VAR ref V02 arg2 u:1 (last use) $102 /--* t987 byref +--* t334 ref [001383] -A-XG------- * STOREIND ref ------------ BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} [001384] ------------ IL_OFFSET void IL offset: 0x1b8 N001 ( 2, 2) [000288] ------------ t288 = LCL_VAR ubyte V03 arg3 u:1 (last use) $140 N003 ( 1, 1) [000289] -c---------- t289 = CNS_INT ubyte 2 $c2 /--* t288 ubyte +--* t289 ubyte N004 ( 5, 6) [000290] N------N-U-- * EQ void $600 N005 ( 7, 8) [000291] ------------ * JTRUE void ------------ BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} ------------ BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} [001385] ------------ IL_OFFSET void IL offset: 0x1c4 N001 ( 1, 1) [001259] ------------ t1259 = LCL_VAR byref V66 cse1 u:1 $91 /--* t1259 byref N003 ( 2, 2) [001009] -c---------- t1009 = * LEA(b+20) byref /--* t1009 byref N004 ( 4, 4) [000220] *--XG------- t220 = * IND int /--* t220 int N006 ( 4, 4) [000222] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:3 [001386] ------------ IL_OFFSET void IL offset: 0x1d3 N001 ( 1, 1) [000223] ------------ t223 = LCL_VAR int V07 loc3 u:3 (last use) $3c3 N002 ( 1, 1) [000224] -c---------- t224 = CNS_INT int 1 $c1 /--* t223 int +--* t224 int N003 ( 3, 3) [000225] ------------ t225 = * ADD int $81a /--* t225 int N005 ( 3, 3) [000227] DA---------- * STORE_LCL_VAR int V07 loc3 d:4 [001387] ------------ IL_OFFSET void IL offset: 0x1d7 N001 ( 1, 1) [001328] ------------ t1328 = LCL_VAR int V76 cse11 N002 ( 1, 1) [000228] ------------ t228 = LCL_VAR int V07 loc3 u:4 $81a /--* t1328 int +--* t228 int N003 ( 3, 3) [000231] N------N-U-- * LT void N004 ( 5, 5) [000232] ------------ * JTRUE void ------------ BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} ------------ BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} N001 ( 0, 0) [001237] ------------ t1237 = PHI_ARG int V07 loc3 u:5 $3c1 N002 ( 0, 0) [001228] ------------ t1228 = PHI_ARG int V07 loc3 u:3 $3c3 /--* t1237 int +--* t1228 int N003 ( 0, 0) [001180] ------------ t1180 = * PHI int /--* t1180 int N005 ( 0, 0) [001181] DA---------- * STORE_LCL_VAR int V07 loc3 d:2 [001388] ------------ IL_OFFSET void IL offset: 0x1e4 N001 ( 1, 1) [000067] ------------ t67 = LCL_VAR ref V00 this u:1 $100 /--* t67 ref N003 ( 2, 2) [001025] -c---------- t1025 = * LEA(b+64) byref /--* t1025 byref N004 ( 4, 4) [000068] nc--GO------ t68 = * IND int N005 ( 1, 1) [000069] -c---------- t69 = CNS_INT int 0 $c0 /--* t68 int +--* t69 int N006 ( 6, 6) [000070] J---GO-N---- * LE void N007 ( 8, 8) [000071] ----GO------ * JTRUE void ------------ BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} [001389] ------------ IL_OFFSET void IL offset: 0x1ed N001 ( 1, 1) [000171] ------------ t171 = LCL_VAR ref V00 this u:1 $100 /--* t171 ref N003 ( 2, 2) [001027] -c---------- t1027 = * LEA(b+60) byref /--* t1027 byref N004 ( 4, 4) [000172] n---GO------ t172 = * IND int /--* t172 int N006 ( 8, 7) [001306] DA--GO------ * STORE_LCL_VAR int V74 cse9 d:1 N007 ( 3, 2) [001307] ------------ t1307 = LCL_VAR int V74 cse9 u:1 /--* t1307 int N010 ( 15, 12) [000174] DA--GO------ * STORE_LCL_VAR int V10 loc6 d:3 [001390] ------------ IL_OFFSET void IL offset: 0x1f5 N001 ( 3, 2) [001309] ------------ t1309 = LCL_VAR int V74 cse9 u:1 /--* t1309 int N003 ( 3, 3) [001032] DA--G------- * STORE_LCL_VAR int V62 tmp48 d:1 N004 ( 1, 1) [001033] ------------ t1033 = LCL_VAR int V62 tmp48 u:1 N005 ( 1, 1) [001329] ------------ t1329 = LCL_VAR int V76 cse11 /--* t1033 int +--* t1329 int N006 ( 6, 9) [001036] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void N007 ( 1, 1) [001030] ------------ t1030 = LCL_VAR ref V04 loc0 u:1 N008 ( 1, 1) [001034] ------------ t1034 = LCL_VAR int V62 tmp48 u:1 (last use) /--* t1034 int N009 ( 2, 3) [001037] ------------ t1037 = * CAST long <- int N010 ( 1, 1) [001047] -c---------- t1047 = CNS_INT long 3 $24b /--* t1037 long +--* t1047 long N011 ( 7, 7) [001048] ------------ t1048 = * MUL long /--* t1030 ref +--* t1048 long N022 ( 31, 34) [001029] -c---------- t1029 = * LEA(b+(i*8)+36) byref /--* t1029 byref N023 ( 33, 36) [000181] *--XG------- t181 = * IND int /--* t181 int N024 ( 34, 37) [001050] ---XG------- t1050 = * NEG int N025 ( 1, 1) [000175] -c---------- t175 = CNS_INT int -3 $e1 /--* t1050 int +--* t175 int N026 ( 36, 39) [000182] ---XG------- t182 = * ADD int N027 ( 1, 1) [000183] -c---------- t183 = CNS_INT int -1 $c4 /--* t182 int +--* t183 int N028 ( 41, 41) [000184] ---XG------- t184 = * GE int /--* t184 int N030 ( 45, 44) [000688] DA-XG------- * STORE_LCL_VAR int V49 tmp35 d:1 [001391] ------------ IL_OFFSET void IL offset: 0x1f5 N001 ( 1, 1) [001300] ------------ t1300 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1300 ref N003 ( 5, 4) [000698] DA--G------- * STORE_LCL_VAR ref V50 tmp36 d:1 [001392] ------------ IL_OFFSET void IL offset: 0x1f5 N001 ( 3, 2) [000690] ------------ t690 = LCL_VAR int V49 tmp35 u:1 (last use) N002 ( 1, 1) [000691] -c---------- t691 = CNS_INT int 0 $c0 /--* t690 int +--* t691 int N003 ( 5, 4) [000692] J------N---- * NE void N004 ( 7, 6) [000693] ------------ * JTRUE void ------------ BB46 [1F5..1F6), preds={BB45} succs={BB47} [001393] ------------ IL_OFFSET void IL offset: 0x1f5 N003 ( 2, 10) [001051] H----------- t1051 = CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" $5e /--* t1051 long N004 ( 4, 12) [001052] #---G------- t1052 = * IND ref $114 /--* t1052 ref [001485] ----G------- t1485 = * PUTARG_REG ref REG rcx N005 ( 3, 2) [000695] ------------ t695 = LCL_VAR ref V50 tmp36 u:1 (last use) $105 /--* t695 ref [001486] ------------ t1486 = * PUTARG_REG ref REG rdx /--* t1485 ref arg0 in rcx +--* t1486 ref arg1 in rdx N006 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} [001394] ------------ IL_OFFSET void IL offset: 0x219 N001 ( 1, 1) [000190] ------------ t190 = LCL_VAR ref V00 this u:1 $100 /--* t190 ref N003 ( 2, 2) [001056] -c---------- t1056 = * LEA(b+60) byref N005 ( 1, 1) [000193] ------------ t193 = LCL_VAR ref V00 this u:1 $100 /--* t193 ref N007 ( 2, 2) [001075] -c---------- t1075 = * LEA(b+60) byref /--* t1075 byref N008 ( 4, 4) [000194] n---GO------ t194 = * IND int /--* t194 int N010 ( 4, 4) [001061] DA--GO------ * STORE_LCL_VAR int V63 tmp49 d:1 N011 ( 1, 1) [001062] ------------ t1062 = LCL_VAR int V63 tmp49 u:1 N012 ( 1, 1) [001330] ------------ t1330 = LCL_VAR int V76 cse11 /--* t1062 int +--* t1330 int N013 ( 6, 9) [001065] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void N014 ( 1, 1) [001059] ------------ t1059 = LCL_VAR ref V04 loc0 u:1 N015 ( 1, 1) [001063] ------------ t1063 = LCL_VAR int V63 tmp49 u:1 (last use) /--* t1063 int N016 ( 2, 3) [001066] ------------ t1066 = * CAST long <- int N017 ( 1, 1) [001076] -c---------- t1076 = CNS_INT long 3 $24b /--* t1066 long +--* t1076 long N018 ( 7, 7) [001077] ------------ t1077 = * MUL long /--* t1059 ref +--* t1077 long N029 ( 32, 35) [001058] -c---------- t1058 = * LEA(b+(i*8)+36) byref /--* t1058 byref N030 ( 34, 37) [000197] *--XGO------ t197 = * IND int /--* t197 int N031 ( 35, 38) [001079] ---XGO------ t1079 = * NEG int N032 ( 1, 1) [000191] -c---------- t191 = CNS_INT int -3 $e1 /--* t1079 int +--* t191 int N033 ( 37, 40) [000198] ---XGO------ t198 = * ADD int /--* t1056 byref +--* t198 int [001395] -A-XGO------ * STOREIND int [001396] ------------ IL_OFFSET void IL offset: 0x233 N001 ( 1, 1) [000202] -c---------- t202 = LCL_VAR ref V00 this u:1 $100 /--* t202 ref N003 ( 2, 2) [001083] -c---------- t1083 = * LEA(b+64) byref /--* t1083 byref N004 ( 4, 4) [000203] nc--GO------ t203 = * IND int N005 ( 1, 1) [000204] -c---------- t204 = CNS_INT int -1 $c4 /--* t203 int +--* t204 int N006 ( 6, 6) [000205] -c--GO------ t205 = * ADD int N007 ( 1, 1) [000201] ------------ t201 = LCL_VAR ref V00 this u:1 $100 /--* t201 ref N009 ( 2, 2) [001081] -c---------- t1081 = * LEA(b+64) byref /--* t1081 byref +--* t205 int [001397] -A--GO------ * STOREIND int ------------ BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} [001398] ------------ IL_OFFSET void IL offset: 0x243 N001 ( 1, 1) [000072] ------------ t72 = LCL_VAR ref V00 this u:1 $100 /--* t72 ref N003 ( 2, 2) [001085] -c---------- t1085 = * LEA(b+56) byref /--* t1085 byref N004 ( 4, 4) [000073] n---GO------ t73 = * IND int /--* t73 int N006 ( 8, 7) [001311] DA--GO------ * STORE_LCL_VAR int V75 cse10 d:1 N007 ( 3, 2) [001312] ------------ t1312 = LCL_VAR int V75 cse10 u:1 /--* t1312 int N010 ( 15, 12) [000075] DA--GO------ * STORE_LCL_VAR int V13 loc9 d:1 [001399] ------------ IL_OFFSET void IL offset: 0x24b N001 ( 1, 1) [001331] ------------ t1331 = LCL_VAR int V76 cse11 N002 ( 3, 2) [000076] ------------ t76 = LCL_VAR int V13 loc9 u:1 /--* t1331 int +--* t76 int N003 ( 5, 4) [000079] N------N-U-- * NE void N004 ( 7, 6) [000080] ------------ * JTRUE void ------------ BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} [001400] ------------ IL_OFFSET void IL offset: 0x252 N003 ( 3, 2) [001314] ------------ t1314 = LCL_VAR int V75 cse10 u:1 /--* t1314 int [001487] ------------ t1487 = * PUTARG_REG int REG rcx /--* t1487 int arg0 in rcx N004 ( 17, 8) [000702] --CXG------- t702 = * CALL int System.Collections.HashHelpers.ExpandPrime $1d7 /--* t702 int N006 ( 21, 11) [001090] DA-XG-----L- * STORE_LCL_VAR int V64 tmp50 d:1 N008 ( 3, 2) [001091] ------------ t1091 = LCL_VAR int V64 tmp50 u:1 (last use) $1d7 /--* t1091 int [001488] ------------ t1488 = * PUTARG_REG int REG rdx N009 ( 1, 1) [000163] ------------ t163 = LCL_VAR ref V00 this u:1 $100 /--* t163 ref [001489] ------------ t1489 = * PUTARG_REG ref REG rcx N010 ( 1, 1) [000704] ------------ t704 = CNS_INT int 0 $c0 /--* t704 int [001490] ------------ t1490 = * PUTARG_REG int REG r8 /--* t1488 int arg1 in rdx +--* t1489 ref this in rcx +--* t1490 int arg2 in r8 N011 ( 43, 24) [000705] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void [001401] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [000165] ------------ t165 = LCL_VAR ref V00 this u:1 $100 /--* t165 ref N003 ( 2, 2) [001095] -c---------- t1095 = * LEA(b+8) byref /--* t1095 byref N004 ( 4, 4) [000709] n---GO------ t709 = * IND ref /--* t709 ref N006 ( 8, 7) [000711] DA--GO------ * STORE_LCL_VAR ref V52 tmp38 d:1 [001402] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000713] ------------ t713 = LCL_VAR ref V52 tmp38 u:1 /--* t713 ref [001450] -c---------- t1450 = * LEA(b+8) ref /--* t1450 ref N002 ( 5, 4) [000714] ---X-------- t714 = * IND int /--* t714 int N004 ( 9, 7) [001286] DA-X-------- * STORE_LCL_VAR int V72 cse7 d:1 N005 ( 3, 2) [001287] ------------ t1287 = LCL_VAR int V72 cse7 u:1 /--* t1287 int N008 ( 12, 9) [000760] DA-X-------- * STORE_LCL_VAR int V53 tmp39 d:1 [001403] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [000715] ------------ t715 = LCL_VAR ref V00 this u:1 $100 /--* t715 ref N003 ( 2, 2) [001097] -c---------- t1097 = * LEA(b+48) byref /--* t1097 byref N004 ( 4, 4) [000716] n---GO------ t716 = * IND long /--* t716 long N006 ( 8, 7) [000762] DA--GO------ * STORE_LCL_VAR long V54 tmp40 d:1 [001404] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [000728] ------------ t728 = LCL_VAR int V53 tmp39 u:1 N002 ( 1, 4) [000729] -c---------- t729 = CNS_INT int 0x7FFFFFFF $ce /--* t728 int +--* t729 int N003 ( 6, 6) [000730] N--------U-- t730 = * LE int /--* t730 int N005 ( 10, 9) [000773] DA---------- * STORE_LCL_VAR int V56 tmp42 d:1 [001405] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [001301] ------------ t1301 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1301 ref N003 ( 5, 4) [000783] DA--G------- * STORE_LCL_VAR ref V57 tmp43 d:1 [001406] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [001302] ------------ t1302 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1302 ref N003 ( 5, 4) [000785] DA--G------- * STORE_LCL_VAR ref V58 tmp44 d:1 [001407] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000775] ------------ t775 = LCL_VAR int V56 tmp42 u:1 (last use) N002 ( 1, 1) [000776] -c---------- t776 = CNS_INT int 0 $c0 /--* t775 int +--* t776 int N003 ( 5, 4) [000777] J------N---- * NE void N004 ( 7, 6) [000778] ------------ * JTRUE void ------------ BB50 [258..259), preds={BB49} succs={BB51} [001408] ------------ IL_OFFSET void IL offset: 0x258 N003 ( 3, 2) [000779] ------------ t779 = LCL_VAR ref V58 tmp44 u:1 (last use) $105 /--* t779 ref [001491] ------------ t1491 = * PUTARG_REG ref REG rcx N004 ( 3, 2) [000780] ------------ t780 = LCL_VAR ref V58 tmp44 u:1 (last use) $105 /--* t780 ref [001492] ------------ t1492 = * PUTARG_REG ref REG rdx /--* t1491 ref arg0 in rcx +--* t1492 ref arg1 in rdx N005 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} [001409] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000735] ------------ t735 = LCL_VAR long V54 tmp40 u:1 (last use) N002 ( 1, 1) [000166] ------------ t166 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t166 int N003 ( 2, 3) [000736] ---------U-- t736 = * CAST long <- ulong <- uint $310 /--* t735 long +--* t736 long N004 ( 9, 8) [000737] ------------ t737 = * MUL long N005 ( 1, 1) [000738] -c---------- t738 = CNS_INT int 32 $d2 /--* t737 long +--* t738 int N006 ( 11, 10) [000739] ------------ t739 = * RSZ long N007 ( 1, 1) [000741] -c---------- t741 = CNS_INT long 1 $247 /--* t739 long +--* t741 long N008 ( 13, 12) [000742] ------------ t742 = * ADD long N009 ( 1, 1) [000743] ------------ t743 = LCL_VAR int V53 tmp39 u:1 /--* t743 int N010 ( 2, 3) [000744] ---------U-- t744 = * CAST long <- ulong <- uint /--* t742 long +--* t744 long N011 ( 19, 18) [000745] ------------ t745 = * MUL long N012 ( 1, 1) [000746] -c---------- t746 = CNS_INT int 32 $d2 /--* t745 long +--* t746 int N013 ( 21, 20) [000747] ------------ t747 = * RSZ long /--* t747 long N014 ( 22, 22) [000748] ------------ t748 = * CAST int <- uint <- long /--* t748 int N016 ( 26, 25) [000750] DA---------- * STORE_LCL_VAR int V55 tmp41 d:1 [001410] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [000752] ------------ t752 = LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000753] ------------ t753 = LCL_VAR int V53 tmp39 u:1 (last use) /--* t752 int +--* t753 int N003 ( 22, 5) [000754] ---X-------- t754 = * UMOD int N004 ( 3, 2) [000751] ------------ t751 = LCL_VAR int V55 tmp41 u:1 /--* t754 int +--* t751 int N005 ( 29, 8) [000755] ---X-------- t755 = * EQ int /--* t755 int N007 ( 33, 11) [000796] DA-X-------- * STORE_LCL_VAR int V59 tmp45 d:1 [001411] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [001303] ------------ t1303 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1303 ref N003 ( 5, 4) [000806] DA--G------- * STORE_LCL_VAR ref V60 tmp46 d:1 [001412] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [001304] ------------ t1304 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1304 ref N003 ( 5, 4) [000808] DA--G------- * STORE_LCL_VAR ref V61 tmp47 d:1 [001413] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000798] ------------ t798 = LCL_VAR int V59 tmp45 u:1 (last use) N002 ( 1, 1) [000799] -c---------- t799 = CNS_INT int 0 $c0 /--* t798 int +--* t799 int N003 ( 5, 4) [000800] J------N---- * NE void N004 ( 7, 6) [000801] ------------ * JTRUE void ------------ BB52 [258..259), preds={BB51} succs={BB53} [001414] ------------ IL_OFFSET void IL offset: 0x258 N003 ( 3, 2) [000802] ------------ t802 = LCL_VAR ref V61 tmp47 u:1 (last use) $105 /--* t802 ref [001493] ------------ t1493 = * PUTARG_REG ref REG rcx N004 ( 3, 2) [000803] ------------ t803 = LCL_VAR ref V61 tmp47 u:1 (last use) $105 /--* t803 ref [001494] ------------ t1494 = * PUTARG_REG ref REG rdx /--* t1493 ref arg0 in rcx +--* t1494 ref arg1 in rdx N005 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB53 [258..259), preds={BB51,BB52} succs={BB54} [001415] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000758] ------------ t758 = LCL_VAR int V55 tmp41 u:1 N002 ( 3, 2) [001289] ------------ t1289 = LCL_VAR int V72 cse7 u:1 /--* t758 int +--* t1289 int N003 ( 10, 11) [001105] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void N004 ( 3, 2) [001102] ------------ t1102 = LCL_VAR ref V52 tmp38 u:1 (last use) N005 ( 3, 2) [001103] ------------ t1103 = LCL_VAR int V55 tmp41 u:1 (last use) /--* t1103 int N006 ( 4, 4) [001106] ------------ t1106 = * CAST long <- int /--* t1102 ref +--* t1106 long N011 ( 9, 8) [001111] -------N---- t1111 = * LEA(b+(i*4)+16) byref /--* t1111 byref N016 ( 33, 31) [000722] DA-XG------- * STORE_LCL_VAR byref V51 tmp37 d:1 N001 ( 3, 2) [000723] ------------ t723 = LCL_VAR byref V51 tmp37 u:1 (last use) $87 /--* t723 byref N003 ( 7, 5) [000170] DA---------- * STORE_LCL_VAR byref V08 loc4 d:4 ------------ BB54 [261..276), preds={BB48,BB53} succs={BB55} N001 ( 0, 0) [001224] ------------ t1224 = PHI_ARG byref V08 loc4 u:4 $87 N002 ( 0, 0) [001220] ------------ t1220 = PHI_ARG byref V08 loc4 u:1 $81 /--* t1224 byref +--* t1220 byref N003 ( 0, 0) [001192] ------------ t1192 = * PHI byref /--* t1192 byref N005 ( 0, 0) [001193] DA---------- * STORE_LCL_VAR byref V08 loc4 d:3 [001416] ------------ IL_OFFSET void IL offset: 0x261 N001 ( 3, 2) [000081] ------------ t81 = LCL_VAR int V13 loc9 u:1 /--* t81 int N003 ( 7, 5) [000083] DA---------- * STORE_LCL_VAR int V10 loc6 d:2 [001417] ------------ IL_OFFSET void IL offset: 0x265 N001 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V10 loc6 u:2 (last use) N002 ( 1, 1) [000086] -c---------- t86 = CNS_INT int 1 $c1 /--* t85 int +--* t86 int N003 ( 5, 4) [000087] ------------ t87 = * ADD int N004 ( 1, 1) [000084] ------------ t84 = LCL_VAR ref V00 this u:1 $100 /--* t84 ref N006 ( 2, 2) [001115] -c---------- t1115 = * LEA(b+56) byref /--* t1115 byref +--* t87 int [001418] -A--GO------ * STOREIND int [001419] ------------ IL_OFFSET void IL offset: 0x26f N001 ( 1, 1) [000090] ------------ t90 = LCL_VAR ref V00 this u:1 $100 /--* t90 ref N003 ( 2, 2) [001117] -c---------- t1117 = * LEA(b+16) byref /--* t1117 byref N004 ( 4, 4) [000091] n---GO------ t91 = * IND ref /--* t91 ref N006 ( 4, 4) [000093] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:3 ------------ BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} N001 ( 0, 0) [001225] ------------ t1225 = PHI_ARG byref V08 loc4 u:1 $81 N002 ( 0, 0) [001221] ------------ t1221 = PHI_ARG byref V08 loc4 u:3 $780 /--* t1225 byref +--* t1221 byref N003 ( 0, 0) [001195] ------------ t1195 = * PHI byref /--* t1195 byref N005 ( 0, 0) [001196] DA---------- * STORE_LCL_VAR byref V08 loc4 d:2 N001 ( 0, 0) [001226] ------------ t1226 = PHI_ARG ref V04 loc0 u:1 N002 ( 0, 0) [001222] ------------ t1222 = PHI_ARG ref V04 loc0 u:3 /--* t1226 ref +--* t1222 ref N003 ( 0, 0) [001189] ------------ t1189 = * PHI ref /--* t1189 ref N005 ( 0, 0) [001190] DA---------- * STORE_LCL_VAR ref V04 loc0 d:2 N001 ( 0, 0) [001227] ------------ t1227 = PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [001223] ------------ t1223 = PHI_ARG int V10 loc6 u:2 /--* t1227 int +--* t1223 int N003 ( 0, 0) [001186] ------------ t1186 = * PHI int /--* t1186 int N005 ( 0, 0) [001187] DA---------- * STORE_LCL_VAR int V10 loc6 d:1 [001420] ------------ IL_OFFSET void IL offset: 0x276 N001 ( 3, 2) [000095] ------------ t95 = LCL_VAR int V10 loc6 u:1 $3cc N002 ( 1, 1) [000094] ------------ t94 = LCL_VAR ref V04 loc0 u:2 $684 /--* t94 ref [001452] -c---------- t1452 = * LEA(b+8) ref /--* t1452 ref N003 ( 3, 3) [001120] -c-X-------- t1120 = * IND int $73d /--* t95 int +--* t1120 int N004 ( 10, 12) [001121] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void $7cd N005 ( 1, 1) [001118] ------------ t1118 = LCL_VAR ref V04 loc0 u:2 $684 N006 ( 3, 2) [001119] ------------ t1119 = LCL_VAR int V10 loc6 u:1 $3cc /--* t1119 int N007 ( 4, 4) [001122] ------------ t1122 = * CAST long <- int $6dc N008 ( 1, 1) [001129] -c---------- t1129 = CNS_INT long 3 $24b /--* t1122 long +--* t1129 long N009 ( 9, 8) [001130] ------------ t1130 = * MUL long $6dd /--* t1118 ref +--* t1130 long N014 ( 12, 11) [001127] -------N---- t1127 = * LEA(b+(i*8)+16) byref /--* t1127 byref N019 ( 39, 38) [000099] DA-XG------- * STORE_LCL_VAR byref V11 loc7 d:1 [001421] ------------ IL_OFFSET void IL offset: 0x280 N001 ( 3, 2) [000100] ------------ t100 = LCL_VAR byref V11 loc7 u:1 $8c /--* t100 byref N003 ( 4, 3) [001133] -c---------- t1133 = * LEA(b+16) byref N005 ( 1, 1) [000101] ------------ t101 = LCL_VAR int V06 loc2 u:1 (last use) $3c0 /--* t1133 byref +--* t101 int [001422] -A-XG------- * STOREIND int [001423] ------------ IL_OFFSET void IL offset: 0x288 N001 ( 3, 2) [000105] ------------ t105 = LCL_VAR byref V08 loc4 u:2 $781 /--* t105 byref N002 ( 6, 4) [000106] *--XG------- t106 = * IND int N003 ( 1, 1) [000107] -c---------- t107 = CNS_INT int -1 $c4 /--* t106 int +--* t107 int N004 ( 8, 6) [000108] ---XG------- t108 = * ADD int N005 ( 3, 2) [000104] ------------ t104 = LCL_VAR byref V11 loc7 u:1 $8c /--* t104 byref N007 ( 4, 3) [001135] -c---------- t1135 = * LEA(b+20) byref /--* t1135 byref +--* t108 int [001424] -A-XGO------ * STOREIND int [001425] ------------ IL_OFFSET void IL offset: 0x294 N001 ( 3, 2) [000111] ------------ t111 = LCL_VAR byref V11 loc7 u:1 Zero Fseq[key] $8f N003 ( 1, 1) [000112] ------------ t112 = LCL_VAR ref V01 arg1 u:1 (last use) $101 /--* t111 byref +--* t112 ref [001426] -A-XG------- * STOREIND ref [001427] ------------ IL_OFFSET void IL offset: 0x29c N001 ( 3, 2) [000115] ------------ t115 = LCL_VAR byref V11 loc7 u:1 (last use) $8c /--* t115 byref N003 ( 4, 3) [001137] ------------ t1137 = * LEA(b+8) byref N005 ( 1, 1) [000116] ------------ t116 = LCL_VAR ref V02 arg2 u:1 (last use) $102 /--* t1137 byref +--* t116 ref [001428] -A--GO------ * STOREIND ref [001429] ------------ IL_OFFSET void IL offset: 0x2a4 N001 ( 3, 2) [000120] ------------ t120 = LCL_VAR int V10 loc6 u:1 (last use) $3cc N002 ( 1, 1) [000121] -c---------- t121 = CNS_INT int 1 $c1 /--* t120 int +--* t121 int N003 ( 5, 4) [000122] ------------ t122 = * ADD int $804 N004 ( 3, 2) [000119] ------------ t119 = LCL_VAR byref V08 loc4 u:2 (last use) $781 /--* t119 byref +--* t122 int [001430] -A--GO------ * STOREIND int [001431] ------------ IL_OFFSET void IL offset: 0x2ab N001 ( 1, 1) [000126] -c---------- t126 = LCL_VAR ref V00 this u:1 $100 /--* t126 ref N003 ( 2, 2) [001141] -c---------- t1141 = * LEA(b+68) byref /--* t1141 byref N004 ( 4, 4) [000127] nc--GO------ t127 = * IND int N005 ( 1, 1) [000128] -c---------- t128 = CNS_INT int 1 $c1 /--* t127 int +--* t128 int N006 ( 6, 6) [000129] -c--GO------ t129 = * ADD int N007 ( 1, 1) [000125] ------------ t125 = LCL_VAR ref V00 this u:1 $100 /--* t125 ref N009 ( 2, 2) [001139] -c---------- t1139 = * LEA(b+68) byref /--* t1139 byref +--* t129 int [001432] -A--GO------ * STOREIND int [001433] ------------ IL_OFFSET void IL offset: 0x2ca N001 ( 1, 1) [000145] ------------ t145 = LCL_VAR int V07 loc3 u:2 (last use) $3c5 N002 ( 1, 1) [000146] -c---------- t146 = CNS_INT int 100 $e3 /--* t145 int +--* t146 int N003 ( 3, 3) [000147] N------N-U-- * LE void $80d N004 ( 5, 5) [000148] ------------ * JTRUE void ------------ BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} [001434] ------------ IL_OFFSET void IL offset: 0x2cf N003 ( 1, 1) [000151] ------------ t151 = LCL_VAR ref V05 loc1 u:1 (last use) /--* t151 ref [001495] ------------ t1495 = * PUTARG_REG ref REG rdx N004 ( 2, 10) [000152] H------N---- t152 = CNS_INT(h) long 0xd1ffab1e class $62 /--* t152 long [001496] ------------ t1496 = * PUTARG_REG long REG rcx /--* t1495 ref arg1 in rdx +--* t1496 long arg0 in rcx N005 ( 17, 18) [000153] --C-G------- t153 = * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS N006 ( 1, 1) [000154] -c---------- t154 = CNS_INT ref null $VN.Null /--* t153 ref +--* t154 ref N007 ( 19, 20) [000155] J---G--N---- * EQ void N008 ( 21, 22) [000156] ----G------- * JTRUE void ------------ BB57 [2D7..2E3), preds={BB56} succs={BB58} [001435] ------------ IL_OFFSET void IL offset: 0x2d7 N004 ( 1, 1) [000158] ------------ t158 = LCL_VAR ref V04 loc0 u:2 (last use) $684 /--* t158 ref [001454] -c---------- t1454 = * LEA(b+8) ref /--* t1454 ref N005 ( 3, 3) [000159] ---X-------- t159 = * IND int $73d /--* t159 int [001497] ---X-------- t1497 = * PUTARG_REG int REG rdx N006 ( 1, 1) [000157] ------------ t157 = LCL_VAR ref V00 this u:1 $100 /--* t157 ref [001498] ------------ t1498 = * PUTARG_REG ref REG rcx N007 ( 1, 1) [000160] ------------ t160 = CNS_INT int 1 $c1 /--* t160 int [001499] ------------ t1499 = * PUTARG_REG int REG r8 /--* t1497 int arg1 in rdx +--* t1498 ref this in rcx +--* t1499 int arg2 in r8 N008 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void ------------ BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} N001 ( 1, 1) [000482] ------------ t482 = CNS_INT int 1 $c1 /--* t482 int N002 ( 2, 2) [000810] ------------ * RETURN int $1f4 ------------ BB59 [008..00E) (throw), preds={BB01} succs={} [001436] ------------ IL_OFFSET void IL offset: 0x8 N002 ( 1, 1) [000532] ------------ t532 = CNS_INT int 4 $c5 /--* t532 int [001500] ------------ t1500 = * PUTARG_REG int REG rcx /--* t1500 int arg0 in rcx N003 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException $VN.Void ------------ BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} [001437] ------------ IL_OFFSET void IL offset: 0x14f N001 ( 1, 1) [000441] !----------- t441 = LCL_VAR ref V00 this u:1 $100 /--* t441 ref N002 ( 3, 2) [000442] #----O------ t442 = * IND long $2e8 /--* t442 long N004 ( 7, 5) [000444] DA---O------ * STORE_LCL_VAR long V26 tmp12 d:1 N001 ( 3, 2) [000446] ------------ t446 = LCL_VAR long V26 tmp12 u:1 $2e7 /--* t446 long N003 ( 4, 3) [000448] -c---------- t448 = * LEA(b+56) long /--* t448 long N004 ( 6, 5) [000449] #----------- t449 = * IND long $2e9 /--* t449 long N005 ( 9, 7) [000450] #----------- t450 = * IND long $2ea /--* t450 long N007 ( 10, 8) [000452] -c---------- t452 = * LEA(b+56) long /--* t452 long N008 ( 12, 10) [000456] nc---------- t456 = * IND long N009 ( 1, 1) [000459] -c---------- t459 = CNS_INT long 0 $243 /--* t456 long +--* t459 long N010 ( 14, 12) [000460] J------N---- * EQ void N011 ( 16, 14) [001158] ------------ * JTRUE void ------------ BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} N001 ( 3, 2) [000466] ------?----- t466 = LCL_VAR long V26 tmp12 u:1 (last use) $2e7 /--* t466 long N003 ( 4, 3) [000465] -c----?----- t465 = * LEA(b+56) long /--* t465 long N004 ( 6, 5) [000464] #-----?----- t464 = * IND long $2e9 /--* t464 long N005 ( 9, 7) [000463] #-----?----- t463 = * IND long $2ea /--* t463 long N007 ( 10, 8) [000462] -c----?----- t462 = * LEA(b+56) long /--* t462 long N008 ( 12, 10) [000461] n-----?----- t461 = * IND long /--* t461 long N010 ( 16, 13) [001160] DA---------- * STORE_LCL_VAR long V28 tmp14 d:3 ------------ BB62 [???..???), preds={BB60} succs={BB63} N003 ( 3, 2) [000445] ------?----- t445 = LCL_VAR long V26 tmp12 u:1 (last use) $2e7 /--* t445 long [001501] ------------ t1501 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000457] H-----?----- t457 = CNS_INT(h) long 0xd1ffab1e global ptr $52 /--* t457 long [001502] ------------ t1502 = * PUTARG_REG long REG rdx /--* t1501 long arg0 in rcx +--* t1502 long arg1 in rdx N005 ( 19, 19) [000458] --C-G-?----- t458 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 /--* t458 long N007 ( 23, 22) [001162] DA--G------- * STORE_LCL_VAR long V28 tmp14 d:2 ------------ BB63 [???..157) (throw), preds={BB61,BB62} succs={} N001 ( 0, 0) [001241] ------------ t1241 = PHI_ARG long V28 tmp14 u:3 N002 ( 0, 0) [001240] ------------ t1240 = PHI_ARG long V28 tmp14 u:2 $332 /--* t1241 long +--* t1240 long N003 ( 0, 0) [001183] ------------ t1183 = * PHI long /--* t1183 long N005 ( 0, 0) [001184] DA---------- * STORE_LCL_VAR long V28 tmp14 d:1 N003 ( 3, 2) [000473] ------------ t473 = LCL_VAR long V28 tmp14 u:1 (last use) $347 /--* t473 long [001503] ------------ t1503 = * PUTARG_REG long REG rcx N004 ( 1, 1) [000455] ------------ t455 = LCL_VAR ref V01 arg1 u:1 (last use) $101 /--* t455 ref [001504] ------------ t1504 = * PUTARG_REG ref REG rdx /--* t1503 long arg0 in rcx +--* t1504 ref arg1 in rdx N005 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void ------------ BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} [001438] ------------ IL_OFFSET void IL offset: 0x1bc N001 ( 1, 1) [000296] !----------- t296 = LCL_VAR ref V00 this u:1 $100 /--* t296 ref N002 ( 3, 2) [000297] #----O------ t297 = * IND long $2e8 /--* t297 long N004 ( 7, 5) [000299] DA---O------ * STORE_LCL_VAR long V21 tmp7 d:1 N001 ( 3, 2) [000301] ------------ t301 = LCL_VAR long V21 tmp7 u:1 $2e7 /--* t301 long N003 ( 4, 3) [000303] -c---------- t303 = * LEA(b+56) long /--* t303 long N004 ( 6, 5) [000304] #----------- t304 = * IND long $2e9 /--* t304 long N005 ( 9, 7) [000305] #----------- t305 = * IND long $2ea /--* t305 long N007 ( 10, 8) [000307] -c---------- t307 = * LEA(b+56) long /--* t307 long N008 ( 12, 10) [000311] nc---------- t311 = * IND long N009 ( 1, 1) [000314] -c---------- t314 = CNS_INT long 0 $243 /--* t311 long +--* t314 long N010 ( 14, 12) [000315] J------N---- * EQ void N011 ( 16, 14) [001168] ------------ * JTRUE void ------------ BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} N001 ( 3, 2) [000321] ------?----- t321 = LCL_VAR long V21 tmp7 u:1 (last use) $2e7 /--* t321 long N003 ( 4, 3) [000320] -c----?----- t320 = * LEA(b+56) long /--* t320 long N004 ( 6, 5) [000319] #-----?----- t319 = * IND long $2e9 /--* t319 long N005 ( 9, 7) [000318] #-----?----- t318 = * IND long $2ea /--* t318 long N007 ( 10, 8) [000317] -c----?----- t317 = * LEA(b+56) long /--* t317 long N008 ( 12, 10) [000316] n-----?----- t316 = * IND long /--* t316 long N010 ( 16, 13) [001170] DA---------- * STORE_LCL_VAR long V23 tmp9 d:3 ------------ BB66 [???..???), preds={BB64} succs={BB67} N003 ( 3, 2) [000300] ------?----- t300 = LCL_VAR long V21 tmp7 u:1 (last use) $2e7 /--* t300 long [001505] ------------ t1505 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000312] H-----?----- t312 = CNS_INT(h) long 0xd1ffab1e global ptr $52 /--* t312 long [001506] ------------ t1506 = * PUTARG_REG long REG rdx /--* t1505 long arg0 in rcx +--* t1506 long arg1 in rdx N005 ( 19, 19) [000313] --C-G-?----- t313 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 /--* t313 long N007 ( 23, 22) [001172] DA--G------- * STORE_LCL_VAR long V23 tmp9 d:2 ------------ BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} N001 ( 0, 0) [001232] ------------ t1232 = PHI_ARG long V23 tmp9 u:3 N002 ( 0, 0) [001231] ------------ t1231 = PHI_ARG long V23 tmp9 u:2 $332 /--* t1232 long +--* t1231 long N003 ( 0, 0) [001201] ------------ t1201 = * PHI long /--* t1201 long N005 ( 0, 0) [001202] DA---------- * STORE_LCL_VAR long V23 tmp9 d:1 N003 ( 3, 2) [000328] ------------ t328 = LCL_VAR long V23 tmp9 u:1 (last use) $34b /--* t328 long [001507] ------------ t1507 = * PUTARG_REG long REG rcx N004 ( 1, 1) [000310] ------------ t310 = LCL_VAR ref V01 arg1 u:1 (last use) $101 /--* t310 ref [001508] ------------ t1508 = * PUTARG_REG ref REG rdx /--* t1507 long arg0 in rcx +--* t1508 ref arg1 in rdx N005 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void ------------ BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} [001439] ------------ IL_OFFSET void IL offset: 0x1dd N001 ( 14, 5) [000233] --CXG------- CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported $VN.Void ------------ BB69 [???..???) (throw), preds={} succs={} N001 ( 14, 5) [001444] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL ------------------------------------------------------------------------------------------------------------------- *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V01: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 2, refCntWtd = 1.50 New refCnts for V00: refCnt = 3, refCntWtd = 2.50 New refCnts for V33: refCnt = 1, refCntWtd = 2 New refCnts for V73: refCnt = 1, refCntWtd = 1 New refCnts for V73: refCnt = 2, refCntWtd = 2 New refCnts for V34: refCnt = 1, refCntWtd = 2 New refCnts for V73: refCnt = 3, refCntWtd = 3 New refCnts for V35: refCnt = 1, refCntWtd = 2 New refCnts for V33: refCnt = 2, refCntWtd = 4 New refCnts for V35: refCnt = 2, refCntWtd = 3 New refCnts for V35: refCnt = 3, refCntWtd = 4 New refCnts for V00: refCnt = 4, refCntWtd = 3.50 New refCnts for V04: refCnt = 1, refCntWtd = 1 New refCnts for V04: refCnt = 2, refCntWtd = 2 New refCnts for V36: refCnt = 1, refCntWtd = 2 New refCnts for V73: refCnt = 4, refCntWtd = 4 New refCnts for V37: refCnt = 1, refCntWtd = 2 New refCnts for V36: refCnt = 2, refCntWtd = 4 New refCnts for V37: refCnt = 2, refCntWtd = 3 New refCnts for V00: refCnt = 5, refCntWtd = 4.50 New refCnts for V05: refCnt = 1, refCntWtd = 1 New refCnts for V05: refCnt = 2, refCntWtd = 2 New refCnts for V00: refCnt = 6, refCntWtd = 5 New refCnts for V29: refCnt = 1, refCntWtd = 1 New refCnts for V29: refCnt = 2, refCntWtd = 2 New refCnts for V68: refCnt = 1, refCntWtd = 0.50 New refCnts for V68: refCnt = 2, refCntWtd = 1 New refCnts for V68: refCnt = 3, refCntWtd = 1.25 New refCnts for V31: refCnt = 1, refCntWtd = 0.50 New refCnts for V29: refCnt = 3, refCntWtd = 2.50 New refCnts for V31: refCnt = 2, refCntWtd = 1 New refCnts for V05: refCnt = 3, refCntWtd = 2.50 New refCnts for V31: refCnt = 3, refCntWtd = 2 New refCnts for V01: refCnt = 2, refCntWtd = 1.50 New refCnts for V31: refCnt = 4, refCntWtd = 3 New refCnts for V15: refCnt = 1, refCntWtd = 0.50 New refCnts for V01: refCnt = 3, refCntWtd = 2 New refCnts for V01: refCnt = 4, refCntWtd = 2.50 New refCnts for V15: refCnt = 2, refCntWtd = 1 New refCnts for V15: refCnt = 3, refCntWtd = 2 New refCnts for V06: refCnt = 1, refCntWtd = 1 New refCnts for V07: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 7, refCntWtd = 6 New refCnts for V39: refCnt = 1, refCntWtd = 1 New refCnts for V39: refCnt = 2, refCntWtd = 2 New refCnts for V40: refCnt = 1, refCntWtd = 2 New refCnts for V00: refCnt = 8, refCntWtd = 7 New refCnts for V41: refCnt = 1, refCntWtd = 2 New refCnts for V40: refCnt = 2, refCntWtd = 4 New refCnts for V43: refCnt = 1, refCntWtd = 2 New refCnts for V73: refCnt = 5, refCntWtd = 5 New refCnts for V44: refCnt = 1, refCntWtd = 2 New refCnts for V73: refCnt = 6, refCntWtd = 6 New refCnts for V45: refCnt = 1, refCntWtd = 2 New refCnts for V43: refCnt = 2, refCntWtd = 4 New refCnts for V45: refCnt = 2, refCntWtd = 3 New refCnts for V45: refCnt = 3, refCntWtd = 4 New refCnts for V41: refCnt = 2, refCntWtd = 4 New refCnts for V06: refCnt = 2, refCntWtd = 2 New refCnts for V40: refCnt = 3, refCntWtd = 6 New refCnts for V42: refCnt = 1, refCntWtd = 1 New refCnts for V06: refCnt = 3, refCntWtd = 3 New refCnts for V40: refCnt = 4, refCntWtd = 8 New refCnts for V42: refCnt = 2, refCntWtd = 2 New refCnts for V46: refCnt = 1, refCntWtd = 2 New refCnts for V73: refCnt = 7, refCntWtd = 7 New refCnts for V47: refCnt = 1, refCntWtd = 2 New refCnts for V73: refCnt = 8, refCntWtd = 8 New refCnts for V48: refCnt = 1, refCntWtd = 2 New refCnts for V46: refCnt = 2, refCntWtd = 4 New refCnts for V48: refCnt = 2, refCntWtd = 3 New refCnts for V48: refCnt = 3, refCntWtd = 4 New refCnts for V42: refCnt = 3, refCntWtd = 3 New refCnts for V39: refCnt = 3, refCntWtd = 3 New refCnts for V39: refCnt = 4, refCntWtd = 4 New refCnts for V42: refCnt = 4, refCntWtd = 4 New refCnts for V38: refCnt = 1, refCntWtd = 1 New refCnts for V38: refCnt = 2, refCntWtd = 2 New refCnts for V08: refCnt = 1, refCntWtd = 1 New refCnts for V08: refCnt = 2, refCntWtd = 2 New refCnts for V09: refCnt = 1, refCntWtd = 1 New refCnts for V05: refCnt = 4, refCntWtd = 3.50 New refCnts for V00: refCnt = 9, refCntWtd = 7.50 New refCnts for V24: refCnt = 1, refCntWtd = 1 New refCnts for V24: refCnt = 2, refCntWtd = 2 New refCnts for V69: refCnt = 1, refCntWtd = 0.50 New refCnts for V69: refCnt = 2, refCntWtd = 1 New refCnts for V69: refCnt = 3, refCntWtd = 1.25 New refCnts for V25: refCnt = 1, refCntWtd = 0.50 New refCnts for V24: refCnt = 3, refCntWtd = 2.50 New refCnts for V25: refCnt = 2, refCntWtd = 1 New refCnts for V25: refCnt = 3, refCntWtd = 2 New refCnts for V12: refCnt = 1, refCntWtd = 0.50 New refCnts for V04: refCnt = 3, refCntWtd = 6 New refCnts for V76: refCnt = 1, refCntWtd = 4 New refCnts for V76: refCnt = 2, refCntWtd = 8 New refCnts for V09: refCnt = 2, refCntWtd = 5 New refCnts for V04: refCnt = 4, refCntWtd = 10 New refCnts for V09: refCnt = 3, refCntWtd = 9 New refCnts for V70: refCnt = 1, refCntWtd = 4 New refCnts for V70: refCnt = 2, refCntWtd = 8 New refCnts for V65: refCnt = 1, refCntWtd = 4 New refCnts for V65: refCnt = 2, refCntWtd = 8 New refCnts for V06: refCnt = 4, refCntWtd = 7 New refCnts for V04: refCnt = 5, refCntWtd = 12 New refCnts for V70: refCnt = 3, refCntWtd = 10 New refCnts for V12: refCnt = 2, refCntWtd = 2.50 New refCnts for V01: refCnt = 5, refCntWtd = 4.50 New refCnts for V12: refCnt = 3, refCntWtd = 4.50 New refCnts for V65: refCnt = 3, refCntWtd = 12 New refCnts for V09: refCnt = 4, refCntWtd = 13 New refCnts for V07: refCnt = 2, refCntWtd = 5 New refCnts for V07: refCnt = 3, refCntWtd = 9 New refCnts for V76: refCnt = 3, refCntWtd = 12 New refCnts for V07: refCnt = 4, refCntWtd = 13 New refCnts for V03: refCnt = 1, refCntWtd = 0.50 New refCnts for V65: refCnt = 4, refCntWtd = 12.50 New refCnts for V02: refCnt = 1, refCntWtd = 0.50 New refCnts for V03: refCnt = 2, refCntWtd = 1 New refCnts for V04: refCnt = 6, refCntWtd = 16 New refCnts for V76: refCnt = 4, refCntWtd = 16 New refCnts for V76: refCnt = 5, refCntWtd = 20 New refCnts for V09: refCnt = 5, refCntWtd = 17 New refCnts for V04: refCnt = 7, refCntWtd = 20 New refCnts for V09: refCnt = 6, refCntWtd = 21 New refCnts for V71: refCnt = 1, refCntWtd = 4 New refCnts for V71: refCnt = 2, refCntWtd = 8 New refCnts for V66: refCnt = 1, refCntWtd = 4 New refCnts for V66: refCnt = 2, refCntWtd = 8 New refCnts for V06: refCnt = 5, refCntWtd = 11 New refCnts for V04: refCnt = 8, refCntWtd = 22 New refCnts for V71: refCnt = 3, refCntWtd = 10 New refCnts for V17: refCnt = 1, refCntWtd = 4 New refCnts for V00: refCnt = 10, refCntWtd = 9.50 New refCnts for V16: refCnt = 1, refCntWtd = 4 New refCnts for V16: refCnt = 2, refCntWtd = 8 New refCnts for V67: refCnt = 1, refCntWtd = 2 New refCnts for V67: refCnt = 2, refCntWtd = 4 New refCnts for V67: refCnt = 3, refCntWtd = 5 New refCnts for V19: refCnt = 1, refCntWtd = 2 New refCnts for V16: refCnt = 3, refCntWtd = 10 New refCnts for V19: refCnt = 2, refCntWtd = 4 New refCnts for V05: refCnt = 5, refCntWtd = 5.50 New refCnts for V19: refCnt = 3, refCntWtd = 8 New refCnts for V17: refCnt = 2, refCntWtd = 8 New refCnts for V01: refCnt = 6, refCntWtd = 6.50 New refCnts for V19: refCnt = 4, refCntWtd = 12 New refCnts for V03: refCnt = 3, refCntWtd = 1.50 New refCnts for V66: refCnt = 3, refCntWtd = 8.50 New refCnts for V02: refCnt = 2, refCntWtd = 1 New refCnts for V03: refCnt = 4, refCntWtd = 2 New refCnts for V66: refCnt = 4, refCntWtd = 12.50 New refCnts for V09: refCnt = 7, refCntWtd = 25 New refCnts for V07: refCnt = 5, refCntWtd = 17 New refCnts for V07: refCnt = 6, refCntWtd = 21 New refCnts for V76: refCnt = 6, refCntWtd = 24 New refCnts for V07: refCnt = 7, refCntWtd = 25 New refCnts for V00: refCnt = 11, refCntWtd = 10 New refCnts for V00: refCnt = 12, refCntWtd = 10.50 New refCnts for V74: refCnt = 1, refCntWtd = 0.50 New refCnts for V74: refCnt = 2, refCntWtd = 1 New refCnts for V10: refCnt = 1, refCntWtd = 0.50 New refCnts for V74: refCnt = 3, refCntWtd = 1.50 New refCnts for V62: refCnt = 1, refCntWtd = 1 New refCnts for V62: refCnt = 2, refCntWtd = 2 New refCnts for V76: refCnt = 7, refCntWtd = 24.50 New refCnts for V04: refCnt = 9, refCntWtd = 22.50 New refCnts for V62: refCnt = 3, refCntWtd = 3 New refCnts for V49: refCnt = 1, refCntWtd = 1 New refCnts for V73: refCnt = 9, refCntWtd = 8.50 New refCnts for V50: refCnt = 1, refCntWtd = 1 New refCnts for V49: refCnt = 2, refCntWtd = 2 New refCnts for V50: refCnt = 2, refCntWtd = 2 New refCnts for V00: refCnt = 13, refCntWtd = 11 New refCnts for V00: refCnt = 14, refCntWtd = 11.50 New refCnts for V63: refCnt = 1, refCntWtd = 1 New refCnts for V63: refCnt = 2, refCntWtd = 2 New refCnts for V76: refCnt = 8, refCntWtd = 25 New refCnts for V04: refCnt = 10, refCntWtd = 23 New refCnts for V63: refCnt = 3, refCntWtd = 3 New refCnts for V00: refCnt = 15, refCntWtd = 12 New refCnts for V00: refCnt = 16, refCntWtd = 12.50 New refCnts for V00: refCnt = 17, refCntWtd = 13 New refCnts for V75: refCnt = 1, refCntWtd = 0.50 New refCnts for V75: refCnt = 2, refCntWtd = 1 New refCnts for V13: refCnt = 1, refCntWtd = 0.50 New refCnts for V76: refCnt = 9, refCntWtd = 25.50 New refCnts for V13: refCnt = 2, refCntWtd = 1 New refCnts for V75: refCnt = 3, refCntWtd = 1.50 New refCnts for V64: refCnt = 1, refCntWtd = 1 New refCnts for V64: refCnt = 2, refCntWtd = 2 New refCnts for V00: refCnt = 18, refCntWtd = 13.50 New refCnts for V00: refCnt = 19, refCntWtd = 14 New refCnts for V52: refCnt = 1, refCntWtd = 0.50 New refCnts for V52: refCnt = 2, refCntWtd = 1 New refCnts for V72: refCnt = 1, refCntWtd = 0.50 New refCnts for V72: refCnt = 2, refCntWtd = 1 New refCnts for V53: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 20, refCntWtd = 14.50 New refCnts for V54: refCnt = 1, refCntWtd = 1 New refCnts for V53: refCnt = 2, refCntWtd = 2 New refCnts for V56: refCnt = 1, refCntWtd = 1 New refCnts for V73: refCnt = 10, refCntWtd = 9 New refCnts for V57: refCnt = 1, refCntWtd = 1 New refCnts for V73: refCnt = 11, refCntWtd = 9.50 New refCnts for V58: refCnt = 1, refCntWtd = 1 New refCnts for V56: refCnt = 2, refCntWtd = 2 New refCnts for V58: refCnt = 2, refCntWtd = 2 New refCnts for V58: refCnt = 3, refCntWtd = 3 New refCnts for V54: refCnt = 2, refCntWtd = 2 New refCnts for V06: refCnt = 6, refCntWtd = 11.50 New refCnts for V53: refCnt = 3, refCntWtd = 3 New refCnts for V55: refCnt = 1, refCntWtd = 0.50 New refCnts for V06: refCnt = 7, refCntWtd = 12 New refCnts for V53: refCnt = 4, refCntWtd = 4 New refCnts for V55: refCnt = 2, refCntWtd = 1 New refCnts for V59: refCnt = 1, refCntWtd = 1 New refCnts for V73: refCnt = 12, refCntWtd = 10 New refCnts for V60: refCnt = 1, refCntWtd = 1 New refCnts for V73: refCnt = 13, refCntWtd = 10.50 New refCnts for V61: refCnt = 1, refCntWtd = 1 New refCnts for V59: refCnt = 2, refCntWtd = 2 New refCnts for V61: refCnt = 2, refCntWtd = 2 New refCnts for V61: refCnt = 3, refCntWtd = 3 New refCnts for V55: refCnt = 3, refCntWtd = 1.50 New refCnts for V72: refCnt = 3, refCntWtd = 1.50 New refCnts for V52: refCnt = 3, refCntWtd = 1.50 New refCnts for V55: refCnt = 4, refCntWtd = 2 New refCnts for V51: refCnt = 1, refCntWtd = 0.50 New refCnts for V51: refCnt = 2, refCntWtd = 1 New refCnts for V08: refCnt = 3, refCntWtd = 2.50 New refCnts for V13: refCnt = 3, refCntWtd = 1.50 New refCnts for V10: refCnt = 2, refCntWtd = 1 New refCnts for V10: refCnt = 3, refCntWtd = 1.50 New refCnts for V00: refCnt = 21, refCntWtd = 15 New refCnts for V00: refCnt = 22, refCntWtd = 15.50 New refCnts for V04: refCnt = 11, refCntWtd = 23.50 New refCnts for V10: refCnt = 4, refCntWtd = 2 New refCnts for V04: refCnt = 12, refCntWtd = 24 New refCnts for V04: refCnt = 13, refCntWtd = 24.50 New refCnts for V10: refCnt = 5, refCntWtd = 2.50 New refCnts for V11: refCnt = 1, refCntWtd = 0.50 New refCnts for V11: refCnt = 2, refCntWtd = 1 New refCnts for V06: refCnt = 8, refCntWtd = 12.50 New refCnts for V08: refCnt = 4, refCntWtd = 3 New refCnts for V11: refCnt = 3, refCntWtd = 1.50 New refCnts for V11: refCnt = 4, refCntWtd = 2 New refCnts for V01: refCnt = 7, refCntWtd = 7 New refCnts for V11: refCnt = 5, refCntWtd = 2.50 New refCnts for V02: refCnt = 3, refCntWtd = 1.50 New refCnts for V10: refCnt = 6, refCntWtd = 3 New refCnts for V08: refCnt = 5, refCntWtd = 3.50 New refCnts for V00: refCnt = 23, refCntWtd = 16 New refCnts for V00: refCnt = 24, refCntWtd = 16.50 New refCnts for V07: refCnt = 8, refCntWtd = 25.50 New refCnts for V05: refCnt = 6, refCntWtd = 6 New refCnts for V04: refCnt = 14, refCntWtd = 25 New refCnts for V00: refCnt = 25, refCntWtd = 17 New refCnts for V00: refCnt = 26, refCntWtd = 17 New refCnts for V26: refCnt = 1, refCntWtd = 0 New refCnts for V26: refCnt = 2, refCntWtd = 0 New refCnts for V26: refCnt = 3, refCntWtd = 0 New refCnts for V28: refCnt = 1, refCntWtd = 0 New refCnts for V26: refCnt = 4, refCntWtd = 0 New refCnts for V28: refCnt = 2, refCntWtd = 0 New refCnts for V28: refCnt = 3, refCntWtd = 0 New refCnts for V01: refCnt = 8, refCntWtd = 7 New refCnts for V00: refCnt = 27, refCntWtd = 17 New refCnts for V21: refCnt = 1, refCntWtd = 0 New refCnts for V21: refCnt = 2, refCntWtd = 0 New refCnts for V21: refCnt = 3, refCntWtd = 0 New refCnts for V23: refCnt = 1, refCntWtd = 0 New refCnts for V21: refCnt = 4, refCntWtd = 0 New refCnts for V23: refCnt = 2, refCntWtd = 0 New refCnts for V23: refCnt = 3, refCntWtd = 0 New refCnts for V01: refCnt = 9, refCntWtd = 7 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 28, refCntWtd = 18 New refCnts for V00: refCnt = 29, refCntWtd = 19 New refCnts for V01: refCnt = 10, refCntWtd = 8 New refCnts for V01: refCnt = 11, refCntWtd = 9 New refCnts for V02: refCnt = 4, refCntWtd = 2.50 New refCnts for V02: refCnt = 5, refCntWtd = 3.50 New refCnts for V03: refCnt = 5, refCntWtd = 3 New refCnts for V03: refCnt = 6, refCntWtd = 4 *************** In fgLocalVarLiveness() ; Initial local variable assignments ; ; V00 this ref this class-hnd ; V01 arg1 ref ld-addr-op class-hnd ; V02 arg2 ref class-hnd ; V03 arg3 ubyte ; V04 loc0 ref class-hnd ; V05 loc1 ref class-hnd ; V06 loc2 int ; V07 loc3 int ; V08 loc4 byref ; V09 loc5 int ; V10 loc6 int ; V11 loc7 byref ; V12 loc8 ref class-hnd ; V13 loc9 int ; V14 OutArgs lclBlk <32> "OutgoingArgSpace" ; V15 tmp1 int ; V16 tmp2 long "impRuntimeLookup slot" ; V17 tmp3 ref class-hnd "impAppendStmt" ; V18 tmp4 ref class-hnd "bubbling QMark1" ; V19 tmp5 long "spilling Runtime Lookup tree" ; V20 tmp6 long "VirtualCall with runtime lookup" ; V21 tmp7 long "impRuntimeLookup slot" ; V22 tmp8 ref class-hnd "bubbling QMark1" ; V23 tmp9 long "spilling Runtime Lookup tree" ; V24 tmp10 long "impRuntimeLookup slot" ; V25 tmp11 long "spilling Runtime Lookup tree" ; V26 tmp12 long "impRuntimeLookup slot" ; V27 tmp13 ref class-hnd "bubbling QMark1" ; V28 tmp14 long "spilling Runtime Lookup tree" ; V29 tmp15 long "impRuntimeLookup slot" ; V30 tmp16 ref class-hnd "bubbling QMark1" ; V31 tmp17 long "spilling Runtime Lookup tree" ; V32 tmp18 long "VirtualCall with runtime lookup" ; V33 tmp19 bool "Inlining Arg" ; V34 tmp20 ref class-hnd "Inlining Arg" ; V35 tmp21 ref class-hnd "Inlining Arg" ; V36 tmp22 bool "Inlining Arg" ; V37 tmp23 ref class-hnd "Inlining Arg" ; V38 tmp24 byref "Inline return value spill temp" ; V39 tmp25 ref class-hnd "Inline stloc first use temp" ; V40 tmp26 int "Inlining Arg" ; V41 tmp27 long "Inlining Arg" ; V42 tmp28 int "Inline stloc first use temp" ; V43 tmp29 bool "Inlining Arg" ; V44 tmp30 ref class-hnd "Inlining Arg" ; V45 tmp31 ref class-hnd "Inlining Arg" ; V46 tmp32 bool "Inlining Arg" ; V47 tmp33 ref class-hnd "Inlining Arg" ; V48 tmp34 ref class-hnd "Inlining Arg" ; V49 tmp35 bool "Inlining Arg" ; V50 tmp36 ref class-hnd "Inlining Arg" ; V51 tmp37 byref "Inline return value spill temp" ; V52 tmp38 ref class-hnd "Inline stloc first use temp" ; V53 tmp39 int "Inlining Arg" ; V54 tmp40 long "Inlining Arg" ; V55 tmp41 int "Inline stloc first use temp" ; V56 tmp42 bool "Inlining Arg" ; V57 tmp43 ref class-hnd "Inlining Arg" ; V58 tmp44 ref class-hnd "Inlining Arg" ; V59 tmp45 bool "Inlining Arg" ; V60 tmp46 ref class-hnd "Inlining Arg" ; V61 tmp47 ref class-hnd "Inlining Arg" ; V62 tmp48 int "index expr" ; V63 tmp49 int "index expr" ; V64 tmp50 int "argument with side effect" ; V65 cse0 byref "CSE - aggressive" ; V66 cse1 byref "CSE - aggressive" ; V67 cse2 long "CSE - moderate" ; V68 cse3 long "CSE - conservative" ; V69 cse4 long "CSE - conservative" ; V70 cse5 long "CSE - aggressive" ; V71 cse6 long "CSE - aggressive" ; V72 cse7 int "CSE - conservative" ; V73 cse8 ref "CSE - aggressive" ; V74 cse9 int "CSE - conservative" ; V75 cse10 int "CSE - conservative" ; V76 cse11 int "CSE - aggressive" In fgLocalVarLivenessInit Tracked variable (70 out of 77) table: V76 cse11 [ int]: refCnt = 9, refCntWtd = 25.50 V07 loc3 [ int]: refCnt = 8, refCntWtd = 25.50 V04 loc0 [ ref]: refCnt = 14, refCntWtd = 25 V09 loc5 [ int]: refCnt = 7, refCntWtd = 25 V00 this [ ref]: refCnt = 29, refCntWtd = 19 V06 loc2 [ int]: refCnt = 8, refCntWtd = 12.50 V65 cse0 [ byref]: refCnt = 4, refCntWtd = 12.50 V66 cse1 [ byref]: refCnt = 4, refCntWtd = 12.50 V19 tmp5 [ long]: refCnt = 4, refCntWtd = 12 V01 arg1 [ ref]: refCnt = 11, refCntWtd = 9 V73 cse8 [ ref]: refCnt = 13, refCntWtd = 10.50 V16 tmp2 [ long]: refCnt = 3, refCntWtd = 10 V70 cse5 [ long]: refCnt = 3, refCntWtd = 10 V71 cse6 [ long]: refCnt = 3, refCntWtd = 10 V40 tmp26 [ int]: refCnt = 4, refCntWtd = 8 V17 tmp3 [ ref]: refCnt = 2, refCntWtd = 8 V05 loc1 [ ref]: refCnt = 6, refCntWtd = 6 V03 arg3 [ ubyte]: refCnt = 6, refCntWtd = 4 V02 arg2 [ ref]: refCnt = 5, refCntWtd = 3.50 V67 cse2 [ long]: refCnt = 3, refCntWtd = 5 V12 loc8 [ ref]: refCnt = 3, refCntWtd = 4.50 V39 tmp25 [ ref]: refCnt = 4, refCntWtd = 4 V42 tmp28 [ int]: refCnt = 4, refCntWtd = 4 V53 tmp39 [ int]: refCnt = 4, refCntWtd = 4 V35 tmp21 [ ref]: refCnt = 3, refCntWtd = 4 V45 tmp31 [ ref]: refCnt = 3, refCntWtd = 4 V48 tmp34 [ ref]: refCnt = 3, refCntWtd = 4 V33 tmp19 [ bool]: refCnt = 2, refCntWtd = 4 V36 tmp22 [ bool]: refCnt = 2, refCntWtd = 4 V41 tmp27 [ long]: refCnt = 2, refCntWtd = 4 V43 tmp29 [ bool]: refCnt = 2, refCntWtd = 4 V46 tmp32 [ bool]: refCnt = 2, refCntWtd = 4 V08 loc4 [ byref]: refCnt = 5, refCntWtd = 3.50 V10 loc6 [ int]: refCnt = 6, refCntWtd = 3 V31 tmp17 [ long]: refCnt = 4, refCntWtd = 3 V58 tmp44 [ ref]: refCnt = 3, refCntWtd = 3 V61 tmp47 [ ref]: refCnt = 3, refCntWtd = 3 V62 tmp48 [ int]: refCnt = 3, refCntWtd = 3 V63 tmp49 [ int]: refCnt = 3, refCntWtd = 3 V37 tmp23 [ ref]: refCnt = 2, refCntWtd = 3 V11 loc7 [ byref]: refCnt = 5, refCntWtd = 2.50 V24 tmp10 [ long]: refCnt = 3, refCntWtd = 2.50 V29 tmp15 [ long]: refCnt = 3, refCntWtd = 2.50 V55 tmp41 [ int]: refCnt = 4, refCntWtd = 2 V15 tmp1 [ int]: refCnt = 3, refCntWtd = 2 V25 tmp11 [ long]: refCnt = 3, refCntWtd = 2 V38 tmp24 [ byref]: refCnt = 2, refCntWtd = 2 V50 tmp36 [ ref]: refCnt = 2, refCntWtd = 2 V49 tmp35 [ bool]: refCnt = 2, refCntWtd = 2 V54 tmp40 [ long]: refCnt = 2, refCntWtd = 2 V56 tmp42 [ bool]: refCnt = 2, refCntWtd = 2 V59 tmp45 [ bool]: refCnt = 2, refCntWtd = 2 V64 tmp50 [ int]: refCnt = 2, refCntWtd = 2 V34 tmp20 [ ref]: refCnt = 1, refCntWtd = 2 V44 tmp30 [ ref]: refCnt = 1, refCntWtd = 2 V47 tmp33 [ ref]: refCnt = 1, refCntWtd = 2 V52 tmp38 [ ref]: refCnt = 3, refCntWtd = 1.50 V13 loc9 [ int]: refCnt = 3, refCntWtd = 1.50 V72 cse7 [ int]: refCnt = 3, refCntWtd = 1.50 V74 cse9 [ int]: refCnt = 3, refCntWtd = 1.50 V75 cse10 [ int]: refCnt = 3, refCntWtd = 1.50 V68 cse3 [ long]: refCnt = 3, refCntWtd = 1.25 V69 cse4 [ long]: refCnt = 3, refCntWtd = 1.25 V51 tmp37 [ byref]: refCnt = 2, refCntWtd = 1 V57 tmp43 [ ref]: refCnt = 1, refCntWtd = 1 V60 tmp46 [ ref]: refCnt = 1, refCntWtd = 1 V21 tmp7 [ long]: refCnt = 4, refCntWtd = 0 V26 tmp12 [ long]: refCnt = 4, refCntWtd = 0 V23 tmp9 [ long]: refCnt = 3, refCntWtd = 0 V28 tmp14 [ long]: refCnt = 3, refCntWtd = 0 *************** In fgPerBlockLocalVarLiveness() BB01 USE(1)={V01} DEF(0)={ } BB02 USE(1)={V00} + ByrefExposed + GcHeap DEF(0)={ } BB03 USE(1)={V00} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB04 USE(1)={V00 } + ByrefExposed + GcHeap DEF(4)={ V73 V35 V33 V34} BB05 USE(1)={V35} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB06 USE(2)={ V00 V73 } + ByrefExposed + GcHeap DEF(3)={V04 V36 V37} BB07 USE(1)={V37} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB08 USE(1)={V00 } + ByrefExposed + GcHeap DEF(1)={ V05} BB09 USE(1)={V00 } + ByrefExposed + GcHeap DEF(2)={ V29 V68} BB10 USE(1)={ V68} DEF(1)={V31 } BB11 USE(1)={ V29} DEF(1)={V31 } BB12 USE(3)={V01 V05 V31 } + ByrefExposed + GcHeap DEF(1)={ V15} + ByrefExposed* + GcHeap* BB13 USE(1)={V01 } + ByrefExposed + GcHeap DEF(1)={ V15} + ByrefExposed* + GcHeap* BB14 USE(3)={ V00 V73 V15 } + ByrefExposed + GcHeap DEF(8)={V07 V06 V40 V39 V45 V41 V43 V44} BB15 USE(1)={V45} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB16 USE(4)={V06 V73 V40 V41 } DEF(4)={ V42 V48 V46 V47} BB17 USE(1)={V48} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB18 USE(3)={ V05 V39 V42 } + ByrefExposed + GcHeap DEF(3)={V09 V08 V38} BB19 USE(1)={V00 } + ByrefExposed + GcHeap DEF(2)={ V24 V69} BB20 USE(1)={ V69} DEF(1)={V25 } BB21 USE(1)={V24 } DEF(1)={ V25} BB22 USE(1)={ V25} + ByrefExposed + GcHeap DEF(1)={V12 } + ByrefExposed* + GcHeap* BB23 USE(2)={ V04 V09} + ByrefExposed + GcHeap DEF(1)={V76 } BB24 USE(3)={V04 V09 V06 } + ByrefExposed + GcHeap DEF(2)={ V65 V70} BB25 USE(4)={V04 V01 V70 V12} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB26 USE(3)={V76 V07 V65} + ByrefExposed + GcHeap DEF(2)={ V07 V09 } BB27 USE(0)={} DEF(0)={} BB28 USE(1)={V03} DEF(0)={ } BB29 USE(2)={V65 V02} DEF(0)={ } BB30 USE(1)={V03} DEF(0)={ } BB31 USE(0)={} DEF(0)={} BB32 USE(2)={ V04 V09} + ByrefExposed + GcHeap DEF(1)={V76 } BB33 USE(3)={V04 V09 V06 } + ByrefExposed + GcHeap DEF(2)={ V66 V71} BB34 USE(3)={V04 V00 V71 } + ByrefExposed + GcHeap DEF(3)={ V16 V17 V67} BB35 USE(1)={ V67} DEF(1)={V19 } BB36 USE(1)={ V16} DEF(1)={V19 } BB37 USE(4)={V19 V01 V17 V05} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB38 USE(1)={V03} DEF(0)={ } BB39 USE(2)={V66 V02} DEF(0)={ } BB40 USE(1)={V03} DEF(0)={ } BB41 USE(0)={} DEF(0)={} BB42 USE(3)={V76 V07 V66} + ByrefExposed + GcHeap DEF(2)={ V07 V09 } BB43 USE(0)={} DEF(0)={} BB44 USE(1)={V00} + ByrefExposed + GcHeap DEF(0)={ } BB45 USE(4)={V76 V04 V00 V73 } + ByrefExposed + GcHeap DEF(5)={ V10 V62 V50 V49 V74} BB46 USE(1)={V50} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB47 USE(3)={V76 V04 V00 } + ByrefExposed + GcHeap DEF(1)={ V63} BB48 USE(2)={V76 V00 } + ByrefExposed + GcHeap DEF(2)={ V13 V75} BB49 USE(3)={V00 V73 V75 } + ByrefExposed + GcHeap DEF(8)={ V53 V58 V54 V56 V64 V52 V72 V57} + ByrefExposed* + GcHeap* BB50 USE(1)={V58} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB51 USE(4)={V06 V73 V53 V54 } DEF(4)={ V61 V55 V59 V60} BB52 USE(1)={V61} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB53 USE(3)={ V55 V52 V72 } DEF(2)={V08 V51} BB54 USE(2)={ V00 V13} + ByrefExposed + GcHeap DEF(2)={V04 V10 } BB55 USE(8)={V07 V04 V00 V06 V01 V02 V08 V10 } + ByrefExposed + GcHeap DEF(1)={ V11} BB56 USE(1)={V05} DEF(0)={ } BB57 USE(2)={V04 V00} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB58 USE(0)={} DEF(0)={} BB59 USE(0)={} + ByrefExposed + GcHeap DEF(0)={} + ByrefExposed* + GcHeap* BB60 USE(1)={V00 } + ByrefExposed + GcHeap DEF(1)={ V26} BB61 USE(1)={V26 } + ByrefExposed + GcHeap DEF(1)={ V28} BB62 USE(1)={V26 } DEF(1)={ V28} BB63 USE(2)={V01 V28} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB64 USE(1)={V00 } + ByrefExposed + GcHeap DEF(1)={ V21} BB65 USE(1)={V21 } + ByrefExposed + GcHeap DEF(1)={ V23} BB66 USE(1)={V21 } DEF(1)={ V23} BB67 USE(2)={V01 V23} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* BB68 USE(0)={} + ByrefExposed + GcHeap DEF(0)={} + ByrefExposed* + GcHeap* BB69 USE(0)={} DEF(0)={} ** Memory liveness computed, GcHeap states and ByrefExposed states match *************** In fgInterBlockLocalVarLiveness() Reporting this as generic context: referenced BB liveness after fgLiveVarAnalysis(): BB01 IN (4)={V00 V01 V03 V02} + ByrefExposed + GcHeap OUT(4)={V00 V01 V03 V02} + ByrefExposed + GcHeap BB02 IN (4)={V00 V01 V03 V02} + ByrefExposed + GcHeap OUT(4)={V00 V01 V03 V02} + ByrefExposed + GcHeap BB03 IN (4)={V00 V01 V03 V02} + ByrefExposed + GcHeap OUT(4)={V00 V01 V03 V02} + ByrefExposed + GcHeap BB04 IN (4)={V00 V01 V03 V02 } + ByrefExposed + GcHeap OUT(6)={V00 V01 V73 V03 V02 V35} + ByrefExposed + GcHeap BB05 IN (6)={V00 V01 V73 V03 V02 V35} + ByrefExposed + GcHeap OUT(5)={V00 V01 V73 V03 V02 } + ByrefExposed + GcHeap BB06 IN (5)={ V00 V01 V73 V03 V02 } + ByrefExposed + GcHeap OUT(7)={V04 V00 V01 V73 V03 V02 V37} + ByrefExposed + GcHeap BB07 IN (7)={V04 V00 V01 V73 V03 V02 V37} + ByrefExposed + GcHeap OUT(6)={V04 V00 V01 V73 V03 V02 } + ByrefExposed + GcHeap BB08 IN (6)={V04 V00 V01 V73 V03 V02} + ByrefExposed + GcHeap OUT(7)={V04 V00 V01 V73 V05 V03 V02} + ByrefExposed + GcHeap BB09 IN (7)={V04 V00 V01 V73 V05 V03 V02 } + ByrefExposed + GcHeap OUT(9)={V04 V00 V01 V73 V05 V03 V02 V29 V68} + ByrefExposed + GcHeap BB10 IN (8)={V04 V00 V01 V73 V05 V03 V02 V68} + ByrefExposed + GcHeap OUT(8)={V04 V00 V01 V73 V05 V03 V02 V31 } + ByrefExposed + GcHeap BB11 IN (8)={V04 V00 V01 V73 V05 V03 V02 V29} + ByrefExposed + GcHeap OUT(8)={V04 V00 V01 V73 V05 V03 V02 V31 } + ByrefExposed + GcHeap BB12 IN (8)={V04 V00 V01 V73 V05 V03 V02 V31 } + ByrefExposed + GcHeap OUT(8)={V04 V00 V01 V73 V05 V03 V02 V15} + ByrefExposed + GcHeap BB13 IN (7)={V04 V00 V01 V73 V05 V03 V02 } + ByrefExposed + GcHeap OUT(8)={V04 V00 V01 V73 V05 V03 V02 V15} + ByrefExposed + GcHeap BB14 IN (8)={ V04 V00 V01 V73 V05 V03 V02 V15} + ByrefExposed + GcHeap OUT(13)={V07 V04 V00 V06 V01 V73 V40 V05 V03 V02 V39 V45 V41 } + ByrefExposed + GcHeap BB15 IN (13)={V07 V04 V00 V06 V01 V73 V40 V05 V03 V02 V39 V45 V41} + ByrefExposed + GcHeap OUT(12)={V07 V04 V00 V06 V01 V73 V40 V05 V03 V02 V39 V41} + ByrefExposed + GcHeap BB16 IN (12)={V07 V04 V00 V06 V01 V73 V40 V05 V03 V02 V39 V41} + ByrefExposed + GcHeap OUT(12)={V07 V04 V00 V06 V01 V73 V05 V03 V02 V39 V42 V48 } + ByrefExposed + GcHeap BB17 IN (12)={V07 V04 V00 V06 V01 V73 V05 V03 V02 V39 V42 V48} + ByrefExposed + GcHeap OUT(11)={V07 V04 V00 V06 V01 V73 V05 V03 V02 V39 V42 } + ByrefExposed + GcHeap BB18 IN (11)={V07 V04 V00 V06 V01 V73 V05 V03 V02 V39 V42 } + ByrefExposed + GcHeap OUT(11)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08} + ByrefExposed + GcHeap BB19 IN (11)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08 } + ByrefExposed + GcHeap OUT(13)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08 V24 V69} + ByrefExposed + GcHeap BB20 IN (12)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08 V69} + ByrefExposed + GcHeap OUT(12)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08 V25 } + ByrefExposed + GcHeap BB21 IN (12)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08 V24 } + ByrefExposed + GcHeap OUT(12)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08 V25} + ByrefExposed + GcHeap BB22 IN (12)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08 V25} + ByrefExposed + GcHeap OUT(12)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V12 V08 } + ByrefExposed + GcHeap BB23 IN (12)={ V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap OUT(13)={V76 V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap BB24 IN (13)={V76 V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap OUT(14)={V76 V07 V04 V00 V06 V65 V01 V73 V70 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap BB25 IN (14)={V76 V07 V04 V00 V06 V65 V01 V73 V70 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap OUT(13)={V76 V07 V04 V00 V06 V65 V01 V73 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap BB26 IN (13)={V76 V07 V04 V00 V06 V65 V01 V73 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap OUT(12)={ V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap BB27 IN (12)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap OUT(12)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap BB28 IN (5)={V00 V65 V01 V03 V02} + ByrefExposed + GcHeap OUT(5)={V00 V65 V01 V03 V02} + ByrefExposed + GcHeap BB29 IN (3)={V00 V65 V02} OUT(1)={V00 } BB30 IN (3)={V00 V01 V03} + ByrefExposed + GcHeap OUT(2)={V00 V01 } + ByrefExposed + GcHeap BB31 IN (1)={V00} OUT(1)={V00} BB32 IN (11)={ V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(12)={V76 V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08} + ByrefExposed + GcHeap BB33 IN (12)={V76 V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(13)={V76 V07 V04 V00 V06 V66 V01 V73 V71 V05 V03 V02 V08} + ByrefExposed + GcHeap BB34 IN (13)={V76 V07 V04 V00 V06 V66 V01 V73 V71 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(15)={V76 V07 V04 V00 V06 V66 V01 V73 V16 V17 V05 V03 V02 V67 V08} + ByrefExposed + GcHeap BB35 IN (14)={V76 V07 V04 V00 V06 V66 V01 V73 V17 V05 V03 V02 V67 V08} + ByrefExposed + GcHeap OUT(14)={V76 V07 V04 V00 V06 V66 V19 V01 V73 V17 V05 V03 V02 V08} + ByrefExposed + GcHeap BB36 IN (14)={V76 V07 V04 V00 V06 V66 V01 V73 V16 V17 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(14)={V76 V07 V04 V00 V06 V66 V19 V01 V73 V17 V05 V03 V02 V08} + ByrefExposed + GcHeap BB37 IN (14)={V76 V07 V04 V00 V06 V66 V19 V01 V73 V17 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(12)={V76 V07 V04 V00 V06 V66 V01 V73 V05 V03 V02 V08} + ByrefExposed + GcHeap BB38 IN (5)={V00 V66 V01 V03 V02} + ByrefExposed + GcHeap OUT(5)={V00 V66 V01 V03 V02} + ByrefExposed + GcHeap BB39 IN (3)={V00 V66 V02} OUT(1)={V00 } BB40 IN (3)={V00 V01 V03} + ByrefExposed + GcHeap OUT(2)={V00 V01 } + ByrefExposed + GcHeap BB41 IN (1)={V00} OUT(1)={V00} BB42 IN (12)={V76 V07 V04 V00 V06 V66 V01 V73 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(11)={ V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08} + ByrefExposed + GcHeap BB43 IN (11)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(11)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08} + ByrefExposed + GcHeap BB44 IN (10)={V76 V07 V04 V00 V06 V01 V73 V05 V02 V08} + ByrefExposed + GcHeap OUT(10)={V76 V07 V04 V00 V06 V01 V73 V05 V02 V08} + ByrefExposed + GcHeap BB45 IN (10)={V76 V07 V04 V00 V06 V01 V73 V05 V02 V08 } + ByrefExposed + GcHeap OUT(11)={V76 V07 V04 V00 V06 V01 V05 V02 V08 V10 V50} + ByrefExposed + GcHeap BB46 IN (11)={V76 V07 V04 V00 V06 V01 V05 V02 V08 V10 V50} + ByrefExposed + GcHeap OUT(10)={V76 V07 V04 V00 V06 V01 V05 V02 V08 V10 } + ByrefExposed + GcHeap BB47 IN (10)={V76 V07 V04 V00 V06 V01 V05 V02 V08 V10} + ByrefExposed + GcHeap OUT(9)={ V07 V04 V00 V06 V01 V05 V02 V08 V10} + ByrefExposed + GcHeap BB48 IN (9)={V76 V07 V00 V06 V01 V73 V05 V02 V08 } + ByrefExposed + GcHeap OUT(10)={ V07 V00 V06 V01 V73 V05 V02 V08 V13 V75} + ByrefExposed + GcHeap BB49 IN (9)={V07 V00 V06 V01 V73 V05 V02 V13 V75} + ByrefExposed + GcHeap OUT(13)={V07 V00 V06 V01 V73 V05 V02 V53 V58 V54 V52 V13 V72 } + ByrefExposed + GcHeap BB50 IN (13)={V07 V00 V06 V01 V73 V05 V02 V53 V58 V54 V52 V13 V72} + ByrefExposed + GcHeap OUT(12)={V07 V00 V06 V01 V73 V05 V02 V53 V54 V52 V13 V72} + ByrefExposed + GcHeap BB51 IN (12)={V07 V00 V06 V01 V73 V05 V02 V53 V54 V52 V13 V72} + ByrefExposed + GcHeap OUT(11)={V07 V00 V06 V01 V05 V02 V61 V55 V52 V13 V72} + ByrefExposed + GcHeap BB52 IN (11)={V07 V00 V06 V01 V05 V02 V61 V55 V52 V13 V72} + ByrefExposed + GcHeap OUT(10)={V07 V00 V06 V01 V05 V02 V55 V52 V13 V72} + ByrefExposed + GcHeap BB53 IN (10)={V07 V00 V06 V01 V05 V02 V55 V52 V13 V72} + ByrefExposed + GcHeap OUT(8)={V07 V00 V06 V01 V05 V02 V08 V13 } + ByrefExposed + GcHeap BB54 IN (8)={V07 V00 V06 V01 V05 V02 V08 V13} + ByrefExposed + GcHeap OUT(9)={V07 V04 V00 V06 V01 V05 V02 V08 V10 } + ByrefExposed + GcHeap BB55 IN (9)={V07 V04 V00 V06 V01 V05 V02 V08 V10} + ByrefExposed + GcHeap OUT(3)={ V04 V00 V05 } + ByrefExposed + GcHeap BB56 IN (3)={V04 V00 V05} + ByrefExposed + GcHeap OUT(2)={V04 V00 } + ByrefExposed + GcHeap BB57 IN (2)={V04 V00} + ByrefExposed + GcHeap OUT(1)={ V00} BB58 IN (1)={V00} OUT(1)={V00} BB59 IN (1)={V00} + ByrefExposed + GcHeap OUT(1)={V00} BB60 IN (2)={V00 V01 } + ByrefExposed + GcHeap OUT(3)={V00 V01 V26} + ByrefExposed + GcHeap BB61 IN (3)={V00 V01 V26 } + ByrefExposed + GcHeap OUT(3)={V00 V01 V28} + ByrefExposed + GcHeap BB62 IN (3)={V00 V01 V26 } + ByrefExposed + GcHeap OUT(3)={V00 V01 V28} + ByrefExposed + GcHeap BB63 IN (3)={V00 V01 V28} + ByrefExposed + GcHeap OUT(1)={V00 } BB64 IN (2)={V00 V01 } + ByrefExposed + GcHeap OUT(3)={V00 V01 V21} + ByrefExposed + GcHeap BB65 IN (3)={V00 V01 V21 } + ByrefExposed + GcHeap OUT(3)={V00 V01 V23} + ByrefExposed + GcHeap BB66 IN (3)={V00 V01 V21 } + ByrefExposed + GcHeap OUT(3)={V00 V01 V23} + ByrefExposed + GcHeap BB67 IN (3)={V00 V01 V23} + ByrefExposed + GcHeap OUT(1)={V00 } BB68 IN (1)={V00} + ByrefExposed + GcHeap OUT(1)={V00} BB69 IN (1)={V00} OUT(1)={V00} Removing dead store: N008 ( 5, 13) [000554] DA--G------- * STORE_LCL_VAR ref V34 tmp20 d:1 (last use) Removing dead LclVar use: N005 ( 1, 1) [001292] ------------ * LCL_VAR ref V73 cse8 u:1 $105 Removing dead store: N003 ( 1, 3) [000652] DA--G------- * STORE_LCL_VAR ref V44 tmp30 d:1 (last use) Removing dead LclVar use: N001 ( 1, 1) [001296] ------------ * LCL_VAR ref V73 cse8 u:1 $105 Removing dead store: N003 ( 1, 3) [000675] DA--G------- * STORE_LCL_VAR ref V47 tmp33 d:1 (last use) Removing dead LclVar use: N001 ( 1, 1) [001298] ------------ * LCL_VAR ref V73 cse8 u:1 $105 Removing dead store: N003 ( 5, 4) [000783] DA--G------- * STORE_LCL_VAR ref V57 tmp43 d:1 (last use) Removing dead LclVar use: N001 ( 1, 1) [001301] ------------ * LCL_VAR ref V73 cse8 u:1 $105 Removing dead store: N003 ( 5, 4) [000806] DA--G------- * STORE_LCL_VAR ref V60 tmp46 d:1 (last use) Removing dead LclVar use: N001 ( 1, 1) [001303] ------------ * LCL_VAR ref V73 cse8 u:1 $105 *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i LIR BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i LIR BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe LIR BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i LIR BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe LIR BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i LIR BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe LIR BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i LIR BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe LIR BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe LIR BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe LIR BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe LIR BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe LIR BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen LIR BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe LIR BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen LIR BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe LIR BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen LIR BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe LIR BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe LIR BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe LIR BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe LIR BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target LIR BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd LIR BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd LIR BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd LIR BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal LIR BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd LIR BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen LIR BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd LIR BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal Loop1 gcsafe LIR BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target LIR BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd LIR BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd LIR BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe LIR BB36 [0108] 1 BB34 1 [???..???) i gcsafe LIR BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd LIR BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd LIR BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen LIR BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd LIR BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe LIR BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd LIR BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal LIR BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i LIR BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen LIR BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe LIR BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen LIR BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen LIR BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen LIR BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe LIR BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen LIR BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe LIR BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen LIR BB54 [0044] 2 BB48,BB53 0.50 [261..276) i LIR BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen LIR BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall LIR BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen LIR BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal LIR BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe LIR BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd LIR BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe LIR BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe LIR BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd LIR BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd LIR BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe LIR BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe LIR BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd LIR BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd LIR BB69 [0117] 0 0 [???..???) (throw ) keep i internal rare LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V01: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 2, refCntWtd = 1.50 New refCnts for V00: refCnt = 3, refCntWtd = 2.50 New refCnts for V33: refCnt = 1, refCntWtd = 2 New refCnts for V73: refCnt = 1, refCntWtd = 1 New refCnts for V73: refCnt = 2, refCntWtd = 2 New refCnts for V35: refCnt = 1, refCntWtd = 2 New refCnts for V33: refCnt = 2, refCntWtd = 4 New refCnts for V35: refCnt = 2, refCntWtd = 3 New refCnts for V35: refCnt = 3, refCntWtd = 4 New refCnts for V00: refCnt = 4, refCntWtd = 3.50 New refCnts for V04: refCnt = 1, refCntWtd = 1 New refCnts for V04: refCnt = 2, refCntWtd = 2 New refCnts for V36: refCnt = 1, refCntWtd = 2 New refCnts for V73: refCnt = 3, refCntWtd = 3 New refCnts for V37: refCnt = 1, refCntWtd = 2 New refCnts for V36: refCnt = 2, refCntWtd = 4 New refCnts for V37: refCnt = 2, refCntWtd = 3 New refCnts for V00: refCnt = 5, refCntWtd = 4.50 New refCnts for V05: refCnt = 1, refCntWtd = 1 New refCnts for V05: refCnt = 2, refCntWtd = 2 New refCnts for V00: refCnt = 6, refCntWtd = 5 New refCnts for V29: refCnt = 1, refCntWtd = 1 New refCnts for V29: refCnt = 2, refCntWtd = 2 New refCnts for V68: refCnt = 1, refCntWtd = 0.50 New refCnts for V68: refCnt = 2, refCntWtd = 1 New refCnts for V68: refCnt = 3, refCntWtd = 1.25 New refCnts for V31: refCnt = 1, refCntWtd = 0.50 New refCnts for V29: refCnt = 3, refCntWtd = 2.50 New refCnts for V31: refCnt = 2, refCntWtd = 1 New refCnts for V05: refCnt = 3, refCntWtd = 2.50 New refCnts for V31: refCnt = 3, refCntWtd = 2 New refCnts for V01: refCnt = 2, refCntWtd = 1.50 New refCnts for V31: refCnt = 4, refCntWtd = 3 New refCnts for V15: refCnt = 1, refCntWtd = 0.50 New refCnts for V01: refCnt = 3, refCntWtd = 2 New refCnts for V01: refCnt = 4, refCntWtd = 2.50 New refCnts for V15: refCnt = 2, refCntWtd = 1 New refCnts for V15: refCnt = 3, refCntWtd = 2 New refCnts for V06: refCnt = 1, refCntWtd = 1 New refCnts for V07: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 7, refCntWtd = 6 New refCnts for V39: refCnt = 1, refCntWtd = 1 New refCnts for V39: refCnt = 2, refCntWtd = 2 New refCnts for V40: refCnt = 1, refCntWtd = 2 New refCnts for V00: refCnt = 8, refCntWtd = 7 New refCnts for V41: refCnt = 1, refCntWtd = 2 New refCnts for V40: refCnt = 2, refCntWtd = 4 New refCnts for V43: refCnt = 1, refCntWtd = 2 New refCnts for V73: refCnt = 4, refCntWtd = 4 New refCnts for V45: refCnt = 1, refCntWtd = 2 New refCnts for V43: refCnt = 2, refCntWtd = 4 New refCnts for V45: refCnt = 2, refCntWtd = 3 New refCnts for V45: refCnt = 3, refCntWtd = 4 New refCnts for V41: refCnt = 2, refCntWtd = 4 New refCnts for V06: refCnt = 2, refCntWtd = 2 New refCnts for V40: refCnt = 3, refCntWtd = 6 New refCnts for V42: refCnt = 1, refCntWtd = 1 New refCnts for V06: refCnt = 3, refCntWtd = 3 New refCnts for V40: refCnt = 4, refCntWtd = 8 New refCnts for V42: refCnt = 2, refCntWtd = 2 New refCnts for V46: refCnt = 1, refCntWtd = 2 New refCnts for V73: refCnt = 5, refCntWtd = 5 New refCnts for V48: refCnt = 1, refCntWtd = 2 New refCnts for V46: refCnt = 2, refCntWtd = 4 New refCnts for V48: refCnt = 2, refCntWtd = 3 New refCnts for V48: refCnt = 3, refCntWtd = 4 New refCnts for V42: refCnt = 3, refCntWtd = 3 New refCnts for V39: refCnt = 3, refCntWtd = 3 New refCnts for V39: refCnt = 4, refCntWtd = 4 New refCnts for V42: refCnt = 4, refCntWtd = 4 New refCnts for V38: refCnt = 1, refCntWtd = 1 New refCnts for V38: refCnt = 2, refCntWtd = 2 New refCnts for V08: refCnt = 1, refCntWtd = 1 New refCnts for V08: refCnt = 2, refCntWtd = 2 New refCnts for V09: refCnt = 1, refCntWtd = 1 New refCnts for V05: refCnt = 4, refCntWtd = 3.50 New refCnts for V00: refCnt = 9, refCntWtd = 7.50 New refCnts for V24: refCnt = 1, refCntWtd = 1 New refCnts for V24: refCnt = 2, refCntWtd = 2 New refCnts for V69: refCnt = 1, refCntWtd = 0.50 New refCnts for V69: refCnt = 2, refCntWtd = 1 New refCnts for V69: refCnt = 3, refCntWtd = 1.25 New refCnts for V25: refCnt = 1, refCntWtd = 0.50 New refCnts for V24: refCnt = 3, refCntWtd = 2.50 New refCnts for V25: refCnt = 2, refCntWtd = 1 New refCnts for V25: refCnt = 3, refCntWtd = 2 New refCnts for V12: refCnt = 1, refCntWtd = 0.50 New refCnts for V04: refCnt = 3, refCntWtd = 6 New refCnts for V76: refCnt = 1, refCntWtd = 4 New refCnts for V76: refCnt = 2, refCntWtd = 8 New refCnts for V09: refCnt = 2, refCntWtd = 5 New refCnts for V04: refCnt = 4, refCntWtd = 10 New refCnts for V09: refCnt = 3, refCntWtd = 9 New refCnts for V70: refCnt = 1, refCntWtd = 4 New refCnts for V70: refCnt = 2, refCntWtd = 8 New refCnts for V65: refCnt = 1, refCntWtd = 4 New refCnts for V65: refCnt = 2, refCntWtd = 8 New refCnts for V06: refCnt = 4, refCntWtd = 7 New refCnts for V04: refCnt = 5, refCntWtd = 12 New refCnts for V70: refCnt = 3, refCntWtd = 10 New refCnts for V12: refCnt = 2, refCntWtd = 2.50 New refCnts for V01: refCnt = 5, refCntWtd = 4.50 New refCnts for V12: refCnt = 3, refCntWtd = 4.50 New refCnts for V65: refCnt = 3, refCntWtd = 12 New refCnts for V09: refCnt = 4, refCntWtd = 13 New refCnts for V07: refCnt = 2, refCntWtd = 5 New refCnts for V07: refCnt = 3, refCntWtd = 9 New refCnts for V76: refCnt = 3, refCntWtd = 12 New refCnts for V07: refCnt = 4, refCntWtd = 13 New refCnts for V03: refCnt = 1, refCntWtd = 0.50 New refCnts for V65: refCnt = 4, refCntWtd = 12.50 New refCnts for V02: refCnt = 1, refCntWtd = 0.50 New refCnts for V03: refCnt = 2, refCntWtd = 1 New refCnts for V04: refCnt = 6, refCntWtd = 16 New refCnts for V76: refCnt = 4, refCntWtd = 16 New refCnts for V76: refCnt = 5, refCntWtd = 20 New refCnts for V09: refCnt = 5, refCntWtd = 17 New refCnts for V04: refCnt = 7, refCntWtd = 20 New refCnts for V09: refCnt = 6, refCntWtd = 21 New refCnts for V71: refCnt = 1, refCntWtd = 4 New refCnts for V71: refCnt = 2, refCntWtd = 8 New refCnts for V66: refCnt = 1, refCntWtd = 4 New refCnts for V66: refCnt = 2, refCntWtd = 8 New refCnts for V06: refCnt = 5, refCntWtd = 11 New refCnts for V04: refCnt = 8, refCntWtd = 22 New refCnts for V71: refCnt = 3, refCntWtd = 10 New refCnts for V17: refCnt = 1, refCntWtd = 4 New refCnts for V00: refCnt = 10, refCntWtd = 9.50 New refCnts for V16: refCnt = 1, refCntWtd = 4 New refCnts for V16: refCnt = 2, refCntWtd = 8 New refCnts for V67: refCnt = 1, refCntWtd = 2 New refCnts for V67: refCnt = 2, refCntWtd = 4 New refCnts for V67: refCnt = 3, refCntWtd = 5 New refCnts for V19: refCnt = 1, refCntWtd = 2 New refCnts for V16: refCnt = 3, refCntWtd = 10 New refCnts for V19: refCnt = 2, refCntWtd = 4 New refCnts for V05: refCnt = 5, refCntWtd = 5.50 New refCnts for V19: refCnt = 3, refCntWtd = 8 New refCnts for V17: refCnt = 2, refCntWtd = 8 New refCnts for V01: refCnt = 6, refCntWtd = 6.50 New refCnts for V19: refCnt = 4, refCntWtd = 12 New refCnts for V03: refCnt = 3, refCntWtd = 1.50 New refCnts for V66: refCnt = 3, refCntWtd = 8.50 New refCnts for V02: refCnt = 2, refCntWtd = 1 New refCnts for V03: refCnt = 4, refCntWtd = 2 New refCnts for V66: refCnt = 4, refCntWtd = 12.50 New refCnts for V09: refCnt = 7, refCntWtd = 25 New refCnts for V07: refCnt = 5, refCntWtd = 17 New refCnts for V07: refCnt = 6, refCntWtd = 21 New refCnts for V76: refCnt = 6, refCntWtd = 24 New refCnts for V07: refCnt = 7, refCntWtd = 25 New refCnts for V00: refCnt = 11, refCntWtd = 10 New refCnts for V00: refCnt = 12, refCntWtd = 10.50 New refCnts for V74: refCnt = 1, refCntWtd = 0.50 New refCnts for V74: refCnt = 2, refCntWtd = 1 New refCnts for V10: refCnt = 1, refCntWtd = 0.50 New refCnts for V74: refCnt = 3, refCntWtd = 1.50 New refCnts for V62: refCnt = 1, refCntWtd = 1 New refCnts for V62: refCnt = 2, refCntWtd = 2 New refCnts for V76: refCnt = 7, refCntWtd = 24.50 New refCnts for V04: refCnt = 9, refCntWtd = 22.50 New refCnts for V62: refCnt = 3, refCntWtd = 3 New refCnts for V49: refCnt = 1, refCntWtd = 1 New refCnts for V73: refCnt = 6, refCntWtd = 5.50 New refCnts for V50: refCnt = 1, refCntWtd = 1 New refCnts for V49: refCnt = 2, refCntWtd = 2 New refCnts for V50: refCnt = 2, refCntWtd = 2 New refCnts for V00: refCnt = 13, refCntWtd = 11 New refCnts for V00: refCnt = 14, refCntWtd = 11.50 New refCnts for V63: refCnt = 1, refCntWtd = 1 New refCnts for V63: refCnt = 2, refCntWtd = 2 New refCnts for V76: refCnt = 8, refCntWtd = 25 New refCnts for V04: refCnt = 10, refCntWtd = 23 New refCnts for V63: refCnt = 3, refCntWtd = 3 New refCnts for V00: refCnt = 15, refCntWtd = 12 New refCnts for V00: refCnt = 16, refCntWtd = 12.50 New refCnts for V00: refCnt = 17, refCntWtd = 13 New refCnts for V75: refCnt = 1, refCntWtd = 0.50 New refCnts for V75: refCnt = 2, refCntWtd = 1 New refCnts for V13: refCnt = 1, refCntWtd = 0.50 New refCnts for V76: refCnt = 9, refCntWtd = 25.50 New refCnts for V13: refCnt = 2, refCntWtd = 1 New refCnts for V75: refCnt = 3, refCntWtd = 1.50 New refCnts for V64: refCnt = 1, refCntWtd = 1 New refCnts for V64: refCnt = 2, refCntWtd = 2 New refCnts for V00: refCnt = 18, refCntWtd = 13.50 New refCnts for V00: refCnt = 19, refCntWtd = 14 New refCnts for V52: refCnt = 1, refCntWtd = 0.50 New refCnts for V52: refCnt = 2, refCntWtd = 1 New refCnts for V72: refCnt = 1, refCntWtd = 0.50 New refCnts for V72: refCnt = 2, refCntWtd = 1 New refCnts for V53: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 20, refCntWtd = 14.50 New refCnts for V54: refCnt = 1, refCntWtd = 1 New refCnts for V53: refCnt = 2, refCntWtd = 2 New refCnts for V56: refCnt = 1, refCntWtd = 1 New refCnts for V73: refCnt = 7, refCntWtd = 6 New refCnts for V58: refCnt = 1, refCntWtd = 1 New refCnts for V56: refCnt = 2, refCntWtd = 2 New refCnts for V58: refCnt = 2, refCntWtd = 2 New refCnts for V58: refCnt = 3, refCntWtd = 3 New refCnts for V54: refCnt = 2, refCntWtd = 2 New refCnts for V06: refCnt = 6, refCntWtd = 11.50 New refCnts for V53: refCnt = 3, refCntWtd = 3 New refCnts for V55: refCnt = 1, refCntWtd = 0.50 New refCnts for V06: refCnt = 7, refCntWtd = 12 New refCnts for V53: refCnt = 4, refCntWtd = 4 New refCnts for V55: refCnt = 2, refCntWtd = 1 New refCnts for V59: refCnt = 1, refCntWtd = 1 New refCnts for V73: refCnt = 8, refCntWtd = 6.50 New refCnts for V61: refCnt = 1, refCntWtd = 1 New refCnts for V59: refCnt = 2, refCntWtd = 2 New refCnts for V61: refCnt = 2, refCntWtd = 2 New refCnts for V61: refCnt = 3, refCntWtd = 3 New refCnts for V55: refCnt = 3, refCntWtd = 1.50 New refCnts for V72: refCnt = 3, refCntWtd = 1.50 New refCnts for V52: refCnt = 3, refCntWtd = 1.50 New refCnts for V55: refCnt = 4, refCntWtd = 2 New refCnts for V51: refCnt = 1, refCntWtd = 0.50 New refCnts for V51: refCnt = 2, refCntWtd = 1 New refCnts for V08: refCnt = 3, refCntWtd = 2.50 New refCnts for V13: refCnt = 3, refCntWtd = 1.50 New refCnts for V10: refCnt = 2, refCntWtd = 1 New refCnts for V10: refCnt = 3, refCntWtd = 1.50 New refCnts for V00: refCnt = 21, refCntWtd = 15 New refCnts for V00: refCnt = 22, refCntWtd = 15.50 New refCnts for V04: refCnt = 11, refCntWtd = 23.50 New refCnts for V10: refCnt = 4, refCntWtd = 2 New refCnts for V04: refCnt = 12, refCntWtd = 24 New refCnts for V04: refCnt = 13, refCntWtd = 24.50 New refCnts for V10: refCnt = 5, refCntWtd = 2.50 New refCnts for V11: refCnt = 1, refCntWtd = 0.50 New refCnts for V11: refCnt = 2, refCntWtd = 1 New refCnts for V06: refCnt = 8, refCntWtd = 12.50 New refCnts for V08: refCnt = 4, refCntWtd = 3 New refCnts for V11: refCnt = 3, refCntWtd = 1.50 New refCnts for V11: refCnt = 4, refCntWtd = 2 New refCnts for V01: refCnt = 7, refCntWtd = 7 New refCnts for V11: refCnt = 5, refCntWtd = 2.50 New refCnts for V02: refCnt = 3, refCntWtd = 1.50 New refCnts for V10: refCnt = 6, refCntWtd = 3 New refCnts for V08: refCnt = 5, refCntWtd = 3.50 New refCnts for V00: refCnt = 23, refCntWtd = 16 New refCnts for V00: refCnt = 24, refCntWtd = 16.50 New refCnts for V07: refCnt = 8, refCntWtd = 25.50 New refCnts for V05: refCnt = 6, refCntWtd = 6 New refCnts for V04: refCnt = 14, refCntWtd = 25 New refCnts for V00: refCnt = 25, refCntWtd = 17 New refCnts for V00: refCnt = 26, refCntWtd = 17 New refCnts for V26: refCnt = 1, refCntWtd = 0 New refCnts for V26: refCnt = 2, refCntWtd = 0 New refCnts for V26: refCnt = 3, refCntWtd = 0 New refCnts for V28: refCnt = 1, refCntWtd = 0 New refCnts for V26: refCnt = 4, refCntWtd = 0 New refCnts for V28: refCnt = 2, refCntWtd = 0 New refCnts for V28: refCnt = 3, refCntWtd = 0 New refCnts for V01: refCnt = 8, refCntWtd = 7 New refCnts for V00: refCnt = 27, refCntWtd = 17 New refCnts for V21: refCnt = 1, refCntWtd = 0 New refCnts for V21: refCnt = 2, refCntWtd = 0 New refCnts for V21: refCnt = 3, refCntWtd = 0 New refCnts for V23: refCnt = 1, refCntWtd = 0 New refCnts for V21: refCnt = 4, refCntWtd = 0 New refCnts for V23: refCnt = 2, refCntWtd = 0 New refCnts for V23: refCnt = 3, refCntWtd = 0 New refCnts for V01: refCnt = 9, refCntWtd = 7 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 28, refCntWtd = 18 New refCnts for V00: refCnt = 29, refCntWtd = 19 New refCnts for V01: refCnt = 10, refCntWtd = 8 New refCnts for V01: refCnt = 11, refCntWtd = 9 New refCnts for V02: refCnt = 4, refCntWtd = 2.50 New refCnts for V02: refCnt = 5, refCntWtd = 3.50 New refCnts for V03: refCnt = 5, refCntWtd = 3 New refCnts for V03: refCnt = 6, refCntWtd = 4 *************** Finishing PHASE Lowering nodeinfo Trees after Lowering nodeinfo ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i LIR BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i LIR BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe LIR BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i LIR BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe LIR BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i LIR BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe LIR BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i LIR BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe LIR BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe LIR BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe LIR BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe LIR BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe LIR BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen LIR BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe LIR BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen LIR BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe LIR BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen LIR BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe LIR BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe LIR BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe LIR BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe LIR BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target LIR BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd LIR BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd LIR BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd LIR BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal LIR BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd LIR BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen LIR BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd LIR BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal Loop1 gcsafe LIR BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target LIR BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd LIR BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd LIR BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe LIR BB36 [0108] 1 BB34 1 [???..???) i gcsafe LIR BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd LIR BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd LIR BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen LIR BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd LIR BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe LIR BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd LIR BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal LIR BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i LIR BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen LIR BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe LIR BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen LIR BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen LIR BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen LIR BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe LIR BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen LIR BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe LIR BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen LIR BB54 [0044] 2 BB48,BB53 0.50 [261..276) i LIR BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen LIR BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall LIR BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen LIR BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal LIR BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe LIR BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd LIR BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe LIR BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe LIR BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd LIR BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd LIR BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe LIR BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe LIR BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd LIR BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd LIR BB69 [0117] 0 0 [???..???) (throw ) keep i internal rare LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} [001332] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V01 arg1 u:1 $101 N002 ( 1, 1) [000001] -c---------- t1 = CNS_INT ref null $VN.Null /--* t0 ref +--* t1 ref N003 ( 3, 3) [000002] J------N---- * EQ void $180 N004 ( 5, 5) [000003] ------------ * JTRUE void ------------ BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} [001333] ------------ IL_OFFSET void IL offset: 0xe N001 ( 1, 1) [000004] ------------ t4 = LCL_VAR ref V00 this u:1 $100 /--* t4 ref N003 ( 2, 2) [000814] -c---------- t814 = * LEA(b+8) byref /--* t814 byref N004 ( 4, 4) [000005] -c-XG------- t5 = * IND ref N005 ( 1, 1) [000006] -c---------- t6 = CNS_INT ref null $VN.Null /--* t5 ref +--* t6 ref N006 ( 6, 6) [000007] J--XG--N---- * NE void N007 ( 8, 8) [000008] ---XG------- * JTRUE void ------------ BB03 [016..01E), preds={BB02} succs={BB04} N003 ( 1, 1) [000526] ------------ t526 = LCL_VAR ref V00 this u:1 $100 /--* t526 ref [001455] ------------ t1455 = * PUTARG_REG ref REG rcx N004 ( 1, 1) [000527] ------------ t527 = CNS_INT int 0 $c0 /--* t527 int [001456] ------------ t1456 = * PUTARG_REG int REG rdx /--* t1455 ref this in rcx +--* t1456 int arg1 in rdx N005 ( 16, 10) [000528] --CXG------- t528 = * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize $1c2 ------------ BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} [001334] ------------ IL_OFFSET void IL offset: 0x1e N001 ( 1, 1) [000009] ------------ t9 = LCL_VAR ref V00 this u:1 $100 /--* t9 ref N003 ( 2, 2) [000818] -c---------- t818 = * LEA(b+8) byref /--* t818 byref N004 ( 4, 4) [000010] nc--GO------ t10 = * IND ref N005 ( 1, 1) [000011] -c---------- t11 = CNS_INT ref null $VN.Null /--* t10 ref +--* t11 ref N006 ( 9, 6) [000012] N---GO------ t12 = * NE int /--* t12 int N008 ( 9, 6) [000544] DA--GO------ * STORE_LCL_VAR int V33 tmp19 d:1 [001335] ------------ IL_OFFSET void IL offset: 0x1e N001 ( 2, 10) [000537] H----------- t537 = CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 /--* t537 long N002 ( 4, 12) [000538] #---G------- t538 = * IND ref $105 /--* t538 ref N004 ( 4, 12) [001291] DA--G------- * STORE_LCL_VAR ref V73 cse8 d:1 [001336] ------------ IL_OFFSET void IL offset: 0x1e N001 ( 1, 1) [001294] ------------ t1294 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1294 ref N003 ( 1, 3) [000556] DA--G------- * STORE_LCL_VAR ref V35 tmp21 d:1 [001337] ------------ IL_OFFSET void IL offset: 0x1e N001 ( 1, 1) [000546] ------------ t546 = LCL_VAR int V33 tmp19 u:1 (last use) N002 ( 1, 1) [000547] -c---------- t547 = CNS_INT int 0 $c0 /--* t546 int +--* t547 int N003 ( 3, 3) [000548] J------N---- * NE void N004 ( 5, 5) [000549] ------------ * JTRUE void ------------ BB05 [01E..01F), preds={BB04} succs={BB06} [001338] ------------ IL_OFFSET void IL offset: 0x1e N003 ( 1, 1) [000550] ------------ t550 = LCL_VAR ref V35 tmp21 u:1 $105 /--* t550 ref [001457] ------------ t1457 = * PUTARG_REG ref REG rcx N004 ( 1, 1) [000551] ------------ t551 = LCL_VAR ref V35 tmp21 u:1 (last use) $105 /--* t551 ref [001458] ------------ t1458 = * PUTARG_REG ref REG rdx /--* t1457 ref arg0 in rcx +--* t1458 ref arg1 in rdx N005 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} [001339] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 1) [000015] ------------ t15 = LCL_VAR ref V00 this u:1 $100 /--* t15 ref N003 ( 2, 2) [000822] -c---------- t822 = * LEA(b+16) byref /--* t822 byref N004 ( 4, 4) [000016] n---GO------ t16 = * IND ref /--* t16 ref N006 ( 4, 4) [000018] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:1 [001340] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 1, 1) [000019] ------------ t19 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000020] -c---------- t20 = CNS_INT ref null $VN.Null /--* t19 ref +--* t20 ref N003 ( 6, 3) [000021] N----------- t21 = * NE int /--* t21 int N005 ( 6, 3) [000566] DA---------- * STORE_LCL_VAR int V36 tmp22 d:1 [001341] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 1, 1) [001295] ------------ t1295 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1295 ref N003 ( 1, 3) [000576] DA--G------- * STORE_LCL_VAR ref V37 tmp23 d:1 [001342] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 1, 1) [000568] ------------ t568 = LCL_VAR int V36 tmp22 u:1 (last use) N002 ( 1, 1) [000569] -c---------- t569 = CNS_INT int 0 $c0 /--* t568 int +--* t569 int N003 ( 3, 3) [000570] J------N---- * NE void N004 ( 5, 5) [000571] ------------ * JTRUE void ------------ BB07 [033..034), preds={BB06} succs={BB08} [001343] ------------ IL_OFFSET void IL offset: 0x33 N003 ( 2, 10) [000823] H----------- t823 = CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" $46 /--* t823 long N004 ( 4, 12) [000824] #---G------- t824 = * IND ref $106 /--* t824 ref [001459] ----G------- t1459 = * PUTARG_REG ref REG rcx N005 ( 1, 1) [000573] ------------ t573 = LCL_VAR ref V37 tmp23 u:1 (last use) $105 /--* t573 ref [001460] ------------ t1460 = * PUTARG_REG ref REG rdx /--* t1459 ref arg0 in rcx +--* t1460 ref arg1 in rdx N006 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} [001344] ------------ IL_OFFSET void IL offset: 0x41 N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR ref V00 this u:1 $100 /--* t25 ref N003 ( 2, 2) [000828] -c---------- t828 = * LEA(b+24) byref /--* t828 byref N004 ( 4, 4) [000026] n---GO------ t26 = * IND ref /--* t26 ref N006 ( 4, 4) [000028] DA--GO------ * STORE_LCL_VAR ref V05 loc1 d:1 [001345] ------------ IL_OFFSET void IL offset: 0x48 N001 ( 1, 1) [000029] ------------ t29 = LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000030] -c---------- t30 = CNS_INT ref null $VN.Null /--* t29 ref +--* t30 ref N003 ( 3, 3) [000031] J------N---- * EQ void N004 ( 5, 5) [000032] ------------ * JTRUE void ------------ BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} [001346] ------------ IL_OFFSET void IL offset: 0x4b N001 ( 1, 1) [000486] !----------- t486 = LCL_VAR ref V00 this u:1 $100 /--* t486 ref N002 ( 3, 2) [000487] #----O------ t487 = * IND long $2e8 /--* t487 long N004 ( 3, 3) [000489] DA---O------ * STORE_LCL_VAR long V29 tmp15 d:1 N001 ( 1, 1) [000491] ------------ t491 = LCL_VAR long V29 tmp15 u:1 $2e7 /--* t491 long N003 ( 2, 2) [000493] -c---------- t493 = * LEA(b+56) long /--* t493 long N004 ( 4, 4) [000494] #----------- t494 = * IND long $2e9 /--* t494 long N005 ( 7, 6) [000495] #----------- t495 = * IND long $2ea /--* t495 long N007 ( 8, 7) [000497] -c---------- t497 = * LEA(b+64) long /--* t497 long N008 ( 10, 9) [000501] n----------- t501 = * IND long /--* t501 long N010 ( 14, 12) [001266] DA---------- * STORE_LCL_VAR long V68 cse3 d:1 N011 ( 3, 2) [001267] ------------ t1267 = LCL_VAR long V68 cse3 u:1 N013 ( 1, 1) [000504] -c---------- t504 = CNS_INT long 0 $243 /--* t1267 long +--* t504 long N014 ( 19, 16) [000505] J------N---- * EQ void N015 ( 21, 18) [001148] ------------ * JTRUE void ------------ BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} N001 ( 3, 2) [001269] ------------ t1269 = LCL_VAR long V68 cse3 u:1 (last use) /--* t1269 long N003 ( 3, 3) [001150] DA---------- * STORE_LCL_VAR long V31 tmp17 d:3 ------------ BB11 [???..???), preds={BB09} succs={BB12} N003 ( 1, 1) [000490] ------?----- t490 = LCL_VAR long V29 tmp15 u:1 (last use) $2e7 /--* t490 long [001461] ------------ t1461 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000502] H-----?----- t502 = CNS_INT(h) long 0xd1ffab1e global ptr $49 /--* t502 long [001462] ------------ t1462 = * PUTARG_REG long REG rdx /--* t1461 long arg0 in rcx +--* t1462 long arg1 in rdx N005 ( 17, 18) [000503] --C-G-?----- t503 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $308 /--* t503 long N007 ( 17, 18) [001152] DA--G------- * STORE_LCL_VAR long V31 tmp17 d:2 ------------ BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} N001 ( 0, 0) [001247] ------------ t1247 = PHI_ARG long V31 tmp17 u:3 N002 ( 0, 0) [001246] ------------ t1246 = PHI_ARG long V31 tmp17 u:2 $308 /--* t1247 long +--* t1246 long N003 ( 0, 0) [001216] ------------ t1216 = * PHI long /--* t1216 long N005 ( 0, 0) [001217] DA---------- * STORE_LCL_VAR long V31 tmp17 d:1 N004 ( 1, 1) [000484] ------------ t484 = LCL_VAR ref V05 loc1 u:1 /--* t484 ref [001463] ------------ t1463 = * PUTARG_REG ref REG rcx N005 ( 1, 1) [000831] ------------ t831 = LCL_VAR long V31 tmp17 u:1 r11 REG r11 $342 /--* t831 long [001464] ------------ t1464 = * PUTARG_REG long REG r11 N006 ( 1, 1) [000500] ------------ t500 = LCL_VAR ref V01 arg1 u:1 $101 /--* t500 ref [001465] ------------ t1465 = * PUTARG_REG ref REG rdx N007 ( 1, 1) [000521] ------------ t521 = LCL_VAR long V31 tmp17 u:1 (last use) $342 /--* t521 long [001466] Dc---------- t1466 = * IND long REG NA /--* t1463 ref this in rcx +--* t1464 long arg1 in r11 +--* t1465 ref arg2 in rdx +--* t1466 long calli tgt N008 ( 27, 12) [000522] --CXG------- t522 = * CALL ind stub int $1c7 /--* t522 int N010 ( 31, 15) [000524] DA-XG------- * STORE_LCL_VAR int V15 tmp1 d:3 ------------ BB13 [054..061), preds={BB08} succs={BB14} [001347] ------------ IL_OFFSET void IL offset: 0x54 N002 ( 1, 1) [000033] ------------ t33 = LCL_VAR ref V01 arg1 u:1 $101 /--* t33 ref [001467] ------------ t1467 = * PUTARG_REG ref REG rcx N003 ( 1, 1) [000836] ------------ t836 = LCL_VAR ref V01 arg1 u:1 $101 /--* t836 ref N004 ( 3, 2) [000837] #----O------ t837 = * IND long $2e4 /--* t837 long N006 ( 4, 3) [000839] -c---------- t839 = * LEA(b+72) long /--* t839 long N007 ( 6, 5) [000840] #----O------ t840 = * IND long $2e6 /--* t840 long N009 ( 7, 6) [000842] -c---------- t842 = * LEA(b+24) long /--* t842 long N010 ( 9, 8) [000843] nc---O------ t843 = * IND long REG NA /--* t1467 ref this in rcx +--* t843 long control expr N011 ( 30, 18) [000035] --CXGO------ t35 = * CALLV vt-ind int System.Object.GetHashCode $1c5 /--* t35 int N013 ( 34, 21) [000038] DA-XGO------ * STORE_LCL_VAR int V15 tmp1 d:2 ------------ BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} N001 ( 0, 0) [001245] ------------ t1245 = PHI_ARG int V15 tmp1 u:3 $1c7 N002 ( 0, 0) [001244] ------------ t1244 = PHI_ARG int V15 tmp1 u:2 $1c5 /--* t1245 int +--* t1244 int N003 ( 0, 0) [001213] ------------ t1213 = * PHI int /--* t1213 int N005 ( 0, 0) [001214] DA---------- * STORE_LCL_VAR int V15 tmp1 d:1 N001 ( 3, 2) [000040] ------------ t40 = LCL_VAR int V15 tmp1 u:1 (last use) $3c0 /--* t40 int N003 ( 3, 3) [000042] DA---------- * STORE_LCL_VAR int V06 loc2 d:1 [001348] ------------ IL_OFFSET void IL offset: 0x62 N001 ( 1, 1) [000043] ------------ t43 = CNS_INT int 0 $c0 /--* t43 int N003 ( 1, 3) [000045] DA---------- * STORE_LCL_VAR int V07 loc3 d:1 [001349] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000046] ------------ t46 = LCL_VAR ref V00 this u:1 $100 /--* t46 ref N003 ( 2, 2) [000845] -c---------- t845 = * LEA(b+8) byref /--* t845 byref N004 ( 4, 4) [000578] n---GO------ t578 = * IND ref /--* t578 ref N006 ( 4, 4) [000580] DA--GO------ * STORE_LCL_VAR ref V39 tmp25 d:1 [001350] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000582] ------------ t582 = LCL_VAR ref V39 tmp25 u:1 /--* t582 ref [001441] -c---------- t1441 = * LEA(b+8) ref /--* t1441 ref N002 ( 3, 3) [000583] ---X-------- t583 = * IND int /--* t583 int N004 ( 3, 3) [000629] DA-X-------- * STORE_LCL_VAR int V40 tmp26 d:1 [001351] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000584] ------------ t584 = LCL_VAR ref V00 this u:1 $100 /--* t584 ref N003 ( 2, 2) [000847] -c---------- t847 = * LEA(b+48) byref /--* t847 byref N004 ( 4, 4) [000585] n---GO------ t585 = * IND long /--* t585 long N006 ( 4, 4) [000631] DA--GO------ * STORE_LCL_VAR long V41 tmp27 d:1 [001352] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000597] ------------ t597 = LCL_VAR int V40 tmp26 u:1 N002 ( 1, 4) [000598] -c---------- t598 = CNS_INT int 0x7FFFFFFF $ce /--* t597 int +--* t598 int N003 ( 6, 6) [000599] N--------U-- t599 = * LE int /--* t599 int N005 ( 6, 6) [000642] DA---------- * STORE_LCL_VAR int V43 tmp29 d:1 [001353] ------------ IL_OFFSET void IL offset: 0x64 [001354] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [001297] ------------ t1297 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1297 ref N003 ( 1, 3) [000654] DA--G------- * STORE_LCL_VAR ref V45 tmp31 d:1 [001355] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000644] ------------ t644 = LCL_VAR int V43 tmp29 u:1 (last use) N002 ( 1, 1) [000645] -c---------- t645 = CNS_INT int 0 $c0 /--* t644 int +--* t645 int N003 ( 3, 3) [000646] J------N---- * NE void N004 ( 5, 5) [000647] ------------ * JTRUE void ------------ BB15 [064..065), preds={BB14} succs={BB16} [001356] ------------ IL_OFFSET void IL offset: 0x64 N003 ( 1, 1) [000648] ------------ t648 = LCL_VAR ref V45 tmp31 u:1 $105 /--* t648 ref [001468] ------------ t1468 = * PUTARG_REG ref REG rcx N004 ( 1, 1) [000649] ------------ t649 = LCL_VAR ref V45 tmp31 u:1 (last use) $105 /--* t649 ref [001469] ------------ t1469 = * PUTARG_REG ref REG rdx /--* t1468 ref arg0 in rcx +--* t1469 ref arg1 in rdx N005 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} [001357] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000604] ------------ t604 = LCL_VAR long V41 tmp27 u:1 (last use) N002 ( 1, 1) [000047] ------------ t47 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t47 int N003 ( 2, 3) [000605] ---------U-- t605 = * CAST long <- ulong <- uint $310 /--* t604 long +--* t605 long N004 ( 7, 7) [000606] ------------ t606 = * MUL long N005 ( 1, 1) [000607] -c---------- t607 = CNS_INT int 32 $d2 /--* t606 long +--* t607 int N006 ( 9, 9) [000608] ------------ t608 = * RSZ long N007 ( 1, 1) [000610] -c---------- t610 = CNS_INT long 1 $247 /--* t608 long +--* t610 long N008 ( 11, 11) [000611] ------------ t611 = * ADD long N009 ( 1, 1) [000612] ------------ t612 = LCL_VAR int V40 tmp26 u:1 /--* t612 int N010 ( 2, 3) [000613] ---------U-- t613 = * CAST long <- ulong <- uint /--* t611 long +--* t613 long N011 ( 17, 17) [000614] ------------ t614 = * MUL long N012 ( 1, 1) [000615] -c---------- t615 = CNS_INT int 32 $d2 /--* t614 long +--* t615 int N013 ( 19, 19) [000616] ------------ t616 = * RSZ long /--* t616 long N014 ( 20, 21) [000617] ------------ t617 = * CAST int <- uint <- long /--* t617 int N016 ( 20, 21) [000619] DA---------- * STORE_LCL_VAR int V42 tmp28 d:1 [001358] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000621] ------------ t621 = LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000622] ------------ t622 = LCL_VAR int V40 tmp26 u:1 (last use) /--* t621 int +--* t622 int N003 ( 22, 5) [000623] ---X-------- t623 = * UMOD int N004 ( 1, 1) [000620] ------------ t620 = LCL_VAR int V42 tmp28 u:1 /--* t623 int +--* t620 int N005 ( 27, 7) [000624] ---X-------- t624 = * EQ int /--* t624 int N007 ( 27, 7) [000665] DA-X-------- * STORE_LCL_VAR int V46 tmp32 d:1 [001359] ------------ IL_OFFSET void IL offset: 0x64 [001360] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [001299] ------------ t1299 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1299 ref N003 ( 1, 3) [000677] DA--G------- * STORE_LCL_VAR ref V48 tmp34 d:1 [001361] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000667] ------------ t667 = LCL_VAR int V46 tmp32 u:1 (last use) N002 ( 1, 1) [000668] -c---------- t668 = CNS_INT int 0 $c0 /--* t667 int +--* t668 int N003 ( 3, 3) [000669] J------N---- * NE void N004 ( 5, 5) [000670] ------------ * JTRUE void ------------ BB17 [064..065), preds={BB16} succs={BB18} [001362] ------------ IL_OFFSET void IL offset: 0x64 N003 ( 1, 1) [000671] ------------ t671 = LCL_VAR ref V48 tmp34 u:1 $105 /--* t671 ref [001470] ------------ t1470 = * PUTARG_REG ref REG rcx N004 ( 1, 1) [000672] ------------ t672 = LCL_VAR ref V48 tmp34 u:1 (last use) $105 /--* t672 ref [001471] ------------ t1471 = * PUTARG_REG ref REG rdx /--* t1470 ref arg0 in rcx +--* t1471 ref arg1 in rdx N005 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} [001363] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000627] ------------ t627 = LCL_VAR int V42 tmp28 u:1 N002 ( 1, 1) [000581] ------------ t581 = LCL_VAR ref V39 tmp25 u:1 /--* t581 ref [001443] -c---------- t1443 = * LEA(b+8) ref /--* t1443 ref N003 ( 3, 3) [000854] -c-X-------- t854 = * IND int /--* t627 int +--* t854 int N004 ( 8, 11) [000855] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void N005 ( 1, 1) [000852] ------------ t852 = LCL_VAR ref V39 tmp25 u:1 (last use) N006 ( 1, 1) [000853] ------------ t853 = LCL_VAR int V42 tmp28 u:1 (last use) /--* t853 int N007 ( 2, 3) [000856] ------------ t856 = * CAST long <- int /--* t852 ref +--* t856 long N012 ( 5, 6) [000861] -------N---- t861 = * LEA(b+(i*4)+16) byref /--* t861 byref N017 ( 19, 24) [000591] DA-XG------- * STORE_LCL_VAR byref V38 tmp24 d:1 N001 ( 1, 1) [000592] ------------ t592 = LCL_VAR byref V38 tmp24 u:1 (last use) $81 /--* t592 byref N003 ( 5, 4) [000051] DA---------- * STORE_LCL_VAR byref V08 loc4 d:1 [001364] ------------ IL_OFFSET void IL offset: 0x6d N001 ( 1, 1) [000052] ------------ t52 = LCL_VAR byref V08 loc4 u:1 $81 /--* t52 byref N002 ( 3, 2) [000053] *--XG------- t53 = * IND int N003 ( 1, 1) [000054] -c---------- t54 = CNS_INT int -1 $c4 /--* t53 int +--* t54 int N004 ( 5, 4) [000055] ---XG------- t55 = * ADD int /--* t55 int N006 ( 5, 4) [000057] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:1 [001365] ------------ IL_OFFSET void IL offset: 0x74 N001 ( 1, 1) [000058] ------------ t58 = LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000059] -c---------- t59 = CNS_INT ref null $VN.Null /--* t58 ref +--* t59 ref N003 ( 3, 3) [000060] J------N---- * NE void N004 ( 5, 5) [000061] ------------ * JTRUE void ------------ BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} [001366] ------------ IL_OFFSET void IL offset: 0xff N001 ( 1, 1) [000353] !----------- t353 = LCL_VAR ref V00 this u:1 $100 /--* t353 ref N002 ( 3, 2) [000354] #----O------ t354 = * IND long $2e8 /--* t354 long N004 ( 3, 3) [000356] DA---O------ * STORE_LCL_VAR long V24 tmp10 d:1 N001 ( 1, 1) [000358] ------------ t358 = LCL_VAR long V24 tmp10 u:1 $2e7 /--* t358 long N003 ( 2, 2) [000360] -c---------- t360 = * LEA(b+56) long /--* t360 long N004 ( 4, 4) [000361] #----------- t361 = * IND long $2e9 /--* t361 long N005 ( 7, 6) [000362] #----------- t362 = * IND long $2ea /--* t362 long N007 ( 8, 7) [000364] -c---------- t364 = * LEA(b+32) long /--* t364 long N008 ( 10, 9) [000365] n----------- t365 = * IND long /--* t365 long N010 ( 14, 12) [001271] DA---------- * STORE_LCL_VAR long V69 cse4 d:1 N011 ( 3, 2) [001272] ------------ t1272 = LCL_VAR long V69 cse4 u:1 N013 ( 1, 1) [000368] -c---------- t368 = CNS_INT long 0 $243 /--* t1272 long +--* t368 long N014 ( 19, 16) [000369] J------N---- * EQ void N015 ( 21, 18) [001153] ------------ * JTRUE void ------------ BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} N001 ( 3, 2) [001274] ------------ t1274 = LCL_VAR long V69 cse4 u:1 (last use) /--* t1274 long N003 ( 7, 5) [001155] DA---------- * STORE_LCL_VAR long V25 tmp11 d:3 ------------ BB21 [???..???), preds={BB19} succs={BB22} N003 ( 1, 1) [000357] ------?----- t357 = LCL_VAR long V24 tmp10 u:1 (last use) $2e7 /--* t357 long [001472] ------------ t1472 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000366] H-----?----- t366 = CNS_INT(h) long 0xd1ffab1e global ptr $4f /--* t366 long [001473] ------------ t1473 = * PUTARG_REG long REG rdx /--* t1472 long arg0 in rcx +--* t1473 long arg1 in rdx N005 ( 17, 18) [000367] --C-G-?----- t367 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $325 /--* t367 long N007 ( 21, 21) [001157] DA--G------- * STORE_LCL_VAR long V25 tmp11 d:2 ------------ BB22 [???..106), preds={BB20,BB21} succs={BB23} N001 ( 0, 0) [001243] ------------ t1243 = PHI_ARG long V25 tmp11 u:3 N002 ( 0, 0) [001242] ------------ t1242 = PHI_ARG long V25 tmp11 u:2 $325 /--* t1243 long +--* t1242 long N003 ( 0, 0) [001198] ------------ t1198 = * PHI long /--* t1198 long N005 ( 0, 0) [001199] DA---------- * STORE_LCL_VAR long V25 tmp11 d:1 N002 ( 3, 2) [000382] ------------ t382 = LCL_VAR long V25 tmp11 u:1 (last use) $344 /--* t382 long [001474] ------------ t1474 = * PUTARG_REG long REG rcx /--* t1474 long arg0 in rcx N003 ( 17, 8) [000352] --CXG------- t352 = * CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default $223 /--* t352 ref N005 ( 17, 8) [000386] DA-XG------- * STORE_LCL_VAR ref V12 loc8 d:1 ------------ BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} N001 ( 0, 0) [001238] ------------ t1238 = PHI_ARG int V07 loc3 u:6 N002 ( 0, 0) [001235] ------------ t1235 = PHI_ARG int V07 loc3 u:1 $c0 /--* t1238 int +--* t1235 int N003 ( 0, 0) [001177] ------------ t1177 = * PHI int /--* t1177 int N005 ( 0, 0) [001178] DA---------- * STORE_LCL_VAR int V07 loc3 d:5 N001 ( 0, 0) [001239] ------------ t1239 = PHI_ARG int V09 loc5 u:5 N002 ( 0, 0) [001236] ------------ t1236 = PHI_ARG int V09 loc5 u:1 /--* t1239 int +--* t1236 int N003 ( 0, 0) [001174] ------------ t1174 = * PHI int /--* t1174 int N005 ( 0, 0) [001175] DA---------- * STORE_LCL_VAR int V09 loc5 d:4 [001367] ------------ IL_OFFSET void IL offset: 0x106 N001 ( 1, 1) [000388] ------------ t388 = LCL_VAR ref V04 loc0 u:1 /--* t388 ref [001446] -c---------- t1446 = * LEA(b+8) ref /--* t1446 ref N002 ( 3, 3) [000389] ---X-------- t389 = * IND int /--* t389 int N004 ( 3, 3) [001316] DA-X-------- * STORE_LCL_VAR int V76 cse11 N005 ( 1, 1) [001317] ------------ t1317 = LCL_VAR int V76 cse11 N007 ( 1, 1) [000387] ------------ t387 = LCL_VAR int V09 loc5 u:4 $3c2 /--* t1317 int +--* t387 int N008 ( 6, 6) [000390] N--X---N-U-- * LE void N009 ( 8, 8) [000391] ---X-------- * JTRUE void ------------ BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} [001368] ------------ IL_OFFSET void IL offset: 0x110 N001 ( 1, 1) [000869] ------------ t869 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000870] ------------ t870 = LCL_VAR int V09 loc5 u:4 (last use) $3c2 /--* t870 int N003 ( 2, 3) [000873] ------------ t873 = * CAST long <- int $326 N004 ( 1, 1) [000880] -c---------- t880 = CNS_INT long 3 $24b /--* t873 long +--* t880 long N005 ( 7, 7) [000881] ------------ t881 = * MUL long $327 /--* t881 long N007 ( 7, 7) [001276] DA---------- * STORE_LCL_VAR long V70 cse5 d:1 N008 ( 1, 1) [001277] ------------ t1277 = LCL_VAR long V70 cse5 u:1 $327 /--* t869 ref +--* t1277 long N014 ( 11, 11) [000878] -------N---- t878 = * LEA(b+(i*8)+16) byref /--* t878 byref N018 ( 23, 23) [001249] DA--G------- * STORE_LCL_VAR byref V65 cse0 d:1 N019 ( 1, 1) [001250] ------------ t1250 = LCL_VAR byref V65 cse0 u:1 /--* t1250 byref N022 ( 25, 25) [000868] -c---------- t868 = * LEA(b+16) byref /--* t868 byref N023 ( 27, 27) [000396] *c-XG------- t396 = * IND int N024 ( 1, 1) [000397] ------------ t397 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t396 int +--* t397 int N025 ( 29, 29) [000398] N--XG--N-U-- * NE void N026 ( 31, 31) [000399] ---XG------- * JTRUE void ------------ BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} [001369] ------------ IL_OFFSET void IL offset: 0x120 N004 ( 1, 1) [000883] ------------ t883 = LCL_VAR ref V04 loc0 u:1 N005 ( 1, 1) [001279] ------------ t1279 = LCL_VAR long V70 cse5 u:1 (last use) $327 /--* t883 ref +--* t1279 long N010 ( 4, 4) [000892] -c---------- t892 = * LEA(b+(i*8)+16) byref /--* t892 byref N013 ( 12, 11) [000897] *---G--N---- t897 = * IND ref /--* t897 ref [001475] ----G------- t1475 = * PUTARG_REG ref REG rdx N014 ( 1, 1) [000418] ------------ t418 = LCL_VAR ref V12 loc8 u:1 $223 /--* t418 ref [001476] ------------ t1476 = * PUTARG_REG ref REG rcx N015 ( 1, 1) [000424] ------------ t424 = LCL_VAR ref V01 arg1 u:1 $101 /--* t424 ref [001477] ------------ t1477 = * PUTARG_REG ref REG r8 N016 ( 1, 1) [000901] ------------ t901 = LCL_VAR ref V12 loc8 u:1 $223 /--* t901 ref N017 ( 3, 2) [000902] #--X-------- t902 = * IND long $463 /--* t902 long N019 ( 4, 3) [000904] -c---------- t904 = * LEA(b+72) long /--* t904 long N020 ( 6, 5) [000905] #--X-------- t905 = * IND long $465 /--* t905 long N022 ( 7, 6) [000907] -c---------- t907 = * LEA(b+32) long /--* t907 long N023 ( 9, 8) [000908] nc-X-------- t908 = * IND long REG NA /--* t1475 ref arg1 in rdx +--* t1476 ref this in rcx +--* t1477 ref arg2 in r8 +--* t908 long control expr N024 ( 43, 32) [000425] --CXG------- t425 = * CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals $581 N025 ( 1, 1) [000426] -c---------- t426 = CNS_INT int 0 $c0 /--* t425 int +--* t426 int N026 ( 45, 34) [000427] J--XG--N---- * NE void $1bd N027 ( 47, 36) [000428] ---XG------- * JTRUE void ------------ BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} [001370] ------------ IL_OFFSET void IL offset: 0x157 N001 ( 1, 1) [001252] ------------ t1252 = LCL_VAR byref V65 cse0 u:1 (last use) $82 /--* t1252 byref N003 ( 2, 2) [000932] -c---------- t932 = * LEA(b+20) byref /--* t932 byref N004 ( 4, 4) [000404] *--XG------- t404 = * IND int /--* t404 int N006 ( 4, 4) [000406] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:5 [001371] ------------ IL_OFFSET void IL offset: 0x166 N001 ( 1, 1) [000407] ------------ t407 = LCL_VAR int V07 loc3 u:5 (last use) $3c1 N002 ( 1, 1) [000408] -c---------- t408 = CNS_INT int 1 $c1 /--* t407 int +--* t408 int N003 ( 3, 3) [000409] ------------ t409 = * ADD int $605 /--* t409 int N005 ( 3, 3) [000411] DA---------- * STORE_LCL_VAR int V07 loc3 d:6 [001372] ------------ IL_OFFSET void IL offset: 0x16a N001 ( 1, 1) [001321] ------------ t1321 = LCL_VAR int V76 cse11 (last use) N002 ( 1, 1) [000412] ------------ t412 = LCL_VAR int V07 loc3 u:6 $605 /--* t1321 int +--* t412 int N003 ( 3, 3) [000415] N------N-U-- * LT void N004 ( 5, 5) [000416] ------------ * JTRUE void ------------ BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} ------------ BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} [001373] ------------ IL_OFFSET void IL offset: 0x137 N001 ( 2, 2) [000429] ------------ t429 = LCL_VAR ubyte V03 arg3 u:1 $140 N003 ( 1, 1) [000430] -c---------- t430 = CNS_INT ubyte 1 $c1 /--* t429 ubyte +--* t430 ubyte N004 ( 5, 6) [000431] N------N-U-- * NE void $1bf N005 ( 7, 8) [000432] ------------ * JTRUE void ------------ BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} [001374] ------------ IL_OFFSET void IL offset: 0x13b N001 ( 1, 1) [001253] ------------ t1253 = LCL_VAR byref V65 cse0 u:1 (last use) $82 /--* t1253 byref N003 ( 2, 2) [000911] ------------ t911 = * LEA(b+8) byref N005 ( 1, 1) [000479] ------------ t479 = LCL_VAR ref V02 arg2 u:1 (last use) $102 /--* t911 byref +--* t479 ref [001375] -A-XG------- * STOREIND ref ------------ BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} [001376] ------------ IL_OFFSET void IL offset: 0x14b N001 ( 2, 2) [000433] ------------ t433 = LCL_VAR ubyte V03 arg3 u:1 (last use) $140 N003 ( 1, 1) [000434] -c---------- t434 = CNS_INT ubyte 2 $c2 /--* t433 ubyte +--* t434 ubyte N004 ( 5, 6) [000435] N------N-U-- * EQ void $600 N005 ( 7, 8) [000436] ------------ * JTRUE void ------------ BB31 [???..???) (return), preds={BB30,BB41} succs={} N001 ( 1, 1) [000437] ------------ t437 = CNS_INT int 0 $c0 /--* t437 int N002 ( 2, 2) [000811] ------------ * RETURN int $1f3 ------------ BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} N001 ( 0, 0) [001229] ------------ t1229 = PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [001218] ------------ t1218 = PHI_ARG int V07 loc3 u:1 $c0 /--* t1229 int +--* t1218 int N003 ( 0, 0) [001207] ------------ t1207 = * PHI int /--* t1207 int N005 ( 0, 0) [001208] DA---------- * STORE_LCL_VAR int V07 loc3 d:3 N001 ( 0, 0) [001230] ------------ t1230 = PHI_ARG int V09 loc5 u:3 N002 ( 0, 0) [001219] ------------ t1219 = PHI_ARG int V09 loc5 u:1 /--* t1230 int +--* t1219 int N003 ( 0, 0) [001204] ------------ t1204 = * PHI int /--* t1204 int N005 ( 0, 0) [001205] DA---------- * STORE_LCL_VAR int V09 loc5 d:2 [001377] ------------ IL_OFFSET void IL offset: 0x177 N001 ( 1, 1) [000063] ------------ t63 = LCL_VAR ref V04 loc0 u:1 /--* t63 ref [001448] -c---------- t1448 = * LEA(b+8) ref /--* t1448 ref N002 ( 3, 3) [000064] ---X-------- t64 = * IND int /--* t64 int N004 ( 3, 3) [001323] DA-X-------- * STORE_LCL_VAR int V76 cse11 N005 ( 1, 1) [001324] ------------ t1324 = LCL_VAR int V76 cse11 N007 ( 1, 1) [000062] ------------ t62 = LCL_VAR int V09 loc5 u:2 $3c4 /--* t1324 int +--* t62 int N008 ( 6, 6) [000065] N--X---N-U-- * LE void N009 ( 8, 8) [000066] ---X-------- * JTRUE void ------------ BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} [001378] ------------ IL_OFFSET void IL offset: 0x17e N001 ( 1, 1) [000949] ------------ t949 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000950] ------------ t950 = LCL_VAR int V09 loc5 u:2 (last use) $3c4 /--* t950 int N003 ( 2, 3) [000953] ------------ t953 = * CAST long <- int $6e1 N004 ( 1, 1) [000960] -c---------- t960 = CNS_INT long 3 $24b /--* t953 long +--* t960 long N005 ( 7, 7) [000961] ------------ t961 = * MUL long $6e2 /--* t961 long N007 ( 7, 7) [001281] DA---------- * STORE_LCL_VAR long V71 cse6 d:1 N008 ( 1, 1) [001282] ------------ t1282 = LCL_VAR long V71 cse6 u:1 $6e2 /--* t949 ref +--* t1282 long N014 ( 11, 11) [000958] -------N---- t958 = * LEA(b+(i*8)+16) byref /--* t958 byref N018 ( 23, 23) [001255] DA--G------- * STORE_LCL_VAR byref V66 cse1 d:1 N019 ( 1, 1) [001256] ------------ t1256 = LCL_VAR byref V66 cse1 u:1 /--* t1256 byref N022 ( 25, 25) [000948] -c---------- t948 = * LEA(b+16) byref /--* t948 byref N023 ( 27, 27) [000212] *c-XG------- t212 = * IND int N024 ( 1, 1) [000213] ------------ t213 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t212 int +--* t213 int N025 ( 29, 29) [000214] N--XG--N-U-- * NE void N026 ( 31, 31) [000215] ---XG------- * JTRUE void ------------ BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} [001379] ------------ IL_OFFSET void IL offset: 0x18e N001 ( 1, 1) [000963] ------------ t963 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [001284] ------------ t1284 = LCL_VAR long V71 cse6 u:1 (last use) $6e2 /--* t963 ref +--* t1284 long N007 ( 4, 4) [000972] -c---------- t972 = * LEA(b+(i*8)+16) byref /--* t972 byref N010 ( 12, 11) [000977] *---G--N---- t977 = * IND ref /--* t977 ref N012 ( 12, 11) [000246] DA--G------- * STORE_LCL_VAR ref V17 tmp3 d:1 [001380] ------------ IL_OFFSET void IL offset: 0x18e N001 ( 1, 1) [000241] !----------- t241 = LCL_VAR ref V00 this u:1 $100 /--* t241 ref N002 ( 3, 2) [000242] #----O------ t242 = * IND long $2e8 /--* t242 long N004 ( 3, 3) [000244] DA---O------ * STORE_LCL_VAR long V16 tmp2 d:1 N001 ( 1, 1) [000249] ------------ t249 = LCL_VAR long V16 tmp2 u:1 $2e7 /--* t249 long N003 ( 2, 2) [000251] -c---------- t251 = * LEA(b+56) long /--* t251 long N004 ( 4, 4) [000252] #----------- t252 = * IND long $2e9 /--* t252 long N005 ( 7, 6) [000253] #----------- t253 = * IND long $2ea /--* t253 long N007 ( 8, 7) [000255] -c---------- t255 = * LEA(b+48) long /--* t255 long N008 ( 10, 9) [000259] n----------- t259 = * IND long /--* t259 long N010 ( 10, 9) [001261] DA---------- * STORE_LCL_VAR long V67 cse2 d:1 N011 ( 1, 1) [001262] ------------ t1262 = LCL_VAR long V67 cse2 u:1 N013 ( 1, 1) [000262] -c---------- t262 = CNS_INT long 0 $243 /--* t1262 long +--* t262 long N014 ( 13, 12) [000263] J------N---- * EQ void N015 ( 15, 14) [001163] ------------ * JTRUE void ------------ BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} N001 ( 1, 1) [001264] ------------ t1264 = LCL_VAR long V67 cse2 u:1 (last use) /--* t1264 long N003 ( 1, 3) [001165] DA---------- * STORE_LCL_VAR long V19 tmp5 d:3 ------------ BB36 [???..???), preds={BB34} succs={BB37} N003 ( 1, 1) [000248] ------?----- t248 = LCL_VAR long V16 tmp2 u:1 (last use) $2e7 /--* t248 long [001478] ------------ t1478 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000260] H-----?----- t260 = CNS_INT(h) long 0xd1ffab1e global ptr $63 /--* t260 long [001479] ------------ t1479 = * PUTARG_REG long REG rdx /--* t1478 long arg0 in rcx +--* t1479 long arg1 in rdx N005 ( 17, 18) [000261] --C-G-?----- t261 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $6e7 /--* t261 long N007 ( 17, 18) [001167] DA--G------- * STORE_LCL_VAR long V19 tmp5 d:2 ------------ BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} N001 ( 0, 0) [001234] ------------ t1234 = PHI_ARG long V19 tmp5 u:3 N002 ( 0, 0) [001233] ------------ t1233 = PHI_ARG long V19 tmp5 u:2 $6e7 /--* t1234 long +--* t1233 long N003 ( 0, 0) [001210] ------------ t1210 = * PHI long /--* t1210 long N005 ( 0, 0) [001211] DA---------- * STORE_LCL_VAR long V19 tmp5 d:1 N005 ( 1, 1) [000234] ------------ t234 = LCL_VAR ref V05 loc1 u:1 /--* t234 ref [001480] ------------ t1480 = * PUTARG_REG ref REG rcx N006 ( 1, 1) [000980] ------------ t980 = LCL_VAR long V19 tmp5 u:1 r11 REG r11 $349 /--* t980 long [001481] ------------ t1481 = * PUTARG_REG long REG r11 N007 ( 1, 1) [000247] ------------ t247 = LCL_VAR ref V17 tmp3 u:1 (last use) /--* t247 ref [001482] ------------ t1482 = * PUTARG_REG ref REG rdx N008 ( 1, 1) [000258] ------------ t258 = LCL_VAR ref V01 arg1 u:1 $101 /--* t258 ref [001483] ------------ t1483 = * PUTARG_REG ref REG r8 N009 ( 1, 1) [000279] ------------ t279 = LCL_VAR long V19 tmp5 u:1 (last use) $349 /--* t279 long [001484] Dc---------- t1484 = * IND long REG NA /--* t1480 ref this in rcx +--* t1481 long arg1 in r11 +--* t1482 ref arg2 in rdx +--* t1483 ref arg3 in r8 +--* t1484 long calli tgt N010 ( 28, 14) [000280] --CXG------- t280 = * CALL ind stub int $1ef N011 ( 1, 1) [000281] -c---------- t281 = CNS_INT int 0 $c0 /--* t280 int +--* t281 int N012 ( 30, 16) [000282] J--XG--N---- * EQ void $817 N013 ( 32, 18) [000283] ---XG------- * JTRUE void ------------ BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} [001381] ------------ IL_OFFSET void IL offset: 0x1a4 N001 ( 2, 2) [000284] ------------ t284 = LCL_VAR ubyte V03 arg3 u:1 $140 N003 ( 1, 1) [000285] -c---------- t285 = CNS_INT ubyte 1 $c1 /--* t284 ubyte +--* t285 ubyte N004 ( 5, 6) [000286] N------N-U-- * NE void $1bf N005 ( 7, 8) [000287] ------------ * JTRUE void ------------ BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} [001382] ------------ IL_OFFSET void IL offset: 0x1a8 N001 ( 1, 1) [001258] ------------ t1258 = LCL_VAR byref V66 cse1 u:1 (last use) $91 /--* t1258 byref N003 ( 2, 2) [000987] ------------ t987 = * LEA(b+8) byref N005 ( 1, 1) [000334] ------------ t334 = LCL_VAR ref V02 arg2 u:1 (last use) $102 /--* t987 byref +--* t334 ref [001383] -A-XG------- * STOREIND ref ------------ BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} [001384] ------------ IL_OFFSET void IL offset: 0x1b8 N001 ( 2, 2) [000288] ------------ t288 = LCL_VAR ubyte V03 arg3 u:1 (last use) $140 N003 ( 1, 1) [000289] -c---------- t289 = CNS_INT ubyte 2 $c2 /--* t288 ubyte +--* t289 ubyte N004 ( 5, 6) [000290] N------N-U-- * EQ void $600 N005 ( 7, 8) [000291] ------------ * JTRUE void ------------ BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} ------------ BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} [001385] ------------ IL_OFFSET void IL offset: 0x1c4 N001 ( 1, 1) [001259] ------------ t1259 = LCL_VAR byref V66 cse1 u:1 (last use) $91 /--* t1259 byref N003 ( 2, 2) [001009] -c---------- t1009 = * LEA(b+20) byref /--* t1009 byref N004 ( 4, 4) [000220] *--XG------- t220 = * IND int /--* t220 int N006 ( 4, 4) [000222] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:3 [001386] ------------ IL_OFFSET void IL offset: 0x1d3 N001 ( 1, 1) [000223] ------------ t223 = LCL_VAR int V07 loc3 u:3 (last use) $3c3 N002 ( 1, 1) [000224] -c---------- t224 = CNS_INT int 1 $c1 /--* t223 int +--* t224 int N003 ( 3, 3) [000225] ------------ t225 = * ADD int $81a /--* t225 int N005 ( 3, 3) [000227] DA---------- * STORE_LCL_VAR int V07 loc3 d:4 [001387] ------------ IL_OFFSET void IL offset: 0x1d7 N001 ( 1, 1) [001328] ------------ t1328 = LCL_VAR int V76 cse11 (last use) N002 ( 1, 1) [000228] ------------ t228 = LCL_VAR int V07 loc3 u:4 $81a /--* t1328 int +--* t228 int N003 ( 3, 3) [000231] N------N-U-- * LT void N004 ( 5, 5) [000232] ------------ * JTRUE void ------------ BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} ------------ BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} N001 ( 0, 0) [001237] ------------ t1237 = PHI_ARG int V07 loc3 u:5 $3c1 N002 ( 0, 0) [001228] ------------ t1228 = PHI_ARG int V07 loc3 u:3 $3c3 /--* t1237 int +--* t1228 int N003 ( 0, 0) [001180] ------------ t1180 = * PHI int /--* t1180 int N005 ( 0, 0) [001181] DA---------- * STORE_LCL_VAR int V07 loc3 d:2 [001388] ------------ IL_OFFSET void IL offset: 0x1e4 N001 ( 1, 1) [000067] ------------ t67 = LCL_VAR ref V00 this u:1 $100 /--* t67 ref N003 ( 2, 2) [001025] -c---------- t1025 = * LEA(b+64) byref /--* t1025 byref N004 ( 4, 4) [000068] nc--GO------ t68 = * IND int N005 ( 1, 1) [000069] -c---------- t69 = CNS_INT int 0 $c0 /--* t68 int +--* t69 int N006 ( 6, 6) [000070] J---GO-N---- * LE void N007 ( 8, 8) [000071] ----GO------ * JTRUE void ------------ BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} [001389] ------------ IL_OFFSET void IL offset: 0x1ed N001 ( 1, 1) [000171] ------------ t171 = LCL_VAR ref V00 this u:1 $100 /--* t171 ref N003 ( 2, 2) [001027] -c---------- t1027 = * LEA(b+60) byref /--* t1027 byref N004 ( 4, 4) [000172] n---GO------ t172 = * IND int /--* t172 int N006 ( 8, 7) [001306] DA--GO------ * STORE_LCL_VAR int V74 cse9 d:1 N007 ( 3, 2) [001307] ------------ t1307 = LCL_VAR int V74 cse9 u:1 /--* t1307 int N010 ( 15, 12) [000174] DA--GO------ * STORE_LCL_VAR int V10 loc6 d:3 [001390] ------------ IL_OFFSET void IL offset: 0x1f5 N001 ( 3, 2) [001309] ------------ t1309 = LCL_VAR int V74 cse9 u:1 (last use) /--* t1309 int N003 ( 3, 3) [001032] DA--G------- * STORE_LCL_VAR int V62 tmp48 d:1 N004 ( 1, 1) [001033] ------------ t1033 = LCL_VAR int V62 tmp48 u:1 N005 ( 1, 1) [001329] ------------ t1329 = LCL_VAR int V76 cse11 /--* t1033 int +--* t1329 int N006 ( 6, 9) [001036] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void N007 ( 1, 1) [001030] ------------ t1030 = LCL_VAR ref V04 loc0 u:1 N008 ( 1, 1) [001034] ------------ t1034 = LCL_VAR int V62 tmp48 u:1 (last use) /--* t1034 int N009 ( 2, 3) [001037] ------------ t1037 = * CAST long <- int N010 ( 1, 1) [001047] -c---------- t1047 = CNS_INT long 3 $24b /--* t1037 long +--* t1047 long N011 ( 7, 7) [001048] ------------ t1048 = * MUL long /--* t1030 ref +--* t1048 long N022 ( 31, 34) [001029] -c---------- t1029 = * LEA(b+(i*8)+36) byref /--* t1029 byref N023 ( 33, 36) [000181] *--XG------- t181 = * IND int /--* t181 int N024 ( 34, 37) [001050] ---XG------- t1050 = * NEG int N025 ( 1, 1) [000175] -c---------- t175 = CNS_INT int -3 $e1 /--* t1050 int +--* t175 int N026 ( 36, 39) [000182] ---XG------- t182 = * ADD int N027 ( 1, 1) [000183] -c---------- t183 = CNS_INT int -1 $c4 /--* t182 int +--* t183 int N028 ( 41, 41) [000184] ---XG------- t184 = * GE int /--* t184 int N030 ( 45, 44) [000688] DA-XG------- * STORE_LCL_VAR int V49 tmp35 d:1 [001391] ------------ IL_OFFSET void IL offset: 0x1f5 N001 ( 1, 1) [001300] ------------ t1300 = LCL_VAR ref V73 cse8 u:1 (last use) $105 /--* t1300 ref N003 ( 5, 4) [000698] DA--G------- * STORE_LCL_VAR ref V50 tmp36 d:1 [001392] ------------ IL_OFFSET void IL offset: 0x1f5 N001 ( 3, 2) [000690] ------------ t690 = LCL_VAR int V49 tmp35 u:1 (last use) N002 ( 1, 1) [000691] -c---------- t691 = CNS_INT int 0 $c0 /--* t690 int +--* t691 int N003 ( 5, 4) [000692] J------N---- * NE void N004 ( 7, 6) [000693] ------------ * JTRUE void ------------ BB46 [1F5..1F6), preds={BB45} succs={BB47} [001393] ------------ IL_OFFSET void IL offset: 0x1f5 N003 ( 2, 10) [001051] H----------- t1051 = CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" $5e /--* t1051 long N004 ( 4, 12) [001052] #---G------- t1052 = * IND ref $114 /--* t1052 ref [001485] ----G------- t1485 = * PUTARG_REG ref REG rcx N005 ( 3, 2) [000695] ------------ t695 = LCL_VAR ref V50 tmp36 u:1 (last use) $105 /--* t695 ref [001486] ------------ t1486 = * PUTARG_REG ref REG rdx /--* t1485 ref arg0 in rcx +--* t1486 ref arg1 in rdx N006 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} [001394] ------------ IL_OFFSET void IL offset: 0x219 N001 ( 1, 1) [000190] ------------ t190 = LCL_VAR ref V00 this u:1 $100 /--* t190 ref N003 ( 2, 2) [001056] -c---------- t1056 = * LEA(b+60) byref N005 ( 1, 1) [000193] ------------ t193 = LCL_VAR ref V00 this u:1 $100 /--* t193 ref N007 ( 2, 2) [001075] -c---------- t1075 = * LEA(b+60) byref /--* t1075 byref N008 ( 4, 4) [000194] n---GO------ t194 = * IND int /--* t194 int N010 ( 4, 4) [001061] DA--GO------ * STORE_LCL_VAR int V63 tmp49 d:1 N011 ( 1, 1) [001062] ------------ t1062 = LCL_VAR int V63 tmp49 u:1 N012 ( 1, 1) [001330] ------------ t1330 = LCL_VAR int V76 cse11 (last use) /--* t1062 int +--* t1330 int N013 ( 6, 9) [001065] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void N014 ( 1, 1) [001059] ------------ t1059 = LCL_VAR ref V04 loc0 u:1 N015 ( 1, 1) [001063] ------------ t1063 = LCL_VAR int V63 tmp49 u:1 (last use) /--* t1063 int N016 ( 2, 3) [001066] ------------ t1066 = * CAST long <- int N017 ( 1, 1) [001076] -c---------- t1076 = CNS_INT long 3 $24b /--* t1066 long +--* t1076 long N018 ( 7, 7) [001077] ------------ t1077 = * MUL long /--* t1059 ref +--* t1077 long N029 ( 32, 35) [001058] -c---------- t1058 = * LEA(b+(i*8)+36) byref /--* t1058 byref N030 ( 34, 37) [000197] *--XGO------ t197 = * IND int /--* t197 int N031 ( 35, 38) [001079] ---XGO------ t1079 = * NEG int N032 ( 1, 1) [000191] -c---------- t191 = CNS_INT int -3 $e1 /--* t1079 int +--* t191 int N033 ( 37, 40) [000198] ---XGO------ t198 = * ADD int /--* t1056 byref +--* t198 int [001395] -A-XGO------ * STOREIND int [001396] ------------ IL_OFFSET void IL offset: 0x233 N001 ( 1, 1) [000202] -c---------- t202 = LCL_VAR ref V00 this u:1 $100 /--* t202 ref N003 ( 2, 2) [001083] -c---------- t1083 = * LEA(b+64) byref /--* t1083 byref N004 ( 4, 4) [000203] nc--GO------ t203 = * IND int N005 ( 1, 1) [000204] -c---------- t204 = CNS_INT int -1 $c4 /--* t203 int +--* t204 int N006 ( 6, 6) [000205] -c--GO------ t205 = * ADD int N007 ( 1, 1) [000201] ------------ t201 = LCL_VAR ref V00 this u:1 $100 /--* t201 ref N009 ( 2, 2) [001081] -c---------- t1081 = * LEA(b+64) byref /--* t1081 byref +--* t205 int [001397] -A--GO------ * STOREIND int ------------ BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} [001398] ------------ IL_OFFSET void IL offset: 0x243 N001 ( 1, 1) [000072] ------------ t72 = LCL_VAR ref V00 this u:1 $100 /--* t72 ref N003 ( 2, 2) [001085] -c---------- t1085 = * LEA(b+56) byref /--* t1085 byref N004 ( 4, 4) [000073] n---GO------ t73 = * IND int /--* t73 int N006 ( 8, 7) [001311] DA--GO------ * STORE_LCL_VAR int V75 cse10 d:1 N007 ( 3, 2) [001312] ------------ t1312 = LCL_VAR int V75 cse10 u:1 /--* t1312 int N010 ( 15, 12) [000075] DA--GO------ * STORE_LCL_VAR int V13 loc9 d:1 [001399] ------------ IL_OFFSET void IL offset: 0x24b N001 ( 1, 1) [001331] ------------ t1331 = LCL_VAR int V76 cse11 (last use) N002 ( 3, 2) [000076] ------------ t76 = LCL_VAR int V13 loc9 u:1 /--* t1331 int +--* t76 int N003 ( 5, 4) [000079] N------N-U-- * NE void N004 ( 7, 6) [000080] ------------ * JTRUE void ------------ BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} [001400] ------------ IL_OFFSET void IL offset: 0x252 N003 ( 3, 2) [001314] ------------ t1314 = LCL_VAR int V75 cse10 u:1 (last use) /--* t1314 int [001487] ------------ t1487 = * PUTARG_REG int REG rcx /--* t1487 int arg0 in rcx N004 ( 17, 8) [000702] --CXG------- t702 = * CALL int System.Collections.HashHelpers.ExpandPrime $1d7 /--* t702 int N006 ( 21, 11) [001090] DA-XG-----L- * STORE_LCL_VAR int V64 tmp50 d:1 N008 ( 3, 2) [001091] ------------ t1091 = LCL_VAR int V64 tmp50 u:1 (last use) $1d7 /--* t1091 int [001488] ------------ t1488 = * PUTARG_REG int REG rdx N009 ( 1, 1) [000163] ------------ t163 = LCL_VAR ref V00 this u:1 $100 /--* t163 ref [001489] ------------ t1489 = * PUTARG_REG ref REG rcx N010 ( 1, 1) [000704] ------------ t704 = CNS_INT int 0 $c0 /--* t704 int [001490] ------------ t1490 = * PUTARG_REG int REG r8 /--* t1488 int arg1 in rdx +--* t1489 ref this in rcx +--* t1490 int arg2 in r8 N011 ( 43, 24) [000705] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void [001401] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [000165] ------------ t165 = LCL_VAR ref V00 this u:1 $100 /--* t165 ref N003 ( 2, 2) [001095] -c---------- t1095 = * LEA(b+8) byref /--* t1095 byref N004 ( 4, 4) [000709] n---GO------ t709 = * IND ref /--* t709 ref N006 ( 8, 7) [000711] DA--GO------ * STORE_LCL_VAR ref V52 tmp38 d:1 [001402] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000713] ------------ t713 = LCL_VAR ref V52 tmp38 u:1 /--* t713 ref [001450] -c---------- t1450 = * LEA(b+8) ref /--* t1450 ref N002 ( 5, 4) [000714] ---X-------- t714 = * IND int /--* t714 int N004 ( 9, 7) [001286] DA-X-------- * STORE_LCL_VAR int V72 cse7 d:1 N005 ( 3, 2) [001287] ------------ t1287 = LCL_VAR int V72 cse7 u:1 /--* t1287 int N008 ( 12, 9) [000760] DA-X-------- * STORE_LCL_VAR int V53 tmp39 d:1 [001403] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [000715] ------------ t715 = LCL_VAR ref V00 this u:1 $100 /--* t715 ref N003 ( 2, 2) [001097] -c---------- t1097 = * LEA(b+48) byref /--* t1097 byref N004 ( 4, 4) [000716] n---GO------ t716 = * IND long /--* t716 long N006 ( 8, 7) [000762] DA--GO------ * STORE_LCL_VAR long V54 tmp40 d:1 [001404] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [000728] ------------ t728 = LCL_VAR int V53 tmp39 u:1 N002 ( 1, 4) [000729] -c---------- t729 = CNS_INT int 0x7FFFFFFF $ce /--* t728 int +--* t729 int N003 ( 6, 6) [000730] N--------U-- t730 = * LE int /--* t730 int N005 ( 10, 9) [000773] DA---------- * STORE_LCL_VAR int V56 tmp42 d:1 [001405] ------------ IL_OFFSET void IL offset: 0x258 [001406] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [001302] ------------ t1302 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1302 ref N003 ( 5, 4) [000785] DA--G------- * STORE_LCL_VAR ref V58 tmp44 d:1 [001407] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000775] ------------ t775 = LCL_VAR int V56 tmp42 u:1 (last use) N002 ( 1, 1) [000776] -c---------- t776 = CNS_INT int 0 $c0 /--* t775 int +--* t776 int N003 ( 5, 4) [000777] J------N---- * NE void N004 ( 7, 6) [000778] ------------ * JTRUE void ------------ BB50 [258..259), preds={BB49} succs={BB51} [001408] ------------ IL_OFFSET void IL offset: 0x258 N003 ( 3, 2) [000779] ------------ t779 = LCL_VAR ref V58 tmp44 u:1 $105 /--* t779 ref [001491] ------------ t1491 = * PUTARG_REG ref REG rcx N004 ( 3, 2) [000780] ------------ t780 = LCL_VAR ref V58 tmp44 u:1 (last use) $105 /--* t780 ref [001492] ------------ t1492 = * PUTARG_REG ref REG rdx /--* t1491 ref arg0 in rcx +--* t1492 ref arg1 in rdx N005 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} [001409] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000735] ------------ t735 = LCL_VAR long V54 tmp40 u:1 (last use) N002 ( 1, 1) [000166] ------------ t166 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t166 int N003 ( 2, 3) [000736] ---------U-- t736 = * CAST long <- ulong <- uint $310 /--* t735 long +--* t736 long N004 ( 9, 8) [000737] ------------ t737 = * MUL long N005 ( 1, 1) [000738] -c---------- t738 = CNS_INT int 32 $d2 /--* t737 long +--* t738 int N006 ( 11, 10) [000739] ------------ t739 = * RSZ long N007 ( 1, 1) [000741] -c---------- t741 = CNS_INT long 1 $247 /--* t739 long +--* t741 long N008 ( 13, 12) [000742] ------------ t742 = * ADD long N009 ( 1, 1) [000743] ------------ t743 = LCL_VAR int V53 tmp39 u:1 /--* t743 int N010 ( 2, 3) [000744] ---------U-- t744 = * CAST long <- ulong <- uint /--* t742 long +--* t744 long N011 ( 19, 18) [000745] ------------ t745 = * MUL long N012 ( 1, 1) [000746] -c---------- t746 = CNS_INT int 32 $d2 /--* t745 long +--* t746 int N013 ( 21, 20) [000747] ------------ t747 = * RSZ long /--* t747 long N014 ( 22, 22) [000748] ------------ t748 = * CAST int <- uint <- long /--* t748 int N016 ( 26, 25) [000750] DA---------- * STORE_LCL_VAR int V55 tmp41 d:1 [001410] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [000752] ------------ t752 = LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000753] ------------ t753 = LCL_VAR int V53 tmp39 u:1 (last use) /--* t752 int +--* t753 int N003 ( 22, 5) [000754] ---X-------- t754 = * UMOD int N004 ( 3, 2) [000751] ------------ t751 = LCL_VAR int V55 tmp41 u:1 /--* t754 int +--* t751 int N005 ( 29, 8) [000755] ---X-------- t755 = * EQ int /--* t755 int N007 ( 33, 11) [000796] DA-X-------- * STORE_LCL_VAR int V59 tmp45 d:1 [001411] ------------ IL_OFFSET void IL offset: 0x258 [001412] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [001304] ------------ t1304 = LCL_VAR ref V73 cse8 u:1 (last use) $105 /--* t1304 ref N003 ( 5, 4) [000808] DA--G------- * STORE_LCL_VAR ref V61 tmp47 d:1 [001413] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000798] ------------ t798 = LCL_VAR int V59 tmp45 u:1 (last use) N002 ( 1, 1) [000799] -c---------- t799 = CNS_INT int 0 $c0 /--* t798 int +--* t799 int N003 ( 5, 4) [000800] J------N---- * NE void N004 ( 7, 6) [000801] ------------ * JTRUE void ------------ BB52 [258..259), preds={BB51} succs={BB53} [001414] ------------ IL_OFFSET void IL offset: 0x258 N003 ( 3, 2) [000802] ------------ t802 = LCL_VAR ref V61 tmp47 u:1 $105 /--* t802 ref [001493] ------------ t1493 = * PUTARG_REG ref REG rcx N004 ( 3, 2) [000803] ------------ t803 = LCL_VAR ref V61 tmp47 u:1 (last use) $105 /--* t803 ref [001494] ------------ t1494 = * PUTARG_REG ref REG rdx /--* t1493 ref arg0 in rcx +--* t1494 ref arg1 in rdx N005 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB53 [258..259), preds={BB51,BB52} succs={BB54} [001415] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000758] ------------ t758 = LCL_VAR int V55 tmp41 u:1 N002 ( 3, 2) [001289] ------------ t1289 = LCL_VAR int V72 cse7 u:1 (last use) /--* t758 int +--* t1289 int N003 ( 10, 11) [001105] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void N004 ( 3, 2) [001102] ------------ t1102 = LCL_VAR ref V52 tmp38 u:1 (last use) N005 ( 3, 2) [001103] ------------ t1103 = LCL_VAR int V55 tmp41 u:1 (last use) /--* t1103 int N006 ( 4, 4) [001106] ------------ t1106 = * CAST long <- int /--* t1102 ref +--* t1106 long N011 ( 9, 8) [001111] -------N---- t1111 = * LEA(b+(i*4)+16) byref /--* t1111 byref N016 ( 33, 31) [000722] DA-XG------- * STORE_LCL_VAR byref V51 tmp37 d:1 N001 ( 3, 2) [000723] ------------ t723 = LCL_VAR byref V51 tmp37 u:1 (last use) $87 /--* t723 byref N003 ( 7, 5) [000170] DA---------- * STORE_LCL_VAR byref V08 loc4 d:4 ------------ BB54 [261..276), preds={BB48,BB53} succs={BB55} N001 ( 0, 0) [001224] ------------ t1224 = PHI_ARG byref V08 loc4 u:4 $87 N002 ( 0, 0) [001220] ------------ t1220 = PHI_ARG byref V08 loc4 u:1 $81 /--* t1224 byref +--* t1220 byref N003 ( 0, 0) [001192] ------------ t1192 = * PHI byref /--* t1192 byref N005 ( 0, 0) [001193] DA---------- * STORE_LCL_VAR byref V08 loc4 d:3 [001416] ------------ IL_OFFSET void IL offset: 0x261 N001 ( 3, 2) [000081] ------------ t81 = LCL_VAR int V13 loc9 u:1 (last use) /--* t81 int N003 ( 7, 5) [000083] DA---------- * STORE_LCL_VAR int V10 loc6 d:2 [001417] ------------ IL_OFFSET void IL offset: 0x265 N001 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V10 loc6 u:2 N002 ( 1, 1) [000086] -c---------- t86 = CNS_INT int 1 $c1 /--* t85 int +--* t86 int N003 ( 5, 4) [000087] ------------ t87 = * ADD int N004 ( 1, 1) [000084] ------------ t84 = LCL_VAR ref V00 this u:1 $100 /--* t84 ref N006 ( 2, 2) [001115] -c---------- t1115 = * LEA(b+56) byref /--* t1115 byref +--* t87 int [001418] -A--GO------ * STOREIND int [001419] ------------ IL_OFFSET void IL offset: 0x26f N001 ( 1, 1) [000090] ------------ t90 = LCL_VAR ref V00 this u:1 $100 /--* t90 ref N003 ( 2, 2) [001117] -c---------- t1117 = * LEA(b+16) byref /--* t1117 byref N004 ( 4, 4) [000091] n---GO------ t91 = * IND ref /--* t91 ref N006 ( 4, 4) [000093] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:3 ------------ BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} N001 ( 0, 0) [001225] ------------ t1225 = PHI_ARG byref V08 loc4 u:1 $81 N002 ( 0, 0) [001221] ------------ t1221 = PHI_ARG byref V08 loc4 u:3 $780 /--* t1225 byref +--* t1221 byref N003 ( 0, 0) [001195] ------------ t1195 = * PHI byref /--* t1195 byref N005 ( 0, 0) [001196] DA---------- * STORE_LCL_VAR byref V08 loc4 d:2 N001 ( 0, 0) [001226] ------------ t1226 = PHI_ARG ref V04 loc0 u:1 N002 ( 0, 0) [001222] ------------ t1222 = PHI_ARG ref V04 loc0 u:3 /--* t1226 ref +--* t1222 ref N003 ( 0, 0) [001189] ------------ t1189 = * PHI ref /--* t1189 ref N005 ( 0, 0) [001190] DA---------- * STORE_LCL_VAR ref V04 loc0 d:2 N001 ( 0, 0) [001227] ------------ t1227 = PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [001223] ------------ t1223 = PHI_ARG int V10 loc6 u:2 /--* t1227 int +--* t1223 int N003 ( 0, 0) [001186] ------------ t1186 = * PHI int /--* t1186 int N005 ( 0, 0) [001187] DA---------- * STORE_LCL_VAR int V10 loc6 d:1 [001420] ------------ IL_OFFSET void IL offset: 0x276 N001 ( 3, 2) [000095] ------------ t95 = LCL_VAR int V10 loc6 u:1 $3cc N002 ( 1, 1) [000094] ------------ t94 = LCL_VAR ref V04 loc0 u:2 $684 /--* t94 ref [001452] -c---------- t1452 = * LEA(b+8) ref /--* t1452 ref N003 ( 3, 3) [001120] -c-X-------- t1120 = * IND int $73d /--* t95 int +--* t1120 int N004 ( 10, 12) [001121] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void $7cd N005 ( 1, 1) [001118] ------------ t1118 = LCL_VAR ref V04 loc0 u:2 $684 N006 ( 3, 2) [001119] ------------ t1119 = LCL_VAR int V10 loc6 u:1 $3cc /--* t1119 int N007 ( 4, 4) [001122] ------------ t1122 = * CAST long <- int $6dc N008 ( 1, 1) [001129] -c---------- t1129 = CNS_INT long 3 $24b /--* t1122 long +--* t1129 long N009 ( 9, 8) [001130] ------------ t1130 = * MUL long $6dd /--* t1118 ref +--* t1130 long N014 ( 12, 11) [001127] -------N---- t1127 = * LEA(b+(i*8)+16) byref /--* t1127 byref N019 ( 39, 38) [000099] DA-XG------- * STORE_LCL_VAR byref V11 loc7 d:1 [001421] ------------ IL_OFFSET void IL offset: 0x280 N001 ( 3, 2) [000100] ------------ t100 = LCL_VAR byref V11 loc7 u:1 $8c /--* t100 byref N003 ( 4, 3) [001133] -c---------- t1133 = * LEA(b+16) byref N005 ( 1, 1) [000101] ------------ t101 = LCL_VAR int V06 loc2 u:1 (last use) $3c0 /--* t1133 byref +--* t101 int [001422] -A-XG------- * STOREIND int [001423] ------------ IL_OFFSET void IL offset: 0x288 N001 ( 3, 2) [000105] ------------ t105 = LCL_VAR byref V08 loc4 u:2 $781 /--* t105 byref N002 ( 6, 4) [000106] *--XG------- t106 = * IND int N003 ( 1, 1) [000107] -c---------- t107 = CNS_INT int -1 $c4 /--* t106 int +--* t107 int N004 ( 8, 6) [000108] ---XG------- t108 = * ADD int N005 ( 3, 2) [000104] ------------ t104 = LCL_VAR byref V11 loc7 u:1 $8c /--* t104 byref N007 ( 4, 3) [001135] -c---------- t1135 = * LEA(b+20) byref /--* t1135 byref +--* t108 int [001424] -A-XGO------ * STOREIND int [001425] ------------ IL_OFFSET void IL offset: 0x294 N001 ( 3, 2) [000111] ------------ t111 = LCL_VAR byref V11 loc7 u:1 Zero Fseq[key] $8f N003 ( 1, 1) [000112] ------------ t112 = LCL_VAR ref V01 arg1 u:1 (last use) $101 /--* t111 byref +--* t112 ref [001426] -A-XG------- * STOREIND ref [001427] ------------ IL_OFFSET void IL offset: 0x29c N001 ( 3, 2) [000115] ------------ t115 = LCL_VAR byref V11 loc7 u:1 (last use) $8c /--* t115 byref N003 ( 4, 3) [001137] ------------ t1137 = * LEA(b+8) byref N005 ( 1, 1) [000116] ------------ t116 = LCL_VAR ref V02 arg2 u:1 (last use) $102 /--* t1137 byref +--* t116 ref [001428] -A--GO------ * STOREIND ref [001429] ------------ IL_OFFSET void IL offset: 0x2a4 N001 ( 3, 2) [000120] ------------ t120 = LCL_VAR int V10 loc6 u:1 (last use) $3cc N002 ( 1, 1) [000121] -c---------- t121 = CNS_INT int 1 $c1 /--* t120 int +--* t121 int N003 ( 5, 4) [000122] ------------ t122 = * ADD int $804 N004 ( 3, 2) [000119] ------------ t119 = LCL_VAR byref V08 loc4 u:2 (last use) $781 /--* t119 byref +--* t122 int [001430] -A--GO------ * STOREIND int [001431] ------------ IL_OFFSET void IL offset: 0x2ab N001 ( 1, 1) [000126] -c---------- t126 = LCL_VAR ref V00 this u:1 $100 /--* t126 ref N003 ( 2, 2) [001141] -c---------- t1141 = * LEA(b+68) byref /--* t1141 byref N004 ( 4, 4) [000127] nc--GO------ t127 = * IND int N005 ( 1, 1) [000128] -c---------- t128 = CNS_INT int 1 $c1 /--* t127 int +--* t128 int N006 ( 6, 6) [000129] -c--GO------ t129 = * ADD int N007 ( 1, 1) [000125] ------------ t125 = LCL_VAR ref V00 this u:1 $100 /--* t125 ref N009 ( 2, 2) [001139] -c---------- t1139 = * LEA(b+68) byref /--* t1139 byref +--* t129 int [001432] -A--GO------ * STOREIND int [001433] ------------ IL_OFFSET void IL offset: 0x2ca N001 ( 1, 1) [000145] ------------ t145 = LCL_VAR int V07 loc3 u:2 (last use) $3c5 N002 ( 1, 1) [000146] -c---------- t146 = CNS_INT int 100 $e3 /--* t145 int +--* t146 int N003 ( 3, 3) [000147] N------N-U-- * LE void $80d N004 ( 5, 5) [000148] ------------ * JTRUE void ------------ BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} [001434] ------------ IL_OFFSET void IL offset: 0x2cf N003 ( 1, 1) [000151] ------------ t151 = LCL_VAR ref V05 loc1 u:1 (last use) /--* t151 ref [001495] ------------ t1495 = * PUTARG_REG ref REG rdx N004 ( 2, 10) [000152] H------N---- t152 = CNS_INT(h) long 0xd1ffab1e class $62 /--* t152 long [001496] ------------ t1496 = * PUTARG_REG long REG rcx /--* t1495 ref arg1 in rdx +--* t1496 long arg0 in rcx N005 ( 17, 18) [000153] --C-G------- t153 = * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS N006 ( 1, 1) [000154] -c---------- t154 = CNS_INT ref null $VN.Null /--* t153 ref +--* t154 ref N007 ( 19, 20) [000155] J---G--N---- * EQ void N008 ( 21, 22) [000156] ----G------- * JTRUE void ------------ BB57 [2D7..2E3), preds={BB56} succs={BB58} [001435] ------------ IL_OFFSET void IL offset: 0x2d7 N004 ( 1, 1) [000158] ------------ t158 = LCL_VAR ref V04 loc0 u:2 (last use) $684 /--* t158 ref [001454] -c---------- t1454 = * LEA(b+8) ref /--* t1454 ref N005 ( 3, 3) [000159] ---X-------- t159 = * IND int $73d /--* t159 int [001497] ---X-------- t1497 = * PUTARG_REG int REG rdx N006 ( 1, 1) [000157] ------------ t157 = LCL_VAR ref V00 this u:1 $100 /--* t157 ref [001498] ------------ t1498 = * PUTARG_REG ref REG rcx N007 ( 1, 1) [000160] ------------ t160 = CNS_INT int 1 $c1 /--* t160 int [001499] ------------ t1499 = * PUTARG_REG int REG r8 /--* t1497 int arg1 in rdx +--* t1498 ref this in rcx +--* t1499 int arg2 in r8 N008 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void ------------ BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} N001 ( 1, 1) [000482] ------------ t482 = CNS_INT int 1 $c1 /--* t482 int N002 ( 2, 2) [000810] ------------ * RETURN int $1f4 ------------ BB59 [008..00E) (throw), preds={BB01} succs={} [001436] ------------ IL_OFFSET void IL offset: 0x8 N002 ( 1, 1) [000532] ------------ t532 = CNS_INT int 4 $c5 /--* t532 int [001500] ------------ t1500 = * PUTARG_REG int REG rcx /--* t1500 int arg0 in rcx N003 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException $VN.Void ------------ BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} [001437] ------------ IL_OFFSET void IL offset: 0x14f N001 ( 1, 1) [000441] !----------- t441 = LCL_VAR ref V00 this u:1 $100 /--* t441 ref N002 ( 3, 2) [000442] #----O------ t442 = * IND long $2e8 /--* t442 long N004 ( 7, 5) [000444] DA---O------ * STORE_LCL_VAR long V26 tmp12 d:1 N001 ( 3, 2) [000446] ------------ t446 = LCL_VAR long V26 tmp12 u:1 $2e7 /--* t446 long N003 ( 4, 3) [000448] -c---------- t448 = * LEA(b+56) long /--* t448 long N004 ( 6, 5) [000449] #----------- t449 = * IND long $2e9 /--* t449 long N005 ( 9, 7) [000450] #----------- t450 = * IND long $2ea /--* t450 long N007 ( 10, 8) [000452] -c---------- t452 = * LEA(b+56) long /--* t452 long N008 ( 12, 10) [000456] nc---------- t456 = * IND long N009 ( 1, 1) [000459] -c---------- t459 = CNS_INT long 0 $243 /--* t456 long +--* t459 long N010 ( 14, 12) [000460] J------N---- * EQ void N011 ( 16, 14) [001158] ------------ * JTRUE void ------------ BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} N001 ( 3, 2) [000466] ------?----- t466 = LCL_VAR long V26 tmp12 u:1 (last use) $2e7 /--* t466 long N003 ( 4, 3) [000465] -c----?----- t465 = * LEA(b+56) long /--* t465 long N004 ( 6, 5) [000464] #-----?----- t464 = * IND long $2e9 /--* t464 long N005 ( 9, 7) [000463] #-----?----- t463 = * IND long $2ea /--* t463 long N007 ( 10, 8) [000462] -c----?----- t462 = * LEA(b+56) long /--* t462 long N008 ( 12, 10) [000461] n-----?----- t461 = * IND long /--* t461 long N010 ( 16, 13) [001160] DA---------- * STORE_LCL_VAR long V28 tmp14 d:3 ------------ BB62 [???..???), preds={BB60} succs={BB63} N003 ( 3, 2) [000445] ------?----- t445 = LCL_VAR long V26 tmp12 u:1 (last use) $2e7 /--* t445 long [001501] ------------ t1501 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000457] H-----?----- t457 = CNS_INT(h) long 0xd1ffab1e global ptr $52 /--* t457 long [001502] ------------ t1502 = * PUTARG_REG long REG rdx /--* t1501 long arg0 in rcx +--* t1502 long arg1 in rdx N005 ( 19, 19) [000458] --C-G-?----- t458 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 /--* t458 long N007 ( 23, 22) [001162] DA--G------- * STORE_LCL_VAR long V28 tmp14 d:2 ------------ BB63 [???..157) (throw), preds={BB61,BB62} succs={} N001 ( 0, 0) [001241] ------------ t1241 = PHI_ARG long V28 tmp14 u:3 N002 ( 0, 0) [001240] ------------ t1240 = PHI_ARG long V28 tmp14 u:2 $332 /--* t1241 long +--* t1240 long N003 ( 0, 0) [001183] ------------ t1183 = * PHI long /--* t1183 long N005 ( 0, 0) [001184] DA---------- * STORE_LCL_VAR long V28 tmp14 d:1 N003 ( 3, 2) [000473] ------------ t473 = LCL_VAR long V28 tmp14 u:1 (last use) $347 /--* t473 long [001503] ------------ t1503 = * PUTARG_REG long REG rcx N004 ( 1, 1) [000455] ------------ t455 = LCL_VAR ref V01 arg1 u:1 (last use) $101 /--* t455 ref [001504] ------------ t1504 = * PUTARG_REG ref REG rdx /--* t1503 long arg0 in rcx +--* t1504 ref arg1 in rdx N005 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void ------------ BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} [001438] ------------ IL_OFFSET void IL offset: 0x1bc N001 ( 1, 1) [000296] !----------- t296 = LCL_VAR ref V00 this u:1 $100 /--* t296 ref N002 ( 3, 2) [000297] #----O------ t297 = * IND long $2e8 /--* t297 long N004 ( 7, 5) [000299] DA---O------ * STORE_LCL_VAR long V21 tmp7 d:1 N001 ( 3, 2) [000301] ------------ t301 = LCL_VAR long V21 tmp7 u:1 $2e7 /--* t301 long N003 ( 4, 3) [000303] -c---------- t303 = * LEA(b+56) long /--* t303 long N004 ( 6, 5) [000304] #----------- t304 = * IND long $2e9 /--* t304 long N005 ( 9, 7) [000305] #----------- t305 = * IND long $2ea /--* t305 long N007 ( 10, 8) [000307] -c---------- t307 = * LEA(b+56) long /--* t307 long N008 ( 12, 10) [000311] nc---------- t311 = * IND long N009 ( 1, 1) [000314] -c---------- t314 = CNS_INT long 0 $243 /--* t311 long +--* t314 long N010 ( 14, 12) [000315] J------N---- * EQ void N011 ( 16, 14) [001168] ------------ * JTRUE void ------------ BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} N001 ( 3, 2) [000321] ------?----- t321 = LCL_VAR long V21 tmp7 u:1 (last use) $2e7 /--* t321 long N003 ( 4, 3) [000320] -c----?----- t320 = * LEA(b+56) long /--* t320 long N004 ( 6, 5) [000319] #-----?----- t319 = * IND long $2e9 /--* t319 long N005 ( 9, 7) [000318] #-----?----- t318 = * IND long $2ea /--* t318 long N007 ( 10, 8) [000317] -c----?----- t317 = * LEA(b+56) long /--* t317 long N008 ( 12, 10) [000316] n-----?----- t316 = * IND long /--* t316 long N010 ( 16, 13) [001170] DA---------- * STORE_LCL_VAR long V23 tmp9 d:3 ------------ BB66 [???..???), preds={BB64} succs={BB67} N003 ( 3, 2) [000300] ------?----- t300 = LCL_VAR long V21 tmp7 u:1 (last use) $2e7 /--* t300 long [001505] ------------ t1505 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000312] H-----?----- t312 = CNS_INT(h) long 0xd1ffab1e global ptr $52 /--* t312 long [001506] ------------ t1506 = * PUTARG_REG long REG rdx /--* t1505 long arg0 in rcx +--* t1506 long arg1 in rdx N005 ( 19, 19) [000313] --C-G-?----- t313 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 /--* t313 long N007 ( 23, 22) [001172] DA--G------- * STORE_LCL_VAR long V23 tmp9 d:2 ------------ BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} N001 ( 0, 0) [001232] ------------ t1232 = PHI_ARG long V23 tmp9 u:3 N002 ( 0, 0) [001231] ------------ t1231 = PHI_ARG long V23 tmp9 u:2 $332 /--* t1232 long +--* t1231 long N003 ( 0, 0) [001201] ------------ t1201 = * PHI long /--* t1201 long N005 ( 0, 0) [001202] DA---------- * STORE_LCL_VAR long V23 tmp9 d:1 N003 ( 3, 2) [000328] ------------ t328 = LCL_VAR long V23 tmp9 u:1 (last use) $34b /--* t328 long [001507] ------------ t1507 = * PUTARG_REG long REG rcx N004 ( 1, 1) [000310] ------------ t310 = LCL_VAR ref V01 arg1 u:1 (last use) $101 /--* t310 ref [001508] ------------ t1508 = * PUTARG_REG ref REG rdx /--* t1507 long arg0 in rcx +--* t1508 ref arg1 in rdx N005 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void ------------ BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} [001439] ------------ IL_OFFSET void IL offset: 0x1dd N001 ( 14, 5) [000233] --CXG------- CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported $VN.Void ------------ BB69 [???..???) (throw), preds={} succs={} N001 ( 14, 5) [001444] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Trees before Calculate stack level slots ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i LIR BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i LIR BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe LIR BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i LIR BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe LIR BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i LIR BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe LIR BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i LIR BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe LIR BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe LIR BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe LIR BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe LIR BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe LIR BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen LIR BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe LIR BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen LIR BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe LIR BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen LIR BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe LIR BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe LIR BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe LIR BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe LIR BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target LIR BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd LIR BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd LIR BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd LIR BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal LIR BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd LIR BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen LIR BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd LIR BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal Loop1 gcsafe LIR BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target LIR BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd LIR BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd LIR BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe LIR BB36 [0108] 1 BB34 1 [???..???) i gcsafe LIR BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd LIR BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd LIR BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen LIR BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd LIR BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe LIR BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd LIR BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal LIR BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i LIR BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen LIR BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe LIR BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen LIR BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen LIR BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen LIR BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe LIR BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen LIR BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe LIR BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen LIR BB54 [0044] 2 BB48,BB53 0.50 [261..276) i LIR BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen LIR BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall LIR BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen LIR BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal LIR BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe LIR BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd LIR BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe LIR BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe LIR BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd LIR BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd LIR BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe LIR BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe LIR BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd LIR BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd LIR BB69 [0117] 0 0 [???..???) (throw ) keep i internal rare LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} [001332] ------------ IL_OFFSET void IL offset: 0x0 N001 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V01 arg1 u:1 $101 N002 ( 1, 1) [000001] -c---------- t1 = CNS_INT ref null $VN.Null /--* t0 ref +--* t1 ref N003 ( 3, 3) [000002] J------N---- * EQ void $180 N004 ( 5, 5) [000003] ------------ * JTRUE void ------------ BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} [001333] ------------ IL_OFFSET void IL offset: 0xe N001 ( 1, 1) [000004] ------------ t4 = LCL_VAR ref V00 this u:1 $100 /--* t4 ref N003 ( 2, 2) [000814] -c---------- t814 = * LEA(b+8) byref /--* t814 byref N004 ( 4, 4) [000005] -c-XG------- t5 = * IND ref N005 ( 1, 1) [000006] -c---------- t6 = CNS_INT ref null $VN.Null /--* t5 ref +--* t6 ref N006 ( 6, 6) [000007] J--XG--N---- * NE void N007 ( 8, 8) [000008] ---XG------- * JTRUE void ------------ BB03 [016..01E), preds={BB02} succs={BB04} N003 ( 1, 1) [000526] ------------ t526 = LCL_VAR ref V00 this u:1 $100 /--* t526 ref [001455] ------------ t1455 = * PUTARG_REG ref REG rcx N004 ( 1, 1) [000527] ------------ t527 = CNS_INT int 0 $c0 /--* t527 int [001456] ------------ t1456 = * PUTARG_REG int REG rdx /--* t1455 ref this in rcx +--* t1456 int arg1 in rdx N005 ( 16, 10) [000528] --CXG------- t528 = * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize $1c2 ------------ BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} [001334] ------------ IL_OFFSET void IL offset: 0x1e N001 ( 1, 1) [000009] ------------ t9 = LCL_VAR ref V00 this u:1 $100 /--* t9 ref N003 ( 2, 2) [000818] -c---------- t818 = * LEA(b+8) byref /--* t818 byref N004 ( 4, 4) [000010] nc--GO------ t10 = * IND ref N005 ( 1, 1) [000011] -c---------- t11 = CNS_INT ref null $VN.Null /--* t10 ref +--* t11 ref N006 ( 9, 6) [000012] N---GO------ t12 = * NE int /--* t12 int N008 ( 9, 6) [000544] DA--GO------ * STORE_LCL_VAR int V33 tmp19 d:1 [001335] ------------ IL_OFFSET void IL offset: 0x1e N001 ( 2, 10) [000537] H----------- t537 = CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] $43 /--* t537 long N002 ( 4, 12) [000538] #---G------- t538 = * IND ref $105 /--* t538 ref N004 ( 4, 12) [001291] DA--G------- * STORE_LCL_VAR ref V73 cse8 d:1 [001336] ------------ IL_OFFSET void IL offset: 0x1e N001 ( 1, 1) [001294] ------------ t1294 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1294 ref N003 ( 1, 3) [000556] DA--G------- * STORE_LCL_VAR ref V35 tmp21 d:1 [001337] ------------ IL_OFFSET void IL offset: 0x1e N001 ( 1, 1) [000546] ------------ t546 = LCL_VAR int V33 tmp19 u:1 (last use) N002 ( 1, 1) [000547] -c---------- t547 = CNS_INT int 0 $c0 /--* t546 int +--* t547 int N003 ( 3, 3) [000548] J------N---- * NE void N004 ( 5, 5) [000549] ------------ * JTRUE void ------------ BB05 [01E..01F), preds={BB04} succs={BB06} [001338] ------------ IL_OFFSET void IL offset: 0x1e N003 ( 1, 1) [000550] ------------ t550 = LCL_VAR ref V35 tmp21 u:1 $105 /--* t550 ref [001457] ------------ t1457 = * PUTARG_REG ref REG rcx N004 ( 1, 1) [000551] ------------ t551 = LCL_VAR ref V35 tmp21 u:1 (last use) $105 /--* t551 ref [001458] ------------ t1458 = * PUTARG_REG ref REG rdx /--* t1457 ref arg0 in rcx +--* t1458 ref arg1 in rdx N005 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} [001339] ------------ IL_OFFSET void IL offset: 0x2c N001 ( 1, 1) [000015] ------------ t15 = LCL_VAR ref V00 this u:1 $100 /--* t15 ref N003 ( 2, 2) [000822] -c---------- t822 = * LEA(b+16) byref /--* t822 byref N004 ( 4, 4) [000016] n---GO------ t16 = * IND ref /--* t16 ref N006 ( 4, 4) [000018] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:1 [001340] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 1, 1) [000019] ------------ t19 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000020] -c---------- t20 = CNS_INT ref null $VN.Null /--* t19 ref +--* t20 ref N003 ( 6, 3) [000021] N----------- t21 = * NE int /--* t21 int N005 ( 6, 3) [000566] DA---------- * STORE_LCL_VAR int V36 tmp22 d:1 [001341] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 1, 1) [001295] ------------ t1295 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1295 ref N003 ( 1, 3) [000576] DA--G------- * STORE_LCL_VAR ref V37 tmp23 d:1 [001342] ------------ IL_OFFSET void IL offset: 0x33 N001 ( 1, 1) [000568] ------------ t568 = LCL_VAR int V36 tmp22 u:1 (last use) N002 ( 1, 1) [000569] -c---------- t569 = CNS_INT int 0 $c0 /--* t568 int +--* t569 int N003 ( 3, 3) [000570] J------N---- * NE void N004 ( 5, 5) [000571] ------------ * JTRUE void ------------ BB07 [033..034), preds={BB06} succs={BB08} [001343] ------------ IL_OFFSET void IL offset: 0x33 N003 ( 2, 10) [000823] H----------- t823 = CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" $46 /--* t823 long N004 ( 4, 12) [000824] #---G------- t824 = * IND ref $106 /--* t824 ref [001459] ----G------- t1459 = * PUTARG_REG ref REG rcx N005 ( 1, 1) [000573] ------------ t573 = LCL_VAR ref V37 tmp23 u:1 (last use) $105 /--* t573 ref [001460] ------------ t1460 = * PUTARG_REG ref REG rdx /--* t1459 ref arg0 in rcx +--* t1460 ref arg1 in rdx N006 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} [001344] ------------ IL_OFFSET void IL offset: 0x41 N001 ( 1, 1) [000025] ------------ t25 = LCL_VAR ref V00 this u:1 $100 /--* t25 ref N003 ( 2, 2) [000828] -c---------- t828 = * LEA(b+24) byref /--* t828 byref N004 ( 4, 4) [000026] n---GO------ t26 = * IND ref /--* t26 ref N006 ( 4, 4) [000028] DA--GO------ * STORE_LCL_VAR ref V05 loc1 d:1 [001345] ------------ IL_OFFSET void IL offset: 0x48 N001 ( 1, 1) [000029] ------------ t29 = LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000030] -c---------- t30 = CNS_INT ref null $VN.Null /--* t29 ref +--* t30 ref N003 ( 3, 3) [000031] J------N---- * EQ void N004 ( 5, 5) [000032] ------------ * JTRUE void ------------ BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} [001346] ------------ IL_OFFSET void IL offset: 0x4b N001 ( 1, 1) [000486] !----------- t486 = LCL_VAR ref V00 this u:1 $100 /--* t486 ref N002 ( 3, 2) [000487] #----O------ t487 = * IND long $2e8 /--* t487 long N004 ( 3, 3) [000489] DA---O------ * STORE_LCL_VAR long V29 tmp15 d:1 N001 ( 1, 1) [000491] ------------ t491 = LCL_VAR long V29 tmp15 u:1 $2e7 /--* t491 long N003 ( 2, 2) [000493] -c---------- t493 = * LEA(b+56) long /--* t493 long N004 ( 4, 4) [000494] #----------- t494 = * IND long $2e9 /--* t494 long N005 ( 7, 6) [000495] #----------- t495 = * IND long $2ea /--* t495 long N007 ( 8, 7) [000497] -c---------- t497 = * LEA(b+64) long /--* t497 long N008 ( 10, 9) [000501] n----------- t501 = * IND long /--* t501 long N010 ( 14, 12) [001266] DA---------- * STORE_LCL_VAR long V68 cse3 d:1 N011 ( 3, 2) [001267] ------------ t1267 = LCL_VAR long V68 cse3 u:1 N013 ( 1, 1) [000504] -c---------- t504 = CNS_INT long 0 $243 /--* t1267 long +--* t504 long N014 ( 19, 16) [000505] J------N---- * EQ void N015 ( 21, 18) [001148] ------------ * JTRUE void ------------ BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} N001 ( 3, 2) [001269] ------------ t1269 = LCL_VAR long V68 cse3 u:1 (last use) /--* t1269 long N003 ( 3, 3) [001150] DA---------- * STORE_LCL_VAR long V31 tmp17 d:3 ------------ BB11 [???..???), preds={BB09} succs={BB12} N003 ( 1, 1) [000490] ------?----- t490 = LCL_VAR long V29 tmp15 u:1 (last use) $2e7 /--* t490 long [001461] ------------ t1461 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000502] H-----?----- t502 = CNS_INT(h) long 0xd1ffab1e global ptr $49 /--* t502 long [001462] ------------ t1462 = * PUTARG_REG long REG rdx /--* t1461 long arg0 in rcx +--* t1462 long arg1 in rdx N005 ( 17, 18) [000503] --C-G-?----- t503 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $308 /--* t503 long N007 ( 17, 18) [001152] DA--G------- * STORE_LCL_VAR long V31 tmp17 d:2 ------------ BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} N001 ( 0, 0) [001247] ------------ t1247 = PHI_ARG long V31 tmp17 u:3 N002 ( 0, 0) [001246] ------------ t1246 = PHI_ARG long V31 tmp17 u:2 $308 /--* t1247 long +--* t1246 long N003 ( 0, 0) [001216] ------------ t1216 = * PHI long /--* t1216 long N005 ( 0, 0) [001217] DA---------- * STORE_LCL_VAR long V31 tmp17 d:1 N004 ( 1, 1) [000484] ------------ t484 = LCL_VAR ref V05 loc1 u:1 /--* t484 ref [001463] ------------ t1463 = * PUTARG_REG ref REG rcx N005 ( 1, 1) [000831] ------------ t831 = LCL_VAR long V31 tmp17 u:1 r11 REG r11 $342 /--* t831 long [001464] ------------ t1464 = * PUTARG_REG long REG r11 N006 ( 1, 1) [000500] ------------ t500 = LCL_VAR ref V01 arg1 u:1 $101 /--* t500 ref [001465] ------------ t1465 = * PUTARG_REG ref REG rdx N007 ( 1, 1) [000521] ------------ t521 = LCL_VAR long V31 tmp17 u:1 (last use) $342 /--* t521 long [001466] Dc---------- t1466 = * IND long REG NA /--* t1463 ref this in rcx +--* t1464 long arg1 in r11 +--* t1465 ref arg2 in rdx +--* t1466 long calli tgt N008 ( 27, 12) [000522] --CXG------- t522 = * CALL ind stub int $1c7 /--* t522 int N010 ( 31, 15) [000524] DA-XG------- * STORE_LCL_VAR int V15 tmp1 d:3 ------------ BB13 [054..061), preds={BB08} succs={BB14} [001347] ------------ IL_OFFSET void IL offset: 0x54 N002 ( 1, 1) [000033] ------------ t33 = LCL_VAR ref V01 arg1 u:1 $101 /--* t33 ref [001467] ------------ t1467 = * PUTARG_REG ref REG rcx N003 ( 1, 1) [000836] ------------ t836 = LCL_VAR ref V01 arg1 u:1 $101 /--* t836 ref N004 ( 3, 2) [000837] #----O------ t837 = * IND long $2e4 /--* t837 long N006 ( 4, 3) [000839] -c---------- t839 = * LEA(b+72) long /--* t839 long N007 ( 6, 5) [000840] #----O------ t840 = * IND long $2e6 /--* t840 long N009 ( 7, 6) [000842] -c---------- t842 = * LEA(b+24) long /--* t842 long N010 ( 9, 8) [000843] nc---O------ t843 = * IND long REG NA /--* t1467 ref this in rcx +--* t843 long control expr N011 ( 30, 18) [000035] --CXGO------ t35 = * CALLV vt-ind int System.Object.GetHashCode $1c5 /--* t35 int N013 ( 34, 21) [000038] DA-XGO------ * STORE_LCL_VAR int V15 tmp1 d:2 ------------ BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} N001 ( 0, 0) [001245] ------------ t1245 = PHI_ARG int V15 tmp1 u:3 $1c7 N002 ( 0, 0) [001244] ------------ t1244 = PHI_ARG int V15 tmp1 u:2 $1c5 /--* t1245 int +--* t1244 int N003 ( 0, 0) [001213] ------------ t1213 = * PHI int /--* t1213 int N005 ( 0, 0) [001214] DA---------- * STORE_LCL_VAR int V15 tmp1 d:1 N001 ( 3, 2) [000040] ------------ t40 = LCL_VAR int V15 tmp1 u:1 (last use) $3c0 /--* t40 int N003 ( 3, 3) [000042] DA---------- * STORE_LCL_VAR int V06 loc2 d:1 [001348] ------------ IL_OFFSET void IL offset: 0x62 N001 ( 1, 1) [000043] ------------ t43 = CNS_INT int 0 $c0 /--* t43 int N003 ( 1, 3) [000045] DA---------- * STORE_LCL_VAR int V07 loc3 d:1 [001349] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000046] ------------ t46 = LCL_VAR ref V00 this u:1 $100 /--* t46 ref N003 ( 2, 2) [000845] -c---------- t845 = * LEA(b+8) byref /--* t845 byref N004 ( 4, 4) [000578] n---GO------ t578 = * IND ref /--* t578 ref N006 ( 4, 4) [000580] DA--GO------ * STORE_LCL_VAR ref V39 tmp25 d:1 [001350] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000582] ------------ t582 = LCL_VAR ref V39 tmp25 u:1 /--* t582 ref [001441] -c---------- t1441 = * LEA(b+8) ref /--* t1441 ref N002 ( 3, 3) [000583] ---X-------- t583 = * IND int /--* t583 int N004 ( 3, 3) [000629] DA-X-------- * STORE_LCL_VAR int V40 tmp26 d:1 [001351] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000584] ------------ t584 = LCL_VAR ref V00 this u:1 $100 /--* t584 ref N003 ( 2, 2) [000847] -c---------- t847 = * LEA(b+48) byref /--* t847 byref N004 ( 4, 4) [000585] n---GO------ t585 = * IND long /--* t585 long N006 ( 4, 4) [000631] DA--GO------ * STORE_LCL_VAR long V41 tmp27 d:1 [001352] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000597] ------------ t597 = LCL_VAR int V40 tmp26 u:1 N002 ( 1, 4) [000598] -c---------- t598 = CNS_INT int 0x7FFFFFFF $ce /--* t597 int +--* t598 int N003 ( 6, 6) [000599] N--------U-- t599 = * LE int /--* t599 int N005 ( 6, 6) [000642] DA---------- * STORE_LCL_VAR int V43 tmp29 d:1 [001353] ------------ IL_OFFSET void IL offset: 0x64 [001354] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [001297] ------------ t1297 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1297 ref N003 ( 1, 3) [000654] DA--G------- * STORE_LCL_VAR ref V45 tmp31 d:1 [001355] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000644] ------------ t644 = LCL_VAR int V43 tmp29 u:1 (last use) N002 ( 1, 1) [000645] -c---------- t645 = CNS_INT int 0 $c0 /--* t644 int +--* t645 int N003 ( 3, 3) [000646] J------N---- * NE void N004 ( 5, 5) [000647] ------------ * JTRUE void ------------ BB15 [064..065), preds={BB14} succs={BB16} [001356] ------------ IL_OFFSET void IL offset: 0x64 N003 ( 1, 1) [000648] ------------ t648 = LCL_VAR ref V45 tmp31 u:1 $105 /--* t648 ref [001468] ------------ t1468 = * PUTARG_REG ref REG rcx N004 ( 1, 1) [000649] ------------ t649 = LCL_VAR ref V45 tmp31 u:1 (last use) $105 /--* t649 ref [001469] ------------ t1469 = * PUTARG_REG ref REG rdx /--* t1468 ref arg0 in rcx +--* t1469 ref arg1 in rdx N005 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} [001357] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000604] ------------ t604 = LCL_VAR long V41 tmp27 u:1 (last use) N002 ( 1, 1) [000047] ------------ t47 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t47 int N003 ( 2, 3) [000605] ---------U-- t605 = * CAST long <- ulong <- uint $310 /--* t604 long +--* t605 long N004 ( 7, 7) [000606] ------------ t606 = * MUL long N005 ( 1, 1) [000607] -c---------- t607 = CNS_INT int 32 $d2 /--* t606 long +--* t607 int N006 ( 9, 9) [000608] ------------ t608 = * RSZ long N007 ( 1, 1) [000610] -c---------- t610 = CNS_INT long 1 $247 /--* t608 long +--* t610 long N008 ( 11, 11) [000611] ------------ t611 = * ADD long N009 ( 1, 1) [000612] ------------ t612 = LCL_VAR int V40 tmp26 u:1 /--* t612 int N010 ( 2, 3) [000613] ---------U-- t613 = * CAST long <- ulong <- uint /--* t611 long +--* t613 long N011 ( 17, 17) [000614] ------------ t614 = * MUL long N012 ( 1, 1) [000615] -c---------- t615 = CNS_INT int 32 $d2 /--* t614 long +--* t615 int N013 ( 19, 19) [000616] ------------ t616 = * RSZ long /--* t616 long N014 ( 20, 21) [000617] ------------ t617 = * CAST int <- uint <- long /--* t617 int N016 ( 20, 21) [000619] DA---------- * STORE_LCL_VAR int V42 tmp28 d:1 [001358] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000621] ------------ t621 = LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000622] ------------ t622 = LCL_VAR int V40 tmp26 u:1 (last use) /--* t621 int +--* t622 int N003 ( 22, 5) [000623] ---X-------- t623 = * UMOD int N004 ( 1, 1) [000620] ------------ t620 = LCL_VAR int V42 tmp28 u:1 /--* t623 int +--* t620 int N005 ( 27, 7) [000624] ---X-------- t624 = * EQ int /--* t624 int N007 ( 27, 7) [000665] DA-X-------- * STORE_LCL_VAR int V46 tmp32 d:1 [001359] ------------ IL_OFFSET void IL offset: 0x64 [001360] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [001299] ------------ t1299 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1299 ref N003 ( 1, 3) [000677] DA--G------- * STORE_LCL_VAR ref V48 tmp34 d:1 [001361] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000667] ------------ t667 = LCL_VAR int V46 tmp32 u:1 (last use) N002 ( 1, 1) [000668] -c---------- t668 = CNS_INT int 0 $c0 /--* t667 int +--* t668 int N003 ( 3, 3) [000669] J------N---- * NE void N004 ( 5, 5) [000670] ------------ * JTRUE void ------------ BB17 [064..065), preds={BB16} succs={BB18} [001362] ------------ IL_OFFSET void IL offset: 0x64 N003 ( 1, 1) [000671] ------------ t671 = LCL_VAR ref V48 tmp34 u:1 $105 /--* t671 ref [001470] ------------ t1470 = * PUTARG_REG ref REG rcx N004 ( 1, 1) [000672] ------------ t672 = LCL_VAR ref V48 tmp34 u:1 (last use) $105 /--* t672 ref [001471] ------------ t1471 = * PUTARG_REG ref REG rdx /--* t1470 ref arg0 in rcx +--* t1471 ref arg1 in rdx N005 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} [001363] ------------ IL_OFFSET void IL offset: 0x64 N001 ( 1, 1) [000627] ------------ t627 = LCL_VAR int V42 tmp28 u:1 N002 ( 1, 1) [000581] ------------ t581 = LCL_VAR ref V39 tmp25 u:1 /--* t581 ref [001443] -c---------- t1443 = * LEA(b+8) ref /--* t1443 ref N003 ( 3, 3) [000854] -c-X-------- t854 = * IND int /--* t627 int +--* t854 int N004 ( 8, 11) [000855] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void N005 ( 1, 1) [000852] ------------ t852 = LCL_VAR ref V39 tmp25 u:1 (last use) N006 ( 1, 1) [000853] ------------ t853 = LCL_VAR int V42 tmp28 u:1 (last use) /--* t853 int N007 ( 2, 3) [000856] ------------ t856 = * CAST long <- int /--* t852 ref +--* t856 long N012 ( 5, 6) [000861] -------N---- t861 = * LEA(b+(i*4)+16) byref /--* t861 byref N017 ( 19, 24) [000591] DA-XG------- * STORE_LCL_VAR byref V38 tmp24 d:1 N001 ( 1, 1) [000592] ------------ t592 = LCL_VAR byref V38 tmp24 u:1 (last use) $81 /--* t592 byref N003 ( 5, 4) [000051] DA---------- * STORE_LCL_VAR byref V08 loc4 d:1 [001364] ------------ IL_OFFSET void IL offset: 0x6d N001 ( 1, 1) [000052] ------------ t52 = LCL_VAR byref V08 loc4 u:1 $81 /--* t52 byref N002 ( 3, 2) [000053] *--XG------- t53 = * IND int N003 ( 1, 1) [000054] -c---------- t54 = CNS_INT int -1 $c4 /--* t53 int +--* t54 int N004 ( 5, 4) [000055] ---XG------- t55 = * ADD int /--* t55 int N006 ( 5, 4) [000057] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:1 [001365] ------------ IL_OFFSET void IL offset: 0x74 N001 ( 1, 1) [000058] ------------ t58 = LCL_VAR ref V05 loc1 u:1 N002 ( 1, 1) [000059] -c---------- t59 = CNS_INT ref null $VN.Null /--* t58 ref +--* t59 ref N003 ( 3, 3) [000060] J------N---- * NE void N004 ( 5, 5) [000061] ------------ * JTRUE void ------------ BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} [001366] ------------ IL_OFFSET void IL offset: 0xff N001 ( 1, 1) [000353] !----------- t353 = LCL_VAR ref V00 this u:1 $100 /--* t353 ref N002 ( 3, 2) [000354] #----O------ t354 = * IND long $2e8 /--* t354 long N004 ( 3, 3) [000356] DA---O------ * STORE_LCL_VAR long V24 tmp10 d:1 N001 ( 1, 1) [000358] ------------ t358 = LCL_VAR long V24 tmp10 u:1 $2e7 /--* t358 long N003 ( 2, 2) [000360] -c---------- t360 = * LEA(b+56) long /--* t360 long N004 ( 4, 4) [000361] #----------- t361 = * IND long $2e9 /--* t361 long N005 ( 7, 6) [000362] #----------- t362 = * IND long $2ea /--* t362 long N007 ( 8, 7) [000364] -c---------- t364 = * LEA(b+32) long /--* t364 long N008 ( 10, 9) [000365] n----------- t365 = * IND long /--* t365 long N010 ( 14, 12) [001271] DA---------- * STORE_LCL_VAR long V69 cse4 d:1 N011 ( 3, 2) [001272] ------------ t1272 = LCL_VAR long V69 cse4 u:1 N013 ( 1, 1) [000368] -c---------- t368 = CNS_INT long 0 $243 /--* t1272 long +--* t368 long N014 ( 19, 16) [000369] J------N---- * EQ void N015 ( 21, 18) [001153] ------------ * JTRUE void ------------ BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} N001 ( 3, 2) [001274] ------------ t1274 = LCL_VAR long V69 cse4 u:1 (last use) /--* t1274 long N003 ( 7, 5) [001155] DA---------- * STORE_LCL_VAR long V25 tmp11 d:3 ------------ BB21 [???..???), preds={BB19} succs={BB22} N003 ( 1, 1) [000357] ------?----- t357 = LCL_VAR long V24 tmp10 u:1 (last use) $2e7 /--* t357 long [001472] ------------ t1472 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000366] H-----?----- t366 = CNS_INT(h) long 0xd1ffab1e global ptr $4f /--* t366 long [001473] ------------ t1473 = * PUTARG_REG long REG rdx /--* t1472 long arg0 in rcx +--* t1473 long arg1 in rdx N005 ( 17, 18) [000367] --C-G-?----- t367 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $325 /--* t367 long N007 ( 21, 21) [001157] DA--G------- * STORE_LCL_VAR long V25 tmp11 d:2 ------------ BB22 [???..106), preds={BB20,BB21} succs={BB23} N001 ( 0, 0) [001243] ------------ t1243 = PHI_ARG long V25 tmp11 u:3 N002 ( 0, 0) [001242] ------------ t1242 = PHI_ARG long V25 tmp11 u:2 $325 /--* t1243 long +--* t1242 long N003 ( 0, 0) [001198] ------------ t1198 = * PHI long /--* t1198 long N005 ( 0, 0) [001199] DA---------- * STORE_LCL_VAR long V25 tmp11 d:1 N002 ( 3, 2) [000382] ------------ t382 = LCL_VAR long V25 tmp11 u:1 (last use) $344 /--* t382 long [001474] ------------ t1474 = * PUTARG_REG long REG rcx /--* t1474 long arg0 in rcx N003 ( 17, 8) [000352] --CXG------- t352 = * CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default $223 /--* t352 ref N005 ( 17, 8) [000386] DA-XG------- * STORE_LCL_VAR ref V12 loc8 d:1 ------------ BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} N001 ( 0, 0) [001238] ------------ t1238 = PHI_ARG int V07 loc3 u:6 N002 ( 0, 0) [001235] ------------ t1235 = PHI_ARG int V07 loc3 u:1 $c0 /--* t1238 int +--* t1235 int N003 ( 0, 0) [001177] ------------ t1177 = * PHI int /--* t1177 int N005 ( 0, 0) [001178] DA---------- * STORE_LCL_VAR int V07 loc3 d:5 N001 ( 0, 0) [001239] ------------ t1239 = PHI_ARG int V09 loc5 u:5 N002 ( 0, 0) [001236] ------------ t1236 = PHI_ARG int V09 loc5 u:1 /--* t1239 int +--* t1236 int N003 ( 0, 0) [001174] ------------ t1174 = * PHI int /--* t1174 int N005 ( 0, 0) [001175] DA---------- * STORE_LCL_VAR int V09 loc5 d:4 [001367] ------------ IL_OFFSET void IL offset: 0x106 N001 ( 1, 1) [000388] ------------ t388 = LCL_VAR ref V04 loc0 u:1 /--* t388 ref [001446] -c---------- t1446 = * LEA(b+8) ref /--* t1446 ref N002 ( 3, 3) [000389] ---X-------- t389 = * IND int /--* t389 int N004 ( 3, 3) [001316] DA-X-------- * STORE_LCL_VAR int V76 cse11 N005 ( 1, 1) [001317] ------------ t1317 = LCL_VAR int V76 cse11 N007 ( 1, 1) [000387] ------------ t387 = LCL_VAR int V09 loc5 u:4 $3c2 /--* t1317 int +--* t387 int N008 ( 6, 6) [000390] N--X---N-U-- * LE void N009 ( 8, 8) [000391] ---X-------- * JTRUE void ------------ BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} [001368] ------------ IL_OFFSET void IL offset: 0x110 N001 ( 1, 1) [000869] ------------ t869 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000870] ------------ t870 = LCL_VAR int V09 loc5 u:4 (last use) $3c2 /--* t870 int N003 ( 2, 3) [000873] ------------ t873 = * CAST long <- int $326 N004 ( 1, 1) [000880] -c---------- t880 = CNS_INT long 3 $24b /--* t873 long +--* t880 long N005 ( 7, 7) [000881] ------------ t881 = * MUL long $327 /--* t881 long N007 ( 7, 7) [001276] DA---------- * STORE_LCL_VAR long V70 cse5 d:1 N008 ( 1, 1) [001277] ------------ t1277 = LCL_VAR long V70 cse5 u:1 $327 /--* t869 ref +--* t1277 long N014 ( 11, 11) [000878] -------N---- t878 = * LEA(b+(i*8)+16) byref /--* t878 byref N018 ( 23, 23) [001249] DA--G------- * STORE_LCL_VAR byref V65 cse0 d:1 N019 ( 1, 1) [001250] ------------ t1250 = LCL_VAR byref V65 cse0 u:1 /--* t1250 byref N022 ( 25, 25) [000868] -c---------- t868 = * LEA(b+16) byref /--* t868 byref N023 ( 27, 27) [000396] *c-XG------- t396 = * IND int N024 ( 1, 1) [000397] ------------ t397 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t396 int +--* t397 int N025 ( 29, 29) [000398] N--XG--N-U-- * NE void N026 ( 31, 31) [000399] ---XG------- * JTRUE void ------------ BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} [001369] ------------ IL_OFFSET void IL offset: 0x120 N004 ( 1, 1) [000883] ------------ t883 = LCL_VAR ref V04 loc0 u:1 N005 ( 1, 1) [001279] ------------ t1279 = LCL_VAR long V70 cse5 u:1 (last use) $327 /--* t883 ref +--* t1279 long N010 ( 4, 4) [000892] -c---------- t892 = * LEA(b+(i*8)+16) byref /--* t892 byref N013 ( 12, 11) [000897] *---G--N---- t897 = * IND ref /--* t897 ref [001475] ----G------- t1475 = * PUTARG_REG ref REG rdx N014 ( 1, 1) [000418] ------------ t418 = LCL_VAR ref V12 loc8 u:1 $223 /--* t418 ref [001476] ------------ t1476 = * PUTARG_REG ref REG rcx N015 ( 1, 1) [000424] ------------ t424 = LCL_VAR ref V01 arg1 u:1 $101 /--* t424 ref [001477] ------------ t1477 = * PUTARG_REG ref REG r8 N016 ( 1, 1) [000901] ------------ t901 = LCL_VAR ref V12 loc8 u:1 $223 /--* t901 ref N017 ( 3, 2) [000902] #--X-------- t902 = * IND long $463 /--* t902 long N019 ( 4, 3) [000904] -c---------- t904 = * LEA(b+72) long /--* t904 long N020 ( 6, 5) [000905] #--X-------- t905 = * IND long $465 /--* t905 long N022 ( 7, 6) [000907] -c---------- t907 = * LEA(b+32) long /--* t907 long N023 ( 9, 8) [000908] nc-X-------- t908 = * IND long REG NA /--* t1475 ref arg1 in rdx +--* t1476 ref this in rcx +--* t1477 ref arg2 in r8 +--* t908 long control expr N024 ( 43, 32) [000425] --CXG------- t425 = * CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals $581 N025 ( 1, 1) [000426] -c---------- t426 = CNS_INT int 0 $c0 /--* t425 int +--* t426 int N026 ( 45, 34) [000427] J--XG--N---- * NE void $1bd N027 ( 47, 36) [000428] ---XG------- * JTRUE void ------------ BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} [001370] ------------ IL_OFFSET void IL offset: 0x157 N001 ( 1, 1) [001252] ------------ t1252 = LCL_VAR byref V65 cse0 u:1 (last use) $82 /--* t1252 byref N003 ( 2, 2) [000932] -c---------- t932 = * LEA(b+20) byref /--* t932 byref N004 ( 4, 4) [000404] *--XG------- t404 = * IND int /--* t404 int N006 ( 4, 4) [000406] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:5 [001371] ------------ IL_OFFSET void IL offset: 0x166 N001 ( 1, 1) [000407] ------------ t407 = LCL_VAR int V07 loc3 u:5 (last use) $3c1 N002 ( 1, 1) [000408] -c---------- t408 = CNS_INT int 1 $c1 /--* t407 int +--* t408 int N003 ( 3, 3) [000409] ------------ t409 = * ADD int $605 /--* t409 int N005 ( 3, 3) [000411] DA---------- * STORE_LCL_VAR int V07 loc3 d:6 [001372] ------------ IL_OFFSET void IL offset: 0x16a N001 ( 1, 1) [001321] ------------ t1321 = LCL_VAR int V76 cse11 (last use) N002 ( 1, 1) [000412] ------------ t412 = LCL_VAR int V07 loc3 u:6 $605 /--* t1321 int +--* t412 int N003 ( 3, 3) [000415] N------N-U-- * LT void N004 ( 5, 5) [000416] ------------ * JTRUE void ------------ BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} ------------ BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} [001373] ------------ IL_OFFSET void IL offset: 0x137 N001 ( 2, 2) [000429] ------------ t429 = LCL_VAR ubyte V03 arg3 u:1 $140 N003 ( 1, 1) [000430] -c---------- t430 = CNS_INT ubyte 1 $c1 /--* t429 ubyte +--* t430 ubyte N004 ( 5, 6) [000431] N------N-U-- * NE void $1bf N005 ( 7, 8) [000432] ------------ * JTRUE void ------------ BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} [001374] ------------ IL_OFFSET void IL offset: 0x13b N001 ( 1, 1) [001253] ------------ t1253 = LCL_VAR byref V65 cse0 u:1 (last use) $82 /--* t1253 byref N003 ( 2, 2) [000911] ------------ t911 = * LEA(b+8) byref N005 ( 1, 1) [000479] ------------ t479 = LCL_VAR ref V02 arg2 u:1 (last use) $102 /--* t911 byref +--* t479 ref [001375] -A-XG------- * STOREIND ref ------------ BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} [001376] ------------ IL_OFFSET void IL offset: 0x14b N001 ( 2, 2) [000433] ------------ t433 = LCL_VAR ubyte V03 arg3 u:1 (last use) $140 N003 ( 1, 1) [000434] -c---------- t434 = CNS_INT ubyte 2 $c2 /--* t433 ubyte +--* t434 ubyte N004 ( 5, 6) [000435] N------N-U-- * EQ void $600 N005 ( 7, 8) [000436] ------------ * JTRUE void ------------ BB31 [???..???) (return), preds={BB30,BB41} succs={} N001 ( 1, 1) [000437] ------------ t437 = CNS_INT int 0 $c0 /--* t437 int N002 ( 2, 2) [000811] ------------ * RETURN int $1f3 ------------ BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} N001 ( 0, 0) [001229] ------------ t1229 = PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [001218] ------------ t1218 = PHI_ARG int V07 loc3 u:1 $c0 /--* t1229 int +--* t1218 int N003 ( 0, 0) [001207] ------------ t1207 = * PHI int /--* t1207 int N005 ( 0, 0) [001208] DA---------- * STORE_LCL_VAR int V07 loc3 d:3 N001 ( 0, 0) [001230] ------------ t1230 = PHI_ARG int V09 loc5 u:3 N002 ( 0, 0) [001219] ------------ t1219 = PHI_ARG int V09 loc5 u:1 /--* t1230 int +--* t1219 int N003 ( 0, 0) [001204] ------------ t1204 = * PHI int /--* t1204 int N005 ( 0, 0) [001205] DA---------- * STORE_LCL_VAR int V09 loc5 d:2 [001377] ------------ IL_OFFSET void IL offset: 0x177 N001 ( 1, 1) [000063] ------------ t63 = LCL_VAR ref V04 loc0 u:1 /--* t63 ref [001448] -c---------- t1448 = * LEA(b+8) ref /--* t1448 ref N002 ( 3, 3) [000064] ---X-------- t64 = * IND int /--* t64 int N004 ( 3, 3) [001323] DA-X-------- * STORE_LCL_VAR int V76 cse11 N005 ( 1, 1) [001324] ------------ t1324 = LCL_VAR int V76 cse11 N007 ( 1, 1) [000062] ------------ t62 = LCL_VAR int V09 loc5 u:2 $3c4 /--* t1324 int +--* t62 int N008 ( 6, 6) [000065] N--X---N-U-- * LE void N009 ( 8, 8) [000066] ---X-------- * JTRUE void ------------ BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} [001378] ------------ IL_OFFSET void IL offset: 0x17e N001 ( 1, 1) [000949] ------------ t949 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [000950] ------------ t950 = LCL_VAR int V09 loc5 u:2 (last use) $3c4 /--* t950 int N003 ( 2, 3) [000953] ------------ t953 = * CAST long <- int $6e1 N004 ( 1, 1) [000960] -c---------- t960 = CNS_INT long 3 $24b /--* t953 long +--* t960 long N005 ( 7, 7) [000961] ------------ t961 = * MUL long $6e2 /--* t961 long N007 ( 7, 7) [001281] DA---------- * STORE_LCL_VAR long V71 cse6 d:1 N008 ( 1, 1) [001282] ------------ t1282 = LCL_VAR long V71 cse6 u:1 $6e2 /--* t949 ref +--* t1282 long N014 ( 11, 11) [000958] -------N---- t958 = * LEA(b+(i*8)+16) byref /--* t958 byref N018 ( 23, 23) [001255] DA--G------- * STORE_LCL_VAR byref V66 cse1 d:1 N019 ( 1, 1) [001256] ------------ t1256 = LCL_VAR byref V66 cse1 u:1 /--* t1256 byref N022 ( 25, 25) [000948] -c---------- t948 = * LEA(b+16) byref /--* t948 byref N023 ( 27, 27) [000212] *c-XG------- t212 = * IND int N024 ( 1, 1) [000213] ------------ t213 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t212 int +--* t213 int N025 ( 29, 29) [000214] N--XG--N-U-- * NE void N026 ( 31, 31) [000215] ---XG------- * JTRUE void ------------ BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} [001379] ------------ IL_OFFSET void IL offset: 0x18e N001 ( 1, 1) [000963] ------------ t963 = LCL_VAR ref V04 loc0 u:1 N002 ( 1, 1) [001284] ------------ t1284 = LCL_VAR long V71 cse6 u:1 (last use) $6e2 /--* t963 ref +--* t1284 long N007 ( 4, 4) [000972] -c---------- t972 = * LEA(b+(i*8)+16) byref /--* t972 byref N010 ( 12, 11) [000977] *---G--N---- t977 = * IND ref /--* t977 ref N012 ( 12, 11) [000246] DA--G------- * STORE_LCL_VAR ref V17 tmp3 d:1 [001380] ------------ IL_OFFSET void IL offset: 0x18e N001 ( 1, 1) [000241] !----------- t241 = LCL_VAR ref V00 this u:1 $100 /--* t241 ref N002 ( 3, 2) [000242] #----O------ t242 = * IND long $2e8 /--* t242 long N004 ( 3, 3) [000244] DA---O------ * STORE_LCL_VAR long V16 tmp2 d:1 N001 ( 1, 1) [000249] ------------ t249 = LCL_VAR long V16 tmp2 u:1 $2e7 /--* t249 long N003 ( 2, 2) [000251] -c---------- t251 = * LEA(b+56) long /--* t251 long N004 ( 4, 4) [000252] #----------- t252 = * IND long $2e9 /--* t252 long N005 ( 7, 6) [000253] #----------- t253 = * IND long $2ea /--* t253 long N007 ( 8, 7) [000255] -c---------- t255 = * LEA(b+48) long /--* t255 long N008 ( 10, 9) [000259] n----------- t259 = * IND long /--* t259 long N010 ( 10, 9) [001261] DA---------- * STORE_LCL_VAR long V67 cse2 d:1 N011 ( 1, 1) [001262] ------------ t1262 = LCL_VAR long V67 cse2 u:1 N013 ( 1, 1) [000262] -c---------- t262 = CNS_INT long 0 $243 /--* t1262 long +--* t262 long N014 ( 13, 12) [000263] J------N---- * EQ void N015 ( 15, 14) [001163] ------------ * JTRUE void ------------ BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} N001 ( 1, 1) [001264] ------------ t1264 = LCL_VAR long V67 cse2 u:1 (last use) /--* t1264 long N003 ( 1, 3) [001165] DA---------- * STORE_LCL_VAR long V19 tmp5 d:3 ------------ BB36 [???..???), preds={BB34} succs={BB37} N003 ( 1, 1) [000248] ------?----- t248 = LCL_VAR long V16 tmp2 u:1 (last use) $2e7 /--* t248 long [001478] ------------ t1478 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000260] H-----?----- t260 = CNS_INT(h) long 0xd1ffab1e global ptr $63 /--* t260 long [001479] ------------ t1479 = * PUTARG_REG long REG rdx /--* t1478 long arg0 in rcx +--* t1479 long arg1 in rdx N005 ( 17, 18) [000261] --C-G-?----- t261 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $6e7 /--* t261 long N007 ( 17, 18) [001167] DA--G------- * STORE_LCL_VAR long V19 tmp5 d:2 ------------ BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} N001 ( 0, 0) [001234] ------------ t1234 = PHI_ARG long V19 tmp5 u:3 N002 ( 0, 0) [001233] ------------ t1233 = PHI_ARG long V19 tmp5 u:2 $6e7 /--* t1234 long +--* t1233 long N003 ( 0, 0) [001210] ------------ t1210 = * PHI long /--* t1210 long N005 ( 0, 0) [001211] DA---------- * STORE_LCL_VAR long V19 tmp5 d:1 N005 ( 1, 1) [000234] ------------ t234 = LCL_VAR ref V05 loc1 u:1 /--* t234 ref [001480] ------------ t1480 = * PUTARG_REG ref REG rcx N006 ( 1, 1) [000980] ------------ t980 = LCL_VAR long V19 tmp5 u:1 r11 REG r11 $349 /--* t980 long [001481] ------------ t1481 = * PUTARG_REG long REG r11 N007 ( 1, 1) [000247] ------------ t247 = LCL_VAR ref V17 tmp3 u:1 (last use) /--* t247 ref [001482] ------------ t1482 = * PUTARG_REG ref REG rdx N008 ( 1, 1) [000258] ------------ t258 = LCL_VAR ref V01 arg1 u:1 $101 /--* t258 ref [001483] ------------ t1483 = * PUTARG_REG ref REG r8 N009 ( 1, 1) [000279] ------------ t279 = LCL_VAR long V19 tmp5 u:1 (last use) $349 /--* t279 long [001484] Dc---------- t1484 = * IND long REG NA /--* t1480 ref this in rcx +--* t1481 long arg1 in r11 +--* t1482 ref arg2 in rdx +--* t1483 ref arg3 in r8 +--* t1484 long calli tgt N010 ( 28, 14) [000280] --CXG------- t280 = * CALL ind stub int $1ef N011 ( 1, 1) [000281] -c---------- t281 = CNS_INT int 0 $c0 /--* t280 int +--* t281 int N012 ( 30, 16) [000282] J--XG--N---- * EQ void $817 N013 ( 32, 18) [000283] ---XG------- * JTRUE void ------------ BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} [001381] ------------ IL_OFFSET void IL offset: 0x1a4 N001 ( 2, 2) [000284] ------------ t284 = LCL_VAR ubyte V03 arg3 u:1 $140 N003 ( 1, 1) [000285] -c---------- t285 = CNS_INT ubyte 1 $c1 /--* t284 ubyte +--* t285 ubyte N004 ( 5, 6) [000286] N------N-U-- * NE void $1bf N005 ( 7, 8) [000287] ------------ * JTRUE void ------------ BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} [001382] ------------ IL_OFFSET void IL offset: 0x1a8 N001 ( 1, 1) [001258] ------------ t1258 = LCL_VAR byref V66 cse1 u:1 (last use) $91 /--* t1258 byref N003 ( 2, 2) [000987] ------------ t987 = * LEA(b+8) byref N005 ( 1, 1) [000334] ------------ t334 = LCL_VAR ref V02 arg2 u:1 (last use) $102 /--* t987 byref +--* t334 ref [001383] -A-XG------- * STOREIND ref ------------ BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} [001384] ------------ IL_OFFSET void IL offset: 0x1b8 N001 ( 2, 2) [000288] ------------ t288 = LCL_VAR ubyte V03 arg3 u:1 (last use) $140 N003 ( 1, 1) [000289] -c---------- t289 = CNS_INT ubyte 2 $c2 /--* t288 ubyte +--* t289 ubyte N004 ( 5, 6) [000290] N------N-U-- * EQ void $600 N005 ( 7, 8) [000291] ------------ * JTRUE void ------------ BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} ------------ BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} [001385] ------------ IL_OFFSET void IL offset: 0x1c4 N001 ( 1, 1) [001259] ------------ t1259 = LCL_VAR byref V66 cse1 u:1 (last use) $91 /--* t1259 byref N003 ( 2, 2) [001009] -c---------- t1009 = * LEA(b+20) byref /--* t1009 byref N004 ( 4, 4) [000220] *--XG------- t220 = * IND int /--* t220 int N006 ( 4, 4) [000222] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:3 [001386] ------------ IL_OFFSET void IL offset: 0x1d3 N001 ( 1, 1) [000223] ------------ t223 = LCL_VAR int V07 loc3 u:3 (last use) $3c3 N002 ( 1, 1) [000224] -c---------- t224 = CNS_INT int 1 $c1 /--* t223 int +--* t224 int N003 ( 3, 3) [000225] ------------ t225 = * ADD int $81a /--* t225 int N005 ( 3, 3) [000227] DA---------- * STORE_LCL_VAR int V07 loc3 d:4 [001387] ------------ IL_OFFSET void IL offset: 0x1d7 N001 ( 1, 1) [001328] ------------ t1328 = LCL_VAR int V76 cse11 (last use) N002 ( 1, 1) [000228] ------------ t228 = LCL_VAR int V07 loc3 u:4 $81a /--* t1328 int +--* t228 int N003 ( 3, 3) [000231] N------N-U-- * LT void N004 ( 5, 5) [000232] ------------ * JTRUE void ------------ BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} ------------ BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} N001 ( 0, 0) [001237] ------------ t1237 = PHI_ARG int V07 loc3 u:5 $3c1 N002 ( 0, 0) [001228] ------------ t1228 = PHI_ARG int V07 loc3 u:3 $3c3 /--* t1237 int +--* t1228 int N003 ( 0, 0) [001180] ------------ t1180 = * PHI int /--* t1180 int N005 ( 0, 0) [001181] DA---------- * STORE_LCL_VAR int V07 loc3 d:2 [001388] ------------ IL_OFFSET void IL offset: 0x1e4 N001 ( 1, 1) [000067] ------------ t67 = LCL_VAR ref V00 this u:1 $100 /--* t67 ref N003 ( 2, 2) [001025] -c---------- t1025 = * LEA(b+64) byref /--* t1025 byref N004 ( 4, 4) [000068] nc--GO------ t68 = * IND int N005 ( 1, 1) [000069] -c---------- t69 = CNS_INT int 0 $c0 /--* t68 int +--* t69 int N006 ( 6, 6) [000070] J---GO-N---- * LE void N007 ( 8, 8) [000071] ----GO------ * JTRUE void ------------ BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} [001389] ------------ IL_OFFSET void IL offset: 0x1ed N001 ( 1, 1) [000171] ------------ t171 = LCL_VAR ref V00 this u:1 $100 /--* t171 ref N003 ( 2, 2) [001027] -c---------- t1027 = * LEA(b+60) byref /--* t1027 byref N004 ( 4, 4) [000172] n---GO------ t172 = * IND int /--* t172 int N006 ( 8, 7) [001306] DA--GO------ * STORE_LCL_VAR int V74 cse9 d:1 N007 ( 3, 2) [001307] ------------ t1307 = LCL_VAR int V74 cse9 u:1 /--* t1307 int N010 ( 15, 12) [000174] DA--GO------ * STORE_LCL_VAR int V10 loc6 d:3 [001390] ------------ IL_OFFSET void IL offset: 0x1f5 N001 ( 3, 2) [001309] ------------ t1309 = LCL_VAR int V74 cse9 u:1 (last use) /--* t1309 int N003 ( 3, 3) [001032] DA--G------- * STORE_LCL_VAR int V62 tmp48 d:1 N004 ( 1, 1) [001033] ------------ t1033 = LCL_VAR int V62 tmp48 u:1 N005 ( 1, 1) [001329] ------------ t1329 = LCL_VAR int V76 cse11 /--* t1033 int +--* t1329 int N006 ( 6, 9) [001036] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void N007 ( 1, 1) [001030] ------------ t1030 = LCL_VAR ref V04 loc0 u:1 N008 ( 1, 1) [001034] ------------ t1034 = LCL_VAR int V62 tmp48 u:1 (last use) /--* t1034 int N009 ( 2, 3) [001037] ------------ t1037 = * CAST long <- int N010 ( 1, 1) [001047] -c---------- t1047 = CNS_INT long 3 $24b /--* t1037 long +--* t1047 long N011 ( 7, 7) [001048] ------------ t1048 = * MUL long /--* t1030 ref +--* t1048 long N022 ( 31, 34) [001029] -c---------- t1029 = * LEA(b+(i*8)+36) byref /--* t1029 byref N023 ( 33, 36) [000181] *--XG------- t181 = * IND int /--* t181 int N024 ( 34, 37) [001050] ---XG------- t1050 = * NEG int N025 ( 1, 1) [000175] -c---------- t175 = CNS_INT int -3 $e1 /--* t1050 int +--* t175 int N026 ( 36, 39) [000182] ---XG------- t182 = * ADD int N027 ( 1, 1) [000183] -c---------- t183 = CNS_INT int -1 $c4 /--* t182 int +--* t183 int N028 ( 41, 41) [000184] ---XG------- t184 = * GE int /--* t184 int N030 ( 45, 44) [000688] DA-XG------- * STORE_LCL_VAR int V49 tmp35 d:1 [001391] ------------ IL_OFFSET void IL offset: 0x1f5 N001 ( 1, 1) [001300] ------------ t1300 = LCL_VAR ref V73 cse8 u:1 (last use) $105 /--* t1300 ref N003 ( 5, 4) [000698] DA--G------- * STORE_LCL_VAR ref V50 tmp36 d:1 [001392] ------------ IL_OFFSET void IL offset: 0x1f5 N001 ( 3, 2) [000690] ------------ t690 = LCL_VAR int V49 tmp35 u:1 (last use) N002 ( 1, 1) [000691] -c---------- t691 = CNS_INT int 0 $c0 /--* t690 int +--* t691 int N003 ( 5, 4) [000692] J------N---- * NE void N004 ( 7, 6) [000693] ------------ * JTRUE void ------------ BB46 [1F5..1F6), preds={BB45} succs={BB47} [001393] ------------ IL_OFFSET void IL offset: 0x1f5 N003 ( 2, 10) [001051] H----------- t1051 = CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" $5e /--* t1051 long N004 ( 4, 12) [001052] #---G------- t1052 = * IND ref $114 /--* t1052 ref [001485] ----G------- t1485 = * PUTARG_REG ref REG rcx N005 ( 3, 2) [000695] ------------ t695 = LCL_VAR ref V50 tmp36 u:1 (last use) $105 /--* t695 ref [001486] ------------ t1486 = * PUTARG_REG ref REG rdx /--* t1485 ref arg0 in rcx +--* t1486 ref arg1 in rdx N006 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} [001394] ------------ IL_OFFSET void IL offset: 0x219 N001 ( 1, 1) [000190] ------------ t190 = LCL_VAR ref V00 this u:1 $100 /--* t190 ref N003 ( 2, 2) [001056] -c---------- t1056 = * LEA(b+60) byref N005 ( 1, 1) [000193] ------------ t193 = LCL_VAR ref V00 this u:1 $100 /--* t193 ref N007 ( 2, 2) [001075] -c---------- t1075 = * LEA(b+60) byref /--* t1075 byref N008 ( 4, 4) [000194] n---GO------ t194 = * IND int /--* t194 int N010 ( 4, 4) [001061] DA--GO------ * STORE_LCL_VAR int V63 tmp49 d:1 N011 ( 1, 1) [001062] ------------ t1062 = LCL_VAR int V63 tmp49 u:1 N012 ( 1, 1) [001330] ------------ t1330 = LCL_VAR int V76 cse11 (last use) /--* t1062 int +--* t1330 int N013 ( 6, 9) [001065] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void N014 ( 1, 1) [001059] ------------ t1059 = LCL_VAR ref V04 loc0 u:1 N015 ( 1, 1) [001063] ------------ t1063 = LCL_VAR int V63 tmp49 u:1 (last use) /--* t1063 int N016 ( 2, 3) [001066] ------------ t1066 = * CAST long <- int N017 ( 1, 1) [001076] -c---------- t1076 = CNS_INT long 3 $24b /--* t1066 long +--* t1076 long N018 ( 7, 7) [001077] ------------ t1077 = * MUL long /--* t1059 ref +--* t1077 long N029 ( 32, 35) [001058] -c---------- t1058 = * LEA(b+(i*8)+36) byref /--* t1058 byref N030 ( 34, 37) [000197] *--XGO------ t197 = * IND int /--* t197 int N031 ( 35, 38) [001079] ---XGO------ t1079 = * NEG int N032 ( 1, 1) [000191] -c---------- t191 = CNS_INT int -3 $e1 /--* t1079 int +--* t191 int N033 ( 37, 40) [000198] ---XGO------ t198 = * ADD int /--* t1056 byref +--* t198 int [001395] -A-XGO------ * STOREIND int [001396] ------------ IL_OFFSET void IL offset: 0x233 N001 ( 1, 1) [000202] -c---------- t202 = LCL_VAR ref V00 this u:1 $100 /--* t202 ref N003 ( 2, 2) [001083] -c---------- t1083 = * LEA(b+64) byref /--* t1083 byref N004 ( 4, 4) [000203] nc--GO------ t203 = * IND int N005 ( 1, 1) [000204] -c---------- t204 = CNS_INT int -1 $c4 /--* t203 int +--* t204 int N006 ( 6, 6) [000205] -c--GO------ t205 = * ADD int N007 ( 1, 1) [000201] ------------ t201 = LCL_VAR ref V00 this u:1 $100 /--* t201 ref N009 ( 2, 2) [001081] -c---------- t1081 = * LEA(b+64) byref /--* t1081 byref +--* t205 int [001397] -A--GO------ * STOREIND int ------------ BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} [001398] ------------ IL_OFFSET void IL offset: 0x243 N001 ( 1, 1) [000072] ------------ t72 = LCL_VAR ref V00 this u:1 $100 /--* t72 ref N003 ( 2, 2) [001085] -c---------- t1085 = * LEA(b+56) byref /--* t1085 byref N004 ( 4, 4) [000073] n---GO------ t73 = * IND int /--* t73 int N006 ( 8, 7) [001311] DA--GO------ * STORE_LCL_VAR int V75 cse10 d:1 N007 ( 3, 2) [001312] ------------ t1312 = LCL_VAR int V75 cse10 u:1 /--* t1312 int N010 ( 15, 12) [000075] DA--GO------ * STORE_LCL_VAR int V13 loc9 d:1 [001399] ------------ IL_OFFSET void IL offset: 0x24b N001 ( 1, 1) [001331] ------------ t1331 = LCL_VAR int V76 cse11 (last use) N002 ( 3, 2) [000076] ------------ t76 = LCL_VAR int V13 loc9 u:1 /--* t1331 int +--* t76 int N003 ( 5, 4) [000079] N------N-U-- * NE void N004 ( 7, 6) [000080] ------------ * JTRUE void ------------ BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} [001400] ------------ IL_OFFSET void IL offset: 0x252 N003 ( 3, 2) [001314] ------------ t1314 = LCL_VAR int V75 cse10 u:1 (last use) /--* t1314 int [001487] ------------ t1487 = * PUTARG_REG int REG rcx /--* t1487 int arg0 in rcx N004 ( 17, 8) [000702] --CXG------- t702 = * CALL int System.Collections.HashHelpers.ExpandPrime $1d7 /--* t702 int N006 ( 21, 11) [001090] DA-XG-----L- * STORE_LCL_VAR int V64 tmp50 d:1 N008 ( 3, 2) [001091] ------------ t1091 = LCL_VAR int V64 tmp50 u:1 (last use) $1d7 /--* t1091 int [001488] ------------ t1488 = * PUTARG_REG int REG rdx N009 ( 1, 1) [000163] ------------ t163 = LCL_VAR ref V00 this u:1 $100 /--* t163 ref [001489] ------------ t1489 = * PUTARG_REG ref REG rcx N010 ( 1, 1) [000704] ------------ t704 = CNS_INT int 0 $c0 /--* t704 int [001490] ------------ t1490 = * PUTARG_REG int REG r8 /--* t1488 int arg1 in rdx +--* t1489 ref this in rcx +--* t1490 int arg2 in r8 N011 ( 43, 24) [000705] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void [001401] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [000165] ------------ t165 = LCL_VAR ref V00 this u:1 $100 /--* t165 ref N003 ( 2, 2) [001095] -c---------- t1095 = * LEA(b+8) byref /--* t1095 byref N004 ( 4, 4) [000709] n---GO------ t709 = * IND ref /--* t709 ref N006 ( 8, 7) [000711] DA--GO------ * STORE_LCL_VAR ref V52 tmp38 d:1 [001402] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000713] ------------ t713 = LCL_VAR ref V52 tmp38 u:1 /--* t713 ref [001450] -c---------- t1450 = * LEA(b+8) ref /--* t1450 ref N002 ( 5, 4) [000714] ---X-------- t714 = * IND int /--* t714 int N004 ( 9, 7) [001286] DA-X-------- * STORE_LCL_VAR int V72 cse7 d:1 N005 ( 3, 2) [001287] ------------ t1287 = LCL_VAR int V72 cse7 u:1 /--* t1287 int N008 ( 12, 9) [000760] DA-X-------- * STORE_LCL_VAR int V53 tmp39 d:1 [001403] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [000715] ------------ t715 = LCL_VAR ref V00 this u:1 $100 /--* t715 ref N003 ( 2, 2) [001097] -c---------- t1097 = * LEA(b+48) byref /--* t1097 byref N004 ( 4, 4) [000716] n---GO------ t716 = * IND long /--* t716 long N006 ( 8, 7) [000762] DA--GO------ * STORE_LCL_VAR long V54 tmp40 d:1 [001404] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [000728] ------------ t728 = LCL_VAR int V53 tmp39 u:1 N002 ( 1, 4) [000729] -c---------- t729 = CNS_INT int 0x7FFFFFFF $ce /--* t728 int +--* t729 int N003 ( 6, 6) [000730] N--------U-- t730 = * LE int /--* t730 int N005 ( 10, 9) [000773] DA---------- * STORE_LCL_VAR int V56 tmp42 d:1 [001405] ------------ IL_OFFSET void IL offset: 0x258 [001406] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [001302] ------------ t1302 = LCL_VAR ref V73 cse8 u:1 $105 /--* t1302 ref N003 ( 5, 4) [000785] DA--G------- * STORE_LCL_VAR ref V58 tmp44 d:1 [001407] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000775] ------------ t775 = LCL_VAR int V56 tmp42 u:1 (last use) N002 ( 1, 1) [000776] -c---------- t776 = CNS_INT int 0 $c0 /--* t775 int +--* t776 int N003 ( 5, 4) [000777] J------N---- * NE void N004 ( 7, 6) [000778] ------------ * JTRUE void ------------ BB50 [258..259), preds={BB49} succs={BB51} [001408] ------------ IL_OFFSET void IL offset: 0x258 N003 ( 3, 2) [000779] ------------ t779 = LCL_VAR ref V58 tmp44 u:1 $105 /--* t779 ref [001491] ------------ t1491 = * PUTARG_REG ref REG rcx N004 ( 3, 2) [000780] ------------ t780 = LCL_VAR ref V58 tmp44 u:1 (last use) $105 /--* t780 ref [001492] ------------ t1492 = * PUTARG_REG ref REG rdx /--* t1491 ref arg0 in rcx +--* t1492 ref arg1 in rdx N005 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} [001409] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000735] ------------ t735 = LCL_VAR long V54 tmp40 u:1 (last use) N002 ( 1, 1) [000166] ------------ t166 = LCL_VAR int V06 loc2 u:1 $3c0 /--* t166 int N003 ( 2, 3) [000736] ---------U-- t736 = * CAST long <- ulong <- uint $310 /--* t735 long +--* t736 long N004 ( 9, 8) [000737] ------------ t737 = * MUL long N005 ( 1, 1) [000738] -c---------- t738 = CNS_INT int 32 $d2 /--* t737 long +--* t738 int N006 ( 11, 10) [000739] ------------ t739 = * RSZ long N007 ( 1, 1) [000741] -c---------- t741 = CNS_INT long 1 $247 /--* t739 long +--* t741 long N008 ( 13, 12) [000742] ------------ t742 = * ADD long N009 ( 1, 1) [000743] ------------ t743 = LCL_VAR int V53 tmp39 u:1 /--* t743 int N010 ( 2, 3) [000744] ---------U-- t744 = * CAST long <- ulong <- uint /--* t742 long +--* t744 long N011 ( 19, 18) [000745] ------------ t745 = * MUL long N012 ( 1, 1) [000746] -c---------- t746 = CNS_INT int 32 $d2 /--* t745 long +--* t746 int N013 ( 21, 20) [000747] ------------ t747 = * RSZ long /--* t747 long N014 ( 22, 22) [000748] ------------ t748 = * CAST int <- uint <- long /--* t748 int N016 ( 26, 25) [000750] DA---------- * STORE_LCL_VAR int V55 tmp41 d:1 [001410] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [000752] ------------ t752 = LCL_VAR int V06 loc2 u:1 $3c0 N002 ( 1, 1) [000753] ------------ t753 = LCL_VAR int V53 tmp39 u:1 (last use) /--* t752 int +--* t753 int N003 ( 22, 5) [000754] ---X-------- t754 = * UMOD int N004 ( 3, 2) [000751] ------------ t751 = LCL_VAR int V55 tmp41 u:1 /--* t754 int +--* t751 int N005 ( 29, 8) [000755] ---X-------- t755 = * EQ int /--* t755 int N007 ( 33, 11) [000796] DA-X-------- * STORE_LCL_VAR int V59 tmp45 d:1 [001411] ------------ IL_OFFSET void IL offset: 0x258 [001412] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 1, 1) [001304] ------------ t1304 = LCL_VAR ref V73 cse8 u:1 (last use) $105 /--* t1304 ref N003 ( 5, 4) [000808] DA--G------- * STORE_LCL_VAR ref V61 tmp47 d:1 [001413] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000798] ------------ t798 = LCL_VAR int V59 tmp45 u:1 (last use) N002 ( 1, 1) [000799] -c---------- t799 = CNS_INT int 0 $c0 /--* t798 int +--* t799 int N003 ( 5, 4) [000800] J------N---- * NE void N004 ( 7, 6) [000801] ------------ * JTRUE void ------------ BB52 [258..259), preds={BB51} succs={BB53} [001414] ------------ IL_OFFSET void IL offset: 0x258 N003 ( 3, 2) [000802] ------------ t802 = LCL_VAR ref V61 tmp47 u:1 $105 /--* t802 ref [001493] ------------ t1493 = * PUTARG_REG ref REG rcx N004 ( 3, 2) [000803] ------------ t803 = LCL_VAR ref V61 tmp47 u:1 (last use) $105 /--* t803 ref [001494] ------------ t1494 = * PUTARG_REG ref REG rdx /--* t1493 ref arg0 in rcx +--* t1494 ref arg1 in rdx N005 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail $VN.Void ------------ BB53 [258..259), preds={BB51,BB52} succs={BB54} [001415] ------------ IL_OFFSET void IL offset: 0x258 N001 ( 3, 2) [000758] ------------ t758 = LCL_VAR int V55 tmp41 u:1 N002 ( 3, 2) [001289] ------------ t1289 = LCL_VAR int V72 cse7 u:1 (last use) /--* t758 int +--* t1289 int N003 ( 10, 11) [001105] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void N004 ( 3, 2) [001102] ------------ t1102 = LCL_VAR ref V52 tmp38 u:1 (last use) N005 ( 3, 2) [001103] ------------ t1103 = LCL_VAR int V55 tmp41 u:1 (last use) /--* t1103 int N006 ( 4, 4) [001106] ------------ t1106 = * CAST long <- int /--* t1102 ref +--* t1106 long N011 ( 9, 8) [001111] -------N---- t1111 = * LEA(b+(i*4)+16) byref /--* t1111 byref N016 ( 33, 31) [000722] DA-XG------- * STORE_LCL_VAR byref V51 tmp37 d:1 N001 ( 3, 2) [000723] ------------ t723 = LCL_VAR byref V51 tmp37 u:1 (last use) $87 /--* t723 byref N003 ( 7, 5) [000170] DA---------- * STORE_LCL_VAR byref V08 loc4 d:4 ------------ BB54 [261..276), preds={BB48,BB53} succs={BB55} N001 ( 0, 0) [001224] ------------ t1224 = PHI_ARG byref V08 loc4 u:4 $87 N002 ( 0, 0) [001220] ------------ t1220 = PHI_ARG byref V08 loc4 u:1 $81 /--* t1224 byref +--* t1220 byref N003 ( 0, 0) [001192] ------------ t1192 = * PHI byref /--* t1192 byref N005 ( 0, 0) [001193] DA---------- * STORE_LCL_VAR byref V08 loc4 d:3 [001416] ------------ IL_OFFSET void IL offset: 0x261 N001 ( 3, 2) [000081] ------------ t81 = LCL_VAR int V13 loc9 u:1 (last use) /--* t81 int N003 ( 7, 5) [000083] DA---------- * STORE_LCL_VAR int V10 loc6 d:2 [001417] ------------ IL_OFFSET void IL offset: 0x265 N001 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V10 loc6 u:2 N002 ( 1, 1) [000086] -c---------- t86 = CNS_INT int 1 $c1 /--* t85 int +--* t86 int N003 ( 5, 4) [000087] ------------ t87 = * ADD int N004 ( 1, 1) [000084] ------------ t84 = LCL_VAR ref V00 this u:1 $100 /--* t84 ref N006 ( 2, 2) [001115] -c---------- t1115 = * LEA(b+56) byref /--* t1115 byref +--* t87 int [001418] -A--GO------ * STOREIND int [001419] ------------ IL_OFFSET void IL offset: 0x26f N001 ( 1, 1) [000090] ------------ t90 = LCL_VAR ref V00 this u:1 $100 /--* t90 ref N003 ( 2, 2) [001117] -c---------- t1117 = * LEA(b+16) byref /--* t1117 byref N004 ( 4, 4) [000091] n---GO------ t91 = * IND ref /--* t91 ref N006 ( 4, 4) [000093] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:3 ------------ BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} N001 ( 0, 0) [001225] ------------ t1225 = PHI_ARG byref V08 loc4 u:1 $81 N002 ( 0, 0) [001221] ------------ t1221 = PHI_ARG byref V08 loc4 u:3 $780 /--* t1225 byref +--* t1221 byref N003 ( 0, 0) [001195] ------------ t1195 = * PHI byref /--* t1195 byref N005 ( 0, 0) [001196] DA---------- * STORE_LCL_VAR byref V08 loc4 d:2 N001 ( 0, 0) [001226] ------------ t1226 = PHI_ARG ref V04 loc0 u:1 N002 ( 0, 0) [001222] ------------ t1222 = PHI_ARG ref V04 loc0 u:3 /--* t1226 ref +--* t1222 ref N003 ( 0, 0) [001189] ------------ t1189 = * PHI ref /--* t1189 ref N005 ( 0, 0) [001190] DA---------- * STORE_LCL_VAR ref V04 loc0 d:2 N001 ( 0, 0) [001227] ------------ t1227 = PHI_ARG int V10 loc6 u:3 N002 ( 0, 0) [001223] ------------ t1223 = PHI_ARG int V10 loc6 u:2 /--* t1227 int +--* t1223 int N003 ( 0, 0) [001186] ------------ t1186 = * PHI int /--* t1186 int N005 ( 0, 0) [001187] DA---------- * STORE_LCL_VAR int V10 loc6 d:1 [001420] ------------ IL_OFFSET void IL offset: 0x276 N001 ( 3, 2) [000095] ------------ t95 = LCL_VAR int V10 loc6 u:1 $3cc N002 ( 1, 1) [000094] ------------ t94 = LCL_VAR ref V04 loc0 u:2 $684 /--* t94 ref [001452] -c---------- t1452 = * LEA(b+8) ref /--* t1452 ref N003 ( 3, 3) [001120] -c-X-------- t1120 = * IND int $73d /--* t95 int +--* t1120 int N004 ( 10, 12) [001121] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void $7cd N005 ( 1, 1) [001118] ------------ t1118 = LCL_VAR ref V04 loc0 u:2 $684 N006 ( 3, 2) [001119] ------------ t1119 = LCL_VAR int V10 loc6 u:1 $3cc /--* t1119 int N007 ( 4, 4) [001122] ------------ t1122 = * CAST long <- int $6dc N008 ( 1, 1) [001129] -c---------- t1129 = CNS_INT long 3 $24b /--* t1122 long +--* t1129 long N009 ( 9, 8) [001130] ------------ t1130 = * MUL long $6dd /--* t1118 ref +--* t1130 long N014 ( 12, 11) [001127] -------N---- t1127 = * LEA(b+(i*8)+16) byref /--* t1127 byref N019 ( 39, 38) [000099] DA-XG------- * STORE_LCL_VAR byref V11 loc7 d:1 [001421] ------------ IL_OFFSET void IL offset: 0x280 N001 ( 3, 2) [000100] ------------ t100 = LCL_VAR byref V11 loc7 u:1 $8c /--* t100 byref N003 ( 4, 3) [001133] -c---------- t1133 = * LEA(b+16) byref N005 ( 1, 1) [000101] ------------ t101 = LCL_VAR int V06 loc2 u:1 (last use) $3c0 /--* t1133 byref +--* t101 int [001422] -A-XG------- * STOREIND int [001423] ------------ IL_OFFSET void IL offset: 0x288 N001 ( 3, 2) [000105] ------------ t105 = LCL_VAR byref V08 loc4 u:2 $781 /--* t105 byref N002 ( 6, 4) [000106] *--XG------- t106 = * IND int N003 ( 1, 1) [000107] -c---------- t107 = CNS_INT int -1 $c4 /--* t106 int +--* t107 int N004 ( 8, 6) [000108] ---XG------- t108 = * ADD int N005 ( 3, 2) [000104] ------------ t104 = LCL_VAR byref V11 loc7 u:1 $8c /--* t104 byref N007 ( 4, 3) [001135] -c---------- t1135 = * LEA(b+20) byref /--* t1135 byref +--* t108 int [001424] -A-XGO------ * STOREIND int [001425] ------------ IL_OFFSET void IL offset: 0x294 N001 ( 3, 2) [000111] ------------ t111 = LCL_VAR byref V11 loc7 u:1 Zero Fseq[key] $8f N003 ( 1, 1) [000112] ------------ t112 = LCL_VAR ref V01 arg1 u:1 (last use) $101 /--* t111 byref +--* t112 ref [001426] -A-XG------- * STOREIND ref [001427] ------------ IL_OFFSET void IL offset: 0x29c N001 ( 3, 2) [000115] ------------ t115 = LCL_VAR byref V11 loc7 u:1 (last use) $8c /--* t115 byref N003 ( 4, 3) [001137] ------------ t1137 = * LEA(b+8) byref N005 ( 1, 1) [000116] ------------ t116 = LCL_VAR ref V02 arg2 u:1 (last use) $102 /--* t1137 byref +--* t116 ref [001428] -A--GO------ * STOREIND ref [001429] ------------ IL_OFFSET void IL offset: 0x2a4 N001 ( 3, 2) [000120] ------------ t120 = LCL_VAR int V10 loc6 u:1 (last use) $3cc N002 ( 1, 1) [000121] -c---------- t121 = CNS_INT int 1 $c1 /--* t120 int +--* t121 int N003 ( 5, 4) [000122] ------------ t122 = * ADD int $804 N004 ( 3, 2) [000119] ------------ t119 = LCL_VAR byref V08 loc4 u:2 (last use) $781 /--* t119 byref +--* t122 int [001430] -A--GO------ * STOREIND int [001431] ------------ IL_OFFSET void IL offset: 0x2ab N001 ( 1, 1) [000126] -c---------- t126 = LCL_VAR ref V00 this u:1 $100 /--* t126 ref N003 ( 2, 2) [001141] -c---------- t1141 = * LEA(b+68) byref /--* t1141 byref N004 ( 4, 4) [000127] nc--GO------ t127 = * IND int N005 ( 1, 1) [000128] -c---------- t128 = CNS_INT int 1 $c1 /--* t127 int +--* t128 int N006 ( 6, 6) [000129] -c--GO------ t129 = * ADD int N007 ( 1, 1) [000125] ------------ t125 = LCL_VAR ref V00 this u:1 $100 /--* t125 ref N009 ( 2, 2) [001139] -c---------- t1139 = * LEA(b+68) byref /--* t1139 byref +--* t129 int [001432] -A--GO------ * STOREIND int [001433] ------------ IL_OFFSET void IL offset: 0x2ca N001 ( 1, 1) [000145] ------------ t145 = LCL_VAR int V07 loc3 u:2 (last use) $3c5 N002 ( 1, 1) [000146] -c---------- t146 = CNS_INT int 100 $e3 /--* t145 int +--* t146 int N003 ( 3, 3) [000147] N------N-U-- * LE void $80d N004 ( 5, 5) [000148] ------------ * JTRUE void ------------ BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} [001434] ------------ IL_OFFSET void IL offset: 0x2cf N003 ( 1, 1) [000151] ------------ t151 = LCL_VAR ref V05 loc1 u:1 (last use) /--* t151 ref [001495] ------------ t1495 = * PUTARG_REG ref REG rdx N004 ( 2, 10) [000152] H------N---- t152 = CNS_INT(h) long 0xd1ffab1e class $62 /--* t152 long [001496] ------------ t1496 = * PUTARG_REG long REG rcx /--* t1495 ref arg1 in rdx +--* t1496 long arg0 in rcx N005 ( 17, 18) [000153] --C-G------- t153 = * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS N006 ( 1, 1) [000154] -c---------- t154 = CNS_INT ref null $VN.Null /--* t153 ref +--* t154 ref N007 ( 19, 20) [000155] J---G--N---- * EQ void N008 ( 21, 22) [000156] ----G------- * JTRUE void ------------ BB57 [2D7..2E3), preds={BB56} succs={BB58} [001435] ------------ IL_OFFSET void IL offset: 0x2d7 N004 ( 1, 1) [000158] ------------ t158 = LCL_VAR ref V04 loc0 u:2 (last use) $684 /--* t158 ref [001454] -c---------- t1454 = * LEA(b+8) ref /--* t1454 ref N005 ( 3, 3) [000159] ---X-------- t159 = * IND int $73d /--* t159 int [001497] ---X-------- t1497 = * PUTARG_REG int REG rdx N006 ( 1, 1) [000157] ------------ t157 = LCL_VAR ref V00 this u:1 $100 /--* t157 ref [001498] ------------ t1498 = * PUTARG_REG ref REG rcx N007 ( 1, 1) [000160] ------------ t160 = CNS_INT int 1 $c1 /--* t160 int [001499] ------------ t1499 = * PUTARG_REG int REG r8 /--* t1497 int arg1 in rdx +--* t1498 ref this in rcx +--* t1499 int arg2 in r8 N008 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize $VN.Void ------------ BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} N001 ( 1, 1) [000482] ------------ t482 = CNS_INT int 1 $c1 /--* t482 int N002 ( 2, 2) [000810] ------------ * RETURN int $1f4 ------------ BB59 [008..00E) (throw), preds={BB01} succs={} [001436] ------------ IL_OFFSET void IL offset: 0x8 N002 ( 1, 1) [000532] ------------ t532 = CNS_INT int 4 $c5 /--* t532 int [001500] ------------ t1500 = * PUTARG_REG int REG rcx /--* t1500 int arg0 in rcx N003 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException $VN.Void ------------ BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} [001437] ------------ IL_OFFSET void IL offset: 0x14f N001 ( 1, 1) [000441] !----------- t441 = LCL_VAR ref V00 this u:1 $100 /--* t441 ref N002 ( 3, 2) [000442] #----O------ t442 = * IND long $2e8 /--* t442 long N004 ( 7, 5) [000444] DA---O------ * STORE_LCL_VAR long V26 tmp12 d:1 N001 ( 3, 2) [000446] ------------ t446 = LCL_VAR long V26 tmp12 u:1 $2e7 /--* t446 long N003 ( 4, 3) [000448] -c---------- t448 = * LEA(b+56) long /--* t448 long N004 ( 6, 5) [000449] #----------- t449 = * IND long $2e9 /--* t449 long N005 ( 9, 7) [000450] #----------- t450 = * IND long $2ea /--* t450 long N007 ( 10, 8) [000452] -c---------- t452 = * LEA(b+56) long /--* t452 long N008 ( 12, 10) [000456] nc---------- t456 = * IND long N009 ( 1, 1) [000459] -c---------- t459 = CNS_INT long 0 $243 /--* t456 long +--* t459 long N010 ( 14, 12) [000460] J------N---- * EQ void N011 ( 16, 14) [001158] ------------ * JTRUE void ------------ BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} N001 ( 3, 2) [000466] ------?----- t466 = LCL_VAR long V26 tmp12 u:1 (last use) $2e7 /--* t466 long N003 ( 4, 3) [000465] -c----?----- t465 = * LEA(b+56) long /--* t465 long N004 ( 6, 5) [000464] #-----?----- t464 = * IND long $2e9 /--* t464 long N005 ( 9, 7) [000463] #-----?----- t463 = * IND long $2ea /--* t463 long N007 ( 10, 8) [000462] -c----?----- t462 = * LEA(b+56) long /--* t462 long N008 ( 12, 10) [000461] n-----?----- t461 = * IND long /--* t461 long N010 ( 16, 13) [001160] DA---------- * STORE_LCL_VAR long V28 tmp14 d:3 ------------ BB62 [???..???), preds={BB60} succs={BB63} N003 ( 3, 2) [000445] ------?----- t445 = LCL_VAR long V26 tmp12 u:1 (last use) $2e7 /--* t445 long [001501] ------------ t1501 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000457] H-----?----- t457 = CNS_INT(h) long 0xd1ffab1e global ptr $52 /--* t457 long [001502] ------------ t1502 = * PUTARG_REG long REG rdx /--* t1501 long arg0 in rcx +--* t1502 long arg1 in rdx N005 ( 19, 19) [000458] --C-G-?----- t458 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 /--* t458 long N007 ( 23, 22) [001162] DA--G------- * STORE_LCL_VAR long V28 tmp14 d:2 ------------ BB63 [???..157) (throw), preds={BB61,BB62} succs={} N001 ( 0, 0) [001241] ------------ t1241 = PHI_ARG long V28 tmp14 u:3 N002 ( 0, 0) [001240] ------------ t1240 = PHI_ARG long V28 tmp14 u:2 $332 /--* t1241 long +--* t1240 long N003 ( 0, 0) [001183] ------------ t1183 = * PHI long /--* t1183 long N005 ( 0, 0) [001184] DA---------- * STORE_LCL_VAR long V28 tmp14 d:1 N003 ( 3, 2) [000473] ------------ t473 = LCL_VAR long V28 tmp14 u:1 (last use) $347 /--* t473 long [001503] ------------ t1503 = * PUTARG_REG long REG rcx N004 ( 1, 1) [000455] ------------ t455 = LCL_VAR ref V01 arg1 u:1 (last use) $101 /--* t455 ref [001504] ------------ t1504 = * PUTARG_REG ref REG rdx /--* t1503 long arg0 in rcx +--* t1504 ref arg1 in rdx N005 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void ------------ BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} [001438] ------------ IL_OFFSET void IL offset: 0x1bc N001 ( 1, 1) [000296] !----------- t296 = LCL_VAR ref V00 this u:1 $100 /--* t296 ref N002 ( 3, 2) [000297] #----O------ t297 = * IND long $2e8 /--* t297 long N004 ( 7, 5) [000299] DA---O------ * STORE_LCL_VAR long V21 tmp7 d:1 N001 ( 3, 2) [000301] ------------ t301 = LCL_VAR long V21 tmp7 u:1 $2e7 /--* t301 long N003 ( 4, 3) [000303] -c---------- t303 = * LEA(b+56) long /--* t303 long N004 ( 6, 5) [000304] #----------- t304 = * IND long $2e9 /--* t304 long N005 ( 9, 7) [000305] #----------- t305 = * IND long $2ea /--* t305 long N007 ( 10, 8) [000307] -c---------- t307 = * LEA(b+56) long /--* t307 long N008 ( 12, 10) [000311] nc---------- t311 = * IND long N009 ( 1, 1) [000314] -c---------- t314 = CNS_INT long 0 $243 /--* t311 long +--* t314 long N010 ( 14, 12) [000315] J------N---- * EQ void N011 ( 16, 14) [001168] ------------ * JTRUE void ------------ BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} N001 ( 3, 2) [000321] ------?----- t321 = LCL_VAR long V21 tmp7 u:1 (last use) $2e7 /--* t321 long N003 ( 4, 3) [000320] -c----?----- t320 = * LEA(b+56) long /--* t320 long N004 ( 6, 5) [000319] #-----?----- t319 = * IND long $2e9 /--* t319 long N005 ( 9, 7) [000318] #-----?----- t318 = * IND long $2ea /--* t318 long N007 ( 10, 8) [000317] -c----?----- t317 = * LEA(b+56) long /--* t317 long N008 ( 12, 10) [000316] n-----?----- t316 = * IND long /--* t316 long N010 ( 16, 13) [001170] DA---------- * STORE_LCL_VAR long V23 tmp9 d:3 ------------ BB66 [???..???), preds={BB64} succs={BB67} N003 ( 3, 2) [000300] ------?----- t300 = LCL_VAR long V21 tmp7 u:1 (last use) $2e7 /--* t300 long [001505] ------------ t1505 = * PUTARG_REG long REG rcx N004 ( 2, 10) [000312] H-----?----- t312 = CNS_INT(h) long 0xd1ffab1e global ptr $52 /--* t312 long [001506] ------------ t1506 = * PUTARG_REG long REG rdx /--* t1505 long arg0 in rcx +--* t1506 long arg1 in rdx N005 ( 19, 19) [000313] --C-G-?----- t313 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS $332 /--* t313 long N007 ( 23, 22) [001172] DA--G------- * STORE_LCL_VAR long V23 tmp9 d:2 ------------ BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} N001 ( 0, 0) [001232] ------------ t1232 = PHI_ARG long V23 tmp9 u:3 N002 ( 0, 0) [001231] ------------ t1231 = PHI_ARG long V23 tmp9 u:2 $332 /--* t1232 long +--* t1231 long N003 ( 0, 0) [001201] ------------ t1201 = * PHI long /--* t1201 long N005 ( 0, 0) [001202] DA---------- * STORE_LCL_VAR long V23 tmp9 d:1 N003 ( 3, 2) [000328] ------------ t328 = LCL_VAR long V23 tmp9 u:1 (last use) $34b /--* t328 long [001507] ------------ t1507 = * PUTARG_REG long REG rcx N004 ( 1, 1) [000310] ------------ t310 = LCL_VAR ref V01 arg1 u:1 (last use) $101 /--* t310 ref [001508] ------------ t1508 = * PUTARG_REG ref REG rdx /--* t1507 long arg0 in rcx +--* t1508 ref arg1 in rdx N005 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException $VN.Void ------------ BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} [001439] ------------ IL_OFFSET void IL offset: 0x1dd N001 ( 14, 5) [000233] --CXG------- CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported $VN.Void ------------ BB69 [???..???) (throw), preds={} succs={} N001 ( 14, 5) [001444] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Calculate stack level slots *************** Finishing PHASE Calculate stack level slots [no changes] *************** Starting PHASE Linear scan register alloc Clearing modified regs. buildIntervals ======== ----------------- LIVENESS: ----------------- BB01 use def in out {V01} {} {V00 V01 V02 V03} {V00 V01 V02 V03} BB02 use def in out {V00} {} {V00 V01 V02 V03} {V00 V01 V02 V03} BB03 use def in out {V00} {} {V00 V01 V02 V03} {V00 V01 V02 V03} BB04 use def in out {V00} {V33 V34 V35 V73} {V00 V01 V02 V03} {V00 V01 V02 V03 V35 V73} BB05 use def in out {V35} {} {V00 V01 V02 V03 V35 V73} {V00 V01 V02 V03 V73} BB06 use def in out {V00 V73} {V04 V36 V37} {V00 V01 V02 V03 V73} {V00 V01 V02 V03 V04 V37 V73} BB07 use def in out {V37} {} {V00 V01 V02 V03 V04 V37 V73} {V00 V01 V02 V03 V04 V73} BB08 use def in out {V00} {V05} {V00 V01 V02 V03 V04 V73} {V00 V01 V02 V03 V04 V05 V73} BB09 use def in out {V00} {V29 V68} {V00 V01 V02 V03 V04 V05 V73} {V00 V01 V02 V03 V04 V05 V29 V68 V73} BB10 use def in out {V68} {V31} {V00 V01 V02 V03 V04 V05 V68 V73} {V00 V01 V02 V03 V04 V05 V31 V73} BB11 use def in out {V29} {V31} {V00 V01 V02 V03 V04 V05 V29 V73} {V00 V01 V02 V03 V04 V05 V31 V73} BB12 use def in out {V01 V05 V31} {V15} {V00 V01 V02 V03 V04 V05 V31 V73} {V00 V01 V02 V03 V04 V05 V15 V73} BB13 use def in out {V01} {V15} {V00 V01 V02 V03 V04 V05 V73} {V00 V01 V02 V03 V04 V05 V15 V73} BB14 use def in out {V00 V15 V73} {V06 V07 V39 V40 V41 V43 V44 V45} {V00 V01 V02 V03 V04 V05 V15 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V45 V73} BB15 use def in out {V45} {} {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V45 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V73} BB16 use def in out {V06 V40 V41 V73} {V42 V46 V47 V48} {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V48 V73} BB17 use def in out {V48} {} {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V48 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V73} BB18 use def in out {V05 V39 V42} {V08 V09 V38} {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} BB19 use def in out {V00} {V24 V69} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V24 V69 V73} BB20 use def in out {V69} {V25} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V69 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V25 V73} BB21 use def in out {V24} {V25} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V24 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V25 V73} BB22 use def in out {V25} {V12} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V25 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73} BB23 use def in out {V04 V09} {V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73 V76} BB24 use def in out {V04 V06 V09} {V65 V70} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73 V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V65 V70 V73 V76} BB25 use def in out {V01 V04 V12 V70} {} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V65 V70 V73 V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V65 V73 V76} BB26 use def in out {V07 V65 V76} {V07 V09} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V65 V73 V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73} BB27 use def in out {} {} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73} BB28 use def in out {V03} {} {V00 V01 V02 V03 V65} {V00 V01 V02 V03 V65} BB29 use def in out {V02 V65} {} {V00 V02 V65} {V00} BB30 use def in out {V03} {} {V00 V01 V03} {V00 V01} BB31 use def in out {} {} {V00} {V00} BB32 use def in out {V04 V09} {V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73 V76} BB33 use def in out {V04 V06 V09} {V66 V71} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73 V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V66 V71 V73 V76} BB34 use def in out {V00 V04 V71} {V16 V17 V67} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V66 V71 V73 V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V16 V17 V66 V67 V73 V76} BB35 use def in out {V67} {V19} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V66 V67 V73 V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V19 V66 V73 V76} BB36 use def in out {V16} {V19} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V16 V17 V66 V73 V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V19 V66 V73 V76} BB37 use def in out {V01 V05 V17 V19} {} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V19 V66 V73 V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V66 V73 V76} BB38 use def in out {V03} {} {V00 V01 V02 V03 V66} {V00 V01 V02 V03 V66} BB39 use def in out {V02 V66} {} {V00 V02 V66} {V00} BB40 use def in out {V03} {} {V00 V01 V03} {V00 V01} BB41 use def in out {} {} {V00} {V00} BB42 use def in out {V07 V66 V76} {V07 V09} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V66 V73 V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} BB43 use def in out {} {} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} BB44 use def in out {V00} {} {V00 V01 V02 V04 V05 V06 V07 V08 V73 V76} {V00 V01 V02 V04 V05 V06 V07 V08 V73 V76} BB45 use def in out {V00 V04 V73 V76} {V10 V49 V50 V62 V74} {V00 V01 V02 V04 V05 V06 V07 V08 V73 V76} {V00 V01 V02 V04 V05 V06 V07 V08 V10 V50 V76} BB46 use def in out {V50} {} {V00 V01 V02 V04 V05 V06 V07 V08 V10 V50 V76} {V00 V01 V02 V04 V05 V06 V07 V08 V10 V76} BB47 use def in out {V00 V04 V76} {V63} {V00 V01 V02 V04 V05 V06 V07 V08 V10 V76} {V00 V01 V02 V04 V05 V06 V07 V08 V10} BB48 use def in out {V00 V76} {V13 V75} {V00 V01 V02 V05 V06 V07 V08 V73 V76} {V00 V01 V02 V05 V06 V07 V08 V13 V73 V75} BB49 use def in out {V00 V73 V75} {V52 V53 V54 V56 V57 V58 V64 V72} {V00 V01 V02 V05 V06 V07 V13 V73 V75} {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V58 V72 V73} BB50 use def in out {V58} {} {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V58 V72 V73} {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V72 V73} BB51 use def in out {V06 V53 V54 V73} {V55 V59 V60 V61} {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V72 V73} {V00 V01 V02 V05 V06 V07 V13 V52 V55 V61 V72} BB52 use def in out {V61} {} {V00 V01 V02 V05 V06 V07 V13 V52 V55 V61 V72} {V00 V01 V02 V05 V06 V07 V13 V52 V55 V72} BB53 use def in out {V52 V55 V72} {V08 V51} {V00 V01 V02 V05 V06 V07 V13 V52 V55 V72} {V00 V01 V02 V05 V06 V07 V08 V13} BB54 use def in out {V00 V13} {V04 V10} {V00 V01 V02 V05 V06 V07 V08 V13} {V00 V01 V02 V04 V05 V06 V07 V08 V10} BB55 use def in out {V00 V01 V02 V04 V06 V07 V08 V10} {V11} {V00 V01 V02 V04 V05 V06 V07 V08 V10} {V00 V04 V05} BB56 use def in out {V05} {} {V00 V04 V05} {V00 V04} BB57 use def in out {V00 V04} {} {V00 V04} {V00} BB58 use def in out {} {} {V00} {V00} BB59 use def in out {} {} {V00} {V00} BB60 use def in out {V00} {V26} {V00 V01} {V00 V01 V26} BB61 use def in out {V26} {V28} {V00 V01 V26} {V00 V01 V28} BB62 use def in out {V26} {V28} {V00 V01 V26} {V00 V01 V28} BB63 use def in out {V01 V28} {} {V00 V01 V28} {V00} BB64 use def in out {V00} {V21} {V00 V01} {V00 V01 V21} BB65 use def in out {V21} {V23} {V00 V01 V21} {V00 V01 V23} BB66 use def in out {V21} {V23} {V00 V01 V21} {V00 V01 V23} BB67 use def in out {V01 V23} {} {V00 V01 V23} {V00} BB68 use def in out {} {} {V00} {V00} BB69 use def in out {} {} {V00} {V00} Interval 0: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 0: (V00) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 1: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 1: (V01) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 2: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 2: (V02) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 3: int RefPositions {} physReg:NA Preferences=[allInt] Interval 3: (V03) int RefPositions {} physReg:NA Preferences=[allInt] Interval 4: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 4: (V04) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 5: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 5: (V05) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 6: int RefPositions {} physReg:NA Preferences=[allInt] Interval 6: (V06) int RefPositions {} physReg:NA Preferences=[allInt] Interval 7: int RefPositions {} physReg:NA Preferences=[allInt] Interval 7: (V07) int RefPositions {} physReg:NA Preferences=[allInt] Interval 8: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 8: (V08) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 9: int RefPositions {} physReg:NA Preferences=[allInt] Interval 9: (V09) int RefPositions {} physReg:NA Preferences=[allInt] Interval 10: int RefPositions {} physReg:NA Preferences=[allInt] Interval 10: (V10) int RefPositions {} physReg:NA Preferences=[allInt] Interval 11: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 11: (V11) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 12: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 12: (V12) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 13: int RefPositions {} physReg:NA Preferences=[allInt] Interval 13: (V13) int RefPositions {} physReg:NA Preferences=[allInt] Interval 14: int RefPositions {} physReg:NA Preferences=[allInt] Interval 14: (V15) int RefPositions {} physReg:NA Preferences=[allInt] Interval 15: long RefPositions {} physReg:NA Preferences=[allInt] Interval 15: (V16) long RefPositions {} physReg:NA Preferences=[allInt] Interval 16: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 16: (V17) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 17: long RefPositions {} physReg:NA Preferences=[allInt] Interval 17: (V19) long RefPositions {} physReg:NA Preferences=[allInt] Interval 18: long RefPositions {} physReg:NA Preferences=[allInt] Interval 18: (V21) long RefPositions {} physReg:NA Preferences=[allInt] Interval 19: long RefPositions {} physReg:NA Preferences=[allInt] Interval 19: (V23) long RefPositions {} physReg:NA Preferences=[allInt] Interval 20: long RefPositions {} physReg:NA Preferences=[allInt] Interval 20: (V24) long RefPositions {} physReg:NA Preferences=[allInt] Interval 21: long RefPositions {} physReg:NA Preferences=[allInt] Interval 21: (V25) long RefPositions {} physReg:NA Preferences=[allInt] Interval 22: long RefPositions {} physReg:NA Preferences=[allInt] Interval 22: (V26) long RefPositions {} physReg:NA Preferences=[allInt] Interval 23: long RefPositions {} physReg:NA Preferences=[allInt] Interval 23: (V28) long RefPositions {} physReg:NA Preferences=[allInt] Interval 24: long RefPositions {} physReg:NA Preferences=[allInt] Interval 24: (V29) long RefPositions {} physReg:NA Preferences=[allInt] Interval 25: long RefPositions {} physReg:NA Preferences=[allInt] Interval 25: (V31) long RefPositions {} physReg:NA Preferences=[allInt] Interval 26: int RefPositions {} physReg:NA Preferences=[allInt] Interval 26: (V33) int RefPositions {} physReg:NA Preferences=[allInt] Interval 27: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 27: (V35) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 28: int RefPositions {} physReg:NA Preferences=[allInt] Interval 28: (V36) int RefPositions {} physReg:NA Preferences=[allInt] Interval 29: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 29: (V37) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 30: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 30: (V38) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 31: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 31: (V39) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 32: int RefPositions {} physReg:NA Preferences=[allInt] Interval 32: (V40) int RefPositions {} physReg:NA Preferences=[allInt] Interval 33: long RefPositions {} physReg:NA Preferences=[allInt] Interval 33: (V41) long RefPositions {} physReg:NA Preferences=[allInt] Interval 34: int RefPositions {} physReg:NA Preferences=[allInt] Interval 34: (V42) int RefPositions {} physReg:NA Preferences=[allInt] Interval 35: int RefPositions {} physReg:NA Preferences=[allInt] Interval 35: (V43) int RefPositions {} physReg:NA Preferences=[allInt] Interval 36: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 36: (V45) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 37: int RefPositions {} physReg:NA Preferences=[allInt] Interval 37: (V46) int RefPositions {} physReg:NA Preferences=[allInt] Interval 38: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 38: (V48) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 39: int RefPositions {} physReg:NA Preferences=[allInt] Interval 39: (V49) int RefPositions {} physReg:NA Preferences=[allInt] Interval 40: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 40: (V50) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 41: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 41: (V51) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 42: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 42: (V52) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 43: int RefPositions {} physReg:NA Preferences=[allInt] Interval 43: (V53) int RefPositions {} physReg:NA Preferences=[allInt] Interval 44: long RefPositions {} physReg:NA Preferences=[allInt] Interval 44: (V54) long RefPositions {} physReg:NA Preferences=[allInt] Interval 45: int RefPositions {} physReg:NA Preferences=[allInt] Interval 45: (V55) int RefPositions {} physReg:NA Preferences=[allInt] Interval 46: int RefPositions {} physReg:NA Preferences=[allInt] Interval 46: (V56) int RefPositions {} physReg:NA Preferences=[allInt] Interval 47: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 47: (V58) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 48: int RefPositions {} physReg:NA Preferences=[allInt] Interval 48: (V59) int RefPositions {} physReg:NA Preferences=[allInt] Interval 49: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 49: (V61) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 50: int RefPositions {} physReg:NA Preferences=[allInt] Interval 50: (V62) int RefPositions {} physReg:NA Preferences=[allInt] Interval 51: int RefPositions {} physReg:NA Preferences=[allInt] Interval 51: (V63) int RefPositions {} physReg:NA Preferences=[allInt] Interval 52: int RefPositions {} physReg:NA Preferences=[allInt] Interval 52: (V64) int RefPositions {} physReg:NA Preferences=[allInt] Interval 53: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 53: (V65) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 54: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 54: (V66) byref RefPositions {} physReg:NA Preferences=[allInt] Interval 55: long RefPositions {} physReg:NA Preferences=[allInt] Interval 55: (V67) long RefPositions {} physReg:NA Preferences=[allInt] Interval 56: long RefPositions {} physReg:NA Preferences=[allInt] Interval 56: (V68) long RefPositions {} physReg:NA Preferences=[allInt] Interval 57: long RefPositions {} physReg:NA Preferences=[allInt] Interval 57: (V69) long RefPositions {} physReg:NA Preferences=[allInt] Interval 58: long RefPositions {} physReg:NA Preferences=[allInt] Interval 58: (V70) long RefPositions {} physReg:NA Preferences=[allInt] Interval 59: long RefPositions {} physReg:NA Preferences=[allInt] Interval 59: (V71) long RefPositions {} physReg:NA Preferences=[allInt] Interval 60: int RefPositions {} physReg:NA Preferences=[allInt] Interval 60: (V72) int RefPositions {} physReg:NA Preferences=[allInt] Interval 61: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 61: (V73) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 62: int RefPositions {} physReg:NA Preferences=[allInt] Interval 62: (V74) int RefPositions {} physReg:NA Preferences=[allInt] Interval 63: int RefPositions {} physReg:NA Preferences=[allInt] Interval 63: (V75) int RefPositions {} physReg:NA Preferences=[allInt] Interval 64: int RefPositions {} physReg:NA Preferences=[allInt] Interval 64: (V76) int RefPositions {} physReg:NA Preferences=[allInt] FP callee save candidate vars: None floatVarCount = 0; hasLoops = 1, singleExit = 0 TUPLE STYLE DUMP BEFORE LSRA New BlockSet epoch 7, # of blocks (including unused BB00): 70, bitset array size: 2 (long) LSRA Block Sequence: BB01( 1 ) BB02( 1 ) BB03( 0.50) BB04( 1 ) BB05( 0.50) BB06( 1 ) BB07( 0.50) BB08( 1 ) BB09( 0.50) BB10( 0.25) BB11( 0.25) BB12( 0.50) BB13( 0.50) BB14( 1 ) BB15( 0.50) BB16( 1 ) BB17( 0.50) BB18( 1 ) BB19( 0.50) BB20( 0.25) BB21( 0.25) BB22( 0.50) BB23( 4 ) BB24( 4 ) BB25( 2 ) BB26( 4 ) BB27( 4 ) BB28( 0.50) BB29( 0.50) BB30( 0.50) BB31( 0.50) BB32( 4 ) BB33( 4 ) BB34( 2 ) BB35( 1 ) BB36( 1 ) BB37( 2 ) BB38( 0.50) BB39( 0.50) BB40( 0.50) BB41( 0.50) BB42( 4 ) BB43( 4 ) BB44( 0.50) BB45( 0.50) BB46( 0.50) BB47( 0.50) BB48( 0.50) BB49( 0.50) BB50( 0.50) BB51( 0.50) BB52( 0.50) BB53( 0.50) BB54( 0.50) BB55( 0.50) BB56( 0.50) BB57( 0.50) BB58( 0.50) BB59( 0 ) BB60( 0 ) BB61( 0 ) BB62( 0 ) BB63( 0 ) BB64( 0 ) BB65( 0 ) BB66( 0 ) BB67( 0 ) BB68( 0 ) BB69( 0 ) BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} ===== N000. IL_OFFSET IL offset: 0x0 N001. V01(t0) N002. CNS_INT null N003. EQ ; t0 N004. JTRUE BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ===== N000. IL_OFFSET IL offset: 0xe N001. V00(t4) N003. t814 = LEA(b+8) ; t4 N004. t5 = IND ; t814 N005. CNS_INT null N006. NE ; t5 N007. JTRUE BB03 [016..01E), preds={BB02} succs={BB04} ===== N003. V00(t526) N000. t1455 = PUTARG_REG; t526 N004. t527 = CNS_INT 0 N000. t1456 = PUTARG_REG; t527 N005. CALL ; t1455,t1456 BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ===== N000. IL_OFFSET IL offset: 0x1e N001. V00(t9) N003. t818 = LEA(b+8) ; t9 N004. t10 = IND ; t818 N005. CNS_INT null N006. t12 = NE ; t10 N008. V33(t544); t12 N000. IL_OFFSET IL offset: 0x1e N001. t537 = CNS_INT(h) 0xD1FFAB1E [ICON_STR_HDL] N002. t538 = IND ; t537 N004. V73(t1291); t538 N000. IL_OFFSET IL offset: 0x1e N001. V73(t1294) N003. V35(t556); t1294 N000. IL_OFFSET IL offset: 0x1e N001. V33(t546*) N002. CNS_INT 0 N003. NE ; t546* N004. JTRUE BB05 [01E..01F), preds={BB04} succs={BB06} ===== N000. IL_OFFSET IL offset: 0x1e N003. V35(t550) N000. t1457 = PUTARG_REG; t550 N004. V35(t551*) N000. t1458 = PUTARG_REG; t551* N005. CALL ; t1457,t1458 BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} ===== N000. IL_OFFSET IL offset: 0x2c N001. V00(t15) N003. t822 = LEA(b+16); t15 N004. t16 = IND ; t822 N006. V04(t18); t16 N000. IL_OFFSET IL offset: 0x33 N001. V04(t19) N002. CNS_INT null N003. t21 = NE ; t19 N005. V36(t566); t21 N000. IL_OFFSET IL offset: 0x33 N001. V73(t1295) N003. V37(t576); t1295 N000. IL_OFFSET IL offset: 0x33 N001. V36(t568*) N002. CNS_INT 0 N003. NE ; t568* N004. JTRUE BB07 [033..034), preds={BB06} succs={BB08} ===== N000. IL_OFFSET IL offset: 0x33 N003. t823 = CNS_INT(h) 0xD1FFAB1E "expected entries to be non-null" N004. t824 = IND ; t823 N000. t1459 = PUTARG_REG; t824 N005. V37(t573*) N000. t1460 = PUTARG_REG; t573* N006. CALL ; t1459,t1460 BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} ===== N000. IL_OFFSET IL offset: 0x41 N001. V00(t25) N003. t828 = LEA(b+24); t25 N004. t26 = IND ; t828 N006. V05(t28); t26 N000. IL_OFFSET IL offset: 0x48 N001. V05(t29) N002. CNS_INT null N003. EQ ; t29 N004. JTRUE BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} ===== N000. IL_OFFSET IL offset: 0x4b N001. V00(t486) N002. t487 = IND ; t486 N004. V29(t489); t487 N001. V29(t491) N003. t493 = LEA(b+56); t491 N004. t494 = IND ; t493 N005. t495 = IND ; t494 N007. t497 = LEA(b+64); t495 N008. t501 = IND ; t497 N010. V68(t1266); t501 N011. V68(t1267) N013. CNS_INT 0 N014. EQ ; t1267 N015. JTRUE BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} ===== N001. V68(t1269*) N003. V31(t1150); t1269* BB11 [???..???), preds={BB09} succs={BB12} ===== N003. V29(t490*) N000. t1461 = PUTARG_REG; t490* N004. t502 = CNS_INT(h) 0xd1ffab1e global ptr N000. t1462 = PUTARG_REG; t502 N005. t503 = CALL help; t1461,t1462 N007. V31(t1152); t503 BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} ===== N004. V05(t484) N000. t1463 = PUTARG_REG; t484 N005. V31(t831) N000. t1464 = PUTARG_REG; t831 N006. V01(t500) N000. t1465 = PUTARG_REG; t500 N007. V31(t521*) N000. t1466 = IND ; t521* N008. t522 = CALL ind stub; t1463,t1464,t1465,t1466 N010. V15(t524); t522 BB13 [054..061), preds={BB08} succs={BB14} ===== N000. IL_OFFSET IL offset: 0x54 N002. V01(t33) N000. t1467 = PUTARG_REG; t33 N003. V01(t836) N004. t837 = IND ; t836 N006. t839 = LEA(b+72); t837 N007. t840 = IND ; t839 N009. t842 = LEA(b+24); t840 N010. t843 = IND ; t842 N011. t35 = CALLV vt-ind; t1467,t843 N013. V15(t38); t35 BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ===== N001. V15(t40*) N003. V06(t42); t40* N000. IL_OFFSET IL offset: 0x62 N001. t43 = CNS_INT 0 N003. V07(t45); t43 N000. IL_OFFSET IL offset: 0x64 N001. V00(t46) N003. t845 = LEA(b+8) ; t46 N004. t578 = IND ; t845 N006. V39(t580); t578 N000. IL_OFFSET IL offset: 0x64 N001. V39(t582) N000. t1441 = LEA(b+8) ; t582 N002. t583 = IND ; t1441 N004. V40(t629); t583 N000. IL_OFFSET IL offset: 0x64 N001. V00(t584) N003. t847 = LEA(b+48); t584 N004. t585 = IND ; t847 N006. V41(t631); t585 N000. IL_OFFSET IL offset: 0x64 N001. V40(t597) N002. CNS_INT 0x7FFFFFFF N003. t599 = LE ; t597 N005. V43(t642); t599 N000. IL_OFFSET IL offset: 0x64 N000. IL_OFFSET IL offset: 0x64 N001. V73(t1297) N003. V45(t654); t1297 N000. IL_OFFSET IL offset: 0x64 N001. V43(t644*) N002. CNS_INT 0 N003. NE ; t644* N004. JTRUE BB15 [064..065), preds={BB14} succs={BB16} ===== N000. IL_OFFSET IL offset: 0x64 N003. V45(t648) N000. t1468 = PUTARG_REG; t648 N004. V45(t649*) N000. t1469 = PUTARG_REG; t649* N005. CALL ; t1468,t1469 BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} ===== N000. IL_OFFSET IL offset: 0x64 N001. V41(t604*) N002. V06(t47) N003. t605 = CAST ; t47 N004. t606 = MUL ; t604*,t605 N005. CNS_INT 32 N006. t608 = RSZ ; t606 N007. CNS_INT 1 N008. t611 = ADD ; t608 N009. V40(t612) N010. t613 = CAST ; t612 N011. t614 = MUL ; t611,t613 N012. CNS_INT 32 N013. t616 = RSZ ; t614 N014. t617 = CAST ; t616 N016. V42(t619); t617 N000. IL_OFFSET IL offset: 0x64 N001. V06(t621) N002. V40(t622*) N003. t623 = UMOD ; t621,t622* N004. V42(t620) N005. t624 = EQ ; t623,t620 N007. V46(t665); t624 N000. IL_OFFSET IL offset: 0x64 N000. IL_OFFSET IL offset: 0x64 N001. V73(t1299) N003. V48(t677); t1299 N000. IL_OFFSET IL offset: 0x64 N001. V46(t667*) N002. CNS_INT 0 N003. NE ; t667* N004. JTRUE BB17 [064..065), preds={BB16} succs={BB18} ===== N000. IL_OFFSET IL offset: 0x64 N003. V48(t671) N000. t1470 = PUTARG_REG; t671 N004. V48(t672*) N000. t1471 = PUTARG_REG; t672* N005. CALL ; t1470,t1471 BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} ===== N000. IL_OFFSET IL offset: 0x64 N001. V42(t627) N002. V39(t581) N000. t1443 = LEA(b+8) ; t581 N003. t854 = IND ; t1443 N004. ARR_BOUNDS_CHECK_Rng -> BB69; t627,t854 N005. V39(t852*) N006. V42(t853*) N007. t856 = CAST ; t853* N012. t861 = LEA(b+(i*4)+16); t852*,t856 N017. V38(t591); t861 N001. V38(t592*) N003. V08(t51); t592* N000. IL_OFFSET IL offset: 0x6d N001. V08(t52) N002. t53 = IND ; t52 N003. CNS_INT -1 N004. t55 = ADD ; t53 N006. V09(t57); t55 N000. IL_OFFSET IL offset: 0x74 N001. V05(t58) N002. CNS_INT null N003. NE ; t58 N004. JTRUE BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} ===== N000. IL_OFFSET IL offset: 0xff N001. V00(t353) N002. t354 = IND ; t353 N004. V24(t356); t354 N001. V24(t358) N003. t360 = LEA(b+56); t358 N004. t361 = IND ; t360 N005. t362 = IND ; t361 N007. t364 = LEA(b+32); t362 N008. t365 = IND ; t364 N010. V69(t1271); t365 N011. V69(t1272) N013. CNS_INT 0 N014. EQ ; t1272 N015. JTRUE BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} ===== N001. V69(t1274*) N003. V25(t1155); t1274* BB21 [???..???), preds={BB19} succs={BB22} ===== N003. V24(t357*) N000. t1472 = PUTARG_REG; t357* N004. t366 = CNS_INT(h) 0xd1ffab1e global ptr N000. t1473 = PUTARG_REG; t366 N005. t367 = CALL help; t1472,t1473 N007. V25(t1157); t367 BB22 [???..106), preds={BB20,BB21} succs={BB23} ===== N002. V25(t382*) N000. t1474 = PUTARG_REG; t382* N003. t352 = CALL ; t1474 N005. V12(t386); t352 BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} ===== N000. IL_OFFSET IL offset: 0x106 N001. V04(t388) N000. t1446 = LEA(b+8) ; t388 N002. t389 = IND ; t1446 N004. V76(t1316); t389 N005. V76(t1317) N007. V09(t387) N008. LE ; t1317,t387 N009. JTRUE BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} ===== N000. IL_OFFSET IL offset: 0x110 N001. V04(t869) N002. V09(t870*) N003. t873 = CAST ; t870* N004. CNS_INT 3 N005. t881 = MUL ; t873 N007. V70(t1276); t881 N008. V70(t1277) N014. t878 = LEA(b+(i*8)+16); t869,t1277 N018. V65(t1249); t878 N019. V65(t1250) N022. t868 = LEA(b+16); t1250 N023. t396 = IND ; t868 N024. V06(t397) N025. NE ; t396,t397 N026. JTRUE BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} ===== N000. IL_OFFSET IL offset: 0x120 N004. V04(t883) N005. V70(t1279*) N010. t892 = LEA(b+(i*8)+16); t883,t1279* N013. t897 = IND ; t892 N000. t1475 = PUTARG_REG; t897 N014. V12(t418) N000. t1476 = PUTARG_REG; t418 N015. V01(t424) N000. t1477 = PUTARG_REG; t424 N016. V12(t901) N017. t902 = IND ; t901 N019. t904 = LEA(b+72); t902 N020. t905 = IND ; t904 N022. t907 = LEA(b+32); t905 N023. t908 = IND ; t907 N024. t425 = CALLV vt-ind; t1475,t1476,t1477,t908 N025. CNS_INT 0 N026. NE ; t425 N027. JTRUE BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} ===== N000. IL_OFFSET IL offset: 0x157 N001. V65(t1252*) N003. t932 = LEA(b+20); t1252* N004. t404 = IND ; t932 N006. V09(t406); t404 N000. IL_OFFSET IL offset: 0x166 N001. V07(t407*) N002. CNS_INT 1 N003. t409 = ADD ; t407* N005. V07(t411); t409 N000. IL_OFFSET IL offset: 0x16a N001. V76(t1321*) N002. V07(t412) N003. LT ; t1321*,t412 N004. JTRUE BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} ===== BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} ===== N000. IL_OFFSET IL offset: 0x137 N001. V03(t429) N003. CNS_INT 1 N004. NE ; t429 N005. JTRUE BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} ===== N000. IL_OFFSET IL offset: 0x13b N001. V65(t1253*) N003. t911 = LEA(b+8) ; t1253* N005. V02(t479*) N000. STOREIND ; t911,t479* BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} ===== N000. IL_OFFSET IL offset: 0x14b N001. V03(t433*) N003. CNS_INT 2 N004. EQ ; t433* N005. JTRUE BB31 [???..???) (return), preds={BB30,BB41} succs={} ===== N001. t437 = CNS_INT 0 N002. RETURN ; t437 BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} ===== N000. IL_OFFSET IL offset: 0x177 N001. V04(t63) N000. t1448 = LEA(b+8) ; t63 N002. t64 = IND ; t1448 N004. V76(t1323); t64 N005. V76(t1324) N007. V09(t62) N008. LE ; t1324,t62 N009. JTRUE BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} ===== N000. IL_OFFSET IL offset: 0x17e N001. V04(t949) N002. V09(t950*) N003. t953 = CAST ; t950* N004. CNS_INT 3 N005. t961 = MUL ; t953 N007. V71(t1281); t961 N008. V71(t1282) N014. t958 = LEA(b+(i*8)+16); t949,t1282 N018. V66(t1255); t958 N019. V66(t1256) N022. t948 = LEA(b+16); t1256 N023. t212 = IND ; t948 N024. V06(t213) N025. NE ; t212,t213 N026. JTRUE BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} ===== N000. IL_OFFSET IL offset: 0x18e N001. V04(t963) N002. V71(t1284*) N007. t972 = LEA(b+(i*8)+16); t963,t1284* N010. t977 = IND ; t972 N012. V17(t246); t977 N000. IL_OFFSET IL offset: 0x18e N001. V00(t241) N002. t242 = IND ; t241 N004. V16(t244); t242 N001. V16(t249) N003. t251 = LEA(b+56); t249 N004. t252 = IND ; t251 N005. t253 = IND ; t252 N007. t255 = LEA(b+48); t253 N008. t259 = IND ; t255 N010. V67(t1261); t259 N011. V67(t1262) N013. CNS_INT 0 N014. EQ ; t1262 N015. JTRUE BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} ===== N001. V67(t1264*) N003. V19(t1165); t1264* BB36 [???..???), preds={BB34} succs={BB37} ===== N003. V16(t248*) N000. t1478 = PUTARG_REG; t248* N004. t260 = CNS_INT(h) 0xd1ffab1e global ptr N000. t1479 = PUTARG_REG; t260 N005. t261 = CALL help; t1478,t1479 N007. V19(t1167); t261 BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} ===== N005. V05(t234) N000. t1480 = PUTARG_REG; t234 N006. V19(t980) N000. t1481 = PUTARG_REG; t980 N007. V17(t247*) N000. t1482 = PUTARG_REG; t247* N008. V01(t258) N000. t1483 = PUTARG_REG; t258 N009. V19(t279*) N000. t1484 = IND ; t279* N010. t280 = CALL ind stub; t1480,t1481,t1482,t1483,t1484 N011. CNS_INT 0 N012. EQ ; t280 N013. JTRUE BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} ===== N000. IL_OFFSET IL offset: 0x1a4 N001. V03(t284) N003. CNS_INT 1 N004. NE ; t284 N005. JTRUE BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} ===== N000. IL_OFFSET IL offset: 0x1a8 N001. V66(t1258*) N003. t987 = LEA(b+8) ; t1258* N005. V02(t334*) N000. STOREIND ; t987,t334* BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} ===== N000. IL_OFFSET IL offset: 0x1b8 N001. V03(t288*) N003. CNS_INT 2 N004. EQ ; t288* N005. JTRUE BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} ===== BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} ===== N000. IL_OFFSET IL offset: 0x1c4 N001. V66(t1259*) N003. t1009 = LEA(b+20); t1259* N004. t220 = IND ; t1009 N006. V09(t222); t220 N000. IL_OFFSET IL offset: 0x1d3 N001. V07(t223*) N002. CNS_INT 1 N003. t225 = ADD ; t223* N005. V07(t227); t225 N000. IL_OFFSET IL offset: 0x1d7 N001. V76(t1328*) N002. V07(t228) N003. LT ; t1328*,t228 N004. JTRUE BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} ===== BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} ===== N000. IL_OFFSET IL offset: 0x1e4 N001. V00(t67) N003. t1025 = LEA(b+64); t67 N004. t68 = IND ; t1025 N005. CNS_INT 0 N006. LE ; t68 N007. JTRUE BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} ===== N000. IL_OFFSET IL offset: 0x1ed N001. V00(t171) N003. t1027 = LEA(b+60); t171 N004. t172 = IND ; t1027 N006. V74(t1306); t172 N007. V74(t1307) N010. V10(t174); t1307 N000. IL_OFFSET IL offset: 0x1f5 N001. V74(t1309*) N003. V62(t1032); t1309* N004. V62(t1033) N005. V76(t1329) N006. ARR_BOUNDS_CHECK_Rng -> BB69; t1033,t1329 N007. V04(t1030) N008. V62(t1034*) N009. t1037 = CAST ; t1034* N010. CNS_INT 3 N011. t1048 = MUL ; t1037 N022. t1029 = LEA(b+(i*8)+36); t1030,t1048 N023. t181 = IND ; t1029 N024. t1050 = NEG ; t181 N025. CNS_INT -3 N026. t182 = ADD ; t1050 N027. CNS_INT -1 N028. t184 = GE ; t182 N030. V49(t688); t184 N000. IL_OFFSET IL offset: 0x1f5 N001. V73(t1300*) N003. V50(t698); t1300* N000. IL_OFFSET IL offset: 0x1f5 N001. V49(t690*) N002. CNS_INT 0 N003. NE ; t690* N004. JTRUE BB46 [1F5..1F6), preds={BB45} succs={BB47} ===== N000. IL_OFFSET IL offset: 0x1f5 N003. t1051 = CNS_INT(h) 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" N004. t1052 = IND ; t1051 N000. t1485 = PUTARG_REG; t1052 N005. V50(t695*) N000. t1486 = PUTARG_REG; t695* N006. CALL ; t1485,t1486 BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} ===== N000. IL_OFFSET IL offset: 0x219 N001. V00(t190) N003. t1056 = LEA(b+60); t190 N005. V00(t193) N007. t1075 = LEA(b+60); t193 N008. t194 = IND ; t1075 N010. V63(t1061); t194 N011. V63(t1062) N012. V76(t1330*) N013. ARR_BOUNDS_CHECK_Rng -> BB69; t1062,t1330* N014. V04(t1059) N015. V63(t1063*) N016. t1066 = CAST ; t1063* N017. CNS_INT 3 N018. t1077 = MUL ; t1066 N029. t1058 = LEA(b+(i*8)+36); t1059,t1077 N030. t197 = IND ; t1058 N031. t1079 = NEG ; t197 N032. CNS_INT -3 N033. t198 = ADD ; t1079 N000. STOREIND ; t1056,t198 N000. IL_OFFSET IL offset: 0x233 N001. V00(t202) N003. LEA(b+64) N004. IND N005. CNS_INT -1 N006. ADD N007. V00(t201) N009. t1081 = LEA(b+64); t201 N000. STOREIND ; t1081 BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} ===== N000. IL_OFFSET IL offset: 0x243 N001. V00(t72) N003. t1085 = LEA(b+56); t72 N004. t73 = IND ; t1085 N006. V75(t1311); t73 N007. V75(t1312) N010. V13(t75); t1312 N000. IL_OFFSET IL offset: 0x24b N001. V76(t1331*) N002. V13(t76) N003. NE ; t1331*,t76 N004. JTRUE BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ===== N000. IL_OFFSET IL offset: 0x252 N003. V75(t1314*) N000. t1487 = PUTARG_REG; t1314* N004. t702 = CALL ; t1487 N006. V64(t1090); t702 N008. V64(t1091*) N000. t1488 = PUTARG_REG; t1091* N009. V00(t163) N000. t1489 = PUTARG_REG; t163 N010. t704 = CNS_INT 0 N000. t1490 = PUTARG_REG; t704 N011. CALL ; t1488,t1489,t1490 N000. IL_OFFSET IL offset: 0x258 N001. V00(t165) N003. t1095 = LEA(b+8) ; t165 N004. t709 = IND ; t1095 N006. V52(t711); t709 N000. IL_OFFSET IL offset: 0x258 N001. V52(t713) N000. t1450 = LEA(b+8) ; t713 N002. t714 = IND ; t1450 N004. V72(t1286); t714 N005. V72(t1287) N008. V53(t760); t1287 N000. IL_OFFSET IL offset: 0x258 N001. V00(t715) N003. t1097 = LEA(b+48); t715 N004. t716 = IND ; t1097 N006. V54(t762); t716 N000. IL_OFFSET IL offset: 0x258 N001. V53(t728) N002. CNS_INT 0x7FFFFFFF N003. t730 = LE ; t728 N005. V56(t773); t730 N000. IL_OFFSET IL offset: 0x258 N000. IL_OFFSET IL offset: 0x258 N001. V73(t1302) N003. V58(t785); t1302 N000. IL_OFFSET IL offset: 0x258 N001. V56(t775*) N002. CNS_INT 0 N003. NE ; t775* N004. JTRUE BB50 [258..259), preds={BB49} succs={BB51} ===== N000. IL_OFFSET IL offset: 0x258 N003. V58(t779) N000. t1491 = PUTARG_REG; t779 N004. V58(t780*) N000. t1492 = PUTARG_REG; t780* N005. CALL ; t1491,t1492 BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} ===== N000. IL_OFFSET IL offset: 0x258 N001. V54(t735*) N002. V06(t166) N003. t736 = CAST ; t166 N004. t737 = MUL ; t735*,t736 N005. CNS_INT 32 N006. t739 = RSZ ; t737 N007. CNS_INT 1 N008. t742 = ADD ; t739 N009. V53(t743) N010. t744 = CAST ; t743 N011. t745 = MUL ; t742,t744 N012. CNS_INT 32 N013. t747 = RSZ ; t745 N014. t748 = CAST ; t747 N016. V55(t750); t748 N000. IL_OFFSET IL offset: 0x258 N001. V06(t752) N002. V53(t753*) N003. t754 = UMOD ; t752,t753* N004. V55(t751) N005. t755 = EQ ; t754,t751 N007. V59(t796); t755 N000. IL_OFFSET IL offset: 0x258 N000. IL_OFFSET IL offset: 0x258 N001. V73(t1304*) N003. V61(t808); t1304* N000. IL_OFFSET IL offset: 0x258 N001. V59(t798*) N002. CNS_INT 0 N003. NE ; t798* N004. JTRUE BB52 [258..259), preds={BB51} succs={BB53} ===== N000. IL_OFFSET IL offset: 0x258 N003. V61(t802) N000. t1493 = PUTARG_REG; t802 N004. V61(t803*) N000. t1494 = PUTARG_REG; t803* N005. CALL ; t1493,t1494 BB53 [258..259), preds={BB51,BB52} succs={BB54} ===== N000. IL_OFFSET IL offset: 0x258 N001. V55(t758) N002. V72(t1289*) N003. ARR_BOUNDS_CHECK_Rng -> BB69; t758,t1289* N004. V52(t1102*) N005. V55(t1103*) N006. t1106 = CAST ; t1103* N011. t1111 = LEA(b+(i*4)+16); t1102*,t1106 N016. V51(t722); t1111 N001. V51(t723*) N003. V08(t170); t723* BB54 [261..276), preds={BB48,BB53} succs={BB55} ===== N000. IL_OFFSET IL offset: 0x261 N001. V13(t81*) N003. V10(t83); t81* N000. IL_OFFSET IL offset: 0x265 N001. V10(t85) N002. CNS_INT 1 N003. t87 = ADD ; t85 N004. V00(t84) N006. t1115 = LEA(b+56); t84 N000. STOREIND ; t1115,t87 N000. IL_OFFSET IL offset: 0x26f N001. V00(t90) N003. t1117 = LEA(b+16); t90 N004. t91 = IND ; t1117 N006. V04(t93); t91 BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} ===== N000. IL_OFFSET IL offset: 0x276 N001. V10(t95) N002. V04(t94) N000. t1452 = LEA(b+8) ; t94 N003. t1120 = IND ; t1452 N004. ARR_BOUNDS_CHECK_Rng -> BB69; t95,t1120 N005. V04(t1118) N006. V10(t1119) N007. t1122 = CAST ; t1119 N008. CNS_INT 3 N009. t1130 = MUL ; t1122 N014. t1127 = LEA(b+(i*8)+16); t1118,t1130 N019. V11(t99); t1127 N000. IL_OFFSET IL offset: 0x280 N001. V11(t100) N003. t1133 = LEA(b+16); t100 N005. V06(t101*) N000. STOREIND ; t1133,t101* N000. IL_OFFSET IL offset: 0x288 N001. V08(t105) N002. t106 = IND ; t105 N003. CNS_INT -1 N004. t108 = ADD ; t106 N005. V11(t104) N007. t1135 = LEA(b+20); t104 N000. STOREIND ; t1135,t108 N000. IL_OFFSET IL offset: 0x294 N001. V11(t111) N003. V01(t112*) N000. STOREIND ; t111,t112* N000. IL_OFFSET IL offset: 0x29c N001. V11(t115*) N003. t1137 = LEA(b+8) ; t115* N005. V02(t116*) N000. STOREIND ; t1137,t116* N000. IL_OFFSET IL offset: 0x2a4 N001. V10(t120*) N002. CNS_INT 1 N003. t122 = ADD ; t120* N004. V08(t119*) N000. STOREIND ; t119*,t122 N000. IL_OFFSET IL offset: 0x2ab N001. V00(t126) N003. LEA(b+68) N004. IND N005. CNS_INT 1 N006. ADD N007. V00(t125) N009. t1139 = LEA(b+68); t125 N000. STOREIND ; t1139 N000. IL_OFFSET IL offset: 0x2ca N001. V07(t145*) N002. CNS_INT 100 N003. LE ; t145* N004. JTRUE BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} ===== N000. IL_OFFSET IL offset: 0x2cf N003. V05(t151*) N000. t1495 = PUTARG_REG; t151* N004. t152 = CNS_INT(h) 0xd1ffab1e class N000. t1496 = PUTARG_REG; t152 N005. t153 = CALL help; t1495,t1496 N006. CNS_INT null N007. EQ ; t153 N008. JTRUE BB57 [2D7..2E3), preds={BB56} succs={BB58} ===== N000. IL_OFFSET IL offset: 0x2d7 N004. V04(t158*) N000. t1454 = LEA(b+8) ; t158* N005. t159 = IND ; t1454 N000. t1497 = PUTARG_REG; t159 N006. V00(t157) N000. t1498 = PUTARG_REG; t157 N007. t160 = CNS_INT 1 N000. t1499 = PUTARG_REG; t160 N008. CALL ; t1497,t1498,t1499 BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} ===== N001. t482 = CNS_INT 1 N002. RETURN ; t482 BB59 [008..00E) (throw), preds={BB01} succs={} ===== N000. IL_OFFSET IL offset: 0x8 N002. t532 = CNS_INT 4 N000. t1500 = PUTARG_REG; t532 N003. CALL ; t1500 BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} ===== N000. IL_OFFSET IL offset: 0x14f N001. V00(t441) N002. t442 = IND ; t441 N004. V26(t444); t442 N001. V26(t446) N003. t448 = LEA(b+56); t446 N004. t449 = IND ; t448 N005. t450 = IND ; t449 N007. t452 = LEA(b+56); t450 N008. t456 = IND ; t452 N009. CNS_INT 0 N010. EQ ; t456 N011. JTRUE BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} ===== N001. V26(t466*) N003. t465 = LEA(b+56); t466* N004. t464 = IND ; t465 N005. t463 = IND ; t464 N007. t462 = LEA(b+56); t463 N008. t461 = IND ; t462 N010. V28(t1160); t461 BB62 [???..???), preds={BB60} succs={BB63} ===== N003. V26(t445*) N000. t1501 = PUTARG_REG; t445* N004. t457 = CNS_INT(h) 0xd1ffab1e global ptr N000. t1502 = PUTARG_REG; t457 N005. t458 = CALL help; t1501,t1502 N007. V28(t1162); t458 BB63 [???..157) (throw), preds={BB61,BB62} succs={} ===== N003. V28(t473*) N000. t1503 = PUTARG_REG; t473* N004. V01(t455*) N000. t1504 = PUTARG_REG; t455* N005. CALL ; t1503,t1504 BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} ===== N000. IL_OFFSET IL offset: 0x1bc N001. V00(t296) N002. t297 = IND ; t296 N004. V21(t299); t297 N001. V21(t301) N003. t303 = LEA(b+56); t301 N004. t304 = IND ; t303 N005. t305 = IND ; t304 N007. t307 = LEA(b+56); t305 N008. t311 = IND ; t307 N009. CNS_INT 0 N010. EQ ; t311 N011. JTRUE BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} ===== N001. V21(t321*) N003. t320 = LEA(b+56); t321* N004. t319 = IND ; t320 N005. t318 = IND ; t319 N007. t317 = LEA(b+56); t318 N008. t316 = IND ; t317 N010. V23(t1170); t316 BB66 [???..???), preds={BB64} succs={BB67} ===== N003. V21(t300*) N000. t1505 = PUTARG_REG; t300* N004. t312 = CNS_INT(h) 0xd1ffab1e global ptr N000. t1506 = PUTARG_REG; t312 N005. t313 = CALL help; t1505,t1506 N007. V23(t1172); t313 BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} ===== N003. V23(t328*) N000. t1507 = PUTARG_REG; t328* N004. V01(t310*) N000. t1508 = PUTARG_REG; t310* N005. CALL ; t1507,t1508 BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} ===== N000. IL_OFFSET IL offset: 0x1dd N001. CALL BB69 [???..???) (throw), preds={} succs={} ===== N001. CALL help buildIntervals second part ======== Int arg V00 in reg rcx BB00 regmask=[rcx] minReg=1 fixed> Int arg V01 in reg rdx BB00 regmask=[rdx] minReg=1 fixed> Int arg V03 in reg r9 BB00 regmask=[r9] minReg=1 fixed> Int arg V02 in reg r8 BB00 regmask=[r8] minReg=1 fixed> NEW BLOCK BB01 DefList: { } N003 (???,???) [001332] ------------ * IL_OFFSET void IL offset: 0x0 REG NA DefList: { } N005 ( 1, 1) [000000] ------------ * LCL_VAR ref V01 arg1 u:1 NA REG NA $101 DefList: { } N007 ( 1, 1) [000001] -c---------- * CNS_INT ref null REG NA $VN.Null Contained DefList: { } N009 ( 3, 3) [000002] J------N---- * EQ void REG NA $180 LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N011 ( 5, 5) [000003] ------------ * JTRUE void REG NA CHECKING LAST USES for BB01, liveout={V00 V01 V02 V03} ============================== Reporting this as generic context: referenced use: {V01} def: {} NEW BLOCK BB02 Setting BB01 as the predecessor for determining incoming variable registers of BB02 DefList: { } N015 (???,???) [001333] ------------ * IL_OFFSET void IL offset: 0xe REG NA DefList: { } N017 ( 1, 1) [000004] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N019 ( 2, 2) [000814] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N021 ( 4, 4) [000005] -c-XG------- * IND ref REG NA Contained DefList: { } N023 ( 1, 1) [000006] -c---------- * CNS_INT ref null REG NA $VN.Null Contained DefList: { } N025 ( 6, 6) [000007] J--XG--N---- * NE void REG NA LCL_VAR BB02 regmask=[allInt] minReg=1 last> DefList: { } N027 ( 8, 8) [000008] ---XG------- * JTRUE void REG NA CHECKING LAST USES for BB02, liveout={V00 V01 V02 V03} ============================== Reporting this as generic context: referenced use: {V00} def: {} NEW BLOCK BB03 Setting BB02 as the predecessor for determining incoming variable registers of BB03 DefList: { } N031 ( 1, 1) [000526] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N033 (???,???) [001455] ------------ * PUTARG_REG ref REG rcx BB03 regmask=[rcx] minReg=1> LCL_VAR BB03 regmask=[rcx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 65: ref RefPositions {} physReg:NA Preferences=[allInt] BB03 regmask=[rcx] minReg=1> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed> Assigning related to DefList: { N033.t1455. PUTARG_REG } N035 ( 1, 1) [000527] ------------ * CNS_INT int 0 REG NA $c0 Interval 66: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB03 regmask=[allInt] minReg=1> DefList: { N033.t1455. PUTARG_REG; N035.t527. CNS_INT } N037 (???,???) [001456] ------------ * PUTARG_REG int REG rdx BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1 last fixed> Interval 67: int RefPositions {} physReg:NA Preferences=[allInt] BB03 regmask=[rdx] minReg=1> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed> DefList: { N033.t1455. PUTARG_REG; N037.t1456. PUTARG_REG } N039 ( 16, 10) [000528] --CXG------- * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize REG NA $1c2 BB03 regmask=[rcx] minReg=1> BB03 regmask=[rcx] minReg=1 last fixed> BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1 last fixed> BB03 regmask=[rax] minReg=1> BB03 regmask=[rcx] minReg=1> BB03 regmask=[rdx] minReg=1> BB03 regmask=[r8] minReg=1> BB03 regmask=[r9] minReg=1> BB03 regmask=[r10] minReg=1> BB03 regmask=[r11] minReg=1> Interval 68: int RefPositions {} physReg:NA Preferences=[allInt] BB03 regmask=[rax] minReg=1> CALL BB03 regmask=[rax] minReg=1 fixed> CHECKING LAST USES for BB03, liveout={V00 V01 V02 V03} ============================== Reporting this as generic context: referenced use: {V00} def: {} NEW BLOCK BB04 Setting BB02 as the predecessor for determining incoming variable registers of BB04 DefList: { } N043 (???,???) [001334] ------------ * IL_OFFSET void IL offset: 0x1e REG NA DefList: { } N045 ( 1, 1) [000009] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N047 ( 2, 2) [000818] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N049 ( 4, 4) [000010] nc--GO------ * IND ref REG NA Contained DefList: { } N051 ( 1, 1) [000011] -c---------- * CNS_INT ref null REG NA $VN.Null Contained DefList: { } N053 ( 9, 6) [000012] N---GO------ * NE int REG NA LCL_VAR BB04 regmask=[allInt] minReg=1 last> Interval 69: int RefPositions {} physReg:NA Preferences=[allInt] NE BB04 regmask=[allInt] minReg=1> DefList: { N053.t12. NE } N055 ( 9, 6) [000544] DA--GO------ * STORE_LCL_VAR int V33 tmp19 d:1 NA REG NA BB04 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB04 regmask=[allInt] minReg=1 last> DefList: { } N057 (???,???) [001335] ------------ * IL_OFFSET void IL offset: 0x1e REG NA DefList: { } N059 ( 2, 10) [000537] H----------- * CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] REG NA $43 Interval 70: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB04 regmask=[allInt] minReg=1> DefList: { N059.t537. CNS_INT } N061 ( 4, 12) [000538] #---G------- * IND ref REG NA $105 BB04 regmask=[allInt] minReg=1 last> Interval 71: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB04 regmask=[allInt] minReg=1> DefList: { N061.t538. IND } N063 ( 4, 12) [001291] DA--G------- * STORE_LCL_VAR ref V73 cse8 d:1 NA REG NA BB04 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB04 regmask=[allInt] minReg=1 last> DefList: { } N065 (???,???) [001336] ------------ * IL_OFFSET void IL offset: 0x1e REG NA DefList: { } N067 ( 1, 1) [001294] ------------ * LCL_VAR ref V73 cse8 u:1 NA REG NA $105 DefList: { } N069 ( 1, 3) [000556] DA--G------- * STORE_LCL_VAR ref V35 tmp21 d:1 NA REG NA LCL_VAR BB04 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1 last> DefList: { } N071 (???,???) [001337] ------------ * IL_OFFSET void IL offset: 0x1e REG NA DefList: { } N073 ( 1, 1) [000546] ------------ * LCL_VAR int V33 tmp19 u:1 NA (last use) REG NA DefList: { } N075 ( 1, 1) [000547] -c---------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N077 ( 3, 3) [000548] J------N---- * NE void REG NA LCL_VAR BB04 regmask=[allInt] minReg=1 last> DefList: { } N079 ( 5, 5) [000549] ------------ * JTRUE void REG NA CHECKING LAST USES for BB04, liveout={V00 V01 V02 V03 V35 V73} ============================== Reporting this as generic context: referenced use: {V00} def: {V33 V34 V35 V73} NEW BLOCK BB05 Setting BB04 as the predecessor for determining incoming variable registers of BB05 DefList: { } N083 (???,???) [001338] ------------ * IL_OFFSET void IL offset: 0x1e REG NA DefList: { } N085 ( 1, 1) [000550] ------------ * LCL_VAR ref V35 tmp21 u:1 NA REG NA $105 DefList: { } N087 (???,???) [001457] ------------ * PUTARG_REG ref REG rcx BB05 regmask=[rcx] minReg=1> LCL_VAR BB05 regmask=[rcx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 72: ref RefPositions {} physReg:NA Preferences=[allInt] BB05 regmask=[rcx] minReg=1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> Assigning related to DefList: { N087.t1457. PUTARG_REG } N089 ( 1, 1) [000551] ------------ * LCL_VAR ref V35 tmp21 u:1 NA (last use) REG NA $105 DefList: { N087.t1457. PUTARG_REG } N091 (???,???) [001458] ------------ * PUTARG_REG ref REG rdx BB05 regmask=[rdx] minReg=1> LCL_VAR BB05 regmask=[rdx] minReg=1 last fixed> Interval 73: ref RefPositions {} physReg:NA Preferences=[allInt] BB05 regmask=[rdx] minReg=1> PUTARG_REG BB05 regmask=[rdx] minReg=1 fixed> DefList: { N087.t1457. PUTARG_REG; N091.t1458. PUTARG_REG } N093 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail REG NA $VN.Void BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> BB05 regmask=[rdx] minReg=1> BB05 regmask=[rdx] minReg=1 last fixed> BB05 regmask=[rax] minReg=1> BB05 regmask=[rcx] minReg=1> BB05 regmask=[rdx] minReg=1> BB05 regmask=[r8] minReg=1> BB05 regmask=[r9] minReg=1> BB05 regmask=[r10] minReg=1> BB05 regmask=[r11] minReg=1> CHECKING LAST USES for BB05, liveout={V00 V01 V02 V03 V73} ============================== Reporting this as generic context: referenced use: {V35} def: {} NEW BLOCK BB06 Setting BB04 as the predecessor for determining incoming variable registers of BB06 DefList: { } N097 (???,???) [001339] ------------ * IL_OFFSET void IL offset: 0x2c REG NA DefList: { } N099 ( 1, 1) [000015] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N101 ( 2, 2) [000822] -c---------- * LEA(b+16) byref REG NA Contained DefList: { } N103 ( 4, 4) [000016] n---GO------ * IND ref REG NA LCL_VAR BB06 regmask=[allInt] minReg=1 last> Interval 74: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB06 regmask=[allInt] minReg=1> DefList: { N103.t16. IND } N105 ( 4, 4) [000018] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:1 NA REG NA BB06 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB06 regmask=[allInt] minReg=1 last> DefList: { } N107 (???,???) [001340] ------------ * IL_OFFSET void IL offset: 0x33 REG NA DefList: { } N109 ( 1, 1) [000019] ------------ * LCL_VAR ref V04 loc0 u:1 NA REG NA DefList: { } N111 ( 1, 1) [000020] -c---------- * CNS_INT ref null REG NA $VN.Null Contained DefList: { } N113 ( 6, 3) [000021] N----------- * NE int REG NA LCL_VAR BB06 regmask=[allInt] minReg=1 last> Interval 75: int RefPositions {} physReg:NA Preferences=[allInt] NE BB06 regmask=[allInt] minReg=1> DefList: { N113.t21. NE } N115 ( 6, 3) [000566] DA---------- * STORE_LCL_VAR int V36 tmp22 d:1 NA REG NA BB06 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB06 regmask=[allInt] minReg=1 last> DefList: { } N117 (???,???) [001341] ------------ * IL_OFFSET void IL offset: 0x33 REG NA DefList: { } N119 ( 1, 1) [001295] ------------ * LCL_VAR ref V73 cse8 u:1 NA REG NA $105 DefList: { } N121 ( 1, 3) [000576] DA--G------- * STORE_LCL_VAR ref V37 tmp23 d:1 NA REG NA LCL_VAR BB06 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1 last> DefList: { } N123 (???,???) [001342] ------------ * IL_OFFSET void IL offset: 0x33 REG NA DefList: { } N125 ( 1, 1) [000568] ------------ * LCL_VAR int V36 tmp22 u:1 NA (last use) REG NA DefList: { } N127 ( 1, 1) [000569] -c---------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N129 ( 3, 3) [000570] J------N---- * NE void REG NA LCL_VAR BB06 regmask=[allInt] minReg=1 last> DefList: { } N131 ( 5, 5) [000571] ------------ * JTRUE void REG NA CHECKING LAST USES for BB06, liveout={V00 V01 V02 V03 V04 V37 V73} ============================== Reporting this as generic context: referenced use: {V00 V73} def: {V04 V36 V37} NEW BLOCK BB07 Setting BB06 as the predecessor for determining incoming variable registers of BB07 DefList: { } N135 (???,???) [001343] ------------ * IL_OFFSET void IL offset: 0x33 REG NA DefList: { } N137 ( 2, 10) [000823] H----------- * CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" REG NA $46 Interval 76: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB07 regmask=[allInt] minReg=1> DefList: { N137.t823. CNS_INT } N139 ( 4, 12) [000824] #---G------- * IND ref REG NA $106 BB07 regmask=[allInt] minReg=1 last> Interval 77: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB07 regmask=[allInt] minReg=1> DefList: { N139.t824. IND } N141 (???,???) [001459] ----G------- * PUTARG_REG ref REG rcx BB07 regmask=[rcx] minReg=1> BB07 regmask=[rcx] minReg=1 last fixed> Interval 78: ref RefPositions {} physReg:NA Preferences=[allInt] BB07 regmask=[rcx] minReg=1> PUTARG_REG BB07 regmask=[rcx] minReg=1 fixed> DefList: { N141.t1459. PUTARG_REG } N143 ( 1, 1) [000573] ------------ * LCL_VAR ref V37 tmp23 u:1 NA (last use) REG NA $105 DefList: { N141.t1459. PUTARG_REG } N145 (???,???) [001460] ------------ * PUTARG_REG ref REG rdx BB07 regmask=[rdx] minReg=1> LCL_VAR BB07 regmask=[rdx] minReg=1 last fixed> Interval 79: ref RefPositions {} physReg:NA Preferences=[allInt] BB07 regmask=[rdx] minReg=1> PUTARG_REG BB07 regmask=[rdx] minReg=1 fixed> DefList: { N141.t1459. PUTARG_REG; N145.t1460. PUTARG_REG } N147 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail REG NA $VN.Void BB07 regmask=[rcx] minReg=1> BB07 regmask=[rcx] minReg=1 last fixed> BB07 regmask=[rdx] minReg=1> BB07 regmask=[rdx] minReg=1 last fixed> BB07 regmask=[rax] minReg=1> BB07 regmask=[rcx] minReg=1> BB07 regmask=[rdx] minReg=1> BB07 regmask=[r8] minReg=1> BB07 regmask=[r9] minReg=1> BB07 regmask=[r10] minReg=1> BB07 regmask=[r11] minReg=1> CHECKING LAST USES for BB07, liveout={V00 V01 V02 V03 V04 V73} ============================== Reporting this as generic context: referenced use: {V37} def: {} NEW BLOCK BB08 Setting BB06 as the predecessor for determining incoming variable registers of BB08 DefList: { } N151 (???,???) [001344] ------------ * IL_OFFSET void IL offset: 0x41 REG NA DefList: { } N153 ( 1, 1) [000025] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N155 ( 2, 2) [000828] -c---------- * LEA(b+24) byref REG NA Contained DefList: { } N157 ( 4, 4) [000026] n---GO------ * IND ref REG NA LCL_VAR BB08 regmask=[allInt] minReg=1 last> Interval 80: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB08 regmask=[allInt] minReg=1> DefList: { N157.t26. IND } N159 ( 4, 4) [000028] DA--GO------ * STORE_LCL_VAR ref V05 loc1 d:1 NA REG NA BB08 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB08 regmask=[allInt] minReg=1 last> DefList: { } N161 (???,???) [001345] ------------ * IL_OFFSET void IL offset: 0x48 REG NA DefList: { } N163 ( 1, 1) [000029] ------------ * LCL_VAR ref V05 loc1 u:1 NA REG NA DefList: { } N165 ( 1, 1) [000030] -c---------- * CNS_INT ref null REG NA $VN.Null Contained DefList: { } N167 ( 3, 3) [000031] J------N---- * EQ void REG NA LCL_VAR BB08 regmask=[allInt] minReg=1 last> DefList: { } N169 ( 5, 5) [000032] ------------ * JTRUE void REG NA CHECKING LAST USES for BB08, liveout={V00 V01 V02 V03 V04 V05 V73} ============================== Reporting this as generic context: referenced use: {V00} def: {V05} NEW BLOCK BB09 Setting BB08 as the predecessor for determining incoming variable registers of BB09 DefList: { } N173 (???,???) [001346] ------------ * IL_OFFSET void IL offset: 0x4b REG NA DefList: { } N175 ( 1, 1) [000486] !----------- * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N177 ( 3, 2) [000487] #----O------ * IND long REG NA $2e8 LCL_VAR BB09 regmask=[allInt] minReg=1 last> Interval 81: long RefPositions {} physReg:NA Preferences=[allInt] IND BB09 regmask=[allInt] minReg=1> DefList: { N177.t487. IND } N179 ( 3, 3) [000489] DA---O------ * STORE_LCL_VAR long V29 tmp15 d:1 NA REG NA BB09 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB09 regmask=[allInt] minReg=1 last> DefList: { } N181 ( 1, 1) [000491] ------------ * LCL_VAR long V29 tmp15 u:1 NA REG NA $2e7 DefList: { } N183 ( 2, 2) [000493] -c---------- * LEA(b+56) long REG NA Contained DefList: { } N185 ( 4, 4) [000494] #----------- * IND long REG NA $2e9 LCL_VAR BB09 regmask=[allInt] minReg=1 last> Interval 82: long RefPositions {} physReg:NA Preferences=[allInt] IND BB09 regmask=[allInt] minReg=1> DefList: { N185.t494. IND } N187 ( 7, 6) [000495] #----------- * IND long REG NA $2ea BB09 regmask=[allInt] minReg=1 last> Interval 83: long RefPositions {} physReg:NA Preferences=[allInt] IND BB09 regmask=[allInt] minReg=1> DefList: { N187.t495. IND } N189 ( 8, 7) [000497] -c---------- * LEA(b+64) long REG NA Contained DefList: { N187.t495. IND } N191 ( 10, 9) [000501] n----------- * IND long REG NA BB09 regmask=[allInt] minReg=1 last> Interval 84: long RefPositions {} physReg:NA Preferences=[allInt] IND BB09 regmask=[allInt] minReg=1> DefList: { N191.t501. IND } N193 ( 14, 12) [001266] DA---------- * STORE_LCL_VAR long V68 cse3 d:1 NA REG NA BB09 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB09 regmask=[allInt] minReg=1 last> DefList: { } N195 ( 3, 2) [001267] ------------ * LCL_VAR long V68 cse3 u:1 NA REG NA DefList: { } N197 ( 1, 1) [000504] -c---------- * CNS_INT long 0 REG NA $243 Contained DefList: { } N199 ( 19, 16) [000505] J------N---- * EQ void REG NA LCL_VAR BB09 regmask=[allInt] minReg=1 last> DefList: { } N201 ( 21, 18) [001148] ------------ * JTRUE void REG NA CHECKING LAST USES for BB09, liveout={V00 V01 V02 V03 V04 V05 V29 V68 V73} ============================== Reporting this as generic context: referenced use: {V00} def: {V29 V68} NEW BLOCK BB10 Setting BB09 as the predecessor for determining incoming variable registers of BB10 DefList: { } N205 ( 3, 2) [001269] ------------ * LCL_VAR long V68 cse3 u:1 NA (last use) REG NA DefList: { } N207 ( 3, 3) [001150] DA---------- * STORE_LCL_VAR long V31 tmp17 d:3 NA REG NA LCL_VAR BB10 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB10 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB10, liveout={V00 V01 V02 V03 V04 V05 V31 V73} ============================== Reporting this as generic context: referenced use: {V68} def: {V31} NEW BLOCK BB11 Setting BB09 as the predecessor for determining incoming variable registers of BB11 DefList: { } N211 ( 1, 1) [000490] ------?----- * LCL_VAR long V29 tmp15 u:1 NA (last use) REG NA $2e7 DefList: { } N213 (???,???) [001461] ------------ * PUTARG_REG long REG rcx BB11 regmask=[rcx] minReg=1> LCL_VAR BB11 regmask=[rcx] minReg=1 last fixed> Interval 85: long RefPositions {} physReg:NA Preferences=[allInt] BB11 regmask=[rcx] minReg=1> PUTARG_REG BB11 regmask=[rcx] minReg=1 fixed> DefList: { N213.t1461. PUTARG_REG } N215 ( 2, 10) [000502] H-----?----- * CNS_INT(h) long 0xd1ffab1e global ptr REG NA $49 Interval 86: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB11 regmask=[allInt] minReg=1> DefList: { N213.t1461. PUTARG_REG; N215.t502. CNS_INT } N217 (???,???) [001462] ------------ * PUTARG_REG long REG rdx BB11 regmask=[rdx] minReg=1> BB11 regmask=[rdx] minReg=1 last fixed> Interval 87: long RefPositions {} physReg:NA Preferences=[allInt] BB11 regmask=[rdx] minReg=1> PUTARG_REG BB11 regmask=[rdx] minReg=1 fixed> DefList: { N213.t1461. PUTARG_REG; N217.t1462. PUTARG_REG } N219 ( 17, 18) [000503] --C-G-?----- * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS REG NA $308 BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> BB11 regmask=[rdx] minReg=1> BB11 regmask=[rdx] minReg=1 last fixed> BB11 regmask=[rax] minReg=1> BB11 regmask=[rcx] minReg=1> BB11 regmask=[rdx] minReg=1> BB11 regmask=[r8] minReg=1> BB11 regmask=[r9] minReg=1> BB11 regmask=[r10] minReg=1> BB11 regmask=[r11] minReg=1> Interval 88: long RefPositions {} physReg:NA Preferences=[allInt] BB11 regmask=[rax] minReg=1> CALL BB11 regmask=[rax] minReg=1 fixed> DefList: { N219.t503. CALL } N221 ( 17, 18) [001152] DA--G------- * STORE_LCL_VAR long V31 tmp17 d:2 NA REG NA BB11 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB11 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB11, liveout={V00 V01 V02 V03 V04 V05 V31 V73} ============================== Reporting this as generic context: referenced use: {V29} def: {V31} NEW BLOCK BB12 Setting BB10 as the predecessor for determining incoming variable registers of BB12 DefList: { } N225 ( 1, 1) [000484] ------------ * LCL_VAR ref V05 loc1 u:1 NA REG NA DefList: { } N227 (???,???) [001463] ------------ * PUTARG_REG ref REG rcx BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 89: ref RefPositions {} physReg:NA Preferences=[allInt] BB12 regmask=[rcx] minReg=1> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> Assigning related to DefList: { N227.t1463. PUTARG_REG } N229 ( 1, 1) [000831] ------------ * LCL_VAR long V31 tmp17 u:1 r11 REG r11 $342 DefList: { N227.t1463. PUTARG_REG } N231 (???,???) [001464] ------------ * PUTARG_REG long REG r11 BB12 regmask=[r11] minReg=1> LCL_VAR BB12 regmask=[r11] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 90: long RefPositions {} physReg:NA Preferences=[allInt] BB12 regmask=[r11] minReg=1> PUTARG_REG BB12 regmask=[r11] minReg=1 fixed> Assigning related to DefList: { N227.t1463. PUTARG_REG; N231.t1464. PUTARG_REG } N233 ( 1, 1) [000500] ------------ * LCL_VAR ref V01 arg1 u:1 NA REG NA $101 DefList: { N227.t1463. PUTARG_REG; N231.t1464. PUTARG_REG } N235 (???,???) [001465] ------------ * PUTARG_REG ref REG rdx BB12 regmask=[rdx] minReg=1> LCL_VAR BB12 regmask=[rdx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 91: ref RefPositions {} physReg:NA Preferences=[allInt] BB12 regmask=[rdx] minReg=1> PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed> Assigning related to DefList: { N227.t1463. PUTARG_REG; N231.t1464. PUTARG_REG; N235.t1465. PUTARG_REG } N237 ( 1, 1) [000521] ------------ * LCL_VAR long V31 tmp17 u:1 NA (last use) REG NA $342 DefList: { N227.t1463. PUTARG_REG; N231.t1464. PUTARG_REG; N235.t1465. PUTARG_REG } N239 (???,???) [001466] Dc---------- * IND long REG NA Contained DefList: { N227.t1463. PUTARG_REG; N231.t1464. PUTARG_REG; N235.t1465. PUTARG_REG } N241 ( 27, 12) [000522] --CXG------- * CALL ind stub int REG NA $1c7 BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> BB12 regmask=[r11] minReg=1> BB12 regmask=[r11] minReg=1 last fixed> BB12 regmask=[rdx] minReg=1> BB12 regmask=[rdx] minReg=1 last fixed> LCL_VAR BB12 regmask=[allInt] minReg=1 last> BB12 regmask=[rax] minReg=1> BB12 regmask=[rcx] minReg=1> BB12 regmask=[rdx] minReg=1> BB12 regmask=[r8] minReg=1> BB12 regmask=[r9] minReg=1> BB12 regmask=[r10] minReg=1> BB12 regmask=[r11] minReg=1> Interval 92: int RefPositions {} physReg:NA Preferences=[allInt] BB12 regmask=[rax] minReg=1> CALL BB12 regmask=[rax] minReg=1 fixed> DefList: { N241.t522. CALL } N243 ( 31, 15) [000524] DA-XG------- * STORE_LCL_VAR int V15 tmp1 d:3 NA REG NA BB12 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB12 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB12, liveout={V00 V01 V02 V03 V04 V05 V15 V73} ============================== Reporting this as generic context: referenced use: {V01 V05 V31} def: {V15} NEW BLOCK BB13 Setting BB08 as the predecessor for determining incoming variable registers of BB13 DefList: { } N247 (???,???) [001347] ------------ * IL_OFFSET void IL offset: 0x54 REG NA DefList: { } N249 ( 1, 1) [000033] ------------ * LCL_VAR ref V01 arg1 u:1 NA REG NA $101 DefList: { } N251 (???,???) [001467] ------------ * PUTARG_REG ref REG rcx BB13 regmask=[rcx] minReg=1> LCL_VAR BB13 regmask=[rcx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 93: ref RefPositions {} physReg:NA Preferences=[allInt] BB13 regmask=[rcx] minReg=1> PUTARG_REG BB13 regmask=[rcx] minReg=1 fixed> Assigning related to DefList: { N251.t1467. PUTARG_REG } N253 ( 1, 1) [000836] ------------ * LCL_VAR ref V01 arg1 u:1 NA REG NA $101 DefList: { N251.t1467. PUTARG_REG } N255 ( 3, 2) [000837] #----O------ * IND long REG NA $2e4 LCL_VAR BB13 regmask=[allInt] minReg=1 last> Interval 94: long RefPositions {} physReg:NA Preferences=[allInt] IND BB13 regmask=[allInt] minReg=1> DefList: { N251.t1467. PUTARG_REG; N255.t837. IND } N257 ( 4, 3) [000839] -c---------- * LEA(b+72) long REG NA Contained DefList: { N251.t1467. PUTARG_REG; N255.t837. IND } N259 ( 6, 5) [000840] #----O------ * IND long REG NA $2e6 BB13 regmask=[allInt] minReg=1 last> Interval 95: long RefPositions {} physReg:NA Preferences=[allInt] IND BB13 regmask=[allInt] minReg=1> DefList: { N251.t1467. PUTARG_REG; N259.t840. IND } N261 ( 7, 6) [000842] -c---------- * LEA(b+24) long REG NA Contained DefList: { N251.t1467. PUTARG_REG; N259.t840. IND } N263 ( 9, 8) [000843] nc---O------ * IND long REG NA Contained DefList: { N251.t1467. PUTARG_REG; N259.t840. IND } N265 ( 30, 18) [000035] --CXGO------ * CALLV vt-ind int System.Object.GetHashCode REG NA $1c5 BB13 regmask=[rcx] minReg=1> BB13 regmask=[rcx] minReg=1 last fixed> BB13 regmask=[allInt] minReg=1 last> BB13 regmask=[rax] minReg=1> BB13 regmask=[rcx] minReg=1> BB13 regmask=[rdx] minReg=1> BB13 regmask=[r8] minReg=1> BB13 regmask=[r9] minReg=1> BB13 regmask=[r10] minReg=1> BB13 regmask=[r11] minReg=1> Interval 96: int RefPositions {} physReg:NA Preferences=[allInt] BB13 regmask=[rax] minReg=1> CALL BB13 regmask=[rax] minReg=1 fixed> DefList: { N265.t35. CALL } N267 ( 34, 21) [000038] DA-XGO------ * STORE_LCL_VAR int V15 tmp1 d:2 NA REG NA BB13 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB13 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB13, liveout={V00 V01 V02 V03 V04 V05 V15 V73} ============================== Reporting this as generic context: referenced use: {V01} def: {V15} NEW BLOCK BB14 Setting BB12 as the predecessor for determining incoming variable registers of BB14 DefList: { } N271 ( 3, 2) [000040] ------------ * LCL_VAR int V15 tmp1 u:1 NA (last use) REG NA $3c0 DefList: { } N273 ( 3, 3) [000042] DA---------- * STORE_LCL_VAR int V06 loc2 d:1 NA REG NA LCL_VAR BB14 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB14 regmask=[allInt] minReg=1 last> DefList: { } N275 (???,???) [001348] ------------ * IL_OFFSET void IL offset: 0x62 REG NA DefList: { } N277 ( 1, 1) [000043] ------------ * CNS_INT int 0 REG NA $c0 Interval 97: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB14 regmask=[allInt] minReg=1> DefList: { N277.t43. CNS_INT } N279 ( 1, 3) [000045] DA---------- * STORE_LCL_VAR int V07 loc3 d:1 NA REG NA BB14 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB14 regmask=[allInt] minReg=1 last> DefList: { } N281 (???,???) [001349] ------------ * IL_OFFSET void IL offset: 0x64 REG NA DefList: { } N283 ( 1, 1) [000046] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N285 ( 2, 2) [000845] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N287 ( 4, 4) [000578] n---GO------ * IND ref REG NA LCL_VAR BB14 regmask=[allInt] minReg=1 last> Interval 98: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB14 regmask=[allInt] minReg=1> DefList: { N287.t578. IND } N289 ( 4, 4) [000580] DA--GO------ * STORE_LCL_VAR ref V39 tmp25 d:1 NA REG NA BB14 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB14 regmask=[allInt] minReg=1 last> DefList: { } N291 (???,???) [001350] ------------ * IL_OFFSET void IL offset: 0x64 REG NA DefList: { } N293 ( 1, 1) [000582] ------------ * LCL_VAR ref V39 tmp25 u:1 NA REG NA DefList: { } N295 (???,???) [001441] -c---------- * LEA(b+8) ref REG NA Contained DefList: { } N297 ( 3, 3) [000583] ---X-------- * IND int REG NA LCL_VAR BB14 regmask=[allInt] minReg=1 last> Interval 99: int RefPositions {} physReg:NA Preferences=[allInt] IND BB14 regmask=[allInt] minReg=1> DefList: { N297.t583. IND } N299 ( 3, 3) [000629] DA-X-------- * STORE_LCL_VAR int V40 tmp26 d:1 NA REG NA BB14 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB14 regmask=[allInt] minReg=1 last> DefList: { } N301 (???,???) [001351] ------------ * IL_OFFSET void IL offset: 0x64 REG NA DefList: { } N303 ( 1, 1) [000584] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N305 ( 2, 2) [000847] -c---------- * LEA(b+48) byref REG NA Contained DefList: { } N307 ( 4, 4) [000585] n---GO------ * IND long REG NA LCL_VAR BB14 regmask=[allInt] minReg=1 last> Interval 100: long RefPositions {} physReg:NA Preferences=[allInt] IND BB14 regmask=[allInt] minReg=1> DefList: { N307.t585. IND } N309 ( 4, 4) [000631] DA--GO------ * STORE_LCL_VAR long V41 tmp27 d:1 NA REG NA BB14 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB14 regmask=[allInt] minReg=1 last> DefList: { } N311 (???,???) [001352] ------------ * IL_OFFSET void IL offset: 0x64 REG NA DefList: { } N313 ( 1, 1) [000597] ------------ * LCL_VAR int V40 tmp26 u:1 NA REG NA DefList: { } N315 ( 1, 4) [000598] -c---------- * CNS_INT int 0x7FFFFFFF REG NA $ce Contained DefList: { } N317 ( 6, 6) [000599] N--------U-- * LE int REG NA LCL_VAR BB14 regmask=[allInt] minReg=1 last> Interval 101: int RefPositions {} physReg:NA Preferences=[allInt] LE BB14 regmask=[allInt] minReg=1> DefList: { N317.t599. LE } N319 ( 6, 6) [000642] DA---------- * STORE_LCL_VAR int V43 tmp29 d:1 NA REG NA BB14 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB14 regmask=[allInt] minReg=1 last> DefList: { } N321 (???,???) [001353] ------------ * IL_OFFSET void IL offset: 0x64 REG NA DefList: { } N323 (???,???) [001354] ------------ * IL_OFFSET void IL offset: 0x64 REG NA DefList: { } N325 ( 1, 1) [001297] ------------ * LCL_VAR ref V73 cse8 u:1 NA REG NA $105 DefList: { } N327 ( 1, 3) [000654] DA--G------- * STORE_LCL_VAR ref V45 tmp31 d:1 NA REG NA LCL_VAR BB14 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB14 regmask=[allInt] minReg=1 last> DefList: { } N329 (???,???) [001355] ------------ * IL_OFFSET void IL offset: 0x64 REG NA DefList: { } N331 ( 1, 1) [000644] ------------ * LCL_VAR int V43 tmp29 u:1 NA (last use) REG NA DefList: { } N333 ( 1, 1) [000645] -c---------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N335 ( 3, 3) [000646] J------N---- * NE void REG NA LCL_VAR BB14 regmask=[allInt] minReg=1 last> DefList: { } N337 ( 5, 5) [000647] ------------ * JTRUE void REG NA CHECKING LAST USES for BB14, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V45 V73} ============================== Reporting this as generic context: referenced use: {V00 V15 V73} def: {V06 V07 V39 V40 V41 V43 V44 V45} NEW BLOCK BB15 Setting BB14 as the predecessor for determining incoming variable registers of BB15 DefList: { } N341 (???,???) [001356] ------------ * IL_OFFSET void IL offset: 0x64 REG NA DefList: { } N343 ( 1, 1) [000648] ------------ * LCL_VAR ref V45 tmp31 u:1 NA REG NA $105 DefList: { } N345 (???,???) [001468] ------------ * PUTARG_REG ref REG rcx BB15 regmask=[rcx] minReg=1> LCL_VAR BB15 regmask=[rcx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 102: ref RefPositions {} physReg:NA Preferences=[allInt] BB15 regmask=[rcx] minReg=1> PUTARG_REG BB15 regmask=[rcx] minReg=1 fixed> Assigning related to DefList: { N345.t1468. PUTARG_REG } N347 ( 1, 1) [000649] ------------ * LCL_VAR ref V45 tmp31 u:1 NA (last use) REG NA $105 DefList: { N345.t1468. PUTARG_REG } N349 (???,???) [001469] ------------ * PUTARG_REG ref REG rdx BB15 regmask=[rdx] minReg=1> LCL_VAR BB15 regmask=[rdx] minReg=1 last fixed> Interval 103: ref RefPositions {} physReg:NA Preferences=[allInt] BB15 regmask=[rdx] minReg=1> PUTARG_REG BB15 regmask=[rdx] minReg=1 fixed> DefList: { N345.t1468. PUTARG_REG; N349.t1469. PUTARG_REG } N351 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail REG NA $VN.Void BB15 regmask=[rcx] minReg=1> BB15 regmask=[rcx] minReg=1 last fixed> BB15 regmask=[rdx] minReg=1> BB15 regmask=[rdx] minReg=1 last fixed> BB15 regmask=[rax] minReg=1> BB15 regmask=[rcx] minReg=1> BB15 regmask=[rdx] minReg=1> BB15 regmask=[r8] minReg=1> BB15 regmask=[r9] minReg=1> BB15 regmask=[r10] minReg=1> BB15 regmask=[r11] minReg=1> CHECKING LAST USES for BB15, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V73} ============================== Reporting this as generic context: referenced use: {V45} def: {} NEW BLOCK BB16 Setting BB14 as the predecessor for determining incoming variable registers of BB16 DefList: { } N355 (???,???) [001357] ------------ * IL_OFFSET void IL offset: 0x64 REG NA DefList: { } N357 ( 1, 1) [000604] ------------ * LCL_VAR long V41 tmp27 u:1 NA (last use) REG NA DefList: { } N359 ( 1, 1) [000047] ------------ * LCL_VAR int V06 loc2 u:1 NA REG NA $3c0 DefList: { } N361 ( 2, 3) [000605] ---------U-- * CAST long <- ulong <- uint REG NA $310 LCL_VAR BB16 regmask=[allInt] minReg=1 last> Interval 104: long RefPositions {} physReg:NA Preferences=[allInt] CAST BB16 regmask=[allInt] minReg=1> DefList: { N361.t605. CAST } N363 ( 7, 7) [000606] ------------ * MUL long REG NA LCL_VAR BB16 regmask=[allInt] minReg=1 last> BB16 regmask=[allInt] minReg=1 last> Interval 105: long RefPositions {} physReg:NA Preferences=[allInt] MUL BB16 regmask=[allInt] minReg=1> Assigning related to Assigning related to DefList: { N363.t606. MUL } N365 ( 1, 1) [000607] -c---------- * CNS_INT int 32 REG NA $d2 Contained DefList: { N363.t606. MUL } N367 ( 9, 9) [000608] ------------ * RSZ long REG NA BB16 regmask=[allInt] minReg=1 last> Interval 106: long RefPositions {} physReg:NA Preferences=[allInt] RSZ BB16 regmask=[allInt] minReg=1> Assigning related to DefList: { N367.t608. RSZ } N369 ( 1, 1) [000610] -c---------- * CNS_INT long 1 REG NA $247 Contained DefList: { N367.t608. RSZ } N371 ( 11, 11) [000611] ------------ * ADD long REG NA BB16 regmask=[allInt] minReg=1 last> Interval 107: long RefPositions {} physReg:NA Preferences=[allInt] ADD BB16 regmask=[allInt] minReg=1> Assigning related to DefList: { N371.t611. ADD } N373 ( 1, 1) [000612] ------------ * LCL_VAR int V40 tmp26 u:1 NA REG NA DefList: { N371.t611. ADD } N375 ( 2, 3) [000613] ---------U-- * CAST long <- ulong <- uint REG NA LCL_VAR BB16 regmask=[allInt] minReg=1 last> Interval 108: long RefPositions {} physReg:NA Preferences=[allInt] CAST BB16 regmask=[allInt] minReg=1> DefList: { N371.t611. ADD; N375.t613. CAST } N377 ( 17, 17) [000614] ------------ * MUL long REG NA BB16 regmask=[allInt] minReg=1 last> BB16 regmask=[allInt] minReg=1 last> Interval 109: long RefPositions {} physReg:NA Preferences=[allInt] MUL BB16 regmask=[allInt] minReg=1> Assigning related to Assigning related to DefList: { N377.t614. MUL } N379 ( 1, 1) [000615] -c---------- * CNS_INT int 32 REG NA $d2 Contained DefList: { N377.t614. MUL } N381 ( 19, 19) [000616] ------------ * RSZ long REG NA BB16 regmask=[allInt] minReg=1 last> Interval 110: long RefPositions {} physReg:NA Preferences=[allInt] RSZ BB16 regmask=[allInt] minReg=1> Assigning related to DefList: { N381.t616. RSZ } N383 ( 20, 21) [000617] ------------ * CAST int <- uint <- long REG NA BB16 regmask=[allInt] minReg=1 last> Interval 111: int RefPositions {} physReg:NA Preferences=[allInt] CAST BB16 regmask=[allInt] minReg=1> DefList: { N383.t617. CAST } N385 ( 20, 21) [000619] DA---------- * STORE_LCL_VAR int V42 tmp28 d:1 NA REG NA BB16 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB16 regmask=[allInt] minReg=1 last> DefList: { } N387 (???,???) [001358] ------------ * IL_OFFSET void IL offset: 0x64 REG NA DefList: { } N389 ( 1, 1) [000621] ------------ * LCL_VAR int V06 loc2 u:1 NA REG NA $3c0 DefList: { } N391 ( 1, 1) [000622] ------------ * LCL_VAR int V40 tmp26 u:1 NA (last use) REG NA DefList: { } N393 ( 22, 5) [000623] ---X-------- * UMOD int REG NA BB16 regmask=[rax] minReg=1> LCL_VAR BB16 regmask=[rax] minReg=1 last fixed> LCL_VAR BB16 regmask=[rcx rbx rbp rsi rdi r8-r15] minReg=1 last> BB16 regmask=[rax] minReg=1> BB16 regmask=[rdx] minReg=1> Interval 112: int RefPositions {} physReg:NA Preferences=[allInt] BB16 regmask=[rdx] minReg=1> UMOD BB16 regmask=[rdx] minReg=1 fixed> DefList: { N393.t623. UMOD } N395 ( 1, 1) [000620] ------------ * LCL_VAR int V42 tmp28 u:1 NA REG NA DefList: { N393.t623. UMOD } N397 ( 27, 7) [000624] ---X-------- * EQ int REG NA BB16 regmask=[allInt] minReg=1 last> LCL_VAR BB16 regmask=[allInt] minReg=1 last> Interval 113: int RefPositions {} physReg:NA Preferences=[allInt] EQ BB16 regmask=[allInt] minReg=1> DefList: { N397.t624. EQ } N399 ( 27, 7) [000665] DA-X-------- * STORE_LCL_VAR int V46 tmp32 d:1 NA REG NA BB16 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB16 regmask=[allInt] minReg=1 last> DefList: { } N401 (???,???) [001359] ------------ * IL_OFFSET void IL offset: 0x64 REG NA DefList: { } N403 (???,???) [001360] ------------ * IL_OFFSET void IL offset: 0x64 REG NA DefList: { } N405 ( 1, 1) [001299] ------------ * LCL_VAR ref V73 cse8 u:1 NA REG NA $105 DefList: { } N407 ( 1, 3) [000677] DA--G------- * STORE_LCL_VAR ref V48 tmp34 d:1 NA REG NA LCL_VAR BB16 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB16 regmask=[allInt] minReg=1 last> DefList: { } N409 (???,???) [001361] ------------ * IL_OFFSET void IL offset: 0x64 REG NA DefList: { } N411 ( 1, 1) [000667] ------------ * LCL_VAR int V46 tmp32 u:1 NA (last use) REG NA DefList: { } N413 ( 1, 1) [000668] -c---------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N415 ( 3, 3) [000669] J------N---- * NE void REG NA LCL_VAR BB16 regmask=[allInt] minReg=1 last> DefList: { } N417 ( 5, 5) [000670] ------------ * JTRUE void REG NA CHECKING LAST USES for BB16, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V48 V73} ============================== Reporting this as generic context: referenced use: {V06 V40 V41 V73} def: {V42 V46 V47 V48} NEW BLOCK BB17 Setting BB16 as the predecessor for determining incoming variable registers of BB17 DefList: { } N421 (???,???) [001362] ------------ * IL_OFFSET void IL offset: 0x64 REG NA DefList: { } N423 ( 1, 1) [000671] ------------ * LCL_VAR ref V48 tmp34 u:1 NA REG NA $105 DefList: { } N425 (???,???) [001470] ------------ * PUTARG_REG ref REG rcx BB17 regmask=[rcx] minReg=1> LCL_VAR BB17 regmask=[rcx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 114: ref RefPositions {} physReg:NA Preferences=[allInt] BB17 regmask=[rcx] minReg=1> PUTARG_REG BB17 regmask=[rcx] minReg=1 fixed> Assigning related to DefList: { N425.t1470. PUTARG_REG } N427 ( 1, 1) [000672] ------------ * LCL_VAR ref V48 tmp34 u:1 NA (last use) REG NA $105 DefList: { N425.t1470. PUTARG_REG } N429 (???,???) [001471] ------------ * PUTARG_REG ref REG rdx BB17 regmask=[rdx] minReg=1> LCL_VAR BB17 regmask=[rdx] minReg=1 last fixed> Interval 115: ref RefPositions {} physReg:NA Preferences=[allInt] BB17 regmask=[rdx] minReg=1> PUTARG_REG BB17 regmask=[rdx] minReg=1 fixed> DefList: { N425.t1470. PUTARG_REG; N429.t1471. PUTARG_REG } N431 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail REG NA $VN.Void BB17 regmask=[rcx] minReg=1> BB17 regmask=[rcx] minReg=1 last fixed> BB17 regmask=[rdx] minReg=1> BB17 regmask=[rdx] minReg=1 last fixed> BB17 regmask=[rax] minReg=1> BB17 regmask=[rcx] minReg=1> BB17 regmask=[rdx] minReg=1> BB17 regmask=[r8] minReg=1> BB17 regmask=[r9] minReg=1> BB17 regmask=[r10] minReg=1> BB17 regmask=[r11] minReg=1> CHECKING LAST USES for BB17, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V73} ============================== Reporting this as generic context: referenced use: {V48} def: {} NEW BLOCK BB18 Setting BB16 as the predecessor for determining incoming variable registers of BB18 DefList: { } N435 (???,???) [001363] ------------ * IL_OFFSET void IL offset: 0x64 REG NA DefList: { } N437 ( 1, 1) [000627] ------------ * LCL_VAR int V42 tmp28 u:1 NA REG NA DefList: { } N439 ( 1, 1) [000581] ------------ * LCL_VAR ref V39 tmp25 u:1 NA REG NA DefList: { } N441 (???,???) [001443] -c---------- * LEA(b+8) ref REG NA Contained DefList: { } N443 ( 3, 3) [000854] -c-X-------- * IND int REG NA Contained DefList: { } N445 ( 8, 11) [000855] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void REG NA LCL_VAR BB18 regmask=[allInt] minReg=1 last> LCL_VAR BB18 regmask=[allInt] minReg=1 last> DefList: { } N447 ( 1, 1) [000852] ------------ * LCL_VAR ref V39 tmp25 u:1 NA (last use) REG NA DefList: { } N449 ( 1, 1) [000853] ------------ * LCL_VAR int V42 tmp28 u:1 NA (last use) REG NA DefList: { } N451 ( 2, 3) [000856] ------------ * CAST long <- int REG NA LCL_VAR BB18 regmask=[allInt] minReg=1 last> Interval 116: long RefPositions {} physReg:NA Preferences=[allInt] CAST BB18 regmask=[allInt] minReg=1> DefList: { N451.t856. CAST } N453 ( 5, 6) [000861] -------N---- * LEA(b+(i*4)+16) byref REG NA LCL_VAR BB18 regmask=[allInt] minReg=1 last> BB18 regmask=[allInt] minReg=1 last> Interval 117: byref RefPositions {} physReg:NA Preferences=[allInt] LEA BB18 regmask=[allInt] minReg=1> DefList: { N453.t861. LEA } N455 ( 19, 24) [000591] DA-XG------- * STORE_LCL_VAR byref V38 tmp24 d:1 NA REG NA BB18 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB18 regmask=[allInt] minReg=1 last> DefList: { } N457 ( 1, 1) [000592] ------------ * LCL_VAR byref V38 tmp24 u:1 NA (last use) REG NA $81 DefList: { } N459 ( 5, 4) [000051] DA---------- * STORE_LCL_VAR byref V08 loc4 d:1 NA REG NA LCL_VAR BB18 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB18 regmask=[allInt] minReg=1 last> DefList: { } N461 (???,???) [001364] ------------ * IL_OFFSET void IL offset: 0x6d REG NA DefList: { } N463 ( 1, 1) [000052] ------------ * LCL_VAR byref V08 loc4 u:1 NA REG NA $81 DefList: { } N465 ( 3, 2) [000053] *--XG------- * IND int REG NA LCL_VAR BB18 regmask=[allInt] minReg=1 last> Interval 118: int RefPositions {} physReg:NA Preferences=[allInt] IND BB18 regmask=[allInt] minReg=1> DefList: { N465.t53. IND } N467 ( 1, 1) [000054] -c---------- * CNS_INT int -1 REG NA $c4 Contained DefList: { N465.t53. IND } N469 ( 5, 4) [000055] ---XG------- * ADD int REG NA BB18 regmask=[allInt] minReg=1 last> Interval 119: int RefPositions {} physReg:NA Preferences=[allInt] ADD BB18 regmask=[allInt] minReg=1> Assigning related to DefList: { N469.t55. ADD } N471 ( 5, 4) [000057] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:1 NA REG NA BB18 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB18 regmask=[allInt] minReg=1 last> DefList: { } N473 (???,???) [001365] ------------ * IL_OFFSET void IL offset: 0x74 REG NA DefList: { } N475 ( 1, 1) [000058] ------------ * LCL_VAR ref V05 loc1 u:1 NA REG NA DefList: { } N477 ( 1, 1) [000059] -c---------- * CNS_INT ref null REG NA $VN.Null Contained DefList: { } N479 ( 3, 3) [000060] J------N---- * NE void REG NA LCL_VAR BB18 regmask=[allInt] minReg=1 last> DefList: { } N481 ( 5, 5) [000061] ------------ * JTRUE void REG NA CHECKING LAST USES for BB18, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} ============================== Reporting this as generic context: referenced use: {V05 V39 V42} def: {V08 V09 V38} NEW BLOCK BB19 Setting BB18 as the predecessor for determining incoming variable registers of BB19 DefList: { } N485 (???,???) [001366] ------------ * IL_OFFSET void IL offset: 0xff REG NA DefList: { } N487 ( 1, 1) [000353] !----------- * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N489 ( 3, 2) [000354] #----O------ * IND long REG NA $2e8 LCL_VAR BB19 regmask=[allInt] minReg=1 last> Interval 120: long RefPositions {} physReg:NA Preferences=[allInt] IND BB19 regmask=[allInt] minReg=1> DefList: { N489.t354. IND } N491 ( 3, 3) [000356] DA---O------ * STORE_LCL_VAR long V24 tmp10 d:1 NA REG NA BB19 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB19 regmask=[allInt] minReg=1 last> DefList: { } N493 ( 1, 1) [000358] ------------ * LCL_VAR long V24 tmp10 u:1 NA REG NA $2e7 DefList: { } N495 ( 2, 2) [000360] -c---------- * LEA(b+56) long REG NA Contained DefList: { } N497 ( 4, 4) [000361] #----------- * IND long REG NA $2e9 LCL_VAR BB19 regmask=[allInt] minReg=1 last> Interval 121: long RefPositions {} physReg:NA Preferences=[allInt] IND BB19 regmask=[allInt] minReg=1> DefList: { N497.t361. IND } N499 ( 7, 6) [000362] #----------- * IND long REG NA $2ea BB19 regmask=[allInt] minReg=1 last> Interval 122: long RefPositions {} physReg:NA Preferences=[allInt] IND BB19 regmask=[allInt] minReg=1> DefList: { N499.t362. IND } N501 ( 8, 7) [000364] -c---------- * LEA(b+32) long REG NA Contained DefList: { N499.t362. IND } N503 ( 10, 9) [000365] n----------- * IND long REG NA BB19 regmask=[allInt] minReg=1 last> Interval 123: long RefPositions {} physReg:NA Preferences=[allInt] IND BB19 regmask=[allInt] minReg=1> DefList: { N503.t365. IND } N505 ( 14, 12) [001271] DA---------- * STORE_LCL_VAR long V69 cse4 d:1 NA REG NA BB19 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB19 regmask=[allInt] minReg=1 last> DefList: { } N507 ( 3, 2) [001272] ------------ * LCL_VAR long V69 cse4 u:1 NA REG NA DefList: { } N509 ( 1, 1) [000368] -c---------- * CNS_INT long 0 REG NA $243 Contained DefList: { } N511 ( 19, 16) [000369] J------N---- * EQ void REG NA LCL_VAR BB19 regmask=[allInt] minReg=1 last> DefList: { } N513 ( 21, 18) [001153] ------------ * JTRUE void REG NA CHECKING LAST USES for BB19, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V24 V69 V73} ============================== Reporting this as generic context: referenced use: {V00} def: {V24 V69} NEW BLOCK BB20 Setting BB19 as the predecessor for determining incoming variable registers of BB20 DefList: { } N517 ( 3, 2) [001274] ------------ * LCL_VAR long V69 cse4 u:1 NA (last use) REG NA DefList: { } N519 ( 7, 5) [001155] DA---------- * STORE_LCL_VAR long V25 tmp11 d:3 NA REG NA LCL_VAR BB20 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB20 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB20, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V25 V73} ============================== Reporting this as generic context: referenced use: {V69} def: {V25} NEW BLOCK BB21 Setting BB19 as the predecessor for determining incoming variable registers of BB21 DefList: { } N523 ( 1, 1) [000357] ------?----- * LCL_VAR long V24 tmp10 u:1 NA (last use) REG NA $2e7 DefList: { } N525 (???,???) [001472] ------------ * PUTARG_REG long REG rcx BB21 regmask=[rcx] minReg=1> LCL_VAR BB21 regmask=[rcx] minReg=1 last fixed> Interval 124: long RefPositions {} physReg:NA Preferences=[allInt] BB21 regmask=[rcx] minReg=1> PUTARG_REG BB21 regmask=[rcx] minReg=1 fixed> DefList: { N525.t1472. PUTARG_REG } N527 ( 2, 10) [000366] H-----?----- * CNS_INT(h) long 0xd1ffab1e global ptr REG NA $4f Interval 125: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB21 regmask=[allInt] minReg=1> DefList: { N525.t1472. PUTARG_REG; N527.t366. CNS_INT } N529 (???,???) [001473] ------------ * PUTARG_REG long REG rdx BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1 last fixed> Interval 126: long RefPositions {} physReg:NA Preferences=[allInt] BB21 regmask=[rdx] minReg=1> PUTARG_REG BB21 regmask=[rdx] minReg=1 fixed> DefList: { N525.t1472. PUTARG_REG; N529.t1473. PUTARG_REG } N531 ( 17, 18) [000367] --C-G-?----- * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS REG NA $325 BB21 regmask=[rcx] minReg=1> BB21 regmask=[rcx] minReg=1 last fixed> BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1 last fixed> BB21 regmask=[rax] minReg=1> BB21 regmask=[rcx] minReg=1> BB21 regmask=[rdx] minReg=1> BB21 regmask=[r8] minReg=1> BB21 regmask=[r9] minReg=1> BB21 regmask=[r10] minReg=1> BB21 regmask=[r11] minReg=1> Interval 127: long RefPositions {} physReg:NA Preferences=[allInt] BB21 regmask=[rax] minReg=1> CALL BB21 regmask=[rax] minReg=1 fixed> DefList: { N531.t367. CALL } N533 ( 21, 21) [001157] DA--G------- * STORE_LCL_VAR long V25 tmp11 d:2 NA REG NA BB21 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB21 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB21, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V25 V73} ============================== Reporting this as generic context: referenced use: {V24} def: {V25} NEW BLOCK BB22 Setting BB20 as the predecessor for determining incoming variable registers of BB22 DefList: { } N537 ( 3, 2) [000382] ------------ * LCL_VAR long V25 tmp11 u:1 NA (last use) REG NA $344 DefList: { } N539 (???,???) [001474] ------------ * PUTARG_REG long REG rcx BB22 regmask=[rcx] minReg=1> LCL_VAR BB22 regmask=[rcx] minReg=1 last fixed> Interval 128: long RefPositions {} physReg:NA Preferences=[allInt] BB22 regmask=[rcx] minReg=1> PUTARG_REG BB22 regmask=[rcx] minReg=1 fixed> DefList: { N539.t1474. PUTARG_REG } N541 ( 17, 8) [000352] --CXG------- * CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default REG NA $223 BB22 regmask=[rcx] minReg=1> BB22 regmask=[rcx] minReg=1 last fixed> BB22 regmask=[rax] minReg=1> BB22 regmask=[rcx] minReg=1> BB22 regmask=[rdx] minReg=1> BB22 regmask=[r8] minReg=1> BB22 regmask=[r9] minReg=1> BB22 regmask=[r10] minReg=1> BB22 regmask=[r11] minReg=1> Interval 129: ref RefPositions {} physReg:NA Preferences=[allInt] BB22 regmask=[rax] minReg=1> CALL BB22 regmask=[rax] minReg=1 fixed> DefList: { N541.t352. CALL } N543 ( 17, 8) [000386] DA-XG------- * STORE_LCL_VAR ref V12 loc8 d:1 NA REG NA BB22 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB22 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB22, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73} ============================== Reporting this as generic context: referenced use: {V25} def: {V12} NEW BLOCK BB23 Setting BB22 as the predecessor for determining incoming variable registers of BB23 DefList: { } N547 (???,???) [001367] ------------ * IL_OFFSET void IL offset: 0x106 REG NA DefList: { } N549 ( 1, 1) [000388] ------------ * LCL_VAR ref V04 loc0 u:1 NA REG NA DefList: { } N551 (???,???) [001446] -c---------- * LEA(b+8) ref REG NA Contained DefList: { } N553 ( 3, 3) [000389] ---X-------- * IND int REG NA LCL_VAR BB23 regmask=[allInt] minReg=1 last> Interval 130: int RefPositions {} physReg:NA Preferences=[allInt] IND BB23 regmask=[allInt] minReg=1> DefList: { N553.t389. IND } N555 ( 3, 3) [001316] DA-X-------- * STORE_LCL_VAR int V76 cse11 NA REG NA BB23 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N557 ( 1, 1) [001317] ------------ * LCL_VAR int V76 cse11 NA REG NA DefList: { } N559 ( 1, 1) [000387] ------------ * LCL_VAR int V09 loc5 u:4 NA REG NA $3c2 DefList: { } N561 ( 6, 6) [000390] N--X---N-U-- * LE void REG NA LCL_VAR BB23 regmask=[allInt] minReg=1 last> LCL_VAR BB23 regmask=[allInt] minReg=1 last> DefList: { } N563 ( 8, 8) [000391] ---X-------- * JTRUE void REG NA CHECKING LAST USES for BB23, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73 V76} ============================== Reporting this as generic context: referenced use: {V04 V09} def: {V76} NEW BLOCK BB24 Setting BB23 as the predecessor for determining incoming variable registers of BB24 DefList: { } N567 (???,???) [001368] ------------ * IL_OFFSET void IL offset: 0x110 REG NA DefList: { } N569 ( 1, 1) [000869] ------------ * LCL_VAR ref V04 loc0 u:1 NA REG NA DefList: { } N571 ( 1, 1) [000870] ------------ * LCL_VAR int V09 loc5 u:4 NA (last use) REG NA $3c2 DefList: { } N573 ( 2, 3) [000873] ------------ * CAST long <- int REG NA $326 LCL_VAR BB24 regmask=[allInt] minReg=1 last> Interval 131: long RefPositions {} physReg:NA Preferences=[allInt] CAST BB24 regmask=[allInt] minReg=1> DefList: { N573.t873. CAST } N575 ( 1, 1) [000880] -c---------- * CNS_INT long 3 REG NA $24b Contained DefList: { N573.t873. CAST } N577 ( 7, 7) [000881] ------------ * MUL long REG NA $327 BB24 regmask=[allInt] minReg=1 last> Interval 132: long RefPositions {} physReg:NA Preferences=[allInt] MUL BB24 regmask=[allInt] minReg=1> DefList: { N577.t881. MUL } N579 ( 7, 7) [001276] DA---------- * STORE_LCL_VAR long V70 cse5 d:1 NA REG NA BB24 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB24 regmask=[allInt] minReg=1 last> DefList: { } N581 ( 1, 1) [001277] ------------ * LCL_VAR long V70 cse5 u:1 NA REG NA $327 DefList: { } N583 ( 11, 11) [000878] -------N---- * LEA(b+(i*8)+16) byref REG NA LCL_VAR BB24 regmask=[allInt] minReg=1 last> LCL_VAR BB24 regmask=[allInt] minReg=1 last> Interval 133: byref RefPositions {} physReg:NA Preferences=[allInt] LEA BB24 regmask=[allInt] minReg=1> DefList: { N583.t878. LEA } N585 ( 23, 23) [001249] DA--G------- * STORE_LCL_VAR byref V65 cse0 d:1 NA REG NA BB24 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB24 regmask=[allInt] minReg=1 last> DefList: { } N587 ( 1, 1) [001250] ------------ * LCL_VAR byref V65 cse0 u:1 NA REG NA DefList: { } N589 ( 25, 25) [000868] -c---------- * LEA(b+16) byref REG NA Contained DefList: { } N591 ( 27, 27) [000396] *c-XG------- * IND int REG NA Contained DefList: { } N593 ( 1, 1) [000397] ------------ * LCL_VAR int V06 loc2 u:1 NA REG NA $3c0 DefList: { } N595 ( 29, 29) [000398] N--XG--N-U-- * NE void REG NA LCL_VAR BB24 regmask=[allInt] minReg=1 last> LCL_VAR BB24 regmask=[allInt] minReg=1 last> DefList: { } N597 ( 31, 31) [000399] ---XG------- * JTRUE void REG NA CHECKING LAST USES for BB24, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V65 V70 V73 V76} ============================== Reporting this as generic context: referenced use: {V04 V06 V09} def: {V65 V70} NEW BLOCK BB25 Setting BB24 as the predecessor for determining incoming variable registers of BB25 DefList: { } N601 (???,???) [001369] ------------ * IL_OFFSET void IL offset: 0x120 REG NA DefList: { } N603 ( 1, 1) [000883] ------------ * LCL_VAR ref V04 loc0 u:1 NA REG NA DefList: { } N605 ( 1, 1) [001279] ------------ * LCL_VAR long V70 cse5 u:1 NA (last use) REG NA $327 DefList: { } N607 ( 4, 4) [000892] -c---------- * LEA(b+(i*8)+16) byref REG NA Contained DefList: { } N609 ( 12, 11) [000897] *---G--N---- * IND ref REG NA LCL_VAR BB25 regmask=[allInt] minReg=1 last> LCL_VAR BB25 regmask=[allInt] minReg=1 last> Interval 134: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB25 regmask=[allInt] minReg=1> DefList: { N609.t897. IND } N611 (???,???) [001475] ----G------- * PUTARG_REG ref REG rdx BB25 regmask=[rdx] minReg=1> BB25 regmask=[rdx] minReg=1 last fixed> Interval 135: ref RefPositions {} physReg:NA Preferences=[allInt] BB25 regmask=[rdx] minReg=1> PUTARG_REG BB25 regmask=[rdx] minReg=1 fixed> DefList: { N611.t1475. PUTARG_REG } N613 ( 1, 1) [000418] ------------ * LCL_VAR ref V12 loc8 u:1 NA REG NA $223 DefList: { N611.t1475. PUTARG_REG } N615 (???,???) [001476] ------------ * PUTARG_REG ref REG rcx BB25 regmask=[rcx] minReg=1> LCL_VAR BB25 regmask=[rcx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 136: ref RefPositions {} physReg:NA Preferences=[allInt] BB25 regmask=[rcx] minReg=1> PUTARG_REG BB25 regmask=[rcx] minReg=1 fixed> Assigning related to DefList: { N611.t1475. PUTARG_REG; N615.t1476. PUTARG_REG } N617 ( 1, 1) [000424] ------------ * LCL_VAR ref V01 arg1 u:1 NA REG NA $101 DefList: { N611.t1475. PUTARG_REG; N615.t1476. PUTARG_REG } N619 (???,???) [001477] ------------ * PUTARG_REG ref REG r8 BB25 regmask=[r8] minReg=1> LCL_VAR BB25 regmask=[r8] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 137: ref RefPositions {} physReg:NA Preferences=[allInt] BB25 regmask=[r8] minReg=1> PUTARG_REG BB25 regmask=[r8] minReg=1 fixed> Assigning related to DefList: { N611.t1475. PUTARG_REG; N615.t1476. PUTARG_REG; N619.t1477. PUTARG_REG } N621 ( 1, 1) [000901] ------------ * LCL_VAR ref V12 loc8 u:1 NA REG NA $223 DefList: { N611.t1475. PUTARG_REG; N615.t1476. PUTARG_REG; N619.t1477. PUTARG_REG } N623 ( 3, 2) [000902] #--X-------- * IND long REG NA $463 LCL_VAR BB25 regmask=[allInt] minReg=1 last> Interval 138: long RefPositions {} physReg:NA Preferences=[allInt] IND BB25 regmask=[allInt] minReg=1> DefList: { N611.t1475. PUTARG_REG; N615.t1476. PUTARG_REG; N619.t1477. PUTARG_REG; N623.t902. IND } N625 ( 4, 3) [000904] -c---------- * LEA(b+72) long REG NA Contained DefList: { N611.t1475. PUTARG_REG; N615.t1476. PUTARG_REG; N619.t1477. PUTARG_REG; N623.t902. IND } N627 ( 6, 5) [000905] #--X-------- * IND long REG NA $465 BB25 regmask=[allInt] minReg=1 last> Interval 139: long RefPositions {} physReg:NA Preferences=[allInt] IND BB25 regmask=[allInt] minReg=1> DefList: { N611.t1475. PUTARG_REG; N615.t1476. PUTARG_REG; N619.t1477. PUTARG_REG; N627.t905. IND } N629 ( 7, 6) [000907] -c---------- * LEA(b+32) long REG NA Contained DefList: { N611.t1475. PUTARG_REG; N615.t1476. PUTARG_REG; N619.t1477. PUTARG_REG; N627.t905. IND } N631 ( 9, 8) [000908] nc-X-------- * IND long REG NA Contained DefList: { N611.t1475. PUTARG_REG; N615.t1476. PUTARG_REG; N619.t1477. PUTARG_REG; N627.t905. IND } N633 ( 43, 32) [000425] --CXG------- * CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals REG NA $581 BB25 regmask=[rdx] minReg=1> BB25 regmask=[rdx] minReg=1 last fixed> BB25 regmask=[rcx] minReg=1> BB25 regmask=[rcx] minReg=1 last fixed> BB25 regmask=[r8] minReg=1> BB25 regmask=[r8] minReg=1 last fixed> BB25 regmask=[allInt] minReg=1 last> BB25 regmask=[rax] minReg=1> BB25 regmask=[rcx] minReg=1> BB25 regmask=[rdx] minReg=1> BB25 regmask=[r8] minReg=1> BB25 regmask=[r9] minReg=1> BB25 regmask=[r10] minReg=1> BB25 regmask=[r11] minReg=1> Interval 140: int RefPositions {} physReg:NA Preferences=[allInt] BB25 regmask=[rax] minReg=1> CALL BB25 regmask=[rax] minReg=1 fixed> DefList: { N633.t425. CALL } N635 ( 1, 1) [000426] -c---------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N633.t425. CALL } N637 ( 45, 34) [000427] J--XG--N---- * NE void REG NA $1bd BB25 regmask=[allInt] minReg=1 last> DefList: { } N639 ( 47, 36) [000428] ---XG------- * JTRUE void REG NA CHECKING LAST USES for BB25, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V65 V73 V76} ============================== Reporting this as generic context: referenced use: {V01 V04 V12 V70} def: {} NEW BLOCK BB26 Setting BB24 as the predecessor for determining incoming variable registers of BB26 DefList: { } N643 (???,???) [001370] ------------ * IL_OFFSET void IL offset: 0x157 REG NA DefList: { } N645 ( 1, 1) [001252] ------------ * LCL_VAR byref V65 cse0 u:1 NA (last use) REG NA $82 DefList: { } N647 ( 2, 2) [000932] -c---------- * LEA(b+20) byref REG NA Contained DefList: { } N649 ( 4, 4) [000404] *--XG------- * IND int REG NA LCL_VAR BB26 regmask=[allInt] minReg=1 last> Interval 141: int RefPositions {} physReg:NA Preferences=[allInt] IND BB26 regmask=[allInt] minReg=1> DefList: { N649.t404. IND } N651 ( 4, 4) [000406] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:5 NA REG NA BB26 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB26 regmask=[allInt] minReg=1 last> DefList: { } N653 (???,???) [001371] ------------ * IL_OFFSET void IL offset: 0x166 REG NA DefList: { } N655 ( 1, 1) [000407] ------------ * LCL_VAR int V07 loc3 u:5 NA (last use) REG NA $3c1 DefList: { } N657 ( 1, 1) [000408] -c---------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N659 ( 3, 3) [000409] ------------ * ADD int REG NA $605 LCL_VAR BB26 regmask=[allInt] minReg=1 last> Interval 142: int RefPositions {} physReg:NA Preferences=[allInt] ADD BB26 regmask=[allInt] minReg=1> Assigning related to DefList: { N659.t409. ADD } N661 ( 3, 3) [000411] DA---------- * STORE_LCL_VAR int V07 loc3 d:6 NA REG NA BB26 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB26 regmask=[allInt] minReg=1 last> DefList: { } N663 (???,???) [001372] ------------ * IL_OFFSET void IL offset: 0x16a REG NA DefList: { } N665 ( 1, 1) [001321] ------------ * LCL_VAR int V76 cse11 NA (last use) REG NA DefList: { } N667 ( 1, 1) [000412] ------------ * LCL_VAR int V07 loc3 u:6 NA REG NA $605 DefList: { } N669 ( 3, 3) [000415] N------N-U-- * LT void REG NA LCL_VAR BB26 regmask=[allInt] minReg=1 last> LCL_VAR BB26 regmask=[allInt] minReg=1 last> DefList: { } N671 ( 5, 5) [000416] ------------ * JTRUE void REG NA CHECKING LAST USES for BB26, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73} ============================== Reporting this as generic context: referenced use: {V07 V65 V76} def: {V07 V09} NEW BLOCK BB27 Setting BB26 as the predecessor for determining incoming variable registers of BB27 Exposed uses: BB27 regmask=[allInt] minReg=1> V07 BB27 regmask=[allInt] minReg=1> V04 BB27 regmask=[allInt] minReg=1> V09 BB27 regmask=[allInt] minReg=1> V06 BB27 regmask=[allInt] minReg=1> V73 BB27 regmask=[allInt] minReg=1> V05 BB27 regmask=[allInt] minReg=1> V12 BB27 regmask=[allInt] minReg=1> V08 CHECKING LAST USES for BB27, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73} ============================== Reporting this as generic context: referenced use: {} def: {} NEW BLOCK BB28 Setting BB24 as the predecessor for determining incoming variable registers of BB28 DefList: { } N677 (???,???) [001373] ------------ * IL_OFFSET void IL offset: 0x137 REG NA DefList: { } N679 ( 2, 2) [000429] ------------ * LCL_VAR ubyte V03 arg3 u:1 NA REG NA $140 DefList: { } N681 ( 1, 1) [000430] -c---------- * CNS_INT ubyte 1 REG NA $c1 Contained DefList: { } N683 ( 5, 6) [000431] N------N-U-- * NE void REG NA $1bf LCL_VAR BB28 regmask=[allInt] minReg=1 last> DefList: { } N685 ( 7, 8) [000432] ------------ * JTRUE void REG NA CHECKING LAST USES for BB28, liveout={V00 V01 V02 V03 V65} ============================== Reporting this as generic context: referenced use: {V03} def: {} NEW BLOCK BB29 Setting BB28 as the predecessor for determining incoming variable registers of BB29 DefList: { } N689 (???,???) [001374] ------------ * IL_OFFSET void IL offset: 0x13b REG NA DefList: { } N691 ( 1, 1) [001253] ------------ * LCL_VAR byref V65 cse0 u:1 NA (last use) REG NA $82 DefList: { } N693 ( 2, 2) [000911] ------------ * LEA(b+8) byref REG NA LCL_VAR BB29 regmask=[allInt] minReg=1 last> Interval 143: byref RefPositions {} physReg:NA Preferences=[allInt] LEA BB29 regmask=[allInt] minReg=1> DefList: { N693.t911. LEA } N695 ( 1, 1) [000479] ------------ * LCL_VAR ref V02 arg2 u:1 NA (last use) REG NA $102 DefList: { N693.t911. LEA } N697 (???,???) [001375] -A-XG------- * STOREIND ref REG NA BB29 regmask=[rcx] minReg=1> BB29 regmask=[rcx] minReg=1 last fixed> BB29 regmask=[rdx] minReg=1> LCL_VAR BB29 regmask=[rdx] minReg=1 last fixed> BB29 regmask=[rax] minReg=1> BB29 regmask=[rcx] minReg=1> BB29 regmask=[rdx] minReg=1> BB29 regmask=[r8] minReg=1> BB29 regmask=[r9] minReg=1> BB29 regmask=[r10] minReg=1> BB29 regmask=[r11] minReg=1> BB29 regmask=[mm0] minReg=1> BB29 regmask=[mm1] minReg=1> BB29 regmask=[mm2] minReg=1> BB29 regmask=[mm3] minReg=1> BB29 regmask=[mm4] minReg=1> BB29 regmask=[mm5] minReg=1> CHECKING LAST USES for BB29, liveout={V00} ============================== Reporting this as generic context: referenced use: {V02 V65} def: {} NEW BLOCK BB30 Setting BB28 as the predecessor for determining incoming variable registers of BB30 DefList: { } N701 (???,???) [001376] ------------ * IL_OFFSET void IL offset: 0x14b REG NA DefList: { } N703 ( 2, 2) [000433] ------------ * LCL_VAR ubyte V03 arg3 u:1 NA (last use) REG NA $140 DefList: { } N705 ( 1, 1) [000434] -c---------- * CNS_INT ubyte 2 REG NA $c2 Contained DefList: { } N707 ( 5, 6) [000435] N------N-U-- * EQ void REG NA $600 LCL_VAR BB30 regmask=[allInt] minReg=1 last> DefList: { } N709 ( 7, 8) [000436] ------------ * JTRUE void REG NA CHECKING LAST USES for BB30, liveout={V00 V01} ============================== Reporting this as generic context: referenced use: {V03} def: {} NEW BLOCK BB31 Setting BB30 as the predecessor for determining incoming variable registers of BB31 DefList: { } N713 ( 1, 1) [000437] ------------ * CNS_INT int 0 REG NA $c0 Interval 144: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB31 regmask=[allInt] minReg=1> DefList: { N713.t437. CNS_INT } N715 ( 2, 2) [000811] ------------ * RETURN int REG NA $1f3 BB31 regmask=[rax] minReg=1> BB31 regmask=[rax] minReg=1 last fixed> CHECKING LAST USES for BB31, liveout={V00} ============================== Reporting this as generic context: referenced use: {} def: {} NEW BLOCK BB32 Setting BB18 as the predecessor for determining incoming variable registers of BB32 DefList: { } N719 (???,???) [001377] ------------ * IL_OFFSET void IL offset: 0x177 REG NA DefList: { } N721 ( 1, 1) [000063] ------------ * LCL_VAR ref V04 loc0 u:1 NA REG NA DefList: { } N723 (???,???) [001448] -c---------- * LEA(b+8) ref REG NA Contained DefList: { } N725 ( 3, 3) [000064] ---X-------- * IND int REG NA LCL_VAR BB32 regmask=[allInt] minReg=1 last> Interval 145: int RefPositions {} physReg:NA Preferences=[allInt] IND BB32 regmask=[allInt] minReg=1> DefList: { N725.t64. IND } N727 ( 3, 3) [001323] DA-X-------- * STORE_LCL_VAR int V76 cse11 NA REG NA BB32 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB32 regmask=[allInt] minReg=1 last> DefList: { } N729 ( 1, 1) [001324] ------------ * LCL_VAR int V76 cse11 NA REG NA DefList: { } N731 ( 1, 1) [000062] ------------ * LCL_VAR int V09 loc5 u:2 NA REG NA $3c4 DefList: { } N733 ( 6, 6) [000065] N--X---N-U-- * LE void REG NA LCL_VAR BB32 regmask=[allInt] minReg=1 last> LCL_VAR BB32 regmask=[allInt] minReg=1 last> DefList: { } N735 ( 8, 8) [000066] ---X-------- * JTRUE void REG NA CHECKING LAST USES for BB32, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73 V76} ============================== Reporting this as generic context: referenced use: {V04 V09} def: {V76} NEW BLOCK BB33 Setting BB32 as the predecessor for determining incoming variable registers of BB33 DefList: { } N739 (???,???) [001378] ------------ * IL_OFFSET void IL offset: 0x17e REG NA DefList: { } N741 ( 1, 1) [000949] ------------ * LCL_VAR ref V04 loc0 u:1 NA REG NA DefList: { } N743 ( 1, 1) [000950] ------------ * LCL_VAR int V09 loc5 u:2 NA (last use) REG NA $3c4 DefList: { } N745 ( 2, 3) [000953] ------------ * CAST long <- int REG NA $6e1 LCL_VAR BB33 regmask=[allInt] minReg=1 last> Interval 146: long RefPositions {} physReg:NA Preferences=[allInt] CAST BB33 regmask=[allInt] minReg=1> DefList: { N745.t953. CAST } N747 ( 1, 1) [000960] -c---------- * CNS_INT long 3 REG NA $24b Contained DefList: { N745.t953. CAST } N749 ( 7, 7) [000961] ------------ * MUL long REG NA $6e2 BB33 regmask=[allInt] minReg=1 last> Interval 147: long RefPositions {} physReg:NA Preferences=[allInt] MUL BB33 regmask=[allInt] minReg=1> DefList: { N749.t961. MUL } N751 ( 7, 7) [001281] DA---------- * STORE_LCL_VAR long V71 cse6 d:1 NA REG NA BB33 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB33 regmask=[allInt] minReg=1 last> DefList: { } N753 ( 1, 1) [001282] ------------ * LCL_VAR long V71 cse6 u:1 NA REG NA $6e2 DefList: { } N755 ( 11, 11) [000958] -------N---- * LEA(b+(i*8)+16) byref REG NA LCL_VAR BB33 regmask=[allInt] minReg=1 last> LCL_VAR BB33 regmask=[allInt] minReg=1 last> Interval 148: byref RefPositions {} physReg:NA Preferences=[allInt] LEA BB33 regmask=[allInt] minReg=1> DefList: { N755.t958. LEA } N757 ( 23, 23) [001255] DA--G------- * STORE_LCL_VAR byref V66 cse1 d:1 NA REG NA BB33 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB33 regmask=[allInt] minReg=1 last> DefList: { } N759 ( 1, 1) [001256] ------------ * LCL_VAR byref V66 cse1 u:1 NA REG NA DefList: { } N761 ( 25, 25) [000948] -c---------- * LEA(b+16) byref REG NA Contained DefList: { } N763 ( 27, 27) [000212] *c-XG------- * IND int REG NA Contained DefList: { } N765 ( 1, 1) [000213] ------------ * LCL_VAR int V06 loc2 u:1 NA REG NA $3c0 DefList: { } N767 ( 29, 29) [000214] N--XG--N-U-- * NE void REG NA LCL_VAR BB33 regmask=[allInt] minReg=1 last> LCL_VAR BB33 regmask=[allInt] minReg=1 last> DefList: { } N769 ( 31, 31) [000215] ---XG------- * JTRUE void REG NA CHECKING LAST USES for BB33, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V08 V66 V71 V73 V76} ============================== Reporting this as generic context: referenced use: {V04 V06 V09} def: {V66 V71} NEW BLOCK BB34 Setting BB33 as the predecessor for determining incoming variable registers of BB34 DefList: { } N773 (???,???) [001379] ------------ * IL_OFFSET void IL offset: 0x18e REG NA DefList: { } N775 ( 1, 1) [000963] ------------ * LCL_VAR ref V04 loc0 u:1 NA REG NA DefList: { } N777 ( 1, 1) [001284] ------------ * LCL_VAR long V71 cse6 u:1 NA (last use) REG NA $6e2 DefList: { } N779 ( 4, 4) [000972] -c---------- * LEA(b+(i*8)+16) byref REG NA Contained DefList: { } N781 ( 12, 11) [000977] *---G--N---- * IND ref REG NA LCL_VAR BB34 regmask=[allInt] minReg=1 last> LCL_VAR BB34 regmask=[allInt] minReg=1 last> Interval 149: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB34 regmask=[allInt] minReg=1> DefList: { N781.t977. IND } N783 ( 12, 11) [000246] DA--G------- * STORE_LCL_VAR ref V17 tmp3 d:1 NA REG NA BB34 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB34 regmask=[allInt] minReg=1 last> DefList: { } N785 (???,???) [001380] ------------ * IL_OFFSET void IL offset: 0x18e REG NA DefList: { } N787 ( 1, 1) [000241] !----------- * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N789 ( 3, 2) [000242] #----O------ * IND long REG NA $2e8 LCL_VAR BB34 regmask=[allInt] minReg=1 last> Interval 150: long RefPositions {} physReg:NA Preferences=[allInt] IND BB34 regmask=[allInt] minReg=1> DefList: { N789.t242. IND } N791 ( 3, 3) [000244] DA---O------ * STORE_LCL_VAR long V16 tmp2 d:1 NA REG NA BB34 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB34 regmask=[allInt] minReg=1 last> DefList: { } N793 ( 1, 1) [000249] ------------ * LCL_VAR long V16 tmp2 u:1 NA REG NA $2e7 DefList: { } N795 ( 2, 2) [000251] -c---------- * LEA(b+56) long REG NA Contained DefList: { } N797 ( 4, 4) [000252] #----------- * IND long REG NA $2e9 LCL_VAR BB34 regmask=[allInt] minReg=1 last> Interval 151: long RefPositions {} physReg:NA Preferences=[allInt] IND BB34 regmask=[allInt] minReg=1> DefList: { N797.t252. IND } N799 ( 7, 6) [000253] #----------- * IND long REG NA $2ea BB34 regmask=[allInt] minReg=1 last> Interval 152: long RefPositions {} physReg:NA Preferences=[allInt] IND BB34 regmask=[allInt] minReg=1> DefList: { N799.t253. IND } N801 ( 8, 7) [000255] -c---------- * LEA(b+48) long REG NA Contained DefList: { N799.t253. IND } N803 ( 10, 9) [000259] n----------- * IND long REG NA BB34 regmask=[allInt] minReg=1 last> Interval 153: long RefPositions {} physReg:NA Preferences=[allInt] IND BB34 regmask=[allInt] minReg=1> DefList: { N803.t259. IND } N805 ( 10, 9) [001261] DA---------- * STORE_LCL_VAR long V67 cse2 d:1 NA REG NA BB34 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB34 regmask=[allInt] minReg=1 last> DefList: { } N807 ( 1, 1) [001262] ------------ * LCL_VAR long V67 cse2 u:1 NA REG NA DefList: { } N809 ( 1, 1) [000262] -c---------- * CNS_INT long 0 REG NA $243 Contained DefList: { } N811 ( 13, 12) [000263] J------N---- * EQ void REG NA LCL_VAR BB34 regmask=[allInt] minReg=1 last> DefList: { } N813 ( 15, 14) [001163] ------------ * JTRUE void REG NA CHECKING LAST USES for BB34, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V08 V16 V17 V66 V67 V73 V76} ============================== Reporting this as generic context: referenced use: {V00 V04 V71} def: {V16 V17 V67} NEW BLOCK BB35 Setting BB34 as the predecessor for determining incoming variable registers of BB35 DefList: { } N817 ( 1, 1) [001264] ------------ * LCL_VAR long V67 cse2 u:1 NA (last use) REG NA DefList: { } N819 ( 1, 3) [001165] DA---------- * STORE_LCL_VAR long V19 tmp5 d:3 NA REG NA LCL_VAR BB35 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB35 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB35, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V19 V66 V73 V76} ============================== Reporting this as generic context: referenced use: {V67} def: {V19} NEW BLOCK BB36 Setting BB34 as the predecessor for determining incoming variable registers of BB36 DefList: { } N823 ( 1, 1) [000248] ------?----- * LCL_VAR long V16 tmp2 u:1 NA (last use) REG NA $2e7 DefList: { } N825 (???,???) [001478] ------------ * PUTARG_REG long REG rcx BB36 regmask=[rcx] minReg=1> LCL_VAR BB36 regmask=[rcx] minReg=1 last fixed> Interval 154: long RefPositions {} physReg:NA Preferences=[allInt] BB36 regmask=[rcx] minReg=1> PUTARG_REG BB36 regmask=[rcx] minReg=1 fixed> DefList: { N825.t1478. PUTARG_REG } N827 ( 2, 10) [000260] H-----?----- * CNS_INT(h) long 0xd1ffab1e global ptr REG NA $63 Interval 155: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB36 regmask=[allInt] minReg=1> DefList: { N825.t1478. PUTARG_REG; N827.t260. CNS_INT } N829 (???,???) [001479] ------------ * PUTARG_REG long REG rdx BB36 regmask=[rdx] minReg=1> BB36 regmask=[rdx] minReg=1 last fixed> Interval 156: long RefPositions {} physReg:NA Preferences=[allInt] BB36 regmask=[rdx] minReg=1> PUTARG_REG BB36 regmask=[rdx] minReg=1 fixed> DefList: { N825.t1478. PUTARG_REG; N829.t1479. PUTARG_REG } N831 ( 17, 18) [000261] --C-G-?----- * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS REG NA $6e7 BB36 regmask=[rcx] minReg=1> BB36 regmask=[rcx] minReg=1 last fixed> BB36 regmask=[rdx] minReg=1> BB36 regmask=[rdx] minReg=1 last fixed> BB36 regmask=[rax] minReg=1> BB36 regmask=[rcx] minReg=1> BB36 regmask=[rdx] minReg=1> BB36 regmask=[r8] minReg=1> BB36 regmask=[r9] minReg=1> BB36 regmask=[r10] minReg=1> BB36 regmask=[r11] minReg=1> Interval 157: long RefPositions {} physReg:NA Preferences=[allInt] BB36 regmask=[rax] minReg=1> CALL BB36 regmask=[rax] minReg=1 fixed> DefList: { N831.t261. CALL } N833 ( 17, 18) [001167] DA--G------- * STORE_LCL_VAR long V19 tmp5 d:2 NA REG NA BB36 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB36 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB36, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V19 V66 V73 V76} ============================== Reporting this as generic context: referenced use: {V16} def: {V19} NEW BLOCK BB37 Setting BB35 as the predecessor for determining incoming variable registers of BB37 DefList: { } N837 ( 1, 1) [000234] ------------ * LCL_VAR ref V05 loc1 u:1 NA REG NA DefList: { } N839 (???,???) [001480] ------------ * PUTARG_REG ref REG rcx BB37 regmask=[rcx] minReg=1> LCL_VAR BB37 regmask=[rcx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 158: ref RefPositions {} physReg:NA Preferences=[allInt] BB37 regmask=[rcx] minReg=1> PUTARG_REG BB37 regmask=[rcx] minReg=1 fixed> Assigning related to DefList: { N839.t1480. PUTARG_REG } N841 ( 1, 1) [000980] ------------ * LCL_VAR long V19 tmp5 u:1 r11 REG r11 $349 DefList: { N839.t1480. PUTARG_REG } N843 (???,???) [001481] ------------ * PUTARG_REG long REG r11 BB37 regmask=[r11] minReg=1> LCL_VAR BB37 regmask=[r11] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 159: long RefPositions {} physReg:NA Preferences=[allInt] BB37 regmask=[r11] minReg=1> PUTARG_REG BB37 regmask=[r11] minReg=1 fixed> Assigning related to DefList: { N839.t1480. PUTARG_REG; N843.t1481. PUTARG_REG } N845 ( 1, 1) [000247] ------------ * LCL_VAR ref V17 tmp3 u:1 NA (last use) REG NA DefList: { N839.t1480. PUTARG_REG; N843.t1481. PUTARG_REG } N847 (???,???) [001482] ------------ * PUTARG_REG ref REG rdx BB37 regmask=[rdx] minReg=1> LCL_VAR BB37 regmask=[rdx] minReg=1 last fixed> Interval 160: ref RefPositions {} physReg:NA Preferences=[allInt] BB37 regmask=[rdx] minReg=1> PUTARG_REG BB37 regmask=[rdx] minReg=1 fixed> DefList: { N839.t1480. PUTARG_REG; N843.t1481. PUTARG_REG; N847.t1482. PUTARG_REG } N849 ( 1, 1) [000258] ------------ * LCL_VAR ref V01 arg1 u:1 NA REG NA $101 DefList: { N839.t1480. PUTARG_REG; N843.t1481. PUTARG_REG; N847.t1482. PUTARG_REG } N851 (???,???) [001483] ------------ * PUTARG_REG ref REG r8 BB37 regmask=[r8] minReg=1> LCL_VAR BB37 regmask=[r8] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 161: ref RefPositions {} physReg:NA Preferences=[allInt] BB37 regmask=[r8] minReg=1> PUTARG_REG BB37 regmask=[r8] minReg=1 fixed> Assigning related to DefList: { N839.t1480. PUTARG_REG; N843.t1481. PUTARG_REG; N847.t1482. PUTARG_REG; N851.t1483. PUTARG_REG } N853 ( 1, 1) [000279] ------------ * LCL_VAR long V19 tmp5 u:1 NA (last use) REG NA $349 DefList: { N839.t1480. PUTARG_REG; N843.t1481. PUTARG_REG; N847.t1482. PUTARG_REG; N851.t1483. PUTARG_REG } N855 (???,???) [001484] Dc---------- * IND long REG NA Contained DefList: { N839.t1480. PUTARG_REG; N843.t1481. PUTARG_REG; N847.t1482. PUTARG_REG; N851.t1483. PUTARG_REG } N857 ( 28, 14) [000280] --CXG------- * CALL ind stub int REG NA $1ef BB37 regmask=[rcx] minReg=1> BB37 regmask=[rcx] minReg=1 last fixed> BB37 regmask=[r11] minReg=1> BB37 regmask=[r11] minReg=1 last fixed> BB37 regmask=[rdx] minReg=1> BB37 regmask=[rdx] minReg=1 last fixed> BB37 regmask=[r8] minReg=1> BB37 regmask=[r8] minReg=1 last fixed> LCL_VAR BB37 regmask=[allInt] minReg=1 last> BB37 regmask=[rax] minReg=1> BB37 regmask=[rcx] minReg=1> BB37 regmask=[rdx] minReg=1> BB37 regmask=[r8] minReg=1> BB37 regmask=[r9] minReg=1> BB37 regmask=[r10] minReg=1> BB37 regmask=[r11] minReg=1> Interval 162: int RefPositions {} physReg:NA Preferences=[allInt] BB37 regmask=[rax] minReg=1> CALL BB37 regmask=[rax] minReg=1 fixed> DefList: { N857.t280. CALL } N859 ( 1, 1) [000281] -c---------- * CNS_INT int 0 REG NA $c0 Contained DefList: { N857.t280. CALL } N861 ( 30, 16) [000282] J--XG--N---- * EQ void REG NA $817 BB37 regmask=[allInt] minReg=1 last> DefList: { } N863 ( 32, 18) [000283] ---XG------- * JTRUE void REG NA CHECKING LAST USES for BB37, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V08 V66 V73 V76} ============================== Reporting this as generic context: referenced use: {V01 V05 V17 V19} def: {} NEW BLOCK BB38 Setting BB37 as the predecessor for determining incoming variable registers of BB38 DefList: { } N867 (???,???) [001381] ------------ * IL_OFFSET void IL offset: 0x1a4 REG NA DefList: { } N869 ( 2, 2) [000284] ------------ * LCL_VAR ubyte V03 arg3 u:1 NA REG NA $140 DefList: { } N871 ( 1, 1) [000285] -c---------- * CNS_INT ubyte 1 REG NA $c1 Contained DefList: { } N873 ( 5, 6) [000286] N------N-U-- * NE void REG NA $1bf LCL_VAR BB38 regmask=[allInt] minReg=1 last> DefList: { } N875 ( 7, 8) [000287] ------------ * JTRUE void REG NA CHECKING LAST USES for BB38, liveout={V00 V01 V02 V03 V66} ============================== Reporting this as generic context: referenced use: {V03} def: {} NEW BLOCK BB39 Setting BB38 as the predecessor for determining incoming variable registers of BB39 DefList: { } N879 (???,???) [001382] ------------ * IL_OFFSET void IL offset: 0x1a8 REG NA DefList: { } N881 ( 1, 1) [001258] ------------ * LCL_VAR byref V66 cse1 u:1 NA (last use) REG NA $91 DefList: { } N883 ( 2, 2) [000987] ------------ * LEA(b+8) byref REG NA LCL_VAR BB39 regmask=[allInt] minReg=1 last> Interval 163: byref RefPositions {} physReg:NA Preferences=[allInt] LEA BB39 regmask=[allInt] minReg=1> DefList: { N883.t987. LEA } N885 ( 1, 1) [000334] ------------ * LCL_VAR ref V02 arg2 u:1 NA (last use) REG NA $102 DefList: { N883.t987. LEA } N887 (???,???) [001383] -A-XG------- * STOREIND ref REG NA BB39 regmask=[rcx] minReg=1> BB39 regmask=[rcx] minReg=1 last fixed> BB39 regmask=[rdx] minReg=1> LCL_VAR BB39 regmask=[rdx] minReg=1 last fixed> BB39 regmask=[rax] minReg=1> BB39 regmask=[rcx] minReg=1> BB39 regmask=[rdx] minReg=1> BB39 regmask=[r8] minReg=1> BB39 regmask=[r9] minReg=1> BB39 regmask=[r10] minReg=1> BB39 regmask=[r11] minReg=1> BB39 regmask=[mm0] minReg=1> BB39 regmask=[mm1] minReg=1> BB39 regmask=[mm2] minReg=1> BB39 regmask=[mm3] minReg=1> BB39 regmask=[mm4] minReg=1> BB39 regmask=[mm5] minReg=1> CHECKING LAST USES for BB39, liveout={V00} ============================== Reporting this as generic context: referenced use: {V02 V66} def: {} NEW BLOCK BB40 Setting BB38 as the predecessor for determining incoming variable registers of BB40 DefList: { } N891 (???,???) [001384] ------------ * IL_OFFSET void IL offset: 0x1b8 REG NA DefList: { } N893 ( 2, 2) [000288] ------------ * LCL_VAR ubyte V03 arg3 u:1 NA (last use) REG NA $140 DefList: { } N895 ( 1, 1) [000289] -c---------- * CNS_INT ubyte 2 REG NA $c2 Contained DefList: { } N897 ( 5, 6) [000290] N------N-U-- * EQ void REG NA $600 LCL_VAR BB40 regmask=[allInt] minReg=1 last> DefList: { } N899 ( 7, 8) [000291] ------------ * JTRUE void REG NA CHECKING LAST USES for BB40, liveout={V00 V01} ============================== Reporting this as generic context: referenced use: {V03} def: {} NEW BLOCK BB41 Setting BB40 as the predecessor for determining incoming variable registers of BB41 CHECKING LAST USES for BB41, liveout={V00} ============================== Reporting this as generic context: referenced use: {} def: {} NEW BLOCK BB42 Setting BB33 as the predecessor for determining incoming variable registers of BB42 DefList: { } N905 (???,???) [001385] ------------ * IL_OFFSET void IL offset: 0x1c4 REG NA DefList: { } N907 ( 1, 1) [001259] ------------ * LCL_VAR byref V66 cse1 u:1 NA (last use) REG NA $91 DefList: { } N909 ( 2, 2) [001009] -c---------- * LEA(b+20) byref REG NA Contained DefList: { } N911 ( 4, 4) [000220] *--XG------- * IND int REG NA LCL_VAR BB42 regmask=[allInt] minReg=1 last> Interval 164: int RefPositions {} physReg:NA Preferences=[allInt] IND BB42 regmask=[allInt] minReg=1> DefList: { N911.t220. IND } N913 ( 4, 4) [000222] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:3 NA REG NA BB42 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB42 regmask=[allInt] minReg=1 last> DefList: { } N915 (???,???) [001386] ------------ * IL_OFFSET void IL offset: 0x1d3 REG NA DefList: { } N917 ( 1, 1) [000223] ------------ * LCL_VAR int V07 loc3 u:3 NA (last use) REG NA $3c3 DefList: { } N919 ( 1, 1) [000224] -c---------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N921 ( 3, 3) [000225] ------------ * ADD int REG NA $81a LCL_VAR BB42 regmask=[allInt] minReg=1 last> Interval 165: int RefPositions {} physReg:NA Preferences=[allInt] ADD BB42 regmask=[allInt] minReg=1> Interval already has a related interval DefList: { N921.t225. ADD } N923 ( 3, 3) [000227] DA---------- * STORE_LCL_VAR int V07 loc3 d:4 NA REG NA BB42 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB42 regmask=[allInt] minReg=1 last> DefList: { } N925 (???,???) [001387] ------------ * IL_OFFSET void IL offset: 0x1d7 REG NA DefList: { } N927 ( 1, 1) [001328] ------------ * LCL_VAR int V76 cse11 NA (last use) REG NA DefList: { } N929 ( 1, 1) [000228] ------------ * LCL_VAR int V07 loc3 u:4 NA REG NA $81a DefList: { } N931 ( 3, 3) [000231] N------N-U-- * LT void REG NA LCL_VAR BB42 regmask=[allInt] minReg=1 last> LCL_VAR BB42 regmask=[allInt] minReg=1 last> DefList: { } N933 ( 5, 5) [000232] ------------ * JTRUE void REG NA CHECKING LAST USES for BB42, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} ============================== Reporting this as generic context: referenced use: {V07 V66 V76} def: {V07 V09} NEW BLOCK BB43 Setting BB42 as the predecessor for determining incoming variable registers of BB43 Exposed uses: BB43 regmask=[allInt] minReg=1> V09 BB43 regmask=[allInt] minReg=1> V03 CHECKING LAST USES for BB43, liveout={V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} ============================== Reporting this as generic context: referenced use: {} def: {} NEW BLOCK BB44 Setting BB23 as the predecessor for determining incoming variable registers of BB44 DefList: { } N939 (???,???) [001388] ------------ * IL_OFFSET void IL offset: 0x1e4 REG NA DefList: { } N941 ( 1, 1) [000067] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N943 ( 2, 2) [001025] -c---------- * LEA(b+64) byref REG NA Contained DefList: { } N945 ( 4, 4) [000068] nc--GO------ * IND int REG NA Contained DefList: { } N947 ( 1, 1) [000069] -c---------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N949 ( 6, 6) [000070] J---GO-N---- * LE void REG NA LCL_VAR BB44 regmask=[allInt] minReg=1 last> DefList: { } N951 ( 8, 8) [000071] ----GO------ * JTRUE void REG NA CHECKING LAST USES for BB44, liveout={V00 V01 V02 V04 V05 V06 V07 V08 V73 V76} ============================== Reporting this as generic context: referenced use: {V00} def: {} NEW BLOCK BB45 Setting BB44 as the predecessor for determining incoming variable registers of BB45 DefList: { } N955 (???,???) [001389] ------------ * IL_OFFSET void IL offset: 0x1ed REG NA DefList: { } N957 ( 1, 1) [000171] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N959 ( 2, 2) [001027] -c---------- * LEA(b+60) byref REG NA Contained DefList: { } N961 ( 4, 4) [000172] n---GO------ * IND int REG NA LCL_VAR BB45 regmask=[allInt] minReg=1 last> Interval 166: int RefPositions {} physReg:NA Preferences=[allInt] IND BB45 regmask=[allInt] minReg=1> DefList: { N961.t172. IND } N963 ( 8, 7) [001306] DA--GO------ * STORE_LCL_VAR int V74 cse9 d:1 NA REG NA BB45 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB45 regmask=[allInt] minReg=1 last> DefList: { } N965 ( 3, 2) [001307] ------------ * LCL_VAR int V74 cse9 u:1 NA REG NA DefList: { } N967 ( 15, 12) [000174] DA--GO------ * STORE_LCL_VAR int V10 loc6 d:3 NA REG NA LCL_VAR BB45 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB45 regmask=[allInt] minReg=1 last> DefList: { } N969 (???,???) [001390] ------------ * IL_OFFSET void IL offset: 0x1f5 REG NA DefList: { } N971 ( 3, 2) [001309] ------------ * LCL_VAR int V74 cse9 u:1 NA (last use) REG NA DefList: { } N973 ( 3, 3) [001032] DA--G------- * STORE_LCL_VAR int V62 tmp48 d:1 NA REG NA LCL_VAR BB45 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB45 regmask=[allInt] minReg=1 last> DefList: { } N975 ( 1, 1) [001033] ------------ * LCL_VAR int V62 tmp48 u:1 NA REG NA DefList: { } N977 ( 1, 1) [001329] ------------ * LCL_VAR int V76 cse11 NA REG NA DefList: { } N979 ( 6, 9) [001036] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void REG NA LCL_VAR BB45 regmask=[allInt] minReg=1 last> LCL_VAR BB45 regmask=[allInt] minReg=1 last> DefList: { } N981 ( 1, 1) [001030] ------------ * LCL_VAR ref V04 loc0 u:1 NA REG NA DefList: { } N983 ( 1, 1) [001034] ------------ * LCL_VAR int V62 tmp48 u:1 NA (last use) REG NA DefList: { } N985 ( 2, 3) [001037] ------------ * CAST long <- int REG NA LCL_VAR BB45 regmask=[allInt] minReg=1 last> Interval 167: long RefPositions {} physReg:NA Preferences=[allInt] CAST BB45 regmask=[allInt] minReg=1> DefList: { N985.t1037. CAST } N987 ( 1, 1) [001047] -c---------- * CNS_INT long 3 REG NA $24b Contained DefList: { N985.t1037. CAST } N989 ( 7, 7) [001048] ------------ * MUL long REG NA BB45 regmask=[allInt] minReg=1 last> Interval 168: long RefPositions {} physReg:NA Preferences=[allInt] MUL BB45 regmask=[allInt] minReg=1> DefList: { N989.t1048. MUL } N991 ( 31, 34) [001029] -c---------- * LEA(b+(i*8)+36) byref REG NA Contained DefList: { N989.t1048. MUL } N993 ( 33, 36) [000181] *--XG------- * IND int REG NA LCL_VAR BB45 regmask=[allInt] minReg=1 last> BB45 regmask=[allInt] minReg=1 last> Interval 169: int RefPositions {} physReg:NA Preferences=[allInt] IND BB45 regmask=[allInt] minReg=1> DefList: { N993.t181. IND } N995 ( 34, 37) [001050] ---XG------- * NEG int REG NA BB45 regmask=[allInt] minReg=1 last> Interval 170: int RefPositions {} physReg:NA Preferences=[allInt] NEG BB45 regmask=[allInt] minReg=1> DefList: { N995.t1050. NEG } N997 ( 1, 1) [000175] -c---------- * CNS_INT int -3 REG NA $e1 Contained DefList: { N995.t1050. NEG } N999 ( 36, 39) [000182] ---XG------- * ADD int REG NA BB45 regmask=[allInt] minReg=1 last> Interval 171: int RefPositions {} physReg:NA Preferences=[allInt] ADD BB45 regmask=[allInt] minReg=1> Assigning related to DefList: { N999.t182. ADD } N1001 ( 1, 1) [000183] -c---------- * CNS_INT int -1 REG NA $c4 Contained DefList: { N999.t182. ADD } N1003 ( 41, 41) [000184] ---XG------- * GE int REG NA BB45 regmask=[allInt] minReg=1 last> Interval 172: int RefPositions {} physReg:NA Preferences=[allInt] GE BB45 regmask=[allInt] minReg=1> DefList: { N1003.t184. GE } N1005 ( 45, 44) [000688] DA-XG------- * STORE_LCL_VAR int V49 tmp35 d:1 NA REG NA BB45 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB45 regmask=[allInt] minReg=1 last> DefList: { } N1007 (???,???) [001391] ------------ * IL_OFFSET void IL offset: 0x1f5 REG NA DefList: { } N1009 ( 1, 1) [001300] ------------ * LCL_VAR ref V73 cse8 u:1 NA (last use) REG NA $105 DefList: { } N1011 ( 5, 4) [000698] DA--G------- * STORE_LCL_VAR ref V50 tmp36 d:1 NA REG NA LCL_VAR BB45 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB45 regmask=[allInt] minReg=1 last> DefList: { } N1013 (???,???) [001392] ------------ * IL_OFFSET void IL offset: 0x1f5 REG NA DefList: { } N1015 ( 3, 2) [000690] ------------ * LCL_VAR int V49 tmp35 u:1 NA (last use) REG NA DefList: { } N1017 ( 1, 1) [000691] -c---------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N1019 ( 5, 4) [000692] J------N---- * NE void REG NA LCL_VAR BB45 regmask=[allInt] minReg=1 last> DefList: { } N1021 ( 7, 6) [000693] ------------ * JTRUE void REG NA CHECKING LAST USES for BB45, liveout={V00 V01 V02 V04 V05 V06 V07 V08 V10 V50 V76} ============================== Reporting this as generic context: referenced use: {V00 V04 V73 V76} def: {V10 V49 V50 V62 V74} NEW BLOCK BB46 Setting BB45 as the predecessor for determining incoming variable registers of BB46 DefList: { } N1025 (???,???) [001393] ------------ * IL_OFFSET void IL offset: 0x1f5 REG NA DefList: { } N1027 ( 2, 10) [001051] H----------- * CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" REG NA $5e Interval 173: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB46 regmask=[allInt] minReg=1> DefList: { N1027.t1051. CNS_INT } N1029 ( 4, 12) [001052] #---G------- * IND ref REG NA $114 BB46 regmask=[allInt] minReg=1 last> Interval 174: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB46 regmask=[allInt] minReg=1> DefList: { N1029.t1052. IND } N1031 (???,???) [001485] ----G------- * PUTARG_REG ref REG rcx BB46 regmask=[rcx] minReg=1> BB46 regmask=[rcx] minReg=1 last fixed> Interval 175: ref RefPositions {} physReg:NA Preferences=[allInt] BB46 regmask=[rcx] minReg=1> PUTARG_REG BB46 regmask=[rcx] minReg=1 fixed> DefList: { N1031.t1485. PUTARG_REG } N1033 ( 3, 2) [000695] ------------ * LCL_VAR ref V50 tmp36 u:1 NA (last use) REG NA $105 DefList: { N1031.t1485. PUTARG_REG } N1035 (???,???) [001486] ------------ * PUTARG_REG ref REG rdx BB46 regmask=[rdx] minReg=1> LCL_VAR BB46 regmask=[rdx] minReg=1 last fixed> Interval 176: ref RefPositions {} physReg:NA Preferences=[allInt] BB46 regmask=[rdx] minReg=1> PUTARG_REG BB46 regmask=[rdx] minReg=1 fixed> DefList: { N1031.t1485. PUTARG_REG; N1035.t1486. PUTARG_REG } N1037 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail REG NA $VN.Void BB46 regmask=[rcx] minReg=1> BB46 regmask=[rcx] minReg=1 last fixed> BB46 regmask=[rdx] minReg=1> BB46 regmask=[rdx] minReg=1 last fixed> BB46 regmask=[rax] minReg=1> BB46 regmask=[rcx] minReg=1> BB46 regmask=[rdx] minReg=1> BB46 regmask=[r8] minReg=1> BB46 regmask=[r9] minReg=1> BB46 regmask=[r10] minReg=1> BB46 regmask=[r11] minReg=1> CHECKING LAST USES for BB46, liveout={V00 V01 V02 V04 V05 V06 V07 V08 V10 V76} ============================== Reporting this as generic context: referenced use: {V50} def: {} NEW BLOCK BB47 Setting BB45 as the predecessor for determining incoming variable registers of BB47 DefList: { } N1041 (???,???) [001394] ------------ * IL_OFFSET void IL offset: 0x219 REG NA DefList: { } N1043 ( 1, 1) [000190] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N1045 ( 2, 2) [001056] -c---------- * LEA(b+60) byref REG NA Contained DefList: { } N1047 ( 1, 1) [000193] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N1049 ( 2, 2) [001075] -c---------- * LEA(b+60) byref REG NA Contained DefList: { } N1051 ( 4, 4) [000194] n---GO------ * IND int REG NA LCL_VAR BB47 regmask=[allInt] minReg=1 last> Interval 177: int RefPositions {} physReg:NA Preferences=[allInt] IND BB47 regmask=[allInt] minReg=1> DefList: { N1051.t194. IND } N1053 ( 4, 4) [001061] DA--GO------ * STORE_LCL_VAR int V63 tmp49 d:1 NA REG NA BB47 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB47 regmask=[allInt] minReg=1 last> DefList: { } N1055 ( 1, 1) [001062] ------------ * LCL_VAR int V63 tmp49 u:1 NA REG NA DefList: { } N1057 ( 1, 1) [001330] ------------ * LCL_VAR int V76 cse11 NA (last use) REG NA DefList: { } N1059 ( 6, 9) [001065] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void REG NA LCL_VAR BB47 regmask=[allInt] minReg=1 last> LCL_VAR BB47 regmask=[allInt] minReg=1 last> DefList: { } N1061 ( 1, 1) [001059] ------------ * LCL_VAR ref V04 loc0 u:1 NA REG NA DefList: { } N1063 ( 1, 1) [001063] ------------ * LCL_VAR int V63 tmp49 u:1 NA (last use) REG NA DefList: { } N1065 ( 2, 3) [001066] ------------ * CAST long <- int REG NA LCL_VAR BB47 regmask=[allInt] minReg=1 last> Interval 178: long RefPositions {} physReg:NA Preferences=[allInt] CAST BB47 regmask=[allInt] minReg=1> DefList: { N1065.t1066. CAST } N1067 ( 1, 1) [001076] -c---------- * CNS_INT long 3 REG NA $24b Contained DefList: { N1065.t1066. CAST } N1069 ( 7, 7) [001077] ------------ * MUL long REG NA BB47 regmask=[allInt] minReg=1 last> Interval 179: long RefPositions {} physReg:NA Preferences=[allInt] MUL BB47 regmask=[allInt] minReg=1> DefList: { N1069.t1077. MUL } N1071 ( 32, 35) [001058] -c---------- * LEA(b+(i*8)+36) byref REG NA Contained DefList: { N1069.t1077. MUL } N1073 ( 34, 37) [000197] *--XGO------ * IND int REG NA LCL_VAR BB47 regmask=[allInt] minReg=1 last> BB47 regmask=[allInt] minReg=1 last> Interval 180: int RefPositions {} physReg:NA Preferences=[allInt] IND BB47 regmask=[allInt] minReg=1> DefList: { N1073.t197. IND } N1075 ( 35, 38) [001079] ---XGO------ * NEG int REG NA BB47 regmask=[allInt] minReg=1 last> Interval 181: int RefPositions {} physReg:NA Preferences=[allInt] NEG BB47 regmask=[allInt] minReg=1> DefList: { N1075.t1079. NEG } N1077 ( 1, 1) [000191] -c---------- * CNS_INT int -3 REG NA $e1 Contained DefList: { N1075.t1079. NEG } N1079 ( 37, 40) [000198] ---XGO------ * ADD int REG NA BB47 regmask=[allInt] minReg=1 last> Interval 182: int RefPositions {} physReg:NA Preferences=[allInt] ADD BB47 regmask=[allInt] minReg=1> Assigning related to DefList: { N1079.t198. ADD } N1081 (???,???) [001395] -A-XGO------ * STOREIND int REG NA LCL_VAR BB47 regmask=[allInt] minReg=1 last> BB47 regmask=[allInt] minReg=1 last> DefList: { } N1083 (???,???) [001396] ------------ * IL_OFFSET void IL offset: 0x233 REG NA DefList: { } N1085 ( 1, 1) [000202] -c---------- * LCL_VAR ref V00 this u:1 NA REG NA $100 Contained DefList: { } N1087 ( 2, 2) [001083] -c---------- * LEA(b+64) byref REG NA Contained DefList: { } N1089 ( 4, 4) [000203] nc--GO------ * IND int REG NA Contained DefList: { } N1091 ( 1, 1) [000204] -c---------- * CNS_INT int -1 REG NA $c4 Contained DefList: { } N1093 ( 6, 6) [000205] -c--GO------ * ADD int REG NA Contained DefList: { } N1095 ( 1, 1) [000201] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N1097 ( 2, 2) [001081] -c---------- * LEA(b+64) byref REG NA Contained DefList: { } N1099 (???,???) [001397] -A--GO------ * STOREIND int REG NA LCL_VAR BB47 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB47, liveout={V00 V01 V02 V04 V05 V06 V07 V08 V10} ============================== Reporting this as generic context: referenced use: {V00 V04 V76} def: {V63} NEW BLOCK BB48 Setting BB44 as the predecessor for determining incoming variable registers of BB48 DefList: { } N1103 (???,???) [001398] ------------ * IL_OFFSET void IL offset: 0x243 REG NA DefList: { } N1105 ( 1, 1) [000072] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N1107 ( 2, 2) [001085] -c---------- * LEA(b+56) byref REG NA Contained DefList: { } N1109 ( 4, 4) [000073] n---GO------ * IND int REG NA LCL_VAR BB48 regmask=[allInt] minReg=1 last> Interval 183: int RefPositions {} physReg:NA Preferences=[allInt] IND BB48 regmask=[allInt] minReg=1> DefList: { N1109.t73. IND } N1111 ( 8, 7) [001311] DA--GO------ * STORE_LCL_VAR int V75 cse10 d:1 NA REG NA BB48 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB48 regmask=[allInt] minReg=1 last> DefList: { } N1113 ( 3, 2) [001312] ------------ * LCL_VAR int V75 cse10 u:1 NA REG NA DefList: { } N1115 ( 15, 12) [000075] DA--GO------ * STORE_LCL_VAR int V13 loc9 d:1 NA REG NA LCL_VAR BB48 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB48 regmask=[allInt] minReg=1 last> DefList: { } N1117 (???,???) [001399] ------------ * IL_OFFSET void IL offset: 0x24b REG NA DefList: { } N1119 ( 1, 1) [001331] ------------ * LCL_VAR int V76 cse11 NA (last use) REG NA DefList: { } N1121 ( 3, 2) [000076] ------------ * LCL_VAR int V13 loc9 u:1 NA REG NA DefList: { } N1123 ( 5, 4) [000079] N------N-U-- * NE void REG NA LCL_VAR BB48 regmask=[allInt] minReg=1 last> LCL_VAR BB48 regmask=[allInt] minReg=1 last> DefList: { } N1125 ( 7, 6) [000080] ------------ * JTRUE void REG NA CHECKING LAST USES for BB48, liveout={V00 V01 V02 V05 V06 V07 V08 V13 V73 V75} ============================== Reporting this as generic context: referenced use: {V00 V76} def: {V13 V75} NEW BLOCK BB49 Setting BB48 as the predecessor for determining incoming variable registers of BB49 DefList: { } N1129 (???,???) [001400] ------------ * IL_OFFSET void IL offset: 0x252 REG NA DefList: { } N1131 ( 3, 2) [001314] ------------ * LCL_VAR int V75 cse10 u:1 NA (last use) REG NA DefList: { } N1133 (???,???) [001487] ------------ * PUTARG_REG int REG rcx BB49 regmask=[rcx] minReg=1> LCL_VAR BB49 regmask=[rcx] minReg=1 last fixed> Interval 184: int RefPositions {} physReg:NA Preferences=[allInt] BB49 regmask=[rcx] minReg=1> PUTARG_REG BB49 regmask=[rcx] minReg=1 fixed> DefList: { N1133.t1487. PUTARG_REG } N1135 ( 17, 8) [000702] --CXG------- * CALL int System.Collections.HashHelpers.ExpandPrime REG NA $1d7 BB49 regmask=[rcx] minReg=1> BB49 regmask=[rcx] minReg=1 last fixed> BB49 regmask=[rax] minReg=1> BB49 regmask=[rcx] minReg=1> BB49 regmask=[rdx] minReg=1> BB49 regmask=[r8] minReg=1> BB49 regmask=[r9] minReg=1> BB49 regmask=[r10] minReg=1> BB49 regmask=[r11] minReg=1> Interval 185: int RefPositions {} physReg:NA Preferences=[allInt] BB49 regmask=[rax] minReg=1> CALL BB49 regmask=[rax] minReg=1 fixed> DefList: { N1135.t702. CALL } N1137 ( 21, 11) [001090] DA-XG-----L- * STORE_LCL_VAR int V64 tmp50 d:1 NA REG NA BB49 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB49 regmask=[allInt] minReg=1 last> DefList: { } N1139 ( 3, 2) [001091] ------------ * LCL_VAR int V64 tmp50 u:1 NA (last use) REG NA $1d7 DefList: { } N1141 (???,???) [001488] ------------ * PUTARG_REG int REG rdx BB49 regmask=[rdx] minReg=1> LCL_VAR BB49 regmask=[rdx] minReg=1 last fixed> Interval 186: int RefPositions {} physReg:NA Preferences=[allInt] BB49 regmask=[rdx] minReg=1> PUTARG_REG BB49 regmask=[rdx] minReg=1 fixed> DefList: { N1141.t1488. PUTARG_REG } N1143 ( 1, 1) [000163] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { N1141.t1488. PUTARG_REG } N1145 (???,???) [001489] ------------ * PUTARG_REG ref REG rcx BB49 regmask=[rcx] minReg=1> LCL_VAR BB49 regmask=[rcx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 187: ref RefPositions {} physReg:NA Preferences=[allInt] BB49 regmask=[rcx] minReg=1> PUTARG_REG BB49 regmask=[rcx] minReg=1 fixed> Assigning related to DefList: { N1141.t1488. PUTARG_REG; N1145.t1489. PUTARG_REG } N1147 ( 1, 1) [000704] ------------ * CNS_INT int 0 REG NA $c0 Interval 188: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB49 regmask=[allInt] minReg=1> DefList: { N1141.t1488. PUTARG_REG; N1145.t1489. PUTARG_REG; N1147.t704. CNS_INT } N1149 (???,???) [001490] ------------ * PUTARG_REG int REG r8 BB49 regmask=[r8] minReg=1> BB49 regmask=[r8] minReg=1 last fixed> Interval 189: int RefPositions {} physReg:NA Preferences=[allInt] BB49 regmask=[r8] minReg=1> PUTARG_REG BB49 regmask=[r8] minReg=1 fixed> DefList: { N1141.t1488. PUTARG_REG; N1145.t1489. PUTARG_REG; N1149.t1490. PUTARG_REG } N1151 ( 43, 24) [000705] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize REG NA $VN.Void BB49 regmask=[rdx] minReg=1> BB49 regmask=[rdx] minReg=1 last fixed> BB49 regmask=[rcx] minReg=1> BB49 regmask=[rcx] minReg=1 last fixed> BB49 regmask=[r8] minReg=1> BB49 regmask=[r8] minReg=1 last fixed> BB49 regmask=[rax] minReg=1> BB49 regmask=[rcx] minReg=1> BB49 regmask=[rdx] minReg=1> BB49 regmask=[r8] minReg=1> BB49 regmask=[r9] minReg=1> BB49 regmask=[r10] minReg=1> BB49 regmask=[r11] minReg=1> DefList: { } N1153 (???,???) [001401] ------------ * IL_OFFSET void IL offset: 0x258 REG NA DefList: { } N1155 ( 1, 1) [000165] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N1157 ( 2, 2) [001095] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N1159 ( 4, 4) [000709] n---GO------ * IND ref REG NA LCL_VAR BB49 regmask=[allInt] minReg=1 last> Interval 190: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB49 regmask=[allInt] minReg=1> DefList: { N1159.t709. IND } N1161 ( 8, 7) [000711] DA--GO------ * STORE_LCL_VAR ref V52 tmp38 d:1 NA REG NA BB49 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB49 regmask=[allInt] minReg=1 last> DefList: { } N1163 (???,???) [001402] ------------ * IL_OFFSET void IL offset: 0x258 REG NA DefList: { } N1165 ( 3, 2) [000713] ------------ * LCL_VAR ref V52 tmp38 u:1 NA REG NA DefList: { } N1167 (???,???) [001450] -c---------- * LEA(b+8) ref REG NA Contained DefList: { } N1169 ( 5, 4) [000714] ---X-------- * IND int REG NA LCL_VAR BB49 regmask=[allInt] minReg=1 last> Interval 191: int RefPositions {} physReg:NA Preferences=[allInt] IND BB49 regmask=[allInt] minReg=1> DefList: { N1169.t714. IND } N1171 ( 9, 7) [001286] DA-X-------- * STORE_LCL_VAR int V72 cse7 d:1 NA REG NA BB49 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB49 regmask=[allInt] minReg=1 last> DefList: { } N1173 ( 3, 2) [001287] ------------ * LCL_VAR int V72 cse7 u:1 NA REG NA DefList: { } N1175 ( 12, 9) [000760] DA-X-------- * STORE_LCL_VAR int V53 tmp39 d:1 NA REG NA LCL_VAR BB49 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB49 regmask=[allInt] minReg=1 last> DefList: { } N1177 (???,???) [001403] ------------ * IL_OFFSET void IL offset: 0x258 REG NA DefList: { } N1179 ( 1, 1) [000715] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N1181 ( 2, 2) [001097] -c---------- * LEA(b+48) byref REG NA Contained DefList: { } N1183 ( 4, 4) [000716] n---GO------ * IND long REG NA LCL_VAR BB49 regmask=[allInt] minReg=1 last> Interval 192: long RefPositions {} physReg:NA Preferences=[allInt] IND BB49 regmask=[allInt] minReg=1> DefList: { N1183.t716. IND } N1185 ( 8, 7) [000762] DA--GO------ * STORE_LCL_VAR long V54 tmp40 d:1 NA REG NA BB49 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB49 regmask=[allInt] minReg=1 last> DefList: { } N1187 (???,???) [001404] ------------ * IL_OFFSET void IL offset: 0x258 REG NA DefList: { } N1189 ( 1, 1) [000728] ------------ * LCL_VAR int V53 tmp39 u:1 NA REG NA DefList: { } N1191 ( 1, 4) [000729] -c---------- * CNS_INT int 0x7FFFFFFF REG NA $ce Contained DefList: { } N1193 ( 6, 6) [000730] N--------U-- * LE int REG NA LCL_VAR BB49 regmask=[allInt] minReg=1 last> Interval 193: int RefPositions {} physReg:NA Preferences=[allInt] LE BB49 regmask=[allInt] minReg=1> DefList: { N1193.t730. LE } N1195 ( 10, 9) [000773] DA---------- * STORE_LCL_VAR int V56 tmp42 d:1 NA REG NA BB49 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB49 regmask=[allInt] minReg=1 last> DefList: { } N1197 (???,???) [001405] ------------ * IL_OFFSET void IL offset: 0x258 REG NA DefList: { } N1199 (???,???) [001406] ------------ * IL_OFFSET void IL offset: 0x258 REG NA DefList: { } N1201 ( 1, 1) [001302] ------------ * LCL_VAR ref V73 cse8 u:1 NA REG NA $105 DefList: { } N1203 ( 5, 4) [000785] DA--G------- * STORE_LCL_VAR ref V58 tmp44 d:1 NA REG NA LCL_VAR BB49 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB49 regmask=[allInt] minReg=1 last> DefList: { } N1205 (???,???) [001407] ------------ * IL_OFFSET void IL offset: 0x258 REG NA DefList: { } N1207 ( 3, 2) [000775] ------------ * LCL_VAR int V56 tmp42 u:1 NA (last use) REG NA DefList: { } N1209 ( 1, 1) [000776] -c---------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N1211 ( 5, 4) [000777] J------N---- * NE void REG NA LCL_VAR BB49 regmask=[allInt] minReg=1 last> DefList: { } N1213 ( 7, 6) [000778] ------------ * JTRUE void REG NA CHECKING LAST USES for BB49, liveout={V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V58 V72 V73} ============================== Reporting this as generic context: referenced use: {V00 V73 V75} def: {V52 V53 V54 V56 V57 V58 V64 V72} NEW BLOCK BB50 Setting BB49 as the predecessor for determining incoming variable registers of BB50 DefList: { } N1217 (???,???) [001408] ------------ * IL_OFFSET void IL offset: 0x258 REG NA DefList: { } N1219 ( 3, 2) [000779] ------------ * LCL_VAR ref V58 tmp44 u:1 NA REG NA $105 DefList: { } N1221 (???,???) [001491] ------------ * PUTARG_REG ref REG rcx BB50 regmask=[rcx] minReg=1> LCL_VAR BB50 regmask=[rcx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 194: ref RefPositions {} physReg:NA Preferences=[allInt] BB50 regmask=[rcx] minReg=1> PUTARG_REG BB50 regmask=[rcx] minReg=1 fixed> Assigning related to DefList: { N1221.t1491. PUTARG_REG } N1223 ( 3, 2) [000780] ------------ * LCL_VAR ref V58 tmp44 u:1 NA (last use) REG NA $105 DefList: { N1221.t1491. PUTARG_REG } N1225 (???,???) [001492] ------------ * PUTARG_REG ref REG rdx BB50 regmask=[rdx] minReg=1> LCL_VAR BB50 regmask=[rdx] minReg=1 last fixed> Interval 195: ref RefPositions {} physReg:NA Preferences=[allInt] BB50 regmask=[rdx] minReg=1> PUTARG_REG BB50 regmask=[rdx] minReg=1 fixed> DefList: { N1221.t1491. PUTARG_REG; N1225.t1492. PUTARG_REG } N1227 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail REG NA $VN.Void BB50 regmask=[rcx] minReg=1> BB50 regmask=[rcx] minReg=1 last fixed> BB50 regmask=[rdx] minReg=1> BB50 regmask=[rdx] minReg=1 last fixed> BB50 regmask=[rax] minReg=1> BB50 regmask=[rcx] minReg=1> BB50 regmask=[rdx] minReg=1> BB50 regmask=[r8] minReg=1> BB50 regmask=[r9] minReg=1> BB50 regmask=[r10] minReg=1> BB50 regmask=[r11] minReg=1> CHECKING LAST USES for BB50, liveout={V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V72 V73} ============================== Reporting this as generic context: referenced use: {V58} def: {} NEW BLOCK BB51 Setting BB49 as the predecessor for determining incoming variable registers of BB51 DefList: { } N1231 (???,???) [001409] ------------ * IL_OFFSET void IL offset: 0x258 REG NA DefList: { } N1233 ( 3, 2) [000735] ------------ * LCL_VAR long V54 tmp40 u:1 NA (last use) REG NA DefList: { } N1235 ( 1, 1) [000166] ------------ * LCL_VAR int V06 loc2 u:1 NA REG NA $3c0 DefList: { } N1237 ( 2, 3) [000736] ---------U-- * CAST long <- ulong <- uint REG NA $310 LCL_VAR BB51 regmask=[allInt] minReg=1 last> Interval 196: long RefPositions {} physReg:NA Preferences=[allInt] CAST BB51 regmask=[allInt] minReg=1> DefList: { N1237.t736. CAST } N1239 ( 9, 8) [000737] ------------ * MUL long REG NA LCL_VAR BB51 regmask=[allInt] minReg=1 last> BB51 regmask=[allInt] minReg=1 last> Interval 197: long RefPositions {} physReg:NA Preferences=[allInt] MUL BB51 regmask=[allInt] minReg=1> Assigning related to Assigning related to DefList: { N1239.t737. MUL } N1241 ( 1, 1) [000738] -c---------- * CNS_INT int 32 REG NA $d2 Contained DefList: { N1239.t737. MUL } N1243 ( 11, 10) [000739] ------------ * RSZ long REG NA BB51 regmask=[allInt] minReg=1 last> Interval 198: long RefPositions {} physReg:NA Preferences=[allInt] RSZ BB51 regmask=[allInt] minReg=1> Assigning related to DefList: { N1243.t739. RSZ } N1245 ( 1, 1) [000741] -c---------- * CNS_INT long 1 REG NA $247 Contained DefList: { N1243.t739. RSZ } N1247 ( 13, 12) [000742] ------------ * ADD long REG NA BB51 regmask=[allInt] minReg=1 last> Interval 199: long RefPositions {} physReg:NA Preferences=[allInt] ADD BB51 regmask=[allInt] minReg=1> Assigning related to DefList: { N1247.t742. ADD } N1249 ( 1, 1) [000743] ------------ * LCL_VAR int V53 tmp39 u:1 NA REG NA DefList: { N1247.t742. ADD } N1251 ( 2, 3) [000744] ---------U-- * CAST long <- ulong <- uint REG NA LCL_VAR BB51 regmask=[allInt] minReg=1 last> Interval 200: long RefPositions {} physReg:NA Preferences=[allInt] CAST BB51 regmask=[allInt] minReg=1> DefList: { N1247.t742. ADD; N1251.t744. CAST } N1253 ( 19, 18) [000745] ------------ * MUL long REG NA BB51 regmask=[allInt] minReg=1 last> BB51 regmask=[allInt] minReg=1 last> Interval 201: long RefPositions {} physReg:NA Preferences=[allInt] MUL BB51 regmask=[allInt] minReg=1> Assigning related to Assigning related to DefList: { N1253.t745. MUL } N1255 ( 1, 1) [000746] -c---------- * CNS_INT int 32 REG NA $d2 Contained DefList: { N1253.t745. MUL } N1257 ( 21, 20) [000747] ------------ * RSZ long REG NA BB51 regmask=[allInt] minReg=1 last> Interval 202: long RefPositions {} physReg:NA Preferences=[allInt] RSZ BB51 regmask=[allInt] minReg=1> Assigning related to DefList: { N1257.t747. RSZ } N1259 ( 22, 22) [000748] ------------ * CAST int <- uint <- long REG NA BB51 regmask=[allInt] minReg=1 last> Interval 203: int RefPositions {} physReg:NA Preferences=[allInt] CAST BB51 regmask=[allInt] minReg=1> DefList: { N1259.t748. CAST } N1261 ( 26, 25) [000750] DA---------- * STORE_LCL_VAR int V55 tmp41 d:1 NA REG NA BB51 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB51 regmask=[allInt] minReg=1 last> DefList: { } N1263 (???,???) [001410] ------------ * IL_OFFSET void IL offset: 0x258 REG NA DefList: { } N1265 ( 1, 1) [000752] ------------ * LCL_VAR int V06 loc2 u:1 NA REG NA $3c0 DefList: { } N1267 ( 1, 1) [000753] ------------ * LCL_VAR int V53 tmp39 u:1 NA (last use) REG NA DefList: { } N1269 ( 22, 5) [000754] ---X-------- * UMOD int REG NA BB51 regmask=[rax] minReg=1> LCL_VAR BB51 regmask=[rax] minReg=1 last fixed> LCL_VAR BB51 regmask=[rcx rbx rbp rsi rdi r8-r15] minReg=1 last> BB51 regmask=[rax] minReg=1> BB51 regmask=[rdx] minReg=1> Interval 204: int RefPositions {} physReg:NA Preferences=[allInt] BB51 regmask=[rdx] minReg=1> UMOD BB51 regmask=[rdx] minReg=1 fixed> DefList: { N1269.t754. UMOD } N1271 ( 3, 2) [000751] ------------ * LCL_VAR int V55 tmp41 u:1 NA REG NA DefList: { N1269.t754. UMOD } N1273 ( 29, 8) [000755] ---X-------- * EQ int REG NA BB51 regmask=[allInt] minReg=1 last> LCL_VAR BB51 regmask=[allInt] minReg=1 last> Interval 205: int RefPositions {} physReg:NA Preferences=[allInt] EQ BB51 regmask=[allInt] minReg=1> DefList: { N1273.t755. EQ } N1275 ( 33, 11) [000796] DA-X-------- * STORE_LCL_VAR int V59 tmp45 d:1 NA REG NA BB51 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB51 regmask=[allInt] minReg=1 last> DefList: { } N1277 (???,???) [001411] ------------ * IL_OFFSET void IL offset: 0x258 REG NA DefList: { } N1279 (???,???) [001412] ------------ * IL_OFFSET void IL offset: 0x258 REG NA DefList: { } N1281 ( 1, 1) [001304] ------------ * LCL_VAR ref V73 cse8 u:1 NA (last use) REG NA $105 DefList: { } N1283 ( 5, 4) [000808] DA--G------- * STORE_LCL_VAR ref V61 tmp47 d:1 NA REG NA LCL_VAR BB51 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB51 regmask=[allInt] minReg=1 last> DefList: { } N1285 (???,???) [001413] ------------ * IL_OFFSET void IL offset: 0x258 REG NA DefList: { } N1287 ( 3, 2) [000798] ------------ * LCL_VAR int V59 tmp45 u:1 NA (last use) REG NA DefList: { } N1289 ( 1, 1) [000799] -c---------- * CNS_INT int 0 REG NA $c0 Contained DefList: { } N1291 ( 5, 4) [000800] J------N---- * NE void REG NA LCL_VAR BB51 regmask=[allInt] minReg=1 last> DefList: { } N1293 ( 7, 6) [000801] ------------ * JTRUE void REG NA CHECKING LAST USES for BB51, liveout={V00 V01 V02 V05 V06 V07 V13 V52 V55 V61 V72} ============================== Reporting this as generic context: referenced use: {V06 V53 V54 V73} def: {V55 V59 V60 V61} NEW BLOCK BB52 Setting BB51 as the predecessor for determining incoming variable registers of BB52 DefList: { } N1297 (???,???) [001414] ------------ * IL_OFFSET void IL offset: 0x258 REG NA DefList: { } N1299 ( 3, 2) [000802] ------------ * LCL_VAR ref V61 tmp47 u:1 NA REG NA $105 DefList: { } N1301 (???,???) [001493] ------------ * PUTARG_REG ref REG rcx BB52 regmask=[rcx] minReg=1> LCL_VAR BB52 regmask=[rcx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 206: ref RefPositions {} physReg:NA Preferences=[allInt] BB52 regmask=[rcx] minReg=1> PUTARG_REG BB52 regmask=[rcx] minReg=1 fixed> Assigning related to DefList: { N1301.t1493. PUTARG_REG } N1303 ( 3, 2) [000803] ------------ * LCL_VAR ref V61 tmp47 u:1 NA (last use) REG NA $105 DefList: { N1301.t1493. PUTARG_REG } N1305 (???,???) [001494] ------------ * PUTARG_REG ref REG rdx BB52 regmask=[rdx] minReg=1> LCL_VAR BB52 regmask=[rdx] minReg=1 last fixed> Interval 207: ref RefPositions {} physReg:NA Preferences=[allInt] BB52 regmask=[rdx] minReg=1> PUTARG_REG BB52 regmask=[rdx] minReg=1 fixed> DefList: { N1301.t1493. PUTARG_REG; N1305.t1494. PUTARG_REG } N1307 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail REG NA $VN.Void BB52 regmask=[rcx] minReg=1> BB52 regmask=[rcx] minReg=1 last fixed> BB52 regmask=[rdx] minReg=1> BB52 regmask=[rdx] minReg=1 last fixed> BB52 regmask=[rax] minReg=1> BB52 regmask=[rcx] minReg=1> BB52 regmask=[rdx] minReg=1> BB52 regmask=[r8] minReg=1> BB52 regmask=[r9] minReg=1> BB52 regmask=[r10] minReg=1> BB52 regmask=[r11] minReg=1> CHECKING LAST USES for BB52, liveout={V00 V01 V02 V05 V06 V07 V13 V52 V55 V72} ============================== Reporting this as generic context: referenced use: {V61} def: {} NEW BLOCK BB53 Setting BB51 as the predecessor for determining incoming variable registers of BB53 DefList: { } N1311 (???,???) [001415] ------------ * IL_OFFSET void IL offset: 0x258 REG NA DefList: { } N1313 ( 3, 2) [000758] ------------ * LCL_VAR int V55 tmp41 u:1 NA REG NA DefList: { } N1315 ( 3, 2) [001289] ------------ * LCL_VAR int V72 cse7 u:1 NA (last use) REG NA DefList: { } N1317 ( 10, 11) [001105] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void REG NA LCL_VAR BB53 regmask=[allInt] minReg=1 last> LCL_VAR BB53 regmask=[allInt] minReg=1 last> DefList: { } N1319 ( 3, 2) [001102] ------------ * LCL_VAR ref V52 tmp38 u:1 NA (last use) REG NA DefList: { } N1321 ( 3, 2) [001103] ------------ * LCL_VAR int V55 tmp41 u:1 NA (last use) REG NA DefList: { } N1323 ( 4, 4) [001106] ------------ * CAST long <- int REG NA LCL_VAR BB53 regmask=[allInt] minReg=1 last> Interval 208: long RefPositions {} physReg:NA Preferences=[allInt] CAST BB53 regmask=[allInt] minReg=1> DefList: { N1323.t1106. CAST } N1325 ( 9, 8) [001111] -------N---- * LEA(b+(i*4)+16) byref REG NA LCL_VAR BB53 regmask=[allInt] minReg=1 last> BB53 regmask=[allInt] minReg=1 last> Interval 209: byref RefPositions {} physReg:NA Preferences=[allInt] LEA BB53 regmask=[allInt] minReg=1> DefList: { N1325.t1111. LEA } N1327 ( 33, 31) [000722] DA-XG------- * STORE_LCL_VAR byref V51 tmp37 d:1 NA REG NA BB53 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB53 regmask=[allInt] minReg=1 last> DefList: { } N1329 ( 3, 2) [000723] ------------ * LCL_VAR byref V51 tmp37 u:1 NA (last use) REG NA $87 DefList: { } N1331 ( 7, 5) [000170] DA---------- * STORE_LCL_VAR byref V08 loc4 d:4 NA REG NA LCL_VAR BB53 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB53 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB53, liveout={V00 V01 V02 V05 V06 V07 V08 V13} ============================== Reporting this as generic context: referenced use: {V52 V55 V72} def: {V08 V51} NEW BLOCK BB54 Setting BB48 as the predecessor for determining incoming variable registers of BB54 DefList: { } N1335 (???,???) [001416] ------------ * IL_OFFSET void IL offset: 0x261 REG NA DefList: { } N1337 ( 3, 2) [000081] ------------ * LCL_VAR int V13 loc9 u:1 NA (last use) REG NA DefList: { } N1339 ( 7, 5) [000083] DA---------- * STORE_LCL_VAR int V10 loc6 d:2 NA REG NA LCL_VAR BB54 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB54 regmask=[allInt] minReg=1 last> DefList: { } N1341 (???,???) [001417] ------------ * IL_OFFSET void IL offset: 0x265 REG NA DefList: { } N1343 ( 3, 2) [000085] ------------ * LCL_VAR int V10 loc6 u:2 NA REG NA DefList: { } N1345 ( 1, 1) [000086] -c---------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N1347 ( 5, 4) [000087] ------------ * ADD int REG NA LCL_VAR BB54 regmask=[allInt] minReg=1 last> Interval 210: int RefPositions {} physReg:NA Preferences=[allInt] ADD BB54 regmask=[allInt] minReg=1> DefList: { N1347.t87. ADD } N1349 ( 1, 1) [000084] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { N1347.t87. ADD } N1351 ( 2, 2) [001115] -c---------- * LEA(b+56) byref REG NA Contained DefList: { N1347.t87. ADD } N1353 (???,???) [001418] -A--GO------ * STOREIND int REG NA LCL_VAR BB54 regmask=[allInt] minReg=1 last> BB54 regmask=[allInt] minReg=1 last> DefList: { } N1355 (???,???) [001419] ------------ * IL_OFFSET void IL offset: 0x26f REG NA DefList: { } N1357 ( 1, 1) [000090] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N1359 ( 2, 2) [001117] -c---------- * LEA(b+16) byref REG NA Contained DefList: { } N1361 ( 4, 4) [000091] n---GO------ * IND ref REG NA LCL_VAR BB54 regmask=[allInt] minReg=1 last> Interval 211: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB54 regmask=[allInt] minReg=1> DefList: { N1361.t91. IND } N1363 ( 4, 4) [000093] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:3 NA REG NA BB54 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB54 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB54, liveout={V00 V01 V02 V04 V05 V06 V07 V08 V10} ============================== Reporting this as generic context: referenced use: {V00 V13} def: {V04 V10} NEW BLOCK BB55 Setting BB47 as the predecessor for determining incoming variable registers of BB55 DefList: { } N1367 (???,???) [001420] ------------ * IL_OFFSET void IL offset: 0x276 REG NA DefList: { } N1369 ( 3, 2) [000095] ------------ * LCL_VAR int V10 loc6 u:1 NA REG NA $3cc DefList: { } N1371 ( 1, 1) [000094] ------------ * LCL_VAR ref V04 loc0 u:2 NA REG NA $684 DefList: { } N1373 (???,???) [001452] -c---------- * LEA(b+8) ref REG NA Contained DefList: { } N1375 ( 3, 3) [001120] -c-X-------- * IND int REG NA $73d Contained DefList: { } N1377 ( 10, 12) [001121] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void REG NA $7cd LCL_VAR BB55 regmask=[allInt] minReg=1 last> LCL_VAR BB55 regmask=[allInt] minReg=1 last> DefList: { } N1379 ( 1, 1) [001118] ------------ * LCL_VAR ref V04 loc0 u:2 NA REG NA $684 DefList: { } N1381 ( 3, 2) [001119] ------------ * LCL_VAR int V10 loc6 u:1 NA REG NA $3cc DefList: { } N1383 ( 4, 4) [001122] ------------ * CAST long <- int REG NA $6dc LCL_VAR BB55 regmask=[allInt] minReg=1 last> Interval 212: long RefPositions {} physReg:NA Preferences=[allInt] CAST BB55 regmask=[allInt] minReg=1> DefList: { N1383.t1122. CAST } N1385 ( 1, 1) [001129] -c---------- * CNS_INT long 3 REG NA $24b Contained DefList: { N1383.t1122. CAST } N1387 ( 9, 8) [001130] ------------ * MUL long REG NA $6dd BB55 regmask=[allInt] minReg=1 last> Interval 213: long RefPositions {} physReg:NA Preferences=[allInt] MUL BB55 regmask=[allInt] minReg=1> DefList: { N1387.t1130. MUL } N1389 ( 12, 11) [001127] -------N---- * LEA(b+(i*8)+16) byref REG NA LCL_VAR BB55 regmask=[allInt] minReg=1 last> BB55 regmask=[allInt] minReg=1 last> Interval 214: byref RefPositions {} physReg:NA Preferences=[allInt] LEA BB55 regmask=[allInt] minReg=1> DefList: { N1389.t1127. LEA } N1391 ( 39, 38) [000099] DA-XG------- * STORE_LCL_VAR byref V11 loc7 d:1 NA REG NA BB55 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB55 regmask=[allInt] minReg=1 last> DefList: { } N1393 (???,???) [001421] ------------ * IL_OFFSET void IL offset: 0x280 REG NA DefList: { } N1395 ( 3, 2) [000100] ------------ * LCL_VAR byref V11 loc7 u:1 NA REG NA $8c DefList: { } N1397 ( 4, 3) [001133] -c---------- * LEA(b+16) byref REG NA Contained DefList: { } N1399 ( 1, 1) [000101] ------------ * LCL_VAR int V06 loc2 u:1 NA (last use) REG NA $3c0 DefList: { } N1401 (???,???) [001422] -A-XG------- * STOREIND int REG NA LCL_VAR BB55 regmask=[allInt] minReg=1 last> LCL_VAR BB55 regmask=[allInt] minReg=1 last> DefList: { } N1403 (???,???) [001423] ------------ * IL_OFFSET void IL offset: 0x288 REG NA DefList: { } N1405 ( 3, 2) [000105] ------------ * LCL_VAR byref V08 loc4 u:2 NA REG NA $781 DefList: { } N1407 ( 6, 4) [000106] *--XG------- * IND int REG NA LCL_VAR BB55 regmask=[allInt] minReg=1 last> Interval 215: int RefPositions {} physReg:NA Preferences=[allInt] IND BB55 regmask=[allInt] minReg=1> DefList: { N1407.t106. IND } N1409 ( 1, 1) [000107] -c---------- * CNS_INT int -1 REG NA $c4 Contained DefList: { N1407.t106. IND } N1411 ( 8, 6) [000108] ---XG------- * ADD int REG NA BB55 regmask=[allInt] minReg=1 last> Interval 216: int RefPositions {} physReg:NA Preferences=[allInt] ADD BB55 regmask=[allInt] minReg=1> Assigning related to DefList: { N1411.t108. ADD } N1413 ( 3, 2) [000104] ------------ * LCL_VAR byref V11 loc7 u:1 NA REG NA $8c DefList: { N1411.t108. ADD } N1415 ( 4, 3) [001135] -c---------- * LEA(b+20) byref REG NA Contained DefList: { N1411.t108. ADD } N1417 (???,???) [001424] -A-XGO------ * STOREIND int REG NA LCL_VAR BB55 regmask=[allInt] minReg=1 last> BB55 regmask=[allInt] minReg=1 last> DefList: { } N1419 (???,???) [001425] ------------ * IL_OFFSET void IL offset: 0x294 REG NA DefList: { } N1421 ( 3, 2) [000111] ------------ * LCL_VAR byref V11 loc7 u:1 NA Zero Fseq[key] REG NA $8f DefList: { } N1423 ( 1, 1) [000112] ------------ * LCL_VAR ref V01 arg1 u:1 NA (last use) REG NA $101 DefList: { } N1425 (???,???) [001426] -A-XG------- * STOREIND ref REG NA BB55 regmask=[rcx] minReg=1> LCL_VAR BB55 regmask=[rcx] minReg=1 last fixed> BB55 regmask=[rdx] minReg=1> LCL_VAR BB55 regmask=[rdx] minReg=1 last fixed> BB55 regmask=[rax] minReg=1> BB55 regmask=[rcx] minReg=1> BB55 regmask=[rdx] minReg=1> BB55 regmask=[r8] minReg=1> BB55 regmask=[r9] minReg=1> BB55 regmask=[r10] minReg=1> BB55 regmask=[r11] minReg=1> BB55 regmask=[mm0] minReg=1> BB55 regmask=[mm1] minReg=1> BB55 regmask=[mm2] minReg=1> BB55 regmask=[mm3] minReg=1> BB55 regmask=[mm4] minReg=1> BB55 regmask=[mm5] minReg=1> DefList: { } N1427 (???,???) [001427] ------------ * IL_OFFSET void IL offset: 0x29c REG NA DefList: { } N1429 ( 3, 2) [000115] ------------ * LCL_VAR byref V11 loc7 u:1 NA (last use) REG NA $8c DefList: { } N1431 ( 4, 3) [001137] ------------ * LEA(b+8) byref REG NA LCL_VAR BB55 regmask=[allInt] minReg=1 last> Interval 217: byref RefPositions {} physReg:NA Preferences=[allInt] LEA BB55 regmask=[allInt] minReg=1> DefList: { N1431.t1137. LEA } N1433 ( 1, 1) [000116] ------------ * LCL_VAR ref V02 arg2 u:1 NA (last use) REG NA $102 DefList: { N1431.t1137. LEA } N1435 (???,???) [001428] -A--GO------ * STOREIND ref REG NA BB55 regmask=[rcx] minReg=1> BB55 regmask=[rcx] minReg=1 last fixed> BB55 regmask=[rdx] minReg=1> LCL_VAR BB55 regmask=[rdx] minReg=1 last fixed> BB55 regmask=[rax] minReg=1> BB55 regmask=[rcx] minReg=1> BB55 regmask=[rdx] minReg=1> BB55 regmask=[r8] minReg=1> BB55 regmask=[r9] minReg=1> BB55 regmask=[r10] minReg=1> BB55 regmask=[r11] minReg=1> BB55 regmask=[mm0] minReg=1> BB55 regmask=[mm1] minReg=1> BB55 regmask=[mm2] minReg=1> BB55 regmask=[mm3] minReg=1> BB55 regmask=[mm4] minReg=1> BB55 regmask=[mm5] minReg=1> DefList: { } N1437 (???,???) [001429] ------------ * IL_OFFSET void IL offset: 0x2a4 REG NA DefList: { } N1439 ( 3, 2) [000120] ------------ * LCL_VAR int V10 loc6 u:1 NA (last use) REG NA $3cc DefList: { } N1441 ( 1, 1) [000121] -c---------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N1443 ( 5, 4) [000122] ------------ * ADD int REG NA $804 LCL_VAR BB55 regmask=[allInt] minReg=1 last> Interval 218: int RefPositions {} physReg:NA Preferences=[allInt] ADD BB55 regmask=[allInt] minReg=1> Assigning related to DefList: { N1443.t122. ADD } N1445 ( 3, 2) [000119] ------------ * LCL_VAR byref V08 loc4 u:2 NA (last use) REG NA $781 DefList: { N1443.t122. ADD } N1447 (???,???) [001430] -A--GO------ * STOREIND int REG NA LCL_VAR BB55 regmask=[allInt] minReg=1 last> BB55 regmask=[allInt] minReg=1 last> DefList: { } N1449 (???,???) [001431] ------------ * IL_OFFSET void IL offset: 0x2ab REG NA DefList: { } N1451 ( 1, 1) [000126] -c---------- * LCL_VAR ref V00 this u:1 NA REG NA $100 Contained DefList: { } N1453 ( 2, 2) [001141] -c---------- * LEA(b+68) byref REG NA Contained DefList: { } N1455 ( 4, 4) [000127] nc--GO------ * IND int REG NA Contained DefList: { } N1457 ( 1, 1) [000128] -c---------- * CNS_INT int 1 REG NA $c1 Contained DefList: { } N1459 ( 6, 6) [000129] -c--GO------ * ADD int REG NA Contained DefList: { } N1461 ( 1, 1) [000125] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N1463 ( 2, 2) [001139] -c---------- * LEA(b+68) byref REG NA Contained DefList: { } N1465 (???,???) [001432] -A--GO------ * STOREIND int REG NA LCL_VAR BB55 regmask=[allInt] minReg=1 last> DefList: { } N1467 (???,???) [001433] ------------ * IL_OFFSET void IL offset: 0x2ca REG NA DefList: { } N1469 ( 1, 1) [000145] ------------ * LCL_VAR int V07 loc3 u:2 NA (last use) REG NA $3c5 DefList: { } N1471 ( 1, 1) [000146] -c---------- * CNS_INT int 100 REG NA $e3 Contained DefList: { } N1473 ( 3, 3) [000147] N------N-U-- * LE void REG NA $80d LCL_VAR BB55 regmask=[allInt] minReg=1 last> DefList: { } N1475 ( 5, 5) [000148] ------------ * JTRUE void REG NA CHECKING LAST USES for BB55, liveout={V00 V04 V05} ============================== Reporting this as generic context: referenced use: {V00 V01 V02 V04 V06 V07 V08 V10} def: {V11} NEW BLOCK BB56 Setting BB55 as the predecessor for determining incoming variable registers of BB56 DefList: { } N1479 (???,???) [001434] ------------ * IL_OFFSET void IL offset: 0x2cf REG NA DefList: { } N1481 ( 1, 1) [000151] ------------ * LCL_VAR ref V05 loc1 u:1 NA (last use) REG NA DefList: { } N1483 (???,???) [001495] ------------ * PUTARG_REG ref REG rdx BB56 regmask=[rdx] minReg=1> LCL_VAR BB56 regmask=[rdx] minReg=1 last fixed> Interval 219: ref RefPositions {} physReg:NA Preferences=[allInt] BB56 regmask=[rdx] minReg=1> PUTARG_REG BB56 regmask=[rdx] minReg=1 fixed> DefList: { N1483.t1495. PUTARG_REG } N1485 ( 2, 10) [000152] H------N---- * CNS_INT(h) long 0xd1ffab1e class REG NA $62 Interval 220: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB56 regmask=[allInt] minReg=1> DefList: { N1483.t1495. PUTARG_REG; N1485.t152. CNS_INT } N1487 (???,???) [001496] ------------ * PUTARG_REG long REG rcx BB56 regmask=[rcx] minReg=1> BB56 regmask=[rcx] minReg=1 last fixed> Interval 221: long RefPositions {} physReg:NA Preferences=[allInt] BB56 regmask=[rcx] minReg=1> PUTARG_REG BB56 regmask=[rcx] minReg=1 fixed> DefList: { N1483.t1495. PUTARG_REG; N1487.t1496. PUTARG_REG } N1489 ( 17, 18) [000153] --C-G------- * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS REG NA BB56 regmask=[rdx] minReg=1> BB56 regmask=[rdx] minReg=1 last fixed> BB56 regmask=[rcx] minReg=1> BB56 regmask=[rcx] minReg=1 last fixed> BB56 regmask=[rax] minReg=1> BB56 regmask=[rcx] minReg=1> BB56 regmask=[rdx] minReg=1> BB56 regmask=[r8] minReg=1> BB56 regmask=[r9] minReg=1> BB56 regmask=[r10] minReg=1> BB56 regmask=[r11] minReg=1> Interval 222: ref RefPositions {} physReg:NA Preferences=[allInt] BB56 regmask=[rax] minReg=1> CALL BB56 regmask=[rax] minReg=1 fixed> DefList: { N1489.t153. CALL } N1491 ( 1, 1) [000154] -c---------- * CNS_INT ref null REG NA $VN.Null Contained DefList: { N1489.t153. CALL } N1493 ( 19, 20) [000155] J---G--N---- * EQ void REG NA BB56 regmask=[allInt] minReg=1 last> DefList: { } N1495 ( 21, 22) [000156] ----G------- * JTRUE void REG NA CHECKING LAST USES for BB56, liveout={V00 V04} ============================== Reporting this as generic context: referenced use: {V05} def: {} NEW BLOCK BB57 Setting BB56 as the predecessor for determining incoming variable registers of BB57 DefList: { } N1499 (???,???) [001435] ------------ * IL_OFFSET void IL offset: 0x2d7 REG NA DefList: { } N1501 ( 1, 1) [000158] ------------ * LCL_VAR ref V04 loc0 u:2 NA (last use) REG NA $684 DefList: { } N1503 (???,???) [001454] -c---------- * LEA(b+8) ref REG NA Contained DefList: { } N1505 ( 3, 3) [000159] ---X-------- * IND int REG NA $73d LCL_VAR BB57 regmask=[allInt] minReg=1 last> Interval 223: int RefPositions {} physReg:NA Preferences=[allInt] IND BB57 regmask=[allInt] minReg=1> DefList: { N1505.t159. IND } N1507 (???,???) [001497] ---X-------- * PUTARG_REG int REG rdx BB57 regmask=[rdx] minReg=1> BB57 regmask=[rdx] minReg=1 last fixed> Interval 224: int RefPositions {} physReg:NA Preferences=[allInt] BB57 regmask=[rdx] minReg=1> PUTARG_REG BB57 regmask=[rdx] minReg=1 fixed> DefList: { N1507.t1497. PUTARG_REG } N1509 ( 1, 1) [000157] ------------ * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { N1507.t1497. PUTARG_REG } N1511 (???,???) [001498] ------------ * PUTARG_REG ref REG rcx BB57 regmask=[rcx] minReg=1> LCL_VAR BB57 regmask=[rcx] minReg=1 last fixed> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 225: ref RefPositions {} physReg:NA Preferences=[allInt] BB57 regmask=[rcx] minReg=1> PUTARG_REG BB57 regmask=[rcx] minReg=1 fixed> Assigning related to DefList: { N1507.t1497. PUTARG_REG; N1511.t1498. PUTARG_REG } N1513 ( 1, 1) [000160] ------------ * CNS_INT int 1 REG NA $c1 Interval 226: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB57 regmask=[allInt] minReg=1> DefList: { N1507.t1497. PUTARG_REG; N1511.t1498. PUTARG_REG; N1513.t160. CNS_INT } N1515 (???,???) [001499] ------------ * PUTARG_REG int REG r8 BB57 regmask=[r8] minReg=1> BB57 regmask=[r8] minReg=1 last fixed> Interval 227: int RefPositions {} physReg:NA Preferences=[allInt] BB57 regmask=[r8] minReg=1> PUTARG_REG BB57 regmask=[r8] minReg=1 fixed> DefList: { N1507.t1497. PUTARG_REG; N1511.t1498. PUTARG_REG; N1515.t1499. PUTARG_REG } N1517 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize REG NA $VN.Void BB57 regmask=[rdx] minReg=1> BB57 regmask=[rdx] minReg=1 last fixed> BB57 regmask=[rcx] minReg=1> BB57 regmask=[rcx] minReg=1 last fixed> BB57 regmask=[r8] minReg=1> BB57 regmask=[r8] minReg=1 last fixed> BB57 regmask=[rax] minReg=1> BB57 regmask=[rcx] minReg=1> BB57 regmask=[rdx] minReg=1> BB57 regmask=[r8] minReg=1> BB57 regmask=[r9] minReg=1> BB57 regmask=[r10] minReg=1> BB57 regmask=[r11] minReg=1> CHECKING LAST USES for BB57, liveout={V00} ============================== Reporting this as generic context: referenced use: {V00 V04} def: {} NEW BLOCK BB58 Setting BB29 as the predecessor for determining incoming variable registers of BB58 DefList: { } N1521 ( 1, 1) [000482] ------------ * CNS_INT int 1 REG NA $c1 Interval 228: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB58 regmask=[allInt] minReg=1> DefList: { N1521.t482. CNS_INT } N1523 ( 2, 2) [000810] ------------ * RETURN int REG NA $1f4 BB58 regmask=[rax] minReg=1> BB58 regmask=[rax] minReg=1 last fixed> CHECKING LAST USES for BB58, liveout={V00} ============================== Reporting this as generic context: referenced use: {} def: {} NEW BLOCK BB59 Setting BB01 as the predecessor for determining incoming variable registers of BB59 firstColdLoc = 1527 DefList: { } N1527 (???,???) [001436] ------------ * IL_OFFSET void IL offset: 0x8 REG NA DefList: { } N1529 ( 1, 1) [000532] ------------ * CNS_INT int 4 REG NA $c5 Interval 229: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB59 regmask=[allInt] minReg=1> DefList: { N1529.t532. CNS_INT } N1531 (???,???) [001500] ------------ * PUTARG_REG int REG rcx BB59 regmask=[rcx] minReg=1> BB59 regmask=[rcx] minReg=1 last fixed> Interval 230: int RefPositions {} physReg:NA Preferences=[allInt] BB59 regmask=[rcx] minReg=1> PUTARG_REG BB59 regmask=[rcx] minReg=1 fixed> DefList: { N1531.t1500. PUTARG_REG } N1533 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException REG NA $VN.Void BB59 regmask=[rcx] minReg=1> BB59 regmask=[rcx] minReg=1 last fixed> BB59 regmask=[rax] minReg=1> BB59 regmask=[rcx] minReg=1> BB59 regmask=[rdx] minReg=1> BB59 regmask=[r8] minReg=1> BB59 regmask=[r9] minReg=1> BB59 regmask=[r10] minReg=1> BB59 regmask=[r11] minReg=1> CHECKING LAST USES for BB59, liveout={V00} ============================== Reporting this as generic context: referenced use: {} def: {} NEW BLOCK BB60 Setting BB30 as the predecessor for determining incoming variable registers of BB60 DefList: { } N1537 (???,???) [001437] ------------ * IL_OFFSET void IL offset: 0x14f REG NA DefList: { } N1539 ( 1, 1) [000441] !----------- * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N1541 ( 3, 2) [000442] #----O------ * IND long REG NA $2e8 LCL_VAR BB60 regmask=[allInt] minReg=1 last> Interval 231: long RefPositions {} physReg:NA Preferences=[allInt] IND BB60 regmask=[allInt] minReg=1> DefList: { N1541.t442. IND } N1543 ( 7, 5) [000444] DA---O------ * STORE_LCL_VAR long V26 tmp12 d:1 NA REG NA BB60 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB60 regmask=[allInt] minReg=1 last> DefList: { } N1545 ( 3, 2) [000446] ------------ * LCL_VAR long V26 tmp12 u:1 NA REG NA $2e7 DefList: { } N1547 ( 4, 3) [000448] -c---------- * LEA(b+56) long REG NA Contained DefList: { } N1549 ( 6, 5) [000449] #----------- * IND long REG NA $2e9 LCL_VAR BB60 regmask=[allInt] minReg=1 last> Interval 232: long RefPositions {} physReg:NA Preferences=[allInt] IND BB60 regmask=[allInt] minReg=1> DefList: { N1549.t449. IND } N1551 ( 9, 7) [000450] #----------- * IND long REG NA $2ea BB60 regmask=[allInt] minReg=1 last> Interval 233: long RefPositions {} physReg:NA Preferences=[allInt] IND BB60 regmask=[allInt] minReg=1> DefList: { N1551.t450. IND } N1553 ( 10, 8) [000452] -c---------- * LEA(b+56) long REG NA Contained DefList: { N1551.t450. IND } N1555 ( 12, 10) [000456] nc---------- * IND long REG NA Contained DefList: { N1551.t450. IND } N1557 ( 1, 1) [000459] -c---------- * CNS_INT long 0 REG NA $243 Contained DefList: { N1551.t450. IND } N1559 ( 14, 12) [000460] J------N---- * EQ void REG NA BB60 regmask=[allInt] minReg=1 last> DefList: { } N1561 ( 16, 14) [001158] ------------ * JTRUE void REG NA CHECKING LAST USES for BB60, liveout={V00 V01 V26} ============================== Reporting this as generic context: referenced use: {V00} def: {V26} NEW BLOCK BB61 Setting BB60 as the predecessor for determining incoming variable registers of BB61 DefList: { } N1565 ( 3, 2) [000466] ------?----- * LCL_VAR long V26 tmp12 u:1 NA (last use) REG NA $2e7 DefList: { } N1567 ( 4, 3) [000465] -c----?----- * LEA(b+56) long REG NA Contained DefList: { } N1569 ( 6, 5) [000464] #-----?----- * IND long REG NA $2e9 LCL_VAR BB61 regmask=[allInt] minReg=1 last> Interval 234: long RefPositions {} physReg:NA Preferences=[allInt] IND BB61 regmask=[allInt] minReg=1> DefList: { N1569.t464. IND } N1571 ( 9, 7) [000463] #-----?----- * IND long REG NA $2ea BB61 regmask=[allInt] minReg=1 last> Interval 235: long RefPositions {} physReg:NA Preferences=[allInt] IND BB61 regmask=[allInt] minReg=1> DefList: { N1571.t463. IND } N1573 ( 10, 8) [000462] -c----?----- * LEA(b+56) long REG NA Contained DefList: { N1571.t463. IND } N1575 ( 12, 10) [000461] n-----?----- * IND long REG NA BB61 regmask=[allInt] minReg=1 last> Interval 236: long RefPositions {} physReg:NA Preferences=[allInt] IND BB61 regmask=[allInt] minReg=1> DefList: { N1575.t461. IND } N1577 ( 16, 13) [001160] DA---------- * STORE_LCL_VAR long V28 tmp14 d:3 NA REG NA BB61 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB61 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB61, liveout={V00 V01 V28} ============================== Reporting this as generic context: referenced use: {V26} def: {V28} NEW BLOCK BB62 Setting BB60 as the predecessor for determining incoming variable registers of BB62 DefList: { } N1581 ( 3, 2) [000445] ------?----- * LCL_VAR long V26 tmp12 u:1 NA (last use) REG NA $2e7 DefList: { } N1583 (???,???) [001501] ------------ * PUTARG_REG long REG rcx BB62 regmask=[rcx] minReg=1> LCL_VAR BB62 regmask=[rcx] minReg=1 last fixed> Interval 237: long RefPositions {} physReg:NA Preferences=[allInt] BB62 regmask=[rcx] minReg=1> PUTARG_REG BB62 regmask=[rcx] minReg=1 fixed> DefList: { N1583.t1501. PUTARG_REG } N1585 ( 2, 10) [000457] H-----?----- * CNS_INT(h) long 0xd1ffab1e global ptr REG NA $52 Interval 238: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB62 regmask=[allInt] minReg=1> DefList: { N1583.t1501. PUTARG_REG; N1585.t457. CNS_INT } N1587 (???,???) [001502] ------------ * PUTARG_REG long REG rdx BB62 regmask=[rdx] minReg=1> BB62 regmask=[rdx] minReg=1 last fixed> Interval 239: long RefPositions {} physReg:NA Preferences=[allInt] BB62 regmask=[rdx] minReg=1> PUTARG_REG BB62 regmask=[rdx] minReg=1 fixed> DefList: { N1583.t1501. PUTARG_REG; N1587.t1502. PUTARG_REG } N1589 ( 19, 19) [000458] --C-G-?----- * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS REG NA $332 BB62 regmask=[rcx] minReg=1> BB62 regmask=[rcx] minReg=1 last fixed> BB62 regmask=[rdx] minReg=1> BB62 regmask=[rdx] minReg=1 last fixed> BB62 regmask=[rax] minReg=1> BB62 regmask=[rcx] minReg=1> BB62 regmask=[rdx] minReg=1> BB62 regmask=[r8] minReg=1> BB62 regmask=[r9] minReg=1> BB62 regmask=[r10] minReg=1> BB62 regmask=[r11] minReg=1> Interval 240: long RefPositions {} physReg:NA Preferences=[allInt] BB62 regmask=[rax] minReg=1> CALL BB62 regmask=[rax] minReg=1 fixed> DefList: { N1589.t458. CALL } N1591 ( 23, 22) [001162] DA--G------- * STORE_LCL_VAR long V28 tmp14 d:2 NA REG NA BB62 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB62 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB62, liveout={V00 V01 V28} ============================== Reporting this as generic context: referenced use: {V26} def: {V28} NEW BLOCK BB63 Setting BB61 as the predecessor for determining incoming variable registers of BB63 DefList: { } N1595 ( 3, 2) [000473] ------------ * LCL_VAR long V28 tmp14 u:1 NA (last use) REG NA $347 DefList: { } N1597 (???,???) [001503] ------------ * PUTARG_REG long REG rcx BB63 regmask=[rcx] minReg=1> LCL_VAR BB63 regmask=[rcx] minReg=1 last fixed> Interval 241: long RefPositions {} physReg:NA Preferences=[allInt] BB63 regmask=[rcx] minReg=1> PUTARG_REG BB63 regmask=[rcx] minReg=1 fixed> DefList: { N1597.t1503. PUTARG_REG } N1599 ( 1, 1) [000455] ------------ * LCL_VAR ref V01 arg1 u:1 NA (last use) REG NA $101 DefList: { N1597.t1503. PUTARG_REG } N1601 (???,???) [001504] ------------ * PUTARG_REG ref REG rdx BB63 regmask=[rdx] minReg=1> LCL_VAR BB63 regmask=[rdx] minReg=1 last fixed> Interval 242: ref RefPositions {} physReg:NA Preferences=[allInt] BB63 regmask=[rdx] minReg=1> PUTARG_REG BB63 regmask=[rdx] minReg=1 fixed> DefList: { N1597.t1503. PUTARG_REG; N1601.t1504. PUTARG_REG } N1603 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException REG NA $VN.Void BB63 regmask=[rcx] minReg=1> BB63 regmask=[rcx] minReg=1 last fixed> BB63 regmask=[rdx] minReg=1> BB63 regmask=[rdx] minReg=1 last fixed> BB63 regmask=[rax] minReg=1> BB63 regmask=[rcx] minReg=1> BB63 regmask=[rdx] minReg=1> BB63 regmask=[r8] minReg=1> BB63 regmask=[r9] minReg=1> BB63 regmask=[r10] minReg=1> BB63 regmask=[r11] minReg=1> CHECKING LAST USES for BB63, liveout={V00} ============================== Reporting this as generic context: referenced use: {V01 V28} def: {} NEW BLOCK BB64 Setting BB40 as the predecessor for determining incoming variable registers of BB64 DefList: { } N1607 (???,???) [001438] ------------ * IL_OFFSET void IL offset: 0x1bc REG NA DefList: { } N1609 ( 1, 1) [000296] !----------- * LCL_VAR ref V00 this u:1 NA REG NA $100 DefList: { } N1611 ( 3, 2) [000297] #----O------ * IND long REG NA $2e8 LCL_VAR BB64 regmask=[allInt] minReg=1 last> Interval 243: long RefPositions {} physReg:NA Preferences=[allInt] IND BB64 regmask=[allInt] minReg=1> DefList: { N1611.t297. IND } N1613 ( 7, 5) [000299] DA---O------ * STORE_LCL_VAR long V21 tmp7 d:1 NA REG NA BB64 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB64 regmask=[allInt] minReg=1 last> DefList: { } N1615 ( 3, 2) [000301] ------------ * LCL_VAR long V21 tmp7 u:1 NA REG NA $2e7 DefList: { } N1617 ( 4, 3) [000303] -c---------- * LEA(b+56) long REG NA Contained DefList: { } N1619 ( 6, 5) [000304] #----------- * IND long REG NA $2e9 LCL_VAR BB64 regmask=[allInt] minReg=1 last> Interval 244: long RefPositions {} physReg:NA Preferences=[allInt] IND BB64 regmask=[allInt] minReg=1> DefList: { N1619.t304. IND } N1621 ( 9, 7) [000305] #----------- * IND long REG NA $2ea BB64 regmask=[allInt] minReg=1 last> Interval 245: long RefPositions {} physReg:NA Preferences=[allInt] IND BB64 regmask=[allInt] minReg=1> DefList: { N1621.t305. IND } N1623 ( 10, 8) [000307] -c---------- * LEA(b+56) long REG NA Contained DefList: { N1621.t305. IND } N1625 ( 12, 10) [000311] nc---------- * IND long REG NA Contained DefList: { N1621.t305. IND } N1627 ( 1, 1) [000314] -c---------- * CNS_INT long 0 REG NA $243 Contained DefList: { N1621.t305. IND } N1629 ( 14, 12) [000315] J------N---- * EQ void REG NA BB64 regmask=[allInt] minReg=1 last> DefList: { } N1631 ( 16, 14) [001168] ------------ * JTRUE void REG NA CHECKING LAST USES for BB64, liveout={V00 V01 V21} ============================== Reporting this as generic context: referenced use: {V00} def: {V21} NEW BLOCK BB65 Setting BB64 as the predecessor for determining incoming variable registers of BB65 DefList: { } N1635 ( 3, 2) [000321] ------?----- * LCL_VAR long V21 tmp7 u:1 NA (last use) REG NA $2e7 DefList: { } N1637 ( 4, 3) [000320] -c----?----- * LEA(b+56) long REG NA Contained DefList: { } N1639 ( 6, 5) [000319] #-----?----- * IND long REG NA $2e9 LCL_VAR BB65 regmask=[allInt] minReg=1 last> Interval 246: long RefPositions {} physReg:NA Preferences=[allInt] IND BB65 regmask=[allInt] minReg=1> DefList: { N1639.t319. IND } N1641 ( 9, 7) [000318] #-----?----- * IND long REG NA $2ea BB65 regmask=[allInt] minReg=1 last> Interval 247: long RefPositions {} physReg:NA Preferences=[allInt] IND BB65 regmask=[allInt] minReg=1> DefList: { N1641.t318. IND } N1643 ( 10, 8) [000317] -c----?----- * LEA(b+56) long REG NA Contained DefList: { N1641.t318. IND } N1645 ( 12, 10) [000316] n-----?----- * IND long REG NA BB65 regmask=[allInt] minReg=1 last> Interval 248: long RefPositions {} physReg:NA Preferences=[allInt] IND BB65 regmask=[allInt] minReg=1> DefList: { N1645.t316. IND } N1647 ( 16, 13) [001170] DA---------- * STORE_LCL_VAR long V23 tmp9 d:3 NA REG NA BB65 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB65 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB65, liveout={V00 V01 V23} ============================== Reporting this as generic context: referenced use: {V21} def: {V23} NEW BLOCK BB66 Setting BB64 as the predecessor for determining incoming variable registers of BB66 DefList: { } N1651 ( 3, 2) [000300] ------?----- * LCL_VAR long V21 tmp7 u:1 NA (last use) REG NA $2e7 DefList: { } N1653 (???,???) [001505] ------------ * PUTARG_REG long REG rcx BB66 regmask=[rcx] minReg=1> LCL_VAR BB66 regmask=[rcx] minReg=1 last fixed> Interval 249: long RefPositions {} physReg:NA Preferences=[allInt] BB66 regmask=[rcx] minReg=1> PUTARG_REG BB66 regmask=[rcx] minReg=1 fixed> DefList: { N1653.t1505. PUTARG_REG } N1655 ( 2, 10) [000312] H-----?----- * CNS_INT(h) long 0xd1ffab1e global ptr REG NA $52 Interval 250: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB66 regmask=[allInt] minReg=1> DefList: { N1653.t1505. PUTARG_REG; N1655.t312. CNS_INT } N1657 (???,???) [001506] ------------ * PUTARG_REG long REG rdx BB66 regmask=[rdx] minReg=1> BB66 regmask=[rdx] minReg=1 last fixed> Interval 251: long RefPositions {} physReg:NA Preferences=[allInt] BB66 regmask=[rdx] minReg=1> PUTARG_REG BB66 regmask=[rdx] minReg=1 fixed> DefList: { N1653.t1505. PUTARG_REG; N1657.t1506. PUTARG_REG } N1659 ( 19, 19) [000313] --C-G-?----- * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS REG NA $332 BB66 regmask=[rcx] minReg=1> BB66 regmask=[rcx] minReg=1 last fixed> BB66 regmask=[rdx] minReg=1> BB66 regmask=[rdx] minReg=1 last fixed> BB66 regmask=[rax] minReg=1> BB66 regmask=[rcx] minReg=1> BB66 regmask=[rdx] minReg=1> BB66 regmask=[r8] minReg=1> BB66 regmask=[r9] minReg=1> BB66 regmask=[r10] minReg=1> BB66 regmask=[r11] minReg=1> Interval 252: long RefPositions {} physReg:NA Preferences=[allInt] BB66 regmask=[rax] minReg=1> CALL BB66 regmask=[rax] minReg=1 fixed> DefList: { N1659.t313. CALL } N1661 ( 23, 22) [001172] DA--G------- * STORE_LCL_VAR long V23 tmp9 d:2 NA REG NA BB66 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB66 regmask=[allInt] minReg=1 last> CHECKING LAST USES for BB66, liveout={V00 V01 V23} ============================== Reporting this as generic context: referenced use: {V21} def: {V23} NEW BLOCK BB67 Setting BB65 as the predecessor for determining incoming variable registers of BB67 DefList: { } N1665 ( 3, 2) [000328] ------------ * LCL_VAR long V23 tmp9 u:1 NA (last use) REG NA $34b DefList: { } N1667 (???,???) [001507] ------------ * PUTARG_REG long REG rcx BB67 regmask=[rcx] minReg=1> LCL_VAR BB67 regmask=[rcx] minReg=1 last fixed> Interval 253: long RefPositions {} physReg:NA Preferences=[allInt] BB67 regmask=[rcx] minReg=1> PUTARG_REG BB67 regmask=[rcx] minReg=1 fixed> DefList: { N1667.t1507. PUTARG_REG } N1669 ( 1, 1) [000310] ------------ * LCL_VAR ref V01 arg1 u:1 NA (last use) REG NA $101 DefList: { N1667.t1507. PUTARG_REG } N1671 (???,???) [001508] ------------ * PUTARG_REG ref REG rdx BB67 regmask=[rdx] minReg=1> LCL_VAR BB67 regmask=[rdx] minReg=1 last fixed> Interval 254: ref RefPositions {} physReg:NA Preferences=[allInt] BB67 regmask=[rdx] minReg=1> PUTARG_REG BB67 regmask=[rdx] minReg=1 fixed> DefList: { N1667.t1507. PUTARG_REG; N1671.t1508. PUTARG_REG } N1673 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException REG NA $VN.Void BB67 regmask=[rcx] minReg=1> BB67 regmask=[rcx] minReg=1 last fixed> BB67 regmask=[rdx] minReg=1> BB67 regmask=[rdx] minReg=1 last fixed> BB67 regmask=[rax] minReg=1> BB67 regmask=[rcx] minReg=1> BB67 regmask=[rdx] minReg=1> BB67 regmask=[r8] minReg=1> BB67 regmask=[r9] minReg=1> BB67 regmask=[r10] minReg=1> BB67 regmask=[r11] minReg=1> CHECKING LAST USES for BB67, liveout={V00} ============================== Reporting this as generic context: referenced use: {V01 V23} def: {} NEW BLOCK BB68 Setting BB26 as the predecessor for determining incoming variable registers of BB68 DefList: { } N1677 (???,???) [001439] ------------ * IL_OFFSET void IL offset: 0x1dd REG NA DefList: { } N1679 ( 14, 5) [000233] --CXG------- * CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported REG NA $VN.Void BB68 regmask=[rax] minReg=1> BB68 regmask=[rcx] minReg=1> BB68 regmask=[rdx] minReg=1> BB68 regmask=[r8] minReg=1> BB68 regmask=[r9] minReg=1> BB68 regmask=[r10] minReg=1> BB68 regmask=[r11] minReg=1> CHECKING LAST USES for BB68, liveout={V00} ============================== Reporting this as generic context: referenced use: {} def: {} NEW BLOCK BB69 No predecessor; - throw block; Creating dummy definitions BB69 regmask=[allInt] minReg=1 last> Finished creating dummy definitions DefList: { } N1683 ( 14, 5) [001444] --CXG------- * CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL REG NA BB69 regmask=[rax] minReg=1> BB69 regmask=[rcx] minReg=1> BB69 regmask=[rdx] minReg=1> BB69 regmask=[r8] minReg=1> BB69 regmask=[r9] minReg=1> BB69 regmask=[r10] minReg=1> BB69 regmask=[r11] minReg=1> Exposed uses: BB69 regmask=[allInt] minReg=1> V00 CHECKING LAST USES for BB69, liveout={V00} ============================== Reporting this as generic context: referenced use: {} def: {} Reporting this as generic context: referenced Adding exposed use of this, for lvaKeepAliveAndReportThis BB69 regmask=[allInt] minReg=1> Linear scan intervals BEFORE VALIDATING INTERVALS: Interval 0: (V00) ref RefPositions {#0@0 #7@25 #10@33 #32@53 #65@103 #100@157 #106@177 #207@287 #215@307 #322@489 #514@789 #631@949 #633@961 #685@1051 #702@1081 #704@1099 #706@1109 #737@1145 #758@1159 #768@1183 #872@1353 #874@1361 #938@1465 #972@1511 #1013@1541 #1077@1611 #1148@1681 #1157@1685 #1158@1685} physReg:rcx Preferences=[rbx rbp rsi rdi r12-r15] Interval 1: (V01) ref RefPositions {#1@0 #5@9 #157@235 #180@251 #183@255 #415@619 #569@851 #901@1425 #1062@1601 #1126@1671} physReg:rdx Preferences=[rbx rbp rsi rdi r12-r15] Interval 2: (V02) ref RefPositions {#3@0 #467@697 #599@887 #920@1435} physReg:r8 Preferences=[rbx rbp rsi rdi r12-r15] Interval 3: (V03) int RefPositions {#2@0 #460@683 #482@707 #592@873 #614@897 #629@937} physReg:r9 Preferences=[rbx rbp rsi rdi r12-r15] Interval 4: (V04) ref RefPositions {#68@106 #69@113 #382@553 #395@583 #403@609 #452@675 #488@725 #501@755 #509@781 #647@993 #695@1073 #877@1364 #880@1377 #885@1389 #965@1505} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 5: (V05) ref RefPositions {#103@160 #104@167 #149@227 #320@479 #456@675 #557@839 #942@1483} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 6: (V06) int RefPositions {#203@274 #247@361 #268@393 #401@595 #454@675 #507@767 #800@1237 #821@1269 #891@1401} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 7: (V07) int RefPositions {#206@280 #444@659 #447@662 #449@669 #451@675 #621@921 #624@924 #626@931 #939@1473} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 8: (V08) byref RefPositions {#313@460 #314@465 #458@675 #866@1332 #892@1407 #936@1447} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 9: (V09) int RefPositions {#319@472 #387@561 #389@573 #443@652 #453@675 #493@733 #495@745 #620@914 #628@937} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 10: (V10) int RefPositions {#638@968 #869@1340 #870@1347 #879@1377 #881@1383 #934@1443} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 11: (V11) byref RefPositions {#889@1392 #890@1401 #896@1417 #899@1425 #915@1431} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 12: (V12) ref RefPositions {#380@544 #411@615 #418@623 #457@675} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 13: (V13) int RefPositions {#711@1116 #713@1123 #868@1339} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 14: (V15) int RefPositions {#177@244 #200@268 #202@273} physReg:NA Preferences=[allInt] RelatedInterval Interval 15: (V16) long RefPositions {#517@792 #518@797 #532@825} physReg:NA Preferences=[rcx] Interval 16: (V17) ref RefPositions {#513@784 #565@847} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 17: (V19) long RefPositions {#529@820 #554@834 #561@843 #580@857} physReg:NA Preferences=[r11] Interval 18: (V21) long RefPositions {#1080@1614 #1081@1619 #1087@1639 #1097@1653} physReg:NA Preferences=[rcx] Interval 19: (V23) long RefPositions {#1094@1648 #1119@1662 #1122@1667} physReg:NA Preferences=[rcx] Interval 20: (V24) long RefPositions {#325@492 #326@497 #340@525} physReg:NA Preferences=[rcx] Interval 21: (V25) long RefPositions {#337@520 #362@534 #365@539} physReg:NA Preferences=[rcx] Interval 22: (V26) long RefPositions {#1016@1544 #1017@1549 #1023@1569 #1033@1583} physReg:NA Preferences=[rcx] Interval 23: (V28) long RefPositions {#1030@1578 #1055@1592 #1058@1597} physReg:NA Preferences=[rcx] Interval 24: (V29) long RefPositions {#109@180 #110@185 #124@213} physReg:NA Preferences=[rcx] Interval 25: (V31) long RefPositions {#121@208 #146@222 #153@231 #166@241} physReg:NA Preferences=[r11] Interval 26: (V33) int RefPositions {#35@56 #43@77} physReg:NA Preferences=[allInt] Interval 27: (V35) ref RefPositions {#42@70 #46@87 #50@91} physReg:NA Preferences=[rcx rdx] Interval 28: (V36) int RefPositions {#72@116 #75@129} physReg:NA Preferences=[allInt] Interval 29: (V37) ref RefPositions {#74@122 #85@145} physReg:NA Preferences=[rdx] Interval 30: (V38) byref RefPositions {#311@456 #312@459} physReg:NA Preferences=[allInt] RelatedInterval Interval 31: (V39) ref RefPositions {#210@290 #211@297 #304@445 #307@453} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 32: (V40) int RefPositions {#214@300 #219@317 #256@375 #269@393} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 33: (V41) long RefPositions {#218@310 #249@363} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 34: (V42) int RefPositions {#266@386 #275@397 #303@445 #305@451} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 35: (V43) int RefPositions {#222@320 #225@335} physReg:NA Preferences=[allInt] Interval 36: (V45) ref RefPositions {#224@328 #228@345 #232@349} physReg:NA Preferences=[rcx rdx] Interval 37: (V46) int RefPositions {#278@400 #281@415} physReg:NA Preferences=[allInt] Interval 38: (V48) ref RefPositions {#280@408 #284@425 #288@429} physReg:NA Preferences=[rcx rdx] Interval 39: (V49) int RefPositions {#657@1006 #660@1019} physReg:NA Preferences=[allInt] Interval 40: (V50) ref RefPositions {#659@1012 #670@1035} physReg:NA Preferences=[rdx] Interval 41: (V51) byref RefPositions {#864@1328 #865@1331} physReg:NA Preferences=[allInt] RelatedInterval Interval 42: (V52) ref RefPositions {#761@1162 #762@1169 #860@1325} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 43: (V53) int RefPositions {#767@1176 #772@1193 #809@1251 #822@1269} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 44: (V54) long RefPositions {#771@1186 #802@1239} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 45: (V55) int RefPositions {#819@1262 #828@1273 #856@1317 #858@1323} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 46: (V56) int RefPositions {#775@1196 #778@1211} physReg:NA Preferences=[allInt] Interval 47: (V58) ref RefPositions {#777@1204 #781@1221 #785@1225} physReg:NA Preferences=[rcx rdx] Interval 48: (V59) int RefPositions {#831@1276 #834@1291} physReg:NA Preferences=[allInt] Interval 49: (V61) ref RefPositions {#833@1284 #837@1301 #841@1305} physReg:NA Preferences=[rcx rdx] Interval 50: (V62) int RefPositions {#640@974 #641@979 #643@985} physReg:NA Preferences=[allInt] Interval 51: (V63) int RefPositions {#688@1054 #689@1059 #691@1065} physReg:NA Preferences=[allInt] Interval 52: (V64) int RefPositions {#731@1138 #733@1141} physReg:NA Preferences=[rdx] Interval 53: (V65) byref RefPositions {#399@586 #400@595 #440@649 #462@693} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 54: (V66) byref RefPositions {#505@758 #506@767 #594@883 #617@911} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 55: (V67) long RefPositions {#525@806 #526@811 #528@819} physReg:NA Preferences=[allInt] RelatedInterval Interval 56: (V68) long RefPositions {#117@194 #118@199 #120@207} physReg:NA Preferences=[allInt] RelatedInterval Interval 57: (V69) long RefPositions {#333@506 #334@511 #336@519} physReg:NA Preferences=[allInt] RelatedInterval Interval 58: (V70) long RefPositions {#394@580 #396@583 #404@609} physReg:NA Preferences=[allInt] Interval 59: (V71) long RefPositions {#500@752 #502@755 #510@781} physReg:NA Preferences=[allInt] Interval 60: (V72) int RefPositions {#765@1172 #766@1175 #857@1317} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 61: (V73) ref RefPositions {#40@64 #41@69 #73@121 #223@327 #279@407 #455@675 #658@1011 #776@1203 #832@1283} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 62: (V74) int RefPositions {#636@964 #637@967 #639@973} physReg:NA Preferences=[allInt] RelatedInterval Interval 63: (V75) int RefPositions {#709@1112 #710@1115 #716@1133} physReg:NA Preferences=[rcx] Interval 64: (V76) int RefPositions {#385@556 #386@561 #448@669 #491@728 #492@733 #625@931 #642@979 #690@1059 #712@1123} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 65: ref (specialPutArg) RefPositions {#12@34 #19@39} physReg:NA Preferences=[rcx] RelatedInterval Interval 66: int (constant) RefPositions {#13@36 #15@37} physReg:NA Preferences=[rdx] Interval 67: int RefPositions {#17@38 #21@39} physReg:NA Preferences=[rdx] Interval 68: int RefPositions {#30@40} physReg:NA Preferences=[rax] Interval 69: int RefPositions {#33@54 #34@55} physReg:NA Preferences=[allInt] RelatedInterval Interval 70: long (constant) RefPositions {#36@60 #37@61} physReg:NA Preferences=[allInt] Interval 71: ref RefPositions {#38@62 #39@63} physReg:NA Preferences=[allInt] RelatedInterval Interval 72: ref (specialPutArg) RefPositions {#48@88 #54@93} physReg:NA Preferences=[rcx] RelatedInterval Interval 73: ref RefPositions {#52@92 #56@93} physReg:NA Preferences=[rdx] Interval 74: ref RefPositions {#66@104 #67@105} physReg:NA Preferences=[allInt] RelatedInterval Interval 75: int RefPositions {#70@114 #71@115} physReg:NA Preferences=[allInt] RelatedInterval Interval 76: long (constant) RefPositions {#77@138 #78@139} physReg:NA Preferences=[allInt] Interval 77: ref RefPositions {#79@140 #81@141} physReg:NA Preferences=[rcx] Interval 78: ref RefPositions {#83@142 #89@147} physReg:NA Preferences=[rcx] Interval 79: ref RefPositions {#87@146 #91@147} physReg:NA Preferences=[rdx] Interval 80: ref RefPositions {#101@158 #102@159} physReg:NA Preferences=[allInt] RelatedInterval Interval 81: long RefPositions {#107@178 #108@179} physReg:NA Preferences=[allInt] RelatedInterval Interval 82: long RefPositions {#111@186 #112@187} physReg:NA Preferences=[allInt] Interval 83: long RefPositions {#113@188 #114@191} physReg:NA Preferences=[allInt] Interval 84: long RefPositions {#115@192 #116@193} physReg:NA Preferences=[allInt] RelatedInterval Interval 85: long RefPositions {#126@214 #133@219} physReg:NA Preferences=[rcx] Interval 86: long (constant) RefPositions {#127@216 #129@217} physReg:NA Preferences=[rdx] Interval 87: long RefPositions {#131@218 #135@219} physReg:NA Preferences=[rdx] Interval 88: long RefPositions {#144@220 #145@221} physReg:NA Preferences=[rax] RelatedInterval Interval 89: ref (specialPutArg) RefPositions {#151@228 #161@241} physReg:NA Preferences=[rcx] RelatedInterval Interval 90: long (specialPutArg) RefPositions {#155@232 #163@241} physReg:NA Preferences=[r11] RelatedInterval Interval 91: ref (specialPutArg) RefPositions {#159@236 #165@241} physReg:NA Preferences=[rdx] RelatedInterval Interval 92: int RefPositions {#175@242 #176@243} physReg:NA Preferences=[rax] RelatedInterval Interval 93: ref (specialPutArg) RefPositions {#182@252 #188@265} physReg:NA Preferences=[rcx] RelatedInterval Interval 94: long RefPositions {#184@256 #185@259} physReg:NA Preferences=[allInt] Interval 95: long RefPositions {#186@260 #189@265} physReg:NA Preferences=[allInt] Interval 96: int RefPositions {#198@266 #199@267} physReg:NA Preferences=[rax] RelatedInterval Interval 97: int (constant) RefPositions {#204@278 #205@279} physReg:NA Preferences=[allInt] RelatedInterval Interval 98: ref RefPositions {#208@288 #209@289} physReg:NA Preferences=[allInt] RelatedInterval Interval 99: int RefPositions {#212@298 #213@299} physReg:NA Preferences=[allInt] RelatedInterval Interval 100: long RefPositions {#216@308 #217@309} physReg:NA Preferences=[allInt] RelatedInterval Interval 101: int RefPositions {#220@318 #221@319} physReg:NA Preferences=[allInt] RelatedInterval Interval 102: ref (specialPutArg) RefPositions {#230@346 #236@351} physReg:NA Preferences=[rcx] RelatedInterval Interval 103: ref RefPositions {#234@350 #238@351} physReg:NA Preferences=[rdx] Interval 104: long RefPositions {#248@362 #250@363} physReg:NA Preferences=[allInt] RelatedInterval Interval 105: long RefPositions {#251@364 #252@367} physReg:NA Preferences=[allInt] RelatedInterval Interval 106: long RefPositions {#253@368 #254@371} physReg:NA Preferences=[allInt] RelatedInterval Interval 107: long RefPositions {#255@372 #258@377} physReg:NA Preferences=[allInt] RelatedInterval Interval 108: long RefPositions {#257@376 #259@377} physReg:NA Preferences=[allInt] RelatedInterval Interval 109: long RefPositions {#260@378 #261@381} physReg:NA Preferences=[allInt] RelatedInterval Interval 110: long RefPositions {#262@382 #263@383} physReg:NA Preferences=[allInt] Interval 111: int RefPositions {#264@384 #265@385} physReg:NA Preferences=[allInt] RelatedInterval Interval 112: int (interfering uses) RefPositions {#273@394 #274@397} physReg:NA Preferences=[rdx] Interval 113: int RefPositions {#276@398 #277@399} physReg:NA Preferences=[allInt] RelatedInterval Interval 114: ref (specialPutArg) RefPositions {#286@426 #292@431} physReg:NA Preferences=[rcx] RelatedInterval Interval 115: ref RefPositions {#290@430 #294@431} physReg:NA Preferences=[rdx] Interval 116: long RefPositions {#306@452 #308@453} physReg:NA Preferences=[allInt] Interval 117: byref RefPositions {#309@454 #310@455} physReg:NA Preferences=[allInt] RelatedInterval Interval 118: int RefPositions {#315@466 #316@469} physReg:NA Preferences=[allInt] RelatedInterval Interval 119: int RefPositions {#317@470 #318@471} physReg:NA Preferences=[allInt] RelatedInterval Interval 120: long RefPositions {#323@490 #324@491} physReg:NA Preferences=[allInt] RelatedInterval Interval 121: long RefPositions {#327@498 #328@499} physReg:NA Preferences=[allInt] Interval 122: long RefPositions {#329@500 #330@503} physReg:NA Preferences=[allInt] Interval 123: long RefPositions {#331@504 #332@505} physReg:NA Preferences=[allInt] RelatedInterval Interval 124: long RefPositions {#342@526 #349@531} physReg:NA Preferences=[rcx] Interval 125: long (constant) RefPositions {#343@528 #345@529} physReg:NA Preferences=[rdx] Interval 126: long RefPositions {#347@530 #351@531} physReg:NA Preferences=[rdx] Interval 127: long RefPositions {#360@532 #361@533} physReg:NA Preferences=[rax] RelatedInterval Interval 128: long RefPositions {#367@540 #369@541} physReg:NA Preferences=[rcx] Interval 129: ref RefPositions {#378@542 #379@543} physReg:NA Preferences=[rax] RelatedInterval Interval 130: int RefPositions {#383@554 #384@555} physReg:NA Preferences=[allInt] RelatedInterval Interval 131: long RefPositions {#390@574 #391@577} physReg:NA Preferences=[allInt] Interval 132: long RefPositions {#392@578 #393@579} physReg:NA Preferences=[allInt] RelatedInterval Interval 133: byref RefPositions {#397@584 #398@585} physReg:NA Preferences=[allInt] RelatedInterval Interval 134: ref RefPositions {#405@610 #407@611} physReg:NA Preferences=[rdx] Interval 135: ref RefPositions {#409@612 #423@633} physReg:NA Preferences=[rdx] Interval 136: ref (specialPutArg) RefPositions {#413@616 #425@633} physReg:NA Preferences=[rcx] RelatedInterval Interval 137: ref (specialPutArg) RefPositions {#417@620 #427@633} physReg:NA Preferences=[r8] RelatedInterval Interval 138: long RefPositions {#419@624 #420@627} physReg:NA Preferences=[allInt] Interval 139: long RefPositions {#421@628 #428@633} physReg:NA Preferences=[allInt] Interval 140: int RefPositions {#437@634 #438@637} physReg:NA Preferences=[rax] Interval 141: int RefPositions {#441@650 #442@651} physReg:NA Preferences=[allInt] RelatedInterval Interval 142: int RefPositions {#445@660 #446@661} physReg:NA Preferences=[allInt] RelatedInterval Interval 143: byref RefPositions {#463@694 #465@697} physReg:NA Preferences=[rcx] Interval 144: int (constant) RefPositions {#484@714 #486@715} physReg:NA Preferences=[rax] Interval 145: int RefPositions {#489@726 #490@727} physReg:NA Preferences=[allInt] RelatedInterval Interval 146: long RefPositions {#496@746 #497@749} physReg:NA Preferences=[allInt] Interval 147: long RefPositions {#498@750 #499@751} physReg:NA Preferences=[allInt] RelatedInterval Interval 148: byref RefPositions {#503@756 #504@757} physReg:NA Preferences=[allInt] RelatedInterval Interval 149: ref RefPositions {#511@782 #512@783} physReg:NA Preferences=[allInt] RelatedInterval Interval 150: long RefPositions {#515@790 #516@791} physReg:NA Preferences=[allInt] RelatedInterval Interval 151: long RefPositions {#519@798 #520@799} physReg:NA Preferences=[allInt] Interval 152: long RefPositions {#521@800 #522@803} physReg:NA Preferences=[allInt] Interval 153: long RefPositions {#523@804 #524@805} physReg:NA Preferences=[allInt] RelatedInterval Interval 154: long RefPositions {#534@826 #541@831} physReg:NA Preferences=[rcx] Interval 155: long (constant) RefPositions {#535@828 #537@829} physReg:NA Preferences=[rdx] Interval 156: long RefPositions {#539@830 #543@831} physReg:NA Preferences=[rdx] Interval 157: long RefPositions {#552@832 #553@833} physReg:NA Preferences=[rax] RelatedInterval Interval 158: ref (specialPutArg) RefPositions {#559@840 #573@857} physReg:NA Preferences=[rcx] RelatedInterval Interval 159: long (specialPutArg) RefPositions {#563@844 #575@857} physReg:NA Preferences=[r11] RelatedInterval Interval 160: ref RefPositions {#567@848 #577@857} physReg:NA Preferences=[rdx] Interval 161: ref (specialPutArg) RefPositions {#571@852 #579@857} physReg:NA Preferences=[r8] RelatedInterval Interval 162: int RefPositions {#589@858 #590@861} physReg:NA Preferences=[rax] Interval 163: byref RefPositions {#595@884 #597@887} physReg:NA Preferences=[rcx] Interval 164: int RefPositions {#618@912 #619@913} physReg:NA Preferences=[allInt] RelatedInterval Interval 165: int RefPositions {#622@922 #623@923} physReg:NA Preferences=[allInt] RelatedInterval Interval 166: int RefPositions {#634@962 #635@963} physReg:NA Preferences=[allInt] RelatedInterval Interval 167: long RefPositions {#644@986 #645@989} physReg:NA Preferences=[allInt] Interval 168: long RefPositions {#646@990 #648@993} physReg:NA Preferences=[allInt] Interval 169: int RefPositions {#649@994 #650@995} physReg:NA Preferences=[allInt] Interval 170: int RefPositions {#651@996 #652@999} physReg:NA Preferences=[allInt] RelatedInterval Interval 171: int RefPositions {#653@1000 #654@1003} physReg:NA Preferences=[allInt] Interval 172: int RefPositions {#655@1004 #656@1005} physReg:NA Preferences=[allInt] RelatedInterval Interval 173: long (constant) RefPositions {#662@1028 #663@1029} physReg:NA Preferences=[allInt] Interval 174: ref RefPositions {#664@1030 #666@1031} physReg:NA Preferences=[rcx] Interval 175: ref RefPositions {#668@1032 #674@1037} physReg:NA Preferences=[rcx] Interval 176: ref RefPositions {#672@1036 #676@1037} physReg:NA Preferences=[rdx] Interval 177: int RefPositions {#686@1052 #687@1053} physReg:NA Preferences=[allInt] RelatedInterval Interval 178: long RefPositions {#692@1066 #693@1069} physReg:NA Preferences=[allInt] Interval 179: long RefPositions {#694@1070 #696@1073} physReg:NA Preferences=[allInt] Interval 180: int RefPositions {#697@1074 #698@1075} physReg:NA Preferences=[allInt] Interval 181: int RefPositions {#699@1076 #700@1079} physReg:NA Preferences=[allInt] RelatedInterval Interval 182: int RefPositions {#701@1080 #703@1081} physReg:NA Preferences=[allInt] Interval 183: int RefPositions {#707@1110 #708@1111} physReg:NA Preferences=[allInt] RelatedInterval Interval 184: int RefPositions {#718@1134 #720@1135} physReg:NA Preferences=[rcx] Interval 185: int RefPositions {#729@1136 #730@1137} physReg:NA Preferences=[rax] RelatedInterval Interval 186: int RefPositions {#735@1142 #746@1151} physReg:NA Preferences=[rdx] Interval 187: ref (specialPutArg) RefPositions {#739@1146 #748@1151} physReg:NA Preferences=[rcx] RelatedInterval Interval 188: int (constant) RefPositions {#740@1148 #742@1149} physReg:NA Preferences=[r8] Interval 189: int RefPositions {#744@1150 #750@1151} physReg:NA Preferences=[r8] Interval 190: ref RefPositions {#759@1160 #760@1161} physReg:NA Preferences=[allInt] RelatedInterval Interval 191: int RefPositions {#763@1170 #764@1171} physReg:NA Preferences=[allInt] RelatedInterval Interval 192: long RefPositions {#769@1184 #770@1185} physReg:NA Preferences=[allInt] RelatedInterval Interval 193: int RefPositions {#773@1194 #774@1195} physReg:NA Preferences=[allInt] RelatedInterval Interval 194: ref (specialPutArg) RefPositions {#783@1222 #789@1227} physReg:NA Preferences=[rcx] RelatedInterval Interval 195: ref RefPositions {#787@1226 #791@1227} physReg:NA Preferences=[rdx] Interval 196: long RefPositions {#801@1238 #803@1239} physReg:NA Preferences=[allInt] RelatedInterval Interval 197: long RefPositions {#804@1240 #805@1243} physReg:NA Preferences=[allInt] RelatedInterval Interval 198: long RefPositions {#806@1244 #807@1247} physReg:NA Preferences=[allInt] RelatedInterval Interval 199: long RefPositions {#808@1248 #811@1253} physReg:NA Preferences=[allInt] RelatedInterval Interval 200: long RefPositions {#810@1252 #812@1253} physReg:NA Preferences=[allInt] RelatedInterval Interval 201: long RefPositions {#813@1254 #814@1257} physReg:NA Preferences=[allInt] RelatedInterval Interval 202: long RefPositions {#815@1258 #816@1259} physReg:NA Preferences=[allInt] Interval 203: int RefPositions {#817@1260 #818@1261} physReg:NA Preferences=[allInt] RelatedInterval Interval 204: int (interfering uses) RefPositions {#826@1270 #827@1273} physReg:NA Preferences=[rdx] Interval 205: int RefPositions {#829@1274 #830@1275} physReg:NA Preferences=[allInt] RelatedInterval Interval 206: ref (specialPutArg) RefPositions {#839@1302 #845@1307} physReg:NA Preferences=[rcx] RelatedInterval Interval 207: ref RefPositions {#843@1306 #847@1307} physReg:NA Preferences=[rdx] Interval 208: long RefPositions {#859@1324 #861@1325} physReg:NA Preferences=[allInt] Interval 209: byref RefPositions {#862@1326 #863@1327} physReg:NA Preferences=[allInt] RelatedInterval Interval 210: int RefPositions {#871@1348 #873@1353} physReg:NA Preferences=[allInt] Interval 211: ref RefPositions {#875@1362 #876@1363} physReg:NA Preferences=[allInt] RelatedInterval Interval 212: long RefPositions {#882@1384 #883@1387} physReg:NA Preferences=[allInt] Interval 213: long RefPositions {#884@1388 #886@1389} physReg:NA Preferences=[allInt] Interval 214: byref RefPositions {#887@1390 #888@1391} physReg:NA Preferences=[allInt] RelatedInterval Interval 215: int RefPositions {#893@1408 #894@1411} physReg:NA Preferences=[allInt] RelatedInterval Interval 216: int RefPositions {#895@1412 #897@1417} physReg:NA Preferences=[allInt] Interval 217: byref RefPositions {#916@1432 #918@1435} physReg:NA Preferences=[rcx] Interval 218: int RefPositions {#935@1444 #937@1447} physReg:NA Preferences=[allInt] Interval 219: ref RefPositions {#944@1484 #951@1489} physReg:NA Preferences=[rdx] Interval 220: long (constant) RefPositions {#945@1486 #947@1487} physReg:NA Preferences=[rcx] Interval 221: long RefPositions {#949@1488 #953@1489} physReg:NA Preferences=[rcx] Interval 222: ref RefPositions {#962@1490 #963@1493} physReg:NA Preferences=[rax] Interval 223: int RefPositions {#966@1506 #968@1507} physReg:NA Preferences=[rdx] Interval 224: int RefPositions {#970@1508 #981@1517} physReg:NA Preferences=[rdx] Interval 225: ref (specialPutArg) RefPositions {#974@1512 #983@1517} physReg:NA Preferences=[rcx] RelatedInterval Interval 226: int (constant) RefPositions {#975@1514 #977@1515} physReg:NA Preferences=[r8] Interval 227: int RefPositions {#979@1516 #985@1517} physReg:NA Preferences=[r8] Interval 228: int (constant) RefPositions {#994@1522 #996@1523} physReg:NA Preferences=[rax] Interval 229: int (constant) RefPositions {#998@1530 #1000@1531} physReg:NA Preferences=[rcx] Interval 230: int RefPositions {#1002@1532 #1004@1533} physReg:NA Preferences=[rcx] Interval 231: long RefPositions {#1014@1542 #1015@1543} physReg:NA Preferences=[allInt] RelatedInterval Interval 232: long RefPositions {#1018@1550 #1019@1551} physReg:NA Preferences=[allInt] Interval 233: long RefPositions {#1020@1552 #1021@1559} physReg:NA Preferences=[allInt] Interval 234: long RefPositions {#1024@1570 #1025@1571} physReg:NA Preferences=[allInt] Interval 235: long RefPositions {#1026@1572 #1027@1575} physReg:NA Preferences=[allInt] Interval 236: long RefPositions {#1028@1576 #1029@1577} physReg:NA Preferences=[allInt] RelatedInterval Interval 237: long RefPositions {#1035@1584 #1042@1589} physReg:NA Preferences=[rcx] Interval 238: long (constant) RefPositions {#1036@1586 #1038@1587} physReg:NA Preferences=[rdx] Interval 239: long RefPositions {#1040@1588 #1044@1589} physReg:NA Preferences=[rdx] Interval 240: long RefPositions {#1053@1590 #1054@1591} physReg:NA Preferences=[rax] RelatedInterval Interval 241: long RefPositions {#1060@1598 #1066@1603} physReg:NA Preferences=[rcx] Interval 242: ref RefPositions {#1064@1602 #1068@1603} physReg:NA Preferences=[rdx] Interval 243: long RefPositions {#1078@1612 #1079@1613} physReg:NA Preferences=[allInt] RelatedInterval Interval 244: long RefPositions {#1082@1620 #1083@1621} physReg:NA Preferences=[allInt] Interval 245: long RefPositions {#1084@1622 #1085@1629} physReg:NA Preferences=[allInt] Interval 246: long RefPositions {#1088@1640 #1089@1641} physReg:NA Preferences=[allInt] Interval 247: long RefPositions {#1090@1642 #1091@1645} physReg:NA Preferences=[allInt] Interval 248: long RefPositions {#1092@1646 #1093@1647} physReg:NA Preferences=[allInt] RelatedInterval Interval 249: long RefPositions {#1099@1654 #1106@1659} physReg:NA Preferences=[rcx] Interval 250: long (constant) RefPositions {#1100@1656 #1102@1657} physReg:NA Preferences=[rdx] Interval 251: long RefPositions {#1104@1658 #1108@1659} physReg:NA Preferences=[rdx] Interval 252: long RefPositions {#1117@1660 #1118@1661} physReg:NA Preferences=[rax] RelatedInterval Interval 253: long RefPositions {#1124@1668 #1130@1673} physReg:NA Preferences=[rcx] Interval 254: ref RefPositions {#1128@1672 #1132@1673} physReg:NA Preferences=[rdx] ------------ REFPOSITIONS BEFORE VALIDATING INTERVALS: ------------ BB00 regmask=[rcx] minReg=1 fixed regOptional> BB00 regmask=[rdx] minReg=1 fixed regOptional> BB00 regmask=[r9] minReg=1 fixed regOptional> BB00 regmask=[r8] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB02 regmask=[allInt] minReg=1> BB03 regmask=[rcx] minReg=1> LCL_VAR BB03 regmask=[rcx] minReg=1 fixed> BB03 regmask=[rcx] minReg=1> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed> CNS_INT BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1 last fixed> BB03 regmask=[rdx] minReg=1> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed> BB03 regmask=[rcx] minReg=1> BB03 regmask=[rcx] minReg=1 last fixed> BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1 last fixed> BB03 regmask=[rax] minReg=1 last> BB03 regmask=[rcx] minReg=1 last> BB03 regmask=[rdx] minReg=1 last> BB03 regmask=[r8] minReg=1 last> BB03 regmask=[r9] minReg=1 last> BB03 regmask=[r10] minReg=1 last> BB03 regmask=[r11] minReg=1 last> BB03 regmask=[rax] minReg=1> CALL BB03 regmask=[rax] minReg=1 last fixed local> LCL_VAR BB04 regmask=[allInt] minReg=1> NE BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> CNS_INT BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> IND BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1 last regOptional> BB05 regmask=[rcx] minReg=1> LCL_VAR BB05 regmask=[rcx] minReg=1 fixed> BB05 regmask=[rcx] minReg=1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> BB05 regmask=[rdx] minReg=1> LCL_VAR BB05 regmask=[rdx] minReg=1 last fixed> BB05 regmask=[rdx] minReg=1> PUTARG_REG BB05 regmask=[rdx] minReg=1 fixed> BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> BB05 regmask=[rdx] minReg=1> BB05 regmask=[rdx] minReg=1 last fixed> BB05 regmask=[rax] minReg=1 last> BB05 regmask=[rcx] minReg=1 last> BB05 regmask=[rdx] minReg=1 last> BB05 regmask=[r8] minReg=1 last> BB05 regmask=[r9] minReg=1 last> BB05 regmask=[r10] minReg=1 last> BB05 regmask=[r11] minReg=1 last> LCL_VAR BB06 regmask=[allInt] minReg=1> IND BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1 regOptional> NE BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1 last regOptional> CNS_INT BB07 regmask=[allInt] minReg=1> BB07 regmask=[allInt] minReg=1 last> IND BB07 regmask=[rcx] minReg=1> BB07 regmask=[rcx] minReg=1> BB07 regmask=[rcx] minReg=1 last fixed> BB07 regmask=[rcx] minReg=1> PUTARG_REG BB07 regmask=[rcx] minReg=1 fixed> BB07 regmask=[rdx] minReg=1> LCL_VAR BB07 regmask=[rdx] minReg=1 last fixed> BB07 regmask=[rdx] minReg=1> PUTARG_REG BB07 regmask=[rdx] minReg=1 fixed> BB07 regmask=[rcx] minReg=1> BB07 regmask=[rcx] minReg=1 last fixed> BB07 regmask=[rdx] minReg=1> BB07 regmask=[rdx] minReg=1 last fixed> BB07 regmask=[rax] minReg=1 last> BB07 regmask=[rcx] minReg=1 last> BB07 regmask=[rdx] minReg=1 last> BB07 regmask=[r8] minReg=1 last> BB07 regmask=[r9] minReg=1 last> BB07 regmask=[r10] minReg=1 last> BB07 regmask=[r11] minReg=1 last> LCL_VAR BB08 regmask=[allInt] minReg=1> IND BB08 regmask=[allInt] minReg=1> BB08 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB08 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB09 regmask=[allInt] minReg=1> IND BB09 regmask=[allInt] minReg=1> BB09 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[allInt] minReg=1> IND BB09 regmask=[allInt] minReg=1> BB09 regmask=[allInt] minReg=1 last> IND BB09 regmask=[allInt] minReg=1> BB09 regmask=[allInt] minReg=1 last> IND BB09 regmask=[allInt] minReg=1> BB09 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB10 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> BB11 regmask=[rcx] minReg=1> LCL_VAR BB11 regmask=[rcx] minReg=1 last fixed> BB11 regmask=[rcx] minReg=1> PUTARG_REG BB11 regmask=[rcx] minReg=1 fixed> CNS_INT BB11 regmask=[rdx] minReg=1> BB11 regmask=[rdx] minReg=1> BB11 regmask=[rdx] minReg=1 last fixed> BB11 regmask=[rdx] minReg=1> PUTARG_REG BB11 regmask=[rdx] minReg=1 fixed> BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> BB11 regmask=[rdx] minReg=1> BB11 regmask=[rdx] minReg=1 last fixed> BB11 regmask=[rax] minReg=1 last> BB11 regmask=[rcx] minReg=1 last> BB11 regmask=[rdx] minReg=1 last> BB11 regmask=[r8] minReg=1 last> BB11 regmask=[r9] minReg=1 last> BB11 regmask=[r10] minReg=1 last> BB11 regmask=[r11] minReg=1 last> BB11 regmask=[rax] minReg=1> CALL BB11 regmask=[rax] minReg=1 fixed> BB11 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 fixed> BB12 regmask=[rcx] minReg=1> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> BB12 regmask=[r11] minReg=1> LCL_VAR BB12 regmask=[r11] minReg=1 fixed> BB12 regmask=[r11] minReg=1> PUTARG_REG BB12 regmask=[r11] minReg=1 fixed> BB12 regmask=[rdx] minReg=1> LCL_VAR BB12 regmask=[rdx] minReg=1 fixed> BB12 regmask=[rdx] minReg=1> PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed> BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> BB12 regmask=[r11] minReg=1> BB12 regmask=[r11] minReg=1 last fixed> BB12 regmask=[rdx] minReg=1> BB12 regmask=[rdx] minReg=1 last fixed> LCL_VAR BB12 regmask=[allInt] minReg=1 last> BB12 regmask=[rax] minReg=1 last> BB12 regmask=[rcx] minReg=1 last> BB12 regmask=[rdx] minReg=1 last> BB12 regmask=[r8] minReg=1 last> BB12 regmask=[r9] minReg=1 last> BB12 regmask=[r10] minReg=1 last> BB12 regmask=[r11] minReg=1 last> BB12 regmask=[rax] minReg=1> CALL BB12 regmask=[rax] minReg=1 fixed> BB12 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB12 regmask=[allInt] minReg=1> BB13 regmask=[rcx] minReg=1> LCL_VAR BB13 regmask=[rcx] minReg=1 fixed> BB13 regmask=[rcx] minReg=1> PUTARG_REG BB13 regmask=[rcx] minReg=1 fixed> LCL_VAR BB13 regmask=[allInt] minReg=1> IND BB13 regmask=[allInt] minReg=1> BB13 regmask=[allInt] minReg=1 last> IND BB13 regmask=[allInt] minReg=1> BB13 regmask=[rcx] minReg=1> BB13 regmask=[rcx] minReg=1 last fixed> BB13 regmask=[allInt] minReg=1 last> BB13 regmask=[rax] minReg=1 last> BB13 regmask=[rcx] minReg=1 last> BB13 regmask=[rdx] minReg=1 last> BB13 regmask=[r8] minReg=1 last> BB13 regmask=[r9] minReg=1 last> BB13 regmask=[r10] minReg=1 last> BB13 regmask=[r11] minReg=1 last> BB13 regmask=[rax] minReg=1> CALL BB13 regmask=[rax] minReg=1 fixed> BB13 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB13 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> CNS_INT BB14 regmask=[allInt] minReg=1> BB14 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> IND BB14 regmask=[allInt] minReg=1> BB14 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> IND BB14 regmask=[allInt] minReg=1> BB14 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> IND BB14 regmask=[allInt] minReg=1> BB14 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 regOptional> LE BB14 regmask=[allInt] minReg=1> BB14 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 last regOptional> BB15 regmask=[rcx] minReg=1> LCL_VAR BB15 regmask=[rcx] minReg=1 fixed> BB15 regmask=[rcx] minReg=1> PUTARG_REG BB15 regmask=[rcx] minReg=1 fixed> BB15 regmask=[rdx] minReg=1> LCL_VAR BB15 regmask=[rdx] minReg=1 last fixed> BB15 regmask=[rdx] minReg=1> PUTARG_REG BB15 regmask=[rdx] minReg=1 fixed> BB15 regmask=[rcx] minReg=1> BB15 regmask=[rcx] minReg=1 last fixed> BB15 regmask=[rdx] minReg=1> BB15 regmask=[rdx] minReg=1 last fixed> BB15 regmask=[rax] minReg=1 last> BB15 regmask=[rcx] minReg=1 last> BB15 regmask=[rdx] minReg=1 last> BB15 regmask=[r8] minReg=1 last> BB15 regmask=[r9] minReg=1 last> BB15 regmask=[r10] minReg=1 last> BB15 regmask=[r11] minReg=1 last> LCL_VAR BB16 regmask=[allInt] minReg=1> CAST BB16 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1 last regOptional> BB16 regmask=[allInt] minReg=1 last> MUL BB16 regmask=[allInt] minReg=1> BB16 regmask=[allInt] minReg=1 last> RSZ BB16 regmask=[allInt] minReg=1> BB16 regmask=[allInt] minReg=1 last> ADD BB16 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1> CAST BB16 regmask=[allInt] minReg=1> BB16 regmask=[allInt] minReg=1 last regOptional> BB16 regmask=[allInt] minReg=1 last> MUL BB16 regmask=[allInt] minReg=1> BB16 regmask=[allInt] minReg=1 last> RSZ BB16 regmask=[allInt] minReg=1> BB16 regmask=[allInt] minReg=1 last> CAST BB16 regmask=[allInt] minReg=1> BB16 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB16 regmask=[allInt] minReg=1> BB16 regmask=[rax] minReg=1> LCL_VAR BB16 regmask=[rax] minReg=1 fixed> LCL_VAR BB16 regmask=[rcx rbx rbp rsi rdi r8-r15] minReg=1 last delay regOptional> BB16 regmask=[rax] minReg=1 last> BB16 regmask=[rdx] minReg=1 last> BB16 regmask=[rdx] minReg=1> UMOD BB16 regmask=[rdx] minReg=1 fixed> BB16 regmask=[allInt] minReg=1 last> LCL_VAR BB16 regmask=[allInt] minReg=1 regOptional> EQ BB16 regmask=[allInt] minReg=1> BB16 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB16 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1> STORE_LCL_VAR BB16 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1 last regOptional> BB17 regmask=[rcx] minReg=1> LCL_VAR BB17 regmask=[rcx] minReg=1 fixed> BB17 regmask=[rcx] minReg=1> PUTARG_REG BB17 regmask=[rcx] minReg=1 fixed> BB17 regmask=[rdx] minReg=1> LCL_VAR BB17 regmask=[rdx] minReg=1 last fixed> BB17 regmask=[rdx] minReg=1> PUTARG_REG BB17 regmask=[rdx] minReg=1 fixed> BB17 regmask=[rcx] minReg=1> BB17 regmask=[rcx] minReg=1 last fixed> BB17 regmask=[rdx] minReg=1> BB17 regmask=[rdx] minReg=1 last fixed> BB17 regmask=[rax] minReg=1 last> BB17 regmask=[rcx] minReg=1 last> BB17 regmask=[rdx] minReg=1 last> BB17 regmask=[r8] minReg=1 last> BB17 regmask=[r9] minReg=1 last> BB17 regmask=[r10] minReg=1 last> BB17 regmask=[r11] minReg=1 last> LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> CAST BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> BB18 regmask=[allInt] minReg=1 last> LEA BB18 regmask=[allInt] minReg=1> BB18 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1> IND BB18 regmask=[allInt] minReg=1> BB18 regmask=[allInt] minReg=1 last> ADD BB18 regmask=[allInt] minReg=1> BB18 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB19 regmask=[allInt] minReg=1> IND BB19 regmask=[allInt] minReg=1> BB19 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB19 regmask=[allInt] minReg=1> LCL_VAR BB19 regmask=[allInt] minReg=1> IND BB19 regmask=[allInt] minReg=1> BB19 regmask=[allInt] minReg=1 last> IND BB19 regmask=[allInt] minReg=1> BB19 regmask=[allInt] minReg=1 last> IND BB19 regmask=[allInt] minReg=1> BB19 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB19 regmask=[allInt] minReg=1> LCL_VAR BB19 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB20 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> BB21 regmask=[rcx] minReg=1> LCL_VAR BB21 regmask=[rcx] minReg=1 last fixed> BB21 regmask=[rcx] minReg=1> PUTARG_REG BB21 regmask=[rcx] minReg=1 fixed> CNS_INT BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1 last fixed> BB21 regmask=[rdx] minReg=1> PUTARG_REG BB21 regmask=[rdx] minReg=1 fixed> BB21 regmask=[rcx] minReg=1> BB21 regmask=[rcx] minReg=1 last fixed> BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1 last fixed> BB21 regmask=[rax] minReg=1 last> BB21 regmask=[rcx] minReg=1 last> BB21 regmask=[rdx] minReg=1 last> BB21 regmask=[r8] minReg=1 last> BB21 regmask=[r9] minReg=1 last> BB21 regmask=[r10] minReg=1 last> BB21 regmask=[r11] minReg=1 last> BB21 regmask=[rax] minReg=1> CALL BB21 regmask=[rax] minReg=1 fixed> BB21 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> BB22 regmask=[rcx] minReg=1> LCL_VAR BB22 regmask=[rcx] minReg=1 last fixed> BB22 regmask=[rcx] minReg=1> PUTARG_REG BB22 regmask=[rcx] minReg=1 fixed> BB22 regmask=[rcx] minReg=1> BB22 regmask=[rcx] minReg=1 last fixed> BB22 regmask=[rax] minReg=1 last> BB22 regmask=[rcx] minReg=1 last> BB22 regmask=[rdx] minReg=1 last> BB22 regmask=[r8] minReg=1 last> BB22 regmask=[r9] minReg=1 last> BB22 regmask=[r10] minReg=1 last> BB22 regmask=[r11] minReg=1 last> BB22 regmask=[rax] minReg=1> CALL BB22 regmask=[rax] minReg=1 fixed> BB22 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB22 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> IND BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB24 regmask=[allInt] minReg=1 last> CAST BB24 regmask=[allInt] minReg=1> BB24 regmask=[allInt] minReg=1 last> MUL BB24 regmask=[allInt] minReg=1> BB24 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB24 regmask=[allInt] minReg=1> LEA BB24 regmask=[allInt] minReg=1> BB24 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1 last> IND BB25 regmask=[rdx] minReg=1> BB25 regmask=[rdx] minReg=1> BB25 regmask=[rdx] minReg=1 last fixed> BB25 regmask=[rdx] minReg=1> PUTARG_REG BB25 regmask=[rdx] minReg=1 fixed> BB25 regmask=[rcx] minReg=1> LCL_VAR BB25 regmask=[rcx] minReg=1 fixed> BB25 regmask=[rcx] minReg=1> PUTARG_REG BB25 regmask=[rcx] minReg=1 fixed> BB25 regmask=[r8] minReg=1> LCL_VAR BB25 regmask=[r8] minReg=1 fixed> BB25 regmask=[r8] minReg=1> PUTARG_REG BB25 regmask=[r8] minReg=1 fixed> LCL_VAR BB25 regmask=[allInt] minReg=1> IND BB25 regmask=[allInt] minReg=1> BB25 regmask=[allInt] minReg=1 last> IND BB25 regmask=[allInt] minReg=1> BB25 regmask=[rdx] minReg=1> BB25 regmask=[rdx] minReg=1 last fixed> BB25 regmask=[rcx] minReg=1> BB25 regmask=[rcx] minReg=1 last fixed> BB25 regmask=[r8] minReg=1> BB25 regmask=[r8] minReg=1 last fixed> BB25 regmask=[allInt] minReg=1 last> BB25 regmask=[rax] minReg=1 last> BB25 regmask=[rcx] minReg=1 last> BB25 regmask=[rdx] minReg=1 last> BB25 regmask=[r8] minReg=1 last> BB25 regmask=[r9] minReg=1 last> BB25 regmask=[r10] minReg=1 last> BB25 regmask=[r11] minReg=1 last> BB25 regmask=[rax] minReg=1> CALL BB25 regmask=[rax] minReg=1 fixed> BB25 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB26 regmask=[allInt] minReg=1 last> IND BB26 regmask=[allInt] minReg=1> BB26 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1 last> ADD BB26 regmask=[allInt] minReg=1> BB26 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB26 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB28 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB29 regmask=[allInt] minReg=1 last> LEA BB29 regmask=[rcx] minReg=1> BB29 regmask=[rcx] minReg=1> BB29 regmask=[rcx] minReg=1 last fixed> BB29 regmask=[rdx] minReg=1> LCL_VAR BB29 regmask=[rdx] minReg=1 last fixed> BB29 regmask=[rax] minReg=1 last> BB29 regmask=[rcx] minReg=1 last> BB29 regmask=[rdx] minReg=1 last> BB29 regmask=[r8] minReg=1 last> BB29 regmask=[r9] minReg=1 last> BB29 regmask=[r10] minReg=1 last> BB29 regmask=[r11] minReg=1 last> BB29 regmask=[mm0] minReg=1 last> BB29 regmask=[mm1] minReg=1 last> BB29 regmask=[mm2] minReg=1 last> BB29 regmask=[mm3] minReg=1 last> BB29 regmask=[mm4] minReg=1 last> BB29 regmask=[mm5] minReg=1 last> LCL_VAR BB30 regmask=[allInt] minReg=1 last regOptional> CNS_INT BB31 regmask=[rax] minReg=1> BB31 regmask=[rax] minReg=1> BB31 regmask=[rax] minReg=1 last fixed> LCL_VAR BB32 regmask=[allInt] minReg=1> IND BB32 regmask=[allInt] minReg=1> BB32 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1 last> CAST BB33 regmask=[allInt] minReg=1> BB33 regmask=[allInt] minReg=1 last> MUL BB33 regmask=[allInt] minReg=1> BB33 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1> LEA BB33 regmask=[allInt] minReg=1> BB33 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1 last> IND BB34 regmask=[allInt] minReg=1> BB34 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1> IND BB34 regmask=[allInt] minReg=1> BB34 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1> IND BB34 regmask=[allInt] minReg=1> BB34 regmask=[allInt] minReg=1 last> IND BB34 regmask=[allInt] minReg=1> BB34 regmask=[allInt] minReg=1 last> IND BB34 regmask=[allInt] minReg=1> BB34 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB35 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> BB36 regmask=[rcx] minReg=1> LCL_VAR BB36 regmask=[rcx] minReg=1 last fixed> BB36 regmask=[rcx] minReg=1> PUTARG_REG BB36 regmask=[rcx] minReg=1 fixed> CNS_INT BB36 regmask=[rdx] minReg=1> BB36 regmask=[rdx] minReg=1> BB36 regmask=[rdx] minReg=1 last fixed> BB36 regmask=[rdx] minReg=1> PUTARG_REG BB36 regmask=[rdx] minReg=1 fixed> BB36 regmask=[rcx] minReg=1> BB36 regmask=[rcx] minReg=1 last fixed> BB36 regmask=[rdx] minReg=1> BB36 regmask=[rdx] minReg=1 last fixed> BB36 regmask=[rax] minReg=1 last> BB36 regmask=[rcx] minReg=1 last> BB36 regmask=[rdx] minReg=1 last> BB36 regmask=[r8] minReg=1 last> BB36 regmask=[r9] minReg=1 last> BB36 regmask=[r10] minReg=1 last> BB36 regmask=[r11] minReg=1 last> BB36 regmask=[rax] minReg=1> CALL BB36 regmask=[rax] minReg=1 fixed> BB36 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB36 regmask=[allInt] minReg=1> BB37 regmask=[rcx] minReg=1> LCL_VAR BB37 regmask=[rcx] minReg=1 fixed> BB37 regmask=[rcx] minReg=1> PUTARG_REG BB37 regmask=[rcx] minReg=1 fixed> BB37 regmask=[r11] minReg=1> LCL_VAR BB37 regmask=[r11] minReg=1 fixed> BB37 regmask=[r11] minReg=1> PUTARG_REG BB37 regmask=[r11] minReg=1 fixed> BB37 regmask=[rdx] minReg=1> LCL_VAR BB37 regmask=[rdx] minReg=1 last fixed> BB37 regmask=[rdx] minReg=1> PUTARG_REG BB37 regmask=[rdx] minReg=1 fixed> BB37 regmask=[r8] minReg=1> LCL_VAR BB37 regmask=[r8] minReg=1 fixed> BB37 regmask=[r8] minReg=1> PUTARG_REG BB37 regmask=[r8] minReg=1 fixed> BB37 regmask=[rcx] minReg=1> BB37 regmask=[rcx] minReg=1 last fixed> BB37 regmask=[r11] minReg=1> BB37 regmask=[r11] minReg=1 last fixed> BB37 regmask=[rdx] minReg=1> BB37 regmask=[rdx] minReg=1 last fixed> BB37 regmask=[r8] minReg=1> BB37 regmask=[r8] minReg=1 last fixed> LCL_VAR BB37 regmask=[allInt] minReg=1 last> BB37 regmask=[rax] minReg=1 last> BB37 regmask=[rcx] minReg=1 last> BB37 regmask=[rdx] minReg=1 last> BB37 regmask=[r8] minReg=1 last> BB37 regmask=[r9] minReg=1 last> BB37 regmask=[r10] minReg=1 last> BB37 regmask=[r11] minReg=1 last> BB37 regmask=[rax] minReg=1> CALL BB37 regmask=[rax] minReg=1 fixed> BB37 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB38 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB39 regmask=[allInt] minReg=1 last> LEA BB39 regmask=[rcx] minReg=1> BB39 regmask=[rcx] minReg=1> BB39 regmask=[rcx] minReg=1 last fixed> BB39 regmask=[rdx] minReg=1> LCL_VAR BB39 regmask=[rdx] minReg=1 last fixed> BB39 regmask=[rax] minReg=1 last> BB39 regmask=[rcx] minReg=1 last> BB39 regmask=[rdx] minReg=1 last> BB39 regmask=[r8] minReg=1 last> BB39 regmask=[r9] minReg=1 last> BB39 regmask=[r10] minReg=1 last> BB39 regmask=[r11] minReg=1 last> BB39 regmask=[mm0] minReg=1 last> BB39 regmask=[mm1] minReg=1 last> BB39 regmask=[mm2] minReg=1 last> BB39 regmask=[mm3] minReg=1 last> BB39 regmask=[mm4] minReg=1 last> BB39 regmask=[mm5] minReg=1 last> LCL_VAR BB40 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB42 regmask=[allInt] minReg=1 last> IND BB42 regmask=[allInt] minReg=1> BB42 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB42 regmask=[allInt] minReg=1> LCL_VAR BB42 regmask=[allInt] minReg=1 last> ADD BB42 regmask=[allInt] minReg=1> BB42 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB42 regmask=[allInt] minReg=1> LCL_VAR BB42 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB42 regmask=[allInt] minReg=1> BB43 regmask=[allInt] minReg=1 regOptional> BB43 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB44 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1> IND BB45 regmask=[allInt] minReg=1> BB45 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1> STORE_LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB45 regmask=[allInt] minReg=1 last> CAST BB45 regmask=[allInt] minReg=1> BB45 regmask=[allInt] minReg=1 last> MUL BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1> BB45 regmask=[allInt] minReg=1 last> IND BB45 regmask=[allInt] minReg=1> BB45 regmask=[allInt] minReg=1 last> NEG BB45 regmask=[allInt] minReg=1> BB45 regmask=[allInt] minReg=1 last> ADD BB45 regmask=[allInt] minReg=1> BB45 regmask=[allInt] minReg=1 last regOptional> GE BB45 regmask=[allInt] minReg=1> BB45 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1 last regOptional> CNS_INT BB46 regmask=[allInt] minReg=1> BB46 regmask=[allInt] minReg=1 last> IND BB46 regmask=[rcx] minReg=1> BB46 regmask=[rcx] minReg=1> BB46 regmask=[rcx] minReg=1 last fixed> BB46 regmask=[rcx] minReg=1> PUTARG_REG BB46 regmask=[rcx] minReg=1 fixed> BB46 regmask=[rdx] minReg=1> LCL_VAR BB46 regmask=[rdx] minReg=1 last fixed> BB46 regmask=[rdx] minReg=1> PUTARG_REG BB46 regmask=[rdx] minReg=1 fixed> BB46 regmask=[rcx] minReg=1> BB46 regmask=[rcx] minReg=1 last fixed> BB46 regmask=[rdx] minReg=1> BB46 regmask=[rdx] minReg=1 last fixed> BB46 regmask=[rax] minReg=1 last> BB46 regmask=[rcx] minReg=1 last> BB46 regmask=[rdx] minReg=1 last> BB46 regmask=[r8] minReg=1 last> BB46 regmask=[r9] minReg=1 last> BB46 regmask=[r10] minReg=1 last> BB46 regmask=[r11] minReg=1 last> LCL_VAR BB47 regmask=[allInt] minReg=1> IND BB47 regmask=[allInt] minReg=1> BB47 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB47 regmask=[allInt] minReg=1> LCL_VAR BB47 regmask=[allInt] minReg=1> LCL_VAR BB47 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB47 regmask=[allInt] minReg=1 last> CAST BB47 regmask=[allInt] minReg=1> BB47 regmask=[allInt] minReg=1 last> MUL BB47 regmask=[allInt] minReg=1> LCL_VAR BB47 regmask=[allInt] minReg=1> BB47 regmask=[allInt] minReg=1 last> IND BB47 regmask=[allInt] minReg=1> BB47 regmask=[allInt] minReg=1 last> NEG BB47 regmask=[allInt] minReg=1> BB47 regmask=[allInt] minReg=1 last> ADD BB47 regmask=[allInt] minReg=1> LCL_VAR BB47 regmask=[allInt] minReg=1> BB47 regmask=[allInt] minReg=1 last> LCL_VAR BB47 regmask=[allInt] minReg=1> LCL_VAR BB48 regmask=[allInt] minReg=1> IND BB48 regmask=[allInt] minReg=1> BB48 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB48 regmask=[allInt] minReg=1> LCL_VAR BB48 regmask=[allInt] minReg=1> STORE_LCL_VAR BB48 regmask=[allInt] minReg=1> LCL_VAR BB48 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB48 regmask=[allInt] minReg=1> BB49 regmask=[rcx] minReg=1> LCL_VAR BB49 regmask=[rcx] minReg=1 last fixed> BB49 regmask=[rcx] minReg=1> PUTARG_REG BB49 regmask=[rcx] minReg=1 fixed> BB49 regmask=[rcx] minReg=1> BB49 regmask=[rcx] minReg=1 last fixed> BB49 regmask=[rax] minReg=1 last> BB49 regmask=[rcx] minReg=1 last> BB49 regmask=[rdx] minReg=1 last> BB49 regmask=[r8] minReg=1 last> BB49 regmask=[r9] minReg=1 last> BB49 regmask=[r10] minReg=1 last> BB49 regmask=[r11] minReg=1 last> BB49 regmask=[rax] minReg=1> CALL BB49 regmask=[rax] minReg=1 fixed> BB49 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> BB49 regmask=[rdx] minReg=1> LCL_VAR BB49 regmask=[rdx] minReg=1 last fixed> BB49 regmask=[rdx] minReg=1> PUTARG_REG BB49 regmask=[rdx] minReg=1 fixed> BB49 regmask=[rcx] minReg=1> LCL_VAR BB49 regmask=[rcx] minReg=1 fixed> BB49 regmask=[rcx] minReg=1> PUTARG_REG BB49 regmask=[rcx] minReg=1 fixed> CNS_INT BB49 regmask=[r8] minReg=1> BB49 regmask=[r8] minReg=1> BB49 regmask=[r8] minReg=1 last fixed> BB49 regmask=[r8] minReg=1> PUTARG_REG BB49 regmask=[r8] minReg=1 fixed> BB49 regmask=[rdx] minReg=1> BB49 regmask=[rdx] minReg=1 last fixed> BB49 regmask=[rcx] minReg=1> BB49 regmask=[rcx] minReg=1 last fixed> BB49 regmask=[r8] minReg=1> BB49 regmask=[r8] minReg=1 last fixed> BB49 regmask=[rax] minReg=1 last> BB49 regmask=[rcx] minReg=1 last> BB49 regmask=[rdx] minReg=1 last> BB49 regmask=[r8] minReg=1 last> BB49 regmask=[r9] minReg=1 last> BB49 regmask=[r10] minReg=1 last> BB49 regmask=[r11] minReg=1 last> LCL_VAR BB49 regmask=[allInt] minReg=1> IND BB49 regmask=[allInt] minReg=1> BB49 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1> IND BB49 regmask=[allInt] minReg=1> BB49 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1> STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1> IND BB49 regmask=[allInt] minReg=1> BB49 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1 regOptional> LE BB49 regmask=[allInt] minReg=1> BB49 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1> STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1 last regOptional> BB50 regmask=[rcx] minReg=1> LCL_VAR BB50 regmask=[rcx] minReg=1 fixed> BB50 regmask=[rcx] minReg=1> PUTARG_REG BB50 regmask=[rcx] minReg=1 fixed> BB50 regmask=[rdx] minReg=1> LCL_VAR BB50 regmask=[rdx] minReg=1 last fixed> BB50 regmask=[rdx] minReg=1> PUTARG_REG BB50 regmask=[rdx] minReg=1 fixed> BB50 regmask=[rcx] minReg=1> BB50 regmask=[rcx] minReg=1 last fixed> BB50 regmask=[rdx] minReg=1> BB50 regmask=[rdx] minReg=1 last fixed> BB50 regmask=[rax] minReg=1 last> BB50 regmask=[rcx] minReg=1 last> BB50 regmask=[rdx] minReg=1 last> BB50 regmask=[r8] minReg=1 last> BB50 regmask=[r9] minReg=1 last> BB50 regmask=[r10] minReg=1 last> BB50 regmask=[r11] minReg=1 last> LCL_VAR BB51 regmask=[allInt] minReg=1> CAST BB51 regmask=[allInt] minReg=1> LCL_VAR BB51 regmask=[allInt] minReg=1 last regOptional> BB51 regmask=[allInt] minReg=1 last> MUL BB51 regmask=[allInt] minReg=1> BB51 regmask=[allInt] minReg=1 last> RSZ BB51 regmask=[allInt] minReg=1> BB51 regmask=[allInt] minReg=1 last> ADD BB51 regmask=[allInt] minReg=1> LCL_VAR BB51 regmask=[allInt] minReg=1> CAST BB51 regmask=[allInt] minReg=1> BB51 regmask=[allInt] minReg=1 last regOptional> BB51 regmask=[allInt] minReg=1 last> MUL BB51 regmask=[allInt] minReg=1> BB51 regmask=[allInt] minReg=1 last> RSZ BB51 regmask=[allInt] minReg=1> BB51 regmask=[allInt] minReg=1 last> CAST BB51 regmask=[allInt] minReg=1> BB51 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB51 regmask=[allInt] minReg=1> BB51 regmask=[rax] minReg=1> LCL_VAR BB51 regmask=[rax] minReg=1 fixed> LCL_VAR BB51 regmask=[rcx rbx rbp rsi rdi r8-r15] minReg=1 last delay regOptional> BB51 regmask=[rax] minReg=1 last> BB51 regmask=[rdx] minReg=1 last> BB51 regmask=[rdx] minReg=1> UMOD BB51 regmask=[rdx] minReg=1 fixed> BB51 regmask=[allInt] minReg=1 last> LCL_VAR BB51 regmask=[allInt] minReg=1 regOptional> EQ BB51 regmask=[allInt] minReg=1> BB51 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB51 regmask=[allInt] minReg=1> LCL_VAR BB51 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB51 regmask=[allInt] minReg=1> LCL_VAR BB51 regmask=[allInt] minReg=1 last regOptional> BB52 regmask=[rcx] minReg=1> LCL_VAR BB52 regmask=[rcx] minReg=1 fixed> BB52 regmask=[rcx] minReg=1> PUTARG_REG BB52 regmask=[rcx] minReg=1 fixed> BB52 regmask=[rdx] minReg=1> LCL_VAR BB52 regmask=[rdx] minReg=1 last fixed> BB52 regmask=[rdx] minReg=1> PUTARG_REG BB52 regmask=[rdx] minReg=1 fixed> BB52 regmask=[rcx] minReg=1> BB52 regmask=[rcx] minReg=1 last fixed> BB52 regmask=[rdx] minReg=1> BB52 regmask=[rdx] minReg=1 last fixed> BB52 regmask=[rax] minReg=1 last> BB52 regmask=[rcx] minReg=1 last> BB52 regmask=[rdx] minReg=1 last> BB52 regmask=[r8] minReg=1 last> BB52 regmask=[r9] minReg=1 last> BB52 regmask=[r10] minReg=1 last> BB52 regmask=[r11] minReg=1 last> LCL_VAR BB53 regmask=[allInt] minReg=1> LCL_VAR BB53 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB53 regmask=[allInt] minReg=1 last> CAST BB53 regmask=[allInt] minReg=1> LCL_VAR BB53 regmask=[allInt] minReg=1 last> BB53 regmask=[allInt] minReg=1 last> LEA BB53 regmask=[allInt] minReg=1> BB53 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB53 regmask=[allInt] minReg=1> LCL_VAR BB53 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB53 regmask=[allInt] minReg=1> LCL_VAR BB54 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB54 regmask=[allInt] minReg=1> LCL_VAR BB54 regmask=[allInt] minReg=1> ADD BB54 regmask=[allInt] minReg=1> LCL_VAR BB54 regmask=[allInt] minReg=1> BB54 regmask=[allInt] minReg=1 last> LCL_VAR BB54 regmask=[allInt] minReg=1> IND BB54 regmask=[allInt] minReg=1> BB54 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB54 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> CAST BB55 regmask=[allInt] minReg=1> BB55 regmask=[allInt] minReg=1 last> MUL BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> BB55 regmask=[allInt] minReg=1 last> LEA BB55 regmask=[allInt] minReg=1> BB55 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1 last> LCL_VAR BB55 regmask=[allInt] minReg=1> IND BB55 regmask=[allInt] minReg=1> BB55 regmask=[allInt] minReg=1 last> ADD BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> BB55 regmask=[allInt] minReg=1 last> BB55 regmask=[rcx] minReg=1> LCL_VAR BB55 regmask=[rcx] minReg=1 fixed> BB55 regmask=[rdx] minReg=1> LCL_VAR BB55 regmask=[rdx] minReg=1 last fixed> BB55 regmask=[rax] minReg=1 last> BB55 regmask=[rcx] minReg=1 last> BB55 regmask=[rdx] minReg=1 last> BB55 regmask=[r8] minReg=1 last> BB55 regmask=[r9] minReg=1 last> BB55 regmask=[r10] minReg=1 last> BB55 regmask=[r11] minReg=1 last> BB55 regmask=[mm0] minReg=1 last> BB55 regmask=[mm1] minReg=1 last> BB55 regmask=[mm2] minReg=1 last> BB55 regmask=[mm3] minReg=1 last> BB55 regmask=[mm4] minReg=1 last> BB55 regmask=[mm5] minReg=1 last> LCL_VAR BB55 regmask=[allInt] minReg=1 last> LEA BB55 regmask=[rcx] minReg=1> BB55 regmask=[rcx] minReg=1> BB55 regmask=[rcx] minReg=1 last fixed> BB55 regmask=[rdx] minReg=1> LCL_VAR BB55 regmask=[rdx] minReg=1 last fixed> BB55 regmask=[rax] minReg=1 last> BB55 regmask=[rcx] minReg=1 last> BB55 regmask=[rdx] minReg=1 last> BB55 regmask=[r8] minReg=1 last> BB55 regmask=[r9] minReg=1 last> BB55 regmask=[r10] minReg=1 last> BB55 regmask=[r11] minReg=1 last> BB55 regmask=[mm0] minReg=1 last> BB55 regmask=[mm1] minReg=1 last> BB55 regmask=[mm2] minReg=1 last> BB55 regmask=[mm3] minReg=1 last> BB55 regmask=[mm4] minReg=1 last> BB55 regmask=[mm5] minReg=1 last> LCL_VAR BB55 regmask=[allInt] minReg=1 last> ADD BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1 last> BB55 regmask=[allInt] minReg=1 last> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1 last regOptional> BB56 regmask=[rdx] minReg=1> LCL_VAR BB56 regmask=[rdx] minReg=1 last fixed> BB56 regmask=[rdx] minReg=1> PUTARG_REG BB56 regmask=[rdx] minReg=1 fixed> CNS_INT BB56 regmask=[rcx] minReg=1> BB56 regmask=[rcx] minReg=1> BB56 regmask=[rcx] minReg=1 last fixed> BB56 regmask=[rcx] minReg=1> PUTARG_REG BB56 regmask=[rcx] minReg=1 fixed> BB56 regmask=[rdx] minReg=1> BB56 regmask=[rdx] minReg=1 last fixed> BB56 regmask=[rcx] minReg=1> BB56 regmask=[rcx] minReg=1 last fixed> BB56 regmask=[rax] minReg=1 last> BB56 regmask=[rcx] minReg=1 last> BB56 regmask=[rdx] minReg=1 last> BB56 regmask=[r8] minReg=1 last> BB56 regmask=[r9] minReg=1 last> BB56 regmask=[r10] minReg=1 last> BB56 regmask=[r11] minReg=1 last> BB56 regmask=[rax] minReg=1> CALL BB56 regmask=[rax] minReg=1 fixed> BB56 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB57 regmask=[allInt] minReg=1 last> IND BB57 regmask=[rdx] minReg=1> BB57 regmask=[rdx] minReg=1> BB57 regmask=[rdx] minReg=1 last fixed> BB57 regmask=[rdx] minReg=1> PUTARG_REG BB57 regmask=[rdx] minReg=1 fixed> BB57 regmask=[rcx] minReg=1> LCL_VAR BB57 regmask=[rcx] minReg=1 fixed> BB57 regmask=[rcx] minReg=1> PUTARG_REG BB57 regmask=[rcx] minReg=1 fixed> CNS_INT BB57 regmask=[r8] minReg=1> BB57 regmask=[r8] minReg=1> BB57 regmask=[r8] minReg=1 last fixed> BB57 regmask=[r8] minReg=1> PUTARG_REG BB57 regmask=[r8] minReg=1 fixed> BB57 regmask=[rdx] minReg=1> BB57 regmask=[rdx] minReg=1 last fixed> BB57 regmask=[rcx] minReg=1> BB57 regmask=[rcx] minReg=1 last fixed> BB57 regmask=[r8] minReg=1> BB57 regmask=[r8] minReg=1 last fixed> BB57 regmask=[rax] minReg=1 last> BB57 regmask=[rcx] minReg=1 last> BB57 regmask=[rdx] minReg=1 last> BB57 regmask=[r8] minReg=1 last> BB57 regmask=[r9] minReg=1 last> BB57 regmask=[r10] minReg=1 last> BB57 regmask=[r11] minReg=1 last> CNS_INT BB58 regmask=[rax] minReg=1> BB58 regmask=[rax] minReg=1> BB58 regmask=[rax] minReg=1 last fixed> CNS_INT BB59 regmask=[rcx] minReg=1> BB59 regmask=[rcx] minReg=1> BB59 regmask=[rcx] minReg=1 last fixed> BB59 regmask=[rcx] minReg=1> PUTARG_REG BB59 regmask=[rcx] minReg=1 fixed> BB59 regmask=[rcx] minReg=1> BB59 regmask=[rcx] minReg=1 last fixed> BB59 regmask=[rax] minReg=1 last> BB59 regmask=[rcx] minReg=1 last> BB59 regmask=[rdx] minReg=1 last> BB59 regmask=[r8] minReg=1 last> BB59 regmask=[r9] minReg=1 last> BB59 regmask=[r10] minReg=1 last> BB59 regmask=[r11] minReg=1 last> LCL_VAR BB60 regmask=[allInt] minReg=1> IND BB60 regmask=[allInt] minReg=1> BB60 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB60 regmask=[allInt] minReg=1> LCL_VAR BB60 regmask=[allInt] minReg=1> IND BB60 regmask=[allInt] minReg=1> BB60 regmask=[allInt] minReg=1 last> IND BB60 regmask=[allInt] minReg=1> BB60 regmask=[allInt] minReg=1 last> LCL_VAR BB61 regmask=[allInt] minReg=1 last> IND BB61 regmask=[allInt] minReg=1> BB61 regmask=[allInt] minReg=1 last> IND BB61 regmask=[allInt] minReg=1> BB61 regmask=[allInt] minReg=1 last> IND BB61 regmask=[allInt] minReg=1> BB61 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB61 regmask=[allInt] minReg=1> BB62 regmask=[rcx] minReg=1> LCL_VAR BB62 regmask=[rcx] minReg=1 last fixed> BB62 regmask=[rcx] minReg=1> PUTARG_REG BB62 regmask=[rcx] minReg=1 fixed> CNS_INT BB62 regmask=[rdx] minReg=1> BB62 regmask=[rdx] minReg=1> BB62 regmask=[rdx] minReg=1 last fixed> BB62 regmask=[rdx] minReg=1> PUTARG_REG BB62 regmask=[rdx] minReg=1 fixed> BB62 regmask=[rcx] minReg=1> BB62 regmask=[rcx] minReg=1 last fixed> BB62 regmask=[rdx] minReg=1> BB62 regmask=[rdx] minReg=1 last fixed> BB62 regmask=[rax] minReg=1 last> BB62 regmask=[rcx] minReg=1 last> BB62 regmask=[rdx] minReg=1 last> BB62 regmask=[r8] minReg=1 last> BB62 regmask=[r9] minReg=1 last> BB62 regmask=[r10] minReg=1 last> BB62 regmask=[r11] minReg=1 last> BB62 regmask=[rax] minReg=1> CALL BB62 regmask=[rax] minReg=1 fixed> BB62 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB62 regmask=[allInt] minReg=1> BB63 regmask=[rcx] minReg=1> LCL_VAR BB63 regmask=[rcx] minReg=1 last fixed> BB63 regmask=[rcx] minReg=1> PUTARG_REG BB63 regmask=[rcx] minReg=1 fixed> BB63 regmask=[rdx] minReg=1> LCL_VAR BB63 regmask=[rdx] minReg=1 last fixed> BB63 regmask=[rdx] minReg=1> PUTARG_REG BB63 regmask=[rdx] minReg=1 fixed> BB63 regmask=[rcx] minReg=1> BB63 regmask=[rcx] minReg=1 last fixed> BB63 regmask=[rdx] minReg=1> BB63 regmask=[rdx] minReg=1 last fixed> BB63 regmask=[rax] minReg=1 last> BB63 regmask=[rcx] minReg=1 last> BB63 regmask=[rdx] minReg=1 last> BB63 regmask=[r8] minReg=1 last> BB63 regmask=[r9] minReg=1 last> BB63 regmask=[r10] minReg=1 last> BB63 regmask=[r11] minReg=1 last> LCL_VAR BB64 regmask=[allInt] minReg=1> IND BB64 regmask=[allInt] minReg=1> BB64 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB64 regmask=[allInt] minReg=1> LCL_VAR BB64 regmask=[allInt] minReg=1> IND BB64 regmask=[allInt] minReg=1> BB64 regmask=[allInt] minReg=1 last> IND BB64 regmask=[allInt] minReg=1> BB64 regmask=[allInt] minReg=1 last> LCL_VAR BB65 regmask=[allInt] minReg=1 last> IND BB65 regmask=[allInt] minReg=1> BB65 regmask=[allInt] minReg=1 last> IND BB65 regmask=[allInt] minReg=1> BB65 regmask=[allInt] minReg=1 last> IND BB65 regmask=[allInt] minReg=1> BB65 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB65 regmask=[allInt] minReg=1> BB66 regmask=[rcx] minReg=1> LCL_VAR BB66 regmask=[rcx] minReg=1 last fixed> BB66 regmask=[rcx] minReg=1> PUTARG_REG BB66 regmask=[rcx] minReg=1 fixed> CNS_INT BB66 regmask=[rdx] minReg=1> BB66 regmask=[rdx] minReg=1> BB66 regmask=[rdx] minReg=1 last fixed> BB66 regmask=[rdx] minReg=1> PUTARG_REG BB66 regmask=[rdx] minReg=1 fixed> BB66 regmask=[rcx] minReg=1> BB66 regmask=[rcx] minReg=1 last fixed> BB66 regmask=[rdx] minReg=1> BB66 regmask=[rdx] minReg=1 last fixed> BB66 regmask=[rax] minReg=1 last> BB66 regmask=[rcx] minReg=1 last> BB66 regmask=[rdx] minReg=1 last> BB66 regmask=[r8] minReg=1 last> BB66 regmask=[r9] minReg=1 last> BB66 regmask=[r10] minReg=1 last> BB66 regmask=[r11] minReg=1 last> BB66 regmask=[rax] minReg=1> CALL BB66 regmask=[rax] minReg=1 fixed> BB66 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB66 regmask=[allInt] minReg=1> BB67 regmask=[rcx] minReg=1> LCL_VAR BB67 regmask=[rcx] minReg=1 last fixed> BB67 regmask=[rcx] minReg=1> PUTARG_REG BB67 regmask=[rcx] minReg=1 fixed> BB67 regmask=[rdx] minReg=1> LCL_VAR BB67 regmask=[rdx] minReg=1 last fixed> BB67 regmask=[rdx] minReg=1> PUTARG_REG BB67 regmask=[rdx] minReg=1 fixed> BB67 regmask=[rcx] minReg=1> BB67 regmask=[rcx] minReg=1 last fixed> BB67 regmask=[rdx] minReg=1> BB67 regmask=[rdx] minReg=1 last fixed> BB67 regmask=[rax] minReg=1 last> BB67 regmask=[rcx] minReg=1 last> BB67 regmask=[rdx] minReg=1 last> BB67 regmask=[r8] minReg=1 last> BB67 regmask=[r9] minReg=1 last> BB67 regmask=[r10] minReg=1 last> BB67 regmask=[r11] minReg=1 last> BB68 regmask=[rax] minReg=1 last> BB68 regmask=[rcx] minReg=1 last> BB68 regmask=[rdx] minReg=1 last> BB68 regmask=[r8] minReg=1 last> BB68 regmask=[r9] minReg=1 last> BB68 regmask=[r10] minReg=1 last> BB68 regmask=[r11] minReg=1 last> BB69 regmask=[allInt] minReg=1 regOptional> BB69 regmask=[rax] minReg=1 last> BB69 regmask=[rcx] minReg=1 last> BB69 regmask=[rdx] minReg=1 last> BB69 regmask=[r8] minReg=1 last> BB69 regmask=[r9] minReg=1 last> BB69 regmask=[r10] minReg=1 last> BB69 regmask=[r11] minReg=1 last> BB69 regmask=[allInt] minReg=1 regOptional> BB69 regmask=[allInt] minReg=1 regOptional> ----------------- STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB26 regmask=[allInt] minReg=1 last regOptional> STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB42 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB45 regmask=[allInt] minReg=1 regOptional> TryInsert: LocalVar V76: undefined use at 979 LCL_VAR BB47 regmask=[allInt] minReg=1 last regOptional> TryInsert: LocalVar V76: undefined use at 1059 LCL_VAR BB48 regmask=[allInt] minReg=1 last regOptional> TryInsert: LocalVar V76: undefined use at 1123 ----------------- STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB42 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB42 regmask=[allInt] minReg=1> LCL_VAR BB42 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1 last regOptional> ----------------- STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB47 regmask=[allInt] minReg=1> STORE_LCL_VAR BB54 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB57 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB24 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB42 regmask=[allInt] minReg=1> BB43 regmask=[allInt] minReg=1 regOptional> ----------------- BB00 regmask=[rcx] minReg=1 fixed regOptional> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB03 regmask=[rcx] minReg=1 fixed> LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB19 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB44 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB47 regmask=[allInt] minReg=1> LCL_VAR BB47 regmask=[allInt] minReg=1> LCL_VAR BB47 regmask=[allInt] minReg=1> LCL_VAR BB48 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[rcx] minReg=1 fixed> LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB54 regmask=[allInt] minReg=1> LCL_VAR BB54 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB57 regmask=[rcx] minReg=1 fixed> LCL_VAR BB60 regmask=[allInt] minReg=1> LCL_VAR BB64 regmask=[allInt] minReg=1> BB69 regmask=[allInt] minReg=1 regOptional> BB69 regmask=[allInt] minReg=1 regOptional> BB69 regmask=[allInt] minReg=1 regOptional> ----------------- STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[rax] minReg=1 fixed> LCL_VAR BB24 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB51 regmask=[allInt] minReg=1> LCL_VAR BB51 regmask=[rax] minReg=1 fixed> LCL_VAR BB55 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1 last> LCL_VAR BB29 regmask=[allInt] minReg=1 last> TryInsert: LocalVar V65: undefined use at 693 ----------------- STORE_LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB39 regmask=[allInt] minReg=1 last> LCL_VAR BB42 regmask=[allInt] minReg=1 last> TryInsert: LocalVar V66: undefined use at 911 ----------------- STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> STORE_LCL_VAR BB36 regmask=[allInt] minReg=1> LCL_VAR BB37 regmask=[r11] minReg=1 fixed> LCL_VAR BB37 regmask=[allInt] minReg=1 last> ----------------- BB00 regmask=[rdx] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB12 regmask=[rdx] minReg=1 fixed> LCL_VAR BB13 regmask=[rcx] minReg=1 fixed> LCL_VAR BB13 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[r8] minReg=1 fixed> LCL_VAR BB37 regmask=[r8] minReg=1 fixed> LCL_VAR BB55 regmask=[rdx] minReg=1 last fixed> LCL_VAR BB63 regmask=[rdx] minReg=1 last fixed> TryInsert: LocalVar V01: undefined use at 1601 LCL_VAR BB67 regmask=[rdx] minReg=1 last fixed> TryInsert: LocalVar V01: undefined use at 1671 ----------------- STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB45 regmask=[allInt] minReg=1 last> LCL_VAR BB49 regmask=[allInt] minReg=1> TryInsert: LocalVar V73: undefined use at 1203 LCL_VAR BB51 regmask=[allInt] minReg=1 last> TryInsert: LocalVar V73: undefined use at 1283 ----------------- STORE_LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB36 regmask=[rcx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB16 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[rcx rbx rbp rsi rdi r8-r15] minReg=1 last delay regOptional> ----------------- STORE_LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB37 regmask=[rdx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB08 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB12 regmask=[rcx] minReg=1 fixed> LCL_VAR BB18 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB37 regmask=[rcx] minReg=1 fixed> LCL_VAR BB56 regmask=[rdx] minReg=1 last fixed> ----------------- BB00 regmask=[r9] minReg=1 fixed regOptional> LCL_VAR BB28 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB30 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB38 regmask=[allInt] minReg=1 regOptional> TryInsert: LocalVar V03: undefined use at 873 LCL_VAR BB40 regmask=[allInt] minReg=1 last regOptional> TryInsert: LocalVar V03: undefined use at 897 BB43 regmask=[allInt] minReg=1 regOptional> TryInsert: LocalVar V03: undefined use at 937 ----------------- BB00 regmask=[r8] minReg=1 fixed regOptional> LCL_VAR BB29 regmask=[rdx] minReg=1 last fixed> LCL_VAR BB39 regmask=[rdx] minReg=1 last fixed> TryInsert: LocalVar V02: undefined use at 887 LCL_VAR BB55 regmask=[rdx] minReg=1 last fixed> TryInsert: LocalVar V02: undefined use at 1435 ----------------- STORE_LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB35 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB22 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[rcx] minReg=1 fixed> LCL_VAR BB25 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> ----------------- STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB16 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB51 regmask=[allInt] minReg=1> LCL_VAR BB51 regmask=[rcx rbx rbp rsi rdi r8-r15] minReg=1 last delay regOptional> ----------------- STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB05 regmask=[rcx] minReg=1 fixed> LCL_VAR BB05 regmask=[rdx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB15 regmask=[rcx] minReg=1 fixed> LCL_VAR BB15 regmask=[rdx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB16 regmask=[allInt] minReg=1> LCL_VAR BB17 regmask=[rcx] minReg=1 fixed> LCL_VAR BB17 regmask=[rdx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1 last regOptional> ----------------- STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1 last regOptional> ----------------- STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1 last regOptional> ----------------- STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 last regOptional> ----------------- STORE_LCL_VAR BB16 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1 last regOptional> ----------------- STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB53 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB45 regmask=[allInt] minReg=1> STORE_LCL_VAR BB54 regmask=[allInt] minReg=1> LCL_VAR BB54 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB12 regmask=[r11] minReg=1 fixed> LCL_VAR BB12 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB50 regmask=[rcx] minReg=1 fixed> LCL_VAR BB50 regmask=[rdx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB51 regmask=[allInt] minReg=1> LCL_VAR BB52 regmask=[rcx] minReg=1 fixed> LCL_VAR BB52 regmask=[rdx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB47 regmask=[allInt] minReg=1> LCL_VAR BB47 regmask=[allInt] minReg=1> LCL_VAR BB47 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB07 regmask=[rdx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[rcx] minReg=1 fixed> LCL_VAR BB55 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB19 regmask=[allInt] minReg=1> LCL_VAR BB19 regmask=[allInt] minReg=1> LCL_VAR BB21 regmask=[rcx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB11 regmask=[rcx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB51 regmask=[allInt] minReg=1> LCL_VAR BB51 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB53 regmask=[allInt] minReg=1> LCL_VAR BB53 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB12 regmask=[allInt] minReg=1> STORE_LCL_VAR BB13 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> LCL_VAR BB22 regmask=[rcx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB46 regmask=[rdx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1 last regOptional> ----------------- STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB51 regmask=[allInt] minReg=1 last regOptional> ----------------- STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1 last regOptional> ----------------- STORE_LCL_VAR BB51 regmask=[allInt] minReg=1> LCL_VAR BB51 regmask=[allInt] minReg=1 last regOptional> ----------------- STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[rdx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB53 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB48 regmask=[allInt] minReg=1> LCL_VAR BB48 regmask=[allInt] minReg=1> LCL_VAR BB54 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB53 regmask=[allInt] minReg=1 last regOptional> ----------------- STORE_LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB48 regmask=[allInt] minReg=1> LCL_VAR BB48 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[rcx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB10 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB19 regmask=[allInt] minReg=1> LCL_VAR BB19 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB20 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB53 regmask=[allInt] minReg=1> LCL_VAR BB53 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB64 regmask=[allInt] minReg=1> LCL_VAR BB64 regmask=[allInt] minReg=1> LCL_VAR BB65 regmask=[allInt] minReg=1 last> LCL_VAR BB66 regmask=[rcx] minReg=1 last fixed> TryInsert: LocalVar V21: undefined use at 1653 ----------------- STORE_LCL_VAR BB60 regmask=[allInt] minReg=1> LCL_VAR BB60 regmask=[allInt] minReg=1> LCL_VAR BB61 regmask=[allInt] minReg=1 last> LCL_VAR BB62 regmask=[rcx] minReg=1 last fixed> TryInsert: LocalVar V26: undefined use at 1583 ----------------- STORE_LCL_VAR BB65 regmask=[allInt] minReg=1> STORE_LCL_VAR BB66 regmask=[allInt] minReg=1> LCL_VAR BB67 regmask=[rcx] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB61 regmask=[allInt] minReg=1> STORE_LCL_VAR BB62 regmask=[allInt] minReg=1> LCL_VAR BB63 regmask=[rcx] minReg=1 last fixed> TUPLE STYLE DUMP WITH REF POSITIONS Incoming Parameters: V00 V01 V03 V02 BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} ===== N003. IL_OFFSET IL offset: 0x0 N005. V01(L1) N007. CNS_INT null N009. EQ Use:(#5) N011. JTRUE BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ===== N015. IL_OFFSET IL offset: 0xe N017. V00(L0) N019. LEA(b+8) N021. IND N023. CNS_INT null N025. NE Use:(#7) N027. JTRUE BB03 [016..01E), preds={BB02} succs={BB04} ===== N031. V00(L0) N033. PUTARG_REG Use:(#10) Fixed:rcx(#9) Def:(#12) rcx Pref: N035. CNS_INT 0 Def:(#13) N037. PUTARG_REG Use:(#15) Fixed:rdx(#14) * Def:(#17) rdx N039. CALL Use:(#19) Fixed:rcx(#18) * Use:(#21) Fixed:rdx(#20) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#30) rax LocalDefUse * BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ===== N043. IL_OFFSET IL offset: 0x1e N045. V00(L0) N047. LEA(b+8) N049. IND N051. CNS_INT null N053. NE Use:(#32) Def:(#33) Pref: N055. V33(L26) Use:(#34) * Def:(#35) N057. IL_OFFSET IL offset: 0x1e N059. CNS_INT(h) 0xD1FFAB1E [ICON_STR_HDL] Def:(#36) N061. IND Use:(#37) * Def:(#38) Pref: N063. V73(L61) Use:(#39) * Def:(#40) Pref: N065. IL_OFFSET IL offset: 0x1e N067. V73(L61) N069. V35(L27) Use:(#41) Def:(#42) N071. IL_OFFSET IL offset: 0x1e N073. V33(L26) N075. CNS_INT 0 N077. NE Use:(#43) * N079. JTRUE BB05 [01E..01F), preds={BB04} succs={BB06} ===== N083. IL_OFFSET IL offset: 0x1e N085. V35(L27) N087. PUTARG_REG Use:(#46) Fixed:rcx(#45) Def:(#48) rcx Pref: N089. V35(L27) N091. PUTARG_REG Use:(#50) Fixed:rdx(#49) * Def:(#52) rdx N093. CALL Use:(#54) Fixed:rcx(#53) * Use:(#56) Fixed:rdx(#55) * Kill: rax rcx rdx r8 r9 r10 r11 BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} ===== N097. IL_OFFSET IL offset: 0x2c N099. V00(L0) N101. LEA(b+16) N103. IND Use:(#65) Def:(#66) Pref: N105. V04(L4) Use:(#67) * Def:(#68) N107. IL_OFFSET IL offset: 0x33 N109. V04(L4) N111. CNS_INT null N113. NE Use:(#69) Def:(#70) Pref: N115. V36(L28) Use:(#71) * Def:(#72) N117. IL_OFFSET IL offset: 0x33 N119. V73(L61) N121. V37(L29) Use:(#73) Def:(#74) N123. IL_OFFSET IL offset: 0x33 N125. V36(L28) N127. CNS_INT 0 N129. NE Use:(#75) * N131. JTRUE BB07 [033..034), preds={BB06} succs={BB08} ===== N135. IL_OFFSET IL offset: 0x33 N137. CNS_INT(h) 0xD1FFAB1E "expected entries to be non-null" Def:(#77) N139. IND Use:(#78) * Def:(#79) N141. PUTARG_REG Use:(#81) Fixed:rcx(#80) * Def:(#83) rcx N143. V37(L29) N145. PUTARG_REG Use:(#85) Fixed:rdx(#84) * Def:(#87) rdx N147. CALL Use:(#89) Fixed:rcx(#88) * Use:(#91) Fixed:rdx(#90) * Kill: rax rcx rdx r8 r9 r10 r11 BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} ===== N151. IL_OFFSET IL offset: 0x41 N153. V00(L0) N155. LEA(b+24) N157. IND Use:(#100) Def:(#101) Pref: N159. V05(L5) Use:(#102) * Def:(#103) N161. IL_OFFSET IL offset: 0x48 N163. V05(L5) N165. CNS_INT null N167. EQ Use:(#104) N169. JTRUE BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} ===== N173. IL_OFFSET IL offset: 0x4b N175. V00(L0) N177. IND Use:(#106) Def:(#107) Pref: N179. V29(L24) Use:(#108) * Def:(#109) N181. V29(L24) N183. LEA(b+56) N185. IND Use:(#110) Def:(#111) N187. IND Use:(#112) * Def:(#113) N189. LEA(b+64) N191. IND Use:(#114) * Def:(#115) Pref: N193. V68(L56) Use:(#116) * Def:(#117) Pref: N195. V68(L56) N197. CNS_INT 0 N199. EQ Use:(#118) N201. JTRUE BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} ===== N205. V68(L56) N207. V31(L25) Use:(#120) * Def:(#121) BB11 [???..???), preds={BB09} succs={BB12} ===== N211. V29(L24) N213. PUTARG_REG Use:(#124) Fixed:rcx(#123) * Def:(#126) rcx N215. CNS_INT(h) 0xd1ffab1e global ptr Def:(#127) N217. PUTARG_REG Use:(#129) Fixed:rdx(#128) * Def:(#131) rdx N219. CALL help Use:(#133) Fixed:rcx(#132) * Use:(#135) Fixed:rdx(#134) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#144) rax Pref: N221. V31(L25) Use:(#145) * Def:(#146) BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} ===== N225. V05(L5) N227. PUTARG_REG Use:(#149) Fixed:rcx(#148) Def:(#151) rcx Pref: N229. V31(L25) N231. PUTARG_REG Use:(#153) Fixed:r11(#152) Def:(#155) r11 Pref: N233. V01(L1) N235. PUTARG_REG Use:(#157) Fixed:rdx(#156) Def:(#159) rdx Pref: N237. V31(L25) N239. IND N241. CALL ind stub Use:(#161) Fixed:rcx(#160) * Use:(#163) Fixed:r11(#162) * Use:(#165) Fixed:rdx(#164) * Use:(#166) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#175) rax Pref: N243. V15(L14) Use:(#176) * Def:(#177) Pref: BB13 [054..061), preds={BB08} succs={BB14} ===== N247. IL_OFFSET IL offset: 0x54 N249. V01(L1) N251. PUTARG_REG Use:(#180) Fixed:rcx(#179) Def:(#182) rcx Pref: N253. V01(L1) N255. IND Use:(#183) Def:(#184) N257. LEA(b+72) N259. IND Use:(#185) * Def:(#186) N261. LEA(b+24) N263. IND N265. CALLV vt-ind Use:(#188) Fixed:rcx(#187) * Use:(#189) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#198) rax Pref: N267. V15(L14) Use:(#199) * Def:(#200) Pref: BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ===== N271. V15(L14) N273. V06(L6) Use:(#202) * Def:(#203) N275. IL_OFFSET IL offset: 0x62 N277. CNS_INT 0 Def:(#204) Pref: N279. V07(L7) Use:(#205) * Def:(#206) Pref: N281. IL_OFFSET IL offset: 0x64 N283. V00(L0) N285. LEA(b+8) N287. IND Use:(#207) Def:(#208) Pref: N289. V39(L31) Use:(#209) * Def:(#210) N291. IL_OFFSET IL offset: 0x64 N293. V39(L31) N295. LEA(b+8) N297. IND Use:(#211) Def:(#212) Pref: N299. V40(L32) Use:(#213) * Def:(#214) N301. IL_OFFSET IL offset: 0x64 N303. V00(L0) N305. LEA(b+48) N307. IND Use:(#215) Def:(#216) Pref: N309. V41(L33) Use:(#217) * Def:(#218) Pref: N311. IL_OFFSET IL offset: 0x64 N313. V40(L32) N315. CNS_INT 0x7FFFFFFF N317. LE Use:(#219) Def:(#220) Pref: N319. V43(L35) Use:(#221) * Def:(#222) N321. IL_OFFSET IL offset: 0x64 N323. IL_OFFSET IL offset: 0x64 N325. V73(L61) N327. V45(L36) Use:(#223) Def:(#224) N329. IL_OFFSET IL offset: 0x64 N331. V43(L35) N333. CNS_INT 0 N335. NE Use:(#225) * N337. JTRUE BB15 [064..065), preds={BB14} succs={BB16} ===== N341. IL_OFFSET IL offset: 0x64 N343. V45(L36) N345. PUTARG_REG Use:(#228) Fixed:rcx(#227) Def:(#230) rcx Pref: N347. V45(L36) N349. PUTARG_REG Use:(#232) Fixed:rdx(#231) * Def:(#234) rdx N351. CALL Use:(#236) Fixed:rcx(#235) * Use:(#238) Fixed:rdx(#237) * Kill: rax rcx rdx r8 r9 r10 r11 BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} ===== N355. IL_OFFSET IL offset: 0x64 N357. V41(L33) N359. V06(L6) N361. CAST Use:(#247) Def:(#248) Pref: N363. MUL Use:(#249) * Use:(#250) * Def:(#251) Pref: N365. CNS_INT 32 N367. RSZ Use:(#252) * Def:(#253) Pref: N369. CNS_INT 1 N371. ADD Use:(#254) * Def:(#255) Pref: N373. V40(L32) N375. CAST Use:(#256) Def:(#257) Pref: N377. MUL Use:(#258) * Use:(#259) * Def:(#260) Pref: N379. CNS_INT 32 N381. RSZ Use:(#261) * Def:(#262) N383. CAST Use:(#263) * Def:(#264) Pref: N385. V42(L34) Use:(#265) * Def:(#266) N387. IL_OFFSET IL offset: 0x64 N389. V06(L6) N391. V40(L32) N393. UMOD Use:(#268) Fixed:rax(#267) Use:(#269) * Kill: rax rdx Def:(#273) rdx N395. V42(L34) N397. EQ Use:(#274) * Use:(#275) Def:(#276) Pref: N399. V46(L37) Use:(#277) * Def:(#278) N401. IL_OFFSET IL offset: 0x64 N403. IL_OFFSET IL offset: 0x64 N405. V73(L61) N407. V48(L38) Use:(#279) Def:(#280) N409. IL_OFFSET IL offset: 0x64 N411. V46(L37) N413. CNS_INT 0 N415. NE Use:(#281) * N417. JTRUE BB17 [064..065), preds={BB16} succs={BB18} ===== N421. IL_OFFSET IL offset: 0x64 N423. V48(L38) N425. PUTARG_REG Use:(#284) Fixed:rcx(#283) Def:(#286) rcx Pref: N427. V48(L38) N429. PUTARG_REG Use:(#288) Fixed:rdx(#287) * Def:(#290) rdx N431. CALL Use:(#292) Fixed:rcx(#291) * Use:(#294) Fixed:rdx(#293) * Kill: rax rcx rdx r8 r9 r10 r11 BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} ===== N435. IL_OFFSET IL offset: 0x64 N437. V42(L34) N439. V39(L31) N441. LEA(b+8) N443. IND N445. ARR_BOUNDS_CHECK_Rng -> BB69 Use:(#303) Use:(#304) N447. V39(L31) N449. V42(L34) N451. CAST Use:(#305) * Def:(#306) N453. LEA(b+(i*4)+16) Use:(#307) * Use:(#308) * Def:(#309) Pref: N455. V38(L30) Use:(#310) * Def:(#311) Pref: N457. V38(L30) N459. V08(L8) Use:(#312) * Def:(#313) N461. IL_OFFSET IL offset: 0x6d N463. V08(L8) N465. IND Use:(#314) Def:(#315) Pref: N467. CNS_INT -1 N469. ADD Use:(#316) * Def:(#317) Pref: N471. V09(L9) Use:(#318) * Def:(#319) N473. IL_OFFSET IL offset: 0x74 N475. V05(L5) N477. CNS_INT null N479. NE Use:(#320) N481. JTRUE BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} ===== N485. IL_OFFSET IL offset: 0xff N487. V00(L0) N489. IND Use:(#322) Def:(#323) Pref: N491. V24(L20) Use:(#324) * Def:(#325) N493. V24(L20) N495. LEA(b+56) N497. IND Use:(#326) Def:(#327) N499. IND Use:(#328) * Def:(#329) N501. LEA(b+32) N503. IND Use:(#330) * Def:(#331) Pref: N505. V69(L57) Use:(#332) * Def:(#333) Pref: N507. V69(L57) N509. CNS_INT 0 N511. EQ Use:(#334) N513. JTRUE BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} ===== N517. V69(L57) N519. V25(L21) Use:(#336) * Def:(#337) BB21 [???..???), preds={BB19} succs={BB22} ===== N523. V24(L20) N525. PUTARG_REG Use:(#340) Fixed:rcx(#339) * Def:(#342) rcx N527. CNS_INT(h) 0xd1ffab1e global ptr Def:(#343) N529. PUTARG_REG Use:(#345) Fixed:rdx(#344) * Def:(#347) rdx N531. CALL help Use:(#349) Fixed:rcx(#348) * Use:(#351) Fixed:rdx(#350) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#360) rax Pref: N533. V25(L21) Use:(#361) * Def:(#362) BB22 [???..106), preds={BB20,BB21} succs={BB23} ===== N537. V25(L21) N539. PUTARG_REG Use:(#365) Fixed:rcx(#364) * Def:(#367) rcx N541. CALL Use:(#369) Fixed:rcx(#368) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#378) rax Pref: N543. V12(L12) Use:(#379) * Def:(#380) BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} ===== N547. IL_OFFSET IL offset: 0x106 N549. V04(L4) N551. LEA(b+8) N553. IND Use:(#382) Def:(#383) Pref: N555. V76(L64) Use:(#384) * Def:(#385) N557. V76(L64) N559. V09(L9) N561. LE Use:(#386) Use:(#387) N563. JTRUE BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} ===== N567. IL_OFFSET IL offset: 0x110 N569. V04(L4) N571. V09(L9) N573. CAST Use:(#389) * Def:(#390) N575. CNS_INT 3 N577. MUL Use:(#391) * Def:(#392) Pref: N579. V70(L58) Use:(#393) * Def:(#394) N581. V70(L58) N583. LEA(b+(i*8)+16) Use:(#395) Use:(#396) Def:(#397) Pref: N585. V65(L53) Use:(#398) * Def:(#399) N587. V65(L53) N589. LEA(b+16) N591. IND N593. V06(L6) N595. NE Use:(#400) Use:(#401) N597. JTRUE BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} ===== N601. IL_OFFSET IL offset: 0x120 N603. V04(L4) N605. V70(L58) N607. LEA(b+(i*8)+16) N609. IND Use:(#403) Use:(#404) * Def:(#405) N611. PUTARG_REG Use:(#407) Fixed:rdx(#406) * Def:(#409) rdx N613. V12(L12) N615. PUTARG_REG Use:(#411) Fixed:rcx(#410) Def:(#413) rcx Pref: N617. V01(L1) N619. PUTARG_REG Use:(#415) Fixed:r8(#414) Def:(#417) r8 Pref: N621. V12(L12) N623. IND Use:(#418) Def:(#419) N625. LEA(b+72) N627. IND Use:(#420) * Def:(#421) N629. LEA(b+32) N631. IND N633. CALLV vt-ind Use:(#423) Fixed:rdx(#422) * Use:(#425) Fixed:rcx(#424) * Use:(#427) Fixed:r8(#426) * Use:(#428) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#437) rax N635. CNS_INT 0 N637. NE Use:(#438) * N639. JTRUE BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} ===== N643. IL_OFFSET IL offset: 0x157 N645. V65(L53) N647. LEA(b+20) N649. IND Use:(#440) * Def:(#441) Pref: N651. V09(L9) Use:(#442) * Def:(#443) N653. IL_OFFSET IL offset: 0x166 N655. V07(L7) N657. CNS_INT 1 N659. ADD Use:(#444) * Def:(#445) Pref: N661. V07(L7) Use:(#446) * Def:(#447) Pref: N663. IL_OFFSET IL offset: 0x16a N665. V76(L64) N667. V07(L7) N669. LT Use:(#448) * Use:(#449) N671. JTRUE BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} ===== Exposed use of V07 at #451 Exposed use of V04 at #452 Exposed use of V09 at #453 Exposed use of V06 at #454 Exposed use of V73 at #455 Exposed use of V05 at #456 Exposed use of V12 at #457 Exposed use of V08 at #458 BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} ===== N677. IL_OFFSET IL offset: 0x137 N679. V03(L3) N681. CNS_INT 1 N683. NE Use:(#460) N685. JTRUE BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} ===== N689. IL_OFFSET IL offset: 0x13b N691. V65(L53) N693. LEA(b+8) Use:(#462) * Def:(#463) N695. V02(L2) N697. STOREIND Use:(#465) Fixed:rcx(#464) * Use:(#467) Fixed:rdx(#466) * Kill: rax rcx rdx r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5 BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} ===== N701. IL_OFFSET IL offset: 0x14b N703. V03(L3) N705. CNS_INT 2 N707. EQ Use:(#482) * N709. JTRUE BB31 [???..???) (return), preds={BB30,BB41} succs={} ===== N713. CNS_INT 0 Def:(#484) N715. RETURN Use:(#486) Fixed:rax(#485) * BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} ===== N719. IL_OFFSET IL offset: 0x177 N721. V04(L4) N723. LEA(b+8) N725. IND Use:(#488) Def:(#489) Pref: N727. V76(L64) Use:(#490) * Def:(#491) N729. V76(L64) N731. V09(L9) N733. LE Use:(#492) Use:(#493) N735. JTRUE BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} ===== N739. IL_OFFSET IL offset: 0x17e N741. V04(L4) N743. V09(L9) N745. CAST Use:(#495) * Def:(#496) N747. CNS_INT 3 N749. MUL Use:(#497) * Def:(#498) Pref: N751. V71(L59) Use:(#499) * Def:(#500) N753. V71(L59) N755. LEA(b+(i*8)+16) Use:(#501) Use:(#502) Def:(#503) Pref: N757. V66(L54) Use:(#504) * Def:(#505) N759. V66(L54) N761. LEA(b+16) N763. IND N765. V06(L6) N767. NE Use:(#506) Use:(#507) N769. JTRUE BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} ===== N773. IL_OFFSET IL offset: 0x18e N775. V04(L4) N777. V71(L59) N779. LEA(b+(i*8)+16) N781. IND Use:(#509) Use:(#510) * Def:(#511) Pref: N783. V17(L16) Use:(#512) * Def:(#513) N785. IL_OFFSET IL offset: 0x18e N787. V00(L0) N789. IND Use:(#514) Def:(#515) Pref: N791. V16(L15) Use:(#516) * Def:(#517) N793. V16(L15) N795. LEA(b+56) N797. IND Use:(#518) Def:(#519) N799. IND Use:(#520) * Def:(#521) N801. LEA(b+48) N803. IND Use:(#522) * Def:(#523) Pref: N805. V67(L55) Use:(#524) * Def:(#525) Pref: N807. V67(L55) N809. CNS_INT 0 N811. EQ Use:(#526) N813. JTRUE BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} ===== N817. V67(L55) N819. V19(L17) Use:(#528) * Def:(#529) BB36 [???..???), preds={BB34} succs={BB37} ===== N823. V16(L15) N825. PUTARG_REG Use:(#532) Fixed:rcx(#531) * Def:(#534) rcx N827. CNS_INT(h) 0xd1ffab1e global ptr Def:(#535) N829. PUTARG_REG Use:(#537) Fixed:rdx(#536) * Def:(#539) rdx N831. CALL help Use:(#541) Fixed:rcx(#540) * Use:(#543) Fixed:rdx(#542) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#552) rax Pref: N833. V19(L17) Use:(#553) * Def:(#554) BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} ===== N837. V05(L5) N839. PUTARG_REG Use:(#557) Fixed:rcx(#556) Def:(#559) rcx Pref: N841. V19(L17) N843. PUTARG_REG Use:(#561) Fixed:r11(#560) Def:(#563) r11 Pref: N845. V17(L16) N847. PUTARG_REG Use:(#565) Fixed:rdx(#564) * Def:(#567) rdx N849. V01(L1) N851. PUTARG_REG Use:(#569) Fixed:r8(#568) Def:(#571) r8 Pref: N853. V19(L17) N855. IND N857. CALL ind stub Use:(#573) Fixed:rcx(#572) * Use:(#575) Fixed:r11(#574) * Use:(#577) Fixed:rdx(#576) * Use:(#579) Fixed:r8(#578) * Use:(#580) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#589) rax N859. CNS_INT 0 N861. EQ Use:(#590) * N863. JTRUE BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} ===== N867. IL_OFFSET IL offset: 0x1a4 N869. V03(L3) N871. CNS_INT 1 N873. NE Use:(#592) N875. JTRUE BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} ===== N879. IL_OFFSET IL offset: 0x1a8 N881. V66(L54) N883. LEA(b+8) Use:(#594) * Def:(#595) N885. V02(L2) N887. STOREIND Use:(#597) Fixed:rcx(#596) * Use:(#599) Fixed:rdx(#598) * Kill: rax rcx rdx r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5 BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} ===== N891. IL_OFFSET IL offset: 0x1b8 N893. V03(L3) N895. CNS_INT 2 N897. EQ Use:(#614) * N899. JTRUE BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} ===== BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} ===== N905. IL_OFFSET IL offset: 0x1c4 N907. V66(L54) N909. LEA(b+20) N911. IND Use:(#617) * Def:(#618) Pref: N913. V09(L9) Use:(#619) * Def:(#620) N915. IL_OFFSET IL offset: 0x1d3 N917. V07(L7) N919. CNS_INT 1 N921. ADD Use:(#621) * Def:(#622) Pref: N923. V07(L7) Use:(#623) * Def:(#624) Pref: N925. IL_OFFSET IL offset: 0x1d7 N927. V76(L64) N929. V07(L7) N931. LT Use:(#625) * Use:(#626) N933. JTRUE BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} ===== Exposed use of V09 at #628 Exposed use of V03 at #629 BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} ===== N939. IL_OFFSET IL offset: 0x1e4 N941. V00(L0) N943. LEA(b+64) N945. IND N947. CNS_INT 0 N949. LE Use:(#631) N951. JTRUE BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} ===== N955. IL_OFFSET IL offset: 0x1ed N957. V00(L0) N959. LEA(b+60) N961. IND Use:(#633) Def:(#634) Pref: N963. V74(L62) Use:(#635) * Def:(#636) Pref: N965. V74(L62) N967. V10(L10) Use:(#637) Def:(#638) Pref: N969. IL_OFFSET IL offset: 0x1f5 N971. V74(L62) N973. V62(L50) Use:(#639) * Def:(#640) N975. V62(L50) N977. V76(L64) N979. ARR_BOUNDS_CHECK_Rng -> BB69 Use:(#641) Use:(#642) N981. V04(L4) N983. V62(L50) N985. CAST Use:(#643) * Def:(#644) N987. CNS_INT 3 N989. MUL Use:(#645) * Def:(#646) N991. LEA(b+(i*8)+36) N993. IND Use:(#647) Use:(#648) * Def:(#649) N995. NEG Use:(#650) * Def:(#651) Pref: N997. CNS_INT -3 N999. ADD Use:(#652) * Def:(#653) N1001. CNS_INT -1 N1003. GE Use:(#654) * Def:(#655) Pref: N1005. V49(L39) Use:(#656) * Def:(#657) N1007. IL_OFFSET IL offset: 0x1f5 N1009. V73(L61) N1011. V50(L40) Use:(#658) * Def:(#659) N1013. IL_OFFSET IL offset: 0x1f5 N1015. V49(L39) N1017. CNS_INT 0 N1019. NE Use:(#660) * N1021. JTRUE BB46 [1F5..1F6), preds={BB45} succs={BB47} ===== N1025. IL_OFFSET IL offset: 0x1f5 N1027. CNS_INT(h) 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" Def:(#662) N1029. IND Use:(#663) * Def:(#664) N1031. PUTARG_REG Use:(#666) Fixed:rcx(#665) * Def:(#668) rcx N1033. V50(L40) N1035. PUTARG_REG Use:(#670) Fixed:rdx(#669) * Def:(#672) rdx N1037. CALL Use:(#674) Fixed:rcx(#673) * Use:(#676) Fixed:rdx(#675) * Kill: rax rcx rdx r8 r9 r10 r11 BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} ===== N1041. IL_OFFSET IL offset: 0x219 N1043. V00(L0) N1045. LEA(b+60) N1047. V00(L0) N1049. LEA(b+60) N1051. IND Use:(#685) Def:(#686) Pref: N1053. V63(L51) Use:(#687) * Def:(#688) N1055. V63(L51) N1057. V76(L64) N1059. ARR_BOUNDS_CHECK_Rng -> BB69 Use:(#689) Use:(#690) * N1061. V04(L4) N1063. V63(L51) N1065. CAST Use:(#691) * Def:(#692) N1067. CNS_INT 3 N1069. MUL Use:(#693) * Def:(#694) N1071. LEA(b+(i*8)+36) N1073. IND Use:(#695) Use:(#696) * Def:(#697) N1075. NEG Use:(#698) * Def:(#699) Pref: N1077. CNS_INT -3 N1079. ADD Use:(#700) * Def:(#701) N1081. STOREIND Use:(#702) Use:(#703) * N1083. IL_OFFSET IL offset: 0x233 N1085. V00(L0) N1087. LEA(b+64) N1089. IND N1091. CNS_INT -1 N1093. ADD N1095. V00(L0) N1097. LEA(b+64) N1099. STOREIND Use:(#704) BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} ===== N1103. IL_OFFSET IL offset: 0x243 N1105. V00(L0) N1107. LEA(b+56) N1109. IND Use:(#706) Def:(#707) Pref: N1111. V75(L63) Use:(#708) * Def:(#709) N1113. V75(L63) N1115. V13(L13) Use:(#710) Def:(#711) Pref: N1117. IL_OFFSET IL offset: 0x24b N1119. V76(L64) N1121. V13(L13) N1123. NE Use:(#712) * Use:(#713) N1125. JTRUE BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ===== N1129. IL_OFFSET IL offset: 0x252 N1131. V75(L63) N1133. PUTARG_REG Use:(#716) Fixed:rcx(#715) * Def:(#718) rcx N1135. CALL Use:(#720) Fixed:rcx(#719) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#729) rax Pref: N1137. V64(L52) Use:(#730) * Def:(#731) N1139. V64(L52) N1141. PUTARG_REG Use:(#733) Fixed:rdx(#732) * Def:(#735) rdx N1143. V00(L0) N1145. PUTARG_REG Use:(#737) Fixed:rcx(#736) Def:(#739) rcx Pref: N1147. CNS_INT 0 Def:(#740) N1149. PUTARG_REG Use:(#742) Fixed:r8(#741) * Def:(#744) r8 N1151. CALL Use:(#746) Fixed:rdx(#745) * Use:(#748) Fixed:rcx(#747) * Use:(#750) Fixed:r8(#749) * Kill: rax rcx rdx r8 r9 r10 r11 N1153. IL_OFFSET IL offset: 0x258 N1155. V00(L0) N1157. LEA(b+8) N1159. IND Use:(#758) Def:(#759) Pref: N1161. V52(L42) Use:(#760) * Def:(#761) N1163. IL_OFFSET IL offset: 0x258 N1165. V52(L42) N1167. LEA(b+8) N1169. IND Use:(#762) Def:(#763) Pref: N1171. V72(L60) Use:(#764) * Def:(#765) N1173. V72(L60) N1175. V53(L43) Use:(#766) Def:(#767) N1177. IL_OFFSET IL offset: 0x258 N1179. V00(L0) N1181. LEA(b+48) N1183. IND Use:(#768) Def:(#769) Pref: N1185. V54(L44) Use:(#770) * Def:(#771) Pref: N1187. IL_OFFSET IL offset: 0x258 N1189. V53(L43) N1191. CNS_INT 0x7FFFFFFF N1193. LE Use:(#772) Def:(#773) Pref: N1195. V56(L46) Use:(#774) * Def:(#775) N1197. IL_OFFSET IL offset: 0x258 N1199. IL_OFFSET IL offset: 0x258 N1201. V73(L61) N1203. V58(L47) Use:(#776) Def:(#777) N1205. IL_OFFSET IL offset: 0x258 N1207. V56(L46) N1209. CNS_INT 0 N1211. NE Use:(#778) * N1213. JTRUE BB50 [258..259), preds={BB49} succs={BB51} ===== N1217. IL_OFFSET IL offset: 0x258 N1219. V58(L47) N1221. PUTARG_REG Use:(#781) Fixed:rcx(#780) Def:(#783) rcx Pref: N1223. V58(L47) N1225. PUTARG_REG Use:(#785) Fixed:rdx(#784) * Def:(#787) rdx N1227. CALL Use:(#789) Fixed:rcx(#788) * Use:(#791) Fixed:rdx(#790) * Kill: rax rcx rdx r8 r9 r10 r11 BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} ===== N1231. IL_OFFSET IL offset: 0x258 N1233. V54(L44) N1235. V06(L6) N1237. CAST Use:(#800) Def:(#801) Pref: N1239. MUL Use:(#802) * Use:(#803) * Def:(#804) Pref: N1241. CNS_INT 32 N1243. RSZ Use:(#805) * Def:(#806) Pref: N1245. CNS_INT 1 N1247. ADD Use:(#807) * Def:(#808) Pref: N1249. V53(L43) N1251. CAST Use:(#809) Def:(#810) Pref: N1253. MUL Use:(#811) * Use:(#812) * Def:(#813) Pref: N1255. CNS_INT 32 N1257. RSZ Use:(#814) * Def:(#815) N1259. CAST Use:(#816) * Def:(#817) Pref: N1261. V55(L45) Use:(#818) * Def:(#819) N1263. IL_OFFSET IL offset: 0x258 N1265. V06(L6) N1267. V53(L43) N1269. UMOD Use:(#821) Fixed:rax(#820) Use:(#822) * Kill: rax rdx Def:(#826) rdx N1271. V55(L45) N1273. EQ Use:(#827) * Use:(#828) Def:(#829) Pref: N1275. V59(L48) Use:(#830) * Def:(#831) N1277. IL_OFFSET IL offset: 0x258 N1279. IL_OFFSET IL offset: 0x258 N1281. V73(L61) N1283. V61(L49) Use:(#832) * Def:(#833) N1285. IL_OFFSET IL offset: 0x258 N1287. V59(L48) N1289. CNS_INT 0 N1291. NE Use:(#834) * N1293. JTRUE BB52 [258..259), preds={BB51} succs={BB53} ===== N1297. IL_OFFSET IL offset: 0x258 N1299. V61(L49) N1301. PUTARG_REG Use:(#837) Fixed:rcx(#836) Def:(#839) rcx Pref: N1303. V61(L49) N1305. PUTARG_REG Use:(#841) Fixed:rdx(#840) * Def:(#843) rdx N1307. CALL Use:(#845) Fixed:rcx(#844) * Use:(#847) Fixed:rdx(#846) * Kill: rax rcx rdx r8 r9 r10 r11 BB53 [258..259), preds={BB51,BB52} succs={BB54} ===== N1311. IL_OFFSET IL offset: 0x258 N1313. V55(L45) N1315. V72(L60) N1317. ARR_BOUNDS_CHECK_Rng -> BB69 Use:(#856) Use:(#857) * N1319. V52(L42) N1321. V55(L45) N1323. CAST Use:(#858) * Def:(#859) N1325. LEA(b+(i*4)+16) Use:(#860) * Use:(#861) * Def:(#862) Pref: N1327. V51(L41) Use:(#863) * Def:(#864) Pref: N1329. V51(L41) N1331. V08(L8) Use:(#865) * Def:(#866) BB54 [261..276), preds={BB48,BB53} succs={BB55} ===== N1335. IL_OFFSET IL offset: 0x261 N1337. V13(L13) N1339. V10(L10) Use:(#868) * Def:(#869) Pref: N1341. IL_OFFSET IL offset: 0x265 N1343. V10(L10) N1345. CNS_INT 1 N1347. ADD Use:(#870) Def:(#871) N1349. V00(L0) N1351. LEA(b+56) N1353. STOREIND Use:(#872) Use:(#873) * N1355. IL_OFFSET IL offset: 0x26f N1357. V00(L0) N1359. LEA(b+16) N1361. IND Use:(#874) Def:(#875) Pref: N1363. V04(L4) Use:(#876) * Def:(#877) BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} ===== N1367. IL_OFFSET IL offset: 0x276 N1369. V10(L10) N1371. V04(L4) N1373. LEA(b+8) N1375. IND N1377. ARR_BOUNDS_CHECK_Rng -> BB69 Use:(#879) Use:(#880) N1379. V04(L4) N1381. V10(L10) N1383. CAST Use:(#881) Def:(#882) N1385. CNS_INT 3 N1387. MUL Use:(#883) * Def:(#884) N1389. LEA(b+(i*8)+16) Use:(#885) Use:(#886) * Def:(#887) Pref: N1391. V11(L11) Use:(#888) * Def:(#889) N1393. IL_OFFSET IL offset: 0x280 N1395. V11(L11) N1397. LEA(b+16) N1399. V06(L6) N1401. STOREIND Use:(#890) Use:(#891) * N1403. IL_OFFSET IL offset: 0x288 N1405. V08(L8) N1407. IND Use:(#892) Def:(#893) Pref: N1409. CNS_INT -1 N1411. ADD Use:(#894) * Def:(#895) N1413. V11(L11) N1415. LEA(b+20) N1417. STOREIND Use:(#896) Use:(#897) * N1419. IL_OFFSET IL offset: 0x294 N1421. V11(L11) N1423. V01(L1) N1425. STOREIND Use:(#899) Fixed:rcx(#898) Use:(#901) Fixed:rdx(#900) * Kill: rax rcx rdx r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5 N1427. IL_OFFSET IL offset: 0x29c N1429. V11(L11) N1431. LEA(b+8) Use:(#915) * Def:(#916) N1433. V02(L2) N1435. STOREIND Use:(#918) Fixed:rcx(#917) * Use:(#920) Fixed:rdx(#919) * Kill: rax rcx rdx r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5 N1437. IL_OFFSET IL offset: 0x2a4 N1439. V10(L10) N1441. CNS_INT 1 N1443. ADD Use:(#934) * Def:(#935) N1445. V08(L8) N1447. STOREIND Use:(#936) * Use:(#937) * N1449. IL_OFFSET IL offset: 0x2ab N1451. V00(L0) N1453. LEA(b+68) N1455. IND N1457. CNS_INT 1 N1459. ADD N1461. V00(L0) N1463. LEA(b+68) N1465. STOREIND Use:(#938) N1467. IL_OFFSET IL offset: 0x2ca N1469. V07(L7) N1471. CNS_INT 100 N1473. LE Use:(#939) * N1475. JTRUE BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} ===== N1479. IL_OFFSET IL offset: 0x2cf N1481. V05(L5) N1483. PUTARG_REG Use:(#942) Fixed:rdx(#941) * Def:(#944) rdx N1485. CNS_INT(h) 0xd1ffab1e class Def:(#945) N1487. PUTARG_REG Use:(#947) Fixed:rcx(#946) * Def:(#949) rcx N1489. CALL help Use:(#951) Fixed:rdx(#950) * Use:(#953) Fixed:rcx(#952) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#962) rax N1491. CNS_INT null N1493. EQ Use:(#963) * N1495. JTRUE BB57 [2D7..2E3), preds={BB56} succs={BB58} ===== N1499. IL_OFFSET IL offset: 0x2d7 N1501. V04(L4) N1503. LEA(b+8) N1505. IND Use:(#965) * Def:(#966) N1507. PUTARG_REG Use:(#968) Fixed:rdx(#967) * Def:(#970) rdx N1509. V00(L0) N1511. PUTARG_REG Use:(#972) Fixed:rcx(#971) Def:(#974) rcx Pref: N1513. CNS_INT 1 Def:(#975) N1515. PUTARG_REG Use:(#977) Fixed:r8(#976) * Def:(#979) r8 N1517. CALL Use:(#981) Fixed:rdx(#980) * Use:(#983) Fixed:rcx(#982) * Use:(#985) Fixed:r8(#984) * Kill: rax rcx rdx r8 r9 r10 r11 BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} ===== N1521. CNS_INT 1 Def:(#994) N1523. RETURN Use:(#996) Fixed:rax(#995) * BB59 [008..00E) (throw), preds={BB01} succs={} ===== N1527. IL_OFFSET IL offset: 0x8 N1529. CNS_INT 4 Def:(#998) N1531. PUTARG_REG Use:(#1000) Fixed:rcx(#999) * Def:(#1002) rcx N1533. CALL Use:(#1004) Fixed:rcx(#1003) * Kill: rax rcx rdx r8 r9 r10 r11 BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} ===== N1537. IL_OFFSET IL offset: 0x14f N1539. V00(L0) N1541. IND Use:(#1013) Def:(#1014) Pref: N1543. V26(L22) Use:(#1015) * Def:(#1016) N1545. V26(L22) N1547. LEA(b+56) N1549. IND Use:(#1017) Def:(#1018) N1551. IND Use:(#1019) * Def:(#1020) N1553. LEA(b+56) N1555. IND N1557. CNS_INT 0 N1559. EQ Use:(#1021) * N1561. JTRUE BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} ===== N1565. V26(L22) N1567. LEA(b+56) N1569. IND Use:(#1023) * Def:(#1024) N1571. IND Use:(#1025) * Def:(#1026) N1573. LEA(b+56) N1575. IND Use:(#1027) * Def:(#1028) Pref: N1577. V28(L23) Use:(#1029) * Def:(#1030) BB62 [???..???), preds={BB60} succs={BB63} ===== N1581. V26(L22) N1583. PUTARG_REG Use:(#1033) Fixed:rcx(#1032) * Def:(#1035) rcx N1585. CNS_INT(h) 0xd1ffab1e global ptr Def:(#1036) N1587. PUTARG_REG Use:(#1038) Fixed:rdx(#1037) * Def:(#1040) rdx N1589. CALL help Use:(#1042) Fixed:rcx(#1041) * Use:(#1044) Fixed:rdx(#1043) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#1053) rax Pref: N1591. V28(L23) Use:(#1054) * Def:(#1055) BB63 [???..157) (throw), preds={BB61,BB62} succs={} ===== N1595. V28(L23) N1597. PUTARG_REG Use:(#1058) Fixed:rcx(#1057) * Def:(#1060) rcx N1599. V01(L1) N1601. PUTARG_REG Use:(#1062) Fixed:rdx(#1061) * Def:(#1064) rdx N1603. CALL Use:(#1066) Fixed:rcx(#1065) * Use:(#1068) Fixed:rdx(#1067) * Kill: rax rcx rdx r8 r9 r10 r11 BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} ===== N1607. IL_OFFSET IL offset: 0x1bc N1609. V00(L0) N1611. IND Use:(#1077) Def:(#1078) Pref: N1613. V21(L18) Use:(#1079) * Def:(#1080) N1615. V21(L18) N1617. LEA(b+56) N1619. IND Use:(#1081) Def:(#1082) N1621. IND Use:(#1083) * Def:(#1084) N1623. LEA(b+56) N1625. IND N1627. CNS_INT 0 N1629. EQ Use:(#1085) * N1631. JTRUE BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} ===== N1635. V21(L18) N1637. LEA(b+56) N1639. IND Use:(#1087) * Def:(#1088) N1641. IND Use:(#1089) * Def:(#1090) N1643. LEA(b+56) N1645. IND Use:(#1091) * Def:(#1092) Pref: N1647. V23(L19) Use:(#1093) * Def:(#1094) BB66 [???..???), preds={BB64} succs={BB67} ===== N1651. V21(L18) N1653. PUTARG_REG Use:(#1097) Fixed:rcx(#1096) * Def:(#1099) rcx N1655. CNS_INT(h) 0xd1ffab1e global ptr Def:(#1100) N1657. PUTARG_REG Use:(#1102) Fixed:rdx(#1101) * Def:(#1104) rdx N1659. CALL help Use:(#1106) Fixed:rcx(#1105) * Use:(#1108) Fixed:rdx(#1107) * Kill: rax rcx rdx r8 r9 r10 r11 Def:(#1117) rax Pref: N1661. V23(L19) Use:(#1118) * Def:(#1119) BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} ===== N1665. V23(L19) N1667. PUTARG_REG Use:(#1122) Fixed:rcx(#1121) * Def:(#1124) rcx N1669. V01(L1) N1671. PUTARG_REG Use:(#1126) Fixed:rdx(#1125) * Def:(#1128) rdx N1673. CALL Use:(#1130) Fixed:rcx(#1129) * Use:(#1132) Fixed:rdx(#1131) * Kill: rax rcx rdx r8 r9 r10 r11 BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} ===== N1677. IL_OFFSET IL offset: 0x1dd N1679. CALL Kill: rax rcx rdx r8 r9 r10 r11 Dummy def of V00 at #1148 BB69 [???..???) (throw), preds={} succs={} ===== N1683. CALL help Kill: rax rcx rdx r8 r9 r10 r11 Linear scan intervals after buildIntervals: Interval 0: (V00) ref RefPositions {#0@0 #7@25 #10@33 #32@53 #65@103 #100@157 #106@177 #207@287 #215@307 #322@489 #514@789 #631@949 #633@961 #685@1051 #702@1081 #704@1099 #706@1109 #737@1145 #758@1159 #768@1183 #872@1353 #874@1361 #938@1465 #972@1511 #1013@1541 #1077@1611 #1148@1681 #1157@1685 #1158@1685} physReg:rcx Preferences=[rbx rbp rsi rdi r12-r15] Interval 1: (V01) ref RefPositions {#1@0 #5@9 #157@235 #180@251 #183@255 #415@619 #569@851 #901@1425 #1062@1601 #1126@1671} physReg:rdx Preferences=[rbx rbp rsi rdi r12-r15] Interval 2: (V02) ref RefPositions {#3@0 #467@697 #599@887 #920@1435} physReg:r8 Preferences=[rbx rbp rsi rdi r12-r15] Interval 3: (V03) int RefPositions {#2@0 #460@683 #482@707 #592@873 #614@897 #629@937} physReg:r9 Preferences=[rbx rbp rsi rdi r12-r15] Interval 4: (V04) ref RefPositions {#68@106 #69@113 #382@553 #395@583 #403@609 #452@675 #488@725 #501@755 #509@781 #647@993 #695@1073 #877@1364 #880@1377 #885@1389 #965@1505} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 5: (V05) ref RefPositions {#103@160 #104@167 #149@227 #320@479 #456@675 #557@839 #942@1483} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 6: (V06) int RefPositions {#203@274 #247@361 #268@393 #401@595 #454@675 #507@767 #800@1237 #821@1269 #891@1401} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 7: (V07) int RefPositions {#206@280 #444@659 #447@662 #449@669 #451@675 #621@921 #624@924 #626@931 #939@1473} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 8: (V08) byref RefPositions {#313@460 #314@465 #458@675 #866@1332 #892@1407 #936@1447} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 9: (V09) int RefPositions {#319@472 #387@561 #389@573 #443@652 #453@675 #493@733 #495@745 #620@914 #628@937} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 10: (V10) int RefPositions {#638@968 #869@1340 #870@1347 #879@1377 #881@1383 #934@1443} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 11: (V11) byref RefPositions {#889@1392 #890@1401 #896@1417 #899@1425 #915@1431} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 12: (V12) ref RefPositions {#380@544 #411@615 #418@623 #457@675} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 13: (V13) int RefPositions {#711@1116 #713@1123 #868@1339} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 14: (V15) int RefPositions {#177@244 #200@268 #202@273} physReg:NA Preferences=[allInt] RelatedInterval Interval 15: (V16) long RefPositions {#517@792 #518@797 #532@825} physReg:NA Preferences=[rcx] Interval 16: (V17) ref RefPositions {#513@784 #565@847} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 17: (V19) long RefPositions {#529@820 #554@834 #561@843 #580@857} physReg:NA Preferences=[r11] Interval 18: (V21) long RefPositions {#1080@1614 #1081@1619 #1087@1639 #1097@1653} physReg:NA Preferences=[rcx] Interval 19: (V23) long RefPositions {#1094@1648 #1119@1662 #1122@1667} physReg:NA Preferences=[rcx] Interval 20: (V24) long RefPositions {#325@492 #326@497 #340@525} physReg:NA Preferences=[rcx] Interval 21: (V25) long RefPositions {#337@520 #362@534 #365@539} physReg:NA Preferences=[rcx] Interval 22: (V26) long RefPositions {#1016@1544 #1017@1549 #1023@1569 #1033@1583} physReg:NA Preferences=[rcx] Interval 23: (V28) long RefPositions {#1030@1578 #1055@1592 #1058@1597} physReg:NA Preferences=[rcx] Interval 24: (V29) long RefPositions {#109@180 #110@185 #124@213} physReg:NA Preferences=[rcx] Interval 25: (V31) long RefPositions {#121@208 #146@222 #153@231 #166@241} physReg:NA Preferences=[r11] Interval 26: (V33) int RefPositions {#35@56 #43@77} physReg:NA Preferences=[allInt] Interval 27: (V35) ref RefPositions {#42@70 #46@87 #50@91} physReg:NA Preferences=[rcx rdx] Interval 28: (V36) int RefPositions {#72@116 #75@129} physReg:NA Preferences=[allInt] Interval 29: (V37) ref RefPositions {#74@122 #85@145} physReg:NA Preferences=[rdx] Interval 30: (V38) byref RefPositions {#311@456 #312@459} physReg:NA Preferences=[allInt] RelatedInterval Interval 31: (V39) ref RefPositions {#210@290 #211@297 #304@445 #307@453} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 32: (V40) int RefPositions {#214@300 #219@317 #256@375 #269@393} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 33: (V41) long RefPositions {#218@310 #249@363} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 34: (V42) int RefPositions {#266@386 #275@397 #303@445 #305@451} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 35: (V43) int RefPositions {#222@320 #225@335} physReg:NA Preferences=[allInt] Interval 36: (V45) ref RefPositions {#224@328 #228@345 #232@349} physReg:NA Preferences=[rcx rdx] Interval 37: (V46) int RefPositions {#278@400 #281@415} physReg:NA Preferences=[allInt] Interval 38: (V48) ref RefPositions {#280@408 #284@425 #288@429} physReg:NA Preferences=[rcx rdx] Interval 39: (V49) int RefPositions {#657@1006 #660@1019} physReg:NA Preferences=[allInt] Interval 40: (V50) ref RefPositions {#659@1012 #670@1035} physReg:NA Preferences=[rdx] Interval 41: (V51) byref RefPositions {#864@1328 #865@1331} physReg:NA Preferences=[allInt] RelatedInterval Interval 42: (V52) ref RefPositions {#761@1162 #762@1169 #860@1325} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 43: (V53) int RefPositions {#767@1176 #772@1193 #809@1251 #822@1269} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 44: (V54) long RefPositions {#771@1186 #802@1239} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 45: (V55) int RefPositions {#819@1262 #828@1273 #856@1317 #858@1323} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 46: (V56) int RefPositions {#775@1196 #778@1211} physReg:NA Preferences=[allInt] Interval 47: (V58) ref RefPositions {#777@1204 #781@1221 #785@1225} physReg:NA Preferences=[rcx rdx] Interval 48: (V59) int RefPositions {#831@1276 #834@1291} physReg:NA Preferences=[allInt] Interval 49: (V61) ref RefPositions {#833@1284 #837@1301 #841@1305} physReg:NA Preferences=[rcx rdx] Interval 50: (V62) int RefPositions {#640@974 #641@979 #643@985} physReg:NA Preferences=[allInt] Interval 51: (V63) int RefPositions {#688@1054 #689@1059 #691@1065} physReg:NA Preferences=[allInt] Interval 52: (V64) int RefPositions {#731@1138 #733@1141} physReg:NA Preferences=[rdx] Interval 53: (V65) byref RefPositions {#399@586 #400@595 #440@649 #462@693} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 54: (V66) byref RefPositions {#505@758 #506@767 #594@883 #617@911} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 55: (V67) long RefPositions {#525@806 #526@811 #528@819} physReg:NA Preferences=[allInt] RelatedInterval Interval 56: (V68) long RefPositions {#117@194 #118@199 #120@207} physReg:NA Preferences=[allInt] RelatedInterval Interval 57: (V69) long RefPositions {#333@506 #334@511 #336@519} physReg:NA Preferences=[allInt] RelatedInterval Interval 58: (V70) long RefPositions {#394@580 #396@583 #404@609} physReg:NA Preferences=[allInt] Interval 59: (V71) long RefPositions {#500@752 #502@755 #510@781} physReg:NA Preferences=[allInt] Interval 60: (V72) int RefPositions {#765@1172 #766@1175 #857@1317} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 61: (V73) ref RefPositions {#40@64 #41@69 #73@121 #223@327 #279@407 #455@675 #658@1011 #776@1203 #832@1283} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 62: (V74) int RefPositions {#636@964 #637@967 #639@973} physReg:NA Preferences=[allInt] RelatedInterval Interval 63: (V75) int RefPositions {#709@1112 #710@1115 #716@1133} physReg:NA Preferences=[rcx] Interval 64: (V76) int RefPositions {#385@556 #386@561 #448@669 #491@728 #492@733 #625@931 #642@979 #690@1059 #712@1123} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 65: ref (specialPutArg) RefPositions {#12@34 #19@39} physReg:NA Preferences=[rcx] RelatedInterval Interval 66: int (constant) RefPositions {#13@36 #15@37} physReg:NA Preferences=[rdx] Interval 67: int RefPositions {#17@38 #21@39} physReg:NA Preferences=[rdx] Interval 68: int RefPositions {#30@40} physReg:NA Preferences=[rax] Interval 69: int RefPositions {#33@54 #34@55} physReg:NA Preferences=[allInt] RelatedInterval Interval 70: long (constant) RefPositions {#36@60 #37@61} physReg:NA Preferences=[allInt] Interval 71: ref RefPositions {#38@62 #39@63} physReg:NA Preferences=[allInt] RelatedInterval Interval 72: ref (specialPutArg) RefPositions {#48@88 #54@93} physReg:NA Preferences=[rcx] RelatedInterval Interval 73: ref RefPositions {#52@92 #56@93} physReg:NA Preferences=[rdx] Interval 74: ref RefPositions {#66@104 #67@105} physReg:NA Preferences=[allInt] RelatedInterval Interval 75: int RefPositions {#70@114 #71@115} physReg:NA Preferences=[allInt] RelatedInterval Interval 76: long (constant) RefPositions {#77@138 #78@139} physReg:NA Preferences=[allInt] Interval 77: ref RefPositions {#79@140 #81@141} physReg:NA Preferences=[rcx] Interval 78: ref RefPositions {#83@142 #89@147} physReg:NA Preferences=[rcx] Interval 79: ref RefPositions {#87@146 #91@147} physReg:NA Preferences=[rdx] Interval 80: ref RefPositions {#101@158 #102@159} physReg:NA Preferences=[allInt] RelatedInterval Interval 81: long RefPositions {#107@178 #108@179} physReg:NA Preferences=[allInt] RelatedInterval Interval 82: long RefPositions {#111@186 #112@187} physReg:NA Preferences=[allInt] Interval 83: long RefPositions {#113@188 #114@191} physReg:NA Preferences=[allInt] Interval 84: long RefPositions {#115@192 #116@193} physReg:NA Preferences=[allInt] RelatedInterval Interval 85: long RefPositions {#126@214 #133@219} physReg:NA Preferences=[rcx] Interval 86: long (constant) RefPositions {#127@216 #129@217} physReg:NA Preferences=[rdx] Interval 87: long RefPositions {#131@218 #135@219} physReg:NA Preferences=[rdx] Interval 88: long RefPositions {#144@220 #145@221} physReg:NA Preferences=[rax] RelatedInterval Interval 89: ref (specialPutArg) RefPositions {#151@228 #161@241} physReg:NA Preferences=[rcx] RelatedInterval Interval 90: long (specialPutArg) RefPositions {#155@232 #163@241} physReg:NA Preferences=[r11] RelatedInterval Interval 91: ref (specialPutArg) RefPositions {#159@236 #165@241} physReg:NA Preferences=[rdx] RelatedInterval Interval 92: int RefPositions {#175@242 #176@243} physReg:NA Preferences=[rax] RelatedInterval Interval 93: ref (specialPutArg) RefPositions {#182@252 #188@265} physReg:NA Preferences=[rcx] RelatedInterval Interval 94: long RefPositions {#184@256 #185@259} physReg:NA Preferences=[allInt] Interval 95: long RefPositions {#186@260 #189@265} physReg:NA Preferences=[allInt] Interval 96: int RefPositions {#198@266 #199@267} physReg:NA Preferences=[rax] RelatedInterval Interval 97: int (constant) RefPositions {#204@278 #205@279} physReg:NA Preferences=[allInt] RelatedInterval Interval 98: ref RefPositions {#208@288 #209@289} physReg:NA Preferences=[allInt] RelatedInterval Interval 99: int RefPositions {#212@298 #213@299} physReg:NA Preferences=[allInt] RelatedInterval Interval 100: long RefPositions {#216@308 #217@309} physReg:NA Preferences=[allInt] RelatedInterval Interval 101: int RefPositions {#220@318 #221@319} physReg:NA Preferences=[allInt] RelatedInterval Interval 102: ref (specialPutArg) RefPositions {#230@346 #236@351} physReg:NA Preferences=[rcx] RelatedInterval Interval 103: ref RefPositions {#234@350 #238@351} physReg:NA Preferences=[rdx] Interval 104: long RefPositions {#248@362 #250@363} physReg:NA Preferences=[allInt] RelatedInterval Interval 105: long RefPositions {#251@364 #252@367} physReg:NA Preferences=[allInt] RelatedInterval Interval 106: long RefPositions {#253@368 #254@371} physReg:NA Preferences=[allInt] RelatedInterval Interval 107: long RefPositions {#255@372 #258@377} physReg:NA Preferences=[allInt] RelatedInterval Interval 108: long RefPositions {#257@376 #259@377} physReg:NA Preferences=[allInt] RelatedInterval Interval 109: long RefPositions {#260@378 #261@381} physReg:NA Preferences=[allInt] RelatedInterval Interval 110: long RefPositions {#262@382 #263@383} physReg:NA Preferences=[allInt] Interval 111: int RefPositions {#264@384 #265@385} physReg:NA Preferences=[allInt] RelatedInterval Interval 112: int (interfering uses) RefPositions {#273@394 #274@397} physReg:NA Preferences=[rdx] Interval 113: int RefPositions {#276@398 #277@399} physReg:NA Preferences=[allInt] RelatedInterval Interval 114: ref (specialPutArg) RefPositions {#286@426 #292@431} physReg:NA Preferences=[rcx] RelatedInterval Interval 115: ref RefPositions {#290@430 #294@431} physReg:NA Preferences=[rdx] Interval 116: long RefPositions {#306@452 #308@453} physReg:NA Preferences=[allInt] Interval 117: byref RefPositions {#309@454 #310@455} physReg:NA Preferences=[allInt] RelatedInterval Interval 118: int RefPositions {#315@466 #316@469} physReg:NA Preferences=[allInt] RelatedInterval Interval 119: int RefPositions {#317@470 #318@471} physReg:NA Preferences=[allInt] RelatedInterval Interval 120: long RefPositions {#323@490 #324@491} physReg:NA Preferences=[allInt] RelatedInterval Interval 121: long RefPositions {#327@498 #328@499} physReg:NA Preferences=[allInt] Interval 122: long RefPositions {#329@500 #330@503} physReg:NA Preferences=[allInt] Interval 123: long RefPositions {#331@504 #332@505} physReg:NA Preferences=[allInt] RelatedInterval Interval 124: long RefPositions {#342@526 #349@531} physReg:NA Preferences=[rcx] Interval 125: long (constant) RefPositions {#343@528 #345@529} physReg:NA Preferences=[rdx] Interval 126: long RefPositions {#347@530 #351@531} physReg:NA Preferences=[rdx] Interval 127: long RefPositions {#360@532 #361@533} physReg:NA Preferences=[rax] RelatedInterval Interval 128: long RefPositions {#367@540 #369@541} physReg:NA Preferences=[rcx] Interval 129: ref RefPositions {#378@542 #379@543} physReg:NA Preferences=[rax] RelatedInterval Interval 130: int RefPositions {#383@554 #384@555} physReg:NA Preferences=[allInt] RelatedInterval Interval 131: long RefPositions {#390@574 #391@577} physReg:NA Preferences=[allInt] Interval 132: long RefPositions {#392@578 #393@579} physReg:NA Preferences=[allInt] RelatedInterval Interval 133: byref RefPositions {#397@584 #398@585} physReg:NA Preferences=[allInt] RelatedInterval Interval 134: ref RefPositions {#405@610 #407@611} physReg:NA Preferences=[rdx] Interval 135: ref RefPositions {#409@612 #423@633} physReg:NA Preferences=[rdx] Interval 136: ref (specialPutArg) RefPositions {#413@616 #425@633} physReg:NA Preferences=[rcx] RelatedInterval Interval 137: ref (specialPutArg) RefPositions {#417@620 #427@633} physReg:NA Preferences=[r8] RelatedInterval Interval 138: long RefPositions {#419@624 #420@627} physReg:NA Preferences=[allInt] Interval 139: long RefPositions {#421@628 #428@633} physReg:NA Preferences=[allInt] Interval 140: int RefPositions {#437@634 #438@637} physReg:NA Preferences=[rax] Interval 141: int RefPositions {#441@650 #442@651} physReg:NA Preferences=[allInt] RelatedInterval Interval 142: int RefPositions {#445@660 #446@661} physReg:NA Preferences=[allInt] RelatedInterval Interval 143: byref RefPositions {#463@694 #465@697} physReg:NA Preferences=[rcx] Interval 144: int (constant) RefPositions {#484@714 #486@715} physReg:NA Preferences=[rax] Interval 145: int RefPositions {#489@726 #490@727} physReg:NA Preferences=[allInt] RelatedInterval Interval 146: long RefPositions {#496@746 #497@749} physReg:NA Preferences=[allInt] Interval 147: long RefPositions {#498@750 #499@751} physReg:NA Preferences=[allInt] RelatedInterval Interval 148: byref RefPositions {#503@756 #504@757} physReg:NA Preferences=[allInt] RelatedInterval Interval 149: ref RefPositions {#511@782 #512@783} physReg:NA Preferences=[allInt] RelatedInterval Interval 150: long RefPositions {#515@790 #516@791} physReg:NA Preferences=[allInt] RelatedInterval Interval 151: long RefPositions {#519@798 #520@799} physReg:NA Preferences=[allInt] Interval 152: long RefPositions {#521@800 #522@803} physReg:NA Preferences=[allInt] Interval 153: long RefPositions {#523@804 #524@805} physReg:NA Preferences=[allInt] RelatedInterval Interval 154: long RefPositions {#534@826 #541@831} physReg:NA Preferences=[rcx] Interval 155: long (constant) RefPositions {#535@828 #537@829} physReg:NA Preferences=[rdx] Interval 156: long RefPositions {#539@830 #543@831} physReg:NA Preferences=[rdx] Interval 157: long RefPositions {#552@832 #553@833} physReg:NA Preferences=[rax] RelatedInterval Interval 158: ref (specialPutArg) RefPositions {#559@840 #573@857} physReg:NA Preferences=[rcx] RelatedInterval Interval 159: long (specialPutArg) RefPositions {#563@844 #575@857} physReg:NA Preferences=[r11] RelatedInterval Interval 160: ref RefPositions {#567@848 #577@857} physReg:NA Preferences=[rdx] Interval 161: ref (specialPutArg) RefPositions {#571@852 #579@857} physReg:NA Preferences=[r8] RelatedInterval Interval 162: int RefPositions {#589@858 #590@861} physReg:NA Preferences=[rax] Interval 163: byref RefPositions {#595@884 #597@887} physReg:NA Preferences=[rcx] Interval 164: int RefPositions {#618@912 #619@913} physReg:NA Preferences=[allInt] RelatedInterval Interval 165: int RefPositions {#622@922 #623@923} physReg:NA Preferences=[allInt] RelatedInterval Interval 166: int RefPositions {#634@962 #635@963} physReg:NA Preferences=[allInt] RelatedInterval Interval 167: long RefPositions {#644@986 #645@989} physReg:NA Preferences=[allInt] Interval 168: long RefPositions {#646@990 #648@993} physReg:NA Preferences=[allInt] Interval 169: int RefPositions {#649@994 #650@995} physReg:NA Preferences=[allInt] Interval 170: int RefPositions {#651@996 #652@999} physReg:NA Preferences=[allInt] RelatedInterval Interval 171: int RefPositions {#653@1000 #654@1003} physReg:NA Preferences=[allInt] Interval 172: int RefPositions {#655@1004 #656@1005} physReg:NA Preferences=[allInt] RelatedInterval Interval 173: long (constant) RefPositions {#662@1028 #663@1029} physReg:NA Preferences=[allInt] Interval 174: ref RefPositions {#664@1030 #666@1031} physReg:NA Preferences=[rcx] Interval 175: ref RefPositions {#668@1032 #674@1037} physReg:NA Preferences=[rcx] Interval 176: ref RefPositions {#672@1036 #676@1037} physReg:NA Preferences=[rdx] Interval 177: int RefPositions {#686@1052 #687@1053} physReg:NA Preferences=[allInt] RelatedInterval Interval 178: long RefPositions {#692@1066 #693@1069} physReg:NA Preferences=[allInt] Interval 179: long RefPositions {#694@1070 #696@1073} physReg:NA Preferences=[allInt] Interval 180: int RefPositions {#697@1074 #698@1075} physReg:NA Preferences=[allInt] Interval 181: int RefPositions {#699@1076 #700@1079} physReg:NA Preferences=[allInt] RelatedInterval Interval 182: int RefPositions {#701@1080 #703@1081} physReg:NA Preferences=[allInt] Interval 183: int RefPositions {#707@1110 #708@1111} physReg:NA Preferences=[allInt] RelatedInterval Interval 184: int RefPositions {#718@1134 #720@1135} physReg:NA Preferences=[rcx] Interval 185: int RefPositions {#729@1136 #730@1137} physReg:NA Preferences=[rax] RelatedInterval Interval 186: int RefPositions {#735@1142 #746@1151} physReg:NA Preferences=[rdx] Interval 187: ref (specialPutArg) RefPositions {#739@1146 #748@1151} physReg:NA Preferences=[rcx] RelatedInterval Interval 188: int (constant) RefPositions {#740@1148 #742@1149} physReg:NA Preferences=[r8] Interval 189: int RefPositions {#744@1150 #750@1151} physReg:NA Preferences=[r8] Interval 190: ref RefPositions {#759@1160 #760@1161} physReg:NA Preferences=[allInt] RelatedInterval Interval 191: int RefPositions {#763@1170 #764@1171} physReg:NA Preferences=[allInt] RelatedInterval Interval 192: long RefPositions {#769@1184 #770@1185} physReg:NA Preferences=[allInt] RelatedInterval Interval 193: int RefPositions {#773@1194 #774@1195} physReg:NA Preferences=[allInt] RelatedInterval Interval 194: ref (specialPutArg) RefPositions {#783@1222 #789@1227} physReg:NA Preferences=[rcx] RelatedInterval Interval 195: ref RefPositions {#787@1226 #791@1227} physReg:NA Preferences=[rdx] Interval 196: long RefPositions {#801@1238 #803@1239} physReg:NA Preferences=[allInt] RelatedInterval Interval 197: long RefPositions {#804@1240 #805@1243} physReg:NA Preferences=[allInt] RelatedInterval Interval 198: long RefPositions {#806@1244 #807@1247} physReg:NA Preferences=[allInt] RelatedInterval Interval 199: long RefPositions {#808@1248 #811@1253} physReg:NA Preferences=[allInt] RelatedInterval Interval 200: long RefPositions {#810@1252 #812@1253} physReg:NA Preferences=[allInt] RelatedInterval Interval 201: long RefPositions {#813@1254 #814@1257} physReg:NA Preferences=[allInt] RelatedInterval Interval 202: long RefPositions {#815@1258 #816@1259} physReg:NA Preferences=[allInt] Interval 203: int RefPositions {#817@1260 #818@1261} physReg:NA Preferences=[allInt] RelatedInterval Interval 204: int (interfering uses) RefPositions {#826@1270 #827@1273} physReg:NA Preferences=[rdx] Interval 205: int RefPositions {#829@1274 #830@1275} physReg:NA Preferences=[allInt] RelatedInterval Interval 206: ref (specialPutArg) RefPositions {#839@1302 #845@1307} physReg:NA Preferences=[rcx] RelatedInterval Interval 207: ref RefPositions {#843@1306 #847@1307} physReg:NA Preferences=[rdx] Interval 208: long RefPositions {#859@1324 #861@1325} physReg:NA Preferences=[allInt] Interval 209: byref RefPositions {#862@1326 #863@1327} physReg:NA Preferences=[allInt] RelatedInterval Interval 210: int RefPositions {#871@1348 #873@1353} physReg:NA Preferences=[allInt] Interval 211: ref RefPositions {#875@1362 #876@1363} physReg:NA Preferences=[allInt] RelatedInterval Interval 212: long RefPositions {#882@1384 #883@1387} physReg:NA Preferences=[allInt] Interval 213: long RefPositions {#884@1388 #886@1389} physReg:NA Preferences=[allInt] Interval 214: byref RefPositions {#887@1390 #888@1391} physReg:NA Preferences=[allInt] RelatedInterval Interval 215: int RefPositions {#893@1408 #894@1411} physReg:NA Preferences=[allInt] RelatedInterval Interval 216: int RefPositions {#895@1412 #897@1417} physReg:NA Preferences=[allInt] Interval 217: byref RefPositions {#916@1432 #918@1435} physReg:NA Preferences=[rcx] Interval 218: int RefPositions {#935@1444 #937@1447} physReg:NA Preferences=[allInt] Interval 219: ref RefPositions {#944@1484 #951@1489} physReg:NA Preferences=[rdx] Interval 220: long (constant) RefPositions {#945@1486 #947@1487} physReg:NA Preferences=[rcx] Interval 221: long RefPositions {#949@1488 #953@1489} physReg:NA Preferences=[rcx] Interval 222: ref RefPositions {#962@1490 #963@1493} physReg:NA Preferences=[rax] Interval 223: int RefPositions {#966@1506 #968@1507} physReg:NA Preferences=[rdx] Interval 224: int RefPositions {#970@1508 #981@1517} physReg:NA Preferences=[rdx] Interval 225: ref (specialPutArg) RefPositions {#974@1512 #983@1517} physReg:NA Preferences=[rcx] RelatedInterval Interval 226: int (constant) RefPositions {#975@1514 #977@1515} physReg:NA Preferences=[r8] Interval 227: int RefPositions {#979@1516 #985@1517} physReg:NA Preferences=[r8] Interval 228: int (constant) RefPositions {#994@1522 #996@1523} physReg:NA Preferences=[rax] Interval 229: int (constant) RefPositions {#998@1530 #1000@1531} physReg:NA Preferences=[rcx] Interval 230: int RefPositions {#1002@1532 #1004@1533} physReg:NA Preferences=[rcx] Interval 231: long RefPositions {#1014@1542 #1015@1543} physReg:NA Preferences=[allInt] RelatedInterval Interval 232: long RefPositions {#1018@1550 #1019@1551} physReg:NA Preferences=[allInt] Interval 233: long RefPositions {#1020@1552 #1021@1559} physReg:NA Preferences=[allInt] Interval 234: long RefPositions {#1024@1570 #1025@1571} physReg:NA Preferences=[allInt] Interval 235: long RefPositions {#1026@1572 #1027@1575} physReg:NA Preferences=[allInt] Interval 236: long RefPositions {#1028@1576 #1029@1577} physReg:NA Preferences=[allInt] RelatedInterval Interval 237: long RefPositions {#1035@1584 #1042@1589} physReg:NA Preferences=[rcx] Interval 238: long (constant) RefPositions {#1036@1586 #1038@1587} physReg:NA Preferences=[rdx] Interval 239: long RefPositions {#1040@1588 #1044@1589} physReg:NA Preferences=[rdx] Interval 240: long RefPositions {#1053@1590 #1054@1591} physReg:NA Preferences=[rax] RelatedInterval Interval 241: long RefPositions {#1060@1598 #1066@1603} physReg:NA Preferences=[rcx] Interval 242: ref RefPositions {#1064@1602 #1068@1603} physReg:NA Preferences=[rdx] Interval 243: long RefPositions {#1078@1612 #1079@1613} physReg:NA Preferences=[allInt] RelatedInterval Interval 244: long RefPositions {#1082@1620 #1083@1621} physReg:NA Preferences=[allInt] Interval 245: long RefPositions {#1084@1622 #1085@1629} physReg:NA Preferences=[allInt] Interval 246: long RefPositions {#1088@1640 #1089@1641} physReg:NA Preferences=[allInt] Interval 247: long RefPositions {#1090@1642 #1091@1645} physReg:NA Preferences=[allInt] Interval 248: long RefPositions {#1092@1646 #1093@1647} physReg:NA Preferences=[allInt] RelatedInterval Interval 249: long RefPositions {#1099@1654 #1106@1659} physReg:NA Preferences=[rcx] Interval 250: long (constant) RefPositions {#1100@1656 #1102@1657} physReg:NA Preferences=[rdx] Interval 251: long RefPositions {#1104@1658 #1108@1659} physReg:NA Preferences=[rdx] Interval 252: long RefPositions {#1117@1660 #1118@1661} physReg:NA Preferences=[rax] RelatedInterval Interval 253: long RefPositions {#1124@1668 #1130@1673} physReg:NA Preferences=[rcx] Interval 254: ref RefPositions {#1128@1672 #1132@1673} physReg:NA Preferences=[rdx] *************** In LinearScan::allocateRegisters() Linear scan intervals before allocateRegisters: Interval 0: (V00) ref RefPositions {#0@0 #7@25 #10@33 #32@53 #65@103 #100@157 #106@177 #207@287 #215@307 #322@489 #514@789 #631@949 #633@961 #685@1051 #702@1081 #704@1099 #706@1109 #737@1145 #758@1159 #768@1183 #872@1353 #874@1361 #938@1465 #972@1511 #1013@1541 #1077@1611 #1148@1681 #1157@1685 #1158@1685} physReg:rcx Preferences=[rbx rbp rsi rdi r12-r15] Interval 1: (V01) ref RefPositions {#1@0 #5@9 #157@235 #180@251 #183@255 #415@619 #569@851 #901@1425 #1062@1601 #1126@1671} physReg:rdx Preferences=[rbx rbp rsi rdi r12-r15] Interval 2: (V02) ref RefPositions {#3@0 #467@697 #599@887 #920@1435} physReg:r8 Preferences=[rbx rbp rsi rdi r12-r15] Interval 3: (V03) int RefPositions {#2@0 #460@683 #482@707 #592@873 #614@897 #629@937} physReg:r9 Preferences=[rbx rbp rsi rdi r12-r15] Interval 4: (V04) ref RefPositions {#68@106 #69@113 #382@553 #395@583 #403@609 #452@675 #488@725 #501@755 #509@781 #647@993 #695@1073 #877@1364 #880@1377 #885@1389 #965@1505} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 5: (V05) ref RefPositions {#103@160 #104@167 #149@227 #320@479 #456@675 #557@839 #942@1483} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 6: (V06) int RefPositions {#203@274 #247@361 #268@393 #401@595 #454@675 #507@767 #800@1237 #821@1269 #891@1401} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 7: (V07) int RefPositions {#206@280 #444@659 #447@662 #449@669 #451@675 #621@921 #624@924 #626@931 #939@1473} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 8: (V08) byref RefPositions {#313@460 #314@465 #458@675 #866@1332 #892@1407 #936@1447} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 9: (V09) int RefPositions {#319@472 #387@561 #389@573 #443@652 #453@675 #493@733 #495@745 #620@914 #628@937} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 10: (V10) int RefPositions {#638@968 #869@1340 #870@1347 #879@1377 #881@1383 #934@1443} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 11: (V11) byref RefPositions {#889@1392 #890@1401 #896@1417 #899@1425 #915@1431} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 12: (V12) ref RefPositions {#380@544 #411@615 #418@623 #457@675} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 13: (V13) int RefPositions {#711@1116 #713@1123 #868@1339} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 14: (V15) int RefPositions {#177@244 #200@268 #202@273} physReg:NA Preferences=[allInt] RelatedInterval Interval 15: (V16) long RefPositions {#517@792 #518@797 #532@825} physReg:NA Preferences=[rcx] Interval 16: (V17) ref RefPositions {#513@784 #565@847} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 17: (V19) long RefPositions {#529@820 #554@834 #561@843 #580@857} physReg:NA Preferences=[r11] Interval 18: (V21) long RefPositions {#1080@1614 #1081@1619 #1087@1639 #1097@1653} physReg:NA Preferences=[rcx] Interval 19: (V23) long RefPositions {#1094@1648 #1119@1662 #1122@1667} physReg:NA Preferences=[rcx] Interval 20: (V24) long RefPositions {#325@492 #326@497 #340@525} physReg:NA Preferences=[rcx] Interval 21: (V25) long RefPositions {#337@520 #362@534 #365@539} physReg:NA Preferences=[rcx] Interval 22: (V26) long RefPositions {#1016@1544 #1017@1549 #1023@1569 #1033@1583} physReg:NA Preferences=[rcx] Interval 23: (V28) long RefPositions {#1030@1578 #1055@1592 #1058@1597} physReg:NA Preferences=[rcx] Interval 24: (V29) long RefPositions {#109@180 #110@185 #124@213} physReg:NA Preferences=[rcx] Interval 25: (V31) long RefPositions {#121@208 #146@222 #153@231 #166@241} physReg:NA Preferences=[r11] Interval 26: (V33) int RefPositions {#35@56 #43@77} physReg:NA Preferences=[allInt] Interval 27: (V35) ref RefPositions {#42@70 #46@87 #50@91} physReg:NA Preferences=[rcx rdx] Interval 28: (V36) int RefPositions {#72@116 #75@129} physReg:NA Preferences=[allInt] Interval 29: (V37) ref RefPositions {#74@122 #85@145} physReg:NA Preferences=[rdx] Interval 30: (V38) byref RefPositions {#311@456 #312@459} physReg:NA Preferences=[allInt] RelatedInterval Interval 31: (V39) ref RefPositions {#210@290 #211@297 #304@445 #307@453} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 32: (V40) int RefPositions {#214@300 #219@317 #256@375 #269@393} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 33: (V41) long RefPositions {#218@310 #249@363} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 34: (V42) int RefPositions {#266@386 #275@397 #303@445 #305@451} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 35: (V43) int RefPositions {#222@320 #225@335} physReg:NA Preferences=[allInt] Interval 36: (V45) ref RefPositions {#224@328 #228@345 #232@349} physReg:NA Preferences=[rcx rdx] Interval 37: (V46) int RefPositions {#278@400 #281@415} physReg:NA Preferences=[allInt] Interval 38: (V48) ref RefPositions {#280@408 #284@425 #288@429} physReg:NA Preferences=[rcx rdx] Interval 39: (V49) int RefPositions {#657@1006 #660@1019} physReg:NA Preferences=[allInt] Interval 40: (V50) ref RefPositions {#659@1012 #670@1035} physReg:NA Preferences=[rdx] Interval 41: (V51) byref RefPositions {#864@1328 #865@1331} physReg:NA Preferences=[allInt] RelatedInterval Interval 42: (V52) ref RefPositions {#761@1162 #762@1169 #860@1325} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 43: (V53) int RefPositions {#767@1176 #772@1193 #809@1251 #822@1269} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 44: (V54) long RefPositions {#771@1186 #802@1239} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 45: (V55) int RefPositions {#819@1262 #828@1273 #856@1317 #858@1323} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 46: (V56) int RefPositions {#775@1196 #778@1211} physReg:NA Preferences=[allInt] Interval 47: (V58) ref RefPositions {#777@1204 #781@1221 #785@1225} physReg:NA Preferences=[rcx rdx] Interval 48: (V59) int RefPositions {#831@1276 #834@1291} physReg:NA Preferences=[allInt] Interval 49: (V61) ref RefPositions {#833@1284 #837@1301 #841@1305} physReg:NA Preferences=[rcx rdx] Interval 50: (V62) int RefPositions {#640@974 #641@979 #643@985} physReg:NA Preferences=[allInt] Interval 51: (V63) int RefPositions {#688@1054 #689@1059 #691@1065} physReg:NA Preferences=[allInt] Interval 52: (V64) int RefPositions {#731@1138 #733@1141} physReg:NA Preferences=[rdx] Interval 53: (V65) byref RefPositions {#399@586 #400@595 #440@649 #462@693} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 54: (V66) byref RefPositions {#505@758 #506@767 #594@883 #617@911} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 55: (V67) long RefPositions {#525@806 #526@811 #528@819} physReg:NA Preferences=[allInt] RelatedInterval Interval 56: (V68) long RefPositions {#117@194 #118@199 #120@207} physReg:NA Preferences=[allInt] RelatedInterval Interval 57: (V69) long RefPositions {#333@506 #334@511 #336@519} physReg:NA Preferences=[allInt] RelatedInterval Interval 58: (V70) long RefPositions {#394@580 #396@583 #404@609} physReg:NA Preferences=[allInt] Interval 59: (V71) long RefPositions {#500@752 #502@755 #510@781} physReg:NA Preferences=[allInt] Interval 60: (V72) int RefPositions {#765@1172 #766@1175 #857@1317} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 61: (V73) ref RefPositions {#40@64 #41@69 #73@121 #223@327 #279@407 #455@675 #658@1011 #776@1203 #832@1283} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] RelatedInterval Interval 62: (V74) int RefPositions {#636@964 #637@967 #639@973} physReg:NA Preferences=[allInt] RelatedInterval Interval 63: (V75) int RefPositions {#709@1112 #710@1115 #716@1133} physReg:NA Preferences=[rcx] Interval 64: (V76) int RefPositions {#385@556 #386@561 #448@669 #491@728 #492@733 #625@931 #642@979 #690@1059 #712@1123} physReg:NA Preferences=[rbx rbp rsi rdi r12-r15] Interval 65: ref (specialPutArg) RefPositions {#12@34 #19@39} physReg:NA Preferences=[rcx] RelatedInterval Interval 66: int (constant) RefPositions {#13@36 #15@37} physReg:NA Preferences=[rdx] Interval 67: int RefPositions {#17@38 #21@39} physReg:NA Preferences=[rdx] Interval 68: int RefPositions {#30@40} physReg:NA Preferences=[rax] Interval 69: int RefPositions {#33@54 #34@55} physReg:NA Preferences=[allInt] RelatedInterval Interval 70: long (constant) RefPositions {#36@60 #37@61} physReg:NA Preferences=[allInt] Interval 71: ref RefPositions {#38@62 #39@63} physReg:NA Preferences=[allInt] RelatedInterval Interval 72: ref (specialPutArg) RefPositions {#48@88 #54@93} physReg:NA Preferences=[rcx] RelatedInterval Interval 73: ref RefPositions {#52@92 #56@93} physReg:NA Preferences=[rdx] Interval 74: ref RefPositions {#66@104 #67@105} physReg:NA Preferences=[allInt] RelatedInterval Interval 75: int RefPositions {#70@114 #71@115} physReg:NA Preferences=[allInt] RelatedInterval Interval 76: long (constant) RefPositions {#77@138 #78@139} physReg:NA Preferences=[allInt] Interval 77: ref RefPositions {#79@140 #81@141} physReg:NA Preferences=[rcx] Interval 78: ref RefPositions {#83@142 #89@147} physReg:NA Preferences=[rcx] Interval 79: ref RefPositions {#87@146 #91@147} physReg:NA Preferences=[rdx] Interval 80: ref RefPositions {#101@158 #102@159} physReg:NA Preferences=[allInt] RelatedInterval Interval 81: long RefPositions {#107@178 #108@179} physReg:NA Preferences=[allInt] RelatedInterval Interval 82: long RefPositions {#111@186 #112@187} physReg:NA Preferences=[allInt] Interval 83: long RefPositions {#113@188 #114@191} physReg:NA Preferences=[allInt] Interval 84: long RefPositions {#115@192 #116@193} physReg:NA Preferences=[allInt] RelatedInterval Interval 85: long RefPositions {#126@214 #133@219} physReg:NA Preferences=[rcx] Interval 86: long (constant) RefPositions {#127@216 #129@217} physReg:NA Preferences=[rdx] Interval 87: long RefPositions {#131@218 #135@219} physReg:NA Preferences=[rdx] Interval 88: long RefPositions {#144@220 #145@221} physReg:NA Preferences=[rax] RelatedInterval Interval 89: ref (specialPutArg) RefPositions {#151@228 #161@241} physReg:NA Preferences=[rcx] RelatedInterval Interval 90: long (specialPutArg) RefPositions {#155@232 #163@241} physReg:NA Preferences=[r11] RelatedInterval Interval 91: ref (specialPutArg) RefPositions {#159@236 #165@241} physReg:NA Preferences=[rdx] RelatedInterval Interval 92: int RefPositions {#175@242 #176@243} physReg:NA Preferences=[rax] RelatedInterval Interval 93: ref (specialPutArg) RefPositions {#182@252 #188@265} physReg:NA Preferences=[rcx] RelatedInterval Interval 94: long RefPositions {#184@256 #185@259} physReg:NA Preferences=[allInt] Interval 95: long RefPositions {#186@260 #189@265} physReg:NA Preferences=[allInt] Interval 96: int RefPositions {#198@266 #199@267} physReg:NA Preferences=[rax] RelatedInterval Interval 97: int (constant) RefPositions {#204@278 #205@279} physReg:NA Preferences=[allInt] RelatedInterval Interval 98: ref RefPositions {#208@288 #209@289} physReg:NA Preferences=[allInt] RelatedInterval Interval 99: int RefPositions {#212@298 #213@299} physReg:NA Preferences=[allInt] RelatedInterval Interval 100: long RefPositions {#216@308 #217@309} physReg:NA Preferences=[allInt] RelatedInterval Interval 101: int RefPositions {#220@318 #221@319} physReg:NA Preferences=[allInt] RelatedInterval Interval 102: ref (specialPutArg) RefPositions {#230@346 #236@351} physReg:NA Preferences=[rcx] RelatedInterval Interval 103: ref RefPositions {#234@350 #238@351} physReg:NA Preferences=[rdx] Interval 104: long RefPositions {#248@362 #250@363} physReg:NA Preferences=[allInt] RelatedInterval Interval 105: long RefPositions {#251@364 #252@367} physReg:NA Preferences=[allInt] RelatedInterval Interval 106: long RefPositions {#253@368 #254@371} physReg:NA Preferences=[allInt] RelatedInterval Interval 107: long RefPositions {#255@372 #258@377} physReg:NA Preferences=[allInt] RelatedInterval Interval 108: long RefPositions {#257@376 #259@377} physReg:NA Preferences=[allInt] RelatedInterval Interval 109: long RefPositions {#260@378 #261@381} physReg:NA Preferences=[allInt] RelatedInterval Interval 110: long RefPositions {#262@382 #263@383} physReg:NA Preferences=[allInt] Interval 111: int RefPositions {#264@384 #265@385} physReg:NA Preferences=[allInt] RelatedInterval Interval 112: int (interfering uses) RefPositions {#273@394 #274@397} physReg:NA Preferences=[rdx] Interval 113: int RefPositions {#276@398 #277@399} physReg:NA Preferences=[allInt] RelatedInterval Interval 114: ref (specialPutArg) RefPositions {#286@426 #292@431} physReg:NA Preferences=[rcx] RelatedInterval Interval 115: ref RefPositions {#290@430 #294@431} physReg:NA Preferences=[rdx] Interval 116: long RefPositions {#306@452 #308@453} physReg:NA Preferences=[allInt] Interval 117: byref RefPositions {#309@454 #310@455} physReg:NA Preferences=[allInt] RelatedInterval Interval 118: int RefPositions {#315@466 #316@469} physReg:NA Preferences=[allInt] RelatedInterval Interval 119: int RefPositions {#317@470 #318@471} physReg:NA Preferences=[allInt] RelatedInterval Interval 120: long RefPositions {#323@490 #324@491} physReg:NA Preferences=[allInt] RelatedInterval Interval 121: long RefPositions {#327@498 #328@499} physReg:NA Preferences=[allInt] Interval 122: long RefPositions {#329@500 #330@503} physReg:NA Preferences=[allInt] Interval 123: long RefPositions {#331@504 #332@505} physReg:NA Preferences=[allInt] RelatedInterval Interval 124: long RefPositions {#342@526 #349@531} physReg:NA Preferences=[rcx] Interval 125: long (constant) RefPositions {#343@528 #345@529} physReg:NA Preferences=[rdx] Interval 126: long RefPositions {#347@530 #351@531} physReg:NA Preferences=[rdx] Interval 127: long RefPositions {#360@532 #361@533} physReg:NA Preferences=[rax] RelatedInterval Interval 128: long RefPositions {#367@540 #369@541} physReg:NA Preferences=[rcx] Interval 129: ref RefPositions {#378@542 #379@543} physReg:NA Preferences=[rax] RelatedInterval Interval 130: int RefPositions {#383@554 #384@555} physReg:NA Preferences=[allInt] RelatedInterval Interval 131: long RefPositions {#390@574 #391@577} physReg:NA Preferences=[allInt] Interval 132: long RefPositions {#392@578 #393@579} physReg:NA Preferences=[allInt] RelatedInterval Interval 133: byref RefPositions {#397@584 #398@585} physReg:NA Preferences=[allInt] RelatedInterval Interval 134: ref RefPositions {#405@610 #407@611} physReg:NA Preferences=[rdx] Interval 135: ref RefPositions {#409@612 #423@633} physReg:NA Preferences=[rdx] Interval 136: ref (specialPutArg) RefPositions {#413@616 #425@633} physReg:NA Preferences=[rcx] RelatedInterval Interval 137: ref (specialPutArg) RefPositions {#417@620 #427@633} physReg:NA Preferences=[r8] RelatedInterval Interval 138: long RefPositions {#419@624 #420@627} physReg:NA Preferences=[allInt] Interval 139: long RefPositions {#421@628 #428@633} physReg:NA Preferences=[allInt] Interval 140: int RefPositions {#437@634 #438@637} physReg:NA Preferences=[rax] Interval 141: int RefPositions {#441@650 #442@651} physReg:NA Preferences=[allInt] RelatedInterval Interval 142: int RefPositions {#445@660 #446@661} physReg:NA Preferences=[allInt] RelatedInterval Interval 143: byref RefPositions {#463@694 #465@697} physReg:NA Preferences=[rcx] Interval 144: int (constant) RefPositions {#484@714 #486@715} physReg:NA Preferences=[rax] Interval 145: int RefPositions {#489@726 #490@727} physReg:NA Preferences=[allInt] RelatedInterval Interval 146: long RefPositions {#496@746 #497@749} physReg:NA Preferences=[allInt] Interval 147: long RefPositions {#498@750 #499@751} physReg:NA Preferences=[allInt] RelatedInterval Interval 148: byref RefPositions {#503@756 #504@757} physReg:NA Preferences=[allInt] RelatedInterval Interval 149: ref RefPositions {#511@782 #512@783} physReg:NA Preferences=[allInt] RelatedInterval Interval 150: long RefPositions {#515@790 #516@791} physReg:NA Preferences=[allInt] RelatedInterval Interval 151: long RefPositions {#519@798 #520@799} physReg:NA Preferences=[allInt] Interval 152: long RefPositions {#521@800 #522@803} physReg:NA Preferences=[allInt] Interval 153: long RefPositions {#523@804 #524@805} physReg:NA Preferences=[allInt] RelatedInterval Interval 154: long RefPositions {#534@826 #541@831} physReg:NA Preferences=[rcx] Interval 155: long (constant) RefPositions {#535@828 #537@829} physReg:NA Preferences=[rdx] Interval 156: long RefPositions {#539@830 #543@831} physReg:NA Preferences=[rdx] Interval 157: long RefPositions {#552@832 #553@833} physReg:NA Preferences=[rax] RelatedInterval Interval 158: ref (specialPutArg) RefPositions {#559@840 #573@857} physReg:NA Preferences=[rcx] RelatedInterval Interval 159: long (specialPutArg) RefPositions {#563@844 #575@857} physReg:NA Preferences=[r11] RelatedInterval Interval 160: ref RefPositions {#567@848 #577@857} physReg:NA Preferences=[rdx] Interval 161: ref (specialPutArg) RefPositions {#571@852 #579@857} physReg:NA Preferences=[r8] RelatedInterval Interval 162: int RefPositions {#589@858 #590@861} physReg:NA Preferences=[rax] Interval 163: byref RefPositions {#595@884 #597@887} physReg:NA Preferences=[rcx] Interval 164: int RefPositions {#618@912 #619@913} physReg:NA Preferences=[allInt] RelatedInterval Interval 165: int RefPositions {#622@922 #623@923} physReg:NA Preferences=[allInt] RelatedInterval Interval 166: int RefPositions {#634@962 #635@963} physReg:NA Preferences=[allInt] RelatedInterval Interval 167: long RefPositions {#644@986 #645@989} physReg:NA Preferences=[allInt] Interval 168: long RefPositions {#646@990 #648@993} physReg:NA Preferences=[allInt] Interval 169: int RefPositions {#649@994 #650@995} physReg:NA Preferences=[allInt] Interval 170: int RefPositions {#651@996 #652@999} physReg:NA Preferences=[allInt] RelatedInterval Interval 171: int RefPositions {#653@1000 #654@1003} physReg:NA Preferences=[allInt] Interval 172: int RefPositions {#655@1004 #656@1005} physReg:NA Preferences=[allInt] RelatedInterval Interval 173: long (constant) RefPositions {#662@1028 #663@1029} physReg:NA Preferences=[allInt] Interval 174: ref RefPositions {#664@1030 #666@1031} physReg:NA Preferences=[rcx] Interval 175: ref RefPositions {#668@1032 #674@1037} physReg:NA Preferences=[rcx] Interval 176: ref RefPositions {#672@1036 #676@1037} physReg:NA Preferences=[rdx] Interval 177: int RefPositions {#686@1052 #687@1053} physReg:NA Preferences=[allInt] RelatedInterval Interval 178: long RefPositions {#692@1066 #693@1069} physReg:NA Preferences=[allInt] Interval 179: long RefPositions {#694@1070 #696@1073} physReg:NA Preferences=[allInt] Interval 180: int RefPositions {#697@1074 #698@1075} physReg:NA Preferences=[allInt] Interval 181: int RefPositions {#699@1076 #700@1079} physReg:NA Preferences=[allInt] RelatedInterval Interval 182: int RefPositions {#701@1080 #703@1081} physReg:NA Preferences=[allInt] Interval 183: int RefPositions {#707@1110 #708@1111} physReg:NA Preferences=[allInt] RelatedInterval Interval 184: int RefPositions {#718@1134 #720@1135} physReg:NA Preferences=[rcx] Interval 185: int RefPositions {#729@1136 #730@1137} physReg:NA Preferences=[rax] RelatedInterval Interval 186: int RefPositions {#735@1142 #746@1151} physReg:NA Preferences=[rdx] Interval 187: ref (specialPutArg) RefPositions {#739@1146 #748@1151} physReg:NA Preferences=[rcx] RelatedInterval Interval 188: int (constant) RefPositions {#740@1148 #742@1149} physReg:NA Preferences=[r8] Interval 189: int RefPositions {#744@1150 #750@1151} physReg:NA Preferences=[r8] Interval 190: ref RefPositions {#759@1160 #760@1161} physReg:NA Preferences=[allInt] RelatedInterval Interval 191: int RefPositions {#763@1170 #764@1171} physReg:NA Preferences=[allInt] RelatedInterval Interval 192: long RefPositions {#769@1184 #770@1185} physReg:NA Preferences=[allInt] RelatedInterval Interval 193: int RefPositions {#773@1194 #774@1195} physReg:NA Preferences=[allInt] RelatedInterval Interval 194: ref (specialPutArg) RefPositions {#783@1222 #789@1227} physReg:NA Preferences=[rcx] RelatedInterval Interval 195: ref RefPositions {#787@1226 #791@1227} physReg:NA Preferences=[rdx] Interval 196: long RefPositions {#801@1238 #803@1239} physReg:NA Preferences=[allInt] RelatedInterval Interval 197: long RefPositions {#804@1240 #805@1243} physReg:NA Preferences=[allInt] RelatedInterval Interval 198: long RefPositions {#806@1244 #807@1247} physReg:NA Preferences=[allInt] RelatedInterval Interval 199: long RefPositions {#808@1248 #811@1253} physReg:NA Preferences=[allInt] RelatedInterval Interval 200: long RefPositions {#810@1252 #812@1253} physReg:NA Preferences=[allInt] RelatedInterval Interval 201: long RefPositions {#813@1254 #814@1257} physReg:NA Preferences=[allInt] RelatedInterval Interval 202: long RefPositions {#815@1258 #816@1259} physReg:NA Preferences=[allInt] Interval 203: int RefPositions {#817@1260 #818@1261} physReg:NA Preferences=[allInt] RelatedInterval Interval 204: int (interfering uses) RefPositions {#826@1270 #827@1273} physReg:NA Preferences=[rdx] Interval 205: int RefPositions {#829@1274 #830@1275} physReg:NA Preferences=[allInt] RelatedInterval Interval 206: ref (specialPutArg) RefPositions {#839@1302 #845@1307} physReg:NA Preferences=[rcx] RelatedInterval Interval 207: ref RefPositions {#843@1306 #847@1307} physReg:NA Preferences=[rdx] Interval 208: long RefPositions {#859@1324 #861@1325} physReg:NA Preferences=[allInt] Interval 209: byref RefPositions {#862@1326 #863@1327} physReg:NA Preferences=[allInt] RelatedInterval Interval 210: int RefPositions {#871@1348 #873@1353} physReg:NA Preferences=[allInt] Interval 211: ref RefPositions {#875@1362 #876@1363} physReg:NA Preferences=[allInt] RelatedInterval Interval 212: long RefPositions {#882@1384 #883@1387} physReg:NA Preferences=[allInt] Interval 213: long RefPositions {#884@1388 #886@1389} physReg:NA Preferences=[allInt] Interval 214: byref RefPositions {#887@1390 #888@1391} physReg:NA Preferences=[allInt] RelatedInterval Interval 215: int RefPositions {#893@1408 #894@1411} physReg:NA Preferences=[allInt] RelatedInterval Interval 216: int RefPositions {#895@1412 #897@1417} physReg:NA Preferences=[allInt] Interval 217: byref RefPositions {#916@1432 #918@1435} physReg:NA Preferences=[rcx] Interval 218: int RefPositions {#935@1444 #937@1447} physReg:NA Preferences=[allInt] Interval 219: ref RefPositions {#944@1484 #951@1489} physReg:NA Preferences=[rdx] Interval 220: long (constant) RefPositions {#945@1486 #947@1487} physReg:NA Preferences=[rcx] Interval 221: long RefPositions {#949@1488 #953@1489} physReg:NA Preferences=[rcx] Interval 222: ref RefPositions {#962@1490 #963@1493} physReg:NA Preferences=[rax] Interval 223: int RefPositions {#966@1506 #968@1507} physReg:NA Preferences=[rdx] Interval 224: int RefPositions {#970@1508 #981@1517} physReg:NA Preferences=[rdx] Interval 225: ref (specialPutArg) RefPositions {#974@1512 #983@1517} physReg:NA Preferences=[rcx] RelatedInterval Interval 226: int (constant) RefPositions {#975@1514 #977@1515} physReg:NA Preferences=[r8] Interval 227: int RefPositions {#979@1516 #985@1517} physReg:NA Preferences=[r8] Interval 228: int (constant) RefPositions {#994@1522 #996@1523} physReg:NA Preferences=[rax] Interval 229: int (constant) RefPositions {#998@1530 #1000@1531} physReg:NA Preferences=[rcx] Interval 230: int RefPositions {#1002@1532 #1004@1533} physReg:NA Preferences=[rcx] Interval 231: long RefPositions {#1014@1542 #1015@1543} physReg:NA Preferences=[allInt] RelatedInterval Interval 232: long RefPositions {#1018@1550 #1019@1551} physReg:NA Preferences=[allInt] Interval 233: long RefPositions {#1020@1552 #1021@1559} physReg:NA Preferences=[allInt] Interval 234: long RefPositions {#1024@1570 #1025@1571} physReg:NA Preferences=[allInt] Interval 235: long RefPositions {#1026@1572 #1027@1575} physReg:NA Preferences=[allInt] Interval 236: long RefPositions {#1028@1576 #1029@1577} physReg:NA Preferences=[allInt] RelatedInterval Interval 237: long RefPositions {#1035@1584 #1042@1589} physReg:NA Preferences=[rcx] Interval 238: long (constant) RefPositions {#1036@1586 #1038@1587} physReg:NA Preferences=[rdx] Interval 239: long RefPositions {#1040@1588 #1044@1589} physReg:NA Preferences=[rdx] Interval 240: long RefPositions {#1053@1590 #1054@1591} physReg:NA Preferences=[rax] RelatedInterval Interval 241: long RefPositions {#1060@1598 #1066@1603} physReg:NA Preferences=[rcx] Interval 242: ref RefPositions {#1064@1602 #1068@1603} physReg:NA Preferences=[rdx] Interval 243: long RefPositions {#1078@1612 #1079@1613} physReg:NA Preferences=[allInt] RelatedInterval Interval 244: long RefPositions {#1082@1620 #1083@1621} physReg:NA Preferences=[allInt] Interval 245: long RefPositions {#1084@1622 #1085@1629} physReg:NA Preferences=[allInt] Interval 246: long RefPositions {#1088@1640 #1089@1641} physReg:NA Preferences=[allInt] Interval 247: long RefPositions {#1090@1642 #1091@1645} physReg:NA Preferences=[allInt] Interval 248: long RefPositions {#1092@1646 #1093@1647} physReg:NA Preferences=[allInt] RelatedInterval Interval 249: long RefPositions {#1099@1654 #1106@1659} physReg:NA Preferences=[rcx] Interval 250: long (constant) RefPositions {#1100@1656 #1102@1657} physReg:NA Preferences=[rdx] Interval 251: long RefPositions {#1104@1658 #1108@1659} physReg:NA Preferences=[rdx] Interval 252: long RefPositions {#1117@1660 #1118@1661} physReg:NA Preferences=[rax] RelatedInterval Interval 253: long RefPositions {#1124@1668 #1130@1673} physReg:NA Preferences=[rcx] Interval 254: ref RefPositions {#1128@1672 #1132@1673} physReg:NA Preferences=[rdx] ------------ REFPOSITIONS BEFORE ALLOCATION: ------------ BB00 regmask=[rcx] minReg=1 fixed regOptional> BB00 regmask=[rdx] minReg=1 fixed regOptional> BB00 regmask=[r9] minReg=1 fixed regOptional> BB00 regmask=[r8] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB02 regmask=[allInt] minReg=1> BB03 regmask=[rcx] minReg=1> LCL_VAR BB03 regmask=[rcx] minReg=1 fixed> BB03 regmask=[rcx] minReg=1> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed> CNS_INT BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1 last fixed> BB03 regmask=[rdx] minReg=1> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed> BB03 regmask=[rcx] minReg=1> BB03 regmask=[rcx] minReg=1 last fixed> BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1 last fixed> BB03 regmask=[rax] minReg=1 last> BB03 regmask=[rcx] minReg=1 last> BB03 regmask=[rdx] minReg=1 last> BB03 regmask=[r8] minReg=1 last> BB03 regmask=[r9] minReg=1 last> BB03 regmask=[r10] minReg=1 last> BB03 regmask=[r11] minReg=1 last> BB03 regmask=[rax] minReg=1> CALL BB03 regmask=[rax] minReg=1 last fixed local> LCL_VAR BB04 regmask=[allInt] minReg=1> NE BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> CNS_INT BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> IND BB04 regmask=[allInt] minReg=1> BB04 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1> STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1 last regOptional> BB05 regmask=[rcx] minReg=1> LCL_VAR BB05 regmask=[rcx] minReg=1 fixed> BB05 regmask=[rcx] minReg=1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> BB05 regmask=[rdx] minReg=1> LCL_VAR BB05 regmask=[rdx] minReg=1 last fixed> BB05 regmask=[rdx] minReg=1> PUTARG_REG BB05 regmask=[rdx] minReg=1 fixed> BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> BB05 regmask=[rdx] minReg=1> BB05 regmask=[rdx] minReg=1 last fixed> BB05 regmask=[rax] minReg=1 last> BB05 regmask=[rcx] minReg=1 last> BB05 regmask=[rdx] minReg=1 last> BB05 regmask=[r8] minReg=1 last> BB05 regmask=[r9] minReg=1 last> BB05 regmask=[r10] minReg=1 last> BB05 regmask=[r11] minReg=1 last> LCL_VAR BB06 regmask=[allInt] minReg=1> IND BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1 regOptional> NE BB06 regmask=[allInt] minReg=1> BB06 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1> STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1 last regOptional> CNS_INT BB07 regmask=[allInt] minReg=1> BB07 regmask=[allInt] minReg=1 last> IND BB07 regmask=[rcx] minReg=1> BB07 regmask=[rcx] minReg=1> BB07 regmask=[rcx] minReg=1 last fixed> BB07 regmask=[rcx] minReg=1> PUTARG_REG BB07 regmask=[rcx] minReg=1 fixed> BB07 regmask=[rdx] minReg=1> LCL_VAR BB07 regmask=[rdx] minReg=1 last fixed> BB07 regmask=[rdx] minReg=1> PUTARG_REG BB07 regmask=[rdx] minReg=1 fixed> BB07 regmask=[rcx] minReg=1> BB07 regmask=[rcx] minReg=1 last fixed> BB07 regmask=[rdx] minReg=1> BB07 regmask=[rdx] minReg=1 last fixed> BB07 regmask=[rax] minReg=1 last> BB07 regmask=[rcx] minReg=1 last> BB07 regmask=[rdx] minReg=1 last> BB07 regmask=[r8] minReg=1 last> BB07 regmask=[r9] minReg=1 last> BB07 regmask=[r10] minReg=1 last> BB07 regmask=[r11] minReg=1 last> LCL_VAR BB08 regmask=[allInt] minReg=1> IND BB08 regmask=[allInt] minReg=1> BB08 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB08 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB09 regmask=[allInt] minReg=1> IND BB09 regmask=[allInt] minReg=1> BB09 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[allInt] minReg=1> IND BB09 regmask=[allInt] minReg=1> BB09 regmask=[allInt] minReg=1 last> IND BB09 regmask=[allInt] minReg=1> BB09 regmask=[allInt] minReg=1 last> IND BB09 regmask=[allInt] minReg=1> BB09 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB10 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> BB11 regmask=[rcx] minReg=1> LCL_VAR BB11 regmask=[rcx] minReg=1 last fixed> BB11 regmask=[rcx] minReg=1> PUTARG_REG BB11 regmask=[rcx] minReg=1 fixed> CNS_INT BB11 regmask=[rdx] minReg=1> BB11 regmask=[rdx] minReg=1> BB11 regmask=[rdx] minReg=1 last fixed> BB11 regmask=[rdx] minReg=1> PUTARG_REG BB11 regmask=[rdx] minReg=1 fixed> BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> BB11 regmask=[rdx] minReg=1> BB11 regmask=[rdx] minReg=1 last fixed> BB11 regmask=[rax] minReg=1 last> BB11 regmask=[rcx] minReg=1 last> BB11 regmask=[rdx] minReg=1 last> BB11 regmask=[r8] minReg=1 last> BB11 regmask=[r9] minReg=1 last> BB11 regmask=[r10] minReg=1 last> BB11 regmask=[r11] minReg=1 last> BB11 regmask=[rax] minReg=1> CALL BB11 regmask=[rax] minReg=1 fixed> BB11 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 fixed> BB12 regmask=[rcx] minReg=1> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> BB12 regmask=[r11] minReg=1> LCL_VAR BB12 regmask=[r11] minReg=1 fixed> BB12 regmask=[r11] minReg=1> PUTARG_REG BB12 regmask=[r11] minReg=1 fixed> BB12 regmask=[rdx] minReg=1> LCL_VAR BB12 regmask=[rdx] minReg=1 fixed> BB12 regmask=[rdx] minReg=1> PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed> BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> BB12 regmask=[r11] minReg=1> BB12 regmask=[r11] minReg=1 last fixed> BB12 regmask=[rdx] minReg=1> BB12 regmask=[rdx] minReg=1 last fixed> LCL_VAR BB12 regmask=[allInt] minReg=1 last> BB12 regmask=[rax] minReg=1 last> BB12 regmask=[rcx] minReg=1 last> BB12 regmask=[rdx] minReg=1 last> BB12 regmask=[r8] minReg=1 last> BB12 regmask=[r9] minReg=1 last> BB12 regmask=[r10] minReg=1 last> BB12 regmask=[r11] minReg=1 last> BB12 regmask=[rax] minReg=1> CALL BB12 regmask=[rax] minReg=1 fixed> BB12 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB12 regmask=[allInt] minReg=1> BB13 regmask=[rcx] minReg=1> LCL_VAR BB13 regmask=[rcx] minReg=1 fixed> BB13 regmask=[rcx] minReg=1> PUTARG_REG BB13 regmask=[rcx] minReg=1 fixed> LCL_VAR BB13 regmask=[allInt] minReg=1> IND BB13 regmask=[allInt] minReg=1> BB13 regmask=[allInt] minReg=1 last> IND BB13 regmask=[allInt] minReg=1> BB13 regmask=[rcx] minReg=1> BB13 regmask=[rcx] minReg=1 last fixed> BB13 regmask=[allInt] minReg=1 last> BB13 regmask=[rax] minReg=1 last> BB13 regmask=[rcx] minReg=1 last> BB13 regmask=[rdx] minReg=1 last> BB13 regmask=[r8] minReg=1 last> BB13 regmask=[r9] minReg=1 last> BB13 regmask=[r10] minReg=1 last> BB13 regmask=[r11] minReg=1 last> BB13 regmask=[rax] minReg=1> CALL BB13 regmask=[rax] minReg=1 fixed> BB13 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB13 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> CNS_INT BB14 regmask=[allInt] minReg=1> BB14 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> IND BB14 regmask=[allInt] minReg=1> BB14 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> IND BB14 regmask=[allInt] minReg=1> BB14 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> IND BB14 regmask=[allInt] minReg=1> BB14 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 regOptional> LE BB14 regmask=[allInt] minReg=1> BB14 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 last regOptional> BB15 regmask=[rcx] minReg=1> LCL_VAR BB15 regmask=[rcx] minReg=1 fixed> BB15 regmask=[rcx] minReg=1> PUTARG_REG BB15 regmask=[rcx] minReg=1 fixed> BB15 regmask=[rdx] minReg=1> LCL_VAR BB15 regmask=[rdx] minReg=1 last fixed> BB15 regmask=[rdx] minReg=1> PUTARG_REG BB15 regmask=[rdx] minReg=1 fixed> BB15 regmask=[rcx] minReg=1> BB15 regmask=[rcx] minReg=1 last fixed> BB15 regmask=[rdx] minReg=1> BB15 regmask=[rdx] minReg=1 last fixed> BB15 regmask=[rax] minReg=1 last> BB15 regmask=[rcx] minReg=1 last> BB15 regmask=[rdx] minReg=1 last> BB15 regmask=[r8] minReg=1 last> BB15 regmask=[r9] minReg=1 last> BB15 regmask=[r10] minReg=1 last> BB15 regmask=[r11] minReg=1 last> LCL_VAR BB16 regmask=[allInt] minReg=1> CAST BB16 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1 last regOptional> BB16 regmask=[allInt] minReg=1 last> MUL BB16 regmask=[allInt] minReg=1> BB16 regmask=[allInt] minReg=1 last> RSZ BB16 regmask=[allInt] minReg=1> BB16 regmask=[allInt] minReg=1 last> ADD BB16 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1> CAST BB16 regmask=[allInt] minReg=1> BB16 regmask=[allInt] minReg=1 last regOptional> BB16 regmask=[allInt] minReg=1 last> MUL BB16 regmask=[allInt] minReg=1> BB16 regmask=[allInt] minReg=1 last> RSZ BB16 regmask=[allInt] minReg=1> BB16 regmask=[allInt] minReg=1 last> CAST BB16 regmask=[allInt] minReg=1> BB16 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB16 regmask=[allInt] minReg=1> BB16 regmask=[rax] minReg=1> LCL_VAR BB16 regmask=[rax] minReg=1 fixed> LCL_VAR BB16 regmask=[rcx rbx rbp rsi rdi r8-r15] minReg=1 last delay regOptional> BB16 regmask=[rax] minReg=1 last> BB16 regmask=[rdx] minReg=1 last> BB16 regmask=[rdx] minReg=1> UMOD BB16 regmask=[rdx] minReg=1 fixed> BB16 regmask=[allInt] minReg=1 last> LCL_VAR BB16 regmask=[allInt] minReg=1 regOptional> EQ BB16 regmask=[allInt] minReg=1> BB16 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB16 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1> STORE_LCL_VAR BB16 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1 last regOptional> BB17 regmask=[rcx] minReg=1> LCL_VAR BB17 regmask=[rcx] minReg=1 fixed> BB17 regmask=[rcx] minReg=1> PUTARG_REG BB17 regmask=[rcx] minReg=1 fixed> BB17 regmask=[rdx] minReg=1> LCL_VAR BB17 regmask=[rdx] minReg=1 last fixed> BB17 regmask=[rdx] minReg=1> PUTARG_REG BB17 regmask=[rdx] minReg=1 fixed> BB17 regmask=[rcx] minReg=1> BB17 regmask=[rcx] minReg=1 last fixed> BB17 regmask=[rdx] minReg=1> BB17 regmask=[rdx] minReg=1 last fixed> BB17 regmask=[rax] minReg=1 last> BB17 regmask=[rcx] minReg=1 last> BB17 regmask=[rdx] minReg=1 last> BB17 regmask=[r8] minReg=1 last> BB17 regmask=[r9] minReg=1 last> BB17 regmask=[r10] minReg=1 last> BB17 regmask=[r11] minReg=1 last> LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> CAST BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> BB18 regmask=[allInt] minReg=1 last> LEA BB18 regmask=[allInt] minReg=1> BB18 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1> IND BB18 regmask=[allInt] minReg=1> BB18 regmask=[allInt] minReg=1 last> ADD BB18 regmask=[allInt] minReg=1> BB18 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB19 regmask=[allInt] minReg=1> IND BB19 regmask=[allInt] minReg=1> BB19 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB19 regmask=[allInt] minReg=1> LCL_VAR BB19 regmask=[allInt] minReg=1> IND BB19 regmask=[allInt] minReg=1> BB19 regmask=[allInt] minReg=1 last> IND BB19 regmask=[allInt] minReg=1> BB19 regmask=[allInt] minReg=1 last> IND BB19 regmask=[allInt] minReg=1> BB19 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB19 regmask=[allInt] minReg=1> LCL_VAR BB19 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB20 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> BB21 regmask=[rcx] minReg=1> LCL_VAR BB21 regmask=[rcx] minReg=1 last fixed> BB21 regmask=[rcx] minReg=1> PUTARG_REG BB21 regmask=[rcx] minReg=1 fixed> CNS_INT BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1 last fixed> BB21 regmask=[rdx] minReg=1> PUTARG_REG BB21 regmask=[rdx] minReg=1 fixed> BB21 regmask=[rcx] minReg=1> BB21 regmask=[rcx] minReg=1 last fixed> BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1 last fixed> BB21 regmask=[rax] minReg=1 last> BB21 regmask=[rcx] minReg=1 last> BB21 regmask=[rdx] minReg=1 last> BB21 regmask=[r8] minReg=1 last> BB21 regmask=[r9] minReg=1 last> BB21 regmask=[r10] minReg=1 last> BB21 regmask=[r11] minReg=1 last> BB21 regmask=[rax] minReg=1> CALL BB21 regmask=[rax] minReg=1 fixed> BB21 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> BB22 regmask=[rcx] minReg=1> LCL_VAR BB22 regmask=[rcx] minReg=1 last fixed> BB22 regmask=[rcx] minReg=1> PUTARG_REG BB22 regmask=[rcx] minReg=1 fixed> BB22 regmask=[rcx] minReg=1> BB22 regmask=[rcx] minReg=1 last fixed> BB22 regmask=[rax] minReg=1 last> BB22 regmask=[rcx] minReg=1 last> BB22 regmask=[rdx] minReg=1 last> BB22 regmask=[r8] minReg=1 last> BB22 regmask=[r9] minReg=1 last> BB22 regmask=[r10] minReg=1 last> BB22 regmask=[r11] minReg=1 last> BB22 regmask=[rax] minReg=1> CALL BB22 regmask=[rax] minReg=1 fixed> BB22 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB22 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> IND BB23 regmask=[allInt] minReg=1> BB23 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB24 regmask=[allInt] minReg=1 last> CAST BB24 regmask=[allInt] minReg=1> BB24 regmask=[allInt] minReg=1 last> MUL BB24 regmask=[allInt] minReg=1> BB24 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB24 regmask=[allInt] minReg=1> LEA BB24 regmask=[allInt] minReg=1> BB24 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1 last> IND BB25 regmask=[rdx] minReg=1> BB25 regmask=[rdx] minReg=1> BB25 regmask=[rdx] minReg=1 last fixed> BB25 regmask=[rdx] minReg=1> PUTARG_REG BB25 regmask=[rdx] minReg=1 fixed> BB25 regmask=[rcx] minReg=1> LCL_VAR BB25 regmask=[rcx] minReg=1 fixed> BB25 regmask=[rcx] minReg=1> PUTARG_REG BB25 regmask=[rcx] minReg=1 fixed> BB25 regmask=[r8] minReg=1> LCL_VAR BB25 regmask=[r8] minReg=1 fixed> BB25 regmask=[r8] minReg=1> PUTARG_REG BB25 regmask=[r8] minReg=1 fixed> LCL_VAR BB25 regmask=[allInt] minReg=1> IND BB25 regmask=[allInt] minReg=1> BB25 regmask=[allInt] minReg=1 last> IND BB25 regmask=[allInt] minReg=1> BB25 regmask=[rdx] minReg=1> BB25 regmask=[rdx] minReg=1 last fixed> BB25 regmask=[rcx] minReg=1> BB25 regmask=[rcx] minReg=1 last fixed> BB25 regmask=[r8] minReg=1> BB25 regmask=[r8] minReg=1 last fixed> BB25 regmask=[allInt] minReg=1 last> BB25 regmask=[rax] minReg=1 last> BB25 regmask=[rcx] minReg=1 last> BB25 regmask=[rdx] minReg=1 last> BB25 regmask=[r8] minReg=1 last> BB25 regmask=[r9] minReg=1 last> BB25 regmask=[r10] minReg=1 last> BB25 regmask=[r11] minReg=1 last> BB25 regmask=[rax] minReg=1> CALL BB25 regmask=[rax] minReg=1 fixed> BB25 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB26 regmask=[allInt] minReg=1 last> IND BB26 regmask=[allInt] minReg=1> BB26 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1 last> ADD BB26 regmask=[allInt] minReg=1> BB26 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB26 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB28 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB29 regmask=[allInt] minReg=1 last> LEA BB29 regmask=[rcx] minReg=1> BB29 regmask=[rcx] minReg=1> BB29 regmask=[rcx] minReg=1 last fixed> BB29 regmask=[rdx] minReg=1> LCL_VAR BB29 regmask=[rdx] minReg=1 last fixed> BB29 regmask=[rax] minReg=1 last> BB29 regmask=[rcx] minReg=1 last> BB29 regmask=[rdx] minReg=1 last> BB29 regmask=[r8] minReg=1 last> BB29 regmask=[r9] minReg=1 last> BB29 regmask=[r10] minReg=1 last> BB29 regmask=[r11] minReg=1 last> BB29 regmask=[mm0] minReg=1 last> BB29 regmask=[mm1] minReg=1 last> BB29 regmask=[mm2] minReg=1 last> BB29 regmask=[mm3] minReg=1 last> BB29 regmask=[mm4] minReg=1 last> BB29 regmask=[mm5] minReg=1 last> LCL_VAR BB30 regmask=[allInt] minReg=1 last regOptional> CNS_INT BB31 regmask=[rax] minReg=1> BB31 regmask=[rax] minReg=1> BB31 regmask=[rax] minReg=1 last fixed> LCL_VAR BB32 regmask=[allInt] minReg=1> IND BB32 regmask=[allInt] minReg=1> BB32 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1 last> CAST BB33 regmask=[allInt] minReg=1> BB33 regmask=[allInt] minReg=1 last> MUL BB33 regmask=[allInt] minReg=1> BB33 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1> LEA BB33 regmask=[allInt] minReg=1> BB33 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1 last> IND BB34 regmask=[allInt] minReg=1> BB34 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1> IND BB34 regmask=[allInt] minReg=1> BB34 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1> IND BB34 regmask=[allInt] minReg=1> BB34 regmask=[allInt] minReg=1 last> IND BB34 regmask=[allInt] minReg=1> BB34 regmask=[allInt] minReg=1 last> IND BB34 regmask=[allInt] minReg=1> BB34 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB35 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> BB36 regmask=[rcx] minReg=1> LCL_VAR BB36 regmask=[rcx] minReg=1 last fixed> BB36 regmask=[rcx] minReg=1> PUTARG_REG BB36 regmask=[rcx] minReg=1 fixed> CNS_INT BB36 regmask=[rdx] minReg=1> BB36 regmask=[rdx] minReg=1> BB36 regmask=[rdx] minReg=1 last fixed> BB36 regmask=[rdx] minReg=1> PUTARG_REG BB36 regmask=[rdx] minReg=1 fixed> BB36 regmask=[rcx] minReg=1> BB36 regmask=[rcx] minReg=1 last fixed> BB36 regmask=[rdx] minReg=1> BB36 regmask=[rdx] minReg=1 last fixed> BB36 regmask=[rax] minReg=1 last> BB36 regmask=[rcx] minReg=1 last> BB36 regmask=[rdx] minReg=1 last> BB36 regmask=[r8] minReg=1 last> BB36 regmask=[r9] minReg=1 last> BB36 regmask=[r10] minReg=1 last> BB36 regmask=[r11] minReg=1 last> BB36 regmask=[rax] minReg=1> CALL BB36 regmask=[rax] minReg=1 fixed> BB36 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB36 regmask=[allInt] minReg=1> BB37 regmask=[rcx] minReg=1> LCL_VAR BB37 regmask=[rcx] minReg=1 fixed> BB37 regmask=[rcx] minReg=1> PUTARG_REG BB37 regmask=[rcx] minReg=1 fixed> BB37 regmask=[r11] minReg=1> LCL_VAR BB37 regmask=[r11] minReg=1 fixed> BB37 regmask=[r11] minReg=1> PUTARG_REG BB37 regmask=[r11] minReg=1 fixed> BB37 regmask=[rdx] minReg=1> LCL_VAR BB37 regmask=[rdx] minReg=1 last fixed> BB37 regmask=[rdx] minReg=1> PUTARG_REG BB37 regmask=[rdx] minReg=1 fixed> BB37 regmask=[r8] minReg=1> LCL_VAR BB37 regmask=[r8] minReg=1 fixed> BB37 regmask=[r8] minReg=1> PUTARG_REG BB37 regmask=[r8] minReg=1 fixed> BB37 regmask=[rcx] minReg=1> BB37 regmask=[rcx] minReg=1 last fixed> BB37 regmask=[r11] minReg=1> BB37 regmask=[r11] minReg=1 last fixed> BB37 regmask=[rdx] minReg=1> BB37 regmask=[rdx] minReg=1 last fixed> BB37 regmask=[r8] minReg=1> BB37 regmask=[r8] minReg=1 last fixed> LCL_VAR BB37 regmask=[allInt] minReg=1 last> BB37 regmask=[rax] minReg=1 last> BB37 regmask=[rcx] minReg=1 last> BB37 regmask=[rdx] minReg=1 last> BB37 regmask=[r8] minReg=1 last> BB37 regmask=[r9] minReg=1 last> BB37 regmask=[r10] minReg=1 last> BB37 regmask=[r11] minReg=1 last> BB37 regmask=[rax] minReg=1> CALL BB37 regmask=[rax] minReg=1 fixed> BB37 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB38 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB39 regmask=[allInt] minReg=1 last> LEA BB39 regmask=[rcx] minReg=1> BB39 regmask=[rcx] minReg=1> BB39 regmask=[rcx] minReg=1 last fixed> BB39 regmask=[rdx] minReg=1> LCL_VAR BB39 regmask=[rdx] minReg=1 last fixed> BB39 regmask=[rax] minReg=1 last> BB39 regmask=[rcx] minReg=1 last> BB39 regmask=[rdx] minReg=1 last> BB39 regmask=[r8] minReg=1 last> BB39 regmask=[r9] minReg=1 last> BB39 regmask=[r10] minReg=1 last> BB39 regmask=[r11] minReg=1 last> BB39 regmask=[mm0] minReg=1 last> BB39 regmask=[mm1] minReg=1 last> BB39 regmask=[mm2] minReg=1 last> BB39 regmask=[mm3] minReg=1 last> BB39 regmask=[mm4] minReg=1 last> BB39 regmask=[mm5] minReg=1 last> LCL_VAR BB40 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB42 regmask=[allInt] minReg=1 last> IND BB42 regmask=[allInt] minReg=1> BB42 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB42 regmask=[allInt] minReg=1> LCL_VAR BB42 regmask=[allInt] minReg=1 last> ADD BB42 regmask=[allInt] minReg=1> BB42 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB42 regmask=[allInt] minReg=1> LCL_VAR BB42 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB42 regmask=[allInt] minReg=1> BB43 regmask=[allInt] minReg=1 regOptional> BB43 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB44 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1> IND BB45 regmask=[allInt] minReg=1> BB45 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1> STORE_LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB45 regmask=[allInt] minReg=1 last> CAST BB45 regmask=[allInt] minReg=1> BB45 regmask=[allInt] minReg=1 last> MUL BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1> BB45 regmask=[allInt] minReg=1 last> IND BB45 regmask=[allInt] minReg=1> BB45 regmask=[allInt] minReg=1 last> NEG BB45 regmask=[allInt] minReg=1> BB45 regmask=[allInt] minReg=1 last> ADD BB45 regmask=[allInt] minReg=1> BB45 regmask=[allInt] minReg=1 last regOptional> GE BB45 regmask=[allInt] minReg=1> BB45 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1 last regOptional> CNS_INT BB46 regmask=[allInt] minReg=1> BB46 regmask=[allInt] minReg=1 last> IND BB46 regmask=[rcx] minReg=1> BB46 regmask=[rcx] minReg=1> BB46 regmask=[rcx] minReg=1 last fixed> BB46 regmask=[rcx] minReg=1> PUTARG_REG BB46 regmask=[rcx] minReg=1 fixed> BB46 regmask=[rdx] minReg=1> LCL_VAR BB46 regmask=[rdx] minReg=1 last fixed> BB46 regmask=[rdx] minReg=1> PUTARG_REG BB46 regmask=[rdx] minReg=1 fixed> BB46 regmask=[rcx] minReg=1> BB46 regmask=[rcx] minReg=1 last fixed> BB46 regmask=[rdx] minReg=1> BB46 regmask=[rdx] minReg=1 last fixed> BB46 regmask=[rax] minReg=1 last> BB46 regmask=[rcx] minReg=1 last> BB46 regmask=[rdx] minReg=1 last> BB46 regmask=[r8] minReg=1 last> BB46 regmask=[r9] minReg=1 last> BB46 regmask=[r10] minReg=1 last> BB46 regmask=[r11] minReg=1 last> LCL_VAR BB47 regmask=[allInt] minReg=1> IND BB47 regmask=[allInt] minReg=1> BB47 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB47 regmask=[allInt] minReg=1> LCL_VAR BB47 regmask=[allInt] minReg=1> LCL_VAR BB47 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB47 regmask=[allInt] minReg=1 last> CAST BB47 regmask=[allInt] minReg=1> BB47 regmask=[allInt] minReg=1 last> MUL BB47 regmask=[allInt] minReg=1> LCL_VAR BB47 regmask=[allInt] minReg=1> BB47 regmask=[allInt] minReg=1 last> IND BB47 regmask=[allInt] minReg=1> BB47 regmask=[allInt] minReg=1 last> NEG BB47 regmask=[allInt] minReg=1> BB47 regmask=[allInt] minReg=1 last> ADD BB47 regmask=[allInt] minReg=1> LCL_VAR BB47 regmask=[allInt] minReg=1> BB47 regmask=[allInt] minReg=1 last> LCL_VAR BB47 regmask=[allInt] minReg=1> LCL_VAR BB48 regmask=[allInt] minReg=1> IND BB48 regmask=[allInt] minReg=1> BB48 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB48 regmask=[allInt] minReg=1> LCL_VAR BB48 regmask=[allInt] minReg=1> STORE_LCL_VAR BB48 regmask=[allInt] minReg=1> LCL_VAR BB48 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB48 regmask=[allInt] minReg=1> BB49 regmask=[rcx] minReg=1> LCL_VAR BB49 regmask=[rcx] minReg=1 last fixed> BB49 regmask=[rcx] minReg=1> PUTARG_REG BB49 regmask=[rcx] minReg=1 fixed> BB49 regmask=[rcx] minReg=1> BB49 regmask=[rcx] minReg=1 last fixed> BB49 regmask=[rax] minReg=1 last> BB49 regmask=[rcx] minReg=1 last> BB49 regmask=[rdx] minReg=1 last> BB49 regmask=[r8] minReg=1 last> BB49 regmask=[r9] minReg=1 last> BB49 regmask=[r10] minReg=1 last> BB49 regmask=[r11] minReg=1 last> BB49 regmask=[rax] minReg=1> CALL BB49 regmask=[rax] minReg=1 fixed> BB49 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> BB49 regmask=[rdx] minReg=1> LCL_VAR BB49 regmask=[rdx] minReg=1 last fixed> BB49 regmask=[rdx] minReg=1> PUTARG_REG BB49 regmask=[rdx] minReg=1 fixed> BB49 regmask=[rcx] minReg=1> LCL_VAR BB49 regmask=[rcx] minReg=1 fixed> BB49 regmask=[rcx] minReg=1> PUTARG_REG BB49 regmask=[rcx] minReg=1 fixed> CNS_INT BB49 regmask=[r8] minReg=1> BB49 regmask=[r8] minReg=1> BB49 regmask=[r8] minReg=1 last fixed> BB49 regmask=[r8] minReg=1> PUTARG_REG BB49 regmask=[r8] minReg=1 fixed> BB49 regmask=[rdx] minReg=1> BB49 regmask=[rdx] minReg=1 last fixed> BB49 regmask=[rcx] minReg=1> BB49 regmask=[rcx] minReg=1 last fixed> BB49 regmask=[r8] minReg=1> BB49 regmask=[r8] minReg=1 last fixed> BB49 regmask=[rax] minReg=1 last> BB49 regmask=[rcx] minReg=1 last> BB49 regmask=[rdx] minReg=1 last> BB49 regmask=[r8] minReg=1 last> BB49 regmask=[r9] minReg=1 last> BB49 regmask=[r10] minReg=1 last> BB49 regmask=[r11] minReg=1 last> LCL_VAR BB49 regmask=[allInt] minReg=1> IND BB49 regmask=[allInt] minReg=1> BB49 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1> IND BB49 regmask=[allInt] minReg=1> BB49 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1> STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1> IND BB49 regmask=[allInt] minReg=1> BB49 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1 regOptional> LE BB49 regmask=[allInt] minReg=1> BB49 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1> STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1 last regOptional> BB50 regmask=[rcx] minReg=1> LCL_VAR BB50 regmask=[rcx] minReg=1 fixed> BB50 regmask=[rcx] minReg=1> PUTARG_REG BB50 regmask=[rcx] minReg=1 fixed> BB50 regmask=[rdx] minReg=1> LCL_VAR BB50 regmask=[rdx] minReg=1 last fixed> BB50 regmask=[rdx] minReg=1> PUTARG_REG BB50 regmask=[rdx] minReg=1 fixed> BB50 regmask=[rcx] minReg=1> BB50 regmask=[rcx] minReg=1 last fixed> BB50 regmask=[rdx] minReg=1> BB50 regmask=[rdx] minReg=1 last fixed> BB50 regmask=[rax] minReg=1 last> BB50 regmask=[rcx] minReg=1 last> BB50 regmask=[rdx] minReg=1 last> BB50 regmask=[r8] minReg=1 last> BB50 regmask=[r9] minReg=1 last> BB50 regmask=[r10] minReg=1 last> BB50 regmask=[r11] minReg=1 last> LCL_VAR BB51 regmask=[allInt] minReg=1> CAST BB51 regmask=[allInt] minReg=1> LCL_VAR BB51 regmask=[allInt] minReg=1 last regOptional> BB51 regmask=[allInt] minReg=1 last> MUL BB51 regmask=[allInt] minReg=1> BB51 regmask=[allInt] minReg=1 last> RSZ BB51 regmask=[allInt] minReg=1> BB51 regmask=[allInt] minReg=1 last> ADD BB51 regmask=[allInt] minReg=1> LCL_VAR BB51 regmask=[allInt] minReg=1> CAST BB51 regmask=[allInt] minReg=1> BB51 regmask=[allInt] minReg=1 last regOptional> BB51 regmask=[allInt] minReg=1 last> MUL BB51 regmask=[allInt] minReg=1> BB51 regmask=[allInt] minReg=1 last> RSZ BB51 regmask=[allInt] minReg=1> BB51 regmask=[allInt] minReg=1 last> CAST BB51 regmask=[allInt] minReg=1> BB51 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB51 regmask=[allInt] minReg=1> BB51 regmask=[rax] minReg=1> LCL_VAR BB51 regmask=[rax] minReg=1 fixed> LCL_VAR BB51 regmask=[rcx rbx rbp rsi rdi r8-r15] minReg=1 last delay regOptional> BB51 regmask=[rax] minReg=1 last> BB51 regmask=[rdx] minReg=1 last> BB51 regmask=[rdx] minReg=1> UMOD BB51 regmask=[rdx] minReg=1 fixed> BB51 regmask=[allInt] minReg=1 last> LCL_VAR BB51 regmask=[allInt] minReg=1 regOptional> EQ BB51 regmask=[allInt] minReg=1> BB51 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB51 regmask=[allInt] minReg=1> LCL_VAR BB51 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB51 regmask=[allInt] minReg=1> LCL_VAR BB51 regmask=[allInt] minReg=1 last regOptional> BB52 regmask=[rcx] minReg=1> LCL_VAR BB52 regmask=[rcx] minReg=1 fixed> BB52 regmask=[rcx] minReg=1> PUTARG_REG BB52 regmask=[rcx] minReg=1 fixed> BB52 regmask=[rdx] minReg=1> LCL_VAR BB52 regmask=[rdx] minReg=1 last fixed> BB52 regmask=[rdx] minReg=1> PUTARG_REG BB52 regmask=[rdx] minReg=1 fixed> BB52 regmask=[rcx] minReg=1> BB52 regmask=[rcx] minReg=1 last fixed> BB52 regmask=[rdx] minReg=1> BB52 regmask=[rdx] minReg=1 last fixed> BB52 regmask=[rax] minReg=1 last> BB52 regmask=[rcx] minReg=1 last> BB52 regmask=[rdx] minReg=1 last> BB52 regmask=[r8] minReg=1 last> BB52 regmask=[r9] minReg=1 last> BB52 regmask=[r10] minReg=1 last> BB52 regmask=[r11] minReg=1 last> LCL_VAR BB53 regmask=[allInt] minReg=1> LCL_VAR BB53 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB53 regmask=[allInt] minReg=1 last> CAST BB53 regmask=[allInt] minReg=1> LCL_VAR BB53 regmask=[allInt] minReg=1 last> BB53 regmask=[allInt] minReg=1 last> LEA BB53 regmask=[allInt] minReg=1> BB53 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB53 regmask=[allInt] minReg=1> LCL_VAR BB53 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB53 regmask=[allInt] minReg=1> LCL_VAR BB54 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB54 regmask=[allInt] minReg=1> LCL_VAR BB54 regmask=[allInt] minReg=1> ADD BB54 regmask=[allInt] minReg=1> LCL_VAR BB54 regmask=[allInt] minReg=1> BB54 regmask=[allInt] minReg=1 last> LCL_VAR BB54 regmask=[allInt] minReg=1> IND BB54 regmask=[allInt] minReg=1> BB54 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB54 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> CAST BB55 regmask=[allInt] minReg=1> BB55 regmask=[allInt] minReg=1 last> MUL BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> BB55 regmask=[allInt] minReg=1 last> LEA BB55 regmask=[allInt] minReg=1> BB55 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1 last> LCL_VAR BB55 regmask=[allInt] minReg=1> IND BB55 regmask=[allInt] minReg=1> BB55 regmask=[allInt] minReg=1 last> ADD BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> BB55 regmask=[allInt] minReg=1 last> BB55 regmask=[rcx] minReg=1> LCL_VAR BB55 regmask=[rcx] minReg=1 fixed> BB55 regmask=[rdx] minReg=1> LCL_VAR BB55 regmask=[rdx] minReg=1 last fixed> BB55 regmask=[rax] minReg=1 last> BB55 regmask=[rcx] minReg=1 last> BB55 regmask=[rdx] minReg=1 last> BB55 regmask=[r8] minReg=1 last> BB55 regmask=[r9] minReg=1 last> BB55 regmask=[r10] minReg=1 last> BB55 regmask=[r11] minReg=1 last> BB55 regmask=[mm0] minReg=1 last> BB55 regmask=[mm1] minReg=1 last> BB55 regmask=[mm2] minReg=1 last> BB55 regmask=[mm3] minReg=1 last> BB55 regmask=[mm4] minReg=1 last> BB55 regmask=[mm5] minReg=1 last> LCL_VAR BB55 regmask=[allInt] minReg=1 last> LEA BB55 regmask=[rcx] minReg=1> BB55 regmask=[rcx] minReg=1> BB55 regmask=[rcx] minReg=1 last fixed> BB55 regmask=[rdx] minReg=1> LCL_VAR BB55 regmask=[rdx] minReg=1 last fixed> BB55 regmask=[rax] minReg=1 last> BB55 regmask=[rcx] minReg=1 last> BB55 regmask=[rdx] minReg=1 last> BB55 regmask=[r8] minReg=1 last> BB55 regmask=[r9] minReg=1 last> BB55 regmask=[r10] minReg=1 last> BB55 regmask=[r11] minReg=1 last> BB55 regmask=[mm0] minReg=1 last> BB55 regmask=[mm1] minReg=1 last> BB55 regmask=[mm2] minReg=1 last> BB55 regmask=[mm3] minReg=1 last> BB55 regmask=[mm4] minReg=1 last> BB55 regmask=[mm5] minReg=1 last> LCL_VAR BB55 regmask=[allInt] minReg=1 last> ADD BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1 last> BB55 regmask=[allInt] minReg=1 last> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1 last regOptional> BB56 regmask=[rdx] minReg=1> LCL_VAR BB56 regmask=[rdx] minReg=1 last fixed> BB56 regmask=[rdx] minReg=1> PUTARG_REG BB56 regmask=[rdx] minReg=1 fixed> CNS_INT BB56 regmask=[rcx] minReg=1> BB56 regmask=[rcx] minReg=1> BB56 regmask=[rcx] minReg=1 last fixed> BB56 regmask=[rcx] minReg=1> PUTARG_REG BB56 regmask=[rcx] minReg=1 fixed> BB56 regmask=[rdx] minReg=1> BB56 regmask=[rdx] minReg=1 last fixed> BB56 regmask=[rcx] minReg=1> BB56 regmask=[rcx] minReg=1 last fixed> BB56 regmask=[rax] minReg=1 last> BB56 regmask=[rcx] minReg=1 last> BB56 regmask=[rdx] minReg=1 last> BB56 regmask=[r8] minReg=1 last> BB56 regmask=[r9] minReg=1 last> BB56 regmask=[r10] minReg=1 last> BB56 regmask=[r11] minReg=1 last> BB56 regmask=[rax] minReg=1> CALL BB56 regmask=[rax] minReg=1 fixed> BB56 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB57 regmask=[allInt] minReg=1 last> IND BB57 regmask=[rdx] minReg=1> BB57 regmask=[rdx] minReg=1> BB57 regmask=[rdx] minReg=1 last fixed> BB57 regmask=[rdx] minReg=1> PUTARG_REG BB57 regmask=[rdx] minReg=1 fixed> BB57 regmask=[rcx] minReg=1> LCL_VAR BB57 regmask=[rcx] minReg=1 fixed> BB57 regmask=[rcx] minReg=1> PUTARG_REG BB57 regmask=[rcx] minReg=1 fixed> CNS_INT BB57 regmask=[r8] minReg=1> BB57 regmask=[r8] minReg=1> BB57 regmask=[r8] minReg=1 last fixed> BB57 regmask=[r8] minReg=1> PUTARG_REG BB57 regmask=[r8] minReg=1 fixed> BB57 regmask=[rdx] minReg=1> BB57 regmask=[rdx] minReg=1 last fixed> BB57 regmask=[rcx] minReg=1> BB57 regmask=[rcx] minReg=1 last fixed> BB57 regmask=[r8] minReg=1> BB57 regmask=[r8] minReg=1 last fixed> BB57 regmask=[rax] minReg=1 last> BB57 regmask=[rcx] minReg=1 last> BB57 regmask=[rdx] minReg=1 last> BB57 regmask=[r8] minReg=1 last> BB57 regmask=[r9] minReg=1 last> BB57 regmask=[r10] minReg=1 last> BB57 regmask=[r11] minReg=1 last> CNS_INT BB58 regmask=[rax] minReg=1> BB58 regmask=[rax] minReg=1> BB58 regmask=[rax] minReg=1 last fixed> CNS_INT BB59 regmask=[rcx] minReg=1> BB59 regmask=[rcx] minReg=1> BB59 regmask=[rcx] minReg=1 last fixed> BB59 regmask=[rcx] minReg=1> PUTARG_REG BB59 regmask=[rcx] minReg=1 fixed> BB59 regmask=[rcx] minReg=1> BB59 regmask=[rcx] minReg=1 last fixed> BB59 regmask=[rax] minReg=1 last> BB59 regmask=[rcx] minReg=1 last> BB59 regmask=[rdx] minReg=1 last> BB59 regmask=[r8] minReg=1 last> BB59 regmask=[r9] minReg=1 last> BB59 regmask=[r10] minReg=1 last> BB59 regmask=[r11] minReg=1 last> LCL_VAR BB60 regmask=[allInt] minReg=1> IND BB60 regmask=[allInt] minReg=1> BB60 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB60 regmask=[allInt] minReg=1> LCL_VAR BB60 regmask=[allInt] minReg=1> IND BB60 regmask=[allInt] minReg=1> BB60 regmask=[allInt] minReg=1 last> IND BB60 regmask=[allInt] minReg=1> BB60 regmask=[allInt] minReg=1 last> LCL_VAR BB61 regmask=[allInt] minReg=1 last> IND BB61 regmask=[allInt] minReg=1> BB61 regmask=[allInt] minReg=1 last> IND BB61 regmask=[allInt] minReg=1> BB61 regmask=[allInt] minReg=1 last> IND BB61 regmask=[allInt] minReg=1> BB61 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB61 regmask=[allInt] minReg=1> BB62 regmask=[rcx] minReg=1> LCL_VAR BB62 regmask=[rcx] minReg=1 last fixed> BB62 regmask=[rcx] minReg=1> PUTARG_REG BB62 regmask=[rcx] minReg=1 fixed> CNS_INT BB62 regmask=[rdx] minReg=1> BB62 regmask=[rdx] minReg=1> BB62 regmask=[rdx] minReg=1 last fixed> BB62 regmask=[rdx] minReg=1> PUTARG_REG BB62 regmask=[rdx] minReg=1 fixed> BB62 regmask=[rcx] minReg=1> BB62 regmask=[rcx] minReg=1 last fixed> BB62 regmask=[rdx] minReg=1> BB62 regmask=[rdx] minReg=1 last fixed> BB62 regmask=[rax] minReg=1 last> BB62 regmask=[rcx] minReg=1 last> BB62 regmask=[rdx] minReg=1 last> BB62 regmask=[r8] minReg=1 last> BB62 regmask=[r9] minReg=1 last> BB62 regmask=[r10] minReg=1 last> BB62 regmask=[r11] minReg=1 last> BB62 regmask=[rax] minReg=1> CALL BB62 regmask=[rax] minReg=1 fixed> BB62 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB62 regmask=[allInt] minReg=1> BB63 regmask=[rcx] minReg=1> LCL_VAR BB63 regmask=[rcx] minReg=1 last fixed> BB63 regmask=[rcx] minReg=1> PUTARG_REG BB63 regmask=[rcx] minReg=1 fixed> BB63 regmask=[rdx] minReg=1> LCL_VAR BB63 regmask=[rdx] minReg=1 last fixed> BB63 regmask=[rdx] minReg=1> PUTARG_REG BB63 regmask=[rdx] minReg=1 fixed> BB63 regmask=[rcx] minReg=1> BB63 regmask=[rcx] minReg=1 last fixed> BB63 regmask=[rdx] minReg=1> BB63 regmask=[rdx] minReg=1 last fixed> BB63 regmask=[rax] minReg=1 last> BB63 regmask=[rcx] minReg=1 last> BB63 regmask=[rdx] minReg=1 last> BB63 regmask=[r8] minReg=1 last> BB63 regmask=[r9] minReg=1 last> BB63 regmask=[r10] minReg=1 last> BB63 regmask=[r11] minReg=1 last> LCL_VAR BB64 regmask=[allInt] minReg=1> IND BB64 regmask=[allInt] minReg=1> BB64 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB64 regmask=[allInt] minReg=1> LCL_VAR BB64 regmask=[allInt] minReg=1> IND BB64 regmask=[allInt] minReg=1> BB64 regmask=[allInt] minReg=1 last> IND BB64 regmask=[allInt] minReg=1> BB64 regmask=[allInt] minReg=1 last> LCL_VAR BB65 regmask=[allInt] minReg=1 last> IND BB65 regmask=[allInt] minReg=1> BB65 regmask=[allInt] minReg=1 last> IND BB65 regmask=[allInt] minReg=1> BB65 regmask=[allInt] minReg=1 last> IND BB65 regmask=[allInt] minReg=1> BB65 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB65 regmask=[allInt] minReg=1> BB66 regmask=[rcx] minReg=1> LCL_VAR BB66 regmask=[rcx] minReg=1 last fixed> BB66 regmask=[rcx] minReg=1> PUTARG_REG BB66 regmask=[rcx] minReg=1 fixed> CNS_INT BB66 regmask=[rdx] minReg=1> BB66 regmask=[rdx] minReg=1> BB66 regmask=[rdx] minReg=1 last fixed> BB66 regmask=[rdx] minReg=1> PUTARG_REG BB66 regmask=[rdx] minReg=1 fixed> BB66 regmask=[rcx] minReg=1> BB66 regmask=[rcx] minReg=1 last fixed> BB66 regmask=[rdx] minReg=1> BB66 regmask=[rdx] minReg=1 last fixed> BB66 regmask=[rax] minReg=1 last> BB66 regmask=[rcx] minReg=1 last> BB66 regmask=[rdx] minReg=1 last> BB66 regmask=[r8] minReg=1 last> BB66 regmask=[r9] minReg=1 last> BB66 regmask=[r10] minReg=1 last> BB66 regmask=[r11] minReg=1 last> BB66 regmask=[rax] minReg=1> CALL BB66 regmask=[rax] minReg=1 fixed> BB66 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB66 regmask=[allInt] minReg=1> BB67 regmask=[rcx] minReg=1> LCL_VAR BB67 regmask=[rcx] minReg=1 last fixed> BB67 regmask=[rcx] minReg=1> PUTARG_REG BB67 regmask=[rcx] minReg=1 fixed> BB67 regmask=[rdx] minReg=1> LCL_VAR BB67 regmask=[rdx] minReg=1 last fixed> BB67 regmask=[rdx] minReg=1> PUTARG_REG BB67 regmask=[rdx] minReg=1 fixed> BB67 regmask=[rcx] minReg=1> BB67 regmask=[rcx] minReg=1 last fixed> BB67 regmask=[rdx] minReg=1> BB67 regmask=[rdx] minReg=1 last fixed> BB67 regmask=[rax] minReg=1 last> BB67 regmask=[rcx] minReg=1 last> BB67 regmask=[rdx] minReg=1 last> BB67 regmask=[r8] minReg=1 last> BB67 regmask=[r9] minReg=1 last> BB67 regmask=[r10] minReg=1 last> BB67 regmask=[r11] minReg=1 last> BB68 regmask=[rax] minReg=1 last> BB68 regmask=[rcx] minReg=1 last> BB68 regmask=[rdx] minReg=1 last> BB68 regmask=[r8] minReg=1 last> BB68 regmask=[r9] minReg=1 last> BB68 regmask=[r10] minReg=1 last> BB68 regmask=[r11] minReg=1 last> BB69 regmask=[allInt] minReg=1 regOptional> BB69 regmask=[rax] minReg=1 last> BB69 regmask=[rcx] minReg=1 last> BB69 regmask=[rdx] minReg=1 last> BB69 regmask=[r8] minReg=1 last> BB69 regmask=[r9] minReg=1 last> BB69 regmask=[r10] minReg=1 last> BB69 regmask=[r11] minReg=1 last> BB69 regmask=[allInt] minReg=1 regOptional> BB69 regmask=[allInt] minReg=1 regOptional> VAR REFPOSITIONS BEFORE ALLOCATION --- V00 (Interval 0) BB00 regmask=[rcx] minReg=1 fixed regOptional> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB03 regmask=[rcx] minReg=1 fixed> LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB19 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB44 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB47 regmask=[allInt] minReg=1> LCL_VAR BB47 regmask=[allInt] minReg=1> LCL_VAR BB47 regmask=[allInt] minReg=1> LCL_VAR BB48 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[rcx] minReg=1 fixed> LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB54 regmask=[allInt] minReg=1> LCL_VAR BB54 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB57 regmask=[rcx] minReg=1 fixed> LCL_VAR BB60 regmask=[allInt] minReg=1> LCL_VAR BB64 regmask=[allInt] minReg=1> BB69 regmask=[allInt] minReg=1 regOptional> BB69 regmask=[allInt] minReg=1 regOptional> BB69 regmask=[allInt] minReg=1 regOptional> --- V01 (Interval 1) BB00 regmask=[rdx] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB12 regmask=[rdx] minReg=1 fixed> LCL_VAR BB13 regmask=[rcx] minReg=1 fixed> LCL_VAR BB13 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[r8] minReg=1 fixed> LCL_VAR BB37 regmask=[r8] minReg=1 fixed> LCL_VAR BB55 regmask=[rdx] minReg=1 last fixed> LCL_VAR BB63 regmask=[rdx] minReg=1 last fixed> LCL_VAR BB67 regmask=[rdx] minReg=1 last fixed> --- V02 (Interval 2) BB00 regmask=[r8] minReg=1 fixed regOptional> LCL_VAR BB29 regmask=[rdx] minReg=1 last fixed> LCL_VAR BB39 regmask=[rdx] minReg=1 last fixed> LCL_VAR BB55 regmask=[rdx] minReg=1 last fixed> --- V03 (Interval 3) BB00 regmask=[r9] minReg=1 fixed regOptional> LCL_VAR BB28 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB30 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB38 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB40 regmask=[allInt] minReg=1 last regOptional> BB43 regmask=[allInt] minReg=1 regOptional> --- V04 (Interval 4) STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB47 regmask=[allInt] minReg=1> STORE_LCL_VAR BB54 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB57 regmask=[allInt] minReg=1 last> --- V05 (Interval 5) STORE_LCL_VAR BB08 regmask=[allInt] minReg=1> LCL_VAR BB08 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB12 regmask=[rcx] minReg=1 fixed> LCL_VAR BB18 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB37 regmask=[rcx] minReg=1 fixed> LCL_VAR BB56 regmask=[rdx] minReg=1 last fixed> --- V06 (Interval 6) STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[rax] minReg=1 fixed> LCL_VAR BB24 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB51 regmask=[allInt] minReg=1> LCL_VAR BB51 regmask=[rax] minReg=1 fixed> LCL_VAR BB55 regmask=[allInt] minReg=1 last> --- V07 (Interval 7) STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB42 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB42 regmask=[allInt] minReg=1> LCL_VAR BB42 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1 last regOptional> --- V08 (Interval 8) STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> STORE_LCL_VAR BB53 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1 last> --- V09 (Interval 9) STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB24 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB26 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB42 regmask=[allInt] minReg=1> BB43 regmask=[allInt] minReg=1 regOptional> --- V10 (Interval 10) STORE_LCL_VAR BB45 regmask=[allInt] minReg=1> STORE_LCL_VAR BB54 regmask=[allInt] minReg=1> LCL_VAR BB54 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1 last> --- V11 (Interval 11) STORE_LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[allInt] minReg=1> LCL_VAR BB55 regmask=[rcx] minReg=1 fixed> LCL_VAR BB55 regmask=[allInt] minReg=1 last> --- V12 (Interval 12) STORE_LCL_VAR BB22 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[rcx] minReg=1 fixed> LCL_VAR BB25 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> --- V13 (Interval 13) STORE_LCL_VAR BB48 regmask=[allInt] minReg=1> LCL_VAR BB48 regmask=[allInt] minReg=1> LCL_VAR BB54 regmask=[allInt] minReg=1 last> --- V14 --- V15 (Interval 14) STORE_LCL_VAR BB12 regmask=[allInt] minReg=1> STORE_LCL_VAR BB13 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 last> --- V16 (Interval 15) STORE_LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB36 regmask=[rcx] minReg=1 last fixed> --- V17 (Interval 16) STORE_LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB37 regmask=[rdx] minReg=1 last fixed> --- V18 --- V19 (Interval 17) STORE_LCL_VAR BB35 regmask=[allInt] minReg=1> STORE_LCL_VAR BB36 regmask=[allInt] minReg=1> LCL_VAR BB37 regmask=[r11] minReg=1 fixed> LCL_VAR BB37 regmask=[allInt] minReg=1 last> --- V20 --- V21 (Interval 18) STORE_LCL_VAR BB64 regmask=[allInt] minReg=1> LCL_VAR BB64 regmask=[allInt] minReg=1> LCL_VAR BB65 regmask=[allInt] minReg=1 last> LCL_VAR BB66 regmask=[rcx] minReg=1 last fixed> --- V22 --- V23 (Interval 19) STORE_LCL_VAR BB65 regmask=[allInt] minReg=1> STORE_LCL_VAR BB66 regmask=[allInt] minReg=1> LCL_VAR BB67 regmask=[rcx] minReg=1 last fixed> --- V24 (Interval 20) STORE_LCL_VAR BB19 regmask=[allInt] minReg=1> LCL_VAR BB19 regmask=[allInt] minReg=1> LCL_VAR BB21 regmask=[rcx] minReg=1 last fixed> --- V25 (Interval 21) STORE_LCL_VAR BB20 regmask=[allInt] minReg=1> STORE_LCL_VAR BB21 regmask=[allInt] minReg=1> LCL_VAR BB22 regmask=[rcx] minReg=1 last fixed> --- V26 (Interval 22) STORE_LCL_VAR BB60 regmask=[allInt] minReg=1> LCL_VAR BB60 regmask=[allInt] minReg=1> LCL_VAR BB61 regmask=[allInt] minReg=1 last> LCL_VAR BB62 regmask=[rcx] minReg=1 last fixed> --- V27 --- V28 (Interval 23) STORE_LCL_VAR BB61 regmask=[allInt] minReg=1> STORE_LCL_VAR BB62 regmask=[allInt] minReg=1> LCL_VAR BB63 regmask=[rcx] minReg=1 last fixed> --- V29 (Interval 24) STORE_LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB11 regmask=[rcx] minReg=1 last fixed> --- V30 --- V31 (Interval 25) STORE_LCL_VAR BB10 regmask=[allInt] minReg=1> STORE_LCL_VAR BB11 regmask=[allInt] minReg=1> LCL_VAR BB12 regmask=[r11] minReg=1 fixed> LCL_VAR BB12 regmask=[allInt] minReg=1 last> --- V32 --- V33 (Interval 26) STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1 last regOptional> --- V34 --- V35 (Interval 27) STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB05 regmask=[rcx] minReg=1 fixed> LCL_VAR BB05 regmask=[rdx] minReg=1 last fixed> --- V36 (Interval 28) STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1 last regOptional> --- V37 (Interval 29) STORE_LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB07 regmask=[rdx] minReg=1 last fixed> --- V38 (Interval 30) STORE_LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> --- V39 (Interval 31) STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> --- V40 (Interval 32) STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB16 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[rcx rbx rbp rsi rdi r8-r15] minReg=1 last delay regOptional> --- V41 (Interval 33) STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1 last regOptional> --- V42 (Interval 34) STORE_LCL_VAR BB16 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB18 regmask=[allInt] minReg=1> LCL_VAR BB18 regmask=[allInt] minReg=1 last> --- V43 (Interval 35) STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1 last regOptional> --- V44 --- V45 (Interval 36) STORE_LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB15 regmask=[rcx] minReg=1 fixed> LCL_VAR BB15 regmask=[rdx] minReg=1 last fixed> --- V46 (Interval 37) STORE_LCL_VAR BB16 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1 last regOptional> --- V47 --- V48 (Interval 38) STORE_LCL_VAR BB16 regmask=[allInt] minReg=1> LCL_VAR BB17 regmask=[rcx] minReg=1 fixed> LCL_VAR BB17 regmask=[rdx] minReg=1 last fixed> --- V49 (Interval 39) STORE_LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1 last regOptional> --- V50 (Interval 40) STORE_LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB46 regmask=[rdx] minReg=1 last fixed> --- V51 (Interval 41) STORE_LCL_VAR BB53 regmask=[allInt] minReg=1> LCL_VAR BB53 regmask=[allInt] minReg=1 last> --- V52 (Interval 42) STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB53 regmask=[allInt] minReg=1 last> --- V53 (Interval 43) STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB51 regmask=[allInt] minReg=1> LCL_VAR BB51 regmask=[rcx rbx rbp rsi rdi r8-r15] minReg=1 last delay regOptional> --- V54 (Interval 44) STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB51 regmask=[allInt] minReg=1 last regOptional> --- V55 (Interval 45) STORE_LCL_VAR BB51 regmask=[allInt] minReg=1> LCL_VAR BB51 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB53 regmask=[allInt] minReg=1> LCL_VAR BB53 regmask=[allInt] minReg=1 last> --- V56 (Interval 46) STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1 last regOptional> --- V57 --- V58 (Interval 47) STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB50 regmask=[rcx] minReg=1 fixed> LCL_VAR BB50 regmask=[rdx] minReg=1 last fixed> --- V59 (Interval 48) STORE_LCL_VAR BB51 regmask=[allInt] minReg=1> LCL_VAR BB51 regmask=[allInt] minReg=1 last regOptional> --- V60 --- V61 (Interval 49) STORE_LCL_VAR BB51 regmask=[allInt] minReg=1> LCL_VAR BB52 regmask=[rcx] minReg=1 fixed> LCL_VAR BB52 regmask=[rdx] minReg=1 last fixed> --- V62 (Interval 50) STORE_LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1 last> --- V63 (Interval 51) STORE_LCL_VAR BB47 regmask=[allInt] minReg=1> LCL_VAR BB47 regmask=[allInt] minReg=1> LCL_VAR BB47 regmask=[allInt] minReg=1 last> --- V64 (Interval 52) STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[rdx] minReg=1 last fixed> --- V65 (Interval 53) STORE_LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB26 regmask=[allInt] minReg=1 last> LCL_VAR BB29 regmask=[allInt] minReg=1 last> --- V66 (Interval 54) STORE_LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB39 regmask=[allInt] minReg=1 last> LCL_VAR BB42 regmask=[allInt] minReg=1 last> --- V67 (Interval 55) STORE_LCL_VAR BB34 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB35 regmask=[allInt] minReg=1 last> --- V68 (Interval 56) STORE_LCL_VAR BB09 regmask=[allInt] minReg=1> LCL_VAR BB09 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB10 regmask=[allInt] minReg=1 last> --- V69 (Interval 57) STORE_LCL_VAR BB19 regmask=[allInt] minReg=1> LCL_VAR BB19 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB20 regmask=[allInt] minReg=1 last> --- V70 (Interval 58) STORE_LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB24 regmask=[allInt] minReg=1> LCL_VAR BB25 regmask=[allInt] minReg=1 last> --- V71 (Interval 59) STORE_LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB33 regmask=[allInt] minReg=1> LCL_VAR BB34 regmask=[allInt] minReg=1 last> --- V72 (Interval 60) STORE_LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB53 regmask=[allInt] minReg=1 last regOptional> --- V73 (Interval 61) STORE_LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB04 regmask=[allInt] minReg=1> LCL_VAR BB06 regmask=[allInt] minReg=1> LCL_VAR BB14 regmask=[allInt] minReg=1> LCL_VAR BB16 regmask=[allInt] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB45 regmask=[allInt] minReg=1 last> LCL_VAR BB49 regmask=[allInt] minReg=1> LCL_VAR BB51 regmask=[allInt] minReg=1 last> --- V74 (Interval 62) STORE_LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1> LCL_VAR BB45 regmask=[allInt] minReg=1 last> --- V75 (Interval 63) STORE_LCL_VAR BB48 regmask=[allInt] minReg=1> LCL_VAR BB48 regmask=[allInt] minReg=1> LCL_VAR BB49 regmask=[rcx] minReg=1 last fixed> --- V76 (Interval 64) STORE_LCL_VAR BB23 regmask=[allInt] minReg=1> LCL_VAR BB23 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB26 regmask=[allInt] minReg=1 last regOptional> STORE_LCL_VAR BB32 regmask=[allInt] minReg=1> LCL_VAR BB32 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB42 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB45 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB47 regmask=[allInt] minReg=1 last regOptional> LCL_VAR BB48 regmask=[allInt] minReg=1 last regOptional> Allocating Registers -------------------- The following table has one or more rows for each RefPosition that is handled during allocation. The first column provides the basic information about the RefPosition, with its type (e.g. Def, Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the action taken during allocation (e.g. Alloc a new register, or Keep an existing one). The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which may increase during allocation, in which case additional columns will appear. Registers which are not marked modified have ---- in their column. --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+ | |V0 a|V1 a| | | | |V2 a|V3 a| 0.#0 V0 Parm ORDER(A) rsi | | |V1 a| | |V0 a| |V2 a|V3 a| 0.#1 V1 Parm ORDER(A) rdi | | | | | |V0 a|V1 a|V2 a|V3 a| 0.#2 V3 Parm ORDER(A) rbx | | | |V3 a| |V0 a|V1 a|V2 a| | 0.#3 V2 Parm ORDER(A) rbp | | | |V3 a|V2 a|V0 a|V1 a| | | 1.#4 BB1 PredBB0 | | | |V3 a|V2 a|V0 a|V1 a| | | 9.#5 V1 Use Keep rdi | | | |V3 a|V2 a|V0 a|V1 a| | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 13.#6 BB2 PredBB1 | | | |V3 a|V2 a|V0 a|V1 a| | | 25.#7 V0 Use Keep rsi | | | |V3 a|V2 a|V0 a|V1 a| | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 29.#8 BB3 PredBB2 | | | |V3 a|V2 a|V0 a|V1 a| | | 33.#9 rcx Fixd Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | 33.#10 V0 Use Copy rcx | |V0 a| |V3 a|V2 a|V0 a|V1 a| | | 34.#11 rcx Fixd Keep rcx | |V0 a| |V3 a|V2 a|V0 a|V1 a| | | 34.#12 I65 Def Alloc rcx | |I65 a| |V3 a|V2 a|V0 a|V1 a| | | 36.#13 C66 Def Alloc rdx | |I65 a|C66 a|V3 a|V2 a|V0 a|V1 a| | | 37.#14 rdx Fixd Keep rdx | |I65 a|C66 a|V3 a|V2 a|V0 a|V1 a| | | 37.#15 C66 Use * Keep rdx | |I65 a|C66 a|V3 a|V2 a|V0 a|V1 a| | | 38.#16 rdx Fixd Keep rdx | |I65 a| |V3 a|V2 a|V0 a|V1 a| | | 38.#17 I67 Def Alloc rdx | |I65 a|I67 a|V3 a|V2 a|V0 a|V1 a| | | 39.#18 rcx Fixd Keep rcx | |I65 a|I67 a|V3 a|V2 a|V0 a|V1 a| | | 39.#19 I65 Use * Keep rcx | |I65 a|I67 a|V3 a|V2 a|V0 a|V1 a| | | 39.#20 rdx Fixd Keep rdx | |I65 a|I67 a|V3 a|V2 a|V0 a|V1 a| | | 39.#21 I67 Use * Keep rdx | |I65 a|I67 a|V3 a|V2 a|V0 a|V1 a| | | 40.#22 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | 40.#23 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | 40.#24 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| | | 40.#25 r8 Kill Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | | 40.#26 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | | 40.#27 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | 40.#28 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | 40.#29 rax Fixd Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | 40.#30 I68 Def * Alloc rax |I68 a| | |V3 a|V2 a|V0 a|V1 a| | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 41.#31 BB4 PredBB2 | | | |V3 a|V2 a|V0 a|V1 a| | | 53.#32 V0 Use Keep rsi | | | |V3 a|V2 a|V0 a|V1 a| | | 54.#33 I69 Def BSFIT(A) rcx | |I69 a| |V3 a|V2 a|V0 a|V1 a| | | 55.#34 I69 Use * Keep rcx | |I69 a| |V3 a|V2 a|V0 a|V1 a| | | 56.#35 V33 Def COVRS(A) rcx | |V33 a| |V3 a|V2 a|V0 a|V1 a| | | 60.#36 C70 Def BSFIT(A) rdx | |V33 a|C70 a|V3 a|V2 a|V0 a|V1 a| | | 61.#37 C70 Use * Keep rdx | |V33 a|C70 a|V3 a|V2 a|V0 a|V1 a| | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 62.#38 I71 Def ORDER(A) r14 | |V33 a|C70 i|V3 a|V2 a|V0 a|V1 a| | |I71 a| 63.#39 I71 Use * Keep r14 | |V33 a|C70 i|V3 a|V2 a|V0 a|V1 a| | |I71 a| 64.#40 V73 Def COVRS(A) r14 | |V33 a|C70 i|V3 a|V2 a|V0 a|V1 a| | |V73 a| 69.#41 V73 Use Keep r14 | |V33 a|C70 i|V3 a|V2 a|V0 a|V1 a| | |V73 a| 70.#42 V35 Def COVRS(A) rdx | |V33 a|V35 a|V3 a|V2 a|V0 a|V1 a| | |V73 a| 77.#43 V33 Use * Keep rcx | |V33 a|V35 a|V3 a|V2 a|V0 a|V1 a| | |V73 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 81.#44 BB5 PredBB4 | | |V35 a|V3 a|V2 a|V0 a|V1 a| | |V73 a| 87.#45 rcx Fixd Keep rcx | | |V35 a|V3 a|V2 a|V0 a|V1 a| | |V73 a| 87.#46 V35 Use Copy rcx | |V35 a|V35 a|V3 a|V2 a|V0 a|V1 a| | |V73 a| 88.#47 rcx Fixd Keep rcx | |V35 a|V35 a|V3 a|V2 a|V0 a|V1 a| | |V73 a| 88.#48 I72 Def Alloc rcx | |I72 a|V35 a|V3 a|V2 a|V0 a|V1 a| | |V73 a| 91.#49 rdx Fixd Keep rdx | |I72 a|V35 a|V3 a|V2 a|V0 a|V1 a| | |V73 a| 91.#50 V35 Use * Keep rdx | |I72 a|V35 a|V3 a|V2 a|V0 a|V1 a| | |V73 a| 92.#51 rdx Fixd Keep rdx | |I72 a| |V3 a|V2 a|V0 a|V1 a| | |V73 a| 92.#52 I73 Def Alloc rdx | |I72 a|I73 a|V3 a|V2 a|V0 a|V1 a| | |V73 a| 93.#53 rcx Fixd Keep rcx | |I72 a|I73 a|V3 a|V2 a|V0 a|V1 a| | |V73 a| 93.#54 I72 Use * Keep rcx | |I72 a|I73 a|V3 a|V2 a|V0 a|V1 a| | |V73 a| 93.#55 rdx Fixd Keep rdx | |I72 a|I73 a|V3 a|V2 a|V0 a|V1 a| | |V73 a| 93.#56 I73 Use * Keep rdx | |I72 a|I73 a|V3 a|V2 a|V0 a|V1 a| | |V73 a| 94.#57 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a| 94.#58 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a| 94.#59 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a| 94.#60 r8 Kill Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a| 94.#61 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a| 94.#62 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a| 94.#63 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 95.#64 BB6 PredBB4 | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a| 103.#65 V0 Use Keep rsi | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 104.#66 I74 Def ORDER(A) r15 | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a|I74 a| 105.#67 I74 Use * Keep r15 | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a|I74 a| 106.#68 V4 Def COVRS(A) r15 | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 113.#69 V4 Use Keep r15 | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 114.#70 I75 Def BSFIT(A) rcx | |I75 a| |V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 115.#71 I75 Use * Keep rcx | |I75 a| |V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 116.#72 V36 Def COVRS(A) rcx | |V36 a| |V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 121.#73 V73 Use Keep r14 | |V36 a| |V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 122.#74 V37 Def COVRS(A) rdx | |V36 a|V37 a|V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 129.#75 V36 Use * Keep rcx | |V36 a|V37 a|V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 133.#76 BB7 PredBB6 | | |V37 a|V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 138.#77 C76 Def BSFIT(A) rcx | |C76 a|V37 a|V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 139.#78 C76 Use * Keep rcx | |C76 a|V37 a|V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 140.#79 I77 Def Alloc rcx | |I77 a|V37 a|V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 141.#80 rcx Fixd Keep rcx | |I77 a|V37 a|V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 141.#81 I77 Use * Keep rcx | |I77 a|V37 a|V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 142.#82 rcx Fixd Keep rcx | | |V37 a|V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 142.#83 I78 Def Alloc rcx | |I78 a|V37 a|V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 145.#84 rdx Fixd Keep rdx | |I78 a|V37 a|V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 145.#85 V37 Use * Keep rdx | |I78 a|V37 a|V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 146.#86 rdx Fixd Keep rdx | |I78 a| |V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 146.#87 I79 Def Alloc rdx | |I78 a|I79 a|V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 147.#88 rcx Fixd Keep rcx | |I78 a|I79 a|V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 147.#89 I78 Use * Keep rcx | |I78 a|I79 a|V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 147.#90 rdx Fixd Keep rdx | |I78 a|I79 a|V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 147.#91 I79 Use * Keep rdx | |I78 a|I79 a|V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 148.#92 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 148.#93 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 148.#94 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 148.#95 r8 Kill Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 148.#96 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 148.#97 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 148.#98 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 149.#99 BB8 PredBB6 | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| 157.#100 V0 Use Keep rsi | | | |V3 a|V2 a|V0 a|V1 a| | |V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 158.#101 I80 Def ORDER(A) r12 | | | |V3 a|V2 a|V0 a|V1 a| | |I80 a|V73 a|V4 a| 159.#102 I80 Use * Keep r12 | | | |V3 a|V2 a|V0 a|V1 a| | |I80 a|V73 a|V4 a| 160.#103 V5 Def COVRS(A) r12 | | | |V3 a|V2 a|V0 a|V1 a| | |V5 a|V73 a|V4 a| 167.#104 V5 Use Keep r12 | | | |V3 a|V2 a|V0 a|V1 a| | |V5 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r12 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 171.#105 BB9 PredBB8 | | | |V3 a|V2 a|V0 a|V1 a| | |V5 a|V73 a|V4 a| 177.#106 V0 Use Keep rsi | | | |V3 a|V2 a|V0 a|V1 a| | |V5 a|V73 a|V4 a| 178.#107 I81 Def RELPR(A) rcx | |I81 a| |V3 a|V2 a|V0 a|V1 a| | |V5 a|V73 a|V4 a| 179.#108 I81 Use * Keep rcx | |I81 a| |V3 a|V2 a|V0 a|V1 a| | |V5 a|V73 a|V4 a| 180.#109 V29 Def COVRS(A) rcx | |V29 a| |V3 a|V2 a|V0 a|V1 a| | |V5 a|V73 a|V4 a| 185.#110 V29 Use Keep rcx | |V29 a| |V3 a|V2 a|V0 a|V1 a| | |V5 a|V73 a|V4 a| 186.#111 I82 Def BSFIT(A) rdx | |V29 a|I82 a|V3 a|V2 a|V0 a|V1 a| | |V5 a|V73 a|V4 a| 187.#112 I82 Use * Keep rdx | |V29 a|I82 a|V3 a|V2 a|V0 a|V1 a| | |V5 a|V73 a|V4 a| 188.#113 I83 Def BSFIT(A) rdx | |V29 a|I83 a|V3 a|V2 a|V0 a|V1 a| | |V5 a|V73 a|V4 a| 191.#114 I83 Use * Keep rdx | |V29 a|I83 a|V3 a|V2 a|V0 a|V1 a| | |V5 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r11 |r12 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 192.#115 I84 Def COREL(A) r11 | |V29 a| |V3 a|V2 a|V0 a|V1 a| | |I84 a|V5 a|V73 a|V4 a| 193.#116 I84 Use * Keep r11 | |V29 a| |V3 a|V2 a|V0 a|V1 a| | |I84 a|V5 a|V73 a|V4 a| 194.#117 V68 Def COVRS(A) r11 | |V29 a| |V3 a|V2 a|V0 a|V1 a| | |V68 a|V5 a|V73 a|V4 a| 199.#118 V68 Use Keep r11 | |V29 a| |V3 a|V2 a|V0 a|V1 a| | |V68 a|V5 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r11 |r12 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 203.#119 BB10 PredBB9 | |V29 i| |V3 a|V2 a|V0 a|V1 a| | |V68 a|V5 a|V73 a|V4 a| 207.#120 V68 Use * Keep r11 | |V29 i| |V3 a|V2 a|V0 a|V1 a| | |V68 a|V5 a|V73 a|V4 a| 208.#121 V31 Def OWNPR(A) r11 | |V29 i| |V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r11 |r12 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 209.#122 BB11 PredBB9 | |V29 a| |V3 a|V2 a|V0 a|V1 a| | |V31 i|V5 a|V73 a|V4 a| 213.#123 rcx Fixd Keep rcx | |V29 a| |V3 a|V2 a|V0 a|V1 a| | |V31 i|V5 a|V73 a|V4 a| 213.#124 V29 Use * Keep rcx | |V29 a| |V3 a|V2 a|V0 a|V1 a| | |V31 i|V5 a|V73 a|V4 a| 214.#125 rcx Fixd Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | |V31 i|V5 a|V73 a|V4 a| 214.#126 I85 Def Alloc rcx | |I85 a| |V3 a|V2 a|V0 a|V1 a| | |V31 i|V5 a|V73 a|V4 a| 216.#127 C86 Def Alloc rdx | |I85 a|C86 a|V3 a|V2 a|V0 a|V1 a| | |V31 i|V5 a|V73 a|V4 a| 217.#128 rdx Fixd Keep rdx | |I85 a|C86 a|V3 a|V2 a|V0 a|V1 a| | |V31 i|V5 a|V73 a|V4 a| 217.#129 C86 Use * Keep rdx | |I85 a|C86 a|V3 a|V2 a|V0 a|V1 a| | |V31 i|V5 a|V73 a|V4 a| 218.#130 rdx Fixd Keep rdx | |I85 a| |V3 a|V2 a|V0 a|V1 a| | |V31 i|V5 a|V73 a|V4 a| 218.#131 I87 Def Alloc rdx | |I85 a|I87 a|V3 a|V2 a|V0 a|V1 a| | |V31 i|V5 a|V73 a|V4 a| 219.#132 rcx Fixd Keep rcx | |I85 a|I87 a|V3 a|V2 a|V0 a|V1 a| | |V31 i|V5 a|V73 a|V4 a| 219.#133 I85 Use * Keep rcx | |I85 a|I87 a|V3 a|V2 a|V0 a|V1 a| | |V31 i|V5 a|V73 a|V4 a| 219.#134 rdx Fixd Keep rdx | |I85 a|I87 a|V3 a|V2 a|V0 a|V1 a| | |V31 i|V5 a|V73 a|V4 a| 219.#135 I87 Use * Keep rdx | |I85 a|I87 a|V3 a|V2 a|V0 a|V1 a| | |V31 i|V5 a|V73 a|V4 a| 220.#136 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | |V31 i|V5 a|V73 a|V4 a| 220.#137 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | |V31 i|V5 a|V73 a|V4 a| 220.#138 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| | |V31 i|V5 a|V73 a|V4 a| 220.#139 r8 Kill Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | |V31 i|V5 a|V73 a|V4 a| 220.#140 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | |V31 i|V5 a|V73 a|V4 a| 220.#141 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | |V31 i|V5 a|V73 a|V4 a| 220.#142 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V73 a|V4 a| 220.#143 rax Fixd Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V73 a|V4 a| 220.#144 I88 Def Alloc rax |I88 a| | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V73 a|V4 a| 221.#145 I88 Use * Keep rax |I88 a| | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V73 a|V4 a| 222.#146 V31 Def THISA(A) r11 | | | |V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r11 |r12 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 223.#147 BB12 PredBB10 | | | |V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| 227.#148 rcx Fixd Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| 227.#149 V5 Use Copy rcx | |V5 a| |V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| 228.#150 rcx Fixd Keep rcx | |V5 a| |V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| 228.#151 I89 Def Alloc rcx | |I89 a| |V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| 231.#152 r11 Fixd Keep r11 | |I89 a| |V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| 231.#153 V31 Use Keep r11 | |I89 a| |V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| 232.#154 r11 Fixd Keep r11 | |I89 a| |V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| 232.#155 I90 Def PtArg r11 | |I89 a| |V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| 235.#156 rdx Fixd Keep rdx | |I89 a| |V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| 235.#157 V1 Use Copy rdx | |I89 a|V1 a|V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| 236.#158 rdx Fixd Keep rdx | |I89 a|V1 a|V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| 236.#159 I91 Def Alloc rdx | |I89 a|I91 a|V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| 241.#160 rcx Fixd Keep rcx | |I89 a|I91 a|V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| 241.#161 I89 Use * Keep rcx | |I89 a|I91 a|V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| 241.#162 r11 Fixd Keep r11 | |I89 a|I91 a|V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| 241.#163 I90 Use * PtArg r11 | |I89 a|I91 a|V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| 241.#164 rdx Fixd Keep rdx | |I89 a|I91 a|V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| 241.#165 I91 Use * Keep rdx | |I89 a|I91 a|V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| 241.#166 V31 Use * Keep r11 | |I89 a|I91 a|V3 a|V2 a|V0 a|V1 a| | |V31 a|V5 a|V73 a|V4 a| 242.#167 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | |Busy |V5 a|V73 a|V4 a| 242.#168 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | |Busy |V5 a|V73 a|V4 a| 242.#169 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| | |Busy |V5 a|V73 a|V4 a| 242.#170 r8 Kill Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | |Busy |V5 a|V73 a|V4 a| 242.#171 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | |Busy |V5 a|V73 a|V4 a| 242.#172 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | |Busy |V5 a|V73 a|V4 a| 242.#173 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V73 a|V4 a| 242.#174 rax Fixd Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V73 a|V4 a| 242.#175 I92 Def Alloc rax |I92 a| | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V73 a|V4 a| 243.#176 I92 Use * Keep rax |I92 a| | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 244.#177 V15 Def COVRS(A) r13 | | | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 245.#178 BB13 PredBB8 | | | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 251.#179 rcx Fixd Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 251.#180 V1 Use Copy rcx | |V1 a| |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 252.#181 rcx Fixd Keep rcx | |V1 a| |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 252.#182 I93 Def Alloc rcx | |I93 a| |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 255.#183 V1 Use Keep rdi | |I93 a| |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 256.#184 I94 Def ORDER(A) rax |I94 a|I93 a| |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 259.#185 I94 Use * Keep rax |I94 a|I93 a| |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 260.#186 I95 Def ORDER(A) rax |I95 a|I93 a| |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 265.#187 rcx Fixd Keep rcx |I95 a|I93 a| |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 265.#188 I93 Use * Keep rcx |I95 a|I93 a| |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 265.#189 I95 Use * Keep rax |I95 a|I93 a| |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 266.#190 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 266.#191 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 266.#192 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 266.#193 r8 Kill Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 266.#194 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 266.#195 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 266.#196 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 266.#197 rax Fixd Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 266.#198 I96 Def Alloc rax |I96 a| | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 267.#199 I96 Use * Keep rax |I96 a| | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 i|V73 a|V4 a| 268.#200 V15 Def Keep r13 | | | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 269.#201 BB14 PredBB12 | | | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 a|V73 a|V4 a| 273.#202 V15 Use * Keep r13 | | | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V15 a|V73 a|V4 a| 274.#203 V6 Def COVRS(A) r13 | | | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V6 a|V73 a|V4 a| 278.#204 C97 Def ORDER(A) rax |C97 a| | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V6 a|V73 a|V4 a| 279.#205 C97 Use * Keep rax |C97 a| | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V6 a|V73 a|V4 a| 280.#206 V7 Def ORDER(A) rax |V7 a| | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V6 a|V73 a|V4 a| 287.#207 V0 Use Keep rsi |V7 a| | |V3 a|V2 a|V0 a|V1 a| | | |V5 a|V6 a|V73 a|V4 a| 288.#208 I98 Def ORDER(A) r8 |V7 a| | |V3 a|V2 a|V0 a|V1 a|I98 a| | |V5 a|V6 a|V73 a|V4 a| 289.#209 I98 Use * Keep r8 |V7 a| | |V3 a|V2 a|V0 a|V1 a|I98 a| | |V5 a|V6 a|V73 a|V4 a| 290.#210 V39 Def ORDER(A) r8 |V7 a| | |V3 a|V2 a|V0 a|V1 a|V39 a| | |V5 a|V6 a|V73 a|V4 a| 297.#211 V39 Use Keep r8 |V7 a| | |V3 a|V2 a|V0 a|V1 a|V39 a| | |V5 a|V6 a|V73 a|V4 a| 298.#212 I99 Def ORDER(A) r9 |V7 a| | |V3 a|V2 a|V0 a|V1 a|V39 a|I99 a| |V5 a|V6 a|V73 a|V4 a| 299.#213 I99 Use * Keep r9 |V7 a| | |V3 a|V2 a|V0 a|V1 a|V39 a|I99 a| |V5 a|V6 a|V73 a|V4 a| 300.#214 V40 Def ORDER(A) r9 |V7 a| | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a| |V5 a|V6 a|V73 a|V4 a| 307.#215 V0 Use Keep rsi |V7 a| | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a| |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 308.#216 I100 Def ORDER(A) r10 |V7 a| | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|I100a| |V5 a|V6 a|V73 a|V4 a| 309.#217 I100 Use * Keep r10 |V7 a| | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|I100a| |V5 a|V6 a|V73 a|V4 a| 310.#218 V41 Def ORDER(A) r10 |V7 a| | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 317.#219 V40 Use Keep r9 |V7 a| | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 318.#220 I101 Def BSFIT(A) rcx |V7 a|I101a| |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 319.#221 I101 Use * Keep rcx |V7 a|I101a| |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 320.#222 V43 Def COVRS(A) rcx |V7 a|V43 a| |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 327.#223 V73 Use Keep r14 |V7 a|V43 a| |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 328.#224 V45 Def COVRS(A) rdx |V7 a|V43 a|V45 a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 335.#225 V43 Use * Keep rcx |V7 a|V43 a|V45 a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 339.#226 BB15 PredBB14 |V7 a| |V45 a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 345.#227 rcx Fixd Keep rcx |V7 a| |V45 a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 345.#228 V45 Use Copy rcx |V7 a|V45 a|V45 a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 346.#229 rcx Fixd Keep rcx |V7 a|V45 a|V45 a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 346.#230 I102 Def Alloc rcx |V7 a|I102a|V45 a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 349.#231 rdx Fixd Keep rdx |V7 a|I102a|V45 a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 349.#232 V45 Use * Keep rdx |V7 a|I102a|V45 a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 350.#233 rdx Fixd Keep rdx |V7 a|I102a| |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 350.#234 I103 Def Alloc rdx |V7 a|I102a|I103a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 351.#235 rcx Fixd Keep rcx |V7 a|I102a|I103a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 351.#236 I102 Use * Keep rcx |V7 a|I102a|I103a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 351.#237 rdx Fixd Keep rdx |V7 a|I102a|I103a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 351.#238 I103 Use * Keep rdx |V7 a|I102a|I103a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 352.#239 rax Kill Spill rax | | | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| Keep rax | | | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 352.#240 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 352.#241 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 352.#242 r8 Kill Spill r8 | | | |V3 a|V2 a|V0 a|V1 a| |V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| |V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 352.#243 r9 Kill Spill r9 | | | |V3 a|V2 a|V0 a|V1 a| | |V41 a| |V5 a|V6 a|V73 a|V4 a| Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | |V41 a| |V5 a|V6 a|V73 a|V4 a| 352.#244 r10 Kill Spill r10 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 352.#245 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 353.#246 BB16 PredBB14 |V7 a| | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 361.#247 V6 Use Keep r13 |V7 a| | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 362.#248 I104 Def BSFIT(A) rdx |V7 a| |I104a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 363.#249 V41 Use * Keep r10 |V7 a| |I104a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 363.#250 I104 Use * Keep rdx |V7 a| |I104a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V41 a| |V5 a|V6 a|V73 a|V4 a| 364.#251 I105 Def BSFIT(A) rdx |V7 a| |I105a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a| | |V5 a|V6 a|V73 a|V4 a| 367.#252 I105 Use * Keep rdx |V7 a| |I105a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a| | |V5 a|V6 a|V73 a|V4 a| 368.#253 I106 Def COVRS(A) rdx |V7 a| |I106a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a| | |V5 a|V6 a|V73 a|V4 a| 371.#254 I106 Use * Keep rdx |V7 a| |I106a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a| | |V5 a|V6 a|V73 a|V4 a| 372.#255 I107 Def COVRS(A) rdx |V7 a| |I107a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a| | |V5 a|V6 a|V73 a|V4 a| 375.#256 V40 Use Keep r9 |V7 a| |I107a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a| | |V5 a|V6 a|V73 a|V4 a| 376.#257 I108 Def BSFIT(A) rcx |V7 a|I108a|I107a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a| | |V5 a|V6 a|V73 a|V4 a| 377.#258 I107 Use * Keep rdx |V7 a|I108a|I107a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a| | |V5 a|V6 a|V73 a|V4 a| 377.#259 I108 Use * Keep rcx |V7 a|I108a|I107a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a| | |V5 a|V6 a|V73 a|V4 a| 378.#260 I109 Def BSFIT(A) rdx |V7 a| |I109a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a| | |V5 a|V6 a|V73 a|V4 a| 381.#261 I109 Use * Keep rdx |V7 a| |I109a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a| | |V5 a|V6 a|V73 a|V4 a| 382.#262 I110 Def COVRS(A) rdx |V7 a| |I110a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a| | |V5 a|V6 a|V73 a|V4 a| 383.#263 I110 Use * Keep rdx |V7 a| |I110a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a| | |V5 a|V6 a|V73 a|V4 a| 384.#264 I111 Def ORDER(A) r10 |V7 a| | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|I111a| |V5 a|V6 a|V73 a|V4 a| 385.#265 I111 Use * Keep r10 |V7 a| | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|I111a| |V5 a|V6 a|V73 a|V4 a| 386.#266 V42 Def ORDER(A) r10 |V7 a| | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V42 a| |V5 a|V6 a|V73 a|V4 a| 393.#267 rax Fixd Keep rax |V7 a| | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V42 a| |V5 a|V6 a|V73 a|V4 a| 393.#268 V6 Use Spill rax | | | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V42 a| |V5 a|V6 i|V73 a|V4 a| Copy rax |V6 a| | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V42 a| |V5 a|V6 a|V73 a|V4 a| 393.#269 V40 Use *D Keep r9 |V6 a| | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V42 a| |V5 a|V6 a|V73 a|V4 a| 394.#270 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V42 a| |V5 a|V6 a|V73 a|V4 a| 394.#271 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V42 a| |V5 a|V6 a|V73 a|V4 a| 394.#272 rdx Fixd Keep rdx | | | |V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V42 a| |V5 a|V6 a|V73 a|V4 a| 394.#273 I112 Def Alloc rdx | | |I112a|V3 a|V2 a|V0 a|V1 a|V39 a|V40 a|V42 a| |V5 a|V6 a|V73 a|V4 a| 397.#274 I112 Use * Keep rdx | | |I112a|V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 397.#275 V42 Use Keep r10 | | |I112a|V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 398.#276 I113 Def BSFIT(A) rcx | |I113a| |V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 399.#277 I113 Use * Keep rcx | |I113a| |V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 400.#278 V46 Def COVRS(A) rcx | |V46 a| |V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 407.#279 V73 Use Keep r14 | |V46 a| |V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 408.#280 V48 Def COVRS(A) rdx | |V46 a|V48 a|V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 415.#281 V46 Use * Keep rcx | |V46 a|V48 a|V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 419.#282 BB17 PredBB16 | | |V48 a|V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 425.#283 rcx Fixd Keep rcx | | |V48 a|V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 425.#284 V48 Use Copy rcx | |V48 a|V48 a|V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 426.#285 rcx Fixd Keep rcx | |V48 a|V48 a|V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 426.#286 I114 Def Alloc rcx | |I114a|V48 a|V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 429.#287 rdx Fixd Keep rdx | |I114a|V48 a|V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 429.#288 V48 Use * Keep rdx | |I114a|V48 a|V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 430.#289 rdx Fixd Keep rdx | |I114a| |V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 430.#290 I115 Def Alloc rdx | |I114a|I115a|V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 431.#291 rcx Fixd Keep rcx | |I114a|I115a|V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 431.#292 I114 Use * Keep rcx | |I114a|I115a|V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 431.#293 rdx Fixd Keep rdx | |I114a|I115a|V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 431.#294 I115 Use * Keep rdx | |I114a|I115a|V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 432.#295 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 432.#296 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 432.#297 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 432.#298 r8 Kill Spill r8 | | | |V3 a|V2 a|V0 a|V1 a| | |V42 a| |V5 a|V6 a|V73 a|V4 a| Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | |V42 a| |V5 a|V6 a|V73 a|V4 a| 432.#299 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | |V42 a| |V5 a|V6 a|V73 a|V4 a| 432.#300 r10 Kill Spill r10 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 432.#301 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 433.#302 BB18 PredBB16 | | | |V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 445.#303 V42 Use Keep r10 | | | |V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 445.#304 V39 Use Keep r8 | | | |V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 451.#305 V42 Use * Keep r10 | | | |V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 452.#306 I116 Def BSFIT(A) rcx | |I116a| |V3 a|V2 a|V0 a|V1 a|V39 a| | | |V5 a|V6 a|V73 a|V4 a| 453.#307 V39 Use * Keep r8 | |I116a| |V3 a|V2 a|V0 a|V1 a|V39 a| | | |V5 a|V6 a|V73 a|V4 a| 453.#308 I116 Use * Keep rcx | |I116a| |V3 a|V2 a|V0 a|V1 a|V39 a| | | |V5 a|V6 a|V73 a|V4 a| 454.#309 I117 Def ORDER(A) rax |I117a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 455.#310 I117 Use * Keep rax |I117a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 456.#311 V38 Def ORDER(A) rax |V38 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 459.#312 V38 Use * Keep rax |V38 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 460.#313 V8 Def ORDER(A) rax |V8 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 465.#314 V8 Use Keep rax |V8 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 466.#315 I118 Def ORDER(A) r8 |V8 a| | |V3 a|V2 a|V0 a|V1 a|I118a| | | |V5 a|V6 a|V73 a|V4 a| 469.#316 I118 Use * Keep r8 |V8 a| | |V3 a|V2 a|V0 a|V1 a|I118a| | | |V5 a|V6 a|V73 a|V4 a| 470.#317 I119 Def ORDER(A) r8 |V8 a| | |V3 a|V2 a|V0 a|V1 a|I119a| | | |V5 a|V6 a|V73 a|V4 a| 471.#318 I119 Use * Keep r8 |V8 a| | |V3 a|V2 a|V0 a|V1 a|I119a| | | |V5 a|V6 a|V73 a|V4 a| 472.#319 V9 Def ORDER(A) r8 |V8 a| | |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 479.#320 V5 Use Keep r12 |V8 a| | |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 483.#321 BB19 PredBB18 |V8 a| | |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 489.#322 V0 Use Keep rsi |V8 a| | |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 490.#323 I120 Def RELPR(A) rcx |V8 a|I120a| |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 491.#324 I120 Use * Keep rcx |V8 a|I120a| |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 492.#325 V24 Def COVRS(A) rcx |V8 a|V24 a| |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 497.#326 V24 Use Keep rcx |V8 a|V24 a| |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 498.#327 I121 Def BSFIT(A) rdx |V8 a|V24 a|I121a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 499.#328 I121 Use * Keep rdx |V8 a|V24 a|I121a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 500.#329 I122 Def BSFIT(A) rdx |V8 a|V24 a|I122a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 503.#330 I122 Use * Keep rdx |V8 a|V24 a|I122a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 504.#331 I123 Def BSFIT(A) rdx |V8 a|V24 a|I123a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 505.#332 I123 Use * Keep rdx |V8 a|V24 a|I123a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 506.#333 V69 Def COVRS(A) rdx |V8 a|V24 a|V69 a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 511.#334 V69 Use Keep rdx |V8 a|V24 a|V69 a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 515.#335 BB20 PredBB19 |V8 a|V24 i|V69 a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 519.#336 V69 Use * Keep rdx |V8 a|V24 i|V69 a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 520.#337 V25 Def UNASG(A) rdx |V8 a|V24 i|V25 a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 521.#338 BB21 PredBB19 |V8 a|V24 a|V25 i|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 525.#339 rcx Fixd Keep rcx |V8 a|V24 a|V25 i|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 525.#340 V24 Use * Keep rcx |V8 a|V24 a|V25 i|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 526.#341 rcx Fixd Keep rcx |V8 a| |V25 i|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 526.#342 I124 Def Alloc rcx |V8 a|I124a|V25 i|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 528.#343 C125 Def Alloc rdx |V8 a|I124a|C125a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 529.#344 rdx Fixd Keep rdx |V8 a|I124a|C125a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 529.#345 C125 Use * Keep rdx |V8 a|I124a|C125a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 530.#346 rdx Fixd Keep rdx |V8 a|I124a| |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 530.#347 I126 Def Alloc rdx |V8 a|I124a|I126a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 531.#348 rcx Fixd Keep rcx |V8 a|I124a|I126a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 531.#349 I124 Use * Keep rcx |V8 a|I124a|I126a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 531.#350 rdx Fixd Keep rdx |V8 a|I124a|I126a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 531.#351 I126 Use * Keep rdx |V8 a|I124a|I126a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| Restr rdx |V8 a| |V25 i|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 532.#352 rax Kill Spill rax | | |V25 i|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| Keep rax | | |V25 i|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 532.#353 rcx Kill Keep rcx | | |V25 i|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 532.#354 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 532.#355 r8 Kill Spill r8 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 532.#356 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 532.#357 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 532.#358 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 532.#359 rax Fixd Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 532.#360 I127 Def Alloc rax |I127a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 533.#361 I127 Use * Keep rax |I127a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 534.#362 V25 Def THISA(A) rdx | | |V25 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 535.#363 BB22 PredBB20 |V8 a| |V25 a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 539.#364 rcx Fixd Keep rcx |V8 a| |V25 a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 539.#365 V25 Use * Copy rcx |V8 a|V25 a|V25 a|V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 540.#366 rcx Fixd Keep rcx |V8 a| | |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 540.#367 I128 Def Alloc rcx |V8 a|I128a| |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 541.#368 rcx Fixd Keep rcx |V8 a|I128a| |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 541.#369 I128 Use * Keep rcx |V8 a|I128a| |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 542.#370 rax Kill Spill rax | | | |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| Keep rax | | | |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 542.#371 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 542.#372 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 542.#373 r8 Kill Spill r8 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 542.#374 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 542.#375 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 542.#376 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 542.#377 rax Fixd Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 542.#378 I129 Def Alloc rax |I129a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 543.#379 I129 Use * Keep rax |I129a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 544.#380 V12 Def ORDER(A) rax |V12 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 545.#381 BB23 PredBB22 |V12 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 553.#382 V4 Use Keep r15 |V12 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 554.#383 I130 Def ORDER(A) r9 |V12 a| | |V3 a|V2 a|V0 a|V1 a| |I130a| | |V5 a|V6 a|V73 a|V4 a| 555.#384 I130 Use * Keep r9 |V12 a| | |V3 a|V2 a|V0 a|V1 a| |I130a| | |V5 a|V6 a|V73 a|V4 a| 556.#385 V76 Def ORDER(A) r9 |V12 a| | |V3 a|V2 a|V0 a|V1 a| |V76 a| | |V5 a|V6 a|V73 a|V4 a| 561.#386 V76 Use Keep r9 |V12 a| | |V3 a|V2 a|V0 a|V1 a| |V76 a| | |V5 a|V6 a|V73 a|V4 a| 561.#387 V9 Use ReLod NA |V12 a| | |V3 a|V2 a|V0 a|V1 a| |V76 a| | |V5 a|V6 a|V73 a|V4 a| ORDER(A) r10 |V12 a| | |V3 a|V2 a|V0 a|V1 a| |V76 a|V9 a| |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 565.#388 BB24 PredBB23 |V12 a| | |V3 a|V2 a|V0 a|V1 a| |V76 a|V9 a| |V5 a|V6 a|V73 a|V4 a| 573.#389 V9 Use * Keep r10 |V12 a| | |V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i| |V5 a|V6 a|V73 a|V4 a| 574.#390 I131 Def BSFIT(A) rdx |V12 a| |I131a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i| |V5 a|V6 a|V73 a|V4 a| 577.#391 I131 Use * Keep rdx |V12 a| |I131a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i| |V5 a|V6 a|V73 a|V4 a| 578.#392 I132 Def BSFIT(A) rdx |V12 a| |I132a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i| |V5 a|V6 a|V73 a|V4 a| 579.#393 I132 Use * Keep rdx |V12 a| |I132a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i| |V5 a|V6 a|V73 a|V4 a| 580.#394 V70 Def COVRS(A) rdx |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i| |V5 a|V6 a|V73 a|V4 a| 583.#395 V4 Use Keep r15 |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i| |V5 a|V6 a|V73 a|V4 a| 583.#396 V70 Use Keep rdx |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i| |V5 a|V6 a|V73 a|V4 a| 584.#397 I133 Def BSFIT(A) r11 |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i|I133a|V5 a|V6 a|V73 a|V4 a| 585.#398 I133 Use * Keep r11 |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i|I133a|V5 a|V6 a|V73 a|V4 a| 586.#399 V65 Def BSFIT(A) r11 |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i|V65 a|V5 a|V6 a|V73 a|V4 a| 595.#400 V65 Use Keep r11 |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i|V65 a|V5 a|V6 a|V73 a|V4 a| 595.#401 V6 Use Keep r13 |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i|V65 a|V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 599.#402 BB25 PredBB24 |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i|V65 a|V5 a|V6 a|V73 a|V4 a| 609.#403 V4 Use Keep r15 |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i|V65 a|V5 a|V6 a|V73 a|V4 a| 609.#404 V70 Use * Keep rdx |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i|V65 a|V5 a|V6 a|V73 a|V4 a| 610.#405 I134 Def Alloc rdx |V12 a| |I134a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i|V65 a|V5 a|V6 a|V73 a|V4 a| 611.#406 rdx Fixd Keep rdx |V12 a| |I134a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i|V65 a|V5 a|V6 a|V73 a|V4 a| 611.#407 I134 Use * Keep rdx |V12 a| |I134a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i|V65 a|V5 a|V6 a|V73 a|V4 a| 612.#408 rdx Fixd Keep rdx |V12 a| | |V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i|V65 a|V5 a|V6 a|V73 a|V4 a| 612.#409 I135 Def Alloc rdx |V12 a| |I135a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i|V65 a|V5 a|V6 a|V73 a|V4 a| 615.#410 rcx Fixd Keep rcx |V12 a| |I135a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i|V65 a|V5 a|V6 a|V73 a|V4 a| 615.#411 V12 Use Copy rcx |V12 a|V12 a|I135a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i|V65 a|V5 a|V6 a|V73 a|V4 a| 616.#412 rcx Fixd Keep rcx |V12 a|V12 a|I135a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i|V65 a|V5 a|V6 a|V73 a|V4 a| 616.#413 I136 Def Alloc rcx |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i|V65 a|V5 a|V6 a|V73 a|V4 a| 619.#414 r8 Fixd Keep r8 |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a| |V76 a|V9 i|V65 a|V5 a|V6 a|V73 a|V4 a| 619.#415 V1 Use Copy r8 |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a|V1 a|V76 a|V9 i|V65 a|V5 a|V6 a|V73 a|V4 a| 620.#416 r8 Fixd Keep r8 |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a|V1 a|V76 a|V9 i|V65 a|V5 a|V6 a|V73 a|V4 a| 620.#417 I137 Def Alloc r8 |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a|I137a|V76 a|V9 i|V65 a|V5 a|V6 a|V73 a|V4 a| 623.#418 V12 Use Keep rax |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a|I137a|V76 a|V9 i|V65 a|V5 a|V6 a|V73 a|V4 a| 624.#419 I138 Def FREE (A) r10 |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a|I137a|V76 a|I138a|V65 a|V5 a|V6 a|V73 a|V4 a| 627.#420 I138 Use * Keep r10 |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a|I137a|V76 a|I138a|V65 a|V5 a|V6 a|V73 a|V4 a| Restr r10 |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a|I137a|V76 a|V9 i|V65 a|V5 a|V6 a|V73 a|V4 a| 628.#421 I139 Def FREE (A) r10 |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a|I137a|V76 a|I139a|V65 a|V5 a|V6 a|V73 a|V4 a| 633.#422 rdx Fixd Keep rdx |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a|I137a|V76 a|I139a|V65 a|V5 a|V6 a|V73 a|V4 a| 633.#423 I135 Use * Keep rdx |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a|I137a|V76 a|I139a|V65 a|V5 a|V6 a|V73 a|V4 a| 633.#424 rcx Fixd Keep rcx |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a|I137a|V76 a|I139a|V65 a|V5 a|V6 a|V73 a|V4 a| 633.#425 I136 Use * Keep rcx |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a|I137a|V76 a|I139a|V65 a|V5 a|V6 a|V73 a|V4 a| 633.#426 r8 Fixd Keep r8 |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a|I137a|V76 a|I139a|V65 a|V5 a|V6 a|V73 a|V4 a| 633.#427 I137 Use * Keep r8 |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a|I137a|V76 a|I139a|V65 a|V5 a|V6 a|V73 a|V4 a| 633.#428 I139 Use * Keep r10 |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a|I137a|V76 a|I139a|V65 a|V5 a|V6 a|V73 a|V4 a| 634.#429 rax Kill Spill rax | | | |V3 a|V2 a|V0 a|V1 a| |V76 a| |V65 a|V5 a|V6 a|V73 a|V4 a| Keep rax | | | |V3 a|V2 a|V0 a|V1 a| |V76 a| |V65 a|V5 a|V6 a|V73 a|V4 a| 634.#430 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| |V76 a| |V65 a|V5 a|V6 a|V73 a|V4 a| 634.#431 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| |V76 a| |V65 a|V5 a|V6 a|V73 a|V4 a| 634.#432 r8 Kill Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| |V76 a| |V65 a|V5 a|V6 a|V73 a|V4 a| 634.#433 r9 Kill Spill r9 | | | |V3 a|V2 a|V0 a|V1 a| | | |V65 a|V5 a|V6 a|V73 a|V4 a| Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | | |V65 a|V5 a|V6 a|V73 a|V4 a| 634.#434 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | |V65 a|V5 a|V6 a|V73 a|V4 a| 634.#435 r11 Kill Spill r11 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 634.#436 rax Fixd Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 634.#437 I140 Def Alloc rax |I140a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 637.#438 I140 Use * Keep rax |I140a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 641.#439 BB26 PredBB24 |V12 a| | |V3 a|V2 a|V0 a|V1 a| |V76 a| |V65 a|V5 a|V6 a|V73 a|V4 a| 649.#440 V65 Use * Keep r11 |V12 a| | |V3 a|V2 a|V0 a|V1 a| |V76 a| |V65 i|V5 a|V6 a|V73 a|V4 a| 650.#441 I141 Def RELPR(A) r10 |V12 a| | |V3 a|V2 a|V0 a|V1 a| |V76 a|I141a|V65 i|V5 a|V6 a|V73 a|V4 a| 651.#442 I141 Use * Keep r10 |V12 a| | |V3 a|V2 a|V0 a|V1 a| |V76 a|I141a|V65 i|V5 a|V6 a|V73 a|V4 a| 652.#443 V9 Def ORDER(A) r8 |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 a| |V65 i|V5 a|V6 a|V73 a|V4 a| 659.#444 V7 Use * ReLod NA |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 a| |V65 i|V5 a|V6 a|V73 a|V4 a| BSFIT(A) r11 |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 a| |V7 i|V5 a|V6 a|V73 a|V4 a| 660.#445 I142 Def COVRS(A) r11 |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 a| |I142a|V5 a|V6 a|V73 a|V4 a| 661.#446 I142 Use * Keep r11 |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 a| |I142a|V5 a|V6 a|V73 a|V4 a| Restr r11 |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 a| |V7 i|V5 a|V6 a|V73 a|V4 a| 662.#447 V7 Def THISA(A) r11 |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 a| |V7 a|V5 a|V6 a|V73 a|V4 a| 669.#448 V76 Use * Keep r9 |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 i| |V7 a|V5 a|V6 a|V73 a|V4 a| 669.#449 V7 Use Keep r11 |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 i| |V7 a|V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 673.#450 BB27 PredBB26 |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 i| |V7 a|V5 a|V6 a|V73 a|V4 a| 675.#451 V7 ExpU Keep NA |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 i| |V7 a|V5 a|V6 a|V73 a|V4 a| 675.#452 V4 ExpU Keep NA |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 i| |V7 a|V5 a|V6 a|V73 a|V4 a| 675.#453 V9 ExpU Keep NA |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 i| |V7 a|V5 a|V6 a|V73 a|V4 a| 675.#454 V6 ExpU Keep NA |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 i| |V7 a|V5 a|V6 a|V73 a|V4 a| 675.#455 V73 ExpU Keep NA |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 i| |V7 a|V5 a|V6 a|V73 a|V4 a| 675.#456 V5 ExpU Keep NA |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 i| |V7 a|V5 a|V6 a|V73 a|V4 a| 675.#457 V12 ExpU Keep NA |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 i| |V7 a|V5 a|V6 a|V73 a|V4 a| 675.#458 V8 ExpU Keep NA |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 i| |V7 a|V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 675.#459 BB28 PredBB24 | | | |V3 a|V2 a|V0 a|V1 a|V9 i|V76 i| |V65 a|V5 i|V6 i|V73 i|V4 i| 683.#460 V3 Use Keep rbx | | | |V3 a|V2 a|V0 a|V1 a|V9 i|V76 i| |V65 a|V5 i|V6 i|V73 i|V4 i| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 687.#461 BB29 PredBB28 | | | |V3 i|V2 a|V0 a|V1 i|V9 i|V76 i| |V65 a|V5 i|V6 i|V73 i|V4 i| 693.#462 V65 Use * Keep r11 | | | |V3 i|V2 a|V0 a|V1 i|V9 i|V76 i| |V65 a|V5 i|V6 i|V73 i|V4 i| 694.#463 I143 Def Alloc rcx | |I143a| |V3 i|V2 a|V0 a|V1 i|V9 i|V76 i| | |V5 i|V6 i|V73 i|V4 i| 697.#464 rcx Fixd Keep rcx | |I143a| |V3 i|V2 a|V0 a|V1 i|V9 i|V76 i| | |V5 i|V6 i|V73 i|V4 i| 697.#465 I143 Use * Keep rcx | |I143a| |V3 i|V2 a|V0 a|V1 i|V9 i|V76 i| | |V5 i|V6 i|V73 i|V4 i| 697.#466 rdx Fixd Keep rdx | |I143a| |V3 i|V2 a|V0 a|V1 i|V9 i|V76 i| | |V5 i|V6 i|V73 i|V4 i| 697.#467 V2 Use * Copy rdx | |I143a|V2 a|V3 i|V2 a|V0 a|V1 i|V9 i|V76 i| | |V5 i|V6 i|V73 i|V4 i| 698.#468 rax Kill Keep rax | | |V2 i|V3 i|V2 i|V0 a|V1 i|V9 i|V76 i| | |V5 i|V6 i|V73 i|V4 i| 698.#469 rcx Kill Keep rcx | | |V2 i|V3 i|V2 i|V0 a|V1 i|V9 i|V76 i| | |V5 i|V6 i|V73 i|V4 i| 698.#470 rdx Kill Keep rdx | | | |V3 i|V2 i|V0 a|V1 i|V9 i|V76 i| | |V5 i|V6 i|V73 i|V4 i| 698.#471 r8 Kill Keep r8 | | | |V3 i|V2 i|V0 a|V1 i| |V76 i| | |V5 i|V6 i|V73 i|V4 i| 698.#472 r9 Kill Keep r9 | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V4 i| 698.#473 r10 Kill Keep r10 | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V4 i| 698.#474 r11 Kill Keep r11 | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V4 i| 698.#475 mm0 Kill Keep mm0 | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V4 i| 698.#476 mm1 Kill Keep mm1 | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V4 i| 698.#477 mm2 Kill Keep mm2 | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V4 i| 698.#478 mm3 Kill Keep mm3 | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V4 i| 698.#479 mm4 Kill Keep mm4 | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V4 i| 698.#480 mm5 Kill Keep mm5 | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V4 i| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 699.#481 BB30 PredBB28 | | | |V3 a|V2 i|V0 a|V1 a| | | | |V5 i|V6 i|V73 i|V4 i| 707.#482 V3 Use * Keep rbx | | | |V3 i|V2 i|V0 a|V1 a| | | | |V5 i|V6 i|V73 i|V4 i| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 711.#483 BB31 PredBB30 | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V4 i| 714.#484 C144 Def Alloc rax |C144a| | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V4 i| 715.#485 rax Fixd Keep rax |C144a| | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V4 i| 715.#486 C144 Use * Keep rax |C144a| | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V4 i| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 717.#487 BB32 PredBB18 |V8 a| | |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 725.#488 V4 Use Keep r15 |V8 a| | |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 726.#489 I145 Def RELPR(A) r9 |V8 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|I145a| | |V5 a|V6 a|V73 a|V4 a| 727.#490 I145 Use * Keep r9 |V8 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|I145a| | |V5 a|V6 a|V73 a|V4 a| 728.#491 V76 Def ORDER(A) r9 |V8 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 733.#492 V76 Use Keep r9 |V8 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 733.#493 V9 Use Keep r8 |V8 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 737.#494 BB33 PredBB32 |V8 a| | |V3 a|V2 a|V0 a|V1 a|V9 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 745.#495 V9 Use * Keep r8 |V8 a| | |V3 a|V2 a|V0 a|V1 a|V9 i|V76 a| | |V5 a|V6 a|V73 a|V4 a| 746.#496 I146 Def BSFIT(A) rcx |V8 a|I146a| |V3 a|V2 a|V0 a|V1 a|V9 i|V76 a| | |V5 a|V6 a|V73 a|V4 a| 749.#497 I146 Use * Keep rcx |V8 a|I146a| |V3 a|V2 a|V0 a|V1 a|V9 i|V76 a| | |V5 a|V6 a|V73 a|V4 a| 750.#498 I147 Def BSFIT(A) rcx |V8 a|I147a| |V3 a|V2 a|V0 a|V1 a|V9 i|V76 a| | |V5 a|V6 a|V73 a|V4 a| 751.#499 I147 Use * Keep rcx |V8 a|I147a| |V3 a|V2 a|V0 a|V1 a|V9 i|V76 a| | |V5 a|V6 a|V73 a|V4 a| 752.#500 V71 Def COVRS(A) rcx |V8 a|V71 a| |V3 a|V2 a|V0 a|V1 a|V9 i|V76 a| | |V5 a|V6 a|V73 a|V4 a| 755.#501 V4 Use Keep r15 |V8 a|V71 a| |V3 a|V2 a|V0 a|V1 a|V9 i|V76 a| | |V5 a|V6 a|V73 a|V4 a| 755.#502 V71 Use Keep rcx |V8 a|V71 a| |V3 a|V2 a|V0 a|V1 a|V9 i|V76 a| | |V5 a|V6 a|V73 a|V4 a| 756.#503 I148 Def ORDER(A) r8 |V8 a|V71 a| |V3 a|V2 a|V0 a|V1 a|I148a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 757.#504 I148 Use * Keep r8 |V8 a|V71 a| |V3 a|V2 a|V0 a|V1 a|I148a|V76 a| | |V5 a|V6 a|V73 a|V4 a| Restr r8 |V8 a|V71 a| |V3 a|V2 a|V0 a|V1 a|V9 i|V76 a| | |V5 a|V6 a|V73 a|V4 a| 758.#505 V66 Def ORDER(A) r8 |V8 a|V71 a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 767.#506 V66 Use Keep r8 |V8 a|V71 a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 767.#507 V6 Use Keep r13 |V8 a|V71 a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 771.#508 BB34 PredBB33 |V8 a|V71 a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 781.#509 V4 Use Keep r15 |V8 a|V71 a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 781.#510 V71 Use * Keep rcx |V8 a|V71 a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 782.#511 I149 Def ORDER(A) r10 |V8 a| | |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|I149a| |V5 a|V6 a|V73 a|V4 a| 783.#512 I149 Use * Keep r10 |V8 a| | |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|I149a| |V5 a|V6 a|V73 a|V4 a| 784.#513 V17 Def ORDER(A) r10 |V8 a| | |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a| |V5 a|V6 a|V73 a|V4 a| 789.#514 V0 Use Keep rsi |V8 a| | |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a| |V5 a|V6 a|V73 a|V4 a| 790.#515 I150 Def RELPR(A) rcx |V8 a|I150a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a| |V5 a|V6 a|V73 a|V4 a| 791.#516 I150 Use * Keep rcx |V8 a|I150a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a| |V5 a|V6 a|V73 a|V4 a| 792.#517 V16 Def COVRS(A) rcx |V8 a|V16 a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a| |V5 a|V6 a|V73 a|V4 a| 797.#518 V16 Use Keep rcx |V8 a|V16 a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a| |V5 a|V6 a|V73 a|V4 a| 798.#519 I151 Def BSFIT(A) rdx |V8 a|V16 a|I151a|V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a| |V5 a|V6 a|V73 a|V4 a| 799.#520 I151 Use * Keep rdx |V8 a|V16 a|I151a|V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a| |V5 a|V6 a|V73 a|V4 a| 800.#521 I152 Def BSFIT(A) rdx |V8 a|V16 a|I152a|V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a| |V5 a|V6 a|V73 a|V4 a| 803.#522 I152 Use * Keep rdx |V8 a|V16 a|I152a|V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a| |V5 a|V6 a|V73 a|V4 a| 804.#523 I153 Def COREL(A) r11 |V8 a|V16 a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|I153a|V5 a|V6 a|V73 a|V4 a| 805.#524 I153 Use * Keep r11 |V8 a|V16 a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|I153a|V5 a|V6 a|V73 a|V4 a| 806.#525 V67 Def COVRS(A) r11 |V8 a|V16 a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V67 a|V5 a|V6 a|V73 a|V4 a| 811.#526 V67 Use Keep r11 |V8 a|V16 a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V67 a|V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 815.#527 BB35 PredBB34 |V8 a|V16 i| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V67 a|V5 a|V6 a|V73 a|V4 a| 819.#528 V67 Use * Keep r11 |V8 a|V16 i| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V67 a|V5 a|V6 a|V73 a|V4 a| 820.#529 V19 Def OWNPR(A) r11 |V8 a|V16 i| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 821.#530 BB36 PredBB34 |V8 a|V16 a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| 825.#531 rcx Fixd Keep rcx |V8 a|V16 a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| 825.#532 V16 Use * Keep rcx |V8 a|V16 a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| 826.#533 rcx Fixd Keep rcx |V8 a| | |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| 826.#534 I154 Def Alloc rcx |V8 a|I154a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| 828.#535 C155 Def Alloc rdx |V8 a|I154a|C155a|V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| 829.#536 rdx Fixd Keep rdx |V8 a|I154a|C155a|V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| 829.#537 C155 Use * Keep rdx |V8 a|I154a|C155a|V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| 830.#538 rdx Fixd Keep rdx |V8 a|I154a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| 830.#539 I156 Def Alloc rdx |V8 a|I154a|I156a|V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| 831.#540 rcx Fixd Keep rcx |V8 a|I154a|I156a|V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| 831.#541 I154 Use * Keep rcx |V8 a|I154a|I156a|V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| 831.#542 rdx Fixd Keep rdx |V8 a|I154a|I156a|V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| 831.#543 I156 Use * Keep rdx |V8 a|I154a|I156a|V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| 832.#544 rax Kill Spill rax | | | |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| Keep rax | | | |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| 832.#545 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| 832.#546 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| 832.#547 r8 Kill Spill r8 | | | |V3 a|V2 a|V0 a|V1 a| |V76 a|V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| |V76 a|V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| 832.#548 r9 Kill Spill r9 | | | |V3 a|V2 a|V0 a|V1 a| | |V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | |V17 a|V19 i|V5 a|V6 a|V73 a|V4 a| 832.#549 r10 Kill Spill r10 | | | |V3 a|V2 a|V0 a|V1 a| | | |V19 i|V5 a|V6 a|V73 a|V4 a| Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | |V19 i|V5 a|V6 a|V73 a|V4 a| 832.#550 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 832.#551 rax Fixd Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 832.#552 I157 Def Alloc rax |I157a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 833.#553 I157 Use * Keep rax |I157a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 834.#554 V19 Def THISA(A) r11 | | | |V3 a|V2 a|V0 a|V1 a| | | |V19 a|V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 835.#555 BB37 PredBB35 |V8 a| | |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| 839.#556 rcx Fixd Keep rcx |V8 a| | |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| 839.#557 V5 Use Copy rcx |V8 a|V5 a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| 840.#558 rcx Fixd Keep rcx |V8 a|V5 a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| 840.#559 I158 Def Alloc rcx |V8 a|I158a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| 843.#560 r11 Fixd Keep r11 |V8 a|I158a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| 843.#561 V19 Use Keep r11 |V8 a|I158a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| 844.#562 r11 Fixd Keep r11 |V8 a|I158a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| 844.#563 I159 Def PtArg r11 |V8 a|I158a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| 847.#564 rdx Fixd Keep rdx |V8 a|I158a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| 847.#565 V17 Use * Copy rdx |V8 a|I158a|V17 a|V3 a|V2 a|V0 a|V1 a|V66 a|V76 a|V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| 848.#566 rdx Fixd Keep rdx |V8 a|I158a| |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a| |V19 a|V5 a|V6 a|V73 a|V4 a| 848.#567 I160 Def Alloc rdx |V8 a|I158a|I160a|V3 a|V2 a|V0 a|V1 a|V66 a|V76 a| |V19 a|V5 a|V6 a|V73 a|V4 a| 851.#568 r8 Fixd Keep r8 |V8 a|I158a|I160a|V3 a|V2 a|V0 a|V1 a|V66 a|V76 a| |V19 a|V5 a|V6 a|V73 a|V4 a| 851.#569 V1 Use Spill r8 |V8 a|I158a|I160a|V3 a|V2 a|V0 a|V1 i| |V76 a| |V19 a|V5 a|V6 a|V73 a|V4 a| Copy r8 |V8 a|I158a|I160a|V3 a|V2 a|V0 a|V1 a|V1 a|V76 a| |V19 a|V5 a|V6 a|V73 a|V4 a| 852.#570 r8 Fixd Keep r8 |V8 a|I158a|I160a|V3 a|V2 a|V0 a|V1 a|V1 a|V76 a| |V19 a|V5 a|V6 a|V73 a|V4 a| 852.#571 I161 Def Alloc r8 |V8 a|I158a|I160a|V3 a|V2 a|V0 a|V1 a|I161a|V76 a| |V19 a|V5 a|V6 a|V73 a|V4 a| 857.#572 rcx Fixd Keep rcx |V8 a|I158a|I160a|V3 a|V2 a|V0 a|V1 a|I161a|V76 a| |V19 a|V5 a|V6 a|V73 a|V4 a| 857.#573 I158 Use * Keep rcx |V8 a|I158a|I160a|V3 a|V2 a|V0 a|V1 a|I161a|V76 a| |V19 a|V5 a|V6 a|V73 a|V4 a| 857.#574 r11 Fixd Keep r11 |V8 a|I158a|I160a|V3 a|V2 a|V0 a|V1 a|I161a|V76 a| |V19 a|V5 a|V6 a|V73 a|V4 a| 857.#575 I159 Use * PtArg r11 |V8 a|I158a|I160a|V3 a|V2 a|V0 a|V1 a|I161a|V76 a| |V19 a|V5 a|V6 a|V73 a|V4 a| 857.#576 rdx Fixd Keep rdx |V8 a|I158a|I160a|V3 a|V2 a|V0 a|V1 a|I161a|V76 a| |V19 a|V5 a|V6 a|V73 a|V4 a| 857.#577 I160 Use * Keep rdx |V8 a|I158a|I160a|V3 a|V2 a|V0 a|V1 a|I161a|V76 a| |V19 a|V5 a|V6 a|V73 a|V4 a| 857.#578 r8 Fixd Keep r8 |V8 a|I158a|I160a|V3 a|V2 a|V0 a|V1 a|I161a|V76 a| |V19 a|V5 a|V6 a|V73 a|V4 a| 857.#579 I161 Use * Keep r8 |V8 a|I158a|I160a|V3 a|V2 a|V0 a|V1 a|I161a|V76 a| |V19 a|V5 a|V6 a|V73 a|V4 a| 857.#580 V19 Use * Keep r11 |V8 a|I158a|I160a|V3 a|V2 a|V0 a|V1 a|I161a|V76 a| |V19 a|V5 a|V6 a|V73 a|V4 a| 858.#581 rax Kill Spill rax | | | |V3 a|V2 a|V0 a|V1 a| |V76 a| |Busy |V5 a|V6 a|V73 a|V4 a| Keep rax | | | |V3 a|V2 a|V0 a|V1 a| |V76 a| |Busy |V5 a|V6 a|V73 a|V4 a| 858.#582 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| |V76 a| |Busy |V5 a|V6 a|V73 a|V4 a| 858.#583 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| |V76 a| |Busy |V5 a|V6 a|V73 a|V4 a| 858.#584 r8 Kill Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| |V76 a| |Busy |V5 a|V6 a|V73 a|V4 a| 858.#585 r9 Kill Spill r9 | | | |V3 a|V2 a|V0 a|V1 a| | | |Busy |V5 a|V6 a|V73 a|V4 a| Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | | |Busy |V5 a|V6 a|V73 a|V4 a| 858.#586 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | |Busy |V5 a|V6 a|V73 a|V4 a| 858.#587 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 858.#588 rax Fixd Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 858.#589 I162 Def Alloc rax |I162a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 861.#590 I162 Use * Keep rax |I162a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 865.#591 BB38 PredBB37 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 i|V6 i|V73 i|V4 i| 873.#592 V3 Use Keep rbx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 i|V6 i|V73 i|V4 i| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 877.#593 BB39 PredBB38 | | | |V3 i|V2 a|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V4 i| 883.#594 V66 Use * ReLod NA | | | |V3 i|V2 a|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V4 i| BSFIT(A) r15 | | | |V3 i|V2 a|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V66 i| 884.#595 I163 Def Alloc rcx | |I163a| |V3 i|V2 a|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V66 i| 887.#596 rcx Fixd Keep rcx | |I163a| |V3 i|V2 a|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V66 i| 887.#597 I163 Use * Keep rcx | |I163a| |V3 i|V2 a|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V66 i| 887.#598 rdx Fixd Keep rdx | |I163a| |V3 i|V2 a|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V66 i| 887.#599 V2 Use * Copy rdx | |I163a|V2 a|V3 i|V2 a|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V66 i| 888.#600 rax Kill Keep rax | | |V2 i|V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V66 i| 888.#601 rcx Kill Keep rcx | | |V2 i|V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V66 i| 888.#602 rdx Kill Keep rdx | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V66 i| 888.#603 r8 Kill Keep r8 | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V66 i| 888.#604 r9 Kill Keep r9 | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V66 i| 888.#605 r10 Kill Keep r10 | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V66 i| 888.#606 r11 Kill Keep r11 | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V66 i| 888.#607 mm0 Kill Keep mm0 | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V66 i| 888.#608 mm1 Kill Keep mm1 | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V66 i| 888.#609 mm2 Kill Keep mm2 | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V66 i| 888.#610 mm3 Kill Keep mm3 | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V66 i| 888.#611 mm4 Kill Keep mm4 | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V66 i| 888.#612 mm5 Kill Keep mm5 | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V66 i| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 889.#613 BB40 PredBB38 | | | |V3 a|V2 i|V0 a|V1 a| | | | |V5 i|V6 i|V73 i|V66 i| 897.#614 V3 Use * Keep rbx | | | |V3 i|V2 i|V0 a|V1 a| | | | |V5 i|V6 i|V73 i|V66 i| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 901.#615 BB41 PredBB40 | | | |V3 i|V2 i|V0 a|V1 i| | | | |V5 i|V6 i|V73 i|V66 i| Restr r15 | | | |V3 i|V2 i|V0 a|V1 i| |V76 a| | |V5 i|V6 i|V73 i|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 903.#616 BB42 PredBB33 |V8 a| | |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 911.#617 V66 Use * Keep r8 |V8 a| | |V3 a|V2 a|V0 a|V1 a|V66 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 912.#618 I164 Def COREL(A) r8 |V8 a| | |V3 a|V2 a|V0 a|V1 a|I164a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 913.#619 I164 Use * Keep r8 |V8 a| | |V3 a|V2 a|V0 a|V1 a|I164a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 914.#620 V9 Def BSFIT(A) rcx |V8 a|V9 a| |V3 a|V2 a|V0 a|V1 a| |V76 a| | |V5 a|V6 a|V73 a|V4 a| 921.#621 V7 Use * ReLod NA |V8 a|V9 a| |V3 a|V2 a|V0 a|V1 a| |V76 a| | |V5 a|V6 a|V73 a|V4 a| ORDER(A) r8 |V8 a|V9 a| |V3 a|V2 a|V0 a|V1 a|V7 i|V76 a| | |V5 a|V6 a|V73 a|V4 a| 922.#622 I165 Def RELPR(A) r8 |V8 a|V9 a| |V3 a|V2 a|V0 a|V1 a|I165a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 923.#623 I165 Use * Keep r8 |V8 a|V9 a| |V3 a|V2 a|V0 a|V1 a|I165a|V76 a| | |V5 a|V6 a|V73 a|V4 a| Restr r8 |V8 a|V9 a| |V3 a|V2 a|V0 a|V1 a|V7 i|V76 a| | |V5 a|V6 a|V73 a|V4 a| 924.#624 V7 Def THISA(A) r8 |V8 a|V9 a| |V3 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 931.#625 V76 Use * Keep r9 |V8 a|V9 a| |V3 a|V2 a|V0 a|V1 a|V7 a|V76 i| | |V5 a|V6 a|V73 a|V4 a| 931.#626 V7 Use Keep r8 |V8 a|V9 a| |V3 a|V2 a|V0 a|V1 a|V7 a|V76 i| | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 935.#627 BB43 PredBB42 |V8 a|V9 a| |V3 a|V2 a|V0 a|V1 a|V7 a|V76 i| | |V5 a|V6 a|V73 a|V4 a| 937.#628 V9 ExpU Keep NA |V8 a|V9 a| |V3 a|V2 a|V0 a|V1 a|V7 a|V76 i| | |V5 a|V6 a|V73 a|V4 a| 937.#629 V3 ExpU Keep NA |V8 a|V9 a| |V3 a|V2 a|V0 a|V1 a|V7 a|V76 i| | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 937.#630 BB44 PredBB23 |V8 a| | | |V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 949.#631 V0 Use Keep rsi |V8 a| | | |V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 953.#632 BB45 PredBB44 |V8 a| | | |V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 961.#633 V0 Use Keep rsi |V8 a| | | |V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 962.#634 I166 Def BSFIT(A) rcx |V8 a|I166a| | |V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 963.#635 I166 Use * Keep rcx |V8 a|I166a| | |V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 964.#636 V74 Def COVRS(A) rcx |V8 a|V74 a| | |V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 967.#637 V74 Use Keep rcx |V8 a|V74 a| | |V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 968.#638 V10 Def COVRS(A) rbx |V8 a|V74 a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 973.#639 V74 Use * Keep rcx |V8 a|V74 a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 974.#640 V62 Def COVRS(A) rcx |V8 a|V62 a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 979.#641 V62 Use Keep rcx |V8 a|V62 a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 979.#642 V76 Use Keep r9 |V8 a|V62 a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 985.#643 V62 Use * Keep rcx |V8 a|V62 a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 986.#644 I167 Def BSFIT(A) rcx |V8 a|I167a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 989.#645 I167 Use * Keep rcx |V8 a|I167a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 990.#646 I168 Def BSFIT(A) rcx |V8 a|I168a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 993.#647 V4 Use Keep r15 |V8 a|I168a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 993.#648 I168 Use * Keep rcx |V8 a|I168a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 994.#649 I169 Def BSFIT(A) rcx |V8 a|I169a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 995.#650 I169 Use * Keep rcx |V8 a|I169a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 996.#651 I170 Def BSFIT(A) rcx |V8 a|I170a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 999.#652 I170 Use * Keep rcx |V8 a|I170a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 1000.#653 I171 Def COVRS(A) rcx |V8 a|I171a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 1003.#654 I171 Use * Keep rcx |V8 a|I171a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 1004.#655 I172 Def BSFIT(A) rcx |V8 a|I172a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 1005.#656 I172 Use * Keep rcx |V8 a|I172a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 1006.#657 V49 Def COVRS(A) rcx |V8 a|V49 a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 a| 1011.#658 V73 Use * Keep r14 |V8 a|V49 a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1012.#659 V50 Def CRCE (A) rdx |V8 a|V49 a|V50 a|V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1019.#660 V49 Use * Keep rcx |V8 a|V49 a|V50 a|V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1023.#661 BB46 PredBB45 |V8 a| |V50 a|V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1028.#662 C173 Def BSFIT(A) rcx |V8 a|C173a|V50 a|V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1029.#663 C173 Use * Keep rcx |V8 a|C173a|V50 a|V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1030.#664 I174 Def Alloc rcx |V8 a|I174a|V50 a|V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1031.#665 rcx Fixd Keep rcx |V8 a|I174a|V50 a|V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1031.#666 I174 Use * Keep rcx |V8 a|I174a|V50 a|V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1032.#667 rcx Fixd Keep rcx |V8 a| |V50 a|V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1032.#668 I175 Def Alloc rcx |V8 a|I175a|V50 a|V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1035.#669 rdx Fixd Keep rdx |V8 a|I175a|V50 a|V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1035.#670 V50 Use * Keep rdx |V8 a|I175a|V50 a|V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1036.#671 rdx Fixd Keep rdx |V8 a|I175a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1036.#672 I176 Def Alloc rdx |V8 a|I175a|I176a|V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1037.#673 rcx Fixd Keep rcx |V8 a|I175a|I176a|V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1037.#674 I175 Use * Keep rcx |V8 a|I175a|I176a|V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1037.#675 rdx Fixd Keep rdx |V8 a|I175a|I176a|V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1037.#676 I176 Use * Keep rdx |V8 a|I175a|I176a|V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1038.#677 rax Kill Spill rax | | | |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| Keep rax | | | |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1038.#678 rcx Kill Keep rcx | | | |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1038.#679 rdx Kill Keep rdx | | | |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1038.#680 r8 Kill Spill r8 | | | |V10 a|V2 a|V0 a|V1 a| |V76 a| | |V5 a|V6 a|V73 i|V4 a| Keep r8 | | | |V10 a|V2 a|V0 a|V1 a| |V76 a| | |V5 a|V6 a|V73 i|V4 a| 1038.#681 r9 Kill Spill r9 | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 i|V4 a| Keep r9 | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 i|V4 a| 1038.#682 r10 Kill Keep r10 | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 i|V4 a| 1038.#683 r11 Kill Keep r11 | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 i|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1039.#684 BB47 PredBB45 |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1051.#685 V0 Use Keep rsi |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1052.#686 I177 Def BSFIT(A) rcx |V8 a|I177a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1053.#687 I177 Use * Keep rcx |V8 a|I177a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1054.#688 V63 Def COVRS(A) rcx |V8 a|V63 a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1059.#689 V63 Use Keep rcx |V8 a|V63 a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 i|V4 a| 1059.#690 V76 Use * Keep r9 |V8 a|V63 a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 i| | |V5 a|V6 a|V73 i|V4 a| 1065.#691 V63 Use * Keep rcx |V8 a|V63 a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 i| | |V5 a|V6 a|V73 i|V4 a| 1066.#692 I178 Def BSFIT(A) r9 |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a|I178a| | |V5 a|V6 a|V73 i|V4 a| 1069.#693 I178 Use * Keep r9 |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a|I178a| | |V5 a|V6 a|V73 i|V4 a| Restr r9 |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a|V76 i| | |V5 a|V6 a|V73 i|V4 a| 1070.#694 I179 Def BSFIT(A) rcx |V8 a|I179a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 i| | |V5 a|V6 a|V73 i|V4 a| 1073.#695 V4 Use Keep r15 |V8 a|I179a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 i| | |V5 a|V6 a|V73 i|V4 a| 1073.#696 I179 Use * Keep rcx |V8 a|I179a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 i| | |V5 a|V6 a|V73 i|V4 a| 1074.#697 I180 Def BSFIT(A) rcx |V8 a|I180a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 i| | |V5 a|V6 a|V73 i|V4 a| 1075.#698 I180 Use * Keep rcx |V8 a|I180a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 i| | |V5 a|V6 a|V73 i|V4 a| 1076.#699 I181 Def BSFIT(A) rcx |V8 a|I181a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 i| | |V5 a|V6 a|V73 i|V4 a| 1079.#700 I181 Use * Keep rcx |V8 a|I181a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 i| | |V5 a|V6 a|V73 i|V4 a| 1080.#701 I182 Def COVRS(A) rcx |V8 a|I182a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 i| | |V5 a|V6 a|V73 i|V4 a| 1081.#702 V0 Use Keep rsi |V8 a|I182a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 i| | |V5 a|V6 a|V73 i|V4 a| 1081.#703 I182 Use * Keep rcx |V8 a|I182a| |V10 a|V2 a|V0 a|V1 a|V7 a|V76 i| | |V5 a|V6 a|V73 i|V4 a| 1099.#704 V0 Use Keep rsi |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a|V76 i| | |V5 a|V6 a|V73 i|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1101.#705 BB48 PredBB44 |V8 a| | |V10 i|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 i| 1109.#706 V0 Use Keep rsi |V8 a| | |V10 i|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 i| 1110.#707 I183 Def RELPR(A) rcx |V8 a|I183a| |V10 i|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 i| 1111.#708 I183 Use * Keep rcx |V8 a|I183a| |V10 i|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 i| 1112.#709 V75 Def COVRS(A) rcx |V8 a|V75 a| |V10 i|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 i| 1115.#710 V75 Use Keep rcx |V8 a|V75 a| |V10 i|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 i| 1116.#711 V13 Def RELPR(A) rbx |V8 a|V75 a| |V13 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 i| 1123.#712 V76 Use * Keep r9 |V8 a|V75 a| |V13 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 i| 1123.#713 V13 Use Keep rbx |V8 a|V75 a| |V13 a|V2 a|V0 a|V1 a|V7 a|V76 a| | |V5 a|V6 a|V73 a|V4 i| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1127.#714 BB49 PredBB48 |V8 i|V75 a| |V13 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a|V73 a|V4 i| 1133.#715 rcx Fixd Keep rcx |V8 i|V75 a| |V13 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a|V73 a|V4 i| 1133.#716 V75 Use * Keep rcx |V8 i|V75 a| |V13 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a|V73 a|V4 i| 1134.#717 rcx Fixd Keep rcx |V8 i| | |V13 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a|V73 a|V4 i| 1134.#718 I184 Def Alloc rcx |V8 i|I184a| |V13 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a|V73 a|V4 i| 1135.#719 rcx Fixd Keep rcx |V8 i|I184a| |V13 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a|V73 a|V4 i| 1135.#720 I184 Use * Keep rcx |V8 i|I184a| |V13 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a|V73 a|V4 i| 1136.#721 rax Kill Keep rax | | | |V13 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a|V73 a|V4 i| 1136.#722 rcx Kill Keep rcx | | | |V13 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a|V73 a|V4 i| 1136.#723 rdx Kill Keep rdx | | | |V13 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a|V73 a|V4 i| 1136.#724 r8 Kill Spill r8 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| Keep r8 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1136.#725 r9 Kill Keep r9 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1136.#726 r10 Kill Keep r10 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1136.#727 r11 Kill Keep r11 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1136.#728 rax Fixd Keep rax | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1136.#729 I185 Def Alloc rax |I185a| | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1137.#730 I185 Use * Keep rax |I185a| | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1138.#731 V64 Def BSFIT(A) rdx | | |V64 a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1141.#732 rdx Fixd Keep rdx | | |V64 a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1141.#733 V64 Use * Keep rdx | | |V64 a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1142.#734 rdx Fixd Keep rdx | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1142.#735 I186 Def Alloc rdx | | |I186a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1145.#736 rcx Fixd Keep rcx | | |I186a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1145.#737 V0 Use Copy rcx | |V0 a|I186a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1146.#738 rcx Fixd Keep rcx | |V0 a|I186a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1146.#739 I187 Def Alloc rcx | |I187a|I186a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1148.#740 C188 Def Alloc r8 | |I187a|I186a|V13 a|V2 a|V0 a|V1 a|C188a| | | |V5 a|V6 a|V73 a|V4 i| 1149.#741 r8 Fixd Keep r8 | |I187a|I186a|V13 a|V2 a|V0 a|V1 a|C188a| | | |V5 a|V6 a|V73 a|V4 i| 1149.#742 C188 Use * Keep r8 | |I187a|I186a|V13 a|V2 a|V0 a|V1 a|C188a| | | |V5 a|V6 a|V73 a|V4 i| 1150.#743 r8 Fixd Keep r8 | |I187a|I186a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1150.#744 I189 Def Alloc r8 | |I187a|I186a|V13 a|V2 a|V0 a|V1 a|I189a| | | |V5 a|V6 a|V73 a|V4 i| 1151.#745 rdx Fixd Keep rdx | |I187a|I186a|V13 a|V2 a|V0 a|V1 a|I189a| | | |V5 a|V6 a|V73 a|V4 i| 1151.#746 I186 Use * Keep rdx | |I187a|I186a|V13 a|V2 a|V0 a|V1 a|I189a| | | |V5 a|V6 a|V73 a|V4 i| 1151.#747 rcx Fixd Keep rcx | |I187a|I186a|V13 a|V2 a|V0 a|V1 a|I189a| | | |V5 a|V6 a|V73 a|V4 i| 1151.#748 I187 Use * Keep rcx | |I187a|I186a|V13 a|V2 a|V0 a|V1 a|I189a| | | |V5 a|V6 a|V73 a|V4 i| 1151.#749 r8 Fixd Keep r8 | |I187a|I186a|V13 a|V2 a|V0 a|V1 a|I189a| | | |V5 a|V6 a|V73 a|V4 i| 1151.#750 I189 Use * Keep r8 | |I187a|I186a|V13 a|V2 a|V0 a|V1 a|I189a| | | |V5 a|V6 a|V73 a|V4 i| 1152.#751 rax Kill Keep rax | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1152.#752 rcx Kill Keep rcx | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1152.#753 rdx Kill Keep rdx | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1152.#754 r8 Kill Keep r8 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1152.#755 r9 Kill Keep r9 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1152.#756 r10 Kill Keep r10 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1152.#757 r11 Kill Keep r11 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1159.#758 V0 Use Keep rsi | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1160.#759 I190 Def COREL(A) r15 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|I190a| 1161.#760 I190 Use * Keep r15 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|I190a| Restr r15 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 i| 1162.#761 V52 Def COVRS(A) r15 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1169.#762 V52 Use Keep r15 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1170.#763 I191 Def ORDER(A) rax |I191a| | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1171.#764 I191 Use * Keep rax |I191a| | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1172.#765 V72 Def ORDER(A) rax |V72 a| | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1175.#766 V72 Use Keep rax |V72 a| | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1176.#767 V53 Def ORDER(A) r8 |V72 a| | |V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1183.#768 V0 Use Keep rsi |V72 a| | |V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1184.#769 I192 Def ORDER(A) r9 |V72 a| | |V13 a|V2 a|V0 a|V1 a|V53 a|I192a| | |V5 a|V6 a|V73 a|V52 a| 1185.#770 I192 Use * Keep r9 |V72 a| | |V13 a|V2 a|V0 a|V1 a|V53 a|I192a| | |V5 a|V6 a|V73 a|V52 a| 1186.#771 V54 Def ORDER(A) r9 |V72 a| | |V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1193.#772 V53 Use Keep r8 |V72 a| | |V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1194.#773 I193 Def BSFIT(A) rcx |V72 a|I193a| |V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1195.#774 I193 Use * Keep rcx |V72 a|I193a| |V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1196.#775 V56 Def COVRS(A) rcx |V72 a|V56 a| |V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1203.#776 V73 Use Keep r14 |V72 a|V56 a| |V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1204.#777 V58 Def COVRS(A) rdx |V72 a|V56 a|V58 a|V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1211.#778 V56 Use * Keep rcx |V72 a|V56 a|V58 a|V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1215.#779 BB50 PredBB49 |V72 a| |V58 a|V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1221.#780 rcx Fixd Keep rcx |V72 a| |V58 a|V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1221.#781 V58 Use Copy rcx |V72 a|V58 a|V58 a|V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1222.#782 rcx Fixd Keep rcx |V72 a|V58 a|V58 a|V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1222.#783 I194 Def Alloc rcx |V72 a|I194a|V58 a|V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1225.#784 rdx Fixd Keep rdx |V72 a|I194a|V58 a|V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1225.#785 V58 Use * Keep rdx |V72 a|I194a|V58 a|V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1226.#786 rdx Fixd Keep rdx |V72 a|I194a| |V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1226.#787 I195 Def Alloc rdx |V72 a|I194a|I195a|V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1227.#788 rcx Fixd Keep rcx |V72 a|I194a|I195a|V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1227.#789 I194 Use * Keep rcx |V72 a|I194a|I195a|V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1227.#790 rdx Fixd Keep rdx |V72 a|I194a|I195a|V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1227.#791 I195 Use * Keep rdx |V72 a|I194a|I195a|V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1228.#792 rax Kill Spill rax | | | |V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| Keep rax | | | |V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1228.#793 rcx Kill Keep rcx | | | |V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1228.#794 rdx Kill Keep rdx | | | |V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1228.#795 r8 Kill Spill r8 | | | |V13 a|V2 a|V0 a|V1 a| |V54 a| | |V5 a|V6 a|V73 a|V52 a| Keep r8 | | | |V13 a|V2 a|V0 a|V1 a| |V54 a| | |V5 a|V6 a|V73 a|V52 a| 1228.#796 r9 Kill Spill r9 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| Keep r9 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1228.#797 r10 Kill Keep r10 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1228.#798 r11 Kill Keep r11 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1229.#799 BB51 PredBB49 |V72 a| | |V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1237.#800 V6 Use Keep r13 |V72 a| | |V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1238.#801 I196 Def BSFIT(A) rdx |V72 a| |I196a|V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1239.#802 V54 Use * Keep r9 |V72 a| |I196a|V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1239.#803 I196 Use * Keep rdx |V72 a| |I196a|V13 a|V2 a|V0 a|V1 a|V53 a|V54 a| | |V5 a|V6 a|V73 a|V52 a| 1240.#804 I197 Def BSFIT(A) rdx |V72 a| |I197a|V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1243.#805 I197 Use * Keep rdx |V72 a| |I197a|V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1244.#806 I198 Def COVRS(A) rdx |V72 a| |I198a|V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1247.#807 I198 Use * Keep rdx |V72 a| |I198a|V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1248.#808 I199 Def COVRS(A) rdx |V72 a| |I199a|V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1251.#809 V53 Use Keep r8 |V72 a| |I199a|V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1252.#810 I200 Def BSFIT(A) rcx |V72 a|I200a|I199a|V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1253.#811 I199 Use * Keep rdx |V72 a|I200a|I199a|V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1253.#812 I200 Use * Keep rcx |V72 a|I200a|I199a|V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1254.#813 I201 Def BSFIT(A) rdx |V72 a| |I201a|V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1257.#814 I201 Use * Keep rdx |V72 a| |I201a|V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1258.#815 I202 Def COVRS(A) rdx |V72 a| |I202a|V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1259.#816 I202 Use * Keep rdx |V72 a| |I202a|V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1260.#817 I203 Def ORDER(A) r9 |V72 a| | |V13 a|V2 a|V0 a|V1 a|V53 a|I203a| | |V5 a|V6 a|V73 a|V52 a| 1261.#818 I203 Use * Keep r9 |V72 a| | |V13 a|V2 a|V0 a|V1 a|V53 a|I203a| | |V5 a|V6 a|V73 a|V52 a| 1262.#819 V55 Def ORDER(A) r9 |V72 a| | |V13 a|V2 a|V0 a|V1 a|V53 a|V55 a| | |V5 a|V6 a|V73 a|V52 a| 1269.#820 rax Fixd Keep rax |V72 a| | |V13 a|V2 a|V0 a|V1 a|V53 a|V55 a| | |V5 a|V6 a|V73 a|V52 a| 1269.#821 V6 Use Spill rax | | | |V13 a|V2 a|V0 a|V1 a|V53 a|V55 a| | |V5 a|V6 i|V73 a|V52 a| Copy rax |V6 a| | |V13 a|V2 a|V0 a|V1 a|V53 a|V55 a| | |V5 a|V6 a|V73 a|V52 a| 1269.#822 V53 Use *D Keep r8 |V6 a| | |V13 a|V2 a|V0 a|V1 a|V53 a|V55 a| | |V5 a|V6 a|V73 a|V52 a| 1270.#823 rax Kill Keep rax | | | |V13 a|V2 a|V0 a|V1 a|V53 a|V55 a| | |V5 a|V6 a|V73 a|V52 a| 1270.#824 rdx Kill Keep rdx | | | |V13 a|V2 a|V0 a|V1 a|V53 a|V55 a| | |V5 a|V6 a|V73 a|V52 a| 1270.#825 rdx Fixd Keep rdx | | | |V13 a|V2 a|V0 a|V1 a|V53 a|V55 a| | |V5 a|V6 a|V73 a|V52 a| 1270.#826 I204 Def Alloc rdx | | |I204a|V13 a|V2 a|V0 a|V1 a|V53 a|V55 a| | |V5 a|V6 a|V73 a|V52 a| 1273.#827 I204 Use * Keep rdx | | |I204a|V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a|V73 a|V52 a| 1273.#828 V55 Use Keep r9 | | |I204a|V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a|V73 a|V52 a| 1274.#829 I205 Def BSFIT(A) rcx | |I205a| |V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a|V73 a|V52 a| 1275.#830 I205 Use * Keep rcx | |I205a| |V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a|V73 a|V52 a| 1276.#831 V59 Def COVRS(A) rcx | |V59 a| |V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a|V73 a|V52 a| 1283.#832 V73 Use * Keep r14 | |V59 a| |V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a|V73 a|V52 a| 1284.#833 V61 Def COVRS(A) rdx | |V59 a|V61 a|V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1291.#834 V59 Use * Keep rcx | |V59 a|V61 a|V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1295.#835 BB52 PredBB51 | | |V61 a|V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1301.#836 rcx Fixd Keep rcx | | |V61 a|V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1301.#837 V61 Use Copy rcx | |V61 a|V61 a|V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1302.#838 rcx Fixd Keep rcx | |V61 a|V61 a|V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1302.#839 I206 Def Alloc rcx | |I206a|V61 a|V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1305.#840 rdx Fixd Keep rdx | |I206a|V61 a|V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1305.#841 V61 Use * Keep rdx | |I206a|V61 a|V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1306.#842 rdx Fixd Keep rdx | |I206a| |V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1306.#843 I207 Def Alloc rdx | |I206a|I207a|V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1307.#844 rcx Fixd Keep rcx | |I206a|I207a|V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1307.#845 I206 Use * Keep rcx | |I206a|I207a|V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1307.#846 rdx Fixd Keep rdx | |I206a|I207a|V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1307.#847 I207 Use * Keep rdx | |I206a|I207a|V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1308.#848 rax Kill Keep rax | | | |V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1308.#849 rcx Kill Keep rcx | | | |V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1308.#850 rdx Kill Keep rdx | | | |V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1308.#851 r8 Kill Keep r8 | | | |V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1308.#852 r9 Kill Spill r9 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| Keep r9 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1308.#853 r10 Kill Keep r10 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1308.#854 r11 Kill Keep r11 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1309.#855 BB53 PredBB51 | | | |V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1317.#856 V55 Use Keep r9 | | | |V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1317.#857 V72 Use * ReLod NA | | | |V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| NoReg | | | |V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1323.#858 V55 Use * Keep r9 | | | |V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1324.#859 I208 Def ORDER(A) rdx | | |I208a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1325.#860 V52 Use * Keep r15 | | |I208a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1325.#861 I208 Use * Keep rdx | | |I208a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1326.#862 I209 Def COREL(A) rax |I209a| | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| | | 1327.#863 I209 Use * Keep rax |I209a| | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| | | 1328.#864 V51 Def COVRS(A) rax |V51 a| | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| | | 1331.#865 V51 Use * Keep rax |V51 a| | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| | | 1332.#866 V8 Def ORDER(A) r14 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V8 a| | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1333.#867 BB54 PredBB48 |V8 a| | |V13 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a| | | 1339.#868 V13 Use * Keep rbx |V8 a| | |V13 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a| | | Restr rbx |V8 a| | |V10 i|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a| | | 1340.#869 V10 Def THISA(A) rbx |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a| | | 1347.#870 V10 Use Keep rbx |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a| | | 1348.#871 I210 Def ORDER(A) rdx |V8 a| |I210a|V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a| | | 1353.#872 V0 Use Keep rsi |V8 a| |I210a|V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a| | | 1353.#873 I210 Use * Keep rdx |V8 a| |I210a|V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a| | | 1361.#874 V0 Use Keep rsi |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a| | | 1362.#875 I211 Def COREL(A) r15 |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a| |I211a| 1363.#876 I211 Use * Keep r15 |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a| |I211a| 1364.#877 V4 Def THISA(A) r15 |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a| |V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1365.#878 BB55 PredBB47 |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a| |V4 a| 1377.#879 V10 Use Keep rbx |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a| |V4 a| 1377.#880 V4 Use Keep r15 |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a| |V4 a| 1383.#881 V10 Use Keep rbx |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a| |V4 a| 1384.#882 I212 Def ORDER(A) rdx |V8 a| |I212a|V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a| |V4 a| 1387.#883 I212 Use * Keep rdx |V8 a| |I212a|V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a| |V4 a| 1388.#884 I213 Def ORDER(A) rdx |V8 a| |I213a|V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a| |V4 a| 1389.#885 V4 Use Keep r15 |V8 a| |I213a|V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a| |V4 a| 1389.#886 I213 Use * Keep rdx |V8 a| |I213a|V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a| |V4 a| 1390.#887 I214 Def COREL(A) r14 |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a|I214a|V4 a| 1391.#888 I214 Use * Keep r14 |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a|I214a|V4 a| 1392.#889 V11 Def COVRS(A) r14 |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a|V11 a|V4 a| 1401.#890 V11 Use Keep r14 |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a|V11 a|V4 a| 1401.#891 V6 Use * Keep r13 |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a|V11 a|V4 a| 1407.#892 V8 Use Keep rax |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a| |V11 a|V4 a| 1408.#893 I215 Def ORDER(A) rdx |V8 a| |I215a|V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a| |V11 a|V4 a| 1411.#894 I215 Use * Keep rdx |V8 a| |I215a|V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a| |V11 a|V4 a| 1412.#895 I216 Def COVRS(A) rdx |V8 a| |I216a|V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a| |V11 a|V4 a| 1417.#896 V11 Use Keep r14 |V8 a| |I216a|V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a| |V11 a|V4 a| 1417.#897 I216 Use * Keep rdx |V8 a| |I216a|V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a| |V11 a|V4 a| 1425.#898 rcx Fixd Keep rcx |V8 a| | |V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a| |V11 a|V4 a| 1425.#899 V11 Use Copy rcx |V8 a|V11 a| |V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a| |V11 a|V4 a| 1425.#900 rdx Fixd Keep rdx |V8 a|V11 a| |V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a| |V11 a|V4 a| 1425.#901 V1 Use * Copy rdx |V8 a|V11 a|V1 a|V10 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a| |V11 a|V4 a| 1426.#902 rax Kill Spill rax | |V11 a|V1 i|V10 a|V2 a|V0 a|V1 i|V7 a| | | |V5 a| |V11 a|V4 a| Keep rax | |V11 a|V1 i|V10 a|V2 a|V0 a|V1 i|V7 a| | | |V5 a| |V11 a|V4 a| 1426.#903 rcx Kill Keep rcx | | |V1 i|V10 a|V2 a|V0 a|V1 i|V7 a| | | |V5 a| |V11 a|V4 a| 1426.#904 rdx Kill Keep rdx | | | |V10 a|V2 a|V0 a|V1 i|V7 a| | | |V5 a| |V11 a|V4 a| 1426.#905 r8 Kill Spill r8 | | | |V10 a|V2 a|V0 a|V1 i| | | | |V5 a| |V11 a|V4 a| Keep r8 | | | |V10 a|V2 a|V0 a|V1 i| | | | |V5 a| |V11 a|V4 a| 1426.#906 r9 Kill Keep r9 | | | |V10 a|V2 a|V0 a|V1 i| | | | |V5 a| |V11 a|V4 a| 1426.#907 r10 Kill Keep r10 | | | |V10 a|V2 a|V0 a|V1 i| | | | |V5 a| |V11 a|V4 a| 1426.#908 r11 Kill Keep r11 | | | |V10 a|V2 a|V0 a|V1 i| | | | |V5 a| |V11 a|V4 a| 1426.#909 mm0 Kill Keep mm0 | | | |V10 a|V2 a|V0 a|V1 i| | | | |V5 a| |V11 a|V4 a| 1426.#910 mm1 Kill Keep mm1 | | | |V10 a|V2 a|V0 a|V1 i| | | | |V5 a| |V11 a|V4 a| 1426.#911 mm2 Kill Keep mm2 | | | |V10 a|V2 a|V0 a|V1 i| | | | |V5 a| |V11 a|V4 a| 1426.#912 mm3 Kill Keep mm3 | | | |V10 a|V2 a|V0 a|V1 i| | | | |V5 a| |V11 a|V4 a| 1426.#913 mm4 Kill Keep mm4 | | | |V10 a|V2 a|V0 a|V1 i| | | | |V5 a| |V11 a|V4 a| 1426.#914 mm5 Kill Keep mm5 | | | |V10 a|V2 a|V0 a|V1 i| | | | |V5 a| |V11 a|V4 a| 1431.#915 V11 Use * Keep r14 | | | |V10 a|V2 a|V0 a|V1 i| | | | |V5 a| |V11 a|V4 a| 1432.#916 I217 Def Alloc rcx | |I217a| |V10 a|V2 a|V0 a|V1 i| | | | |V5 a| | |V4 a| 1435.#917 rcx Fixd Keep rcx | |I217a| |V10 a|V2 a|V0 a|V1 i| | | | |V5 a| | |V4 a| 1435.#918 I217 Use * Keep rcx | |I217a| |V10 a|V2 a|V0 a|V1 i| | | | |V5 a| | |V4 a| 1435.#919 rdx Fixd Keep rdx | |I217a| |V10 a|V2 a|V0 a|V1 i| | | | |V5 a| | |V4 a| 1435.#920 V2 Use * Copy rdx | |I217a|V2 a|V10 a|V2 a|V0 a|V1 i| | | | |V5 a| | |V4 a| 1436.#921 rax Kill Keep rax | | | |V10 a| |V0 a|V1 i| | | | |V5 a| | |V4 a| 1436.#922 rcx Kill Keep rcx | | | |V10 a| |V0 a|V1 i| | | | |V5 a| | |V4 a| 1436.#923 rdx Kill Keep rdx | | | |V10 a| |V0 a|V1 i| | | | |V5 a| | |V4 a| 1436.#924 r8 Kill Keep r8 | | | |V10 a| |V0 a|V1 i| | | | |V5 a| | |V4 a| 1436.#925 r9 Kill Keep r9 | | | |V10 a| |V0 a|V1 i| | | | |V5 a| | |V4 a| 1436.#926 r10 Kill Keep r10 | | | |V10 a| |V0 a|V1 i| | | | |V5 a| | |V4 a| 1436.#927 r11 Kill Keep r11 | | | |V10 a| |V0 a|V1 i| | | | |V5 a| | |V4 a| 1436.#928 mm0 Kill Keep mm0 | | | |V10 a| |V0 a|V1 i| | | | |V5 a| | |V4 a| 1436.#929 mm1 Kill Keep mm1 | | | |V10 a| |V0 a|V1 i| | | | |V5 a| | |V4 a| 1436.#930 mm2 Kill Keep mm2 | | | |V10 a| |V0 a|V1 i| | | | |V5 a| | |V4 a| 1436.#931 mm3 Kill Keep mm3 | | | |V10 a| |V0 a|V1 i| | | | |V5 a| | |V4 a| 1436.#932 mm4 Kill Keep mm4 | | | |V10 a| |V0 a|V1 i| | | | |V5 a| | |V4 a| 1436.#933 mm5 Kill Keep mm5 | | | |V10 a| |V0 a|V1 i| | | | |V5 a| | |V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1443.#934 V10 Use * Keep rbx | | | |V10 a| |V0 a|V1 i| | | | |V5 a| | |V4 a| 1444.#935 I218 Def COVRS(A) rbx | | | |I218a| |V0 a|V1 i| | | | |V5 a| | |V4 a| 1447.#936 V8 Use * ReLod NA | | | |I218a| |V0 a|V1 i| | | | |V5 a| | |V4 a| COVRS(A) r14 | | | |I218a| |V0 a|V1 i| | | | |V5 a| |V8 a|V4 a| 1447.#937 I218 Use * Keep rbx | | | |I218a| |V0 a|V1 i| | | | |V5 a| |V8 a|V4 a| 1465.#938 V0 Use Keep rsi | | | | | |V0 a|V1 i| | | | |V5 a| | |V4 a| 1473.#939 V7 Use * ReLod NA | | | | | |V0 a|V1 i| | | | |V5 a| | |V4 a| NoReg | | | | | |V0 a|V1 i| | | | |V5 a| | |V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1477.#940 BB56 PredBB55 | | | | | |V0 a|V1 i| | | | |V5 a| | |V4 a| 1483.#941 rdx Fixd Keep rdx | | | | | |V0 a|V1 i| | | | |V5 a| | |V4 a| 1483.#942 V5 Use * Copy rdx | | |V5 a| | |V0 a|V1 i| | | | |V5 a| | |V4 a| 1484.#943 rdx Fixd Keep rdx | | | | | |V0 a|V1 i| | | | | | | |V4 a| 1484.#944 I219 Def Alloc rdx | | |I219a| | |V0 a|V1 i| | | | | | | |V4 a| 1486.#945 C220 Def Alloc rcx | |C220a|I219a| | |V0 a|V1 i| | | | | | | |V4 a| 1487.#946 rcx Fixd Keep rcx | |C220a|I219a| | |V0 a|V1 i| | | | | | | |V4 a| 1487.#947 C220 Use * Keep rcx | |C220a|I219a| | |V0 a|V1 i| | | | | | | |V4 a| 1488.#948 rcx Fixd Keep rcx | | |I219a| | |V0 a|V1 i| | | | | | | |V4 a| 1488.#949 I221 Def Alloc rcx | |I221a|I219a| | |V0 a|V1 i| | | | | | | |V4 a| 1489.#950 rdx Fixd Keep rdx | |I221a|I219a| | |V0 a|V1 i| | | | | | | |V4 a| 1489.#951 I219 Use * Keep rdx | |I221a|I219a| | |V0 a|V1 i| | | | | | | |V4 a| 1489.#952 rcx Fixd Keep rcx | |I221a|I219a| | |V0 a|V1 i| | | | | | | |V4 a| 1489.#953 I221 Use * Keep rcx | |I221a|I219a| | |V0 a|V1 i| | | | | | | |V4 a| 1490.#954 rax Kill Keep rax | | | | | |V0 a|V1 i| | | | | | | |V4 a| 1490.#955 rcx Kill Keep rcx | | | | | |V0 a|V1 i| | | | | | | |V4 a| 1490.#956 rdx Kill Keep rdx | | | | | |V0 a|V1 i| | | | | | | |V4 a| 1490.#957 r8 Kill Keep r8 | | | | | |V0 a|V1 i| | | | | | | |V4 a| 1490.#958 r9 Kill Keep r9 | | | | | |V0 a|V1 i| | | | | | | |V4 a| 1490.#959 r10 Kill Keep r10 | | | | | |V0 a|V1 i| | | | | | | |V4 a| 1490.#960 r11 Kill Keep r11 | | | | | |V0 a|V1 i| | | | | | | |V4 a| 1490.#961 rax Fixd Keep rax | | | | | |V0 a|V1 i| | | | | | | |V4 a| 1490.#962 I222 Def Alloc rax |I222a| | | | |V0 a|V1 i| | | | | | | |V4 a| 1493.#963 I222 Use * Keep rax |I222a| | | | |V0 a|V1 i| | | | | | | |V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1497.#964 BB57 PredBB56 | | | | | |V0 a|V1 i| | | | | | | |V4 a| 1505.#965 V4 Use * Keep r15 | | | | | |V0 a|V1 i| | | | | | | |V4 a| 1506.#966 I223 Def Alloc rdx | | |I223a| | |V0 a|V1 i| | | | | | | | | 1507.#967 rdx Fixd Keep rdx | | |I223a| | |V0 a|V1 i| | | | | | | | | 1507.#968 I223 Use * Keep rdx | | |I223a| | |V0 a|V1 i| | | | | | | | | 1508.#969 rdx Fixd Keep rdx | | | | | |V0 a|V1 i| | | | | | | | | 1508.#970 I224 Def Alloc rdx | | |I224a| | |V0 a|V1 i| | | | | | | | | 1511.#971 rcx Fixd Keep rcx | | |I224a| | |V0 a|V1 i| | | | | | | | | 1511.#972 V0 Use Copy rcx | |V0 a|I224a| | |V0 a|V1 i| | | | | | | | | 1512.#973 rcx Fixd Keep rcx | |V0 a|I224a| | |V0 a|V1 i| | | | | | | | | 1512.#974 I225 Def Alloc rcx | |I225a|I224a| | |V0 a|V1 i| | | | | | | | | 1514.#975 C226 Def Alloc r8 | |I225a|I224a| | |V0 a|V1 i|C226a| | | | | | | | 1515.#976 r8 Fixd Keep r8 | |I225a|I224a| | |V0 a|V1 i|C226a| | | | | | | | 1515.#977 C226 Use * Keep r8 | |I225a|I224a| | |V0 a|V1 i|C226a| | | | | | | | 1516.#978 r8 Fixd Keep r8 | |I225a|I224a| | |V0 a|V1 i| | | | | | | | | 1516.#979 I227 Def Alloc r8 | |I225a|I224a| | |V0 a|V1 i|I227a| | | | | | | | 1517.#980 rdx Fixd Keep rdx | |I225a|I224a| | |V0 a|V1 i|I227a| | | | | | | | 1517.#981 I224 Use * Keep rdx | |I225a|I224a| | |V0 a|V1 i|I227a| | | | | | | | 1517.#982 rcx Fixd Keep rcx | |I225a|I224a| | |V0 a|V1 i|I227a| | | | | | | | 1517.#983 I225 Use * Keep rcx | |I225a|I224a| | |V0 a|V1 i|I227a| | | | | | | | 1517.#984 r8 Fixd Keep r8 | |I225a|I224a| | |V0 a|V1 i|I227a| | | | | | | | 1517.#985 I227 Use * Keep r8 | |I225a|I224a| | |V0 a|V1 i|I227a| | | | | | | | 1518.#986 rax Kill Keep rax | | | | | |V0 a|V1 i| | | | | | | | | 1518.#987 rcx Kill Keep rcx | | | | | |V0 a|V1 i| | | | | | | | | 1518.#988 rdx Kill Keep rdx | | | | | |V0 a|V1 i| | | | | | | | | 1518.#989 r8 Kill Keep r8 | | | | | |V0 a|V1 i| | | | | | | | | 1518.#990 r9 Kill Keep r9 | | | | | |V0 a|V1 i| | | | | | | | | 1518.#991 r10 Kill Keep r10 | | | | | |V0 a|V1 i| | | | | | | | | 1518.#992 r11 Kill Keep r11 | | | | | |V0 a|V1 i| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1519.#993 BB58 PredBB29 | | | | | |V0 a|V1 i| | | | | | | | | 1522.#994 C228 Def Alloc rax |C228a| | | | |V0 a|V1 i| | | | | | | | | 1523.#995 rax Fixd Keep rax |C228a| | | | |V0 a|V1 i| | | | | | | | | 1523.#996 C228 Use * Keep rax |C228a| | | | |V0 a|V1 i| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1525.#997 BB59 PredBB1 | | | | | |V0 a|V1 i| | | | | | | | | 1530.#998 C229 Def Alloc rcx | |C229a| | | |V0 a|V1 i| | | | | | | | | 1531.#999 rcx Fixd Keep rcx | |C229a| | | |V0 a|V1 i| | | | | | | | | 1531.#1000 C229 Use * Keep rcx | |C229a| | | |V0 a|V1 i| | | | | | | | | 1532.#1001 rcx Fixd Keep rcx | | | | | |V0 a|V1 i| | | | | | | | | 1532.#1002 I230 Def Alloc rcx | |I230a| | | |V0 a|V1 i| | | | | | | | | 1533.#1003 rcx Fixd Keep rcx | |I230a| | | |V0 a|V1 i| | | | | | | | | 1533.#1004 I230 Use * Keep rcx | |I230a| | | |V0 a|V1 i| | | | | | | | | 1534.#1005 rax Kill Keep rax | | | | | |V0 a|V1 i| | | | | | | | | 1534.#1006 rcx Kill Keep rcx | | | | | |V0 a|V1 i| | | | | | | | | 1534.#1007 rdx Kill Keep rdx | | | | | |V0 a|V1 i| | | | | | | | | 1534.#1008 r8 Kill Keep r8 | | | | | |V0 a|V1 i| | | | | | | | | 1534.#1009 r9 Kill Keep r9 | | | | | |V0 a|V1 i| | | | | | | | | 1534.#1010 r10 Kill Keep r10 | | | | | |V0 a|V1 i| | | | | | | | | 1534.#1011 r11 Kill Keep r11 | | | | | |V0 a|V1 i| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1535.#1012 BB60 PredBB30 | | | | | |V0 a|V1 a| | | | | | | | | 1541.#1013 V0 Use Keep rsi | | | | | |V0 a|V1 a| | | | | | | | | 1542.#1014 I231 Def RELPR(A) rcx | |I231a| | | |V0 a|V1 a| | | | | | | | | 1543.#1015 I231 Use * Keep rcx | |I231a| | | |V0 a|V1 a| | | | | | | | | 1544.#1016 V26 Def COVRS(A) rcx | |V26 a| | | |V0 a|V1 a| | | | | | | | | 1549.#1017 V26 Use Keep rcx | |V26 a| | | |V0 a|V1 a| | | | | | | | | 1550.#1018 I232 Def BSFIT(A) rdx | |V26 a|I232a| | |V0 a|V1 a| | | | | | | | | 1551.#1019 I232 Use * Keep rdx | |V26 a|I232a| | |V0 a|V1 a| | | | | | | | | 1552.#1020 I233 Def BSFIT(A) rdx | |V26 a|I233a| | |V0 a|V1 a| | | | | | | | | 1559.#1021 I233 Use * Keep rdx | |V26 a|I233a| | |V0 a|V1 a| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1563.#1022 BB61 PredBB60 | |V26 a| | | |V0 a|V1 a| | | | | | | | | 1569.#1023 V26 Use * Keep rcx | |V26 i| | | |V0 a|V1 a| | | | | | | | | 1570.#1024 I234 Def BSFIT(A) rcx | |I234a| | | |V0 a|V1 a| | | | | | | | | 1571.#1025 I234 Use * Keep rcx | |I234a| | | |V0 a|V1 a| | | | | | | | | Restr rcx | |V26 i| | | |V0 a|V1 a| | | | | | | | | 1572.#1026 I235 Def BSFIT(A) rcx | |I235a| | | |V0 a|V1 a| | | | | | | | | 1575.#1027 I235 Use * Keep rcx | |I235a| | | |V0 a|V1 a| | | | | | | | | 1576.#1028 I236 Def RELPR(A) rcx | |I236a| | | |V0 a|V1 a| | | | | | | | | 1577.#1029 I236 Use * Keep rcx | |I236a| | | |V0 a|V1 a| | | | | | | | | 1578.#1030 V28 Def OWNPR(A) rcx | |V28 a| | | |V0 a|V1 a| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1579.#1031 BB62 PredBB60 | |V26 a| | | |V0 a|V1 a| | | | | | | | | 1583.#1032 rcx Fixd Keep rcx | |V26 a| | | |V0 a|V1 a| | | | | | | | | 1583.#1033 V26 Use * Keep rcx | |V26 a| | | |V0 a|V1 a| | | | | | | | | 1584.#1034 rcx Fixd Keep rcx | | | | | |V0 a|V1 a| | | | | | | | | 1584.#1035 I237 Def Alloc rcx | |I237a| | | |V0 a|V1 a| | | | | | | | | 1586.#1036 C238 Def Alloc rdx | |I237a|C238a| | |V0 a|V1 a| | | | | | | | | 1587.#1037 rdx Fixd Keep rdx | |I237a|C238a| | |V0 a|V1 a| | | | | | | | | 1587.#1038 C238 Use * Keep rdx | |I237a|C238a| | |V0 a|V1 a| | | | | | | | | 1588.#1039 rdx Fixd Keep rdx | |I237a| | | |V0 a|V1 a| | | | | | | | | 1588.#1040 I239 Def Alloc rdx | |I237a|I239a| | |V0 a|V1 a| | | | | | | | | 1589.#1041 rcx Fixd Keep rcx | |I237a|I239a| | |V0 a|V1 a| | | | | | | | | 1589.#1042 I237 Use * Keep rcx | |I237a|I239a| | |V0 a|V1 a| | | | | | | | | 1589.#1043 rdx Fixd Keep rdx | |I237a|I239a| | |V0 a|V1 a| | | | | | | | | 1589.#1044 I239 Use * Keep rdx | |I237a|I239a| | |V0 a|V1 a| | | | | | | | | 1590.#1045 rax Kill Keep rax | | | | | |V0 a|V1 a| | | | | | | | | 1590.#1046 rcx Kill Keep rcx | | | | | |V0 a|V1 a| | | | | | | | | 1590.#1047 rdx Kill Keep rdx | | | | | |V0 a|V1 a| | | | | | | | | 1590.#1048 r8 Kill Keep r8 | | | | | |V0 a|V1 a| | | | | | | | | 1590.#1049 r9 Kill Keep r9 | | | | | |V0 a|V1 a| | | | | | | | | 1590.#1050 r10 Kill Keep r10 | | | | | |V0 a|V1 a| | | | | | | | | 1590.#1051 r11 Kill Keep r11 | | | | | |V0 a|V1 a| | | | | | | | | 1590.#1052 rax Fixd Keep rax | | | | | |V0 a|V1 a| | | | | | | | | 1590.#1053 I240 Def Alloc rax |I240a| | | | |V0 a|V1 a| | | | | | | | | 1591.#1054 I240 Use * Keep rax |I240a| | | | |V0 a|V1 a| | | | | | | | | 1592.#1055 V28 Def THISA(A) rcx | |V28 a| | | |V0 a|V1 a| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1593.#1056 BB63 PredBB61 | |V28 a| | | |V0 a|V1 a| | | | | | | | | 1597.#1057 rcx Fixd Keep rcx | |V28 a| | | |V0 a|V1 a| | | | | | | | | 1597.#1058 V28 Use * Keep rcx | |V28 a| | | |V0 a|V1 a| | | | | | | | | 1598.#1059 rcx Fixd Keep rcx | | | | | |V0 a|V1 a| | | | | | | | | 1598.#1060 I241 Def Alloc rcx | |I241a| | | |V0 a|V1 a| | | | | | | | | 1601.#1061 rdx Fixd Keep rdx | |I241a| | | |V0 a|V1 a| | | | | | | | | 1601.#1062 V1 Use * Copy rdx | |I241a|V1 a| | |V0 a|V1 a| | | | | | | | | 1602.#1063 rdx Fixd Keep rdx | |I241a|V1 i| | |V0 a|V1 i| | | | | | | | | 1602.#1064 I242 Def Alloc rdx | |I241a|I242a| | |V0 a|V1 i| | | | | | | | | 1603.#1065 rcx Fixd Keep rcx | |I241a|I242a| | |V0 a|V1 i| | | | | | | | | 1603.#1066 I241 Use * Keep rcx | |I241a|I242a| | |V0 a|V1 i| | | | | | | | | 1603.#1067 rdx Fixd Keep rdx | |I241a|I242a| | |V0 a|V1 i| | | | | | | | | 1603.#1068 I242 Use * Keep rdx | |I241a|I242a| | |V0 a|V1 i| | | | | | | | | 1604.#1069 rax Kill Keep rax | | | | | |V0 a|V1 i| | | | | | | | | 1604.#1070 rcx Kill Keep rcx | | | | | |V0 a|V1 i| | | | | | | | | 1604.#1071 rdx Kill Keep rdx | | | | | |V0 a|V1 i| | | | | | | | | 1604.#1072 r8 Kill Keep r8 | | | | | |V0 a|V1 i| | | | | | | | | 1604.#1073 r9 Kill Keep r9 | | | | | |V0 a|V1 i| | | | | | | | | 1604.#1074 r10 Kill Keep r10 | | | | | |V0 a|V1 i| | | | | | | | | 1604.#1075 r11 Kill Keep r11 | | | | | |V0 a|V1 i| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1605.#1076 BB64 PredBB40 | | | | | |V0 a|V1 a| | | | | | | | | 1611.#1077 V0 Use Keep rsi | | | | | |V0 a|V1 a| | | | | | | | | 1612.#1078 I243 Def RELPR(A) rcx | |I243a| | | |V0 a|V1 a| | | | | | | | | 1613.#1079 I243 Use * Keep rcx | |I243a| | | |V0 a|V1 a| | | | | | | | | 1614.#1080 V21 Def COVRS(A) rcx | |V21 a| | | |V0 a|V1 a| | | | | | | | | 1619.#1081 V21 Use Keep rcx | |V21 a| | | |V0 a|V1 a| | | | | | | | | 1620.#1082 I244 Def BSFIT(A) rdx | |V21 a|I244a| | |V0 a|V1 a| | | | | | | | | 1621.#1083 I244 Use * Keep rdx | |V21 a|I244a| | |V0 a|V1 a| | | | | | | | | 1622.#1084 I245 Def BSFIT(A) rdx | |V21 a|I245a| | |V0 a|V1 a| | | | | | | | | 1629.#1085 I245 Use * Keep rdx | |V21 a|I245a| | |V0 a|V1 a| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1633.#1086 BB65 PredBB64 | |V21 a| | | |V0 a|V1 a| | | | | | | | | 1639.#1087 V21 Use * Keep rcx | |V21 i| | | |V0 a|V1 a| | | | | | | | | 1640.#1088 I246 Def BSFIT(A) rcx | |I246a| | | |V0 a|V1 a| | | | | | | | | 1641.#1089 I246 Use * Keep rcx | |I246a| | | |V0 a|V1 a| | | | | | | | | Restr rcx | |V21 i| | | |V0 a|V1 a| | | | | | | | | 1642.#1090 I247 Def BSFIT(A) rcx | |I247a| | | |V0 a|V1 a| | | | | | | | | 1645.#1091 I247 Use * Keep rcx | |I247a| | | |V0 a|V1 a| | | | | | | | | 1646.#1092 I248 Def RELPR(A) rcx | |I248a| | | |V0 a|V1 a| | | | | | | | | 1647.#1093 I248 Use * Keep rcx | |I248a| | | |V0 a|V1 a| | | | | | | | | 1648.#1094 V23 Def OWNPR(A) rcx | |V23 a| | | |V0 a|V1 a| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1649.#1095 BB66 PredBB64 | |V21 a| | | |V0 a|V1 a| | | | | | | | | 1653.#1096 rcx Fixd Keep rcx | |V21 a| | | |V0 a|V1 a| | | | | | | | | 1653.#1097 V21 Use * Keep rcx | |V21 a| | | |V0 a|V1 a| | | | | | | | | 1654.#1098 rcx Fixd Keep rcx | | | | | |V0 a|V1 a| | | | | | | | | 1654.#1099 I249 Def Alloc rcx | |I249a| | | |V0 a|V1 a| | | | | | | | | 1656.#1100 C250 Def Alloc rdx | |I249a|C250a| | |V0 a|V1 a| | | | | | | | | 1657.#1101 rdx Fixd Keep rdx | |I249a|C250a| | |V0 a|V1 a| | | | | | | | | 1657.#1102 C250 Use * Keep rdx | |I249a|C250a| | |V0 a|V1 a| | | | | | | | | 1658.#1103 rdx Fixd Keep rdx | |I249a| | | |V0 a|V1 a| | | | | | | | | 1658.#1104 I251 Def Alloc rdx | |I249a|I251a| | |V0 a|V1 a| | | | | | | | | 1659.#1105 rcx Fixd Keep rcx | |I249a|I251a| | |V0 a|V1 a| | | | | | | | | 1659.#1106 I249 Use * Keep rcx | |I249a|I251a| | |V0 a|V1 a| | | | | | | | | 1659.#1107 rdx Fixd Keep rdx | |I249a|I251a| | |V0 a|V1 a| | | | | | | | | 1659.#1108 I251 Use * Keep rdx | |I249a|I251a| | |V0 a|V1 a| | | | | | | | | 1660.#1109 rax Kill Keep rax | | | | | |V0 a|V1 a| | | | | | | | | 1660.#1110 rcx Kill Keep rcx | | | | | |V0 a|V1 a| | | | | | | | | 1660.#1111 rdx Kill Keep rdx | | | | | |V0 a|V1 a| | | | | | | | | 1660.#1112 r8 Kill Keep r8 | | | | | |V0 a|V1 a| | | | | | | | | 1660.#1113 r9 Kill Keep r9 | | | | | |V0 a|V1 a| | | | | | | | | 1660.#1114 r10 Kill Keep r10 | | | | | |V0 a|V1 a| | | | | | | | | 1660.#1115 r11 Kill Keep r11 | | | | | |V0 a|V1 a| | | | | | | | | 1660.#1116 rax Fixd Keep rax | | | | | |V0 a|V1 a| | | | | | | | | 1660.#1117 I252 Def Alloc rax |I252a| | | | |V0 a|V1 a| | | | | | | | | 1661.#1118 I252 Use * Keep rax |I252a| | | | |V0 a|V1 a| | | | | | | | | 1662.#1119 V23 Def THISA(A) rcx | |V23 a| | | |V0 a|V1 a| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1663.#1120 BB67 PredBB65 | |V23 a| | | |V0 a|V1 a| | | | | | | | | 1667.#1121 rcx Fixd Keep rcx | |V23 a| | | |V0 a|V1 a| | | | | | | | | 1667.#1122 V23 Use * Keep rcx | |V23 a| | | |V0 a|V1 a| | | | | | | | | 1668.#1123 rcx Fixd Keep rcx | | | | | |V0 a|V1 a| | | | | | | | | 1668.#1124 I253 Def Alloc rcx | |I253a| | | |V0 a|V1 a| | | | | | | | | 1671.#1125 rdx Fixd Keep rdx | |I253a| | | |V0 a|V1 a| | | | | | | | | 1671.#1126 V1 Use * Copy rdx | |I253a|V1 a| | |V0 a|V1 a| | | | | | | | | 1672.#1127 rdx Fixd Keep rdx | |I253a| | | |V0 a| | | | | | | | | | 1672.#1128 I254 Def Alloc rdx | |I253a|I254a| | |V0 a| | | | | | | | | | 1673.#1129 rcx Fixd Keep rcx | |I253a|I254a| | |V0 a| | | | | | | | | | 1673.#1130 I253 Use * Keep rcx | |I253a|I254a| | |V0 a| | | | | | | | | | 1673.#1131 rdx Fixd Keep rdx | |I253a|I254a| | |V0 a| | | | | | | | | | 1673.#1132 I254 Use * Keep rdx | |I253a|I254a| | |V0 a| | | | | | | | | | 1674.#1133 rax Kill Keep rax | | | | | |V0 a| | | | | | | | | | 1674.#1134 rcx Kill Keep rcx | | | | | |V0 a| | | | | | | | | | 1674.#1135 rdx Kill Keep rdx | | | | | |V0 a| | | | | | | | | | 1674.#1136 r8 Kill Keep r8 | | | | | |V0 a| | | | | | | | | | 1674.#1137 r9 Kill Keep r9 | | | | | |V0 a| | | | | | | | | | 1674.#1138 r10 Kill Keep r10 | | | | | |V0 a| | | | | | | | | | 1674.#1139 r11 Kill Keep r11 | | | | | |V0 a| | | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1675.#1140 BB68 PredBB26 | | | | | |V0 a| | | | | | | | | | 1680.#1141 rax Kill Keep rax | | | | | |V0 a| | | | | | | | | | 1680.#1142 rcx Kill Keep rcx | | | | | |V0 a| | | | | | | | | | 1680.#1143 rdx Kill Keep rdx | | | | | |V0 a| | | | | | | | | | 1680.#1144 r8 Kill Keep r8 | | | | | |V0 a| | | | | | | | | | 1680.#1145 r9 Kill Keep r9 | | | | | |V0 a| | | | | | | | | | 1680.#1146 r10 Kill Keep r10 | | | | | |V0 a| | | | | | | | | | 1680.#1147 r11 Kill Keep r11 | | | | | |V0 a| | | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ DDefs | | | | | |V0 a| | | | | | | | | | 1681.#1148 V0 DDef Keep rsi | | | | | |V0 a| | | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1681.#1149 BB69 PredBB0 | | | | | |V0 a| | | | | | | | | | 1684.#1150 rax Kill Keep rax | | | | | |V0 a| | | | | | | | | | 1684.#1151 rcx Kill Keep rcx | | | | | |V0 a| | | | | | | | | | 1684.#1152 rdx Kill Keep rdx | | | | | |V0 a| | | | | | | | | | 1684.#1153 r8 Kill Keep r8 | | | | | |V0 a| | | | | | | | | | 1684.#1154 r9 Kill Keep r9 | | | | | |V0 a| | | | | | | | | | 1684.#1155 r10 Kill Keep r10 | | | | | |V0 a| | | | | | | | | | 1684.#1156 r11 Kill Keep r11 | | | | | |V0 a| | | | | | | | | | 1685.#1157 V0 ExpU Keep NA | | | | | |V0 a| | | | | | | | | | 1685.#1158 V0 ExpU Keep NA | | | | | |V0 a| | | | | | | | | | ------------ REFPOSITIONS AFTER ALLOCATION: ------------ BB00 regmask=[rsi] minReg=1 regOptional> BB00 regmask=[rdi] minReg=1 regOptional> BB00 regmask=[rbx] minReg=1 regOptional> BB00 regmask=[rbp] minReg=1 regOptional> LCL_VAR BB01 regmask=[rdi] minReg=1 regOptional> LCL_VAR BB02 regmask=[rsi] minReg=1> BB03 regmask=[rcx] minReg=1> LCL_VAR BB03 regmask=[rcx] minReg=1 copy fixed> BB03 regmask=[rcx] minReg=1> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed> CNS_INT BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1 last fixed> BB03 regmask=[rdx] minReg=1> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed> BB03 regmask=[rcx] minReg=1> BB03 regmask=[rcx] minReg=1 last fixed> BB03 regmask=[rdx] minReg=1> BB03 regmask=[rdx] minReg=1 last fixed> BB03 regmask=[rax] minReg=1 last> BB03 regmask=[rcx] minReg=1 last> BB03 regmask=[rdx] minReg=1 last> BB03 regmask=[r8] minReg=1 last> BB03 regmask=[r9] minReg=1 last> BB03 regmask=[r10] minReg=1 last> BB03 regmask=[r11] minReg=1 last> BB03 regmask=[rax] minReg=1> CALL BB03 regmask=[rax] minReg=1 last fixed local> LCL_VAR BB04 regmask=[rsi] minReg=1> NE BB04 regmask=[rcx] minReg=1> BB04 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB04 regmask=[rcx] minReg=1> CNS_INT BB04 regmask=[rdx] minReg=1> BB04 regmask=[rdx] minReg=1 last> IND BB04 regmask=[r14] minReg=1> BB04 regmask=[r14] minReg=1 last> STORE_LCL_VAR BB04 regmask=[r14] minReg=1> LCL_VAR BB04 regmask=[r14] minReg=1> STORE_LCL_VAR BB04 regmask=[rdx] minReg=1> LCL_VAR BB04 regmask=[rcx] minReg=1 last regOptional> BB05 regmask=[rcx] minReg=1> LCL_VAR BB05 regmask=[rcx] minReg=1 copy fixed> BB05 regmask=[rcx] minReg=1> PUTARG_REG BB05 regmask=[rcx] minReg=1 fixed> BB05 regmask=[rdx] minReg=1> LCL_VAR BB05 regmask=[rdx] minReg=1 last fixed> BB05 regmask=[rdx] minReg=1> PUTARG_REG BB05 regmask=[rdx] minReg=1 fixed> BB05 regmask=[rcx] minReg=1> BB05 regmask=[rcx] minReg=1 last fixed> BB05 regmask=[rdx] minReg=1> BB05 regmask=[rdx] minReg=1 last fixed> BB05 regmask=[rax] minReg=1 last> BB05 regmask=[rcx] minReg=1 last> BB05 regmask=[rdx] minReg=1 last> BB05 regmask=[r8] minReg=1 last> BB05 regmask=[r9] minReg=1 last> BB05 regmask=[r10] minReg=1 last> BB05 regmask=[r11] minReg=1 last> LCL_VAR BB06 regmask=[rsi] minReg=1> IND BB06 regmask=[r15] minReg=1> BB06 regmask=[r15] minReg=1 last> STORE_LCL_VAR BB06 regmask=[r15] minReg=1> LCL_VAR BB06 regmask=[r15] minReg=1 regOptional> NE BB06 regmask=[rcx] minReg=1> BB06 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB06 regmask=[rcx] minReg=1> LCL_VAR BB06 regmask=[r14] minReg=1> STORE_LCL_VAR BB06 regmask=[rdx] minReg=1> LCL_VAR BB06 regmask=[rcx] minReg=1 last regOptional> CNS_INT BB07 regmask=[rcx] minReg=1> BB07 regmask=[rcx] minReg=1 last> IND BB07 regmask=[rcx] minReg=1> BB07 regmask=[rcx] minReg=1> BB07 regmask=[rcx] minReg=1 last fixed> BB07 regmask=[rcx] minReg=1> PUTARG_REG BB07 regmask=[rcx] minReg=1 fixed> BB07 regmask=[rdx] minReg=1> LCL_VAR BB07 regmask=[rdx] minReg=1 last fixed> BB07 regmask=[rdx] minReg=1> PUTARG_REG BB07 regmask=[rdx] minReg=1 fixed> BB07 regmask=[rcx] minReg=1> BB07 regmask=[rcx] minReg=1 last fixed> BB07 regmask=[rdx] minReg=1> BB07 regmask=[rdx] minReg=1 last fixed> BB07 regmask=[rax] minReg=1 last> BB07 regmask=[rcx] minReg=1 last> BB07 regmask=[rdx] minReg=1 last> BB07 regmask=[r8] minReg=1 last> BB07 regmask=[r9] minReg=1 last> BB07 regmask=[r10] minReg=1 last> BB07 regmask=[r11] minReg=1 last> LCL_VAR BB08 regmask=[rsi] minReg=1> IND BB08 regmask=[r12] minReg=1> BB08 regmask=[r12] minReg=1 last> STORE_LCL_VAR BB08 regmask=[r12] minReg=1> LCL_VAR BB08 regmask=[r12] minReg=1 regOptional> LCL_VAR BB09 regmask=[rsi] minReg=1> IND BB09 regmask=[rcx] minReg=1> BB09 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB09 regmask=[rcx] minReg=1> LCL_VAR BB09 regmask=[rcx] minReg=1> IND BB09 regmask=[rdx] minReg=1> BB09 regmask=[rdx] minReg=1 last> IND BB09 regmask=[rdx] minReg=1> BB09 regmask=[rdx] minReg=1 last> IND BB09 regmask=[r11] minReg=1> BB09 regmask=[r11] minReg=1 last> STORE_LCL_VAR BB09 regmask=[r11] minReg=1> LCL_VAR BB09 regmask=[r11] minReg=1 regOptional> LCL_VAR BB10 regmask=[r11] minReg=1 last> STORE_LCL_VAR BB10 regmask=[r11] minReg=1> BB11 regmask=[rcx] minReg=1> LCL_VAR BB11 regmask=[rcx] minReg=1 last fixed> BB11 regmask=[rcx] minReg=1> PUTARG_REG BB11 regmask=[rcx] minReg=1 fixed> CNS_INT BB11 regmask=[rdx] minReg=1> BB11 regmask=[rdx] minReg=1> BB11 regmask=[rdx] minReg=1 last fixed> BB11 regmask=[rdx] minReg=1> PUTARG_REG BB11 regmask=[rdx] minReg=1 fixed> BB11 regmask=[rcx] minReg=1> BB11 regmask=[rcx] minReg=1 last fixed> BB11 regmask=[rdx] minReg=1> BB11 regmask=[rdx] minReg=1 last fixed> BB11 regmask=[rax] minReg=1 last> BB11 regmask=[rcx] minReg=1 last> BB11 regmask=[rdx] minReg=1 last> BB11 regmask=[r8] minReg=1 last> BB11 regmask=[r9] minReg=1 last> BB11 regmask=[r10] minReg=1 last> BB11 regmask=[r11] minReg=1 last> BB11 regmask=[rax] minReg=1> CALL BB11 regmask=[rax] minReg=1 fixed> BB11 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB11 regmask=[r11] minReg=1> BB12 regmask=[rcx] minReg=1> LCL_VAR BB12 regmask=[rcx] minReg=1 copy fixed> BB12 regmask=[rcx] minReg=1> PUTARG_REG BB12 regmask=[rcx] minReg=1 fixed> BB12 regmask=[r11] minReg=1> LCL_VAR BB12 regmask=[r11] minReg=1 fixed> BB12 regmask=[r11] minReg=1> PUTARG_REG BB12 regmask=[r11] minReg=1 fixed> BB12 regmask=[rdx] minReg=1> LCL_VAR BB12 regmask=[rdx] minReg=1 copy fixed> BB12 regmask=[rdx] minReg=1> PUTARG_REG BB12 regmask=[rdx] minReg=1 fixed> BB12 regmask=[rcx] minReg=1> BB12 regmask=[rcx] minReg=1 last fixed> BB12 regmask=[r11] minReg=1> BB12 regmask=[r11] minReg=1 last fixed> BB12 regmask=[rdx] minReg=1> BB12 regmask=[rdx] minReg=1 last fixed> LCL_VAR BB12 regmask=[r11] minReg=1 last> BB12 regmask=[rax] minReg=1 last> BB12 regmask=[rcx] minReg=1 last> BB12 regmask=[rdx] minReg=1 last> BB12 regmask=[r8] minReg=1 last> BB12 regmask=[r9] minReg=1 last> BB12 regmask=[r10] minReg=1 last> BB12 regmask=[r11] minReg=1 last> BB12 regmask=[rax] minReg=1> CALL BB12 regmask=[rax] minReg=1 fixed> BB12 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB12 regmask=[r13] minReg=1> BB13 regmask=[rcx] minReg=1> LCL_VAR BB13 regmask=[rcx] minReg=1 copy fixed> BB13 regmask=[rcx] minReg=1> PUTARG_REG BB13 regmask=[rcx] minReg=1 fixed> LCL_VAR BB13 regmask=[rdi] minReg=1> IND BB13 regmask=[rax] minReg=1> BB13 regmask=[rax] minReg=1 last> IND BB13 regmask=[rax] minReg=1> BB13 regmask=[rcx] minReg=1> BB13 regmask=[rcx] minReg=1 last fixed> BB13 regmask=[rax] minReg=1 last> BB13 regmask=[rax] minReg=1 last> BB13 regmask=[rcx] minReg=1 last> BB13 regmask=[rdx] minReg=1 last> BB13 regmask=[r8] minReg=1 last> BB13 regmask=[r9] minReg=1 last> BB13 regmask=[r10] minReg=1 last> BB13 regmask=[r11] minReg=1 last> BB13 regmask=[rax] minReg=1> CALL BB13 regmask=[rax] minReg=1 fixed> BB13 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB13 regmask=[r13] minReg=1> LCL_VAR BB14 regmask=[r13] minReg=1 last> STORE_LCL_VAR BB14 regmask=[r13] minReg=1> CNS_INT BB14 regmask=[rax] minReg=1> BB14 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB14 regmask=[rax] minReg=1 spillAfter> LCL_VAR BB14 regmask=[rsi] minReg=1> IND BB14 regmask=[r8] minReg=1> BB14 regmask=[r8] minReg=1 last> STORE_LCL_VAR BB14 regmask=[r8] minReg=1> LCL_VAR BB14 regmask=[r8] minReg=1 spillAfter> IND BB14 regmask=[r9] minReg=1> BB14 regmask=[r9] minReg=1 last> STORE_LCL_VAR BB14 regmask=[r9] minReg=1> LCL_VAR BB14 regmask=[rsi] minReg=1> IND BB14 regmask=[r10] minReg=1> BB14 regmask=[r10] minReg=1 last> STORE_LCL_VAR BB14 regmask=[r10] minReg=1 spillAfter> LCL_VAR BB14 regmask=[r9] minReg=1 spillAfter regOptional> LE BB14 regmask=[rcx] minReg=1> BB14 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB14 regmask=[rcx] minReg=1> LCL_VAR BB14 regmask=[r14] minReg=1> STORE_LCL_VAR BB14 regmask=[rdx] minReg=1> LCL_VAR BB14 regmask=[rcx] minReg=1 last regOptional> BB15 regmask=[rcx] minReg=1> LCL_VAR BB15 regmask=[rcx] minReg=1 copy fixed> BB15 regmask=[rcx] minReg=1> PUTARG_REG BB15 regmask=[rcx] minReg=1 fixed> BB15 regmask=[rdx] minReg=1> LCL_VAR BB15 regmask=[rdx] minReg=1 last fixed> BB15 regmask=[rdx] minReg=1> PUTARG_REG BB15 regmask=[rdx] minReg=1 fixed> BB15 regmask=[rcx] minReg=1> BB15 regmask=[rcx] minReg=1 last fixed> BB15 regmask=[rdx] minReg=1> BB15 regmask=[rdx] minReg=1 last fixed> BB15 regmask=[rax] minReg=1 last> BB15 regmask=[rcx] minReg=1 last> BB15 regmask=[rdx] minReg=1 last> BB15 regmask=[r8] minReg=1 last> BB15 regmask=[r9] minReg=1 last> BB15 regmask=[r10] minReg=1 last> BB15 regmask=[r11] minReg=1 last> LCL_VAR BB16 regmask=[r13] minReg=1> CAST BB16 regmask=[rdx] minReg=1> LCL_VAR BB16 regmask=[r10] minReg=1 last regOptional> BB16 regmask=[rdx] minReg=1 last> MUL BB16 regmask=[rdx] minReg=1> BB16 regmask=[rdx] minReg=1 last> RSZ BB16 regmask=[rdx] minReg=1> BB16 regmask=[rdx] minReg=1 last> ADD BB16 regmask=[rdx] minReg=1> LCL_VAR BB16 regmask=[r9] minReg=1> CAST BB16 regmask=[rcx] minReg=1> BB16 regmask=[rdx] minReg=1 last regOptional> BB16 regmask=[rcx] minReg=1 last> MUL BB16 regmask=[rdx] minReg=1> BB16 regmask=[rdx] minReg=1 last> RSZ BB16 regmask=[rdx] minReg=1> BB16 regmask=[rdx] minReg=1 last> CAST BB16 regmask=[r10] minReg=1> BB16 regmask=[r10] minReg=1 last> STORE_LCL_VAR BB16 regmask=[r10] minReg=1> BB16 regmask=[rax] minReg=1> LCL_VAR BB16 regmask=[rax] minReg=1 copy fixed> LCL_VAR BB16 regmask=[r9] minReg=1 last delay regOptional> BB16 regmask=[rax] minReg=1 last> BB16 regmask=[rdx] minReg=1 last> BB16 regmask=[rdx] minReg=1> UMOD BB16 regmask=[rdx] minReg=1 fixed> BB16 regmask=[rdx] minReg=1 last> LCL_VAR BB16 regmask=[r10] minReg=1 spillAfter regOptional> EQ BB16 regmask=[rcx] minReg=1> BB16 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB16 regmask=[rcx] minReg=1> LCL_VAR BB16 regmask=[r14] minReg=1> STORE_LCL_VAR BB16 regmask=[rdx] minReg=1> LCL_VAR BB16 regmask=[rcx] minReg=1 last regOptional> BB17 regmask=[rcx] minReg=1> LCL_VAR BB17 regmask=[rcx] minReg=1 copy fixed> BB17 regmask=[rcx] minReg=1> PUTARG_REG BB17 regmask=[rcx] minReg=1 fixed> BB17 regmask=[rdx] minReg=1> LCL_VAR BB17 regmask=[rdx] minReg=1 last fixed> BB17 regmask=[rdx] minReg=1> PUTARG_REG BB17 regmask=[rdx] minReg=1 fixed> BB17 regmask=[rcx] minReg=1> BB17 regmask=[rcx] minReg=1 last fixed> BB17 regmask=[rdx] minReg=1> BB17 regmask=[rdx] minReg=1 last fixed> BB17 regmask=[rax] minReg=1 last> BB17 regmask=[rcx] minReg=1 last> BB17 regmask=[rdx] minReg=1 last> BB17 regmask=[r8] minReg=1 last> BB17 regmask=[r9] minReg=1 last> BB17 regmask=[r10] minReg=1 last> BB17 regmask=[r11] minReg=1 last> LCL_VAR BB18 regmask=[r10] minReg=1> LCL_VAR BB18 regmask=[r8] minReg=1> LCL_VAR BB18 regmask=[r10] minReg=1 last> CAST BB18 regmask=[rcx] minReg=1> LCL_VAR BB18 regmask=[r8] minReg=1 last> BB18 regmask=[rcx] minReg=1 last> LEA BB18 regmask=[rax] minReg=1> BB18 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB18 regmask=[rax] minReg=1> LCL_VAR BB18 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB18 regmask=[rax] minReg=1> LCL_VAR BB18 regmask=[rax] minReg=1 spillAfter> IND BB18 regmask=[r8] minReg=1> BB18 regmask=[r8] minReg=1 last> ADD BB18 regmask=[r8] minReg=1> BB18 regmask=[r8] minReg=1 last> STORE_LCL_VAR BB18 regmask=[r8] minReg=1 spillAfter> LCL_VAR BB18 regmask=[r12] minReg=1 regOptional> LCL_VAR BB19 regmask=[rsi] minReg=1> IND BB19 regmask=[rcx] minReg=1> BB19 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB19 regmask=[rcx] minReg=1> LCL_VAR BB19 regmask=[rcx] minReg=1> IND BB19 regmask=[rdx] minReg=1> BB19 regmask=[rdx] minReg=1 last> IND BB19 regmask=[rdx] minReg=1> BB19 regmask=[rdx] minReg=1 last> IND BB19 regmask=[rdx] minReg=1> BB19 regmask=[rdx] minReg=1 last> STORE_LCL_VAR BB19 regmask=[rdx] minReg=1> LCL_VAR BB19 regmask=[rdx] minReg=1 regOptional> LCL_VAR BB20 regmask=[rdx] minReg=1 last> STORE_LCL_VAR BB20 regmask=[rdx] minReg=1> BB21 regmask=[rcx] minReg=1> LCL_VAR BB21 regmask=[rcx] minReg=1 last fixed> BB21 regmask=[rcx] minReg=1> PUTARG_REG BB21 regmask=[rcx] minReg=1 fixed> CNS_INT BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1 last fixed> BB21 regmask=[rdx] minReg=1> PUTARG_REG BB21 regmask=[rdx] minReg=1 fixed> BB21 regmask=[rcx] minReg=1> BB21 regmask=[rcx] minReg=1 last fixed> BB21 regmask=[rdx] minReg=1> BB21 regmask=[rdx] minReg=1 last fixed> BB21 regmask=[rax] minReg=1 last> BB21 regmask=[rcx] minReg=1 last> BB21 regmask=[rdx] minReg=1 last> BB21 regmask=[r8] minReg=1 last> BB21 regmask=[r9] minReg=1 last> BB21 regmask=[r10] minReg=1 last> BB21 regmask=[r11] minReg=1 last> BB21 regmask=[rax] minReg=1> CALL BB21 regmask=[rax] minReg=1 fixed> BB21 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB21 regmask=[rdx] minReg=1> BB22 regmask=[rcx] minReg=1> LCL_VAR BB22 regmask=[rcx] minReg=1 last copy fixed> BB22 regmask=[rcx] minReg=1> PUTARG_REG BB22 regmask=[rcx] minReg=1 fixed> BB22 regmask=[rcx] minReg=1> BB22 regmask=[rcx] minReg=1 last fixed> BB22 regmask=[rax] minReg=1 last> BB22 regmask=[rcx] minReg=1 last> BB22 regmask=[rdx] minReg=1 last> BB22 regmask=[r8] minReg=1 last> BB22 regmask=[r9] minReg=1 last> BB22 regmask=[r10] minReg=1 last> BB22 regmask=[r11] minReg=1 last> BB22 regmask=[rax] minReg=1> CALL BB22 regmask=[rax] minReg=1 fixed> BB22 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB22 regmask=[rax] minReg=1> LCL_VAR BB23 regmask=[r15] minReg=1> IND BB23 regmask=[r9] minReg=1> BB23 regmask=[r9] minReg=1 last> STORE_LCL_VAR BB23 regmask=[r9] minReg=1> LCL_VAR BB23 regmask=[r9] minReg=1 spillAfter regOptional> LCL_VAR BB23 regmask=[r10] minReg=1 reload> LCL_VAR BB24 regmask=[r10] minReg=1 last> CAST BB24 regmask=[rdx] minReg=1> BB24 regmask=[rdx] minReg=1 last> MUL BB24 regmask=[rdx] minReg=1> BB24 regmask=[rdx] minReg=1 last> STORE_LCL_VAR BB24 regmask=[rdx] minReg=1> LCL_VAR BB24 regmask=[r15] minReg=1> LCL_VAR BB24 regmask=[rdx] minReg=1> LEA BB24 regmask=[r11] minReg=1> BB24 regmask=[r11] minReg=1 last> STORE_LCL_VAR BB24 regmask=[r11] minReg=1> LCL_VAR BB24 regmask=[r11] minReg=1 spillAfter> LCL_VAR BB24 regmask=[r13] minReg=1> LCL_VAR BB25 regmask=[r15] minReg=1> LCL_VAR BB25 regmask=[rdx] minReg=1 last> IND BB25 regmask=[rdx] minReg=1> BB25 regmask=[rdx] minReg=1> BB25 regmask=[rdx] minReg=1 last fixed> BB25 regmask=[rdx] minReg=1> PUTARG_REG BB25 regmask=[rdx] minReg=1 fixed> BB25 regmask=[rcx] minReg=1> LCL_VAR BB25 regmask=[rcx] minReg=1 copy fixed> BB25 regmask=[rcx] minReg=1> PUTARG_REG BB25 regmask=[rcx] minReg=1 fixed> BB25 regmask=[r8] minReg=1> LCL_VAR BB25 regmask=[r8] minReg=1 copy fixed> BB25 regmask=[r8] minReg=1> PUTARG_REG BB25 regmask=[r8] minReg=1 fixed> LCL_VAR BB25 regmask=[rax] minReg=1 spillAfter> IND BB25 regmask=[r10] minReg=1> BB25 regmask=[r10] minReg=1 last> IND BB25 regmask=[r10] minReg=1> BB25 regmask=[rdx] minReg=1> BB25 regmask=[rdx] minReg=1 last fixed> BB25 regmask=[rcx] minReg=1> BB25 regmask=[rcx] minReg=1 last fixed> BB25 regmask=[r8] minReg=1> BB25 regmask=[r8] minReg=1 last fixed> BB25 regmask=[r10] minReg=1 last> BB25 regmask=[rax] minReg=1 last> BB25 regmask=[rcx] minReg=1 last> BB25 regmask=[rdx] minReg=1 last> BB25 regmask=[r8] minReg=1 last> BB25 regmask=[r9] minReg=1 last> BB25 regmask=[r10] minReg=1 last> BB25 regmask=[r11] minReg=1 last> BB25 regmask=[rax] minReg=1> CALL BB25 regmask=[rax] minReg=1 fixed> BB25 regmask=[rax] minReg=1 last regOptional> LCL_VAR BB26 regmask=[r11] minReg=1 last> IND BB26 regmask=[r10] minReg=1> BB26 regmask=[r10] minReg=1 last> STORE_LCL_VAR BB26 regmask=[r8] minReg=1> LCL_VAR BB26 regmask=[r11] minReg=1 last reload> ADD BB26 regmask=[r11] minReg=1> BB26 regmask=[r11] minReg=1 last> STORE_LCL_VAR BB26 regmask=[r11] minReg=1> LCL_VAR BB26 regmask=[r9] minReg=1 last regOptional> LCL_VAR BB26 regmask=[r11] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> BB27 regmask=[] minReg=1 regOptional> LCL_VAR BB28 regmask=[rbx] minReg=1 regOptional> LCL_VAR BB29 regmask=[r11] minReg=1 last> LEA BB29 regmask=[rcx] minReg=1> BB29 regmask=[rcx] minReg=1> BB29 regmask=[rcx] minReg=1 last fixed> BB29 regmask=[rdx] minReg=1> LCL_VAR BB29 regmask=[rdx] minReg=1 last copy fixed> BB29 regmask=[rax] minReg=1 last> BB29 regmask=[rcx] minReg=1 last> BB29 regmask=[rdx] minReg=1 last> BB29 regmask=[r8] minReg=1 last> BB29 regmask=[r9] minReg=1 last> BB29 regmask=[r10] minReg=1 last> BB29 regmask=[r11] minReg=1 last> BB29 regmask=[mm0] minReg=1 last> BB29 regmask=[mm1] minReg=1 last> BB29 regmask=[mm2] minReg=1 last> BB29 regmask=[mm3] minReg=1 last> BB29 regmask=[mm4] minReg=1 last> BB29 regmask=[mm5] minReg=1 last> LCL_VAR BB30 regmask=[rbx] minReg=1 last regOptional> CNS_INT BB31 regmask=[rax] minReg=1> BB31 regmask=[rax] minReg=1> BB31 regmask=[rax] minReg=1 last fixed> LCL_VAR BB32 regmask=[r15] minReg=1 outOfOrder> IND BB32 regmask=[r9] minReg=1> BB32 regmask=[r9] minReg=1 last> STORE_LCL_VAR BB32 regmask=[r9] minReg=1> LCL_VAR BB32 regmask=[r9] minReg=1 spillAfter regOptional> LCL_VAR BB32 regmask=[r8] minReg=1 outOfOrder> LCL_VAR BB33 regmask=[r8] minReg=1 last> CAST BB33 regmask=[rcx] minReg=1> BB33 regmask=[rcx] minReg=1 last> MUL BB33 regmask=[rcx] minReg=1> BB33 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB33 regmask=[rcx] minReg=1> LCL_VAR BB33 regmask=[r15] minReg=1> LCL_VAR BB33 regmask=[rcx] minReg=1> LEA BB33 regmask=[r8] minReg=1> BB33 regmask=[r8] minReg=1 last> STORE_LCL_VAR BB33 regmask=[r8] minReg=1> LCL_VAR BB33 regmask=[r8] minReg=1 spillAfter> LCL_VAR BB33 regmask=[r13] minReg=1 outOfOrder> LCL_VAR BB34 regmask=[r15] minReg=1> LCL_VAR BB34 regmask=[rcx] minReg=1 last> IND BB34 regmask=[r10] minReg=1> BB34 regmask=[r10] minReg=1 last> STORE_LCL_VAR BB34 regmask=[r10] minReg=1 spillAfter> LCL_VAR BB34 regmask=[rsi] minReg=1> IND BB34 regmask=[rcx] minReg=1> BB34 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB34 regmask=[rcx] minReg=1> LCL_VAR BB34 regmask=[rcx] minReg=1> IND BB34 regmask=[rdx] minReg=1> BB34 regmask=[rdx] minReg=1 last> IND BB34 regmask=[rdx] minReg=1> BB34 regmask=[rdx] minReg=1 last> IND BB34 regmask=[r11] minReg=1> BB34 regmask=[r11] minReg=1 last> STORE_LCL_VAR BB34 regmask=[r11] minReg=1> LCL_VAR BB34 regmask=[r11] minReg=1 regOptional> LCL_VAR BB35 regmask=[r11] minReg=1 last> STORE_LCL_VAR BB35 regmask=[r11] minReg=1> BB36 regmask=[rcx] minReg=1> LCL_VAR BB36 regmask=[rcx] minReg=1 last fixed> BB36 regmask=[rcx] minReg=1> PUTARG_REG BB36 regmask=[rcx] minReg=1 fixed> CNS_INT BB36 regmask=[rdx] minReg=1> BB36 regmask=[rdx] minReg=1> BB36 regmask=[rdx] minReg=1 last fixed> BB36 regmask=[rdx] minReg=1> PUTARG_REG BB36 regmask=[rdx] minReg=1 fixed> BB36 regmask=[rcx] minReg=1> BB36 regmask=[rcx] minReg=1 last fixed> BB36 regmask=[rdx] minReg=1> BB36 regmask=[rdx] minReg=1 last fixed> BB36 regmask=[rax] minReg=1 last> BB36 regmask=[rcx] minReg=1 last> BB36 regmask=[rdx] minReg=1 last> BB36 regmask=[r8] minReg=1 last> BB36 regmask=[r9] minReg=1 last> BB36 regmask=[r10] minReg=1 last> BB36 regmask=[r11] minReg=1 last> BB36 regmask=[rax] minReg=1> CALL BB36 regmask=[rax] minReg=1 fixed> BB36 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB36 regmask=[r11] minReg=1> BB37 regmask=[rcx] minReg=1> LCL_VAR BB37 regmask=[rcx] minReg=1 copy fixed outOfOrder> BB37 regmask=[rcx] minReg=1> PUTARG_REG BB37 regmask=[rcx] minReg=1 fixed> BB37 regmask=[r11] minReg=1> LCL_VAR BB37 regmask=[r11] minReg=1 fixed> BB37 regmask=[r11] minReg=1> PUTARG_REG BB37 regmask=[r11] minReg=1 fixed> BB37 regmask=[rdx] minReg=1> LCL_VAR BB37 regmask=[rdx] minReg=1 last copy fixed> BB37 regmask=[rdx] minReg=1> PUTARG_REG BB37 regmask=[rdx] minReg=1 fixed> BB37 regmask=[r8] minReg=1> LCL_VAR BB37 regmask=[r8] minReg=1 copy fixed> BB37 regmask=[r8] minReg=1> PUTARG_REG BB37 regmask=[r8] minReg=1 fixed> BB37 regmask=[rcx] minReg=1> BB37 regmask=[rcx] minReg=1 last fixed> BB37 regmask=[r11] minReg=1> BB37 regmask=[r11] minReg=1 last fixed> BB37 regmask=[rdx] minReg=1> BB37 regmask=[rdx] minReg=1 last fixed> BB37 regmask=[r8] minReg=1> BB37 regmask=[r8] minReg=1 last fixed> LCL_VAR BB37 regmask=[r11] minReg=1 last> BB37 regmask=[rax] minReg=1 last> BB37 regmask=[rcx] minReg=1 last> BB37 regmask=[rdx] minReg=1 last> BB37 regmask=[r8] minReg=1 last> BB37 regmask=[r9] minReg=1 last> BB37 regmask=[r10] minReg=1 last> BB37 regmask=[r11] minReg=1 last> BB37 regmask=[rax] minReg=1> CALL BB37 regmask=[rax] minReg=1 fixed> BB37 regmask=[rax] minReg=1 last regOptional> LCL_VAR BB38 regmask=[rbx] minReg=1 regOptional> LCL_VAR BB39 regmask=[r15] minReg=1 last reload> LEA BB39 regmask=[rcx] minReg=1> BB39 regmask=[rcx] minReg=1> BB39 regmask=[rcx] minReg=1 last fixed> BB39 regmask=[rdx] minReg=1> LCL_VAR BB39 regmask=[rdx] minReg=1 last copy fixed> BB39 regmask=[rax] minReg=1 last> BB39 regmask=[rcx] minReg=1 last> BB39 regmask=[rdx] minReg=1 last> BB39 regmask=[r8] minReg=1 last> BB39 regmask=[r9] minReg=1 last> BB39 regmask=[r10] minReg=1 last> BB39 regmask=[r11] minReg=1 last> BB39 regmask=[mm0] minReg=1 last> BB39 regmask=[mm1] minReg=1 last> BB39 regmask=[mm2] minReg=1 last> BB39 regmask=[mm3] minReg=1 last> BB39 regmask=[mm4] minReg=1 last> BB39 regmask=[mm5] minReg=1 last> LCL_VAR BB40 regmask=[rbx] minReg=1 last regOptional> LCL_VAR BB42 regmask=[r8] minReg=1 last outOfOrder> IND BB42 regmask=[r8] minReg=1> BB42 regmask=[r8] minReg=1 last> STORE_LCL_VAR BB42 regmask=[rcx] minReg=1> LCL_VAR BB42 regmask=[r8] minReg=1 last reload> ADD BB42 regmask=[r8] minReg=1> BB42 regmask=[r8] minReg=1 last> STORE_LCL_VAR BB42 regmask=[r8] minReg=1> LCL_VAR BB42 regmask=[r9] minReg=1 last regOptional> LCL_VAR BB42 regmask=[r8] minReg=1 spillAfter> BB43 regmask=[allInt] minReg=1 regOptional> BB43 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB44 regmask=[rsi] minReg=1> LCL_VAR BB45 regmask=[rsi] minReg=1> IND BB45 regmask=[rcx] minReg=1> BB45 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB45 regmask=[rcx] minReg=1> LCL_VAR BB45 regmask=[rcx] minReg=1> STORE_LCL_VAR BB45 regmask=[rbx] minReg=1> LCL_VAR BB45 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB45 regmask=[rcx] minReg=1> LCL_VAR BB45 regmask=[rcx] minReg=1> LCL_VAR BB45 regmask=[r9] minReg=1 spillAfter regOptional> LCL_VAR BB45 regmask=[rcx] minReg=1 last> CAST BB45 regmask=[rcx] minReg=1> BB45 regmask=[rcx] minReg=1 last> MUL BB45 regmask=[rcx] minReg=1> LCL_VAR BB45 regmask=[r15] minReg=1> BB45 regmask=[rcx] minReg=1 last> IND BB45 regmask=[rcx] minReg=1> BB45 regmask=[rcx] minReg=1 last> NEG BB45 regmask=[rcx] minReg=1> BB45 regmask=[rcx] minReg=1 last> ADD BB45 regmask=[rcx] minReg=1> BB45 regmask=[rcx] minReg=1 last regOptional> GE BB45 regmask=[rcx] minReg=1> BB45 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB45 regmask=[rcx] minReg=1> LCL_VAR BB45 regmask=[r14] minReg=1 last outOfOrder> STORE_LCL_VAR BB45 regmask=[rdx] minReg=1> LCL_VAR BB45 regmask=[rcx] minReg=1 last regOptional> CNS_INT BB46 regmask=[rcx] minReg=1> BB46 regmask=[rcx] minReg=1 last> IND BB46 regmask=[rcx] minReg=1> BB46 regmask=[rcx] minReg=1> BB46 regmask=[rcx] minReg=1 last fixed> BB46 regmask=[rcx] minReg=1> PUTARG_REG BB46 regmask=[rcx] minReg=1 fixed> BB46 regmask=[rdx] minReg=1> LCL_VAR BB46 regmask=[rdx] minReg=1 last fixed> BB46 regmask=[rdx] minReg=1> PUTARG_REG BB46 regmask=[rdx] minReg=1 fixed> BB46 regmask=[rcx] minReg=1> BB46 regmask=[rcx] minReg=1 last fixed> BB46 regmask=[rdx] minReg=1> BB46 regmask=[rdx] minReg=1 last fixed> BB46 regmask=[rax] minReg=1 last> BB46 regmask=[rcx] minReg=1 last> BB46 regmask=[rdx] minReg=1 last> BB46 regmask=[r8] minReg=1 last> BB46 regmask=[r9] minReg=1 last> BB46 regmask=[r10] minReg=1 last> BB46 regmask=[r11] minReg=1 last> LCL_VAR BB47 regmask=[rsi] minReg=1> IND BB47 regmask=[rcx] minReg=1> BB47 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB47 regmask=[rcx] minReg=1> LCL_VAR BB47 regmask=[rcx] minReg=1> LCL_VAR BB47 regmask=[r9] minReg=1 last regOptional> LCL_VAR BB47 regmask=[rcx] minReg=1 last> CAST BB47 regmask=[r9] minReg=1> BB47 regmask=[r9] minReg=1 last> MUL BB47 regmask=[rcx] minReg=1> LCL_VAR BB47 regmask=[r15] minReg=1> BB47 regmask=[rcx] minReg=1 last> IND BB47 regmask=[rcx] minReg=1> BB47 regmask=[rcx] minReg=1 last> NEG BB47 regmask=[rcx] minReg=1> BB47 regmask=[rcx] minReg=1 last> ADD BB47 regmask=[rcx] minReg=1> LCL_VAR BB47 regmask=[rsi] minReg=1> BB47 regmask=[rcx] minReg=1 last> LCL_VAR BB47 regmask=[rsi] minReg=1> LCL_VAR BB48 regmask=[rsi] minReg=1> IND BB48 regmask=[rcx] minReg=1> BB48 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB48 regmask=[rcx] minReg=1> LCL_VAR BB48 regmask=[rcx] minReg=1> STORE_LCL_VAR BB48 regmask=[rbx] minReg=1> LCL_VAR BB48 regmask=[r9] minReg=1 last regOptional> LCL_VAR BB48 regmask=[rbx] minReg=1> BB49 regmask=[rcx] minReg=1> LCL_VAR BB49 regmask=[rcx] minReg=1 last fixed> BB49 regmask=[rcx] minReg=1> PUTARG_REG BB49 regmask=[rcx] minReg=1 fixed> BB49 regmask=[rcx] minReg=1> BB49 regmask=[rcx] minReg=1 last fixed> BB49 regmask=[rax] minReg=1 last> BB49 regmask=[rcx] minReg=1 last> BB49 regmask=[rdx] minReg=1 last> BB49 regmask=[r8] minReg=1 last> BB49 regmask=[r9] minReg=1 last> BB49 regmask=[r10] minReg=1 last> BB49 regmask=[r11] minReg=1 last> BB49 regmask=[rax] minReg=1> CALL BB49 regmask=[rax] minReg=1 fixed> BB49 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB49 regmask=[rdx] minReg=1> BB49 regmask=[rdx] minReg=1> LCL_VAR BB49 regmask=[rdx] minReg=1 last fixed> BB49 regmask=[rdx] minReg=1> PUTARG_REG BB49 regmask=[rdx] minReg=1 fixed> BB49 regmask=[rcx] minReg=1> LCL_VAR BB49 regmask=[rcx] minReg=1 copy fixed> BB49 regmask=[rcx] minReg=1> PUTARG_REG BB49 regmask=[rcx] minReg=1 fixed> CNS_INT BB49 regmask=[r8] minReg=1> BB49 regmask=[r8] minReg=1> BB49 regmask=[r8] minReg=1 last fixed> BB49 regmask=[r8] minReg=1> PUTARG_REG BB49 regmask=[r8] minReg=1 fixed> BB49 regmask=[rdx] minReg=1> BB49 regmask=[rdx] minReg=1 last fixed> BB49 regmask=[rcx] minReg=1> BB49 regmask=[rcx] minReg=1 last fixed> BB49 regmask=[r8] minReg=1> BB49 regmask=[r8] minReg=1 last fixed> BB49 regmask=[rax] minReg=1 last> BB49 regmask=[rcx] minReg=1 last> BB49 regmask=[rdx] minReg=1 last> BB49 regmask=[r8] minReg=1 last> BB49 regmask=[r9] minReg=1 last> BB49 regmask=[r10] minReg=1 last> BB49 regmask=[r11] minReg=1 last> LCL_VAR BB49 regmask=[rsi] minReg=1> IND BB49 regmask=[r15] minReg=1> BB49 regmask=[r15] minReg=1 last> STORE_LCL_VAR BB49 regmask=[r15] minReg=1> LCL_VAR BB49 regmask=[r15] minReg=1> IND BB49 regmask=[rax] minReg=1> BB49 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB49 regmask=[rax] minReg=1> LCL_VAR BB49 regmask=[rax] minReg=1 spillAfter> STORE_LCL_VAR BB49 regmask=[r8] minReg=1> LCL_VAR BB49 regmask=[rsi] minReg=1> IND BB49 regmask=[r9] minReg=1> BB49 regmask=[r9] minReg=1 last> STORE_LCL_VAR BB49 regmask=[r9] minReg=1 spillAfter> LCL_VAR BB49 regmask=[r8] minReg=1 spillAfter regOptional> LE BB49 regmask=[rcx] minReg=1> BB49 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB49 regmask=[rcx] minReg=1> LCL_VAR BB49 regmask=[r14] minReg=1> STORE_LCL_VAR BB49 regmask=[rdx] minReg=1> LCL_VAR BB49 regmask=[rcx] minReg=1 last regOptional> BB50 regmask=[rcx] minReg=1> LCL_VAR BB50 regmask=[rcx] minReg=1 copy fixed> BB50 regmask=[rcx] minReg=1> PUTARG_REG BB50 regmask=[rcx] minReg=1 fixed> BB50 regmask=[rdx] minReg=1> LCL_VAR BB50 regmask=[rdx] minReg=1 last fixed> BB50 regmask=[rdx] minReg=1> PUTARG_REG BB50 regmask=[rdx] minReg=1 fixed> BB50 regmask=[rcx] minReg=1> BB50 regmask=[rcx] minReg=1 last fixed> BB50 regmask=[rdx] minReg=1> BB50 regmask=[rdx] minReg=1 last fixed> BB50 regmask=[rax] minReg=1 last> BB50 regmask=[rcx] minReg=1 last> BB50 regmask=[rdx] minReg=1 last> BB50 regmask=[r8] minReg=1 last> BB50 regmask=[r9] minReg=1 last> BB50 regmask=[r10] minReg=1 last> BB50 regmask=[r11] minReg=1 last> LCL_VAR BB51 regmask=[r13] minReg=1> CAST BB51 regmask=[rdx] minReg=1> LCL_VAR BB51 regmask=[r9] minReg=1 last regOptional> BB51 regmask=[rdx] minReg=1 last> MUL BB51 regmask=[rdx] minReg=1> BB51 regmask=[rdx] minReg=1 last> RSZ BB51 regmask=[rdx] minReg=1> BB51 regmask=[rdx] minReg=1 last> ADD BB51 regmask=[rdx] minReg=1> LCL_VAR BB51 regmask=[r8] minReg=1> CAST BB51 regmask=[rcx] minReg=1> BB51 regmask=[rdx] minReg=1 last regOptional> BB51 regmask=[rcx] minReg=1 last> MUL BB51 regmask=[rdx] minReg=1> BB51 regmask=[rdx] minReg=1 last> RSZ BB51 regmask=[rdx] minReg=1> BB51 regmask=[rdx] minReg=1 last> CAST BB51 regmask=[r9] minReg=1> BB51 regmask=[r9] minReg=1 last> STORE_LCL_VAR BB51 regmask=[r9] minReg=1> BB51 regmask=[rax] minReg=1> LCL_VAR BB51 regmask=[rax] minReg=1 copy fixed> LCL_VAR BB51 regmask=[r8] minReg=1 last delay regOptional> BB51 regmask=[rax] minReg=1 last> BB51 regmask=[rdx] minReg=1 last> BB51 regmask=[rdx] minReg=1> UMOD BB51 regmask=[rdx] minReg=1 fixed> BB51 regmask=[rdx] minReg=1 last> LCL_VAR BB51 regmask=[r9] minReg=1 spillAfter regOptional> EQ BB51 regmask=[rcx] minReg=1> BB51 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB51 regmask=[rcx] minReg=1> LCL_VAR BB51 regmask=[r14] minReg=1 last> STORE_LCL_VAR BB51 regmask=[rdx] minReg=1> LCL_VAR BB51 regmask=[rcx] minReg=1 last regOptional> BB52 regmask=[rcx] minReg=1> LCL_VAR BB52 regmask=[rcx] minReg=1 copy fixed> BB52 regmask=[rcx] minReg=1> PUTARG_REG BB52 regmask=[rcx] minReg=1 fixed> BB52 regmask=[rdx] minReg=1> LCL_VAR BB52 regmask=[rdx] minReg=1 last fixed> BB52 regmask=[rdx] minReg=1> PUTARG_REG BB52 regmask=[rdx] minReg=1 fixed> BB52 regmask=[rcx] minReg=1> BB52 regmask=[rcx] minReg=1 last fixed> BB52 regmask=[rdx] minReg=1> BB52 regmask=[rdx] minReg=1 last fixed> BB52 regmask=[rax] minReg=1 last> BB52 regmask=[rcx] minReg=1 last> BB52 regmask=[rdx] minReg=1 last> BB52 regmask=[r8] minReg=1 last> BB52 regmask=[r9] minReg=1 last> BB52 regmask=[r10] minReg=1 last> BB52 regmask=[r11] minReg=1 last> LCL_VAR BB53 regmask=[r9] minReg=1> LCL_VAR BB53 regmask=[] minReg=1 last regOptional> LCL_VAR BB53 regmask=[r9] minReg=1 last> CAST BB53 regmask=[rdx] minReg=1> LCL_VAR BB53 regmask=[r15] minReg=1 last> BB53 regmask=[rdx] minReg=1 last> LEA BB53 regmask=[rax] minReg=1> BB53 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB53 regmask=[rax] minReg=1> LCL_VAR BB53 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB53 regmask=[r14] minReg=1 outOfOrder> LCL_VAR BB54 regmask=[rbx] minReg=1 last> STORE_LCL_VAR BB54 regmask=[rbx] minReg=1> LCL_VAR BB54 regmask=[rbx] minReg=1> ADD BB54 regmask=[rdx] minReg=1> LCL_VAR BB54 regmask=[rsi] minReg=1> BB54 regmask=[rdx] minReg=1 last> LCL_VAR BB54 regmask=[rsi] minReg=1> IND BB54 regmask=[r15] minReg=1> BB54 regmask=[r15] minReg=1 last> STORE_LCL_VAR BB54 regmask=[r15] minReg=1> LCL_VAR BB55 regmask=[rbx] minReg=1> LCL_VAR BB55 regmask=[r15] minReg=1> LCL_VAR BB55 regmask=[rbx] minReg=1> CAST BB55 regmask=[rdx] minReg=1> BB55 regmask=[rdx] minReg=1 last> MUL BB55 regmask=[rdx] minReg=1> LCL_VAR BB55 regmask=[r15] minReg=1> BB55 regmask=[rdx] minReg=1 last> LEA BB55 regmask=[r14] minReg=1> BB55 regmask=[r14] minReg=1 last> STORE_LCL_VAR BB55 regmask=[r14] minReg=1> LCL_VAR BB55 regmask=[r14] minReg=1> LCL_VAR BB55 regmask=[r13] minReg=1 last> LCL_VAR BB55 regmask=[rax] minReg=1 spillAfter outOfOrder> IND BB55 regmask=[rdx] minReg=1> BB55 regmask=[rdx] minReg=1 last> ADD BB55 regmask=[rdx] minReg=1> LCL_VAR BB55 regmask=[r14] minReg=1> BB55 regmask=[rdx] minReg=1 last> BB55 regmask=[rcx] minReg=1> LCL_VAR BB55 regmask=[rcx] minReg=1 copy fixed> BB55 regmask=[rdx] minReg=1> LCL_VAR BB55 regmask=[rdx] minReg=1 last copy fixed> BB55 regmask=[rax] minReg=1 last> BB55 regmask=[rcx] minReg=1 last> BB55 regmask=[rdx] minReg=1 last> BB55 regmask=[r8] minReg=1 last> BB55 regmask=[r9] minReg=1 last> BB55 regmask=[r10] minReg=1 last> BB55 regmask=[r11] minReg=1 last> BB55 regmask=[mm0] minReg=1 last> BB55 regmask=[mm1] minReg=1 last> BB55 regmask=[mm2] minReg=1 last> BB55 regmask=[mm3] minReg=1 last> BB55 regmask=[mm4] minReg=1 last> BB55 regmask=[mm5] minReg=1 last> LCL_VAR BB55 regmask=[r14] minReg=1 last> LEA BB55 regmask=[rcx] minReg=1> BB55 regmask=[rcx] minReg=1> BB55 regmask=[rcx] minReg=1 last fixed> BB55 regmask=[rdx] minReg=1> LCL_VAR BB55 regmask=[rdx] minReg=1 last copy fixed> BB55 regmask=[rax] minReg=1 last> BB55 regmask=[rcx] minReg=1 last> BB55 regmask=[rdx] minReg=1 last> BB55 regmask=[r8] minReg=1 last> BB55 regmask=[r9] minReg=1 last> BB55 regmask=[r10] minReg=1 last> BB55 regmask=[r11] minReg=1 last> BB55 regmask=[mm0] minReg=1 last> BB55 regmask=[mm1] minReg=1 last> BB55 regmask=[mm2] minReg=1 last> BB55 regmask=[mm3] minReg=1 last> BB55 regmask=[mm4] minReg=1 last> BB55 regmask=[mm5] minReg=1 last> LCL_VAR BB55 regmask=[rbx] minReg=1 last> ADD BB55 regmask=[rbx] minReg=1> LCL_VAR BB55 regmask=[r14] minReg=1 last reload> BB55 regmask=[rbx] minReg=1 last> LCL_VAR BB55 regmask=[rsi] minReg=1> LCL_VAR BB55 regmask=[] minReg=1 last regOptional> BB56 regmask=[rdx] minReg=1> LCL_VAR BB56 regmask=[rdx] minReg=1 last copy fixed> BB56 regmask=[rdx] minReg=1> PUTARG_REG BB56 regmask=[rdx] minReg=1 fixed> CNS_INT BB56 regmask=[rcx] minReg=1> BB56 regmask=[rcx] minReg=1> BB56 regmask=[rcx] minReg=1 last fixed> BB56 regmask=[rcx] minReg=1> PUTARG_REG BB56 regmask=[rcx] minReg=1 fixed> BB56 regmask=[rdx] minReg=1> BB56 regmask=[rdx] minReg=1 last fixed> BB56 regmask=[rcx] minReg=1> BB56 regmask=[rcx] minReg=1 last fixed> BB56 regmask=[rax] minReg=1 last> BB56 regmask=[rcx] minReg=1 last> BB56 regmask=[rdx] minReg=1 last> BB56 regmask=[r8] minReg=1 last> BB56 regmask=[r9] minReg=1 last> BB56 regmask=[r10] minReg=1 last> BB56 regmask=[r11] minReg=1 last> BB56 regmask=[rax] minReg=1> CALL BB56 regmask=[rax] minReg=1 fixed> BB56 regmask=[rax] minReg=1 last regOptional> LCL_VAR BB57 regmask=[r15] minReg=1 last> IND BB57 regmask=[rdx] minReg=1> BB57 regmask=[rdx] minReg=1> BB57 regmask=[rdx] minReg=1 last fixed> BB57 regmask=[rdx] minReg=1> PUTARG_REG BB57 regmask=[rdx] minReg=1 fixed> BB57 regmask=[rcx] minReg=1> LCL_VAR BB57 regmask=[rcx] minReg=1 copy fixed> BB57 regmask=[rcx] minReg=1> PUTARG_REG BB57 regmask=[rcx] minReg=1 fixed> CNS_INT BB57 regmask=[r8] minReg=1> BB57 regmask=[r8] minReg=1> BB57 regmask=[r8] minReg=1 last fixed> BB57 regmask=[r8] minReg=1> PUTARG_REG BB57 regmask=[r8] minReg=1 fixed> BB57 regmask=[rdx] minReg=1> BB57 regmask=[rdx] minReg=1 last fixed> BB57 regmask=[rcx] minReg=1> BB57 regmask=[rcx] minReg=1 last fixed> BB57 regmask=[r8] minReg=1> BB57 regmask=[r8] minReg=1 last fixed> BB57 regmask=[rax] minReg=1 last> BB57 regmask=[rcx] minReg=1 last> BB57 regmask=[rdx] minReg=1 last> BB57 regmask=[r8] minReg=1 last> BB57 regmask=[r9] minReg=1 last> BB57 regmask=[r10] minReg=1 last> BB57 regmask=[r11] minReg=1 last> CNS_INT BB58 regmask=[rax] minReg=1> BB58 regmask=[rax] minReg=1> BB58 regmask=[rax] minReg=1 last fixed> CNS_INT BB59 regmask=[rcx] minReg=1> BB59 regmask=[rcx] minReg=1> BB59 regmask=[rcx] minReg=1 last fixed> BB59 regmask=[rcx] minReg=1> PUTARG_REG BB59 regmask=[rcx] minReg=1 fixed> BB59 regmask=[rcx] minReg=1> BB59 regmask=[rcx] minReg=1 last fixed> BB59 regmask=[rax] minReg=1 last> BB59 regmask=[rcx] minReg=1 last> BB59 regmask=[rdx] minReg=1 last> BB59 regmask=[r8] minReg=1 last> BB59 regmask=[r9] minReg=1 last> BB59 regmask=[r10] minReg=1 last> BB59 regmask=[r11] minReg=1 last> LCL_VAR BB60 regmask=[rsi] minReg=1> IND BB60 regmask=[rcx] minReg=1> BB60 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB60 regmask=[rcx] minReg=1> LCL_VAR BB60 regmask=[rcx] minReg=1> IND BB60 regmask=[rdx] minReg=1> BB60 regmask=[rdx] minReg=1 last> IND BB60 regmask=[rdx] minReg=1> BB60 regmask=[rdx] minReg=1 last> LCL_VAR BB61 regmask=[rcx] minReg=1 last> IND BB61 regmask=[rcx] minReg=1> BB61 regmask=[rcx] minReg=1 last> IND BB61 regmask=[rcx] minReg=1> BB61 regmask=[rcx] minReg=1 last> IND BB61 regmask=[rcx] minReg=1> BB61 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB61 regmask=[rcx] minReg=1> BB62 regmask=[rcx] minReg=1> LCL_VAR BB62 regmask=[rcx] minReg=1 last fixed> BB62 regmask=[rcx] minReg=1> PUTARG_REG BB62 regmask=[rcx] minReg=1 fixed> CNS_INT BB62 regmask=[rdx] minReg=1> BB62 regmask=[rdx] minReg=1> BB62 regmask=[rdx] minReg=1 last fixed> BB62 regmask=[rdx] minReg=1> PUTARG_REG BB62 regmask=[rdx] minReg=1 fixed> BB62 regmask=[rcx] minReg=1> BB62 regmask=[rcx] minReg=1 last fixed> BB62 regmask=[rdx] minReg=1> BB62 regmask=[rdx] minReg=1 last fixed> BB62 regmask=[rax] minReg=1 last> BB62 regmask=[rcx] minReg=1 last> BB62 regmask=[rdx] minReg=1 last> BB62 regmask=[r8] minReg=1 last> BB62 regmask=[r9] minReg=1 last> BB62 regmask=[r10] minReg=1 last> BB62 regmask=[r11] minReg=1 last> BB62 regmask=[rax] minReg=1> CALL BB62 regmask=[rax] minReg=1 fixed> BB62 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB62 regmask=[rcx] minReg=1> BB63 regmask=[rcx] minReg=1> LCL_VAR BB63 regmask=[rcx] minReg=1 last fixed> BB63 regmask=[rcx] minReg=1> PUTARG_REG BB63 regmask=[rcx] minReg=1 fixed> BB63 regmask=[rdx] minReg=1> LCL_VAR BB63 regmask=[rdx] minReg=1 last copy fixed> BB63 regmask=[rdx] minReg=1> PUTARG_REG BB63 regmask=[rdx] minReg=1 fixed> BB63 regmask=[rcx] minReg=1> BB63 regmask=[rcx] minReg=1 last fixed> BB63 regmask=[rdx] minReg=1> BB63 regmask=[rdx] minReg=1 last fixed> BB63 regmask=[rax] minReg=1 last> BB63 regmask=[rcx] minReg=1 last> BB63 regmask=[rdx] minReg=1 last> BB63 regmask=[r8] minReg=1 last> BB63 regmask=[r9] minReg=1 last> BB63 regmask=[r10] minReg=1 last> BB63 regmask=[r11] minReg=1 last> LCL_VAR BB64 regmask=[rsi] minReg=1> IND BB64 regmask=[rcx] minReg=1> BB64 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB64 regmask=[rcx] minReg=1> LCL_VAR BB64 regmask=[rcx] minReg=1> IND BB64 regmask=[rdx] minReg=1> BB64 regmask=[rdx] minReg=1 last> IND BB64 regmask=[rdx] minReg=1> BB64 regmask=[rdx] minReg=1 last> LCL_VAR BB65 regmask=[rcx] minReg=1 last> IND BB65 regmask=[rcx] minReg=1> BB65 regmask=[rcx] minReg=1 last> IND BB65 regmask=[rcx] minReg=1> BB65 regmask=[rcx] minReg=1 last> IND BB65 regmask=[rcx] minReg=1> BB65 regmask=[rcx] minReg=1 last> STORE_LCL_VAR BB65 regmask=[rcx] minReg=1> BB66 regmask=[rcx] minReg=1> LCL_VAR BB66 regmask=[rcx] minReg=1 last fixed> BB66 regmask=[rcx] minReg=1> PUTARG_REG BB66 regmask=[rcx] minReg=1 fixed> CNS_INT BB66 regmask=[rdx] minReg=1> BB66 regmask=[rdx] minReg=1> BB66 regmask=[rdx] minReg=1 last fixed> BB66 regmask=[rdx] minReg=1> PUTARG_REG BB66 regmask=[rdx] minReg=1 fixed> BB66 regmask=[rcx] minReg=1> BB66 regmask=[rcx] minReg=1 last fixed> BB66 regmask=[rdx] minReg=1> BB66 regmask=[rdx] minReg=1 last fixed> BB66 regmask=[rax] minReg=1 last> BB66 regmask=[rcx] minReg=1 last> BB66 regmask=[rdx] minReg=1 last> BB66 regmask=[r8] minReg=1 last> BB66 regmask=[r9] minReg=1 last> BB66 regmask=[r10] minReg=1 last> BB66 regmask=[r11] minReg=1 last> BB66 regmask=[rax] minReg=1> CALL BB66 regmask=[rax] minReg=1 fixed> BB66 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB66 regmask=[rcx] minReg=1> BB67 regmask=[rcx] minReg=1> LCL_VAR BB67 regmask=[rcx] minReg=1 last fixed> BB67 regmask=[rcx] minReg=1> PUTARG_REG BB67 regmask=[rcx] minReg=1 fixed> BB67 regmask=[rdx] minReg=1> LCL_VAR BB67 regmask=[rdx] minReg=1 last copy fixed> BB67 regmask=[rdx] minReg=1> PUTARG_REG BB67 regmask=[rdx] minReg=1 fixed> BB67 regmask=[rcx] minReg=1> BB67 regmask=[rcx] minReg=1 last fixed> BB67 regmask=[rdx] minReg=1> BB67 regmask=[rdx] minReg=1 last fixed> BB67 regmask=[rax] minReg=1 last> BB67 regmask=[rcx] minReg=1 last> BB67 regmask=[rdx] minReg=1 last> BB67 regmask=[r8] minReg=1 last> BB67 regmask=[r9] minReg=1 last> BB67 regmask=[r10] minReg=1 last> BB67 regmask=[r11] minReg=1 last> BB68 regmask=[rax] minReg=1 last> BB68 regmask=[rcx] minReg=1 last> BB68 regmask=[rdx] minReg=1 last> BB68 regmask=[r8] minReg=1 last> BB68 regmask=[r9] minReg=1 last> BB68 regmask=[r10] minReg=1 last> BB68 regmask=[r11] minReg=1 last> BB69 regmask=[rsi] minReg=1 regOptional> BB69 regmask=[rax] minReg=1 last> BB69 regmask=[rcx] minReg=1 last> BB69 regmask=[rdx] minReg=1 last> BB69 regmask=[r8] minReg=1 last> BB69 regmask=[r9] minReg=1 last> BB69 regmask=[r10] minReg=1 last> BB69 regmask=[r11] minReg=1 last> BB69 regmask=[allInt] minReg=1 outOfOrder regOptional> BB69 regmask=[allInt] minReg=1 regOptional> VAR REFPOSITIONS AFTER ALLOCATION --- V00 (Interval 0) BB00 regmask=[rsi] minReg=1 regOptional> LCL_VAR BB02 regmask=[rsi] minReg=1> LCL_VAR BB03 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB04 regmask=[rsi] minReg=1> LCL_VAR BB06 regmask=[rsi] minReg=1> LCL_VAR BB08 regmask=[rsi] minReg=1> LCL_VAR BB09 regmask=[rsi] minReg=1> LCL_VAR BB14 regmask=[rsi] minReg=1> LCL_VAR BB14 regmask=[rsi] minReg=1> LCL_VAR BB19 regmask=[rsi] minReg=1> LCL_VAR BB34 regmask=[rsi] minReg=1> LCL_VAR BB44 regmask=[rsi] minReg=1> LCL_VAR BB45 regmask=[rsi] minReg=1> LCL_VAR BB47 regmask=[rsi] minReg=1> LCL_VAR BB47 regmask=[rsi] minReg=1> LCL_VAR BB47 regmask=[rsi] minReg=1> LCL_VAR BB48 regmask=[rsi] minReg=1> LCL_VAR BB49 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB49 regmask=[rsi] minReg=1> LCL_VAR BB49 regmask=[rsi] minReg=1> LCL_VAR BB54 regmask=[rsi] minReg=1> LCL_VAR BB54 regmask=[rsi] minReg=1> LCL_VAR BB55 regmask=[rsi] minReg=1> LCL_VAR BB57 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB60 regmask=[rsi] minReg=1> LCL_VAR BB64 regmask=[rsi] minReg=1> BB69 regmask=[rsi] minReg=1 regOptional> BB69 regmask=[allInt] minReg=1 outOfOrder regOptional> BB69 regmask=[allInt] minReg=1 regOptional> --- V01 (Interval 1) BB00 regmask=[rdi] minReg=1 regOptional> LCL_VAR BB01 regmask=[rdi] minReg=1 regOptional> LCL_VAR BB12 regmask=[rdx] minReg=1 copy fixed> LCL_VAR BB13 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB13 regmask=[rdi] minReg=1> LCL_VAR BB25 regmask=[r8] minReg=1 copy fixed> LCL_VAR BB37 regmask=[r8] minReg=1 copy fixed> LCL_VAR BB55 regmask=[rdx] minReg=1 last copy fixed> LCL_VAR BB63 regmask=[rdx] minReg=1 last copy fixed> LCL_VAR BB67 regmask=[rdx] minReg=1 last copy fixed> --- V02 (Interval 2) BB00 regmask=[rbp] minReg=1 regOptional> LCL_VAR BB29 regmask=[rdx] minReg=1 last copy fixed> LCL_VAR BB39 regmask=[rdx] minReg=1 last copy fixed> LCL_VAR BB55 regmask=[rdx] minReg=1 last copy fixed> --- V03 (Interval 3) BB00 regmask=[rbx] minReg=1 regOptional> LCL_VAR BB28 regmask=[rbx] minReg=1 regOptional> LCL_VAR BB30 regmask=[rbx] minReg=1 last regOptional> LCL_VAR BB38 regmask=[rbx] minReg=1 regOptional> LCL_VAR BB40 regmask=[rbx] minReg=1 last regOptional> BB43 regmask=[allInt] minReg=1 regOptional> --- V04 (Interval 4) STORE_LCL_VAR BB06 regmask=[r15] minReg=1> LCL_VAR BB06 regmask=[r15] minReg=1 regOptional> LCL_VAR BB23 regmask=[r15] minReg=1> LCL_VAR BB24 regmask=[r15] minReg=1> LCL_VAR BB25 regmask=[r15] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB32 regmask=[r15] minReg=1 outOfOrder> LCL_VAR BB33 regmask=[r15] minReg=1> LCL_VAR BB34 regmask=[r15] minReg=1> LCL_VAR BB45 regmask=[r15] minReg=1> LCL_VAR BB47 regmask=[r15] minReg=1> STORE_LCL_VAR BB54 regmask=[r15] minReg=1> LCL_VAR BB55 regmask=[r15] minReg=1> LCL_VAR BB55 regmask=[r15] minReg=1> LCL_VAR BB57 regmask=[r15] minReg=1 last> --- V05 (Interval 5) STORE_LCL_VAR BB08 regmask=[r12] minReg=1> LCL_VAR BB08 regmask=[r12] minReg=1 regOptional> LCL_VAR BB12 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB18 regmask=[r12] minReg=1 regOptional> BB27 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB37 regmask=[rcx] minReg=1 copy fixed outOfOrder> LCL_VAR BB56 regmask=[rdx] minReg=1 last copy fixed> --- V06 (Interval 6) STORE_LCL_VAR BB14 regmask=[r13] minReg=1> LCL_VAR BB16 regmask=[r13] minReg=1> LCL_VAR BB16 regmask=[rax] minReg=1 copy fixed> LCL_VAR BB24 regmask=[r13] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB33 regmask=[r13] minReg=1 outOfOrder> LCL_VAR BB51 regmask=[r13] minReg=1> LCL_VAR BB51 regmask=[rax] minReg=1 copy fixed> LCL_VAR BB55 regmask=[r13] minReg=1 last> --- V07 (Interval 7) STORE_LCL_VAR BB14 regmask=[rax] minReg=1 spillAfter> LCL_VAR BB26 regmask=[r11] minReg=1 last reload> STORE_LCL_VAR BB26 regmask=[r11] minReg=1> LCL_VAR BB26 regmask=[r11] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB42 regmask=[r8] minReg=1 last reload> STORE_LCL_VAR BB42 regmask=[r8] minReg=1> LCL_VAR BB42 regmask=[r8] minReg=1 spillAfter> LCL_VAR BB55 regmask=[] minReg=1 last regOptional> --- V08 (Interval 8) STORE_LCL_VAR BB18 regmask=[rax] minReg=1> LCL_VAR BB18 regmask=[rax] minReg=1 spillAfter> BB27 regmask=[] minReg=1 regOptional> STORE_LCL_VAR BB53 regmask=[r14] minReg=1 outOfOrder> LCL_VAR BB55 regmask=[rax] minReg=1 spillAfter outOfOrder> LCL_VAR BB55 regmask=[r14] minReg=1 last reload> --- V09 (Interval 9) STORE_LCL_VAR BB18 regmask=[r8] minReg=1 spillAfter> LCL_VAR BB23 regmask=[r10] minReg=1 reload> LCL_VAR BB24 regmask=[r10] minReg=1 last> STORE_LCL_VAR BB26 regmask=[r8] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB32 regmask=[r8] minReg=1 outOfOrder> LCL_VAR BB33 regmask=[r8] minReg=1 last> STORE_LCL_VAR BB42 regmask=[rcx] minReg=1> BB43 regmask=[allInt] minReg=1 regOptional> --- V10 (Interval 10) STORE_LCL_VAR BB45 regmask=[rbx] minReg=1> STORE_LCL_VAR BB54 regmask=[rbx] minReg=1> LCL_VAR BB54 regmask=[rbx] minReg=1> LCL_VAR BB55 regmask=[rbx] minReg=1> LCL_VAR BB55 regmask=[rbx] minReg=1> LCL_VAR BB55 regmask=[rbx] minReg=1 last> --- V11 (Interval 11) STORE_LCL_VAR BB55 regmask=[r14] minReg=1> LCL_VAR BB55 regmask=[r14] minReg=1> LCL_VAR BB55 regmask=[r14] minReg=1> LCL_VAR BB55 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB55 regmask=[r14] minReg=1 last> --- V12 (Interval 12) STORE_LCL_VAR BB22 regmask=[rax] minReg=1> LCL_VAR BB25 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB25 regmask=[rax] minReg=1 spillAfter> BB27 regmask=[allInt] minReg=1 regOptional> --- V13 (Interval 13) STORE_LCL_VAR BB48 regmask=[rbx] minReg=1> LCL_VAR BB48 regmask=[rbx] minReg=1> LCL_VAR BB54 regmask=[rbx] minReg=1 last> --- V14 --- V15 (Interval 14) STORE_LCL_VAR BB12 regmask=[r13] minReg=1> STORE_LCL_VAR BB13 regmask=[r13] minReg=1> LCL_VAR BB14 regmask=[r13] minReg=1 last> --- V16 (Interval 15) STORE_LCL_VAR BB34 regmask=[rcx] minReg=1> LCL_VAR BB34 regmask=[rcx] minReg=1> LCL_VAR BB36 regmask=[rcx] minReg=1 last fixed> --- V17 (Interval 16) STORE_LCL_VAR BB34 regmask=[r10] minReg=1 spillAfter> LCL_VAR BB37 regmask=[rdx] minReg=1 last copy fixed> --- V18 --- V19 (Interval 17) STORE_LCL_VAR BB35 regmask=[r11] minReg=1> STORE_LCL_VAR BB36 regmask=[r11] minReg=1> LCL_VAR BB37 regmask=[r11] minReg=1 fixed> LCL_VAR BB37 regmask=[r11] minReg=1 last> --- V20 --- V21 (Interval 18) STORE_LCL_VAR BB64 regmask=[rcx] minReg=1> LCL_VAR BB64 regmask=[rcx] minReg=1> LCL_VAR BB65 regmask=[rcx] minReg=1 last> LCL_VAR BB66 regmask=[rcx] minReg=1 last fixed> --- V22 --- V23 (Interval 19) STORE_LCL_VAR BB65 regmask=[rcx] minReg=1> STORE_LCL_VAR BB66 regmask=[rcx] minReg=1> LCL_VAR BB67 regmask=[rcx] minReg=1 last fixed> --- V24 (Interval 20) STORE_LCL_VAR BB19 regmask=[rcx] minReg=1> LCL_VAR BB19 regmask=[rcx] minReg=1> LCL_VAR BB21 regmask=[rcx] minReg=1 last fixed> --- V25 (Interval 21) STORE_LCL_VAR BB20 regmask=[rdx] minReg=1> STORE_LCL_VAR BB21 regmask=[rdx] minReg=1> LCL_VAR BB22 regmask=[rcx] minReg=1 last copy fixed> --- V26 (Interval 22) STORE_LCL_VAR BB60 regmask=[rcx] minReg=1> LCL_VAR BB60 regmask=[rcx] minReg=1> LCL_VAR BB61 regmask=[rcx] minReg=1 last> LCL_VAR BB62 regmask=[rcx] minReg=1 last fixed> --- V27 --- V28 (Interval 23) STORE_LCL_VAR BB61 regmask=[rcx] minReg=1> STORE_LCL_VAR BB62 regmask=[rcx] minReg=1> LCL_VAR BB63 regmask=[rcx] minReg=1 last fixed> --- V29 (Interval 24) STORE_LCL_VAR BB09 regmask=[rcx] minReg=1> LCL_VAR BB09 regmask=[rcx] minReg=1> LCL_VAR BB11 regmask=[rcx] minReg=1 last fixed> --- V30 --- V31 (Interval 25) STORE_LCL_VAR BB10 regmask=[r11] minReg=1> STORE_LCL_VAR BB11 regmask=[r11] minReg=1> LCL_VAR BB12 regmask=[r11] minReg=1 fixed> LCL_VAR BB12 regmask=[r11] minReg=1 last> --- V32 --- V33 (Interval 26) STORE_LCL_VAR BB04 regmask=[rcx] minReg=1> LCL_VAR BB04 regmask=[rcx] minReg=1 last regOptional> --- V34 --- V35 (Interval 27) STORE_LCL_VAR BB04 regmask=[rdx] minReg=1> LCL_VAR BB05 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB05 regmask=[rdx] minReg=1 last fixed> --- V36 (Interval 28) STORE_LCL_VAR BB06 regmask=[rcx] minReg=1> LCL_VAR BB06 regmask=[rcx] minReg=1 last regOptional> --- V37 (Interval 29) STORE_LCL_VAR BB06 regmask=[rdx] minReg=1> LCL_VAR BB07 regmask=[rdx] minReg=1 last fixed> --- V38 (Interval 30) STORE_LCL_VAR BB18 regmask=[rax] minReg=1> LCL_VAR BB18 regmask=[rax] minReg=1 last> --- V39 (Interval 31) STORE_LCL_VAR BB14 regmask=[r8] minReg=1> LCL_VAR BB14 regmask=[r8] minReg=1 spillAfter> LCL_VAR BB18 regmask=[r8] minReg=1> LCL_VAR BB18 regmask=[r8] minReg=1 last> --- V40 (Interval 32) STORE_LCL_VAR BB14 regmask=[r9] minReg=1> LCL_VAR BB14 regmask=[r9] minReg=1 spillAfter regOptional> LCL_VAR BB16 regmask=[r9] minReg=1> LCL_VAR BB16 regmask=[r9] minReg=1 last delay regOptional> --- V41 (Interval 33) STORE_LCL_VAR BB14 regmask=[r10] minReg=1 spillAfter> LCL_VAR BB16 regmask=[r10] minReg=1 last regOptional> --- V42 (Interval 34) STORE_LCL_VAR BB16 regmask=[r10] minReg=1> LCL_VAR BB16 regmask=[r10] minReg=1 spillAfter regOptional> LCL_VAR BB18 regmask=[r10] minReg=1> LCL_VAR BB18 regmask=[r10] minReg=1 last> --- V43 (Interval 35) STORE_LCL_VAR BB14 regmask=[rcx] minReg=1> LCL_VAR BB14 regmask=[rcx] minReg=1 last regOptional> --- V44 --- V45 (Interval 36) STORE_LCL_VAR BB14 regmask=[rdx] minReg=1> LCL_VAR BB15 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB15 regmask=[rdx] minReg=1 last fixed> --- V46 (Interval 37) STORE_LCL_VAR BB16 regmask=[rcx] minReg=1> LCL_VAR BB16 regmask=[rcx] minReg=1 last regOptional> --- V47 --- V48 (Interval 38) STORE_LCL_VAR BB16 regmask=[rdx] minReg=1> LCL_VAR BB17 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB17 regmask=[rdx] minReg=1 last fixed> --- V49 (Interval 39) STORE_LCL_VAR BB45 regmask=[rcx] minReg=1> LCL_VAR BB45 regmask=[rcx] minReg=1 last regOptional> --- V50 (Interval 40) STORE_LCL_VAR BB45 regmask=[rdx] minReg=1> LCL_VAR BB46 regmask=[rdx] minReg=1 last fixed> --- V51 (Interval 41) STORE_LCL_VAR BB53 regmask=[rax] minReg=1> LCL_VAR BB53 regmask=[rax] minReg=1 last> --- V52 (Interval 42) STORE_LCL_VAR BB49 regmask=[r15] minReg=1> LCL_VAR BB49 regmask=[r15] minReg=1> LCL_VAR BB53 regmask=[r15] minReg=1 last> --- V53 (Interval 43) STORE_LCL_VAR BB49 regmask=[r8] minReg=1> LCL_VAR BB49 regmask=[r8] minReg=1 spillAfter regOptional> LCL_VAR BB51 regmask=[r8] minReg=1> LCL_VAR BB51 regmask=[r8] minReg=1 last delay regOptional> --- V54 (Interval 44) STORE_LCL_VAR BB49 regmask=[r9] minReg=1 spillAfter> LCL_VAR BB51 regmask=[r9] minReg=1 last regOptional> --- V55 (Interval 45) STORE_LCL_VAR BB51 regmask=[r9] minReg=1> LCL_VAR BB51 regmask=[r9] minReg=1 spillAfter regOptional> LCL_VAR BB53 regmask=[r9] minReg=1> LCL_VAR BB53 regmask=[r9] minReg=1 last> --- V56 (Interval 46) STORE_LCL_VAR BB49 regmask=[rcx] minReg=1> LCL_VAR BB49 regmask=[rcx] minReg=1 last regOptional> --- V57 --- V58 (Interval 47) STORE_LCL_VAR BB49 regmask=[rdx] minReg=1> LCL_VAR BB50 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB50 regmask=[rdx] minReg=1 last fixed> --- V59 (Interval 48) STORE_LCL_VAR BB51 regmask=[rcx] minReg=1> LCL_VAR BB51 regmask=[rcx] minReg=1 last regOptional> --- V60 --- V61 (Interval 49) STORE_LCL_VAR BB51 regmask=[rdx] minReg=1> LCL_VAR BB52 regmask=[rcx] minReg=1 copy fixed> LCL_VAR BB52 regmask=[rdx] minReg=1 last fixed> --- V62 (Interval 50) STORE_LCL_VAR BB45 regmask=[rcx] minReg=1> LCL_VAR BB45 regmask=[rcx] minReg=1> LCL_VAR BB45 regmask=[rcx] minReg=1 last> --- V63 (Interval 51) STORE_LCL_VAR BB47 regmask=[rcx] minReg=1> LCL_VAR BB47 regmask=[rcx] minReg=1> LCL_VAR BB47 regmask=[rcx] minReg=1 last> --- V64 (Interval 52) STORE_LCL_VAR BB49 regmask=[rdx] minReg=1> LCL_VAR BB49 regmask=[rdx] minReg=1 last fixed> --- V65 (Interval 53) STORE_LCL_VAR BB24 regmask=[r11] minReg=1> LCL_VAR BB24 regmask=[r11] minReg=1 spillAfter> LCL_VAR BB26 regmask=[r11] minReg=1 last> LCL_VAR BB29 regmask=[r11] minReg=1 last> --- V66 (Interval 54) STORE_LCL_VAR BB33 regmask=[r8] minReg=1> LCL_VAR BB33 regmask=[r8] minReg=1 spillAfter> LCL_VAR BB39 regmask=[r15] minReg=1 last reload> LCL_VAR BB42 regmask=[r8] minReg=1 last outOfOrder> --- V67 (Interval 55) STORE_LCL_VAR BB34 regmask=[r11] minReg=1> LCL_VAR BB34 regmask=[r11] minReg=1 regOptional> LCL_VAR BB35 regmask=[r11] minReg=1 last> --- V68 (Interval 56) STORE_LCL_VAR BB09 regmask=[r11] minReg=1> LCL_VAR BB09 regmask=[r11] minReg=1 regOptional> LCL_VAR BB10 regmask=[r11] minReg=1 last> --- V69 (Interval 57) STORE_LCL_VAR BB19 regmask=[rdx] minReg=1> LCL_VAR BB19 regmask=[rdx] minReg=1 regOptional> LCL_VAR BB20 regmask=[rdx] minReg=1 last> --- V70 (Interval 58) STORE_LCL_VAR BB24 regmask=[rdx] minReg=1> LCL_VAR BB24 regmask=[rdx] minReg=1> LCL_VAR BB25 regmask=[rdx] minReg=1 last> --- V71 (Interval 59) STORE_LCL_VAR BB33 regmask=[rcx] minReg=1> LCL_VAR BB33 regmask=[rcx] minReg=1> LCL_VAR BB34 regmask=[rcx] minReg=1 last> --- V72 (Interval 60) STORE_LCL_VAR BB49 regmask=[rax] minReg=1> LCL_VAR BB49 regmask=[rax] minReg=1 spillAfter> LCL_VAR BB53 regmask=[] minReg=1 last regOptional> --- V73 (Interval 61) STORE_LCL_VAR BB04 regmask=[r14] minReg=1> LCL_VAR BB04 regmask=[r14] minReg=1> LCL_VAR BB06 regmask=[r14] minReg=1> LCL_VAR BB14 regmask=[r14] minReg=1> LCL_VAR BB16 regmask=[r14] minReg=1> BB27 regmask=[allInt] minReg=1 regOptional> LCL_VAR BB45 regmask=[r14] minReg=1 last outOfOrder> LCL_VAR BB49 regmask=[r14] minReg=1> LCL_VAR BB51 regmask=[r14] minReg=1 last> --- V74 (Interval 62) STORE_LCL_VAR BB45 regmask=[rcx] minReg=1> LCL_VAR BB45 regmask=[rcx] minReg=1> LCL_VAR BB45 regmask=[rcx] minReg=1 last> --- V75 (Interval 63) STORE_LCL_VAR BB48 regmask=[rcx] minReg=1> LCL_VAR BB48 regmask=[rcx] minReg=1> LCL_VAR BB49 regmask=[rcx] minReg=1 last fixed> --- V76 (Interval 64) STORE_LCL_VAR BB23 regmask=[r9] minReg=1> LCL_VAR BB23 regmask=[r9] minReg=1 spillAfter regOptional> LCL_VAR BB26 regmask=[r9] minReg=1 last regOptional> STORE_LCL_VAR BB32 regmask=[r9] minReg=1> LCL_VAR BB32 regmask=[r9] minReg=1 spillAfter regOptional> LCL_VAR BB42 regmask=[r9] minReg=1 last regOptional> LCL_VAR BB45 regmask=[r9] minReg=1 spillAfter regOptional> LCL_VAR BB47 regmask=[r9] minReg=1 last regOptional> LCL_VAR BB48 regmask=[r9] minReg=1 last regOptional> Active intervals at end of allocation: Active Interval 0: (V00) ref RefPositions {#0@0 #7@25 #10@33 #32@53 #65@103 #100@157 #106@177 #207@287 #215@307 #322@489 #514@789 #631@949 #633@961 #685@1051 #702@1081 #704@1099 #706@1109 #737@1145 #758@1159 #768@1183 #872@1353 #874@1361 #938@1465 #972@1511 #1013@1541 #1077@1611 #1148@1681 #1157@1685 #1158@1685} physReg:rsi Preferences=[rsi] ----------------------- RESOLVING BB BOUNDARIES ----------------------- Resolution Candidates: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V12 V13 V15 V16 V17 V19 V21 V23 V24 V25 V26 V28 V29 V31 V35 V37 V39 V40 V41 V42 V45 V48 V50 V52 V53 V54 V55 V58 V61 V65 V66 V67 V68 V69 V70 V71 V72 V73 V75 V76} Has Critical Edges Prior to Resolution BB01 use def in out {V01} {} {V00 V01 V02 V03} {V00 V01 V02 V03} Var=Reg beg of BB01: V00=rsi V01=rdi V03=rbx V02=rbp Var=Reg end of BB01: V00=rsi V01=rdi V03=rbx V02=rbp BB02 use def in out {V00} {} {V00 V01 V02 V03} {V00 V01 V02 V03} Var=Reg beg of BB02: V00=rsi V01=rdi V03=rbx V02=rbp Var=Reg end of BB02: V00=rsi V01=rdi V03=rbx V02=rbp BB03 use def in out {V00} {} {V00 V01 V02 V03} {V00 V01 V02 V03} Var=Reg beg of BB03: V00=rsi V01=rdi V03=rbx V02=rbp Var=Reg end of BB03: V00=rsi V01=rdi V03=rbx V02=rbp BB04 use def in out {V00} {V33 V34 V35 V73} {V00 V01 V02 V03} {V00 V01 V02 V03 V35 V73} Var=Reg beg of BB04: V00=rsi V01=rdi V03=rbx V02=rbp Var=Reg end of BB04: V00=rsi V01=rdi V73=r14 V03=rbx V02=rbp V35=rdx BB05 use def in out {V35} {} {V00 V01 V02 V03 V35 V73} {V00 V01 V02 V03 V73} Var=Reg beg of BB05: V00=rsi V01=rdi V73=r14 V03=rbx V02=rbp V35=rdx Var=Reg end of BB05: V00=rsi V01=rdi V73=r14 V03=rbx V02=rbp BB06 use def in out {V00 V73} {V04 V36 V37} {V00 V01 V02 V03 V73} {V00 V01 V02 V03 V04 V37 V73} Var=Reg beg of BB06: V00=rsi V01=rdi V73=r14 V03=rbx V02=rbp Var=Reg end of BB06: V04=r15 V00=rsi V01=rdi V73=r14 V03=rbx V02=rbp V37=rdx BB07 use def in out {V37} {} {V00 V01 V02 V03 V04 V37 V73} {V00 V01 V02 V03 V04 V73} Var=Reg beg of BB07: V04=r15 V00=rsi V01=rdi V73=r14 V03=rbx V02=rbp V37=rdx Var=Reg end of BB07: V04=r15 V00=rsi V01=rdi V73=r14 V03=rbx V02=rbp BB08 use def in out {V00} {V05} {V00 V01 V02 V03 V04 V73} {V00 V01 V02 V03 V04 V05 V73} Var=Reg beg of BB08: V04=r15 V00=rsi V01=rdi V73=r14 V03=rbx V02=rbp Var=Reg end of BB08: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp BB09 use def in out {V00} {V29 V68} {V00 V01 V02 V03 V04 V05 V73} {V00 V01 V02 V03 V04 V05 V29 V68 V73} Var=Reg beg of BB09: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp Var=Reg end of BB09: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V29=rcx V68=r11 BB10 use def in out {V68} {V31} {V00 V01 V02 V03 V04 V05 V68 V73} {V00 V01 V02 V03 V04 V05 V31 V73} Var=Reg beg of BB10: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V68=r11 Var=Reg end of BB10: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V31=r11 BB11 use def in out {V29} {V31} {V00 V01 V02 V03 V04 V05 V29 V73} {V00 V01 V02 V03 V04 V05 V31 V73} Var=Reg beg of BB11: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V29=rcx Var=Reg end of BB11: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V31=r11 BB12 use def in out {V01 V05 V31} {V15} {V00 V01 V02 V03 V04 V05 V31 V73} {V00 V01 V02 V03 V04 V05 V15 V73} Var=Reg beg of BB12: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V31=r11 Var=Reg end of BB12: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V15=r13 BB13 use def in out {V01} {V15} {V00 V01 V02 V03 V04 V05 V73} {V00 V01 V02 V03 V04 V05 V15 V73} Var=Reg beg of BB13: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp Var=Reg end of BB13: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V15=r13 BB14 use def in out {V00 V15 V73} {V06 V07 V39 V40 V41 V43 V44 V45} {V00 V01 V02 V03 V04 V05 V15 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V45 V73} Var=Reg beg of BB14: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V15=r13 Var=Reg end of BB14: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V45=rdx BB15 use def in out {V45} {} {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V45 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V73} Var=Reg beg of BB15: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V45=rdx Var=Reg end of BB15: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp BB16 use def in out {V06 V40 V41 V73} {V42 V46 V47 V48} {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V48 V73} Var=Reg beg of BB16: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp Var=Reg end of BB16: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V48=rdx BB17 use def in out {V48} {} {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V48 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V73} Var=Reg beg of BB17: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V48=rdx Var=Reg end of BB17: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp BB18 use def in out {V05 V39 V42} {V08 V09 V38} {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} Var=Reg beg of BB18: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp Var=Reg end of BB18: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp BB19 use def in out {V00} {V24 V69} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V24 V69 V73} Var=Reg beg of BB19: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp Var=Reg end of BB19: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V24=rcx V69=rdx BB20 use def in out {V69} {V25} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V69 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V25 V73} Var=Reg beg of BB20: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V69=rdx Var=Reg end of BB20: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V25=rdx BB21 use def in out {V24} {V25} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V24 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V25 V73} Var=Reg beg of BB21: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V24=rcx Var=Reg end of BB21: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V25=rdx BB22 use def in out {V25} {V12} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V25 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73} Var=Reg beg of BB22: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V25=rdx Var=Reg end of BB22: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V12=rax BB23 use def in out {V04 V09} {V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73 V76} Var=Reg beg of BB23: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V12=rax Var=Reg end of BB23: V04=r15 V09=r10 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V12=rax BB24 use def in out {V04 V06 V09} {V65 V70} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73 V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V65 V70 V73 V76} Var=Reg beg of BB24: V04=r15 V09=r10 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V12=rax Var=Reg end of BB24: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V70=rdx V05=r12 V03=rbx V02=rbp V12=rax BB25 use def in out {V01 V04 V12 V70} {} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V65 V70 V73 V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V65 V73 V76} Var=Reg beg of BB25: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V70=rdx V05=r12 V03=rbx V02=rbp V12=rax Var=Reg end of BB25: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp BB26 use def in out {V07 V65 V76} {V07 V09} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V65 V73 V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73} Var=Reg beg of BB26: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V12=rax Var=Reg end of BB26: V07=r11 V04=r15 V09=r8 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V12=rax BB27 use def in out {} {} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73} Var=Reg beg of BB27: V07=r11 V04=r15 V09=r8 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V12=rax Var=Reg end of BB27: V07=r11 V04=r15 V09=r8 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V12=rax BB28 use def in out {V03} {} {V00 V01 V02 V03 V65} {V00 V01 V02 V03 V65} Var=Reg beg of BB28: V00=rsi V01=rdi V03=rbx V02=rbp Var=Reg end of BB28: V00=rsi V01=rdi V03=rbx V02=rbp BB29 use def in out {V02 V65} {} {V00 V02 V65} {V00} Var=Reg beg of BB29: V00=rsi V02=rbp Var=Reg end of BB29: V00=rsi BB30 use def in out {V03} {} {V00 V01 V03} {V00 V01} Var=Reg beg of BB30: V00=rsi V01=rdi V03=rbx Var=Reg end of BB30: V00=rsi V01=rdi BB31 use def in out {} {} {V00} {V00} Var=Reg beg of BB31: V00=rsi Var=Reg end of BB31: V00=rsi BB32 use def in out {V04 V09} {V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73 V76} Var=Reg beg of BB32: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp Var=Reg end of BB32: V04=r15 V09=r8 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp BB33 use def in out {V04 V06 V09} {V66 V71} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73 V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V66 V71 V73 V76} Var=Reg beg of BB33: V04=r15 V09=r8 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp Var=Reg end of BB33: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V71=rcx V05=r12 V03=rbx V02=rbp BB34 use def in out {V00 V04 V71} {V16 V17 V67} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V66 V71 V73 V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V16 V17 V66 V67 V73 V76} Var=Reg beg of BB34: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V71=rcx V05=r12 V03=rbx V02=rbp Var=Reg end of BB34: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V16=rcx V05=r12 V03=rbx V02=rbp V67=r11 BB35 use def in out {V67} {V19} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V66 V67 V73 V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V19 V66 V73 V76} Var=Reg beg of BB35: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V17=r10 V05=r12 V03=rbx V02=rbp V67=r11 Var=Reg end of BB35: V04=r15 V00=rsi V06=r13 V19=r11 V01=rdi V73=r14 V17=r10 V05=r12 V03=rbx V02=rbp BB36 use def in out {V16} {V19} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V16 V17 V66 V73 V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V19 V66 V73 V76} Var=Reg beg of BB36: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V16=rcx V05=r12 V03=rbx V02=rbp Var=Reg end of BB36: V04=r15 V00=rsi V06=r13 V19=r11 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp BB37 use def in out {V01 V05 V17 V19} {} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V19 V66 V73 V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V66 V73 V76} Var=Reg beg of BB37: V04=r15 V00=rsi V06=r13 V19=r11 V01=rdi V73=r14 V17=r10 V05=r12 V03=rbx V02=rbp Var=Reg end of BB37: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp BB38 use def in out {V03} {} {V00 V01 V02 V03 V66} {V00 V01 V02 V03 V66} Var=Reg beg of BB38: V00=rsi V01=rdi V03=rbx V02=rbp Var=Reg end of BB38: V00=rsi V01=rdi V03=rbx V02=rbp BB39 use def in out {V02 V66} {} {V00 V02 V66} {V00} Var=Reg beg of BB39: V00=rsi V02=rbp Var=Reg end of BB39: V00=rsi BB40 use def in out {V03} {} {V00 V01 V03} {V00 V01} Var=Reg beg of BB40: V00=rsi V01=rdi V03=rbx Var=Reg end of BB40: V00=rsi V01=rdi BB41 use def in out {} {} {V00} {V00} Var=Reg beg of BB41: V00=rsi Var=Reg end of BB41: V00=rsi BB42 use def in out {V07 V66 V76} {V07 V09} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V66 V73 V76} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} Var=Reg beg of BB42: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp Var=Reg end of BB42: V04=r15 V09=rcx V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp BB43 use def in out {} {} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} Var=Reg beg of BB43: V04=r15 V09=rcx V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp Var=Reg end of BB43: V04=r15 V09=rcx V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp BB44 use def in out {V00} {} {V00 V01 V02 V04 V05 V06 V07 V08 V73 V76} {V00 V01 V02 V04 V05 V06 V07 V08 V73 V76} Var=Reg beg of BB44: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V02=rbp Var=Reg end of BB44: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V02=rbp BB45 use def in out {V00 V04 V73 V76} {V10 V49 V50 V62 V74} {V00 V01 V02 V04 V05 V06 V07 V08 V73 V76} {V00 V01 V02 V04 V05 V06 V07 V08 V10 V50 V76} Var=Reg beg of BB45: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V02=rbp Var=Reg end of BB45: V04=r15 V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V10=rbx V50=rdx BB46 use def in out {V50} {} {V00 V01 V02 V04 V05 V06 V07 V08 V10 V50 V76} {V00 V01 V02 V04 V05 V06 V07 V08 V10 V76} Var=Reg beg of BB46: V04=r15 V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V10=rbx V50=rdx Var=Reg end of BB46: V04=r15 V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V10=rbx BB47 use def in out {V00 V04 V76} {V63} {V00 V01 V02 V04 V05 V06 V07 V08 V10 V76} {V00 V01 V02 V04 V05 V06 V07 V08 V10} Var=Reg beg of BB47: V04=r15 V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V10=rbx Var=Reg end of BB47: V04=r15 V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V10=rbx BB48 use def in out {V00 V76} {V13 V75} {V00 V01 V02 V05 V06 V07 V08 V73 V76} {V00 V01 V02 V05 V06 V07 V08 V13 V73 V75} Var=Reg beg of BB48: V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V02=rbp Var=Reg end of BB48: V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V02=rbp V13=rbx V75=rcx BB49 use def in out {V00 V73 V75} {V52 V53 V54 V56 V57 V58 V64 V72} {V00 V01 V02 V05 V06 V07 V13 V73 V75} {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V58 V72 V73} Var=Reg beg of BB49: V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V02=rbp V13=rbx V75=rcx Var=Reg end of BB49: V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V02=rbp V58=rdx V52=r15 V13=rbx BB50 use def in out {V58} {} {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V58 V72 V73} {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V72 V73} Var=Reg beg of BB50: V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V02=rbp V58=rdx V52=r15 V13=rbx Var=Reg end of BB50: V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V02=rbp V52=r15 V13=rbx BB51 use def in out {V06 V53 V54 V73} {V55 V59 V60 V61} {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V72 V73} {V00 V01 V02 V05 V06 V07 V13 V52 V55 V61 V72} Var=Reg beg of BB51: V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V02=rbp V52=r15 V13=rbx Var=Reg end of BB51: V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V61=rdx V52=r15 V13=rbx BB52 use def in out {V61} {} {V00 V01 V02 V05 V06 V07 V13 V52 V55 V61 V72} {V00 V01 V02 V05 V06 V07 V13 V52 V55 V72} Var=Reg beg of BB52: V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V61=rdx V52=r15 V13=rbx Var=Reg end of BB52: V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V52=r15 V13=rbx BB53 use def in out {V52 V55 V72} {V08 V51} {V00 V01 V02 V05 V06 V07 V13 V52 V55 V72} {V00 V01 V02 V05 V06 V07 V08 V13} Var=Reg beg of BB53: V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V52=r15 V13=rbx Var=Reg end of BB53: V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V08=r14 V13=rbx BB54 use def in out {V00 V13} {V04 V10} {V00 V01 V02 V05 V06 V07 V08 V13} {V00 V01 V02 V04 V05 V06 V07 V08 V10} Var=Reg beg of BB54: V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V13=rbx Var=Reg end of BB54: V04=r15 V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V10=rbx BB55 use def in out {V00 V01 V02 V04 V06 V07 V08 V10} {V11} {V00 V01 V02 V04 V05 V06 V07 V08 V10} {V00 V04 V05} Var=Reg beg of BB55: V04=r15 V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V10=rbx Var=Reg end of BB55: V04=r15 V00=rsi V05=r12 BB56 use def in out {V05} {} {V00 V04 V05} {V00 V04} Var=Reg beg of BB56: V04=r15 V00=rsi V05=r12 Var=Reg end of BB56: V04=r15 V00=rsi BB57 use def in out {V00 V04} {} {V00 V04} {V00} Var=Reg beg of BB57: V04=r15 V00=rsi Var=Reg end of BB57: V00=rsi BB58 use def in out {} {} {V00} {V00} Var=Reg beg of BB58: V00=rsi Var=Reg end of BB58: V00=rsi BB59 use def in out {} {} {V00} {V00} Var=Reg beg of BB59: V00=rsi Var=Reg end of BB59: V00=rsi BB60 use def in out {V00} {V26} {V00 V01} {V00 V01 V26} Var=Reg beg of BB60: V00=rsi V01=rdi Var=Reg end of BB60: V00=rsi V01=rdi V26=rcx BB61 use def in out {V26} {V28} {V00 V01 V26} {V00 V01 V28} Var=Reg beg of BB61: V00=rsi V01=rdi V26=rcx Var=Reg end of BB61: V00=rsi V01=rdi V28=rcx BB62 use def in out {V26} {V28} {V00 V01 V26} {V00 V01 V28} Var=Reg beg of BB62: V00=rsi V01=rdi V26=rcx Var=Reg end of BB62: V00=rsi V01=rdi V28=rcx BB63 use def in out {V01 V28} {} {V00 V01 V28} {V00} Var=Reg beg of BB63: V00=rsi V01=rdi V28=rcx Var=Reg end of BB63: V00=rsi BB64 use def in out {V00} {V21} {V00 V01} {V00 V01 V21} Var=Reg beg of BB64: V00=rsi V01=rdi Var=Reg end of BB64: V00=rsi V01=rdi V21=rcx BB65 use def in out {V21} {V23} {V00 V01 V21} {V00 V01 V23} Var=Reg beg of BB65: V00=rsi V01=rdi V21=rcx Var=Reg end of BB65: V00=rsi V01=rdi V23=rcx BB66 use def in out {V21} {V23} {V00 V01 V21} {V00 V01 V23} Var=Reg beg of BB66: V00=rsi V01=rdi V21=rcx Var=Reg end of BB66: V00=rsi V01=rdi V23=rcx BB67 use def in out {V01 V23} {} {V00 V01 V23} {V00} Var=Reg beg of BB67: V00=rsi V01=rdi V23=rcx Var=Reg end of BB67: V00=rsi BB68 use def in out {} {} {V00} {V00} Var=Reg beg of BB68: V00=rsi Var=Reg end of BB68: V00=rsi BB69 use def in out {} {} {V00} {V00} Var=Reg beg of BB69: V00=rsi Var=Reg end of BB69: V00=rsi RESOLVING EDGES BB25 bottom: move V12 from STK to rax (SharedCritical) BB27 bottom: move V07 from r11 to STK (Join) BB27 bottom: move V09 from r8 to STK (Join) BB35 top: move V17 from STK to r10 (Split) BB36 bottom: move V17 from STK to r10 (Join) BB43 bottom: move V09 from rcx to STK (Join) BB53 bottom: move V08 from r14 to STK (Join) Set V00 argument initial register to rsi Set V01 argument initial register to rdi Set V02 argument initial register to rbp Set V03 argument initial register to rbx Trees after linear scan register allocator (LSRA) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i LIR BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i LIR BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe LIR BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i LIR BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe LIR BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i LIR BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe LIR BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i LIR BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe LIR BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe LIR BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe LIR BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe LIR BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe LIR BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen LIR BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe LIR BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen LIR BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe LIR BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen LIR BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe LIR BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe LIR BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe LIR BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe LIR BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target LIR BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd LIR BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd LIR BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd LIR BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal LIR BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd LIR BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen LIR BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd LIR BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal Loop1 gcsafe LIR BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target LIR BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd LIR BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd LIR BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe LIR BB36 [0108] 1 BB34 1 [???..???) i gcsafe LIR BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd LIR BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd LIR BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen LIR BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd LIR BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe LIR BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd LIR BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal LIR BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i LIR BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen LIR BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe LIR BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen LIR BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen LIR BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen LIR BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe LIR BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen LIR BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe LIR BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen LIR BB54 [0044] 2 BB48,BB53 0.50 [261..276) i LIR BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen LIR BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall LIR BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen LIR BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal LIR BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe LIR BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd LIR BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe LIR BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe LIR BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd LIR BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd LIR BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe LIR BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe LIR BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd LIR BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd LIR BB69 [0117] 0 0 [???..???) (throw ) keep i internal rare LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} N003 (???,???) [001332] ------------ IL_OFFSET void IL offset: 0x0 REG NA N005 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V01 arg1 u:1 rdi REG rdi $101 N007 ( 1, 1) [000001] -c---------- t1 = CNS_INT ref null REG NA $VN.Null /--* t0 ref +--* t1 ref N009 ( 3, 3) [000002] J------N---- * EQ void REG NA $180 N011 ( 5, 5) [000003] ------------ * JTRUE void REG NA ------------ BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} N015 (???,???) [001333] ------------ IL_OFFSET void IL offset: 0xe REG NA N017 ( 1, 1) [000004] ------------ t4 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t4 ref N019 ( 2, 2) [000814] -c---------- t814 = * LEA(b+8) byref REG NA /--* t814 byref N021 ( 4, 4) [000005] -c-XG------- t5 = * IND ref REG NA N023 ( 1, 1) [000006] -c---------- t6 = CNS_INT ref null REG NA $VN.Null /--* t5 ref +--* t6 ref N025 ( 6, 6) [000007] J--XG--N---- * NE void REG NA N027 ( 8, 8) [000008] ---XG------- * JTRUE void REG NA ------------ BB03 [016..01E), preds={BB02} succs={BB04} N031 ( 1, 1) [000526] ------------ t526 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t526 ref N033 (???,???) [001455] ------------ t1455 = * PUTARG_REG ref REG rcx N035 ( 1, 1) [000527] ------------ t527 = CNS_INT int 0 REG rdx $c0 /--* t527 int N037 (???,???) [001456] ------------ t1456 = * PUTARG_REG int REG rdx /--* t1455 ref this in rcx +--* t1456 int arg1 in rdx N039 ( 16, 10) [000528] --CXG------- t528 = * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize REG rax $1c2 ------------ BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} N043 (???,???) [001334] ------------ IL_OFFSET void IL offset: 0x1e REG NA N045 ( 1, 1) [000009] ------------ t9 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t9 ref N047 ( 2, 2) [000818] -c---------- t818 = * LEA(b+8) byref REG NA /--* t818 byref N049 ( 4, 4) [000010] nc--GO------ t10 = * IND ref REG NA N051 ( 1, 1) [000011] -c---------- t11 = CNS_INT ref null REG NA $VN.Null /--* t10 ref +--* t11 ref N053 ( 9, 6) [000012] N---GO------ t12 = * NE int REG rcx /--* t12 int N055 ( 9, 6) [000544] DA--GO------ * STORE_LCL_VAR int V33 tmp19 d:1 rcx REG rcx N057 (???,???) [001335] ------------ IL_OFFSET void IL offset: 0x1e REG NA N059 ( 2, 10) [000537] H----------- t537 = CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] REG rdx $43 /--* t537 long N061 ( 4, 12) [000538] #---G------- t538 = * IND ref REG r14 $105 /--* t538 ref N063 ( 4, 12) [001291] DA--G------- * STORE_LCL_VAR ref V73 cse8 d:1 r14 REG r14 N065 (???,???) [001336] ------------ IL_OFFSET void IL offset: 0x1e REG NA N067 ( 1, 1) [001294] ------------ t1294 = LCL_VAR ref V73 cse8 u:1 r14 REG r14 $105 /--* t1294 ref N069 ( 1, 3) [000556] DA--G------- * STORE_LCL_VAR ref V35 tmp21 d:1 rdx REG rdx N071 (???,???) [001337] ------------ IL_OFFSET void IL offset: 0x1e REG NA N073 ( 1, 1) [000546] ------------ t546 = LCL_VAR int V33 tmp19 u:1 rcx (last use) REG rcx N075 ( 1, 1) [000547] -c---------- t547 = CNS_INT int 0 REG NA $c0 /--* t546 int +--* t547 int N077 ( 3, 3) [000548] J------N---- * NE void REG NA N079 ( 5, 5) [000549] ------------ * JTRUE void REG NA ------------ BB05 [01E..01F), preds={BB04} succs={BB06} N083 (???,???) [001338] ------------ IL_OFFSET void IL offset: 0x1e REG NA N085 ( 1, 1) [000550] ------------ t550 = LCL_VAR ref V35 tmp21 u:1 rdx REG rdx $105 /--* t550 ref N087 (???,???) [001457] ------------ t1457 = * PUTARG_REG ref REG rcx N089 ( 1, 1) [000551] ------------ t551 = LCL_VAR ref V35 tmp21 u:1 rdx (last use) REG rdx $105 /--* t551 ref N091 (???,???) [001458] ------------ t1458 = * PUTARG_REG ref REG rdx /--* t1457 ref arg0 in rcx +--* t1458 ref arg1 in rdx N093 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail REG NA $VN.Void ------------ BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} N097 (???,???) [001339] ------------ IL_OFFSET void IL offset: 0x2c REG NA N099 ( 1, 1) [000015] ------------ t15 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t15 ref N101 ( 2, 2) [000822] -c---------- t822 = * LEA(b+16) byref REG NA /--* t822 byref N103 ( 4, 4) [000016] n---GO------ t16 = * IND ref REG r15 /--* t16 ref N105 ( 4, 4) [000018] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:1 r15 REG r15 N107 (???,???) [001340] ------------ IL_OFFSET void IL offset: 0x33 REG NA N109 ( 1, 1) [000019] ------------ t19 = LCL_VAR ref V04 loc0 u:1 r15 REG r15 N111 ( 1, 1) [000020] -c---------- t20 = CNS_INT ref null REG NA $VN.Null /--* t19 ref +--* t20 ref N113 ( 6, 3) [000021] N----------- t21 = * NE int REG rcx /--* t21 int N115 ( 6, 3) [000566] DA---------- * STORE_LCL_VAR int V36 tmp22 d:1 rcx REG rcx N117 (???,???) [001341] ------------ IL_OFFSET void IL offset: 0x33 REG NA N119 ( 1, 1) [001295] ------------ t1295 = LCL_VAR ref V73 cse8 u:1 r14 REG r14 $105 /--* t1295 ref N121 ( 1, 3) [000576] DA--G------- * STORE_LCL_VAR ref V37 tmp23 d:1 rdx REG rdx N123 (???,???) [001342] ------------ IL_OFFSET void IL offset: 0x33 REG NA N125 ( 1, 1) [000568] ------------ t568 = LCL_VAR int V36 tmp22 u:1 rcx (last use) REG rcx N127 ( 1, 1) [000569] -c---------- t569 = CNS_INT int 0 REG NA $c0 /--* t568 int +--* t569 int N129 ( 3, 3) [000570] J------N---- * NE void REG NA N131 ( 5, 5) [000571] ------------ * JTRUE void REG NA ------------ BB07 [033..034), preds={BB06} succs={BB08} N135 (???,???) [001343] ------------ IL_OFFSET void IL offset: 0x33 REG NA N137 ( 2, 10) [000823] H----------- t823 = CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" REG rcx $46 /--* t823 long N139 ( 4, 12) [000824] #---G------- t824 = * IND ref REG rcx $106 /--* t824 ref N141 (???,???) [001459] ----G------- t1459 = * PUTARG_REG ref REG rcx N143 ( 1, 1) [000573] ------------ t573 = LCL_VAR ref V37 tmp23 u:1 rdx (last use) REG rdx $105 /--* t573 ref N145 (???,???) [001460] ------------ t1460 = * PUTARG_REG ref REG rdx /--* t1459 ref arg0 in rcx +--* t1460 ref arg1 in rdx N147 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail REG NA $VN.Void ------------ BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} N151 (???,???) [001344] ------------ IL_OFFSET void IL offset: 0x41 REG NA N153 ( 1, 1) [000025] ------------ t25 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t25 ref N155 ( 2, 2) [000828] -c---------- t828 = * LEA(b+24) byref REG NA /--* t828 byref N157 ( 4, 4) [000026] n---GO------ t26 = * IND ref REG r12 /--* t26 ref N159 ( 4, 4) [000028] DA--GO------ * STORE_LCL_VAR ref V05 loc1 d:1 r12 REG r12 N161 (???,???) [001345] ------------ IL_OFFSET void IL offset: 0x48 REG NA N163 ( 1, 1) [000029] ------------ t29 = LCL_VAR ref V05 loc1 u:1 r12 REG r12 N165 ( 1, 1) [000030] -c---------- t30 = CNS_INT ref null REG NA $VN.Null /--* t29 ref +--* t30 ref N167 ( 3, 3) [000031] J------N---- * EQ void REG NA N169 ( 5, 5) [000032] ------------ * JTRUE void REG NA ------------ BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} N173 (???,???) [001346] ------------ IL_OFFSET void IL offset: 0x4b REG NA N175 ( 1, 1) [000486] !----------- t486 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t486 ref N177 ( 3, 2) [000487] #----O------ t487 = * IND long REG rcx $2e8 /--* t487 long N179 ( 3, 3) [000489] DA---O------ * STORE_LCL_VAR long V29 tmp15 d:1 rcx REG rcx N181 ( 1, 1) [000491] ------------ t491 = LCL_VAR long V29 tmp15 u:1 rcx REG rcx $2e7 /--* t491 long N183 ( 2, 2) [000493] -c---------- t493 = * LEA(b+56) long REG NA /--* t493 long N185 ( 4, 4) [000494] #----------- t494 = * IND long REG rdx $2e9 /--* t494 long N187 ( 7, 6) [000495] #----------- t495 = * IND long REG rdx $2ea /--* t495 long N189 ( 8, 7) [000497] -c---------- t497 = * LEA(b+64) long REG NA /--* t497 long N191 ( 10, 9) [000501] n----------- t501 = * IND long REG r11 /--* t501 long N193 ( 14, 12) [001266] DA---------- * STORE_LCL_VAR long V68 cse3 d:1 r11 REG r11 N195 ( 3, 2) [001267] ------------ t1267 = LCL_VAR long V68 cse3 u:1 r11 REG r11 N197 ( 1, 1) [000504] -c---------- t504 = CNS_INT long 0 REG NA $243 /--* t1267 long +--* t504 long N199 ( 19, 16) [000505] J------N---- * EQ void REG NA N201 ( 21, 18) [001148] ------------ * JTRUE void REG NA ------------ BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} N205 ( 3, 2) [001269] ------------ t1269 = LCL_VAR long V68 cse3 u:1 r11 (last use) REG r11 /--* t1269 long N207 ( 3, 3) [001150] DA---------- * STORE_LCL_VAR long V31 tmp17 d:3 r11 REG r11 ------------ BB11 [???..???), preds={BB09} succs={BB12} N211 ( 1, 1) [000490] ------?----- t490 = LCL_VAR long V29 tmp15 u:1 rcx (last use) REG rcx $2e7 /--* t490 long N213 (???,???) [001461] ------------ t1461 = * PUTARG_REG long REG rcx N215 ( 2, 10) [000502] H-----?----- t502 = CNS_INT(h) long 0xd1ffab1e global ptr REG rdx $49 /--* t502 long N217 (???,???) [001462] ------------ t1462 = * PUTARG_REG long REG rdx /--* t1461 long arg0 in rcx +--* t1462 long arg1 in rdx N219 ( 17, 18) [000503] --C-G-?----- t503 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS REG rax $308 /--* t503 long N221 ( 17, 18) [001152] DA--G------- * STORE_LCL_VAR long V31 tmp17 d:2 r11 REG r11 ------------ BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} N001 ( 0, 0) [001247] ------------ t1247 = PHI_ARG long V31 tmp17 u:3 r11 N002 ( 0, 0) [001246] ------------ t1246 = PHI_ARG long V31 tmp17 u:2 r11 $308 /--* t1247 long +--* t1246 long N003 ( 0, 0) [001216] ------------ t1216 = * PHI long /--* t1216 long N005 ( 0, 0) [001217] DA---------- * STORE_LCL_VAR long V31 tmp17 d:1 r11 N225 ( 1, 1) [000484] ------------ t484 = LCL_VAR ref V05 loc1 u:1 r12 REG r12 /--* t484 ref N227 (???,???) [001463] ------------ t1463 = * PUTARG_REG ref REG rcx N229 ( 1, 1) [000831] ------------ t831 = LCL_VAR long V31 tmp17 u:1 r11 REG r11 $342 /--* t831 long N231 (???,???) [001464] ------------ t1464 = * PUTARG_REG long REG r11 N233 ( 1, 1) [000500] ------------ t500 = LCL_VAR ref V01 arg1 u:1 rdi REG rdi $101 /--* t500 ref N235 (???,???) [001465] ------------ t1465 = * PUTARG_REG ref REG rdx N237 ( 1, 1) [000521] ------------ t521 = LCL_VAR long V31 tmp17 u:1 r11 (last use) REG r11 $342 /--* t521 long N239 (???,???) [001466] Dc---------- t1466 = * IND long REG NA /--* t1463 ref this in rcx +--* t1464 long arg1 in r11 +--* t1465 ref arg2 in rdx +--* t1466 long calli tgt N241 ( 27, 12) [000522] --CXG------- t522 = * CALL ind stub int REG rax $1c7 /--* t522 int N243 ( 31, 15) [000524] DA-XG------- * STORE_LCL_VAR int V15 tmp1 d:3 r13 REG r13 ------------ BB13 [054..061), preds={BB08} succs={BB14} N247 (???,???) [001347] ------------ IL_OFFSET void IL offset: 0x54 REG NA N249 ( 1, 1) [000033] ------------ t33 = LCL_VAR ref V01 arg1 u:1 rdi REG rdi $101 /--* t33 ref N251 (???,???) [001467] ------------ t1467 = * PUTARG_REG ref REG rcx N253 ( 1, 1) [000836] ------------ t836 = LCL_VAR ref V01 arg1 u:1 rdi REG rdi $101 /--* t836 ref N255 ( 3, 2) [000837] #----O------ t837 = * IND long REG rax $2e4 /--* t837 long N257 ( 4, 3) [000839] -c---------- t839 = * LEA(b+72) long REG NA /--* t839 long N259 ( 6, 5) [000840] #----O------ t840 = * IND long REG rax $2e6 /--* t840 long N261 ( 7, 6) [000842] -c---------- t842 = * LEA(b+24) long REG NA /--* t842 long N263 ( 9, 8) [000843] nc---O------ t843 = * IND long REG NA /--* t1467 ref this in rcx +--* t843 long control expr N265 ( 30, 18) [000035] --CXGO------ t35 = * CALLV vt-ind int System.Object.GetHashCode REG rax $1c5 /--* t35 int N267 ( 34, 21) [000038] DA-XGO------ * STORE_LCL_VAR int V15 tmp1 d:2 r13 REG r13 ------------ BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} N001 ( 0, 0) [001245] ------------ t1245 = PHI_ARG int V15 tmp1 u:3 r13 $1c7 N002 ( 0, 0) [001244] ------------ t1244 = PHI_ARG int V15 tmp1 u:2 r13 $1c5 /--* t1245 int +--* t1244 int N003 ( 0, 0) [001213] ------------ t1213 = * PHI int /--* t1213 int N005 ( 0, 0) [001214] DA---------- * STORE_LCL_VAR int V15 tmp1 d:1 r13 N271 ( 3, 2) [000040] ------------ t40 = LCL_VAR int V15 tmp1 u:1 r13 (last use) REG r13 $3c0 /--* t40 int N273 ( 3, 3) [000042] DA---------- * STORE_LCL_VAR int V06 loc2 d:1 r13 REG r13 N275 (???,???) [001348] ------------ IL_OFFSET void IL offset: 0x62 REG NA N277 ( 1, 1) [000043] ------------ t43 = CNS_INT int 0 REG rax $c0 /--* t43 int N279 ( 1, 3) [000045] DA---------- * STORE_LCL_VAR int V07 loc3 d:1 NA REG NA N281 (???,???) [001349] ------------ IL_OFFSET void IL offset: 0x64 REG NA N283 ( 1, 1) [000046] ------------ t46 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t46 ref N285 ( 2, 2) [000845] -c---------- t845 = * LEA(b+8) byref REG NA /--* t845 byref N287 ( 4, 4) [000578] n---GO------ t578 = * IND ref REG r8 /--* t578 ref N289 ( 4, 4) [000580] DA--GO------ * STORE_LCL_VAR ref V39 tmp25 d:1 r8 REG r8 N291 (???,???) [001350] ------------ IL_OFFSET void IL offset: 0x64 REG NA N293 ( 1, 1) [000582] -----------Z t582 = LCL_VAR ref V39 tmp25 u:1 r8 REG r8 /--* t582 ref N295 (???,???) [001441] -c---------- t1441 = * LEA(b+8) ref REG NA /--* t1441 ref N297 ( 3, 3) [000583] ---X-------- t583 = * IND int REG r9 /--* t583 int N299 ( 3, 3) [000629] DA-X-------- * STORE_LCL_VAR int V40 tmp26 d:1 r9 REG r9 N301 (???,???) [001351] ------------ IL_OFFSET void IL offset: 0x64 REG NA N303 ( 1, 1) [000584] ------------ t584 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t584 ref N305 ( 2, 2) [000847] -c---------- t847 = * LEA(b+48) byref REG NA /--* t847 byref N307 ( 4, 4) [000585] n---GO------ t585 = * IND long REG r10 /--* t585 long N309 ( 4, 4) [000631] DA--GO------ * STORE_LCL_VAR long V41 tmp27 d:1 NA REG NA N311 (???,???) [001352] ------------ IL_OFFSET void IL offset: 0x64 REG NA N313 ( 1, 1) [000597] -----------Z t597 = LCL_VAR int V40 tmp26 u:1 r9 REG r9 N315 ( 1, 4) [000598] -c---------- t598 = CNS_INT int 0x7FFFFFFF REG NA $ce /--* t597 int +--* t598 int N317 ( 6, 6) [000599] N--------U-- t599 = * LE int REG rcx /--* t599 int N319 ( 6, 6) [000642] DA---------- * STORE_LCL_VAR int V43 tmp29 d:1 rcx REG rcx N321 (???,???) [001353] ------------ IL_OFFSET void IL offset: 0x64 REG NA N323 (???,???) [001354] ------------ IL_OFFSET void IL offset: 0x64 REG NA N325 ( 1, 1) [001297] ------------ t1297 = LCL_VAR ref V73 cse8 u:1 r14 REG r14 $105 /--* t1297 ref N327 ( 1, 3) [000654] DA--G------- * STORE_LCL_VAR ref V45 tmp31 d:1 rdx REG rdx N329 (???,???) [001355] ------------ IL_OFFSET void IL offset: 0x64 REG NA N331 ( 1, 1) [000644] ------------ t644 = LCL_VAR int V43 tmp29 u:1 rcx (last use) REG rcx N333 ( 1, 1) [000645] -c---------- t645 = CNS_INT int 0 REG NA $c0 /--* t644 int +--* t645 int N335 ( 3, 3) [000646] J------N---- * NE void REG NA N337 ( 5, 5) [000647] ------------ * JTRUE void REG NA ------------ BB15 [064..065), preds={BB14} succs={BB16} N341 (???,???) [001356] ------------ IL_OFFSET void IL offset: 0x64 REG NA N343 ( 1, 1) [000648] ------------ t648 = LCL_VAR ref V45 tmp31 u:1 rdx REG rdx $105 /--* t648 ref N345 (???,???) [001468] ------------ t1468 = * PUTARG_REG ref REG rcx N347 ( 1, 1) [000649] ------------ t649 = LCL_VAR ref V45 tmp31 u:1 rdx (last use) REG rdx $105 /--* t649 ref N349 (???,???) [001469] ------------ t1469 = * PUTARG_REG ref REG rdx /--* t1468 ref arg0 in rcx +--* t1469 ref arg1 in rdx N351 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail REG NA $VN.Void ------------ BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} N355 (???,???) [001357] ------------ IL_OFFSET void IL offset: 0x64 REG NA N357 ( 1, 1) [000604] -c---------- t604 = LCL_VAR long V41 tmp27 u:1 NA (last use) REG NA N359 ( 1, 1) [000047] ------------ t47 = LCL_VAR int V06 loc2 u:1 r13 REG r13 $3c0 /--* t47 int N361 ( 2, 3) [000605] ---------U-- t605 = * CAST long <- ulong <- uint REG rdx $310 /--* t604 long +--* t605 long N363 ( 7, 7) [000606] ------------ t606 = * MUL long REG rdx N365 ( 1, 1) [000607] -c---------- t607 = CNS_INT int 32 REG NA $d2 /--* t606 long +--* t607 int N367 ( 9, 9) [000608] ------------ t608 = * RSZ long REG rdx N369 ( 1, 1) [000610] -c---------- t610 = CNS_INT long 1 REG NA $247 /--* t608 long +--* t610 long N371 ( 11, 11) [000611] ------------ t611 = * ADD long REG rdx N373 ( 1, 1) [000612] -----------z t612 = LCL_VAR int V40 tmp26 u:1 r9 REG r9 /--* t612 int N375 ( 2, 3) [000613] ---------U-- t613 = * CAST long <- ulong <- uint REG rcx /--* t611 long +--* t613 long N377 ( 17, 17) [000614] ------------ t614 = * MUL long REG rdx N379 ( 1, 1) [000615] -c---------- t615 = CNS_INT int 32 REG NA $d2 /--* t614 long +--* t615 int N381 ( 19, 19) [000616] ------------ t616 = * RSZ long REG rdx /--* t616 long N383 ( 20, 21) [000617] ------------ t617 = * CAST int <- uint <- long REG r10 /--* t617 int N385 ( 20, 21) [000619] DA---------- * STORE_LCL_VAR int V42 tmp28 d:1 r10 REG r10 N387 (???,???) [001358] ------------ IL_OFFSET void IL offset: 0x64 REG NA N389 ( 1, 1) [000621] ------------ t621 = LCL_VAR int V06 loc2 u:1 r13 REG r13 $3c0 N391 ( 1, 1) [000622] ------------ t622 = LCL_VAR int V40 tmp26 u:1 r9 (last use) REG r9 /--* t621 int +--* t622 int N393 ( 22, 5) [000623] ---X-------- t623 = * UMOD int REG rdx N395 ( 1, 1) [000620] -----------Z t620 = LCL_VAR int V42 tmp28 u:1 r10 REG r10 /--* t623 int +--* t620 int N397 ( 27, 7) [000624] ---X-------- t624 = * EQ int REG rcx /--* t624 int N399 ( 27, 7) [000665] DA-X-------- * STORE_LCL_VAR int V46 tmp32 d:1 rcx REG rcx N401 (???,???) [001359] ------------ IL_OFFSET void IL offset: 0x64 REG NA N403 (???,???) [001360] ------------ IL_OFFSET void IL offset: 0x64 REG NA N405 ( 1, 1) [001299] ------------ t1299 = LCL_VAR ref V73 cse8 u:1 r14 REG r14 $105 /--* t1299 ref N407 ( 1, 3) [000677] DA--G------- * STORE_LCL_VAR ref V48 tmp34 d:1 rdx REG rdx N409 (???,???) [001361] ------------ IL_OFFSET void IL offset: 0x64 REG NA N411 ( 1, 1) [000667] ------------ t667 = LCL_VAR int V46 tmp32 u:1 rcx (last use) REG rcx N413 ( 1, 1) [000668] -c---------- t668 = CNS_INT int 0 REG NA $c0 /--* t667 int +--* t668 int N415 ( 3, 3) [000669] J------N---- * NE void REG NA N417 ( 5, 5) [000670] ------------ * JTRUE void REG NA ------------ BB17 [064..065), preds={BB16} succs={BB18} N421 (???,???) [001362] ------------ IL_OFFSET void IL offset: 0x64 REG NA N423 ( 1, 1) [000671] ------------ t671 = LCL_VAR ref V48 tmp34 u:1 rdx REG rdx $105 /--* t671 ref N425 (???,???) [001470] ------------ t1470 = * PUTARG_REG ref REG rcx N427 ( 1, 1) [000672] ------------ t672 = LCL_VAR ref V48 tmp34 u:1 rdx (last use) REG rdx $105 /--* t672 ref N429 (???,???) [001471] ------------ t1471 = * PUTARG_REG ref REG rdx /--* t1470 ref arg0 in rcx +--* t1471 ref arg1 in rdx N431 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail REG NA $VN.Void ------------ BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} N435 (???,???) [001363] ------------ IL_OFFSET void IL offset: 0x64 REG NA N437 ( 1, 1) [000627] -----------z t627 = LCL_VAR int V42 tmp28 u:1 r10 REG r10 N439 ( 1, 1) [000581] -----------z t581 = LCL_VAR ref V39 tmp25 u:1 r8 REG r8 /--* t581 ref N441 (???,???) [001443] -c---------- t1443 = * LEA(b+8) ref REG NA /--* t1443 ref N443 ( 3, 3) [000854] -c-X-------- t854 = * IND int REG NA /--* t627 int +--* t854 int N445 ( 8, 11) [000855] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void REG NA N447 ( 1, 1) [000852] ------------ t852 = LCL_VAR ref V39 tmp25 u:1 r8 (last use) REG r8 N449 ( 1, 1) [000853] ------------ t853 = LCL_VAR int V42 tmp28 u:1 r10 (last use) REG r10 /--* t853 int N451 ( 2, 3) [000856] ------------ t856 = * CAST long <- int REG rcx /--* t852 ref +--* t856 long N453 ( 5, 6) [000861] -------N---- t861 = * LEA(b+(i*4)+16) byref REG rax /--* t861 byref N455 ( 19, 24) [000591] DA-XG------- * STORE_LCL_VAR byref V38 tmp24 d:1 rax REG rax N457 ( 1, 1) [000592] ------------ t592 = LCL_VAR byref V38 tmp24 u:1 rax (last use) REG rax $81 /--* t592 byref N459 ( 5, 4) [000051] DA---------- * STORE_LCL_VAR byref V08 loc4 d:1 rax REG rax N461 (???,???) [001364] ------------ IL_OFFSET void IL offset: 0x6d REG NA N463 ( 1, 1) [000052] -----------Z t52 = LCL_VAR byref V08 loc4 u:1 rax REG rax $81 /--* t52 byref N465 ( 3, 2) [000053] *--XG------- t53 = * IND int REG r8 N467 ( 1, 1) [000054] -c---------- t54 = CNS_INT int -1 REG NA $c4 /--* t53 int +--* t54 int N469 ( 5, 4) [000055] ---XG------- t55 = * ADD int REG r8 /--* t55 int N471 ( 5, 4) [000057] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:1 NA REG NA N473 (???,???) [001365] ------------ IL_OFFSET void IL offset: 0x74 REG NA N475 ( 1, 1) [000058] ------------ t58 = LCL_VAR ref V05 loc1 u:1 r12 REG r12 N477 ( 1, 1) [000059] -c---------- t59 = CNS_INT ref null REG NA $VN.Null /--* t58 ref +--* t59 ref N479 ( 3, 3) [000060] J------N---- * NE void REG NA N481 ( 5, 5) [000061] ------------ * JTRUE void REG NA ------------ BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} N485 (???,???) [001366] ------------ IL_OFFSET void IL offset: 0xff REG NA N487 ( 1, 1) [000353] !----------- t353 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t353 ref N489 ( 3, 2) [000354] #----O------ t354 = * IND long REG rcx $2e8 /--* t354 long N491 ( 3, 3) [000356] DA---O------ * STORE_LCL_VAR long V24 tmp10 d:1 rcx REG rcx N493 ( 1, 1) [000358] ------------ t358 = LCL_VAR long V24 tmp10 u:1 rcx REG rcx $2e7 /--* t358 long N495 ( 2, 2) [000360] -c---------- t360 = * LEA(b+56) long REG NA /--* t360 long N497 ( 4, 4) [000361] #----------- t361 = * IND long REG rdx $2e9 /--* t361 long N499 ( 7, 6) [000362] #----------- t362 = * IND long REG rdx $2ea /--* t362 long N501 ( 8, 7) [000364] -c---------- t364 = * LEA(b+32) long REG NA /--* t364 long N503 ( 10, 9) [000365] n----------- t365 = * IND long REG rdx /--* t365 long N505 ( 14, 12) [001271] DA---------- * STORE_LCL_VAR long V69 cse4 d:1 rdx REG rdx N507 ( 3, 2) [001272] ------------ t1272 = LCL_VAR long V69 cse4 u:1 rdx REG rdx N509 ( 1, 1) [000368] -c---------- t368 = CNS_INT long 0 REG NA $243 /--* t1272 long +--* t368 long N511 ( 19, 16) [000369] J------N---- * EQ void REG NA N513 ( 21, 18) [001153] ------------ * JTRUE void REG NA ------------ BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} N517 ( 3, 2) [001274] ------------ t1274 = LCL_VAR long V69 cse4 u:1 rdx (last use) REG rdx /--* t1274 long N519 ( 7, 5) [001155] DA---------- * STORE_LCL_VAR long V25 tmp11 d:3 rdx REG rdx ------------ BB21 [???..???), preds={BB19} succs={BB22} N523 ( 1, 1) [000357] ------?----- t357 = LCL_VAR long V24 tmp10 u:1 rcx (last use) REG rcx $2e7 /--* t357 long N525 (???,???) [001472] ------------ t1472 = * PUTARG_REG long REG rcx N527 ( 2, 10) [000366] H-----?----- t366 = CNS_INT(h) long 0xd1ffab1e global ptr REG rdx $4f /--* t366 long N529 (???,???) [001473] ------------ t1473 = * PUTARG_REG long REG rdx /--* t1472 long arg0 in rcx +--* t1473 long arg1 in rdx N531 ( 17, 18) [000367] --C-G-?----- t367 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS REG rax $325 /--* t367 long N533 ( 21, 21) [001157] DA--G------- * STORE_LCL_VAR long V25 tmp11 d:2 rdx REG rdx ------------ BB22 [???..106), preds={BB20,BB21} succs={BB23} N001 ( 0, 0) [001243] ------------ t1243 = PHI_ARG long V25 tmp11 u:3 rdx N002 ( 0, 0) [001242] ------------ t1242 = PHI_ARG long V25 tmp11 u:2 rdx $325 /--* t1243 long +--* t1242 long N003 ( 0, 0) [001198] ------------ t1198 = * PHI long /--* t1198 long N005 ( 0, 0) [001199] DA---------- * STORE_LCL_VAR long V25 tmp11 d:1 rdx N537 ( 3, 2) [000382] ------------ t382 = LCL_VAR long V25 tmp11 u:1 rdx (last use) REG rdx $344 /--* t382 long N539 (???,???) [001474] ------------ t1474 = * PUTARG_REG long REG rcx /--* t1474 long arg0 in rcx N541 ( 17, 8) [000352] --CXG------- t352 = * CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default REG rax $223 /--* t352 ref N543 ( 17, 8) [000386] DA-XG------- * STORE_LCL_VAR ref V12 loc8 d:1 rax REG rax ------------ BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} N001 ( 0, 0) [001238] ------------ t1238 = PHI_ARG int V07 loc3 u:6 N002 ( 0, 0) [001235] ------------ t1235 = PHI_ARG int V07 loc3 u:1 $c0 /--* t1238 int +--* t1235 int N003 ( 0, 0) [001177] ------------ t1177 = * PHI int /--* t1177 int N005 ( 0, 0) [001178] DA---------- * STORE_LCL_VAR int V07 loc3 d:5 N001 ( 0, 0) [001239] ------------ t1239 = PHI_ARG int V09 loc5 u:5 N002 ( 0, 0) [001236] ------------ t1236 = PHI_ARG int V09 loc5 u:1 /--* t1239 int +--* t1236 int N003 ( 0, 0) [001174] ------------ t1174 = * PHI int /--* t1174 int N005 ( 0, 0) [001175] DA---------- * STORE_LCL_VAR int V09 loc5 d:4 N547 (???,???) [001367] ------------ IL_OFFSET void IL offset: 0x106 REG NA N549 ( 1, 1) [000388] ------------ t388 = LCL_VAR ref V04 loc0 u:1 r15 REG r15 /--* t388 ref N551 (???,???) [001446] -c---------- t1446 = * LEA(b+8) ref REG NA /--* t1446 ref N553 ( 3, 3) [000389] ---X-------- t389 = * IND int REG r9 /--* t389 int N555 ( 3, 3) [001316] DA-X-------- * STORE_LCL_VAR int V76 cse11 r9 REG r9 N557 ( 1, 1) [001317] -----------Z t1317 = LCL_VAR int V76 cse11 r9 REG r9 N559 ( 1, 1) [000387] -----------z t387 = LCL_VAR int V09 loc5 u:4 r10 REG r10 $3c2 /--* t1317 int +--* t387 int N561 ( 6, 6) [000390] N--X---N-U-- * LE void REG NA N563 ( 8, 8) [000391] ---X-------- * JTRUE void REG NA ------------ BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} N567 (???,???) [001368] ------------ IL_OFFSET void IL offset: 0x110 REG NA N569 ( 1, 1) [000869] ------------ t869 = LCL_VAR ref V04 loc0 u:1 r15 REG r15 N571 ( 1, 1) [000870] ------------ t870 = LCL_VAR int V09 loc5 u:4 r10 (last use) REG r10 $3c2 /--* t870 int N573 ( 2, 3) [000873] ------------ t873 = * CAST long <- int REG rdx $326 N575 ( 1, 1) [000880] -c---------- t880 = CNS_INT long 3 REG NA $24b /--* t873 long +--* t880 long N577 ( 7, 7) [000881] ------------ t881 = * MUL long REG rdx $327 /--* t881 long N579 ( 7, 7) [001276] DA---------- * STORE_LCL_VAR long V70 cse5 d:1 rdx REG rdx N581 ( 1, 1) [001277] ------------ t1277 = LCL_VAR long V70 cse5 u:1 rdx REG rdx $327 /--* t869 ref +--* t1277 long N583 ( 11, 11) [000878] -------N---- t878 = * LEA(b+(i*8)+16) byref REG r11 /--* t878 byref N585 ( 23, 23) [001249] DA--G------- * STORE_LCL_VAR byref V65 cse0 d:1 r11 REG r11 N587 ( 1, 1) [001250] -----------Z t1250 = LCL_VAR byref V65 cse0 u:1 r11 REG r11 /--* t1250 byref N589 ( 25, 25) [000868] -c---------- t868 = * LEA(b+16) byref REG NA /--* t868 byref N591 ( 27, 27) [000396] *c-XG------- t396 = * IND int REG NA N593 ( 1, 1) [000397] ------------ t397 = LCL_VAR int V06 loc2 u:1 r13 REG r13 $3c0 /--* t396 int +--* t397 int N595 ( 29, 29) [000398] N--XG--N-U-- * NE void REG NA N597 ( 31, 31) [000399] ---XG------- * JTRUE void REG NA ------------ BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} N601 (???,???) [001369] ------------ IL_OFFSET void IL offset: 0x120 REG NA N603 ( 1, 1) [000883] ------------ t883 = LCL_VAR ref V04 loc0 u:1 r15 REG r15 N605 ( 1, 1) [001279] ------------ t1279 = LCL_VAR long V70 cse5 u:1 rdx (last use) REG rdx $327 /--* t883 ref +--* t1279 long N607 ( 4, 4) [000892] -c---------- t892 = * LEA(b+(i*8)+16) byref REG NA /--* t892 byref N609 ( 12, 11) [000897] *---G--N---- t897 = * IND ref REG rdx /--* t897 ref N611 (???,???) [001475] ----G------- t1475 = * PUTARG_REG ref REG rdx N613 ( 1, 1) [000418] ------------ t418 = LCL_VAR ref V12 loc8 u:1 rax REG rax $223 /--* t418 ref N615 (???,???) [001476] ------------ t1476 = * PUTARG_REG ref REG rcx N617 ( 1, 1) [000424] ------------ t424 = LCL_VAR ref V01 arg1 u:1 rdi REG rdi $101 /--* t424 ref N619 (???,???) [001477] ------------ t1477 = * PUTARG_REG ref REG r8 N621 ( 1, 1) [000901] -----------Z t901 = LCL_VAR ref V12 loc8 u:1 rax REG rax $223 /--* t901 ref N623 ( 3, 2) [000902] #--X-------- t902 = * IND long REG r10 $463 /--* t902 long N625 ( 4, 3) [000904] -c---------- t904 = * LEA(b+72) long REG NA /--* t904 long N627 ( 6, 5) [000905] #--X-------- t905 = * IND long REG r10 $465 /--* t905 long N629 ( 7, 6) [000907] -c---------- t907 = * LEA(b+32) long REG NA /--* t907 long N631 ( 9, 8) [000908] nc-X-------- t908 = * IND long REG NA /--* t1475 ref arg1 in rdx +--* t1476 ref this in rcx +--* t1477 ref arg2 in r8 +--* t908 long control expr N633 ( 43, 32) [000425] --CXG------- t425 = * CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals REG rax $581 N635 ( 1, 1) [000426] -c---------- t426 = CNS_INT int 0 REG NA $c0 /--* t425 int +--* t426 int N637 ( 45, 34) [000427] J--XG--N---- * NE void REG NA $1bd N001 ( 1, 1) [001509] -----------z t1509 = LCL_VAR ref V12 loc8 rax REG rax N639 ( 47, 36) [000428] ---XG------- * JTRUE void REG NA ------------ BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} N643 (???,???) [001370] ------------ IL_OFFSET void IL offset: 0x157 REG NA N645 ( 1, 1) [001252] -----------z t1252 = LCL_VAR byref V65 cse0 u:1 r11 (last use) REG r11 $82 /--* t1252 byref N647 ( 2, 2) [000932] -c---------- t932 = * LEA(b+20) byref REG NA /--* t932 byref N649 ( 4, 4) [000404] *--XG------- t404 = * IND int REG r10 /--* t404 int N651 ( 4, 4) [000406] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:5 r8 REG r8 N653 (???,???) [001371] ------------ IL_OFFSET void IL offset: 0x166 REG NA N655 ( 1, 1) [000407] -----------z t407 = LCL_VAR int V07 loc3 u:5 r11 (last use) REG r11 $3c1 N657 ( 1, 1) [000408] -c---------- t408 = CNS_INT int 1 REG NA $c1 /--* t407 int +--* t408 int N659 ( 3, 3) [000409] ------------ t409 = * ADD int REG r11 $605 /--* t409 int N661 ( 3, 3) [000411] DA---------- * STORE_LCL_VAR int V07 loc3 d:6 r11 REG r11 N663 (???,???) [001372] ------------ IL_OFFSET void IL offset: 0x16a REG NA N665 ( 1, 1) [001321] -c---------- t1321 = LCL_VAR int V76 cse11 NA (last use) REG NA N667 ( 1, 1) [000412] ------------ t412 = LCL_VAR int V07 loc3 u:6 r11 REG r11 $605 /--* t1321 int +--* t412 int N669 ( 3, 3) [000415] N------N-U-- * LT void REG NA N671 ( 5, 5) [000416] ------------ * JTRUE void REG NA ------------ BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} N001 ( 1, 1) [001510] -----------Z t1510 = LCL_VAR int V07 loc3 r11 REG r11 N001 ( 1, 1) [001511] -----------Z t1511 = LCL_VAR int V09 loc5 r8 REG r8 ------------ BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} N677 (???,???) [001373] ------------ IL_OFFSET void IL offset: 0x137 REG NA N679 ( 2, 2) [000429] ------------ t429 = LCL_VAR ubyte V03 arg3 u:1 rbx REG rbx $140 N681 ( 1, 1) [000430] -c---------- t430 = CNS_INT ubyte 1 REG NA $c1 /--* t429 ubyte +--* t430 ubyte N683 ( 5, 6) [000431] N------N-U-- * NE void REG NA $1bf N685 ( 7, 8) [000432] ------------ * JTRUE void REG NA ------------ BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} N689 (???,???) [001374] ------------ IL_OFFSET void IL offset: 0x13b REG NA N691 ( 1, 1) [001253] -----------z t1253 = LCL_VAR byref V65 cse0 u:1 r11 (last use) REG r11 $82 /--* t1253 byref N693 ( 2, 2) [000911] ------------ t911 = * LEA(b+8) byref REG rcx N695 ( 1, 1) [000479] ------------ t479 = LCL_VAR ref V02 arg2 u:1 rbp (last use) REG rbp $102 /--* t911 byref +--* t479 ref N697 (???,???) [001375] -A-XG------- * STOREIND ref REG NA ------------ BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} N701 (???,???) [001376] ------------ IL_OFFSET void IL offset: 0x14b REG NA N703 ( 2, 2) [000433] ------------ t433 = LCL_VAR ubyte V03 arg3 u:1 rbx (last use) REG rbx $140 N705 ( 1, 1) [000434] -c---------- t434 = CNS_INT ubyte 2 REG NA $c2 /--* t433 ubyte +--* t434 ubyte N707 ( 5, 6) [000435] N------N-U-- * EQ void REG NA $600 N709 ( 7, 8) [000436] ------------ * JTRUE void REG NA ------------ BB31 [???..???) (return), preds={BB30,BB41} succs={} N713 ( 1, 1) [000437] ------------ t437 = CNS_INT int 0 REG rax $c0 /--* t437 int N715 ( 2, 2) [000811] ------------ * RETURN int REG NA $1f3 ------------ BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} N001 ( 0, 0) [001229] ------------ t1229 = PHI_ARG int V07 loc3 u:4 N002 ( 0, 0) [001218] ------------ t1218 = PHI_ARG int V07 loc3 u:1 $c0 /--* t1229 int +--* t1218 int N003 ( 0, 0) [001207] ------------ t1207 = * PHI int /--* t1207 int N005 ( 0, 0) [001208] DA---------- * STORE_LCL_VAR int V07 loc3 d:3 N001 ( 0, 0) [001230] ------------ t1230 = PHI_ARG int V09 loc5 u:3 N002 ( 0, 0) [001219] ------------ t1219 = PHI_ARG int V09 loc5 u:1 /--* t1230 int +--* t1219 int N003 ( 0, 0) [001204] ------------ t1204 = * PHI int /--* t1204 int N005 ( 0, 0) [001205] DA---------- * STORE_LCL_VAR int V09 loc5 d:2 N719 (???,???) [001377] ------------ IL_OFFSET void IL offset: 0x177 REG NA N721 ( 1, 1) [000063] ------------ t63 = LCL_VAR ref V04 loc0 u:1 r15 REG r15 /--* t63 ref N723 (???,???) [001448] -c---------- t1448 = * LEA(b+8) ref REG NA /--* t1448 ref N725 ( 3, 3) [000064] ---X-------- t64 = * IND int REG r9 /--* t64 int N727 ( 3, 3) [001323] DA-X-------- * STORE_LCL_VAR int V76 cse11 r9 REG r9 N729 ( 1, 1) [001324] -----------Z t1324 = LCL_VAR int V76 cse11 r9 REG r9 N731 ( 1, 1) [000062] -----------z t62 = LCL_VAR int V09 loc5 u:2 r8 REG r8 $3c4 /--* t1324 int +--* t62 int N733 ( 6, 6) [000065] N--X---N-U-- * LE void REG NA N735 ( 8, 8) [000066] ---X-------- * JTRUE void REG NA ------------ BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} N739 (???,???) [001378] ------------ IL_OFFSET void IL offset: 0x17e REG NA N741 ( 1, 1) [000949] ------------ t949 = LCL_VAR ref V04 loc0 u:1 r15 REG r15 N743 ( 1, 1) [000950] ------------ t950 = LCL_VAR int V09 loc5 u:2 r8 (last use) REG r8 $3c4 /--* t950 int N745 ( 2, 3) [000953] ------------ t953 = * CAST long <- int REG rcx $6e1 N747 ( 1, 1) [000960] -c---------- t960 = CNS_INT long 3 REG NA $24b /--* t953 long +--* t960 long N749 ( 7, 7) [000961] ------------ t961 = * MUL long REG rcx $6e2 /--* t961 long N751 ( 7, 7) [001281] DA---------- * STORE_LCL_VAR long V71 cse6 d:1 rcx REG rcx N753 ( 1, 1) [001282] ------------ t1282 = LCL_VAR long V71 cse6 u:1 rcx REG rcx $6e2 /--* t949 ref +--* t1282 long N755 ( 11, 11) [000958] -------N---- t958 = * LEA(b+(i*8)+16) byref REG r8 /--* t958 byref N757 ( 23, 23) [001255] DA--G------- * STORE_LCL_VAR byref V66 cse1 d:1 r8 REG r8 N759 ( 1, 1) [001256] -----------Z t1256 = LCL_VAR byref V66 cse1 u:1 r8 REG r8 /--* t1256 byref N761 ( 25, 25) [000948] -c---------- t948 = * LEA(b+16) byref REG NA /--* t948 byref N763 ( 27, 27) [000212] *c-XG------- t212 = * IND int REG NA N765 ( 1, 1) [000213] ------------ t213 = LCL_VAR int V06 loc2 u:1 r13 REG r13 $3c0 /--* t212 int +--* t213 int N767 ( 29, 29) [000214] N--XG--N-U-- * NE void REG NA N769 ( 31, 31) [000215] ---XG------- * JTRUE void REG NA ------------ BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} N773 (???,???) [001379] ------------ IL_OFFSET void IL offset: 0x18e REG NA N775 ( 1, 1) [000963] ------------ t963 = LCL_VAR ref V04 loc0 u:1 r15 REG r15 N777 ( 1, 1) [001284] ------------ t1284 = LCL_VAR long V71 cse6 u:1 rcx (last use) REG rcx $6e2 /--* t963 ref +--* t1284 long N779 ( 4, 4) [000972] -c---------- t972 = * LEA(b+(i*8)+16) byref REG NA /--* t972 byref N781 ( 12, 11) [000977] *---G--N---- t977 = * IND ref REG r10 /--* t977 ref N783 ( 12, 11) [000246] DA--G------- * STORE_LCL_VAR ref V17 tmp3 d:1 NA REG NA N785 (???,???) [001380] ------------ IL_OFFSET void IL offset: 0x18e REG NA N787 ( 1, 1) [000241] !----------- t241 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t241 ref N789 ( 3, 2) [000242] #----O------ t242 = * IND long REG rcx $2e8 /--* t242 long N791 ( 3, 3) [000244] DA---O------ * STORE_LCL_VAR long V16 tmp2 d:1 rcx REG rcx N793 ( 1, 1) [000249] ------------ t249 = LCL_VAR long V16 tmp2 u:1 rcx REG rcx $2e7 /--* t249 long N795 ( 2, 2) [000251] -c---------- t251 = * LEA(b+56) long REG NA /--* t251 long N797 ( 4, 4) [000252] #----------- t252 = * IND long REG rdx $2e9 /--* t252 long N799 ( 7, 6) [000253] #----------- t253 = * IND long REG rdx $2ea /--* t253 long N801 ( 8, 7) [000255] -c---------- t255 = * LEA(b+48) long REG NA /--* t255 long N803 ( 10, 9) [000259] n----------- t259 = * IND long REG r11 /--* t259 long N805 ( 10, 9) [001261] DA---------- * STORE_LCL_VAR long V67 cse2 d:1 r11 REG r11 N807 ( 1, 1) [001262] ------------ t1262 = LCL_VAR long V67 cse2 u:1 r11 REG r11 N809 ( 1, 1) [000262] -c---------- t262 = CNS_INT long 0 REG NA $243 /--* t1262 long +--* t262 long N811 ( 13, 12) [000263] J------N---- * EQ void REG NA N813 ( 15, 14) [001163] ------------ * JTRUE void REG NA ------------ BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} N001 ( 1, 1) [001512] -----------z t1512 = LCL_VAR ref V17 tmp3 r10 REG r10 N817 ( 1, 1) [001264] ------------ t1264 = LCL_VAR long V67 cse2 u:1 r11 (last use) REG r11 /--* t1264 long N819 ( 1, 3) [001165] DA---------- * STORE_LCL_VAR long V19 tmp5 d:3 r11 REG r11 ------------ BB36 [???..???), preds={BB34} succs={BB37} N823 ( 1, 1) [000248] ------?----- t248 = LCL_VAR long V16 tmp2 u:1 rcx (last use) REG rcx $2e7 /--* t248 long N825 (???,???) [001478] ------------ t1478 = * PUTARG_REG long REG rcx N827 ( 2, 10) [000260] H-----?----- t260 = CNS_INT(h) long 0xd1ffab1e global ptr REG rdx $63 /--* t260 long N829 (???,???) [001479] ------------ t1479 = * PUTARG_REG long REG rdx /--* t1478 long arg0 in rcx +--* t1479 long arg1 in rdx N831 ( 17, 18) [000261] --C-G-?----- t261 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS REG rax $6e7 /--* t261 long N833 ( 17, 18) [001167] DA--G------- * STORE_LCL_VAR long V19 tmp5 d:2 r11 REG r11 N001 ( 1, 1) [001513] -----------z t1513 = LCL_VAR ref V17 tmp3 r10 REG r10 ------------ BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} N001 ( 0, 0) [001234] ------------ t1234 = PHI_ARG long V19 tmp5 u:3 r11 N002 ( 0, 0) [001233] ------------ t1233 = PHI_ARG long V19 tmp5 u:2 r11 $6e7 /--* t1234 long +--* t1233 long N003 ( 0, 0) [001210] ------------ t1210 = * PHI long /--* t1210 long N005 ( 0, 0) [001211] DA---------- * STORE_LCL_VAR long V19 tmp5 d:1 r11 N837 ( 1, 1) [000234] ------------ t234 = LCL_VAR ref V05 loc1 u:1 r12 REG r12 /--* t234 ref N839 (???,???) [001480] ------------ t1480 = * PUTARG_REG ref REG rcx N841 ( 1, 1) [000980] ------------ t980 = LCL_VAR long V19 tmp5 u:1 r11 REG r11 $349 /--* t980 long N843 (???,???) [001481] ------------ t1481 = * PUTARG_REG long REG r11 N845 ( 1, 1) [000247] ------------ t247 = LCL_VAR ref V17 tmp3 u:1 r10 (last use) REG r10 /--* t247 ref N847 (???,???) [001482] ------------ t1482 = * PUTARG_REG ref REG rdx N849 ( 1, 1) [000258] ------------ t258 = LCL_VAR ref V01 arg1 u:1 rdi REG rdi $101 /--* t258 ref N851 (???,???) [001483] ------------ t1483 = * PUTARG_REG ref REG r8 N853 ( 1, 1) [000279] ------------ t279 = LCL_VAR long V19 tmp5 u:1 r11 (last use) REG r11 $349 /--* t279 long N855 (???,???) [001484] Dc---------- t1484 = * IND long REG NA /--* t1480 ref this in rcx +--* t1481 long arg1 in r11 +--* t1482 ref arg2 in rdx +--* t1483 ref arg3 in r8 +--* t1484 long calli tgt N857 ( 28, 14) [000280] --CXG------- t280 = * CALL ind stub int REG rax $1ef N859 ( 1, 1) [000281] -c---------- t281 = CNS_INT int 0 REG NA $c0 /--* t280 int +--* t281 int N861 ( 30, 16) [000282] J--XG--N---- * EQ void REG NA $817 N863 ( 32, 18) [000283] ---XG------- * JTRUE void REG NA ------------ BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} N867 (???,???) [001381] ------------ IL_OFFSET void IL offset: 0x1a4 REG NA N869 ( 2, 2) [000284] ------------ t284 = LCL_VAR ubyte V03 arg3 u:1 rbx REG rbx $140 N871 ( 1, 1) [000285] -c---------- t285 = CNS_INT ubyte 1 REG NA $c1 /--* t284 ubyte +--* t285 ubyte N873 ( 5, 6) [000286] N------N-U-- * NE void REG NA $1bf N875 ( 7, 8) [000287] ------------ * JTRUE void REG NA ------------ BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} N879 (???,???) [001382] ------------ IL_OFFSET void IL offset: 0x1a8 REG NA N881 ( 1, 1) [001258] -----------z t1258 = LCL_VAR byref V66 cse1 u:1 r15 (last use) REG r15 $91 /--* t1258 byref N883 ( 2, 2) [000987] ------------ t987 = * LEA(b+8) byref REG rcx N885 ( 1, 1) [000334] ------------ t334 = LCL_VAR ref V02 arg2 u:1 rbp (last use) REG rbp $102 /--* t987 byref +--* t334 ref N887 (???,???) [001383] -A-XG------- * STOREIND ref REG NA ------------ BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} N891 (???,???) [001384] ------------ IL_OFFSET void IL offset: 0x1b8 REG NA N893 ( 2, 2) [000288] ------------ t288 = LCL_VAR ubyte V03 arg3 u:1 rbx (last use) REG rbx $140 N895 ( 1, 1) [000289] -c---------- t289 = CNS_INT ubyte 2 REG NA $c2 /--* t288 ubyte +--* t289 ubyte N897 ( 5, 6) [000290] N------N-U-- * EQ void REG NA $600 N899 ( 7, 8) [000291] ------------ * JTRUE void REG NA ------------ BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} ------------ BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} N905 (???,???) [001385] ------------ IL_OFFSET void IL offset: 0x1c4 REG NA N907 ( 1, 1) [001259] -----------z t1259 = LCL_VAR byref V66 cse1 u:1 r8 (last use) REG r8 $91 /--* t1259 byref N909 ( 2, 2) [001009] -c---------- t1009 = * LEA(b+20) byref REG NA /--* t1009 byref N911 ( 4, 4) [000220] *--XG------- t220 = * IND int REG r8 /--* t220 int N913 ( 4, 4) [000222] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:3 rcx REG rcx N915 (???,???) [001386] ------------ IL_OFFSET void IL offset: 0x1d3 REG NA N917 ( 1, 1) [000223] -----------z t223 = LCL_VAR int V07 loc3 u:3 r8 (last use) REG r8 $3c3 N919 ( 1, 1) [000224] -c---------- t224 = CNS_INT int 1 REG NA $c1 /--* t223 int +--* t224 int N921 ( 3, 3) [000225] ------------ t225 = * ADD int REG r8 $81a /--* t225 int N923 ( 3, 3) [000227] DA---------- * STORE_LCL_VAR int V07 loc3 d:4 r8 REG r8 N925 (???,???) [001387] ------------ IL_OFFSET void IL offset: 0x1d7 REG NA N927 ( 1, 1) [001328] -c---------- t1328 = LCL_VAR int V76 cse11 NA (last use) REG NA N929 ( 1, 1) [000228] -----------Z t228 = LCL_VAR int V07 loc3 u:4 r8 REG r8 $81a /--* t1328 int +--* t228 int N931 ( 3, 3) [000231] N------N-U-- * LT void REG NA N933 ( 5, 5) [000232] ------------ * JTRUE void REG NA ------------ BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} N001 ( 1, 1) [001514] -----------Z t1514 = LCL_VAR int V09 loc5 rcx REG rcx ------------ BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} N001 ( 0, 0) [001237] ------------ t1237 = PHI_ARG int V07 loc3 u:5 $3c1 N002 ( 0, 0) [001228] ------------ t1228 = PHI_ARG int V07 loc3 u:3 $3c3 /--* t1237 int +--* t1228 int N003 ( 0, 0) [001180] ------------ t1180 = * PHI int /--* t1180 int N005 ( 0, 0) [001181] DA---------- * STORE_LCL_VAR int V07 loc3 d:2 N939 (???,???) [001388] ------------ IL_OFFSET void IL offset: 0x1e4 REG NA N941 ( 1, 1) [000067] ------------ t67 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t67 ref N943 ( 2, 2) [001025] -c---------- t1025 = * LEA(b+64) byref REG NA /--* t1025 byref N945 ( 4, 4) [000068] nc--GO------ t68 = * IND int REG NA N947 ( 1, 1) [000069] -c---------- t69 = CNS_INT int 0 REG NA $c0 /--* t68 int +--* t69 int N949 ( 6, 6) [000070] J---GO-N---- * LE void REG NA N951 ( 8, 8) [000071] ----GO------ * JTRUE void REG NA ------------ BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} N955 (???,???) [001389] ------------ IL_OFFSET void IL offset: 0x1ed REG NA N957 ( 1, 1) [000171] ------------ t171 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t171 ref N959 ( 2, 2) [001027] -c---------- t1027 = * LEA(b+60) byref REG NA /--* t1027 byref N961 ( 4, 4) [000172] n---GO------ t172 = * IND int REG rcx /--* t172 int N963 ( 8, 7) [001306] DA--GO------ * STORE_LCL_VAR int V74 cse9 d:1 rcx REG rcx N965 ( 3, 2) [001307] ------------ t1307 = LCL_VAR int V74 cse9 u:1 rcx REG rcx /--* t1307 int N967 ( 15, 12) [000174] DA--GO------ * STORE_LCL_VAR int V10 loc6 d:3 rbx REG rbx N969 (???,???) [001390] ------------ IL_OFFSET void IL offset: 0x1f5 REG NA N971 ( 3, 2) [001309] ------------ t1309 = LCL_VAR int V74 cse9 u:1 rcx (last use) REG rcx /--* t1309 int N973 ( 3, 3) [001032] DA--G------- * STORE_LCL_VAR int V62 tmp48 d:1 rcx REG rcx N975 ( 1, 1) [001033] ------------ t1033 = LCL_VAR int V62 tmp48 u:1 rcx REG rcx N977 ( 1, 1) [001329] -c---------- t1329 = LCL_VAR int V76 cse11 NA REG NA /--* t1033 int +--* t1329 int N979 ( 6, 9) [001036] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void REG NA N981 ( 1, 1) [001030] ------------ t1030 = LCL_VAR ref V04 loc0 u:1 r15 REG r15 N983 ( 1, 1) [001034] ------------ t1034 = LCL_VAR int V62 tmp48 u:1 rcx (last use) REG rcx /--* t1034 int N985 ( 2, 3) [001037] ------------ t1037 = * CAST long <- int REG rcx N987 ( 1, 1) [001047] -c---------- t1047 = CNS_INT long 3 REG NA $24b /--* t1037 long +--* t1047 long N989 ( 7, 7) [001048] ------------ t1048 = * MUL long REG rcx /--* t1030 ref +--* t1048 long N991 ( 31, 34) [001029] -c---------- t1029 = * LEA(b+(i*8)+36) byref REG NA /--* t1029 byref N993 ( 33, 36) [000181] *--XG------- t181 = * IND int REG rcx /--* t181 int N995 ( 34, 37) [001050] ---XG------- t1050 = * NEG int REG rcx N997 ( 1, 1) [000175] -c---------- t175 = CNS_INT int -3 REG NA $e1 /--* t1050 int +--* t175 int N999 ( 36, 39) [000182] ---XG------- t182 = * ADD int REG rcx N1001 ( 1, 1) [000183] -c---------- t183 = CNS_INT int -1 REG NA $c4 /--* t182 int +--* t183 int N1003 ( 41, 41) [000184] ---XG------- t184 = * GE int REG rcx /--* t184 int N1005 ( 45, 44) [000688] DA-XG------- * STORE_LCL_VAR int V49 tmp35 d:1 rcx REG rcx N1007 (???,???) [001391] ------------ IL_OFFSET void IL offset: 0x1f5 REG NA N1009 ( 1, 1) [001300] ------------ t1300 = LCL_VAR ref V73 cse8 u:1 r14 (last use) REG r14 $105 /--* t1300 ref N1011 ( 5, 4) [000698] DA--G------- * STORE_LCL_VAR ref V50 tmp36 d:1 rdx REG rdx N1013 (???,???) [001392] ------------ IL_OFFSET void IL offset: 0x1f5 REG NA N1015 ( 3, 2) [000690] ------------ t690 = LCL_VAR int V49 tmp35 u:1 rcx (last use) REG rcx N1017 ( 1, 1) [000691] -c---------- t691 = CNS_INT int 0 REG NA $c0 /--* t690 int +--* t691 int N1019 ( 5, 4) [000692] J------N---- * NE void REG NA N1021 ( 7, 6) [000693] ------------ * JTRUE void REG NA ------------ BB46 [1F5..1F6), preds={BB45} succs={BB47} N1025 (???,???) [001393] ------------ IL_OFFSET void IL offset: 0x1f5 REG NA N1027 ( 2, 10) [001051] H----------- t1051 = CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" REG rcx $5e /--* t1051 long N1029 ( 4, 12) [001052] #---G------- t1052 = * IND ref REG rcx $114 /--* t1052 ref N1031 (???,???) [001485] ----G------- t1485 = * PUTARG_REG ref REG rcx N1033 ( 3, 2) [000695] ------------ t695 = LCL_VAR ref V50 tmp36 u:1 rdx (last use) REG rdx $105 /--* t695 ref N1035 (???,???) [001486] ------------ t1486 = * PUTARG_REG ref REG rdx /--* t1485 ref arg0 in rcx +--* t1486 ref arg1 in rdx N1037 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail REG NA $VN.Void ------------ BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} N1041 (???,???) [001394] ------------ IL_OFFSET void IL offset: 0x219 REG NA N1043 ( 1, 1) [000190] ------------ t190 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t190 ref N1045 ( 2, 2) [001056] -c---------- t1056 = * LEA(b+60) byref REG NA N1047 ( 1, 1) [000193] ------------ t193 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t193 ref N1049 ( 2, 2) [001075] -c---------- t1075 = * LEA(b+60) byref REG NA /--* t1075 byref N1051 ( 4, 4) [000194] n---GO------ t194 = * IND int REG rcx /--* t194 int N1053 ( 4, 4) [001061] DA--GO------ * STORE_LCL_VAR int V63 tmp49 d:1 rcx REG rcx N1055 ( 1, 1) [001062] ------------ t1062 = LCL_VAR int V63 tmp49 u:1 rcx REG rcx N1057 ( 1, 1) [001330] -c---------- t1330 = LCL_VAR int V76 cse11 NA (last use) REG NA /--* t1062 int +--* t1330 int N1059 ( 6, 9) [001065] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void REG NA N1061 ( 1, 1) [001059] ------------ t1059 = LCL_VAR ref V04 loc0 u:1 r15 REG r15 N1063 ( 1, 1) [001063] ------------ t1063 = LCL_VAR int V63 tmp49 u:1 rcx (last use) REG rcx /--* t1063 int N1065 ( 2, 3) [001066] ------------ t1066 = * CAST long <- int REG r9 N1067 ( 1, 1) [001076] -c---------- t1076 = CNS_INT long 3 REG NA $24b /--* t1066 long +--* t1076 long N1069 ( 7, 7) [001077] ------------ t1077 = * MUL long REG rcx /--* t1059 ref +--* t1077 long N1071 ( 32, 35) [001058] -c---------- t1058 = * LEA(b+(i*8)+36) byref REG NA /--* t1058 byref N1073 ( 34, 37) [000197] *--XGO------ t197 = * IND int REG rcx /--* t197 int N1075 ( 35, 38) [001079] ---XGO------ t1079 = * NEG int REG rcx N1077 ( 1, 1) [000191] -c---------- t191 = CNS_INT int -3 REG NA $e1 /--* t1079 int +--* t191 int N1079 ( 37, 40) [000198] ---XGO------ t198 = * ADD int REG rcx /--* t1056 byref +--* t198 int N1081 (???,???) [001395] -A-XGO------ * STOREIND int REG NA N1083 (???,???) [001396] ------------ IL_OFFSET void IL offset: 0x233 REG NA N1085 ( 1, 1) [000202] -c---------- t202 = LCL_VAR ref V00 this u:1 rsi REG NA $100 /--* t202 ref N1087 ( 2, 2) [001083] -c---------- t1083 = * LEA(b+64) byref REG NA /--* t1083 byref N1089 ( 4, 4) [000203] nc--GO------ t203 = * IND int REG NA N1091 ( 1, 1) [000204] -c---------- t204 = CNS_INT int -1 REG NA $c4 /--* t203 int +--* t204 int N1093 ( 6, 6) [000205] -c--GO------ t205 = * ADD int REG NA N1095 ( 1, 1) [000201] ------------ t201 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t201 ref N1097 ( 2, 2) [001081] -c---------- t1081 = * LEA(b+64) byref REG NA /--* t1081 byref +--* t205 int N1099 (???,???) [001397] -A--GO------ * STOREIND int REG NA ------------ BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} N1103 (???,???) [001398] ------------ IL_OFFSET void IL offset: 0x243 REG NA N1105 ( 1, 1) [000072] ------------ t72 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t72 ref N1107 ( 2, 2) [001085] -c---------- t1085 = * LEA(b+56) byref REG NA /--* t1085 byref N1109 ( 4, 4) [000073] n---GO------ t73 = * IND int REG rcx /--* t73 int N1111 ( 8, 7) [001311] DA--GO------ * STORE_LCL_VAR int V75 cse10 d:1 rcx REG rcx N1113 ( 3, 2) [001312] ------------ t1312 = LCL_VAR int V75 cse10 u:1 rcx REG rcx /--* t1312 int N1115 ( 15, 12) [000075] DA--GO------ * STORE_LCL_VAR int V13 loc9 d:1 rbx REG rbx N1117 (???,???) [001399] ------------ IL_OFFSET void IL offset: 0x24b REG NA N1119 ( 1, 1) [001331] -c---------- t1331 = LCL_VAR int V76 cse11 NA (last use) REG NA N1121 ( 3, 2) [000076] ------------ t76 = LCL_VAR int V13 loc9 u:1 rbx REG rbx /--* t1331 int +--* t76 int N1123 ( 5, 4) [000079] N------N-U-- * NE void REG NA N1125 ( 7, 6) [000080] ------------ * JTRUE void REG NA ------------ BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} N1129 (???,???) [001400] ------------ IL_OFFSET void IL offset: 0x252 REG NA N1131 ( 3, 2) [001314] ------------ t1314 = LCL_VAR int V75 cse10 u:1 rcx (last use) REG rcx /--* t1314 int N1133 (???,???) [001487] ------------ t1487 = * PUTARG_REG int REG rcx /--* t1487 int arg0 in rcx N1135 ( 17, 8) [000702] --CXG------- t702 = * CALL int System.Collections.HashHelpers.ExpandPrime REG rax $1d7 /--* t702 int N1137 ( 21, 11) [001090] DA-XG-----L- * STORE_LCL_VAR int V64 tmp50 d:1 rdx REG rdx N1139 ( 3, 2) [001091] ------------ t1091 = LCL_VAR int V64 tmp50 u:1 rdx (last use) REG rdx $1d7 /--* t1091 int N1141 (???,???) [001488] ------------ t1488 = * PUTARG_REG int REG rdx N1143 ( 1, 1) [000163] ------------ t163 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t163 ref N1145 (???,???) [001489] ------------ t1489 = * PUTARG_REG ref REG rcx N1147 ( 1, 1) [000704] ------------ t704 = CNS_INT int 0 REG r8 $c0 /--* t704 int N1149 (???,???) [001490] ------------ t1490 = * PUTARG_REG int REG r8 /--* t1488 int arg1 in rdx +--* t1489 ref this in rcx +--* t1490 int arg2 in r8 N1151 ( 43, 24) [000705] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize REG NA $VN.Void N1153 (???,???) [001401] ------------ IL_OFFSET void IL offset: 0x258 REG NA N1155 ( 1, 1) [000165] ------------ t165 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t165 ref N1157 ( 2, 2) [001095] -c---------- t1095 = * LEA(b+8) byref REG NA /--* t1095 byref N1159 ( 4, 4) [000709] n---GO------ t709 = * IND ref REG r15 /--* t709 ref N1161 ( 8, 7) [000711] DA--GO------ * STORE_LCL_VAR ref V52 tmp38 d:1 r15 REG r15 N1163 (???,???) [001402] ------------ IL_OFFSET void IL offset: 0x258 REG NA N1165 ( 3, 2) [000713] ------------ t713 = LCL_VAR ref V52 tmp38 u:1 r15 REG r15 /--* t713 ref N1167 (???,???) [001450] -c---------- t1450 = * LEA(b+8) ref REG NA /--* t1450 ref N1169 ( 5, 4) [000714] ---X-------- t714 = * IND int REG rax /--* t714 int N1171 ( 9, 7) [001286] DA-X-------- * STORE_LCL_VAR int V72 cse7 d:1 rax REG rax N1173 ( 3, 2) [001287] -----------Z t1287 = LCL_VAR int V72 cse7 u:1 rax REG rax /--* t1287 int N1175 ( 12, 9) [000760] DA-X-------- * STORE_LCL_VAR int V53 tmp39 d:1 r8 REG r8 N1177 (???,???) [001403] ------------ IL_OFFSET void IL offset: 0x258 REG NA N1179 ( 1, 1) [000715] ------------ t715 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t715 ref N1181 ( 2, 2) [001097] -c---------- t1097 = * LEA(b+48) byref REG NA /--* t1097 byref N1183 ( 4, 4) [000716] n---GO------ t716 = * IND long REG r9 /--* t716 long N1185 ( 8, 7) [000762] DA--GO------ * STORE_LCL_VAR long V54 tmp40 d:1 NA REG NA N1187 (???,???) [001404] ------------ IL_OFFSET void IL offset: 0x258 REG NA N1189 ( 1, 1) [000728] -----------Z t728 = LCL_VAR int V53 tmp39 u:1 r8 REG r8 N1191 ( 1, 4) [000729] -c---------- t729 = CNS_INT int 0x7FFFFFFF REG NA $ce /--* t728 int +--* t729 int N1193 ( 6, 6) [000730] N--------U-- t730 = * LE int REG rcx /--* t730 int N1195 ( 10, 9) [000773] DA---------- * STORE_LCL_VAR int V56 tmp42 d:1 rcx REG rcx N1197 (???,???) [001405] ------------ IL_OFFSET void IL offset: 0x258 REG NA N1199 (???,???) [001406] ------------ IL_OFFSET void IL offset: 0x258 REG NA N1201 ( 1, 1) [001302] ------------ t1302 = LCL_VAR ref V73 cse8 u:1 r14 REG r14 $105 /--* t1302 ref N1203 ( 5, 4) [000785] DA--G------- * STORE_LCL_VAR ref V58 tmp44 d:1 rdx REG rdx N1205 (???,???) [001407] ------------ IL_OFFSET void IL offset: 0x258 REG NA N1207 ( 3, 2) [000775] ------------ t775 = LCL_VAR int V56 tmp42 u:1 rcx (last use) REG rcx N1209 ( 1, 1) [000776] -c---------- t776 = CNS_INT int 0 REG NA $c0 /--* t775 int +--* t776 int N1211 ( 5, 4) [000777] J------N---- * NE void REG NA N1213 ( 7, 6) [000778] ------------ * JTRUE void REG NA ------------ BB50 [258..259), preds={BB49} succs={BB51} N1217 (???,???) [001408] ------------ IL_OFFSET void IL offset: 0x258 REG NA N1219 ( 3, 2) [000779] ------------ t779 = LCL_VAR ref V58 tmp44 u:1 rdx REG rdx $105 /--* t779 ref N1221 (???,???) [001491] ------------ t1491 = * PUTARG_REG ref REG rcx N1223 ( 3, 2) [000780] ------------ t780 = LCL_VAR ref V58 tmp44 u:1 rdx (last use) REG rdx $105 /--* t780 ref N1225 (???,???) [001492] ------------ t1492 = * PUTARG_REG ref REG rdx /--* t1491 ref arg0 in rcx +--* t1492 ref arg1 in rdx N1227 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail REG NA $VN.Void ------------ BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} N1231 (???,???) [001409] ------------ IL_OFFSET void IL offset: 0x258 REG NA N1233 ( 3, 2) [000735] -c---------- t735 = LCL_VAR long V54 tmp40 u:1 NA (last use) REG NA N1235 ( 1, 1) [000166] ------------ t166 = LCL_VAR int V06 loc2 u:1 r13 REG r13 $3c0 /--* t166 int N1237 ( 2, 3) [000736] ---------U-- t736 = * CAST long <- ulong <- uint REG rdx $310 /--* t735 long +--* t736 long N1239 ( 9, 8) [000737] ------------ t737 = * MUL long REG rdx N1241 ( 1, 1) [000738] -c---------- t738 = CNS_INT int 32 REG NA $d2 /--* t737 long +--* t738 int N1243 ( 11, 10) [000739] ------------ t739 = * RSZ long REG rdx N1245 ( 1, 1) [000741] -c---------- t741 = CNS_INT long 1 REG NA $247 /--* t739 long +--* t741 long N1247 ( 13, 12) [000742] ------------ t742 = * ADD long REG rdx N1249 ( 1, 1) [000743] -----------z t743 = LCL_VAR int V53 tmp39 u:1 r8 REG r8 /--* t743 int N1251 ( 2, 3) [000744] ---------U-- t744 = * CAST long <- ulong <- uint REG rcx /--* t742 long +--* t744 long N1253 ( 19, 18) [000745] ------------ t745 = * MUL long REG rdx N1255 ( 1, 1) [000746] -c---------- t746 = CNS_INT int 32 REG NA $d2 /--* t745 long +--* t746 int N1257 ( 21, 20) [000747] ------------ t747 = * RSZ long REG rdx /--* t747 long N1259 ( 22, 22) [000748] ------------ t748 = * CAST int <- uint <- long REG r9 /--* t748 int N1261 ( 26, 25) [000750] DA---------- * STORE_LCL_VAR int V55 tmp41 d:1 r9 REG r9 N1263 (???,???) [001410] ------------ IL_OFFSET void IL offset: 0x258 REG NA N1265 ( 1, 1) [000752] ------------ t752 = LCL_VAR int V06 loc2 u:1 r13 REG r13 $3c0 N1267 ( 1, 1) [000753] ------------ t753 = LCL_VAR int V53 tmp39 u:1 r8 (last use) REG r8 /--* t752 int +--* t753 int N1269 ( 22, 5) [000754] ---X-------- t754 = * UMOD int REG rdx N1271 ( 3, 2) [000751] -----------Z t751 = LCL_VAR int V55 tmp41 u:1 r9 REG r9 /--* t754 int +--* t751 int N1273 ( 29, 8) [000755] ---X-------- t755 = * EQ int REG rcx /--* t755 int N1275 ( 33, 11) [000796] DA-X-------- * STORE_LCL_VAR int V59 tmp45 d:1 rcx REG rcx N1277 (???,???) [001411] ------------ IL_OFFSET void IL offset: 0x258 REG NA N1279 (???,???) [001412] ------------ IL_OFFSET void IL offset: 0x258 REG NA N1281 ( 1, 1) [001304] ------------ t1304 = LCL_VAR ref V73 cse8 u:1 r14 (last use) REG r14 $105 /--* t1304 ref N1283 ( 5, 4) [000808] DA--G------- * STORE_LCL_VAR ref V61 tmp47 d:1 rdx REG rdx N1285 (???,???) [001413] ------------ IL_OFFSET void IL offset: 0x258 REG NA N1287 ( 3, 2) [000798] ------------ t798 = LCL_VAR int V59 tmp45 u:1 rcx (last use) REG rcx N1289 ( 1, 1) [000799] -c---------- t799 = CNS_INT int 0 REG NA $c0 /--* t798 int +--* t799 int N1291 ( 5, 4) [000800] J------N---- * NE void REG NA N1293 ( 7, 6) [000801] ------------ * JTRUE void REG NA ------------ BB52 [258..259), preds={BB51} succs={BB53} N1297 (???,???) [001414] ------------ IL_OFFSET void IL offset: 0x258 REG NA N1299 ( 3, 2) [000802] ------------ t802 = LCL_VAR ref V61 tmp47 u:1 rdx REG rdx $105 /--* t802 ref N1301 (???,???) [001493] ------------ t1493 = * PUTARG_REG ref REG rcx N1303 ( 3, 2) [000803] ------------ t803 = LCL_VAR ref V61 tmp47 u:1 rdx (last use) REG rdx $105 /--* t803 ref N1305 (???,???) [001494] ------------ t1494 = * PUTARG_REG ref REG rdx /--* t1493 ref arg0 in rcx +--* t1494 ref arg1 in rdx N1307 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail REG NA $VN.Void ------------ BB53 [258..259), preds={BB51,BB52} succs={BB54} N1311 (???,???) [001415] ------------ IL_OFFSET void IL offset: 0x258 REG NA N1313 ( 3, 2) [000758] -----------z t758 = LCL_VAR int V55 tmp41 u:1 r9 REG r9 N1315 ( 3, 2) [001289] -c---------- t1289 = LCL_VAR int V72 cse7 u:1 NA (last use) REG NA /--* t758 int +--* t1289 int N1317 ( 10, 11) [001105] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void REG NA N1319 ( 3, 2) [001102] ------------ t1102 = LCL_VAR ref V52 tmp38 u:1 r15 (last use) REG r15 N1321 ( 3, 2) [001103] ------------ t1103 = LCL_VAR int V55 tmp41 u:1 r9 (last use) REG r9 /--* t1103 int N1323 ( 4, 4) [001106] ------------ t1106 = * CAST long <- int REG rdx /--* t1102 ref +--* t1106 long N1325 ( 9, 8) [001111] -------N---- t1111 = * LEA(b+(i*4)+16) byref REG rax /--* t1111 byref N1327 ( 33, 31) [000722] DA-XG------- * STORE_LCL_VAR byref V51 tmp37 d:1 rax REG rax N1329 ( 3, 2) [000723] ------------ t723 = LCL_VAR byref V51 tmp37 u:1 rax (last use) REG rax $87 /--* t723 byref N1331 ( 7, 5) [000170] DA---------- * STORE_LCL_VAR byref V08 loc4 d:4 r14 REG r14 N001 ( 1, 1) [001515] -----------Z t1515 = LCL_VAR byref V08 loc4 r14 REG r14 ------------ BB54 [261..276), preds={BB48,BB53} succs={BB55} N001 ( 0, 0) [001224] ------------ t1224 = PHI_ARG byref V08 loc4 u:4 $87 N002 ( 0, 0) [001220] ------------ t1220 = PHI_ARG byref V08 loc4 u:1 $81 /--* t1224 byref +--* t1220 byref N003 ( 0, 0) [001192] ------------ t1192 = * PHI byref /--* t1192 byref N005 ( 0, 0) [001193] DA---------- * STORE_LCL_VAR byref V08 loc4 d:3 N1335 (???,???) [001416] ------------ IL_OFFSET void IL offset: 0x261 REG NA N1337 ( 3, 2) [000081] ------------ t81 = LCL_VAR int V13 loc9 u:1 rbx (last use) REG rbx /--* t81 int N1339 ( 7, 5) [000083] DA---------- * STORE_LCL_VAR int V10 loc6 d:2 rbx REG rbx N1341 (???,???) [001417] ------------ IL_OFFSET void IL offset: 0x265 REG NA N1343 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V10 loc6 u:2 rbx REG rbx N1345 ( 1, 1) [000086] -c---------- t86 = CNS_INT int 1 REG NA $c1 /--* t85 int +--* t86 int N1347 ( 5, 4) [000087] ------------ t87 = * ADD int REG rdx N1349 ( 1, 1) [000084] ------------ t84 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t84 ref N1351 ( 2, 2) [001115] -c---------- t1115 = * LEA(b+56) byref REG NA /--* t1115 byref +--* t87 int N1353 (???,???) [001418] -A--GO------ * STOREIND int REG NA N1355 (???,???) [001419] ------------ IL_OFFSET void IL offset: 0x26f REG NA N1357 ( 1, 1) [000090] ------------ t90 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t90 ref N1359 ( 2, 2) [001117] -c---------- t1117 = * LEA(b+16) byref REG NA /--* t1117 byref N1361 ( 4, 4) [000091] n---GO------ t91 = * IND ref REG r15 /--* t91 ref N1363 ( 4, 4) [000093] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:3 r15 REG r15 ------------ BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} N001 ( 0, 0) [001225] ------------ t1225 = PHI_ARG byref V08 loc4 u:1 $81 N002 ( 0, 0) [001221] ------------ t1221 = PHI_ARG byref V08 loc4 u:3 $780 /--* t1225 byref +--* t1221 byref N003 ( 0, 0) [001195] ------------ t1195 = * PHI byref /--* t1195 byref N005 ( 0, 0) [001196] DA---------- * STORE_LCL_VAR byref V08 loc4 d:2 N001 ( 0, 0) [001226] ------------ t1226 = PHI_ARG ref V04 loc0 u:1 r15 N002 ( 0, 0) [001222] ------------ t1222 = PHI_ARG ref V04 loc0 u:3 r15 /--* t1226 ref +--* t1222 ref N003 ( 0, 0) [001189] ------------ t1189 = * PHI ref /--* t1189 ref N005 ( 0, 0) [001190] DA---------- * STORE_LCL_VAR ref V04 loc0 d:2 r15 N001 ( 0, 0) [001227] ------------ t1227 = PHI_ARG int V10 loc6 u:3 rbx N002 ( 0, 0) [001223] ------------ t1223 = PHI_ARG int V10 loc6 u:2 rbx /--* t1227 int +--* t1223 int N003 ( 0, 0) [001186] ------------ t1186 = * PHI int /--* t1186 int N005 ( 0, 0) [001187] DA---------- * STORE_LCL_VAR int V10 loc6 d:1 rbx N1367 (???,???) [001420] ------------ IL_OFFSET void IL offset: 0x276 REG NA N1369 ( 3, 2) [000095] ------------ t95 = LCL_VAR int V10 loc6 u:1 rbx REG rbx $3cc N1371 ( 1, 1) [000094] ------------ t94 = LCL_VAR ref V04 loc0 u:2 r15 REG r15 $684 /--* t94 ref N1373 (???,???) [001452] -c---------- t1452 = * LEA(b+8) ref REG NA /--* t1452 ref N1375 ( 3, 3) [001120] -c-X-------- t1120 = * IND int REG NA $73d /--* t95 int +--* t1120 int N1377 ( 10, 12) [001121] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void REG NA $7cd N1379 ( 1, 1) [001118] ------------ t1118 = LCL_VAR ref V04 loc0 u:2 r15 REG r15 $684 N1381 ( 3, 2) [001119] ------------ t1119 = LCL_VAR int V10 loc6 u:1 rbx REG rbx $3cc /--* t1119 int N1383 ( 4, 4) [001122] ------------ t1122 = * CAST long <- int REG rdx $6dc N1385 ( 1, 1) [001129] -c---------- t1129 = CNS_INT long 3 REG NA $24b /--* t1122 long +--* t1129 long N1387 ( 9, 8) [001130] ------------ t1130 = * MUL long REG rdx $6dd /--* t1118 ref +--* t1130 long N1389 ( 12, 11) [001127] -------N---- t1127 = * LEA(b+(i*8)+16) byref REG r14 /--* t1127 byref N1391 ( 39, 38) [000099] DA-XG------- * STORE_LCL_VAR byref V11 loc7 d:1 r14 REG r14 N1393 (???,???) [001421] ------------ IL_OFFSET void IL offset: 0x280 REG NA N1395 ( 3, 2) [000100] ------------ t100 = LCL_VAR byref V11 loc7 u:1 r14 REG r14 $8c /--* t100 byref N1397 ( 4, 3) [001133] -c---------- t1133 = * LEA(b+16) byref REG NA N1399 ( 1, 1) [000101] ------------ t101 = LCL_VAR int V06 loc2 u:1 r13 (last use) REG r13 $3c0 /--* t1133 byref +--* t101 int N1401 (???,???) [001422] -A-XG------- * STOREIND int REG NA N1403 (???,???) [001423] ------------ IL_OFFSET void IL offset: 0x288 REG NA N1405 ( 3, 2) [000105] -----------z t105 = LCL_VAR byref V08 loc4 u:2 rax REG rax $781 /--* t105 byref N1407 ( 6, 4) [000106] *--XG------- t106 = * IND int REG rdx N1409 ( 1, 1) [000107] -c---------- t107 = CNS_INT int -1 REG NA $c4 /--* t106 int +--* t107 int N1411 ( 8, 6) [000108] ---XG------- t108 = * ADD int REG rdx N1413 ( 3, 2) [000104] ------------ t104 = LCL_VAR byref V11 loc7 u:1 r14 REG r14 $8c /--* t104 byref N1415 ( 4, 3) [001135] -c---------- t1135 = * LEA(b+20) byref REG NA /--* t1135 byref +--* t108 int N1417 (???,???) [001424] -A-XGO------ * STOREIND int REG NA N1419 (???,???) [001425] ------------ IL_OFFSET void IL offset: 0x294 REG NA N1421 ( 3, 2) [000111] ------------ t111 = LCL_VAR byref V11 loc7 u:1 r14 Zero Fseq[key] REG r14 $8f N1423 ( 1, 1) [000112] ------------ t112 = LCL_VAR ref V01 arg1 u:1 rdi (last use) REG rdi $101 /--* t111 byref +--* t112 ref N1425 (???,???) [001426] -A-XG------- * STOREIND ref REG NA N1427 (???,???) [001427] ------------ IL_OFFSET void IL offset: 0x29c REG NA N1429 ( 3, 2) [000115] ------------ t115 = LCL_VAR byref V11 loc7 u:1 r14 (last use) REG r14 $8c /--* t115 byref N1431 ( 4, 3) [001137] ------------ t1137 = * LEA(b+8) byref REG rcx N1433 ( 1, 1) [000116] ------------ t116 = LCL_VAR ref V02 arg2 u:1 rbp (last use) REG rbp $102 /--* t1137 byref +--* t116 ref N1435 (???,???) [001428] -A--GO------ * STOREIND ref REG NA N1437 (???,???) [001429] ------------ IL_OFFSET void IL offset: 0x2a4 REG NA N1439 ( 3, 2) [000120] ------------ t120 = LCL_VAR int V10 loc6 u:1 rbx (last use) REG rbx $3cc N1441 ( 1, 1) [000121] -c---------- t121 = CNS_INT int 1 REG NA $c1 /--* t120 int +--* t121 int N1443 ( 5, 4) [000122] ------------ t122 = * ADD int REG rbx $804 N1445 ( 3, 2) [000119] -----------z t119 = LCL_VAR byref V08 loc4 u:2 r14 (last use) REG r14 $781 /--* t119 byref +--* t122 int N1447 (???,???) [001430] -A--GO------ * STOREIND int REG NA N1449 (???,???) [001431] ------------ IL_OFFSET void IL offset: 0x2ab REG NA N1451 ( 1, 1) [000126] -c---------- t126 = LCL_VAR ref V00 this u:1 rsi REG NA $100 /--* t126 ref N1453 ( 2, 2) [001141] -c---------- t1141 = * LEA(b+68) byref REG NA /--* t1141 byref N1455 ( 4, 4) [000127] nc--GO------ t127 = * IND int REG NA N1457 ( 1, 1) [000128] -c---------- t128 = CNS_INT int 1 REG NA $c1 /--* t127 int +--* t128 int N1459 ( 6, 6) [000129] -c--GO------ t129 = * ADD int REG NA N1461 ( 1, 1) [000125] ------------ t125 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t125 ref N1463 ( 2, 2) [001139] -c---------- t1139 = * LEA(b+68) byref REG NA /--* t1139 byref +--* t129 int N1465 (???,???) [001432] -A--GO------ * STOREIND int REG NA N1467 (???,???) [001433] ------------ IL_OFFSET void IL offset: 0x2ca REG NA N1469 ( 1, 1) [000145] -c---------- t145 = LCL_VAR int V07 loc3 u:2 NA (last use) REG NA $3c5 N1471 ( 1, 1) [000146] -c---------- t146 = CNS_INT int 100 REG NA $e3 /--* t145 int +--* t146 int N1473 ( 3, 3) [000147] N------N-U-- * LE void REG NA $80d N1475 ( 5, 5) [000148] ------------ * JTRUE void REG NA ------------ BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} N1479 (???,???) [001434] ------------ IL_OFFSET void IL offset: 0x2cf REG NA N1481 ( 1, 1) [000151] ------------ t151 = LCL_VAR ref V05 loc1 u:1 r12 (last use) REG r12 /--* t151 ref N1483 (???,???) [001495] ------------ t1495 = * PUTARG_REG ref REG rdx N1485 ( 2, 10) [000152] H------N---- t152 = CNS_INT(h) long 0xd1ffab1e class REG rcx $62 /--* t152 long N1487 (???,???) [001496] ------------ t1496 = * PUTARG_REG long REG rcx /--* t1495 ref arg1 in rdx +--* t1496 long arg0 in rcx N1489 ( 17, 18) [000153] --C-G------- t153 = * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS REG rax N1491 ( 1, 1) [000154] -c---------- t154 = CNS_INT ref null REG NA $VN.Null /--* t153 ref +--* t154 ref N1493 ( 19, 20) [000155] J---G--N---- * EQ void REG NA N1495 ( 21, 22) [000156] ----G------- * JTRUE void REG NA ------------ BB57 [2D7..2E3), preds={BB56} succs={BB58} N1499 (???,???) [001435] ------------ IL_OFFSET void IL offset: 0x2d7 REG NA N1501 ( 1, 1) [000158] ------------ t158 = LCL_VAR ref V04 loc0 u:2 r15 (last use) REG r15 $684 /--* t158 ref N1503 (???,???) [001454] -c---------- t1454 = * LEA(b+8) ref REG NA /--* t1454 ref N1505 ( 3, 3) [000159] ---X-------- t159 = * IND int REG rdx $73d /--* t159 int N1507 (???,???) [001497] ---X-------- t1497 = * PUTARG_REG int REG rdx N1509 ( 1, 1) [000157] ------------ t157 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t157 ref N1511 (???,???) [001498] ------------ t1498 = * PUTARG_REG ref REG rcx N1513 ( 1, 1) [000160] ------------ t160 = CNS_INT int 1 REG r8 $c1 /--* t160 int N1515 (???,???) [001499] ------------ t1499 = * PUTARG_REG int REG r8 /--* t1497 int arg1 in rdx +--* t1498 ref this in rcx +--* t1499 int arg2 in r8 N1517 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize REG NA $VN.Void ------------ BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} N1521 ( 1, 1) [000482] ------------ t482 = CNS_INT int 1 REG rax $c1 /--* t482 int N1523 ( 2, 2) [000810] ------------ * RETURN int REG NA $1f4 ------------ BB59 [008..00E) (throw), preds={BB01} succs={} N1527 (???,???) [001436] ------------ IL_OFFSET void IL offset: 0x8 REG NA N1529 ( 1, 1) [000532] ------------ t532 = CNS_INT int 4 REG rcx $c5 /--* t532 int N1531 (???,???) [001500] ------------ t1500 = * PUTARG_REG int REG rcx /--* t1500 int arg0 in rcx N1533 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException REG NA $VN.Void ------------ BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} N1537 (???,???) [001437] ------------ IL_OFFSET void IL offset: 0x14f REG NA N1539 ( 1, 1) [000441] !----------- t441 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t441 ref N1541 ( 3, 2) [000442] #----O------ t442 = * IND long REG rcx $2e8 /--* t442 long N1543 ( 7, 5) [000444] DA---O------ * STORE_LCL_VAR long V26 tmp12 d:1 rcx REG rcx N1545 ( 3, 2) [000446] ------------ t446 = LCL_VAR long V26 tmp12 u:1 rcx REG rcx $2e7 /--* t446 long N1547 ( 4, 3) [000448] -c---------- t448 = * LEA(b+56) long REG NA /--* t448 long N1549 ( 6, 5) [000449] #----------- t449 = * IND long REG rdx $2e9 /--* t449 long N1551 ( 9, 7) [000450] #----------- t450 = * IND long REG rdx $2ea /--* t450 long N1553 ( 10, 8) [000452] -c---------- t452 = * LEA(b+56) long REG NA /--* t452 long N1555 ( 12, 10) [000456] nc---------- t456 = * IND long REG NA N1557 ( 1, 1) [000459] -c---------- t459 = CNS_INT long 0 REG NA $243 /--* t456 long +--* t459 long N1559 ( 14, 12) [000460] J------N---- * EQ void REG NA N1561 ( 16, 14) [001158] ------------ * JTRUE void REG NA ------------ BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} N1565 ( 3, 2) [000466] ------?----- t466 = LCL_VAR long V26 tmp12 u:1 rcx (last use) REG rcx $2e7 /--* t466 long N1567 ( 4, 3) [000465] -c----?----- t465 = * LEA(b+56) long REG NA /--* t465 long N1569 ( 6, 5) [000464] #-----?----- t464 = * IND long REG rcx $2e9 /--* t464 long N1571 ( 9, 7) [000463] #-----?----- t463 = * IND long REG rcx $2ea /--* t463 long N1573 ( 10, 8) [000462] -c----?----- t462 = * LEA(b+56) long REG NA /--* t462 long N1575 ( 12, 10) [000461] n-----?----- t461 = * IND long REG rcx /--* t461 long N1577 ( 16, 13) [001160] DA---------- * STORE_LCL_VAR long V28 tmp14 d:3 rcx REG rcx ------------ BB62 [???..???), preds={BB60} succs={BB63} N1581 ( 3, 2) [000445] ------?----- t445 = LCL_VAR long V26 tmp12 u:1 rcx (last use) REG rcx $2e7 /--* t445 long N1583 (???,???) [001501] ------------ t1501 = * PUTARG_REG long REG rcx N1585 ( 2, 10) [000457] H-----?----- t457 = CNS_INT(h) long 0xd1ffab1e global ptr REG rdx $52 /--* t457 long N1587 (???,???) [001502] ------------ t1502 = * PUTARG_REG long REG rdx /--* t1501 long arg0 in rcx +--* t1502 long arg1 in rdx N1589 ( 19, 19) [000458] --C-G-?----- t458 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS REG rax $332 /--* t458 long N1591 ( 23, 22) [001162] DA--G------- * STORE_LCL_VAR long V28 tmp14 d:2 rcx REG rcx ------------ BB63 [???..157) (throw), preds={BB61,BB62} succs={} N001 ( 0, 0) [001241] ------------ t1241 = PHI_ARG long V28 tmp14 u:3 rcx N002 ( 0, 0) [001240] ------------ t1240 = PHI_ARG long V28 tmp14 u:2 rcx $332 /--* t1241 long +--* t1240 long N003 ( 0, 0) [001183] ------------ t1183 = * PHI long /--* t1183 long N005 ( 0, 0) [001184] DA---------- * STORE_LCL_VAR long V28 tmp14 d:1 rcx N1595 ( 3, 2) [000473] ------------ t473 = LCL_VAR long V28 tmp14 u:1 rcx (last use) REG rcx $347 /--* t473 long N1597 (???,???) [001503] ------------ t1503 = * PUTARG_REG long REG rcx N1599 ( 1, 1) [000455] ------------ t455 = LCL_VAR ref V01 arg1 u:1 rdi (last use) REG rdi $101 /--* t455 ref N1601 (???,???) [001504] ------------ t1504 = * PUTARG_REG ref REG rdx /--* t1503 long arg0 in rcx +--* t1504 ref arg1 in rdx N1603 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException REG NA $VN.Void ------------ BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} N1607 (???,???) [001438] ------------ IL_OFFSET void IL offset: 0x1bc REG NA N1609 ( 1, 1) [000296] !----------- t296 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t296 ref N1611 ( 3, 2) [000297] #----O------ t297 = * IND long REG rcx $2e8 /--* t297 long N1613 ( 7, 5) [000299] DA---O------ * STORE_LCL_VAR long V21 tmp7 d:1 rcx REG rcx N1615 ( 3, 2) [000301] ------------ t301 = LCL_VAR long V21 tmp7 u:1 rcx REG rcx $2e7 /--* t301 long N1617 ( 4, 3) [000303] -c---------- t303 = * LEA(b+56) long REG NA /--* t303 long N1619 ( 6, 5) [000304] #----------- t304 = * IND long REG rdx $2e9 /--* t304 long N1621 ( 9, 7) [000305] #----------- t305 = * IND long REG rdx $2ea /--* t305 long N1623 ( 10, 8) [000307] -c---------- t307 = * LEA(b+56) long REG NA /--* t307 long N1625 ( 12, 10) [000311] nc---------- t311 = * IND long REG NA N1627 ( 1, 1) [000314] -c---------- t314 = CNS_INT long 0 REG NA $243 /--* t311 long +--* t314 long N1629 ( 14, 12) [000315] J------N---- * EQ void REG NA N1631 ( 16, 14) [001168] ------------ * JTRUE void REG NA ------------ BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} N1635 ( 3, 2) [000321] ------?----- t321 = LCL_VAR long V21 tmp7 u:1 rcx (last use) REG rcx $2e7 /--* t321 long N1637 ( 4, 3) [000320] -c----?----- t320 = * LEA(b+56) long REG NA /--* t320 long N1639 ( 6, 5) [000319] #-----?----- t319 = * IND long REG rcx $2e9 /--* t319 long N1641 ( 9, 7) [000318] #-----?----- t318 = * IND long REG rcx $2ea /--* t318 long N1643 ( 10, 8) [000317] -c----?----- t317 = * LEA(b+56) long REG NA /--* t317 long N1645 ( 12, 10) [000316] n-----?----- t316 = * IND long REG rcx /--* t316 long N1647 ( 16, 13) [001170] DA---------- * STORE_LCL_VAR long V23 tmp9 d:3 rcx REG rcx ------------ BB66 [???..???), preds={BB64} succs={BB67} N1651 ( 3, 2) [000300] ------?----- t300 = LCL_VAR long V21 tmp7 u:1 rcx (last use) REG rcx $2e7 /--* t300 long N1653 (???,???) [001505] ------------ t1505 = * PUTARG_REG long REG rcx N1655 ( 2, 10) [000312] H-----?----- t312 = CNS_INT(h) long 0xd1ffab1e global ptr REG rdx $52 /--* t312 long N1657 (???,???) [001506] ------------ t1506 = * PUTARG_REG long REG rdx /--* t1505 long arg0 in rcx +--* t1506 long arg1 in rdx N1659 ( 19, 19) [000313] --C-G-?----- t313 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS REG rax $332 /--* t313 long N1661 ( 23, 22) [001172] DA--G------- * STORE_LCL_VAR long V23 tmp9 d:2 rcx REG rcx ------------ BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} N001 ( 0, 0) [001232] ------------ t1232 = PHI_ARG long V23 tmp9 u:3 rcx N002 ( 0, 0) [001231] ------------ t1231 = PHI_ARG long V23 tmp9 u:2 rcx $332 /--* t1232 long +--* t1231 long N003 ( 0, 0) [001201] ------------ t1201 = * PHI long /--* t1201 long N005 ( 0, 0) [001202] DA---------- * STORE_LCL_VAR long V23 tmp9 d:1 rcx N1665 ( 3, 2) [000328] ------------ t328 = LCL_VAR long V23 tmp9 u:1 rcx (last use) REG rcx $34b /--* t328 long N1667 (???,???) [001507] ------------ t1507 = * PUTARG_REG long REG rcx N1669 ( 1, 1) [000310] ------------ t310 = LCL_VAR ref V01 arg1 u:1 rdi (last use) REG rdi $101 /--* t310 ref N1671 (???,???) [001508] ------------ t1508 = * PUTARG_REG ref REG rdx /--* t1507 long arg0 in rcx +--* t1508 ref arg1 in rdx N1673 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException REG NA $VN.Void ------------ BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} N1677 (???,???) [001439] ------------ IL_OFFSET void IL offset: 0x1dd REG NA N1679 ( 14, 5) [000233] --CXG------- CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported REG NA $VN.Void ------------ BB69 [???..???) (throw), preds={} succs={} N1683 ( 14, 5) [001444] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL REG NA ------------------------------------------------------------------------------------------------------------------- Final allocation --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 0.#0 V0 Parm Alloc rsi | | | | | |V0 a| | | | | | | | | | 0.#1 V1 Parm Alloc rdi | | | | | |V0 a|V1 a| | | | | | | | | 0.#2 V3 Parm Alloc rbx | | | |V3 a| |V0 a|V1 a| | | | | | | | | 0.#3 V2 Parm Alloc rbp | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 1.#4 BB1 PredBB0 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 9.#5 V1 Use Keep rdi | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 13.#6 BB2 PredBB1 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 25.#7 V0 Use Keep rsi | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 29.#8 BB3 PredBB2 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 33.#9 rcx Fixd Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 33.#10 V0 Use Copy rcx | |V0 a| |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 34.#11 rcx Fixd Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 34.#12 I65 Def Alloc rcx | |I65 a| |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 36.#13 C66 Def Alloc rdx | |I65 a|C66 a|V3 a|V2 a|V0 a|V1 a| | | | | | | | | 37.#14 rdx Fixd Keep rdx | |I65 a|C66 a|V3 a|V2 a|V0 a|V1 a| | | | | | | | | 37.#15 C66 Use * Keep rdx | |I65 a|C66 i|V3 a|V2 a|V0 a|V1 a| | | | | | | | | 38.#16 rdx Fixd Keep rdx | |I65 a| |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 38.#17 I67 Def Alloc rdx | |I65 a|I67 a|V3 a|V2 a|V0 a|V1 a| | | | | | | | | 39.#18 rcx Fixd Keep rcx | |I65 a|I67 a|V3 a|V2 a|V0 a|V1 a| | | | | | | | | 39.#19 I65 Use * Keep rcx | |I65 i|I67 a|V3 a|V2 a|V0 a|V1 a| | | | | | | | | 39.#20 rdx Fixd Keep rdx | | |I67 a|V3 a|V2 a|V0 a|V1 a| | | | | | | | | 39.#21 I67 Use * Keep rdx | | |I67 i|V3 a|V2 a|V0 a|V1 a| | | | | | | | | 40.#22 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 40.#23 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 40.#24 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 40.#25 r8 Kill Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 40.#26 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 40.#27 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 40.#28 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 40.#29 rax Fixd Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 40.#30 I68 Def * Alloc rax |I68 i| | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 41.#31 BB4 PredBB2 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 53.#32 V0 Use Keep rsi | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 54.#33 I69 Def Alloc rcx | |I69 a| |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 55.#34 I69 Use * Keep rcx | |I69 i| |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 56.#35 V33 Def Alloc rcx | |V33 a| |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 60.#36 C70 Def Alloc rdx | |V33 a|C70 a|V3 a|V2 a|V0 a|V1 a| | | | | | | | | 61.#37 C70 Use * Keep rdx | |V33 a|C70 i|V3 a|V2 a|V0 a|V1 a| | | | | | | | | 62.#38 I71 Def Alloc r14 | |V33 a| |V3 a|V2 a|V0 a|V1 a| | | | | | |I71 a| | 63.#39 I71 Use * Keep r14 | |V33 a| |V3 a|V2 a|V0 a|V1 a| | | | | | |I71 i| | 64.#40 V73 Def Alloc r14 | |V33 a| |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 69.#41 V73 Use Keep r14 | |V33 a| |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 70.#42 V35 Def Alloc rdx | |V33 a|V35 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 77.#43 V33 Use * Keep rcx | |V33 i|V35 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 81.#44 BB5 PredBB4 | | |V35 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 87.#45 rcx Fixd Keep rcx | | |V35 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 87.#46 V35 Use Copy rcx | |V35 a|V35 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 88.#47 rcx Fixd Keep rcx | | |V35 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 88.#48 I72 Def Alloc rcx | |I72 a|V35 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 91.#49 rdx Fixd Keep rdx | |I72 a|V35 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 91.#50 V35 Use * Keep rdx | |I72 a|V35 i|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 92.#51 rdx Fixd Keep rdx | |I72 a| |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 92.#52 I73 Def Alloc rdx | |I72 a|I73 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 93.#53 rcx Fixd Keep rcx | |I72 a|I73 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 93.#54 I72 Use * Keep rcx | |I72 i|I73 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 93.#55 rdx Fixd Keep rdx | | |I73 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 93.#56 I73 Use * Keep rdx | | |I73 i|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 94.#57 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 94.#58 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 94.#59 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 94.#60 r8 Kill Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 94.#61 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 94.#62 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 94.#63 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 95.#64 BB6 PredBB4 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 103.#65 V0 Use Keep rsi | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a| | 104.#66 I74 Def Alloc r15 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|I74 a| 105.#67 I74 Use * Keep r15 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|I74 i| 106.#68 V4 Def Alloc r15 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 113.#69 V4 Use Keep r15 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 114.#70 I75 Def Alloc rcx | |I75 a| |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 115.#71 I75 Use * Keep rcx | |I75 i| |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 116.#72 V36 Def Alloc rcx | |V36 a| |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 121.#73 V73 Use Keep r14 | |V36 a| |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 122.#74 V37 Def Alloc rdx | |V36 a|V37 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 129.#75 V36 Use * Keep rcx | |V36 i|V37 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 133.#76 BB7 PredBB6 | | |V37 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 138.#77 C76 Def Alloc rcx | |C76 a|V37 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 139.#78 C76 Use * Keep rcx | |C76 i|V37 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 140.#79 I77 Def Alloc rcx | |I77 a|V37 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 141.#80 rcx Fixd Keep rcx | |I77 a|V37 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 141.#81 I77 Use * Keep rcx | |I77 i|V37 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 142.#82 rcx Fixd Keep rcx | | |V37 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 142.#83 I78 Def Alloc rcx | |I78 a|V37 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 145.#84 rdx Fixd Keep rdx | |I78 a|V37 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 145.#85 V37 Use * Keep rdx | |I78 a|V37 i|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 146.#86 rdx Fixd Keep rdx | |I78 a| |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 146.#87 I79 Def Alloc rdx | |I78 a|I79 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 147.#88 rcx Fixd Keep rcx | |I78 a|I79 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 147.#89 I78 Use * Keep rcx | |I78 i|I79 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 147.#90 rdx Fixd Keep rdx | | |I79 a|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 147.#91 I79 Use * Keep rdx | | |I79 i|V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 148.#92 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 148.#93 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 148.#94 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 148.#95 r8 Kill Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 148.#96 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 148.#97 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 148.#98 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 149.#99 BB8 PredBB6 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 157.#100 V0 Use Keep rsi | | | |V3 a|V2 a|V0 a|V1 a| | | | | | |V73 a|V4 a| 158.#101 I80 Def Alloc r12 | | | |V3 a|V2 a|V0 a|V1 a| | | | |I80 a| |V73 a|V4 a| 159.#102 I80 Use * Keep r12 | | | |V3 a|V2 a|V0 a|V1 a| | | | |I80 i| |V73 a|V4 a| 160.#103 V5 Def Alloc r12 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 167.#104 V5 Use Keep r12 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 171.#105 BB9 PredBB8 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 177.#106 V0 Use Keep rsi | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 178.#107 I81 Def Alloc rcx | |I81 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 179.#108 I81 Use * Keep rcx | |I81 i| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 180.#109 V29 Def Alloc rcx | |V29 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 185.#110 V29 Use Keep rcx | |V29 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 186.#111 I82 Def Alloc rdx | |V29 a|I82 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 187.#112 I82 Use * Keep rdx | |V29 a|I82 i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 188.#113 I83 Def Alloc rdx | |V29 a|I83 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 191.#114 I83 Use * Keep rdx | |V29 a|I83 i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 192.#115 I84 Def Alloc r11 | |V29 a| |V3 a|V2 a|V0 a|V1 a| | | |I84 a|V5 a| |V73 a|V4 a| 193.#116 I84 Use * Keep r11 | |V29 a| |V3 a|V2 a|V0 a|V1 a| | | |I84 i|V5 a| |V73 a|V4 a| 194.#117 V68 Def Alloc r11 | |V29 a| |V3 a|V2 a|V0 a|V1 a| | | |V68 a|V5 a| |V73 a|V4 a| 199.#118 V68 Use Keep r11 | |V29 a| |V3 a|V2 a|V0 a|V1 a| | | |V68 a|V5 a| |V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 203.#119 BB10 PredBB9 | | | |V3 a|V2 a|V0 a|V1 a| | | |V68 a|V5 a| |V73 a|V4 a| 207.#120 V68 Use * Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | |V68 i|V5 a| |V73 a|V4 a| 208.#121 V31 Def Alloc r11 | | | |V3 a|V2 a|V0 a|V1 a| | | |V31 a|V5 a| |V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 209.#122 BB11 PredBB9 | |V29 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 213.#123 rcx Fixd Keep rcx | |V29 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 213.#124 V29 Use * Keep rcx | |V29 i| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 214.#125 rcx Fixd Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 214.#126 I85 Def Alloc rcx | |I85 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 216.#127 C86 Def Alloc rdx | |I85 a|C86 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 217.#128 rdx Fixd Keep rdx | |I85 a|C86 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 217.#129 C86 Use * Keep rdx | |I85 a|C86 i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 218.#130 rdx Fixd Keep rdx | |I85 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 218.#131 I87 Def Alloc rdx | |I85 a|I87 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 219.#132 rcx Fixd Keep rcx | |I85 a|I87 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 219.#133 I85 Use * Keep rcx | |I85 i|I87 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 219.#134 rdx Fixd Keep rdx | | |I87 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 219.#135 I87 Use * Keep rdx | | |I87 i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 220.#136 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 220.#137 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 220.#138 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 220.#139 r8 Kill Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 220.#140 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 220.#141 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 220.#142 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 220.#143 rax Fixd Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 220.#144 I88 Def Alloc rax |I88 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 221.#145 I88 Use * Keep rax |I88 i| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 222.#146 V31 Def Alloc r11 | | | |V3 a|V2 a|V0 a|V1 a| | | |V31 a|V5 a| |V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 223.#147 BB12 PredBB10 | | | |V3 a|V2 a|V0 a|V1 a| | | |V31 a|V5 a| |V73 a|V4 a| 227.#148 rcx Fixd Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | |V31 a|V5 a| |V73 a|V4 a| 227.#149 V5 Use Copy rcx | |V5 a| |V3 a|V2 a|V0 a|V1 a| | | |V31 a|V5 a| |V73 a|V4 a| 228.#150 rcx Fixd Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | |V31 a|V5 a| |V73 a|V4 a| 228.#151 I89 Def Alloc rcx | |I89 a| |V3 a|V2 a|V0 a|V1 a| | | |V31 a|V5 a| |V73 a|V4 a| 231.#152 r11 Fixd Keep r11 | |I89 a| |V3 a|V2 a|V0 a|V1 a| | | |V31 a|V5 a| |V73 a|V4 a| 231.#153 V31 Use Keep r11 | |I89 a| |V3 a|V2 a|V0 a|V1 a| | | |V31 a|V5 a| |V73 a|V4 a| 232.#154 r11 Fixd Keep r11 | |I89 a| |V3 a|V2 a|V0 a|V1 a| | | |V31 a|V5 a| |V73 a|V4 a| 232.#155 I90 Def PtArg r11 | |I89 a| |V3 a|V2 a|V0 a|V1 a| | | |V31 a|V5 a| |V73 a|V4 a| 235.#156 rdx Fixd Keep rdx | |I89 a| |V3 a|V2 a|V0 a|V1 a| | | |V31 a|V5 a| |V73 a|V4 a| 235.#157 V1 Use Copy rdx | |I89 a|V1 a|V3 a|V2 a|V0 a|V1 a| | | |V31 a|V5 a| |V73 a|V4 a| 236.#158 rdx Fixd Keep rdx | |I89 a| |V3 a|V2 a|V0 a|V1 a| | | |V31 a|V5 a| |V73 a|V4 a| 236.#159 I91 Def Alloc rdx | |I89 a|I91 a|V3 a|V2 a|V0 a|V1 a| | | |V31 a|V5 a| |V73 a|V4 a| 241.#160 rcx Fixd Keep rcx | |I89 a|I91 a|V3 a|V2 a|V0 a|V1 a| | | |V31 a|V5 a| |V73 a|V4 a| 241.#161 I89 Use * Keep rcx | |I89 i|I91 a|V3 a|V2 a|V0 a|V1 a| | | |V31 a|V5 a| |V73 a|V4 a| 241.#162 r11 Fixd Keep r11 | | |I91 a|V3 a|V2 a|V0 a|V1 a| | | |V31 a|V5 a| |V73 a|V4 a| 241.#163 I90 Use * PtArg r11 | | |I91 a|V3 a|V2 a|V0 a|V1 a| | | |V31 a|V5 a| |V73 a|V4 a| 241.#164 rdx Fixd Keep rdx | | |I91 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 241.#165 I91 Use * Keep rdx | | |I91 i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 241.#166 V31 Use * Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | |V31 i|V5 a| |V73 a|V4 a| 242.#167 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 242.#168 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 242.#169 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 242.#170 r8 Kill Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 242.#171 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 242.#172 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 242.#173 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 242.#174 rax Fixd Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 242.#175 I92 Def Alloc rax |I92 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 243.#176 I92 Use * Keep rax |I92 i| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 244.#177 V15 Def Alloc r13 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V15 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 245.#178 BB13 PredBB8 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 251.#179 rcx Fixd Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 251.#180 V1 Use Copy rcx | |V1 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 252.#181 rcx Fixd Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 252.#182 I93 Def Alloc rcx | |I93 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 255.#183 V1 Use Keep rdi | |I93 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 256.#184 I94 Def Alloc rax |I94 a|I93 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 259.#185 I94 Use * Keep rax |I94 i|I93 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 260.#186 I95 Def Alloc rax |I95 a|I93 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 265.#187 rcx Fixd Keep rcx |I95 a|I93 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 265.#188 I93 Use * Keep rcx |I95 a|I93 i| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 265.#189 I95 Use * Keep rax |I95 i| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 266.#190 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 266.#191 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 266.#192 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 266.#193 r8 Kill Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 266.#194 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 266.#195 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 266.#196 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 266.#197 rax Fixd Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 266.#198 I96 Def Alloc rax |I96 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 267.#199 I96 Use * Keep rax |I96 i| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a| |V73 a|V4 a| 268.#200 V15 Def Alloc r13 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V15 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 269.#201 BB14 PredBB12 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V15 a|V73 a|V4 a| 273.#202 V15 Use * Keep r13 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V15 i|V73 a|V4 a| 274.#203 V6 Def Alloc r13 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 278.#204 C97 Def Alloc rax |C97 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 279.#205 C97 Use * Keep rax |C97 i| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 280.#206 V7 Def Alloc rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| Spill rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 287.#207 V0 Use Keep rsi | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 288.#208 I98 Def Alloc r8 | | | |V3 a|V2 a|V0 a|V1 a|I98 a| | | |V5 a|V6 a|V73 a|V4 a| 289.#209 I98 Use * Keep r8 | | | |V3 a|V2 a|V0 a|V1 a|I98 i| | | |V5 a|V6 a|V73 a|V4 a| 290.#210 V39 Def Alloc r8 | | | |V3 a|V2 a|V0 a|V1 a|V39 a| | | |V5 a|V6 a|V73 a|V4 a| 297.#211 V39 Use Keep r8 | | | |V3 a|V2 a|V0 a|V1 a|V39 i| | | |V5 a|V6 a|V73 a|V4 a| Spill r8 | | | |V3 a|V2 a|V0 a|V1 a|V39 i| | | |V5 a|V6 a|V73 a|V4 a| 298.#212 I99 Def Alloc r9 | | | |V3 a|V2 a|V0 a|V1 a| |I99 a| | |V5 a|V6 a|V73 a|V4 a| 299.#213 I99 Use * Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| |I99 i| | |V5 a|V6 a|V73 a|V4 a| 300.#214 V40 Def Alloc r9 | | | |V3 a|V2 a|V0 a|V1 a| |V40 a| | |V5 a|V6 a|V73 a|V4 a| 307.#215 V0 Use Keep rsi | | | |V3 a|V2 a|V0 a|V1 a| |V40 a| | |V5 a|V6 a|V73 a|V4 a| 308.#216 I100 Def Alloc r10 | | | |V3 a|V2 a|V0 a|V1 a| |V40 a|I100a| |V5 a|V6 a|V73 a|V4 a| 309.#217 I100 Use * Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| |V40 a|I100i| |V5 a|V6 a|V73 a|V4 a| 310.#218 V41 Def Alloc r10 | | | |V3 a|V2 a|V0 a|V1 a| |V40 a| | |V5 a|V6 a|V73 a|V4 a| Spill r10 | | | |V3 a|V2 a|V0 a|V1 a| |V40 a| | |V5 a|V6 a|V73 a|V4 a| 317.#219 V40 Use Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| |V40 i| | |V5 a|V6 a|V73 a|V4 a| Spill r9 | | | |V3 a|V2 a|V0 a|V1 a| |V40 i| | |V5 a|V6 a|V73 a|V4 a| 318.#220 I101 Def Alloc rcx | |I101a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 319.#221 I101 Use * Keep rcx | |I101i| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 320.#222 V43 Def Alloc rcx | |V43 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 327.#223 V73 Use Keep r14 | |V43 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 328.#224 V45 Def Alloc rdx | |V43 a|V45 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 335.#225 V43 Use * Keep rcx | |V43 i|V45 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 339.#226 BB15 PredBB14 | | |V45 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 345.#227 rcx Fixd Keep rcx | | |V45 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 345.#228 V45 Use Copy rcx | |V45 a|V45 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 346.#229 rcx Fixd Keep rcx | | |V45 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 346.#230 I102 Def Alloc rcx | |I102a|V45 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 349.#231 rdx Fixd Keep rdx | |I102a|V45 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 349.#232 V45 Use * Keep rdx | |I102a|V45 i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 350.#233 rdx Fixd Keep rdx | |I102a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 350.#234 I103 Def Alloc rdx | |I102a|I103a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 351.#235 rcx Fixd Keep rcx | |I102a|I103a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 351.#236 I102 Use * Keep rcx | |I102i|I103a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 351.#237 rdx Fixd Keep rdx | | |I103a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 351.#238 I103 Use * Keep rdx | | |I103i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 352.#239 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 352.#240 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 352.#241 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 352.#242 r8 Kill Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 352.#243 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 352.#244 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 352.#245 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 353.#246 BB16 PredBB14 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 361.#247 V6 Use Keep r13 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 362.#248 I104 Def Alloc rdx | | |I104a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 363.#249 V41 Use * NoReg | | |I104a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 363.#250 I104 Use * Keep rdx | | |I104i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 364.#251 I105 Def Alloc rdx | | |I105a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 367.#252 I105 Use * Keep rdx | | |I105i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 368.#253 I106 Def Alloc rdx | | |I106a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 371.#254 I106 Use * Keep rdx | | |I106i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 372.#255 I107 Def Alloc rdx | | |I107a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 375.#256 V40 Use ReLod r9 | | |I107a|V3 a|V2 a|V0 a|V1 a| |V40 a| | |V5 a|V6 a|V73 a|V4 a| Keep r9 | | |I107a|V3 a|V2 a|V0 a|V1 a| |V40 a| | |V5 a|V6 a|V73 a|V4 a| 376.#257 I108 Def Alloc rcx | |I108a|I107a|V3 a|V2 a|V0 a|V1 a| |V40 a| | |V5 a|V6 a|V73 a|V4 a| 377.#258 I107 Use * Keep rdx | |I108a|I107i|V3 a|V2 a|V0 a|V1 a| |V40 a| | |V5 a|V6 a|V73 a|V4 a| 377.#259 I108 Use * Keep rcx | |I108i| |V3 a|V2 a|V0 a|V1 a| |V40 a| | |V5 a|V6 a|V73 a|V4 a| 378.#260 I109 Def Alloc rdx | | |I109a|V3 a|V2 a|V0 a|V1 a| |V40 a| | |V5 a|V6 a|V73 a|V4 a| 381.#261 I109 Use * Keep rdx | | |I109i|V3 a|V2 a|V0 a|V1 a| |V40 a| | |V5 a|V6 a|V73 a|V4 a| 382.#262 I110 Def Alloc rdx | | |I110a|V3 a|V2 a|V0 a|V1 a| |V40 a| | |V5 a|V6 a|V73 a|V4 a| 383.#263 I110 Use * Keep rdx | | |I110i|V3 a|V2 a|V0 a|V1 a| |V40 a| | |V5 a|V6 a|V73 a|V4 a| 384.#264 I111 Def Alloc r10 | | | |V3 a|V2 a|V0 a|V1 a| |V40 a|I111a| |V5 a|V6 a|V73 a|V4 a| 385.#265 I111 Use * Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| |V40 a|I111i| |V5 a|V6 a|V73 a|V4 a| 386.#266 V42 Def Alloc r10 | | | |V3 a|V2 a|V0 a|V1 a| |V40 a|V42 a| |V5 a|V6 a|V73 a|V4 a| 393.#267 rax Fixd Keep rax | | | |V3 a|V2 a|V0 a|V1 a| |V40 a|V42 a| |V5 a|V6 a|V73 a|V4 a| 393.#268 V6 Use Copy rax |V6 a| | |V3 a|V2 a|V0 a|V1 a| |V40 a|V42 a| |V5 a|V6 a|V73 a|V4 a| 393.#269 V40 Use *D Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| |V40 i|V42 a| |V5 a|V6 a|V73 a|V4 a| 394.#270 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | |V42 a| |V5 a|V6 a|V73 a|V4 a| 394.#271 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| | |V42 a| |V5 a|V6 a|V73 a|V4 a| 394.#272 rdx Fixd Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| | |V42 a| |V5 a|V6 a|V73 a|V4 a| 394.#273 I112 Def Alloc rdx | | |I112a|V3 a|V2 a|V0 a|V1 a| | |V42 a| |V5 a|V6 a|V73 a|V4 a| 397.#274 I112 Use * Keep rdx | | |I112i|V3 a|V2 a|V0 a|V1 a| | |V42 a| |V5 a|V6 a|V73 a|V4 a| 397.#275 V42 Use Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | |V42 i| |V5 a|V6 a|V73 a|V4 a| Spill r10 | | | |V3 a|V2 a|V0 a|V1 a| | |V42 i| |V5 a|V6 a|V73 a|V4 a| 398.#276 I113 Def Alloc rcx | |I113a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 399.#277 I113 Use * Keep rcx | |I113i| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 400.#278 V46 Def Alloc rcx | |V46 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 407.#279 V73 Use Keep r14 | |V46 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 408.#280 V48 Def Alloc rdx | |V46 a|V48 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 415.#281 V46 Use * Keep rcx | |V46 i|V48 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 419.#282 BB17 PredBB16 | | |V48 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 425.#283 rcx Fixd Keep rcx | | |V48 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 425.#284 V48 Use Copy rcx | |V48 a|V48 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 426.#285 rcx Fixd Keep rcx | | |V48 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 426.#286 I114 Def Alloc rcx | |I114a|V48 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 429.#287 rdx Fixd Keep rdx | |I114a|V48 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 429.#288 V48 Use * Keep rdx | |I114a|V48 i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 430.#289 rdx Fixd Keep rdx | |I114a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 430.#290 I115 Def Alloc rdx | |I114a|I115a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 431.#291 rcx Fixd Keep rcx | |I114a|I115a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 431.#292 I114 Use * Keep rcx | |I114i|I115a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 431.#293 rdx Fixd Keep rdx | | |I115a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 431.#294 I115 Use * Keep rdx | | |I115i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 432.#295 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 432.#296 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 432.#297 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 432.#298 r8 Kill Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 432.#299 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 432.#300 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 432.#301 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 433.#302 BB18 PredBB16 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 445.#303 V42 Use ReLod r10 | | | |V3 a|V2 a|V0 a|V1 a| | |V42 a| |V5 a|V6 a|V73 a|V4 a| Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | |V42 a| |V5 a|V6 a|V73 a|V4 a| 445.#304 V39 Use ReLod r8 | | | |V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| Keep r8 | | | |V3 a|V2 a|V0 a|V1 a|V39 a| |V42 a| |V5 a|V6 a|V73 a|V4 a| 451.#305 V42 Use * Keep r10 | | | |V3 a|V2 a|V0 a|V1 a|V39 a| |V42 i| |V5 a|V6 a|V73 a|V4 a| 452.#306 I116 Def Alloc rcx | |I116a| |V3 a|V2 a|V0 a|V1 a|V39 a| | | |V5 a|V6 a|V73 a|V4 a| 453.#307 V39 Use * Keep r8 | |I116a| |V3 a|V2 a|V0 a|V1 a|V39 i| | | |V5 a|V6 a|V73 a|V4 a| 453.#308 I116 Use * Keep rcx | |I116i| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 454.#309 I117 Def Alloc rax |I117a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 455.#310 I117 Use * Keep rax |I117i| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 456.#311 V38 Def Alloc rax |V38 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 459.#312 V38 Use * Keep rax |V38 i| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 460.#313 V8 Def Alloc rax |V8 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 465.#314 V8 Use Keep rax |V8 i| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| Spill rax |V8 i| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 466.#315 I118 Def Alloc r8 | | | |V3 a|V2 a|V0 a|V1 a|I118a| | | |V5 a|V6 a|V73 a|V4 a| 469.#316 I118 Use * Keep r8 | | | |V3 a|V2 a|V0 a|V1 a|I118i| | | |V5 a|V6 a|V73 a|V4 a| 470.#317 I119 Def Alloc r8 | | | |V3 a|V2 a|V0 a|V1 a|I119a| | | |V5 a|V6 a|V73 a|V4 a| 471.#318 I119 Use * Keep r8 | | | |V3 a|V2 a|V0 a|V1 a|I119i| | | |V5 a|V6 a|V73 a|V4 a| 472.#319 V9 Def Alloc r8 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| Spill r8 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 479.#320 V5 Use Keep r12 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 483.#321 BB19 PredBB18 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 489.#322 V0 Use Keep rsi | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 490.#323 I120 Def Alloc rcx | |I120a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 491.#324 I120 Use * Keep rcx | |I120i| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 492.#325 V24 Def Alloc rcx | |V24 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 497.#326 V24 Use Keep rcx | |V24 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 498.#327 I121 Def Alloc rdx | |V24 a|I121a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 499.#328 I121 Use * Keep rdx | |V24 a|I121i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 500.#329 I122 Def Alloc rdx | |V24 a|I122a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 503.#330 I122 Use * Keep rdx | |V24 a|I122i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 504.#331 I123 Def Alloc rdx | |V24 a|I123a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 505.#332 I123 Use * Keep rdx | |V24 a|I123i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 506.#333 V69 Def Alloc rdx | |V24 a|V69 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 511.#334 V69 Use Keep rdx | |V24 a|V69 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 515.#335 BB20 PredBB19 | | |V69 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 519.#336 V69 Use * Keep rdx | | |V69 i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 520.#337 V25 Def Alloc rdx | | |V25 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 521.#338 BB21 PredBB19 | |V24 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 525.#339 rcx Fixd Keep rcx | |V24 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 525.#340 V24 Use * Keep rcx | |V24 i| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 526.#341 rcx Fixd Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 526.#342 I124 Def Alloc rcx | |I124a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 528.#343 C125 Def Alloc rdx | |I124a|C125a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 529.#344 rdx Fixd Keep rdx | |I124a|C125a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 529.#345 C125 Use * Keep rdx | |I124a|C125i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 530.#346 rdx Fixd Keep rdx | |I124a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 530.#347 I126 Def Alloc rdx | |I124a|I126a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 531.#348 rcx Fixd Keep rcx | |I124a|I126a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 531.#349 I124 Use * Keep rcx | |I124i|I126a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 531.#350 rdx Fixd Keep rdx | | |I126a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 531.#351 I126 Use * Keep rdx | | |I126i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 532.#352 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 532.#353 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 532.#354 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 532.#355 r8 Kill Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 532.#356 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 532.#357 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 532.#358 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 532.#359 rax Fixd Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 532.#360 I127 Def Alloc rax |I127a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 533.#361 I127 Use * Keep rax |I127i| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 534.#362 V25 Def Alloc rdx | | |V25 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 535.#363 BB22 PredBB20 | | |V25 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 539.#364 rcx Fixd Keep rcx | | |V25 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 539.#365 V25 Use * Copy rcx | |V25 i|V25 i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 540.#366 rcx Fixd Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 540.#367 I128 Def Alloc rcx | |I128a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 541.#368 rcx Fixd Keep rcx | |I128a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 541.#369 I128 Use * Keep rcx | |I128i| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 542.#370 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 542.#371 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 542.#372 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 542.#373 r8 Kill Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 542.#374 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 542.#375 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 542.#376 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 542.#377 rax Fixd Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 542.#378 I129 Def Alloc rax |I129a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 543.#379 I129 Use * Keep rax |I129i| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 544.#380 V12 Def Alloc rax |V12 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 545.#381 BB23 PredBB22 |V12 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 553.#382 V4 Use Keep r15 |V12 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 554.#383 I130 Def Alloc r9 |V12 a| | |V3 a|V2 a|V0 a|V1 a| |I130a| | |V5 a|V6 a|V73 a|V4 a| 555.#384 I130 Use * Keep r9 |V12 a| | |V3 a|V2 a|V0 a|V1 a| |I130i| | |V5 a|V6 a|V73 a|V4 a| 556.#385 V76 Def Alloc r9 |V12 a| | |V3 a|V2 a|V0 a|V1 a| |V76 a| | |V5 a|V6 a|V73 a|V4 a| 561.#386 V76 Use Keep r9 |V12 a| | |V3 a|V2 a|V0 a|V1 a| |V76 i| | |V5 a|V6 a|V73 a|V4 a| Spill r9 |V12 a| | |V3 a|V2 a|V0 a|V1 a| |V76 i| | |V5 a|V6 a|V73 a|V4 a| 561.#387 V9 Use ReLod r10 |V12 a| | |V3 a|V2 a|V0 a|V1 a| | |V9 a| |V5 a|V6 a|V73 a|V4 a| Keep r10 |V12 a| | |V3 a|V2 a|V0 a|V1 a| | |V9 a| |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 565.#388 BB24 PredBB23 |V12 a| | |V3 a|V2 a|V0 a|V1 a| | |V9 a| |V5 a|V6 a|V73 a|V4 a| 573.#389 V9 Use * Keep r10 |V12 a| | |V3 a|V2 a|V0 a|V1 a| | |V9 i| |V5 a|V6 a|V73 a|V4 a| 574.#390 I131 Def Alloc rdx |V12 a| |I131a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 577.#391 I131 Use * Keep rdx |V12 a| |I131i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 578.#392 I132 Def Alloc rdx |V12 a| |I132a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 579.#393 I132 Use * Keep rdx |V12 a| |I132i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 580.#394 V70 Def Alloc rdx |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 583.#395 V4 Use Keep r15 |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 583.#396 V70 Use Keep rdx |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 584.#397 I133 Def Alloc r11 |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| | | |I133a|V5 a|V6 a|V73 a|V4 a| 585.#398 I133 Use * Keep r11 |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| | | |I133i|V5 a|V6 a|V73 a|V4 a| 586.#399 V65 Def Alloc r11 |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| | | |V65 a|V5 a|V6 a|V73 a|V4 a| 595.#400 V65 Use Keep r11 |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| | | |V65 i|V5 a|V6 a|V73 a|V4 a| Spill r11 |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| | | |V65 i|V5 a|V6 a|V73 a|V4 a| 595.#401 V6 Use Keep r13 |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 599.#402 BB25 PredBB24 |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 609.#403 V4 Use Keep r15 |V12 a| |V70 a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 609.#404 V70 Use * Keep rdx |V12 a| |V70 i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 610.#405 I134 Def Alloc rdx |V12 a| |I134a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 611.#406 rdx Fixd Keep rdx |V12 a| |I134a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 611.#407 I134 Use * Keep rdx |V12 a| |I134i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 612.#408 rdx Fixd Keep rdx |V12 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 612.#409 I135 Def Alloc rdx |V12 a| |I135a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 615.#410 rcx Fixd Keep rcx |V12 a| |I135a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 615.#411 V12 Use Copy rcx |V12 a|V12 a|I135a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 616.#412 rcx Fixd Keep rcx |V12 a| |I135a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 616.#413 I136 Def Alloc rcx |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 619.#414 r8 Fixd Keep r8 |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 619.#415 V1 Use Copy r8 |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a|V1 a| | | |V5 a|V6 a|V73 a|V4 a| 620.#416 r8 Fixd Keep r8 |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 620.#417 I137 Def Alloc r8 |V12 a|I136a|I135a|V3 a|V2 a|V0 a|V1 a|I137a| | | |V5 a|V6 a|V73 a|V4 a| 623.#418 V12 Use Keep rax |V12 i|I136a|I135a|V3 a|V2 a|V0 a|V1 a|I137a| | | |V5 a|V6 a|V73 a|V4 a| Spill rax |V12 i|I136a|I135a|V3 a|V2 a|V0 a|V1 a|I137a| | | |V5 a|V6 a|V73 a|V4 a| 624.#419 I138 Def Alloc r10 | |I136a|I135a|V3 a|V2 a|V0 a|V1 a|I137a| |I138a| |V5 a|V6 a|V73 a|V4 a| 627.#420 I138 Use * Keep r10 | |I136a|I135a|V3 a|V2 a|V0 a|V1 a|I137a| |I138i| |V5 a|V6 a|V73 a|V4 a| 628.#421 I139 Def Alloc r10 | |I136a|I135a|V3 a|V2 a|V0 a|V1 a|I137a| |I139a| |V5 a|V6 a|V73 a|V4 a| 633.#422 rdx Fixd Keep rdx | |I136a|I135a|V3 a|V2 a|V0 a|V1 a|I137a| |I139a| |V5 a|V6 a|V73 a|V4 a| 633.#423 I135 Use * Keep rdx | |I136a|I135i|V3 a|V2 a|V0 a|V1 a|I137a| |I139a| |V5 a|V6 a|V73 a|V4 a| 633.#424 rcx Fixd Keep rcx | |I136a| |V3 a|V2 a|V0 a|V1 a|I137a| |I139a| |V5 a|V6 a|V73 a|V4 a| 633.#425 I136 Use * Keep rcx | |I136i| |V3 a|V2 a|V0 a|V1 a|I137a| |I139a| |V5 a|V6 a|V73 a|V4 a| 633.#426 r8 Fixd Keep r8 | | | |V3 a|V2 a|V0 a|V1 a|I137a| |I139a| |V5 a|V6 a|V73 a|V4 a| 633.#427 I137 Use * Keep r8 | | | |V3 a|V2 a|V0 a|V1 a|I137i| |I139a| |V5 a|V6 a|V73 a|V4 a| 633.#428 I139 Use * Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | |I139i| |V5 a|V6 a|V73 a|V4 a| 634.#429 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 634.#430 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 634.#431 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 634.#432 r8 Kill Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 634.#433 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 634.#434 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 634.#435 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 634.#436 rax Fixd Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 634.#437 I140 Def Alloc rax |I140a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 637.#438 I140 Use * Keep rax |I140i| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 641.#0 V12 Move rax |V12 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 641.#439 BB26 PredBB24 |V12 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 649.#440 V65 Use * ReLod r11 |V12 a| | |V3 a|V2 a|V0 a|V1 a| | | |V65 a|V5 a|V6 a|V73 a|V4 a| Keep r11 |V12 a| | |V3 a|V2 a|V0 a|V1 a| | | |V65 i|V5 a|V6 a|V73 a|V4 a| 650.#441 I141 Def Alloc r10 |V12 a| | |V3 a|V2 a|V0 a|V1 a| | |I141a| |V5 a|V6 a|V73 a|V4 a| 651.#442 I141 Use * Keep r10 |V12 a| | |V3 a|V2 a|V0 a|V1 a| | |I141i| |V5 a|V6 a|V73 a|V4 a| 652.#443 V9 Def Alloc r8 |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 659.#444 V7 Use * ReLod r11 |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a| | |V7 a|V5 a|V6 a|V73 a|V4 a| Keep r11 |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a| | |V7 i|V5 a|V6 a|V73 a|V4 a| 660.#445 I142 Def Alloc r11 |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a| | |I142a|V5 a|V6 a|V73 a|V4 a| 661.#446 I142 Use * Keep r11 |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a| | |I142i|V5 a|V6 a|V73 a|V4 a| 662.#447 V7 Def Alloc r11 |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a| | |V7 a|V5 a|V6 a|V73 a|V4 a| 669.#448 V76 Use * NoReg |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a| | |V7 a|V5 a|V6 a|V73 a|V4 a| 669.#449 V7 Use Keep r11 |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a| | |V7 a|V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 673.#450 BB27 PredBB26 |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a| | |V7 a|V5 a|V6 a|V73 a|V4 a| 673.#0 V7 Move STK |V12 a| | |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 673.#0 V9 Move STK |V12 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 675.#451 V7 ExpU |V12 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 675.#452 V4 ExpU |V12 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 675.#453 V9 ExpU |V12 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 675.#454 V6 ExpU |V12 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 675.#455 V73 ExpU |V12 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 675.#456 V5 ExpU |V12 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 675.#457 V12 ExpU |V12 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 675.#458 V8 ExpU |V12 a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 675.#459 BB28 PredBB24 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 683.#460 V3 Use Keep rbx | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 687.#461 BB29 PredBB28 | | | | |V2 a|V0 a| | | | | | | | | | 693.#462 V65 Use * ReLod r11 | | | | |V2 a|V0 a| | | | |V65 a| | | | | Keep r11 | | | | |V2 a|V0 a| | | | |V65 i| | | | | 694.#463 I143 Def Alloc rcx | |I143a| | |V2 a|V0 a| | | | | | | | | | 697.#464 rcx Fixd Keep rcx | |I143a| | |V2 a|V0 a| | | | | | | | | | 697.#465 I143 Use * Keep rcx | |I143i| | |V2 a|V0 a| | | | | | | | | | 697.#466 rdx Fixd Keep rdx | | | | |V2 a|V0 a| | | | | | | | | | 697.#467 V2 Use * Copy rdx | | |V2 i| |V2 i|V0 a| | | | | | | | | | 698.#468 rax Kill Keep rax | | | | | |V0 a| | | | | | | | | | 698.#469 rcx Kill Keep rcx | | | | | |V0 a| | | | | | | | | | 698.#470 rdx Kill Keep rdx | | | | | |V0 a| | | | | | | | | | 698.#471 r8 Kill Keep r8 | | | | | |V0 a| | | | | | | | | | 698.#472 r9 Kill Keep r9 | | | | | |V0 a| | | | | | | | | | 698.#473 r10 Kill Keep r10 | | | | | |V0 a| | | | | | | | | | 698.#474 r11 Kill Keep r11 | | | | | |V0 a| | | | | | | | | | 698.#475 mm0 Kill Keep mm0 | | | | | |V0 a| | | | | | | | | | 698.#476 mm1 Kill Keep mm1 | | | | | |V0 a| | | | | | | | | | 698.#477 mm2 Kill Keep mm2 | | | | | |V0 a| | | | | | | | | | 698.#478 mm3 Kill Keep mm3 | | | | | |V0 a| | | | | | | | | | 698.#479 mm4 Kill Keep mm4 | | | | | |V0 a| | | | | | | | | | 698.#480 mm5 Kill Keep mm5 | | | | | |V0 a| | | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 699.#481 BB30 PredBB28 | | | |V3 a| |V0 a|V1 a| | | | | | | | | 707.#482 V3 Use * Keep rbx | | | |V3 i| |V0 a|V1 a| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 711.#483 BB31 PredBB30 | | | | | |V0 a| | | | | | | | | | 714.#484 C144 Def Alloc rax |C144a| | | | |V0 a| | | | | | | | | | 715.#485 rax Fixd Keep rax |C144a| | | | |V0 a| | | | | | | | | | 715.#486 C144 Use * Keep rax |C144i| | | | |V0 a| | | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 717.#487 BB32 PredBB18 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 725.#488 V4 Use Keep r15 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 726.#489 I145 Def Alloc r9 | | | |V3 a|V2 a|V0 a|V1 a| |I145a| | |V5 a|V6 a|V73 a|V4 a| 727.#490 I145 Use * Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| |I145i| | |V5 a|V6 a|V73 a|V4 a| 728.#491 V76 Def Alloc r9 | | | |V3 a|V2 a|V0 a|V1 a| |V76 a| | |V5 a|V6 a|V73 a|V4 a| 733.#492 V76 Use Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| |V76 i| | |V5 a|V6 a|V73 a|V4 a| Spill r9 | | | |V3 a|V2 a|V0 a|V1 a| |V76 i| | |V5 a|V6 a|V73 a|V4 a| 733.#493 V9 Use ReLod r8 | | | |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| Keep r8 | | | |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 737.#494 BB33 PredBB32 | | | |V3 a|V2 a|V0 a|V1 a|V9 a| | | |V5 a|V6 a|V73 a|V4 a| 745.#495 V9 Use * Keep r8 | | | |V3 a|V2 a|V0 a|V1 a|V9 i| | | |V5 a|V6 a|V73 a|V4 a| 746.#496 I146 Def Alloc rcx | |I146a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 749.#497 I146 Use * Keep rcx | |I146i| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 750.#498 I147 Def Alloc rcx | |I147a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 751.#499 I147 Use * Keep rcx | |I147i| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 752.#500 V71 Def Alloc rcx | |V71 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 755.#501 V4 Use Keep r15 | |V71 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 755.#502 V71 Use Keep rcx | |V71 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 756.#503 I148 Def Alloc r8 | |V71 a| |V3 a|V2 a|V0 a|V1 a|I148a| | | |V5 a|V6 a|V73 a|V4 a| 757.#504 I148 Use * Keep r8 | |V71 a| |V3 a|V2 a|V0 a|V1 a|I148i| | | |V5 a|V6 a|V73 a|V4 a| 758.#505 V66 Def Alloc r8 | |V71 a| |V3 a|V2 a|V0 a|V1 a|V66 a| | | |V5 a|V6 a|V73 a|V4 a| 767.#506 V66 Use Keep r8 | |V71 a| |V3 a|V2 a|V0 a|V1 a|V66 i| | | |V5 a|V6 a|V73 a|V4 a| Spill r8 | |V71 a| |V3 a|V2 a|V0 a|V1 a|V66 i| | | |V5 a|V6 a|V73 a|V4 a| 767.#507 V6 Use Keep r13 | |V71 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 771.#508 BB34 PredBB33 | |V71 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 781.#509 V4 Use Keep r15 | |V71 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 781.#510 V71 Use * Keep rcx | |V71 i| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 782.#511 I149 Def Alloc r10 | | | |V3 a|V2 a|V0 a|V1 a| | |I149a| |V5 a|V6 a|V73 a|V4 a| 783.#512 I149 Use * Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | |I149i| |V5 a|V6 a|V73 a|V4 a| 784.#513 V17 Def Alloc r10 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| Spill r10 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 789.#514 V0 Use Keep rsi | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 790.#515 I150 Def Alloc rcx | |I150a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 791.#516 I150 Use * Keep rcx | |I150i| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 792.#517 V16 Def Alloc rcx | |V16 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 797.#518 V16 Use Keep rcx | |V16 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 798.#519 I151 Def Alloc rdx | |V16 a|I151a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 799.#520 I151 Use * Keep rdx | |V16 a|I151i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 800.#521 I152 Def Alloc rdx | |V16 a|I152a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 803.#522 I152 Use * Keep rdx | |V16 a|I152i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 804.#523 I153 Def Alloc r11 | |V16 a| |V3 a|V2 a|V0 a|V1 a| | | |I153a|V5 a|V6 a|V73 a|V4 a| 805.#524 I153 Use * Keep r11 | |V16 a| |V3 a|V2 a|V0 a|V1 a| | | |I153i|V5 a|V6 a|V73 a|V4 a| 806.#525 V67 Def Alloc r11 | |V16 a| |V3 a|V2 a|V0 a|V1 a| | | |V67 a|V5 a|V6 a|V73 a|V4 a| 811.#526 V67 Use Keep r11 | |V16 a| |V3 a|V2 a|V0 a|V1 a| | | |V67 a|V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 815.#527 BB35 PredBB34 | | | |V3 a|V2 a|V0 a|V1 a| | | |V67 a|V5 a|V6 a|V73 a|V4 a| 815.#0 V17 Move r10 | | | |V3 a|V2 a|V0 a|V1 a| | |V17 a|V67 a|V5 a|V6 a|V73 a|V4 a| 819.#528 V67 Use * Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | |V17 a|V67 i|V5 a|V6 a|V73 a|V4 a| 820.#529 V19 Def Alloc r11 | | | |V3 a|V2 a|V0 a|V1 a| | |V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 821.#530 BB36 PredBB34 | |V16 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 825.#531 rcx Fixd Keep rcx | |V16 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 825.#532 V16 Use * Keep rcx | |V16 i| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 826.#533 rcx Fixd Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 826.#534 I154 Def Alloc rcx | |I154a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 828.#535 C155 Def Alloc rdx | |I154a|C155a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 829.#536 rdx Fixd Keep rdx | |I154a|C155a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 829.#537 C155 Use * Keep rdx | |I154a|C155i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 830.#538 rdx Fixd Keep rdx | |I154a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 830.#539 I156 Def Alloc rdx | |I154a|I156a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 831.#540 rcx Fixd Keep rcx | |I154a|I156a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 831.#541 I154 Use * Keep rcx | |I154i|I156a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 831.#542 rdx Fixd Keep rdx | | |I156a|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 831.#543 I156 Use * Keep rdx | | |I156i|V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 832.#544 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 832.#545 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 832.#546 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 832.#547 r8 Kill Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 832.#548 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 832.#549 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 832.#550 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 832.#551 rax Fixd Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 832.#552 I157 Def Alloc rax |I157a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 833.#553 I157 Use * Keep rax |I157i| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 834.#554 V19 Def Alloc r11 | | | |V3 a|V2 a|V0 a|V1 a| | | |V19 a|V5 a|V6 a|V73 a|V4 a| 835.#0 V17 Move r10 | | | |V3 a|V2 a|V0 a|V1 a| | |V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 835.#555 BB37 PredBB35 | | | |V3 a|V2 a|V0 a|V1 a| | |V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| 839.#556 rcx Fixd Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | |V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| 839.#557 V5 Use Copy rcx | |V5 a| |V3 a|V2 a|V0 a|V1 a| | |V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| 840.#558 rcx Fixd Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | |V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| 840.#559 I158 Def Alloc rcx | |I158a| |V3 a|V2 a|V0 a|V1 a| | |V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| 843.#560 r11 Fixd Keep r11 | |I158a| |V3 a|V2 a|V0 a|V1 a| | |V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| 843.#561 V19 Use Keep r11 | |I158a| |V3 a|V2 a|V0 a|V1 a| | |V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| 844.#562 r11 Fixd Keep r11 | |I158a| |V3 a|V2 a|V0 a|V1 a| | |V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| 844.#563 I159 Def PtArg r11 | |I158a| |V3 a|V2 a|V0 a|V1 a| | |V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| 847.#564 rdx Fixd Keep rdx | |I158a| |V3 a|V2 a|V0 a|V1 a| | |V17 a|V19 a|V5 a|V6 a|V73 a|V4 a| 847.#565 V17 Use * Copy rdx | |I158a|V17 i|V3 a|V2 a|V0 a|V1 a| | |V17 i|V19 a|V5 a|V6 a|V73 a|V4 a| 848.#566 rdx Fixd Keep rdx | |I158a| |V3 a|V2 a|V0 a|V1 a| | | |V19 a|V5 a|V6 a|V73 a|V4 a| 848.#567 I160 Def Alloc rdx | |I158a|I160a|V3 a|V2 a|V0 a|V1 a| | | |V19 a|V5 a|V6 a|V73 a|V4 a| 851.#568 r8 Fixd Keep r8 | |I158a|I160a|V3 a|V2 a|V0 a|V1 a| | | |V19 a|V5 a|V6 a|V73 a|V4 a| 851.#569 V1 Use Copy r8 | |I158a|I160a|V3 a|V2 a|V0 a|V1 a|V1 a| | |V19 a|V5 a|V6 a|V73 a|V4 a| 852.#570 r8 Fixd Keep r8 | |I158a|I160a|V3 a|V2 a|V0 a|V1 a| | | |V19 a|V5 a|V6 a|V73 a|V4 a| 852.#571 I161 Def Alloc r8 | |I158a|I160a|V3 a|V2 a|V0 a|V1 a|I161a| | |V19 a|V5 a|V6 a|V73 a|V4 a| 857.#572 rcx Fixd Keep rcx | |I158a|I160a|V3 a|V2 a|V0 a|V1 a|I161a| | |V19 a|V5 a|V6 a|V73 a|V4 a| 857.#573 I158 Use * Keep rcx | |I158i|I160a|V3 a|V2 a|V0 a|V1 a|I161a| | |V19 a|V5 a|V6 a|V73 a|V4 a| 857.#574 r11 Fixd Keep r11 | | |I160a|V3 a|V2 a|V0 a|V1 a|I161a| | |V19 a|V5 a|V6 a|V73 a|V4 a| 857.#575 I159 Use * PtArg r11 | | |I160a|V3 a|V2 a|V0 a|V1 a|I161a| | |V19 a|V5 a|V6 a|V73 a|V4 a| 857.#576 rdx Fixd Keep rdx | | |I160a|V3 a|V2 a|V0 a|V1 a|I161a| | | |V5 a|V6 a|V73 a|V4 a| 857.#577 I160 Use * Keep rdx | | |I160i|V3 a|V2 a|V0 a|V1 a|I161a| | | |V5 a|V6 a|V73 a|V4 a| 857.#578 r8 Fixd Keep r8 | | | |V3 a|V2 a|V0 a|V1 a|I161a| | | |V5 a|V6 a|V73 a|V4 a| 857.#579 I161 Use * Keep r8 | | | |V3 a|V2 a|V0 a|V1 a|I161i| | | |V5 a|V6 a|V73 a|V4 a| 857.#580 V19 Use * Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | |V19 i|V5 a|V6 a|V73 a|V4 a| 858.#581 rax Kill Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 858.#582 rcx Kill Keep rcx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 858.#583 rdx Kill Keep rdx | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 858.#584 r8 Kill Keep r8 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 858.#585 r9 Kill Keep r9 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 858.#586 r10 Kill Keep r10 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 858.#587 r11 Kill Keep r11 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 858.#588 rax Fixd Keep rax | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 858.#589 I162 Def Alloc rax |I162a| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 861.#590 I162 Use * Keep rax |I162i| | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 865.#591 BB38 PredBB37 | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | 873.#592 V3 Use Keep rbx | | | |V3 a|V2 a|V0 a|V1 a| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 877.#593 BB39 PredBB38 | | | | |V2 a|V0 a| | | | | | | | | | 883.#594 V66 Use * ReLod r15 | | | | |V2 a|V0 a| | | | | | | | |V66 a| Keep r15 | | | | |V2 a|V0 a| | | | | | | | |V66 i| 884.#595 I163 Def Alloc rcx | |I163a| | |V2 a|V0 a| | | | | | | | | | 887.#596 rcx Fixd Keep rcx | |I163a| | |V2 a|V0 a| | | | | | | | | | 887.#597 I163 Use * Keep rcx | |I163i| | |V2 a|V0 a| | | | | | | | | | 887.#598 rdx Fixd Keep rdx | | | | |V2 a|V0 a| | | | | | | | | | 887.#599 V2 Use * Copy rdx | | |V2 i| |V2 i|V0 a| | | | | | | | | | 888.#600 rax Kill Keep rax | | | | | |V0 a| | | | | | | | | | 888.#601 rcx Kill Keep rcx | | | | | |V0 a| | | | | | | | | | 888.#602 rdx Kill Keep rdx | | | | | |V0 a| | | | | | | | | | 888.#603 r8 Kill Keep r8 | | | | | |V0 a| | | | | | | | | | 888.#604 r9 Kill Keep r9 | | | | | |V0 a| | | | | | | | | | 888.#605 r10 Kill Keep r10 | | | | | |V0 a| | | | | | | | | | 888.#606 r11 Kill Keep r11 | | | | | |V0 a| | | | | | | | | | 888.#607 mm0 Kill Keep mm0 | | | | | |V0 a| | | | | | | | | | 888.#608 mm1 Kill Keep mm1 | | | | | |V0 a| | | | | | | | | | 888.#609 mm2 Kill Keep mm2 | | | | | |V0 a| | | | | | | | | | 888.#610 mm3 Kill Keep mm3 | | | | | |V0 a| | | | | | | | | | 888.#611 mm4 Kill Keep mm4 | | | | | |V0 a| | | | | | | | | | 888.#612 mm5 Kill Keep mm5 | | | | | |V0 a| | | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 889.#613 BB40 PredBB38 | | | |V3 a| |V0 a|V1 a| | | | | | | | | 897.#614 V3 Use * Keep rbx | | | |V3 i| |V0 a|V1 a| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 901.#615 BB41 PredBB40 | | | | | |V0 a| | | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 903.#616 BB42 PredBB33 | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 911.#617 V66 Use * ReLod r8 | | | |V3 a|V2 a|V0 a|V1 a|V66 a| | | |V5 a|V6 a|V73 a|V4 a| Keep r8 | | | |V3 a|V2 a|V0 a|V1 a|V66 i| | | |V5 a|V6 a|V73 a|V4 a| 912.#618 I164 Def Alloc r8 | | | |V3 a|V2 a|V0 a|V1 a|I164a| | | |V5 a|V6 a|V73 a|V4 a| 913.#619 I164 Use * Keep r8 | | | |V3 a|V2 a|V0 a|V1 a|I164i| | | |V5 a|V6 a|V73 a|V4 a| 914.#620 V9 Def Alloc rcx | |V9 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 921.#621 V7 Use * ReLod r8 | |V9 a| |V3 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a|V73 a|V4 a| Keep r8 | |V9 a| |V3 a|V2 a|V0 a|V1 a|V7 i| | | |V5 a|V6 a|V73 a|V4 a| 922.#622 I165 Def Alloc r8 | |V9 a| |V3 a|V2 a|V0 a|V1 a|I165a| | | |V5 a|V6 a|V73 a|V4 a| 923.#623 I165 Use * Keep r8 | |V9 a| |V3 a|V2 a|V0 a|V1 a|I165i| | | |V5 a|V6 a|V73 a|V4 a| 924.#624 V7 Def Alloc r8 | |V9 a| |V3 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a|V73 a|V4 a| 931.#625 V76 Use * NoReg | |V9 a| |V3 a|V2 a|V0 a|V1 a|V7 a| | | |V5 a|V6 a|V73 a|V4 a| 931.#626 V7 Use Keep r8 | |V9 a| |V3 a|V2 a|V0 a|V1 a|V7 i| | | |V5 a|V6 a|V73 a|V4 a| Spill r8 | |V9 a| |V3 a|V2 a|V0 a|V1 a|V7 i| | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 935.#627 BB43 PredBB42 | |V9 a| |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 935.#0 V9 Move STK | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 937.#628 V9 ExpU | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 937.#629 V3 ExpU | | | |V3 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 937.#630 BB44 PredBB23 | | | | |V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 949.#631 V0 Use Keep rsi | | | | |V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 953.#632 BB45 PredBB44 | | | | |V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 961.#633 V0 Use Keep rsi | | | | |V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 962.#634 I166 Def Alloc rcx | |I166a| | |V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 963.#635 I166 Use * Keep rcx | |I166i| | |V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 964.#636 V74 Def Alloc rcx | |V74 a| | |V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 967.#637 V74 Use Keep rcx | |V74 a| | |V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 968.#638 V10 Def Alloc rbx | |V74 a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 973.#639 V74 Use * Keep rcx | |V74 i| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 974.#640 V62 Def Alloc rcx | |V62 a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 979.#641 V62 Use Keep rcx | |V62 a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 979.#642 V76 Use ReLod r9 | |V62 a| |V10 a|V2 a|V0 a|V1 a| |V76 a| | |V5 a|V6 a|V73 a|V4 a| Keep r9 | |V62 a| |V10 a|V2 a|V0 a|V1 a| |V76 i| | |V5 a|V6 a|V73 a|V4 a| Spill r9 | |V62 a| |V10 a|V2 a|V0 a|V1 a| |V76 i| | |V5 a|V6 a|V73 a|V4 a| 985.#643 V62 Use * Keep rcx | |V62 i| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 986.#644 I167 Def Alloc rcx | |I167a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 989.#645 I167 Use * Keep rcx | |I167i| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 990.#646 I168 Def Alloc rcx | |I168a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 993.#647 V4 Use Keep r15 | |I168a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 993.#648 I168 Use * Keep rcx | |I168i| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 994.#649 I169 Def Alloc rcx | |I169a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 995.#650 I169 Use * Keep rcx | |I169i| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 996.#651 I170 Def Alloc rcx | |I170a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 999.#652 I170 Use * Keep rcx | |I170i| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 1000.#653 I171 Def Alloc rcx | |I171a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 1003.#654 I171 Use * Keep rcx | |I171i| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 1004.#655 I172 Def Alloc rcx | |I172a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 1005.#656 I172 Use * Keep rcx | |I172i| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 1006.#657 V49 Def Alloc rcx | |V49 a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V4 a| 1011.#658 V73 Use * Keep r14 | |V49 a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 i|V4 a| 1012.#659 V50 Def Alloc rdx | |V49 a|V50 a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1019.#660 V49 Use * Keep rcx | |V49 i|V50 a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1023.#661 BB46 PredBB45 | | |V50 a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1028.#662 C173 Def Alloc rcx | |C173a|V50 a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1029.#663 C173 Use * Keep rcx | |C173i|V50 a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1030.#664 I174 Def Alloc rcx | |I174a|V50 a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1031.#665 rcx Fixd Keep rcx | |I174a|V50 a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1031.#666 I174 Use * Keep rcx | |I174i|V50 a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1032.#667 rcx Fixd Keep rcx | | |V50 a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1032.#668 I175 Def Alloc rcx | |I175a|V50 a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1035.#669 rdx Fixd Keep rdx | |I175a|V50 a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1035.#670 V50 Use * Keep rdx | |I175a|V50 i|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1036.#671 rdx Fixd Keep rdx | |I175a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1036.#672 I176 Def Alloc rdx | |I175a|I176a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1037.#673 rcx Fixd Keep rcx | |I175a|I176a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1037.#674 I175 Use * Keep rcx | |I175i|I176a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1037.#675 rdx Fixd Keep rdx | | |I176a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1037.#676 I176 Use * Keep rdx | | |I176i|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1038.#677 rax Kill Keep rax | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1038.#678 rcx Kill Keep rcx | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1038.#679 rdx Kill Keep rdx | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1038.#680 r8 Kill Keep r8 | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1038.#681 r9 Kill Keep r9 | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1038.#682 r10 Kill Keep r10 | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1038.#683 r11 Kill Keep r11 | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1039.#684 BB47 PredBB45 | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1051.#685 V0 Use Keep rsi | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1052.#686 I177 Def Alloc rcx | |I177a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1053.#687 I177 Use * Keep rcx | |I177i| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1054.#688 V63 Def Alloc rcx | |V63 a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1059.#689 V63 Use Keep rcx | |V63 a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1059.#690 V76 Use * NoReg | |V63 a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1065.#691 V63 Use * Keep rcx | |V63 i| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1066.#692 I178 Def Alloc r9 | | | |V10 a|V2 a|V0 a|V1 a| |I178a| | |V5 a|V6 a| |V4 a| 1069.#693 I178 Use * Keep r9 | | | |V10 a|V2 a|V0 a|V1 a| |I178i| | |V5 a|V6 a| |V4 a| 1070.#694 I179 Def Alloc rcx | |I179a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1073.#695 V4 Use Keep r15 | |I179a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1073.#696 I179 Use * Keep rcx | |I179i| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1074.#697 I180 Def Alloc rcx | |I180a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1075.#698 I180 Use * Keep rcx | |I180i| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1076.#699 I181 Def Alloc rcx | |I181a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1079.#700 I181 Use * Keep rcx | |I181i| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1080.#701 I182 Def Alloc rcx | |I182a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1081.#702 V0 Use Keep rsi | |I182a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1081.#703 I182 Use * Keep rcx | |I182i| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1099.#704 V0 Use Keep rsi | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1101.#705 BB48 PredBB44 | | | | |V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1109.#706 V0 Use Keep rsi | | | | |V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1110.#707 I183 Def Alloc rcx | |I183a| | |V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1111.#708 I183 Use * Keep rcx | |I183i| | |V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1112.#709 V75 Def Alloc rcx | |V75 a| | |V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1115.#710 V75 Use Keep rcx | |V75 a| | |V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1116.#711 V13 Def Alloc rbx | |V75 a| |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1123.#712 V76 Use * NoReg | |V75 a| |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1123.#713 V13 Use Keep rbx | |V75 a| |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1127.#714 BB49 PredBB48 | |V75 a| |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1133.#715 rcx Fixd Keep rcx | |V75 a| |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1133.#716 V75 Use * Keep rcx | |V75 i| |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1134.#717 rcx Fixd Keep rcx | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1134.#718 I184 Def Alloc rcx | |I184a| |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1135.#719 rcx Fixd Keep rcx | |I184a| |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1135.#720 I184 Use * Keep rcx | |I184i| |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1136.#721 rax Kill Keep rax | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1136.#722 rcx Kill Keep rcx | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1136.#723 rdx Kill Keep rdx | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1136.#724 r8 Kill Keep r8 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1136.#725 r9 Kill Keep r9 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1136.#726 r10 Kill Keep r10 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1136.#727 r11 Kill Keep r11 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1136.#728 rax Fixd Keep rax | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1136.#729 I185 Def Alloc rax |I185a| | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1137.#730 I185 Use * Keep rax |I185i| | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1138.#731 V64 Def Alloc rdx | | |V64 a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1141.#732 rdx Fixd Keep rdx | | |V64 a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1141.#733 V64 Use * Keep rdx | | |V64 i|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1142.#734 rdx Fixd Keep rdx | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1142.#735 I186 Def Alloc rdx | | |I186a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1145.#736 rcx Fixd Keep rcx | | |I186a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1145.#737 V0 Use Copy rcx | |V0 a|I186a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1146.#738 rcx Fixd Keep rcx | | |I186a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1146.#739 I187 Def Alloc rcx | |I187a|I186a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1148.#740 C188 Def Alloc r8 | |I187a|I186a|V13 a|V2 a|V0 a|V1 a|C188a| | | |V5 a|V6 a|V73 a| | 1149.#741 r8 Fixd Keep r8 | |I187a|I186a|V13 a|V2 a|V0 a|V1 a|C188a| | | |V5 a|V6 a|V73 a| | 1149.#742 C188 Use * Keep r8 | |I187a|I186a|V13 a|V2 a|V0 a|V1 a|C188i| | | |V5 a|V6 a|V73 a| | 1150.#743 r8 Fixd Keep r8 | |I187a|I186a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1150.#744 I189 Def Alloc r8 | |I187a|I186a|V13 a|V2 a|V0 a|V1 a|I189a| | | |V5 a|V6 a|V73 a| | 1151.#745 rdx Fixd Keep rdx | |I187a|I186a|V13 a|V2 a|V0 a|V1 a|I189a| | | |V5 a|V6 a|V73 a| | 1151.#746 I186 Use * Keep rdx | |I187a|I186i|V13 a|V2 a|V0 a|V1 a|I189a| | | |V5 a|V6 a|V73 a| | 1151.#747 rcx Fixd Keep rcx | |I187a| |V13 a|V2 a|V0 a|V1 a|I189a| | | |V5 a|V6 a|V73 a| | 1151.#748 I187 Use * Keep rcx | |I187i| |V13 a|V2 a|V0 a|V1 a|I189a| | | |V5 a|V6 a|V73 a| | 1151.#749 r8 Fixd Keep r8 | | | |V13 a|V2 a|V0 a|V1 a|I189a| | | |V5 a|V6 a|V73 a| | 1151.#750 I189 Use * Keep r8 | | | |V13 a|V2 a|V0 a|V1 a|I189i| | | |V5 a|V6 a|V73 a| | 1152.#751 rax Kill Keep rax | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1152.#752 rcx Kill Keep rcx | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1152.#753 rdx Kill Keep rdx | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1152.#754 r8 Kill Keep r8 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1152.#755 r9 Kill Keep r9 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1152.#756 r10 Kill Keep r10 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1152.#757 r11 Kill Keep r11 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1159.#758 V0 Use Keep rsi | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a| | 1160.#759 I190 Def Alloc r15 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|I190a| 1161.#760 I190 Use * Keep r15 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|I190i| 1162.#761 V52 Def Alloc r15 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1169.#762 V52 Use Keep r15 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1170.#763 I191 Def Alloc rax |I191a| | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1171.#764 I191 Use * Keep rax |I191i| | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1172.#765 V72 Def Alloc rax |V72 a| | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1175.#766 V72 Use Keep rax |V72 i| | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| Spill rax |V72 i| | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1176.#767 V53 Def Alloc r8 | | | |V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1183.#768 V0 Use Keep rsi | | | |V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1184.#769 I192 Def Alloc r9 | | | |V13 a|V2 a|V0 a|V1 a|V53 a|I192a| | |V5 a|V6 a|V73 a|V52 a| 1185.#770 I192 Use * Keep r9 | | | |V13 a|V2 a|V0 a|V1 a|V53 a|I192i| | |V5 a|V6 a|V73 a|V52 a| 1186.#771 V54 Def Alloc r9 | | | |V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| Spill r9 | | | |V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1193.#772 V53 Use Keep r8 | | | |V13 a|V2 a|V0 a|V1 a|V53 i| | | |V5 a|V6 a|V73 a|V52 a| Spill r8 | | | |V13 a|V2 a|V0 a|V1 a|V53 i| | | |V5 a|V6 a|V73 a|V52 a| 1194.#773 I193 Def Alloc rcx | |I193a| |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1195.#774 I193 Use * Keep rcx | |I193i| |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1196.#775 V56 Def Alloc rcx | |V56 a| |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1203.#776 V73 Use Keep r14 | |V56 a| |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1204.#777 V58 Def Alloc rdx | |V56 a|V58 a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1211.#778 V56 Use * Keep rcx | |V56 i|V58 a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1215.#779 BB50 PredBB49 | | |V58 a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1221.#780 rcx Fixd Keep rcx | | |V58 a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1221.#781 V58 Use Copy rcx | |V58 a|V58 a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1222.#782 rcx Fixd Keep rcx | | |V58 a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1222.#783 I194 Def Alloc rcx | |I194a|V58 a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1225.#784 rdx Fixd Keep rdx | |I194a|V58 a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1225.#785 V58 Use * Keep rdx | |I194a|V58 i|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1226.#786 rdx Fixd Keep rdx | |I194a| |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1226.#787 I195 Def Alloc rdx | |I194a|I195a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1227.#788 rcx Fixd Keep rcx | |I194a|I195a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1227.#789 I194 Use * Keep rcx | |I194i|I195a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1227.#790 rdx Fixd Keep rdx | | |I195a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1227.#791 I195 Use * Keep rdx | | |I195i|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1228.#792 rax Kill Keep rax | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1228.#793 rcx Kill Keep rcx | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1228.#794 rdx Kill Keep rdx | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1228.#795 r8 Kill Keep r8 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1228.#796 r9 Kill Keep r9 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1228.#797 r10 Kill Keep r10 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1228.#798 r11 Kill Keep r11 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1229.#799 BB51 PredBB49 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1237.#800 V6 Use Keep r13 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1238.#801 I196 Def Alloc rdx | | |I196a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1239.#802 V54 Use * NoReg | | |I196a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1239.#803 I196 Use * Keep rdx | | |I196i|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1240.#804 I197 Def Alloc rdx | | |I197a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1243.#805 I197 Use * Keep rdx | | |I197i|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1244.#806 I198 Def Alloc rdx | | |I198a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1247.#807 I198 Use * Keep rdx | | |I198i|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1248.#808 I199 Def Alloc rdx | | |I199a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1251.#809 V53 Use ReLod r8 | | |I199a|V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| Keep r8 | | |I199a|V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1252.#810 I200 Def Alloc rcx | |I200a|I199a|V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1253.#811 I199 Use * Keep rdx | |I200a|I199i|V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1253.#812 I200 Use * Keep rcx | |I200i| |V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1254.#813 I201 Def Alloc rdx | | |I201a|V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1257.#814 I201 Use * Keep rdx | | |I201i|V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1258.#815 I202 Def Alloc rdx | | |I202a|V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1259.#816 I202 Use * Keep rdx | | |I202i|V13 a|V2 a|V0 a|V1 a|V53 a| | | |V5 a|V6 a|V73 a|V52 a| 1260.#817 I203 Def Alloc r9 | | | |V13 a|V2 a|V0 a|V1 a|V53 a|I203a| | |V5 a|V6 a|V73 a|V52 a| 1261.#818 I203 Use * Keep r9 | | | |V13 a|V2 a|V0 a|V1 a|V53 a|I203i| | |V5 a|V6 a|V73 a|V52 a| 1262.#819 V55 Def Alloc r9 | | | |V13 a|V2 a|V0 a|V1 a|V53 a|V55 a| | |V5 a|V6 a|V73 a|V52 a| 1269.#820 rax Fixd Keep rax | | | |V13 a|V2 a|V0 a|V1 a|V53 a|V55 a| | |V5 a|V6 a|V73 a|V52 a| 1269.#821 V6 Use Copy rax |V6 a| | |V13 a|V2 a|V0 a|V1 a|V53 a|V55 a| | |V5 a|V6 a|V73 a|V52 a| 1269.#822 V53 Use *D Keep r8 | | | |V13 a|V2 a|V0 a|V1 a|V53 i|V55 a| | |V5 a|V6 a|V73 a|V52 a| 1270.#823 rax Kill Keep rax | | | |V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a|V73 a|V52 a| 1270.#824 rdx Kill Keep rdx | | | |V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a|V73 a|V52 a| 1270.#825 rdx Fixd Keep rdx | | | |V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a|V73 a|V52 a| 1270.#826 I204 Def Alloc rdx | | |I204a|V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a|V73 a|V52 a| 1273.#827 I204 Use * Keep rdx | | |I204i|V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a|V73 a|V52 a| 1273.#828 V55 Use Keep r9 | | | |V13 a|V2 a|V0 a|V1 a| |V55 i| | |V5 a|V6 a|V73 a|V52 a| Spill r9 | | | |V13 a|V2 a|V0 a|V1 a| |V55 i| | |V5 a|V6 a|V73 a|V52 a| 1274.#829 I205 Def Alloc rcx | |I205a| |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1275.#830 I205 Use * Keep rcx | |I205i| |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1276.#831 V59 Def Alloc rcx | |V59 a| |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 a|V52 a| 1283.#832 V73 Use * Keep r14 | |V59 a| |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V73 i|V52 a| 1284.#833 V61 Def Alloc rdx | |V59 a|V61 a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1291.#834 V59 Use * Keep rcx | |V59 i|V61 a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1295.#835 BB52 PredBB51 | | |V61 a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1301.#836 rcx Fixd Keep rcx | | |V61 a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1301.#837 V61 Use Copy rcx | |V61 a|V61 a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1302.#838 rcx Fixd Keep rcx | | |V61 a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1302.#839 I206 Def Alloc rcx | |I206a|V61 a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1305.#840 rdx Fixd Keep rdx | |I206a|V61 a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1305.#841 V61 Use * Keep rdx | |I206a|V61 i|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1306.#842 rdx Fixd Keep rdx | |I206a| |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1306.#843 I207 Def Alloc rdx | |I206a|I207a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1307.#844 rcx Fixd Keep rcx | |I206a|I207a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1307.#845 I206 Use * Keep rcx | |I206i|I207a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1307.#846 rdx Fixd Keep rdx | | |I207a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1307.#847 I207 Use * Keep rdx | | |I207i|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1308.#848 rax Kill Keep rax | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1308.#849 rcx Kill Keep rcx | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1308.#850 rdx Kill Keep rdx | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1308.#851 r8 Kill Keep r8 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1308.#852 r9 Kill Keep r9 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1308.#853 r10 Kill Keep r10 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1308.#854 r11 Kill Keep r11 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1309.#855 BB53 PredBB51 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1317.#856 V55 Use ReLod r9 | | | |V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| Keep r9 | | | |V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1317.#857 V72 Use * NoReg | | | |V13 a|V2 a|V0 a|V1 a| |V55 a| | |V5 a|V6 a| |V52 a| 1323.#858 V55 Use * Keep r9 | | | |V13 a|V2 a|V0 a|V1 a| |V55 i| | |V5 a|V6 a| |V52 a| 1324.#859 I208 Def Alloc rdx | | |I208a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 a| 1325.#860 V52 Use * Keep r15 | | |I208a|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V52 i| 1325.#861 I208 Use * Keep rdx | | |I208i|V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| | | 1326.#862 I209 Def Alloc rax |I209a| | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| | | 1327.#863 I209 Use * Keep rax |I209i| | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| | | 1328.#864 V51 Def Alloc rax |V51 a| | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| | | 1331.#865 V51 Use * Keep rax |V51 i| | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| | | 1332.#866 V8 Def Alloc r14 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V8 a| | 1333.#0 V8 Move STK | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1333.#867 BB54 PredBB48 | | | |V13 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| | | 1339.#868 V13 Use * Keep rbx | | | |V13 i|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| | | 1340.#869 V10 Def Alloc rbx | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| | | 1347.#870 V10 Use Keep rbx | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| | | 1348.#871 I210 Def Alloc rdx | | |I210a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| | | 1353.#872 V0 Use Keep rsi | | |I210a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| | | 1353.#873 I210 Use * Keep rdx | | |I210i|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| | | 1361.#874 V0 Use Keep rsi | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| | | 1362.#875 I211 Def Alloc r15 | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |I211a| 1363.#876 I211 Use * Keep r15 | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |I211i| 1364.#877 V4 Def Alloc r15 | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1365.#878 BB55 PredBB47 | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1377.#879 V10 Use Keep rbx | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1377.#880 V4 Use Keep r15 | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1383.#881 V10 Use Keep rbx | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1384.#882 I212 Def Alloc rdx | | |I212a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1387.#883 I212 Use * Keep rdx | | |I212i|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1388.#884 I213 Def Alloc rdx | | |I213a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1389.#885 V4 Use Keep r15 | | |I213a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1389.#886 I213 Use * Keep rdx | | |I213i|V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a| |V4 a| 1390.#887 I214 Def Alloc r14 | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|I214a|V4 a| 1391.#888 I214 Use * Keep r14 | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|I214i|V4 a| 1392.#889 V11 Def Alloc r14 | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V11 a|V4 a| 1401.#890 V11 Use Keep r14 | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 a|V11 a|V4 a| 1401.#891 V6 Use * Keep r13 | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a|V6 i|V11 a|V4 a| 1407.#892 V8 Use ReLod rax |V8 a| | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a| |V11 a|V4 a| Keep rax |V8 i| | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a| |V11 a|V4 a| Spill rax |V8 i| | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a| |V11 a|V4 a| 1408.#893 I215 Def Alloc rdx | | |I215a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a| |V11 a|V4 a| 1411.#894 I215 Use * Keep rdx | | |I215i|V10 a|V2 a|V0 a|V1 a| | | | |V5 a| |V11 a|V4 a| 1412.#895 I216 Def Alloc rdx | | |I216a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a| |V11 a|V4 a| 1417.#896 V11 Use Keep r14 | | |I216a|V10 a|V2 a|V0 a|V1 a| | | | |V5 a| |V11 a|V4 a| 1417.#897 I216 Use * Keep rdx | | |I216i|V10 a|V2 a|V0 a|V1 a| | | | |V5 a| |V11 a|V4 a| 1425.#898 rcx Fixd Keep rcx | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a| |V11 a|V4 a| 1425.#899 V11 Use Copy rcx | |V11 a| |V10 a|V2 a|V0 a|V1 a| | | | |V5 a| |V11 a|V4 a| 1425.#900 rdx Fixd Keep rdx | | | |V10 a|V2 a|V0 a|V1 a| | | | |V5 a| |V11 a|V4 a| 1425.#901 V1 Use * Copy rdx | | |V1 i|V10 a|V2 a|V0 a|V1 i| | | | |V5 a| |V11 a|V4 a| 1426.#902 rax Kill Keep rax | | | |V10 a|V2 a|V0 a| | | | | |V5 a| |V11 a|V4 a| 1426.#903 rcx Kill Keep rcx | | | |V10 a|V2 a|V0 a| | | | | |V5 a| |V11 a|V4 a| 1426.#904 rdx Kill Keep rdx | | | |V10 a|V2 a|V0 a| | | | | |V5 a| |V11 a|V4 a| 1426.#905 r8 Kill Keep r8 | | | |V10 a|V2 a|V0 a| | | | | |V5 a| |V11 a|V4 a| 1426.#906 r9 Kill Keep r9 | | | |V10 a|V2 a|V0 a| | | | | |V5 a| |V11 a|V4 a| 1426.#907 r10 Kill Keep r10 | | | |V10 a|V2 a|V0 a| | | | | |V5 a| |V11 a|V4 a| 1426.#908 r11 Kill Keep r11 | | | |V10 a|V2 a|V0 a| | | | | |V5 a| |V11 a|V4 a| 1426.#909 mm0 Kill Keep mm0 | | | |V10 a|V2 a|V0 a| | | | | |V5 a| |V11 a|V4 a| 1426.#910 mm1 Kill Keep mm1 | | | |V10 a|V2 a|V0 a| | | | | |V5 a| |V11 a|V4 a| 1426.#911 mm2 Kill Keep mm2 | | | |V10 a|V2 a|V0 a| | | | | |V5 a| |V11 a|V4 a| 1426.#912 mm3 Kill Keep mm3 | | | |V10 a|V2 a|V0 a| | | | | |V5 a| |V11 a|V4 a| 1426.#913 mm4 Kill Keep mm4 | | | |V10 a|V2 a|V0 a| | | | | |V5 a| |V11 a|V4 a| 1426.#914 mm5 Kill Keep mm5 | | | |V10 a|V2 a|V0 a| | | | | |V5 a| |V11 a|V4 a| 1431.#915 V11 Use * Keep r14 | | | |V10 a|V2 a|V0 a| | | | | |V5 a| |V11 i|V4 a| 1432.#916 I217 Def Alloc rcx | |I217a| |V10 a|V2 a|V0 a| | | | | |V5 a| | |V4 a| 1435.#917 rcx Fixd Keep rcx | |I217a| |V10 a|V2 a|V0 a| | | | | |V5 a| | |V4 a| 1435.#918 I217 Use * Keep rcx | |I217i| |V10 a|V2 a|V0 a| | | | | |V5 a| | |V4 a| 1435.#919 rdx Fixd Keep rdx | | | |V10 a|V2 a|V0 a| | | | | |V5 a| | |V4 a| 1435.#920 V2 Use * Copy rdx | | |V2 i|V10 a|V2 i|V0 a| | | | | |V5 a| | |V4 a| 1436.#921 rax Kill Keep rax | | | |V10 a| |V0 a| | | | | |V5 a| | |V4 a| 1436.#922 rcx Kill Keep rcx | | | |V10 a| |V0 a| | | | | |V5 a| | |V4 a| 1436.#923 rdx Kill Keep rdx | | | |V10 a| |V0 a| | | | | |V5 a| | |V4 a| 1436.#924 r8 Kill Keep r8 | | | |V10 a| |V0 a| | | | | |V5 a| | |V4 a| 1436.#925 r9 Kill Keep r9 | | | |V10 a| |V0 a| | | | | |V5 a| | |V4 a| 1436.#926 r10 Kill Keep r10 | | | |V10 a| |V0 a| | | | | |V5 a| | |V4 a| 1436.#927 r11 Kill Keep r11 | | | |V10 a| |V0 a| | | | | |V5 a| | |V4 a| 1436.#928 mm0 Kill Keep mm0 | | | |V10 a| |V0 a| | | | | |V5 a| | |V4 a| 1436.#929 mm1 Kill Keep mm1 | | | |V10 a| |V0 a| | | | | |V5 a| | |V4 a| 1436.#930 mm2 Kill Keep mm2 | | | |V10 a| |V0 a| | | | | |V5 a| | |V4 a| 1436.#931 mm3 Kill Keep mm3 | | | |V10 a| |V0 a| | | | | |V5 a| | |V4 a| 1436.#932 mm4 Kill Keep mm4 | | | |V10 a| |V0 a| | | | | |V5 a| | |V4 a| 1436.#933 mm5 Kill Keep mm5 | | | |V10 a| |V0 a| | | | | |V5 a| | |V4 a| 1443.#934 V10 Use * Keep rbx | | | |V10 i| |V0 a| | | | | |V5 a| | |V4 a| 1444.#935 I218 Def Alloc rbx | | | |I218a| |V0 a| | | | | |V5 a| | |V4 a| 1447.#936 V8 Use * ReLod r14 | | | |I218a| |V0 a| | | | | |V5 a| |V8 a|V4 a| Keep r14 | | | |I218a| |V0 a| | | | | |V5 a| |V8 i|V4 a| 1447.#937 I218 Use * Keep rbx | | | |I218i| |V0 a| | | | | |V5 a| | |V4 a| 1465.#938 V0 Use Keep rsi | | | | | |V0 a| | | | | |V5 a| | |V4 a| 1473.#939 V7 Use * NoReg | | | | | |V0 a| | | | | |V5 a| | |V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1477.#940 BB56 PredBB55 | | | | | |V0 a| | | | | |V5 a| | |V4 a| 1483.#941 rdx Fixd Keep rdx | | | | | |V0 a| | | | | |V5 a| | |V4 a| 1483.#942 V5 Use * Copy rdx | | |V5 i| | |V0 a| | | | | |V5 i| | |V4 a| 1484.#943 rdx Fixd Keep rdx | | | | | |V0 a| | | | | | | | |V4 a| 1484.#944 I219 Def Alloc rdx | | |I219a| | |V0 a| | | | | | | | |V4 a| 1486.#945 C220 Def Alloc rcx | |C220a|I219a| | |V0 a| | | | | | | | |V4 a| 1487.#946 rcx Fixd Keep rcx | |C220a|I219a| | |V0 a| | | | | | | | |V4 a| 1487.#947 C220 Use * Keep rcx | |C220i|I219a| | |V0 a| | | | | | | | |V4 a| 1488.#948 rcx Fixd Keep rcx | | |I219a| | |V0 a| | | | | | | | |V4 a| 1488.#949 I221 Def Alloc rcx | |I221a|I219a| | |V0 a| | | | | | | | |V4 a| 1489.#950 rdx Fixd Keep rdx | |I221a|I219a| | |V0 a| | | | | | | | |V4 a| 1489.#951 I219 Use * Keep rdx | |I221a|I219i| | |V0 a| | | | | | | | |V4 a| 1489.#952 rcx Fixd Keep rcx | |I221a| | | |V0 a| | | | | | | | |V4 a| 1489.#953 I221 Use * Keep rcx | |I221i| | | |V0 a| | | | | | | | |V4 a| 1490.#954 rax Kill Keep rax | | | | | |V0 a| | | | | | | | |V4 a| 1490.#955 rcx Kill Keep rcx | | | | | |V0 a| | | | | | | | |V4 a| 1490.#956 rdx Kill Keep rdx | | | | | |V0 a| | | | | | | | |V4 a| 1490.#957 r8 Kill Keep r8 | | | | | |V0 a| | | | | | | | |V4 a| 1490.#958 r9 Kill Keep r9 | | | | | |V0 a| | | | | | | | |V4 a| 1490.#959 r10 Kill Keep r10 | | | | | |V0 a| | | | | | | | |V4 a| 1490.#960 r11 Kill Keep r11 | | | | | |V0 a| | | | | | | | |V4 a| 1490.#961 rax Fixd Keep rax | | | | | |V0 a| | | | | | | | |V4 a| 1490.#962 I222 Def Alloc rax |I222a| | | | |V0 a| | | | | | | | |V4 a| 1493.#963 I222 Use * Keep rax |I222i| | | | |V0 a| | | | | | | | |V4 a| --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1497.#964 BB57 PredBB56 | | | | | |V0 a| | | | | | | | |V4 a| 1505.#965 V4 Use * Keep r15 | | | | | |V0 a| | | | | | | | |V4 i| 1506.#966 I223 Def Alloc rdx | | |I223a| | |V0 a| | | | | | | | | | 1507.#967 rdx Fixd Keep rdx | | |I223a| | |V0 a| | | | | | | | | | 1507.#968 I223 Use * Keep rdx | | |I223i| | |V0 a| | | | | | | | | | 1508.#969 rdx Fixd Keep rdx | | | | | |V0 a| | | | | | | | | | 1508.#970 I224 Def Alloc rdx | | |I224a| | |V0 a| | | | | | | | | | 1511.#971 rcx Fixd Keep rcx | | |I224a| | |V0 a| | | | | | | | | | 1511.#972 V0 Use Copy rcx | |V0 a|I224a| | |V0 a| | | | | | | | | | 1512.#973 rcx Fixd Keep rcx | | |I224a| | |V0 a| | | | | | | | | | 1512.#974 I225 Def Alloc rcx | |I225a|I224a| | |V0 a| | | | | | | | | | 1514.#975 C226 Def Alloc r8 | |I225a|I224a| | |V0 a| |C226a| | | | | | | | 1515.#976 r8 Fixd Keep r8 | |I225a|I224a| | |V0 a| |C226a| | | | | | | | 1515.#977 C226 Use * Keep r8 | |I225a|I224a| | |V0 a| |C226i| | | | | | | | 1516.#978 r8 Fixd Keep r8 | |I225a|I224a| | |V0 a| | | | | | | | | | 1516.#979 I227 Def Alloc r8 | |I225a|I224a| | |V0 a| |I227a| | | | | | | | 1517.#980 rdx Fixd Keep rdx | |I225a|I224a| | |V0 a| |I227a| | | | | | | | 1517.#981 I224 Use * Keep rdx | |I225a|I224i| | |V0 a| |I227a| | | | | | | | 1517.#982 rcx Fixd Keep rcx | |I225a| | | |V0 a| |I227a| | | | | | | | 1517.#983 I225 Use * Keep rcx | |I225i| | | |V0 a| |I227a| | | | | | | | 1517.#984 r8 Fixd Keep r8 | | | | | |V0 a| |I227a| | | | | | | | 1517.#985 I227 Use * Keep r8 | | | | | |V0 a| |I227i| | | | | | | | 1518.#986 rax Kill Keep rax | | | | | |V0 a| | | | | | | | | | 1518.#987 rcx Kill Keep rcx | | | | | |V0 a| | | | | | | | | | 1518.#988 rdx Kill Keep rdx | | | | | |V0 a| | | | | | | | | | 1518.#989 r8 Kill Keep r8 | | | | | |V0 a| | | | | | | | | | 1518.#990 r9 Kill Keep r9 | | | | | |V0 a| | | | | | | | | | 1518.#991 r10 Kill Keep r10 | | | | | |V0 a| | | | | | | | | | 1518.#992 r11 Kill Keep r11 | | | | | |V0 a| | | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1519.#993 BB58 PredBB29 | | | | | |V0 a| | | | | | | | | | 1522.#994 C228 Def Alloc rax |C228a| | | | |V0 a| | | | | | | | | | 1523.#995 rax Fixd Keep rax |C228a| | | | |V0 a| | | | | | | | | | 1523.#996 C228 Use * Keep rax |C228i| | | | |V0 a| | | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1525.#997 BB59 PredBB1 | | | | | |V0 a| | | | | | | | | | 1530.#998 C229 Def Alloc rcx | |C229a| | | |V0 a| | | | | | | | | | 1531.#999 rcx Fixd Keep rcx | |C229a| | | |V0 a| | | | | | | | | | 1531.#1000 C229 Use * Keep rcx | |C229i| | | |V0 a| | | | | | | | | | 1532.#1001 rcx Fixd Keep rcx | | | | | |V0 a| | | | | | | | | | 1532.#1002 I230 Def Alloc rcx | |I230a| | | |V0 a| | | | | | | | | | 1533.#1003 rcx Fixd Keep rcx | |I230a| | | |V0 a| | | | | | | | | | 1533.#1004 I230 Use * Keep rcx | |I230i| | | |V0 a| | | | | | | | | | 1534.#1005 rax Kill Keep rax | | | | | |V0 a| | | | | | | | | | 1534.#1006 rcx Kill Keep rcx | | | | | |V0 a| | | | | | | | | | 1534.#1007 rdx Kill Keep rdx | | | | | |V0 a| | | | | | | | | | 1534.#1008 r8 Kill Keep r8 | | | | | |V0 a| | | | | | | | | | 1534.#1009 r9 Kill Keep r9 | | | | | |V0 a| | | | | | | | | | 1534.#1010 r10 Kill Keep r10 | | | | | |V0 a| | | | | | | | | | 1534.#1011 r11 Kill Keep r11 | | | | | |V0 a| | | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1535.#1012 BB60 PredBB30 | | | | | |V0 a|V1 a| | | | | | | | | 1541.#1013 V0 Use Keep rsi | | | | | |V0 a|V1 a| | | | | | | | | 1542.#1014 I231 Def Alloc rcx | |I231a| | | |V0 a|V1 a| | | | | | | | | 1543.#1015 I231 Use * Keep rcx | |I231i| | | |V0 a|V1 a| | | | | | | | | 1544.#1016 V26 Def Alloc rcx | |V26 a| | | |V0 a|V1 a| | | | | | | | | 1549.#1017 V26 Use Keep rcx | |V26 a| | | |V0 a|V1 a| | | | | | | | | 1550.#1018 I232 Def Alloc rdx | |V26 a|I232a| | |V0 a|V1 a| | | | | | | | | 1551.#1019 I232 Use * Keep rdx | |V26 a|I232i| | |V0 a|V1 a| | | | | | | | | 1552.#1020 I233 Def Alloc rdx | |V26 a|I233a| | |V0 a|V1 a| | | | | | | | | 1559.#1021 I233 Use * Keep rdx | |V26 a|I233i| | |V0 a|V1 a| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1563.#1022 BB61 PredBB60 | |V26 a| | | |V0 a|V1 a| | | | | | | | | 1569.#1023 V26 Use * Keep rcx | |V26 i| | | |V0 a|V1 a| | | | | | | | | 1570.#1024 I234 Def Alloc rcx | |I234a| | | |V0 a|V1 a| | | | | | | | | 1571.#1025 I234 Use * Keep rcx | |I234i| | | |V0 a|V1 a| | | | | | | | | 1572.#1026 I235 Def Alloc rcx | |I235a| | | |V0 a|V1 a| | | | | | | | | 1575.#1027 I235 Use * Keep rcx | |I235i| | | |V0 a|V1 a| | | | | | | | | 1576.#1028 I236 Def Alloc rcx | |I236a| | | |V0 a|V1 a| | | | | | | | | 1577.#1029 I236 Use * Keep rcx | |I236i| | | |V0 a|V1 a| | | | | | | | | 1578.#1030 V28 Def Alloc rcx | |V28 a| | | |V0 a|V1 a| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1579.#1031 BB62 PredBB60 | |V26 a| | | |V0 a|V1 a| | | | | | | | | 1583.#1032 rcx Fixd Keep rcx | |V26 a| | | |V0 a|V1 a| | | | | | | | | 1583.#1033 V26 Use * Keep rcx | |V26 i| | | |V0 a|V1 a| | | | | | | | | 1584.#1034 rcx Fixd Keep rcx | | | | | |V0 a|V1 a| | | | | | | | | 1584.#1035 I237 Def Alloc rcx | |I237a| | | |V0 a|V1 a| | | | | | | | | 1586.#1036 C238 Def Alloc rdx | |I237a|C238a| | |V0 a|V1 a| | | | | | | | | 1587.#1037 rdx Fixd Keep rdx | |I237a|C238a| | |V0 a|V1 a| | | | | | | | | 1587.#1038 C238 Use * Keep rdx | |I237a|C238i| | |V0 a|V1 a| | | | | | | | | 1588.#1039 rdx Fixd Keep rdx | |I237a| | | |V0 a|V1 a| | | | | | | | | 1588.#1040 I239 Def Alloc rdx | |I237a|I239a| | |V0 a|V1 a| | | | | | | | | 1589.#1041 rcx Fixd Keep rcx | |I237a|I239a| | |V0 a|V1 a| | | | | | | | | 1589.#1042 I237 Use * Keep rcx | |I237i|I239a| | |V0 a|V1 a| | | | | | | | | 1589.#1043 rdx Fixd Keep rdx | | |I239a| | |V0 a|V1 a| | | | | | | | | 1589.#1044 I239 Use * Keep rdx | | |I239i| | |V0 a|V1 a| | | | | | | | | 1590.#1045 rax Kill Keep rax | | | | | |V0 a|V1 a| | | | | | | | | 1590.#1046 rcx Kill Keep rcx | | | | | |V0 a|V1 a| | | | | | | | | 1590.#1047 rdx Kill Keep rdx | | | | | |V0 a|V1 a| | | | | | | | | 1590.#1048 r8 Kill Keep r8 | | | | | |V0 a|V1 a| | | | | | | | | 1590.#1049 r9 Kill Keep r9 | | | | | |V0 a|V1 a| | | | | | | | | 1590.#1050 r10 Kill Keep r10 | | | | | |V0 a|V1 a| | | | | | | | | 1590.#1051 r11 Kill Keep r11 | | | | | |V0 a|V1 a| | | | | | | | | 1590.#1052 rax Fixd Keep rax | | | | | |V0 a|V1 a| | | | | | | | | 1590.#1053 I240 Def Alloc rax |I240a| | | | |V0 a|V1 a| | | | | | | | | 1591.#1054 I240 Use * Keep rax |I240i| | | | |V0 a|V1 a| | | | | | | | | 1592.#1055 V28 Def Alloc rcx | |V28 a| | | |V0 a|V1 a| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1593.#1056 BB63 PredBB61 | |V28 a| | | |V0 a|V1 a| | | | | | | | | 1597.#1057 rcx Fixd Keep rcx | |V28 a| | | |V0 a|V1 a| | | | | | | | | 1597.#1058 V28 Use * Keep rcx | |V28 i| | | |V0 a|V1 a| | | | | | | | | 1598.#1059 rcx Fixd Keep rcx | | | | | |V0 a|V1 a| | | | | | | | | 1598.#1060 I241 Def Alloc rcx | |I241a| | | |V0 a|V1 a| | | | | | | | | 1601.#1061 rdx Fixd Keep rdx | |I241a| | | |V0 a|V1 a| | | | | | | | | 1601.#1062 V1 Use * Copy rdx | |I241a|V1 i| | |V0 a|V1 i| | | | | | | | | 1602.#1063 rdx Fixd Keep rdx | |I241a| | | |V0 a| | | | | | | | | | 1602.#1064 I242 Def Alloc rdx | |I241a|I242a| | |V0 a| | | | | | | | | | 1603.#1065 rcx Fixd Keep rcx | |I241a|I242a| | |V0 a| | | | | | | | | | 1603.#1066 I241 Use * Keep rcx | |I241i|I242a| | |V0 a| | | | | | | | | | 1603.#1067 rdx Fixd Keep rdx | | |I242a| | |V0 a| | | | | | | | | | 1603.#1068 I242 Use * Keep rdx | | |I242i| | |V0 a| | | | | | | | | | 1604.#1069 rax Kill Keep rax | | | | | |V0 a| | | | | | | | | | 1604.#1070 rcx Kill Keep rcx | | | | | |V0 a| | | | | | | | | | 1604.#1071 rdx Kill Keep rdx | | | | | |V0 a| | | | | | | | | | 1604.#1072 r8 Kill Keep r8 | | | | | |V0 a| | | | | | | | | | 1604.#1073 r9 Kill Keep r9 | | | | | |V0 a| | | | | | | | | | 1604.#1074 r10 Kill Keep r10 | | | | | |V0 a| | | | | | | | | | 1604.#1075 r11 Kill Keep r11 | | | | | |V0 a| | | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1605.#1076 BB64 PredBB40 | | | | | |V0 a|V1 a| | | | | | | | | 1611.#1077 V0 Use Keep rsi | | | | | |V0 a|V1 a| | | | | | | | | 1612.#1078 I243 Def Alloc rcx | |I243a| | | |V0 a|V1 a| | | | | | | | | 1613.#1079 I243 Use * Keep rcx | |I243i| | | |V0 a|V1 a| | | | | | | | | 1614.#1080 V21 Def Alloc rcx | |V21 a| | | |V0 a|V1 a| | | | | | | | | 1619.#1081 V21 Use Keep rcx | |V21 a| | | |V0 a|V1 a| | | | | | | | | 1620.#1082 I244 Def Alloc rdx | |V21 a|I244a| | |V0 a|V1 a| | | | | | | | | 1621.#1083 I244 Use * Keep rdx | |V21 a|I244i| | |V0 a|V1 a| | | | | | | | | 1622.#1084 I245 Def Alloc rdx | |V21 a|I245a| | |V0 a|V1 a| | | | | | | | | 1629.#1085 I245 Use * Keep rdx | |V21 a|I245i| | |V0 a|V1 a| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1633.#1086 BB65 PredBB64 | |V21 a| | | |V0 a|V1 a| | | | | | | | | 1639.#1087 V21 Use * Keep rcx | |V21 i| | | |V0 a|V1 a| | | | | | | | | 1640.#1088 I246 Def Alloc rcx | |I246a| | | |V0 a|V1 a| | | | | | | | | 1641.#1089 I246 Use * Keep rcx | |I246i| | | |V0 a|V1 a| | | | | | | | | 1642.#1090 I247 Def Alloc rcx | |I247a| | | |V0 a|V1 a| | | | | | | | | 1645.#1091 I247 Use * Keep rcx | |I247i| | | |V0 a|V1 a| | | | | | | | | 1646.#1092 I248 Def Alloc rcx | |I248a| | | |V0 a|V1 a| | | | | | | | | 1647.#1093 I248 Use * Keep rcx | |I248i| | | |V0 a|V1 a| | | | | | | | | 1648.#1094 V23 Def Alloc rcx | |V23 a| | | |V0 a|V1 a| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1649.#1095 BB66 PredBB64 | |V21 a| | | |V0 a|V1 a| | | | | | | | | 1653.#1096 rcx Fixd Keep rcx | |V21 a| | | |V0 a|V1 a| | | | | | | | | 1653.#1097 V21 Use * Keep rcx | |V21 i| | | |V0 a|V1 a| | | | | | | | | 1654.#1098 rcx Fixd Keep rcx | | | | | |V0 a|V1 a| | | | | | | | | 1654.#1099 I249 Def Alloc rcx | |I249a| | | |V0 a|V1 a| | | | | | | | | 1656.#1100 C250 Def Alloc rdx | |I249a|C250a| | |V0 a|V1 a| | | | | | | | | 1657.#1101 rdx Fixd Keep rdx | |I249a|C250a| | |V0 a|V1 a| | | | | | | | | 1657.#1102 C250 Use * Keep rdx | |I249a|C250i| | |V0 a|V1 a| | | | | | | | | 1658.#1103 rdx Fixd Keep rdx | |I249a| | | |V0 a|V1 a| | | | | | | | | 1658.#1104 I251 Def Alloc rdx | |I249a|I251a| | |V0 a|V1 a| | | | | | | | | 1659.#1105 rcx Fixd Keep rcx | |I249a|I251a| | |V0 a|V1 a| | | | | | | | | 1659.#1106 I249 Use * Keep rcx | |I249i|I251a| | |V0 a|V1 a| | | | | | | | | 1659.#1107 rdx Fixd Keep rdx | | |I251a| | |V0 a|V1 a| | | | | | | | | 1659.#1108 I251 Use * Keep rdx | | |I251i| | |V0 a|V1 a| | | | | | | | | 1660.#1109 rax Kill Keep rax | | | | | |V0 a|V1 a| | | | | | | | | 1660.#1110 rcx Kill Keep rcx | | | | | |V0 a|V1 a| | | | | | | | | 1660.#1111 rdx Kill Keep rdx | | | | | |V0 a|V1 a| | | | | | | | | 1660.#1112 r8 Kill Keep r8 | | | | | |V0 a|V1 a| | | | | | | | | 1660.#1113 r9 Kill Keep r9 | | | | | |V0 a|V1 a| | | | | | | | | 1660.#1114 r10 Kill Keep r10 | | | | | |V0 a|V1 a| | | | | | | | | 1660.#1115 r11 Kill Keep r11 | | | | | |V0 a|V1 a| | | | | | | | | 1660.#1116 rax Fixd Keep rax | | | | | |V0 a|V1 a| | | | | | | | | 1660.#1117 I252 Def Alloc rax |I252a| | | | |V0 a|V1 a| | | | | | | | | 1661.#1118 I252 Use * Keep rax |I252i| | | | |V0 a|V1 a| | | | | | | | | 1662.#1119 V23 Def Alloc rcx | |V23 a| | | |V0 a|V1 a| | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1663.#1120 BB67 PredBB65 | |V23 a| | | |V0 a|V1 a| | | | | | | | | 1667.#1121 rcx Fixd Keep rcx | |V23 a| | | |V0 a|V1 a| | | | | | | | | 1667.#1122 V23 Use * Keep rcx | |V23 i| | | |V0 a|V1 a| | | | | | | | | 1668.#1123 rcx Fixd Keep rcx | | | | | |V0 a|V1 a| | | | | | | | | 1668.#1124 I253 Def Alloc rcx | |I253a| | | |V0 a|V1 a| | | | | | | | | 1671.#1125 rdx Fixd Keep rdx | |I253a| | | |V0 a|V1 a| | | | | | | | | 1671.#1126 V1 Use * Copy rdx | |I253a|V1 i| | |V0 a|V1 i| | | | | | | | | 1672.#1127 rdx Fixd Keep rdx | |I253a| | | |V0 a| | | | | | | | | | 1672.#1128 I254 Def Alloc rdx | |I253a|I254a| | |V0 a| | | | | | | | | | 1673.#1129 rcx Fixd Keep rcx | |I253a|I254a| | |V0 a| | | | | | | | | | 1673.#1130 I253 Use * Keep rcx | |I253i|I254a| | |V0 a| | | | | | | | | | 1673.#1131 rdx Fixd Keep rdx | | |I254a| | |V0 a| | | | | | | | | | 1673.#1132 I254 Use * Keep rdx | | |I254i| | |V0 a| | | | | | | | | | 1674.#1133 rax Kill Keep rax | | | | | |V0 a| | | | | | | | | | 1674.#1134 rcx Kill Keep rcx | | | | | |V0 a| | | | | | | | | | 1674.#1135 rdx Kill Keep rdx | | | | | |V0 a| | | | | | | | | | 1674.#1136 r8 Kill Keep r8 | | | | | |V0 a| | | | | | | | | | 1674.#1137 r9 Kill Keep r9 | | | | | |V0 a| | | | | | | | | | 1674.#1138 r10 Kill Keep r10 | | | | | |V0 a| | | | | | | | | | 1674.#1139 r11 Kill Keep r11 | | | | | |V0 a| | | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1675.#1140 BB68 PredBB26 | | | | | |V0 a| | | | | | | | | | 1680.#1141 rax Kill Keep rax | | | | | |V0 a| | | | | | | | | | 1680.#1142 rcx Kill Keep rcx | | | | | |V0 a| | | | | | | | | | 1680.#1143 rdx Kill Keep rdx | | | | | |V0 a| | | | | | | | | | 1680.#1144 r8 Kill Keep r8 | | | | | |V0 a| | | | | | | | | | 1680.#1145 r9 Kill Keep r9 | | | | | |V0 a| | | | | | | | | | 1680.#1146 r10 Kill Keep r10 | | | | | |V0 a| | | | | | | | | | 1680.#1147 r11 Kill Keep r11 | | | | | |V0 a| | | | | | | | | | 1681.#1148 V0 DDef | | | | | |V0 a| | | | | | | | | | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rbp |rsi |rdi |r8 |r9 |r10 |r11 |r12 |r13 |r14 |r15 | --------------------------------------+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+-----+ 1681.#1149 BB69 PredBB0 | | | | | |V0 a| | | | | | | | | | 1684.#1150 rax Kill Keep rax | | | | | |V0 a| | | | | | | | | | 1684.#1151 rcx Kill Keep rcx | | | | | |V0 a| | | | | | | | | | 1684.#1152 rdx Kill Keep rdx | | | | | |V0 a| | | | | | | | | | 1684.#1153 r8 Kill Keep r8 | | | | | |V0 a| | | | | | | | | | 1684.#1154 r9 Kill Keep r9 | | | | | |V0 a| | | | | | | | | | 1684.#1155 r10 Kill Keep r10 | | | | | |V0 a| | | | | | | | | | 1684.#1156 r11 Kill Keep r11 | | | | | |V0 a| | | | | | | | | | 1685.#1157 V0 ExpU | | | | | |V0 a| | | | | | | | | | 1685.#1158 V0 ExpU | | | | | |V0 a| | | | | | | | | | Recording the maximum number of concurrent spills: ---------- LSRA Stats ---------- Register selection order: (null) Total Tracked Vars: 70 Total Reg Cand Vars: 65 Total number of Intervals: 254 Total number of RefPositions: 1158 Total Number of spill temps created: 0 .......... BB00 [ 100.00]: REG_ORDER = 4 BB04 [ 100.00]: COVERS = 3, BEST_FIT = 2, REG_ORDER = 1 BB06 [ 100.00]: COVERS = 3, BEST_FIT = 1, REG_ORDER = 1 BB07 [ 50.00]: BEST_FIT = 1 BB08 [ 100.00]: COVERS = 1, REG_ORDER = 1 BB09 [ 50.00]: COVERS = 2, COVERS_RELATED = 1, RELATED_PREFERENCE = 1, BEST_FIT = 2 BB10 [ 25.00]: OWN_PREFERENCE = 1 BB11 [ 25.00]: THIS_ASSIGNED = 1 BB12 [ 50.00]: COVERS = 1 BB13 [ 50.00]: REG_ORDER = 2 BB14 [ 100.00]: SpillCount = 6, COVERS = 3, BEST_FIT = 1, REG_ORDER = 8 BB16 [ 100.00]: SpillCount = 1, COVERS = 5, BEST_FIT = 5, REG_ORDER = 2 BB18 [ 100.00]: SpillCount = 4, BEST_FIT = 1, REG_ORDER = 6 BB19 [ 50.00]: COVERS = 2, RELATED_PREFERENCE = 1, BEST_FIT = 3 BB20 [ 25.00]: UNASSIGNED = 1 BB21 [ 25.00]: THIS_ASSIGNED = 1 BB22 [ 50.00]: REG_ORDER = 1 BB23 [ 400.00]: SpillCount = 1, REG_ORDER = 3 BB24 [ 400.00]: SpillCount = 1, COVERS = 1, BEST_FIT = 4 BB25 [ 200.00]: SpillCount = 1, ResolutionMovs = 1, FREE = 2 BB26 [ 400.00]: COVERS = 1, RELATED_PREFERENCE = 1, BEST_FIT = 1, REG_ORDER = 1 BB27 [ 400.00]: SpillCount = 3, ResolutionMovs = 2 BB32 [ 400.00]: SpillCount = 2, RELATED_PREFERENCE = 1, REG_ORDER = 1 BB33 [ 400.00]: SpillCount = 2, COVERS = 1, BEST_FIT = 2, REG_ORDER = 2 BB34 [ 200.00]: SpillCount = 1, COVERS = 2, COVERS_RELATED = 1, RELATED_PREFERENCE = 1, BEST_FIT = 2, REG_ORDER = 2 BB35 [ 100.00]: ResolutionMovs = 1, OWN_PREFERENCE = 1 BB36 [ 100.00]: ResolutionMovs = 1, THIS_ASSIGNED = 1 BB39 [ 50.00]: BEST_FIT = 1 BB42 [ 400.00]: SpillCount = 3, COVERS_RELATED = 1, RELATED_PREFERENCE = 1, BEST_FIT = 1, REG_ORDER = 1 BB43 [ 400.00]: ResolutionMovs = 1 BB45 [ 50.00]: SpillCount = 1, COVERS = 5, CALLER_CALLEE = 1, BEST_FIT = 6 BB46 [ 50.00]: BEST_FIT = 1 BB47 [ 50.00]: COVERS = 2, BEST_FIT = 5 BB48 [ 50.00]: COVERS = 1, RELATED_PREFERENCE = 2 BB49 [ 50.00]: SpillCount = 4, COVERS = 3, COVERS_RELATED = 1, BEST_FIT = 2, REG_ORDER = 5 BB51 [ 50.00]: SpillCount = 1, COVERS = 5, BEST_FIT = 5, REG_ORDER = 2 BB53 [ 50.00]: ResolutionMovs = 1, COVERS = 1, COVERS_RELATED = 1, REG_ORDER = 2 BB54 [ 50.00]: THIS_ASSIGNED = 1, COVERS_RELATED = 1, REG_ORDER = 1 BB55 [ 50.00]: SpillCount = 1, COVERS = 4, COVERS_RELATED = 1, REG_ORDER = 3 BB60 [ 0.00]: COVERS = 1, RELATED_PREFERENCE = 1, BEST_FIT = 2 BB61 [ 0.00]: OWN_PREFERENCE = 1, RELATED_PREFERENCE = 1, BEST_FIT = 2 BB62 [ 0.00]: THIS_ASSIGNED = 1 BB64 [ 0.00]: COVERS = 1, RELATED_PREFERENCE = 1, BEST_FIT = 2 BB65 [ 0.00]: OWN_PREFERENCE = 1, RELATED_PREFERENCE = 1, BEST_FIT = 2 BB66 [ 0.00]: THIS_ASSIGNED = 1 .......... Total SpillCount : 32 Weighted: 6650.000000 Total CopyReg : 0 Weighted: 0.000000 Total ResolutionMovs : 7 Weighted: 1650.000000 Total SplitEdges : 0 Weighted: 0.000000 .......... Total FREE [# 1] : 2 Weighted: 400.000000 Total THIS_ASSIGNED [# 3] : 6 Weighted: 200.000000 Total COVERS [# 4] : 48 Weighted: 4400.000000 Total OWN_PREFERENCE [# 5] : 4 Weighted: 125.000000 Total COVERS_RELATED [# 6] : 7 Weighted: 850.000000 Total RELATED_PREFERENCE [# 7] : 12 Weighted: 1600.000000 Total CALLER_CALLEE [# 8] : 1 Weighted: 50.000000 Total UNASSIGNED [# 9] : 1 Weighted: 25.000000 Total BEST_FIT [#11] : 54 Weighted: 5900.000000 Total REG_ORDER [#13] : 49 Weighted: 6700.000000 TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS Incoming Parameters: V00(rcx=>rsi) V01(rdx=>rdi) V03(r9=>rbx) V02(r8=>rbp) BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} ===== N003. IL_OFFSET IL offset: 0x0 N005. V01(rdi) N007. CNS_INT null N009. EQ ; rdi N011. JTRUE Var=Reg end of BB01: V00=rsi V01=rdi V03=rbx V02=rbp BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} ===== Predecessor for variable locations: BB01 Var=Reg beg of BB02: V00=rsi V01=rdi V03=rbx V02=rbp N015. IL_OFFSET IL offset: 0xe N017. V00(rsi) N019. STK = LEA(b+8) ; rsi N021. STK = IND ; STK N023. CNS_INT null N025. NE ; STK N027. JTRUE Var=Reg end of BB02: V00=rsi V01=rdi V03=rbx V02=rbp BB03 [016..01E), preds={BB02} succs={BB04} ===== Predecessor for variable locations: BB02 Var=Reg beg of BB03: V00=rsi V01=rdi V03=rbx V02=rbp N031. V00(rsi) N033. rcx = PUTARG_REG; rsi N035. rdx = CNS_INT 0 N037. rdx = PUTARG_REG; rdx * N039. rax = CALL ; rcx,rdx Var=Reg end of BB03: V00=rsi V01=rdi V03=rbx V02=rbp BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} ===== Predecessor for variable locations: BB02 Var=Reg beg of BB04: V00=rsi V01=rdi V03=rbx V02=rbp N043. IL_OFFSET IL offset: 0x1e N045. V00(rsi) N047. STK = LEA(b+8) ; rsi N049. STK = IND ; STK N051. CNS_INT null N053. rcx = NE ; STK * N055. V33(rcx); rcx N057. IL_OFFSET IL offset: 0x1e N059. rdx = CNS_INT(h) 0xD1FFAB1E [ICON_STR_HDL] N061. r14 = IND ; rdx * N063. V73(r14); r14 N065. IL_OFFSET IL offset: 0x1e N067. V73(r14) * N069. V35(rdx); r14 N071. IL_OFFSET IL offset: 0x1e N073. V33(rcx*) N075. CNS_INT 0 N077. NE ; rcx* N079. JTRUE Var=Reg end of BB04: V00=rsi V01=rdi V73=r14 V03=rbx V02=rbp V35=rdx BB05 [01E..01F), preds={BB04} succs={BB06} ===== Predecessor for variable locations: BB04 Var=Reg beg of BB05: V00=rsi V01=rdi V73=r14 V03=rbx V02=rbp V35=rdx N083. IL_OFFSET IL offset: 0x1e N085. V35(rdx) N087. rcx = PUTARG_REG; rdx N089. V35(rdx*) N091. rdx = PUTARG_REG; rdx* N093. CALL ; rcx,rdx Var=Reg end of BB05: V00=rsi V01=rdi V73=r14 V03=rbx V02=rbp BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} ===== Predecessor for variable locations: BB04 Var=Reg beg of BB06: V00=rsi V01=rdi V73=r14 V03=rbx V02=rbp N097. IL_OFFSET IL offset: 0x2c N099. V00(rsi) N101. STK = LEA(b+16); rsi N103. r15 = IND ; STK * N105. V04(r15); r15 N107. IL_OFFSET IL offset: 0x33 N109. V04(r15) N111. CNS_INT null N113. rcx = NE ; r15 * N115. V36(rcx); rcx N117. IL_OFFSET IL offset: 0x33 N119. V73(r14) * N121. V37(rdx); r14 N123. IL_OFFSET IL offset: 0x33 N125. V36(rcx*) N127. CNS_INT 0 N129. NE ; rcx* N131. JTRUE Var=Reg end of BB06: V04=r15 V00=rsi V01=rdi V73=r14 V03=rbx V02=rbp V37=rdx BB07 [033..034), preds={BB06} succs={BB08} ===== Predecessor for variable locations: BB06 Var=Reg beg of BB07: V04=r15 V00=rsi V01=rdi V73=r14 V03=rbx V02=rbp V37=rdx N135. IL_OFFSET IL offset: 0x33 N137. rcx = CNS_INT(h) 0xD1FFAB1E "expected entries to be non-null" N139. rcx = IND ; rcx N141. rcx = PUTARG_REG; rcx N143. V37(rdx*) N145. rdx = PUTARG_REG; rdx* N147. CALL ; rcx,rdx Var=Reg end of BB07: V04=r15 V00=rsi V01=rdi V73=r14 V03=rbx V02=rbp BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} ===== Predecessor for variable locations: BB06 Var=Reg beg of BB08: V04=r15 V00=rsi V01=rdi V73=r14 V03=rbx V02=rbp N151. IL_OFFSET IL offset: 0x41 N153. V00(rsi) N155. STK = LEA(b+24); rsi N157. r12 = IND ; STK * N159. V05(r12); r12 N161. IL_OFFSET IL offset: 0x48 N163. V05(r12) N165. CNS_INT null N167. EQ ; r12 N169. JTRUE Var=Reg end of BB08: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} ===== Predecessor for variable locations: BB08 Var=Reg beg of BB09: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp N173. IL_OFFSET IL offset: 0x4b N175. V00(rsi) N177. rcx = IND ; rsi * N179. V29(rcx); rcx N181. V29(rcx) N183. STK = LEA(b+56); rcx N185. rdx = IND ; STK N187. rdx = IND ; rdx N189. STK = LEA(b+64); rdx N191. r11 = IND ; STK * N193. V68(r11); r11 N195. V68(r11) N197. CNS_INT 0 N199. EQ ; r11 N201. JTRUE Var=Reg end of BB09: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V29=rcx V68=r11 BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} ===== Predecessor for variable locations: BB09 Var=Reg beg of BB10: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V68=r11 N205. V68(r11*) * N207. V31(r11); r11* Var=Reg end of BB10: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V31=r11 BB11 [???..???), preds={BB09} succs={BB12} ===== Predecessor for variable locations: BB09 Var=Reg beg of BB11: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V29=rcx N211. V29(rcx*) N213. rcx = PUTARG_REG; rcx* N215. rdx = CNS_INT(h) 0xd1ffab1e global ptr N217. rdx = PUTARG_REG; rdx N219. rax = CALL help; rcx,rdx * N221. V31(r11); rax Var=Reg end of BB11: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V31=r11 BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} ===== Predecessor for variable locations: BB10 Var=Reg beg of BB12: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V31=r11 N225. V05(r12) N227. rcx = PUTARG_REG; r12 N229. V31(r11) N231. r11 = PUTARG_REG; r11 N233. V01(rdi) N235. rdx = PUTARG_REG; rdi N237. V31(r11*) N239. STK = IND ; r11* N241. rax = CALL ind stub; rcx,r11,rdx,STK * N243. V15(r13); rax Var=Reg end of BB12: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V15=r13 BB13 [054..061), preds={BB08} succs={BB14} ===== Predecessor for variable locations: BB08 Var=Reg beg of BB13: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp N247. IL_OFFSET IL offset: 0x54 N249. V01(rdi) N251. rcx = PUTARG_REG; rdi N253. V01(rdi) N255. rax = IND ; rdi N257. STK = LEA(b+72); rax N259. rax = IND ; STK N261. STK = LEA(b+24); rax N263. STK = IND ; STK N265. rax = CALLV vt-ind; rcx,STK * N267. V15(r13); rax Var=Reg end of BB13: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V15=r13 BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} ===== Predecessor for variable locations: BB12 Var=Reg beg of BB14: V04=r15 V00=rsi V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V15=r13 N271. V15(r13*) * N273. V06(r13); r13* N275. IL_OFFSET IL offset: 0x62 N277. rax = CNS_INT 0 N279. V07(STK); rax N281. IL_OFFSET IL offset: 0x64 N283. V00(rsi) N285. STK = LEA(b+8) ; rsi N287. r8 = IND ; STK * N289. V39(r8); r8 N291. IL_OFFSET IL offset: 0x64 S N293. V39(r8) N295. STK = LEA(b+8) ; r8 N297. r9 = IND ; STK * N299. V40(r9); r9 N301. IL_OFFSET IL offset: 0x64 N303. V00(rsi) N305. STK = LEA(b+48); rsi N307. r10 = IND ; STK N309. V41(STK); r10 N311. IL_OFFSET IL offset: 0x64 S N313. V40(r9) N315. CNS_INT 0x7FFFFFFF N317. rcx = LE ; r9 * N319. V43(rcx); rcx N321. IL_OFFSET IL offset: 0x64 N323. IL_OFFSET IL offset: 0x64 N325. V73(r14) * N327. V45(rdx); r14 N329. IL_OFFSET IL offset: 0x64 N331. V43(rcx*) N333. CNS_INT 0 N335. NE ; rcx* N337. JTRUE Var=Reg end of BB14: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V45=rdx BB15 [064..065), preds={BB14} succs={BB16} ===== Predecessor for variable locations: BB14 Var=Reg beg of BB15: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V45=rdx N341. IL_OFFSET IL offset: 0x64 N343. V45(rdx) N345. rcx = PUTARG_REG; rdx N347. V45(rdx*) N349. rdx = PUTARG_REG; rdx* N351. CALL ; rcx,rdx Var=Reg end of BB15: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} ===== Predecessor for variable locations: BB14 Var=Reg beg of BB16: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp N355. IL_OFFSET IL offset: 0x64 N357. V41(STK*) N359. V06(r13) N361. rdx = CAST ; r13 N363. rdx = MUL ; rdx N365. CNS_INT 32 N367. rdx = RSZ ; rdx N369. CNS_INT 1 N371. rdx = ADD ; rdx N373. V40(r9)R N375. rcx = CAST ; r9 N377. rdx = MUL ; rdx,rcx N379. CNS_INT 32 N381. rdx = RSZ ; rdx N383. r10 = CAST ; rdx * N385. V42(r10); r10 N387. IL_OFFSET IL offset: 0x64 N389. V06(r13) N391. V40(r9*) N393. rdx = UMOD ; r13,r9* S N395. V42(r10) N397. rcx = EQ ; rdx,r10 * N399. V46(rcx); rcx N401. IL_OFFSET IL offset: 0x64 N403. IL_OFFSET IL offset: 0x64 N405. V73(r14) * N407. V48(rdx); r14 N409. IL_OFFSET IL offset: 0x64 N411. V46(rcx*) N413. CNS_INT 0 N415. NE ; rcx* N417. JTRUE Var=Reg end of BB16: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V48=rdx BB17 [064..065), preds={BB16} succs={BB18} ===== Predecessor for variable locations: BB16 Var=Reg beg of BB17: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V48=rdx N421. IL_OFFSET IL offset: 0x64 N423. V48(rdx) N425. rcx = PUTARG_REG; rdx N427. V48(rdx*) N429. rdx = PUTARG_REG; rdx* N431. CALL ; rcx,rdx Var=Reg end of BB17: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} ===== Predecessor for variable locations: BB16 Var=Reg beg of BB18: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp N435. IL_OFFSET IL offset: 0x64 N437. V42(r10)R N439. V39(r8)R N441. STK = LEA(b+8) ; r8 N443. STK = IND ; STK N445. ARR_BOUNDS_CHECK_Rng -> BB69; r10,STK N447. V39(r8*) N449. V42(r10*) N451. rcx = CAST ; r10* N453. rax = LEA(b+(i*4)+16); r8*,rcx * N455. V38(rax); rax N457. V38(rax*) * N459. V08(rax); rax* N461. IL_OFFSET IL offset: 0x6d S N463. V08(rax) N465. r8 = IND ; rax N467. CNS_INT -1 N469. r8 = ADD ; r8 N471. V09(STK); r8 N473. IL_OFFSET IL offset: 0x74 N475. V05(r12) N477. CNS_INT null N479. NE ; r12 N481. JTRUE Var=Reg end of BB18: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} ===== Predecessor for variable locations: BB18 Var=Reg beg of BB19: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp N485. IL_OFFSET IL offset: 0xff N487. V00(rsi) N489. rcx = IND ; rsi * N491. V24(rcx); rcx N493. V24(rcx) N495. STK = LEA(b+56); rcx N497. rdx = IND ; STK N499. rdx = IND ; rdx N501. STK = LEA(b+32); rdx N503. rdx = IND ; STK * N505. V69(rdx); rdx N507. V69(rdx) N509. CNS_INT 0 N511. EQ ; rdx N513. JTRUE Var=Reg end of BB19: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V24=rcx V69=rdx BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} ===== Predecessor for variable locations: BB19 Var=Reg beg of BB20: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V69=rdx N517. V69(rdx*) * N519. V25(rdx); rdx* Var=Reg end of BB20: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V25=rdx BB21 [???..???), preds={BB19} succs={BB22} ===== Predecessor for variable locations: BB19 Var=Reg beg of BB21: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V24=rcx N523. V24(rcx*) N525. rcx = PUTARG_REG; rcx* N527. rdx = CNS_INT(h) 0xd1ffab1e global ptr N529. rdx = PUTARG_REG; rdx N531. rax = CALL help; rcx,rdx * N533. V25(rdx); rax Var=Reg end of BB21: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V25=rdx BB22 [???..106), preds={BB20,BB21} succs={BB23} ===== Predecessor for variable locations: BB20 Var=Reg beg of BB22: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V25=rdx N537. V25(rdx*) N539. rcx = PUTARG_REG; rdx* N541. rax = CALL ; rcx * N543. V12(rax); rax Var=Reg end of BB22: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V12=rax BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} ===== Predecessor for variable locations: BB22 Var=Reg beg of BB23: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V12=rax N547. IL_OFFSET IL offset: 0x106 N549. V04(r15) N551. STK = LEA(b+8) ; r15 N553. r9 = IND ; STK * N555. V76(r9); r9 S N557. V76(r9) N559. V09(r10)R N561. LE ; r9,r10 N563. JTRUE Var=Reg end of BB23: V04=r15 V09=r10 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V12=rax BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} ===== Predecessor for variable locations: BB23 Var=Reg beg of BB24: V04=r15 V09=r10 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V12=rax N567. IL_OFFSET IL offset: 0x110 N569. V04(r15) N571. V09(r10*) N573. rdx = CAST ; r10* N575. CNS_INT 3 N577. rdx = MUL ; rdx * N579. V70(rdx); rdx N581. V70(rdx) N583. r11 = LEA(b+(i*8)+16); r15,rdx * N585. V65(r11); r11 S N587. V65(r11) N589. STK = LEA(b+16); r11 N591. STK = IND ; STK N593. V06(r13) N595. NE ; STK,r13 N597. JTRUE Var=Reg end of BB24: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V70=rdx V05=r12 V03=rbx V02=rbp V12=rax BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} ===== Predecessor for variable locations: BB24 Var=Reg beg of BB25: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V70=rdx V05=r12 V03=rbx V02=rbp V12=rax N601. IL_OFFSET IL offset: 0x120 N603. V04(r15) N605. V70(rdx*) N607. STK = LEA(b+(i*8)+16); r15,rdx* N609. rdx = IND ; STK N611. rdx = PUTARG_REG; rdx N613. V12(rax) N615. rcx = PUTARG_REG; rax N617. V01(rdi) N619. r8 = PUTARG_REG; rdi S N621. V12(rax) N623. r10 = IND ; rax N625. STK = LEA(b+72); r10 N627. r10 = IND ; STK N629. STK = LEA(b+32); r10 N631. STK = IND ; STK N633. rax = CALLV vt-ind; rdx,rcx,r8,STK N635. CNS_INT 0 N637. NE ; rax * N001. V12(rax)R N639. JTRUE Var=Reg end of BB25: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V12=rax BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} ===== Predecessor for variable locations: BB24 Var=Reg beg of BB26: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V12=rax N643. IL_OFFSET IL offset: 0x157 N645. V65(r11*)R N647. STK = LEA(b+20); r11* N649. r10 = IND ; STK * N651. V09(r8); r10 N653. IL_OFFSET IL offset: 0x166 N655. V07(r11*)R N657. CNS_INT 1 N659. r11 = ADD ; r11* * N661. V07(r11); r11 N663. IL_OFFSET IL offset: 0x16a N665. V76(STK*) N667. V07(r11) N669. LT ; r11 N671. JTRUE Var=Reg end of BB26: V07=r11 V04=r15 V09=r8 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V12=rax BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} ===== Predecessor for variable locations: BB26 Var=Reg beg of BB27: V07=r11 V04=r15 V09=r8 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V12=rax $ N001. V07(r11) $ N001. V09(r8) Var=Reg end of BB27: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V12=rax BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} ===== Predecessor for variable locations: BB24 Var=Reg beg of BB28: V00=rsi V01=rdi V03=rbx V02=rbp N677. IL_OFFSET IL offset: 0x137 N679. V03(rbx) N681. CNS_INT 1 N683. NE ; rbx N685. JTRUE Var=Reg end of BB28: V00=rsi V01=rdi V03=rbx V02=rbp BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} ===== Predecessor for variable locations: BB28 Var=Reg beg of BB29: V00=rsi V02=rbp N689. IL_OFFSET IL offset: 0x13b N691. V65(r11*)R N693. rcx = LEA(b+8) ; r11* N695. V02(rbp*) N697. STOREIND ; rcx,rbp* Var=Reg end of BB29: V00=rsi BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} ===== Predecessor for variable locations: BB28 Var=Reg beg of BB30: V00=rsi V01=rdi V03=rbx N701. IL_OFFSET IL offset: 0x14b N703. V03(rbx*) N705. CNS_INT 2 N707. EQ ; rbx* N709. JTRUE Var=Reg end of BB30: V00=rsi V01=rdi BB31 [???..???) (return), preds={BB30,BB41} succs={} ===== Predecessor for variable locations: BB30 Var=Reg beg of BB31: V00=rsi N713. rax = CNS_INT 0 N715. RETURN ; rax Var=Reg end of BB31: V00=rsi BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} ===== Predecessor for variable locations: BB18 Var=Reg beg of BB32: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp N719. IL_OFFSET IL offset: 0x177 N721. V04(r15) N723. STK = LEA(b+8) ; r15 N725. r9 = IND ; STK * N727. V76(r9); r9 S N729. V76(r9) N731. V09(r8)R N733. LE ; r9,r8 N735. JTRUE Var=Reg end of BB32: V04=r15 V09=r8 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} ===== Predecessor for variable locations: BB32 Var=Reg beg of BB33: V04=r15 V09=r8 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp N739. IL_OFFSET IL offset: 0x17e N741. V04(r15) N743. V09(r8*) N745. rcx = CAST ; r8* N747. CNS_INT 3 N749. rcx = MUL ; rcx * N751. V71(rcx); rcx N753. V71(rcx) N755. r8 = LEA(b+(i*8)+16); r15,rcx * N757. V66(r8); r8 S N759. V66(r8) N761. STK = LEA(b+16); r8 N763. STK = IND ; STK N765. V06(r13) N767. NE ; STK,r13 N769. JTRUE Var=Reg end of BB33: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V71=rcx V05=r12 V03=rbx V02=rbp BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} ===== Predecessor for variable locations: BB33 Var=Reg beg of BB34: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V71=rcx V05=r12 V03=rbx V02=rbp N773. IL_OFFSET IL offset: 0x18e N775. V04(r15) N777. V71(rcx*) N779. STK = LEA(b+(i*8)+16); r15,rcx* N781. r10 = IND ; STK N783. V17(STK); r10 N785. IL_OFFSET IL offset: 0x18e N787. V00(rsi) N789. rcx = IND ; rsi * N791. V16(rcx); rcx N793. V16(rcx) N795. STK = LEA(b+56); rcx N797. rdx = IND ; STK N799. rdx = IND ; rdx N801. STK = LEA(b+48); rdx N803. r11 = IND ; STK * N805. V67(r11); r11 N807. V67(r11) N809. CNS_INT 0 N811. EQ ; r11 N813. JTRUE Var=Reg end of BB34: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V16=rcx V05=r12 V03=rbx V02=rbp V67=r11 BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} ===== Predecessor for variable locations: BB34 Var=Reg beg of BB35: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp V67=r11 * N001. V17(r10)R N817. V67(r11*) * N819. V19(r11); r11* Var=Reg end of BB35: V04=r15 V00=rsi V06=r13 V19=r11 V01=rdi V73=r14 V17=r10 V05=r12 V03=rbx V02=rbp BB36 [???..???), preds={BB34} succs={BB37} ===== Predecessor for variable locations: BB34 Var=Reg beg of BB36: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V16=rcx V05=r12 V03=rbx V02=rbp N823. V16(rcx*) N825. rcx = PUTARG_REG; rcx* N827. rdx = CNS_INT(h) 0xd1ffab1e global ptr N829. rdx = PUTARG_REG; rdx N831. rax = CALL help; rcx,rdx * N833. V19(r11); rax * N001. V17(r10)R Var=Reg end of BB36: V04=r15 V00=rsi V06=r13 V19=r11 V01=rdi V73=r14 V17=r10 V05=r12 V03=rbx V02=rbp BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} ===== Predecessor for variable locations: BB35 Var=Reg beg of BB37: V04=r15 V00=rsi V06=r13 V19=r11 V01=rdi V73=r14 V17=r10 V05=r12 V03=rbx V02=rbp N837. V05(r12) N839. rcx = PUTARG_REG; r12 N841. V19(r11) N843. r11 = PUTARG_REG; r11 N845. V17(r10*) N847. rdx = PUTARG_REG; r10* N849. V01(rdi) N851. r8 = PUTARG_REG; rdi N853. V19(r11*) N855. STK = IND ; r11* N857. rax = CALL ind stub; rcx,r11,rdx,r8,STK N859. CNS_INT 0 N861. EQ ; rax N863. JTRUE Var=Reg end of BB37: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} ===== Predecessor for variable locations: BB37 Var=Reg beg of BB38: V00=rsi V01=rdi V03=rbx V02=rbp N867. IL_OFFSET IL offset: 0x1a4 N869. V03(rbx) N871. CNS_INT 1 N873. NE ; rbx N875. JTRUE Var=Reg end of BB38: V00=rsi V01=rdi V03=rbx V02=rbp BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} ===== Predecessor for variable locations: BB38 Var=Reg beg of BB39: V00=rsi V02=rbp N879. IL_OFFSET IL offset: 0x1a8 N881. V66(r15*)R N883. rcx = LEA(b+8) ; r15* N885. V02(rbp*) N887. STOREIND ; rcx,rbp* Var=Reg end of BB39: V00=rsi BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} ===== Predecessor for variable locations: BB38 Var=Reg beg of BB40: V00=rsi V01=rdi V03=rbx N891. IL_OFFSET IL offset: 0x1b8 N893. V03(rbx*) N895. CNS_INT 2 N897. EQ ; rbx* N899. JTRUE Var=Reg end of BB40: V00=rsi V01=rdi BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} ===== Predecessor for variable locations: BB40 Var=Reg beg of BB41: V00=rsi Var=Reg end of BB41: V00=rsi BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} ===== Predecessor for variable locations: BB33 Var=Reg beg of BB42: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp N905. IL_OFFSET IL offset: 0x1c4 N907. V66(r8*)R N909. STK = LEA(b+20); r8* N911. r8 = IND ; STK * N913. V09(rcx); r8 N915. IL_OFFSET IL offset: 0x1d3 N917. V07(r8*)R N919. CNS_INT 1 N921. r8 = ADD ; r8* * N923. V07(r8); r8 N925. IL_OFFSET IL offset: 0x1d7 N927. V76(STK*) S N929. V07(r8) N931. LT ; r8 N933. JTRUE Var=Reg end of BB42: V04=r15 V09=rcx V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} ===== Predecessor for variable locations: BB42 Var=Reg beg of BB43: V04=r15 V09=rcx V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp $ N001. V09(rcx) Var=Reg end of BB43: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V03=rbx V02=rbp BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} ===== Predecessor for variable locations: BB23 Var=Reg beg of BB44: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V02=rbp N939. IL_OFFSET IL offset: 0x1e4 N941. V00(rsi) N943. STK = LEA(b+64); rsi N945. STK = IND ; STK N947. CNS_INT 0 N949. LE ; STK N951. JTRUE Var=Reg end of BB44: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V02=rbp BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} ===== Predecessor for variable locations: BB44 Var=Reg beg of BB45: V04=r15 V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V02=rbp N955. IL_OFFSET IL offset: 0x1ed N957. V00(rsi) N959. STK = LEA(b+60); rsi N961. rcx = IND ; STK * N963. V74(rcx); rcx N965. V74(rcx) * N967. V10(rbx); rcx N969. IL_OFFSET IL offset: 0x1f5 N971. V74(rcx*) * N973. V62(rcx); rcx* N975. V62(rcx) N977. V76(STK) N979. ARR_BOUNDS_CHECK_Rng -> BB69; rcx N981. V04(r15) N983. V62(rcx*) N985. rcx = CAST ; rcx* N987. CNS_INT 3 N989. rcx = MUL ; rcx N991. STK = LEA(b+(i*8)+36); r15,rcx N993. rcx = IND ; STK N995. rcx = NEG ; rcx N997. CNS_INT -3 N999. rcx = ADD ; rcx N1001. CNS_INT -1 N1003. rcx = GE ; rcx * N1005. V49(rcx); rcx N1007. IL_OFFSET IL offset: 0x1f5 N1009. V73(r14*) * N1011. V50(rdx); r14* N1013. IL_OFFSET IL offset: 0x1f5 N1015. V49(rcx*) N1017. CNS_INT 0 N1019. NE ; rcx* N1021. JTRUE Var=Reg end of BB45: V04=r15 V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V10=rbx V50=rdx BB46 [1F5..1F6), preds={BB45} succs={BB47} ===== Predecessor for variable locations: BB45 Var=Reg beg of BB46: V04=r15 V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V10=rbx V50=rdx N1025. IL_OFFSET IL offset: 0x1f5 N1027. rcx = CNS_INT(h) 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" N1029. rcx = IND ; rcx N1031. rcx = PUTARG_REG; rcx N1033. V50(rdx*) N1035. rdx = PUTARG_REG; rdx* N1037. CALL ; rcx,rdx Var=Reg end of BB46: V04=r15 V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V10=rbx BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} ===== Predecessor for variable locations: BB45 Var=Reg beg of BB47: V04=r15 V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V10=rbx N1041. IL_OFFSET IL offset: 0x219 N1043. V00(rsi) N1045. STK = LEA(b+60); rsi N1047. V00(rsi) N1049. STK = LEA(b+60); rsi N1051. rcx = IND ; STK * N1053. V63(rcx); rcx N1055. V63(rcx) N1057. V76(STK*) N1059. ARR_BOUNDS_CHECK_Rng -> BB69; rcx N1061. V04(r15) N1063. V63(rcx*) N1065. r9 = CAST ; rcx* N1067. CNS_INT 3 N1069. rcx = MUL ; r9 N1071. STK = LEA(b+(i*8)+36); r15,rcx N1073. rcx = IND ; STK N1075. rcx = NEG ; rcx N1077. CNS_INT -3 N1079. rcx = ADD ; rcx N1081. STOREIND ; STK,rcx N1083. IL_OFFSET IL offset: 0x233 N1085. V00(STK) N1087. LEA(b+64) N1089. IND N1091. CNS_INT -1 N1093. ADD N1095. V00(rsi) N1097. STK = LEA(b+64); rsi N1099. STOREIND ; STK Var=Reg end of BB47: V04=r15 V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V10=rbx BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} ===== Predecessor for variable locations: BB44 Var=Reg beg of BB48: V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V02=rbp N1103. IL_OFFSET IL offset: 0x243 N1105. V00(rsi) N1107. STK = LEA(b+56); rsi N1109. rcx = IND ; STK * N1111. V75(rcx); rcx N1113. V75(rcx) * N1115. V13(rbx); rcx N1117. IL_OFFSET IL offset: 0x24b N1119. V76(STK*) N1121. V13(rbx) N1123. NE ; rbx N1125. JTRUE Var=Reg end of BB48: V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V02=rbp V13=rbx V75=rcx BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} ===== Predecessor for variable locations: BB48 Var=Reg beg of BB49: V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V02=rbp V13=rbx V75=rcx N1129. IL_OFFSET IL offset: 0x252 N1131. V75(rcx*) N1133. rcx = PUTARG_REG; rcx* N1135. rax = CALL ; rcx * N1137. V64(rdx); rax N1139. V64(rdx*) N1141. rdx = PUTARG_REG; rdx* N1143. V00(rsi) N1145. rcx = PUTARG_REG; rsi N1147. r8 = CNS_INT 0 N1149. r8 = PUTARG_REG; r8 N1151. CALL ; rdx,rcx,r8 N1153. IL_OFFSET IL offset: 0x258 N1155. V00(rsi) N1157. STK = LEA(b+8) ; rsi N1159. r15 = IND ; STK * N1161. V52(r15); r15 N1163. IL_OFFSET IL offset: 0x258 N1165. V52(r15) N1167. STK = LEA(b+8) ; r15 N1169. rax = IND ; STK * N1171. V72(rax); rax S N1173. V72(rax) * N1175. V53(r8); rax N1177. IL_OFFSET IL offset: 0x258 N1179. V00(rsi) N1181. STK = LEA(b+48); rsi N1183. r9 = IND ; STK N1185. V54(STK); r9 N1187. IL_OFFSET IL offset: 0x258 S N1189. V53(r8) N1191. CNS_INT 0x7FFFFFFF N1193. rcx = LE ; r8 * N1195. V56(rcx); rcx N1197. IL_OFFSET IL offset: 0x258 N1199. IL_OFFSET IL offset: 0x258 N1201. V73(r14) * N1203. V58(rdx); r14 N1205. IL_OFFSET IL offset: 0x258 N1207. V56(rcx*) N1209. CNS_INT 0 N1211. NE ; rcx* N1213. JTRUE Var=Reg end of BB49: V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V02=rbp V58=rdx V52=r15 V13=rbx BB50 [258..259), preds={BB49} succs={BB51} ===== Predecessor for variable locations: BB49 Var=Reg beg of BB50: V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V02=rbp V58=rdx V52=r15 V13=rbx N1217. IL_OFFSET IL offset: 0x258 N1219. V58(rdx) N1221. rcx = PUTARG_REG; rdx N1223. V58(rdx*) N1225. rdx = PUTARG_REG; rdx* N1227. CALL ; rcx,rdx Var=Reg end of BB50: V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V02=rbp V52=r15 V13=rbx BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} ===== Predecessor for variable locations: BB49 Var=Reg beg of BB51: V00=rsi V06=r13 V01=rdi V73=r14 V05=r12 V02=rbp V52=r15 V13=rbx N1231. IL_OFFSET IL offset: 0x258 N1233. V54(STK*) N1235. V06(r13) N1237. rdx = CAST ; r13 N1239. rdx = MUL ; rdx N1241. CNS_INT 32 N1243. rdx = RSZ ; rdx N1245. CNS_INT 1 N1247. rdx = ADD ; rdx N1249. V53(r8)R N1251. rcx = CAST ; r8 N1253. rdx = MUL ; rdx,rcx N1255. CNS_INT 32 N1257. rdx = RSZ ; rdx N1259. r9 = CAST ; rdx * N1261. V55(r9); r9 N1263. IL_OFFSET IL offset: 0x258 N1265. V06(r13) N1267. V53(r8*) N1269. rdx = UMOD ; r13,r8* S N1271. V55(r9) N1273. rcx = EQ ; rdx,r9 * N1275. V59(rcx); rcx N1277. IL_OFFSET IL offset: 0x258 N1279. IL_OFFSET IL offset: 0x258 N1281. V73(r14*) * N1283. V61(rdx); r14* N1285. IL_OFFSET IL offset: 0x258 N1287. V59(rcx*) N1289. CNS_INT 0 N1291. NE ; rcx* N1293. JTRUE Var=Reg end of BB51: V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V61=rdx V52=r15 V13=rbx BB52 [258..259), preds={BB51} succs={BB53} ===== Predecessor for variable locations: BB51 Var=Reg beg of BB52: V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V61=rdx V52=r15 V13=rbx N1297. IL_OFFSET IL offset: 0x258 N1299. V61(rdx) N1301. rcx = PUTARG_REG; rdx N1303. V61(rdx*) N1305. rdx = PUTARG_REG; rdx* N1307. CALL ; rcx,rdx Var=Reg end of BB52: V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V52=r15 V13=rbx BB53 [258..259), preds={BB51,BB52} succs={BB54} ===== Predecessor for variable locations: BB51 Var=Reg beg of BB53: V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V52=r15 V13=rbx N1311. IL_OFFSET IL offset: 0x258 N1313. V55(r9)R N1315. V72(STK*) N1317. ARR_BOUNDS_CHECK_Rng -> BB69; r9 N1319. V52(r15*) N1321. V55(r9*) N1323. rdx = CAST ; r9* N1325. rax = LEA(b+(i*4)+16); r15*,rdx * N1327. V51(rax); rax N1329. V51(rax*) * N1331. V08(r14); rax* $ N001. V08(r14) Var=Reg end of BB53: V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V13=rbx BB54 [261..276), preds={BB48,BB53} succs={BB55} ===== Predecessor for variable locations: BB48 Var=Reg beg of BB54: V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V13=rbx N1335. IL_OFFSET IL offset: 0x261 N1337. V13(rbx*) * N1339. V10(rbx); rbx* N1341. IL_OFFSET IL offset: 0x265 N1343. V10(rbx) N1345. CNS_INT 1 N1347. rdx = ADD ; rbx N1349. V00(rsi) N1351. STK = LEA(b+56); rsi N1353. STOREIND ; STK,rdx N1355. IL_OFFSET IL offset: 0x26f N1357. V00(rsi) N1359. STK = LEA(b+16); rsi N1361. r15 = IND ; STK * N1363. V04(r15); r15 Var=Reg end of BB54: V04=r15 V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V10=rbx BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} ===== Predecessor for variable locations: BB47 Var=Reg beg of BB55: V04=r15 V00=rsi V06=r13 V01=rdi V05=r12 V02=rbp V10=rbx N1367. IL_OFFSET IL offset: 0x276 N1369. V10(rbx) N1371. V04(r15) N1373. STK = LEA(b+8) ; r15 N1375. STK = IND ; STK N1377. ARR_BOUNDS_CHECK_Rng -> BB69; rbx,STK N1379. V04(r15) N1381. V10(rbx) N1383. rdx = CAST ; rbx N1385. CNS_INT 3 N1387. rdx = MUL ; rdx N1389. r14 = LEA(b+(i*8)+16); r15,rdx * N1391. V11(r14); r14 N1393. IL_OFFSET IL offset: 0x280 N1395. V11(r14) N1397. STK = LEA(b+16); r14 N1399. V06(r13*) N1401. STOREIND ; STK,r13* N1403. IL_OFFSET IL offset: 0x288 S N1405. V08(rax)R N1407. rdx = IND ; rax N1409. CNS_INT -1 N1411. rdx = ADD ; rdx N1413. V11(r14) N1415. STK = LEA(b+20); r14 N1417. STOREIND ; STK,rdx N1419. IL_OFFSET IL offset: 0x294 N1421. V11(r14) N1423. V01(rdi*) N1425. STOREIND ; r14,rdi* N1427. IL_OFFSET IL offset: 0x29c N1429. V11(r14*) N1431. rcx = LEA(b+8) ; r14* N1433. V02(rbp*) N1435. STOREIND ; rcx,rbp* N1437. IL_OFFSET IL offset: 0x2a4 N1439. V10(rbx*) N1441. CNS_INT 1 N1443. rbx = ADD ; rbx* N1445. V08(r14*)R N1447. STOREIND ; r14*,rbx N1449. IL_OFFSET IL offset: 0x2ab N1451. V00(STK) N1453. LEA(b+68) N1455. IND N1457. CNS_INT 1 N1459. ADD N1461. V00(rsi) N1463. STK = LEA(b+68); rsi N1465. STOREIND ; STK N1467. IL_OFFSET IL offset: 0x2ca N1469. V07(STK*) N1471. CNS_INT 100 N1473. LE N1475. JTRUE Var=Reg end of BB55: V04=r15 V00=rsi V05=r12 BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} ===== Predecessor for variable locations: BB55 Var=Reg beg of BB56: V04=r15 V00=rsi V05=r12 N1479. IL_OFFSET IL offset: 0x2cf N1481. V05(r12*) N1483. rdx = PUTARG_REG; r12* N1485. rcx = CNS_INT(h) 0xd1ffab1e class N1487. rcx = PUTARG_REG; rcx N1489. rax = CALL help; rdx,rcx N1491. CNS_INT null N1493. EQ ; rax N1495. JTRUE Var=Reg end of BB56: V04=r15 V00=rsi BB57 [2D7..2E3), preds={BB56} succs={BB58} ===== Predecessor for variable locations: BB56 Var=Reg beg of BB57: V04=r15 V00=rsi N1499. IL_OFFSET IL offset: 0x2d7 N1501. V04(r15*) N1503. STK = LEA(b+8) ; r15* N1505. rdx = IND ; STK N1507. rdx = PUTARG_REG; rdx N1509. V00(rsi) N1511. rcx = PUTARG_REG; rsi N1513. r8 = CNS_INT 1 N1515. r8 = PUTARG_REG; r8 N1517. CALL ; rdx,rcx,r8 Var=Reg end of BB57: V00=rsi BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} ===== Predecessor for variable locations: BB29 Var=Reg beg of BB58: V00=rsi N1521. rax = CNS_INT 1 N1523. RETURN ; rax Var=Reg end of BB58: V00=rsi BB59 [008..00E) (throw), preds={BB01} succs={} ===== Predecessor for variable locations: BB01 Var=Reg beg of BB59: V00=rsi N1527. IL_OFFSET IL offset: 0x8 N1529. rcx = CNS_INT 4 N1531. rcx = PUTARG_REG; rcx N1533. CALL ; rcx Var=Reg end of BB59: V00=rsi BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} ===== Predecessor for variable locations: BB30 Var=Reg beg of BB60: V00=rsi V01=rdi N1537. IL_OFFSET IL offset: 0x14f N1539. V00(rsi) N1541. rcx = IND ; rsi * N1543. V26(rcx); rcx N1545. V26(rcx) N1547. STK = LEA(b+56); rcx N1549. rdx = IND ; STK N1551. rdx = IND ; rdx N1553. STK = LEA(b+56); rdx N1555. STK = IND ; STK N1557. CNS_INT 0 N1559. EQ ; STK N1561. JTRUE Var=Reg end of BB60: V00=rsi V01=rdi V26=rcx BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} ===== Predecessor for variable locations: BB60 Var=Reg beg of BB61: V00=rsi V01=rdi V26=rcx N1565. V26(rcx*) N1567. STK = LEA(b+56); rcx* N1569. rcx = IND ; STK N1571. rcx = IND ; rcx N1573. STK = LEA(b+56); rcx N1575. rcx = IND ; STK * N1577. V28(rcx); rcx Var=Reg end of BB61: V00=rsi V01=rdi V28=rcx BB62 [???..???), preds={BB60} succs={BB63} ===== Predecessor for variable locations: BB60 Var=Reg beg of BB62: V00=rsi V01=rdi V26=rcx N1581. V26(rcx*) N1583. rcx = PUTARG_REG; rcx* N1585. rdx = CNS_INT(h) 0xd1ffab1e global ptr N1587. rdx = PUTARG_REG; rdx N1589. rax = CALL help; rcx,rdx * N1591. V28(rcx); rax Var=Reg end of BB62: V00=rsi V01=rdi V28=rcx BB63 [???..157) (throw), preds={BB61,BB62} succs={} ===== Predecessor for variable locations: BB61 Var=Reg beg of BB63: V00=rsi V01=rdi V28=rcx N1595. V28(rcx*) N1597. rcx = PUTARG_REG; rcx* N1599. V01(rdi*) N1601. rdx = PUTARG_REG; rdi* N1603. CALL ; rcx,rdx Var=Reg end of BB63: V00=rsi BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} ===== Predecessor for variable locations: BB40 Var=Reg beg of BB64: V00=rsi V01=rdi N1607. IL_OFFSET IL offset: 0x1bc N1609. V00(rsi) N1611. rcx = IND ; rsi * N1613. V21(rcx); rcx N1615. V21(rcx) N1617. STK = LEA(b+56); rcx N1619. rdx = IND ; STK N1621. rdx = IND ; rdx N1623. STK = LEA(b+56); rdx N1625. STK = IND ; STK N1627. CNS_INT 0 N1629. EQ ; STK N1631. JTRUE Var=Reg end of BB64: V00=rsi V01=rdi V21=rcx BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} ===== Predecessor for variable locations: BB64 Var=Reg beg of BB65: V00=rsi V01=rdi V21=rcx N1635. V21(rcx*) N1637. STK = LEA(b+56); rcx* N1639. rcx = IND ; STK N1641. rcx = IND ; rcx N1643. STK = LEA(b+56); rcx N1645. rcx = IND ; STK * N1647. V23(rcx); rcx Var=Reg end of BB65: V00=rsi V01=rdi V23=rcx BB66 [???..???), preds={BB64} succs={BB67} ===== Predecessor for variable locations: BB64 Var=Reg beg of BB66: V00=rsi V01=rdi V21=rcx N1651. V21(rcx*) N1653. rcx = PUTARG_REG; rcx* N1655. rdx = CNS_INT(h) 0xd1ffab1e global ptr N1657. rdx = PUTARG_REG; rdx N1659. rax = CALL help; rcx,rdx * N1661. V23(rcx); rax Var=Reg end of BB66: V00=rsi V01=rdi V23=rcx BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} ===== Predecessor for variable locations: BB65 Var=Reg beg of BB67: V00=rsi V01=rdi V23=rcx N1665. V23(rcx*) N1667. rcx = PUTARG_REG; rcx* N1669. V01(rdi*) N1671. rdx = PUTARG_REG; rdi* N1673. CALL ; rcx,rdx Var=Reg end of BB67: V00=rsi BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} ===== Predecessor for variable locations: BB26 Var=Reg beg of BB68: V00=rsi N1677. IL_OFFSET IL offset: 0x1dd N1679. CALL Var=Reg end of BB68: V00=rsi BB69 [???..???) (throw), preds={} succs={} ===== Predecessor for variable locations: BB00 Var=Reg beg of BB69: V00=rsi N1683. CALL help Var=Reg end of BB69: V00=rsi *************** Finishing PHASE Linear scan register alloc *************** In genGenerateCode() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i LIR BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i LIR BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe LIR BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i LIR BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe LIR BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i LIR BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe LIR BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i LIR BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe LIR BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe LIR BB11 [0096] 1 BB09 0.25 [???..???) i gcsafe LIR BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i hascall gcsafe LIR BB13 [0006] 1 BB08 0.50 [054..061) i hascall gcsafe LIR BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i gcsafe idxlen LIR BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe LIR BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i gcsafe idxlen LIR BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe LIR BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i gcsafe idxlen LIR BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe LIR BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe LIR BB21 [0100] 1 BB19 0.25 [???..???) i gcsafe LIR BB22 [0098] 2 BB20,BB21 0.50 [???..106) i hascall gcsafe LIR BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target LIR BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd LIR BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd LIR BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i idxlen bwd LIR BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal LIR BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i gcsafe bwd LIR BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen LIR BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i gcsafe bwd LIR BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal Loop1 gcsafe LIR BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop Loop0 idxlen bwd bwd-target LIR BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd LIR BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd LIR BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe LIR BB36 [0108] 1 BB34 1 [???..???) i gcsafe LIR BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i hascall gcsafe idxlen bwd LIR BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd LIR BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen LIR BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i gcsafe bwd LIR BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe LIR BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i idxlen bwd LIR BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal LIR BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i LIR BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen LIR BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe LIR BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i idxlen LIR BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i idxlen LIR BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen LIR BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe LIR BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i gcsafe idxlen LIR BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe LIR BB53 [0089] 2 BB51,BB52 0.50 [258..259) i gcsafe idxlen LIR BB54 [0044] 2 BB48,BB53 0.50 [261..276) i LIR BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i idxlen LIR BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall LIR BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen LIR BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal LIR BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare hascall gcsafe LIR BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare hascall gcsafe bwd LIR BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe LIR BB62 [0104] 1 BB60 0 [???..???) i rare gcsafe LIR BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare hascall gcsafe bwd LIR BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare hascall gcsafe bwd LIR BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe LIR BB66 [0112] 1 BB64 0 [???..???) i rare gcsafe LIR BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare hascall gcsafe bwd LIR BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare hascall gcsafe bwd LIR BB69 [0117] 0 0 [???..???) (throw ) keep i internal rare LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Generate code *************** In fgDebugCheckBBlist Finalizing stack frame Recording Var Locations at start of BB01 V00(rsi) V01(rdi) V03(rbx) V02(rbp) Modified regs: [rax rcx rdx rbx rbp rsi rdi r8-r15 mm0-mm5] Callee-saved registers pushed: 8 [rbx rbp rsi rdi r12-r15] *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT) Reporting this as generic context: referenced Assign V07 loc3, size=4, stkOffs=-0x54 Assign V09 loc5, size=4, stkOffs=-0x58 Assign V40 tmp26, size=4, stkOffs=-0x5c Pad V41 tmp27, size=8, stkOffs=-0x60, pad=4 Assign V41 tmp27, size=8, stkOffs=-0x68 Assign V42 tmp28, size=4, stkOffs=-0x6c Assign V53 tmp39, size=4, stkOffs=-0x70 Assign V54 tmp40, size=8, stkOffs=-0x78 Assign V55 tmp41, size=4, stkOffs=-0x7c Assign V72 cse7, size=4, stkOffs=-0x80 Assign V76 cse11, size=4, stkOffs=-0x84 Pad V08 loc4, size=8, stkOffs=-0x88, pad=4 Assign V08 loc4, size=8, stkOffs=-0x90 Assign V12 loc8, size=8, stkOffs=-0x98 Assign V17 tmp3, size=8, stkOffs=-0xa0 Assign V39 tmp25, size=8, stkOffs=-0xa8 Assign V65 cse0, size=8, stkOffs=-0xb0 Assign V66 cse1, size=8, stkOffs=-0xb8 Assign V14 OutArgs, size=32, stkOffs=-0xd8 --- delta bump 8 for RA --- delta bump 216 for RSP frame --- virtual stack offset to actual stack offset delta is 224 -- V00 was 0, now 224 -- V01 was 8, now 232 -- V02 was 16, now 240 -- V03 was 24, now 248 -- V07 was -84, now 140 -- V08 was -144, now 80 -- V09 was -88, now 136 -- V12 was -152, now 72 -- V14 was -216, now 8 -- V17 was -160, now 64 -- V39 was -168, now 56 -- V40 was -92, now 132 -- V41 was -104, now 120 -- V42 was -108, now 116 -- V53 was -112, now 112 -- V54 was -120, now 104 -- V55 was -124, now 100 -- V65 was -176, now 48 -- V66 was -184, now 40 -- V72 was -128, now 96 -- V76 was -132, now 92 ; Final local variable assignments ; ; V00 this [V00,T04] ( 29, 19 ) ref -> rsi this class-hnd ; V01 arg1 [V01,T09] ( 11, 9 ) ref -> rdi ld-addr-op class-hnd ; V02 arg2 [V02,T18] ( 5, 3.50) ref -> rbp class-hnd ; V03 arg3 [V03,T17] ( 6, 4 ) ubyte -> rbx ; V04 loc0 [V04,T02] ( 14, 25 ) ref -> r15 class-hnd ; V05 loc1 [V05,T16] ( 6, 6 ) ref -> r12 class-hnd ; V06 loc2 [V06,T05] ( 8, 12.50) int -> r13 ; V07 loc3 [V07,T01] ( 8, 25.50) int -> [rsp+8CH] ; V08 loc4 [V08,T32] ( 5, 3.50) byref -> [rsp+50H] ; V09 loc5 [V09,T03] ( 7, 25 ) int -> [rsp+88H] ; V10 loc6 [V10,T33] ( 6, 3 ) int -> rbx ; V11 loc7 [V11,T40] ( 5, 2.50) byref -> r14 ; V12 loc8 [V12,T20] ( 3, 4.50) ref -> [rsp+48H] class-hnd ; V13 loc9 [V13,T57] ( 3, 1.50) int -> rbx ; V14 OutArgs [V14 ] ( 1, 1 ) lclBlk (32) [rsp+00H] "OutgoingArgSpace" ; V15 tmp1 [V15,T44] ( 3, 2 ) int -> r13 ; V16 tmp2 [V16,T11] ( 3, 10 ) long -> rcx "impRuntimeLookup slot" ; V17 tmp3 [V17,T15] ( 2, 8 ) ref -> [rsp+40H] class-hnd "impAppendStmt" ;* V18 tmp4 [V18 ] ( 0, 0 ) ref -> zero-ref class-hnd "bubbling QMark1" ; V19 tmp5 [V19,T08] ( 4, 12 ) long -> r11 "spilling Runtime Lookup tree" ;* V20 tmp6 [V20 ] ( 0, 0 ) long -> zero-ref "VirtualCall with runtime lookup" ; V21 tmp7 [V21,T66] ( 4, 0 ) long -> rcx "impRuntimeLookup slot" ;* V22 tmp8 [V22 ] ( 0, 0 ) ref -> zero-ref class-hnd "bubbling QMark1" ; V23 tmp9 [V23,T68] ( 3, 0 ) long -> rcx "spilling Runtime Lookup tree" ; V24 tmp10 [V24,T41] ( 3, 2.50) long -> rcx "impRuntimeLookup slot" ; V25 tmp11 [V25,T45] ( 3, 2 ) long -> rdx "spilling Runtime Lookup tree" ; V26 tmp12 [V26,T67] ( 4, 0 ) long -> rcx "impRuntimeLookup slot" ;* V27 tmp13 [V27 ] ( 0, 0 ) ref -> zero-ref class-hnd "bubbling QMark1" ; V28 tmp14 [V28,T69] ( 3, 0 ) long -> rcx "spilling Runtime Lookup tree" ; V29 tmp15 [V29,T42] ( 3, 2.50) long -> rcx "impRuntimeLookup slot" ;* V30 tmp16 [V30 ] ( 0, 0 ) ref -> zero-ref class-hnd "bubbling QMark1" ; V31 tmp17 [V31,T34] ( 4, 3 ) long -> r11 "spilling Runtime Lookup tree" ;* V32 tmp18 [V32 ] ( 0, 0 ) long -> zero-ref "VirtualCall with runtime lookup" ; V33 tmp19 [V33,T27] ( 2, 4 ) bool -> rcx "Inlining Arg" ;* V34 tmp20 [V34,T53] ( 0, 0 ) ref -> zero-ref class-hnd "Inlining Arg" ; V35 tmp21 [V35,T24] ( 3, 4 ) ref -> rdx class-hnd "Inlining Arg" ; V36 tmp22 [V36,T28] ( 2, 4 ) bool -> rcx "Inlining Arg" ; V37 tmp23 [V37,T39] ( 2, 3 ) ref -> rdx class-hnd "Inlining Arg" ; V38 tmp24 [V38,T46] ( 2, 2 ) byref -> rax "Inline return value spill temp" ; V39 tmp25 [V39,T21] ( 4, 4 ) ref -> [rsp+38H] class-hnd "Inline stloc first use temp" ; V40 tmp26 [V40,T14] ( 4, 8 ) int -> [rsp+84H] "Inlining Arg" ; V41 tmp27 [V41,T29] ( 2, 4 ) long -> [rsp+78H] "Inlining Arg" ; V42 tmp28 [V42,T22] ( 4, 4 ) int -> [rsp+74H] "Inline stloc first use temp" ; V43 tmp29 [V43,T30] ( 2, 4 ) bool -> rcx "Inlining Arg" ;* V44 tmp30 [V44,T54] ( 0, 0 ) ref -> zero-ref class-hnd "Inlining Arg" ; V45 tmp31 [V45,T25] ( 3, 4 ) ref -> rdx class-hnd "Inlining Arg" ; V46 tmp32 [V46,T31] ( 2, 4 ) bool -> rcx "Inlining Arg" ;* V47 tmp33 [V47,T55] ( 0, 0 ) ref -> zero-ref class-hnd "Inlining Arg" ; V48 tmp34 [V48,T26] ( 3, 4 ) ref -> rdx class-hnd "Inlining Arg" ; V49 tmp35 [V49,T48] ( 2, 2 ) bool -> rcx "Inlining Arg" ; V50 tmp36 [V50,T47] ( 2, 2 ) ref -> rdx class-hnd "Inlining Arg" ; V51 tmp37 [V51,T63] ( 2, 1 ) byref -> rax "Inline return value spill temp" ; V52 tmp38 [V52,T56] ( 3, 1.50) ref -> r15 class-hnd "Inline stloc first use temp" ; V53 tmp39 [V53,T23] ( 4, 4 ) int -> [rsp+70H] "Inlining Arg" ; V54 tmp40 [V54,T49] ( 2, 2 ) long -> [rsp+68H] "Inlining Arg" ; V55 tmp41 [V55,T43] ( 4, 2 ) int -> [rsp+64H] "Inline stloc first use temp" ; V56 tmp42 [V56,T50] ( 2, 2 ) bool -> rcx "Inlining Arg" ;* V57 tmp43 [V57,T64] ( 0, 0 ) ref -> zero-ref class-hnd "Inlining Arg" ; V58 tmp44 [V58,T35] ( 3, 3 ) ref -> rdx class-hnd "Inlining Arg" ; V59 tmp45 [V59,T51] ( 2, 2 ) bool -> rcx "Inlining Arg" ;* V60 tmp46 [V60,T65] ( 0, 0 ) ref -> zero-ref class-hnd "Inlining Arg" ; V61 tmp47 [V61,T36] ( 3, 3 ) ref -> rdx class-hnd "Inlining Arg" ; V62 tmp48 [V62,T37] ( 3, 3 ) int -> rcx "index expr" ; V63 tmp49 [V63,T38] ( 3, 3 ) int -> rcx "index expr" ; V64 tmp50 [V64,T52] ( 2, 2 ) int -> rdx "argument with side effect" ; V65 cse0 [V65,T06] ( 4, 12.50) byref -> [rsp+30H] "CSE - aggressive" ; V66 cse1 [V66,T07] ( 4, 12.50) byref -> [rsp+28H] "CSE - aggressive" ; V67 cse2 [V67,T19] ( 3, 5 ) long -> r11 "CSE - moderate" ; V68 cse3 [V68,T61] ( 3, 1.25) long -> r11 "CSE - conservative" ; V69 cse4 [V69,T62] ( 3, 1.25) long -> rdx "CSE - conservative" ; V70 cse5 [V70,T12] ( 3, 10 ) long -> rdx "CSE - aggressive" ; V71 cse6 [V71,T13] ( 3, 10 ) long -> rcx "CSE - aggressive" ; V72 cse7 [V72,T58] ( 3, 1.50) int -> [rsp+60H] "CSE - conservative" ; V73 cse8 [V73,T10] ( 8, 6.50) ref -> r14 "CSE - aggressive" ; V74 cse9 [V74,T59] ( 3, 1.50) int -> rcx "CSE - conservative" ; V75 cse10 [V75,T60] ( 3, 1.50) int -> rcx "CSE - conservative" ; V76 cse11 [V76,T00] ( 9, 25.50) int -> [rsp+5CH] "CSE - aggressive" ; ; Lcl frame size = 152 Mark labels for codegen BB01 : first block BB59 : branch target BB04 : branch target BB06 : branch target BB08 : branch target BB13 : branch target BB11 : branch target BB12 : branch target BB14 : branch target BB16 : branch target BB18 : branch target BB32 : branch target BB21 : branch target BB22 : branch target BB44 : branch target BB26 : branch target BB28 : branch target BB68 : branch target BB23 : branch target BB30 : branch target BB58 : branch target BB60 : branch target BB44 : branch target BB42 : branch target BB36 : branch target BB37 : branch target BB42 : branch target BB40 : branch target BB58 : branch target BB64 : branch target BB31 : branch target BB68 : branch target BB32 : branch target BB48 : branch target BB47 : branch target BB55 : branch target BB54 : branch target BB51 : branch target BB53 : branch target BB58 : branch target BB58 : branch target BB62 : branch target BB63 : branch target BB66 : branch target BB67 : branch target BB69 : throw helper block *************** After genMarkLabelsForCodegen() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..008)-> BB59 ( cond ) i label LIR BB02 [0002] 1 BB01 1 [00E..016)-> BB04 ( cond ) i LIR BB03 [0003] 1 BB02 0.50 [016..01E) i hascall gcsafe LIR BB04 [0004] 2 BB02,BB03 1 [01E..04B)-> BB06 ( cond ) i label LIR BB05 [0052] 1 BB04 0.50 [01E..01F) i hascall gcsafe LIR BB06 [0053] 2 BB04,BB05 1 [01E..034)-> BB08 ( cond ) i label LIR BB07 [0057] 1 BB06 0.50 [033..034) i hascall gcsafe LIR BB08 [0058] 2 BB06,BB07 1 [033..034)-> BB13 ( cond ) i label LIR BB09 [0005] 1 BB08 0.50 [04B..???)-> BB11 ( cond ) i hascall gcsafe LIR BB10 [0097] 1 BB09 0.25 [???..???)-> BB12 (always) i gcsafe LIR BB11 [0096] 1 BB09 0.25 [???..???) i label gcsafe LIR BB12 [0094] 2 BB10,BB11 0.50 [???..054)-> BB14 (always) i label hascall gcsafe LIR BB13 [0006] 1 BB08 0.50 [054..061) i label hascall gcsafe LIR BB14 [0007] 2 BB12,BB13 1 [061..07A)-> BB16 ( cond ) i label gcsafe idxlen LIR BB15 [0064] 1 BB14 0.50 [064..065) i hascall gcsafe LIR BB16 [0065] 2 BB14,BB15 1 [064..065)-> BB18 ( cond ) i label gcsafe idxlen LIR BB17 [0069] 1 BB16 0.50 [064..065) i hascall gcsafe LIR BB18 [0070] 2 BB16,BB17 1 [064..065)-> BB32 ( cond ) i label gcsafe idxlen LIR BB19 [0008] 1 BB18 0.50 [07A..???)-> BB21 ( cond ) i hascall gcsafe LIR BB20 [0101] 1 BB19 0.25 [???..???)-> BB22 (always) i gcsafe LIR BB21 [0100] 1 BB19 0.25 [???..???) i label gcsafe LIR BB22 [0098] 2 BB20,BB21 0.50 [???..106) i label hascall gcsafe LIR BB23 [0020] 2 BB22,BB27 4 0 [106..110)-> BB44 ( cond ) i Loop Loop0 label idxlen bwd bwd-target LIR BB24 [0021] 1 BB23 4 0 [110..120)-> BB26 ( cond ) i idxlen bwd LIR BB25 [0022] 1 BB24 2 0 [120..137)-> BB28 ( cond ) i hascall gcsafe idxlen bwd LIR BB26 [0028] 2 BB24,BB25 4 0 [157..170)-> BB68 ( cond ) i label idxlen bwd LIR BB27 [0114] 1 BB26 4 0 [???..???)-> BB23 (always) internal LIR BB28 [0023] 1 BB25 0.50 [137..13B)-> BB30 ( cond ) i label gcsafe bwd LIR BB29 [0024] 1 BB28 0.50 [13B..14B)-> BB58 (always) i gcsafe idxlen LIR BB30 [0025] 1 BB28 0.50 [14B..14F)-> BB60 ( cond ) i label gcsafe bwd LIR BB31 [0092] 2 BB30,BB41 0.50 [???..???) (return) internal Loop1 label gcsafe LIR BB32 [0030] 2 BB18,BB43 4 [177..17E)-> BB44 ( cond ) i Loop Loop0 label idxlen bwd bwd-target LIR BB33 [0031] 1 BB32 4 [17E..18E)-> BB42 ( cond ) i idxlen bwd LIR BB34 [0032] 1 BB33 2 [18E..???)-> BB36 ( cond ) i hascall gcsafe idxlen bwd LIR BB35 [0109] 1 BB34 1 [???..???)-> BB37 (always) i gcsafe LIR BB36 [0108] 1 BB34 1 [???..???) i label gcsafe LIR BB37 [0106] 2 BB35,BB36 2 [???..1A4)-> BB42 ( cond ) i label hascall gcsafe idxlen bwd LIR BB38 [0033] 1 BB37 0.50 [1A4..1A8)-> BB40 ( cond ) i gcsafe bwd LIR BB39 [0034] 1 BB38 0.50 [1A8..1B8)-> BB58 (always) i gcsafe idxlen LIR BB40 [0035] 1 BB38 0.50 [1B8..1BC)-> BB64 ( cond ) i label gcsafe bwd LIR BB41 [0115] 1 BB40 0.50 [???..???)-> BB31 (always) internal gcsafe LIR BB42 [0038] 2 BB33,BB37 4 [1C4..1DD)-> BB68 ( cond ) i label idxlen bwd LIR BB43 [0116] 1 BB42 4 [???..???)-> BB32 (always) internal LIR BB44 [0040] 2 BB23,BB32 0.50 [1E4..1ED)-> BB48 ( cond ) i label LIR BB45 [0041] 1 BB44 0.50 [1ED..243)-> BB47 ( cond ) i idxlen LIR BB46 [0075] 1 BB45 0.50 [1F5..1F6) i hascall gcsafe LIR BB47 [0076] 2 BB45,BB46 0.50 [1F5..1F6)-> BB55 (always) i label idxlen LIR BB48 [0042] 1 BB44 0.50 [243..252)-> BB54 ( cond ) i label idxlen LIR BB49 [0043] 1 BB48 0.50 [252..261)-> BB51 ( cond ) i hascall gcsafe idxlen LIR BB50 [0083] 1 BB49 0.50 [258..259) i hascall gcsafe LIR BB51 [0084] 2 BB49,BB50 0.50 [258..259)-> BB53 ( cond ) i label gcsafe idxlen LIR BB52 [0088] 1 BB51 0.50 [258..259) i hascall gcsafe LIR BB53 [0089] 2 BB51,BB52 0.50 [258..259) i label gcsafe idxlen LIR BB54 [0044] 2 BB48,BB53 0.50 [261..276) i label LIR BB55 [0045] 2 BB47,BB54 0.50 [276..2CF)-> BB58 ( cond ) i label idxlen LIR BB56 [0047] 1 BB55 0.50 [2CF..2D7)-> BB58 ( cond ) i hascall LIR BB57 [0048] 1 BB56 0.50 [2D7..2E3) i hascall gcsafe idxlen LIR BB58 [0091] 5 BB29,BB39,BB55,BB56,BB57 0.50 [???..???) (return) internal label LIR BB59 [0001] 1 BB01 0 [008..00E) (throw ) i rare label hascall gcsafe LIR BB60 [0026] 1 BB30 0 [14F..???)-> BB62 ( cond ) i rare label hascall gcsafe bwd LIR BB61 [0105] 1 BB60 0 [???..???)-> BB63 (always) i rare gcsafe LIR BB62 [0104] 1 BB60 0 [???..???) i rare label gcsafe LIR BB63 [0102] 2 BB61,BB62 0 [???..157) (throw ) i rare label hascall gcsafe bwd LIR BB64 [0036] 1 BB40 0 [1BC..???)-> BB66 ( cond ) i rare label hascall gcsafe bwd LIR BB65 [0113] 1 BB64 0 [???..???)-> BB67 (always) i rare gcsafe LIR BB66 [0112] 1 BB64 0 [???..???) i rare label gcsafe LIR BB67 [0110] 2 BB65,BB66 0 [???..1C4) (throw ) i rare label hascall gcsafe bwd LIR BB68 [0039] 2 BB26,BB42 0 [1DD..1E4) (throw ) i rare label hascall gcsafe bwd LIR BB69 [0117] 0 0 [???..???) (throw ) keep i internal rare label LIR ----------------------------------------------------------------------------------------------------------------------------------------- Setting stack level from -572662307 to 0 =============== Generating BB01 [000..008) -> BB59 (cond), preds={} succs={BB02,BB59} flags=0x00000000.20010020: i label LIR BB01 IN (4)={V00 V01 V03 V02} + ByrefExposed + GcHeap OUT(4)={V00 V01 V03 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB01 V00(rsi) V01(rdi) V03(rbx) V02(rbp) Change life 00000000000000000000000000000000 {} -> 00000000000000000000000000060210 {V00 V01 V02 V03} V00 in reg rsi is becoming live [------] Live regs: 00000000 {} => 00000040 {rsi} New debug range: first V01 in reg rdi is becoming live [------] Live regs: 00000040 {rsi} => 000000C0 {rsi rdi} New debug range: first V03 in reg rbx is becoming live [------] Live regs: 000000C0 {rsi rdi} => 000000C8 {rbx rsi rdi} New debug range: first V02 in reg rbp is becoming live [------] Live regs: 000000C8 {rbx rsi rdi} => 000000E8 {rbx rbp rsi rdi} New debug range: first Live regs: (unchanged) 000000E8 {rbx rbp rsi rdi} GC regs: (unchanged) 000000E0 {rbp rsi rdi} Byref regs: (unchanged) 00000000 {} L_M38507_BB01: Mapped BB01 to G_M38507_IG02 Label: IG02, GCvars=00000000000000000000000000000000 {}, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {} Scope info: begin block BB01, IL range [000..008) Added IP mapping: 0x0000 STACK_EMPTY (G_M38507_IG02,ins#0,ofs#0) label Generating: N003 (???,???) [001332] ------------ IL_OFFSET void IL offset: 0x0 REG NA Generating: N005 ( 1, 1) [000000] ------------ t0 = LCL_VAR ref V01 arg1 u:1 rdi REG rdi $101 Generating: N007 ( 1, 1) [000001] -c---------- t1 = CNS_INT ref null REG NA $VN.Null /--* t0 ref +--* t1 ref Generating: N009 ( 3, 3) [000002] J------N---- * EQ void REG NA $180 IN0001: test rdi, rdi Generating: N011 ( 5, 5) [000003] ------------ * JTRUE void REG NA IN0002: je L_M38507_BB59 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 1 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 1 =============== Generating BB02 [00E..016) -> BB04 (cond), preds={BB01} succs={BB03,BB04} flags=0x00000000.20000020: i LIR BB02 IN (4)={V00 V01 V03 V02} + ByrefExposed + GcHeap OUT(4)={V00 V01 V03 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB02 V00(rsi) V01(rdi) V03(rbx) V02(rbp) Liveness not changing: 00000000000000000000000000060210 {V00 V01 V02 V03} Live regs: 00000000 {} => 000000E8 {rbx rbp rsi rdi} GC regs: 00000000 {} => 000000E0 {rbp rsi rdi} Byref regs: (unchanged) 00000000 {} L_M38507_BB02: Scope info: begin block BB02, IL range [00E..016) Added IP mapping: 0x000E STACK_EMPTY (G_M38507_IG02,ins#2,ofs#9) label Generating: N015 (???,???) [001333] ------------ IL_OFFSET void IL offset: 0xe REG NA Generating: N017 ( 1, 1) [000004] ------------ t4 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t4 ref Generating: N019 ( 2, 2) [000814] -c---------- t814 = * LEA(b+8) byref REG NA /--* t814 byref Generating: N021 ( 4, 4) [000005] -c-XG------- t5 = * IND ref REG NA Generating: N023 ( 1, 1) [000006] -c---------- t6 = CNS_INT ref null REG NA $VN.Null /--* t5 ref +--* t6 ref Generating: N025 ( 6, 6) [000007] J--XG--N---- * NE void REG NA IN0003: cmp gword ptr [rsi+8], 0 Generating: N027 ( 8, 8) [000008] ---XG------- * JTRUE void REG NA IN0004: jne L_M38507_BB04 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 2 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 2 =============== Generating BB03 [016..01E), preds={BB02} succs={BB04} flags=0x00000002.20080020: i hascall gcsafe LIR BB03 IN (4)={V00 V01 V03 V02} + ByrefExposed + GcHeap OUT(4)={V00 V01 V03 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB03 V00(rsi) V01(rdi) V03(rbx) V02(rbp) Liveness not changing: 00000000000000000000000000060210 {V00 V01 V02 V03} Live regs: 00000000 {} => 000000E8 {rbx rbp rsi rdi} GC regs: 00000000 {} => 000000E0 {rbp rsi rdi} Byref regs: (unchanged) 00000000 {} L_M38507_BB03: Adding label due to BB weight difference: BBJ_COND BB02 with weight 100 different from BB03 with weight 50 G_M38507_IG02: ; offs=000000H, funclet=00, bbWeight=1 Mapped BB03 to G_M38507_IG03 Label: IG03, GCvars=00000000000000000000000000000000 {}, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {} Scope info: begin block BB03, IL range [016..01E) Generating: N031 ( 1, 1) [000526] ------------ t526 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t526 ref Generating: N033 (???,???) [001455] ------------ t1455 = * PUTARG_REG ref REG rcx IN0005: mov rcx, rsi GC regs: 000000E0 {rbp rsi rdi} => 000000E2 {rcx rbp rsi rdi} Generating: N035 ( 1, 1) [000527] ------------ t527 = CNS_INT int 0 REG rdx $c0 IN0006: xor edx, edx /--* t527 int Generating: N037 (???,???) [001456] ------------ t1456 = * PUTARG_REG int REG rdx /--* t1455 ref this in rcx +--* t1456 int arg1 in rdx Generating: N039 ( 16, 10) [000528] --CXG------- t528 = * CALL int System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Initialize REG rax $1c2 GC regs: 000000E2 {rcx rbp rsi rdi} => 000000E0 {rbp rsi rdi} Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {} IN0007: call System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Initialize(int):int:this //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 3 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 3 =============== Generating BB04 [01E..04B) -> BB06 (cond), preds={BB02,BB03} succs={BB05,BB06} flags=0x00000000.20010020: i label LIR BB04 IN (4)={V00 V01 V03 V02 } + ByrefExposed + GcHeap OUT(6)={V00 V01 V73 V03 V02 V35} + ByrefExposed + GcHeap Recording Var Locations at start of BB04 V00(rsi) V01(rdi) V03(rbx) V02(rbp) Liveness not changing: 00000000000000000000000000060210 {V00 V01 V02 V03} Live regs: 00000000 {} => 000000E8 {rbx rbp rsi rdi} GC regs: 00000000 {} => 000000E0 {rbp rsi rdi} Byref regs: (unchanged) 00000000 {} L_M38507_BB04: G_M38507_IG03: ; offs=000014H, funclet=00, bbWeight=0.50 Mapped BB04 to G_M38507_IG04 Label: IG04, GCvars=00000000000000000000000000000000 {}, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {} Scope info: begin block BB04, IL range [01E..04B) Added IP mapping: 0x001E STACK_EMPTY (G_M38507_IG04,ins#0,ofs#0) label Generating: N043 (???,???) [001334] ------------ IL_OFFSET void IL offset: 0x1e REG NA Generating: N045 ( 1, 1) [000009] ------------ t9 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t9 ref Generating: N047 ( 2, 2) [000818] -c---------- t818 = * LEA(b+8) byref REG NA /--* t818 byref Generating: N049 ( 4, 4) [000010] nc--GO------ t10 = * IND ref REG NA Generating: N051 ( 1, 1) [000011] -c---------- t11 = CNS_INT ref null REG NA $VN.Null /--* t10 ref +--* t11 ref Generating: N053 ( 9, 6) [000012] N---GO------ t12 = * NE int REG rcx IN0008: cmp gword ptr [rsi+8], 0 IN0009: setne cl IN000a: movzx rcx, cl /--* t12 int Generating: N055 ( 9, 6) [000544] DA--GO------ * STORE_LCL_VAR int V33 tmp19 d:1 rcx REG rcx V33 in reg rcx is becoming live [000544] Live regs: 000000E8 {rbx rbp rsi rdi} => 000000EA {rcx rbx rbp rsi rdi} Live vars: {V00 V01 V02 V03} => {V00 V01 V02 V03 V33} genIPmappingAdd: ignoring duplicate IL offset 0x1e Generating: N057 (???,???) [001335] ------------ IL_OFFSET void IL offset: 0x1e REG NA Generating: N059 ( 2, 10) [000537] H----------- t537 = CNS_INT(h) long 0xD1FFAB1E [ICON_STR_HDL] REG rdx $43 IN000b: mov rdx, 0xD1FFAB1E /--* t537 long Generating: N061 ( 4, 12) [000538] #---G------- t538 = * IND ref REG r14 $105 IN000c: mov r14, gword ptr [rdx] GC regs: 000000E0 {rbp rsi rdi} => 000040E0 {rbp rsi rdi r14} /--* t538 ref Generating: N063 ( 4, 12) [001291] DA--G------- * STORE_LCL_VAR ref V73 cse8 d:1 r14 REG r14 GC regs: 000040E0 {rbp rsi rdi r14} => 000000E0 {rbp rsi rdi} V73 in reg r14 is becoming live [001291] Live regs: 000000EA {rcx rbx rbp rsi rdi} => 000040EA {rcx rbx rbp rsi rdi r14} Live vars: {V00 V01 V02 V03 V33} => {V00 V01 V02 V03 V33 V73} GC regs: 000000E0 {rbp rsi rdi} => 000040E0 {rbp rsi rdi r14} genIPmappingAdd: ignoring duplicate IL offset 0x1e Generating: N065 (???,???) [001336] ------------ IL_OFFSET void IL offset: 0x1e REG NA Generating: N067 ( 1, 1) [001294] ------------ t1294 = LCL_VAR ref V73 cse8 u:1 r14 REG r14 $105 /--* t1294 ref Generating: N069 ( 1, 3) [000556] DA--G------- * STORE_LCL_VAR ref V35 tmp21 d:1 rdx REG rdx IN000d: mov rdx, r14 V35 in reg rdx is becoming live [000556] Live regs: 000040EA {rcx rbx rbp rsi rdi r14} => 000040EE {rcx rdx rbx rbp rsi rdi r14} Live vars: {V00 V01 V02 V03 V33 V73} => {V00 V01 V02 V03 V33 V35 V73} GC regs: 000040E0 {rbp rsi rdi r14} => 000040E4 {rdx rbp rsi rdi r14} genIPmappingAdd: ignoring duplicate IL offset 0x1e Generating: N071 (???,???) [001337] ------------ IL_OFFSET void IL offset: 0x1e REG NA Generating: N073 ( 1, 1) [000546] ------------ t546 = LCL_VAR int V33 tmp19 u:1 rcx (last use) REG rcx Generating: N075 ( 1, 1) [000547] -c---------- t547 = CNS_INT int 0 REG NA $c0 /--* t546 int +--* t547 int Generating: N077 ( 3, 3) [000548] J------N---- * NE void REG NA V33 in reg rcx is becoming dead [000546] Live regs: 000040EE {rcx rdx rbx rbp rsi rdi r14} => 000040EC {rdx rbx rbp rsi rdi r14} Live vars: {V00 V01 V02 V03 V33 V35 V73} => {V00 V01 V02 V03 V35 V73} IN000e: test ecx, ecx Generating: N079 ( 5, 5) [000549] ------------ * JTRUE void REG NA IN000f: jne L_M38507_BB06 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 4 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 4 =============== Generating BB05 [01E..01F), preds={BB04} succs={BB06} flags=0x00000002.20080020: i hascall gcsafe LIR BB05 IN (6)={V00 V01 V73 V03 V02 V35} + ByrefExposed + GcHeap OUT(5)={V00 V01 V73 V03 V02 } + ByrefExposed + GcHeap Recording Var Locations at start of BB05 V00(rsi) V01(rdi) V73(r14) V03(rbx) V02(rbp) V35(rdx) Liveness not changing: 00000000000000000000000001060610 {V00 V01 V02 V03 V35 V73} Live regs: 00000000 {} => 000040EC {rdx rbx rbp rsi rdi r14} GC regs: 00000000 {} => 000040E4 {rdx rbp rsi rdi r14} Byref regs: (unchanged) 00000000 {} L_M38507_BB05: Adding label due to BB weight difference: BBJ_COND BB04 with weight 100 different from BB05 with weight 50 G_M38507_IG04: ; offs=00001EH, funclet=00, bbWeight=1 Mapped BB05 to G_M38507_IG05 Label: IG05, GCvars=00000000000000000000000000000000 {}, gcrefRegs=000040E4 {rdx rbp rsi rdi r14}, byrefRegs=00000000 {} Scope info: begin block BB05, IL range [01E..01F) genIPmappingAdd: ignoring duplicate IL offset 0x1e Generating: N083 (???,???) [001338] ------------ IL_OFFSET void IL offset: 0x1e REG NA Generating: N085 ( 1, 1) [000550] ------------ t550 = LCL_VAR ref V35 tmp21 u:1 rdx REG rdx $105 /--* t550 ref Generating: N087 (???,???) [001457] ------------ t1457 = * PUTARG_REG ref REG rcx IN0010: mov rcx, rdx GC regs: 000040E4 {rdx rbp rsi rdi r14} => 000040E6 {rcx rdx rbp rsi rdi r14} Generating: N089 ( 1, 1) [000551] ------------ t551 = LCL_VAR ref V35 tmp21 u:1 rdx (last use) REG rdx $105 /--* t551 ref Generating: N091 (???,???) [001458] ------------ t1458 = * PUTARG_REG ref REG rdx V35 in reg rdx is becoming dead [000551] Live regs: 000040EC {rdx rbx rbp rsi rdi r14} => 000040E8 {rbx rbp rsi rdi r14} Live vars: {V00 V01 V02 V03 V35 V73} => {V00 V01 V02 V03 V73} GC regs: 000040E6 {rcx rdx rbp rsi rdi r14} => 000040E2 {rcx rbp rsi rdi r14} GC regs: 000040E2 {rcx rbp rsi rdi r14} => 000040E6 {rcx rdx rbp rsi rdi r14} /--* t1457 ref arg0 in rcx +--* t1458 ref arg1 in rdx Generating: N093 ( 16, 9) [000552] --CXG------- * CALL void System.Diagnostics.Debug.Fail REG NA $VN.Void GC regs: 000040E6 {rcx rdx rbp rsi rdi r14} => 000040E4 {rdx rbp rsi rdi r14} GC regs: 000040E4 {rdx rbp rsi rdi r14} => 000040E0 {rbp rsi rdi r14} Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=000040E0 {rbp rsi rdi r14}, byrefRegs=00000000 {} IN0011: call System.Diagnostics.Debug:Fail(System.String,System.String) //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 5 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 5 =============== Generating BB06 [01E..034) -> BB08 (cond), preds={BB04,BB05} succs={BB07,BB08} flags=0x00000000.20010020: i label LIR BB06 IN (5)={ V00 V01 V73 V03 V02 } + ByrefExposed + GcHeap OUT(7)={V04 V00 V01 V73 V03 V02 V37} + ByrefExposed + GcHeap Recording Var Locations at start of BB06 V00(rsi) V01(rdi) V73(r14) V03(rbx) V02(rbp) Liveness not changing: 00000000000000000000000000060610 {V00 V01 V02 V03 V73} Live regs: 00000000 {} => 000040E8 {rbx rbp rsi rdi r14} GC regs: 00000000 {} => 000040E0 {rbp rsi rdi r14} Byref regs: (unchanged) 00000000 {} L_M38507_BB06: G_M38507_IG05: ; offs=000041H, funclet=00, bbWeight=0.50 Mapped BB06 to G_M38507_IG06 Label: IG06, GCvars=00000000000000000000000000000000 {}, gcrefRegs=000040E0 {rbp rsi rdi r14}, byrefRegs=00000000 {} Scope info: begin block BB06, IL range [01E..034) Added IP mapping: 0x002C STACK_EMPTY (G_M38507_IG06,ins#0,ofs#0) label Generating: N097 (???,???) [001339] ------------ IL_OFFSET void IL offset: 0x2c REG NA Generating: N099 ( 1, 1) [000015] ------------ t15 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t15 ref Generating: N101 ( 2, 2) [000822] -c---------- t822 = * LEA(b+16) byref REG NA /--* t822 byref Generating: N103 ( 4, 4) [000016] n---GO------ t16 = * IND ref REG r15 IN0012: mov r15, gword ptr [rsi+16] GC regs: 000040E0 {rbp rsi rdi r14} => 0000C0E0 {rbp rsi rdi r14 r15} /--* t16 ref Generating: N105 ( 4, 4) [000018] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:1 r15 REG r15 GC regs: 0000C0E0 {rbp rsi rdi r14 r15} => 000040E0 {rbp rsi rdi r14} V04 in reg r15 is becoming live [000018] Live regs: 000040E8 {rbx rbp rsi rdi r14} => 0000C0E8 {rbx rbp rsi rdi r14 r15} Live vars: {V00 V01 V02 V03 V73} => {V00 V01 V02 V03 V04 V73} New debug range: first GC regs: 000040E0 {rbp rsi rdi r14} => 0000C0E0 {rbp rsi rdi r14 r15} Added IP mapping: 0x0033 STACK_EMPTY (G_M38507_IG06,ins#1,ofs#4) Generating: N107 (???,???) [001340] ------------ IL_OFFSET void IL offset: 0x33 REG NA Generating: N109 ( 1, 1) [000019] ------------ t19 = LCL_VAR ref V04 loc0 u:1 r15 REG r15 Generating: N111 ( 1, 1) [000020] -c---------- t20 = CNS_INT ref null REG NA $VN.Null /--* t19 ref +--* t20 ref Generating: N113 ( 6, 3) [000021] N----------- t21 = * NE int REG rcx IN0013: test r15, r15 IN0014: setne cl IN0015: movzx rcx, cl /--* t21 int Generating: N115 ( 6, 3) [000566] DA---------- * STORE_LCL_VAR int V36 tmp22 d:1 rcx REG rcx V36 in reg rcx is becoming live [000566] Live regs: 0000C0E8 {rbx rbp rsi rdi r14 r15} => 0000C0EA {rcx rbx rbp rsi rdi r14 r15} Live vars: {V00 V01 V02 V03 V04 V73} => {V00 V01 V02 V03 V04 V36 V73} genIPmappingAdd: ignoring duplicate IL offset 0x33 Generating: N117 (???,???) [001341] ------------ IL_OFFSET void IL offset: 0x33 REG NA Generating: N119 ( 1, 1) [001295] ------------ t1295 = LCL_VAR ref V73 cse8 u:1 r14 REG r14 $105 /--* t1295 ref Generating: N121 ( 1, 3) [000576] DA--G------- * STORE_LCL_VAR ref V37 tmp23 d:1 rdx REG rdx IN0016: mov rdx, r14 V37 in reg rdx is becoming live [000576] Live regs: 0000C0EA {rcx rbx rbp rsi rdi r14 r15} => 0000C0EE {rcx rdx rbx rbp rsi rdi r14 r15} Live vars: {V00 V01 V02 V03 V04 V36 V73} => {V00 V01 V02 V03 V04 V36 V37 V73} GC regs: 0000C0E0 {rbp rsi rdi r14 r15} => 0000C0E4 {rdx rbp rsi rdi r14 r15} genIPmappingAdd: ignoring duplicate IL offset 0x33 Generating: N123 (???,???) [001342] ------------ IL_OFFSET void IL offset: 0x33 REG NA Generating: N125 ( 1, 1) [000568] ------------ t568 = LCL_VAR int V36 tmp22 u:1 rcx (last use) REG rcx Generating: N127 ( 1, 1) [000569] -c---------- t569 = CNS_INT int 0 REG NA $c0 /--* t568 int +--* t569 int Generating: N129 ( 3, 3) [000570] J------N---- * NE void REG NA V36 in reg rcx is becoming dead [000568] Live regs: 0000C0EE {rcx rdx rbx rbp rsi rdi r14 r15} => 0000C0EC {rdx rbx rbp rsi rdi r14 r15} Live vars: {V00 V01 V02 V03 V04 V36 V37 V73} => {V00 V01 V02 V03 V04 V37 V73} IN0017: test ecx, ecx Generating: N131 ( 5, 5) [000571] ------------ * JTRUE void REG NA IN0018: jne L_M38507_BB08 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 6 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 6 =============== Generating BB07 [033..034), preds={BB06} succs={BB08} flags=0x00000002.20080020: i hascall gcsafe LIR BB07 IN (7)={V04 V00 V01 V73 V03 V02 V37} + ByrefExposed + GcHeap OUT(6)={V04 V00 V01 V73 V03 V02 } + ByrefExposed + GcHeap Recording Var Locations at start of BB07 V04(r15) V00(rsi) V01(rdi) V73(r14) V03(rbx) V02(rbp) V37(rdx) Liveness not changing: 00000000000000000000008000060614 {V00 V01 V02 V03 V04 V37 V73} Live regs: 00000000 {} => 0000C0EC {rdx rbx rbp rsi rdi r14 r15} GC regs: 00000000 {} => 0000C0E4 {rdx rbp rsi rdi r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB07: Adding label due to BB weight difference: BBJ_COND BB06 with weight 100 different from BB07 with weight 50 G_M38507_IG06: ; offs=000049H, funclet=00, bbWeight=1 Mapped BB07 to G_M38507_IG07 Label: IG07, GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000C0E4 {rdx rbp rsi rdi r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB07, IL range [033..034) genIPmappingAdd: ignoring duplicate IL offset 0x33 Generating: N135 (???,???) [001343] ------------ IL_OFFSET void IL offset: 0x33 REG NA Generating: N137 ( 2, 10) [000823] H----------- t823 = CNS_INT(h) long 0xD1FFAB1E "expected entries to be non-null" REG rcx $46 IN0019: mov rcx, 0xD1FFAB1E /--* t823 long Generating: N139 ( 4, 12) [000824] #---G------- t824 = * IND ref REG rcx $106 IN001a: mov rcx, gword ptr [rcx] GC regs: 0000C0E4 {rdx rbp rsi rdi r14 r15} => 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} /--* t824 ref Generating: N141 (???,???) [001459] ----G------- t1459 = * PUTARG_REG ref REG rcx GC regs: 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} => 0000C0E4 {rdx rbp rsi rdi r14 r15} GC regs: 0000C0E4 {rdx rbp rsi rdi r14 r15} => 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} Generating: N143 ( 1, 1) [000573] ------------ t573 = LCL_VAR ref V37 tmp23 u:1 rdx (last use) REG rdx $105 /--* t573 ref Generating: N145 (???,???) [001460] ------------ t1460 = * PUTARG_REG ref REG rdx V37 in reg rdx is becoming dead [000573] Live regs: 0000C0EC {rdx rbx rbp rsi rdi r14 r15} => 0000C0E8 {rbx rbp rsi rdi r14 r15} Live vars: {V00 V01 V02 V03 V04 V37 V73} => {V00 V01 V02 V03 V04 V73} GC regs: 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} => 0000C0E2 {rcx rbp rsi rdi r14 r15} GC regs: 0000C0E2 {rcx rbp rsi rdi r14 r15} => 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} /--* t1459 ref arg0 in rcx +--* t1460 ref arg1 in rdx Generating: N147 ( 19, 20) [000574] --CXG------- * CALL void System.Diagnostics.Debug.Fail REG NA $VN.Void GC regs: 0000C0E6 {rcx rdx rbp rsi rdi r14 r15} => 0000C0E4 {rdx rbp rsi rdi r14 r15} GC regs: 0000C0E4 {rdx rbp rsi rdi r14 r15} => 0000C0E0 {rbp rsi rdi r14 r15} Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000C0E0 {rbp rsi rdi r14 r15}, byrefRegs=00000000 {} IN001b: call System.Diagnostics.Debug:Fail(System.String,System.String) //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 7 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 7 =============== Generating BB08 [033..034) -> BB13 (cond), preds={BB06,BB07} succs={BB09,BB13} flags=0x00000000.20010020: i label LIR BB08 IN (6)={V04 V00 V01 V73 V03 V02} + ByrefExposed + GcHeap OUT(7)={V04 V00 V01 V73 V05 V03 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB08 V04(r15) V00(rsi) V01(rdi) V73(r14) V03(rbx) V02(rbp) Liveness not changing: 00000000000000000000000000060614 {V00 V01 V02 V03 V04 V73} Live regs: 00000000 {} => 0000C0E8 {rbx rbp rsi rdi r14 r15} GC regs: 00000000 {} => 0000C0E0 {rbp rsi rdi r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB08: G_M38507_IG07: ; offs=000061H, funclet=00, bbWeight=0.50 Mapped BB08 to G_M38507_IG08 Label: IG08, GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000C0E0 {rbp rsi rdi r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB08, IL range [033..034) Added IP mapping: 0x0041 STACK_EMPTY (G_M38507_IG08,ins#0,ofs#0) label Generating: N151 (???,???) [001344] ------------ IL_OFFSET void IL offset: 0x41 REG NA Generating: N153 ( 1, 1) [000025] ------------ t25 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t25 ref Generating: N155 ( 2, 2) [000828] -c---------- t828 = * LEA(b+24) byref REG NA /--* t828 byref Generating: N157 ( 4, 4) [000026] n---GO------ t26 = * IND ref REG r12 IN001c: mov r12, gword ptr [rsi+24] GC regs: 0000C0E0 {rbp rsi rdi r14 r15} => 0000D0E0 {rbp rsi rdi r12 r14 r15} /--* t26 ref Generating: N159 ( 4, 4) [000028] DA--GO------ * STORE_LCL_VAR ref V05 loc1 d:1 r12 REG r12 GC regs: 0000D0E0 {rbp rsi rdi r12 r14 r15} => 0000C0E0 {rbp rsi rdi r14 r15} V05 in reg r12 is becoming live [000028] Live regs: 0000C0E8 {rbx rbp rsi rdi r14 r15} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} Live vars: {V00 V01 V02 V03 V04 V73} => {V00 V01 V02 V03 V04 V05 V73} New debug range: first GC regs: 0000C0E0 {rbp rsi rdi r14 r15} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Added IP mapping: 0x0048 STACK_EMPTY (G_M38507_IG08,ins#1,ofs#4) Generating: N161 (???,???) [001345] ------------ IL_OFFSET void IL offset: 0x48 REG NA Generating: N163 ( 1, 1) [000029] ------------ t29 = LCL_VAR ref V05 loc1 u:1 r12 REG r12 Generating: N165 ( 1, 1) [000030] -c---------- t30 = CNS_INT ref null REG NA $VN.Null /--* t29 ref +--* t30 ref Generating: N167 ( 3, 3) [000031] J------N---- * EQ void REG NA IN001d: test r12, r12 Generating: N169 ( 5, 5) [000032] ------------ * JTRUE void REG NA IN001e: je L_M38507_BB13 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 8 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG08,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 8 =============== Generating BB09 [04B..???) -> BB11 (cond), preds={BB08} succs={BB10,BB11} flags=0x00000002.20080020: i hascall gcsafe LIR BB09 IN (7)={V04 V00 V01 V73 V05 V03 V02 } + ByrefExposed + GcHeap OUT(9)={V04 V00 V01 V73 V05 V03 V02 V29 V68} + ByrefExposed + GcHeap Recording Var Locations at start of BB09 V04(r15) V00(rsi) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) Liveness not changing: 00000000000000000000000000070614 {V00 V01 V02 V03 V04 V05 V73} Live regs: 00000000 {} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} GC regs: 00000000 {} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB09: Adding label due to BB weight difference: BBJ_COND BB08 with weight 100 different from BB09 with weight 50 G_M38507_IG08: ; offs=000073H, funclet=00, bbWeight=1 Mapped BB09 to G_M38507_IG09 Label: IG09, GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB09, IL range [04B..???) Added IP mapping: 0x004B STACK_EMPTY (G_M38507_IG09,ins#0,ofs#0) label Generating: N173 (???,???) [001346] ------------ IL_OFFSET void IL offset: 0x4b REG NA Generating: N175 ( 1, 1) [000486] !----------- t486 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t486 ref Generating: N177 ( 3, 2) [000487] #----O------ t487 = * IND long REG rcx $2e8 IN001f: mov rcx, qword ptr [rsi] /--* t487 long Generating: N179 ( 3, 3) [000489] DA---O------ * STORE_LCL_VAR long V29 tmp15 d:1 rcx REG rcx V29 in reg rcx is becoming live [000489] Live regs: 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} => 0000D0EA {rcx rbx rbp rsi rdi r12 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V73} => {V00 V01 V02 V03 V04 V05 V29 V73} Generating: N181 ( 1, 1) [000491] ------------ t491 = LCL_VAR long V29 tmp15 u:1 rcx REG rcx $2e7 /--* t491 long Generating: N183 ( 2, 2) [000493] -c---------- t493 = * LEA(b+56) long REG NA /--* t493 long Generating: N185 ( 4, 4) [000494] #----------- t494 = * IND long REG rdx $2e9 IN0020: mov rdx, qword ptr [rcx+56] /--* t494 long Generating: N187 ( 7, 6) [000495] #----------- t495 = * IND long REG rdx $2ea IN0021: mov rdx, qword ptr [rdx] /--* t495 long Generating: N189 ( 8, 7) [000497] -c---------- t497 = * LEA(b+64) long REG NA /--* t497 long Generating: N191 ( 10, 9) [000501] n----------- t501 = * IND long REG r11 IN0022: mov r11, qword ptr [rdx+64] /--* t501 long Generating: N193 ( 14, 12) [001266] DA---------- * STORE_LCL_VAR long V68 cse3 d:1 r11 REG r11 V68 in reg r11 is becoming live [001266] Live regs: 0000D0EA {rcx rbx rbp rsi rdi r12 r14 r15} => 0000D8EA {rcx rbx rbp rsi rdi r11 r12 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V29 V73} => {V00 V01 V02 V03 V04 V05 V29 V68 V73} Generating: N195 ( 3, 2) [001267] ------------ t1267 = LCL_VAR long V68 cse3 u:1 r11 REG r11 Generating: N197 ( 1, 1) [000504] -c---------- t504 = CNS_INT long 0 REG NA $243 /--* t1267 long +--* t504 long Generating: N199 ( 19, 16) [000505] J------N---- * EQ void REG NA IN0023: test r11, r11 Generating: N201 ( 21, 18) [001148] ------------ * JTRUE void REG NA IN0024: je L_M38507_BB11 Scope info: ignoring block end //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 9 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG08,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 9 =============== Generating BB10 [???..???) -> BB12 (always), preds={BB09} succs={BB12} flags=0x00000000.20080020: i gcsafe LIR BB10 IN (8)={V04 V00 V01 V73 V05 V03 V02 V68} + ByrefExposed + GcHeap OUT(8)={V04 V00 V01 V73 V05 V03 V02 V31 } + ByrefExposed + GcHeap Recording Var Locations at start of BB10 V04(r15) V00(rsi) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) V68(r11) Change life 00000000000000002000040000070614 {V00 V01 V02 V03 V04 V05 V29 V68 V73} -> 00000000000000002000000000070614 {V00 V01 V02 V03 V04 V05 V68 V73} V29 in reg rcx is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 0000D8E8 {rbx rbp rsi rdi r11 r12 r14 r15} GC regs: 00000000 {} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB10: Adding label due to BB weight difference: BBJ_COND BB09 with weight 50 different from BB10 with weight 25 G_M38507_IG09: ; offs=000080H, funclet=00, bbWeight=0.50 Mapped BB10 to G_M38507_IG10 Label: IG10, GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB10, IL range [???..???) Scope info: ignoring block beginning Generating: N205 ( 3, 2) [001269] ------------ t1269 = LCL_VAR long V68 cse3 u:1 r11 (last use) REG r11 /--* t1269 long Generating: N207 ( 3, 3) [001150] DA---------- * STORE_LCL_VAR long V31 tmp17 d:3 r11 REG r11 V68 in reg r11 is becoming dead [001269] Live regs: 0000D8E8 {rbx rbp rsi rdi r11 r12 r14 r15} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V68 V73} => {V00 V01 V02 V03 V04 V05 V73} V31 in reg r11 is becoming live [001150] Live regs: 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} => 0000D8E8 {rbx rbp rsi rdi r11 r12 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V73} => {V00 V01 V02 V03 V04 V05 V31 V73} Scope info: ignoring block end IN0025: jmp L_M38507_BB12 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 10 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG08,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 10 =============== Generating BB11 [???..???), preds={BB09} succs={BB12} flags=0x00000000.20090020: i label gcsafe LIR BB11 IN (8)={V04 V00 V01 V73 V05 V03 V02 V29} + ByrefExposed + GcHeap OUT(8)={V04 V00 V01 V73 V05 V03 V02 V31 } + ByrefExposed + GcHeap Recording Var Locations at start of BB11 V04(r15) V00(rsi) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) V29(rcx) Change life 00000000000000000000000400070614 {V00 V01 V02 V03 V04 V05 V31 V73} -> 00000000000000000000040000070614 {V00 V01 V02 V03 V04 V05 V29 V73} V31 in reg r11 is becoming dead [------] Live regs: (unchanged) 00000000 {} V29 in reg rcx is becoming live [------] Live regs: 00000000 {} => 00000002 {rcx} Live regs: 00000002 {rcx} => 0000D0EA {rcx rbx rbp rsi rdi r12 r14 r15} GC regs: 00000000 {} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB11: G_M38507_IG10: ; offs=000097H, funclet=00, bbWeight=0.25 Mapped BB11 to G_M38507_IG11 Label: IG11, GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB11, IL range [???..???) Scope info: ignoring block beginning Generating: N211 ( 1, 1) [000490] ------?----- t490 = LCL_VAR long V29 tmp15 u:1 rcx (last use) REG rcx $2e7 /--* t490 long Generating: N213 (???,???) [001461] ------------ t1461 = * PUTARG_REG long REG rcx V29 in reg rcx is becoming dead [000490] Live regs: 0000D0EA {rcx rbx rbp rsi rdi r12 r14 r15} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V29 V73} => {V00 V01 V02 V03 V04 V05 V73} Generating: N215 ( 2, 10) [000502] H-----?----- t502 = CNS_INT(h) long 0xd1ffab1e global ptr REG rdx $49 IN0026: mov rdx, 0xD1FFAB1E /--* t502 long Generating: N217 (???,???) [001462] ------------ t1462 = * PUTARG_REG long REG rdx /--* t1461 long arg0 in rcx +--* t1462 long arg1 in rdx Generating: N219 ( 17, 18) [000503] --C-G-?----- t503 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS REG rax $308 Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} IN0027: call CORINFO_HELP_RUNTIMEHANDLE_CLASS /--* t503 long Generating: N221 ( 17, 18) [001152] DA--G------- * STORE_LCL_VAR long V31 tmp17 d:2 r11 REG r11 IN0028: mov r11, rax V31 in reg r11 is becoming live [001152] Live regs: 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} => 0000D8E8 {rbx rbp rsi rdi r11 r12 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V73} => {V00 V01 V02 V03 V04 V05 V31 V73} Scope info: ignoring block end //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 11 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG08,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 11 =============== Generating BB12 [???..054) -> BB14 (always), preds={BB10,BB11} succs={BB14} flags=0x00000002.20090020: i label hascall gcsafe LIR BB12 IN (8)={V04 V00 V01 V73 V05 V03 V02 V31 } + ByrefExposed + GcHeap OUT(8)={V04 V00 V01 V73 V05 V03 V02 V15} + ByrefExposed + GcHeap Recording Var Locations at start of BB12 V04(r15) V00(rsi) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) V31(r11) Liveness not changing: 00000000000000000000000400070614 {V00 V01 V02 V03 V04 V05 V31 V73} Live regs: 00000000 {} => 0000D8E8 {rbx rbp rsi rdi r11 r12 r14 r15} GC regs: 00000000 {} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB12: G_M38507_IG11: ; offs=00009CH, funclet=00, bbWeight=0.25 Mapped BB12 to G_M38507_IG12 Label: IG12, GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB12, IL range [???..054) Scope info: ignoring block beginning Generating: N225 ( 1, 1) [000484] ------------ t484 = LCL_VAR ref V05 loc1 u:1 r12 REG r12 /--* t484 ref Generating: N227 (???,???) [001463] ------------ t1463 = * PUTARG_REG ref REG rcx IN0029: mov rcx, r12 GC regs: 0000D0E0 {rbp rsi rdi r12 r14 r15} => 0000D0E2 {rcx rbp rsi rdi r12 r14 r15} Generating: N229 ( 1, 1) [000831] ------------ t831 = LCL_VAR long V31 tmp17 u:1 r11 REG r11 $342 /--* t831 long Generating: N231 (???,???) [001464] ------------ t1464 = * PUTARG_REG long REG r11 Generating: N233 ( 1, 1) [000500] ------------ t500 = LCL_VAR ref V01 arg1 u:1 rdi REG rdi $101 /--* t500 ref Generating: N235 (???,???) [001465] ------------ t1465 = * PUTARG_REG ref REG rdx IN002a: mov rdx, rdi GC regs: 0000D0E2 {rcx rbp rsi rdi r12 r14 r15} => 0000D0E6 {rcx rdx rbp rsi rdi r12 r14 r15} Generating: N237 ( 1, 1) [000521] ------------ t521 = LCL_VAR long V31 tmp17 u:1 r11 (last use) REG r11 $342 /--* t521 long Generating: N239 (???,???) [001466] Dc---------- t1466 = * IND long REG NA /--* t1463 ref this in rcx +--* t1464 long arg1 in r11 +--* t1465 ref arg2 in rdx +--* t1466 long calli tgt Generating: N241 ( 27, 12) [000522] --CXG------- t522 = * CALL ind stub int REG rax $1c7 GC regs: 0000D0E6 {rcx rdx rbp rsi rdi r12 r14 r15} => 0000D0E4 {rdx rbp rsi rdi r12 r14 r15} GC regs: 0000D0E4 {rdx rbp rsi rdi r12 r14 r15} => 0000D0E0 {rbp rsi rdi r12 r14 r15} V31 in reg r11 is becoming dead [000521] Live regs: 0000D8E8 {rbx rbp rsi rdi r11 r12 r14 r15} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V31 V73} => {V00 V01 V02 V03 V04 V05 V73} Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} IN002b: call qword ptr [r11] /--* t522 int Generating: N243 ( 31, 15) [000524] DA-XG------- * STORE_LCL_VAR int V15 tmp1 d:3 r13 REG r13 IN002c: mov r13d, eax V15 in reg r13 is becoming live [000524] Live regs: 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V73} => {V00 V01 V02 V03 V04 V05 V15 V73} IN002d: jmp L_M38507_BB14 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 12 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG08,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 12 =============== Generating BB13 [054..061), preds={BB08} succs={BB14} flags=0x00000002.20090020: i label hascall gcsafe LIR BB13 IN (7)={V04 V00 V01 V73 V05 V03 V02 } + ByrefExposed + GcHeap OUT(8)={V04 V00 V01 V73 V05 V03 V02 V15} + ByrefExposed + GcHeap Recording Var Locations at start of BB13 V04(r15) V00(rsi) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) Change life 00000000000000000000100000070614 {V00 V01 V02 V03 V04 V05 V15 V73} -> 00000000000000000000000000070614 {V00 V01 V02 V03 V04 V05 V73} V15 in reg r13 is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} GC regs: 00000000 {} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB13: G_M38507_IG12: ; offs=0000AEH, funclet=00, bbWeight=0.50 Mapped BB13 to G_M38507_IG13 Label: IG13, GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB13, IL range [054..061) Added IP mapping: 0x0054 STACK_EMPTY (G_M38507_IG13,ins#0,ofs#0) label Generating: N247 (???,???) [001347] ------------ IL_OFFSET void IL offset: 0x54 REG NA Generating: N249 ( 1, 1) [000033] ------------ t33 = LCL_VAR ref V01 arg1 u:1 rdi REG rdi $101 /--* t33 ref Generating: N251 (???,???) [001467] ------------ t1467 = * PUTARG_REG ref REG rcx IN002e: mov rcx, rdi GC regs: 0000D0E0 {rbp rsi rdi r12 r14 r15} => 0000D0E2 {rcx rbp rsi rdi r12 r14 r15} Generating: N253 ( 1, 1) [000836] ------------ t836 = LCL_VAR ref V01 arg1 u:1 rdi REG rdi $101 /--* t836 ref Generating: N255 ( 3, 2) [000837] #----O------ t837 = * IND long REG rax $2e4 IN002f: mov rax, qword ptr [rdi] /--* t837 long Generating: N257 ( 4, 3) [000839] -c---------- t839 = * LEA(b+72) long REG NA /--* t839 long Generating: N259 ( 6, 5) [000840] #----O------ t840 = * IND long REG rax $2e6 IN0030: mov rax, qword ptr [rax+72] /--* t840 long Generating: N261 ( 7, 6) [000842] -c---------- t842 = * LEA(b+24) long REG NA /--* t842 long Generating: N263 ( 9, 8) [000843] nc---O------ t843 = * IND long REG NA /--* t1467 ref this in rcx +--* t843 long control expr Generating: N265 ( 30, 18) [000035] --CXGO------ t35 = * CALLV vt-ind int System.Object.GetHashCode REG rax $1c5 GC regs: 0000D0E2 {rcx rbp rsi rdi r12 r14 r15} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} IN0031: call qword ptr [rax+24]System.Object:GetHashCode():int:this /--* t35 int Generating: N267 ( 34, 21) [000038] DA-XGO------ * STORE_LCL_VAR int V15 tmp1 d:2 r13 REG r13 IN0032: mov r13d, eax V15 in reg r13 is becoming live [000038] Live regs: 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V73} => {V00 V01 V02 V03 V04 V05 V15 V73} //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 13 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG08,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 13 =============== Generating BB14 [061..07A) -> BB16 (cond), preds={BB12,BB13} succs={BB15,BB16} flags=0x00000000.20190020: i label gcsafe idxlen LIR BB14 IN (8)={ V04 V00 V01 V73 V05 V03 V02 V15} + ByrefExposed + GcHeap OUT(13)={V07 V04 V00 V06 V01 V73 V40 V05 V03 V02 V39 V45 V41 } + ByrefExposed + GcHeap Recording Var Locations at start of BB14 V04(r15) V00(rsi) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) V15(r13) Liveness not changing: 00000000000000000000100000070614 {V00 V01 V02 V03 V04 V05 V15 V73} Live regs: 00000000 {} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB14: G_M38507_IG13: ; offs=0000BFH, funclet=00, bbWeight=0.50 Mapped BB14 to G_M38507_IG14 Label: IG14, GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB14, IL range [061..07A) Generating: N271 ( 3, 2) [000040] ------------ t40 = LCL_VAR int V15 tmp1 u:1 r13 (last use) REG r13 $3c0 /--* t40 int Generating: N273 ( 3, 3) [000042] DA---------- * STORE_LCL_VAR int V06 loc2 d:1 r13 REG r13 V15 in reg r13 is becoming dead [000040] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V15 V73} => {V00 V01 V02 V03 V04 V05 V73} V06 in reg r13 is becoming live [000042] Live regs: 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V73} => {V00 V01 V02 V03 V04 V05 V06 V73} New debug range: first Added IP mapping: 0x0062 STACK_EMPTY (G_M38507_IG14,ins#0,ofs#0) label Generating: N275 (???,???) [001348] ------------ IL_OFFSET void IL offset: 0x62 REG NA Generating: N277 ( 1, 1) [000043] ------------ t43 = CNS_INT int 0 REG rax $c0 IN0033: xor eax, eax /--* t43 int Generating: N279 ( 1, 3) [000045] DA---------- * STORE_LCL_VAR int V07 loc3 d:1 NA REG NA IN0034: mov dword ptr [V07 rsp+8CH], eax Live vars: {V00 V01 V02 V03 V04 V05 V06 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V73} New debug range: first Added IP mapping: 0x0064 STACK_EMPTY (G_M38507_IG14,ins#2,ofs#9) Generating: N281 (???,???) [001349] ------------ IL_OFFSET void IL offset: 0x64 REG NA Generating: N283 ( 1, 1) [000046] ------------ t46 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t46 ref Generating: N285 ( 2, 2) [000845] -c---------- t845 = * LEA(b+8) byref REG NA /--* t845 byref Generating: N287 ( 4, 4) [000578] n---GO------ t578 = * IND ref REG r8 IN0035: mov r8, gword ptr [rsi+8] GC regs: 0000D0E0 {rbp rsi rdi r12 r14 r15} => 0000D1E0 {rbp rsi rdi r8 r12 r14 r15} /--* t578 ref Generating: N289 ( 4, 4) [000580] DA--GO------ * STORE_LCL_VAR ref V39 tmp25 d:1 r8 REG r8 GC regs: 0000D1E0 {rbp rsi rdi r8 r12 r14 r15} => 0000D0E0 {rbp rsi rdi r12 r14 r15} V39 in reg r8 is becoming live [000580] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F1E8 {rbx rbp rsi rdi r8 r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V73} GC regs: 0000D0E0 {rbp rsi rdi r12 r14 r15} => 0000D1E0 {rbp rsi rdi r8 r12 r14 r15} genIPmappingAdd: ignoring duplicate IL offset 0x64 Generating: N291 (???,???) [001350] ------------ IL_OFFSET void IL offset: 0x64 REG NA Generating: N293 ( 1, 1) [000582] -----------Z t582 = LCL_VAR ref V39 tmp25 u:1 r8 REG r8 /--* t582 ref Generating: N295 (???,???) [001441] -c---------- t1441 = * LEA(b+8) ref REG NA /--* t1441 ref Generating: N297 ( 3, 3) [000583] ---X-------- t583 = * IND int REG r9 IN0036: mov gword ptr [V39 rsp+38H], r8 V39 in reg r8 is becoming dead [000582] Live regs: 0000F1E8 {rbx rbp rsi rdi r8 r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 0000D1E0 {rbp rsi rdi r8 r12 r14 r15} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Var V39 becoming live IN0037: mov r9d, dword ptr [r8+8] /--* t583 int Generating: N299 ( 3, 3) [000629] DA-X-------- * STORE_LCL_VAR int V40 tmp26 d:1 r9 REG r9 V40 in reg r9 is becoming live [000629] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F2E8 {rbx rbp rsi rdi r9 r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V73} genIPmappingAdd: ignoring duplicate IL offset 0x64 Generating: N301 (???,???) [001351] ------------ IL_OFFSET void IL offset: 0x64 REG NA Generating: N303 ( 1, 1) [000584] ------------ t584 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t584 ref Generating: N305 ( 2, 2) [000847] -c---------- t847 = * LEA(b+48) byref REG NA /--* t847 byref Generating: N307 ( 4, 4) [000585] n---GO------ t585 = * IND long REG r10 IN0038: mov r10, qword ptr [rsi+48] /--* t585 long Generating: N309 ( 4, 4) [000631] DA--GO------ * STORE_LCL_VAR long V41 tmp27 d:1 NA REG NA IN0039: mov qword ptr [V41 rsp+78H], r10 Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V73} genIPmappingAdd: ignoring duplicate IL offset 0x64 Generating: N311 (???,???) [001352] ------------ IL_OFFSET void IL offset: 0x64 REG NA Generating: N313 ( 1, 1) [000597] -----------Z t597 = LCL_VAR int V40 tmp26 u:1 r9 REG r9 Generating: N315 ( 1, 4) [000598] -c---------- t598 = CNS_INT int 0x7FFFFFFF REG NA $ce /--* t597 int +--* t598 int Generating: N317 ( 6, 6) [000599] N--------U-- t599 = * LE int REG rcx IN003a: mov dword ptr [V40 rsp+84H], r9d V40 in reg r9 is becoming dead [000597] Live regs: 0000F2E8 {rbx rbp rsi rdi r9 r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} IN003b: cmp r9d, 0xD1FFAB1E IN003c: setbe cl IN003d: movzx rcx, cl /--* t599 int Generating: N319 ( 6, 6) [000642] DA---------- * STORE_LCL_VAR int V43 tmp29 d:1 rcx REG rcx V43 in reg rcx is becoming live [000642] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V43 V73} genIPmappingAdd: ignoring duplicate IL offset 0x64 Generating: N321 (???,???) [001353] ------------ IL_OFFSET void IL offset: 0x64 REG NA genIPmappingAdd: ignoring duplicate IL offset 0x64 Generating: N323 (???,???) [001354] ------------ IL_OFFSET void IL offset: 0x64 REG NA Generating: N325 ( 1, 1) [001297] ------------ t1297 = LCL_VAR ref V73 cse8 u:1 r14 REG r14 $105 /--* t1297 ref Generating: N327 ( 1, 3) [000654] DA--G------- * STORE_LCL_VAR ref V45 tmp31 d:1 rdx REG rdx IN003e: mov rdx, r14 V45 in reg rdx is becoming live [000654] Live regs: 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EE {rcx rdx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V43 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V43 V45 V73} GC regs: 0000D0E0 {rbp rsi rdi r12 r14 r15} => 0000D0E4 {rdx rbp rsi rdi r12 r14 r15} genIPmappingAdd: ignoring duplicate IL offset 0x64 Generating: N329 (???,???) [001355] ------------ IL_OFFSET void IL offset: 0x64 REG NA Generating: N331 ( 1, 1) [000644] ------------ t644 = LCL_VAR int V43 tmp29 u:1 rcx (last use) REG rcx Generating: N333 ( 1, 1) [000645] -c---------- t645 = CNS_INT int 0 REG NA $c0 /--* t644 int +--* t645 int Generating: N335 ( 3, 3) [000646] J------N---- * NE void REG NA V43 in reg rcx is becoming dead [000644] Live regs: 0000F0EE {rcx rdx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EC {rdx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V43 V45 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V45 V73} IN003f: test ecx, ecx Generating: N337 ( 5, 5) [000647] ------------ * JTRUE void REG NA IN0040: jne L_M38507_BB16 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 14 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG08,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG14,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG14,ins#2,ofs#9), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 14 =============== Generating BB15 [064..065), preds={BB14} succs={BB16} flags=0x00000002.20080020: i hascall gcsafe LIR BB15 IN (13)={V07 V04 V00 V06 V01 V73 V40 V05 V03 V02 V39 V45 V41} + ByrefExposed + GcHeap OUT(12)={V07 V04 V00 V06 V01 V73 V40 V05 V03 V02 V39 V41} + ByrefExposed + GcHeap Recording Var Locations at start of BB15 V04(r15) V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) V45(rdx) Liveness not changing: 00000000000000000000000022274636 {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V45 V73} Live regs: 00000000 {} => 0000F0EC {rdx rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E4 {rdx rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB15: Adding label due to BB weight difference: BBJ_COND BB14 with weight 100 different from BB15 with weight 50 G_M38507_IG14: ; offs=0000CFH, funclet=00, bbWeight=1 Mapped BB15 to G_M38507_IG15 Label: IG15, GCvars=00000000000000000000000000200000 {V39}, gcrefRegs=0000D0E4 {rdx rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB15, IL range [064..065) genIPmappingAdd: ignoring duplicate IL offset 0x64 Generating: N341 (???,???) [001356] ------------ IL_OFFSET void IL offset: 0x64 REG NA Generating: N343 ( 1, 1) [000648] ------------ t648 = LCL_VAR ref V45 tmp31 u:1 rdx REG rdx $105 /--* t648 ref Generating: N345 (???,???) [001468] ------------ t1468 = * PUTARG_REG ref REG rcx IN0041: mov rcx, rdx GC regs: 0000D0E4 {rdx rbp rsi rdi r12 r14 r15} => 0000D0E6 {rcx rdx rbp rsi rdi r12 r14 r15} Generating: N347 ( 1, 1) [000649] ------------ t649 = LCL_VAR ref V45 tmp31 u:1 rdx (last use) REG rdx $105 /--* t649 ref Generating: N349 (???,???) [001469] ------------ t1469 = * PUTARG_REG ref REG rdx V45 in reg rdx is becoming dead [000649] Live regs: 0000F0EC {rdx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V45 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V73} GC regs: 0000D0E6 {rcx rdx rbp rsi rdi r12 r14 r15} => 0000D0E2 {rcx rbp rsi rdi r12 r14 r15} GC regs: 0000D0E2 {rcx rbp rsi rdi r12 r14 r15} => 0000D0E6 {rcx rdx rbp rsi rdi r12 r14 r15} /--* t1468 ref arg0 in rcx +--* t1469 ref arg1 in rdx Generating: N351 ( 16, 9) [000650] --CXG------- * CALL void System.Diagnostics.Debug.Fail REG NA $VN.Void GC regs: 0000D0E6 {rcx rdx rbp rsi rdi r12 r14 r15} => 0000D0E4 {rdx rbp rsi rdi r12 r14 r15} GC regs: 0000D0E4 {rdx rbp rsi rdi r12 r14 r15} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Call: GCvars=00000000000000000000000000200000 {V39}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} IN0042: call System.Diagnostics.Debug:Fail(System.String,System.String) //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 15 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG08,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG14,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG14,ins#2,ofs#9), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 15 =============== Generating BB16 [064..065) -> BB18 (cond), preds={BB14,BB15} succs={BB17,BB18} flags=0x00000000.20190020: i label gcsafe idxlen LIR BB16 IN (12)={V07 V04 V00 V06 V01 V73 V40 V05 V03 V02 V39 V41} + ByrefExposed + GcHeap OUT(12)={V07 V04 V00 V06 V01 V73 V05 V03 V02 V39 V42 V48 } + ByrefExposed + GcHeap Recording Var Locations at start of BB16 V04(r15) V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) Liveness not changing: 00000000000000000000000020274636 {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V73} Live regs: 00000000 {} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB16: G_M38507_IG15: ; offs=00010EH, funclet=00, bbWeight=0.50 Mapped BB16 to G_M38507_IG16 Label: IG16, GCvars=00000000000000000000000000200000 {V39}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB16, IL range [064..065) genIPmappingAdd: ignoring duplicate IL offset 0x64 Generating: N355 (???,???) [001357] ------------ IL_OFFSET void IL offset: 0x64 REG NA Generating: N357 ( 1, 1) [000604] -c---------- t604 = LCL_VAR long V41 tmp27 u:1 NA (last use) REG NA Generating: N359 ( 1, 1) [000047] ------------ t47 = LCL_VAR int V06 loc2 u:1 r13 REG r13 $3c0 /--* t47 int Generating: N361 ( 2, 3) [000605] ---------U-- t605 = * CAST long <- ulong <- uint REG rdx $310 IN0043: mov edx, r13d /--* t604 long +--* t605 long Generating: N363 ( 7, 7) [000606] ------------ t606 = * MUL long REG rdx Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V41 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V73} IN0044: imul rdx, qword ptr [V41 rsp+78H] Generating: N365 ( 1, 1) [000607] -c---------- t607 = CNS_INT int 32 REG NA $d2 /--* t606 long +--* t607 int Generating: N367 ( 9, 9) [000608] ------------ t608 = * RSZ long REG rdx IN0045: shr rdx, 32 Generating: N369 ( 1, 1) [000610] -c---------- t610 = CNS_INT long 1 REG NA $247 /--* t608 long +--* t610 long Generating: N371 ( 11, 11) [000611] ------------ t611 = * ADD long REG rdx IN0046: inc rdx Generating: N373 ( 1, 1) [000612] -----------z t612 = LCL_VAR int V40 tmp26 u:1 r9 REG r9 /--* t612 int Generating: N375 ( 2, 3) [000613] ---------U-- t613 = * CAST long <- ulong <- uint REG rcx IN0047: mov r9d, dword ptr [V40 rsp+84H] V40 in reg r9 is becoming live [000612] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F2E8 {rbx rbp rsi rdi r9 r12 r13 r14 r15} IN0048: mov ecx, r9d /--* t611 long +--* t613 long Generating: N377 ( 17, 17) [000614] ------------ t614 = * MUL long REG rdx IN0049: imul rdx, rcx Generating: N379 ( 1, 1) [000615] -c---------- t615 = CNS_INT int 32 REG NA $d2 /--* t614 long +--* t615 int Generating: N381 ( 19, 19) [000616] ------------ t616 = * RSZ long REG rdx IN004a: shr rdx, 32 /--* t616 long Generating: N383 ( 20, 21) [000617] ------------ t617 = * CAST int <- uint <- long REG r10 IN004b: mov r10d, edx /--* t617 int Generating: N385 ( 20, 21) [000619] DA---------- * STORE_LCL_VAR int V42 tmp28 d:1 r10 REG r10 V42 in reg r10 is becoming live [000619] Live regs: 0000F2E8 {rbx rbp rsi rdi r9 r12 r13 r14 r15} => 0000F6E8 {rbx rbp rsi rdi r9 r10 r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V42 V73} genIPmappingAdd: ignoring duplicate IL offset 0x64 Generating: N387 (???,???) [001358] ------------ IL_OFFSET void IL offset: 0x64 REG NA Generating: N389 ( 1, 1) [000621] ------------ t621 = LCL_VAR int V06 loc2 u:1 r13 REG r13 $3c0 Generating: N391 ( 1, 1) [000622] ------------ t622 = LCL_VAR int V40 tmp26 u:1 r9 (last use) REG r9 /--* t621 int +--* t622 int Generating: N393 ( 22, 5) [000623] ---X-------- t623 = * UMOD int REG rdx V40 in reg r9 is becoming dead [000622] Live regs: 0000F6E8 {rbx rbp rsi rdi r9 r10 r12 r13 r14 r15} => 0000F4E8 {rbx rbp rsi rdi r10 r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V40 V42 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V73} IN004c: mov eax, r13d IN004d: xor rdx, rdx IN004e: div edx:eax, r9d Generating: N395 ( 1, 1) [000620] -----------Z t620 = LCL_VAR int V42 tmp28 u:1 r10 REG r10 /--* t623 int +--* t620 int Generating: N397 ( 27, 7) [000624] ---X-------- t624 = * EQ int REG rcx IN004f: mov dword ptr [V42 rsp+74H], r10d V42 in reg r10 is becoming dead [000620] Live regs: 0000F4E8 {rbx rbp rsi rdi r10 r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} IN0050: cmp edx, r10d IN0051: sete cl IN0052: movzx rcx, cl /--* t624 int Generating: N399 ( 27, 7) [000665] DA-X-------- * STORE_LCL_VAR int V46 tmp32 d:1 rcx REG rcx V46 in reg rcx is becoming live [000665] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V46 V73} genIPmappingAdd: ignoring duplicate IL offset 0x64 Generating: N401 (???,???) [001359] ------------ IL_OFFSET void IL offset: 0x64 REG NA genIPmappingAdd: ignoring duplicate IL offset 0x64 Generating: N403 (???,???) [001360] ------------ IL_OFFSET void IL offset: 0x64 REG NA Generating: N405 ( 1, 1) [001299] ------------ t1299 = LCL_VAR ref V73 cse8 u:1 r14 REG r14 $105 /--* t1299 ref Generating: N407 ( 1, 3) [000677] DA--G------- * STORE_LCL_VAR ref V48 tmp34 d:1 rdx REG rdx IN0053: mov rdx, r14 V48 in reg rdx is becoming live [000677] Live regs: 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EE {rcx rdx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V46 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V46 V48 V73} GC regs: 0000D0E0 {rbp rsi rdi r12 r14 r15} => 0000D0E4 {rdx rbp rsi rdi r12 r14 r15} genIPmappingAdd: ignoring duplicate IL offset 0x64 Generating: N409 (???,???) [001361] ------------ IL_OFFSET void IL offset: 0x64 REG NA Generating: N411 ( 1, 1) [000667] ------------ t667 = LCL_VAR int V46 tmp32 u:1 rcx (last use) REG rcx Generating: N413 ( 1, 1) [000668] -c---------- t668 = CNS_INT int 0 REG NA $c0 /--* t667 int +--* t668 int Generating: N415 ( 3, 3) [000669] J------N---- * NE void REG NA V46 in reg rcx is becoming dead [000667] Live regs: 0000F0EE {rcx rdx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EC {rdx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V46 V48 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V48 V73} IN0054: test ecx, ecx Generating: N417 ( 5, 5) [000670] ------------ * JTRUE void REG NA IN0055: jne L_M38507_BB18 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 16 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG08,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG14,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG14,ins#2,ofs#9), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 16 =============== Generating BB17 [064..065), preds={BB16} succs={BB18} flags=0x00000002.20080020: i hascall gcsafe LIR BB17 IN (12)={V07 V04 V00 V06 V01 V73 V05 V03 V02 V39 V42 V48} + ByrefExposed + GcHeap OUT(11)={V07 V04 V00 V06 V01 V73 V05 V03 V02 V39 V42 } + ByrefExposed + GcHeap Recording Var Locations at start of BB17 V04(r15) V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) V48(rdx) Liveness not changing: 00000000000000000000000004670636 {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V48 V73} Live regs: 00000000 {} => 0000F0EC {rdx rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E4 {rdx rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB17: Adding label due to BB weight difference: BBJ_COND BB16 with weight 100 different from BB17 with weight 50 G_M38507_IG16: ; offs=000116H, funclet=00, bbWeight=1 Mapped BB17 to G_M38507_IG17 Label: IG17, GCvars=00000000000000000000000000200000 {V39}, gcrefRegs=0000D0E4 {rdx rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB17, IL range [064..065) genIPmappingAdd: ignoring duplicate IL offset 0x64 Generating: N421 (???,???) [001362] ------------ IL_OFFSET void IL offset: 0x64 REG NA Generating: N423 ( 1, 1) [000671] ------------ t671 = LCL_VAR ref V48 tmp34 u:1 rdx REG rdx $105 /--* t671 ref Generating: N425 (???,???) [001470] ------------ t1470 = * PUTARG_REG ref REG rcx IN0056: mov rcx, rdx GC regs: 0000D0E4 {rdx rbp rsi rdi r12 r14 r15} => 0000D0E6 {rcx rdx rbp rsi rdi r12 r14 r15} Generating: N427 ( 1, 1) [000672] ------------ t672 = LCL_VAR ref V48 tmp34 u:1 rdx (last use) REG rdx $105 /--* t672 ref Generating: N429 (???,???) [001471] ------------ t1471 = * PUTARG_REG ref REG rdx V48 in reg rdx is becoming dead [000672] Live regs: 0000F0EC {rdx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V48 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V73} GC regs: 0000D0E6 {rcx rdx rbp rsi rdi r12 r14 r15} => 0000D0E2 {rcx rbp rsi rdi r12 r14 r15} GC regs: 0000D0E2 {rcx rbp rsi rdi r12 r14 r15} => 0000D0E6 {rcx rdx rbp rsi rdi r12 r14 r15} /--* t1470 ref arg0 in rcx +--* t1471 ref arg1 in rdx Generating: N431 ( 16, 9) [000673] --CXG------- * CALL void System.Diagnostics.Debug.Fail REG NA $VN.Void GC regs: 0000D0E6 {rcx rdx rbp rsi rdi r12 r14 r15} => 0000D0E4 {rdx rbp rsi rdi r12 r14 r15} GC regs: 0000D0E4 {rdx rbp rsi rdi r12 r14 r15} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Call: GCvars=00000000000000000000000000200000 {V39}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} IN0057: call System.Diagnostics.Debug:Fail(System.String,System.String) //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 17 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG08,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG14,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG14,ins#2,ofs#9), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 17 =============== Generating BB18 [064..065) -> BB32 (cond), preds={BB16,BB17} succs={BB19,BB32} flags=0x00000000.20190020: i label gcsafe idxlen LIR BB18 IN (11)={V07 V04 V00 V06 V01 V73 V05 V03 V02 V39 V42 } + ByrefExposed + GcHeap OUT(11)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08} + ByrefExposed + GcHeap Recording Var Locations at start of BB18 V04(r15) V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) Liveness not changing: 00000000000000000000000000670636 {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V73} Live regs: 00000000 {} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB18: G_M38507_IG17: ; offs=00015DH, funclet=00, bbWeight=0.50 Mapped BB18 to G_M38507_IG18 Label: IG18, GCvars=00000000000000000000000000200000 {V39}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB18, IL range [064..065) genIPmappingAdd: ignoring duplicate IL offset 0x64 Generating: N435 (???,???) [001363] ------------ IL_OFFSET void IL offset: 0x64 REG NA Generating: N437 ( 1, 1) [000627] -----------z t627 = LCL_VAR int V42 tmp28 u:1 r10 REG r10 Generating: N439 ( 1, 1) [000581] -----------z t581 = LCL_VAR ref V39 tmp25 u:1 r8 REG r8 /--* t581 ref Generating: N441 (???,???) [001443] -c---------- t1443 = * LEA(b+8) ref REG NA /--* t1443 ref Generating: N443 ( 3, 3) [000854] -c-X-------- t854 = * IND int REG NA /--* t627 int +--* t854 int Generating: N445 ( 8, 11) [000855] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void REG NA IN0058: mov r10d, dword ptr [V42 rsp+74H] V42 in reg r10 is becoming live [000627] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F4E8 {rbx rbp rsi rdi r10 r12 r13 r14 r15} IN0059: mov r8, gword ptr [V39 rsp+38H] Removing V39 from gcVarPtrSetCur V39 in reg r8 is becoming live [000581] Live regs: 0000F4E8 {rbx rbp rsi rdi r10 r12 r13 r14 r15} => 0000F5E8 {rbx rbp rsi rdi r8 r10 r12 r13 r14 r15} GC regs: 0000D0E0 {rbp rsi rdi r12 r14 r15} => 0000D1E0 {rbp rsi rdi r8 r12 r14 r15} IN005a: cmp r10d, dword ptr [r8+8] IN005b: jae L_M38507_BB69 Generating: N447 ( 1, 1) [000852] ------------ t852 = LCL_VAR ref V39 tmp25 u:1 r8 (last use) REG r8 Generating: N449 ( 1, 1) [000853] ------------ t853 = LCL_VAR int V42 tmp28 u:1 r10 (last use) REG r10 /--* t853 int Generating: N451 ( 2, 3) [000856] ------------ t856 = * CAST long <- int REG rcx V42 in reg r10 is becoming dead [000853] Live regs: 0000F5E8 {rbx rbp rsi rdi r8 r10 r12 r13 r14 r15} => 0000F1E8 {rbx rbp rsi rdi r8 r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V42 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V39 V73} IN005c: movsxd rcx, r10d /--* t852 ref +--* t856 long Generating: N453 ( 5, 6) [000861] -------N---- t861 = * LEA(b+(i*4)+16) byref REG rax V39 in reg r8 is becoming dead [000852] Live regs: 0000F1E8 {rbx rbp rsi rdi r8 r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V39 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V73} GC regs: 0000D1E0 {rbp rsi rdi r8 r12 r14 r15} => 0000D0E0 {rbp rsi rdi r12 r14 r15} IN005d: lea rax, bword ptr [r8+4*rcx+16] Byref regs: 00000000 {} => 00000001 {rax} /--* t861 byref Generating: N455 ( 19, 24) [000591] DA-XG------- * STORE_LCL_VAR byref V38 tmp24 d:1 rax REG rax Byref regs: 00000001 {rax} => 00000000 {} V38 in reg rax is becoming live [000591] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V38 V73} Byref regs: 00000000 {} => 00000001 {rax} Generating: N457 ( 1, 1) [000592] ------------ t592 = LCL_VAR byref V38 tmp24 u:1 rax (last use) REG rax $81 /--* t592 byref Generating: N459 ( 5, 4) [000051] DA---------- * STORE_LCL_VAR byref V08 loc4 d:1 rax REG rax V38 in reg rax is becoming dead [000592] Live regs: 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V38 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V73} Byref regs: 00000001 {rax} => 00000000 {} V08 in reg rax is becoming live [000051] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V73} New debug range: first Byref regs: 00000000 {} => 00000001 {rax} Added IP mapping: 0x006D STACK_EMPTY (G_M38507_IG18,ins#6,ofs#28) Generating: N461 (???,???) [001364] ------------ IL_OFFSET void IL offset: 0x6d REG NA Generating: N463 ( 1, 1) [000052] -----------Z t52 = LCL_VAR byref V08 loc4 u:1 rax REG rax $81 /--* t52 byref Generating: N465 ( 3, 2) [000053] *--XG------- t53 = * IND int REG r8 IN005e: mov bword ptr [V08 rsp+50H], rax V08 in reg rax is becoming dead [000052] Live regs: 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Byref regs: 00000001 {rax} => 00000000 {} Var V08 becoming live New debug range: not adjacent IN005f: mov r8d, dword ptr [rax] Generating: N467 ( 1, 1) [000054] -c---------- t54 = CNS_INT int -1 REG NA $c4 /--* t53 int +--* t54 int Generating: N469 ( 5, 4) [000055] ---XG------- t55 = * ADD int REG r8 IN0060: dec r8d /--* t55 int Generating: N471 ( 5, 4) [000057] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:1 NA REG NA IN0061: mov dword ptr [V09 rsp+88H], r8d Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} New debug range: first Added IP mapping: 0x0074 STACK_EMPTY (G_M38507_IG18,ins#10,ofs#47) Generating: N473 (???,???) [001365] ------------ IL_OFFSET void IL offset: 0x74 REG NA Generating: N475 ( 1, 1) [000058] ------------ t58 = LCL_VAR ref V05 loc1 u:1 r12 REG r12 Generating: N477 ( 1, 1) [000059] -c---------- t59 = CNS_INT ref null REG NA $VN.Null /--* t58 ref +--* t59 ref Generating: N479 ( 3, 3) [000060] J------N---- * NE void REG NA IN0062: test r12, r12 Generating: N481 ( 5, 5) [000061] ------------ * JTRUE void REG NA IN0063: jne L_M38507_BB32 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 18 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG08,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG14,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG14,ins#2,ofs#9), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rax [ (G_M38507_IG18,ins#6,ofs#28), (G_M38507_IG18,ins#7,ofs#33) ]; rsp'[80] (1 slot) [ (G_M38507_IG18,ins#7,ofs#33), NON_CLOSED_RANGE ]; ] IL Var Num 9: [rsp'[136] (1 slot) [ (G_M38507_IG18,ins#10,ofs#47), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 18 =============== Generating BB19 [07A..???) -> BB21 (cond), preds={BB18} succs={BB20,BB21} flags=0x00000002.20080020: i hascall gcsafe LIR BB19 IN (11)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08 } + ByrefExposed + GcHeap OUT(13)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08 V24 V69} + ByrefExposed + GcHeap Recording Var Locations at start of BB19 V04(r15) V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) Liveness not changing: 0000000000000000000000010007063E {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} Live regs: 00000000 {} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB19: Adding label due to BB weight difference: BBJ_COND BB18 with weight 100 different from BB19 with weight 50 G_M38507_IG18: ; offs=000165H, funclet=00, bbWeight=1 Mapped BB19 to G_M38507_IG19 Label: IG19, GCvars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB19, IL range [07A..???) Added IP mapping: 0x00FF STACK_EMPTY (G_M38507_IG19,ins#0,ofs#0) label Generating: N485 (???,???) [001366] ------------ IL_OFFSET void IL offset: 0xff REG NA Generating: N487 ( 1, 1) [000353] !----------- t353 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t353 ref Generating: N489 ( 3, 2) [000354] #----O------ t354 = * IND long REG rcx $2e8 IN0064: mov rcx, qword ptr [rsi] /--* t354 long Generating: N491 ( 3, 3) [000356] DA---O------ * STORE_LCL_VAR long V24 tmp10 d:1 rcx REG rcx V24 in reg rcx is becoming live [000356] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V24 V73} Generating: N493 ( 1, 1) [000358] ------------ t358 = LCL_VAR long V24 tmp10 u:1 rcx REG rcx $2e7 /--* t358 long Generating: N495 ( 2, 2) [000360] -c---------- t360 = * LEA(b+56) long REG NA /--* t360 long Generating: N497 ( 4, 4) [000361] #----------- t361 = * IND long REG rdx $2e9 IN0065: mov rdx, qword ptr [rcx+56] /--* t361 long Generating: N499 ( 7, 6) [000362] #----------- t362 = * IND long REG rdx $2ea IN0066: mov rdx, qword ptr [rdx] /--* t362 long Generating: N501 ( 8, 7) [000364] -c---------- t364 = * LEA(b+32) long REG NA /--* t364 long Generating: N503 ( 10, 9) [000365] n----------- t365 = * IND long REG rdx IN0067: mov rdx, qword ptr [rdx+32] /--* t365 long Generating: N505 ( 14, 12) [001271] DA---------- * STORE_LCL_VAR long V69 cse4 d:1 rdx REG rdx V69 in reg rdx is becoming live [001271] Live regs: 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EE {rcx rdx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V24 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V24 V69 V73} Generating: N507 ( 3, 2) [001272] ------------ t1272 = LCL_VAR long V69 cse4 u:1 rdx REG rdx Generating: N509 ( 1, 1) [000368] -c---------- t368 = CNS_INT long 0 REG NA $243 /--* t1272 long +--* t368 long Generating: N511 ( 19, 16) [000369] J------N---- * EQ void REG NA IN0068: test rdx, rdx Generating: N513 ( 21, 18) [001153] ------------ * JTRUE void REG NA IN0069: je L_M38507_BB21 Scope info: ignoring block end //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 19 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG08,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG14,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG14,ins#2,ofs#9), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG18,ins#7,ofs#33), NON_CLOSED_RANGE ]; ] IL Var Num 9: [rsp'[136] (1 slot) [ (G_M38507_IG18,ins#10,ofs#47), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 19 =============== Generating BB20 [???..???) -> BB22 (always), preds={BB19} succs={BB22} flags=0x00000000.20080020: i gcsafe LIR BB20 IN (12)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08 V69} + ByrefExposed + GcHeap OUT(12)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08 V25 } + ByrefExposed + GcHeap Recording Var Locations at start of BB20 V04(r15) V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) V69(rdx) Change life 0000000000000000400002010007063E {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V24 V69 V73} -> 0000000000000000400000010007063E {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V69 V73} V24 in reg rcx is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 0000F0EC {rdx rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB20: Adding label due to BB weight difference: BBJ_COND BB19 with weight 50 different from BB20 with weight 25 G_M38507_IG19: ; offs=00019DH, funclet=00, bbWeight=0.50 Mapped BB20 to G_M38507_IG20 Label: IG20, GCvars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB20, IL range [???..???) Scope info: ignoring block beginning Generating: N517 ( 3, 2) [001274] ------------ t1274 = LCL_VAR long V69 cse4 u:1 rdx (last use) REG rdx /--* t1274 long Generating: N519 ( 7, 5) [001155] DA---------- * STORE_LCL_VAR long V25 tmp11 d:3 rdx REG rdx V69 in reg rdx is becoming dead [001274] Live regs: 0000F0EC {rdx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V69 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} V25 in reg rdx is becoming live [001155] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EC {rdx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V25 V73} Scope info: ignoring block end IN006a: jmp L_M38507_BB22 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 20 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG08,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG14,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG14,ins#2,ofs#9), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG18,ins#7,ofs#33), NON_CLOSED_RANGE ]; ] IL Var Num 9: [rsp'[136] (1 slot) [ (G_M38507_IG18,ins#10,ofs#47), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 20 =============== Generating BB21 [???..???), preds={BB19} succs={BB22} flags=0x00000000.20090020: i label gcsafe LIR BB21 IN (12)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08 V24 } + ByrefExposed + GcHeap OUT(12)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08 V25} + ByrefExposed + GcHeap Recording Var Locations at start of BB21 V04(r15) V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) V24(rcx) Change life 0000000000000000000020010007063E {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V25 V73} -> 0000000000000000000002010007063E {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V24 V73} V25 in reg rdx is becoming dead [------] Live regs: (unchanged) 00000000 {} V24 in reg rcx is becoming live [------] Live regs: 00000000 {} => 00000002 {rcx} Live regs: 00000002 {rcx} => 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB21: G_M38507_IG20: ; offs=0001B4H, funclet=00, bbWeight=0.25 Mapped BB21 to G_M38507_IG21 Label: IG21, GCvars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB21, IL range [???..???) Scope info: ignoring block beginning Generating: N523 ( 1, 1) [000357] ------?----- t357 = LCL_VAR long V24 tmp10 u:1 rcx (last use) REG rcx $2e7 /--* t357 long Generating: N525 (???,???) [001472] ------------ t1472 = * PUTARG_REG long REG rcx V24 in reg rcx is becoming dead [000357] Live regs: 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V24 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} Generating: N527 ( 2, 10) [000366] H-----?----- t366 = CNS_INT(h) long 0xd1ffab1e global ptr REG rdx $4f IN006b: mov rdx, 0xD1FFAB1E /--* t366 long Generating: N529 (???,???) [001473] ------------ t1473 = * PUTARG_REG long REG rdx /--* t1472 long arg0 in rcx +--* t1473 long arg1 in rdx Generating: N531 ( 17, 18) [000367] --C-G-?----- t367 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS REG rax $325 Call: GCvars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} IN006c: call CORINFO_HELP_RUNTIMEHANDLE_CLASS /--* t367 long Generating: N533 ( 21, 21) [001157] DA--G------- * STORE_LCL_VAR long V25 tmp11 d:2 rdx REG rdx IN006d: mov rdx, rax V25 in reg rdx is becoming live [001157] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EC {rdx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V25 V73} Scope info: ignoring block end //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 21 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG08,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG14,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG14,ins#2,ofs#9), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG18,ins#7,ofs#33), NON_CLOSED_RANGE ]; ] IL Var Num 9: [rsp'[136] (1 slot) [ (G_M38507_IG18,ins#10,ofs#47), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 21 =============== Generating BB22 [???..106), preds={BB20,BB21} succs={BB23} flags=0x00000002.20090020: i label hascall gcsafe LIR BB22 IN (12)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08 V25} + ByrefExposed + GcHeap OUT(12)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V12 V08 } + ByrefExposed + GcHeap Recording Var Locations at start of BB22 V04(r15) V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) V25(rdx) Liveness not changing: 0000000000000000000020010007063E {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V25 V73} Live regs: 00000000 {} => 0000F0EC {rdx rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB22: G_M38507_IG21: ; offs=0001B9H, funclet=00, bbWeight=0.25 Mapped BB22 to G_M38507_IG22 Label: IG22, GCvars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB22, IL range [???..106) Scope info: ignoring block beginning Generating: N537 ( 3, 2) [000382] ------------ t382 = LCL_VAR long V25 tmp11 u:1 rdx (last use) REG rdx $344 /--* t382 long Generating: N539 (???,???) [001474] ------------ t1474 = * PUTARG_REG long REG rcx V25 in reg rdx is becoming dead [000382] Live regs: 0000F0EC {rdx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V25 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} IN006e: mov rcx, rdx /--* t1474 long arg0 in rcx Generating: N541 ( 17, 8) [000352] --CXG------- t352 = * CALL ref System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].get_Default REG rax $223 Call: GCvars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} IN006f: call System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon]:get_Default():System.Collections.Generic.EqualityComparer`1[__Canon] GC regs: 0000D0E0 {rbp rsi rdi r12 r14 r15} => 0000D0E1 {rax rbp rsi rdi r12 r14 r15} /--* t352 ref Generating: N543 ( 17, 8) [000386] DA-XG------- * STORE_LCL_VAR ref V12 loc8 d:1 rax REG rax GC regs: 0000D0E1 {rax rbp rsi rdi r12 r14 r15} => 0000D0E0 {rbp rsi rdi r12 r14 r15} V12 in reg rax is becoming live [000386] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73} New debug range: first GC regs: 0000D0E0 {rbp rsi rdi r12 r14 r15} => 0000D0E1 {rax rbp rsi rdi r12 r14 r15} //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 22 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG08,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG14,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG14,ins#2,ofs#9), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG18,ins#7,ofs#33), NON_CLOSED_RANGE ]; ] IL Var Num 9: [rsp'[136] (1 slot) [ (G_M38507_IG18,ins#10,ofs#47), NON_CLOSED_RANGE ]; ] IL Var Num 12: [rax [ (G_M38507_IG22,ins#2,ofs#8), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 22 =============== Generating BB23 [106..110) -> BB44 (cond), preds={BB22,BB27} succs={BB24,BB44} flags=0x00000008.21116020: i Loop Loop0 label idxlen bwd bwd-target LIR BB23 IN (12)={ V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap OUT(13)={V76 V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap Recording Var Locations at start of BB23 V04(r15) V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) V12(rax) Liveness not changing: 0000000000000000000000010017063E {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73} Live regs: 00000000 {} => 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E1 {rax rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB23: G_M38507_IG22: ; offs=0001CBH, funclet=00, bbWeight=0.50 Mapped BB23 to G_M38507_IG23 Label: IG23, GCvars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E1 {rax rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB23, IL range [106..110) Added IP mapping: 0x0106 STACK_EMPTY (G_M38507_IG23,ins#0,ofs#0) label Generating: N547 (???,???) [001367] ------------ IL_OFFSET void IL offset: 0x106 REG NA Generating: N549 ( 1, 1) [000388] ------------ t388 = LCL_VAR ref V04 loc0 u:1 r15 REG r15 /--* t388 ref Generating: N551 (???,???) [001446] -c---------- t1446 = * LEA(b+8) ref REG NA /--* t1446 ref Generating: N553 ( 3, 3) [000389] ---X-------- t389 = * IND int REG r9 IN0070: mov r9d, dword ptr [r15+8] /--* t389 int Generating: N555 ( 3, 3) [001316] DA-X-------- * STORE_LCL_VAR int V76 cse11 r9 REG r9 V76 in reg r9 is becoming live [001316] Live regs: 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} => 0000F2E9 {rax rbx rbp rsi rdi r9 r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73 V76} Generating: N557 ( 1, 1) [001317] -----------Z t1317 = LCL_VAR int V76 cse11 r9 REG r9 Generating: N559 ( 1, 1) [000387] -----------z t387 = LCL_VAR int V09 loc5 u:4 r10 REG r10 $3c2 /--* t1317 int +--* t387 int Generating: N561 ( 6, 6) [000390] N--X---N-U-- * LE void REG NA IN0071: mov dword ptr [V76 rsp+5CH], r9d V76 in reg r9 is becoming dead [001317] Live regs: 0000F2E9 {rax rbx rbp rsi rdi r9 r12 r13 r14 r15} => 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} IN0072: mov r10d, dword ptr [V09 rsp+88H] New debug range: not adjacent V09 in reg r10 is becoming live [000387] Live regs: 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} => 0000F4E9 {rax rbx rbp rsi rdi r10 r12 r13 r14 r15} IN0073: cmp r9d, r10d Generating: N563 ( 8, 8) [000391] ---X-------- * JTRUE void REG NA IN0074: jbe L_M38507_BB44 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 23 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG08,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG14,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG14,ins#2,ofs#9), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG18,ins#7,ofs#33), NON_CLOSED_RANGE ]; ] IL Var Num 9: [rsp'[136] (1 slot) [ (G_M38507_IG18,ins#10,ofs#47), (G_M38507_IG23,ins#3,ofs#17) ]; r10 [ (G_M38507_IG23,ins#3,ofs#17), NON_CLOSED_RANGE ]; ] IL Var Num 12: [rax [ (G_M38507_IG22,ins#2,ofs#8), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 23 =============== Generating BB24 [110..120) -> BB26 (cond), preds={BB23} succs={BB25,BB26} flags=0x00000000.21100020: i idxlen bwd LIR BB24 IN (13)={V76 V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap OUT(14)={V76 V07 V04 V00 V06 V65 V01 V73 V70 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap Recording Var Locations at start of BB24 V04(r15) V09(r10) V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) V12(rax) Liveness not changing: 0000000000000000000000010017063F {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73 V76} Live regs: 00000000 {} => 0000F4E9 {rax rbx rbp rsi rdi r10 r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E1 {rax rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB24: Scope info: begin block BB24, IL range [110..120) Added IP mapping: 0x0110 STACK_EMPTY (G_M38507_IG23,ins#5,ofs#26) label Generating: N567 (???,???) [001368] ------------ IL_OFFSET void IL offset: 0x110 REG NA Generating: N569 ( 1, 1) [000869] ------------ t869 = LCL_VAR ref V04 loc0 u:1 r15 REG r15 Generating: N571 ( 1, 1) [000870] ------------ t870 = LCL_VAR int V09 loc5 u:4 r10 (last use) REG r10 $3c2 /--* t870 int Generating: N573 ( 2, 3) [000873] ------------ t873 = * CAST long <- int REG rdx $326 V09 in reg r10 is becoming dead [000870] Live regs: 0000F4E9 {rax rbx rbp rsi rdi r10 r12 r13 r14 r15} => 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V73 V76} IN0075: movsxd rdx, r10d Generating: N575 ( 1, 1) [000880] -c---------- t880 = CNS_INT long 3 REG NA $24b /--* t873 long +--* t880 long Generating: N577 ( 7, 7) [000881] ------------ t881 = * MUL long REG rdx $327 IN0076: lea rdx, [rdx+2*rdx] /--* t881 long Generating: N579 ( 7, 7) [001276] DA---------- * STORE_LCL_VAR long V70 cse5 d:1 rdx REG rdx V70 in reg rdx is becoming live [001276] Live regs: 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0ED {rax rdx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V70 V73 V76} Generating: N581 ( 1, 1) [001277] ------------ t1277 = LCL_VAR long V70 cse5 u:1 rdx REG rdx $327 /--* t869 ref +--* t1277 long Generating: N583 ( 11, 11) [000878] -------N---- t878 = * LEA(b+(i*8)+16) byref REG r11 IN0077: lea r11, bword ptr [r15+8*rdx+16] Byref regs: 00000000 {} => 00000800 {r11} /--* t878 byref Generating: N585 ( 23, 23) [001249] DA--G------- * STORE_LCL_VAR byref V65 cse0 d:1 r11 REG r11 Byref regs: 00000800 {r11} => 00000000 {} V65 in reg r11 is becoming live [001249] Live regs: 0000F0ED {rax rdx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F8ED {rax rdx rbx rbp rsi rdi r11 r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V70 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V65 V70 V73 V76} Byref regs: 00000000 {} => 00000800 {r11} Generating: N587 ( 1, 1) [001250] -----------Z t1250 = LCL_VAR byref V65 cse0 u:1 r11 REG r11 /--* t1250 byref Generating: N589 ( 25, 25) [000868] -c---------- t868 = * LEA(b+16) byref REG NA /--* t868 byref Generating: N591 ( 27, 27) [000396] *c-XG------- t396 = * IND int REG NA Generating: N593 ( 1, 1) [000397] ------------ t397 = LCL_VAR int V06 loc2 u:1 r13 REG r13 $3c0 /--* t396 int +--* t397 int Generating: N595 ( 29, 29) [000398] N--XG--N-U-- * NE void REG NA IN0078: mov bword ptr [V65 rsp+30H], r11 V65 in reg r11 is becoming dead [001250] Live regs: 0000F8ED {rax rdx rbx rbp rsi rdi r11 r12 r13 r14 r15} => 0000F0ED {rax rdx rbx rbp rsi rdi r12 r13 r14 r15} Byref regs: 00000800 {r11} => 00000000 {} Var V65 becoming live IN0079: cmp dword ptr [r11+16], r13d Generating: N597 ( 31, 31) [000399] ---XG------- * JTRUE void REG NA IN007a: jne L_M38507_BB26 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 24 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG08,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG14,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG14,ins#2,ofs#9), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG18,ins#7,ofs#33), NON_CLOSED_RANGE ]; ] IL Var Num 9: [r10 [ (G_M38507_IG23,ins#3,ofs#17), (G_M38507_IG23,ins#5,ofs#26) ]; ] IL Var Num 12: [rax [ (G_M38507_IG22,ins#2,ofs#8), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 24 =============== Generating BB25 [120..137) -> BB28 (cond), preds={BB24} succs={BB26,BB28} flags=0x00000002.21180020: i hascall gcsafe idxlen bwd LIR BB25 IN (14)={V76 V07 V04 V00 V06 V65 V01 V73 V70 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap OUT(13)={V76 V07 V04 V00 V06 V65 V01 V73 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap Recording Var Locations at start of BB25 V04(r15) V00(rsi) V06(r13) V01(rdi) V73(r14) V70(rdx) V05(r12) V03(rbx) V02(rbp) V12(rax) Liveness not changing: 00000000000000000000000100171677 {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V65 V70 V73 V76} Live regs: 00000000 {} => 0000F0ED {rax rdx rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E1 {rax rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB25: Adding label due to BB weight difference: BBJ_COND BB24 with weight 400 different from BB25 with weight 200 G_M38507_IG23: ; offs=0001D3H, funclet=00, bbWeight=4 Mapped BB25 to G_M38507_IG24 Label: IG24, GCvars=00000000000000000000000100000040 {V08 V65}, gcrefRegs=0000D0E1 {rax rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB25, IL range [120..137) Added IP mapping: 0x0120 STACK_EMPTY (G_M38507_IG24,ins#0,ofs#0) label Generating: N601 (???,???) [001369] ------------ IL_OFFSET void IL offset: 0x120 REG NA Generating: N603 ( 1, 1) [000883] ------------ t883 = LCL_VAR ref V04 loc0 u:1 r15 REG r15 Generating: N605 ( 1, 1) [001279] ------------ t1279 = LCL_VAR long V70 cse5 u:1 rdx (last use) REG rdx $327 /--* t883 ref +--* t1279 long Generating: N607 ( 4, 4) [000892] -c---------- t892 = * LEA(b+(i*8)+16) byref REG NA /--* t892 byref Generating: N609 ( 12, 11) [000897] *---G--N---- t897 = * IND ref REG rdx V70 in reg rdx is becoming dead [001279] Live regs: 0000F0ED {rax rdx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V65 V70 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V65 V73 V76} IN007b: mov rdx, gword ptr [r15+8*rdx+16] GC regs: 0000D0E1 {rax rbp rsi rdi r12 r14 r15} => 0000D0E5 {rax rdx rbp rsi rdi r12 r14 r15} /--* t897 ref Generating: N611 (???,???) [001475] ----G------- t1475 = * PUTARG_REG ref REG rdx GC regs: 0000D0E5 {rax rdx rbp rsi rdi r12 r14 r15} => 0000D0E1 {rax rbp rsi rdi r12 r14 r15} GC regs: 0000D0E1 {rax rbp rsi rdi r12 r14 r15} => 0000D0E5 {rax rdx rbp rsi rdi r12 r14 r15} Generating: N613 ( 1, 1) [000418] ------------ t418 = LCL_VAR ref V12 loc8 u:1 rax REG rax $223 /--* t418 ref Generating: N615 (???,???) [001476] ------------ t1476 = * PUTARG_REG ref REG rcx IN007c: mov rcx, rax GC regs: 0000D0E5 {rax rdx rbp rsi rdi r12 r14 r15} => 0000D0E7 {rax rcx rdx rbp rsi rdi r12 r14 r15} Generating: N617 ( 1, 1) [000424] ------------ t424 = LCL_VAR ref V01 arg1 u:1 rdi REG rdi $101 /--* t424 ref Generating: N619 (???,???) [001477] ------------ t1477 = * PUTARG_REG ref REG r8 IN007d: mov r8, rdi GC regs: 0000D0E7 {rax rcx rdx rbp rsi rdi r12 r14 r15} => 0000D1E7 {rax rcx rdx rbp rsi rdi r8 r12 r14 r15} Generating: N621 ( 1, 1) [000901] -----------Z t901 = LCL_VAR ref V12 loc8 u:1 rax REG rax $223 /--* t901 ref Generating: N623 ( 3, 2) [000902] #--X-------- t902 = * IND long REG r10 $463 IN007e: mov gword ptr [V12 rsp+48H], rax V12 in reg rax is becoming dead [000901] Live regs: 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 0000D1E7 {rax rcx rdx rbp rsi rdi r8 r12 r14 r15} => 0000D1E6 {rcx rdx rbp rsi rdi r8 r12 r14 r15} Var V12 becoming live New debug range: not adjacent IN007f: mov r10, qword ptr [rax] /--* t902 long Generating: N625 ( 4, 3) [000904] -c---------- t904 = * LEA(b+72) long REG NA /--* t904 long Generating: N627 ( 6, 5) [000905] #--X-------- t905 = * IND long REG r10 $465 IN0080: mov r10, qword ptr [r10+72] /--* t905 long Generating: N629 ( 7, 6) [000907] -c---------- t907 = * LEA(b+32) long REG NA /--* t907 long Generating: N631 ( 9, 8) [000908] nc-X-------- t908 = * IND long REG NA /--* t1475 ref arg1 in rdx +--* t1476 ref this in rcx +--* t1477 ref arg2 in r8 +--* t908 long control expr Generating: N633 ( 43, 32) [000425] --CXG------- t425 = * CALLV vt-ind int System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon].Equals REG rax $581 GC regs: 0000D1E6 {rcx rdx rbp rsi rdi r8 r12 r14 r15} => 0000D1E2 {rcx rbp rsi rdi r8 r12 r14 r15} GC regs: 0000D1E2 {rcx rbp rsi rdi r8 r12 r14 r15} => 0000D1E0 {rbp rsi rdi r8 r12 r14 r15} GC regs: 0000D1E0 {rbp rsi rdi r8 r12 r14 r15} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Call: GCvars=00000000000000000000000100100040 {V08 V12 V65}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} IN0081: call qword ptr [r10+32]System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon]:Equals(System.__Canon,System.__Canon):bool:this Generating: N635 ( 1, 1) [000426] -c---------- t426 = CNS_INT int 0 REG NA $c0 /--* t425 int +--* t426 int Generating: N637 ( 45, 34) [000427] J--XG--N---- * NE void REG NA $1bd IN0082: test eax, eax Generating: N001 ( 1, 1) [001509] -----------z t1509 = LCL_VAR ref V12 loc8 rax REG rax IN0083: mov rax, gword ptr [V12 rsp+48H] New debug range: not adjacent Removing V12 from gcVarPtrSetCur V12 in reg rax is becoming live [001509] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 0000D0E0 {rbp rsi rdi r12 r14 r15} => 0000D0E1 {rax rbp rsi rdi r12 r14 r15} Generating: N639 ( 47, 36) [000428] ---XG------- * JTRUE void REG NA IN0084: jne L_M38507_BB28 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 25 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG08,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG14,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG14,ins#2,ofs#9), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG18,ins#7,ofs#33), NON_CLOSED_RANGE ]; ] IL Var Num 12: [rax [ (G_M38507_IG22,ins#2,ofs#8), (G_M38507_IG24,ins#4,ofs#16) ]; rsp'[72] (1 slot) [ (G_M38507_IG24,ins#4,ofs#16), (G_M38507_IG24,ins#9,ofs#34) ]; rax [ (G_M38507_IG24,ins#9,ofs#34), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 25 =============== Generating BB26 [157..170) -> BB68 (cond), preds={BB24,BB25} succs={BB27,BB68} flags=0x00000000.21110020: i label idxlen bwd LIR BB26 IN (13)={V76 V07 V04 V00 V06 V65 V01 V73 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap OUT(12)={ V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap Recording Var Locations at start of BB26 V04(r15) V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) V12(rax) Liveness not changing: 00000000000000000000000100170677 {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V65 V73 V76} Live regs: 00000000 {} => 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E1 {rax rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB26: Adding label due to BB weight difference: BBJ_COND BB25 with weight 200 different from BB26 with weight 400 G_M38507_IG24: ; offs=000208H, funclet=00, bbWeight=2 Mapped BB26 to G_M38507_IG25 Label: IG25, GCvars=00000000000000000000000100000040 {V08 V65}, gcrefRegs=0000D0E1 {rax rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB26, IL range [157..170) Added IP mapping: 0x0157 STACK_EMPTY (G_M38507_IG25,ins#0,ofs#0) label Generating: N643 (???,???) [001370] ------------ IL_OFFSET void IL offset: 0x157 REG NA Generating: N645 ( 1, 1) [001252] -----------z t1252 = LCL_VAR byref V65 cse0 u:1 r11 (last use) REG r11 $82 /--* t1252 byref Generating: N647 ( 2, 2) [000932] -c---------- t932 = * LEA(b+20) byref REG NA /--* t932 byref Generating: N649 ( 4, 4) [000404] *--XG------- t404 = * IND int REG r10 IN0085: mov r11, bword ptr [V65 rsp+30H] Removing V65 from gcVarPtrSetCur V65 in reg r11 is becoming live [001252] Live regs: 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} => 0000F8E9 {rax rbx rbp rsi rdi r11 r12 r13 r14 r15} Byref regs: 00000000 {} => 00000800 {r11} V65 in reg r11 is becoming dead [001252] Live regs: 0000F8E9 {rax rbx rbp rsi rdi r11 r12 r13 r14 r15} => 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V65 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V73 V76} Byref regs: 00000800 {r11} => 00000000 {} IN0086: mov r10d, dword ptr [r11+20] /--* t404 int Generating: N651 ( 4, 4) [000406] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:5 r8 REG r8 IN0087: mov r8d, r10d V09 in reg r8 is becoming live [000406] Live regs: 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} => 0000F1E9 {rax rbx rbp rsi rdi r8 r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V12 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73 V76} New debug range: not adjacent Added IP mapping: 0x0166 STACK_EMPTY (G_M38507_IG25,ins#3,ofs#12) Generating: N653 (???,???) [001371] ------------ IL_OFFSET void IL offset: 0x166 REG NA Generating: N655 ( 1, 1) [000407] -----------z t407 = LCL_VAR int V07 loc3 u:5 r11 (last use) REG r11 $3c1 Generating: N657 ( 1, 1) [000408] -c---------- t408 = CNS_INT int 1 REG NA $c1 /--* t407 int +--* t408 int Generating: N659 ( 3, 3) [000409] ------------ t409 = * ADD int REG r11 $605 IN0088: mov r11d, dword ptr [V07 rsp+8CH] V07 in reg r11 is becoming live [000407] Live regs: 0000F1E9 {rax rbx rbp rsi rdi r8 r12 r13 r14 r15} => 0000F9E9 {rax rbx rbp rsi rdi r8 r11 r12 r13 r14 r15} V07 in reg r11 is becoming dead [000407] Live regs: 0000F9E9 {rax rbx rbp rsi rdi r8 r11 r12 r13 r14 r15} => 0000F1E9 {rax rbx rbp rsi rdi r8 r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V08 V09 V12 V73 V76} IN0089: inc r11d /--* t409 int Generating: N661 ( 3, 3) [000411] DA---------- * STORE_LCL_VAR int V07 loc3 d:6 r11 REG r11 V07 in reg r11 is becoming live [000411] Live regs: 0000F1E9 {rax rbx rbp rsi rdi r8 r12 r13 r14 r15} => 0000F9E9 {rax rbx rbp rsi rdi r8 r11 r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V08 V09 V12 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73 V76} New debug range: not adjacent Added IP mapping: 0x016A STACK_EMPTY (G_M38507_IG25,ins#5,ofs#23) Generating: N663 (???,???) [001372] ------------ IL_OFFSET void IL offset: 0x16a REG NA Generating: N665 ( 1, 1) [001321] -c---------- t1321 = LCL_VAR int V76 cse11 NA (last use) REG NA Generating: N667 ( 1, 1) [000412] ------------ t412 = LCL_VAR int V07 loc3 u:6 r11 REG r11 $605 /--* t1321 int +--* t412 int Generating: N669 ( 3, 3) [000415] N------N-U-- * LT void REG NA Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73} IN008a: cmp dword ptr [V76 rsp+5CH], r11d Generating: N671 ( 5, 5) [000416] ------------ * JTRUE void REG NA IN008b: jb L_M38507_BB68 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 26 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG08,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG14,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG14,ins#2,ofs#9), (G_M38507_IG25,ins#4,ofs#20) ]; r11 [ (G_M38507_IG25,ins#5,ofs#23), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG18,ins#7,ofs#33), NON_CLOSED_RANGE ]; ] IL Var Num 9: [r8 [ (G_M38507_IG25,ins#3,ofs#12), NON_CLOSED_RANGE ]; ] IL Var Num 12: [rax [ (G_M38507_IG24,ins#9,ofs#34), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 26 =============== Generating BB27 [???..???) -> BB23 (always), preds={BB26} succs={BB23} flags=0x00000000.20000040: internal LIR BB27 IN (12)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap OUT(12)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V12 V08} + ByrefExposed + GcHeap Recording Var Locations at start of BB27 V07(r11) V04(r15) V09(r8) V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) V12(rax) Liveness not changing: 0000000000000000000000010017063E {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73} Live regs: 00000000 {} => 0000F9E9 {rax rbx rbp rsi rdi r8 r11 r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E1 {rax rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB27: Scope info: begin block BB27, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP STACK_EMPTY (G_M38507_IG25,ins#7,ofs#34) label Generating: N001 ( 1, 1) [001510] -----------Z t1510 = LCL_VAR int V07 loc3 r11 REG r11 IN008c: mov dword ptr [V07 rsp+8CH], r11d V07 in reg r11 is becoming dead [001510] Live regs: 0000F9E9 {rax rbx rbp rsi rdi r8 r11 r12 r13 r14 r15} => 0000F1E9 {rax rbx rbp rsi rdi r8 r12 r13 r14 r15} New debug range: not adjacent Generating: N001 ( 1, 1) [001511] -----------Z t1511 = LCL_VAR int V09 loc5 r8 REG r8 IN008d: mov dword ptr [V09 rsp+88H], r8d V09 in reg r8 is becoming dead [001511] Live regs: 0000F1E9 {rax rbx rbp rsi rdi r8 r12 r13 r14 r15} => 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} New debug range: not adjacent Scope info: ignoring block end IN008e: jmp L_M38507_BB23 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 27 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG08,ins#1,ofs#4), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG14,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 7: [r11 [ (G_M38507_IG25,ins#5,ofs#23), (G_M38507_IG25,ins#8,ofs#42) ]; rsp'[140] (1 slot) [ (G_M38507_IG25,ins#8,ofs#42), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG18,ins#7,ofs#33), NON_CLOSED_RANGE ]; ] IL Var Num 9: [r8 [ (G_M38507_IG25,ins#3,ofs#12), (G_M38507_IG25,ins#9,ofs#50) ]; rsp'[136] (1 slot) [ (G_M38507_IG25,ins#9,ofs#50), NON_CLOSED_RANGE ]; ] IL Var Num 12: [rax [ (G_M38507_IG24,ins#9,ofs#34), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 27 =============== Generating BB28 [137..13B) -> BB30 (cond), preds={BB25} succs={BB29,BB30} flags=0x00000000.21090020: i label gcsafe bwd LIR BB28 IN (5)={V00 V65 V01 V03 V02} + ByrefExposed + GcHeap OUT(5)={V00 V65 V01 V03 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB28 V00(rsi) V65(r11->STK) V01(rdi) V03(rbx) V02(rbp) Change life 0000000000000000000000010017063E {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V12 V73} -> 00000000000000000000000000060250 {V00 V01 V02 V03 V65} V04 in reg r15 is becoming dead [------] Live regs: (unchanged) 00000000 {} V06 in reg r13 is becoming dead [------] Live regs: (unchanged) 00000000 {} V73 in reg r14 is becoming dead [------] Live regs: (unchanged) 00000000 {} V05 in reg r12 is becoming dead [------] Live regs: (unchanged) 00000000 {} V12 in reg rax is becoming dead [------] Live regs: (unchanged) 00000000 {} V08 becoming dead V65 becoming live Live regs: 00000000 {} => 000000E8 {rbx rbp rsi rdi} GC regs: 00000000 {} => 000000E0 {rbp rsi rdi} Byref regs: (unchanged) 00000000 {} L_M38507_BB28: G_M38507_IG25: ; offs=000230H, funclet=00, bbWeight=4 Mapped BB28 to G_M38507_IG26 Label: IG26, GCvars=00000000000000000000000000000040 {V65}, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {} Scope info: begin block BB28, IL range [137..13B) Added IP mapping: 0x0137 STACK_EMPTY (G_M38507_IG26,ins#0,ofs#0) label Generating: N677 (???,???) [001373] ------------ IL_OFFSET void IL offset: 0x137 REG NA Generating: N679 ( 2, 2) [000429] ------------ t429 = LCL_VAR ubyte V03 arg3 u:1 rbx REG rbx $140 Generating: N681 ( 1, 1) [000430] -c---------- t430 = CNS_INT ubyte 1 REG NA $c1 /--* t429 ubyte +--* t430 ubyte Generating: N683 ( 5, 6) [000431] N------N-U-- * NE void REG NA $1bf IN008f: cmp bl, 1 Generating: N685 ( 7, 8) [000432] ------------ * JTRUE void REG NA IN0090: jne L_M38507_BB30 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 28 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG06,ins#1,ofs#4), (G_M38507_IG25,ins#10,ofs#55) ]; ] IL Var Num 5: [r12 [ (G_M38507_IG08,ins#1,ofs#4), (G_M38507_IG25,ins#10,ofs#55) ]; ] IL Var Num 6: [r13 [ (G_M38507_IG14,ins#0,ofs#0), (G_M38507_IG25,ins#10,ofs#55) ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG25,ins#8,ofs#42), (G_M38507_IG25,ins#10,ofs#55) ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG18,ins#7,ofs#33), (G_M38507_IG25,ins#10,ofs#55) ]; ] IL Var Num 9: [rsp'[136] (1 slot) [ (G_M38507_IG25,ins#9,ofs#50), (G_M38507_IG25,ins#10,ofs#55) ]; ] IL Var Num 12: [rax [ (G_M38507_IG24,ins#9,ofs#34), (G_M38507_IG25,ins#10,ofs#55) ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 28 =============== Generating BB29 [13B..14B) -> BB58 (always), preds={BB28} succs={BB58} flags=0x00000000.20180020: i gcsafe idxlen LIR BB29 IN (3)={V00 V65 V02} OUT(1)={V00 } Recording Var Locations at start of BB29 V00(rsi) V02(rbp) Change life 00000000000000000000000000060250 {V00 V01 V02 V03 V65} -> 00000000000000000000000000040050 {V00 V02 V65} V01 in reg rdi is becoming dead [------] Live regs: (unchanged) 00000000 {} V03 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 00000060 {rbp rsi} GC regs: 00000000 {} => 00000060 {rbp rsi} Byref regs: (unchanged) 00000000 {} L_M38507_BB29: Scope info: begin block BB29, IL range [13B..14B) Added IP mapping: 0x013B STACK_EMPTY (G_M38507_IG26,ins#2,ofs#9) label Generating: N689 (???,???) [001374] ------------ IL_OFFSET void IL offset: 0x13b REG NA Generating: N691 ( 1, 1) [001253] -----------z t1253 = LCL_VAR byref V65 cse0 u:1 r11 (last use) REG r11 $82 /--* t1253 byref Generating: N693 ( 2, 2) [000911] ------------ t911 = * LEA(b+8) byref REG rcx IN0091: mov r11, bword ptr [V65 rsp+30H] Removing V65 from gcVarPtrSetCur V65 in reg r11 is becoming live [001253] Live regs: 00000060 {rbp rsi} => 00000860 {rbp rsi r11} Byref regs: 00000000 {} => 00000800 {r11} V65 in reg r11 is becoming dead [001253] Live regs: 00000860 {rbp rsi r11} => 00000060 {rbp rsi} Live vars: {V00 V02 V65} => {V00 V02} Byref regs: 00000800 {r11} => 00000000 {} IN0092: lea rcx, bword ptr [r11+8] Byref regs: 00000000 {} => 00000002 {rcx} Generating: N695 ( 1, 1) [000479] ------------ t479 = LCL_VAR ref V02 arg2 u:1 rbp (last use) REG rbp $102 /--* t911 byref +--* t479 ref Generating: N697 (???,???) [001375] -A-XG------- * STOREIND ref REG NA Byref regs: 00000002 {rcx} => 00000000 {} V02 in reg rbp is becoming dead [000479] Live regs: 00000060 {rbp rsi} => 00000040 {rsi} Live vars: {V00 V02} => {V00} GC regs: 00000060 {rbp rsi} => 00000040 {rsi} IN0093: mov rdx, rbp NoGC Call: savedSet=0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} IN0094: call CORINFO_HELP_CHECKED_ASSIGN_REF IN0095: jmp L_M38507_BB58 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 29 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG02,ins#0,ofs#0), (G_M38507_IG26,ins#2,ofs#9) ]; ] IL Var Num 2: [rbp [ (G_M38507_IG02,ins#0,ofs#0), (G_M38507_IG26,ins#4,ofs#18) ]; ] IL Var Num 3: [rbx [ (G_M38507_IG02,ins#0,ofs#0), (G_M38507_IG26,ins#2,ofs#9) ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 29 =============== Generating BB30 [14B..14F) -> BB60 (cond), preds={BB28} succs={BB31,BB60} flags=0x00000000.21090020: i label gcsafe bwd LIR BB30 IN (3)={V00 V01 V03} + ByrefExposed + GcHeap OUT(2)={V00 V01 } + ByrefExposed + GcHeap Recording Var Locations at start of BB30 V00(rsi) V01(rdi) V03(rbx) Change life 00000000000000000000000000000010 {V00} -> 00000000000000000000000000020210 {V00 V01 V03} V01 in reg rdi is becoming live [------] Live regs: 00000000 {} => 00000080 {rdi} New debug range: new var or location V03 in reg rbx is becoming live [------] Live regs: 00000080 {rdi} => 00000088 {rbx rdi} New debug range: new var or location Live regs: 00000088 {rbx rdi} => 000000C8 {rbx rsi rdi} GC regs: 00000080 {rdi} => 000000C0 {rsi rdi} Byref regs: (unchanged) 00000000 {} L_M38507_BB30: G_M38507_IG26: ; offs=000267H, funclet=00, bbWeight=0.50 Mapped BB30 to G_M38507_IG27 Label: IG27, GCvars=00000000000000000000000000000000 {}, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {} Scope info: begin block BB30, IL range [14B..14F) Added IP mapping: 0x014B STACK_EMPTY (G_M38507_IG27,ins#0,ofs#0) label Generating: N701 (???,???) [001376] ------------ IL_OFFSET void IL offset: 0x14b REG NA Generating: N703 ( 2, 2) [000433] ------------ t433 = LCL_VAR ubyte V03 arg3 u:1 rbx (last use) REG rbx $140 Generating: N705 ( 1, 1) [000434] -c---------- t434 = CNS_INT ubyte 2 REG NA $c2 /--* t433 ubyte +--* t434 ubyte Generating: N707 ( 5, 6) [000435] N------N-U-- * EQ void REG NA $600 V03 in reg rbx is becoming dead [000433] Live regs: 000000C8 {rbx rsi rdi} => 000000C0 {rsi rdi} Live vars: {V00 V01 V03} => {V00 V01} IN0096: cmp bl, 2 Generating: N709 ( 7, 8) [000436] ------------ * JTRUE void REG NA IN0097: je L_M38507_BB60 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 30 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG26,ins#7,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG26,ins#7,ofs#31), (G_M38507_IG27,ins#0,ofs#0) ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 30 =============== Generating BB31 [???..???) (return), preds={BB30,BB41} succs={} flags=0x00000000.20098040: internal Loop1 label gcsafe LIR BB31 IN (1)={V00} OUT(1)={V00} Recording Var Locations at start of BB31 V00(rsi) Change life 00000000000000000000000000000210 {V00 V01} -> 00000000000000000000000000000010 {V00} V01 in reg rdi is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 00000040 {rsi} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: (unchanged) 00000000 {} L_M38507_BB31: G_M38507_IG27: ; offs=000286H, funclet=00, bbWeight=0.50 Mapped BB31 to G_M38507_IG28 Label: IG28, GCvars=00000000000000000000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} Scope info: begin block BB31, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP STACK_EMPTY (G_M38507_IG28,ins#0,ofs#0) label Generating: N713 ( 1, 1) [000437] ------------ t437 = CNS_INT int 0 REG rax $c0 IN0098: xor eax, eax /--* t437 int Generating: N715 ( 2, 2) [000811] ------------ * RETURN int REG NA $1f3 Scope info: ignoring block end Added IP mapping: EPILOG STACK_EMPTY (G_M38507_IG28,ins#1,ofs#2) label Reserving epilog IG for block BB31 G_M38507_IG28: ; offs=00028FH, funclet=00, bbWeight=0.50 *************** After placeholder IG creation G_M38507_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M38507_IG02: ; offs=000000H, size=0014H, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG03: ; offs=000014H, size=000AH, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG04: ; offs=00001EH, size=0023H, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG05: ; offs=000041H, size=0008H, gcrefRegs=000040E4 {rdx rbp rsi rdi r14}, byrefRegs=00000000 {}, byref G_M38507_IG06: ; offs=000049H, size=0018H, gcrefRegs=000040E0 {rbp rsi rdi r14}, byrefRegs=00000000 {}, byref G_M38507_IG07: ; offs=000061H, size=0012H, gcrefRegs=0000C0E4 {rdx rbp rsi rdi r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG08: ; offs=000073H, size=000DH, gcrefRegs=0000C0E0 {rbp rsi rdi r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG09: ; offs=000080H, size=0017H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG10: ; offs=000097H, size=0005H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG11: ; offs=00009CH, size=0012H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG12: ; offs=0000AEH, size=0011H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG13: ; offs=0000BFH, size=0010H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG14: ; offs=0000CFH, size=003FH, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG15: ; offs=00010EH, size=0008H, gcVars=00000000000000000000000000200000 {V39}, gcrefRegs=0000D0E4 {rdx rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG16: ; offs=000116H, size=0047H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG17: ; offs=00015DH, size=0008H, gcrefRegs=0000D0E4 {rdx rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG18: ; offs=000165H, size=0038H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG19: ; offs=00019DH, size=0017H, gcVars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG20: ; offs=0001B4H, size=0005H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG21: ; offs=0001B9H, size=0012H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG22: ; offs=0001CBH, size=0008H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG23: ; offs=0001D3H, size=0035H, gcrefRegs=0000D0E1 {rax rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG24: ; offs=000208H, size=0028H, gcVars=00000000000000000000000100000040 {V08 V65}, gcrefRegs=0000D0E1 {rax rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG25: ; offs=000230H, size=0037H, gcVars=00000000000000000000000100000040 {V08 V65}, gcrefRegs=0000D0E1 {rax rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG26: ; offs=000267H, size=001FH, gcVars=00000000000000000000000000000040 {V65}, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG27: ; offs=000286H, size=0009H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG28: ; offs=00028FH, size=0002H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M38507_IG29: ; epilog placeholder, next placeholder=, BB31 [0092], epilog, extend <-- First placeholder <-- Last placeholder ; PrevGCVars=00000000000000000000000000000000 {}, PrevGCrefRegs=000000C0 {rsi rdi}, PrevByrefRegs=00000000 {} ; InitGCVars=00000000000000000000000000000000 {}, InitGCrefRegs=00000040 {rsi}, InitByrefRegs=00000000 {} G_M38507_IG30: ; offs=000391H, size=0000H, gcrefRegs=00000000 {} <-- Current IG //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 31 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG26,ins#7,ofs#31), (G_M38507_IG27,ins#2,ofs#9) ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 31 =============== Generating BB32 [177..17E) -> BB44 (cond), preds={BB18,BB43} succs={BB33,BB44} flags=0x00000008.21116020: i Loop Loop0 label idxlen bwd bwd-target LIR BB32 IN (11)={ V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(12)={V76 V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08} + ByrefExposed + GcHeap Recording Var Locations at start of BB32 V04(r15) V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) Change life 00000000000000000000000000000010 {V00} -> 0000000000000000000000010007063E {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} New debug range: new var or location V04 in reg r15 is becoming live [------] Live regs: 00000000 {} => 00008000 {r15} New debug range: new var or location New debug range: new var or location V06 in reg r13 is becoming live [------] Live regs: 00008000 {r15} => 0000A000 {r13 r15} New debug range: new var or location V01 in reg rdi is becoming live [------] Live regs: 0000A000 {r13 r15} => 0000A080 {rdi r13 r15} New debug range: new var or location V73 in reg r14 is becoming live [------] Live regs: 0000A080 {rdi r13 r15} => 0000E080 {rdi r13 r14 r15} V05 in reg r12 is becoming live [------] Live regs: 0000E080 {rdi r13 r14 r15} => 0000F080 {rdi r12 r13 r14 r15} New debug range: new var or location V03 in reg rbx is becoming live [------] Live regs: 0000F080 {rdi r12 r13 r14 r15} => 0000F088 {rbx rdi r12 r13 r14 r15} New debug range: new var or location V02 in reg rbp is becoming live [------] Live regs: 0000F088 {rbx rdi r12 r13 r14 r15} => 0000F0A8 {rbx rbp rdi r12 r13 r14 r15} New debug range: new var or location V08 becoming live New debug range: new var or location Live regs: 0000F0A8 {rbx rbp rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 0000D0A0 {rbp rdi r12 r14 r15} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB32: Mapped BB32 to G_M38507_IG30 Label: IG30, GCvars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB32, IL range [177..17E) Added IP mapping: 0x0177 STACK_EMPTY (G_M38507_IG30,ins#0,ofs#0) label Generating: N719 (???,???) [001377] ------------ IL_OFFSET void IL offset: 0x177 REG NA Generating: N721 ( 1, 1) [000063] ------------ t63 = LCL_VAR ref V04 loc0 u:1 r15 REG r15 /--* t63 ref Generating: N723 (???,???) [001448] -c---------- t1448 = * LEA(b+8) ref REG NA /--* t1448 ref Generating: N725 ( 3, 3) [000064] ---X-------- t64 = * IND int REG r9 IN0099: mov r9d, dword ptr [r15+8] /--* t64 int Generating: N727 ( 3, 3) [001323] DA-X-------- * STORE_LCL_VAR int V76 cse11 r9 REG r9 V76 in reg r9 is becoming live [001323] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F2E8 {rbx rbp rsi rdi r9 r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73 V76} Generating: N729 ( 1, 1) [001324] -----------Z t1324 = LCL_VAR int V76 cse11 r9 REG r9 Generating: N731 ( 1, 1) [000062] -----------z t62 = LCL_VAR int V09 loc5 u:2 r8 REG r8 $3c4 /--* t1324 int +--* t62 int Generating: N733 ( 6, 6) [000065] N--X---N-U-- * LE void REG NA IN009a: mov dword ptr [V76 rsp+5CH], r9d V76 in reg r9 is becoming dead [001324] Live regs: 0000F2E8 {rbx rbp rsi rdi r9 r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} IN009b: mov r8d, dword ptr [V09 rsp+88H] New debug range: not adjacent V09 in reg r8 is becoming live [000062] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F1E8 {rbx rbp rsi rdi r8 r12 r13 r14 r15} IN009c: cmp r9d, r8d Generating: N735 ( 8, 8) [000066] ---X-------- * JTRUE void REG NA IN009d: jbe L_M38507_BB44 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 32 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 9: [rsp'[136] (1 slot) [ (G_M38507_IG30,ins#0,ofs#0), (G_M38507_IG30,ins#3,ofs#17) ]; r8 [ (G_M38507_IG30,ins#3,ofs#17), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 32 =============== Generating BB33 [17E..18E) -> BB42 (cond), preds={BB32} succs={BB34,BB42} flags=0x00000000.21100020: i idxlen bwd LIR BB33 IN (12)={V76 V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(13)={V76 V07 V04 V00 V06 V66 V01 V73 V71 V05 V03 V02 V08} + ByrefExposed + GcHeap Recording Var Locations at start of BB33 V04(r15) V09(r8) V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) Liveness not changing: 0000000000000000000000010007063F {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73 V76} Live regs: 00000000 {} => 0000F1E8 {rbx rbp rsi rdi r8 r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB33: Scope info: begin block BB33, IL range [17E..18E) Added IP mapping: 0x017E STACK_EMPTY (G_M38507_IG30,ins#5,ofs#26) label Generating: N739 (???,???) [001378] ------------ IL_OFFSET void IL offset: 0x17e REG NA Generating: N741 ( 1, 1) [000949] ------------ t949 = LCL_VAR ref V04 loc0 u:1 r15 REG r15 Generating: N743 ( 1, 1) [000950] ------------ t950 = LCL_VAR int V09 loc5 u:2 r8 (last use) REG r8 $3c4 /--* t950 int Generating: N745 ( 2, 3) [000953] ------------ t953 = * CAST long <- int REG rcx $6e1 V09 in reg r8 is becoming dead [000950] Live regs: 0000F1E8 {rbx rbp rsi rdi r8 r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V73 V76} IN009e: movsxd rcx, r8d Generating: N747 ( 1, 1) [000960] -c---------- t960 = CNS_INT long 3 REG NA $24b /--* t953 long +--* t960 long Generating: N749 ( 7, 7) [000961] ------------ t961 = * MUL long REG rcx $6e2 IN009f: lea rcx, [rcx+2*rcx] /--* t961 long Generating: N751 ( 7, 7) [001281] DA---------- * STORE_LCL_VAR long V71 cse6 d:1 rcx REG rcx V71 in reg rcx is becoming live [001281] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V71 V73 V76} Generating: N753 ( 1, 1) [001282] ------------ t1282 = LCL_VAR long V71 cse6 u:1 rcx REG rcx $6e2 /--* t949 ref +--* t1282 long Generating: N755 ( 11, 11) [000958] -------N---- t958 = * LEA(b+(i*8)+16) byref REG r8 IN00a0: lea r8, bword ptr [r15+8*rcx+16] Byref regs: 00000000 {} => 00000100 {r8} /--* t958 byref Generating: N757 ( 23, 23) [001255] DA--G------- * STORE_LCL_VAR byref V66 cse1 d:1 r8 REG r8 Byref regs: 00000100 {r8} => 00000000 {} V66 in reg r8 is becoming live [001255] Live regs: 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F1EA {rcx rbx rbp rsi rdi r8 r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V71 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V66 V71 V73 V76} Byref regs: 00000000 {} => 00000100 {r8} Generating: N759 ( 1, 1) [001256] -----------Z t1256 = LCL_VAR byref V66 cse1 u:1 r8 REG r8 /--* t1256 byref Generating: N761 ( 25, 25) [000948] -c---------- t948 = * LEA(b+16) byref REG NA /--* t948 byref Generating: N763 ( 27, 27) [000212] *c-XG------- t212 = * IND int REG NA Generating: N765 ( 1, 1) [000213] ------------ t213 = LCL_VAR int V06 loc2 u:1 r13 REG r13 $3c0 /--* t212 int +--* t213 int Generating: N767 ( 29, 29) [000214] N--XG--N-U-- * NE void REG NA IN00a1: mov bword ptr [V66 rsp+28H], r8 V66 in reg r8 is becoming dead [001256] Live regs: 0000F1EA {rcx rbx rbp rsi rdi r8 r12 r13 r14 r15} => 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} Byref regs: 00000100 {r8} => 00000000 {} Var V66 becoming live IN00a2: cmp dword ptr [r8+16], r13d Generating: N769 ( 31, 31) [000215] ---XG------- * JTRUE void REG NA IN00a3: jne L_M38507_BB42 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 33 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 9: [r8 [ (G_M38507_IG30,ins#3,ofs#17), (G_M38507_IG30,ins#5,ofs#26) ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 33 =============== Generating BB34 [18E..???) -> BB36 (cond), preds={BB33} succs={BB35,BB36} flags=0x00000002.21180020: i hascall gcsafe idxlen bwd LIR BB34 IN (13)={V76 V07 V04 V00 V06 V66 V01 V73 V71 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(15)={V76 V07 V04 V00 V06 V66 V01 V73 V16 V17 V05 V03 V02 V67 V08} + ByrefExposed + GcHeap Recording Var Locations at start of BB34 V04(r15) V00(rsi) V06(r13) V01(rdi) V73(r14) V71(rcx) V05(r12) V03(rbx) V02(rbp) Liveness not changing: 000000000000000000000001000726B7 {V00 V01 V02 V03 V04 V05 V06 V07 V08 V66 V71 V73 V76} Live regs: 00000000 {} => 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB34: Adding label due to BB weight difference: BBJ_COND BB33 with weight 400 different from BB34 with weight 200 G_M38507_IG30: ; offs=000391H, funclet=00, bbWeight=4 Mapped BB34 to G_M38507_IG31 Label: IG31, GCvars=00000000000000000000000100000080 {V08 V66}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB34, IL range [18E..???) Added IP mapping: 0x018E STACK_EMPTY (G_M38507_IG31,ins#0,ofs#0) label Generating: N773 (???,???) [001379] ------------ IL_OFFSET void IL offset: 0x18e REG NA Generating: N775 ( 1, 1) [000963] ------------ t963 = LCL_VAR ref V04 loc0 u:1 r15 REG r15 Generating: N777 ( 1, 1) [001284] ------------ t1284 = LCL_VAR long V71 cse6 u:1 rcx (last use) REG rcx $6e2 /--* t963 ref +--* t1284 long Generating: N779 ( 4, 4) [000972] -c---------- t972 = * LEA(b+(i*8)+16) byref REG NA /--* t972 byref Generating: N781 ( 12, 11) [000977] *---G--N---- t977 = * IND ref REG r10 V71 in reg rcx is becoming dead [001284] Live regs: 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V66 V71 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V66 V73 V76} IN00a4: mov r10, gword ptr [r15+8*rcx+16] GC regs: 0000D0E0 {rbp rsi rdi r12 r14 r15} => 0000D4E0 {rbp rsi rdi r10 r12 r14 r15} /--* t977 ref Generating: N783 ( 12, 11) [000246] DA--G------- * STORE_LCL_VAR ref V17 tmp3 d:1 NA REG NA GC regs: 0000D4E0 {rbp rsi rdi r10 r12 r14 r15} => 0000D0E0 {rbp rsi rdi r12 r14 r15} IN00a5: mov gword ptr [V17 rsp+40H], r10 Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V66 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V66 V73 V76} GCvars: {V08 V66} => {V08 V17 V66} genIPmappingAdd: ignoring duplicate IL offset 0x18e Generating: N785 (???,???) [001380] ------------ IL_OFFSET void IL offset: 0x18e REG NA Generating: N787 ( 1, 1) [000241] !----------- t241 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t241 ref Generating: N789 ( 3, 2) [000242] #----O------ t242 = * IND long REG rcx $2e8 IN00a6: mov rcx, qword ptr [rsi] /--* t242 long Generating: N791 ( 3, 3) [000244] DA---O------ * STORE_LCL_VAR long V16 tmp2 d:1 rcx REG rcx V16 in reg rcx is becoming live [000244] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V66 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V16 V17 V66 V73 V76} Generating: N793 ( 1, 1) [000249] ------------ t249 = LCL_VAR long V16 tmp2 u:1 rcx REG rcx $2e7 /--* t249 long Generating: N795 ( 2, 2) [000251] -c---------- t251 = * LEA(b+56) long REG NA /--* t251 long Generating: N797 ( 4, 4) [000252] #----------- t252 = * IND long REG rdx $2e9 IN00a7: mov rdx, qword ptr [rcx+56] /--* t252 long Generating: N799 ( 7, 6) [000253] #----------- t253 = * IND long REG rdx $2ea IN00a8: mov rdx, qword ptr [rdx] /--* t253 long Generating: N801 ( 8, 7) [000255] -c---------- t255 = * LEA(b+48) long REG NA /--* t255 long Generating: N803 ( 10, 9) [000259] n----------- t259 = * IND long REG r11 IN00a9: mov r11, qword ptr [rdx+48] /--* t259 long Generating: N805 ( 10, 9) [001261] DA---------- * STORE_LCL_VAR long V67 cse2 d:1 r11 REG r11 V67 in reg r11 is becoming live [001261] Live regs: 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F8EA {rcx rbx rbp rsi rdi r11 r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V16 V17 V66 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V16 V17 V66 V67 V73 V76} Generating: N807 ( 1, 1) [001262] ------------ t1262 = LCL_VAR long V67 cse2 u:1 r11 REG r11 Generating: N809 ( 1, 1) [000262] -c---------- t262 = CNS_INT long 0 REG NA $243 /--* t1262 long +--* t262 long Generating: N811 ( 13, 12) [000263] J------N---- * EQ void REG NA IN00aa: test r11, r11 Generating: N813 ( 15, 14) [001163] ------------ * JTRUE void REG NA IN00ab: je L_M38507_BB36 Scope info: ignoring block end //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 34 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 34 =============== Generating BB35 [???..???) -> BB37 (always), preds={BB34} succs={BB37} flags=0x00000000.20080020: i gcsafe LIR BB35 IN (14)={V76 V07 V04 V00 V06 V66 V01 V73 V17 V05 V03 V02 V67 V08} + ByrefExposed + GcHeap OUT(14)={V76 V07 V04 V00 V06 V66 V19 V01 V73 V17 V05 V03 V02 V08} + ByrefExposed + GcHeap Recording Var Locations at start of BB35 V04(r15) V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) V67(r11) Change life 000000000000000000000001000F8EB7 {V00 V01 V02 V03 V04 V05 V06 V07 V08 V16 V17 V66 V67 V73 V76} -> 000000000000000000000001000F86B7 {V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V66 V67 V73 V76} V16 in reg rcx is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 0000F8E8 {rbx rbp rsi rdi r11 r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB35: Adding label due to BB weight difference: BBJ_COND BB34 with weight 200 different from BB35 with weight 100 G_M38507_IG31: ; offs=0003C6H, funclet=00, bbWeight=2 Mapped BB35 to G_M38507_IG32 Label: IG32, GCvars=00000000000000000000000100008080 {V08 V17 V66}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB35, IL range [???..???) Scope info: ignoring block beginning Generating: N001 ( 1, 1) [001512] -----------z t1512 = LCL_VAR ref V17 tmp3 r10 REG r10 IN00ac: mov r10, gword ptr [V17 rsp+40H] Removing V17 from gcVarPtrSetCur V17 in reg r10 is becoming live [001512] Live regs: 0000F8E8 {rbx rbp rsi rdi r11 r12 r13 r14 r15} => 0000FCE8 {rbx rbp rsi rdi r10 r11 r12 r13 r14 r15} GC regs: 0000D0E0 {rbp rsi rdi r12 r14 r15} => 0000D4E0 {rbp rsi rdi r10 r12 r14 r15} Generating: N817 ( 1, 1) [001264] ------------ t1264 = LCL_VAR long V67 cse2 u:1 r11 (last use) REG r11 /--* t1264 long Generating: N819 ( 1, 3) [001165] DA---------- * STORE_LCL_VAR long V19 tmp5 d:3 r11 REG r11 V67 in reg r11 is becoming dead [001264] Live regs: 0000FCE8 {rbx rbp rsi rdi r10 r11 r12 r13 r14 r15} => 0000F4E8 {rbx rbp rsi rdi r10 r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V66 V67 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V66 V73 V76} V19 in reg r11 is becoming live [001165] Live regs: 0000F4E8 {rbx rbp rsi rdi r10 r12 r13 r14 r15} => 0000FCE8 {rbx rbp rsi rdi r10 r11 r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V66 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V19 V66 V73 V76} Scope info: ignoring block end IN00ad: jmp L_M38507_BB37 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 35 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 35 =============== Generating BB36 [???..???), preds={BB34} succs={BB37} flags=0x00000000.20090020: i label gcsafe LIR BB36 IN (14)={V76 V07 V04 V00 V06 V66 V01 V73 V16 V17 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(14)={V76 V07 V04 V00 V06 V66 V19 V01 V73 V17 V05 V03 V02 V08} + ByrefExposed + GcHeap Recording Var Locations at start of BB36 V04(r15) V00(rsi) V06(r13) V01(rdi) V73(r14) V16(rcx) V17(r10->STK) V05(r12) V03(rbx) V02(rbp) Change life 000000000000000000000001000787B7 {V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V19 V66 V73 V76} -> 00000000000000000000000100078EB7 {V00 V01 V02 V03 V04 V05 V06 V07 V08 V16 V17 V66 V73 V76} V19 in reg r11 is becoming dead [------] Live regs: (unchanged) 00000000 {} V16 in reg rcx is becoming live [------] Live regs: 00000000 {} => 00000002 {rcx} Live regs: 00000002 {rcx} => 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} Added GCVars: {V17} GC regs: 00000000 {} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB36: G_M38507_IG32: ; offs=0003E7H, funclet=00, bbWeight=1 Mapped BB36 to G_M38507_IG33 Label: IG33, GCvars=00000000000000000000000100008080 {V08 V17 V66}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB36, IL range [???..???) Scope info: ignoring block beginning Generating: N823 ( 1, 1) [000248] ------?----- t248 = LCL_VAR long V16 tmp2 u:1 rcx (last use) REG rcx $2e7 /--* t248 long Generating: N825 (???,???) [001478] ------------ t1478 = * PUTARG_REG long REG rcx V16 in reg rcx is becoming dead [000248] Live regs: 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V16 V17 V66 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V66 V73 V76} Generating: N827 ( 2, 10) [000260] H-----?----- t260 = CNS_INT(h) long 0xd1ffab1e global ptr REG rdx $63 IN00ae: mov rdx, 0xD1FFAB1E /--* t260 long Generating: N829 (???,???) [001479] ------------ t1479 = * PUTARG_REG long REG rdx /--* t1478 long arg0 in rcx +--* t1479 long arg1 in rdx Generating: N831 ( 17, 18) [000261] --C-G-?----- t261 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS REG rax $6e7 Call: GCvars=00000000000000000000000100008080 {V08 V17 V66}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} IN00af: call CORINFO_HELP_RUNTIMEHANDLE_CLASS /--* t261 long Generating: N833 ( 17, 18) [001167] DA--G------- * STORE_LCL_VAR long V19 tmp5 d:2 r11 REG r11 IN00b0: mov r11, rax V19 in reg r11 is becoming live [001167] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F8E8 {rbx rbp rsi rdi r11 r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V66 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V19 V66 V73 V76} Generating: N001 ( 1, 1) [001513] -----------z t1513 = LCL_VAR ref V17 tmp3 r10 REG r10 IN00b1: mov r10, gword ptr [V17 rsp+40H] Removing V17 from gcVarPtrSetCur V17 in reg r10 is becoming live [001513] Live regs: 0000F8E8 {rbx rbp rsi rdi r11 r12 r13 r14 r15} => 0000FCE8 {rbx rbp rsi rdi r10 r11 r12 r13 r14 r15} GC regs: 0000D0E0 {rbp rsi rdi r12 r14 r15} => 0000D4E0 {rbp rsi rdi r10 r12 r14 r15} Scope info: ignoring block end //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 36 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 36 =============== Generating BB37 [???..1A4) -> BB42 (cond), preds={BB35,BB36} succs={BB38,BB42} flags=0x00000002.21190020: i label hascall gcsafe idxlen bwd LIR BB37 IN (14)={V76 V07 V04 V00 V06 V66 V19 V01 V73 V17 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(12)={V76 V07 V04 V00 V06 V66 V01 V73 V05 V03 V02 V08} + ByrefExposed + GcHeap Recording Var Locations at start of BB37 V04(r15) V00(rsi) V06(r13) V19(r11) V01(rdi) V73(r14) V17(r10) V05(r12) V03(rbx) V02(rbp) Liveness not changing: 000000000000000000000001000787B7 {V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V19 V66 V73 V76} Live regs: 00000000 {} => 0000FCE8 {rbx rbp rsi rdi r10 r11 r12 r13 r14 r15} GC regs: 00000000 {} => 0000D4E0 {rbp rsi rdi r10 r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB37: G_M38507_IG33: ; offs=0003F1H, funclet=00, bbWeight=1 Mapped BB37 to G_M38507_IG34 Label: IG34, GCvars=00000000000000000000000100000080 {V08 V66}, gcrefRegs=0000D4E0 {rbp rsi rdi r10 r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB37, IL range [???..1A4) Scope info: ignoring block beginning Generating: N837 ( 1, 1) [000234] ------------ t234 = LCL_VAR ref V05 loc1 u:1 r12 REG r12 /--* t234 ref Generating: N839 (???,???) [001480] ------------ t1480 = * PUTARG_REG ref REG rcx IN00b2: mov rcx, r12 GC regs: 0000D4E0 {rbp rsi rdi r10 r12 r14 r15} => 0000D4E2 {rcx rbp rsi rdi r10 r12 r14 r15} Generating: N841 ( 1, 1) [000980] ------------ t980 = LCL_VAR long V19 tmp5 u:1 r11 REG r11 $349 /--* t980 long Generating: N843 (???,???) [001481] ------------ t1481 = * PUTARG_REG long REG r11 Generating: N845 ( 1, 1) [000247] ------------ t247 = LCL_VAR ref V17 tmp3 u:1 r10 (last use) REG r10 /--* t247 ref Generating: N847 (???,???) [001482] ------------ t1482 = * PUTARG_REG ref REG rdx V17 in reg r10 is becoming dead [000247] Live regs: 0000FCE8 {rbx rbp rsi rdi r10 r11 r12 r13 r14 r15} => 0000F8E8 {rbx rbp rsi rdi r11 r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V17 V19 V66 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V19 V66 V73 V76} GC regs: 0000D4E2 {rcx rbp rsi rdi r10 r12 r14 r15} => 0000D0E2 {rcx rbp rsi rdi r12 r14 r15} IN00b3: mov rdx, r10 GC regs: 0000D0E2 {rcx rbp rsi rdi r12 r14 r15} => 0000D0E6 {rcx rdx rbp rsi rdi r12 r14 r15} Generating: N849 ( 1, 1) [000258] ------------ t258 = LCL_VAR ref V01 arg1 u:1 rdi REG rdi $101 /--* t258 ref Generating: N851 (???,???) [001483] ------------ t1483 = * PUTARG_REG ref REG r8 IN00b4: mov r8, rdi GC regs: 0000D0E6 {rcx rdx rbp rsi rdi r12 r14 r15} => 0000D1E6 {rcx rdx rbp rsi rdi r8 r12 r14 r15} Generating: N853 ( 1, 1) [000279] ------------ t279 = LCL_VAR long V19 tmp5 u:1 r11 (last use) REG r11 $349 /--* t279 long Generating: N855 (???,???) [001484] Dc---------- t1484 = * IND long REG NA /--* t1480 ref this in rcx +--* t1481 long arg1 in r11 +--* t1482 ref arg2 in rdx +--* t1483 ref arg3 in r8 +--* t1484 long calli tgt Generating: N857 ( 28, 14) [000280] --CXG------- t280 = * CALL ind stub int REG rax $1ef GC regs: 0000D1E6 {rcx rdx rbp rsi rdi r8 r12 r14 r15} => 0000D1E4 {rdx rbp rsi rdi r8 r12 r14 r15} GC regs: 0000D1E4 {rdx rbp rsi rdi r8 r12 r14 r15} => 0000D1E0 {rbp rsi rdi r8 r12 r14 r15} GC regs: 0000D1E0 {rbp rsi rdi r8 r12 r14 r15} => 0000D0E0 {rbp rsi rdi r12 r14 r15} V19 in reg r11 is becoming dead [000279] Live regs: 0000F8E8 {rbx rbp rsi rdi r11 r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V19 V66 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V66 V73 V76} Call: GCvars=00000000000000000000000100000080 {V08 V66}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} IN00b5: call qword ptr [r11] Generating: N859 ( 1, 1) [000281] -c---------- t281 = CNS_INT int 0 REG NA $c0 /--* t280 int +--* t281 int Generating: N861 ( 30, 16) [000282] J--XG--N---- * EQ void REG NA $817 IN00b6: test eax, eax Generating: N863 ( 32, 18) [000283] ---XG------- * JTRUE void REG NA IN00b7: je L_M38507_BB42 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 37 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 37 =============== Generating BB38 [1A4..1A8) -> BB40 (cond), preds={BB37} succs={BB39,BB40} flags=0x00000000.21080020: i gcsafe bwd LIR BB38 IN (5)={V00 V66 V01 V03 V02} + ByrefExposed + GcHeap OUT(5)={V00 V66 V01 V03 V02} + ByrefExposed + GcHeap Recording Var Locations at start of BB38 V00(rsi) V01(rdi) V03(rbx) V02(rbp) Change life 000000000000000000000001000706B7 {V00 V01 V02 V03 V04 V05 V06 V07 V08 V66 V73 V76} -> 00000000000000000000000000060290 {V00 V01 V02 V03 V66} V04 in reg r15 is becoming dead [------] Live regs: (unchanged) 00000000 {} V06 in reg r13 is becoming dead [------] Live regs: (unchanged) 00000000 {} V73 in reg r14 is becoming dead [------] Live regs: (unchanged) 00000000 {} V05 in reg r12 is becoming dead [------] Live regs: (unchanged) 00000000 {} V08 becoming dead Live regs: 00000000 {} => 000000E8 {rbx rbp rsi rdi} GC regs: 00000000 {} => 000000E0 {rbp rsi rdi} Byref regs: (unchanged) 00000000 {} L_M38507_BB38: Adding label due to BB weight difference: BBJ_COND BB37 with weight 200 different from BB38 with weight 50 G_M38507_IG34: ; offs=000408H, funclet=00, bbWeight=2 Mapped BB38 to G_M38507_IG35 Label: IG35, GCvars=00000000000000000000000000000080 {V66}, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {} Scope info: begin block BB38, IL range [1A4..1A8) Added IP mapping: 0x01A4 STACK_EMPTY (G_M38507_IG35,ins#0,ofs#0) label Generating: N867 (???,???) [001381] ------------ IL_OFFSET void IL offset: 0x1a4 REG NA Generating: N869 ( 2, 2) [000284] ------------ t284 = LCL_VAR ubyte V03 arg3 u:1 rbx REG rbx $140 Generating: N871 ( 1, 1) [000285] -c---------- t285 = CNS_INT ubyte 1 REG NA $c1 /--* t284 ubyte +--* t285 ubyte Generating: N873 ( 5, 6) [000286] N------N-U-- * NE void REG NA $1bf IN00b8: cmp bl, 1 Generating: N875 ( 7, 8) [000287] ------------ * JTRUE void REG NA IN00b9: jne L_M38507_BB40 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 38 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG30,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG30,ins#0,ofs#0), (G_M38507_IG34,ins#6,ofs#20) ]; ] IL Var Num 5: [r12 [ (G_M38507_IG30,ins#0,ofs#0), (G_M38507_IG34,ins#6,ofs#20) ]; ] IL Var Num 6: [r13 [ (G_M38507_IG30,ins#0,ofs#0), (G_M38507_IG34,ins#6,ofs#20) ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG30,ins#0,ofs#0), (G_M38507_IG34,ins#6,ofs#20) ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG30,ins#0,ofs#0), (G_M38507_IG34,ins#6,ofs#20) ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 38 =============== Generating BB39 [1A8..1B8) -> BB58 (always), preds={BB38} succs={BB58} flags=0x00000000.20180020: i gcsafe idxlen LIR BB39 IN (3)={V00 V66 V02} OUT(1)={V00 } Recording Var Locations at start of BB39 V00(rsi) V02(rbp) Change life 00000000000000000000000000060290 {V00 V01 V02 V03 V66} -> 00000000000000000000000000040090 {V00 V02 V66} V01 in reg rdi is becoming dead [------] Live regs: (unchanged) 00000000 {} V03 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 00000060 {rbp rsi} GC regs: 00000000 {} => 00000060 {rbp rsi} Byref regs: (unchanged) 00000000 {} L_M38507_BB39: Scope info: begin block BB39, IL range [1A8..1B8) Added IP mapping: 0x01A8 STACK_EMPTY (G_M38507_IG35,ins#2,ofs#9) label Generating: N879 (???,???) [001382] ------------ IL_OFFSET void IL offset: 0x1a8 REG NA Generating: N881 ( 1, 1) [001258] -----------z t1258 = LCL_VAR byref V66 cse1 u:1 r15 (last use) REG r15 $91 /--* t1258 byref Generating: N883 ( 2, 2) [000987] ------------ t987 = * LEA(b+8) byref REG rcx IN00ba: mov r15, bword ptr [V66 rsp+28H] Removing V66 from gcVarPtrSetCur V66 in reg r15 is becoming live [001258] Live regs: 00000060 {rbp rsi} => 00008060 {rbp rsi r15} Byref regs: 00000000 {} => 00008000 {r15} V66 in reg r15 is becoming dead [001258] Live regs: 00008060 {rbp rsi r15} => 00000060 {rbp rsi} Live vars: {V00 V02 V66} => {V00 V02} Byref regs: 00008000 {r15} => 00000000 {} IN00bb: lea rcx, bword ptr [r15+8] Byref regs: 00000000 {} => 00000002 {rcx} Generating: N885 ( 1, 1) [000334] ------------ t334 = LCL_VAR ref V02 arg2 u:1 rbp (last use) REG rbp $102 /--* t987 byref +--* t334 ref Generating: N887 (???,???) [001383] -A-XG------- * STOREIND ref REG NA Byref regs: 00000002 {rcx} => 00000000 {} V02 in reg rbp is becoming dead [000334] Live regs: 00000060 {rbp rsi} => 00000040 {rsi} Live vars: {V00 V02} => {V00} GC regs: 00000060 {rbp rsi} => 00000040 {rsi} IN00bc: mov rdx, rbp NoGC Call: savedSet=0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} IN00bd: call CORINFO_HELP_CHECKED_ASSIGN_REF IN00be: jmp L_M38507_BB58 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 39 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG30,ins#0,ofs#0), (G_M38507_IG35,ins#2,ofs#9) ]; ] IL Var Num 2: [rbp [ (G_M38507_IG30,ins#0,ofs#0), (G_M38507_IG35,ins#4,ofs#18) ]; ] IL Var Num 3: [rbx [ (G_M38507_IG30,ins#0,ofs#0), (G_M38507_IG35,ins#2,ofs#9) ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 39 =============== Generating BB40 [1B8..1BC) -> BB64 (cond), preds={BB38} succs={BB41,BB64} flags=0x00000000.21090020: i label gcsafe bwd LIR BB40 IN (3)={V00 V01 V03} + ByrefExposed + GcHeap OUT(2)={V00 V01 } + ByrefExposed + GcHeap Recording Var Locations at start of BB40 V00(rsi) V01(rdi) V03(rbx) Change life 00000000000000000000000000000010 {V00} -> 00000000000000000000000000020210 {V00 V01 V03} V01 in reg rdi is becoming live [------] Live regs: 00000000 {} => 00000080 {rdi} New debug range: new var or location V03 in reg rbx is becoming live [------] Live regs: 00000080 {rdi} => 00000088 {rbx rdi} New debug range: new var or location Live regs: 00000088 {rbx rdi} => 000000C8 {rbx rsi rdi} GC regs: 00000080 {rdi} => 000000C0 {rsi rdi} Byref regs: (unchanged) 00000000 {} L_M38507_BB40: G_M38507_IG35: ; offs=00041CH, funclet=00, bbWeight=0.50 Mapped BB40 to G_M38507_IG36 Label: IG36, GCvars=00000000000000000000000000000000 {}, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {} Scope info: begin block BB40, IL range [1B8..1BC) Added IP mapping: 0x01B8 STACK_EMPTY (G_M38507_IG36,ins#0,ofs#0) label Generating: N891 (???,???) [001384] ------------ IL_OFFSET void IL offset: 0x1b8 REG NA Generating: N893 ( 2, 2) [000288] ------------ t288 = LCL_VAR ubyte V03 arg3 u:1 rbx (last use) REG rbx $140 Generating: N895 ( 1, 1) [000289] -c---------- t289 = CNS_INT ubyte 2 REG NA $c2 /--* t288 ubyte +--* t289 ubyte Generating: N897 ( 5, 6) [000290] N------N-U-- * EQ void REG NA $600 V03 in reg rbx is becoming dead [000288] Live regs: 000000C8 {rbx rsi rdi} => 000000C0 {rsi rdi} Live vars: {V00 V01 V03} => {V00 V01} IN00bf: cmp bl, 2 Generating: N899 ( 7, 8) [000291] ------------ * JTRUE void REG NA IN00c0: je L_M38507_BB64 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 40 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG35,ins#7,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG35,ins#7,ofs#31), (G_M38507_IG36,ins#0,ofs#0) ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 40 =============== Generating BB41 [???..???) -> BB31 (always), preds={BB40} succs={BB31} flags=0x00000000.20080040: internal gcsafe LIR BB41 IN (1)={V00} OUT(1)={V00} Recording Var Locations at start of BB41 V00(rsi) Change life 00000000000000000000000000000210 {V00 V01} -> 00000000000000000000000000000010 {V00} V01 in reg rdi is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 00000040 {rsi} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: (unchanged) 00000000 {} L_M38507_BB41: Scope info: begin block BB41, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP STACK_EMPTY (G_M38507_IG36,ins#2,ofs#9) label Scope info: ignoring block end IN00c1: jmp L_M38507_BB31 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 41 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG35,ins#7,ofs#31), (G_M38507_IG36,ins#2,ofs#9) ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 41 =============== Generating BB42 [1C4..1DD) -> BB68 (cond), preds={BB33,BB37} succs={BB43,BB68} flags=0x00000000.21110020: i label idxlen bwd LIR BB42 IN (12)={V76 V07 V04 V00 V06 V66 V01 V73 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(11)={ V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08} + ByrefExposed + GcHeap Recording Var Locations at start of BB42 V04(r15) V00(rsi) V06(r13) V66(r15->STK) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) Change life 00000000000000000000000000000010 {V00} -> 000000000000000000000001000706B7 {V00 V01 V02 V03 V04 V05 V06 V07 V08 V66 V73 V76} New debug range: new var or location V04 in reg r15 is becoming live [------] Live regs: 00000000 {} => 00008000 {r15} New debug range: new var or location V06 in reg r13 is becoming live [------] Live regs: 00008000 {r15} => 0000A000 {r13 r15} New debug range: new var or location V66 becoming live V01 in reg rdi is becoming live [------] Live regs: 0000A000 {r13 r15} => 0000A080 {rdi r13 r15} Extending debug range... V73 in reg r14 is becoming live [------] Live regs: 0000A080 {rdi r13 r15} => 0000E080 {rdi r13 r14 r15} V05 in reg r12 is becoming live [------] Live regs: 0000E080 {rdi r13 r14 r15} => 0000F080 {rdi r12 r13 r14 r15} New debug range: new var or location V03 in reg rbx is becoming live [------] Live regs: 0000F080 {rdi r12 r13 r14 r15} => 0000F088 {rbx rdi r12 r13 r14 r15} New debug range: new var or location V02 in reg rbp is becoming live [------] Live regs: 0000F088 {rbx rdi r12 r13 r14 r15} => 0000F0A8 {rbx rbp rdi r12 r13 r14 r15} New debug range: new var or location V08 becoming live New debug range: new var or location Live regs: 0000F0A8 {rbx rbp rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 0000D0A0 {rbp rdi r12 r14 r15} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB42: G_M38507_IG36: ; offs=00043BH, funclet=00, bbWeight=0.50 Mapped BB42 to G_M38507_IG37 Label: IG37, GCvars=00000000000000000000000100000080 {V08 V66}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB42, IL range [1C4..1DD) Added IP mapping: 0x01C4 STACK_EMPTY (G_M38507_IG37,ins#0,ofs#0) label Generating: N905 (???,???) [001385] ------------ IL_OFFSET void IL offset: 0x1c4 REG NA Generating: N907 ( 1, 1) [001259] -----------z t1259 = LCL_VAR byref V66 cse1 u:1 r8 (last use) REG r8 $91 /--* t1259 byref Generating: N909 ( 2, 2) [001009] -c---------- t1009 = * LEA(b+20) byref REG NA /--* t1009 byref Generating: N911 ( 4, 4) [000220] *--XG------- t220 = * IND int REG r8 IN00c2: mov r8, bword ptr [V66 rsp+28H] Removing V66 from gcVarPtrSetCur V66 in reg r8 is becoming live [001259] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F1E8 {rbx rbp rsi rdi r8 r12 r13 r14 r15} Byref regs: 00000000 {} => 00000100 {r8} V66 in reg r8 is becoming dead [001259] Live regs: 0000F1E8 {rbx rbp rsi rdi r8 r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V66 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V73 V76} Byref regs: 00000100 {r8} => 00000000 {} IN00c3: mov r8d, dword ptr [r8+20] /--* t220 int Generating: N913 ( 4, 4) [000222] DA-XG------- * STORE_LCL_VAR int V09 loc5 d:3 rcx REG rcx IN00c4: mov ecx, r8d V09 in reg rcx is becoming live [000222] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73 V76} New debug range: not adjacent Added IP mapping: 0x01D3 STACK_EMPTY (G_M38507_IG37,ins#3,ofs#12) Generating: N915 (???,???) [001386] ------------ IL_OFFSET void IL offset: 0x1d3 REG NA Generating: N917 ( 1, 1) [000223] -----------z t223 = LCL_VAR int V07 loc3 u:3 r8 (last use) REG r8 $3c3 Generating: N919 ( 1, 1) [000224] -c---------- t224 = CNS_INT int 1 REG NA $c1 /--* t223 int +--* t224 int Generating: N921 ( 3, 3) [000225] ------------ t225 = * ADD int REG r8 $81a IN00c5: mov r8d, dword ptr [V07 rsp+8CH] V07 in reg r8 is becoming live [000223] Live regs: 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F1EA {rcx rbx rbp rsi rdi r8 r12 r13 r14 r15} V07 in reg r8 is becoming dead [000223] Live regs: 0000F1EA {rcx rbx rbp rsi rdi r8 r12 r13 r14 r15} => 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V08 V09 V73 V76} IN00c6: inc r8d /--* t225 int Generating: N923 ( 3, 3) [000227] DA---------- * STORE_LCL_VAR int V07 loc3 d:4 r8 REG r8 V07 in reg r8 is becoming live [000227] Live regs: 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F1EA {rcx rbx rbp rsi rdi r8 r12 r13 r14 r15} Live vars: {V00 V01 V02 V03 V04 V05 V06 V08 V09 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73 V76} New debug range: not adjacent Added IP mapping: 0x01D7 STACK_EMPTY (G_M38507_IG37,ins#5,ofs#23) Generating: N925 (???,???) [001387] ------------ IL_OFFSET void IL offset: 0x1d7 REG NA Generating: N927 ( 1, 1) [001328] -c---------- t1328 = LCL_VAR int V76 cse11 NA (last use) REG NA Generating: N929 ( 1, 1) [000228] -----------Z t228 = LCL_VAR int V07 loc3 u:4 r8 REG r8 $81a /--* t1328 int +--* t228 int Generating: N931 ( 3, 3) [000231] N------N-U-- * LT void REG NA Live vars: {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73 V76} => {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} IN00c7: mov dword ptr [V07 rsp+8CH], r8d V07 in reg r8 is becoming dead [000228] Live regs: 0000F1EA {rcx rbx rbp rsi rdi r8 r12 r13 r14 r15} => 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} New debug range: not adjacent IN00c8: cmp dword ptr [V76 rsp+5CH], r8d Generating: N933 ( 5, 5) [000232] ------------ * JTRUE void REG NA IN00c9: jb L_M38507_BB68 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 42 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG35,ins#7,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG36,ins#3,ofs#14), (G_M38507_IG37,ins#4,ofs#20) ]; r8 [ (G_M38507_IG37,ins#5,ofs#23), (G_M38507_IG37,ins#6,ofs#31) ]; rsp'[140] (1 slot) [ (G_M38507_IG37,ins#6,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 9: [rcx [ (G_M38507_IG37,ins#3,ofs#12), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 42 =============== Generating BB43 [???..???) -> BB32 (always), preds={BB42} succs={BB32} flags=0x00000000.20000040: internal LIR BB43 IN (11)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08} + ByrefExposed + GcHeap OUT(11)={V07 V04 V09 V00 V06 V01 V73 V05 V03 V02 V08} + ByrefExposed + GcHeap Recording Var Locations at start of BB43 V04(r15) V09(rcx) V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V03(rbx) V02(rbp) Liveness not changing: 0000000000000000000000010007063E {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} Live regs: 00000000 {} => 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB43: Scope info: begin block BB43, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP STACK_EMPTY (G_M38507_IG37,ins#8,ofs#42) label Generating: N001 ( 1, 1) [001514] -----------Z t1514 = LCL_VAR int V09 loc5 rcx REG rcx IN00ca: mov dword ptr [V09 rsp+88H], ecx V09 in reg rcx is becoming dead [001514] Live regs: 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} New debug range: not adjacent Scope info: ignoring block end IN00cb: jmp L_M38507_BB32 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 43 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG35,ins#7,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG37,ins#6,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 9: [rcx [ (G_M38507_IG37,ins#3,ofs#12), (G_M38507_IG37,ins#9,ofs#49) ]; rsp'[136] (1 slot) [ (G_M38507_IG37,ins#9,ofs#49), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 43 =============== Generating BB44 [1E4..1ED) -> BB48 (cond), preds={BB23,BB32} succs={BB45,BB48} flags=0x00000000.20010020: i label LIR BB44 IN (10)={V76 V07 V04 V00 V06 V01 V73 V05 V02 V08} + ByrefExposed + GcHeap OUT(10)={V76 V07 V04 V00 V06 V01 V73 V05 V02 V08} + ByrefExposed + GcHeap Recording Var Locations at start of BB44 V04(r15) V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V02(rbp) Change life 0000000000000000000000010007063E {V00 V01 V02 V03 V04 V05 V06 V07 V08 V09 V73} -> 00000000000000000000000100050637 {V00 V01 V02 V04 V05 V06 V07 V08 V73 V76} V03 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} Live regs: 00000000 {} => 0000F0E0 {rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB44: G_M38507_IG37: ; offs=000449H, funclet=00, bbWeight=4 Mapped BB44 to G_M38507_IG38 Label: IG38, GCvars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB44, IL range [1E4..1ED) Added IP mapping: 0x01E4 STACK_EMPTY (G_M38507_IG38,ins#0,ofs#0) label Generating: N939 (???,???) [001388] ------------ IL_OFFSET void IL offset: 0x1e4 REG NA Generating: N941 ( 1, 1) [000067] ------------ t67 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t67 ref Generating: N943 ( 2, 2) [001025] -c---------- t1025 = * LEA(b+64) byref REG NA /--* t1025 byref Generating: N945 ( 4, 4) [000068] nc--GO------ t68 = * IND int REG NA Generating: N947 ( 1, 1) [000069] -c---------- t69 = CNS_INT int 0 REG NA $c0 /--* t68 int +--* t69 int Generating: N949 ( 6, 6) [000070] J---GO-N---- * LE void REG NA IN00cc: cmp dword ptr [rsi+64], 0 Generating: N951 ( 8, 8) [000071] ----GO------ * JTRUE void REG NA IN00cd: jle L_M38507_BB48 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 44 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG35,ins#7,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 3: [rbx [ (G_M38507_IG36,ins#3,ofs#14), (G_M38507_IG37,ins#10,ofs#54) ]; ] IL Var Num 4: [r15 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG37,ins#6,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 9: [rsp'[136] (1 slot) [ (G_M38507_IG37,ins#9,ofs#49), (G_M38507_IG37,ins#10,ofs#54) ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 44 =============== Generating BB45 [1ED..243) -> BB47 (cond), preds={BB44} succs={BB46,BB47} flags=0x00000000.20100020: i idxlen LIR BB45 IN (10)={V76 V07 V04 V00 V06 V01 V73 V05 V02 V08 } + ByrefExposed + GcHeap OUT(11)={V76 V07 V04 V00 V06 V01 V05 V02 V08 V10 V50} + ByrefExposed + GcHeap Recording Var Locations at start of BB45 V04(r15) V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V02(rbp) Liveness not changing: 00000000000000000000000100050637 {V00 V01 V02 V04 V05 V06 V07 V08 V73 V76} Live regs: 00000000 {} => 0000F0E0 {rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB45: Scope info: begin block BB45, IL range [1ED..243) Added IP mapping: 0x01ED STACK_EMPTY (G_M38507_IG38,ins#2,ofs#10) label Generating: N955 (???,???) [001389] ------------ IL_OFFSET void IL offset: 0x1ed REG NA Generating: N957 ( 1, 1) [000171] ------------ t171 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t171 ref Generating: N959 ( 2, 2) [001027] -c---------- t1027 = * LEA(b+60) byref REG NA /--* t1027 byref Generating: N961 ( 4, 4) [000172] n---GO------ t172 = * IND int REG rcx IN00ce: mov ecx, dword ptr [rsi+60] /--* t172 int Generating: N963 ( 8, 7) [001306] DA--GO------ * STORE_LCL_VAR int V74 cse9 d:1 rcx REG rcx V74 in reg rcx is becoming live [001306] Live regs: 0000F0E0 {rbp rsi rdi r12 r13 r14 r15} => 0000F0E2 {rcx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V73 V76} => {V00 V01 V02 V04 V05 V06 V07 V08 V73 V74 V76} Generating: N965 ( 3, 2) [001307] ------------ t1307 = LCL_VAR int V74 cse9 u:1 rcx REG rcx /--* t1307 int Generating: N967 ( 15, 12) [000174] DA--GO------ * STORE_LCL_VAR int V10 loc6 d:3 rbx REG rbx IN00cf: mov ebx, ecx V10 in reg rbx is becoming live [000174] Live regs: 0000F0E2 {rcx rbp rsi rdi r12 r13 r14 r15} => 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V73 V74 V76} => {V00 V01 V02 V04 V05 V06 V07 V08 V10 V73 V74 V76} New debug range: first Added IP mapping: 0x01F5 STACK_EMPTY (G_M38507_IG38,ins#4,ofs#15) Generating: N969 (???,???) [001390] ------------ IL_OFFSET void IL offset: 0x1f5 REG NA Generating: N971 ( 3, 2) [001309] ------------ t1309 = LCL_VAR int V74 cse9 u:1 rcx (last use) REG rcx /--* t1309 int Generating: N973 ( 3, 3) [001032] DA--G------- * STORE_LCL_VAR int V62 tmp48 d:1 rcx REG rcx V74 in reg rcx is becoming dead [001309] Live regs: 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10 V73 V74 V76} => {V00 V01 V02 V04 V05 V06 V07 V08 V10 V73 V76} V62 in reg rcx is becoming live [001032] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10 V73 V76} => {V00 V01 V02 V04 V05 V06 V07 V08 V10 V62 V73 V76} Generating: N975 ( 1, 1) [001033] ------------ t1033 = LCL_VAR int V62 tmp48 u:1 rcx REG rcx Generating: N977 ( 1, 1) [001329] -c---------- t1329 = LCL_VAR int V76 cse11 NA REG NA /--* t1033 int +--* t1329 int Generating: N979 ( 6, 9) [001036] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void REG NA IN00d0: cmp ecx, dword ptr [V76 rsp+5CH] IN00d1: jae L_M38507_BB69 Generating: N981 ( 1, 1) [001030] ------------ t1030 = LCL_VAR ref V04 loc0 u:1 r15 REG r15 Generating: N983 ( 1, 1) [001034] ------------ t1034 = LCL_VAR int V62 tmp48 u:1 rcx (last use) REG rcx /--* t1034 int Generating: N985 ( 2, 3) [001037] ------------ t1037 = * CAST long <- int REG rcx V62 in reg rcx is becoming dead [001034] Live regs: 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10 V62 V73 V76} => {V00 V01 V02 V04 V05 V06 V07 V08 V10 V73 V76} IN00d2: movsxd rcx, ecx Generating: N987 ( 1, 1) [001047] -c---------- t1047 = CNS_INT long 3 REG NA $24b /--* t1037 long +--* t1047 long Generating: N989 ( 7, 7) [001048] ------------ t1048 = * MUL long REG rcx IN00d3: lea rcx, [rcx+2*rcx] /--* t1030 ref +--* t1048 long Generating: N991 ( 31, 34) [001029] -c---------- t1029 = * LEA(b+(i*8)+36) byref REG NA /--* t1029 byref Generating: N993 ( 33, 36) [000181] *--XG------- t181 = * IND int REG rcx IN00d4: mov ecx, dword ptr [r15+8*rcx+36] /--* t181 int Generating: N995 ( 34, 37) [001050] ---XG------- t1050 = * NEG int REG rcx IN00d5: neg ecx Generating: N997 ( 1, 1) [000175] -c---------- t175 = CNS_INT int -3 REG NA $e1 /--* t1050 int +--* t175 int Generating: N999 ( 36, 39) [000182] ---XG------- t182 = * ADD int REG rcx IN00d6: add ecx, -3 Generating: N1001 ( 1, 1) [000183] -c---------- t183 = CNS_INT int -1 REG NA $c4 /--* t182 int +--* t183 int Generating: N1003 ( 41, 41) [000184] ---XG------- t184 = * GE int REG rcx IN00d7: cmp ecx, -1 IN00d8: setge cl IN00d9: movzx rcx, cl /--* t184 int Generating: N1005 ( 45, 44) [000688] DA-XG------- * STORE_LCL_VAR int V49 tmp35 d:1 rcx REG rcx V49 in reg rcx is becoming live [000688] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10 V73 V76} => {V00 V01 V02 V04 V05 V06 V07 V08 V10 V49 V73 V76} genIPmappingAdd: ignoring duplicate IL offset 0x1f5 Generating: N1007 (???,???) [001391] ------------ IL_OFFSET void IL offset: 0x1f5 REG NA Generating: N1009 ( 1, 1) [001300] ------------ t1300 = LCL_VAR ref V73 cse8 u:1 r14 (last use) REG r14 $105 /--* t1300 ref Generating: N1011 ( 5, 4) [000698] DA--G------- * STORE_LCL_VAR ref V50 tmp36 d:1 rdx REG rdx V73 in reg r14 is becoming dead [001300] Live regs: 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} => 0000B0EA {rcx rbx rbp rsi rdi r12 r13 r15} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10 V49 V73 V76} => {V00 V01 V02 V04 V05 V06 V07 V08 V10 V49 V76} GC regs: 0000D0E0 {rbp rsi rdi r12 r14 r15} => 000090E0 {rbp rsi rdi r12 r15} IN00da: mov rdx, r14 V50 in reg rdx is becoming live [000698] Live regs: 0000B0EA {rcx rbx rbp rsi rdi r12 r13 r15} => 0000B0EE {rcx rdx rbx rbp rsi rdi r12 r13 r15} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10 V49 V76} => {V00 V01 V02 V04 V05 V06 V07 V08 V10 V49 V50 V76} GC regs: 000090E0 {rbp rsi rdi r12 r15} => 000090E4 {rdx rbp rsi rdi r12 r15} genIPmappingAdd: ignoring duplicate IL offset 0x1f5 Generating: N1013 (???,???) [001392] ------------ IL_OFFSET void IL offset: 0x1f5 REG NA Generating: N1015 ( 3, 2) [000690] ------------ t690 = LCL_VAR int V49 tmp35 u:1 rcx (last use) REG rcx Generating: N1017 ( 1, 1) [000691] -c---------- t691 = CNS_INT int 0 REG NA $c0 /--* t690 int +--* t691 int Generating: N1019 ( 5, 4) [000692] J------N---- * NE void REG NA V49 in reg rcx is becoming dead [000690] Live regs: 0000B0EE {rcx rdx rbx rbp rsi rdi r12 r13 r15} => 0000B0EC {rdx rbx rbp rsi rdi r12 r13 r15} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10 V49 V50 V76} => {V00 V01 V02 V04 V05 V06 V07 V08 V10 V50 V76} IN00db: test ecx, ecx Generating: N1021 ( 7, 6) [000693] ------------ * JTRUE void REG NA IN00dc: jne L_M38507_BB47 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 45 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG35,ins#7,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG37,ins#6,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 10: [rbx [ (G_M38507_IG38,ins#4,ofs#15), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 45 =============== Generating BB46 [1F5..1F6), preds={BB45} succs={BB47} flags=0x00000002.20080020: i hascall gcsafe LIR BB46 IN (11)={V76 V07 V04 V00 V06 V01 V05 V02 V08 V10 V50} + ByrefExposed + GcHeap OUT(10)={V76 V07 V04 V00 V06 V01 V05 V02 V08 V10 } + ByrefExposed + GcHeap Recording Var Locations at start of BB46 V04(r15) V00(rsi) V06(r13) V01(rdi) V05(r12) V02(rbp) V10(rbx) V50(rdx) Liveness not changing: 00000000000000000000800300050237 {V00 V01 V02 V04 V05 V06 V07 V08 V10 V50 V76} Live regs: 00000000 {} => 0000B0EC {rdx rbx rbp rsi rdi r12 r13 r15} GC regs: 00000000 {} => 000090E4 {rdx rbp rsi rdi r12 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB46: Scope info: begin block BB46, IL range [1F5..1F6) genIPmappingAdd: ignoring duplicate IL offset 0x1f5 Generating: N1025 (???,???) [001393] ------------ IL_OFFSET void IL offset: 0x1f5 REG NA Generating: N1027 ( 2, 10) [001051] H----------- t1051 = CNS_INT(h) long 0xD1FFAB1E "shouldn't overflow because `next` cannot underflow" REG rcx $5e IN00dd: mov rcx, 0xD1FFAB1E /--* t1051 long Generating: N1029 ( 4, 12) [001052] #---G------- t1052 = * IND ref REG rcx $114 IN00de: mov rcx, gword ptr [rcx] GC regs: 000090E4 {rdx rbp rsi rdi r12 r15} => 000090E6 {rcx rdx rbp rsi rdi r12 r15} /--* t1052 ref Generating: N1031 (???,???) [001485] ----G------- t1485 = * PUTARG_REG ref REG rcx GC regs: 000090E6 {rcx rdx rbp rsi rdi r12 r15} => 000090E4 {rdx rbp rsi rdi r12 r15} GC regs: 000090E4 {rdx rbp rsi rdi r12 r15} => 000090E6 {rcx rdx rbp rsi rdi r12 r15} Generating: N1033 ( 3, 2) [000695] ------------ t695 = LCL_VAR ref V50 tmp36 u:1 rdx (last use) REG rdx $105 /--* t695 ref Generating: N1035 (???,???) [001486] ------------ t1486 = * PUTARG_REG ref REG rdx V50 in reg rdx is becoming dead [000695] Live regs: 0000B0EC {rdx rbx rbp rsi rdi r12 r13 r15} => 0000B0E8 {rbx rbp rsi rdi r12 r13 r15} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10 V50 V76} => {V00 V01 V02 V04 V05 V06 V07 V08 V10 V76} GC regs: 000090E6 {rcx rdx rbp rsi rdi r12 r15} => 000090E2 {rcx rbp rsi rdi r12 r15} GC regs: 000090E2 {rcx rbp rsi rdi r12 r15} => 000090E6 {rcx rdx rbp rsi rdi r12 r15} /--* t1485 ref arg0 in rcx +--* t1486 ref arg1 in rdx Generating: N1037 ( 21, 21) [000696] --CXG------- * CALL void System.Diagnostics.Debug.Fail REG NA $VN.Void GC regs: 000090E6 {rcx rdx rbp rsi rdi r12 r15} => 000090E4 {rdx rbp rsi rdi r12 r15} GC regs: 000090E4 {rdx rbp rsi rdi r12 r15} => 000090E0 {rbp rsi rdi r12 r15} Call: GCvars=00000000000000000000000100000000 {V08}, gcrefRegs=000090E0 {rbp rsi rdi r12 r15}, byrefRegs=00000000 {} IN00df: call System.Diagnostics.Debug:Fail(System.String,System.String) //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 46 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG35,ins#7,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG37,ins#6,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 10: [rbx [ (G_M38507_IG38,ins#4,ofs#15), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 46 =============== Generating BB47 [1F5..1F6) -> BB55 (always), preds={BB45,BB46} succs={BB55} flags=0x00000000.20110020: i label idxlen LIR BB47 IN (10)={V76 V07 V04 V00 V06 V01 V05 V02 V08 V10} + ByrefExposed + GcHeap OUT(9)={ V07 V04 V00 V06 V01 V05 V02 V08 V10} + ByrefExposed + GcHeap Recording Var Locations at start of BB47 V04(r15) V00(rsi) V06(r13) V01(rdi) V05(r12) V02(rbp) V10(rbx) Liveness not changing: 00000000000000000000000300050237 {V00 V01 V02 V04 V05 V06 V07 V08 V10 V76} Live regs: 00000000 {} => 0000B0E8 {rbx rbp rsi rdi r12 r13 r15} GC regs: 00000000 {} => 000090E0 {rbp rsi rdi r12 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB47: G_M38507_IG38: ; offs=00047FH, funclet=00, bbWeight=0.50 Mapped BB47 to G_M38507_IG39 Label: IG39, GCvars=00000000000000000000000100000000 {V08}, gcrefRegs=000090E0 {rbp rsi rdi r12 r15}, byrefRegs=00000000 {} Scope info: begin block BB47, IL range [1F5..1F6) Added IP mapping: 0x0219 STACK_EMPTY (G_M38507_IG39,ins#0,ofs#0) label Generating: N1041 (???,???) [001394] ------------ IL_OFFSET void IL offset: 0x219 REG NA Generating: N1043 ( 1, 1) [000190] ------------ t190 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t190 ref Generating: N1045 ( 2, 2) [001056] -c---------- t1056 = * LEA(b+60) byref REG NA Generating: N1047 ( 1, 1) [000193] ------------ t193 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t193 ref Generating: N1049 ( 2, 2) [001075] -c---------- t1075 = * LEA(b+60) byref REG NA /--* t1075 byref Generating: N1051 ( 4, 4) [000194] n---GO------ t194 = * IND int REG rcx IN00e0: mov ecx, dword ptr [rsi+60] /--* t194 int Generating: N1053 ( 4, 4) [001061] DA--GO------ * STORE_LCL_VAR int V63 tmp49 d:1 rcx REG rcx V63 in reg rcx is becoming live [001061] Live regs: 0000B0E8 {rbx rbp rsi rdi r12 r13 r15} => 0000B0EA {rcx rbx rbp rsi rdi r12 r13 r15} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10 V76} => {V00 V01 V02 V04 V05 V06 V07 V08 V10 V63 V76} Generating: N1055 ( 1, 1) [001062] ------------ t1062 = LCL_VAR int V63 tmp49 u:1 rcx REG rcx Generating: N1057 ( 1, 1) [001330] -c---------- t1330 = LCL_VAR int V76 cse11 NA (last use) REG NA /--* t1062 int +--* t1330 int Generating: N1059 ( 6, 9) [001065] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void REG NA Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10 V63 V76} => {V00 V01 V02 V04 V05 V06 V07 V08 V10 V63} IN00e1: cmp ecx, dword ptr [V76 rsp+5CH] IN00e2: jae L_M38507_BB69 Generating: N1061 ( 1, 1) [001059] ------------ t1059 = LCL_VAR ref V04 loc0 u:1 r15 REG r15 Generating: N1063 ( 1, 1) [001063] ------------ t1063 = LCL_VAR int V63 tmp49 u:1 rcx (last use) REG rcx /--* t1063 int Generating: N1065 ( 2, 3) [001066] ------------ t1066 = * CAST long <- int REG r9 V63 in reg rcx is becoming dead [001063] Live regs: 0000B0EA {rcx rbx rbp rsi rdi r12 r13 r15} => 0000B0E8 {rbx rbp rsi rdi r12 r13 r15} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10 V63} => {V00 V01 V02 V04 V05 V06 V07 V08 V10} IN00e3: movsxd r9, ecx Generating: N1067 ( 1, 1) [001076] -c---------- t1076 = CNS_INT long 3 REG NA $24b /--* t1066 long +--* t1076 long Generating: N1069 ( 7, 7) [001077] ------------ t1077 = * MUL long REG rcx IN00e4: lea rcx, [r9+2*r9] /--* t1059 ref +--* t1077 long Generating: N1071 ( 32, 35) [001058] -c---------- t1058 = * LEA(b+(i*8)+36) byref REG NA /--* t1058 byref Generating: N1073 ( 34, 37) [000197] *--XGO------ t197 = * IND int REG rcx IN00e5: mov ecx, dword ptr [r15+8*rcx+36] /--* t197 int Generating: N1075 ( 35, 38) [001079] ---XGO------ t1079 = * NEG int REG rcx IN00e6: neg ecx Generating: N1077 ( 1, 1) [000191] -c---------- t191 = CNS_INT int -3 REG NA $e1 /--* t1079 int +--* t191 int Generating: N1079 ( 37, 40) [000198] ---XGO------ t198 = * ADD int REG rcx IN00e7: add ecx, -3 /--* t1056 byref +--* t198 int Generating: N1081 (???,???) [001395] -A-XGO------ * STOREIND int REG NA IN00e8: mov dword ptr [rsi+60], ecx Added IP mapping: 0x0233 STACK_EMPTY (G_M38507_IG39,ins#9,ofs#33) Generating: N1083 (???,???) [001396] ------------ IL_OFFSET void IL offset: 0x233 REG NA Generating: N1085 ( 1, 1) [000202] -c---------- t202 = LCL_VAR ref V00 this u:1 rsi REG NA $100 /--* t202 ref Generating: N1087 ( 2, 2) [001083] -c---------- t1083 = * LEA(b+64) byref REG NA /--* t1083 byref Generating: N1089 ( 4, 4) [000203] nc--GO------ t203 = * IND int REG NA Generating: N1091 ( 1, 1) [000204] -c---------- t204 = CNS_INT int -1 REG NA $c4 /--* t203 int +--* t204 int Generating: N1093 ( 6, 6) [000205] -c--GO------ t205 = * ADD int REG NA Generating: N1095 ( 1, 1) [000201] ------------ t201 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t201 ref Generating: N1097 ( 2, 2) [001081] -c---------- t1081 = * LEA(b+64) byref REG NA /--* t1081 byref +--* t205 int Generating: N1099 (???,???) [001397] -A--GO------ * STOREIND int REG NA IN00e9: dec dword ptr [rsi+64] IN00ea: jmp L_M38507_BB55 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 47 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG35,ins#7,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG37,ins#6,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 10: [rbx [ (G_M38507_IG38,ins#4,ofs#15), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 47 =============== Generating BB48 [243..252) -> BB54 (cond), preds={BB44} succs={BB49,BB54} flags=0x00000000.20110020: i label idxlen LIR BB48 IN (9)={V76 V07 V00 V06 V01 V73 V05 V02 V08 } + ByrefExposed + GcHeap OUT(10)={ V07 V00 V06 V01 V73 V05 V02 V08 V13 V75} + ByrefExposed + GcHeap Recording Var Locations at start of BB48 V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V02(rbp) Change life 00000000000000000000000300050236 {V00 V01 V02 V04 V05 V06 V07 V08 V10} -> 00000000000000000000000100050633 {V00 V01 V02 V05 V06 V07 V08 V73 V76} V04 in reg r15 is becoming dead [------] Live regs: (unchanged) 00000000 {} V10 in reg rbx is becoming dead [------] Live regs: (unchanged) 00000000 {} V73 in reg r14 is becoming live [------] Live regs: 00000000 {} => 00004000 {r14} Live regs: 00004000 {r14} => 000070E0 {rbp rsi rdi r12 r13 r14} GC regs: 00004000 {r14} => 000050E0 {rbp rsi rdi r12 r14} Byref regs: (unchanged) 00000000 {} L_M38507_BB48: G_M38507_IG39: ; offs=0004CFH, funclet=00, bbWeight=0.50 Mapped BB48 to G_M38507_IG40 Label: IG40, GCvars=00000000000000000000000100000000 {V08}, gcrefRegs=000050E0 {rbp rsi rdi r12 r14}, byrefRegs=00000000 {} Scope info: begin block BB48, IL range [243..252) Added IP mapping: 0x0243 STACK_EMPTY (G_M38507_IG40,ins#0,ofs#0) label Generating: N1103 (???,???) [001398] ------------ IL_OFFSET void IL offset: 0x243 REG NA Generating: N1105 ( 1, 1) [000072] ------------ t72 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t72 ref Generating: N1107 ( 2, 2) [001085] -c---------- t1085 = * LEA(b+56) byref REG NA /--* t1085 byref Generating: N1109 ( 4, 4) [000073] n---GO------ t73 = * IND int REG rcx IN00eb: mov ecx, dword ptr [rsi+56] /--* t73 int Generating: N1111 ( 8, 7) [001311] DA--GO------ * STORE_LCL_VAR int V75 cse10 d:1 rcx REG rcx V75 in reg rcx is becoming live [001311] Live regs: 000070E0 {rbp rsi rdi r12 r13 r14} => 000070E2 {rcx rbp rsi rdi r12 r13 r14} Live vars: {V00 V01 V02 V05 V06 V07 V08 V73 V76} => {V00 V01 V02 V05 V06 V07 V08 V73 V75 V76} Generating: N1113 ( 3, 2) [001312] ------------ t1312 = LCL_VAR int V75 cse10 u:1 rcx REG rcx /--* t1312 int Generating: N1115 ( 15, 12) [000075] DA--GO------ * STORE_LCL_VAR int V13 loc9 d:1 rbx REG rbx IN00ec: mov ebx, ecx V13 in reg rbx is becoming live [000075] Live regs: 000070E2 {rcx rbp rsi rdi r12 r13 r14} => 000070EA {rcx rbx rbp rsi rdi r12 r13 r14} Live vars: {V00 V01 V02 V05 V06 V07 V08 V73 V75 V76} => {V00 V01 V02 V05 V06 V07 V08 V13 V73 V75 V76} New debug range: first Added IP mapping: 0x024B STACK_EMPTY (G_M38507_IG40,ins#2,ofs#5) Generating: N1117 (???,???) [001399] ------------ IL_OFFSET void IL offset: 0x24b REG NA Generating: N1119 ( 1, 1) [001331] -c---------- t1331 = LCL_VAR int V76 cse11 NA (last use) REG NA Generating: N1121 ( 3, 2) [000076] ------------ t76 = LCL_VAR int V13 loc9 u:1 rbx REG rbx /--* t1331 int +--* t76 int Generating: N1123 ( 5, 4) [000079] N------N-U-- * NE void REG NA Live vars: {V00 V01 V02 V05 V06 V07 V08 V13 V73 V75 V76} => {V00 V01 V02 V05 V06 V07 V08 V13 V73 V75} IN00ed: cmp dword ptr [V76 rsp+5CH], ebx Generating: N1125 ( 7, 6) [000080] ------------ * JTRUE void REG NA IN00ee: jne L_M38507_BB54 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 48 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG35,ins#7,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG36,ins#3,ofs#14), (G_M38507_IG39,ins#11,ofs#41) ]; ] IL Var Num 5: [r12 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG37,ins#6,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 10: [rbx [ (G_M38507_IG38,ins#4,ofs#15), (G_M38507_IG39,ins#11,ofs#41) ]; ] IL Var Num 13: [rbx [ (G_M38507_IG40,ins#2,ofs#5), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 48 =============== Generating BB49 [252..261) -> BB51 (cond), preds={BB48} succs={BB50,BB51} flags=0x00000002.20180020: i hascall gcsafe idxlen LIR BB49 IN (9)={V07 V00 V06 V01 V73 V05 V02 V13 V75} + ByrefExposed + GcHeap OUT(13)={V07 V00 V06 V01 V73 V05 V02 V53 V58 V54 V52 V13 V72 } + ByrefExposed + GcHeap Recording Var Locations at start of BB49 V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V02(rbp) V13(rbx) V75(rcx) Change life 00000000000000001200000100050632 {V00 V01 V02 V05 V06 V07 V08 V13 V73 V75} -> 00000000000000001200000000050632 {V00 V01 V02 V05 V06 V07 V13 V73 V75} V08 becoming dead Live regs: 00000000 {} => 000070EA {rcx rbx rbp rsi rdi r12 r13 r14} GC regs: 00000000 {} => 000050E0 {rbp rsi rdi r12 r14} Byref regs: (unchanged) 00000000 {} L_M38507_BB49: Scope info: begin block BB49, IL range [252..261) Added IP mapping: 0x0252 STACK_EMPTY (G_M38507_IG40,ins#4,ofs#15) label Generating: N1129 (???,???) [001400] ------------ IL_OFFSET void IL offset: 0x252 REG NA Generating: N1131 ( 3, 2) [001314] ------------ t1314 = LCL_VAR int V75 cse10 u:1 rcx (last use) REG rcx /--* t1314 int Generating: N1133 (???,???) [001487] ------------ t1487 = * PUTARG_REG int REG rcx V75 in reg rcx is becoming dead [001314] Live regs: 000070EA {rcx rbx rbp rsi rdi r12 r13 r14} => 000070E8 {rbx rbp rsi rdi r12 r13 r14} Live vars: {V00 V01 V02 V05 V06 V07 V13 V73 V75} => {V00 V01 V02 V05 V06 V07 V13 V73} /--* t1487 int arg0 in rcx Generating: N1135 ( 17, 8) [000702] --CXG------- t702 = * CALL int System.Collections.HashHelpers.ExpandPrime REG rax $1d7 Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=000050E0 {rbp rsi rdi r12 r14}, byrefRegs=00000000 {} IN00ef: call System.Collections.HashHelpers:ExpandPrime(int):int /--* t702 int Generating: N1137 ( 21, 11) [001090] DA-XG-----L- * STORE_LCL_VAR int V64 tmp50 d:1 rdx REG rdx IN00f0: mov edx, eax V64 in reg rdx is becoming live [001090] Live regs: 000070E8 {rbx rbp rsi rdi r12 r13 r14} => 000070EC {rdx rbx rbp rsi rdi r12 r13 r14} Live vars: {V00 V01 V02 V05 V06 V07 V13 V73} => {V00 V01 V02 V05 V06 V07 V13 V64 V73} Generating: N1139 ( 3, 2) [001091] ------------ t1091 = LCL_VAR int V64 tmp50 u:1 rdx (last use) REG rdx $1d7 /--* t1091 int Generating: N1141 (???,???) [001488] ------------ t1488 = * PUTARG_REG int REG rdx V64 in reg rdx is becoming dead [001091] Live regs: 000070EC {rdx rbx rbp rsi rdi r12 r13 r14} => 000070E8 {rbx rbp rsi rdi r12 r13 r14} Live vars: {V00 V01 V02 V05 V06 V07 V13 V64 V73} => {V00 V01 V02 V05 V06 V07 V13 V73} Generating: N1143 ( 1, 1) [000163] ------------ t163 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t163 ref Generating: N1145 (???,???) [001489] ------------ t1489 = * PUTARG_REG ref REG rcx IN00f1: mov rcx, rsi GC regs: 000050E0 {rbp rsi rdi r12 r14} => 000050E2 {rcx rbp rsi rdi r12 r14} Generating: N1147 ( 1, 1) [000704] ------------ t704 = CNS_INT int 0 REG r8 $c0 IN00f2: xor r8d, r8d /--* t704 int Generating: N1149 (???,???) [001490] ------------ t1490 = * PUTARG_REG int REG r8 /--* t1488 int arg1 in rdx +--* t1489 ref this in rcx +--* t1490 int arg2 in r8 Generating: N1151 ( 43, 24) [000705] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize REG NA $VN.Void GC regs: 000050E2 {rcx rbp rsi rdi r12 r14} => 000050E0 {rbp rsi rdi r12 r14} Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=000050E0 {rbp rsi rdi r12 r14}, byrefRegs=00000000 {} IN00f3: call System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize(int,bool):this Added IP mapping: 0x0258 STACK_EMPTY (G_M38507_IG40,ins#9,ofs#33) Generating: N1153 (???,???) [001401] ------------ IL_OFFSET void IL offset: 0x258 REG NA Generating: N1155 ( 1, 1) [000165] ------------ t165 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t165 ref Generating: N1157 ( 2, 2) [001095] -c---------- t1095 = * LEA(b+8) byref REG NA /--* t1095 byref Generating: N1159 ( 4, 4) [000709] n---GO------ t709 = * IND ref REG r15 IN00f4: mov r15, gword ptr [rsi+8] GC regs: 000050E0 {rbp rsi rdi r12 r14} => 0000D0E0 {rbp rsi rdi r12 r14 r15} /--* t709 ref Generating: N1161 ( 8, 7) [000711] DA--GO------ * STORE_LCL_VAR ref V52 tmp38 d:1 r15 REG r15 GC regs: 0000D0E0 {rbp rsi rdi r12 r14 r15} => 000050E0 {rbp rsi rdi r12 r14} V52 in reg r15 is becoming live [000711] Live regs: 000070E8 {rbx rbp rsi rdi r12 r13 r14} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V05 V06 V07 V13 V73} => {V00 V01 V02 V05 V06 V07 V13 V52 V73} GC regs: 000050E0 {rbp rsi rdi r12 r14} => 0000D0E0 {rbp rsi rdi r12 r14 r15} genIPmappingAdd: ignoring duplicate IL offset 0x258 Generating: N1163 (???,???) [001402] ------------ IL_OFFSET void IL offset: 0x258 REG NA Generating: N1165 ( 3, 2) [000713] ------------ t713 = LCL_VAR ref V52 tmp38 u:1 r15 REG r15 /--* t713 ref Generating: N1167 (???,???) [001450] -c---------- t1450 = * LEA(b+8) ref REG NA /--* t1450 ref Generating: N1169 ( 5, 4) [000714] ---X-------- t714 = * IND int REG rax IN00f5: mov eax, dword ptr [r15+8] /--* t714 int Generating: N1171 ( 9, 7) [001286] DA-X-------- * STORE_LCL_VAR int V72 cse7 d:1 rax REG rax V72 in reg rax is becoming live [001286] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V73} => {V00 V01 V02 V05 V06 V07 V13 V52 V72 V73} Generating: N1173 ( 3, 2) [001287] -----------Z t1287 = LCL_VAR int V72 cse7 u:1 rax REG rax /--* t1287 int Generating: N1175 ( 12, 9) [000760] DA-X-------- * STORE_LCL_VAR int V53 tmp39 d:1 r8 REG r8 IN00f6: mov dword ptr [V72 rsp+60H], eax V72 in reg rax is becoming dead [001287] Live regs: 0000F0E9 {rax rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} IN00f7: mov r8d, eax V53 in reg r8 is becoming live [000760] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F1E8 {rbx rbp rsi rdi r8 r12 r13 r14 r15} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V72 V73} => {V00 V01 V02 V05 V06 V07 V13 V52 V53 V72 V73} genIPmappingAdd: ignoring duplicate IL offset 0x258 Generating: N1177 (???,???) [001403] ------------ IL_OFFSET void IL offset: 0x258 REG NA Generating: N1179 ( 1, 1) [000715] ------------ t715 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t715 ref Generating: N1181 ( 2, 2) [001097] -c---------- t1097 = * LEA(b+48) byref REG NA /--* t1097 byref Generating: N1183 ( 4, 4) [000716] n---GO------ t716 = * IND long REG r9 IN00f8: mov r9, qword ptr [rsi+48] /--* t716 long Generating: N1185 ( 8, 7) [000762] DA--GO------ * STORE_LCL_VAR long V54 tmp40 d:1 NA REG NA IN00f9: mov qword ptr [V54 rsp+68H], r9 Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V53 V72 V73} => {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V72 V73} genIPmappingAdd: ignoring duplicate IL offset 0x258 Generating: N1187 (???,???) [001404] ------------ IL_OFFSET void IL offset: 0x258 REG NA Generating: N1189 ( 1, 1) [000728] -----------Z t728 = LCL_VAR int V53 tmp39 u:1 r8 REG r8 Generating: N1191 ( 1, 4) [000729] -c---------- t729 = CNS_INT int 0x7FFFFFFF REG NA $ce /--* t728 int +--* t729 int Generating: N1193 ( 6, 6) [000730] N--------U-- t730 = * LE int REG rcx IN00fa: mov dword ptr [V53 rsp+70H], r8d V53 in reg r8 is becoming dead [000728] Live regs: 0000F1E8 {rbx rbp rsi rdi r8 r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} IN00fb: cmp r8d, 0xD1FFAB1E IN00fc: setbe cl IN00fd: movzx rcx, cl /--* t730 int Generating: N1195 ( 10, 9) [000773] DA---------- * STORE_LCL_VAR int V56 tmp42 d:1 rcx REG rcx V56 in reg rcx is becoming live [000773] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V72 V73} => {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V56 V72 V73} genIPmappingAdd: ignoring duplicate IL offset 0x258 Generating: N1197 (???,???) [001405] ------------ IL_OFFSET void IL offset: 0x258 REG NA genIPmappingAdd: ignoring duplicate IL offset 0x258 Generating: N1199 (???,???) [001406] ------------ IL_OFFSET void IL offset: 0x258 REG NA Generating: N1201 ( 1, 1) [001302] ------------ t1302 = LCL_VAR ref V73 cse8 u:1 r14 REG r14 $105 /--* t1302 ref Generating: N1203 ( 5, 4) [000785] DA--G------- * STORE_LCL_VAR ref V58 tmp44 d:1 rdx REG rdx IN00fe: mov rdx, r14 V58 in reg rdx is becoming live [000785] Live regs: 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EE {rcx rdx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V56 V72 V73} => {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V56 V58 V72 V73} GC regs: 0000D0E0 {rbp rsi rdi r12 r14 r15} => 0000D0E4 {rdx rbp rsi rdi r12 r14 r15} genIPmappingAdd: ignoring duplicate IL offset 0x258 Generating: N1205 (???,???) [001407] ------------ IL_OFFSET void IL offset: 0x258 REG NA Generating: N1207 ( 3, 2) [000775] ------------ t775 = LCL_VAR int V56 tmp42 u:1 rcx (last use) REG rcx Generating: N1209 ( 1, 1) [000776] -c---------- t776 = CNS_INT int 0 REG NA $c0 /--* t775 int +--* t776 int Generating: N1211 ( 5, 4) [000777] J------N---- * NE void REG NA V56 in reg rcx is becoming dead [000775] Live regs: 0000F0EE {rcx rdx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EC {rdx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V56 V58 V72 V73} => {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V58 V72 V73} IN00ff: test ecx, ecx Generating: N1213 ( 7, 6) [000778] ------------ * JTRUE void REG NA IN0100: jne L_M38507_BB51 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 49 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG35,ins#7,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG37,ins#6,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG36,ins#3,ofs#14), (G_M38507_IG40,ins#4,ofs#15) ]; ] IL Var Num 13: [rbx [ (G_M38507_IG40,ins#2,ofs#5), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 49 =============== Generating BB50 [258..259), preds={BB49} succs={BB51} flags=0x00000002.20080020: i hascall gcsafe LIR BB50 IN (13)={V07 V00 V06 V01 V73 V05 V02 V53 V58 V54 V52 V13 V72} + ByrefExposed + GcHeap OUT(12)={V07 V00 V06 V01 V73 V05 V02 V53 V54 V52 V13 V72} + ByrefExposed + GcHeap Recording Var Locations at start of BB50 V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V02(rbp) V58(rdx) V52(r15) V13(rbx) Liveness not changing: 00000000000000000702000800850632 {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V58 V72 V73} Live regs: 00000000 {} => 0000F0EC {rdx rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E4 {rdx rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB50: Scope info: begin block BB50, IL range [258..259) genIPmappingAdd: ignoring duplicate IL offset 0x258 Generating: N1217 (???,???) [001408] ------------ IL_OFFSET void IL offset: 0x258 REG NA Generating: N1219 ( 3, 2) [000779] ------------ t779 = LCL_VAR ref V58 tmp44 u:1 rdx REG rdx $105 /--* t779 ref Generating: N1221 (???,???) [001491] ------------ t1491 = * PUTARG_REG ref REG rcx IN0101: mov rcx, rdx GC regs: 0000D0E4 {rdx rbp rsi rdi r12 r14 r15} => 0000D0E6 {rcx rdx rbp rsi rdi r12 r14 r15} Generating: N1223 ( 3, 2) [000780] ------------ t780 = LCL_VAR ref V58 tmp44 u:1 rdx (last use) REG rdx $105 /--* t780 ref Generating: N1225 (???,???) [001492] ------------ t1492 = * PUTARG_REG ref REG rdx V58 in reg rdx is becoming dead [000780] Live regs: 0000F0EC {rdx rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V58 V72 V73} => {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V72 V73} GC regs: 0000D0E6 {rcx rdx rbp rsi rdi r12 r14 r15} => 0000D0E2 {rcx rbp rsi rdi r12 r14 r15} GC regs: 0000D0E2 {rcx rbp rsi rdi r12 r14 r15} => 0000D0E6 {rcx rdx rbp rsi rdi r12 r14 r15} /--* t1491 ref arg0 in rcx +--* t1492 ref arg1 in rdx Generating: N1227 ( 20, 11) [000781] --CXG------- * CALL void System.Diagnostics.Debug.Fail REG NA $VN.Void GC regs: 0000D0E6 {rcx rdx rbp rsi rdi r12 r14 r15} => 0000D0E4 {rdx rbp rsi rdi r12 r14 r15} GC regs: 0000D0E4 {rdx rbp rsi rdi r12 r14 r15} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} IN0102: call System.Diagnostics.Debug:Fail(System.String,System.String) //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 50 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG35,ins#7,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG37,ins#6,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 13: [rbx [ (G_M38507_IG40,ins#2,ofs#5), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 50 =============== Generating BB51 [258..259) -> BB53 (cond), preds={BB49,BB50} succs={BB52,BB53} flags=0x00000000.20190020: i label gcsafe idxlen LIR BB51 IN (12)={V07 V00 V06 V01 V73 V05 V02 V53 V54 V52 V13 V72} + ByrefExposed + GcHeap OUT(11)={V07 V00 V06 V01 V05 V02 V61 V55 V52 V13 V72} + ByrefExposed + GcHeap Recording Var Locations at start of BB51 V00(rsi) V06(r13) V01(rdi) V73(r14) V05(r12) V02(rbp) V52(r15) V13(rbx) Liveness not changing: 00000000000000000702000000850632 {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V72 V73} Live regs: 00000000 {} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} GC regs: 00000000 {} => 0000D0E0 {rbp rsi rdi r12 r14 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB51: G_M38507_IG40: ; offs=0004F8H, funclet=00, bbWeight=0.50 Mapped BB51 to G_M38507_IG41 Label: IG41, GCvars=00000000000000000000000000000000 {}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {} Scope info: begin block BB51, IL range [258..259) genIPmappingAdd: ignoring duplicate IL offset 0x258 Generating: N1231 (???,???) [001409] ------------ IL_OFFSET void IL offset: 0x258 REG NA Generating: N1233 ( 3, 2) [000735] -c---------- t735 = LCL_VAR long V54 tmp40 u:1 NA (last use) REG NA Generating: N1235 ( 1, 1) [000166] ------------ t166 = LCL_VAR int V06 loc2 u:1 r13 REG r13 $3c0 /--* t166 int Generating: N1237 ( 2, 3) [000736] ---------U-- t736 = * CAST long <- ulong <- uint REG rdx $310 IN0103: mov edx, r13d /--* t735 long +--* t736 long Generating: N1239 ( 9, 8) [000737] ------------ t737 = * MUL long REG rdx Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V53 V54 V72 V73} => {V00 V01 V02 V05 V06 V07 V13 V52 V53 V72 V73} IN0104: imul rdx, qword ptr [V54 rsp+68H] Generating: N1241 ( 1, 1) [000738] -c---------- t738 = CNS_INT int 32 REG NA $d2 /--* t737 long +--* t738 int Generating: N1243 ( 11, 10) [000739] ------------ t739 = * RSZ long REG rdx IN0105: shr rdx, 32 Generating: N1245 ( 1, 1) [000741] -c---------- t741 = CNS_INT long 1 REG NA $247 /--* t739 long +--* t741 long Generating: N1247 ( 13, 12) [000742] ------------ t742 = * ADD long REG rdx IN0106: inc rdx Generating: N1249 ( 1, 1) [000743] -----------z t743 = LCL_VAR int V53 tmp39 u:1 r8 REG r8 /--* t743 int Generating: N1251 ( 2, 3) [000744] ---------U-- t744 = * CAST long <- ulong <- uint REG rcx IN0107: mov r8d, dword ptr [V53 rsp+70H] V53 in reg r8 is becoming live [000743] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F1E8 {rbx rbp rsi rdi r8 r12 r13 r14 r15} IN0108: mov ecx, r8d /--* t742 long +--* t744 long Generating: N1253 ( 19, 18) [000745] ------------ t745 = * MUL long REG rdx IN0109: imul rdx, rcx Generating: N1255 ( 1, 1) [000746] -c---------- t746 = CNS_INT int 32 REG NA $d2 /--* t745 long +--* t746 int Generating: N1257 ( 21, 20) [000747] ------------ t747 = * RSZ long REG rdx IN010a: shr rdx, 32 /--* t747 long Generating: N1259 ( 22, 22) [000748] ------------ t748 = * CAST int <- uint <- long REG r9 IN010b: mov r9d, edx /--* t748 int Generating: N1261 ( 26, 25) [000750] DA---------- * STORE_LCL_VAR int V55 tmp41 d:1 r9 REG r9 V55 in reg r9 is becoming live [000750] Live regs: 0000F1E8 {rbx rbp rsi rdi r8 r12 r13 r14 r15} => 0000F3E8 {rbx rbp rsi rdi r8 r9 r12 r13 r14 r15} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V53 V72 V73} => {V00 V01 V02 V05 V06 V07 V13 V52 V53 V55 V72 V73} genIPmappingAdd: ignoring duplicate IL offset 0x258 Generating: N1263 (???,???) [001410] ------------ IL_OFFSET void IL offset: 0x258 REG NA Generating: N1265 ( 1, 1) [000752] ------------ t752 = LCL_VAR int V06 loc2 u:1 r13 REG r13 $3c0 Generating: N1267 ( 1, 1) [000753] ------------ t753 = LCL_VAR int V53 tmp39 u:1 r8 (last use) REG r8 /--* t752 int +--* t753 int Generating: N1269 ( 22, 5) [000754] ---X-------- t754 = * UMOD int REG rdx V53 in reg r8 is becoming dead [000753] Live regs: 0000F3E8 {rbx rbp rsi rdi r8 r9 r12 r13 r14 r15} => 0000F2E8 {rbx rbp rsi rdi r9 r12 r13 r14 r15} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V53 V55 V72 V73} => {V00 V01 V02 V05 V06 V07 V13 V52 V55 V72 V73} IN010c: mov eax, r13d IN010d: xor rdx, rdx IN010e: div edx:eax, r8d Generating: N1271 ( 3, 2) [000751] -----------Z t751 = LCL_VAR int V55 tmp41 u:1 r9 REG r9 /--* t754 int +--* t751 int Generating: N1273 ( 29, 8) [000755] ---X-------- t755 = * EQ int REG rcx IN010f: mov dword ptr [V55 rsp+64H], r9d V55 in reg r9 is becoming dead [000751] Live regs: 0000F2E8 {rbx rbp rsi rdi r9 r12 r13 r14 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} IN0110: cmp edx, r9d IN0111: sete cl IN0112: movzx rcx, cl /--* t755 int Generating: N1275 ( 33, 11) [000796] DA-X-------- * STORE_LCL_VAR int V59 tmp45 d:1 rcx REG rcx V59 in reg rcx is becoming live [000796] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V55 V72 V73} => {V00 V01 V02 V05 V06 V07 V13 V52 V55 V59 V72 V73} genIPmappingAdd: ignoring duplicate IL offset 0x258 Generating: N1277 (???,???) [001411] ------------ IL_OFFSET void IL offset: 0x258 REG NA genIPmappingAdd: ignoring duplicate IL offset 0x258 Generating: N1279 (???,???) [001412] ------------ IL_OFFSET void IL offset: 0x258 REG NA Generating: N1281 ( 1, 1) [001304] ------------ t1304 = LCL_VAR ref V73 cse8 u:1 r14 (last use) REG r14 $105 /--* t1304 ref Generating: N1283 ( 5, 4) [000808] DA--G------- * STORE_LCL_VAR ref V61 tmp47 d:1 rdx REG rdx V73 in reg r14 is becoming dead [001304] Live regs: 0000F0EA {rcx rbx rbp rsi rdi r12 r13 r14 r15} => 0000B0EA {rcx rbx rbp rsi rdi r12 r13 r15} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V55 V59 V72 V73} => {V00 V01 V02 V05 V06 V07 V13 V52 V55 V59 V72} GC regs: 0000D0E0 {rbp rsi rdi r12 r14 r15} => 000090E0 {rbp rsi rdi r12 r15} IN0113: mov rdx, r14 V61 in reg rdx is becoming live [000808] Live regs: 0000B0EA {rcx rbx rbp rsi rdi r12 r13 r15} => 0000B0EE {rcx rdx rbx rbp rsi rdi r12 r13 r15} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V55 V59 V72} => {V00 V01 V02 V05 V06 V07 V13 V52 V55 V59 V61 V72} GC regs: 000090E0 {rbp rsi rdi r12 r15} => 000090E4 {rdx rbp rsi rdi r12 r15} genIPmappingAdd: ignoring duplicate IL offset 0x258 Generating: N1285 (???,???) [001413] ------------ IL_OFFSET void IL offset: 0x258 REG NA Generating: N1287 ( 3, 2) [000798] ------------ t798 = LCL_VAR int V59 tmp45 u:1 rcx (last use) REG rcx Generating: N1289 ( 1, 1) [000799] -c---------- t799 = CNS_INT int 0 REG NA $c0 /--* t798 int +--* t799 int Generating: N1291 ( 5, 4) [000800] J------N---- * NE void REG NA V59 in reg rcx is becoming dead [000798] Live regs: 0000B0EE {rcx rdx rbx rbp rsi rdi r12 r13 r15} => 0000B0EC {rdx rbx rbp rsi rdi r12 r13 r15} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V55 V59 V61 V72} => {V00 V01 V02 V05 V06 V07 V13 V52 V55 V61 V72} IN0114: test ecx, ecx Generating: N1293 ( 7, 6) [000801] ------------ * JTRUE void REG NA IN0115: jne L_M38507_BB53 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 51 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG35,ins#7,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG37,ins#6,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 13: [rbx [ (G_M38507_IG40,ins#2,ofs#5), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 51 =============== Generating BB52 [258..259), preds={BB51} succs={BB53} flags=0x00000002.20080020: i hascall gcsafe LIR BB52 IN (11)={V07 V00 V06 V01 V05 V02 V61 V55 V52 V13 V72} + ByrefExposed + GcHeap OUT(10)={V07 V00 V06 V01 V05 V02 V55 V52 V13 V72} + ByrefExposed + GcHeap Recording Var Locations at start of BB52 V00(rsi) V06(r13) V01(rdi) V05(r12) V02(rbp) V61(rdx) V52(r15) V13(rbx) Liveness not changing: 00000000000000000700081000050232 {V00 V01 V02 V05 V06 V07 V13 V52 V55 V61 V72} Live regs: 00000000 {} => 0000B0EC {rdx rbx rbp rsi rdi r12 r13 r15} GC regs: 00000000 {} => 000090E4 {rdx rbp rsi rdi r12 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB52: Scope info: begin block BB52, IL range [258..259) genIPmappingAdd: ignoring duplicate IL offset 0x258 Generating: N1297 (???,???) [001414] ------------ IL_OFFSET void IL offset: 0x258 REG NA Generating: N1299 ( 3, 2) [000802] ------------ t802 = LCL_VAR ref V61 tmp47 u:1 rdx REG rdx $105 /--* t802 ref Generating: N1301 (???,???) [001493] ------------ t1493 = * PUTARG_REG ref REG rcx IN0116: mov rcx, rdx GC regs: 000090E4 {rdx rbp rsi rdi r12 r15} => 000090E6 {rcx rdx rbp rsi rdi r12 r15} Generating: N1303 ( 3, 2) [000803] ------------ t803 = LCL_VAR ref V61 tmp47 u:1 rdx (last use) REG rdx $105 /--* t803 ref Generating: N1305 (???,???) [001494] ------------ t1494 = * PUTARG_REG ref REG rdx V61 in reg rdx is becoming dead [000803] Live regs: 0000B0EC {rdx rbx rbp rsi rdi r12 r13 r15} => 0000B0E8 {rbx rbp rsi rdi r12 r13 r15} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V55 V61 V72} => {V00 V01 V02 V05 V06 V07 V13 V52 V55 V72} GC regs: 000090E6 {rcx rdx rbp rsi rdi r12 r15} => 000090E2 {rcx rbp rsi rdi r12 r15} GC regs: 000090E2 {rcx rbp rsi rdi r12 r15} => 000090E6 {rcx rdx rbp rsi rdi r12 r15} /--* t1493 ref arg0 in rcx +--* t1494 ref arg1 in rdx Generating: N1307 ( 20, 11) [000804] --CXG------- * CALL void System.Diagnostics.Debug.Fail REG NA $VN.Void GC regs: 000090E6 {rcx rdx rbp rsi rdi r12 r15} => 000090E4 {rdx rbp rsi rdi r12 r15} GC regs: 000090E4 {rdx rbp rsi rdi r12 r15} => 000090E0 {rbp rsi rdi r12 r15} Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=000090E0 {rbp rsi rdi r12 r15}, byrefRegs=00000000 {} IN0117: call System.Diagnostics.Debug:Fail(System.String,System.String) //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 52 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG35,ins#7,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG37,ins#6,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 13: [rbx [ (G_M38507_IG40,ins#2,ofs#5), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 52 =============== Generating BB53 [258..259), preds={BB51,BB52} succs={BB54} flags=0x00000000.20190020: i label gcsafe idxlen LIR BB53 IN (10)={V07 V00 V06 V01 V05 V02 V55 V52 V13 V72} + ByrefExposed + GcHeap OUT(8)={V07 V00 V06 V01 V05 V02 V08 V13 } + ByrefExposed + GcHeap Recording Var Locations at start of BB53 V00(rsi) V06(r13) V01(rdi) V05(r12) V02(rbp) V52(r15) V13(rbx) Liveness not changing: 00000000000000000700080000050232 {V00 V01 V02 V05 V06 V07 V13 V52 V55 V72} Live regs: 00000000 {} => 0000B0E8 {rbx rbp rsi rdi r12 r13 r15} GC regs: 00000000 {} => 000090E0 {rbp rsi rdi r12 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB53: G_M38507_IG41: ; offs=000556H, funclet=00, bbWeight=0.50 Mapped BB53 to G_M38507_IG42 Label: IG42, GCvars=00000000000000000000000000000000 {}, gcrefRegs=000090E0 {rbp rsi rdi r12 r15}, byrefRegs=00000000 {} Scope info: begin block BB53, IL range [258..259) genIPmappingAdd: ignoring duplicate IL offset 0x258 Generating: N1311 (???,???) [001415] ------------ IL_OFFSET void IL offset: 0x258 REG NA Generating: N1313 ( 3, 2) [000758] -----------z t758 = LCL_VAR int V55 tmp41 u:1 r9 REG r9 Generating: N1315 ( 3, 2) [001289] -c---------- t1289 = LCL_VAR int V72 cse7 u:1 NA (last use) REG NA /--* t758 int +--* t1289 int Generating: N1317 ( 10, 11) [001105] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void REG NA IN0118: mov r9d, dword ptr [V55 rsp+64H] V55 in reg r9 is becoming live [000758] Live regs: 0000B0E8 {rbx rbp rsi rdi r12 r13 r15} => 0000B2E8 {rbx rbp rsi rdi r9 r12 r13 r15} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V55 V72} => {V00 V01 V02 V05 V06 V07 V13 V52 V55} IN0119: cmp r9d, dword ptr [V72 rsp+60H] IN011a: jae L_M38507_BB69 Generating: N1319 ( 3, 2) [001102] ------------ t1102 = LCL_VAR ref V52 tmp38 u:1 r15 (last use) REG r15 Generating: N1321 ( 3, 2) [001103] ------------ t1103 = LCL_VAR int V55 tmp41 u:1 r9 (last use) REG r9 /--* t1103 int Generating: N1323 ( 4, 4) [001106] ------------ t1106 = * CAST long <- int REG rdx V55 in reg r9 is becoming dead [001103] Live regs: 0000B2E8 {rbx rbp rsi rdi r9 r12 r13 r15} => 0000B0E8 {rbx rbp rsi rdi r12 r13 r15} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52 V55} => {V00 V01 V02 V05 V06 V07 V13 V52} IN011b: movsxd rdx, r9d /--* t1102 ref +--* t1106 long Generating: N1325 ( 9, 8) [001111] -------N---- t1111 = * LEA(b+(i*4)+16) byref REG rax V52 in reg r15 is becoming dead [001102] Live regs: 0000B0E8 {rbx rbp rsi rdi r12 r13 r15} => 000030E8 {rbx rbp rsi rdi r12 r13} Live vars: {V00 V01 V02 V05 V06 V07 V13 V52} => {V00 V01 V02 V05 V06 V07 V13} GC regs: 000090E0 {rbp rsi rdi r12 r15} => 000010E0 {rbp rsi rdi r12} IN011c: lea rax, bword ptr [r15+4*rdx+16] Byref regs: 00000000 {} => 00000001 {rax} /--* t1111 byref Generating: N1327 ( 33, 31) [000722] DA-XG------- * STORE_LCL_VAR byref V51 tmp37 d:1 rax REG rax Byref regs: 00000001 {rax} => 00000000 {} V51 in reg rax is becoming live [000722] Live regs: 000030E8 {rbx rbp rsi rdi r12 r13} => 000030E9 {rax rbx rbp rsi rdi r12 r13} Live vars: {V00 V01 V02 V05 V06 V07 V13} => {V00 V01 V02 V05 V06 V07 V13 V51} Byref regs: 00000000 {} => 00000001 {rax} Generating: N1329 ( 3, 2) [000723] ------------ t723 = LCL_VAR byref V51 tmp37 u:1 rax (last use) REG rax $87 /--* t723 byref Generating: N1331 ( 7, 5) [000170] DA---------- * STORE_LCL_VAR byref V08 loc4 d:4 r14 REG r14 V51 in reg rax is becoming dead [000723] Live regs: 000030E9 {rax rbx rbp rsi rdi r12 r13} => 000030E8 {rbx rbp rsi rdi r12 r13} Live vars: {V00 V01 V02 V05 V06 V07 V13 V51} => {V00 V01 V02 V05 V06 V07 V13} Byref regs: 00000001 {rax} => 00000000 {} IN011d: mov r14, rax V08 in reg r14 is becoming live [000170] Live regs: 000030E8 {rbx rbp rsi rdi r12 r13} => 000070E8 {rbx rbp rsi rdi r12 r13 r14} Live vars: {V00 V01 V02 V05 V06 V07 V13} => {V00 V01 V02 V05 V06 V07 V08 V13} New debug range: not adjacent Byref regs: 00000000 {} => 00004000 {r14} Generating: N001 ( 1, 1) [001515] -----------Z t1515 = LCL_VAR byref V08 loc4 r14 REG r14 IN011e: mov bword ptr [V08 rsp+50H], r14 V08 in reg r14 is becoming dead [001515] Live regs: 000070E8 {rbx rbp rsi rdi r12 r13 r14} => 000030E8 {rbx rbp rsi rdi r12 r13} Byref regs: 00004000 {r14} => 00000000 {} Var V08 becoming live New debug range: not adjacent //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 53 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG35,ins#7,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG37,ins#6,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 8: [r14 [ (G_M38507_IG42,ins#6,ofs#27), (G_M38507_IG42,ins#7,ofs#32) ]; rsp'[80] (1 slot) [ (G_M38507_IG42,ins#7,ofs#32), NON_CLOSED_RANGE ]; ] IL Var Num 13: [rbx [ (G_M38507_IG40,ins#2,ofs#5), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 53 =============== Generating BB54 [261..276), preds={BB48,BB53} succs={BB55} flags=0x00000000.20010020: i label LIR BB54 IN (8)={V07 V00 V06 V01 V05 V02 V08 V13} + ByrefExposed + GcHeap OUT(9)={V07 V04 V00 V06 V01 V05 V02 V08 V10 } + ByrefExposed + GcHeap Recording Var Locations at start of BB54 V00(rsi) V06(r13) V01(rdi) V05(r12) V02(rbp) V13(rbx) Liveness not changing: 00000000000000000200000100050232 {V00 V01 V02 V05 V06 V07 V08 V13} Live regs: 00000000 {} => 000030E8 {rbx rbp rsi rdi r12 r13} GC regs: 00000000 {} => 000010E0 {rbp rsi rdi r12} Byref regs: (unchanged) 00000000 {} L_M38507_BB54: G_M38507_IG42: ; offs=0005A2H, funclet=00, bbWeight=0.50 Mapped BB54 to G_M38507_IG43 Label: IG43, GCvars=00000000000000000000000100000000 {V08}, gcrefRegs=000010E0 {rbp rsi rdi r12}, byrefRegs=00000000 {} Scope info: begin block BB54, IL range [261..276) Added IP mapping: 0x0261 STACK_EMPTY (G_M38507_IG43,ins#0,ofs#0) label Generating: N1335 (???,???) [001416] ------------ IL_OFFSET void IL offset: 0x261 REG NA Generating: N1337 ( 3, 2) [000081] ------------ t81 = LCL_VAR int V13 loc9 u:1 rbx (last use) REG rbx /--* t81 int Generating: N1339 ( 7, 5) [000083] DA---------- * STORE_LCL_VAR int V10 loc6 d:2 rbx REG rbx V13 in reg rbx is becoming dead [000081] Live regs: 000030E8 {rbx rbp rsi rdi r12 r13} => 000030E0 {rbp rsi rdi r12 r13} Live vars: {V00 V01 V02 V05 V06 V07 V08 V13} => {V00 V01 V02 V05 V06 V07 V08} V10 in reg rbx is becoming live [000083] Live regs: 000030E0 {rbp rsi rdi r12 r13} => 000030E8 {rbx rbp rsi rdi r12 r13} Live vars: {V00 V01 V02 V05 V06 V07 V08} => {V00 V01 V02 V05 V06 V07 V08 V10} New debug range: new var or location Added IP mapping: 0x0265 STACK_EMPTY (G_M38507_IG43,ins#0,ofs#0) Generating: N1341 (???,???) [001417] ------------ IL_OFFSET void IL offset: 0x265 REG NA Generating: N1343 ( 3, 2) [000085] ------------ t85 = LCL_VAR int V10 loc6 u:2 rbx REG rbx Generating: N1345 ( 1, 1) [000086] -c---------- t86 = CNS_INT int 1 REG NA $c1 /--* t85 int +--* t86 int Generating: N1347 ( 5, 4) [000087] ------------ t87 = * ADD int REG rdx IN011f: lea edx, [rbx+1] Generating: N1349 ( 1, 1) [000084] ------------ t84 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t84 ref Generating: N1351 ( 2, 2) [001115] -c---------- t1115 = * LEA(b+56) byref REG NA /--* t1115 byref +--* t87 int Generating: N1353 (???,???) [001418] -A--GO------ * STOREIND int REG NA IN0120: mov dword ptr [rsi+56], edx Added IP mapping: 0x026F STACK_EMPTY (G_M38507_IG43,ins#2,ofs#6) Generating: N1355 (???,???) [001419] ------------ IL_OFFSET void IL offset: 0x26f REG NA Generating: N1357 ( 1, 1) [000090] ------------ t90 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t90 ref Generating: N1359 ( 2, 2) [001117] -c---------- t1117 = * LEA(b+16) byref REG NA /--* t1117 byref Generating: N1361 ( 4, 4) [000091] n---GO------ t91 = * IND ref REG r15 IN0121: mov r15, gword ptr [rsi+16] GC regs: 000010E0 {rbp rsi rdi r12} => 000090E0 {rbp rsi rdi r12 r15} /--* t91 ref Generating: N1363 ( 4, 4) [000093] DA--GO------ * STORE_LCL_VAR ref V04 loc0 d:3 r15 REG r15 GC regs: 000090E0 {rbp rsi rdi r12 r15} => 000010E0 {rbp rsi rdi r12} V04 in reg r15 is becoming live [000093] Live regs: 000030E8 {rbx rbp rsi rdi r12 r13} => 0000B0E8 {rbx rbp rsi rdi r12 r13 r15} Live vars: {V00 V01 V02 V05 V06 V07 V08 V10} => {V00 V01 V02 V04 V05 V06 V07 V08 V10} New debug range: new var or location GC regs: 000010E0 {rbp rsi rdi r12} => 000090E0 {rbp rsi rdi r12 r15} //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 54 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG35,ins#7,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 2: [rbp [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG43,ins#3,ofs#10), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG37,ins#6,ofs#31), NON_CLOSED_RANGE ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG42,ins#7,ofs#32), NON_CLOSED_RANGE ]; ] IL Var Num 10: [rbx [ (G_M38507_IG43,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 13: [rbx [ (G_M38507_IG40,ins#2,ofs#5), (G_M38507_IG43,ins#0,ofs#0) ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 54 =============== Generating BB55 [276..2CF) -> BB58 (cond), preds={BB47,BB54} succs={BB56,BB58} flags=0x00000000.20110020: i label idxlen LIR BB55 IN (9)={V07 V04 V00 V06 V01 V05 V02 V08 V10} + ByrefExposed + GcHeap OUT(3)={ V04 V00 V05 } + ByrefExposed + GcHeap Recording Var Locations at start of BB55 V04(r15) V00(rsi) V06(r13) V01(rdi) V05(r12) V02(rbp) V10(rbx) Liveness not changing: 00000000000000000000000300050236 {V00 V01 V02 V04 V05 V06 V07 V08 V10} Live regs: 00000000 {} => 0000B0E8 {rbx rbp rsi rdi r12 r13 r15} GC regs: 00000000 {} => 000090E0 {rbp rsi rdi r12 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB55: G_M38507_IG43: ; offs=0005C2H, funclet=00, bbWeight=0.50 Mapped BB55 to G_M38507_IG44 Label: IG44, GCvars=00000000000000000000000100000000 {V08}, gcrefRegs=000090E0 {rbp rsi rdi r12 r15}, byrefRegs=00000000 {} Scope info: begin block BB55, IL range [276..2CF) Added IP mapping: 0x0276 STACK_EMPTY (G_M38507_IG44,ins#0,ofs#0) label Generating: N1367 (???,???) [001420] ------------ IL_OFFSET void IL offset: 0x276 REG NA Generating: N1369 ( 3, 2) [000095] ------------ t95 = LCL_VAR int V10 loc6 u:1 rbx REG rbx $3cc Generating: N1371 ( 1, 1) [000094] ------------ t94 = LCL_VAR ref V04 loc0 u:2 r15 REG r15 $684 /--* t94 ref Generating: N1373 (???,???) [001452] -c---------- t1452 = * LEA(b+8) ref REG NA /--* t1452 ref Generating: N1375 ( 3, 3) [001120] -c-X-------- t1120 = * IND int REG NA $73d /--* t95 int +--* t1120 int Generating: N1377 ( 10, 12) [001121] ---X-------- * ARR_BOUNDS_CHECK_Rng -> BB69 void REG NA $7cd IN0122: cmp ebx, dword ptr [r15+8] IN0123: jae L_M38507_BB69 Generating: N1379 ( 1, 1) [001118] ------------ t1118 = LCL_VAR ref V04 loc0 u:2 r15 REG r15 $684 Generating: N1381 ( 3, 2) [001119] ------------ t1119 = LCL_VAR int V10 loc6 u:1 rbx REG rbx $3cc /--* t1119 int Generating: N1383 ( 4, 4) [001122] ------------ t1122 = * CAST long <- int REG rdx $6dc IN0124: movsxd rdx, ebx Generating: N1385 ( 1, 1) [001129] -c---------- t1129 = CNS_INT long 3 REG NA $24b /--* t1122 long +--* t1129 long Generating: N1387 ( 9, 8) [001130] ------------ t1130 = * MUL long REG rdx $6dd IN0125: lea rdx, [rdx+2*rdx] /--* t1118 ref +--* t1130 long Generating: N1389 ( 12, 11) [001127] -------N---- t1127 = * LEA(b+(i*8)+16) byref REG r14 IN0126: lea r14, bword ptr [r15+8*rdx+16] Byref regs: 00000000 {} => 00004000 {r14} /--* t1127 byref Generating: N1391 ( 39, 38) [000099] DA-XG------- * STORE_LCL_VAR byref V11 loc7 d:1 r14 REG r14 Byref regs: 00004000 {r14} => 00000000 {} V11 in reg r14 is becoming live [000099] Live regs: 0000B0E8 {rbx rbp rsi rdi r12 r13 r15} => 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10} => {V00 V01 V02 V04 V05 V06 V07 V08 V10 V11} New debug range: first Byref regs: 00000000 {} => 00004000 {r14} Added IP mapping: 0x0280 STACK_EMPTY (G_M38507_IG44,ins#5,ofs#22) Generating: N1393 (???,???) [001421] ------------ IL_OFFSET void IL offset: 0x280 REG NA Generating: N1395 ( 3, 2) [000100] ------------ t100 = LCL_VAR byref V11 loc7 u:1 r14 REG r14 $8c /--* t100 byref Generating: N1397 ( 4, 3) [001133] -c---------- t1133 = * LEA(b+16) byref REG NA Generating: N1399 ( 1, 1) [000101] ------------ t101 = LCL_VAR int V06 loc2 u:1 r13 (last use) REG r13 $3c0 /--* t1133 byref +--* t101 int Generating: N1401 (???,???) [001422] -A-XG------- * STOREIND int REG NA V06 in reg r13 is becoming dead [000101] Live regs: 0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} => 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} Live vars: {V00 V01 V02 V04 V05 V06 V07 V08 V10 V11} => {V00 V01 V02 V04 V05 V07 V08 V10 V11} IN0127: mov dword ptr [r14+16], r13d Added IP mapping: 0x0288 STACK_EMPTY (G_M38507_IG44,ins#6,ofs#26) Generating: N1403 (???,???) [001423] ------------ IL_OFFSET void IL offset: 0x288 REG NA Generating: N1405 ( 3, 2) [000105] -----------z t105 = LCL_VAR byref V08 loc4 u:2 rax REG rax $781 /--* t105 byref Generating: N1407 ( 6, 4) [000106] *--XG------- t106 = * IND int REG rdx IN0128: mov rax, bword ptr [V08 rsp+50H] Byref regs: 00004000 {r14} => 00004001 {rax r14} Byref regs: 00004001 {rax r14} => 00004000 {r14} IN0129: mov edx, dword ptr [rax] Generating: N1409 ( 1, 1) [000107] -c---------- t107 = CNS_INT int -1 REG NA $c4 /--* t106 int +--* t107 int Generating: N1411 ( 8, 6) [000108] ---XG------- t108 = * ADD int REG rdx IN012a: dec edx Generating: N1413 ( 3, 2) [000104] ------------ t104 = LCL_VAR byref V11 loc7 u:1 r14 REG r14 $8c /--* t104 byref Generating: N1415 ( 4, 3) [001135] -c---------- t1135 = * LEA(b+20) byref REG NA /--* t1135 byref +--* t108 int Generating: N1417 (???,???) [001424] -A-XGO------ * STOREIND int REG NA IN012b: mov dword ptr [r14+20], edx Added IP mapping: 0x0294 STACK_EMPTY (G_M38507_IG44,ins#10,ofs#39) Generating: N1419 (???,???) [001425] ------------ IL_OFFSET void IL offset: 0x294 REG NA Generating: N1421 ( 3, 2) [000111] ------------ t111 = LCL_VAR byref V11 loc7 u:1 r14 Zero Fseq[key] REG r14 $8f Generating: N1423 ( 1, 1) [000112] ------------ t112 = LCL_VAR ref V01 arg1 u:1 rdi (last use) REG rdi $101 /--* t111 byref +--* t112 ref Generating: N1425 (???,???) [001426] -A-XG------- * STOREIND ref REG NA V01 in reg rdi is becoming dead [000112] Live regs: 0000D0E8 {rbx rbp rsi rdi r12 r14 r15} => 0000D068 {rbx rbp rsi r12 r14 r15} Live vars: {V00 V01 V02 V04 V05 V07 V08 V10 V11} => {V00 V02 V04 V05 V07 V08 V10 V11} GC regs: 000090E0 {rbp rsi rdi r12 r15} => 00009060 {rbp rsi r12 r15} IN012c: mov rcx, r14 IN012d: mov rdx, rdi NoGC Call: savedSet=0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Call: GCvars=00000000000000000000000100000000 {V08}, gcrefRegs=00009060 {rbp rsi r12 r15}, byrefRegs=00004000 {r14} IN012e: call CORINFO_HELP_CHECKED_ASSIGN_REF Added IP mapping: 0x029C STACK_EMPTY (G_M38507_IG44,ins#13,ofs#50) Generating: N1427 (???,???) [001427] ------------ IL_OFFSET void IL offset: 0x29c REG NA Generating: N1429 ( 3, 2) [000115] ------------ t115 = LCL_VAR byref V11 loc7 u:1 r14 (last use) REG r14 $8c /--* t115 byref Generating: N1431 ( 4, 3) [001137] ------------ t1137 = * LEA(b+8) byref REG rcx V11 in reg r14 is becoming dead [000115] Live regs: 0000D068 {rbx rbp rsi r12 r14 r15} => 00009068 {rbx rbp rsi r12 r15} Live vars: {V00 V02 V04 V05 V07 V08 V10 V11} => {V00 V02 V04 V05 V07 V08 V10} Byref regs: 00004000 {r14} => 00000000 {} IN012f: lea rcx, bword ptr [r14+8] Byref regs: 00000000 {} => 00000002 {rcx} Generating: N1433 ( 1, 1) [000116] ------------ t116 = LCL_VAR ref V02 arg2 u:1 rbp (last use) REG rbp $102 /--* t1137 byref +--* t116 ref Generating: N1435 (???,???) [001428] -A--GO------ * STOREIND ref REG NA Byref regs: 00000002 {rcx} => 00000000 {} V02 in reg rbp is becoming dead [000116] Live regs: 00009068 {rbx rbp rsi r12 r15} => 00009048 {rbx rsi r12 r15} Live vars: {V00 V02 V04 V05 V07 V08 V10} => {V00 V04 V05 V07 V08 V10} GC regs: 00009060 {rbp rsi r12 r15} => 00009040 {rsi r12 r15} IN0130: mov rdx, rbp NoGC Call: savedSet=0000F0E8 {rbx rbp rsi rdi r12 r13 r14 r15} Call: GCvars=00000000000000000000000100000000 {V08}, gcrefRegs=00009040 {rsi r12 r15}, byrefRegs=00000000 {} IN0131: call CORINFO_HELP_CHECKED_ASSIGN_REF Added IP mapping: 0x02A4 STACK_EMPTY (G_M38507_IG44,ins#16,ofs#62) Generating: N1437 (???,???) [001429] ------------ IL_OFFSET void IL offset: 0x2a4 REG NA Generating: N1439 ( 3, 2) [000120] ------------ t120 = LCL_VAR int V10 loc6 u:1 rbx (last use) REG rbx $3cc Generating: N1441 ( 1, 1) [000121] -c---------- t121 = CNS_INT int 1 REG NA $c1 /--* t120 int +--* t121 int Generating: N1443 ( 5, 4) [000122] ------------ t122 = * ADD int REG rbx $804 V10 in reg rbx is becoming dead [000120] Live regs: 00009048 {rbx rsi r12 r15} => 00009040 {rsi r12 r15} Live vars: {V00 V04 V05 V07 V08 V10} => {V00 V04 V05 V07 V08} IN0132: inc ebx Generating: N1445 ( 3, 2) [000119] -----------z t119 = LCL_VAR byref V08 loc4 u:2 r14 (last use) REG r14 $781 /--* t119 byref +--* t122 int Generating: N1447 (???,???) [001430] -A--GO------ * STOREIND int REG NA IN0133: mov r14, bword ptr [V08 rsp+50H] Removing V08 from gcVarPtrSetCur V08 in reg r14 is becoming live [000119] Live regs: 00009040 {rsi r12 r15} => 0000D040 {rsi r12 r14 r15} Byref regs: 00000000 {} => 00004000 {r14} V08 in reg r14 is becoming dead [000119] Live regs: 0000D040 {rsi r12 r14 r15} => 00009040 {rsi r12 r15} Live vars: {V00 V04 V05 V07 V08} => {V00 V04 V05 V07} Byref regs: 00004000 {r14} => 00000000 {} IN0134: mov dword ptr [r14], ebx Added IP mapping: 0x02AB STACK_EMPTY (G_M38507_IG44,ins#19,ofs#72) Generating: N1449 (???,???) [001431] ------------ IL_OFFSET void IL offset: 0x2ab REG NA Generating: N1451 ( 1, 1) [000126] -c---------- t126 = LCL_VAR ref V00 this u:1 rsi REG NA $100 /--* t126 ref Generating: N1453 ( 2, 2) [001141] -c---------- t1141 = * LEA(b+68) byref REG NA /--* t1141 byref Generating: N1455 ( 4, 4) [000127] nc--GO------ t127 = * IND int REG NA Generating: N1457 ( 1, 1) [000128] -c---------- t128 = CNS_INT int 1 REG NA $c1 /--* t127 int +--* t128 int Generating: N1459 ( 6, 6) [000129] -c--GO------ t129 = * ADD int REG NA Generating: N1461 ( 1, 1) [000125] ------------ t125 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t125 ref Generating: N1463 ( 2, 2) [001139] -c---------- t1139 = * LEA(b+68) byref REG NA /--* t1139 byref +--* t129 int Generating: N1465 (???,???) [001432] -A--GO------ * STOREIND int REG NA IN0135: inc dword ptr [rsi+68] Added IP mapping: 0x02CA STACK_EMPTY (G_M38507_IG44,ins#20,ofs#75) Generating: N1467 (???,???) [001433] ------------ IL_OFFSET void IL offset: 0x2ca REG NA Generating: N1469 ( 1, 1) [000145] -c---------- t145 = LCL_VAR int V07 loc3 u:2 NA (last use) REG NA $3c5 Generating: N1471 ( 1, 1) [000146] -c---------- t146 = CNS_INT int 100 REG NA $e3 /--* t145 int +--* t146 int Generating: N1473 ( 3, 3) [000147] N------N-U-- * LE void REG NA $80d Live vars: {V00 V04 V05 V07} => {V00 V04 V05} IN0136: cmp dword ptr [V07 rsp+8CH], 100 Generating: N1475 ( 5, 5) [000148] ------------ * JTRUE void REG NA IN0137: jbe L_M38507_BB58 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 55 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG35,ins#7,ofs#31), (G_M38507_IG44,ins#10,ofs#39) ]; ] IL Var Num 2: [rbp [ (G_M38507_IG36,ins#3,ofs#14), (G_M38507_IG44,ins#14,ofs#54) ]; ] IL Var Num 4: [r15 [ (G_M38507_IG43,ins#3,ofs#10), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG36,ins#3,ofs#14), NON_CLOSED_RANGE ]; ] IL Var Num 6: [r13 [ (G_M38507_IG36,ins#3,ofs#14), (G_M38507_IG44,ins#5,ofs#22) ]; ] IL Var Num 7: [rsp'[140] (1 slot) [ (G_M38507_IG37,ins#6,ofs#31), (G_M38507_IG44,ins#20,ofs#75) ]; ] IL Var Num 8: [rsp'[80] (1 slot) [ (G_M38507_IG42,ins#7,ofs#32), (G_M38507_IG44,ins#18,ofs#69) ]; ] IL Var Num 10: [rbx [ (G_M38507_IG43,ins#0,ofs#0), (G_M38507_IG44,ins#16,ofs#62) ]; ] IL Var Num 11: [r14 [ (G_M38507_IG44,ins#5,ofs#22), (G_M38507_IG44,ins#13,ofs#50) ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 55 =============== Generating BB56 [2CF..2D7) -> BB58 (cond), preds={BB55} succs={BB57,BB58} flags=0x00000002.20000020: i hascall LIR BB56 IN (3)={V04 V00 V05} + ByrefExposed + GcHeap OUT(2)={V04 V00 } + ByrefExposed + GcHeap Recording Var Locations at start of BB56 V04(r15) V00(rsi) V05(r12) Liveness not changing: 00000000000000000000000000010014 {V00 V04 V05} Live regs: 00000000 {} => 00009040 {rsi r12 r15} GC regs: 00000000 {} => 00009040 {rsi r12 r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB56: Scope info: begin block BB56, IL range [2CF..2D7) Added IP mapping: 0x02CF STACK_EMPTY (G_M38507_IG44,ins#22,ofs#89) label Generating: N1479 (???,???) [001434] ------------ IL_OFFSET void IL offset: 0x2cf REG NA Generating: N1481 ( 1, 1) [000151] ------------ t151 = LCL_VAR ref V05 loc1 u:1 r12 (last use) REG r12 /--* t151 ref Generating: N1483 (???,???) [001495] ------------ t1495 = * PUTARG_REG ref REG rdx V05 in reg r12 is becoming dead [000151] Live regs: 00009040 {rsi r12 r15} => 00008040 {rsi r15} Live vars: {V00 V04 V05} => {V00 V04} GC regs: 00009040 {rsi r12 r15} => 00008040 {rsi r15} IN0138: mov rdx, r12 GC regs: 00008040 {rsi r15} => 00008044 {rdx rsi r15} Generating: N1485 ( 2, 10) [000152] H------N---- t152 = CNS_INT(h) long 0xd1ffab1e class REG rcx $62 IN0139: mov rcx, 0xD1FFAB1E /--* t152 long Generating: N1487 (???,???) [001496] ------------ t1496 = * PUTARG_REG long REG rcx /--* t1495 ref arg1 in rdx +--* t1496 long arg0 in rcx Generating: N1489 ( 17, 18) [000153] --C-G------- t153 = * CALL help ref HELPER.CORINFO_HELP_ISINSTANCEOFCLASS REG rax GC regs: 00008044 {rdx rsi r15} => 00008040 {rsi r15} Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=00008040 {rsi r15}, byrefRegs=00000000 {} IN013a: call CORINFO_HELP_ISINSTANCEOFCLASS GC regs: 00008040 {rsi r15} => 00008041 {rax rsi r15} Generating: N1491 ( 1, 1) [000154] -c---------- t154 = CNS_INT ref null REG NA $VN.Null /--* t153 ref +--* t154 ref Generating: N1493 ( 19, 20) [000155] J---G--N---- * EQ void REG NA GC regs: 00008041 {rax rsi r15} => 00008040 {rsi r15} IN013b: test rax, rax Generating: N1495 ( 21, 22) [000156] ----G------- * JTRUE void REG NA IN013c: je L_M38507_BB58 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 56 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG43,ins#3,ofs#10), NON_CLOSED_RANGE ]; ] IL Var Num 5: [r12 [ (G_M38507_IG36,ins#3,ofs#14), (G_M38507_IG44,ins#22,ofs#89) ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 56 =============== Generating BB57 [2D7..2E3), preds={BB56} succs={BB58} flags=0x00000002.20180020: i hascall gcsafe idxlen LIR BB57 IN (2)={V04 V00} + ByrefExposed + GcHeap OUT(1)={ V00} Recording Var Locations at start of BB57 V04(r15) V00(rsi) Liveness not changing: 00000000000000000000000000000014 {V00 V04} Live regs: 00000000 {} => 00008040 {rsi r15} GC regs: 00000000 {} => 00008040 {rsi r15} Byref regs: (unchanged) 00000000 {} L_M38507_BB57: Scope info: begin block BB57, IL range [2D7..2E3) Added IP mapping: 0x02D7 STACK_EMPTY (G_M38507_IG44,ins#27,ofs#116) label Generating: N1499 (???,???) [001435] ------------ IL_OFFSET void IL offset: 0x2d7 REG NA Generating: N1501 ( 1, 1) [000158] ------------ t158 = LCL_VAR ref V04 loc0 u:2 r15 (last use) REG r15 $684 /--* t158 ref Generating: N1503 (???,???) [001454] -c---------- t1454 = * LEA(b+8) ref REG NA /--* t1454 ref Generating: N1505 ( 3, 3) [000159] ---X-------- t159 = * IND int REG rdx $73d V04 in reg r15 is becoming dead [000158] Live regs: 00008040 {rsi r15} => 00000040 {rsi} Live vars: {V00 V04} => {V00} GC regs: 00008040 {rsi r15} => 00000040 {rsi} IN013d: mov edx, dword ptr [r15+8] /--* t159 int Generating: N1507 (???,???) [001497] ---X-------- t1497 = * PUTARG_REG int REG rdx Generating: N1509 ( 1, 1) [000157] ------------ t157 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t157 ref Generating: N1511 (???,???) [001498] ------------ t1498 = * PUTARG_REG ref REG rcx IN013e: mov rcx, rsi GC regs: 00000040 {rsi} => 00000042 {rcx rsi} Generating: N1513 ( 1, 1) [000160] ------------ t160 = CNS_INT int 1 REG r8 $c1 IN013f: mov r8d, 1 /--* t160 int Generating: N1515 (???,???) [001499] ------------ t1499 = * PUTARG_REG int REG r8 /--* t1497 int arg1 in rdx +--* t1498 ref this in rcx +--* t1499 int arg2 in r8 Generating: N1517 ( 19, 14) [000161] --CXG------- * CALL void System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon].Resize REG NA $VN.Void GC regs: 00000042 {rcx rsi} => 00000040 {rsi} Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} IN0140: call System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize(int,bool):this //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 57 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 4: [r15 [ (G_M38507_IG43,ins#3,ofs#10), (G_M38507_IG44,ins#27,ofs#116) ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 57 =============== Generating BB58 [???..???) (return), preds={BB29,BB39,BB55,BB56,BB57} succs={} flags=0x00000000.20010040: internal label LIR BB58 IN (1)={V00} OUT(1)={V00} Recording Var Locations at start of BB58 V00(rsi) Liveness not changing: 00000000000000000000000000000010 {V00} Live regs: 00000000 {} => 00000040 {rsi} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: (unchanged) 00000000 {} L_M38507_BB58: G_M38507_IG44: ; offs=0005CCH, funclet=00, bbWeight=0.50 Mapped BB58 to G_M38507_IG45 Label: IG45, GCvars=00000000000000000000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} Scope info: begin block BB58, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP STACK_EMPTY (G_M38507_IG45,ins#0,ofs#0) label Generating: N1521 ( 1, 1) [000482] ------------ t482 = CNS_INT int 1 REG rax $c1 IN0141: mov eax, 1 /--* t482 int Generating: N1523 ( 2, 2) [000810] ------------ * RETURN int REG NA $1f4 Scope info: ignoring block end Added IP mapping: EPILOG STACK_EMPTY (G_M38507_IG45,ins#1,ofs#5) label Reserving epilog IG for block BB58 G_M38507_IG45: ; offs=000652H, funclet=00, bbWeight=0.50 *************** After placeholder IG creation G_M38507_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M38507_IG02: ; offs=000000H, size=0014H, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG03: ; offs=000014H, size=000AH, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG04: ; offs=00001EH, size=0023H, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG05: ; offs=000041H, size=0008H, gcrefRegs=000040E4 {rdx rbp rsi rdi r14}, byrefRegs=00000000 {}, byref G_M38507_IG06: ; offs=000049H, size=0018H, gcrefRegs=000040E0 {rbp rsi rdi r14}, byrefRegs=00000000 {}, byref G_M38507_IG07: ; offs=000061H, size=0012H, gcrefRegs=0000C0E4 {rdx rbp rsi rdi r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG08: ; offs=000073H, size=000DH, gcrefRegs=0000C0E0 {rbp rsi rdi r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG09: ; offs=000080H, size=0017H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG10: ; offs=000097H, size=0005H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG11: ; offs=00009CH, size=0012H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG12: ; offs=0000AEH, size=0011H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG13: ; offs=0000BFH, size=0010H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG14: ; offs=0000CFH, size=003FH, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG15: ; offs=00010EH, size=0008H, gcVars=00000000000000000000000000200000 {V39}, gcrefRegs=0000D0E4 {rdx rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG16: ; offs=000116H, size=0047H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG17: ; offs=00015DH, size=0008H, gcrefRegs=0000D0E4 {rdx rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG18: ; offs=000165H, size=0038H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG19: ; offs=00019DH, size=0017H, gcVars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG20: ; offs=0001B4H, size=0005H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG21: ; offs=0001B9H, size=0012H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG22: ; offs=0001CBH, size=0008H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG23: ; offs=0001D3H, size=0035H, gcrefRegs=0000D0E1 {rax rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG24: ; offs=000208H, size=0028H, gcVars=00000000000000000000000100000040 {V08 V65}, gcrefRegs=0000D0E1 {rax rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG25: ; offs=000230H, size=0037H, gcVars=00000000000000000000000100000040 {V08 V65}, gcrefRegs=0000D0E1 {rax rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG26: ; offs=000267H, size=001FH, gcVars=00000000000000000000000000000040 {V65}, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG27: ; offs=000286H, size=0009H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG28: ; offs=00028FH, size=0002H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M38507_IG29: ; epilog placeholder, next placeholder=IG46 , BB31 [0092], epilog, extend <-- First placeholder ; PrevGCVars=00000000000000000000000000000000 {}, PrevGCrefRegs=000000C0 {rsi rdi}, PrevByrefRegs=00000000 {} ; InitGCVars=00000000000000000000000000000000 {}, InitGCrefRegs=00000040 {rsi}, InitByrefRegs=00000000 {} G_M38507_IG30: ; offs=000391H, size=0035H, gcVars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG31: ; offs=0003C6H, size=0021H, gcVars=00000000000000000000000100000080 {V08 V66}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG32: ; offs=0003E7H, size=000AH, gcVars=00000000000000000000000100008080 {V08 V17 V66}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG33: ; offs=0003F1H, size=0017H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG34: ; offs=000408H, size=0014H, gcVars=00000000000000000000000100000080 {V08 V66}, gcrefRegs=0000D4E0 {rbp rsi rdi r10 r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG35: ; offs=00041CH, size=001FH, gcVars=00000000000000000000000000000080 {V66}, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG36: ; offs=00043BH, size=000EH, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG37: ; offs=000449H, size=0036H, gcVars=00000000000000000000000100000080 {V08 V66}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG38: ; offs=00047FH, size=0050H, gcVars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG39: ; offs=0004CFH, size=0029H, gcrefRegs=000090E0 {rbp rsi rdi r12 r15}, byrefRegs=00000000 {}, byref G_M38507_IG40: ; offs=0004F8H, size=005EH, gcrefRegs=000050E0 {rbp rsi rdi r12 r14}, byrefRegs=00000000 {}, byref G_M38507_IG41: ; offs=000556H, size=004CH, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG42: ; offs=0005A2H, size=0020H, gcrefRegs=000090E0 {rbp rsi rdi r12 r15}, byrefRegs=00000000 {}, byref G_M38507_IG43: ; offs=0005C2H, size=000AH, gcVars=00000000000000000000000100000000 {V08}, gcrefRegs=000010E0 {rbp rsi rdi r12}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG44: ; offs=0005CCH, size=0086H, gcrefRegs=000090E0 {rbp rsi rdi r12 r15}, byrefRegs=00000000 {}, byref G_M38507_IG45: ; offs=000652H, size=0005H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M38507_IG46: ; epilog placeholder, next placeholder=, BB58 [0091], epilog, extend <-- Last placeholder ; PrevGCVars=00000000000000000000000000000000 {}, PrevGCrefRegs=00000040 {rsi}, PrevByrefRegs=00000000 {} ; InitGCVars=00000000000000000000000000000000 {}, InitGCrefRegs=00000040 {rsi}, InitByrefRegs=00000000 {} G_M38507_IG47: ; offs=000757H, size=0000H, gcrefRegs=00000000 {} <-- Current IG //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 58 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 58 =============== Generating BB59 [008..00E) (throw), preds={BB01} succs={} flags=0x00000002.20091020: i rare label hascall gcsafe LIR BB59 IN (1)={V00} + ByrefExposed + GcHeap OUT(1)={V00} Recording Var Locations at start of BB59 V00(rsi) Liveness not changing: 00000000000000000000000000000010 {V00} Live regs: 00000000 {} => 00000040 {rsi} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: (unchanged) 00000000 {} L_M38507_BB59: Mapped BB59 to G_M38507_IG47 Label: IG47, GCvars=00000000000000000000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} Scope info: begin block BB59, IL range [008..00E) Added IP mapping: 0x0008 STACK_EMPTY (G_M38507_IG47,ins#0,ofs#0) label Generating: N1527 (???,???) [001436] ------------ IL_OFFSET void IL offset: 0x8 REG NA Generating: N1529 ( 1, 1) [000532] ------------ t532 = CNS_INT int 4 REG rcx $c5 IN0142: mov ecx, 4 /--* t532 int Generating: N1531 (???,???) [001500] ------------ t1500 = * PUTARG_REG int REG rcx /--* t1500 int arg0 in rcx Generating: N1533 ( 15, 7) [000533] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentNullException REG NA $VN.Void Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} IN0143: call System.ThrowHelper:ThrowArgumentNullException(int) IN0144: int3 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 59 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 59 =============== Generating BB60 [14F..???) -> BB62 (cond), preds={BB30} succs={BB61,BB62} flags=0x00000002.21091020: i rare label hascall gcsafe bwd LIR BB60 IN (2)={V00 V01 } + ByrefExposed + GcHeap OUT(3)={V00 V01 V26} + ByrefExposed + GcHeap Recording Var Locations at start of BB60 V00(rsi) V01(rdi) Change life 00000000000000000000000000000010 {V00} -> 00000000000000000000000000000210 {V00 V01} V01 in reg rdi is becoming live [------] Live regs: 00000000 {} => 00000080 {rdi} New debug range: new var or location Live regs: 00000080 {rdi} => 000000C0 {rsi rdi} GC regs: 00000080 {rdi} => 000000C0 {rsi rdi} Byref regs: (unchanged) 00000000 {} L_M38507_BB60: G_M38507_IG47: ; offs=000757H, funclet=00, bbWeight=0 Mapped BB60 to G_M38507_IG48 Label: IG48, GCvars=00000000000000000000000000000000 {}, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {} Scope info: begin block BB60, IL range [14F..???) Added IP mapping: 0x014F STACK_EMPTY (G_M38507_IG48,ins#0,ofs#0) label Generating: N1537 (???,???) [001437] ------------ IL_OFFSET void IL offset: 0x14f REG NA Generating: N1539 ( 1, 1) [000441] !----------- t441 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t441 ref Generating: N1541 ( 3, 2) [000442] #----O------ t442 = * IND long REG rcx $2e8 IN0145: mov rcx, qword ptr [rsi] /--* t442 long Generating: N1543 ( 7, 5) [000444] DA---O------ * STORE_LCL_VAR long V26 tmp12 d:1 rcx REG rcx V26 in reg rcx is becoming live [000444] Live regs: 000000C0 {rsi rdi} => 000000C2 {rcx rsi rdi} Live vars: {V00 V01} => {V00 V01 V26} Generating: N1545 ( 3, 2) [000446] ------------ t446 = LCL_VAR long V26 tmp12 u:1 rcx REG rcx $2e7 /--* t446 long Generating: N1547 ( 4, 3) [000448] -c---------- t448 = * LEA(b+56) long REG NA /--* t448 long Generating: N1549 ( 6, 5) [000449] #----------- t449 = * IND long REG rdx $2e9 IN0146: mov rdx, qword ptr [rcx+56] /--* t449 long Generating: N1551 ( 9, 7) [000450] #----------- t450 = * IND long REG rdx $2ea IN0147: mov rdx, qword ptr [rdx] /--* t450 long Generating: N1553 ( 10, 8) [000452] -c---------- t452 = * LEA(b+56) long REG NA /--* t452 long Generating: N1555 ( 12, 10) [000456] nc---------- t456 = * IND long REG NA Generating: N1557 ( 1, 1) [000459] -c---------- t459 = CNS_INT long 0 REG NA $243 /--* t456 long +--* t459 long Generating: N1559 ( 14, 12) [000460] J------N---- * EQ void REG NA IN0148: cmp qword ptr [rdx+56], 0 Generating: N1561 ( 16, 14) [001158] ------------ * JTRUE void REG NA IN0149: je L_M38507_BB62 Scope info: ignoring block end //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 60 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG47,ins#3,ofs#11), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 60 =============== Generating BB61 [???..???) -> BB63 (always), preds={BB60} succs={BB63} flags=0x00000000.20081020: i rare gcsafe LIR BB61 IN (3)={V00 V01 V26 } + ByrefExposed + GcHeap OUT(3)={V00 V01 V28} + ByrefExposed + GcHeap Recording Var Locations at start of BB61 V00(rsi) V01(rdi) V26(rcx) Liveness not changing: 00000000000000080000000000000210 {V00 V01 V26} Live regs: 00000000 {} => 000000C2 {rcx rsi rdi} GC regs: 00000000 {} => 000000C0 {rsi rdi} Byref regs: (unchanged) 00000000 {} L_M38507_BB61: Scope info: begin block BB61, IL range [???..???) Scope info: ignoring block beginning Generating: N1565 ( 3, 2) [000466] ------?----- t466 = LCL_VAR long V26 tmp12 u:1 rcx (last use) REG rcx $2e7 /--* t466 long Generating: N1567 ( 4, 3) [000465] -c----?----- t465 = * LEA(b+56) long REG NA /--* t465 long Generating: N1569 ( 6, 5) [000464] #-----?----- t464 = * IND long REG rcx $2e9 V26 in reg rcx is becoming dead [000466] Live regs: 000000C2 {rcx rsi rdi} => 000000C0 {rsi rdi} Live vars: {V00 V01 V26} => {V00 V01} IN014a: mov rcx, qword ptr [rcx+56] /--* t464 long Generating: N1571 ( 9, 7) [000463] #-----?----- t463 = * IND long REG rcx $2ea IN014b: mov rcx, qword ptr [rcx] /--* t463 long Generating: N1573 ( 10, 8) [000462] -c----?----- t462 = * LEA(b+56) long REG NA /--* t462 long Generating: N1575 ( 12, 10) [000461] n-----?----- t461 = * IND long REG rcx IN014c: mov rcx, qword ptr [rcx+56] /--* t461 long Generating: N1577 ( 16, 13) [001160] DA---------- * STORE_LCL_VAR long V28 tmp14 d:3 rcx REG rcx V28 in reg rcx is becoming live [001160] Live regs: 000000C0 {rsi rdi} => 000000C2 {rcx rsi rdi} Live vars: {V00 V01} => {V00 V01 V28} Scope info: ignoring block end IN014d: jmp L_M38507_BB63 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 61 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG47,ins#3,ofs#11), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 61 =============== Generating BB62 [???..???), preds={BB60} succs={BB63} flags=0x00000000.20091020: i rare label gcsafe LIR BB62 IN (3)={V00 V01 V26 } + ByrefExposed + GcHeap OUT(3)={V00 V01 V28} + ByrefExposed + GcHeap Recording Var Locations at start of BB62 V00(rsi) V01(rdi) V26(rcx) Change life 00000000000000200000000000000210 {V00 V01 V28} -> 00000000000000080000000000000210 {V00 V01 V26} V28 in reg rcx is becoming dead [------] Live regs: (unchanged) 00000000 {} V26 in reg rcx is becoming live [------] Live regs: 00000000 {} => 00000002 {rcx} Live regs: 00000002 {rcx} => 000000C2 {rcx rsi rdi} GC regs: 00000000 {} => 000000C0 {rsi rdi} Byref regs: (unchanged) 00000000 {} L_M38507_BB62: G_M38507_IG48: ; offs=000762H, funclet=00, bbWeight=0 Mapped BB62 to G_M38507_IG49 Label: IG49, GCvars=00000000000000000000000000000000 {}, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {} Scope info: begin block BB62, IL range [???..???) Scope info: ignoring block beginning Generating: N1581 ( 3, 2) [000445] ------?----- t445 = LCL_VAR long V26 tmp12 u:1 rcx (last use) REG rcx $2e7 /--* t445 long Generating: N1583 (???,???) [001501] ------------ t1501 = * PUTARG_REG long REG rcx V26 in reg rcx is becoming dead [000445] Live regs: 000000C2 {rcx rsi rdi} => 000000C0 {rsi rdi} Live vars: {V00 V01 V26} => {V00 V01} Generating: N1585 ( 2, 10) [000457] H-----?----- t457 = CNS_INT(h) long 0xd1ffab1e global ptr REG rdx $52 IN014e: mov rdx, 0xD1FFAB1E /--* t457 long Generating: N1587 (???,???) [001502] ------------ t1502 = * PUTARG_REG long REG rdx /--* t1501 long arg0 in rcx +--* t1502 long arg1 in rdx Generating: N1589 ( 19, 19) [000458] --C-G-?----- t458 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS REG rax $332 Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {} IN014f: call CORINFO_HELP_RUNTIMEHANDLE_CLASS /--* t458 long Generating: N1591 ( 23, 22) [001162] DA--G------- * STORE_LCL_VAR long V28 tmp14 d:2 rcx REG rcx IN0150: mov rcx, rax V28 in reg rcx is becoming live [001162] Live regs: 000000C0 {rsi rdi} => 000000C2 {rcx rsi rdi} Live vars: {V00 V01} => {V00 V01 V28} Scope info: ignoring block end //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 62 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG47,ins#3,ofs#11), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 62 =============== Generating BB63 [???..157) (throw), preds={BB61,BB62} succs={} flags=0x00000002.21091020: i rare label hascall gcsafe bwd LIR BB63 IN (3)={V00 V01 V28} + ByrefExposed + GcHeap OUT(1)={V00 } Recording Var Locations at start of BB63 V00(rsi) V01(rdi) V28(rcx) Liveness not changing: 00000000000000200000000000000210 {V00 V01 V28} Live regs: 00000000 {} => 000000C2 {rcx rsi rdi} GC regs: 00000000 {} => 000000C0 {rsi rdi} Byref regs: (unchanged) 00000000 {} L_M38507_BB63: G_M38507_IG49: ; offs=000787H, funclet=00, bbWeight=0 Mapped BB63 to G_M38507_IG50 Label: IG50, GCvars=00000000000000000000000000000000 {}, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {} Scope info: begin block BB63, IL range [???..157) Scope info: ignoring block beginning Generating: N1595 ( 3, 2) [000473] ------------ t473 = LCL_VAR long V28 tmp14 u:1 rcx (last use) REG rcx $347 /--* t473 long Generating: N1597 (???,???) [001503] ------------ t1503 = * PUTARG_REG long REG rcx V28 in reg rcx is becoming dead [000473] Live regs: 000000C2 {rcx rsi rdi} => 000000C0 {rsi rdi} Live vars: {V00 V01 V28} => {V00 V01} Generating: N1599 ( 1, 1) [000455] ------------ t455 = LCL_VAR ref V01 arg1 u:1 rdi (last use) REG rdi $101 /--* t455 ref Generating: N1601 (???,???) [001504] ------------ t1504 = * PUTARG_REG ref REG rdx V01 in reg rdi is becoming dead [000455] Live regs: 000000C0 {rsi rdi} => 00000040 {rsi} Live vars: {V00 V01} => {V00} GC regs: 000000C0 {rsi rdi} => 00000040 {rsi} IN0151: mov rdx, rdi GC regs: 00000040 {rsi} => 00000044 {rdx rsi} /--* t1503 long arg0 in rcx +--* t1504 ref arg1 in rdx Generating: N1603 ( 18, 10) [000440] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException REG NA $VN.Void GC regs: 00000044 {rdx rsi} => 00000040 {rsi} Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} IN0152: call System.ThrowHelper:ThrowAddingDuplicateWithKeyArgumentException(System.__Canon) IN0153: int3 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 63 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG47,ins#3,ofs#11), (G_M38507_IG50,ins#0,ofs#0) ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 63 =============== Generating BB64 [1BC..???) -> BB66 (cond), preds={BB40} succs={BB65,BB66} flags=0x00000002.21091020: i rare label hascall gcsafe bwd LIR BB64 IN (2)={V00 V01 } + ByrefExposed + GcHeap OUT(3)={V00 V01 V21} + ByrefExposed + GcHeap Recording Var Locations at start of BB64 V00(rsi) V01(rdi) Change life 00000000000000000000000000000010 {V00} -> 00000000000000000000000000000210 {V00 V01} V01 in reg rdi is becoming live [------] Live regs: 00000000 {} => 00000080 {rdi} New debug range: new var or location Live regs: 00000080 {rdi} => 000000C0 {rsi rdi} GC regs: 00000080 {rdi} => 000000C0 {rsi rdi} Byref regs: (unchanged) 00000000 {} L_M38507_BB64: G_M38507_IG50: ; offs=000799H, funclet=00, bbWeight=0 Mapped BB64 to G_M38507_IG51 Label: IG51, GCvars=00000000000000000000000000000000 {}, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {} Scope info: begin block BB64, IL range [1BC..???) Added IP mapping: 0x01BC STACK_EMPTY (G_M38507_IG51,ins#0,ofs#0) label Generating: N1607 (???,???) [001438] ------------ IL_OFFSET void IL offset: 0x1bc REG NA Generating: N1609 ( 1, 1) [000296] !----------- t296 = LCL_VAR ref V00 this u:1 rsi REG rsi $100 /--* t296 ref Generating: N1611 ( 3, 2) [000297] #----O------ t297 = * IND long REG rcx $2e8 IN0154: mov rcx, qword ptr [rsi] /--* t297 long Generating: N1613 ( 7, 5) [000299] DA---O------ * STORE_LCL_VAR long V21 tmp7 d:1 rcx REG rcx V21 in reg rcx is becoming live [000299] Live regs: 000000C0 {rsi rdi} => 000000C2 {rcx rsi rdi} Live vars: {V00 V01} => {V00 V01 V21} Generating: N1615 ( 3, 2) [000301] ------------ t301 = LCL_VAR long V21 tmp7 u:1 rcx REG rcx $2e7 /--* t301 long Generating: N1617 ( 4, 3) [000303] -c---------- t303 = * LEA(b+56) long REG NA /--* t303 long Generating: N1619 ( 6, 5) [000304] #----------- t304 = * IND long REG rdx $2e9 IN0155: mov rdx, qword ptr [rcx+56] /--* t304 long Generating: N1621 ( 9, 7) [000305] #----------- t305 = * IND long REG rdx $2ea IN0156: mov rdx, qword ptr [rdx] /--* t305 long Generating: N1623 ( 10, 8) [000307] -c---------- t307 = * LEA(b+56) long REG NA /--* t307 long Generating: N1625 ( 12, 10) [000311] nc---------- t311 = * IND long REG NA Generating: N1627 ( 1, 1) [000314] -c---------- t314 = CNS_INT long 0 REG NA $243 /--* t311 long +--* t314 long Generating: N1629 ( 14, 12) [000315] J------N---- * EQ void REG NA IN0157: cmp qword ptr [rdx+56], 0 Generating: N1631 ( 16, 14) [001168] ------------ * JTRUE void REG NA IN0158: je L_M38507_BB66 Scope info: ignoring block end //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 64 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG50,ins#3,ofs#9), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 64 =============== Generating BB65 [???..???) -> BB67 (always), preds={BB64} succs={BB67} flags=0x00000000.20081020: i rare gcsafe LIR BB65 IN (3)={V00 V01 V21 } + ByrefExposed + GcHeap OUT(3)={V00 V01 V23} + ByrefExposed + GcHeap Recording Var Locations at start of BB65 V00(rsi) V01(rdi) V21(rcx) Liveness not changing: 00000000000000040000000000000210 {V00 V01 V21} Live regs: 00000000 {} => 000000C2 {rcx rsi rdi} GC regs: 00000000 {} => 000000C0 {rsi rdi} Byref regs: (unchanged) 00000000 {} L_M38507_BB65: Scope info: begin block BB65, IL range [???..???) Scope info: ignoring block beginning Generating: N1635 ( 3, 2) [000321] ------?----- t321 = LCL_VAR long V21 tmp7 u:1 rcx (last use) REG rcx $2e7 /--* t321 long Generating: N1637 ( 4, 3) [000320] -c----?----- t320 = * LEA(b+56) long REG NA /--* t320 long Generating: N1639 ( 6, 5) [000319] #-----?----- t319 = * IND long REG rcx $2e9 V21 in reg rcx is becoming dead [000321] Live regs: 000000C2 {rcx rsi rdi} => 000000C0 {rsi rdi} Live vars: {V00 V01 V21} => {V00 V01} IN0159: mov rcx, qword ptr [rcx+56] /--* t319 long Generating: N1641 ( 9, 7) [000318] #-----?----- t318 = * IND long REG rcx $2ea IN015a: mov rcx, qword ptr [rcx] /--* t318 long Generating: N1643 ( 10, 8) [000317] -c----?----- t317 = * LEA(b+56) long REG NA /--* t317 long Generating: N1645 ( 12, 10) [000316] n-----?----- t316 = * IND long REG rcx IN015b: mov rcx, qword ptr [rcx+56] /--* t316 long Generating: N1647 ( 16, 13) [001170] DA---------- * STORE_LCL_VAR long V23 tmp9 d:3 rcx REG rcx V23 in reg rcx is becoming live [001170] Live regs: 000000C0 {rsi rdi} => 000000C2 {rcx rsi rdi} Live vars: {V00 V01} => {V00 V01 V23} Scope info: ignoring block end IN015c: jmp L_M38507_BB67 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 65 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG50,ins#3,ofs#9), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 65 =============== Generating BB66 [???..???), preds={BB64} succs={BB67} flags=0x00000000.20091020: i rare label gcsafe LIR BB66 IN (3)={V00 V01 V21 } + ByrefExposed + GcHeap OUT(3)={V00 V01 V23} + ByrefExposed + GcHeap Recording Var Locations at start of BB66 V00(rsi) V01(rdi) V21(rcx) Change life 00000000000000100000000000000210 {V00 V01 V23} -> 00000000000000040000000000000210 {V00 V01 V21} V23 in reg rcx is becoming dead [------] Live regs: (unchanged) 00000000 {} V21 in reg rcx is becoming live [------] Live regs: 00000000 {} => 00000002 {rcx} Live regs: 00000002 {rcx} => 000000C2 {rcx rsi rdi} GC regs: 00000000 {} => 000000C0 {rsi rdi} Byref regs: (unchanged) 00000000 {} L_M38507_BB66: G_M38507_IG51: ; offs=0007A2H, funclet=00, bbWeight=0 Mapped BB66 to G_M38507_IG52 Label: IG52, GCvars=00000000000000000000000000000000 {}, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {} Scope info: begin block BB66, IL range [???..???) Scope info: ignoring block beginning Generating: N1651 ( 3, 2) [000300] ------?----- t300 = LCL_VAR long V21 tmp7 u:1 rcx (last use) REG rcx $2e7 /--* t300 long Generating: N1653 (???,???) [001505] ------------ t1505 = * PUTARG_REG long REG rcx V21 in reg rcx is becoming dead [000300] Live regs: 000000C2 {rcx rsi rdi} => 000000C0 {rsi rdi} Live vars: {V00 V01 V21} => {V00 V01} Generating: N1655 ( 2, 10) [000312] H-----?----- t312 = CNS_INT(h) long 0xd1ffab1e global ptr REG rdx $52 IN015d: mov rdx, 0xD1FFAB1E /--* t312 long Generating: N1657 (???,???) [001506] ------------ t1506 = * PUTARG_REG long REG rdx /--* t1505 long arg0 in rcx +--* t1506 long arg1 in rdx Generating: N1659 ( 19, 19) [000313] --C-G-?----- t313 = * CALL help long HELPER.CORINFO_HELP_RUNTIMEHANDLE_CLASS REG rax $332 Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {} IN015e: call CORINFO_HELP_RUNTIMEHANDLE_CLASS /--* t313 long Generating: N1661 ( 23, 22) [001172] DA--G------- * STORE_LCL_VAR long V23 tmp9 d:2 rcx REG rcx IN015f: mov rcx, rax V23 in reg rcx is becoming live [001172] Live regs: 000000C0 {rsi rdi} => 000000C2 {rcx rsi rdi} Live vars: {V00 V01} => {V00 V01 V23} Scope info: ignoring block end //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 66 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG50,ins#3,ofs#9), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 66 =============== Generating BB67 [???..1C4) (throw), preds={BB65,BB66} succs={} flags=0x00000002.21091020: i rare label hascall gcsafe bwd LIR BB67 IN (3)={V00 V01 V23} + ByrefExposed + GcHeap OUT(1)={V00 } Recording Var Locations at start of BB67 V00(rsi) V01(rdi) V23(rcx) Liveness not changing: 00000000000000100000000000000210 {V00 V01 V23} Live regs: 00000000 {} => 000000C2 {rcx rsi rdi} GC regs: 00000000 {} => 000000C0 {rsi rdi} Byref regs: (unchanged) 00000000 {} L_M38507_BB67: G_M38507_IG52: ; offs=0007C7H, funclet=00, bbWeight=0 Mapped BB67 to G_M38507_IG53 Label: IG53, GCvars=00000000000000000000000000000000 {}, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {} Scope info: begin block BB67, IL range [???..1C4) Scope info: ignoring block beginning Generating: N1665 ( 3, 2) [000328] ------------ t328 = LCL_VAR long V23 tmp9 u:1 rcx (last use) REG rcx $34b /--* t328 long Generating: N1667 (???,???) [001507] ------------ t1507 = * PUTARG_REG long REG rcx V23 in reg rcx is becoming dead [000328] Live regs: 000000C2 {rcx rsi rdi} => 000000C0 {rsi rdi} Live vars: {V00 V01 V23} => {V00 V01} Generating: N1669 ( 1, 1) [000310] ------------ t310 = LCL_VAR ref V01 arg1 u:1 rdi (last use) REG rdi $101 /--* t310 ref Generating: N1671 (???,???) [001508] ------------ t1508 = * PUTARG_REG ref REG rdx V01 in reg rdi is becoming dead [000310] Live regs: 000000C0 {rsi rdi} => 00000040 {rsi} Live vars: {V00 V01} => {V00} GC regs: 000000C0 {rsi rdi} => 00000040 {rsi} IN0160: mov rdx, rdi GC regs: 00000040 {rsi} => 00000044 {rdx rsi} /--* t1507 long arg0 in rcx +--* t1508 ref arg1 in rdx Generating: N1673 ( 18, 10) [000295] --CXG------- * CALL void System.ThrowHelper.ThrowAddingDuplicateWithKeyArgumentException REG NA $VN.Void GC regs: 00000044 {rdx rsi} => 00000040 {rsi} Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} IN0161: call System.ThrowHelper:ThrowAddingDuplicateWithKeyArgumentException(System.__Canon) IN0162: int3 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 67 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] IL Var Num 1: [rdi [ (G_M38507_IG50,ins#3,ofs#9), (G_M38507_IG53,ins#0,ofs#0) ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 67 =============== Generating BB68 [1DD..1E4) (throw), preds={BB26,BB42} succs={} flags=0x00000002.21091020: i rare label hascall gcsafe bwd LIR BB68 IN (1)={V00} + ByrefExposed + GcHeap OUT(1)={V00} Recording Var Locations at start of BB68 V00(rsi) Liveness not changing: 00000000000000000000000000000010 {V00} Live regs: 00000000 {} => 00000040 {rsi} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: (unchanged) 00000000 {} L_M38507_BB68: G_M38507_IG53: ; offs=0007D9H, funclet=00, bbWeight=0 Mapped BB68 to G_M38507_IG54 Label: IG54, GCvars=00000000000000000000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} Scope info: begin block BB68, IL range [1DD..1E4) Added IP mapping: 0x01DD STACK_EMPTY (G_M38507_IG54,ins#0,ofs#0) label Generating: N1677 (???,???) [001439] ------------ IL_OFFSET void IL offset: 0x1dd REG NA Generating: N1679 ( 14, 5) [000233] --CXG------- CALL void System.ThrowHelper.ThrowInvalidOperationException_ConcurrentOperationsNotSupported REG NA $VN.Void Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} IN0163: call System.ThrowHelper:ThrowInvalidOperationException_ConcurrentOperationsNotSupported() IN0164: int3 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 68 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), NON_CLOSED_RANGE ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 68 =============== Generating BB69 [???..???) (throw), preds={} succs={} flags=0x00000000.20011070: keep i internal rare label LIR BB69 IN (1)={V00} OUT(1)={V00} Recording Var Locations at start of BB69 V00(rsi) Liveness not changing: 00000000000000000000000000000010 {V00} Live regs: 00000000 {} => 00000040 {rsi} GC regs: 00000000 {} => 00000040 {rsi} Byref regs: (unchanged) 00000000 {} L_M38507_BB69: G_M38507_IG54: ; offs=0007E2H, funclet=00, bbWeight=0 Mapped BB69 to G_M38507_IG55 Label: IG55, GCvars=00000000000000000000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} Scope info: begin block BB69, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP STACK_EMPTY (G_M38507_IG55,ins#0,ofs#0) label Generating: N1683 ( 14, 5) [001444] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL REG NA Call: GCvars=00000000000000000000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {} IN0165: call CORINFO_HELP_RNGCHKFAIL Scope info: ignoring block end IN0166: int3 //////////////////////////////////////// //////////////////////////////////////// Variable Live Range History Dump for Block 69 IL Var Num 0: [rsi [ (G_M38507_IG02,ins#0,ofs#0), (G_M38507_IG55,ins#1,ofs#5) ]; ] //////////////////////////////////////// //////////////////////////////////////// End Generating code for Block 69 Change life 00000000000000000000000000000010 {V00} -> 00000000000000000000000000000000 {} V00 in reg rsi is becoming dead [------] Live regs: 00000040 {rsi} => 00000000 {} # compCycleEstimate = 1494, compSizeEstimate = 1253 System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this ; Final local variable assignments ; ; V00 this [V00,T04] ( 29, 19 ) ref -> rsi this class-hnd ; V01 arg1 [V01,T09] ( 11, 9 ) ref -> rdi ld-addr-op class-hnd ; V02 arg2 [V02,T18] ( 5, 3.50) ref -> rbp class-hnd ; V03 arg3 [V03,T17] ( 6, 4 ) ubyte -> rbx ; V04 loc0 [V04,T02] ( 14, 25 ) ref -> r15 class-hnd ; V05 loc1 [V05,T16] ( 6, 6 ) ref -> r12 class-hnd ; V06 loc2 [V06,T05] ( 8, 12.50) int -> r13 ; V07 loc3 [V07,T01] ( 8, 25.50) int -> [rsp+8CH] ; V08 loc4 [V08,T32] ( 5, 3.50) byref -> [rsp+50H] ; V09 loc5 [V09,T03] ( 7, 25 ) int -> [rsp+88H] ; V10 loc6 [V10,T33] ( 6, 3 ) int -> rbx ; V11 loc7 [V11,T40] ( 5, 2.50) byref -> r14 ; V12 loc8 [V12,T20] ( 3, 4.50) ref -> [rsp+48H] class-hnd ; V13 loc9 [V13,T57] ( 3, 1.50) int -> rbx ; V14 OutArgs [V14 ] ( 1, 1 ) lclBlk (32) [rsp+00H] "OutgoingArgSpace" ; V15 tmp1 [V15,T44] ( 3, 2 ) int -> r13 ; V16 tmp2 [V16,T11] ( 3, 10 ) long -> rcx "impRuntimeLookup slot" ; V17 tmp3 [V17,T15] ( 2, 8 ) ref -> [rsp+40H] class-hnd "impAppendStmt" ;* V18 tmp4 [V18 ] ( 0, 0 ) ref -> zero-ref class-hnd "bubbling QMark1" ; V19 tmp5 [V19,T08] ( 4, 12 ) long -> r11 "spilling Runtime Lookup tree" ;* V20 tmp6 [V20 ] ( 0, 0 ) long -> zero-ref "VirtualCall with runtime lookup" ; V21 tmp7 [V21,T66] ( 4, 0 ) long -> rcx "impRuntimeLookup slot" ;* V22 tmp8 [V22 ] ( 0, 0 ) ref -> zero-ref class-hnd "bubbling QMark1" ; V23 tmp9 [V23,T68] ( 3, 0 ) long -> rcx "spilling Runtime Lookup tree" ; V24 tmp10 [V24,T41] ( 3, 2.50) long -> rcx "impRuntimeLookup slot" ; V25 tmp11 [V25,T45] ( 3, 2 ) long -> rdx "spilling Runtime Lookup tree" ; V26 tmp12 [V26,T67] ( 4, 0 ) long -> rcx "impRuntimeLookup slot" ;* V27 tmp13 [V27 ] ( 0, 0 ) ref -> zero-ref class-hnd "bubbling QMark1" ; V28 tmp14 [V28,T69] ( 3, 0 ) long -> rcx "spilling Runtime Lookup tree" ; V29 tmp15 [V29,T42] ( 3, 2.50) long -> rcx "impRuntimeLookup slot" ;* V30 tmp16 [V30 ] ( 0, 0 ) ref -> zero-ref class-hnd "bubbling QMark1" ; V31 tmp17 [V31,T34] ( 4, 3 ) long -> r11 "spilling Runtime Lookup tree" ;* V32 tmp18 [V32 ] ( 0, 0 ) long -> zero-ref "VirtualCall with runtime lookup" ; V33 tmp19 [V33,T27] ( 2, 4 ) bool -> rcx "Inlining Arg" ;* V34 tmp20 [V34,T53] ( 0, 0 ) ref -> zero-ref class-hnd "Inlining Arg" ; V35 tmp21 [V35,T24] ( 3, 4 ) ref -> rdx class-hnd "Inlining Arg" ; V36 tmp22 [V36,T28] ( 2, 4 ) bool -> rcx "Inlining Arg" ; V37 tmp23 [V37,T39] ( 2, 3 ) ref -> rdx class-hnd "Inlining Arg" ; V38 tmp24 [V38,T46] ( 2, 2 ) byref -> rax "Inline return value spill temp" ; V39 tmp25 [V39,T21] ( 4, 4 ) ref -> [rsp+38H] class-hnd "Inline stloc first use temp" ; V40 tmp26 [V40,T14] ( 4, 8 ) int -> [rsp+84H] "Inlining Arg" ; V41 tmp27 [V41,T29] ( 2, 4 ) long -> [rsp+78H] "Inlining Arg" ; V42 tmp28 [V42,T22] ( 4, 4 ) int -> [rsp+74H] "Inline stloc first use temp" ; V43 tmp29 [V43,T30] ( 2, 4 ) bool -> rcx "Inlining Arg" ;* V44 tmp30 [V44,T54] ( 0, 0 ) ref -> zero-ref class-hnd "Inlining Arg" ; V45 tmp31 [V45,T25] ( 3, 4 ) ref -> rdx class-hnd "Inlining Arg" ; V46 tmp32 [V46,T31] ( 2, 4 ) bool -> rcx "Inlining Arg" ;* V47 tmp33 [V47,T55] ( 0, 0 ) ref -> zero-ref class-hnd "Inlining Arg" ; V48 tmp34 [V48,T26] ( 3, 4 ) ref -> rdx class-hnd "Inlining Arg" ; V49 tmp35 [V49,T48] ( 2, 2 ) bool -> rcx "Inlining Arg" ; V50 tmp36 [V50,T47] ( 2, 2 ) ref -> rdx class-hnd "Inlining Arg" ; V51 tmp37 [V51,T63] ( 2, 1 ) byref -> rax "Inline return value spill temp" ; V52 tmp38 [V52,T56] ( 3, 1.50) ref -> r15 class-hnd "Inline stloc first use temp" ; V53 tmp39 [V53,T23] ( 4, 4 ) int -> [rsp+70H] "Inlining Arg" ; V54 tmp40 [V54,T49] ( 2, 2 ) long -> [rsp+68H] "Inlining Arg" ; V55 tmp41 [V55,T43] ( 4, 2 ) int -> [rsp+64H] "Inline stloc first use temp" ; V56 tmp42 [V56,T50] ( 2, 2 ) bool -> rcx "Inlining Arg" ;* V57 tmp43 [V57,T64] ( 0, 0 ) ref -> zero-ref class-hnd "Inlining Arg" ; V58 tmp44 [V58,T35] ( 3, 3 ) ref -> rdx class-hnd "Inlining Arg" ; V59 tmp45 [V59,T51] ( 2, 2 ) bool -> rcx "Inlining Arg" ;* V60 tmp46 [V60,T65] ( 0, 0 ) ref -> zero-ref class-hnd "Inlining Arg" ; V61 tmp47 [V61,T36] ( 3, 3 ) ref -> rdx class-hnd "Inlining Arg" ; V62 tmp48 [V62,T37] ( 3, 3 ) int -> rcx "index expr" ; V63 tmp49 [V63,T38] ( 3, 3 ) int -> rcx "index expr" ; V64 tmp50 [V64,T52] ( 2, 2 ) int -> rdx "argument with side effect" ; V65 cse0 [V65,T06] ( 4, 12.50) byref -> [rsp+30H] "CSE - aggressive" ; V66 cse1 [V66,T07] ( 4, 12.50) byref -> [rsp+28H] "CSE - aggressive" ; V67 cse2 [V67,T19] ( 3, 5 ) long -> r11 "CSE - moderate" ; V68 cse3 [V68,T61] ( 3, 1.25) long -> r11 "CSE - conservative" ; V69 cse4 [V69,T62] ( 3, 1.25) long -> rdx "CSE - conservative" ; V70 cse5 [V70,T12] ( 3, 10 ) long -> rdx "CSE - aggressive" ; V71 cse6 [V71,T13] ( 3, 10 ) long -> rcx "CSE - aggressive" ; V72 cse7 [V72,T58] ( 3, 1.50) int -> [rsp+60H] "CSE - conservative" ; V73 cse8 [V73,T10] ( 8, 6.50) ref -> r14 "CSE - aggressive" ; V74 cse9 [V74,T59] ( 3, 1.50) int -> rcx "CSE - conservative" ; V75 cse10 [V75,T60] ( 3, 1.50) int -> rcx "CSE - conservative" ; V76 cse11 [V76,T00] ( 9, 25.50) int -> [rsp+5CH] "CSE - aggressive" ; ; Lcl frame size = 152 *************** Before prolog / epilog generation G_M38507_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M38507_IG02: ; offs=000000H, size=0014H, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG03: ; offs=000014H, size=000AH, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG04: ; offs=00001EH, size=0023H, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG05: ; offs=000041H, size=0008H, gcrefRegs=000040E4 {rdx rbp rsi rdi r14}, byrefRegs=00000000 {}, byref G_M38507_IG06: ; offs=000049H, size=0018H, gcrefRegs=000040E0 {rbp rsi rdi r14}, byrefRegs=00000000 {}, byref G_M38507_IG07: ; offs=000061H, size=0012H, gcrefRegs=0000C0E4 {rdx rbp rsi rdi r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG08: ; offs=000073H, size=000DH, gcrefRegs=0000C0E0 {rbp rsi rdi r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG09: ; offs=000080H, size=0017H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG10: ; offs=000097H, size=0005H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG11: ; offs=00009CH, size=0012H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG12: ; offs=0000AEH, size=0011H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG13: ; offs=0000BFH, size=0010H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG14: ; offs=0000CFH, size=003FH, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG15: ; offs=00010EH, size=0008H, gcVars=00000000000000000000000000200000 {V39}, gcrefRegs=0000D0E4 {rdx rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG16: ; offs=000116H, size=0047H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG17: ; offs=00015DH, size=0008H, gcrefRegs=0000D0E4 {rdx rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG18: ; offs=000165H, size=0038H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG19: ; offs=00019DH, size=0017H, gcVars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG20: ; offs=0001B4H, size=0005H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG21: ; offs=0001B9H, size=0012H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG22: ; offs=0001CBH, size=0008H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG23: ; offs=0001D3H, size=0035H, gcrefRegs=0000D0E1 {rax rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG24: ; offs=000208H, size=0028H, gcVars=00000000000000000000000100000040 {V08 V65}, gcrefRegs=0000D0E1 {rax rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG25: ; offs=000230H, size=0037H, gcVars=00000000000000000000000100000040 {V08 V65}, gcrefRegs=0000D0E1 {rax rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG26: ; offs=000267H, size=001FH, gcVars=00000000000000000000000000000040 {V65}, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG27: ; offs=000286H, size=0009H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG28: ; offs=00028FH, size=0002H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M38507_IG29: ; epilog placeholder, next placeholder=IG46 , BB31 [0092], epilog, extend <-- First placeholder ; PrevGCVars=00000000000000000000000000000000 {}, PrevGCrefRegs=000000C0 {rsi rdi}, PrevByrefRegs=00000000 {} ; InitGCVars=00000000000000000000000000000000 {}, InitGCrefRegs=00000040 {rsi}, InitByrefRegs=00000000 {} G_M38507_IG30: ; offs=000391H, size=0035H, gcVars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG31: ; offs=0003C6H, size=0021H, gcVars=00000000000000000000000100000080 {V08 V66}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG32: ; offs=0003E7H, size=000AH, gcVars=00000000000000000000000100008080 {V08 V17 V66}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG33: ; offs=0003F1H, size=0017H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG34: ; offs=000408H, size=0014H, gcVars=00000000000000000000000100000080 {V08 V66}, gcrefRegs=0000D4E0 {rbp rsi rdi r10 r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG35: ; offs=00041CH, size=001FH, gcVars=00000000000000000000000000000080 {V66}, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG36: ; offs=00043BH, size=000EH, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG37: ; offs=000449H, size=0036H, gcVars=00000000000000000000000100000080 {V08 V66}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG38: ; offs=00047FH, size=0050H, gcVars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG39: ; offs=0004CFH, size=0029H, gcrefRegs=000090E0 {rbp rsi rdi r12 r15}, byrefRegs=00000000 {}, byref G_M38507_IG40: ; offs=0004F8H, size=005EH, gcrefRegs=000050E0 {rbp rsi rdi r12 r14}, byrefRegs=00000000 {}, byref G_M38507_IG41: ; offs=000556H, size=004CH, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG42: ; offs=0005A2H, size=0020H, gcrefRegs=000090E0 {rbp rsi rdi r12 r15}, byrefRegs=00000000 {}, byref G_M38507_IG43: ; offs=0005C2H, size=000AH, gcVars=00000000000000000000000100000000 {V08}, gcrefRegs=000010E0 {rbp rsi rdi r12}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG44: ; offs=0005CCH, size=0086H, gcrefRegs=000090E0 {rbp rsi rdi r12 r15}, byrefRegs=00000000 {}, byref G_M38507_IG45: ; offs=000652H, size=0005H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M38507_IG46: ; epilog placeholder, next placeholder=, BB58 [0091], epilog, extend <-- Last placeholder ; PrevGCVars=00000000000000000000000000000000 {}, PrevGCrefRegs=00000040 {rsi}, PrevByrefRegs=00000000 {} ; InitGCVars=00000000000000000000000000000000 {}, InitGCrefRegs=00000040 {rsi}, InitByrefRegs=00000000 {} G_M38507_IG47: ; offs=000757H, size=000BH, gcVars=00000000000000000000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG48: ; offs=000762H, size=0025H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG49: ; offs=000787H, size=0012H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG50: ; offs=000799H, size=0009H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG51: ; offs=0007A2H, size=0025H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG52: ; offs=0007C7H, size=0012H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG53: ; offs=0007D9H, size=0009H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG54: ; offs=0007E2H, size=0006H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M38507_IG55: ; offs=0007E8H, size=0000H, gcrefRegs=00000000 {} <-- Current IG Recording Var Locations at start of BB01 V00(rsi) V01(rdi) V03(rbx) V02(rbp) G_M38507_IG55: ; offs=0007E8H, funclet=00, bbWeight=0 *************** In genFnProlog() Added IP mapping to front: PROLOG STACK_EMPTY (G_M38507_IG01,ins#0,ofs#0) label __prolog: New debug range: first New debug range: first New debug range: first New debug range: first IN0167: push r15 IN0168: push r14 IN0169: push r13 IN016a: push r12 IN016b: push rdi IN016c: push rsi IN016d: push rbp IN016e: push rbx IN016f: sub rsp, 152 Reporting this as generic context: referenced IN0170: mov qword ptr [rsp+90H], rcx *************** In genFnPrologCalleeRegArgs() for int regs IN0171: mov rsi, rcx IN0172: mov rdi, rdx IN0173: mov rbp, r8 IN0174: mov ebx, r9d *************** In genEnregisterIncomingStackArgs() 6 tracked GC refs are at stack offsets 0028 ... 0058 G_M38507_IG01: ; offs=000000H, funclet=00, bbWeight=1 *************** In genFnEpilog() __epilog: gcVarPtrSetCur=00000000000000000000000000000000 {}, gcRegGCrefSetCur=00000040 {rsi}, gcRegByrefSetCur=00000000 {} IN0175: add rsp, 152 IN0176: pop rbx IN0177: pop rbp IN0178: pop rsi IN0179: pop rdi IN017a: pop r12 IN017b: pop r13 IN017c: pop r14 IN017d: pop r15 IN017e: ret G_M38507_IG29: ; offs=000291H, funclet=00, bbWeight=0.50 *************** In genFnEpilog() __epilog: gcVarPtrSetCur=00000000000000000000000000000000 {}, gcRegGCrefSetCur=00000040 {rsi}, gcRegByrefSetCur=00000000 {} IN017f: add rsp, 152 IN0180: pop rbx IN0181: pop rbp IN0182: pop rsi IN0183: pop rdi IN0184: pop r12 IN0185: pop r13 IN0186: pop r14 IN0187: pop r15 IN0188: ret G_M38507_IG46: ; offs=000657H, funclet=00, bbWeight=0.50 0 prologs, 2 epilogs, 0 funclet prologs, 0 funclet epilogs *************** After prolog / epilog generation G_M38507_IG01: ; func=00, offs=000000H, size=0027H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG G_M38507_IG02: ; offs=000027H, size=0014H, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG03: ; offs=00003BH, size=000AH, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG04: ; offs=000045H, size=0023H, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG05: ; offs=000068H, size=0008H, gcrefRegs=000040E4 {rdx rbp rsi rdi r14}, byrefRegs=00000000 {}, byref G_M38507_IG06: ; offs=000070H, size=0018H, gcrefRegs=000040E0 {rbp rsi rdi r14}, byrefRegs=00000000 {}, byref G_M38507_IG07: ; offs=000088H, size=0012H, gcrefRegs=0000C0E4 {rdx rbp rsi rdi r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG08: ; offs=00009AH, size=000DH, gcrefRegs=0000C0E0 {rbp rsi rdi r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG09: ; offs=0000A7H, size=0017H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG10: ; offs=0000BEH, size=0005H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG11: ; offs=0000C3H, size=0012H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG12: ; offs=0000D5H, size=0011H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG13: ; offs=0000E6H, size=0010H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG14: ; offs=0000F6H, size=003FH, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG15: ; offs=000135H, size=0008H, gcVars=00000000000000000000000000200000 {V39}, gcrefRegs=0000D0E4 {rdx rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG16: ; offs=00013DH, size=0047H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG17: ; offs=000184H, size=0008H, gcrefRegs=0000D0E4 {rdx rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG18: ; offs=00018CH, size=0038H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG19: ; offs=0001C4H, size=0017H, gcVars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG20: ; offs=0001DBH, size=0005H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG21: ; offs=0001E0H, size=0012H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG22: ; offs=0001F2H, size=0008H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG23: ; offs=0001FAH, size=0035H, gcrefRegs=0000D0E1 {rax rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG24: ; offs=00022FH, size=0028H, gcVars=00000000000000000000000100000040 {V08 V65}, gcrefRegs=0000D0E1 {rax rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG25: ; offs=000257H, size=0037H, gcVars=00000000000000000000000100000040 {V08 V65}, gcrefRegs=0000D0E1 {rax rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG26: ; offs=00028EH, size=001FH, gcVars=00000000000000000000000000000040 {V65}, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG27: ; offs=0002ADH, size=0009H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG28: ; offs=0002B6H, size=0002H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M38507_IG29: ; offs=0002B8H, size=0014H, epilog, nogc, extend G_M38507_IG30: ; offs=0002CCH, size=0035H, gcVars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG31: ; offs=000301H, size=0021H, gcVars=00000000000000000000000100000080 {V08 V66}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG32: ; offs=000322H, size=000AH, gcVars=00000000000000000000000100008080 {V08 V17 V66}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG33: ; offs=00032CH, size=0017H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG34: ; offs=000343H, size=0014H, gcVars=00000000000000000000000100000080 {V08 V66}, gcrefRegs=0000D4E0 {rbp rsi rdi r10 r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG35: ; offs=000357H, size=001FH, gcVars=00000000000000000000000000000080 {V66}, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG36: ; offs=000376H, size=000EH, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG37: ; offs=000384H, size=0036H, gcVars=00000000000000000000000100000080 {V08 V66}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG38: ; offs=0003BAH, size=0050H, gcVars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG39: ; offs=00040AH, size=0029H, gcrefRegs=000090E0 {rbp rsi rdi r12 r15}, byrefRegs=00000000 {}, byref G_M38507_IG40: ; offs=000433H, size=005EH, gcrefRegs=000050E0 {rbp rsi rdi r12 r14}, byrefRegs=00000000 {}, byref G_M38507_IG41: ; offs=000491H, size=004CH, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref G_M38507_IG42: ; offs=0004DDH, size=0020H, gcrefRegs=000090E0 {rbp rsi rdi r12 r15}, byrefRegs=00000000 {}, byref G_M38507_IG43: ; offs=0004FDH, size=000AH, gcVars=00000000000000000000000100000000 {V08}, gcrefRegs=000010E0 {rbp rsi rdi r12}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG44: ; offs=000507H, size=0086H, gcrefRegs=000090E0 {rbp rsi rdi r12 r15}, byrefRegs=00000000 {}, byref G_M38507_IG45: ; offs=00058DH, size=0005H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M38507_IG46: ; offs=000592H, size=0014H, epilog, nogc, extend G_M38507_IG47: ; offs=0005A6H, size=000BH, gcVars=00000000000000000000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, gcvars, byref G_M38507_IG48: ; offs=0005B1H, size=0025H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG49: ; offs=0005D6H, size=0012H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG50: ; offs=0005E8H, size=0009H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG51: ; offs=0005F1H, size=0025H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG52: ; offs=000616H, size=0012H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG53: ; offs=000628H, size=0009H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref G_M38507_IG54: ; offs=000631H, size=0006H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref G_M38507_IG55: ; offs=000637H, size=0006H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref *************** In emitJumpDistBind() Binding: IN0002: 000000 je L_M38507_BB59 Binding L_M38507_BB59 to G_M38507_IG47 Estimate of fwd jump [D1FFAB1E/002]: 002A -> 05A6 = 057A Binding: IN0004: 000000 jne L_M38507_BB04 Binding L_M38507_BB04 to G_M38507_IG04 Estimate of fwd jump [D1FFAB1E/004]: 0035 -> 0045 = 000E Shrinking jump [D1FFAB1E/004] Adjusted offset of BB03 from 003B to 0037 Adjusted offset of BB04 from 0045 to 0041 Binding: IN000f: 000000 jne L_M38507_BB06 Binding L_M38507_BB06 to G_M38507_IG06 Estimate of fwd jump [D1FFAB1E/015]: 005E -> 006C = 000C Shrinking jump [D1FFAB1E/015] Adjusted offset of BB05 from 0068 to 0060 Adjusted offset of BB06 from 0070 to 0068 Binding: IN0018: 000000 jne L_M38507_BB08 Binding L_M38507_BB08 to G_M38507_IG08 Estimate of fwd jump [D1FFAB1E/024]: 007A -> 0092 = 0016 Shrinking jump [D1FFAB1E/024] Adjusted offset of BB07 from 0088 to 007C Adjusted offset of BB08 from 009A to 008E Binding: IN001e: 000000 je L_M38507_BB13 Binding L_M38507_BB13 to G_M38507_IG13 Estimate of fwd jump [D1FFAB1E/030]: 0095 -> 00DA = 0043 Shrinking jump [D1FFAB1E/030] Adjusted offset of BB09 from 00A7 to 0097 Binding: IN0024: 000000 je L_M38507_BB11 Binding L_M38507_BB11 to G_M38507_IG11 Estimate of fwd jump [D1FFAB1E/036]: 00A8 -> 00B3 = 0009 Shrinking jump [D1FFAB1E/036] Adjusted offset of BB10 from 00BE to 00AA Binding: IN0025: 000000 jmp L_M38507_BB12 Binding L_M38507_BB12 to G_M38507_IG12 Estimate of fwd jump [D1FFAB1E/037]: 00AA -> 00C1 = 0015 Shrinking jump [D1FFAB1E/037] Adjusted offset of BB11 from 00C3 to 00AC Adjusted offset of BB12 from 00D5 to 00BE Binding: IN002d: 000000 jmp L_M38507_BB14 Binding L_M38507_BB14 to G_M38507_IG14 Estimate of fwd jump [D1FFAB1E/045]: 00CA -> 00DF = 0013 Shrinking jump [D1FFAB1E/045] Adjusted offset of BB13 from 00E6 to 00CC Adjusted offset of BB14 from 00F6 to 00DC Binding: IN0040: 000000 jne L_M38507_BB16 Binding L_M38507_BB16 to G_M38507_IG16 Estimate of fwd jump [D1FFAB1E/064]: 0115 -> 0123 = 000C Shrinking jump [D1FFAB1E/064] Adjusted offset of BB15 from 0135 to 0117 Adjusted offset of BB16 from 013D to 011F Binding: IN0055: 000000 jne L_M38507_BB18 Binding L_M38507_BB18 to G_M38507_IG18 Estimate of fwd jump [D1FFAB1E/085]: 0160 -> 016E = 000C Shrinking jump [D1FFAB1E/085] Adjusted offset of BB17 from 0184 to 0162 Adjusted offset of BB18 from 018C to 016A Binding: IN005b: 000000 jae L_M38507_BB69 Binding L_M38507_BB69 to G_M38507_IG55 Estimate of fwd jump [D1FFAB1E/091]: 0178 -> 0615 = 049B Binding: IN0063: 000000 jne L_M38507_BB32 Binding L_M38507_BB32 to G_M38507_IG30 Estimate of fwd jump [D1FFAB1E/099]: 019C -> 02AA = 010C Adjusted offset of BB19 from 01C4 to 01A2 Binding: IN0069: 000000 je L_M38507_BB21 Binding L_M38507_BB21 to G_M38507_IG21 Estimate of fwd jump [D1FFAB1E/105]: 01B3 -> 01BE = 0009 Shrinking jump [D1FFAB1E/105] Adjusted offset of BB20 from 01DB to 01B5 Binding: IN006a: 000000 jmp L_M38507_BB22 Binding L_M38507_BB22 to G_M38507_IG22 Estimate of fwd jump [D1FFAB1E/106]: 01B5 -> 01CC = 0015 Shrinking jump [D1FFAB1E/106] Adjusted offset of BB21 from 01E0 to 01B7 Adjusted offset of BB22 from 01F2 to 01C9 Adjusted offset of BB23 from 01FA to 01D1 Binding: IN0074: 000000 jbe L_M38507_BB44 Binding L_M38507_BB44 to G_M38507_IG38 Estimate of fwd jump [D1FFAB1E/116]: 01E5 -> 0391 = 01AA Binding: IN007a: 000000 jne L_M38507_BB26 Binding L_M38507_BB26 to G_M38507_IG25 Estimate of fwd jump [D1FFAB1E/122]: 0200 -> 022E = 002C Shrinking jump [D1FFAB1E/122] Adjusted offset of BB24 from 022F to 0202 Binding: IN0084: 000000 jne L_M38507_BB28 Binding L_M38507_BB28 to G_M38507_IG26 Estimate of fwd jump [D1FFAB1E/132]: 0224 -> 0261 = 003B Shrinking jump [D1FFAB1E/132] Adjusted offset of BB25 from 0257 to 0226 Binding: IN008b: 000000 jb L_M38507_BB68 Binding L_M38507_BB68 to G_M38507_IG54 Estimate of fwd jump [D1FFAB1E/139]: 0242 -> 0600 = 03BC Binding: IN008e: 000000 jmp L_M38507_BB23 Binding L_M38507_BB23 to G_M38507_IG23 Estimate of bwd jump [D1FFAB1E/142]: 0258 -> 01D1 = 0089 Adjusted offset of BB26 from 028E to 025D Binding: IN0090: 000000 jne L_M38507_BB30 Binding L_M38507_BB30 to G_M38507_IG27 Estimate of fwd jump [D1FFAB1E/144]: 0260 -> 027C = 001A Shrinking jump [D1FFAB1E/144] Binding: IN0095: 000000 jmp L_M38507_BB58 Binding L_M38507_BB58 to G_M38507_IG45 Estimate of fwd jump [D1FFAB1E/149]: 0273 -> 0558 = 02E3 Adjusted offset of BB27 from 02AD to 0278 Binding: IN0097: 000000 je L_M38507_BB60 Binding L_M38507_BB60 to G_M38507_IG48 Estimate of fwd jump [D1FFAB1E/151]: 027B -> 057C = 02FF Adjusted offset of BB28 from 02B6 to 0281 Adjusted offset of BB29 from 02B8 to 0283 Adjusted offset of BB30 from 02CC to 0297 Binding: IN009d: 000000 jbe L_M38507_BB44 Binding L_M38507_BB44 to G_M38507_IG38 Estimate of fwd jump [D1FFAB1E/157]: 02AB -> 0385 = 00D8 Binding: IN00a3: 000000 jne L_M38507_BB42 Binding L_M38507_BB42 to G_M38507_IG37 Estimate of fwd jump [D1FFAB1E/163]: 02C6 -> 034F = 0087 Adjusted offset of BB31 from 0301 to 02CC Binding: IN00ab: 000000 je L_M38507_BB36 Binding L_M38507_BB36 to G_M38507_IG33 Estimate of fwd jump [D1FFAB1E/171]: 02E7 -> 02F7 = 000E Shrinking jump [D1FFAB1E/171] Adjusted offset of BB32 from 0322 to 02E9 Binding: IN00ad: 000000 jmp L_M38507_BB37 Binding L_M38507_BB37 to G_M38507_IG34 Estimate of fwd jump [D1FFAB1E/173]: 02EE -> 030A = 001A Shrinking jump [D1FFAB1E/173] Adjusted offset of BB33 from 032C to 02F0 Adjusted offset of BB34 from 0343 to 0307 Binding: IN00b7: 000000 je L_M38507_BB42 Binding L_M38507_BB42 to G_M38507_IG37 Estimate of fwd jump [D1FFAB1E/183]: 0315 -> 0348 = 0031 Shrinking jump [D1FFAB1E/183] Adjusted offset of BB35 from 0357 to 0317 Binding: IN00b9: 000000 jne L_M38507_BB40 Binding L_M38507_BB40 to G_M38507_IG36 Estimate of fwd jump [D1FFAB1E/185]: 031A -> 0336 = 001A Shrinking jump [D1FFAB1E/185] Binding: IN00be: 000000 jmp L_M38507_BB58 Binding L_M38507_BB58 to G_M38507_IG45 Estimate of fwd jump [D1FFAB1E/190]: 032D -> 0549 = 021A Adjusted offset of BB36 from 0376 to 0332 Binding: IN00c0: 000000 je L_M38507_BB64 Binding L_M38507_BB64 to G_M38507_IG51 Estimate of fwd jump [D1FFAB1E/192]: 0335 -> 05AD = 0276 Binding: IN00c1: 000000 jmp L_M38507_BB31 Binding L_M38507_BB31 to G_M38507_IG28 Estimate of bwd jump [D1FFAB1E/193]: 033B -> 0281 = 00BC Adjusted offset of BB37 from 0384 to 0340 Binding: IN00c9: 000000 jb L_M38507_BB68 Binding L_M38507_BB68 to G_M38507_IG54 Estimate of fwd jump [D1FFAB1E/201]: 0364 -> 05ED = 0287 Binding: IN00cb: 000000 jmp L_M38507_BB32 Binding L_M38507_BB32 to G_M38507_IG30 Estimate of bwd jump [D1FFAB1E/203]: 0371 -> 0297 = 00DC Adjusted offset of BB38 from 03BA to 0376 Binding: IN00cd: 000000 jle L_M38507_BB48 Binding L_M38507_BB48 to G_M38507_IG40 Estimate of fwd jump [D1FFAB1E/205]: 037A -> 03EF = 0073 Shrinking jump [D1FFAB1E/205] Binding: IN00d1: 000000 jae L_M38507_BB69 Binding L_M38507_BB69 to G_M38507_IG55 Estimate of fwd jump [D1FFAB1E/209]: 0385 -> 05EF = 0268 Binding: IN00dc: 000000 jne L_M38507_BB47 Binding L_M38507_BB47 to G_M38507_IG39 Estimate of fwd jump [D1FFAB1E/220]: 03AA -> 03C2 = 0016 Shrinking jump [D1FFAB1E/220] Adjusted offset of BB39 from 040A to 03BE Binding: IN00e2: 000000 jae L_M38507_BB69 Binding L_M38507_BB69 to G_M38507_IG55 Estimate of fwd jump [D1FFAB1E/226]: 03C5 -> 05EB = 0224 Binding: IN00ea: 000000 jmp L_M38507_BB55 Binding L_M38507_BB55 to G_M38507_IG44 Estimate of fwd jump [D1FFAB1E/234]: 03E2 -> 04BB = 00D7 Adjusted offset of BB40 from 0433 to 03E7 Binding: IN00ee: 000000 jne L_M38507_BB54 Binding L_M38507_BB54 to G_M38507_IG43 Estimate of fwd jump [D1FFAB1E/238]: 03F0 -> 04B1 = 00BF Binding: IN0100: 000000 jne L_M38507_BB51 Binding L_M38507_BB51 to G_M38507_IG41 Estimate of fwd jump [D1FFAB1E/256]: 0437 -> 0445 = 000C Shrinking jump [D1FFAB1E/256] Adjusted offset of BB41 from 0491 to 0441 Binding: IN0115: 000000 jne L_M38507_BB53 Binding L_M38507_BB53 to G_M38507_IG42 Estimate of fwd jump [D1FFAB1E/277]: 047F -> 048D = 000C Shrinking jump [D1FFAB1E/277] Adjusted offset of BB42 from 04DD to 0489 Binding: IN011a: 000000 jae L_M38507_BB69 Binding L_M38507_BB69 to G_M38507_IG55 Estimate of fwd jump [D1FFAB1E/282]: 0493 -> 05E3 = 014E Adjusted offset of BB43 from 04FD to 04A9 Adjusted offset of BB44 from 0507 to 04B3 Binding: IN0123: 000000 jae L_M38507_BB69 Binding L_M38507_BB69 to G_M38507_IG55 Estimate of fwd jump [D1FFAB1E/291]: 04B7 -> 05E3 = 012A Binding: IN0137: 000000 jbe L_M38507_BB58 Binding L_M38507_BB58 to G_M38507_IG45 Estimate of fwd jump [D1FFAB1E/311]: 0506 -> 0539 = 0031 Shrinking jump [D1FFAB1E/311] Binding: IN013c: 000000 je L_M38507_BB58 Binding L_M38507_BB58 to G_M38507_IG45 Estimate of fwd jump [D1FFAB1E/316]: 051D -> 0535 = 0016 Shrinking jump [D1FFAB1E/316] Adjusted offset of BB45 from 058D to 0531 Adjusted offset of BB46 from 0592 to 0536 Adjusted offset of BB47 from 05A6 to 054A Adjusted offset of BB48 from 05B1 to 0555 Binding: IN0149: 000000 je L_M38507_BB62 Binding L_M38507_BB62 to G_M38507_IG49 Estimate of fwd jump [D1FFAB1E/329]: 0564 -> 057A = 0014 Shrinking jump [D1FFAB1E/329] Binding: IN014d: 000000 jmp L_M38507_BB63 Binding L_M38507_BB63 to G_M38507_IG50 Estimate of fwd jump [D1FFAB1E/333]: 0571 -> 0588 = 0015 Shrinking jump [D1FFAB1E/333] Adjusted offset of BB49 from 05D6 to 0573 Adjusted offset of BB50 from 05E8 to 0585 Adjusted offset of BB51 from 05F1 to 058E Binding: IN0158: 000000 je L_M38507_BB66 Binding L_M38507_BB66 to G_M38507_IG52 Estimate of fwd jump [D1FFAB1E/344]: 059D -> 05B3 = 0014 Shrinking jump [D1FFAB1E/344] Binding: IN015c: 000000 jmp L_M38507_BB67 Binding L_M38507_BB67 to G_M38507_IG53 Estimate of fwd jump [D1FFAB1E/348]: 05AA -> 05C1 = 0015 Shrinking jump [D1FFAB1E/348] Adjusted offset of BB52 from 0616 to 05AC Adjusted offset of BB53 from 0628 to 05BE Adjusted offset of BB54 from 0631 to 05C7 Adjusted offset of BB55 from 0637 to 05CD Total shrinkage = 106, min extra jump size = 8 Iterating branch shortening. Iteration = 2 Estimate of fwd jump [D1FFAB1E/002]: 002A -> 054A = 051E Adjusted offset of BB03 from 0037 to 0037 Adjusted offset of BB04 from 0041 to 0041 Adjusted offset of BB05 from 0060 to 0060 Adjusted offset of BB06 from 0068 to 0068 Adjusted offset of BB07 from 007C to 007C Adjusted offset of BB08 from 008E to 008E Adjusted offset of BB09 from 0097 to 0097 Adjusted offset of BB10 from 00AA to 00AA Adjusted offset of BB11 from 00AC to 00AC Adjusted offset of BB12 from 00BE to 00BE Adjusted offset of BB13 from 00CC to 00CC Adjusted offset of BB14 from 00DC to 00DC Adjusted offset of BB15 from 0117 to 0117 Adjusted offset of BB16 from 011F to 011F Adjusted offset of BB17 from 0162 to 0162 Adjusted offset of BB18 from 016A to 016A Estimate of fwd jump [D1FFAB1E/091]: 0178 -> 05CD = 0453 Estimate of fwd jump [D1FFAB1E/099]: 019C -> 0297 = 00F9 Adjusted offset of BB19 from 01A2 to 01A2 Adjusted offset of BB20 from 01B5 to 01B5 Adjusted offset of BB21 from 01B7 to 01B7 Adjusted offset of BB22 from 01C9 to 01C9 Adjusted offset of BB23 from 01D1 to 01D1 Estimate of fwd jump [D1FFAB1E/116]: 01E5 -> 0376 = 018F Adjusted offset of BB24 from 0202 to 0202 Adjusted offset of BB25 from 0226 to 0226 Estimate of fwd jump [D1FFAB1E/139]: 0242 -> 05C7 = 0383 Estimate of bwd jump [D1FFAB1E/142]: 0258 -> 01D1 = 0089 Adjusted offset of BB26 from 025D to 025D Estimate of fwd jump [D1FFAB1E/149]: 0273 -> 0531 = 02BC Adjusted offset of BB27 from 0278 to 0278 Estimate of fwd jump [D1FFAB1E/151]: 027B -> 0555 = 02D8 Adjusted offset of BB28 from 0281 to 0281 Adjusted offset of BB29 from 0283 to 0283 Adjusted offset of BB30 from 0297 to 0297 Estimate of fwd jump [D1FFAB1E/157]: 02AB -> 0376 = 00C9 Estimate of fwd jump [D1FFAB1E/163]: 02C6 -> 0340 = 0078 Shrinking jump [D1FFAB1E/163] Adjusted offset of BB31 from 02CC to 02C8 Adjusted offset of BB32 from 02E9 to 02E5 Adjusted offset of BB33 from 02F0 to 02EC Adjusted offset of BB34 from 0307 to 0303 Adjusted offset of BB35 from 0317 to 0313 Estimate of fwd jump [D1FFAB1E/190]: 0329 -> 052D = 0202 Adjusted offset of BB36 from 0332 to 032E Estimate of fwd jump [D1FFAB1E/192]: 0331 -> 058A = 0257 Estimate of bwd jump [D1FFAB1E/193]: 0337 -> 0281 = 00B8 Adjusted offset of BB37 from 0340 to 033C Estimate of fwd jump [D1FFAB1E/201]: 0360 -> 05C3 = 0261 Estimate of bwd jump [D1FFAB1E/203]: 036D -> 0297 = 00D8 Adjusted offset of BB38 from 0376 to 0372 Estimate of fwd jump [D1FFAB1E/209]: 0381 -> 05C9 = 0246 Adjusted offset of BB39 from 03BE to 03BA Estimate of fwd jump [D1FFAB1E/226]: 03C1 -> 05C9 = 0206 Estimate of fwd jump [D1FFAB1E/234]: 03DE -> 04AF = 00CF Adjusted offset of BB40 from 03E7 to 03E3 Estimate of fwd jump [D1FFAB1E/238]: 03EC -> 04A5 = 00B7 Adjusted offset of BB41 from 0441 to 043D Adjusted offset of BB42 from 0489 to 0485 Estimate of fwd jump [D1FFAB1E/282]: 048F -> 05C9 = 0138 Adjusted offset of BB43 from 04A9 to 04A5 Adjusted offset of BB44 from 04B3 to 04AF Estimate of fwd jump [D1FFAB1E/291]: 04B3 -> 05C9 = 0114 Adjusted offset of BB45 from 0531 to 052D Adjusted offset of BB46 from 0536 to 0532 Adjusted offset of BB47 from 054A to 0546 Adjusted offset of BB48 from 0555 to 0551 Adjusted offset of BB49 from 0573 to 056F Adjusted offset of BB50 from 0585 to 0581 Adjusted offset of BB51 from 058E to 058A Adjusted offset of BB52 from 05AC to 05A8 Adjusted offset of BB53 from 05BE to 05BA Adjusted offset of BB54 from 05C7 to 05C3 Adjusted offset of BB55 from 05CD to 05C9 Total shrinkage = 4, min extra jump size = 9 *************** Finishing PHASE Generate code *************** Starting PHASE Emit code Hot code size = 0x5CF bytes Cold code size = 0x0 bytes reserveUnwindInfo(isFunclet=false, isColdCode=false, unwindSize=0x18) *************** In emitEndCodeGen() Converting emitMaxStackDepth from bytes (0) to elements (0) *************************************************************************** Instructions as they come out of the scheduler G_M38507_IG01: ; func=00, offs=000000H, size=0027H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG IN0167: 000000 push r15 IN0168: 000002 push r14 IN0169: 000004 push r13 IN016a: 000006 push r12 IN016b: 000008 push rdi IN016c: 000009 push rsi IN016d: 00000A push rbp IN016e: 00000B push rbx IN016f: 00000C sub rsp, 152 IN0170: 000013 mov qword ptr [rsp+90H], rcx IN0171: 00001B mov rsi, rcx ; gcrRegs +[rsi] IN0172: 00001E mov rdi, rdx ; gcrRegs +[rdi] IN0173: 000021 mov rbp, r8 ; gcrRegs +[rbp] IN0174: 000024 mov ebx, r9d ;; bbWeight=1 PerfScore 10.25 G_M38507_IG02: ; func=00, offs=000027H, size=0010H, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, byref, isz IN0001: 000027 test rdi, rdi IN0002: 00002A je G_M38507_IG47 IN0003: 000030 cmp gword ptr [rsi+8], 0 IN0004: 000035 jne SHORT G_M38507_IG04 ;; bbWeight=1 PerfScore 4.25 G_M38507_IG03: ; func=00, offs=000037H, size=000AH, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, byref IN0005: 000037 mov rcx, rsi ; gcrRegs +[rcx] IN0006: 00003A xor edx, edx IN0007: 00003C call System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Initialize(int):int:this ; gcrRegs -[rcx] ; gcr arg pop 0 ;; bbWeight=0.50 PerfScore 0.75 G_M38507_IG04: ; func=00, offs=000041H, size=001FH, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, byref, isz IN0008: 000041 cmp gword ptr [rsi+8], 0 IN0009: 000046 setne cl IN000a: 000049 movzx rcx, cl IN000b: 00004C mov rdx, 0xD1FFAB1E IN000c: 000056 mov r14, gword ptr [rdx] ; gcrRegs +[r14] IN000d: 000059 mov rdx, r14 ; gcrRegs +[rdx] IN000e: 00005C test ecx, ecx IN000f: 00005E jne SHORT G_M38507_IG06 ;; bbWeight=1 PerfScore 7.00 G_M38507_IG05: ; func=00, offs=000060H, size=0008H, gcrefRegs=000040E4 {rdx rbp rsi rdi r14}, byrefRegs=00000000 {}, byref IN0010: 000060 mov rcx, rdx ; gcrRegs +[rcx] IN0011: 000063 call System.Diagnostics.Debug:Fail(System.String,System.String) ; gcrRegs -[rcx rdx] ; gcr arg pop 0 ;; bbWeight=0.50 PerfScore 0.63 G_M38507_IG06: ; func=00, offs=000068H, size=0014H, gcrefRegs=000040E0 {rbp rsi rdi r14}, byrefRegs=00000000 {}, byref, isz IN0012: 000068 mov r15, gword ptr [rsi+16] ; gcrRegs +[r15] IN0013: 00006C test r15, r15 IN0014: 00006F setne cl IN0015: 000072 movzx rcx, cl IN0016: 000075 mov rdx, r14 ; gcrRegs +[rdx] IN0017: 000078 test ecx, ecx IN0018: 00007A jne SHORT G_M38507_IG08 ;; bbWeight=1 PerfScore 5.00 G_M38507_IG07: ; func=00, offs=00007CH, size=0012H, gcrefRegs=0000C0E4 {rdx rbp rsi rdi r14 r15}, byrefRegs=00000000 {}, byref IN0019: 00007C mov rcx, 0xD1FFAB1E IN001a: 000086 mov rcx, gword ptr [rcx] ; gcrRegs +[rcx] IN001b: 000089 call System.Diagnostics.Debug:Fail(System.String,System.String) ; gcrRegs -[rcx rdx] ; gcr arg pop 0 ;; bbWeight=0.50 PerfScore 1.63 G_M38507_IG08: ; func=00, offs=00008EH, size=0009H, gcrefRegs=0000C0E0 {rbp rsi rdi r14 r15}, byrefRegs=00000000 {}, byref, isz IN001c: 00008E mov r12, gword ptr [rsi+24] ; gcrRegs +[r12] IN001d: 000092 test r12, r12 IN001e: 000095 je SHORT G_M38507_IG13 ;; bbWeight=1 PerfScore 3.25 G_M38507_IG09: ; func=00, offs=000097H, size=0013H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref, isz IN001f: 000097 mov rcx, qword ptr [rsi] IN0020: 00009A mov rdx, qword ptr [rcx+56] IN0021: 00009E mov rdx, qword ptr [rdx] IN0022: 0000A1 mov r11, qword ptr [rdx+64] IN0023: 0000A5 test r11, r11 IN0024: 0000A8 je SHORT G_M38507_IG11 ;; bbWeight=0.50 PerfScore 4.63 G_M38507_IG10: ; func=00, offs=0000AAH, size=0002H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref, isz IN0025: 0000AA jmp SHORT G_M38507_IG12 ;; bbWeight=0.25 PerfScore 0.50 G_M38507_IG11: ; func=00, offs=0000ACH, size=0012H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref IN0026: 0000AC mov rdx, 0xD1FFAB1E IN0027: 0000B6 call CORINFO_HELP_RUNTIMEHANDLE_CLASS ; gcr arg pop 0 IN0028: 0000BB mov r11, rax ;; bbWeight=0.25 PerfScore 0.38 G_M38507_IG12: ; func=00, offs=0000BEH, size=000EH, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref, isz IN0029: 0000BE mov rcx, r12 ; gcrRegs +[rcx] IN002a: 0000C1 mov rdx, rdi ; gcrRegs +[rdx] IN002b: 0000C4 call qword ptr [r11] ; gcrRegs -[rcx rdx] ; gcr arg pop 0 IN002c: 0000C7 mov r13d, eax IN002d: 0000CA jmp SHORT G_M38507_IG14 ;; bbWeight=0.50 PerfScore 2.88 G_M38507_IG13: ; func=00, offs=0000CCH, size=0010H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref IN002e: 0000CC mov rcx, rdi ; gcrRegs +[rcx] IN002f: 0000CF mov rax, qword ptr [rdi] IN0030: 0000D2 mov rax, qword ptr [rax+72] IN0031: 0000D6 call qword ptr [rax+24]System.Object:GetHashCode():int:this ; gcrRegs -[rcx] ; gcr arg pop 0 IN0032: 0000D9 mov r13d, eax ;; bbWeight=0.50 PerfScore 3.75 G_M38507_IG14: ; func=00, offs=0000DCH, size=003BH, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref, isz IN0033: 0000DC xor eax, eax IN0034: 0000DE mov dword ptr [rsp+8CH], eax IN0035: 0000E5 mov r8, gword ptr [rsi+8] ; gcrRegs +[r8] IN0036: 0000E9 mov gword ptr [rsp+38H], r8 ; GC ptr vars +{V39} IN0037: 0000EE mov r9d, dword ptr [r8+8] IN0038: 0000F2 mov r10, qword ptr [rsi+48] IN0039: 0000F6 mov qword ptr [rsp+78H], r10 IN003a: 0000FB mov dword ptr [rsp+84H], r9d IN003b: 000103 cmp r9d, 0xD1FFAB1E IN003c: 00010A setbe cl IN003d: 00010D movzx rcx, cl IN003e: 000110 mov rdx, r14 ; gcrRegs +[rdx] IN003f: 000113 test ecx, ecx IN0040: 000115 jne SHORT G_M38507_IG16 ;; bbWeight=1 PerfScore 13.25 G_M38507_IG15: ; func=00, offs=000117H, size=0008H, gcVars=00000000000000000000000000200000 {V39}, gcrefRegs=0000D0E4 {rdx rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref ; gcrRegs -[r8] IN0041: 000117 mov rcx, rdx ; gcrRegs +[rcx] IN0042: 00011A call System.Diagnostics.Debug:Fail(System.String,System.String) ; gcrRegs -[rcx rdx] ; gcr arg pop 0 ;; bbWeight=0.50 PerfScore 0.63 G_M38507_IG16: ; func=00, offs=00011FH, size=0043H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref, isz IN0043: 00011F mov edx, r13d IN0044: 000122 imul rdx, qword ptr [rsp+78H] IN0045: 000128 shr rdx, 32 IN0046: 00012C inc rdx IN0047: 00012F mov r9d, dword ptr [rsp+84H] IN0048: 000137 mov ecx, r9d IN0049: 00013A imul rdx, rcx IN004a: 00013E shr rdx, 32 IN004b: 000142 mov r10d, edx IN004c: 000145 mov eax, r13d IN004d: 000148 xor edx, edx IN004e: 00014A div edx:eax, r9d IN004f: 00014D mov dword ptr [rsp+74H], r10d IN0050: 000152 cmp edx, r10d IN0051: 000155 sete cl IN0052: 000158 movzx rcx, cl IN0053: 00015B mov rdx, r14 ; gcrRegs +[rdx] IN0054: 00015E test ecx, ecx IN0055: 000160 jne SHORT G_M38507_IG18 ;; bbWeight=1 PerfScore 38.50 G_M38507_IG17: ; func=00, offs=000162H, size=0008H, gcrefRegs=0000D0E4 {rdx rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref IN0056: 000162 mov rcx, rdx ; gcrRegs +[rcx] IN0057: 000165 call System.Diagnostics.Debug:Fail(System.String,System.String) ; gcrRegs -[rcx rdx] ; gcr arg pop 0 ;; bbWeight=0.50 PerfScore 0.63 G_M38507_IG18: ; func=00, offs=00016AH, size=0038H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref IN0058: 00016A mov r10d, dword ptr [rsp+74H] IN0059: 00016F mov r8, gword ptr [rsp+38H] ; gcrRegs +[r8] IN005a: 000174 cmp r10d, dword ptr [r8+8] IN005b: 000178 jae G_M38507_IG55 IN005c: 00017E movsxd rcx, r10d IN005d: 000181 lea rax, bword ptr [r8+4*rcx+16] ; byrRegs +[rax] IN005e: 000186 mov bword ptr [rsp+50H], rax ; GC ptr vars +{V08} IN005f: 00018B mov r8d, dword ptr [rax] ; gcrRegs -[r8] IN0060: 00018E dec r8d IN0061: 000191 mov dword ptr [rsp+88H], r8d IN0062: 000199 test r12, r12 IN0063: 00019C jne G_M38507_IG30 ;; bbWeight=1 PerfScore 11.75 G_M38507_IG19: ; func=00, offs=0001A2H, size=0013H, gcVars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref, isz Reporting this as generic context: referenced ; byrRegs -[rax] ; GC ptr vars -{V39} IN0064: 0001A2 mov rcx, qword ptr [rsi] IN0065: 0001A5 mov rdx, qword ptr [rcx+56] IN0066: 0001A9 mov rdx, qword ptr [rdx] IN0067: 0001AC mov rdx, qword ptr [rdx+32] IN0068: 0001B0 test rdx, rdx IN0069: 0001B3 je SHORT G_M38507_IG21 ;; bbWeight=0.50 PerfScore 4.63 G_M38507_IG20: ; func=00, offs=0001B5H, size=0002H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref, isz IN006a: 0001B5 jmp SHORT G_M38507_IG22 ;; bbWeight=0.25 PerfScore 0.50 G_M38507_IG21: ; func=00, offs=0001B7H, size=0012H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref IN006b: 0001B7 mov rdx, 0xD1FFAB1E IN006c: 0001C1 call CORINFO_HELP_RUNTIMEHANDLE_CLASS ; gcr arg pop 0 IN006d: 0001C6 mov rdx, rax ;; bbWeight=0.25 PerfScore 0.38 G_M38507_IG22: ; func=00, offs=0001C9H, size=0008H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref IN006e: 0001C9 mov rcx, rdx IN006f: 0001CC call System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon]:get_Default():System.Collections.Generic.EqualityComparer`1[__Canon] ; gcrRegs +[rax] ; gcr arg pop 0 ;; bbWeight=0.50 PerfScore 0.63 G_M38507_IG23: ; func=00, offs=0001D1H, size=0031H, gcrefRegs=0000D0E1 {rax rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref, isz IN0070: 0001D1 mov r9d, dword ptr [r15+8] IN0071: 0001D5 mov dword ptr [rsp+5CH], r9d IN0072: 0001DA mov r10d, dword ptr [rsp+88H] IN0073: 0001E2 cmp r9d, r10d IN0074: 0001E5 jbe G_M38507_IG38 IN0075: 0001EB movsxd rdx, r10d IN0076: 0001EE lea rdx, [rdx+2*rdx] IN0077: 0001F2 lea r11, bword ptr [r15+8*rdx+16] ; byrRegs +[r11] IN0078: 0001F7 mov bword ptr [rsp+30H], r11 ; GC ptr vars +{V65} IN0079: 0001FC cmp dword ptr [r11+16], r13d IN007a: 000200 jne SHORT G_M38507_IG25 ;; bbWeight=4 PerfScore 44.00 G_M38507_IG24: ; func=00, offs=000202H, size=0024H, gcVars=00000000000000000000000100000040 {V08 V65}, gcrefRegs=0000D0E1 {rax rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref, isz ; byrRegs -[r11] IN007b: 000202 mov rdx, gword ptr [r15+8*rdx+16] ; gcrRegs +[rdx] IN007c: 000207 mov rcx, rax ; gcrRegs +[rcx] IN007d: 00020A mov r8, rdi ; gcrRegs +[r8] IN007e: 00020D mov gword ptr [rsp+48H], rax ; GC ptr vars +{V12} IN007f: 000212 mov r10, qword ptr [rax] IN0080: 000215 mov r10, qword ptr [r10+72] IN0081: 000219 call qword ptr [r10+32]System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon]:Equals(System.__Canon,System.__Canon):bool:this ; gcrRegs -[rax rcx rdx r8] ; gcr arg pop 0 IN0082: 00021D test eax, eax IN0083: 00021F mov rax, gword ptr [rsp+48H] ; gcrRegs +[rax] IN0084: 000224 jne SHORT G_M38507_IG26 ;; bbWeight=2 PerfScore 25.50 G_M38507_IG25: ; func=00, offs=000226H, size=0037H, gcVars=00000000000000000000000100000040 {V08 V65}, gcrefRegs=0000D0E1 {rax rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref Reporting this as generic context: referenced ; GC ptr vars -{V12} IN0085: 000226 mov r11, bword ptr [rsp+30H] ; byrRegs +[r11] IN0086: 00022B mov r10d, dword ptr [r11+20] IN0087: 00022F mov r8d, r10d IN0088: 000232 mov r11d, dword ptr [rsp+8CH] ; byrRegs -[r11] IN0089: 00023A inc r11d IN008a: 00023D cmp dword ptr [rsp+5CH], r11d IN008b: 000242 jb G_M38507_IG54 IN008c: 000248 mov dword ptr [rsp+8CH], r11d IN008d: 000250 mov dword ptr [rsp+88H], r8d IN008e: 000258 jmp G_M38507_IG23 ;; bbWeight=4 PerfScore 42.00 G_M38507_IG26: ; func=00, offs=00025DH, size=001BH, gcVars=00000000000000000000000000000040 {V65}, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, gcvars, byref, isz Reporting this as generic context: referenced ; gcrRegs -[rax r12 r14-r15] ; GC ptr vars -{V08} IN008f: 00025D cmp bl, 1 IN0090: 000260 jne SHORT G_M38507_IG27 IN0091: 000262 mov r11, bword ptr [rsp+30H] ; byrRegs +[r11] IN0092: 000267 lea rcx, bword ptr [r11+8] ; byrRegs +[rcx] IN0093: 00026B mov rdx, rbp ; gcrRegs +[rdx] Reporting this as generic context: referenced ; GC ptr vars -{V65} IN0094: 00026E call CORINFO_HELP_CHECKED_ASSIGN_REF ; gcrRegs -[rdx rbp rdi] ; byrRegs -[rcx r11] IN0095: 000273 jmp G_M38507_IG45 ;; bbWeight=0.50 PerfScore 3.00 G_M38507_IG27: ; func=00, offs=000278H, size=0009H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref ; gcrRegs +[rdi] IN0096: 000278 cmp bl, 2 IN0097: 00027B je G_M38507_IG48 ;; bbWeight=0.50 PerfScore 0.63 G_M38507_IG28: ; func=00, offs=000281H, size=0002H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref ; gcrRegs -[rdi] IN0098: 000281 xor eax, eax ;; bbWeight=0.50 PerfScore 0.13 G_M38507_IG29: ; func=00, offs=000283H, size=0014H, epilog, nogc, extend IN0175: 000283 add rsp, 152 IN0176: 00028A pop rbx IN0177: 00028B pop rbp IN0178: 00028C pop rsi IN0179: 00028D pop rdi IN017a: 00028E pop r12 IN017b: 000290 pop r13 IN017c: 000292 pop r14 IN017d: 000294 pop r15 IN017e: 000296 ret ;; bbWeight=0.50 PerfScore 2.63 G_M38507_IG30: ; func=00, offs=000297H, size=0031H, gcVars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref, isz ; gcrRegs +[rbp rdi r12 r14-r15] ; GC ptr vars +{V08} IN0099: 000297 mov r9d, dword ptr [r15+8] IN009a: 00029B mov dword ptr [rsp+5CH], r9d IN009b: 0002A0 mov r8d, dword ptr [rsp+88H] IN009c: 0002A8 cmp r9d, r8d IN009d: 0002AB jbe G_M38507_IG38 IN009e: 0002B1 movsxd rcx, r8d IN009f: 0002B4 lea rcx, [rcx+2*rcx] IN00a0: 0002B8 lea r8, bword ptr [r15+8*rcx+16] ; byrRegs +[r8] IN00a1: 0002BD mov bword ptr [rsp+28H], r8 ; GC ptr vars +{V66} IN00a2: 0002C2 cmp dword ptr [r8+16], r13d IN00a3: 0002C6 jne SHORT G_M38507_IG37 ;; bbWeight=4 PerfScore 44.00 G_M38507_IG31: ; func=00, offs=0002C8H, size=001DH, gcVars=00000000000000000000000100000080 {V08 V66}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref, isz ; byrRegs -[r8] IN00a4: 0002C8 mov r10, gword ptr [r15+8*rcx+16] ; gcrRegs +[r10] IN00a5: 0002CD mov gword ptr [rsp+40H], r10 ; GC ptr vars +{V17} IN00a6: 0002D2 mov rcx, qword ptr [rsi] IN00a7: 0002D5 mov rdx, qword ptr [rcx+56] IN00a8: 0002D9 mov rdx, qword ptr [rdx] IN00a9: 0002DC mov r11, qword ptr [rdx+48] IN00aa: 0002E0 test r11, r11 IN00ab: 0002E3 je SHORT G_M38507_IG33 ;; bbWeight=2 PerfScore 24.50 G_M38507_IG32: ; func=00, offs=0002E5H, size=0007H, gcVars=00000000000000000000000100008080 {V08 V17 V66}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref, isz ; gcrRegs -[r10] IN00ac: 0002E5 mov r10, gword ptr [rsp+40H] ; gcrRegs +[r10] IN00ad: 0002EA jmp SHORT G_M38507_IG34 ;; bbWeight=1 PerfScore 3.00 G_M38507_IG33: ; func=00, offs=0002ECH, size=0017H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref ; gcrRegs -[r10] IN00ae: 0002EC mov rdx, 0xD1FFAB1E IN00af: 0002F6 call CORINFO_HELP_RUNTIMEHANDLE_CLASS ; gcr arg pop 0 IN00b0: 0002FB mov r11, rax IN00b1: 0002FE mov r10, gword ptr [rsp+40H] ; gcrRegs +[r10] ;; bbWeight=1 PerfScore 2.50 G_M38507_IG34: ; func=00, offs=000303H, size=0010H, gcVars=00000000000000000000000100000080 {V08 V66}, gcrefRegs=0000D4E0 {rbp rsi rdi r10 r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref, isz Reporting this as generic context: referenced ; GC ptr vars -{V17} IN00b2: 000303 mov rcx, r12 ; gcrRegs +[rcx] IN00b3: 000306 mov rdx, r10 ; gcrRegs +[rdx] IN00b4: 000309 mov r8, rdi ; gcrRegs +[r8] IN00b5: 00030C call qword ptr [r11] ; gcrRegs -[rcx rdx r8 r10] ; gcr arg pop 0 IN00b6: 00030F test eax, eax IN00b7: 000311 je SHORT G_M38507_IG37 ;; bbWeight=2 PerfScore 10.00 G_M38507_IG35: ; func=00, offs=000313H, size=001BH, gcVars=00000000000000000000000000000080 {V66}, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, gcvars, byref, isz Reporting this as generic context: referenced ; gcrRegs -[r12 r14-r15] ; GC ptr vars -{V08} IN00b8: 000313 cmp bl, 1 IN00b9: 000316 jne SHORT G_M38507_IG36 IN00ba: 000318 mov r15, bword ptr [rsp+28H] ; byrRegs +[r15] IN00bb: 00031D lea rcx, bword ptr [r15+8] ; byrRegs +[rcx] IN00bc: 000321 mov rdx, rbp ; gcrRegs +[rdx] Reporting this as generic context: referenced ; GC ptr vars -{V66} IN00bd: 000324 call CORINFO_HELP_CHECKED_ASSIGN_REF ; gcrRegs -[rdx rbp rdi] ; byrRegs -[rcx r15] IN00be: 000329 jmp G_M38507_IG45 ;; bbWeight=0.50 PerfScore 3.00 G_M38507_IG36: ; func=00, offs=00032EH, size=000EH, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref ; gcrRegs +[rdi] IN00bf: 00032E cmp bl, 2 IN00c0: 000331 je G_M38507_IG51 IN00c1: 000337 jmp G_M38507_IG28 ;; bbWeight=0.50 PerfScore 1.63 G_M38507_IG37: ; func=00, offs=00033CH, size=0036H, gcVars=00000000000000000000000100000080 {V08 V66}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref ; gcrRegs +[rbp r12 r14-r15] ; GC ptr vars +{V07 V08 V66} IN00c2: 00033C mov r8, bword ptr [rsp+28H] ; byrRegs +[r8] IN00c3: 000341 mov r8d, dword ptr [r8+20] ; byrRegs -[r8] IN00c4: 000345 mov ecx, r8d IN00c5: 000348 mov r8d, dword ptr [rsp+8CH] IN00c6: 000350 inc r8d IN00c7: 000353 mov dword ptr [rsp+8CH], r8d IN00c8: 00035B cmp dword ptr [rsp+5CH], r8d IN00c9: 000360 jb G_M38507_IG54 IN00ca: 000366 mov dword ptr [rsp+88H], ecx IN00cb: 00036D jmp G_M38507_IG30 ;; bbWeight=4 PerfScore 42.00 G_M38507_IG38: ; func=00, offs=000372H, size=0048H, gcVars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref, isz Reporting this as generic context: referenced ; GC ptr vars -{V07 V66} IN00cc: 000372 cmp dword ptr [rsi+64], 0 IN00cd: 000376 jle SHORT G_M38507_IG40 IN00ce: 000378 mov ecx, dword ptr [rsi+60] IN00cf: 00037B mov ebx, ecx IN00d0: 00037D cmp ecx, dword ptr [rsp+5CH] IN00d1: 000381 jae G_M38507_IG55 IN00d2: 000387 movsxd rcx, ecx IN00d3: 00038A lea rcx, [rcx+2*rcx] IN00d4: 00038E mov ecx, dword ptr [r15+8*rcx+36] IN00d5: 000393 neg ecx IN00d6: 000395 add ecx, -3 IN00d7: 000398 cmp ecx, -1 IN00d8: 00039B setge cl IN00d9: 00039E movzx rcx, cl IN00da: 0003A1 mov rdx, r14 ; gcrRegs +[rdx] IN00db: 0003A4 test ecx, ecx IN00dc: 0003A6 jne SHORT G_M38507_IG39 IN00dd: 0003A8 mov rcx, 0xD1FFAB1E IN00de: 0003B2 mov rcx, gword ptr [rcx] ; gcrRegs +[rcx] IN00df: 0003B5 call System.Diagnostics.Debug:Fail(System.String,System.String) ; gcrRegs -[rcx rdx r14] ; gcr arg pop 0 ;; bbWeight=0.50 PerfScore 8.38 G_M38507_IG39: ; func=00, offs=0003BAH, size=0029H, gcrefRegs=000090E0 {rbp rsi rdi r12 r15}, byrefRegs=00000000 {}, byref IN00e0: 0003BA mov ecx, dword ptr [rsi+60] IN00e1: 0003BD cmp ecx, dword ptr [rsp+5CH] IN00e2: 0003C1 jae G_M38507_IG55 IN00e3: 0003C7 movsxd r9, ecx IN00e4: 0003CA lea rcx, [r9+2*r9] IN00e5: 0003CE mov ecx, dword ptr [r15+8*rcx+36] IN00e6: 0003D3 neg ecx IN00e7: 0003D5 add ecx, -3 IN00e8: 0003D8 mov dword ptr [rsi+60], ecx IN00e9: 0003DB dec dword ptr [rsi+64] IN00ea: 0003DE jmp G_M38507_IG44 ;; bbWeight=0.50 PerfScore 7.63 G_M38507_IG40: ; func=00, offs=0003E3H, size=005AH, gcrefRegs=000050E0 {rbp rsi rdi r12 r14}, byrefRegs=00000000 {}, byref, isz ; gcrRegs -[r15] +[r14] IN00eb: 0003E3 mov ecx, dword ptr [rsi+56] IN00ec: 0003E6 mov ebx, ecx IN00ed: 0003E8 cmp dword ptr [rsp+5CH], ebx IN00ee: 0003EC jne G_M38507_IG43 Reporting this as generic context: referenced ; GC ptr vars -{V08} IN00ef: 0003F2 call System.Collections.HashHelpers:ExpandPrime(int):int ; gcr arg pop 0 IN00f0: 0003F7 mov edx, eax IN00f1: 0003F9 mov rcx, rsi ; gcrRegs +[rcx] IN00f2: 0003FC xor r8d, r8d IN00f3: 0003FF call System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize(int,bool):this ; gcrRegs -[rcx] ; gcr arg pop 0 IN00f4: 000404 mov r15, gword ptr [rsi+8] ; gcrRegs +[r15] IN00f5: 000408 mov eax, dword ptr [r15+8] IN00f6: 00040C mov dword ptr [rsp+60H], eax IN00f7: 000410 mov r8d, eax IN00f8: 000413 mov r9, qword ptr [rsi+48] IN00f9: 000417 mov qword ptr [rsp+68H], r9 IN00fa: 00041C mov dword ptr [rsp+70H], r8d IN00fb: 000421 cmp r8d, 0xD1FFAB1E IN00fc: 000428 setbe cl IN00fd: 00042B movzx rcx, cl IN00fe: 00042E mov rdx, r14 ; gcrRegs +[rdx] IN00ff: 000431 test ecx, ecx IN0100: 000433 jne SHORT G_M38507_IG41 IN0101: 000435 mov rcx, rdx ; gcrRegs +[rcx] IN0102: 000438 call System.Diagnostics.Debug:Fail(System.String,System.String) ; gcrRegs -[rcx rdx] ; gcr arg pop 0 ;; bbWeight=0.50 PerfScore 10.25 G_M38507_IG41: ; func=00, offs=00043DH, size=0048H, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref, isz IN0103: 00043D mov edx, r13d IN0104: 000440 imul rdx, qword ptr [rsp+68H] IN0105: 000446 shr rdx, 32 IN0106: 00044A inc rdx IN0107: 00044D mov r8d, dword ptr [rsp+70H] IN0108: 000452 mov ecx, r8d IN0109: 000455 imul rdx, rcx IN010a: 000459 shr rdx, 32 IN010b: 00045D mov r9d, edx IN010c: 000460 mov eax, r13d IN010d: 000463 xor edx, edx IN010e: 000465 div edx:eax, r8d IN010f: 000468 mov dword ptr [rsp+64H], r9d IN0110: 00046D cmp edx, r9d IN0111: 000470 sete cl IN0112: 000473 movzx rcx, cl IN0113: 000476 mov rdx, r14 ; gcrRegs +[rdx] IN0114: 000479 test ecx, ecx IN0115: 00047B jne SHORT G_M38507_IG42 IN0116: 00047D mov rcx, rdx ; gcrRegs +[rcx] IN0117: 000480 call System.Diagnostics.Debug:Fail(System.String,System.String) ; gcrRegs -[rcx rdx r14] ; gcr arg pop 0 ;; bbWeight=0.50 PerfScore 19.88 G_M38507_IG42: ; func=00, offs=000485H, size=0020H, gcrefRegs=000090E0 {rbp rsi rdi r12 r15}, byrefRegs=00000000 {}, byref IN0118: 000485 mov r9d, dword ptr [rsp+64H] IN0119: 00048A cmp r9d, dword ptr [rsp+60H] IN011a: 00048F jae G_M38507_IG55 IN011b: 000495 movsxd rdx, r9d IN011c: 000498 lea rax, bword ptr [r15+4*rdx+16] ; byrRegs +[rax] IN011d: 00049D mov r14, rax ; byrRegs +[r14] IN011e: 0004A0 mov bword ptr [rsp+50H], r14 ; GC ptr vars +{V08} ;; bbWeight=0.50 PerfScore 2.75 G_M38507_IG43: ; func=00, offs=0004A5H, size=000AH, gcVars=00000000000000000000000100000000 {V08}, gcrefRegs=000010E0 {rbp rsi rdi r12}, byrefRegs=00000000 {}, gcvars, byref ; gcrRegs -[r15] ; byrRegs -[rax r14] IN011f: 0004A5 lea edx, [rbx+1] IN0120: 0004A8 mov dword ptr [rsi+56], edx IN0121: 0004AB mov r15, gword ptr [rsi+16] ; gcrRegs +[r15] ;; bbWeight=0.50 PerfScore 1.75 G_M38507_IG44: ; func=00, offs=0004AFH, size=007EH, gcrefRegs=000090E0 {rbp rsi rdi r12 r15}, byrefRegs=00000000 {}, byref, isz IN0122: 0004AF cmp ebx, dword ptr [r15+8] IN0123: 0004B3 jae G_M38507_IG55 IN0124: 0004B9 movsxd rdx, ebx IN0125: 0004BC lea rdx, [rdx+2*rdx] IN0126: 0004C0 lea r14, bword ptr [r15+8*rdx+16] ; byrRegs +[r14] IN0127: 0004C5 mov dword ptr [r14+16], r13d IN0128: 0004C9 mov rax, bword ptr [rsp+50H] ; byrRegs +[rax] IN0129: 0004CE mov edx, dword ptr [rax] IN012a: 0004D0 dec edx IN012b: 0004D2 mov dword ptr [r14+20], edx IN012c: 0004D6 mov rcx, r14 ; byrRegs +[rcx] IN012d: 0004D9 mov rdx, rdi ; gcrRegs +[rdx] IN012e: 0004DC call CORINFO_HELP_CHECKED_ASSIGN_REF ; gcrRegs -[rdx rdi] ; byrRegs -[rax rcx] IN012f: 0004E1 lea rcx, bword ptr [r14+8] ; byrRegs +[rcx] IN0130: 0004E5 mov rdx, rbp ; gcrRegs +[rdx] IN0131: 0004E8 call CORINFO_HELP_CHECKED_ASSIGN_REF ; gcrRegs -[rdx rbp] ; byrRegs -[rcx r14] IN0132: 0004ED inc ebx IN0133: 0004EF mov r14, bword ptr [rsp+50H] ; byrRegs +[r14] IN0134: 0004F4 mov dword ptr [r14], ebx IN0135: 0004F7 inc dword ptr [rsi+68] IN0136: 0004FA cmp dword ptr [rsp+8CH], 100 IN0137: 000502 jbe SHORT G_M38507_IG45 IN0138: 000504 mov rdx, r12 ; gcrRegs +[rdx] IN0139: 000507 mov rcx, 0xD1FFAB1E Reporting this as generic context: referenced ; GC ptr vars -{V08} IN013a: 000511 call CORINFO_HELP_ISINSTANCEOFCLASS ; gcrRegs -[rdx r12] +[rax] ; byrRegs -[r14] ; gcr arg pop 0 IN013b: 000516 test rax, rax IN013c: 000519 je SHORT G_M38507_IG45 IN013d: 00051B mov edx, dword ptr [r15+8] IN013e: 00051F mov rcx, rsi ; gcrRegs +[rcx] IN013f: 000522 mov r8d, 1 IN0140: 000528 call System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize(int,bool):this ; gcrRegs -[rax rcx r15] ; gcr arg pop 0 ;; bbWeight=0.50 PerfScore 14.38 G_M38507_IG45: ; func=00, offs=00052DH, size=0005H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref IN0141: 00052D mov eax, 1 ;; bbWeight=0.50 PerfScore 0.13 G_M38507_IG46: ; func=00, offs=000532H, size=0014H, epilog, nogc, extend IN017f: 000532 add rsp, 152 IN0180: 000539 pop rbx IN0181: 00053A pop rbp IN0182: 00053B pop rsi IN0183: 00053C pop rdi IN0184: 00053D pop r12 IN0185: 00053F pop r13 IN0186: 000541 pop r14 IN0187: 000543 pop r15 IN0188: 000545 ret ;; bbWeight=0.50 PerfScore 2.63 G_M38507_IG47: ; func=00, offs=000546H, size=000BH, gcVars=00000000000000000000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, gcvars, byref IN0142: 000546 mov ecx, 4 IN0143: 00054B call System.ThrowHelper:ThrowArgumentNullException(int) ; gcr arg pop 0 IN0144: 000550 int3 ;; bbWeight=0 PerfScore 0.00 G_M38507_IG48: ; func=00, offs=000551H, size=001EH, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref, isz ; gcrRegs +[rdi] IN0145: 000551 mov rcx, qword ptr [rsi] IN0146: 000554 mov rdx, qword ptr [rcx+56] IN0147: 000558 mov rdx, qword ptr [rdx] IN0148: 00055B cmp qword ptr [rdx+56], 0 IN0149: 000560 je SHORT G_M38507_IG49 IN014a: 000562 mov rcx, qword ptr [rcx+56] IN014b: 000566 mov rcx, qword ptr [rcx] IN014c: 000569 mov rcx, qword ptr [rcx+56] IN014d: 00056D jmp SHORT G_M38507_IG50 ;; bbWeight=0 PerfScore 0.00 G_M38507_IG49: ; func=00, offs=00056FH, size=0012H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref IN014e: 00056F mov rdx, 0xD1FFAB1E IN014f: 000579 call CORINFO_HELP_RUNTIMEHANDLE_CLASS ; gcr arg pop 0 IN0150: 00057E mov rcx, rax ;; bbWeight=0 PerfScore 0.00 G_M38507_IG50: ; func=00, offs=000581H, size=0009H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref IN0151: 000581 mov rdx, rdi ; gcrRegs +[rdx] IN0152: 000584 call System.ThrowHelper:ThrowAddingDuplicateWithKeyArgumentException(System.__Canon) ; gcrRegs -[rdx rdi] ; gcr arg pop 0 IN0153: 000589 int3 ;; bbWeight=0 PerfScore 0.00 G_M38507_IG51: ; func=00, offs=00058AH, size=001EH, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref, isz ; gcrRegs +[rdi] IN0154: 00058A mov rcx, qword ptr [rsi] IN0155: 00058D mov rdx, qword ptr [rcx+56] IN0156: 000591 mov rdx, qword ptr [rdx] IN0157: 000594 cmp qword ptr [rdx+56], 0 IN0158: 000599 je SHORT G_M38507_IG52 IN0159: 00059B mov rcx, qword ptr [rcx+56] IN015a: 00059F mov rcx, qword ptr [rcx] IN015b: 0005A2 mov rcx, qword ptr [rcx+56] IN015c: 0005A6 jmp SHORT G_M38507_IG53 ;; bbWeight=0 PerfScore 0.00 G_M38507_IG52: ; func=00, offs=0005A8H, size=0012H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref IN015d: 0005A8 mov rdx, 0xD1FFAB1E IN015e: 0005B2 call CORINFO_HELP_RUNTIMEHANDLE_CLASS ; gcr arg pop 0 IN015f: 0005B7 mov rcx, rax ;; bbWeight=0 PerfScore 0.00 G_M38507_IG53: ; func=00, offs=0005BAH, size=0009H, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref IN0160: 0005BA mov rdx, rdi ; gcrRegs +[rdx] IN0161: 0005BD call System.ThrowHelper:ThrowAddingDuplicateWithKeyArgumentException(System.__Canon) ; gcrRegs -[rdx rdi] ; gcr arg pop 0 IN0162: 0005C2 int3 ;; bbWeight=0 PerfScore 0.00 G_M38507_IG54: ; func=00, offs=0005C3H, size=0006H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref IN0163: 0005C3 call System.ThrowHelper:ThrowInvalidOperationException_ConcurrentOperationsNotSupported() ; gcr arg pop 0 IN0164: 0005C8 int3 ;; bbWeight=0 PerfScore 0.00 G_M38507_IG55: ; func=00, offs=0005C9H, size=0006H, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref IN0165: 0005C9 call CORINFO_HELP_RNGCHKFAIL ; gcr arg pop 0 IN0166: 0005CE int3 ;; bbWeight=0 PerfScore 0.00Allocated method code size = 1487 , actual size = 1487, unused size = 0 ; Total bytes of code 1487, prolog size 39, PerfScore 580.70, instruction count 392, allocated bytes for code 1487 (MethodHash=0b956994) for method System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this ; ============================================================ *************** After end code gen, before unwindEmit() G_M38507_IG01: ; func=00, offs=000000H, size=0027H, bbWeight=1 PerfScore 10.25, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG IN0167: 000000 push r15 IN0168: 000002 push r14 IN0169: 000004 push r13 IN016a: 000006 push r12 IN016b: 000008 push rdi IN016c: 000009 push rsi IN016d: 00000A push rbp IN016e: 00000B push rbx IN016f: 00000C sub rsp, 152 IN0170: 000013 mov qword ptr [rsp+90H], rcx IN0171: 00001B mov rsi, rcx IN0172: 00001E mov rdi, rdx IN0173: 000021 mov rbp, r8 IN0174: 000024 mov ebx, r9d G_M38507_IG02: ; offs=000027H, size=0010H, bbWeight=1 PerfScore 4.25, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, byref, isz IN0001: 000027 test rdi, rdi IN0002: 00002A je G_M38507_IG47 IN0003: 000030 cmp gword ptr [rsi+8], 0 IN0004: 000035 jne SHORT G_M38507_IG04 G_M38507_IG03: ; offs=000037H, size=000AH, bbWeight=0.50 PerfScore 0.75, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, byref IN0005: 000037 mov rcx, rsi IN0006: 00003A xor edx, edx IN0007: 00003C call System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Initialize(int):int:this G_M38507_IG04: ; offs=000041H, size=001FH, bbWeight=1 PerfScore 7.00, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, byref, isz IN0008: 000041 cmp gword ptr [rsi+8], 0 IN0009: 000046 setne cl IN000a: 000049 movzx rcx, cl IN000b: 00004C mov rdx, 0xD1FFAB1E IN000c: 000056 mov r14, gword ptr [rdx] IN000d: 000059 mov rdx, r14 IN000e: 00005C test ecx, ecx IN000f: 00005E jne SHORT G_M38507_IG06 G_M38507_IG05: ; offs=000060H, size=0008H, bbWeight=0.50 PerfScore 0.63, gcrefRegs=000040E4 {rdx rbp rsi rdi r14}, byrefRegs=00000000 {}, byref IN0010: 000060 mov rcx, rdx IN0011: 000063 call System.Diagnostics.Debug:Fail(System.String,System.String) G_M38507_IG06: ; offs=000068H, size=0014H, bbWeight=1 PerfScore 5.00, gcrefRegs=000040E0 {rbp rsi rdi r14}, byrefRegs=00000000 {}, byref, isz IN0012: 000068 mov r15, gword ptr [rsi+16] IN0013: 00006C test r15, r15 IN0014: 00006F setne cl IN0015: 000072 movzx rcx, cl IN0016: 000075 mov rdx, r14 IN0017: 000078 test ecx, ecx IN0018: 00007A jne SHORT G_M38507_IG08 G_M38507_IG07: ; offs=00007CH, size=0012H, bbWeight=0.50 PerfScore 1.63, gcrefRegs=0000C0E4 {rdx rbp rsi rdi r14 r15}, byrefRegs=00000000 {}, byref IN0019: 00007C mov rcx, 0xD1FFAB1E IN001a: 000086 mov rcx, gword ptr [rcx] IN001b: 000089 call System.Diagnostics.Debug:Fail(System.String,System.String) G_M38507_IG08: ; offs=00008EH, size=0009H, bbWeight=1 PerfScore 3.25, gcrefRegs=0000C0E0 {rbp rsi rdi r14 r15}, byrefRegs=00000000 {}, byref, isz IN001c: 00008E mov r12, gword ptr [rsi+24] IN001d: 000092 test r12, r12 IN001e: 000095 je SHORT G_M38507_IG13 G_M38507_IG09: ; offs=000097H, size=0013H, bbWeight=0.50 PerfScore 4.63, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref, isz IN001f: 000097 mov rcx, qword ptr [rsi] IN0020: 00009A mov rdx, qword ptr [rcx+56] IN0021: 00009E mov rdx, qword ptr [rdx] IN0022: 0000A1 mov r11, qword ptr [rdx+64] IN0023: 0000A5 test r11, r11 IN0024: 0000A8 je SHORT G_M38507_IG11 G_M38507_IG10: ; offs=0000AAH, size=0002H, bbWeight=0.25 PerfScore 0.50, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref, isz IN0025: 0000AA jmp SHORT G_M38507_IG12 G_M38507_IG11: ; offs=0000ACH, size=0012H, bbWeight=0.25 PerfScore 0.38, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref IN0026: 0000AC mov rdx, 0xD1FFAB1E IN0027: 0000B6 call CORINFO_HELP_RUNTIMEHANDLE_CLASS IN0028: 0000BB mov r11, rax G_M38507_IG12: ; offs=0000BEH, size=000EH, bbWeight=0.50 PerfScore 2.88, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref, isz IN0029: 0000BE mov rcx, r12 IN002a: 0000C1 mov rdx, rdi IN002b: 0000C4 call qword ptr [r11] IN002c: 0000C7 mov r13d, eax IN002d: 0000CA jmp SHORT G_M38507_IG14 G_M38507_IG13: ; offs=0000CCH, size=0010H, bbWeight=0.50 PerfScore 3.75, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref IN002e: 0000CC mov rcx, rdi IN002f: 0000CF mov rax, qword ptr [rdi] IN0030: 0000D2 mov rax, qword ptr [rax+72] IN0031: 0000D6 call qword ptr [rax+24]System.Object:GetHashCode():int:this IN0032: 0000D9 mov r13d, eax G_M38507_IG14: ; offs=0000DCH, size=003BH, bbWeight=1 PerfScore 13.25, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref, isz IN0033: 0000DC xor eax, eax IN0034: 0000DE mov dword ptr [V07 rsp+8CH], eax IN0035: 0000E5 mov r8, gword ptr [rsi+8] IN0036: 0000E9 mov gword ptr [V39 rsp+38H], r8 IN0037: 0000EE mov r9d, dword ptr [r8+8] IN0038: 0000F2 mov r10, qword ptr [rsi+48] IN0039: 0000F6 mov qword ptr [V41 rsp+78H], r10 IN003a: 0000FB mov dword ptr [V40 rsp+84H], r9d IN003b: 000103 cmp r9d, 0xD1FFAB1E IN003c: 00010A setbe cl IN003d: 00010D movzx rcx, cl IN003e: 000110 mov rdx, r14 IN003f: 000113 test ecx, ecx IN0040: 000115 jne SHORT G_M38507_IG16 G_M38507_IG15: ; offs=000117H, size=0008H, bbWeight=0.50 PerfScore 0.63, gcVars=00000000000000000000000000200000 {V39}, gcrefRegs=0000D0E4 {rdx rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref IN0041: 000117 mov rcx, rdx IN0042: 00011A call System.Diagnostics.Debug:Fail(System.String,System.String) G_M38507_IG16: ; offs=00011FH, size=0043H, bbWeight=1 PerfScore 38.50, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref, isz IN0043: 00011F mov edx, r13d IN0044: 000122 imul rdx, qword ptr [V41 rsp+78H] IN0045: 000128 shr rdx, 32 IN0046: 00012C inc rdx IN0047: 00012F mov r9d, dword ptr [V40 rsp+84H] IN0048: 000137 mov ecx, r9d IN0049: 00013A imul rdx, rcx IN004a: 00013E shr rdx, 32 IN004b: 000142 mov r10d, edx IN004c: 000145 mov eax, r13d IN004d: 000148 xor edx, edx IN004e: 00014A div edx:eax, r9d IN004f: 00014D mov dword ptr [V42 rsp+74H], r10d IN0050: 000152 cmp edx, r10d IN0051: 000155 sete cl IN0052: 000158 movzx rcx, cl IN0053: 00015B mov rdx, r14 IN0054: 00015E test ecx, ecx IN0055: 000160 jne SHORT G_M38507_IG18 G_M38507_IG17: ; offs=000162H, size=0008H, bbWeight=0.50 PerfScore 0.63, gcrefRegs=0000D0E4 {rdx rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref IN0056: 000162 mov rcx, rdx IN0057: 000165 call System.Diagnostics.Debug:Fail(System.String,System.String) G_M38507_IG18: ; offs=00016AH, size=0038H, bbWeight=1 PerfScore 11.75, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref IN0058: 00016A mov r10d, dword ptr [V42 rsp+74H] IN0059: 00016F mov r8, gword ptr [V39 rsp+38H] IN005a: 000174 cmp r10d, dword ptr [r8+8] IN005b: 000178 jae G_M38507_IG55 IN005c: 00017E movsxd rcx, r10d IN005d: 000181 lea rax, bword ptr [r8+4*rcx+16] IN005e: 000186 mov bword ptr [V08 rsp+50H], rax IN005f: 00018B mov r8d, dword ptr [rax] IN0060: 00018E dec r8d IN0061: 000191 mov dword ptr [V09 rsp+88H], r8d IN0062: 000199 test r12, r12 IN0063: 00019C jne G_M38507_IG30 G_M38507_IG19: ; offs=0001A2H, size=0013H, bbWeight=0.50 PerfScore 4.63, gcVars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref, isz IN0064: 0001A2 mov rcx, qword ptr [rsi] IN0065: 0001A5 mov rdx, qword ptr [rcx+56] IN0066: 0001A9 mov rdx, qword ptr [rdx] IN0067: 0001AC mov rdx, qword ptr [rdx+32] IN0068: 0001B0 test rdx, rdx IN0069: 0001B3 je SHORT G_M38507_IG21 G_M38507_IG20: ; offs=0001B5H, size=0002H, bbWeight=0.25 PerfScore 0.50, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref, isz IN006a: 0001B5 jmp SHORT G_M38507_IG22 G_M38507_IG21: ; offs=0001B7H, size=0012H, bbWeight=0.25 PerfScore 0.38, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref IN006b: 0001B7 mov rdx, 0xD1FFAB1E IN006c: 0001C1 call CORINFO_HELP_RUNTIMEHANDLE_CLASS IN006d: 0001C6 mov rdx, rax G_M38507_IG22: ; offs=0001C9H, size=0008H, bbWeight=0.50 PerfScore 0.63, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref IN006e: 0001C9 mov rcx, rdx IN006f: 0001CC call System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon]:get_Default():System.Collections.Generic.EqualityComparer`1[__Canon] G_M38507_IG23: ; offs=0001D1H, size=0031H, bbWeight=4 PerfScore 44.00, gcrefRegs=0000D0E1 {rax rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref, isz IN0070: 0001D1 mov r9d, dword ptr [r15+8] IN0071: 0001D5 mov dword ptr [V76 rsp+5CH], r9d IN0072: 0001DA mov r10d, dword ptr [V09 rsp+88H] IN0073: 0001E2 cmp r9d, r10d IN0074: 0001E5 jbe G_M38507_IG38 IN0075: 0001EB movsxd rdx, r10d IN0076: 0001EE lea rdx, [rdx+2*rdx] IN0077: 0001F2 lea r11, bword ptr [r15+8*rdx+16] IN0078: 0001F7 mov bword ptr [V65 rsp+30H], r11 IN0079: 0001FC cmp dword ptr [r11+16], r13d IN007a: 000200 jne SHORT G_M38507_IG25 G_M38507_IG24: ; offs=000202H, size=0024H, bbWeight=2 PerfScore 25.50, gcVars=00000000000000000000000100000040 {V08 V65}, gcrefRegs=0000D0E1 {rax rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref, isz IN007b: 000202 mov rdx, gword ptr [r15+8*rdx+16] IN007c: 000207 mov rcx, rax IN007d: 00020A mov r8, rdi IN007e: 00020D mov gword ptr [V12 rsp+48H], rax IN007f: 000212 mov r10, qword ptr [rax] IN0080: 000215 mov r10, qword ptr [r10+72] IN0081: 000219 call qword ptr [r10+32]System.Collections.Generic.EqualityComparer`1[__Canon][System.__Canon]:Equals(System.__Canon,System.__Canon):bool:this IN0082: 00021D test eax, eax IN0083: 00021F mov rax, gword ptr [V12 rsp+48H] IN0084: 000224 jne SHORT G_M38507_IG26 G_M38507_IG25: ; offs=000226H, size=0037H, bbWeight=4 PerfScore 42.00, gcVars=00000000000000000000000100000040 {V08 V65}, gcrefRegs=0000D0E1 {rax rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref IN0085: 000226 mov r11, bword ptr [V65 rsp+30H] IN0086: 00022B mov r10d, dword ptr [r11+20] IN0087: 00022F mov r8d, r10d IN0088: 000232 mov r11d, dword ptr [V07 rsp+8CH] IN0089: 00023A inc r11d IN008a: 00023D cmp dword ptr [V76 rsp+5CH], r11d IN008b: 000242 jb G_M38507_IG54 IN008c: 000248 mov dword ptr [V07 rsp+8CH], r11d IN008d: 000250 mov dword ptr [V09 rsp+88H], r8d IN008e: 000258 jmp G_M38507_IG23 G_M38507_IG26: ; offs=00025DH, size=001BH, bbWeight=0.50 PerfScore 3.00, gcVars=00000000000000000000000000000040 {V65}, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, gcvars, byref, isz IN008f: 00025D cmp bl, 1 IN0090: 000260 jne SHORT G_M38507_IG27 IN0091: 000262 mov r11, bword ptr [V65 rsp+30H] IN0092: 000267 lea rcx, bword ptr [r11+8] IN0093: 00026B mov rdx, rbp IN0094: 00026E call CORINFO_HELP_CHECKED_ASSIGN_REF IN0095: 000273 jmp G_M38507_IG45 G_M38507_IG27: ; offs=000278H, size=0009H, bbWeight=0.50 PerfScore 0.63, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref IN0096: 000278 cmp bl, 2 IN0097: 00027B je G_M38507_IG48 G_M38507_IG28: ; offs=000281H, size=0002H, bbWeight=0.50 PerfScore 0.13, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref IN0098: 000281 xor eax, eax G_M38507_IG29: ; offs=000283H, size=0014H, bbWeight=0.50 PerfScore 2.63, epilog, nogc, extend IN0175: 000283 add rsp, 152 IN0176: 00028A pop rbx IN0177: 00028B pop rbp IN0178: 00028C pop rsi IN0179: 00028D pop rdi IN017a: 00028E pop r12 IN017b: 000290 pop r13 IN017c: 000292 pop r14 IN017d: 000294 pop r15 IN017e: 000296 ret G_M38507_IG30: ; offs=000297H, size=0031H, bbWeight=4 PerfScore 44.00, gcVars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref, isz IN0099: 000297 mov r9d, dword ptr [r15+8] IN009a: 00029B mov dword ptr [V76 rsp+5CH], r9d IN009b: 0002A0 mov r8d, dword ptr [V09 rsp+88H] IN009c: 0002A8 cmp r9d, r8d IN009d: 0002AB jbe G_M38507_IG38 IN009e: 0002B1 movsxd rcx, r8d IN009f: 0002B4 lea rcx, [rcx+2*rcx] IN00a0: 0002B8 lea r8, bword ptr [r15+8*rcx+16] IN00a1: 0002BD mov bword ptr [V66 rsp+28H], r8 IN00a2: 0002C2 cmp dword ptr [r8+16], r13d IN00a3: 0002C6 jne SHORT G_M38507_IG37 G_M38507_IG31: ; offs=0002C8H, size=001DH, bbWeight=2 PerfScore 24.50, gcVars=00000000000000000000000100000080 {V08 V66}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref, isz IN00a4: 0002C8 mov r10, gword ptr [r15+8*rcx+16] IN00a5: 0002CD mov gword ptr [V17 rsp+40H], r10 IN00a6: 0002D2 mov rcx, qword ptr [rsi] IN00a7: 0002D5 mov rdx, qword ptr [rcx+56] IN00a8: 0002D9 mov rdx, qword ptr [rdx] IN00a9: 0002DC mov r11, qword ptr [rdx+48] IN00aa: 0002E0 test r11, r11 IN00ab: 0002E3 je SHORT G_M38507_IG33 G_M38507_IG32: ; offs=0002E5H, size=0007H, bbWeight=1 PerfScore 3.00, gcVars=00000000000000000000000100008080 {V08 V17 V66}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref, isz IN00ac: 0002E5 mov r10, gword ptr [V17 rsp+40H] IN00ad: 0002EA jmp SHORT G_M38507_IG34 G_M38507_IG33: ; offs=0002ECH, size=0017H, bbWeight=1 PerfScore 2.50, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref IN00ae: 0002EC mov rdx, 0xD1FFAB1E IN00af: 0002F6 call CORINFO_HELP_RUNTIMEHANDLE_CLASS IN00b0: 0002FB mov r11, rax IN00b1: 0002FE mov r10, gword ptr [V17 rsp+40H] G_M38507_IG34: ; offs=000303H, size=0010H, bbWeight=2 PerfScore 10.00, gcVars=00000000000000000000000100000080 {V08 V66}, gcrefRegs=0000D4E0 {rbp rsi rdi r10 r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref, isz IN00b2: 000303 mov rcx, r12 IN00b3: 000306 mov rdx, r10 IN00b4: 000309 mov r8, rdi IN00b5: 00030C call qword ptr [r11] IN00b6: 00030F test eax, eax IN00b7: 000311 je SHORT G_M38507_IG37 G_M38507_IG35: ; offs=000313H, size=001BH, bbWeight=0.50 PerfScore 3.00, gcVars=00000000000000000000000000000080 {V66}, gcrefRegs=000000E0 {rbp rsi rdi}, byrefRegs=00000000 {}, gcvars, byref, isz IN00b8: 000313 cmp bl, 1 IN00b9: 000316 jne SHORT G_M38507_IG36 IN00ba: 000318 mov r15, bword ptr [V66 rsp+28H] IN00bb: 00031D lea rcx, bword ptr [r15+8] IN00bc: 000321 mov rdx, rbp IN00bd: 000324 call CORINFO_HELP_CHECKED_ASSIGN_REF IN00be: 000329 jmp G_M38507_IG45 G_M38507_IG36: ; offs=00032EH, size=000EH, bbWeight=0.50 PerfScore 1.63, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref IN00bf: 00032E cmp bl, 2 IN00c0: 000331 je G_M38507_IG51 IN00c1: 000337 jmp G_M38507_IG28 G_M38507_IG37: ; offs=00033CH, size=0036H, bbWeight=4 PerfScore 42.00, gcVars=00000000000000000000000100000080 {V08 V66}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref IN00c2: 00033C mov r8, bword ptr [V66 rsp+28H] IN00c3: 000341 mov r8d, dword ptr [r8+20] IN00c4: 000345 mov ecx, r8d IN00c5: 000348 mov r8d, dword ptr [V07 rsp+8CH] IN00c6: 000350 inc r8d IN00c7: 000353 mov dword ptr [V07 rsp+8CH], r8d IN00c8: 00035B cmp dword ptr [V76 rsp+5CH], r8d IN00c9: 000360 jb G_M38507_IG54 IN00ca: 000366 mov dword ptr [V09 rsp+88H], ecx IN00cb: 00036D jmp G_M38507_IG30 G_M38507_IG38: ; offs=000372H, size=0048H, bbWeight=0.50 PerfScore 8.38, gcVars=00000000000000000000000100000000 {V08}, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, gcvars, byref, isz IN00cc: 000372 cmp dword ptr [rsi+64], 0 IN00cd: 000376 jle SHORT G_M38507_IG40 IN00ce: 000378 mov ecx, dword ptr [rsi+60] IN00cf: 00037B mov ebx, ecx IN00d0: 00037D cmp ecx, dword ptr [V76 rsp+5CH] IN00d1: 000381 jae G_M38507_IG55 IN00d2: 000387 movsxd rcx, ecx IN00d3: 00038A lea rcx, [rcx+2*rcx] IN00d4: 00038E mov ecx, dword ptr [r15+8*rcx+36] IN00d5: 000393 neg ecx IN00d6: 000395 add ecx, -3 IN00d7: 000398 cmp ecx, -1 IN00d8: 00039B setge cl IN00d9: 00039E movzx rcx, cl IN00da: 0003A1 mov rdx, r14 IN00db: 0003A4 test ecx, ecx IN00dc: 0003A6 jne SHORT G_M38507_IG39 IN00dd: 0003A8 mov rcx, 0xD1FFAB1E IN00de: 0003B2 mov rcx, gword ptr [rcx] IN00df: 0003B5 call System.Diagnostics.Debug:Fail(System.String,System.String) G_M38507_IG39: ; offs=0003BAH, size=0029H, bbWeight=0.50 PerfScore 7.63, gcrefRegs=000090E0 {rbp rsi rdi r12 r15}, byrefRegs=00000000 {}, byref IN00e0: 0003BA mov ecx, dword ptr [rsi+60] IN00e1: 0003BD cmp ecx, dword ptr [V76 rsp+5CH] IN00e2: 0003C1 jae G_M38507_IG55 IN00e3: 0003C7 movsxd r9, ecx IN00e4: 0003CA lea rcx, [r9+2*r9] IN00e5: 0003CE mov ecx, dword ptr [r15+8*rcx+36] IN00e6: 0003D3 neg ecx IN00e7: 0003D5 add ecx, -3 IN00e8: 0003D8 mov dword ptr [rsi+60], ecx IN00e9: 0003DB dec dword ptr [rsi+64] IN00ea: 0003DE jmp G_M38507_IG44 G_M38507_IG40: ; offs=0003E3H, size=005AH, bbWeight=0.50 PerfScore 10.25, gcrefRegs=000050E0 {rbp rsi rdi r12 r14}, byrefRegs=00000000 {}, byref, isz IN00eb: 0003E3 mov ecx, dword ptr [rsi+56] IN00ec: 0003E6 mov ebx, ecx IN00ed: 0003E8 cmp dword ptr [V76 rsp+5CH], ebx IN00ee: 0003EC jne G_M38507_IG43 IN00ef: 0003F2 call System.Collections.HashHelpers:ExpandPrime(int):int IN00f0: 0003F7 mov edx, eax IN00f1: 0003F9 mov rcx, rsi IN00f2: 0003FC xor r8d, r8d IN00f3: 0003FF call System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize(int,bool):this IN00f4: 000404 mov r15, gword ptr [rsi+8] IN00f5: 000408 mov eax, dword ptr [r15+8] IN00f6: 00040C mov dword ptr [V72 rsp+60H], eax IN00f7: 000410 mov r8d, eax IN00f8: 000413 mov r9, qword ptr [rsi+48] IN00f9: 000417 mov qword ptr [V54 rsp+68H], r9 IN00fa: 00041C mov dword ptr [V53 rsp+70H], r8d IN00fb: 000421 cmp r8d, 0xD1FFAB1E IN00fc: 000428 setbe cl IN00fd: 00042B movzx rcx, cl IN00fe: 00042E mov rdx, r14 IN00ff: 000431 test ecx, ecx IN0100: 000433 jne SHORT G_M38507_IG41 IN0101: 000435 mov rcx, rdx IN0102: 000438 call System.Diagnostics.Debug:Fail(System.String,System.String) G_M38507_IG41: ; offs=00043DH, size=0048H, bbWeight=0.50 PerfScore 19.88, gcrefRegs=0000D0E0 {rbp rsi rdi r12 r14 r15}, byrefRegs=00000000 {}, byref, isz IN0103: 00043D mov edx, r13d IN0104: 000440 imul rdx, qword ptr [V54 rsp+68H] IN0105: 000446 shr rdx, 32 IN0106: 00044A inc rdx IN0107: 00044D mov r8d, dword ptr [V53 rsp+70H] IN0108: 000452 mov ecx, r8d IN0109: 000455 imul rdx, rcx IN010a: 000459 shr rdx, 32 IN010b: 00045D mov r9d, edx IN010c: 000460 mov eax, r13d IN010d: 000463 xor edx, edx IN010e: 000465 div edx:eax, r8d IN010f: 000468 mov dword ptr [V55 rsp+64H], r9d IN0110: 00046D cmp edx, r9d IN0111: 000470 sete cl IN0112: 000473 movzx rcx, cl IN0113: 000476 mov rdx, r14 IN0114: 000479 test ecx, ecx IN0115: 00047B jne SHORT G_M38507_IG42 IN0116: 00047D mov rcx, rdx IN0117: 000480 call System.Diagnostics.Debug:Fail(System.String,System.String) G_M38507_IG42: ; offs=000485H, size=0020H, bbWeight=0.50 PerfScore 2.75, gcrefRegs=000090E0 {rbp rsi rdi r12 r15}, byrefRegs=00000000 {}, byref IN0118: 000485 mov r9d, dword ptr [V55 rsp+64H] IN0119: 00048A cmp r9d, dword ptr [V72 rsp+60H] IN011a: 00048F jae G_M38507_IG55 IN011b: 000495 movsxd rdx, r9d IN011c: 000498 lea rax, bword ptr [r15+4*rdx+16] IN011d: 00049D mov r14, rax IN011e: 0004A0 mov bword ptr [V08 rsp+50H], r14 G_M38507_IG43: ; offs=0004A5H, size=000AH, bbWeight=0.50 PerfScore 1.75, gcVars=00000000000000000000000100000000 {V08}, gcrefRegs=000010E0 {rbp rsi rdi r12}, byrefRegs=00000000 {}, gcvars, byref IN011f: 0004A5 lea edx, [rbx+1] IN0120: 0004A8 mov dword ptr [rsi+56], edx IN0121: 0004AB mov r15, gword ptr [rsi+16] G_M38507_IG44: ; offs=0004AFH, size=007EH, bbWeight=0.50 PerfScore 14.38, gcrefRegs=000090E0 {rbp rsi rdi r12 r15}, byrefRegs=00000000 {}, byref, isz IN0122: 0004AF cmp ebx, dword ptr [r15+8] IN0123: 0004B3 jae G_M38507_IG55 IN0124: 0004B9 movsxd rdx, ebx IN0125: 0004BC lea rdx, [rdx+2*rdx] IN0126: 0004C0 lea r14, bword ptr [r15+8*rdx+16] IN0127: 0004C5 mov dword ptr [r14+16], r13d IN0128: 0004C9 mov rax, bword ptr [V08 rsp+50H] IN0129: 0004CE mov edx, dword ptr [rax] IN012a: 0004D0 dec edx IN012b: 0004D2 mov dword ptr [r14+20], edx IN012c: 0004D6 mov rcx, r14 IN012d: 0004D9 mov rdx, rdi IN012e: 0004DC call CORINFO_HELP_CHECKED_ASSIGN_REF IN012f: 0004E1 lea rcx, bword ptr [r14+8] IN0130: 0004E5 mov rdx, rbp IN0131: 0004E8 call CORINFO_HELP_CHECKED_ASSIGN_REF IN0132: 0004ED inc ebx IN0133: 0004EF mov r14, bword ptr [V08 rsp+50H] IN0134: 0004F4 mov dword ptr [r14], ebx IN0135: 0004F7 inc dword ptr [rsi+68] IN0136: 0004FA cmp dword ptr [V07 rsp+8CH], 100 IN0137: 000502 jbe SHORT G_M38507_IG45 IN0138: 000504 mov rdx, r12 IN0139: 000507 mov rcx, 0xD1FFAB1E IN013a: 000511 call CORINFO_HELP_ISINSTANCEOFCLASS IN013b: 000516 test rax, rax IN013c: 000519 je SHORT G_M38507_IG45 IN013d: 00051B mov edx, dword ptr [r15+8] IN013e: 00051F mov rcx, rsi IN013f: 000522 mov r8d, 1 IN0140: 000528 call System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:Resize(int,bool):this G_M38507_IG45: ; offs=00052DH, size=0005H, bbWeight=0.50 PerfScore 0.13, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref IN0141: 00052D mov eax, 1 G_M38507_IG46: ; offs=000532H, size=0014H, bbWeight=0.50 PerfScore 2.63, epilog, nogc, extend IN017f: 000532 add rsp, 152 IN0180: 000539 pop rbx IN0181: 00053A pop rbp IN0182: 00053B pop rsi IN0183: 00053C pop rdi IN0184: 00053D pop r12 IN0185: 00053F pop r13 IN0186: 000541 pop r14 IN0187: 000543 pop r15 IN0188: 000545 ret G_M38507_IG47: ; offs=000546H, size=000BH, bbWeight=0 PerfScore 0.00, gcVars=00000000000000000000000000000000 {}, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, gcvars, byref IN0142: 000546 mov ecx, 4 IN0143: 00054B call System.ThrowHelper:ThrowArgumentNullException(int) IN0144: 000550 int3 G_M38507_IG48: ; offs=000551H, size=001EH, bbWeight=0 PerfScore 0.00, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref, isz IN0145: 000551 mov rcx, qword ptr [rsi] IN0146: 000554 mov rdx, qword ptr [rcx+56] IN0147: 000558 mov rdx, qword ptr [rdx] IN0148: 00055B cmp qword ptr [rdx+56], 0 IN0149: 000560 je SHORT G_M38507_IG49 IN014a: 000562 mov rcx, qword ptr [rcx+56] IN014b: 000566 mov rcx, qword ptr [rcx] IN014c: 000569 mov rcx, qword ptr [rcx+56] IN014d: 00056D jmp SHORT G_M38507_IG50 G_M38507_IG49: ; offs=00056FH, size=0012H, bbWeight=0 PerfScore 0.00, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref IN014e: 00056F mov rdx, 0xD1FFAB1E IN014f: 000579 call CORINFO_HELP_RUNTIMEHANDLE_CLASS IN0150: 00057E mov rcx, rax G_M38507_IG50: ; offs=000581H, size=0009H, bbWeight=0 PerfScore 0.00, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref IN0151: 000581 mov rdx, rdi IN0152: 000584 call System.ThrowHelper:ThrowAddingDuplicateWithKeyArgumentException(System.__Canon) IN0153: 000589 int3 G_M38507_IG51: ; offs=00058AH, size=001EH, bbWeight=0 PerfScore 0.00, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref, isz IN0154: 00058A mov rcx, qword ptr [rsi] IN0155: 00058D mov rdx, qword ptr [rcx+56] IN0156: 000591 mov rdx, qword ptr [rdx] IN0157: 000594 cmp qword ptr [rdx+56], 0 IN0158: 000599 je SHORT G_M38507_IG52 IN0159: 00059B mov rcx, qword ptr [rcx+56] IN015a: 00059F mov rcx, qword ptr [rcx] IN015b: 0005A2 mov rcx, qword ptr [rcx+56] IN015c: 0005A6 jmp SHORT G_M38507_IG53 G_M38507_IG52: ; offs=0005A8H, size=0012H, bbWeight=0 PerfScore 0.00, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref IN015d: 0005A8 mov rdx, 0xD1FFAB1E IN015e: 0005B2 call CORINFO_HELP_RUNTIMEHANDLE_CLASS IN015f: 0005B7 mov rcx, rax G_M38507_IG53: ; offs=0005BAH, size=0009H, bbWeight=0 PerfScore 0.00, gcrefRegs=000000C0 {rsi rdi}, byrefRegs=00000000 {}, byref IN0160: 0005BA mov rdx, rdi IN0161: 0005BD call System.ThrowHelper:ThrowAddingDuplicateWithKeyArgumentException(System.__Canon) IN0162: 0005C2 int3 G_M38507_IG54: ; offs=0005C3H, size=0006H, bbWeight=0 PerfScore 0.00, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref IN0163: 0005C3 call System.ThrowHelper:ThrowInvalidOperationException_ConcurrentOperationsNotSupported() IN0164: 0005C8 int3 G_M38507_IG55: ; offs=0005C9H, size=0006H, bbWeight=0 PerfScore 0.00, gcrefRegs=00000040 {rsi}, byrefRegs=00000000 {}, byref IN0165: 0005C9 call CORINFO_HELP_RNGCHKFAIL IN0166: 0005CE int3 *************** Finishing PHASE Emit code *************** Starting PHASE Emit GC+EH tables Unwind Info: >> Start offset : 0x000000 (not in unwind data) >> End offset : 0xd1ffab1e (not in unwind data) Version : 1 Flags : 0x00 SizeOfProlog : 0x13 CountOfUnwindCodes: 10 FrameRegister : none (0) FrameOffset : N/A (no FrameRegister) (Value=0) UnwindCodes : CodeOffset: 0x13 UnwindOp: UWOP_ALLOC_LARGE (1) OpInfo: 0 - Scaled small Size: 19 * 8 = 152 = 0x00098 CodeOffset: 0x0C UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbx (3) CodeOffset: 0x0B UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5) CodeOffset: 0x0A UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rsi (6) CodeOffset: 0x09 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rdi (7) CodeOffset: 0x08 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r12 (12) CodeOffset: 0x06 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r13 (13) CodeOffset: 0x04 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r14 (14) CodeOffset: 0x02 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r15 (15) allocUnwindInfo(pHotCode=0x00000000D1FFAB1E, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x5cf, unwindSize=0x18, pUnwindBlock=0x00000000D1FFAB1E, funKind=0 (main function)) *************** In genIPmappingGen() IP mapping count : 66 IL offs PROLOG : 0x00000000 ( STACK_EMPTY ) IL offs 0x0000 : 0x00000027 ( STACK_EMPTY ) IL offs 0x000E : 0x00000030 ( STACK_EMPTY ) IL offs 0x001E : 0x00000041 ( STACK_EMPTY ) IL offs 0x002C : 0x00000068 ( STACK_EMPTY ) IL offs 0x0033 : 0x0000006C ( STACK_EMPTY ) IL offs 0x0041 : 0x0000008E ( STACK_EMPTY ) IL offs 0x0048 : 0x00000092 ( STACK_EMPTY ) IL offs 0x004B : 0x00000097 ( STACK_EMPTY ) IL offs 0x0054 : 0x000000CC ( STACK_EMPTY ) IL offs 0x0062 : 0x000000DC ( STACK_EMPTY ) IL offs 0x0064 : 0x000000E5 ( STACK_EMPTY ) IL offs 0x006D : 0x00000186 ( STACK_EMPTY ) IL offs 0x0074 : 0x00000199 ( STACK_EMPTY ) IL offs 0x00FF : 0x000001A2 ( STACK_EMPTY ) IL offs 0x0106 : 0x000001D1 ( STACK_EMPTY ) IL offs 0x0110 : 0x000001EB ( STACK_EMPTY ) IL offs 0x0120 : 0x00000202 ( STACK_EMPTY ) IL offs 0x0157 : 0x00000226 ( STACK_EMPTY ) IL offs 0x0166 : 0x00000232 ( STACK_EMPTY ) IL offs 0x016A : 0x0000023D ( STACK_EMPTY ) IL offs NO_MAP : 0x00000248 ( STACK_EMPTY ) IL offs 0x0137 : 0x0000025D ( STACK_EMPTY ) IL offs 0x013B : 0x00000262 ( STACK_EMPTY ) IL offs 0x014B : 0x00000278 ( STACK_EMPTY ) IL offs NO_MAP : 0x00000281 ( STACK_EMPTY ) IL offs EPILOG : 0x00000283 ( STACK_EMPTY ) IL offs 0x0177 : 0x00000297 ( STACK_EMPTY ) IL offs 0x017E : 0x000002B1 ( STACK_EMPTY ) IL offs 0x018E : 0x000002C8 ( STACK_EMPTY ) IL offs 0x01A4 : 0x00000313 ( STACK_EMPTY ) IL offs 0x01A8 : 0x00000318 ( STACK_EMPTY ) IL offs 0x01B8 : 0x0000032E ( STACK_EMPTY ) IL offs NO_MAP : 0x00000337 ( STACK_EMPTY ) IL offs 0x01C4 : 0x0000033C ( STACK_EMPTY ) IL offs 0x01D3 : 0x00000348 ( STACK_EMPTY ) IL offs 0x01D7 : 0x00000353 ( STACK_EMPTY ) IL offs NO_MAP : 0x00000366 ( STACK_EMPTY ) IL offs 0x01E4 : 0x00000372 ( STACK_EMPTY ) IL offs 0x01ED : 0x00000378 ( STACK_EMPTY ) IL offs 0x01F5 : 0x0000037D ( STACK_EMPTY ) IL offs 0x0219 : 0x000003BA ( STACK_EMPTY ) IL offs 0x0233 : 0x000003DB ( STACK_EMPTY ) IL offs 0x0243 : 0x000003E3 ( STACK_EMPTY ) IL offs 0x024B : 0x000003E8 ( STACK_EMPTY ) IL offs 0x0252 : 0x000003F2 ( STACK_EMPTY ) IL offs 0x0258 : 0x00000404 ( STACK_EMPTY ) IL offs 0x0261 : 0x000004A5 ( STACK_EMPTY ) IL offs 0x026F : 0x000004AB ( STACK_EMPTY ) IL offs 0x0276 : 0x000004AF ( STACK_EMPTY ) IL offs 0x0280 : 0x000004C5 ( STACK_EMPTY ) IL offs 0x0288 : 0x000004C9 ( STACK_EMPTY ) IL offs 0x0294 : 0x000004D6 ( STACK_EMPTY ) IL offs 0x029C : 0x000004E1 ( STACK_EMPTY ) IL offs 0x02A4 : 0x000004ED ( STACK_EMPTY ) IL offs 0x02AB : 0x000004F7 ( STACK_EMPTY ) IL offs 0x02CA : 0x000004FA ( STACK_EMPTY ) IL offs 0x02CF : 0x00000504 ( STACK_EMPTY ) IL offs 0x02D7 : 0x0000051B ( STACK_EMPTY ) IL offs NO_MAP : 0x0000052D ( STACK_EMPTY ) IL offs EPILOG : 0x00000532 ( STACK_EMPTY ) IL offs 0x0008 : 0x00000546 ( STACK_EMPTY ) IL offs 0x014F : 0x00000551 ( STACK_EMPTY ) IL offs 0x01BC : 0x0000058A ( STACK_EMPTY ) IL offs 0x01DD : 0x000005C3 ( STACK_EMPTY ) IL offs NO_MAP : 0x000005C9 ( STACK_EMPTY ) *************** In genSetScopeInfo() VarLocInfo count is 57 ; Variable debug info: 57 live ranges, 14 vars for method System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this 0( UNKNOWN) : From 00000000h to 00000027h, in rcx 0( UNKNOWN) : From 00000027h to 000005CEh, in rsi 1( UNKNOWN) : From 00000000h to 00000027h, in rdx 1( UNKNOWN) : From 00000027h to 00000262h, in rdi 1( UNKNOWN) : From 00000278h to 00000281h, in rdi 1( UNKNOWN) : From 00000297h to 00000318h, in rdi 1( UNKNOWN) : From 0000032Eh to 000004D6h, in rdi 1( UNKNOWN) : From 00000551h to 00000581h, in rdi 1( UNKNOWN) : From 0000058Ah to 000005BAh, in rdi 2( UNKNOWN) : From 00000000h to 00000027h, in r8 2( UNKNOWN) : From 00000027h to 0000026Bh, in rbp 2( UNKNOWN) : From 00000297h to 00000321h, in rbp 2( UNKNOWN) : From 0000033Ch to 000004E5h, in rbp 3( UNKNOWN) : From 00000000h to 00000027h, in r9 3( UNKNOWN) : From 00000027h to 00000262h, in rbx 3( UNKNOWN) : From 00000278h to 00000279h, in rbx 3( UNKNOWN) : From 00000297h to 00000318h, in rbx 3( UNKNOWN) : From 0000032Eh to 0000032Fh, in rbx 3( UNKNOWN) : From 0000033Ch to 00000372h, in rbx 4( UNKNOWN) : From 0000006Ch to 0000025Dh, in r15 4( UNKNOWN) : From 00000297h to 00000313h, in r15 4( UNKNOWN) : From 0000033Ch to 000003E3h, in r15 4( UNKNOWN) : From 000004AFh to 0000051Bh, in r15 5( UNKNOWN) : From 00000092h to 0000025Dh, in r12 5( UNKNOWN) : From 00000297h to 00000313h, in r12 5( UNKNOWN) : From 0000033Ch to 00000504h, in r12 6( UNKNOWN) : From 000000DCh to 0000025Dh, in r13 6( UNKNOWN) : From 00000297h to 00000313h, in r13 6( UNKNOWN) : From 0000033Ch to 000004C5h, in r13 7( UNKNOWN) : From 000000E5h to 0000023Ah, in rsp'[140] (1 slot) 7( UNKNOWN) : From 0000023Dh to 00000250h, in r11 7( UNKNOWN) : From 00000250h to 0000025Dh, in rsp'[140] (1 slot) 7( UNKNOWN) : From 00000297h to 00000313h, in rsp'[140] (1 slot) 7( UNKNOWN) : From 0000033Ch to 00000350h, in rsp'[140] (1 slot) 7( UNKNOWN) : From 00000353h to 0000035Bh, in r8 7( UNKNOWN) : From 0000035Bh to 000004FAh, in rsp'[140] (1 slot) 8( UNKNOWN) : From 00000186h to 0000018Bh, in rax 8( UNKNOWN) : From 0000018Bh to 0000025Dh, in rsp'[80] (1 slot) 8( UNKNOWN) : From 00000297h to 00000313h, in rsp'[80] (1 slot) 8( UNKNOWN) : From 0000033Ch to 000003F2h, in rsp'[80] (1 slot) 8( UNKNOWN) : From 000004A0h to 000004A5h, in r14 8( UNKNOWN) : From 000004A5h to 000004F4h, in rsp'[80] (1 slot) 9( UNKNOWN) : From 00000199h to 000001E2h, in rsp'[136] (1 slot) 9( UNKNOWN) : From 000001E2h to 000001EBh, in r10 9( UNKNOWN) : From 00000232h to 00000258h, in r8 9( UNKNOWN) : From 00000258h to 0000025Dh, in rsp'[136] (1 slot) 9( UNKNOWN) : From 00000297h to 000002A8h, in rsp'[136] (1 slot) 9( UNKNOWN) : From 000002A8h to 000002B1h, in r8 9( UNKNOWN) : From 00000348h to 0000036Dh, in rcx 9( UNKNOWN) : From 0000036Dh to 00000372h, in rsp'[136] (1 slot) 10( UNKNOWN) : From 0000037Dh to 000003E3h, in rbx 10( UNKNOWN) : From 000004A5h to 000004EDh, in rbx 11( UNKNOWN) : From 000004C5h to 000004E1h, in r14 12( UNKNOWN) : From 000001D1h to 00000212h, in rax 12( UNKNOWN) : From 00000212h to 00000224h, in rsp'[72] (1 slot) 12( UNKNOWN) : From 00000224h to 0000025Dh, in rax 13( UNKNOWN) : From 000003E8h to 000004A5h, in rbx //////////////////////////////////////// //////////////////////////////////////// PRINTING VARIABLE LIVE RANGES: IL Var Num 0: [rsi [27 , 5CE )] IL Var Num 1: [rdi [27 , 262 )rdi [278 , 281 )rdi [297 , 318 )rdi [32E , 4D6 )rdi [551 , 581 )rdi [58A , 5BA )] IL Var Num 2: [rbp [27 , 26B )rbp [297 , 321 )rbp [33C , 4E5 )] IL Var Num 3: [rbx [27 , 262 )rbx [278 , 278 )rbx [297 , 318 )rbx [32E , 32E )rbx [33C , 372 )] IL Var Num 4: [r15 [6C , 25D )r15 [297 , 313 )r15 [33C , 3E3 )r15 [4AF , 51B )] IL Var Num 5: [r12 [92 , 25D )r12 [297 , 313 )r12 [33C , 504 )] IL Var Num 6: [r13 [DC , 25D )r13 [297 , 313 )r13 [33C , 4C5 )] IL Var Num 7: [rsp'[140] (1 slot) [E5 , 23A )r11 [23D , 250 )rsp'[140] (1 slot) [250 , 25D )rsp'[140] (1 slot) [297 , 313 )rsp'[140] (1 slot) [33C , 350 )r8 [353 , 35B )rsp'[140] (1 slot) [35B , 4FA )] IL Var Num 8: [rax [186 , 18B )rsp'[80] (1 slot) [18B , 25D )rsp'[80] (1 slot) [297 , 313 )rsp'[80] (1 slot) [33C , 3F2 )r14 [4A0 , 4A5 )rsp'[80] (1 slot) [4A5 , 4F4 )] IL Var Num 9: [rsp'[136] (1 slot) [199 , 1E2 )r10 [1E2 , 1EB )r8 [232 , 258 )rsp'[136] (1 slot) [258 , 25D )rsp'[136] (1 slot) [297 , 2A8 )r8 [2A8 , 2B1 )rcx [348 , 36D )rsp'[136] (1 slot) [36D , 372 )] IL Var Num 10: [rbx [37D , 3E3 )rbx [4A5 , 4ED )] IL Var Num 11: [r14 [4C5 , 4E1 )] IL Var Num 12: [rax [1D1 , 212 )rsp'[72] (1 slot) [212 , 224 )rax [224 , 25D )] IL Var Num 13: [rbx [3E8 , 4A5 )] //////////////////////////////////////// //////////////////////////////////////// *************** In gcInfoBlockHdrSave() Set code length to 1487. Set ReturnKind to Scalar. Reporting this as generic context: referenced Set generic instantiation context stack slot to -80, type is THIS. Reporting this as generic context: referenced Set prolog size 0x27. Set Outgoing stack arg area size to 32. Reporting this as generic context: referenced Stack slot id for offset 144 (0x90) (sp) (untracked) = 0. Stack slot id for offset 56 (0x38) (sp) = 1. Stack slot id for offset 80 (0x50) (sp) (byref) = 2. Stack slot id for offset 48 (0x30) (sp) (byref) = 3. Stack slot id for offset 72 (0x48) (sp) = 4. Stack slot id for offset 40 (0x28) (sp) (byref) = 5. Stack slot id for offset 64 (0x40) (sp) = 6. Register slot id for reg rsi = 7. Register slot id for reg rdi = 8. Register slot id for reg rbp = 9. Register slot id for reg rcx = 10. Register slot id for reg r14 = 11. Register slot id for reg rdx = 12. Register slot id for reg r15 = 13. Register slot id for reg r12 = 14. Register slot id for reg r8 = 15. Register slot id for reg rax (byref) = 16. Register slot id for reg rax = 17. Register slot id for reg r11 (byref) = 18. Register slot id for reg rcx (byref) = 19. Register slot id for reg r8 (byref) = 20. Register slot id for reg r10 = 21. Register slot id for reg r15 (byref) = 22. Register slot id for reg r14 (byref) = 23. Set state of slot 1 at instr offset 0xee to Live. Set state of slot 1 at instr offset 0x1a2 to Dead. Set state of slot 2 at instr offset 0x18b to Live. Set state of slot 2 at instr offset 0x25d to Dead. Set state of slot 3 at instr offset 0x1fc to Live. Set state of slot 3 at instr offset 0x26e to Dead. Set state of slot 4 at instr offset 0x212 to Live. Set state of slot 4 at instr offset 0x226 to Dead. Set state of slot 2 at instr offset 0x297 to Live. Set state of slot 2 at instr offset 0x313 to Dead. Set state of slot 5 at instr offset 0x2c2 to Live. Set state of slot 5 at instr offset 0x324 to Dead. Set state of slot 6 at instr offset 0x2d2 to Live. Set state of slot 6 at instr offset 0x303 to Dead. Set state of slot 5 at instr offset 0x33c to Live. Set state of slot 5 at instr offset 0x372 to Dead. Set state of slot 2 at instr offset 0x33c to Live. Set state of slot 2 at instr offset 0x3f2 to Dead. Set state of slot 2 at instr offset 0x4a5 to Live. Set state of slot 2 at instr offset 0x511 to Dead. Set state of slot 7 at instr offset 0x1e to Live. Set state of slot 8 at instr offset 0x21 to Live. Set state of slot 9 at instr offset 0x24 to Live. Set state of slot 10 at instr offset 0x3a to Live. Set state of slot 10 at instr offset 0x41 to Dead. Set state of slot 11 at instr offset 0x59 to Live. Set state of slot 12 at instr offset 0x5c to Live. Set state of slot 10 at instr offset 0x63 to Live. Set state of slot 10 at instr offset 0x68 to Dead. Set state of slot 12 at instr offset 0x68 to Dead. Set state of slot 13 at instr offset 0x6c to Live. Set state of slot 12 at instr offset 0x78 to Live. Set state of slot 10 at instr offset 0x89 to Live. Set state of slot 10 at instr offset 0x8e to Dead. Set state of slot 12 at instr offset 0x8e to Dead. Set state of slot 14 at instr offset 0x92 to Live. Set state of slot 10 at instr offset 0xc1 to Live. Set state of slot 12 at instr offset 0xc4 to Live. Set state of slot 10 at instr offset 0xc7 to Dead. Set state of slot 12 at instr offset 0xc7 to Dead. Set state of slot 10 at instr offset 0xcf to Live. Set state of slot 10 at instr offset 0xd9 to Dead. Set state of slot 15 at instr offset 0xe9 to Live. Set state of slot 12 at instr offset 0x113 to Live. Set state of slot 15 at instr offset 0x117 to Dead. Set state of slot 10 at instr offset 0x11a to Live. Set state of slot 10 at instr offset 0x11f to Dead. Set state of slot 12 at instr offset 0x11f to Dead. Set state of slot 12 at instr offset 0x15e to Live. Set state of slot 10 at instr offset 0x165 to Live. Set state of slot 10 at instr offset 0x16a to Dead. Set state of slot 12 at instr offset 0x16a to Dead. Set state of slot 15 at instr offset 0x174 to Live. Set state of slot 16 at instr offset 0x186 to Live. Set state of slot 15 at instr offset 0x18e to Dead. Set state of slot 16 at instr offset 0x1a2 to Dead. Set state of slot 17 at instr offset 0x1d1 to Live. Set state of slot 18 at instr offset 0x1f7 to Live. Set state of slot 18 at instr offset 0x202 to Dead. Set state of slot 12 at instr offset 0x207 to Live. Set state of slot 10 at instr offset 0x20a to Live. Set state of slot 15 at instr offset 0x20d to Live. Set state of slot 17 at instr offset 0x21d to Dead. Set state of slot 10 at instr offset 0x21d to Dead. Set state of slot 12 at instr offset 0x21d to Dead. Set state of slot 15 at instr offset 0x21d to Dead. Set state of slot 17 at instr offset 0x224 to Live. Set state of slot 18 at instr offset 0x22b to Live. Set state of slot 18 at instr offset 0x23a to Dead. Set state of slot 17 at instr offset 0x25d to Dead. Set state of slot 14 at instr offset 0x25d to Dead. Set state of slot 11 at instr offset 0x25d to Dead. Set state of slot 13 at instr offset 0x25d to Dead. Set state of slot 18 at instr offset 0x267 to Live. Set state of slot 19 at instr offset 0x26b to Live. Set state of slot 12 at instr offset 0x26e to Live. Set state of slot 12 at instr offset 0x273 to Dead. Set state of slot 9 at instr offset 0x273 to Dead. Set state of slot 8 at instr offset 0x273 to Dead. Set state of slot 19 at instr offset 0x273 to Dead. Set state of slot 18 at instr offset 0x273 to Dead. Set state of slot 8 at instr offset 0x278 to Live. Set state of slot 8 at instr offset 0x281 to Dead. Set state of slot 9 at instr offset 0x297 to Live. Set state of slot 8 at instr offset 0x297 to Live. Set state of slot 14 at instr offset 0x297 to Live. Set state of slot 11 at instr offset 0x297 to Live. Set state of slot 13 at instr offset 0x297 to Live. Set state of slot 20 at instr offset 0x2bd to Live. Set state of slot 20 at instr offset 0x2c8 to Dead. Set state of slot 21 at instr offset 0x2cd to Live. Set state of slot 21 at instr offset 0x2e5 to Dead. Set state of slot 21 at instr offset 0x2ea to Live. Set state of slot 21 at instr offset 0x2ec to Dead. Set state of slot 21 at instr offset 0x303 to Live. Set state of slot 10 at instr offset 0x306 to Live. Set state of slot 12 at instr offset 0x309 to Live. Set state of slot 15 at instr offset 0x30c to Live. Set state of slot 10 at instr offset 0x30f to Dead. Set state of slot 12 at instr offset 0x30f to Dead. Set state of slot 15 at instr offset 0x30f to Dead. Set state of slot 21 at instr offset 0x30f to Dead. Set state of slot 14 at instr offset 0x313 to Dead. Set state of slot 11 at instr offset 0x313 to Dead. Set state of slot 13 at instr offset 0x313 to Dead. Set state of slot 22 at instr offset 0x31d to Live. Set state of slot 19 at instr offset 0x321 to Live. Set state of slot 12 at instr offset 0x324 to Live. Set state of slot 12 at instr offset 0x329 to Dead. Set state of slot 9 at instr offset 0x329 to Dead. Set state of slot 8 at instr offset 0x329 to Dead. Set state of slot 19 at instr offset 0x329 to Dead. Set state of slot 22 at instr offset 0x329 to Dead. Set state of slot 8 at instr offset 0x32e to Live. Set state of slot 9 at instr offset 0x33c to Live. Set state of slot 14 at instr offset 0x33c to Live. Set state of slot 11 at instr offset 0x33c to Live. Set state of slot 13 at instr offset 0x33c to Live. Set state of slot 20 at instr offset 0x341 to Live. Set state of slot 20 at instr offset 0x345 to Dead. Set state of slot 12 at instr offset 0x3a4 to Live. Set state of slot 10 at instr offset 0x3b5 to Live. Set state of slot 10 at instr offset 0x3ba to Dead. Set state of slot 12 at instr offset 0x3ba to Dead. Set state of slot 11 at instr offset 0x3ba to Dead. Set state of slot 11 at instr offset 0x3e3 to Live. Set state of slot 13 at instr offset 0x3e3 to Dead. Set state of slot 10 at instr offset 0x3fc to Live. Set state of slot 10 at instr offset 0x404 to Dead. Set state of slot 13 at instr offset 0x408 to Live. Set state of slot 12 at instr offset 0x431 to Live. Set state of slot 10 at instr offset 0x438 to Live. Set state of slot 10 at instr offset 0x43d to Dead. Set state of slot 12 at instr offset 0x43d to Dead. Set state of slot 12 at instr offset 0x479 to Live. Set state of slot 10 at instr offset 0x480 to Live. Set state of slot 10 at instr offset 0x485 to Dead. Set state of slot 12 at instr offset 0x485 to Dead. Set state of slot 11 at instr offset 0x485 to Dead. Set state of slot 16 at instr offset 0x49d to Live. Set state of slot 23 at instr offset 0x4a0 to Live. Set state of slot 13 at instr offset 0x4a5 to Dead. Set state of slot 16 at instr offset 0x4a5 to Dead. Set state of slot 23 at instr offset 0x4a5 to Dead. Set state of slot 13 at instr offset 0x4af to Live. Set state of slot 23 at instr offset 0x4c5 to Live. Set state of slot 16 at instr offset 0x4ce to Live. Set state of slot 19 at instr offset 0x4d9 to Live. Set state of slot 12 at instr offset 0x4dc to Live. Set state of slot 12 at instr offset 0x4e1 to Dead. Set state of slot 8 at instr offset 0x4e1 to Dead. Set state of slot 16 at instr offset 0x4e1 to Dead. Set state of slot 19 at instr offset 0x4e1 to Dead. Set state of slot 19 at instr offset 0x4e5 to Live. Set state of slot 12 at instr offset 0x4e8 to Live. Set state of slot 12 at instr offset 0x4ed to Dead. Set state of slot 9 at instr offset 0x4ed to Dead. Set state of slot 19 at instr offset 0x4ed to Dead. Set state of slot 23 at instr offset 0x4ed to Dead. Set state of slot 23 at instr offset 0x4f4 to Live. Set state of slot 12 at instr offset 0x507 to Live. Set state of slot 17 at instr offset 0x516 to Live. Set state of slot 12 at instr offset 0x516 to Dead. Set state of slot 14 at instr offset 0x516 to Dead. Set state of slot 23 at instr offset 0x516 to Dead. Set state of slot 10 at instr offset 0x522 to Live. Set state of slot 17 at instr offset 0x52d to Dead. Set state of slot 10 at instr offset 0x52d to Dead. Set state of slot 13 at instr offset 0x52d to Dead. Set state of slot 8 at instr offset 0x551 to Live. Set state of slot 12 at instr offset 0x584 to Live. Set state of slot 12 at instr offset 0x589 to Dead. Set state of slot 8 at instr offset 0x589 to Dead. Set state of slot 8 at instr offset 0x58a to Live. Set state of slot 12 at instr offset 0x5bd to Live. Set state of slot 12 at instr offset 0x5c2 to Dead. Set state of slot 8 at instr offset 0x5c2 to Dead. Set state of slot 7 at instr offset 0x5cf to Dead. Defining interruptible range: [0x27, 0x283). Defining interruptible range: [0x297, 0x532). Defining interruptible range: [0x546, 0x5cf). *************** Finishing PHASE Emit GC+EH tables Method code size: 1487 Allocations for System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this (MethodHash=0b956994) count: 20845, size: 1201275, max = 11760 allocateMemory: 1245184, nraUsed: 1223992 Alloc'd bytes by kind: kind | size | pct ---------------------+------------+-------- AssertionProp | 12540 | 1.04% ASTNode | 196488 | 16.36% InstDesc | 35556 | 2.96% ImpStack | 408 | 0.03% BasicBlock | 34768 | 2.89% fgArgInfo | 3328 | 0.28% fgArgInfoPtrArr | 416 | 0.03% FlowList | 8584 | 0.71% TreeStatementList | 3264 | 0.27% SiScope | 0 | 0.00% DominatorMemory | 5520 | 0.46% LSRA | 24208 | 2.02% LSRA_Interval | 20400 | 1.70% LSRA_RefPosition | 74176 | 6.17% Reachability | 32 | 0.00% SSA | 15328 | 1.28% ValueNumber | 73021 | 6.08% LvaTable | 28648 | 2.38% UnwindInfo | 0 | 0.00% hashBv | 2128 | 0.18% bitset | 51672 | 4.30% FixedBitVect | 332 | 0.03% Generic | 16636 | 1.38% LocalAddressVisitor | 512 | 0.04% FieldSeqStore | 936 | 0.08% ZeroOffsetFieldMap | 992 | 0.08% ArrayInfoMap | 856 | 0.07% MemoryPhiArg | 544 | 0.05% CSE | 12864 | 1.07% GC | 13032 | 1.08% CorTailCallInfo | 0 | 0.00% Inlining | 22376 | 1.86% ArrayStack | 3456 | 0.29% DebugInfo | 2704 | 0.23% DebugOnly | 502096 | 41.80% Codegen | 848 | 0.07% LoopOpt | 2728 | 0.23% LoopClone | 32 | 0.00% LoopHoist | 384 | 0.03% Unknown | 4358 | 0.36% RangeCheck | 9832 | 0.82% CopyProp | 8792 | 0.73% SideEffects | 0 | 0.00% ObjectAllocator | 0 | 0.00% VariableLiveRanges | 6160 | 0.51% ClassLayout | 0 | 0.00% TailMergeThrows | 232 | 0.02% EarlyProp | 0 | 0.00% ZeroInit | 88 | 0.01% Pgo | 0 | 0.00% ****** DONE compiling System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]:TryInsert(System.__Canon,System.__Canon,ubyte):bool:this Compiling 28 OrdinalComparer::GetHashCode, IL size = 21, hash=0x96c50c1a FullOpts Compiling 29 System.String::GetNonRandomizedHashCode, IL size = 152, hash=0xb82be3ba FullOpts Compiling 30 System.Environment::SetCommandLineArgs, IL size = 7, hash=0xd82f3934 FullOpts Compiling 31 System.Environment::.cctor, IL size = 11, hash=0x70727047 Tier-0 switched MinOpts Compiling 32 System.StartupHookProvider::ProcessStartupHooks, IL size = 365, hash=0x5ea4b52c FullOpts Compiling 33 System.StartupHookProvider::get_IsSupported, IL size = 18, hash=0x25c1d13b FullOpts Compiling 34 System.AppContext::TryGetSwitch, IL size = 124, hash=0x1d5a13fc FullOpts Compiling 35 System.AppContext::GetData, IL size = 67, hash=0x31c98ad7 FullOpts Compiling 36 System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]::TryGetValue, IL size = 39, hash=0x0bae2301 FullOpts Compiling 37 System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]::FindValue, IL size = 410, hash=0xe56990cf FullOpts Compiling 38 System.Diagnostics.Tracing.EventSource::.cctor, IL size = 11, hash=0xa40b7d93 Tier-0 switched MinOpts Compiling 39 System.Diagnostics.Tracing.EventSource::InitializeIsSupported, IL size = 18, hash=0xb4a4217c FullOpts Compiling 40 System.Diagnostics.Tracing.RuntimeEventSource::.ctor, IL size = 55, hash=0xd472ed50 FullOpts Compiling 41 System.Diagnostics.Tracing.EventSource::ValidateSettings, IL size = 37, hash=0xac902ced FullOpts Compiling 42 System.Diagnostics.Tracing.EventSource::Initialize, IL size = 414, hash=0x578c91f2 FullOpts Compiling 43 System.Guid::EqualsCore, IL size = 87, hash=0x825297b6 FullOpts Compiling 44 System.Diagnostics.Tracing.ActivityTracker::.cctor, IL size = 11, hash=0x65887377 Tier-0 switched MinOpts Compiling 45 System.Diagnostics.Tracing.ActivityTracker::.ctor, IL size = 7, hash=0x533948e8 FullOpts Compiling 46 System.Diagnostics.Tracing.EventSource::InitializeProviderMetadata, IL size = 391, hash=0x4857e58c FullOpts Compiling 47 System.Diagnostics.Tracing.RuntimeEventSource::get_ProviderMetadata, IL size = 13, hash=0x0210cef7 FullOpts Compiling 48 System.Diagnostics.Tracing.Statics::MetadataForString, IL size = 73, hash=0x4aeabd11 FullOpts Compiling 49 System.Diagnostics.Tracing.Statics::CheckName, IL size = 25, hash=0xe9874671 FullOpts Compiling 50 System.Text.UTF8Encoding::.cctor, IL size = 12, hash=0x7f951b3d Tier-0 switched MinOpts Compiling 51 UTF8EncodingSealed::.ctor, IL size = 8, hash=0x0886580e FullOpts Compiling 52 System.Text.UTF8Encoding::SetDefaultFallbacks, IL size = 64, hash=0xd67ed030 FullOpts Compiling 53 System.Text.EncoderReplacementFallback::.ctor, IL size = 118, hash=0x8f54c7c6 FullOpts Compiling 54 System.Text.DecoderReplacementFallback::.ctor, IL size = 118, hash=0x1d492cac FullOpts Compiling 55 System.Text.UTF8Encoding::GetByteCount, IL size = 41, hash=0x3689cb4e FullOpts Compiling 56 System.Text.Unicode.Utf16Utility::GetPointerToFirstInvalidChar, IL size = 1172, hash=0x5e6a3c37 FullOpts Compiling 57 System.Text.ASCIIUtility::GetIndexOfFirstNonAsciiChar_Sse2, IL size = 872, hash=0xaedd013e FullOpts Compiling 58 System.Text.UTF8Encoding::GetBytes, IL size = 150, hash=0x700b79aa FullOpts Compiling 59 System.Text.Unicode.Utf8Utility::TranscodeToUtf8, IL size = 1625, hash=0xecd2bd7e FullOpts Compiling 60 System.Text.ASCIIUtility::NarrowUtf16ToAscii, IL size = 530, hash=0xe3b6ae50 FullOpts Compiling 61 System.SpanHelpers::SequenceEqual, IL size = 740, hash=0x4b4c1ce1 FullOpts Compiling 62 System.Diagnostics.Tracing.EventProvider::.ctor, IL size = 46, hash=0xe05bc4c3 FullOpts Compiling 63 System.Diagnostics.Tracing.EventProvider::Register, IL size = 48, hash=0x2cc0a2b7 FullOpts Compiling 64 System.Diagnostics.Tracing.EventProvider::EventRegister, IL size = 53, hash=0x1c3f26d0 FullOpts Compiling 65 System.Diagnostics.Tracing.EtwEventProvider::System.Diagnostics.Tracing.IEventProvider.EventRegister, IL size = 19, hash=0xdc6a5587 FullOpts Compiling 66 ILStubClass::IL_STUB_PInvoke, IL size = 92, hash=0x61921e71 FullOpts Compiling 67 System.Runtime.InteropServices.Marshal::GetFunctionPointerForDelegate, IL size = 21, hash=0xe712591b FullOpts Compiling 68 System.Diagnostics.Tracing.EventListener::get_EventListenersLock, IL size = 31, hash=0x4bbe9010 FullOpts Compiling 69 System.Diagnostics.Tracing.EventListener::.cctor, IL size = 11, hash=0xb9216970 Tier-0 switched MinOpts Compiling 70 System.Diagnostics.Tracing.NativeRuntimeEventSource::.cctor, IL size = 11, hash=0xe11bc64e Tier-0 switched MinOpts Compiling 71 System.Diagnostics.Tracing.NativeRuntimeEventSource::.ctor, IL size = 63, hash=0x7a2f8951 FullOpts Compiling 72 System.Diagnostics.Tracing.NativeRuntimeEventSource::get_ProviderMetadata, IL size = 13, hash=0x21f715d6 FullOpts Compiling 73 ILStubClass::IL_STUB_ReversePInvoke, IL size = 98, hash=0x779fff56 FullOpts Compiling 74 System.Diagnostics.Tracing.EventProvider::EtwEnableCallBack, IL size = 413, hash=0xf3a7a61c FullOpts Compiling 75 System.Diagnostics.Tracing.EventProvider::GetSessions, IL size = 275, hash=0xf314983b FullOpts Compiling 76 <>c::.cctor, IL size = 11, hash=0x7a92f338 Tier-0 switched MinOpts Compiling 77 <>c::.ctor, IL size = 7, hash=0xcce2e927 FullOpts Compiling 78 System.Diagnostics.Tracing.EventProvider::GetSessionInfo, IL size = 322, hash=0x0fdeafad FullOpts Compiling 79 ILStubClass::IL_STUB_PInvoke, IL size = 84, hash=0xd947774c FullOpts Compiling 80 System.Runtime.InteropServices.Marshal::AllocHGlobal, IL size = 30, hash=0x8169b6a0 FullOpts Compiling 81 ILStubClass::IL_STUB_PInvoke, IL size = 26, hash=0xa66071d9 FullOpts Compiling 82 <>c::b__37_0, IL size = 9, hash=0xd2233060 FullOpts Compiling 83 System.Diagnostics.Tracing.EventProvider::GetSessionInfoCallback, IL size = 82, hash=0xd5401034 FullOpts Compiling 84 System.Collections.Generic.List`1[SessionInfo][System.Diagnostics.Tracing.EventProvider+SessionInfo]::.ctor, IL size = 47, hash=0xfbb82c44 FullOpts Compiling 85 System.Runtime.InteropServices.Marshal::IsNullOrWin32Atom, IL size = 20, hash=0xed63ddb0 FullOpts Compiling 86 ILStubClass::IL_STUB_PInvoke, IL size = 33, hash=0x97d8ca2a FullOpts Compiling 87 System.Collections.Generic.List`1[KeyValuePair`2][System.Collections.Generic.KeyValuePair`2[System.Diagnostics.Tracing.EventProvider+SessionInfo,System.Boolean]]::.cctor, IL size = 12, hash=0xe7d091c2 Tier-0 switched MinOpts Compiling 88 Enumerator[SessionInfo][System.Diagnostics.Tracing.EventProvider+SessionInfo]::MoveNext, IL size = 81, hash=0x75f46171 FullOpts Compiling 89 System.Diagnostics.Tracing.EventProvider::IndexOfSessionInList, IL size = 41, hash=0x85587de8 FullOpts Compiling 90 System.Collections.Generic.List`1[KeyValuePair`2][System.Collections.Generic.KeyValuePair`2[System.Diagnostics.Tracing.EventProvider+SessionInfo,System.Boolean]]::AddWithResize, IL size = 60, hash=0xc83f8eed FullOpts Compiling 91 System.Collections.Generic.List`1[KeyValuePair`2][System.Collections.Generic.KeyValuePair`2[System.Diagnostics.Tracing.EventProvider+SessionInfo,System.Boolean]]::Grow, IL size = 69, hash=0xbfdf0ee7 FullOpts Compiling 92 System.Collections.Generic.List`1[KeyValuePair`2][System.Collections.Generic.KeyValuePair`2[System.Diagnostics.Tracing.EventProvider+SessionInfo,System.Boolean]]::set_Capacity, IL size = 86, hash=0xeb996a23 FullOpts Compiling 93 Enumerator[SessionInfo][System.Diagnostics.Tracing.EventProvider+SessionInfo]::MoveNextRare, IL size = 57, hash=0x6a092e55 FullOpts Compiling 94 Enumerator[KeyValuePair`2][System.Collections.Generic.KeyValuePair`2[System.Diagnostics.Tracing.EventProvider+SessionInfo,System.Boolean]]::MoveNext, IL size = 81, hash=0x93aa859b FullOpts Compiling 95 System.Diagnostics.Tracing.EventProvider::GetDataFromController, IL size = 237, hash=0x8be3725f FullOpts Compiling 96 System.Guid::ToString, IL size = 227, hash=0xc08c4ace FullOpts Compiling 97 System.Guid::TryFormat, IL size = 951, hash=0x47d96cf2 FullOpts Compiling 98 System.Guid::HexsToChars, IL size = 50, hash=0x5c24e81f FullOpts Compiling 99 System.String::Concat, IL size = 119, hash=0xc73dad8e FullOpts Compiling 100 System.String::FillStringChecked, IL size = 71, hash=0x3942032e FullOpts Compiling 101 System.String::Concat, IL size = 73, hash=0xf9bb77fc FullOpts Compiling 102 System.Globalization.CultureInfo::get_InvariantCulture, IL size = 19, hash=0x71762a31 FullOpts Compiling 103 System.Globalization.CultureInfo::.cctor, IL size = 27, hash=0xe964e79b Tier-0 switched MinOpts Compiling 104 System.Globalization.CultureData::get_Invariant, IL size = 25, hash=0xffe3c89d FullOpts Compiling 105 System.Globalization.CultureData::.cctor, IL size = 11, hash=0x2bf1e525 Tier-0 switched MinOpts Compiling 106 System.Object::.ctor, IL size = 1, hash=0xaefc0dd8 FullOpts Compiling 107 System.Globalization.CultureData::CreateCultureWithInvariantData, IL size = 796, hash=0x8f70e6ce FullOpts Compiling 108 System.Globalization.CultureData::.ctor, IL size = 91, hash=0xaccaf6ba FullOpts Compiling 109 System.Globalization.GlobalizationMode::.cctor, IL size = 54, hash=0x6866a31f Tier-0 switched MinOpts Compiling 110 System.Globalization.GlobalizationMode::GetInvariantSwitchValue, IL size = 16, hash=0x54762333 FullOpts Compiling 111 System.AppContextConfigHelper::GetBooleanConfig, IL size = 50, hash=0xfcd422e7 FullOpts Compiling 112 System.Environment::GetEnvironmentVariable, IL size = 21, hash=0x5f11afff FullOpts Compiling 113 System.Environment::GetEnvironmentVariableCore, IL size = 116, hash=0xd3eb0284 FullOpts Compiling 114 ILStubClass::IL_STUB_PInvoke, IL size = 83, hash=0xe690bdde FullOpts Compiling 115 System.Globalization.GlobalizationMode::get_Invariant, IL size = 6, hash=0xfbafc5f5 FullOpts Compiling 116 System.Globalization.GlobalizationMode::LoadIcu, IL size = 26, hash=0x857a8ff5 FullOpts Compiling 117 System.Globalization.GlobalizationMode::TryGetAppLocalIcuSwitchValue, IL size = 17, hash=0x151deb65 FullOpts Compiling 118 System.Globalization.GlobalizationMode::TryGetStringValue, IL size = 43, hash=0x6da97331 FullOpts Compiling 119 System.Globalization.CalendarData::.cctor, IL size = 11, hash=0x9e51105b Tier-0 switched MinOpts Compiling 120 System.Globalization.CalendarData::CreateInvariant, IL size = 665, hash=0xeeac03d0 FullOpts Compiling 121 System.Globalization.CultureInfo::.ctor, IL size = 42, hash=0x6fa7eb1a FullOpts Compiling 122 System.Globalization.CultureData::get_CultureName, IL size = 66, hash=0xc8596738 FullOpts Compiling 123 System.String::Equals, IL size = 36, hash=0x63f7d387 FullOpts Compiling 124 System.Globalization.CultureInfo::GetUserDefaultLocaleName, IL size = 43, hash=0x18dfb9db FullOpts Compiling 125 System.Globalization.CultureData::GetLocaleInfoEx, IL size = 36, hash=0xea5362ea FullOpts Compiling 126 ILStubClass::IL_STUB_PInvoke, IL size = 82, hash=0x6f9ca401 FullOpts Compiling 127 System.Number::UInt32ToDecStr, IL size = 106, hash=0x0868036a FullOpts Compiling 128 Internal.Win32.Registry::.cctor, IL size = 41, hash=0xc5b7e85a Tier-0 switched MinOpts Compiling 129 System.IntPtr::op_Explicit, IL size = 7, hash=0x7cef7185 FullOpts Compiling 130 Internal.Win32.RegistryKey::OpenBaseKey, IL size = 13, hash=0xb925ff78 FullOpts Compiling 131 System.GC::SuppressFinalize, IL size = 21, hash=0x4310d4e4 FullOpts Compiling 132 Internal.Win32.RegistryKey::OpenSubKey, IL size = 93, hash=0x3ed19bc3 FullOpts Compiling 133 System.SpanHelpers::IndexOf, IL size = 143, hash=0x624ef25e FullOpts Compiling 134 ILStubClass::IL_STUB_PInvoke, IL size = 157, hash=0x58c70cb3 FullOpts Compiling 135 System.StubHelpers.StubHelpers::SafeHandleAddRef, IL size = 26, hash=0x5018d59f FullOpts Compiling 136 System.Runtime.InteropServices.SafeHandle::DangerousAddRef, IL size = 67, hash=0x99d5f733 FullOpts Compiling 137 System.StubHelpers.StubHelpers::SafeHandleRelease, IL size = 19, hash=0xe7d1abb0 FullOpts Compiling 138 System.Runtime.InteropServices.SafeHandle::InternalRelease, IL size = 146, hash=0x55d2cefb FullOpts Compiling 139 System.Runtime.CompilerServices.CastHelpers::IsInstanceOfAny, IL size = 42, hash=0xeb4607a4 FullOpts Compiling 140 OverrideEventProvider::OnControllerCommand, IL size = 44, hash=0x7be0cc88 FullOpts Compiling 141 System.Diagnostics.Tracing.EventSource::SendCommand, IL size = 131, hash=0xe26ad5bb FullOpts Compiling 142 System.Collections.Generic.List`1[__Canon][System.__Canon]::.ctor, IL size = 47, hash=0xae2ba072 FullOpts Compiling 143 Enumerator[KeyValuePair`2][System.Collections.Generic.KeyValuePair`2[System.Diagnostics.Tracing.EventProvider+SessionInfo,System.Boolean]]::MoveNextRare, IL size = 57, hash=0xd376a4bf FullOpts Compiling 144 System.Diagnostics.Tracing.EventPipeEventProvider::System.Diagnostics.Tracing.IEventProvider.EventRegister, IL size = 49, hash=0x27032121 FullOpts Compiling 145 ILStubClass::IL_STUB_PInvoke, IL size = 92, hash=0x78e8e1bc FullOpts Compiling 146 System.Diagnostics.Tracing.EventListener::AddEventSource, IL size = 220, hash=0x7c25cb8d FullOpts Compiling 147 System.Diagnostics.Tracing.EventListener::Validate, IL size = 326, hash=0xddb2c191 FullOpts Compiling 148 System.Collections.Generic.Dictionary`2[__Canon,Boolean][System.__Canon,System.Boolean]::.ctor, IL size = 102, hash=0xd6de57bd FullOpts Compiling 149 System.Collections.Generic.Dictionary`2[__Canon,Boolean][System.__Canon,System.Boolean]::get_Keys, IL size = 26, hash=0x3a7774a2 FullOpts Compiling 150 Enumerator[__Canon,Boolean][System.__Canon,System.Boolean]::MoveNext, IL size = 135, hash=0xd4f7a88c FullOpts Compiling 151 System.Diagnostics.Tracing.EventProvider::SetInformation, IL size = 38, hash=0xe5d05799 FullOpts Compiling 152 ILStubClass::IL_STUB_PInvoke, IL size = 62, hash=0xae3eaeb5 FullOpts Compiling 153 System.Diagnostics.Tracing.EventSource::DoCommand, IL size = 783, hash=0x0dc25a7f FullOpts Compiling 154 System.Diagnostics.Tracing.EventSource::EnsureDescriptorsInitialized, IL size = 274, hash=0xcdc4717e FullOpts Compiling 155 System.Threading.Monitor::IsEntered, IL size = 21, hash=0xc9ba3f20 FullOpts Compiling 156 System.Diagnostics.Tracing.EventSource::CreateManifestAndDescriptors, IL size = 1911, hash=0x391c3a31 FullOpts Compiling 157 System.Diagnostics.Tracing.EventSource::get_SelfDescribingEvents, IL size = 44, hash=0x146cdcbe FullOpts Compiling 158 System.RuntimeType::GetAttributeFlagsImpl, IL size = 7, hash=0xfbb48c49 FullOpts Compiling 159 System.RuntimeType::GetMethods, IL size = 21, hash=0xba10a82b FullOpts Compiling 160 System.RuntimeType::GetMethodCandidates, IL size = 118, hash=0x3d7675c6 FullOpts Compiling 161 System.RuntimeType::FilterHelper, IL size = 94, hash=0x0d0cc886 FullOpts Compiling 162 System.RuntimeType::InitializeCache, IL size = 140, hash=0x52f207fb FullOpts Compiling 163 System.RuntimeTypeHandle::GetNativeHandle, IL size = 35, hash=0x48485345 FullOpts Compiling 164 System.RuntimeTypeHandle::get_Value, IL size = 32, hash=0x5ad30f95 FullOpts Compiling 165 RuntimeTypeCache::.ctor, IL size = 44, hash=0xc115d8c1 FullOpts Compiling 166 System.Reflection.RuntimeModule::get_RuntimeType, IL size = 26, hash=0x3c82451e FullOpts Compiling 167 System.ModuleHandle::GetModuleType, IL size = 23, hash=0xb8026be0 FullOpts Compiling 168 RuntimeTypeCache::GetMemberCache, IL size = 29, hash=0xf8f1c6f8 FullOpts Compiling 169 MemberInfoCache`1[__Canon][System.__Canon]::GetMemberList, IL size = 101, hash=0x83b7a38a FullOpts Compiling 170 MemberInfoCache`1[__Canon][System.__Canon]::Populate, IL size = 180, hash=0x90798aa8 FullOpts Compiling 171 MemberInfoCache`1[__Canon][System.__Canon]::GetListByName, IL size = 157, hash=0xdeb40eb4 FullOpts Compiling 172 MemberInfoCache`1[__Canon][System.__Canon]::PopulateMethods, IL size = 834, hash=0x1d6a2c13 FullOpts Compiling 173 System.RuntimeType::IsValueTypeImpl, IL size = 55, hash=0x447c1bc8 FullOpts Compiling 174 System.RuntimeType::IsSubclassOf, IL size = 94, hash=0x1f9a31b3 FullOpts Compiling 175 System.RuntimeType::GetBaseType, IL size = 140, hash=0x370d2523 FullOpts Compiling 176 System.Type::get_IsInterface, IL size = 31, hash=0x78d5dd53 FullOpts Compiling 177 System.RuntimeType::.cctor, IL size = 81, hash=0x81ba7336 Tier-0 switched MinOpts Compiling 178 IntroducedMethodEnumerator::MoveNext, IL size = 76, hash=0x366d1aee FullOpts Compiling 179 System.RuntimeType::FilterPreCalculate, IL size = 48, hash=0x488fd6b5 FullOpts Compiling 180 ListBuilder`1[__Canon][System.__Canon]::Add, IL size = 154, hash=0xb37a02dc FullOpts Compiling 181 System.String::Equals, IL size = 35, hash=0x5f0995c9 FullOpts Compiling 182 System.Array::Resize, IL size = 82, hash=0x7fb04feb FullOpts Compiling 183 System.Buffer::Memmove, IL size = 59, hash=0x8415318b FullOpts Compiling 184 ListBuilder`1[__Canon][System.__Canon]::ToArray, IL size = 79, hash=0x1a9326a3 FullOpts Compiling 185 System.Buffer::_BulkMoveWithWriteBarrier, IL size = 150, hash=0x153fe603 FullOpts Compiling 186 MemberInfoCache`1[__Canon][System.__Canon]::Insert, IL size = 246, hash=0x8587407a FullOpts Compiling 187 MemberInfoCache`1[__Canon][System.__Canon]::MergeWithGlobalList, IL size = 256, hash=0xf3de4259 FullOpts Compiling 188 System.RuntimeType::FilterApplyMethodBase, IL size = 311, hash=0x2a71fff5 FullOpts Compiling 189 System.Runtime.CompilerServices.CastHelpers::StelemRef_Helper, IL size = 34, hash=0x36729024 FullOpts Compiling 190 System.Runtime.CompilerServices.CastHelpers::StelemRef_Helper_NoCacheLookup, IL size = 35, hash=0x6e703f94 FullOpts Compiling 191 System.Diagnostics.Tracing.EventSource::GetCustomAttributeHelper, IL size = 401, hash=0x06dc157a FullOpts Compiling 192 System.Reflection.MemberInfo::get_Module, IL size = 23, hash=0x275fbe6f FullOpts Compiling 193 System.Runtime.CompilerServices.CastHelpers::IsInstanceOfClass, IL size = 111, hash=0x649b98dc FullOpts Compiling 194 System.RuntimeType::get_Module, IL size = 7, hash=0x4c250fdc FullOpts Compiling 195 System.Reflection.RuntimeModule::get_Assembly, IL size = 7, hash=0x2d898d57 FullOpts Compiling 196 System.Reflection.RuntimeAssembly::get_ReflectionOnly, IL size = 2, hash=0x07524e4c FullOpts Compiling 197 System.Attribute::GetCustomAttribute, IL size = 39, hash=0xccd2d29c FullOpts Compiling 198 System.Attribute::GetCustomAttributes, IL size = 151, hash=0x0e5dace9 FullOpts Compiling 199 System.RuntimeType::get_MemberType, IL size = 25, hash=0xec61a325 FullOpts Compiling 200 System.RuntimeType::GetCustomAttributes, IL size = 60, hash=0xef1c6d74 FullOpts Compiling 201 System.RuntimeType::get_UnderlyingSystemType, IL size = 2, hash=0x23dd578d FullOpts Compiling 202 System.Reflection.CustomAttribute::GetCustomAttributes, IL size = 394, hash=0xba773c55 FullOpts Compiling 203 System.Reflection.PseudoCustomAttribute::GetCustomAttributes, IL size = 166, hash=0x0b0b93eb FullOpts Compiling 204 System.Reflection.PseudoCustomAttribute::.cctor, IL size = 11, hash=0x0d76c8ac Tier-0 switched MinOpts Compiling 205 System.Reflection.PseudoCustomAttribute::CreatePseudoCustomAttributeHashSet, IL size = 206, hash=0xdc470fa2 FullOpts Compiling 206 System.Collections.Generic.HashSet`1[__Canon][System.__Canon]::.ctor, IL size = 79, hash=0x3fd08702 FullOpts Compiling 207 System.Collections.Generic.HashSet`1[__Canon][System.__Canon]::Initialize, IL size = 56, hash=0xae8ab045 FullOpts Compiling 208 System.Reflection.PseudoCustomAttribute::VerifyPseudoCustomAttribute, IL size = 58, hash=0x1be65e24 FullOpts Compiling 209 System.Reflection.CustomAttribute::GetAttributeUsage, IL size = 180, hash=0x4eef75e7 FullOpts Compiling 210 System.Reflection.CustomAttributeData::GetCustomAttributeRecords, IL size = 105, hash=0x41995803 FullOpts Compiling 211 System.Reflection.MetadataEnumResult::get_Item, IL size = 61, hash=0x13f0e411 FullOpts Compiling 212 System.Reflection.RuntimeModule::ResolveType, IL size = 179, hash=0x3447c310 FullOpts Compiling 213 System.Reflection.RuntimeModule::GetModuleHandleImpl, IL size = 7, hash=0x483e3bf9 FullOpts Compiling 214 System.ModuleHandle::ResolveTypeHandle, IL size = 254, hash=0xea92f533 FullOpts Compiling 215 ILStubClass::IL_STUB_PInvoke, IL size = 81, hash=0x7925cc5a FullOpts Compiling 216 System.Collections.Generic.HashSet`1[__Canon][System.__Canon]::AddIfNotPresent, IL size = 677, hash=0x3c67e253 FullOpts Compiling 217 System.RuntimeType::GetHashCode, IL size = 7, hash=0x343c93ad FullOpts Compiling 218 System.RuntimeType::MakeGenericType, IL size = 315, hash=0x4906635a FullOpts Compiling 219 System.RuntimeType::GetGenericArgumentsInternal, IL size = 20, hash=0xbbc42e9e FullOpts Compiling 220 System.Type::GetRootElementType, IL size = 21, hash=0x6cd9fa4e FullOpts Compiling 221 System.RuntimeType::HasElementTypeImpl, IL size = 7, hash=0x4d43681d FullOpts Compiling 222 System.Type::GetTypeHandleInternal, IL size = 7, hash=0x52ffeccd FullOpts Compiling 223 System.RuntimeType::get_TypeHandle, IL size = 7, hash=0xc36eeac9 FullOpts Compiling 224 System.RuntimeTypeHandle::GetInstantiationInternal, IL size = 31, hash=0x56c7f9ea FullOpts Compiling 225 System.RuntimeType::ThrowIfTypeNeverValidGenericArgument, IL size = 52, hash=0x7de74801 FullOpts Compiling 226 System.RuntimeTypeHandle::Instantiate, IL size = 55, hash=0x77b81d9f FullOpts Compiling 227 System.RuntimeType::IsAssignableFrom, IL size = 115, hash=0x12dfbfed FullOpts Compiling 228 System.RuntimeType::get_IsGenericType, IL size = 7, hash=0x8919a943 FullOpts Compiling 229 System.Type::get_IsEnum, IL size = 17, hash=0x117dc945 FullOpts Compiling 230 System.RuntimeTypeHandle::CreateInstanceForAnotherGenericParameter, IL size = 82, hash=0xbad6e0d6 FullOpts Compiling 231 System.Type::.cctor, IL size = 87, hash=0x1ea4fd6a Tier-0 switched MinOpts Compiling 232 System.Array::Empty, IL size = 6, hash=0xdfe11da3 FullOpts Compiling 233 EmptyArray`1[__Canon][System.__Canon]::.cctor, IL size = 12, hash=0x10b86acf Tier-0 switched MinOpts Compiling 234 System.Reflection.Missing::.cctor, IL size = 11, hash=0xcd8c1e3f Tier-0 switched MinOpts Compiling 235 System.Reflection.Missing::.ctor, IL size = 7, hash=0x14831420 FullOpts Compiling 236 System.MulticastDelegate::CtorOpened, IL size = 22, hash=0x70b3b9bb FullOpts Compiling 237 <>c::.cctor, IL size = 11, hash=0x7a92f338 Tier-0 switched MinOpts Compiling 238 <>c::.ctor, IL size = 7, hash=0xcce2e927 FullOpts Compiling 239 System.MulticastDelegate::CtorClosed, IL size = 23, hash=0x14235e3a FullOpts Compiling 240 System.Type::GetConstructor, IL size = 67, hash=0xa96a8dea FullOpts Compiling 241 System.RuntimeType::GetConstructorImpl, IL size = 133, hash=0x4d1fbeae FullOpts Compiling 242 System.RuntimeType::GetConstructorCandidates, IL size = 103, hash=0xd9a65ed9 FullOpts Compiling 243 MemberInfoCache`1[__Canon][System.__Canon]::PopulateConstructors, IL size = 290, hash=0x4dab0773 FullOpts Compiling 244 System.Reflection.RuntimeConstructorInfo::GetParametersNoCopy, IL size = 33, hash=0xdf63f34b FullOpts Compiling 245 System.Reflection.RuntimeConstructorInfo::g__LazyCreateSignature|19_0, IL size = 29, hash=0x1b6712f2 FullOpts Compiling 246 System.Reflection.RuntimeParameterInfo::GetParameters, IL size = 37, hash=0x500f9d4e FullOpts Compiling 247 System.Reflection.RuntimeParameterInfo::GetParameters, IL size = 318, hash=0xf683670a FullOpts Compiling 248 System.Reflection.RuntimeConstructorInfo::System.IRuntimeMethodInfo.get_Value, IL size = 12, hash=0x0125a849 FullOpts Compiling 249 System.Reflection.RuntimeConstructorInfo::get_Attributes, IL size = 7, hash=0x11b16555 FullOpts Compiling 250 System.Collections.Generic.ObjectEqualityComparer`1[__Canon][System.__Canon]::.ctor, IL size = 7, hash=0x7d42486b FullOpts Compiling 251 System.Collections.Generic.HashSet`1[__Canon][System.__Canon]::FindItemIndex, IL size = 385, hash=0x41da1e96 FullOpts Compiling 252 System.Reflection.CustomAttribute::GetCustomAttributes, IL size = 125, hash=0xa4d1511c FullOpts Compiling 253 System.Reflection.CustomAttribute::AddCustomAttributes, IL size = 537, hash=0xba5d58b7 FullOpts Compiling 254 System.Reflection.CustomAttribute::FilterCustomAttributeRecord, IL size = 543, hash=0xe99a7fa6 FullOpts Compiling 255 System.RuntimeType::IsAssignableFrom, IL size = 24, hash=0x78deb82a FullOpts Compiling 256 System.Reflection.TypeInfo::AsType, IL size = 2, hash=0x6580a2f5 FullOpts Compiling 257 System.Reflection.CustomAttribute::AttributeUsageCheck, IL size = 88, hash=0x1c68d633 FullOpts Compiling 258 System.Reflection.RuntimeConstructorInfo::CheckCanCreateInstance, IL size = 163, hash=0xa9d07670 FullOpts Compiling 259 System.RuntimeType::get_ContainsGenericParameters, IL size = 20, hash=0x53f4a4b8 FullOpts Compiling 260 System.RuntimeTypeHandle::GetTypeChecked, IL size = 30, hash=0x4adf779b FullOpts Compiling 261 System.RuntimeType::CreateInstanceDefaultCtor, IL size = 105, hash=0xaa7a49e9 FullOpts Compiling 262 ActivatorCache::.ctor, IL size = 254, hash=0x640fcfa4 FullOpts Compiling 263 System.RuntimeType::CreateInstanceCheckThis, IL size = 81, hash=0xee2ab0a0 FullOpts Compiling 264 System.RuntimeTypeHandle::GetActivationInfo, IL size = 79, hash=0x3e318438 FullOpts Compiling 265 System.Diagnostics.Tracing.EventSourceAttribute::.ctor, IL size = 7, hash=0x701f7df0 FullOpts Compiling 266 System.Reflection.CustomAttribute::.cctor, IL size = 41, hash=0x5664d6f4 Tier-0 switched MinOpts Compiling 267 System.Type::GetProperty, IL size = 45, hash=0x3ecd2fb8 FullOpts Compiling 268 System.RuntimeType::GetPropertyImpl, IL size = 162, hash=0xda3f743c FullOpts Compiling 269 System.RuntimeType::GetPropertyCandidates, IL size = 130, hash=0x99b90ac6 FullOpts Compiling 270 System.Reflection.CerHashtable`2[__Canon,__Canon][System.__Canon,System.__Canon]::get_Item, IL size = 138, hash=0x31b009ac FullOpts Compiling 271 System.Text.UTF8Encoding::GetByteCount, IL size = 34, hash=0xb4a4b4c5 FullOpts Compiling 272 System.Text.UTF8Encoding::GetBytes, IL size = 64, hash=0x6f3a940c FullOpts Compiling 273 MemberInfoCache`1[__Canon][System.__Canon]::PopulateProperties, IL size = 149, hash=0xe42f15a6 FullOpts Compiling 274 MemberInfoCache`1[__Canon][System.__Canon]::PopulateProperties, IL size = 570, hash=0xa195fafa FullOpts Compiling 275 System.Reflection.MetadataToken::IsTokenOfType, IL size = 33, hash=0x80ce541b FullOpts Compiling 276 System.SpanHelpers::IndexOf, IL size = 885, hash=0xe0a010d4 FullOpts Compiling 277 Filter::Match, IL size = 67, hash=0xdea4ec6d FullOpts Compiling 278 Filter::RequiresStringComparison, IL size = 21, hash=0x351931c4 FullOpts Compiling 279 System.Reflection.RuntimePropertyInfo::.ctor, IL size = 143, hash=0xd823cca3 FullOpts Compiling 280 System.Reflection.Associates::AssignAssociates, IL size = 402, hash=0x0d418bf0 FullOpts Compiling 281 System.Reflection.Associates::AssignAssociates, IL size = 262, hash=0xdd306a1b FullOpts Compiling 282 System.ModuleHandle::ResolveMethodHandleInternal, IL size = 144, hash=0xa633ce88 FullOpts Compiling 283 ILStubClass::IL_STUB_PInvoke, IL size = 83, hash=0xa26cde4c FullOpts Compiling 284 System.RuntimeType::GetMethodBase, IL size = 485, hash=0xa0569fd6 FullOpts Compiling 285 MemberInfoCache`1[__Canon][System.__Canon]::AddMethod, IL size = 364, hash=0x7a2bb290 FullOpts Compiling 286 System.Reflection.RuntimeMethodInfo::.ctor, IL size = 88, hash=0x0e8b9ed6 FullOpts Compiling 287 System.Reflection.RuntimeMethodInfo::System.IRuntimeMethodInfo.get_Value, IL size = 12, hash=0x7180eede FullOpts Compiling 288 System.Reflection.RuntimeMethodInfo::CacheEquals, IL size = 30, hash=0xe8a8e334 FullOpts Compiling 289 System.Reflection.Associates::IncludeAccessor, IL size = 22, hash=0xe2d672bb FullOpts Compiling 290 System.Reflection.RuntimeMethodInfo::get_Attributes, IL size = 7, hash=0x8cf0ce42 FullOpts Compiling 291 System.Reflection.CerHashtable`2[__Canon,__Canon][System.__Canon,System.__Canon]::set_Item, IL size = 62, hash=0x493247ce FullOpts Compiling 292 System.Reflection.CerHashtable`2[__Canon,__Canon][System.__Canon,System.__Canon]::Rehash, IL size = 97, hash=0xc44aae7c FullOpts Compiling 293 Table[__Canon,__Canon][System.__Canon,System.__Canon]::.ctor, IL size = 39, hash=0x997e8f4b FullOpts Compiling 294 Table[__Canon,__Canon][System.__Canon,System.__Canon]::Insert, IL size = 132, hash=0xb37b7de7 FullOpts Compiling 295 System.Reflection.CerHashtable`2[__Canon,__Canon][System.__Canon,System.__Canon]::GetHashCodeHelper, IL size = 34, hash=0xf4352936 FullOpts Compiling 296 System.Reflection.RuntimePropertyInfo::GetIndexParameters, IL size = 33, hash=0x15dbb2be FullOpts Compiling 297 System.Reflection.RuntimePropertyInfo::GetIndexParametersNoCopy, IL size = 128, hash=0x5d3027da FullOpts Compiling 298 System.Reflection.RuntimeMethodInfo::GetParametersNoCopy, IL size = 7, hash=0x275df47c FullOpts Compiling 299 System.Reflection.RuntimeMethodInfo::FetchNonReturnParameters, IL size = 33, hash=0x0a2355d7 FullOpts Compiling 300 System.Reflection.RuntimeMethodInfo::g__LazyCreateSignature|24_0, IL size = 27, hash=0xa5c38cab FullOpts Compiling 301 System.Reflection.RuntimePropertyInfo::get_PropertyType, IL size = 12, hash=0x1f7cebaa FullOpts Compiling 302 System.Reflection.RuntimePropertyInfo::get_Signature, IL size = 86, hash=0x15350d2d FullOpts Compiling 303 System.RuntimeType::IsEquivalentTo, IL size = 31, hash=0x14b13407 FullOpts Compiling 304 System.Reflection.RuntimePropertyInfo::GetSetMethod, IL size = 23, hash=0x3cc057d9 FullOpts Compiling 305 System.Reflection.RuntimeMethodInfo::Invoke, IL size = 91, hash=0x19b8c3ba FullOpts Compiling 306 System.Reflection.RuntimeMethodInfo::InvokeArgumentsCheck, IL size = 103, hash=0xe3b7c94d FullOpts Compiling 307 System.Reflection.RuntimeMethodInfo::g__LazyCreateInvocationFlags|13_0, IL size = 113, hash=0x5115bf53 FullOpts Compiling 308 System.Reflection.RuntimeMethodInfo::get_DeclaringType, IL size = 22, hash=0x6a3cc7c8 FullOpts Compiling 309 System.Reflection.RuntimeMethodInfo::get_ContainsGenericParameters, IL size = 74, hash=0xd31d1278 FullOpts Compiling 310 System.Reflection.RuntimeMethodInfo::IsDisallowedByRefType, IL size = 44, hash=0x7d180df8 FullOpts Compiling 311 System.RuntimeType::IsByRefImpl, IL size = 7, hash=0xdc3b7751 FullOpts Compiling 312 System.RuntimeType::get_IsByRefLike, IL size = 7, hash=0x0fd972ab FullOpts Compiling 313 System.Reflection.MethodBase::CheckArguments, IL size = 187, hash=0x029dcf6b FullOpts Compiling 314 System.RuntimeType::CheckValue, IL size = 259, hash=0xb8ffb813 FullOpts Compiling 315 System.Diagnostics.Tracing.EventSourceAttribute::set_Guid, IL size = 8, hash=0xcfab4e68 FullOpts Compiling 316 System.Reflection.RuntimePropertyInfo::CacheEquals, IL size = 54, hash=0x02fc1eec FullOpts Compiling 317 System.Diagnostics.Tracing.EventSourceAttribute::set_Name, IL size = 8, hash=0x29267bd0 FullOpts Compiling 318 System.Reflection.CustomAttribute::CreateAttributeArrayHelper, IL size = 23, hash=0x915d80c6 FullOpts Compiling 319 System.Array::CreateInstance, IL size = 80, hash=0x5d4438a5 FullOpts Compiling 320 System.Diagnostics.Tracing.ManifestBuilder::.ctor, IL size = 339, hash=0x6fc61171 FullOpts Compiling 321 System.Collections.Generic.Dictionary`2[Int32,__Canon][System.Int32,System.__Canon]::.ctor, IL size = 102, hash=0x6b50e962 FullOpts Compiling 322 System.Collections.Generic.List`1[__Canon][System.__Canon]::.cctor, IL size = 12, hash=0x340ebdde Tier-0 switched MinOpts Compiling 323 System.Text.StringBuilder::AppendLine, IL size = 20, hash=0xa98367c6 FullOpts Compiling 324 System.Text.StringBuilder::Append, IL size = 113, hash=0x20c0cc28 FullOpts Compiling 325 System.Text.StringBuilder::AppendHelper, IL size = 35, hash=0x10eea8b8 FullOpts Compiling 326 System.Text.StringBuilder::Append, IL size = 268, hash=0xda2fd903 FullOpts Compiling 327 System.Text.StringBuilder::ExpandByABlock, IL size = 189, hash=0xef483c28 FullOpts Compiling 328 System.Text.StringBuilder::AssertInvariants, IL size = 189, hash=0x9a6519af FullOpts Compiling 329 System.Text.StringBuilder::Append, IL size = 51, hash=0x4693b7b1 FullOpts Compiling 330 System.String::Replace, IL size = 301, hash=0xee849cf8 FullOpts Compiling 331 System.String::ReplaceHelper, IL size = 249, hash=0xda2e157b FullOpts Compiling 332 System.String::Replace, IL size = 287, hash=0x695a7758 FullOpts Compiling 333 System.Diagnostics.Tracing.ManifestBuilder::StartEvent, IL size = 394, hash=0x56771ec2 FullOpts Compiling 334 System.Text.StringBuilder::AppendSpanFormattable, IL size = 114, hash=0xc9e8f5b4 FullOpts Compiling 335 System.Reflection.Assembly::Equals, IL size = 8, hash=0x405ce78b FullOpts Compiling 336 System.Number::TryFormatInt32, IL size = 62, hash=0xc70357cc FullOpts Compiling 337 System.Number::TryUInt32ToDecStr, IL size = 115, hash=0x77e246b8 FullOpts Compiling 338 System.Number::Int32ToDecStr, IL size = 29, hash=0x91ea2d1f FullOpts Compiling 339 System.Number::.cctor, IL size = 544, hash=0x95138151 Tier-0 switched MinOpts Compiling 340 System.Text.StringBuilder::AppendSpanFormattable, IL size = 114, hash=0xa1be64b8 FullOpts Compiling 341 System.Diagnostics.Tracing.ManifestBuilder::AppendLevelName, IL size = 118, hash=0x119325c7 FullOpts Compiling 342 System.Diagnostics.Tracing.ManifestBuilder::WriteMessageAttrib, IL size = 156, hash=0x3c4424a7 FullOpts Compiling 343 System.Diagnostics.Tracing.ManifestBuilder::GetTaskName, IL size = 63, hash=0x9211ba0e FullOpts Compiling 344 System.Collections.Generic.Dictionary`2[Int32,__Canon][System.Int32,System.__Canon]::TryGetValue, IL size = 39, hash=0xbce5bcd4 FullOpts Compiling 345 System.Collections.Generic.Dictionary`2[Int32,__Canon][System.Int32,System.__Canon]::FindValue, IL size = 410, hash=0xf12dbb3a FullOpts Compiling 346 System.Collections.Generic.Dictionary`2[Int32,__Canon][System.Int32,System.__Canon]::TryInsert, IL size = 739, hash=0x9b226d21 FullOpts Compiling 347 System.Collections.Generic.Dictionary`2[Int32,__Canon][System.Int32,System.__Canon]::Initialize, IL size = 56, hash=0xc53ca305 FullOpts Compiling 348 System.Diagnostics.Tracing.ManifestBuilder::AddEventParameter, IL size = 452, hash=0xfa518452 FullOpts Compiling 349 System.Diagnostics.Tracing.ManifestBuilder::GetTypeName, IL size = 319, hash=0xf73036c9 FullOpts Compiling 350 System.RuntimeType::GetTypeCodeImpl, IL size = 286, hash=0xc393095f FullOpts Compiling 351 System.RuntimeType::IsArrayImpl, IL size = 7, hash=0x9e286c02 FullOpts Compiling 352 System.RuntimeType::IsPointerImpl, IL size = 7, hash=0x4d766d20 FullOpts Compiling 353 System.Diagnostics.Tracing.ManifestBuilder::EndEvent, IL size = 208, hash=0x765a30d4 FullOpts Compiling 354 System.RuntimeType::GetNestedType, IL size = 124, hash=0x79875506 FullOpts Compiling 355 System.RuntimeType::SplitName, IL size = 108, hash=0x9543e8ba FullOpts Compiling 356 System.String::LastIndexOf, IL size = 23, hash=0xb644bea9 FullOpts Compiling 357 System.String::LastIndexOf, IL size = 135, hash=0x44c8c5a9 FullOpts Compiling 358 System.Globalization.CompareInfo::.cctor, IL size = 16, hash=0x44ff9330 Tier-0 switched MinOpts Compiling 359 System.Globalization.CultureInfo::get_CompareInfo, IL size = 52, hash=0x27e4e273 FullOpts Compiling 360 System.Globalization.CompareInfo::InitSort, IL size = 33, hash=0x271d6429 FullOpts Compiling 361 System.Globalization.CultureInfo::get_SortName, IL size = 31, hash=0x3946c970 FullOpts Compiling 362 System.Globalization.CultureData::get_SortName, IL size = 26, hash=0xae25a5ce FullOpts Compiling 363 System.Globalization.CompareInfo::IcuInitSortHandle, IL size = 150, hash=0xef247d5e FullOpts Compiling 364 SortHandleCache::GetCachedSortHandle, IL size = 106, hash=0xccbdc782 FullOpts Compiling 365 SortHandleCache::.cctor, IL size = 11, hash=0xb2685ca5 Tier-0 switched MinOpts Compiling 366 System.Collections.Generic.Dictionary`2[__Canon,IntPtr][System.__Canon,System.IntPtr]::.ctor, IL size = 9, hash=0x22097273 FullOpts Compiling 367 System.Collections.Generic.Dictionary`2[__Canon,IntPtr][System.__Canon,System.IntPtr]::.ctor, IL size = 102, hash=0x2399c31d FullOpts Compiling 368 System.Collections.Generic.Dictionary`2[__Canon,IntPtr][System.__Canon,System.IntPtr]::TryGetValue, IL size = 39, hash=0x17a2bc41 FullOpts Compiling 369 System.Collections.Generic.Dictionary`2[__Canon,IntPtr][System.__Canon,System.IntPtr]::FindValue, IL size = 410, hash=0xb1e8140f FullOpts Compiling 370 ILStubClass::IL_STUB_PInvoke, IL size = 126, hash=0xd7a26de1 FullOpts Compiling 371 System.Runtime.InteropServices.Marshal::.cctor, IL size = 53, hash=0xb64f8493 Tier-0 switched MinOpts Compiling 372 System.Guid::.ctor, IL size = 86, hash=0xae68ccc1 FullOpts Compiling 373 ILStubClass::IL_STUB_PInvoke, IL size = 32, hash=0x72746344 FullOpts Compiling 374 System.Runtime.InteropServices.Marshal::GetSystemMaxDBCSCharSize, IL size = 28, hash=0xa587a731 FullOpts Compiling 375 System.StubHelpers.CSTRMarshaler::ConvertToNative, IL size = 224, hash=0xc31c0dcd FullOpts Compiling 376 System.Runtime.InteropServices.Marshal::StringToAnsiString, IL size = 129, hash=0x6e968294 FullOpts Compiling 377 System.Collections.Generic.Dictionary`2[__Canon,IntPtr][System.__Canon,System.IntPtr]::TryInsert, IL size = 739, hash=0xfb763ad8 FullOpts Compiling 378 System.Collections.Generic.Dictionary`2[__Canon,IntPtr][System.__Canon,System.IntPtr]::Initialize, IL size = 56, hash=0xfd4073c5 FullOpts Compiling 379 System.String::GetCompareOptionsFromOrdinalStringComparison, IL size = 26, hash=0x20958e72 FullOpts Compiling 380 System.Globalization.CompareInfo::LastIndexOf, IL size = 131, hash=0x262b062c FullOpts Compiling 381 System.Globalization.CompareInfo::LastIndexOf, IL size = 112, hash=0x0721186c FullOpts Compiling 382 System.SpanHelpers::LastIndexOf, IL size = 131, hash=0x17694294 FullOpts Compiling 383 System.SpanHelpers::LastIndexOf, IL size = 552, hash=0x21b876c6 FullOpts Compiling 384 MemberInfoCache`1[__Canon][System.__Canon]::PopulateNestedClasses, IL size = 187, hash=0xd263488a FullOpts Compiling 385 System.RuntimeType::FilterApplyType, IL size = 85, hash=0x9127ef07 FullOpts Compiling 386 System.RuntimeType::FilterApplyBase, IL size = 233, hash=0xe20feb55 FullOpts Compiling 387 System.RuntimeType::get_DeclaringType, IL size = 12, hash=0xea034008 FullOpts Compiling 388 RuntimeTypeCache::GetEnclosingType, IL size = 105, hash=0x413719e9 FullOpts Compiling 389 System.RuntimeType::get_ReflectedType, IL size = 7, hash=0xdfdcdf3b FullOpts Compiling 390 System.RuntimeType::GetFields, IL size = 18, hash=0x90dfad6b FullOpts Compiling 391 System.RuntimeType::GetFieldCandidates, IL size = 112, hash=0xde4ea13f FullOpts Compiling 392 MemberInfoCache`1[__Canon][System.__Canon]::PopulateFields, IL size = 232, hash=0xbfde0af3 FullOpts Compiling 393 MemberInfoCache`1[__Canon][System.__Canon]::PopulateRtFields, IL size = 98, hash=0x0622677e FullOpts Compiling 394 MemberInfoCache`1[__Canon][System.__Canon]::PopulateLiteralFields, IL size = 285, hash=0x270a6393 FullOpts Compiling 395 System.Diagnostics.Tracing.EventSource::AddProviderEnumKind, IL size = 299, hash=0x189df7ca FullOpts Compiling 396 System.Reflection.RuntimeFieldInfo::get_Module, IL size = 7, hash=0x213d3201 FullOpts Compiling 397 System.Reflection.MdFieldInfo::GetRuntimeModule, IL size = 12, hash=0x026441ab FullOpts Compiling 398 System.Reflection.MdFieldInfo::get_FieldType, IL size = 91, hash=0x6a6728df FullOpts Compiling 399 System.Diagnostics.Tracing.EventSource::AttributeTypeNamesMatch, IL size = 90, hash=0xacad9ecf FullOpts Compiling 400 System.RuntimeType::get_FullName, IL size = 8, hash=0x012abf74 FullOpts Compiling 401 System.RuntimeType::GetCachedName, IL size = 13, hash=0xa0332aa3 FullOpts Compiling 402 RuntimeTypeCache::GetName, IL size = 101, hash=0x0ce6102c FullOpts Compiling 403 System.RuntimeType::get_IsGenericTypeDefinition, IL size = 7, hash=0x581f9616 FullOpts Compiling 404 RuntimeTypeCache::ConstructName, IL size = 32, hash=0xd718c429 FullOpts Compiling 405 System.RuntimeTypeHandle::ConstructName, IL size = 31, hash=0xdb9fb742 FullOpts Compiling 406 System.String::Equals, IL size = 171, hash=0xf9b6c298 FullOpts Compiling 407 System.RuntimeType::get_Name, IL size = 8, hash=0x31c1dd67 FullOpts Compiling 408 System.Reflection.MdFieldInfo::GetRawConstantValue, IL size = 8, hash=0x31307e46 FullOpts Compiling 409 System.Reflection.MdFieldInfo::GetValue, IL size = 56, hash=0x4a4ca1d2 FullOpts Compiling 410 System.Reflection.MdConstant::GetValue, IL size = 618, hash=0x8002a434 FullOpts Compiling 411 System.DBNull::.cctor, IL size = 11, hash=0x9b2f598f Tier-0 switched MinOpts Compiling 412 System.DBNull::.ctor, IL size = 7, hash=0xd42e9890 FullOpts Compiling 413 System.Reflection.MdFieldInfo::get_Name, IL size = 59, hash=0xd807b84f FullOpts Compiling 414 System.MdUtf8String::ToString, IL size = 28, hash=0xd94af060 FullOpts Compiling 415 System.Text.Encoding::GetString, IL size = 25, hash=0x41b91a82 FullOpts Compiling 416 System.String::CreateStringFromEncoding, IL size = 109, hash=0x29eea142 FullOpts Compiling 417 System.Text.UTF8Encoding::GetCharCount, IL size = 36, hash=0x3ed6c0d7 FullOpts Compiling 418 System.Text.Unicode.Utf8Utility::GetPointerToFirstInvalidByte, IL size = 1490, hash=0x54d365fa FullOpts Compiling 419 System.Text.ASCIIUtility::GetIndexOfFirstNonAsciiByte_Intrinsified, IL size = 775, hash=0x9a95b5e9 FullOpts Compiling 420 System.Text.UTF8Encoding::GetChars, IL size = 64, hash=0x0213dfde FullOpts Compiling 421 System.Text.Unicode.Utf8Utility::TranscodeToUtf16, IL size = 1907, hash=0xb11218c1 FullOpts Compiling 422 System.Text.ASCIIUtility::WidenAsciiToUtf16, IL size = 405, hash=0xf1f7a876 FullOpts Compiling 423 System.Diagnostics.Tracing.ManifestBuilder::AddKeyword, IL size = 250, hash=0x6c70d157 FullOpts Compiling 424 System.Collections.Generic.Dictionary`2[UInt64,__Canon][System.UInt64,System.__Canon]::.ctor, IL size = 102, hash=0x81347e74 FullOpts Compiling 425 System.Collections.Generic.Dictionary`2[UInt64,__Canon][System.UInt64,System.__Canon]::TryInsert, IL size = 739, hash=0x7206ee98 FullOpts Compiling 426 System.Collections.Generic.Dictionary`2[UInt64,__Canon][System.UInt64,System.__Canon]::Initialize, IL size = 56, hash=0x85d46f85 FullOpts Compiling 427 System.Collections.HashHelpers::ExpandPrime, IL size = 60, hash=0x1261d6a6 FullOpts Compiling 428 System.Collections.Generic.Dictionary`2[UInt64,__Canon][System.UInt64,System.__Canon]::Resize, IL size = 349, hash=0x3323d4d4 FullOpts Compiling 429 System.Array::Copy, IL size = 149, hash=0x4fdcba9a FullOpts Compiling 430 System.Text.ASCIIUtility::WidenAsciiToUtf16_Intrinsified, IL size = 407, hash=0xdbeca31b FullOpts Compiling 431 System.RuntimeType::CacheEquals, IL size = 30, hash=0x460f7a74 FullOpts Compiling 432 System.Diagnostics.Tracing.ManifestBuilder::AddTask, IL size = 138, hash=0xb176189a FullOpts Compiling 433 System.Collections.Generic.Dictionary`2[Int32,__Canon][System.Int32,System.__Canon]::Resize, IL size = 349, hash=0xb6ccb854 FullOpts Compiling 434 System.String::Equals, IL size = 42, hash=0xd5f72f29 FullOpts Compiling 435 System.Diagnostics.Tracing.ManifestBuilder::AddOpcode, IL size = 112, hash=0xfdce2865 FullOpts Compiling 436 System.Reflection.RuntimeMethodInfo::GetParameters, IL size = 34, hash=0xeca8d8d8 FullOpts Compiling 437 System.Reflection.RuntimeParameterInfo::.ctor, IL size = 166, hash=0xd49d5781 FullOpts Compiling 438 System.Reflection.MetadataImport::.cctor, IL size = 18, hash=0x180a61cb Tier-0 switched MinOpts Compiling 439 System.Reflection.MetadataImport::.ctor, IL size = 15, hash=0x4e68248c FullOpts Compiling 440 System.Reflection.RuntimeMethodInfo::get_Module, IL size = 7, hash=0xafd3881c FullOpts Compiling 441 System.Reflection.RuntimeMethodInfo::get_MemberType, IL size = 2, hash=0xa69e24e5 FullOpts Compiling 442 System.Reflection.RuntimeMethodInfo::GetCustomAttributes, IL size = 66, hash=0x27650834 FullOpts Compiling 443 System.Reflection.CustomAttribute::GetCustomAttributes, IL size = 336, hash=0x9cd08bb5 FullOpts Compiling 444 System.Reflection.PseudoCustomAttribute::GetCustomAttributes, IL size = 158, hash=0x5982d38b FullOpts Compiling 445 System.ModuleHandle::ResolveMethodHandle, IL size = 113, hash=0x64783133 FullOpts Compiling 446 System.RuntimeTypeHandle::CopyRuntimeTypeHandles, IL size = 57, hash=0x1856e0f4 FullOpts Compiling 447 System.RuntimeMethodInfoStub::System.IRuntimeMethodInfo.get_Value, IL size = 7, hash=0x8bb4e867 FullOpts Compiling 448 System.Reflection.CustomAttribute::CreateCaObject, IL size = 46, hash=0x15038ae6 FullOpts Compiling 449 System.Diagnostics.Tracing.EventAttribute::.ctor, IL size = 21, hash=0x5162689e FullOpts Compiling 450 System.Diagnostics.Tracing.EventAttribute::set_Version, IL size = 8, hash=0x7c568f31 FullOpts Compiling 451 System.Diagnostics.Tracing.EventAttribute::set_Level, IL size = 8, hash=0x33eebad1 FullOpts Compiling 452 System.Diagnostics.Tracing.EventAttribute::set_Keywords, IL size = 8, hash=0x5ab14834 FullOpts Compiling 453 System.Reflection.RuntimeMethodInfo::get_Name, IL size = 26, hash=0xc9a50ba7 FullOpts Compiling 454 System.SpanHelpers::LastIndexOf, IL size = 354, hash=0x21b876c6 FullOpts Compiling 455 System.Diagnostics.Tracing.EventSource::GetOpcodeWithDefault, IL size = 40, hash=0xd35407f1 FullOpts Compiling 456 System.String::EndsWith, IL size = 247, hash=0x5149d1b7 FullOpts Compiling 457 System.Diagnostics.Tracing.EventSource::RemoveFirstArgIfRelatedActivityId, IL size = 88, hash=0xb1a0a262 FullOpts Compiling 458 System.Reflection.RuntimeParameterInfo::get_ParameterType, IL size = 96, hash=0x79ae6bea FullOpts Compiling 459 System.Diagnostics.Tracing.ManifestBuilder::AppendKeywords, IL size = 170, hash=0x3cbc46eb FullOpts Compiling 460 System.Collections.Generic.Dictionary`2[UInt64,__Canon][System.UInt64,System.__Canon]::FindValue, IL size = 410, hash=0x6a814cc3 FullOpts Compiling 461 System.Reflection.RuntimeParameterInfo::get_Name, IL size = 78, hash=0x989ec131 FullOpts Compiling 462 System.Diagnostics.Tracing.EventSource::DebugCheckEvent, IL size = 441, hash=0x3e2a48d1 FullOpts Compiling 463 System.Diagnostics.Tracing.EventSource::GetHelperCallFirstArg, IL size = 506, hash=0xdfb967d2 FullOpts Compiling 464 System.Reflection.RuntimeMethodInfo::GetMethodBody, IL size = 25, hash=0x221dbd83 FullOpts Compiling 465 System.Reflection.RuntimeMethodBody::GetILAsByteArray, IL size = 7, hash=0x92fa115c FullOpts Compiling 466 System.Diagnostics.Tracing.EventSource::AddEventDescriptor, IL size = 375, hash=0x4d62da98 FullOpts Compiling 467 System.Diagnostics.Tracing.EventDescriptor::.ctor, IL size = 195, hash=0x0f746a28 FullOpts Compiling 468 System.Text.StringBuilder::Append, IL size = 152, hash=0xa2dd3fee FullOpts Compiling 469 EmptyArray`1[CustomAttributeRecord][System.Reflection.CustomAttributeRecord]::.cctor, IL size = 12, hash=0x1e7096c6 Tier-0 switched MinOpts Compiling 470 RuntimeTypeCache::GetEmptyArray, IL size = 37, hash=0xd4ee8292 FullOpts Compiling 471 System.Reflection.RuntimeMethodInfo::get_ReturnType, IL size = 12, hash=0xeb9232df FullOpts Compiling 472 System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]::Resize, IL size = 349, hash=0xfad26654 FullOpts Compiling 473 System.String::Substring, IL size = 124, hash=0xc7e4f9e5 FullOpts Compiling 474 System.String::InternalSubString, IL size = 102, hash=0x20748982 FullOpts Compiling 475 System.String::Compare, IL size = 74, hash=0x2d8f07df FullOpts Compiling 476 System.Globalization.CultureInfo::get_CurrentCulture, IL size = 37, hash=0xba298cc8 FullOpts Compiling 477 System.Globalization.CultureInfo::InitializeUserDefaultCulture, IL size = 25, hash=0x5cb43c5a FullOpts Compiling 478 System.Globalization.CultureInfo::GetUserDefaultCulture, IL size = 35, hash=0x039c6204 FullOpts Compiling 479 System.Globalization.CultureInfo::GetCultureByName, IL size = 27, hash=0xf8707c7c FullOpts Compiling 480 System.Globalization.CultureInfo::.ctor, IL size = 100, hash=0x37cb6a18 FullOpts Compiling 481 System.Globalization.CultureData::GetCultureData, IL size = 224, hash=0xc3469692 FullOpts Compiling 482 Settings::.cctor, IL size = 21, hash=0xa0056a3c Tier-0 switched MinOpts Compiling 483 System.Globalization.TextInfo::ToLowerAsciiInvariant, IL size = 202, hash=0x7383792e FullOpts Compiling 484 System.Globalization.CultureData::CreateCultureData, IL size = 180, hash=0x868941e0 FullOpts Compiling 485 System.Globalization.CultureData::InitCultureDataCore, IL size = 253, hash=0x144e21b7 FullOpts Compiling 486 System.Globalization.CultureData::InitIcuCultureDataCore, IL size = 336, hash=0x24a685c8 FullOpts Compiling 487 System.Globalization.CultureData::IsValidCultureName, IL size = 163, hash=0xd142fea9 FullOpts Compiling 488 System.Globalization.CultureData::GetLocaleName, IL size = 38, hash=0xc29d82d7 FullOpts Compiling 489 ILStubClass::IL_STUB_PInvoke, IL size = 78, hash=0xad9909a3 FullOpts Compiling 490 System.String::IndexOf, IL size = 128, hash=0x237b69a3 FullOpts Compiling 491 System.Globalization.Ordinal::IndexOf, IL size = 98, hash=0xf3e366dd FullOpts Compiling 492 System.Globalization.CultureData::get_LCID, IL size = 78, hash=0x6d68cc9c FullOpts Compiling 493 System.Globalization.CultureData::IcuLocaleNameToLCID, IL size = 46, hash=0x1f1ab4bc FullOpts Compiling 494 System.Globalization.IcuLocaleData::GetLocaleDataNumericPart, IL size = 401, hash=0x5523e9e3 FullOpts Compiling 495 System.Globalization.IcuLocaleData::SearchCultureName, IL size = 190, hash=0x09fae50b FullOpts Compiling 496 System.Globalization.IcuLocaleData::GetCultureName, IL size = 66, hash=0x16ec3071 FullOpts Compiling 497 System.SpanHelpers::SequenceCompareTo, IL size = 692, hash=0xbda601aa FullOpts Compiling 498 System.Globalization.CultureData::get_TwoLetterISOCountryName, IL size = 28, hash=0x6bf4d63b FullOpts Compiling 499 System.Globalization.CultureData::GetLocaleInfoCore, IL size = 32, hash=0xde0596c2 FullOpts Compiling 500 System.Globalization.CultureData::IcuGetLocaleInfo, IL size = 59, hash=0x1ea0fea6 FullOpts Compiling 501 System.Globalization.CultureData::IcuGetLocaleInfo, IL size = 102, hash=0xe34d1754 FullOpts Compiling 502 ILStubClass::IL_STUB_PInvoke, IL size = 88, hash=0x632a7e1c FullOpts Compiling 503 System.Globalization.CultureData::InitUserOverride, IL size = 48, hash=0x9745a08f FullOpts Compiling 504 System.Globalization.CultureInfo::GetCultureInfo, IL size = 159, hash=0x14d8934e FullOpts Compiling 505 System.Globalization.CultureInfo::get_CachedCulturesByName, IL size = 37, hash=0xd3124187 FullOpts Compiling 506 System.Globalization.CompareInfo::Compare, IL size = 295, hash=0xe1a461b6 FullOpts Compiling 507 System.Globalization.CompareInfo::Compare, IL size = 152, hash=0xcc1e1476 FullOpts Compiling 508 System.Globalization.CompareInfo::IcuCompareString, IL size = 90, hash=0x1ea6f83c FullOpts Compiling 509 System.Diagnostics.Tracing.ManifestBuilder::GetOpcodeName, IL size = 174, hash=0x339d87f1 FullOpts Compiling 510 System.Diagnostics.Tracing.EventAttribute::set_Message, IL size = 8, hash=0x8b73fb01 FullOpts Compiling 511 System.Diagnostics.Tracing.EventAttribute::set_Task, IL size = 8, hash=0xb138b22a FullOpts Compiling 512 System.Diagnostics.Tracing.EventAttribute::set_Opcode, IL size = 15, hash=0x93529415 FullOpts Compiling 513 OrdinalComparer::Equals, IL size = 8, hash=0x8b8e5103 FullOpts Compiling 514 System.Diagnostics.Tracing.ManifestBuilder::TranslateToManifestConvention, IL size = 452, hash=0x170d8c8e FullOpts Compiling 515 System.Text.StringBuilder::Append, IL size = 127, hash=0x0dce03a8 FullOpts Compiling 516 System.Diagnostics.Tracing.ManifestBuilder::TranslateIndexToManifestConvention, IL size = 71, hash=0x5538d850 FullOpts Compiling 517 System.Diagnostics.Tracing.ManifestBuilder::.cctor, IL size = 76, hash=0x4a42c32c Tier-0 switched MinOpts Compiling 518 System.Text.StringBuilder::ToString, IL size = 138, hash=0x5d8a9cc4 FullOpts Compiling 519 System.RuntimeType::GetEnumUnderlyingType, IL size = 31, hash=0x7bb6bd24 FullOpts Compiling 520 System.Enum::GetUnderlyingType, IL size = 27, hash=0x1176428f FullOpts Compiling 521 System.Diagnostics.Tracing.EventSource::IsCustomAttributeDefinedHelper, IL size = 100, hash=0x4967726e FullOpts Compiling 522 System.Reflection.RuntimeMethodInfo::IsDefined, IL size = 66, hash=0x0f188673 FullOpts Compiling 523 System.Reflection.CustomAttribute::IsDefined, IL size = 103, hash=0x7d5318d2 FullOpts Compiling 524 System.Reflection.PseudoCustomAttribute::IsDefined, IL size = 132, hash=0xb7e84168 FullOpts Compiling 525 System.Reflection.CustomAttribute::IsCustomAttributeDefined, IL size = 248, hash=0xeca02bd6 FullOpts Compiling 526 System.Diagnostics.Tracing.NameInfo::ReserveEventIDsBelow, IL size = 44, hash=0xb19c4cbe FullOpts Compiling 527 System.Diagnostics.Tracing.NameInfo::.cctor, IL size = 11, hash=0x519b06cb Tier-0 switched MinOpts Compiling 528 System.Diagnostics.Tracing.EventSource::TrimEventDescriptors, IL size = 68, hash=0x95a5b370 FullOpts Compiling 529 System.Diagnostics.Tracing.ManifestBuilder::GetChannelData, IL size = 155, hash=0x7342de81 FullOpts Compiling 530 EmptyArray`1[UInt64][System.UInt64]::.cctor, IL size = 12, hash=0x81ac9f6f Tier-0 switched MinOpts Compiling 531 System.Diagnostics.Tracing.ManifestBuilder::CreateManifest, IL size = 19, hash=0xb17955a1 FullOpts Compiling 532 System.Diagnostics.Tracing.ManifestBuilder::CreateManifestString, IL size = 2250, hash=0xecf5ab6d FullOpts Compiling 533 System.Collections.Generic.Dictionary`2[Int32,__Canon][System.Int32,System.__Canon]::get_Keys, IL size = 26, hash=0xf4f37874 FullOpts Compiling 534 System.Collections.Generic.List`1[Int32][System.Int32]::.ctor, IL size = 134, hash=0xe6f3819c FullOpts Compiling 535 System.Runtime.CompilerServices.CastHelpers::IsInstanceOfInterface, IL size = 152, hash=0x5d0d2bf7 FullOpts Compiling 536 KeyCollection[Int32,__Canon][System.Int32,System.__Canon]::get_Count, IL size = 12, hash=0x98078020 FullOpts Compiling 537 KeyCollection[Int32,__Canon][System.Int32,System.__Canon]::CopyTo, IL size = 124, hash=0x9be7569d FullOpts Compiling 538 System.Collections.Generic.List`1[Int32][System.Int32]::Sort, IL size = 73, hash=0xc1810e19 FullOpts Compiling 539 System.Array::Sort, IL size = 78, hash=0x4b836743 FullOpts Compiling 540 System.Collections.Generic.ArraySortHelper`1[Int32][System.Int32]::.cctor, IL size = 11, hash=0x22d124b9 Tier-0 switched MinOpts Compiling 541 System.Collections.Generic.ArraySortHelper`1[Int32][System.Int32]::CreateArraySortHelper, IL size = 78, hash=0xb60c5833 FullOpts Compiling 542 System.Collections.Generic.GenericArraySortHelper`1[Int32][System.Int32]::.ctor, IL size = 7, hash=0x4bbe5137 FullOpts Compiling 543 System.Runtime.CompilerServices.CastHelpers::ChkCastInterface, IL size = 140, hash=0xf10595e8 FullOpts Compiling 544 System.Collections.Generic.GenericArraySortHelper`1[Int32][System.Int32]::Sort, IL size = 212, hash=0x9daad181 FullOpts Compiling 545 System.Collections.Generic.GenericArraySortHelper`1[Int32][System.Int32]::IntroSort, IL size = 221, hash=0x286ac286 FullOpts Compiling 546 System.Collections.Generic.GenericArraySortHelper`1[Int32][System.Int32]::PickPivotAndPartition, IL size = 329, hash=0xe6c2ade8 FullOpts Compiling 547 System.Collections.Generic.GenericArraySortHelper`1[Int32][System.Int32]::InsertionSort, IL size = 141, hash=0xd93ce828 FullOpts Compiling 548 System.Collections.Generic.Dictionary`2[Int32,__Canon][System.Int32,System.__Canon]::get_Item, IL size = 39, hash=0xefd604a4 FullOpts Compiling 549 System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]::get_Values, IL size = 26, hash=0x3bfd21ab FullOpts Compiling 550 Enumerator[__Canon,__Canon][System.__Canon,System.__Canon]::MoveNext, IL size = 135, hash=0x2407af6c FullOpts Compiling 551 System.RuntimeType::IsDefined, IL size = 60, hash=0x141b04b3 FullOpts Compiling 552 System.Reflection.CustomAttribute::IsDefined, IL size = 114, hash=0x90a55792 FullOpts Compiling 553 System.Reflection.PseudoCustomAttribute::IsDefined, IL size = 132, hash=0x016ef028 FullOpts Compiling 554 MemberInfoCache`1[__Canon][System.__Canon]::PopulateRtFields, IL size = 275, hash=0x50c420e7 FullOpts Compiling 555 System.Convert::ToInt64, IL size = 19, hash=0x50537686 FullOpts Compiling 556 System.Convert::.cctor, IL size = 455, hash=0x10055505 Tier-0 switched MinOpts Compiling 557 System.Diagnostics.Debug::Assert, IL size = 13, hash=0x11ad1e20 FullOpts Compiling 558 System.UInt32::System.IConvertible.ToInt64, IL size = 8, hash=0xc268664d FullOpts Compiling 559 System.Number::g__TryFormatUInt64Slow|45_0, IL size = 165, hash=0x5e8ff254 FullOpts Compiling 560 System.Number::ParseFormatSpecifier, IL size = 274, hash=0xfebf4a01 FullOpts Compiling 561 System.Number::TryInt64ToHexStr, IL size = 127, hash=0x03d8752b FullOpts Compiling 562 System.Number::Int32ToHexChars, IL size = 47, hash=0x4d4ecfe4 FullOpts Compiling 563 System.Text.StringBuilder::Append, IL size = 40, hash=0x02af3bd8 FullOpts Compiling 564 System.Collections.Generic.Dictionary`2[UInt64,__Canon][System.UInt64,System.__Canon]::get_Keys, IL size = 26, hash=0x6a63a662 FullOpts Compiling 565 System.Collections.Generic.List`1[UInt64][System.UInt64]::.ctor, IL size = 134, hash=0xce51716a FullOpts Compiling 566 KeyCollection[UInt64,__Canon][System.UInt64,System.__Canon]::get_Count, IL size = 12, hash=0x04ac1ea0 FullOpts Compiling 567 KeyCollection[UInt64,__Canon][System.UInt64,System.__Canon]::CopyTo, IL size = 124, hash=0xa285242b FullOpts Compiling 568 System.Collections.Generic.List`1[UInt64][System.UInt64]::Sort, IL size = 73, hash=0xe192260f FullOpts Compiling 569 System.Array::Sort, IL size = 78, hash=0xd68d2d23 FullOpts Compiling 570 System.Collections.Generic.ArraySortHelper`1[UInt64][System.UInt64]::.cctor, IL size = 11, hash=0x8676a419 Tier-0 switched MinOpts Compiling 571 System.Collections.Generic.ArraySortHelper`1[UInt64][System.UInt64]::CreateArraySortHelper, IL size = 78, hash=0x64e20985 FullOpts Compiling 572 System.Collections.Generic.GenericArraySortHelper`1[UInt64][System.UInt64]::.ctor, IL size = 7, hash=0x7f9f5e97 FullOpts Compiling 573 System.Collections.Generic.GenericArraySortHelper`1[UInt64][System.UInt64]::Sort, IL size = 212, hash=0xd4605161 FullOpts Compiling 574 System.Collections.Generic.GenericArraySortHelper`1[UInt64][System.UInt64]::IntroSort, IL size = 221, hash=0x55723bd0 FullOpts Compiling 575 System.Collections.Generic.GenericArraySortHelper`1[UInt64][System.UInt64]::PickPivotAndPartition, IL size = 329, hash=0x7c16703e FullOpts Compiling 576 System.Collections.Generic.GenericArraySortHelper`1[UInt64][System.UInt64]::InsertionSort, IL size = 141, hash=0xd68d981e FullOpts Compiling 577 System.Collections.Generic.Dictionary`2[UInt64,__Canon][System.UInt64,System.__Canon]::get_Item, IL size = 39, hash=0x2d5508fd FullOpts Compiling 578 System.Text.StringBuilder::Append, IL size = 28, hash=0x347c1d9a FullOpts Compiling 579 System.Text.StringBuilder::AppendCore, IL size = 163, hash=0x4611a801 FullOpts Compiling 580 System.Text.StringBuilder::CopyTo, IL size = 196, hash=0x044aacf8 FullOpts Compiling 581 System.Collections.Generic.Dictionary`2[__Canon,__Canon][System.__Canon,System.__Canon]::get_Keys, IL size = 26, hash=0x99c203ab FullOpts Compiling 582 KeyCollection[__Canon,__Canon][System.__Canon,System.__Canon]::CopyTo, IL size = 124, hash=0xb1eaaec2 FullOpts Compiling 583 System.Array::Sort, IL size = 78, hash=0x441675e3 FullOpts Compiling 584 System.Collections.Generic.ArraySortHelper`1[__Canon][System.__Canon]::get_Default, IL size = 6, hash=0x76ade78f FullOpts Compiling 585 System.Collections.Generic.ArraySortHelper`1[__Canon][System.__Canon]::.cctor, IL size = 11, hash=0xdb021279 Tier-0 switched MinOpts Compiling 586 System.Collections.Generic.ArraySortHelper`1[__Canon][System.__Canon]::CreateArraySortHelper, IL size = 78, hash=0x9e3288cc FullOpts Compiling 587 System.Collections.Generic.GenericArraySortHelper`1[__Canon][System.__Canon]::.ctor, IL size = 7, hash=0x33615cf7 FullOpts Compiling 588 System.Collections.Generic.GenericArraySortHelper`1[__Canon][System.__Canon]::Sort, IL size = 212, hash=0xf862bc81 FullOpts Compiling 589 System.Collections.Generic.GenericArraySortHelper`1[__Canon][System.__Canon]::IntroSort, IL size = 221, hash=0x85649459 FullOpts Compiling 590 System.Span`1[__Canon][System.__Canon]::Slice, IL size = 44, hash=0x65b71684 FullOpts Compiling 591 System.Collections.Generic.GenericArraySortHelper`1[__Canon][System.__Canon]::PickPivotAndPartition, IL size = 329, hash=0x05c68df7 FullOpts Compiling 592 System.String::CompareTo, IL size = 9, hash=0xcf0c3357 FullOpts Compiling 593 System.String::Compare, IL size = 191, hash=0xab39783d FullOpts Compiling 594 System.Globalization.CompareInfo::Compare, IL size = 48, hash=0x7e00a336 FullOpts Compiling 595 System.Collections.Generic.GenericArraySortHelper`1[__Canon][System.__Canon]::InsertionSort, IL size = 141, hash=0xc32beff7 FullOpts Compiling 596 System.Globalization.CultureInfo::get_CurrentUICulture, IL size = 26, hash=0x520ec434 FullOpts Compiling 597 System.Globalization.CultureInfo::get_UserDefaultUICulture, IL size = 17, hash=0x69a96707 FullOpts Compiling 598 System.Globalization.CultureInfo::InitializeUserDefaultUICulture, IL size = 25, hash=0x508f10a6 FullOpts Compiling 599 System.Globalization.CultureInfo::GetUserDefaultUICulture, IL size = 138, hash=0xae39af78 FullOpts Compiling 600 System.Span`1[Char][System.Char]::ToString, IL size = 97, hash=0x5b2fcdf5 FullOpts Compiling 601 System.String::Ctor, IL size = 55, hash=0xcb62d7bc FullOpts Compiling 602 System.Globalization.CultureInfo::get_Name, IL size = 40, hash=0x70ed6baa FullOpts Compiling 603 System.Diagnostics.Tracing.ManifestBuilder::GetLocalizedMessage, IL size = 95, hash=0x1535a1a3 FullOpts Compiling 604 UTF8EncodingSealed::GetBytes, IL size = 29, hash=0x84a94ba8 FullOpts Compiling 605 System.Text.Encoding::GetBytes, IL size = 62, hash=0xa3fd87d5 FullOpts Compiling 606 System.Text.ASCIIUtility::NarrowUtf16ToAscii_Sse2, IL size = 624, hash=0xd994f4d8 FullOpts Compiling 607 System.Diagnostics.Tracing.EventSource::DefineEventPipeEvents, IL size = 340, hash=0x303f02b2 FullOpts Compiling 608 System.Diagnostics.Tracing.EventPipeMetadataGenerator::.cctor, IL size = 11, hash=0x36667c3c Tier-0 switched MinOpts Compiling 609 System.Diagnostics.Tracing.EventPipeMetadataGenerator::.ctor, IL size = 7, hash=0xaefad123 FullOpts Compiling 610 System.Diagnostics.Tracing.EventPipeMetadataGenerator::GenerateEventMetadata, IL size = 149, hash=0xe5b53631 FullOpts Compiling 611 System.Diagnostics.Tracing.EventParameterInfo::GetTypeInfoFromType, IL size = 410, hash=0xf4ed1dc1 FullOpts Compiling 612 System.Diagnostics.Tracing.ScalarTypeInfo::UInt32, IL size = 32, hash=0x917ba66f FullOpts Compiling 613 System.Diagnostics.Tracing.TraceLoggingTypeInfo::.ctor, IL size = 72, hash=0xa7ad5fba FullOpts Compiling 614 System.Diagnostics.Tracing.PropertyValue::GetFactory, IL size = 982, hash=0x20911406 FullOpts Compiling 615 <>c::.cctor, IL size = 11, hash=0x7a92f338 Tier-0 switched MinOpts Compiling 616 <>c::.ctor, IL size = 7, hash=0xcce2e927 FullOpts Compiling 617 System.Diagnostics.Tracing.ScalarTypeInfo::UInt16, IL size = 32, hash=0x5b623d29 FullOpts Compiling 618 System.Diagnostics.Tracing.ScalarTypeInfo::UInt64, IL size = 33, hash=0x5a14c28c FullOpts Compiling 619 System.Diagnostics.Tracing.EventPipeMetadataGenerator::GenerateMetadata, IL size = 673, hash=0x0bf0113e FullOpts Compiling 620 System.Diagnostics.Tracing.EventParameterInfo::GetMetadataLength, IL size = 122, hash=0x628dc48b FullOpts Compiling 621 System.Diagnostics.Tracing.EventParameterInfo::GetTypeCodeExtended, IL size = 82, hash=0x4a5ba230 FullOpts Compiling 622 System.Diagnostics.Tracing.EventParameterInfo::GenerateMetadata, IL size = 191, hash=0x1974d673 FullOpts Compiling 623 System.Diagnostics.Tracing.EventPipeMetadataGenerator::WriteToBuffer, IL size = 46, hash=0xe5e62f51 FullOpts Compiling 624 System.Diagnostics.Tracing.EventPipeMetadataGenerator::WriteToBuffer, IL size = 51, hash=0x2522a457 FullOpts Compiling 625 System.Diagnostics.Tracing.EventPipeEventProvider::System.Diagnostics.Tracing.IEventProvider.DefineEventHandle, IL size = 24, hash=0xb5ed90c8 FullOpts Compiling 626 System.Diagnostics.Tracing.ScalarTypeInfo::IntPtr, IL size = 36, hash=0xf6cb144d FullOpts Compiling 627 System.Diagnostics.Tracing.Statics::.cctor, IL size = 46, hash=0x62823d69 Tier-0 switched MinOpts Compiling 628 System.IntPtr::get_Size, IL size = 6, hash=0x8c383a95 FullOpts Compiling 629 System.Diagnostics.Tracing.ScalarTypeInfo::Byte, IL size = 32, hash=0xaf8addc2 FullOpts Compiling 630 System.Diagnostics.Tracing.ScalarTypeInfo::Double, IL size = 33, hash=0x8d5fcbbd FullOpts Compiling 631 System.Diagnostics.Tracing.ScalarTypeInfo::Boolean, IL size = 36, hash=0x0f70d6ac FullOpts Compiling 632 System.Diagnostics.Tracing.ScalarTypeInfo::Guid, IL size = 33, hash=0xa40900d7 FullOpts Compiling 633 System.Diagnostics.Tracing.ScalarTypeInfo::Int32, IL size = 32, hash=0xf0046c5a FullOpts Compiling 634 System.Diagnostics.Tracing.EventSource::GetDispatcher, IL size = 34, hash=0x0299bb1a FullOpts Compiling 635 System.Diagnostics.Tracing.EventSource::IsEnabledByDefault, IL size = 125, hash=0x9ae08d3b FullOpts Compiling 636 System.Diagnostics.Tracing.EventSource::IsEnabledCommon, IL size = 85, hash=0x374b2333 FullOpts Compiling 637 System.Diagnostics.Tracing.EventSource::EnableEventForDispatcher, IL size = 178, hash=0x0d9ab69f FullOpts Compiling 638 System.Diagnostics.Tracing.EventSource::SendManifest, IL size = 427, hash=0xd535f75c FullOpts Compiling 639 System.Diagnostics.Tracing.EventProvider::WriteEvent, IL size = 100, hash=0x13b2d8c4 FullOpts Compiling 640 System.Diagnostics.Tracing.EtwEventProvider::System.Diagnostics.Tracing.IEventProvider.EventWriteTransfer, IL size = 42, hash=0x3cdee063 FullOpts Compiling 641 Advapi32::EventWriteTransfer, IL size = 48, hash=0x3c1fb2f2 FullOpts Compiling 642 ILStubClass::IL_STUB_PInvoke, IL size = 82, hash=0x2a9c778c FullOpts Compiling 643 System.Diagnostics.Tracing.EventSource::OnEventCommand, IL size = 1, hash=0xe0ba2b99 FullOpts Compiling 644 System.GC::KeepAlive, IL size = 1, hash=0x32162803 FullOpts Compiling 645 Runtime_53189::Main, IL size = 66, hash=0xefa2a3c9 MinOpts Compiling 646 System.Console::WriteLine, IL size = 12, hash=0x450bf92f FullOpts Compiling 647 System.Console::get_Out, IL size = 20, hash=0x9e38c00e FullOpts Compiling 648 System.Console::.cctor, IL size = 11, hash=0x701237e5 Tier-0 switched MinOpts Compiling 649 System.Console::g__EnsureInitialized|25_0, IL size = 63, hash=0x062f85e9 FullOpts Compiling 650 System.ConsolePal::OpenStandardOutput, IL size = 34, hash=0x173bd4aa FullOpts Compiling 651 System.Console::get_OutputEncoding, IL size = 72, hash=0x2b0acc16 FullOpts Compiling 652 ILStubClass::IL_STUB_PInvoke, IL size = 26, hash=0xa66071d9 FullOpts Compiling 653 System.Runtime.InteropServices.NativeLibrary::LoadLibraryCallbackStub, IL size = 63, hash=0x64f221e1 FullOpts Compiling 654 System.Text.EncodingHelper::GetSupportedConsoleEncoding, IL size = 53, hash=0xf0f3bf9d FullOpts Compiling 655 System.Text.Encoding::GetEncoding, IL size = 340, hash=0x371368c2 FullOpts Compiling 656 System.Text.EncodingProvider::GetEncodingFromProvider, IL size = 51, hash=0x68226714 FullOpts Compiling 657 System.Text.Encoding::FilterDisallowedEncodings, IL size = 29, hash=0xd29458e9 FullOpts Compiling 658 System.LocalAppContextSwitches::GetCachedSwitchValueInternal, IL size = 46, hash=0xa567d82e FullOpts Compiling 659 System.LocalAppContextSwitches::GetSwitchDefaultValue, IL size = 32, hash=0xed47d64c FullOpts Compiling 660 System.Text.Encoding::.cctor, IL size = 12, hash=0x758f83c2 Tier-0 switched MinOpts Compiling 661 System.Text.Encoding::get_CodePage, IL size = 7, hash=0xcadc7da7 FullOpts Compiling 662 System.Text.Encoding::.ctor, IL size = 42, hash=0x80087dee FullOpts Compiling 663 System.Text.Encoding::SetDefaultFallbacks, IL size = 23, hash=0x39a6cecf FullOpts Compiling 664 System.Text.EncoderReplacementFallback::.cctor, IL size = 11, hash=0xdb623367 Tier-0 switched MinOpts Compiling 665 System.Text.EncoderReplacementFallback::.ctor, IL size = 12, hash=0xa9d404f8 FullOpts Compiling 666 System.Text.DecoderReplacementFallback::.cctor, IL size = 11, hash=0x2345d84d Tier-0 switched MinOpts Compiling 667 System.Text.DecoderReplacementFallback::.ctor, IL size = 12, hash=0x617f1852 FullOpts Compiling 668 System.ConsolePal::GetStandardFile, IL size = 60, hash=0x4b8febbf FullOpts Compiling 669 System.ConsolePal::ConsoleHandleIsWritable, IL size = 26, hash=0x00c12774 FullOpts Compiling 670 ILStubClass::IL_STUB_PInvoke, IL size = 82, hash=0xe2ac144a FullOpts Compiling 671 System.IO.ConsoleStream::.ctor, IL size = 31, hash=0xa143e89d FullOpts Compiling 672 ILStubClass::IL_STUB_PInvoke, IL size = 43, hash=0xe59220d3 FullOpts Compiling 673 System.Console::CreateOutputWriter, IL size = 50, hash=0x8abcf282 FullOpts Compiling 674 System.IO.Stream::.cctor, IL size = 11, hash=0xfa7dc6e6 Tier-0 switched MinOpts Compiling 675 NullStream::.ctor, IL size = 7, hash=0x17580521 FullOpts Compiling 676 System.Text.EncodingExtensions::RemovePreamble, IL size = 25, hash=0x02a7f0d3 FullOpts Compiling 677 System.Text.Encoding::get_Preamble, IL size = 12, hash=0xa9632f36 FullOpts Compiling 678 System.Text.Encoding::GetPreamble, IL size = 6, hash=0x1c6dea32 FullOpts Compiling 679 EmptyArray`1[Byte][System.Byte]::.cctor, IL size = 12, hash=0x164f852f Tier-0 switched MinOpts Compiling 680 System.IO.StreamWriter::.ctor, IL size = 202, hash=0x2bb9be83 FullOpts Compiling 681 System.Threading.Tasks.Task::.cctor, IL size = 76, hash=0x4fb39e8f Tier-0 switched MinOpts Compiling 682 System.Threading.Tasks.TaskFactory::.ctor, IL size = 7, hash=0x80ad1304 FullOpts Compiling 683 System.Threading.Tasks.Task`1[VoidTaskResult][System.Threading.Tasks.VoidTaskResult]::.ctor, IL size = 21, hash=0x950a9a87 FullOpts Compiling 684 <>c::.cctor, IL size = 11, hash=0x7a92f338 Tier-0 switched MinOpts Compiling 685 <>c::.ctor, IL size = 7, hash=0xcce2e927 FullOpts Compiling 686 System.IO.TextWriter::.cctor, IL size = 26, hash=0xe17e9528 Tier-0 switched MinOpts Compiling 687 NullTextWriter::.ctor, IL size = 7, hash=0x5104bd6f FullOpts Compiling 688 System.String::ToCharArray, IL size = 52, hash=0x24037209 FullOpts Compiling 689 System.IO.ConsoleStream::get_CanWrite, IL size = 7, hash=0xfcc48126 FullOpts Compiling 690 System.Text.OSEncoding::GetEncoder, IL size = 7, hash=0xca46f351 FullOpts Compiling 691 System.IO.ConsoleStream::get_CanSeek, IL size = 2, hash=0xc1997943 FullOpts Compiling 692 System.IO.StreamWriter::Flush, IL size = 280, hash=0x92a045da FullOpts Compiling 693 System.Text.OSEncoding::GetMaxByteCount, IL size = 55, hash=0xc586f954 FullOpts Compiling 694 System.Text.Encoder::GetBytes, IL size = 44, hash=0xd25000b2 FullOpts Compiling 695 System.Text.OSEncoder::GetBytes, IL size = 211, hash=0x9ab43d3a FullOpts Compiling 696 WindowsConsoleStream::Flush, IL size = 31, hash=0x5cc617d2 FullOpts Compiling 697 System.IO.TextWriter::Synchronized, IL size = 31, hash=0xe7c0fc5b FullOpts Compiling 698 SyncTextWriter::WriteLine, IL size = 13, hash=0x4206a31a FullOpts Compiling 699 System.IO.StreamWriter::WriteLine, IL size = 20, hash=0x16d12d7f FullOpts Compiling 700 System.Text.OSEncoding::WideCharToMultiByte, IL size = 40, hash=0xf09c38bc FullOpts Compiling 701 WindowsConsoleStream::Write, IL size = 35, hash=0xb592f2b7 FullOpts Compiling 702 WindowsConsoleStream::WriteFileNative, IL size = 107, hash=0xd4357541 FullOpts failed to throw from conv.ovf.i1.un(-1.0) Compiling 703 System.AppContext::OnProcessExit, IL size = 43, hash=0x2830a401 FullOpts Compiling 704 System.Runtime.Loader.AssemblyLoadContext::OnProcessExit, IL size = 101, hash=0x3d0d0d95 FullOpts Compiling 705 System.Diagnostics.Tracing.EventListener::DisposeOnShutdown, IL size = 113, hash=0xa8d10229 FullOpts Compiling 706 System.Diagnostics.Tracing.EventSource::Dispose, IL size = 124, hash=0xcb8d4d71 FullOpts Compiling 707 System.Diagnostics.Tracing.EventProvider::Dispose, IL size = 90, hash=0x471417ad FullOpts Compiling 708 System.Diagnostics.Tracing.EtwEventProvider::System.Diagnostics.Tracing.IEventProvider.EventUnregister, IL size = 7, hash=0x2a36aabe FullOpts Compiling 709 System.Diagnostics.Tracing.EventPipeEventProvider::System.Diagnostics.Tracing.IEventProvider.EventUnregister, IL size = 13, hash=0x1f008fd8 FullOpts Expected: 100 Actual: 101 END EXECUTION - FAILED FAILED