Streamed scene with 146ms latency from Data/EntityScenes/46b433b264c69cbd39f04ad2e5d12be8.0.entities Streamed scene with 9ms latency from Data/EntityScenes/e1d9a388defac7049a631b0047b4278e.0.entities ****** START compiling Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this (MethodHash=08be6857) Generating code for Unix x64 OPTIONS: Tier-0 compilation (set COMPlus_TieredCompilation=0 to disable) OPTIONS: compCodeOpt = BLENDED_CODE OPTIONS: compDbgCode = false OPTIONS: compDbgInfo = true OPTIONS: compDbgEnC = false OPTIONS: compProcedureSplitting = false OPTIONS: compProcedureSplittingEH = false IL to import: IL_0000 72 bb 0f 00 70 ldstr 0x70000FBB IL_0005 04 ldarg.2 IL_0006 7b 25 01 00 0a ldfld 0xA000125 IL_000b 8c 11 00 00 01 box 0x1000011 IL_0010 04 ldarg.2 IL_0011 7b 26 01 00 0a ldfld 0xA000126 IL_0016 8c 18 00 00 01 box 0x1000018 IL_001b 28 27 01 00 0a call 0xA000127 IL_0020 28 6b 00 00 0a call 0xA00006B IL_0025 12 00 ldloca.s 0x0 IL_0027 fe 15 35 00 00 02 initobj 0x2000035 IL_002d 12 00 ldloca.s 0x0 IL_002f 02 ldarg.0 IL_0030 7b ab 00 00 04 ldfld 0x40000AB IL_0035 7d bb 00 00 04 stfld 0x40000BB IL_003a 12 00 ldloca.s 0x0 IL_003c 02 ldarg.0 IL_003d 7b ad 00 00 04 ldfld 0x40000AD IL_0042 7d ba 00 00 04 stfld 0x40000BA IL_0047 06 ldloc.0 IL_0048 04 ldarg.2 IL_0049 28 11 00 00 2b call 0x2B000011 IL_004e 2a ret **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 'this' passed in register rdi **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x79670b20 (Unity.Collections.NativeQueue`1[QueuedSendMessage]), ...) => passedInRegisters = false **** getSystemVAmd64PassStructInRegisterDescriptor(0x79670b20 (Unity.Collections.NativeQueue`1[QueuedSendMessage]), ...) => passedInRegisters = false **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 Arg #2 passed in register(s) firstEightByte: rsi, secondEightByte: rdx lvaGrabTemp returning 4 (V04 tmp0) (a long lifetime temp) called for OutgoingArgSpace. ; Initial local variable assignments ; ; V00 this byref this ; V01 arg1 struct ; V02 arg2 struct ; V03 loc0 struct ; V04 OutArgs lclBlk "OutgoingArgSpace" *************** In compInitDebuggingInfo() for Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this getVars() returned cVars = 0, extendOthers = true info.compVarScopesCount = 4 VarNum LVNum Name Beg End 0: 00h 00h V00 this 000h 04Fh 1: 01h 01h V01 arg1 000h 04Fh 2: 02h 02h V02 arg2 000h 04Fh 3: 03h 03h V03 loc0 000h 04Fh info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE ) *************** In fgFindBasicBlocks() for Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this Jump targets: none New Basic Block BB01 [0000] created. BB01 [000..04F) CLFLG_MINOPT set for method Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this IL Code Size,Instr 79, 23, Basic Block count 1, Local Variable Num,Ref count 5, 9 for method Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this IL Code Size,Instr 79, 23, Basic Block count 1, Local Variable Num,Ref count 5, 9 for method Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this OPTIONS: opts.MinOpts() == true Basic block list for 'Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Pre-import *************** Finishing PHASE Pre-import *************** Starting PHASE Importation *************** In impImport() for Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this impImportBlockPending for BB01 Importing BB01 (PC=000) of 'Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' [ 0] 0 (0x000) ldstr 70000FBB [ 1] 5 (0x005) ldarg.2 [ 2] 6 (0x006) ldfld 0A000125 [ 2] 11 (0x00b) box 01000011 Compiler::impImportAndPushBox -- handling BOX(value class) via inline allocate/copy sequence lvaGrabTemp returning 5 (V05 tmp1) called for Reusable Box Helper. STMT00000 (IL 0x000... ???) [000007] -A---------- * ASG ref [000006] D------N---- +--* LCL_VAR ref V05 tmp1 [000005] ------------ \--* ALLOCOBJ ref [000004] ------------ \--* CNS_INT(h) long 0x7f6678beb1c0 class STMT00001 (IL ???... ???) [000012] -A--G------- * ASG int [000011] -------N---- +--* IND int [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V05 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ----G------- \--* FIELD int Version [000002] ------------ \--* ADDR byref [000001] -------N---- \--* LCL_VAR struct V02 arg2 [ 2] 16 (0x010) ldarg.2 [ 3] 17 (0x011) ldfld 0A000126 [ 3] 22 (0x016) box 01000018 Compiler::impImportAndPushBox -- handling BOX(value class) via inline allocate/copy sequence lvaGrabTemp returning 6 (V06 tmp2) called for Reusable Box Helper. STMT00002 (IL ???... ???) [000021] -A---------- * ASG ref [000020] D------N---- +--* LCL_VAR ref V06 tmp2 [000019] ------------ \--* ALLOCOBJ ref [000018] ------------ \--* CNS_INT(h) long 0x7f6678c127f0 class STMT00003 (IL ???... ???) [000026] -A--G------- * ASG long [000025] -------N---- +--* IND long [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V06 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ----G------- \--* FIELD long JobGroup [000016] ------------ \--* ADDR byref [000015] -------N---- \--* LCL_VAR struct V02 arg2 [ 3] 27 (0x01b) call 0A000127 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 [ 1] 32 (0x020) call 0A00006B In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 STMT00004 (IL ???... ???) [000030] --C-G------- * CALL void UnityEngine.Debug.Log [000029] --C-G------- arg0 \--* CALL ref System.String.Format [000000] ------------ arg0 +--* CNS_STR ref [000014] ------------ arg1 +--* BOX ref [000013] ------------ | \--* LCL_VAR ref V05 tmp1 [000028] ------------ arg2 \--* BOX ref [000027] ------------ \--* LCL_VAR ref V06 tmp2 [ 0] 37 (0x025) ldloca.s 0 [ 1] 39 (0x027) initobj 02000035 STMT00005 (IL 0x025... ???) [000034] IA---------- * ASG struct (init) [000031] D------N---- +--* LCL_VAR struct V03 loc0 [000033] ------------ \--* CNS_INT int 0 [ 0] 45 (0x02d) ldloca.s 0 [ 1] 47 (0x02f) ldarg.0 [ 2] 48 (0x030) ldfld 040000AB [ 2] 53 (0x035) stfld 040000BB STMT00006 (IL 0x02D... ???) [000042] -A-XG------- * ASG struct (copy) [000041] ------------ +--* OBJ struct [000040] ------------ | \--* ADDR byref [000039] -------N---- | \--* FIELD struct Baselib [000036] ------------ | \--* ADDR byref [000035] -------N---- | \--* LCL_VAR struct V03 loc0 [000038] ---XG------- \--* FIELD struct m_Baselib [000037] ------------ \--* LCL_VAR byref V00 this [ 0] 58 (0x03a) ldloca.s 0 [ 1] 60 (0x03c) ldarg.0 [ 2] 61 (0x03d) ldfld 040000AD [ 2] 66 (0x042) stfld 040000BA STMT00007 (IL 0x03A... ???) [000050] -A-XG------- * ASG struct (copy) [000049] ------------ +--* BLK struct [000048] ------------ | \--* ADDR byref [000047] -------N---- | \--* FIELD struct Tx [000044] ------------ | \--* ADDR byref [000043] -------N---- | \--* LCL_VAR struct V03 loc0 [000046] ---XG------- \--* FIELD struct m_PayloadsTx [000045] ------------ \--* LCL_VAR byref V00 this [ 0] 71 (0x047) ldloc.0 [ 1] 72 (0x048) ldarg.2 [ 2] 73 (0x049) call 2B000011 In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16 Calling impNormStructVal on: [000052] ------------ * LCL_VAR struct V02 arg2 resulting tree: [000055] n----------- * OBJ struct [000054] ------------ \--* ADDR byref [000052] -------N---- \--* LCL_VAR struct V02 arg2 Calling impNormStructVal on: [000051] ------------ * LCL_VAR struct V03 loc0 resulting tree: [000057] n----------- * OBJ struct [000056] ------------ \--* ADDR byref [000051] -------N---- \--* LCL_VAR struct V03 loc0 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 lvaGrabTemp returning 7 (V07 tmp3) called for Return value temp for multireg return. STMT00008 (IL 0x047... ???) [000060] -AC-G------- * ASG struct (copy) [000058] D------N---- +--* LCL_VAR struct V07 tmp3 [000053] --C-G------- \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA [000057] n----------- arg0 +--* OBJ struct [000056] ------------ | \--* ADDR byref [000051] -------N---- | \--* LCL_VAR struct V03 loc0 [000055] n----------- arg1 \--* OBJ struct [000054] ------------ \--* ADDR byref [000052] -------N---- \--* LCL_VAR struct V02 arg2 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 [ 1] 78 (0x04e) ret impFixupStructReturnType: retyping [000061] -------N---- * LCL_VAR struct V07 tmp3 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 STMT00009 (IL ???... ???) [000062] ------------ * RETURN struct [000061] -------N---- \--* LCL_VAR struct V07 tmp3 *************** Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} ***** BB01 STMT00000 (IL 0x000...0x028) [000007] -A---------- * ASG ref [000006] D------N---- +--* LCL_VAR ref V05 tmp1 [000005] ------------ \--* ALLOCOBJ ref [000004] ------------ \--* CNS_INT(h) long 0x7f6678beb1c0 class ***** BB01 STMT00001 (IL ???... ???) [000012] -A--G------- * ASG int [000011] -------N---- +--* IND int [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V05 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ----G------- \--* FIELD int Version [000002] ------------ \--* ADDR byref [000001] -------N---- \--* LCL_VAR struct V02 arg2 ***** BB01 STMT00002 (IL ???... ???) [000021] -A---------- * ASG ref [000020] D------N---- +--* LCL_VAR ref V06 tmp2 [000019] ------------ \--* ALLOCOBJ ref [000018] ------------ \--* CNS_INT(h) long 0x7f6678c127f0 class ***** BB01 STMT00003 (IL ???... ???) [000026] -A--G------- * ASG long [000025] -------N---- +--* IND long [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V06 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ----G------- \--* FIELD long JobGroup [000016] ------------ \--* ADDR byref [000015] -------N---- \--* LCL_VAR struct V02 arg2 ***** BB01 STMT00004 (IL ???... ???) [000030] --C-G------- * CALL void UnityEngine.Debug.Log [000029] --C-G------- arg0 \--* CALL ref System.String.Format [000000] ------------ arg0 +--* CNS_STR ref [000014] ------------ arg1 +--* BOX ref [000013] ------------ | \--* LCL_VAR ref V05 tmp1 [000028] ------------ arg2 \--* BOX ref [000027] ------------ \--* LCL_VAR ref V06 tmp2 ***** BB01 STMT00005 (IL 0x025... ???) [000034] IA---------- * ASG struct (init) [000031] D------N---- +--* LCL_VAR struct V03 loc0 [000033] ------------ \--* CNS_INT int 0 ***** BB01 STMT00006 (IL 0x02D...0x035) [000042] -A-XG------- * ASG struct (copy) [000041] ------------ +--* OBJ struct [000040] ------------ | \--* ADDR byref [000039] -------N---- | \--* FIELD struct Baselib [000036] ------------ | \--* ADDR byref [000035] -------N---- | \--* LCL_VAR struct V03 loc0 [000038] ---XG------- \--* FIELD struct m_Baselib [000037] ------------ \--* LCL_VAR byref V00 this ***** BB01 STMT00007 (IL 0x03A...0x042) [000050] -A-XG------- * ASG struct (copy) [000049] ------------ +--* BLK struct [000048] ------------ | \--* ADDR byref [000047] -------N---- | \--* FIELD struct Tx [000044] ------------ | \--* ADDR byref [000043] -------N---- | \--* LCL_VAR struct V03 loc0 [000046] ---XG------- \--* FIELD struct m_PayloadsTx [000045] ------------ \--* LCL_VAR byref V00 this ***** BB01 STMT00008 (IL 0x047...0x04E) [000060] -AC-G------- * ASG struct (copy) [000058] D------N---- +--* LCL_VAR struct V07 tmp3 [000053] --C-G------- \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA [000057] n----------- arg0 +--* OBJ struct [000056] ------------ | \--* ADDR byref [000051] -------N---- | \--* LCL_VAR struct V03 loc0 [000055] n----------- arg1 \--* OBJ struct [000054] ------------ \--* ADDR byref [000052] -------N---- \--* LCL_VAR struct V02 arg2 ***** BB01 STMT00009 (IL ???... ???) [000062] ------------ * RETURN struct [000061] -------N---- \--* LCL_VAR struct V07 tmp3 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Indirect call transform -- no candidates to transform *************** Finishing PHASE Indirect call transform [no changes] *************** Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Finishing PHASE Expand patchpoints [no changes] *************** Starting PHASE Post-import *************** Finishing PHASE Post-import *************** Starting PHASE Morph - Init New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short) *************** In fgRemoveEmptyBlocks *************** Finishing PHASE Morph - Init *************** In fgDebugCheckBBlist *************** Starting PHASE Morph - Inlining *************** Finishing PHASE Morph - Inlining [no changes] *************** Starting PHASE Allocate Objects disabled, punting *************** Finishing PHASE Allocate Objects [no changes] *************** Starting PHASE Morph - Add internal blocks *************** After fgAddInternal() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** Finishing PHASE Morph - Add internal blocks *************** Starting PHASE Remove empty try *************** In fgRemoveEmptyTry() No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty try [no changes] *************** Starting PHASE Remove empty finally No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty finally [no changes] *************** Starting PHASE Merge callfinally chains No EH in this method, nothing to merge. *************** Finishing PHASE Merge callfinally chains [no changes] *************** Starting PHASE Clone finally No EH in this method, no cloning. *************** Finishing PHASE Clone finally [no changes] *************** Starting PHASE Compute preds Renumbering the basic blocks for fgComputePred *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** After renumbering the basic blocks =============== No blocks renumbered! *************** In fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** After fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Compute preds *************** Starting PHASE Morph - Promote Structs *************** In fgPromoteStructs() promotion opt flag not enabled *************** Finishing PHASE Morph - Promote Structs *************** Starting PHASE Morph - Structs/AddrExp *************** In fgMarkAddressExposedLocals() LocalAddressVisitor visiting statement: STMT00000 (IL 0x000...0x028) [000007] -AC--------- * ASG ref [000006] D------N---- +--* LCL_VAR ref V05 tmp1 [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000004] ------------ arg0 \--* CNS_INT(h) long 0x7f6678beb1c0 class LocalAddressVisitor visiting statement: STMT00001 (IL ???... ???) [000012] -A--G------- * ASG int [000011] -------N---- +--* IND int [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V05 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ----G------- \--* FIELD int Version [000002] ------------ \--* ADDR byref [000001] -------N---- \--* LCL_VAR struct V02 arg2 Local V02 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00001 (IL ???... ???) [000012] -A--G------- * ASG int [000011] -------N---- +--* IND int [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V05 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ------------ \--* LCL_FLD int V02 arg2 [+8] Fseq[Version] LocalAddressVisitor visiting statement: STMT00002 (IL ???... ???) [000021] -AC--------- * ASG ref [000020] D------N---- +--* LCL_VAR ref V06 tmp2 [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000018] ------------ arg0 \--* CNS_INT(h) long 0x7f6678c127f0 class LocalAddressVisitor visiting statement: STMT00003 (IL ???... ???) [000026] -A--G------- * ASG long [000025] -------N---- +--* IND long [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V06 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ----G------- \--* FIELD long JobGroup [000016] ------------ \--* ADDR byref [000015] -------N---- \--* LCL_VAR struct V02 arg2 Local V02 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00003 (IL ???... ???) [000026] -A--G------- * ASG long [000025] -------N---- +--* IND long [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V06 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ------------ \--* LCL_FLD long V02 arg2 [+0] Fseq[JobGroup] LocalAddressVisitor visiting statement: STMT00004 (IL ???... ???) [000030] --C-G------- * CALL void UnityEngine.Debug.Log [000029] --C-G------- arg0 \--* CALL ref System.String.Format [000000] ------------ arg0 +--* CNS_STR ref [000014] ------------ arg1 +--* BOX ref [000013] ------------ | \--* LCL_VAR ref V05 tmp1 [000028] ------------ arg2 \--* BOX ref [000027] ------------ \--* LCL_VAR ref V06 tmp2 LocalAddressVisitor visiting statement: STMT00005 (IL 0x025... ???) [000034] IA---------- * ASG struct (init) [000031] D------N---- +--* LCL_VAR struct V03 loc0 [000033] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00006 (IL 0x02D...0x035) [000042] -A-XG------- * ASG struct (copy) [000041] ------------ +--* OBJ struct [000040] ------------ | \--* ADDR byref [000039] -------N---- | \--* FIELD struct Baselib [000036] ------------ | \--* ADDR byref [000035] -------N---- | \--* LCL_VAR struct V03 loc0 [000038] ---XG------- \--* FIELD struct m_Baselib [000037] ------------ \--* LCL_VAR byref V00 this LocalAddressVisitor visiting statement: STMT00007 (IL 0x03A...0x042) [000050] -A-XG------- * ASG struct (copy) [000049] ------------ +--* BLK struct [000048] ------------ | \--* ADDR byref [000047] -------N---- | \--* FIELD struct Tx [000044] ------------ | \--* ADDR byref [000043] -------N---- | \--* LCL_VAR struct V03 loc0 [000046] ---XG------- \--* FIELD struct m_PayloadsTx [000045] ------------ \--* LCL_VAR byref V00 this LocalAddressVisitor visiting statement: STMT00008 (IL 0x047...0x04E) [000060] -AC-G------- * ASG struct (copy) [000058] D------N---- +--* LCL_VAR struct V07 tmp3 [000053] --C-G------- \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA [000057] n----------- arg0 +--* OBJ struct [000056] ------------ | \--* ADDR byref [000051] -------N---- | \--* LCL_VAR struct V03 loc0 [000055] n----------- arg1 \--* OBJ struct [000054] ------------ \--* ADDR byref [000052] -------N---- \--* LCL_VAR struct V02 arg2 LocalAddressVisitor visiting statement: STMT00009 (IL ???... ???) [000062] ------------ * RETURN struct [000061] -------N---- \--* LCL_VAR struct V07 tmp3 *************** Finishing PHASE Morph - Structs/AddrExp *************** Starting PHASE Morph - ByRefs *************** Finishing PHASE Morph - ByRefs *************** Starting PHASE Morph - Global *************** In fgMorphBlocks() Morphing BB01 of 'Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' fgMorphTree BB01, STMT00000 (before) [000007] -AC--------- * ASG ref [000006] D------N---- +--* LCL_VAR ref V05 tmp1 [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000004] ------------ arg0 \--* CNS_INT(h) long 0x7f6678beb1c0 class Initializing arg info for 5.CALL: ArgTable for 5.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 4.CNS_INT long (By ref), 1 reg: rdi, align=1] Morphing args for 5.CALL: argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000004] -----+------ * CNS_INT(h) long 0x7f6678beb1c0 class Replaced with placeholder node: [000063] ----------L- * ARGPLACE long Shuffled argument table: rdi ArgTable for 5.CALL after fgMorphArgs: fgArgTabEntry[arg 0 4.CNS_INT long (By ref), 1 reg: rdi, align=1, lateArgInx=0, processed] fgMorphTree BB01, STMT00000 (after) [000007] -AC--+------ * ASG ref [000006] D----+-N---- +--* LCL_VAR ref V05 tmp1 [000005] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000004] -----+------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class fgMorphTree BB01, STMT00001 (before) [000012] -A--G------- * ASG int [000011] -------N---- +--* IND int [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V05 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ------------ \--* LCL_FLD int V02 arg2 [+8] Fseq[Version] fgMorphTree BB01, STMT00002 (before) [000021] -AC--------- * ASG ref [000020] D------N---- +--* LCL_VAR ref V06 tmp2 [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000018] ------------ arg0 \--* CNS_INT(h) long 0x7f6678c127f0 class Initializing arg info for 19.CALL: ArgTable for 19.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 18.CNS_INT long (By ref), 1 reg: rdi, align=1] Morphing args for 19.CALL: argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000018] -----+------ * CNS_INT(h) long 0x7f6678c127f0 class Replaced with placeholder node: [000064] ----------L- * ARGPLACE long Shuffled argument table: rdi ArgTable for 19.CALL after fgMorphArgs: fgArgTabEntry[arg 0 18.CNS_INT long (By ref), 1 reg: rdi, align=1, lateArgInx=0, processed] fgMorphTree BB01, STMT00002 (after) [000021] -AC--+------ * ASG ref [000020] D----+-N---- +--* LCL_VAR ref V06 tmp2 [000019] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000018] -----+------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class fgMorphTree BB01, STMT00003 (before) [000026] -A--G------- * ASG long [000025] -------N---- +--* IND long [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V06 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ------------ \--* LCL_FLD long V02 arg2 [+0] Fseq[JobGroup] fgMorphTree BB01, STMT00004 (before) [000030] --C-G------- * CALL void UnityEngine.Debug.Log [000029] --C-G------- arg0 \--* CALL ref System.String.Format [000000] ------------ arg0 +--* CNS_STR ref [000014] ------------ arg1 +--* BOX ref [000013] ------------ | \--* LCL_VAR ref V05 tmp1 [000028] ------------ arg2 \--* BOX ref [000027] ------------ \--* LCL_VAR ref V06 tmp2 Initializing arg info for 30.CALL: ArgTable for 30.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 29.CALL ref (By ref), 1 reg: rdi, align=1] Morphing args for 30.CALL: Initializing arg info for 29.CALL: ArgTable for 29.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 0.CNS_STR ref (By ref), 1 reg: rdi, align=1] fgArgTabEntry[arg 1 14.BOX ref (By ref), 1 reg: rsi, align=1] fgArgTabEntry[arg 2 28.BOX ref (By ref), 1 reg: rdx, align=1] Morphing args for 29.CALL: argSlots=3, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rsi'): ( 9, 6) [000014] ------------ * BOX ref ( 3, 2) [000013] ------------ \--* LCL_VAR ref V05 tmp1 Replaced with placeholder node: [000067] ----------L- * ARGPLACE ref Deferred argument ('rdx'): ( 9, 6) [000028] ------------ * BOX ref ( 3, 2) [000027] ------------ \--* LCL_VAR ref V06 tmp2 Replaced with placeholder node: [000068] ----------L- * ARGPLACE ref Deferred argument ('rdi'): ( 4, 12) [000066] n---G------- * IND ref ( 2, 10) [000065] ------------ \--* CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] Replaced with placeholder node: [000069] ----------L- * ARGPLACE ref Shuffled argument table: rsi rdx rdi ArgTable for 29.CALL after fgMorphArgs: fgArgTabEntry[arg 1 14.BOX ref (By ref), 1 reg: rsi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 2 28.BOX ref (By ref), 1 reg: rdx, align=1, lateArgInx=1, processed] fgArgTabEntry[arg 0 66.IND ref (By ref), 1 reg: rdi, align=1, lateArgInx=2, processed] argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000029] --CXG+------ * CALL ref System.String.Format ( 9, 6) [000014] ------------ arg1 in rsi +--* BOX ref ( 3, 2) [000013] ------------ | \--* LCL_VAR ref V05 tmp1 ( 9, 6) [000028] ------------ arg2 in rdx +--* BOX ref ( 3, 2) [000027] ------------ | \--* LCL_VAR ref V06 tmp2 ( 4, 12) [000066] n---G------- arg0 in rdi \--* IND ref ( 2, 10) [000065] ------------ \--* CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] Replaced with placeholder node: [000070] ----------L- * ARGPLACE ref Shuffled argument table: rdi ArgTable for 30.CALL after fgMorphArgs: fgArgTabEntry[arg 0 29.CALL ref (By ref), 1 reg: rdi, align=1, lateArgInx=0, processed] fgMorphTree BB01, STMT00004 (after) [000030] --CXG+------ * CALL void UnityEngine.Debug.Log [000029] --CXG+------ arg0 in rdi \--* CALL ref System.String.Format ( 9, 6) [000014] ------------ arg1 in rsi +--* BOX ref ( 3, 2) [000013] ------------ | \--* LCL_VAR ref V05 tmp1 ( 9, 6) [000028] ------------ arg2 in rdx +--* BOX ref ( 3, 2) [000027] ------------ | \--* LCL_VAR ref V06 tmp2 ( 4, 12) [000066] n---G------- arg0 in rdi \--* IND ref ( 2, 10) [000065] ------------ \--* CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] fgMorphTree BB01, STMT00005 (before) [000034] IA---------- * ASG struct (init) [000031] D------N---- +--* LCL_VAR struct V03 loc0 [000033] ------------ \--* CNS_INT int 0 fgMorphBlkNode for dst tree, before: [000031] D----+-N---- * LCL_VAR struct V03 loc0 fgMorphBlkNode after: [000031] D----+-N---- * LCL_VAR struct V03 loc0 fgMorphInitBlock: Local V03 should not be enregistered because: written in a block op fgMorphTree BB01, STMT00006 (before) [000042] -A-XG------- * ASG struct (copy) [000041] ------------ +--* OBJ struct [000040] ------------ | \--* ADDR byref [000039] -------N---- | \--* FIELD struct Baselib [000036] ------------ | \--* ADDR byref [000035] -------N---- | \--* LCL_VAR struct V03 loc0 [000038] ---XG------- \--* FIELD struct m_Baselib [000037] ------------ \--* LCL_VAR byref V00 this Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000039] *------N---- * IND struct [000072] -----+------ \--* ADD byref [000036] -----+------ +--* ADDR byref [000035] -----+-N---- | \--* LCL_VAR struct V03 loc0 [000071] -----+------ \--* CNS_INT long 40 field offset Fseq[Baselib] Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000038] *--XG------- * IND struct [000074] -----+------ \--* ADD byref [000037] -----+------ +--* LCL_VAR byref V00 this [000073] -----+------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] fgMorphCopyBlock: fgMorphBlkNode for dst tree, before: [000041] n----+------ * OBJ struct [000072] -----+------ \--* ADD byref [000036] -----+------ +--* ADDR byref [000035] U----+-N---- | \--* LCL_VAR struct V03 loc0 [000071] -----+------ \--* CNS_INT long 40 field offset Fseq[Baselib] fgMorphBlkNode after: [000041] n----+------ * OBJ struct [000072] -----+------ \--* ADD byref [000036] -----+------ +--* ADDR byref [000035] U----+-N---- | \--* LCL_VAR struct V03 loc0 [000071] -----+------ \--* CNS_INT long 40 field offset Fseq[Baselib] fgMorphBlkNode for src tree, before: [000038] *--XG+------ * IND struct [000074] -----+------ \--* ADD byref [000037] -----+------ +--* LCL_VAR byref V00 this [000073] -----+------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] fgMorphBlkNode after: [000038] *--XG+------ * IND struct [000074] -----+------ \--* ADD byref [000037] -----+------ +--* LCL_VAR byref V00 this [000073] -----+------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] block assignment to morph: [000042] -A-XG------- * ASG struct (copy) [000041] n----+------ +--* OBJ struct [000072] -----+------ | \--* ADD byref [000036] -----+------ | +--* ADDR byref [000035] U----+-N---- | | \--* LCL_VAR struct V03 loc0 [000071] -----+------ | \--* CNS_INT long 40 field offset Fseq[Baselib] [000038] *--XG+------ \--* IND struct [000074] -----+------ \--* ADD byref [000037] -----+------ +--* LCL_VAR byref V00 this [000073] -----+------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] with no promoted structs this requires a CopyBlock. Local V03 should not be enregistered because: written in a block op fgMorphCopyBlock (after): [000042] -A-XG------- * ASG struct (copy) [000041] n----+------ +--* OBJ struct [000072] -----+------ | \--* ADD byref [000036] -----+------ | +--* ADDR byref [000035] U----+-N---- | | \--* LCL_VAR struct V03 loc0 [000071] -----+------ | \--* CNS_INT long 40 field offset Fseq[Baselib] [000038] *--XG+------ \--* IND struct [000074] -----+------ \--* ADD byref [000037] -----+------ +--* LCL_VAR byref V00 this [000073] -----+------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] fgMorphTree BB01, STMT00006 (after) [000042] -A-XG+------ * ASG struct (copy) [000041] n----+------ +--* OBJ struct [000072] -----+------ | \--* ADD byref [000036] -----+------ | +--* ADDR byref [000035] U----+-N---- | | \--* LCL_VAR struct V03 loc0 [000071] -----+------ | \--* CNS_INT long 40 field offset Fseq[Baselib] [000038] *--XG+------ \--* IND struct [000074] -----+------ \--* ADD byref [000037] -----+------ +--* LCL_VAR byref V00 this [000073] -----+------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] fgMorphTree BB01, STMT00007 (before) [000050] -A-XG------- * ASG struct (copy) [000049] ------------ +--* BLK struct [000048] ------------ | \--* ADDR byref [000047] -------N---- | \--* FIELD struct Tx [000044] ------------ | \--* ADDR byref [000043] -------N---- | \--* LCL_VAR struct V03 loc0 [000046] ---XG------- \--* FIELD struct m_PayloadsTx [000045] ------------ \--* LCL_VAR byref V00 this Before calling fgAddFieldSeqForZeroOffset: [000047] *------N---- * IND struct [000044] ------------ \--* ADDR byref [000043] -------N---- \--* LCL_VAR struct V03 loc0 fgAddFieldSeqForZeroOffset for Fseq[Tx] addr (Before) [000044] ------------ ADDR byref (After) [000044] ------------ ADDR byref Zero Fseq[Tx] Local V03 should not be enregistered because: was accessed as a local field Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000043] -----+-N---- * LCL_FLD struct V03 loc0 [+0] Fseq[Tx] Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000046] *--XG------- * IND struct [000076] -----+------ \--* ADD byref [000045] -----+------ +--* LCL_VAR byref V00 this [000075] -----+------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] fgMorphCopyBlock: fgMorphBlkNode for dst tree, before: [000049] n----+------ * BLK struct [000048] -----+------ \--* ADDR byref [000043] U----+-N---- \--* LCL_FLD struct V03 loc0 [+0] Fseq[Tx] fgMorphBlkNode after: [000049] n----+------ * BLK struct [000048] -----+------ \--* ADDR byref [000043] U----+-N---- \--* LCL_FLD struct V03 loc0 [+0] Fseq[Tx] fgMorphBlkNode for src tree, before: [000046] *--XG+------ * IND struct [000076] -----+------ \--* ADD byref [000045] -----+------ +--* LCL_VAR byref V00 this [000075] -----+------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] fgMorphBlkNode after: [000046] *--XG+------ * IND struct [000076] -----+------ \--* ADD byref [000045] -----+------ +--* LCL_VAR byref V00 this [000075] -----+------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] block assignment to morph: [000050] -A-XG------- * ASG struct (copy) [000049] n----+------ +--* BLK struct [000048] -----+------ | \--* ADDR byref [000043] U----+-N---- | \--* LCL_FLD struct V03 loc0 [+0] Fseq[Tx] [000046] *--XG+------ \--* IND struct [000076] -----+------ \--* ADD byref [000045] -----+------ +--* LCL_VAR byref V00 this [000075] -----+------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] with no promoted structs this requires a CopyBlock. Local V03 should not be enregistered because: written in a block op fgMorphCopyBlock (after): [000050] -A-XG------- * ASG struct (copy) [000049] n----+------ +--* BLK struct [000048] -----+------ | \--* ADDR byref [000043] U----+-N---- | \--* LCL_FLD struct V03 loc0 [+0] Fseq[Tx] [000046] *--XG+------ \--* IND struct [000076] -----+------ \--* ADD byref [000045] -----+------ +--* LCL_VAR byref V00 this [000075] -----+------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] fgMorphTree BB01, STMT00007 (after) [000050] -A-XG+------ * ASG struct (copy) [000049] n----+------ +--* BLK struct [000048] -----+------ | \--* ADDR byref [000043] U----+-N---- | \--* LCL_FLD struct V03 loc0 [+0] Fseq[Tx] [000046] *--XG+------ \--* IND struct [000076] -----+------ \--* ADD byref [000045] -----+------ +--* LCL_VAR byref V00 this [000075] -----+------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] fgMorphTree BB01, STMT00008 (before) [000060] -AC-G------- * ASG struct (copy) [000058] D------N---- +--* LCL_VAR struct V07 tmp3 [000053] --C-G------- \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA [000057] n----------- arg0 +--* OBJ struct [000056] ------------ | \--* ADDR byref [000051] -------N---- | \--* LCL_VAR struct V03 loc0 [000055] n----------- arg1 \--* OBJ struct [000054] ------------ \--* ADDR byref [000052] -------N---- \--* LCL_VAR struct V02 arg2 Initializing arg info for 53.CALL: **** getSystemVAmd64PassStructInRegisterDescriptor(0x7a0b9088 (FlushSendJob), ...) => passedInRegisters = false **** getSystemVAmd64PassStructInRegisterDescriptor(0x7a0b9088 (FlushSendJob), ...) => passedInRegisters = false **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 ArgTable for 53.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 57.OBJ struct (By value), numSlots=12, slotNum=0, align=1, isStruct] fgArgTabEntry[arg 1 55.OBJ struct (By value), 2 regs: rdi rsi, align=1, isStruct] Morphing args for 53.CALL: argSlots=14, preallocatedArgCount=12, nextSlotNum=12, outgoingArgSpaceSize=96 Sorting the arguments: Deferred argument ('rdi'): ( 9, 7) [000055] n----------- * OBJ struct ( 3, 3) [000054] ------------ \--* ADDR byref ( 3, 2) [000052] -------N---- \--* LCL_VAR struct V02 arg2 Replaced with placeholder node: [000077] ----------L- * ARGPLACE struct => [clsHnd=795C7A00] Shuffled argument table: rdi Local V03 should not be enregistered because: it is a struct arg Multireg struct argument V02 : fgArgTabEntry[arg 1 55.OBJ struct (By value), 2 regs: rdi rsi, align=1, lateArgInx=0, processed, isStruct] Local V02 should not be enregistered because: was accessed as a local field Local V02 should not be enregistered because: was accessed as a local field fgMorphMultiregStructArg created tree: [000078] -c---------- * FIELD_LIST struct [000079] ------------ ofs 0 +--* LCL_FLD long V02 arg2 [+0] [000080] ------------ ofs 8 \--* LCL_FLD long V02 arg2 [+8] ArgTable for 53.CALL after fgMorphArgs: fgArgTabEntry[arg 0 57.OBJ struct (By value), numSlots=12, slotNum=0, align=1, processed, isStruct] fgArgTabEntry[arg 1 78.FIELD_LIST struct (By value), 2 regs: rdi rsi, align=1, lateArgInx=0, processed, isStruct] fgMorphCopyBlock: not morphing a multireg call return fgMorphTree BB01, STMT00008 (after) [000060] -ACXG+------ * ASG struct (copy) [000058] D----+-N---- +--* LCL_VAR struct V07 tmp3 [000053] --CXG+------ \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA ( 9, 7) [000057] n----------- arg0 out+00 +--* OBJ struct ( 3, 3) [000056] ------------ | \--* ADDR byref ( 3, 2) [000051] -------N---- | \--* LCL_VAR struct V03 loc0 [000078] -c---------- arg1 rdi,rsi \--* FIELD_LIST struct [000079] ------------ ofs 0 +--* LCL_FLD long V02 arg2 [+0] [000080] ------------ ofs 8 \--* LCL_FLD long V02 arg2 [+8] fgMorphTree BB01, STMT00009 (before) [000062] ------------ * RETURN struct [000061] -------N---- \--* LCL_VAR struct V07 tmp3 *************** Finishing PHASE Morph - Global Trees after Morph - Global ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} ***** BB01 STMT00000 (IL 0x000...0x028) [000007] -AC--+------ * ASG ref [000006] D----+-N---- +--* LCL_VAR ref V05 tmp1 [000005] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000004] -----+------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class ***** BB01 STMT00001 (IL ???... ???) [000012] -A-XG+------ * ASG int [000011] ---X-+-N---- +--* IND int [000010] -----+------ | \--* ADD byref [000008] -----+------ | +--* LCL_VAR ref V05 tmp1 [000009] -----+------ | \--* CNS_INT long 8 [000003] -----+------ \--* LCL_FLD int V02 arg2 [+8] Fseq[Version] ***** BB01 STMT00002 (IL ???... ???) [000021] -AC--+------ * ASG ref [000020] D----+-N---- +--* LCL_VAR ref V06 tmp2 [000019] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000018] -----+------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class ***** BB01 STMT00003 (IL ???... ???) [000026] -A-XG+------ * ASG long [000025] ---X-+-N---- +--* IND long [000024] -----+------ | \--* ADD byref [000022] -----+------ | +--* LCL_VAR ref V06 tmp2 [000023] -----+------ | \--* CNS_INT long 8 [000017] -----+------ \--* LCL_FLD long V02 arg2 [+0] Fseq[JobGroup] ***** BB01 STMT00004 (IL ???... ???) [000030] --CXG+------ * CALL void UnityEngine.Debug.Log [000029] --CXG+------ arg0 in rdi \--* CALL ref System.String.Format ( 9, 6) [000014] ------------ arg1 in rsi +--* BOX ref ( 3, 2) [000013] ------------ | \--* LCL_VAR ref V05 tmp1 ( 9, 6) [000028] ------------ arg2 in rdx +--* BOX ref ( 3, 2) [000027] ------------ | \--* LCL_VAR ref V06 tmp2 ( 4, 12) [000066] n---G------- arg0 in rdi \--* IND ref ( 2, 10) [000065] ------------ \--* CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] ***** BB01 STMT00005 (IL 0x025... ???) [000034] IA---+------ * ASG struct (init) [000031] D----+-N---- +--* LCL_VAR struct V03 loc0 [000033] -----+------ \--* CNS_INT int 0 ***** BB01 STMT00006 (IL 0x02D...0x035) [000042] -A-XG+------ * ASG struct (copy) [000041] n----+------ +--* OBJ struct [000072] -----+------ | \--* ADD byref [000036] -----+------ | +--* ADDR byref [000035] U----+-N---- | | \--* LCL_VAR struct V03 loc0 [000071] -----+------ | \--* CNS_INT long 40 field offset Fseq[Baselib] [000038] *--XG+------ \--* IND struct [000074] -----+------ \--* ADD byref [000037] -----+------ +--* LCL_VAR byref V00 this [000073] -----+------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] ***** BB01 STMT00007 (IL 0x03A...0x042) [000050] -A-XG+------ * ASG struct (copy) [000049] n----+------ +--* BLK struct [000048] -----+------ | \--* ADDR byref [000043] U----+-N---- | \--* LCL_FLD struct V03 loc0 [+0] Fseq[Tx] [000046] *--XG+------ \--* IND struct [000076] -----+------ \--* ADD byref [000045] -----+------ +--* LCL_VAR byref V00 this [000075] -----+------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] ***** BB01 STMT00008 (IL 0x047...0x04E) [000060] -ACXG+------ * ASG struct (copy) [000058] D----+-N---- +--* LCL_VAR struct V07 tmp3 [000053] --CXG+------ \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA ( 9, 7) [000057] n----------- arg0 out+00 +--* OBJ struct ( 3, 3) [000056] ------------ | \--* ADDR byref ( 3, 2) [000051] -------N---- | \--* LCL_VAR struct V03 loc0 [000078] -c---------- arg1 rdi,rsi \--* FIELD_LIST struct [000079] ------------ ofs 0 +--* LCL_FLD long V02 arg2 [+0] [000080] ------------ ofs 8 \--* LCL_FLD long V02 arg2 [+8] ***** BB01 STMT00009 (IL ???... ???) [000062] -----+------ * RETURN struct [000061] -----+-N---- \--* LCL_VAR struct V07 tmp3 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE GS Cookie No GS security needed *************** Finishing PHASE GS Cookie *************** Starting PHASE Mark GC poll blocks *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** After renumbering the basic blocks =============== No blocks renumbered! *************** Finishing PHASE Mark GC poll blocks *************** Starting PHASE Compute edge weights (1, false) *************** In fgComputeBlockAndEdgeWeights() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- -- no profile data, so using default called count -- not optimizing, so not computing edge weights *************** Finishing PHASE Compute edge weights (1, false) *************** Starting PHASE Create EH funclets *************** In fgCreateFunclets() After fgCreateFunclets() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** Finishing PHASE Create EH funclets *************** Starting PHASE Mark local vars *************** In lvaMarkLocalVars() *** lvaComputeRefCounts *** *************** Finishing PHASE Mark local vars *************** Starting PHASE Find oper order *************** In fgFindOperOrder() *************** Finishing PHASE Find oper order *************** Starting PHASE Set block order *************** In fgSetBlockOrder() The biggest BB has 12 tree nodes *************** Finishing PHASE Set block order *************** Starting PHASE Insert GC Polls *************** Finishing PHASE Insert GC Polls [no changes] *************** Starting PHASE Determine first cold block *************** In fgDetermineFirstColdBlock() No procedure splitting will be done for this method *************** Finishing PHASE Determine first cold block Trees before Rationalize IR ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} ***** BB01 STMT00000 (IL 0x000...0x028) N005 ( 20, 19) [000007] -AC-----R--- * ASG ref N004 ( 3, 2) [000006] D------N---- +--* LCL_VAR ref V05 tmp1 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class ***** BB01 STMT00001 (IL ???... ???) N006 ( 10, 10) [000012] -A-XG------- * ASG int N004 ( 6, 5) [000011] ---X---N---- +--* IND int N003 ( 4, 3) [000010] -------N---- | \--* ADD byref N001 ( 3, 2) [000008] ------------ | +--* LCL_VAR ref V05 tmp1 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD int V02 arg2 [+8] Fseq[Version] ***** BB01 STMT00002 (IL ???... ???) N005 ( 20, 19) [000021] -AC-----R--- * ASG ref N004 ( 3, 2) [000020] D------N---- +--* LCL_VAR ref V06 tmp2 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class ***** BB01 STMT00003 (IL ???... ???) N006 ( 10, 10) [000026] -A-XG------- * ASG long N004 ( 6, 5) [000025] ---X---N---- +--* IND long N003 ( 4, 3) [000024] -------N---- | \--* ADD byref N001 ( 3, 2) [000022] ------------ | +--* LCL_VAR ref V06 tmp2 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD long V02 arg2 [+0] Fseq[JobGroup] ***** BB01 STMT00004 (IL ???... ???) N012 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log N011 ( 36, 32) [000029] --CXG------- arg0 in rdi \--* CALL ref System.String.Format N006 ( 9, 6) [000014] ------------ arg1 in rsi +--* BOX ref N005 ( 3, 2) [000013] ------------ | \--* LCL_VAR ref V05 tmp1 N008 ( 9, 6) [000028] ------------ arg2 in rdx +--* BOX ref N007 ( 3, 2) [000027] ------------ | \--* LCL_VAR ref V06 tmp2 N010 ( 4, 12) [000066] n---G------- arg0 in rdi \--* IND ref N009 ( 2, 10) [000065] ------------ \--* CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] ***** BB01 STMT00005 (IL 0x025... ???) N003 ( 5, 4) [000034] IA------R--- * ASG struct (init) N002 ( 3, 2) [000031] D------N---- +--* LCL_VAR struct V03 loc0 N001 ( 1, 1) [000033] ------------ \--* CNS_INT int 0 ***** BB01 STMT00006 (IL 0x02D...0x035) N010 ( 20, 16) [000042] -A-XG---R--- * ASG struct (copy) N009 ( 11, 9) [000041] n----------- +--* OBJ struct N008 ( 5, 5) [000072] ------------ | \--* ADD byref N006 ( 3, 3) [000036] ------------ | +--* ADDR byref N005 ( 3, 2) [000035] U------N---- | | \--* LCL_VAR struct V03 loc0 N007 ( 1, 1) [000071] ------------ | \--* CNS_INT long 40 field offset Fseq[Baselib] N004 ( 8, 6) [000038] *--XG------- \--* IND struct N003 ( 5, 4) [000074] ------------ \--* ADD byref N001 ( 3, 2) [000037] ------------ +--* LCL_VAR byref V00 this N002 ( 1, 1) [000073] ------------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] ***** BB01 STMT00007 (IL 0x03A...0x042) N008 ( 15, 14) [000050] -A-XG---R--- * ASG struct (copy) N007 ( 6, 7) [000049] n----------- +--* BLK struct N006 ( 3, 5) [000048] ------------ | \--* ADDR byref N005 ( 3, 4) [000043] U------N---- | \--* LCL_FLD struct V03 loc0 [+0] Fseq[Tx] N004 ( 8, 6) [000046] *--XG------- \--* IND struct N003 ( 5, 4) [000076] ------------ \--* ADD byref N001 ( 3, 2) [000045] ------------ +--* LCL_VAR byref V00 this N002 ( 1, 1) [000075] ------------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] ***** BB01 STMT00008 (IL 0x047...0x04E) N010 ( 36, 24) [000060] -ACXG---R--- * ASG struct (copy) N009 ( 3, 2) [000058] D------N---- +--* LCL_VAR struct V07 tmp3 N008 ( 32, 21) [000053] --CXG------- \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA N003 ( 9, 7) [000057] n----------- arg0 out+00 +--* OBJ struct N002 ( 3, 3) [000056] ------------ | \--* ADDR byref N001 ( 3, 2) [000051] -------N---- | \--* LCL_VAR struct V03 loc0 N007 ( 6, 8) [000078] -c---------- arg1 rdi,rsi \--* FIELD_LIST struct N005 ( 3, 4) [000079] ------------ ofs 0 +--* LCL_FLD long V02 arg2 [+0] N006 ( 3, 4) [000080] ------------ ofs 8 \--* LCL_FLD long V02 arg2 [+8] ***** BB01 STMT00009 (IL ???... ???) N002 ( 4, 3) [000062] ------------ * RETURN struct N001 ( 3, 2) [000061] -------N---- \--* LCL_VAR struct V07 tmp3 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Rationalize IR rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 20, 19) [000007] DAC--------- * STORE_LCL_VAR ref V05 tmp1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 20, 19) [000021] DAC--------- * STORE_LCL_VAR ref V06 tmp2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000034] DA---------- * STORE_LCL_VAR struct V03 loc0 Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N005 ( 3, 2) [000035] U------N---- t35 = LCL_VAR_ADDR byref V03 loc0 Rewriting GT_ASG(OBJ(X), Y) to STORE_OBJ(X,Y): N001 ( 3, 2) [000037] ------------ t37 = LCL_VAR byref V00 this N002 ( 1, 1) [000073] ------------ t73 = CNS_INT long 16 field offset Fseq[m_Baselib] /--* t37 byref +--* t73 long N003 ( 5, 4) [000074] ------------ t74 = * ADD byref /--* t74 byref N004 ( 8, 6) [000038] *--XG------- t38 = * IND struct N005 ( 3, 2) [000035] U------N---- t35 = LCL_VAR_ADDR byref V03 loc0 N007 ( 1, 1) [000071] ------------ t71 = CNS_INT long 40 field offset Fseq[Baselib] /--* t35 byref +--* t71 long N008 ( 5, 5) [000072] ------------ t72 = * ADD byref /--* t72 byref +--* t38 struct N009 ( 11, 9) [000041] nA-XG------- * STORE_OBJ struct (copy) Rewriting GT_ADDR(GT_LCL_FLD) to GT_LCL_FLD_ADDR: N005 ( 3, 4) [000043] U------N---- t43 = LCL_FLD_ADDR byref V03 loc0 [+0] Fseq[Tx] Rewriting GT_ASG(BLK(X), Y) to STORE_BLK(X,Y): N001 ( 3, 2) [000045] ------------ t45 = LCL_VAR byref V00 this N002 ( 1, 1) [000075] ------------ t75 = CNS_INT long 112 field offset Fseq[m_PayloadsTx] /--* t45 byref +--* t75 long N003 ( 5, 4) [000076] ------------ t76 = * ADD byref /--* t76 byref N004 ( 8, 6) [000046] *--XG------- t46 = * IND struct N005 ( 3, 4) [000043] U------N---- t43 = LCL_FLD_ADDR byref V03 loc0 [+0] Fseq[Tx] /--* t43 byref +--* t46 struct N007 ( 6, 7) [000049] nA-XG------- * STORE_BLK struct (copy) Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N001 ( 3, 2) [000051] -------N---- t51 = LCL_VAR_ADDR byref V03 loc0 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N010 ( 36, 24) [000060] DACXG------- * STORE_LCL_VAR struct V07 tmp3 *************** Finishing PHASE Rationalize IR Trees after Rationalize IR ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} [000081] ------------ IL_OFFSET void IL offset: 0x0 N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class /--* t4 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t5 ref N005 ( 20, 19) [000007] DA---------- * STORE_LCL_VAR ref V05 tmp1 N001 ( 3, 2) [000008] ------------ t8 = LCL_VAR ref V05 tmp1 N002 ( 1, 1) [000009] ------------ t9 = CNS_INT long 8 /--* t8 ref +--* t9 long N003 ( 4, 3) [000010] -------N---- t10 = * ADD byref N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD int V02 arg2 [+8] Fseq[Version] /--* t10 byref +--* t3 int [000082] -A-XG------- * STOREIND int N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class /--* t18 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t19 ref N005 ( 20, 19) [000021] DA---------- * STORE_LCL_VAR ref V06 tmp2 N001 ( 3, 2) [000022] ------------ t22 = LCL_VAR ref V06 tmp2 N002 ( 1, 1) [000023] ------------ t23 = CNS_INT long 8 /--* t22 ref +--* t23 long N003 ( 4, 3) [000024] -------N---- t24 = * ADD byref N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD long V02 arg2 [+0] Fseq[JobGroup] /--* t24 byref +--* t17 long [000083] -A-XG------- * STOREIND long N005 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V05 tmp1 N007 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V06 tmp2 N009 ( 2, 10) [000065] ------------ t65 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] /--* t65 long N010 ( 4, 12) [000066] n---G------- t66 = * IND ref /--* t13 ref arg1 in rsi +--* t27 ref arg2 in rdx +--* t66 ref arg0 in rdi N011 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format /--* t29 ref arg0 in rdi N012 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log [000084] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 1, 1) [000033] ------------ t33 = CNS_INT int 0 /--* t33 int N003 ( 5, 4) [000034] DA---------- * STORE_LCL_VAR struct V03 loc0 [000085] ------------ IL_OFFSET void IL offset: 0x2d N001 ( 3, 2) [000037] ------------ t37 = LCL_VAR byref V00 this N002 ( 1, 1) [000073] ------------ t73 = CNS_INT long 16 field offset Fseq[m_Baselib] /--* t37 byref +--* t73 long N003 ( 5, 4) [000074] ------------ t74 = * ADD byref /--* t74 byref N004 ( 8, 6) [000038] *--XG------- t38 = * IND struct N005 ( 3, 2) [000035] U------N---- t35 = LCL_VAR_ADDR byref V03 loc0 N007 ( 1, 1) [000071] ------------ t71 = CNS_INT long 40 field offset Fseq[Baselib] /--* t35 byref +--* t71 long N008 ( 5, 5) [000072] ------------ t72 = * ADD byref /--* t72 byref +--* t38 struct N009 ( 11, 9) [000041] nA-XG------- * STORE_OBJ struct (copy) [000086] ------------ IL_OFFSET void IL offset: 0x3a N001 ( 3, 2) [000045] ------------ t45 = LCL_VAR byref V00 this N002 ( 1, 1) [000075] ------------ t75 = CNS_INT long 112 field offset Fseq[m_PayloadsTx] /--* t45 byref +--* t75 long N003 ( 5, 4) [000076] ------------ t76 = * ADD byref /--* t76 byref N004 ( 8, 6) [000046] *--XG------- t46 = * IND struct N005 ( 3, 4) [000043] U------N---- t43 = LCL_FLD_ADDR byref V03 loc0 [+0] Fseq[Tx] /--* t43 byref +--* t46 struct N007 ( 6, 7) [000049] nA-XG------- * STORE_BLK struct (copy) [000087] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000051] -------N---- t51 = LCL_VAR_ADDR byref V03 loc0 /--* t51 byref N003 ( 9, 7) [000057] n----------- t57 = * OBJ struct N005 ( 3, 4) [000079] ------------ t79 = LCL_FLD long V02 arg2 [+0] N006 ( 3, 4) [000080] ------------ t80 = LCL_FLD long V02 arg2 [+8] /--* t79 long +--* t80 long N007 ( 6, 8) [000078] -c---------- t78 = * FIELD_LIST struct /--* t57 struct arg0 out+00 +--* t78 struct arg1 rdi,rsi N008 ( 32, 21) [000053] --CXG------- t53 = * CALL struct Unity.Jobs.IJobExtensions.Schedule,NA /--* t53 struct N010 ( 36, 24) [000060] DA-XG------- * STORE_LCL_VAR struct V07 tmp3 N001 ( 3, 2) [000061] -------N---- t61 = LCL_VAR struct V07 tmp3 /--* t61 struct N002 ( 4, 3) [000062] ------------ * RETURN struct ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Do 'simple' lowering outgoingArgSpaceSize 0 sufficient for call [000005], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000019], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000029], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000030], which needs 0 Bumping outgoingArgSpaceSize to 96 for call [000053] *************** Finishing PHASE Do 'simple' lowering *************** In fgDebugCheckBBlist Trees before Lowering nodeinfo ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} [000081] ------------ IL_OFFSET void IL offset: 0x0 N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class /--* t4 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t5 ref N005 ( 20, 19) [000007] DA---------- * STORE_LCL_VAR ref V05 tmp1 N001 ( 3, 2) [000008] ------------ t8 = LCL_VAR ref V05 tmp1 N002 ( 1, 1) [000009] ------------ t9 = CNS_INT long 8 /--* t8 ref +--* t9 long N003 ( 4, 3) [000010] -------N---- t10 = * ADD byref N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD int V02 arg2 [+8] Fseq[Version] /--* t10 byref +--* t3 int [000082] -A-XG------- * STOREIND int N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class /--* t18 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t19 ref N005 ( 20, 19) [000021] DA---------- * STORE_LCL_VAR ref V06 tmp2 N001 ( 3, 2) [000022] ------------ t22 = LCL_VAR ref V06 tmp2 N002 ( 1, 1) [000023] ------------ t23 = CNS_INT long 8 /--* t22 ref +--* t23 long N003 ( 4, 3) [000024] -------N---- t24 = * ADD byref N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD long V02 arg2 [+0] Fseq[JobGroup] /--* t24 byref +--* t17 long [000083] -A-XG------- * STOREIND long N005 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V05 tmp1 N007 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V06 tmp2 N009 ( 2, 10) [000065] ------------ t65 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] /--* t65 long N010 ( 4, 12) [000066] n---G------- t66 = * IND ref /--* t13 ref arg1 in rsi +--* t27 ref arg2 in rdx +--* t66 ref arg0 in rdi N011 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format /--* t29 ref arg0 in rdi N012 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log [000084] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 1, 1) [000033] ------------ t33 = CNS_INT int 0 /--* t33 int N003 ( 5, 4) [000034] DA---------- * STORE_LCL_VAR struct V03 loc0 [000085] ------------ IL_OFFSET void IL offset: 0x2d N001 ( 3, 2) [000037] ------------ t37 = LCL_VAR byref V00 this N002 ( 1, 1) [000073] ------------ t73 = CNS_INT long 16 field offset Fseq[m_Baselib] /--* t37 byref +--* t73 long N003 ( 5, 4) [000074] ------------ t74 = * ADD byref /--* t74 byref N004 ( 8, 6) [000038] *--XG------- t38 = * IND struct N005 ( 3, 2) [000035] U------N---- t35 = LCL_VAR_ADDR byref V03 loc0 N007 ( 1, 1) [000071] ------------ t71 = CNS_INT long 40 field offset Fseq[Baselib] /--* t35 byref +--* t71 long N008 ( 5, 5) [000072] ------------ t72 = * ADD byref /--* t72 byref +--* t38 struct N009 ( 11, 9) [000041] nA-XG------- * STORE_OBJ struct (copy) [000086] ------------ IL_OFFSET void IL offset: 0x3a N001 ( 3, 2) [000045] ------------ t45 = LCL_VAR byref V00 this N002 ( 1, 1) [000075] ------------ t75 = CNS_INT long 112 field offset Fseq[m_PayloadsTx] /--* t45 byref +--* t75 long N003 ( 5, 4) [000076] ------------ t76 = * ADD byref /--* t76 byref N004 ( 8, 6) [000046] *--XG------- t46 = * IND struct N005 ( 3, 4) [000043] U------N---- t43 = LCL_FLD_ADDR byref V03 loc0 [+0] Fseq[Tx] /--* t43 byref +--* t46 struct N007 ( 6, 7) [000049] nA-XG------- * STORE_BLK struct (copy) [000087] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000051] -------N---- t51 = LCL_VAR_ADDR byref V03 loc0 /--* t51 byref N003 ( 9, 7) [000057] n----------- t57 = * OBJ struct N005 ( 3, 4) [000079] ------------ t79 = LCL_FLD long V02 arg2 [+0] N006 ( 3, 4) [000080] ------------ t80 = LCL_FLD long V02 arg2 [+8] /--* t79 long +--* t80 long N007 ( 6, 8) [000078] -c---------- t78 = * FIELD_LIST struct /--* t57 struct arg0 out+00 +--* t78 struct arg1 rdi,rsi N008 ( 32, 21) [000053] --CXG------- t53 = * CALL struct Unity.Jobs.IJobExtensions.Schedule,NA /--* t53 struct N010 ( 36, 24) [000060] DA-XG------- * STORE_LCL_VAR struct V07 tmp3 N001 ( 3, 2) [000061] -------N---- t61 = LCL_VAR struct V07 tmp3 /--* t61 struct N002 ( 4, 3) [000062] ------------ * RETURN struct ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Lowering nodeinfo lowering call (before): N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class /--* t4 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000063] ----------L- * ARGPLACE long late: ====== lowering arg : N002 ( 2, 10) [000004] ------------ * CNS_INT(h) long 0x7f6678beb1c0 class new node is : [000088] ------------ * PUTARG_REG long REG rdi lowering call (after): N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class /--* t4 long [000088] ------------ t88 = * PUTARG_REG long REG rdi /--* t88 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST lowering store lcl var/field (before): N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class /--* t4 long [000088] ------------ t88 = * PUTARG_REG long REG rdi /--* t88 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t5 ref N005 ( 20, 19) [000007] DA---------- * STORE_LCL_VAR ref V05 tmp1 lowering store lcl var/field (after): N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class /--* t4 long [000088] ------------ t88 = * PUTARG_REG long REG rdi /--* t88 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t5 ref N005 ( 20, 19) [000007] DA---------- * STORE_LCL_VAR ref V05 tmp1 Addressing mode: Base N001 ( 3, 2) [000008] ------------ * LCL_VAR ref V05 tmp1 + 8 Removing unused node: N002 ( 1, 1) [000009] -c---------- * CNS_INT long 8 New addressing mode node: N003 ( 4, 3) [000010] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N001 ( 3, 2) [000008] ------------ t8 = LCL_VAR ref V05 tmp1 /--* t8 ref N003 ( 4, 3) [000010] ------------ t10 = * LEA(b+8) byref N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD int V02 arg2 [+8] Fseq[Version] /--* t10 byref +--* t3 int [000082] -A-XG------- * STOREIND int lowering call (before): N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class /--* t18 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000064] ----------L- * ARGPLACE long late: ====== lowering arg : N002 ( 2, 10) [000018] ------------ * CNS_INT(h) long 0x7f6678c127f0 class new node is : [000089] ------------ * PUTARG_REG long REG rdi lowering call (after): N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class /--* t18 long [000089] ------------ t89 = * PUTARG_REG long REG rdi /--* t89 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST lowering store lcl var/field (before): N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class /--* t18 long [000089] ------------ t89 = * PUTARG_REG long REG rdi /--* t89 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t19 ref N005 ( 20, 19) [000021] DA---------- * STORE_LCL_VAR ref V06 tmp2 lowering store lcl var/field (after): N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class /--* t18 long [000089] ------------ t89 = * PUTARG_REG long REG rdi /--* t89 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t19 ref N005 ( 20, 19) [000021] DA---------- * STORE_LCL_VAR ref V06 tmp2 Addressing mode: Base N001 ( 3, 2) [000022] ------------ * LCL_VAR ref V06 tmp2 + 8 Removing unused node: N002 ( 1, 1) [000023] -c---------- * CNS_INT long 8 New addressing mode node: N003 ( 4, 3) [000024] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N001 ( 3, 2) [000022] ------------ t22 = LCL_VAR ref V06 tmp2 /--* t22 ref N003 ( 4, 3) [000024] ------------ t24 = * LEA(b+8) byref N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD long V02 arg2 [+0] Fseq[JobGroup] /--* t24 byref +--* t17 long [000083] -A-XG------- * STOREIND long lowering call (before): N005 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V05 tmp1 N007 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V06 tmp2 N009 ( 2, 10) [000065] ------------ t65 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] /--* t65 long N010 ( 4, 12) [000066] n---G------- t66 = * IND ref /--* t13 ref arg1 in rsi +--* t27 ref arg2 in rdx +--* t66 ref arg0 in rdi N011 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format objp: ====== args: ====== lowering arg : N002 ( 0, 0) [000069] ----------L- * ARGPLACE ref lowering arg : N003 ( 0, 0) [000067] ----------L- * ARGPLACE ref lowering arg : N004 ( 0, 0) [000068] ----------L- * ARGPLACE ref late: ====== lowering arg : N005 ( 3, 2) [000013] ------------ * LCL_VAR ref V05 tmp1 new node is : [000090] ------------ * PUTARG_REG ref REG rsi lowering arg : N007 ( 3, 2) [000027] ------------ * LCL_VAR ref V06 tmp2 new node is : [000091] ------------ * PUTARG_REG ref REG rdx lowering arg : N010 ( 4, 12) [000066] n---G------- * IND ref new node is : [000092] ----G------- * PUTARG_REG ref REG rdi lowering call (after): N005 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V05 tmp1 /--* t13 ref [000090] ------------ t90 = * PUTARG_REG ref REG rsi N007 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V06 tmp2 /--* t27 ref [000091] ------------ t91 = * PUTARG_REG ref REG rdx N009 ( 2, 10) [000065] ------------ t65 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] /--* t65 long N010 ( 4, 12) [000066] n---G------- t66 = * IND ref /--* t66 ref [000092] ----G------- t92 = * PUTARG_REG ref REG rdi /--* t90 ref arg1 in rsi +--* t91 ref arg2 in rdx +--* t92 ref arg0 in rdi N011 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format lowering call (before): N005 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V05 tmp1 /--* t13 ref [000090] ------------ t90 = * PUTARG_REG ref REG rsi N007 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V06 tmp2 /--* t27 ref [000091] ------------ t91 = * PUTARG_REG ref REG rdx N009 ( 2, 10) [000065] ------------ t65 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] /--* t65 long N010 ( 4, 12) [000066] n---G------- t66 = * IND ref /--* t66 ref [000092] ----G------- t92 = * PUTARG_REG ref REG rdi /--* t90 ref arg1 in rsi +--* t91 ref arg2 in rdx +--* t92 ref arg0 in rdi N011 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format /--* t29 ref arg0 in rdi N012 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000070] ----------L- * ARGPLACE ref late: ====== lowering arg : N011 ( 36, 32) [000029] --CXG------- * CALL ref System.String.Format new node is : [000093] --CXG------- * PUTARG_REG ref REG rdi lowering call (after): N005 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V05 tmp1 /--* t13 ref [000090] ------------ t90 = * PUTARG_REG ref REG rsi N007 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V06 tmp2 /--* t27 ref [000091] ------------ t91 = * PUTARG_REG ref REG rdx N009 ( 2, 10) [000065] ------------ t65 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] /--* t65 long N010 ( 4, 12) [000066] n---G------- t66 = * IND ref /--* t66 ref [000092] ----G------- t92 = * PUTARG_REG ref REG rdi /--* t90 ref arg1 in rsi +--* t91 ref arg2 in rdx +--* t92 ref arg0 in rdi N011 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format /--* t29 ref [000093] --CXG------- t93 = * PUTARG_REG ref REG rdi /--* t93 ref arg0 in rdi N012 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log lowering store lcl var/field (before): N001 ( 1, 1) [000033] ------------ t33 = CNS_INT int 0 /--* t33 int N003 ( 5, 4) [000034] DA---------- * STORE_LCL_VAR struct V03 loc0 Addressing mode: Base N001 ( 3, 2) [000045] ------------ * LCL_VAR byref V00 this + 112 Removing unused node: N002 ( 1, 1) [000075] -c---------- * CNS_INT long 112 field offset Fseq[m_PayloadsTx] New addressing mode node: N003 ( 5, 4) [000076] ------------ * LEA(b+112) byref lowering call (before): N001 ( 3, 2) [000051] -c-----N---- t51 = LCL_VAR_ADDR byref V03 loc0 /--* t51 byref N003 ( 9, 7) [000057] n----------- t57 = * OBJ struct N005 ( 3, 4) [000079] ------------ t79 = LCL_FLD long V02 arg2 [+0] N006 ( 3, 4) [000080] ------------ t80 = LCL_FLD long V02 arg2 [+8] /--* t79 long +--* t80 long N007 ( 6, 8) [000078] -c---------- t78 = * FIELD_LIST struct /--* t57 struct arg0 out+00 +--* t78 struct arg1 rdi,rsi N008 ( 32, 21) [000053] --CXG------- t53 = * CALL struct Unity.Jobs.IJobExtensions.Schedule,NA objp: ====== args: ====== lowering arg : N003 ( 9, 7) [000057] n----------- * OBJ struct new node is : [000095] ------------ * PUTARG_STK [+0x00] void (12 slots) lowering arg : N004 ( 0, 0) [000077] ----------L- * ARGPLACE struct => [clsHnd=795C7A00] late: ====== lowering arg : N007 ( 6, 8) [000078] -c---------- * FIELD_LIST struct lowering call (after): N001 ( 3, 2) [000051] -c-----N---- t51 = LCL_VAR_ADDR byref V03 loc0 /--* t51 byref N003 ( 9, 7) [000057] nc---------- t57 = * OBJ struct /--* t57 struct [000095] ------------ * PUTARG_STK [+0x00] void (12 slots) (RepInstr) N005 ( 3, 4) [000079] ------------ t79 = LCL_FLD long V02 arg2 [+0] /--* t79 long [000096] ------------ t96 = * PUTARG_REG long REG rdi N006 ( 3, 4) [000080] ------------ t80 = LCL_FLD long V02 arg2 [+8] /--* t80 long [000097] ------------ t97 = * PUTARG_REG long REG rsi /--* t96 long +--* t97 long N007 ( 6, 8) [000078] -c---------- t78 = * FIELD_LIST struct /--* t78 struct arg1 rdi,rsi N008 ( 32, 21) [000053] --CXG------- t53 = * CALL struct Unity.Jobs.IJobExtensions.Schedule,NA lowering store lcl var/field (before): N001 ( 3, 2) [000051] -c-----N---- t51 = LCL_VAR_ADDR byref V03 loc0 /--* t51 byref N003 ( 9, 7) [000057] nc---------- t57 = * OBJ struct /--* t57 struct [000095] ------------ * PUTARG_STK [+0x00] void (12 slots) (RepInstr) N005 ( 3, 4) [000079] ------------ t79 = LCL_FLD long V02 arg2 [+0] /--* t79 long [000096] ------------ t96 = * PUTARG_REG long REG rdi N006 ( 3, 4) [000080] ------------ t80 = LCL_FLD long V02 arg2 [+8] /--* t80 long [000097] ------------ t97 = * PUTARG_REG long REG rsi /--* t96 long +--* t97 long N007 ( 6, 8) [000078] -c---------- t78 = * FIELD_LIST struct /--* t78 struct arg1 rdi,rsi N008 ( 32, 21) [000053] --CXG------- t53 = * CALL struct Unity.Jobs.IJobExtensions.Schedule,NA /--* t53 struct N010 ( 36, 24) [000060] DA-XG------- * STORE_LCL_VAR struct V07 tmp3 lowering store lcl var/field (after): N001 ( 3, 2) [000051] -c-----N---- t51 = LCL_VAR_ADDR byref V03 loc0 /--* t51 byref N003 ( 9, 7) [000057] nc---------- t57 = * OBJ struct /--* t57 struct [000095] ------------ * PUTARG_STK [+0x00] void (12 slots) (RepInstr) N005 ( 3, 4) [000079] ------------ t79 = LCL_FLD long V02 arg2 [+0] /--* t79 long [000096] ------------ t96 = * PUTARG_REG long REG rdi N006 ( 3, 4) [000080] ------------ t80 = LCL_FLD long V02 arg2 [+8] /--* t80 long [000097] ------------ t97 = * PUTARG_REG long REG rsi /--* t96 long +--* t97 long N007 ( 6, 8) [000078] -c---------- t78 = * FIELD_LIST struct /--* t78 struct arg1 rdi,rsi N008 ( 32, 21) [000053] --CXG------- t53 = * CALL struct Unity.Jobs.IJobExtensions.Schedule,NA /--* t53 struct N010 ( 36, 24) [000060] DA-XG------- * STORE_LCL_VAR struct V07 tmp3 lowering GT_RETURN N002 ( 4, 3) [000062] ------------ * RETURN struct ============**** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 Lower has completed modifying nodes. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} [000081] ------------ IL_OFFSET void IL offset: 0x0 N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class /--* t4 long [000088] ------------ t88 = * PUTARG_REG long REG rdi /--* t88 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t5 ref N005 ( 20, 19) [000007] DA---------- * STORE_LCL_VAR ref V05 tmp1 N001 ( 3, 2) [000008] ------------ t8 = LCL_VAR ref V05 tmp1 /--* t8 ref N003 ( 4, 3) [000010] -c---------- t10 = * LEA(b+8) byref N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD int V02 arg2 [+8] Fseq[Version] /--* t10 byref +--* t3 int [000082] -A-XG------- * STOREIND int N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class /--* t18 long [000089] ------------ t89 = * PUTARG_REG long REG rdi /--* t89 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t19 ref N005 ( 20, 19) [000021] DA---------- * STORE_LCL_VAR ref V06 tmp2 N001 ( 3, 2) [000022] ------------ t22 = LCL_VAR ref V06 tmp2 /--* t22 ref N003 ( 4, 3) [000024] -c---------- t24 = * LEA(b+8) byref N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD long V02 arg2 [+0] Fseq[JobGroup] /--* t24 byref +--* t17 long [000083] -A-XG------- * STOREIND long N005 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V05 tmp1 /--* t13 ref [000090] ------------ t90 = * PUTARG_REG ref REG rsi N007 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V06 tmp2 /--* t27 ref [000091] ------------ t91 = * PUTARG_REG ref REG rdx N009 ( 2, 10) [000065] ------------ t65 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] /--* t65 long N010 ( 4, 12) [000066] n---G------- t66 = * IND ref /--* t66 ref [000092] ----G------- t92 = * PUTARG_REG ref REG rdi /--* t90 ref arg1 in rsi +--* t91 ref arg2 in rdx +--* t92 ref arg0 in rdi N011 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format /--* t29 ref [000093] --CXG------- t93 = * PUTARG_REG ref REG rdi /--* t93 ref arg0 in rdi N012 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log [000084] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 1, 1) [000033] -c---------- t33 = CNS_INT int 0 [000094] Dc-----N---- t94 = LCL_VAR_ADDR byref V03 loc0 /--* t94 byref +--* t33 int N003 ( 5, 4) [000034] sA---------- * STORE_BLK struct (init) (Unroll) [000085] ------------ IL_OFFSET void IL offset: 0x2d N001 ( 3, 2) [000037] ------------ t37 = LCL_VAR byref V00 this N002 ( 1, 1) [000073] -c---------- t73 = CNS_INT long 16 field offset Fseq[m_Baselib] /--* t37 byref +--* t73 long N003 ( 5, 4) [000074] ------------ t74 = * ADD byref /--* t74 byref N004 ( 8, 6) [000038] *c-XG------- t38 = * IND struct N005 ( 3, 2) [000035] U------N---- t35 = LCL_VAR_ADDR byref V03 loc0 N007 ( 1, 1) [000071] -c---------- t71 = CNS_INT long 40 field offset Fseq[Baselib] /--* t35 byref +--* t71 long N008 ( 5, 5) [000072] ------------ t72 = * ADD byref /--* t72 byref +--* t38 struct N009 ( 11, 9) [000041] nA-XG------- * STORE_OBJ struct (copy) (RepInstr) [000086] ------------ IL_OFFSET void IL offset: 0x3a N001 ( 3, 2) [000045] ------------ t45 = LCL_VAR byref V00 this /--* t45 byref N003 ( 5, 4) [000076] -c---------- t76 = * LEA(b+112) byref /--* t76 byref N004 ( 8, 6) [000046] *c-XG------- t46 = * IND struct N005 ( 3, 4) [000043] Uc-----N---- t43 = LCL_FLD_ADDR byref V03 loc0 [+0] Fseq[Tx] /--* t43 byref +--* t46 struct N007 ( 6, 7) [000049] nA-XG------- * STORE_BLK struct (copy) (Unroll) [000087] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000051] -c-----N---- t51 = LCL_VAR_ADDR byref V03 loc0 /--* t51 byref N003 ( 9, 7) [000057] nc---------- t57 = * OBJ struct /--* t57 struct [000095] ------------ * PUTARG_STK [+0x00] void (12 slots) (RepInstr) N005 ( 3, 4) [000079] ------------ t79 = LCL_FLD long V02 arg2 [+0] /--* t79 long [000096] ------------ t96 = * PUTARG_REG long REG rdi N006 ( 3, 4) [000080] ------------ t80 = LCL_FLD long V02 arg2 [+8] /--* t80 long [000097] ------------ t97 = * PUTARG_REG long REG rsi /--* t96 long +--* t97 long N007 ( 6, 8) [000078] -c---------- t78 = * FIELD_LIST struct /--* t78 struct arg1 rdi,rsi N008 ( 32, 21) [000053] --CXG------- t53 = * CALL struct Unity.Jobs.IJobExtensions.Schedule,NA /--* t53 struct N010 ( 36, 24) [000060] DA-XG------- * STORE_LCL_VAR struct V07 tmp3 N001 ( 3, 2) [000061] -c-----N---- t61 = LCL_VAR struct V07 tmp3 /--* t61 struct N002 ( 4, 3) [000062] ------------ * RETURN struct ------------------------------------------------------------------------------------------------------------------- *** lvaComputeRefCounts *** *************** In fgLocalVarLiveness() ; Initial local variable assignments ; ; V00 this byref this ; V01 arg1 struct ; V02 arg2 struct do-not-enreg[SFA] multireg-arg ; V03 loc0 struct do-not-enreg[SFB] ld-addr-op ; V04 OutArgs lclBlk <96> "OutgoingArgSpace" ; V05 tmp1 ref "Reusable Box Helper" ; V06 tmp2 ref "Reusable Box Helper" ; V07 tmp3 struct multireg-ret "Return value temp for multireg return" In fgLocalVarLivenessInit *************** In fgPerBlockLocalVarLiveness() *************** In fgInterBlockLocalVarLiveness() *** lvaComputeRefCounts *** *************** Finishing PHASE Lowering nodeinfo Trees after Lowering nodeinfo ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} [000081] ------------ IL_OFFSET void IL offset: 0x0 N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class /--* t4 long [000088] ------------ t88 = * PUTARG_REG long REG rdi /--* t88 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t5 ref N005 ( 20, 19) [000007] DA---------- * STORE_LCL_VAR ref V05 tmp1 N001 ( 3, 2) [000008] ------------ t8 = LCL_VAR ref V05 tmp1 /--* t8 ref N003 ( 4, 3) [000010] -c---------- t10 = * LEA(b+8) byref N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD int V02 arg2 [+8] Fseq[Version] /--* t10 byref +--* t3 int [000082] -A-XG------- * STOREIND int N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class /--* t18 long [000089] ------------ t89 = * PUTARG_REG long REG rdi /--* t89 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t19 ref N005 ( 20, 19) [000021] DA---------- * STORE_LCL_VAR ref V06 tmp2 N001 ( 3, 2) [000022] ------------ t22 = LCL_VAR ref V06 tmp2 /--* t22 ref N003 ( 4, 3) [000024] -c---------- t24 = * LEA(b+8) byref N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD long V02 arg2 [+0] Fseq[JobGroup] /--* t24 byref +--* t17 long [000083] -A-XG------- * STOREIND long N005 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V05 tmp1 /--* t13 ref [000090] ------------ t90 = * PUTARG_REG ref REG rsi N007 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V06 tmp2 /--* t27 ref [000091] ------------ t91 = * PUTARG_REG ref REG rdx N009 ( 2, 10) [000065] ------------ t65 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] /--* t65 long N010 ( 4, 12) [000066] n---G------- t66 = * IND ref /--* t66 ref [000092] ----G------- t92 = * PUTARG_REG ref REG rdi /--* t90 ref arg1 in rsi +--* t91 ref arg2 in rdx +--* t92 ref arg0 in rdi N011 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format /--* t29 ref [000093] --CXG------- t93 = * PUTARG_REG ref REG rdi /--* t93 ref arg0 in rdi N012 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log [000084] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 1, 1) [000033] -c---------- t33 = CNS_INT int 0 [000094] Dc-----N---- t94 = LCL_VAR_ADDR byref V03 loc0 /--* t94 byref +--* t33 int N003 ( 5, 4) [000034] sA---------- * STORE_BLK struct (init) (Unroll) [000085] ------------ IL_OFFSET void IL offset: 0x2d N001 ( 3, 2) [000037] ------------ t37 = LCL_VAR byref V00 this N002 ( 1, 1) [000073] -c---------- t73 = CNS_INT long 16 field offset Fseq[m_Baselib] /--* t37 byref +--* t73 long N003 ( 5, 4) [000074] ------------ t74 = * ADD byref /--* t74 byref N004 ( 8, 6) [000038] *c-XG------- t38 = * IND struct N005 ( 3, 2) [000035] U------N---- t35 = LCL_VAR_ADDR byref V03 loc0 N007 ( 1, 1) [000071] -c---------- t71 = CNS_INT long 40 field offset Fseq[Baselib] /--* t35 byref +--* t71 long N008 ( 5, 5) [000072] ------------ t72 = * ADD byref /--* t72 byref +--* t38 struct N009 ( 11, 9) [000041] nA-XG------- * STORE_OBJ struct (copy) (RepInstr) [000086] ------------ IL_OFFSET void IL offset: 0x3a N001 ( 3, 2) [000045] ------------ t45 = LCL_VAR byref V00 this /--* t45 byref N003 ( 5, 4) [000076] -c---------- t76 = * LEA(b+112) byref /--* t76 byref N004 ( 8, 6) [000046] *c-XG------- t46 = * IND struct N005 ( 3, 4) [000043] Uc-----N---- t43 = LCL_FLD_ADDR byref V03 loc0 [+0] Fseq[Tx] /--* t43 byref +--* t46 struct N007 ( 6, 7) [000049] nA-XG------- * STORE_BLK struct (copy) (Unroll) [000087] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000051] -c-----N---- t51 = LCL_VAR_ADDR byref V03 loc0 /--* t51 byref N003 ( 9, 7) [000057] nc---------- t57 = * OBJ struct /--* t57 struct [000095] ------------ * PUTARG_STK [+0x00] void (12 slots) (RepInstr) N005 ( 3, 4) [000079] ------------ t79 = LCL_FLD long V02 arg2 [+0] /--* t79 long [000096] ------------ t96 = * PUTARG_REG long REG rdi N006 ( 3, 4) [000080] ------------ t80 = LCL_FLD long V02 arg2 [+8] /--* t80 long [000097] ------------ t97 = * PUTARG_REG long REG rsi /--* t96 long +--* t97 long N007 ( 6, 8) [000078] -c---------- t78 = * FIELD_LIST struct /--* t78 struct arg1 rdi,rsi N008 ( 32, 21) [000053] --CXG------- t53 = * CALL struct Unity.Jobs.IJobExtensions.Schedule,NA /--* t53 struct N010 ( 36, 24) [000060] DA-XG------- * STORE_LCL_VAR struct V07 tmp3 N001 ( 3, 2) [000061] -c-----N---- t61 = LCL_VAR struct V07 tmp3 /--* t61 struct N002 ( 4, 3) [000062] ------------ * RETURN struct ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Trees before Calculate stack level slots ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} [000081] ------------ IL_OFFSET void IL offset: 0x0 N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class /--* t4 long [000088] ------------ t88 = * PUTARG_REG long REG rdi /--* t88 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t5 ref N005 ( 20, 19) [000007] DA---------- * STORE_LCL_VAR ref V05 tmp1 N001 ( 3, 2) [000008] ------------ t8 = LCL_VAR ref V05 tmp1 /--* t8 ref N003 ( 4, 3) [000010] -c---------- t10 = * LEA(b+8) byref N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD int V02 arg2 [+8] Fseq[Version] /--* t10 byref +--* t3 int [000082] -A-XG------- * STOREIND int N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class /--* t18 long [000089] ------------ t89 = * PUTARG_REG long REG rdi /--* t89 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t19 ref N005 ( 20, 19) [000021] DA---------- * STORE_LCL_VAR ref V06 tmp2 N001 ( 3, 2) [000022] ------------ t22 = LCL_VAR ref V06 tmp2 /--* t22 ref N003 ( 4, 3) [000024] -c---------- t24 = * LEA(b+8) byref N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD long V02 arg2 [+0] Fseq[JobGroup] /--* t24 byref +--* t17 long [000083] -A-XG------- * STOREIND long N005 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V05 tmp1 /--* t13 ref [000090] ------------ t90 = * PUTARG_REG ref REG rsi N007 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V06 tmp2 /--* t27 ref [000091] ------------ t91 = * PUTARG_REG ref REG rdx N009 ( 2, 10) [000065] ------------ t65 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] /--* t65 long N010 ( 4, 12) [000066] n---G------- t66 = * IND ref /--* t66 ref [000092] ----G------- t92 = * PUTARG_REG ref REG rdi /--* t90 ref arg1 in rsi +--* t91 ref arg2 in rdx +--* t92 ref arg0 in rdi N011 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format /--* t29 ref [000093] --CXG------- t93 = * PUTARG_REG ref REG rdi /--* t93 ref arg0 in rdi N012 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log [000084] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 1, 1) [000033] -c---------- t33 = CNS_INT int 0 [000094] Dc-----N---- t94 = LCL_VAR_ADDR byref V03 loc0 /--* t94 byref +--* t33 int N003 ( 5, 4) [000034] sA---------- * STORE_BLK struct (init) (Unroll) [000085] ------------ IL_OFFSET void IL offset: 0x2d N001 ( 3, 2) [000037] ------------ t37 = LCL_VAR byref V00 this N002 ( 1, 1) [000073] -c---------- t73 = CNS_INT long 16 field offset Fseq[m_Baselib] /--* t37 byref +--* t73 long N003 ( 5, 4) [000074] ------------ t74 = * ADD byref /--* t74 byref N004 ( 8, 6) [000038] *c-XG------- t38 = * IND struct N005 ( 3, 2) [000035] U------N---- t35 = LCL_VAR_ADDR byref V03 loc0 N007 ( 1, 1) [000071] -c---------- t71 = CNS_INT long 40 field offset Fseq[Baselib] /--* t35 byref +--* t71 long N008 ( 5, 5) [000072] ------------ t72 = * ADD byref /--* t72 byref +--* t38 struct N009 ( 11, 9) [000041] nA-XG------- * STORE_OBJ struct (copy) (RepInstr) [000086] ------------ IL_OFFSET void IL offset: 0x3a N001 ( 3, 2) [000045] ------------ t45 = LCL_VAR byref V00 this /--* t45 byref N003 ( 5, 4) [000076] -c---------- t76 = * LEA(b+112) byref /--* t76 byref N004 ( 8, 6) [000046] *c-XG------- t46 = * IND struct N005 ( 3, 4) [000043] Uc-----N---- t43 = LCL_FLD_ADDR byref V03 loc0 [+0] Fseq[Tx] /--* t43 byref +--* t46 struct N007 ( 6, 7) [000049] nA-XG------- * STORE_BLK struct (copy) (Unroll) [000087] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000051] -c-----N---- t51 = LCL_VAR_ADDR byref V03 loc0 /--* t51 byref N003 ( 9, 7) [000057] nc---------- t57 = * OBJ struct /--* t57 struct [000095] ------------ * PUTARG_STK [+0x00] void (12 slots) (RepInstr) N005 ( 3, 4) [000079] ------------ t79 = LCL_FLD long V02 arg2 [+0] /--* t79 long [000096] ------------ t96 = * PUTARG_REG long REG rdi N006 ( 3, 4) [000080] ------------ t80 = LCL_FLD long V02 arg2 [+8] /--* t80 long [000097] ------------ t97 = * PUTARG_REG long REG rsi /--* t96 long +--* t97 long N007 ( 6, 8) [000078] -c---------- t78 = * FIELD_LIST struct /--* t78 struct arg1 rdi,rsi N008 ( 32, 21) [000053] --CXG------- t53 = * CALL struct Unity.Jobs.IJobExtensions.Schedule,NA /--* t53 struct N010 ( 36, 24) [000060] DA-XG------- * STORE_LCL_VAR struct V07 tmp3 N001 ( 3, 2) [000061] -c-----N---- t61 = LCL_VAR struct V07 tmp3 /--* t61 struct N002 ( 4, 3) [000062] ------------ * RETURN struct ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Calculate stack level slots Too many pushed arguments for an ESP based encoding, forcing an EBP frame *************** Finishing PHASE Calculate stack level slots [no changes] *************** Starting PHASE Linear scan register alloc Clearing modified regs. buildIntervals ======== ----------------- LIVENESS: ----------------- BB01 use def in out {} {} {} {} FP callee save candidate vars: None floatVarCount = 0; hasLoops = 0, singleExit = 1 TUPLE STYLE DUMP BEFORE LSRA LSRA Block Sequence: BB01( 1 ) BB01 [000..04F) (return), preds={} succs={} ===== N000. IL_OFFSET IL offset: 0x0 N002. t4 = CNS_INT(h) 0x7f6678beb1c0 class N000. t88 = PUTARG_REG; t4 N003. t5 = CALL help; t88 N005. V05 MEM; t5 N001. t8 = V05 MEM N003. t10 = LEA(b+8) ; t8 N005. t3 = V02 MEM N000. STOREIND ; t10,t3 N002. t18 = CNS_INT(h) 0x7f6678c127f0 class N000. t89 = PUTARG_REG; t18 N003. t19 = CALL help; t89 N005. V06 MEM; t19 N001. t22 = V06 MEM N003. t24 = LEA(b+8) ; t22 N005. t17 = V02 MEM N000. STOREIND ; t24,t17 N005. t13 = V05 MEM N000. t90 = PUTARG_REG; t13 N007. t27 = V06 MEM N000. t91 = PUTARG_REG; t27 N009. t65 = CNS_INT(h) 0x640084D0 [ICON_STR_HDL] N010. t66 = IND ; t65 N000. t92 = PUTARG_REG; t66 N011. t29 = CALL ; t90,t91,t92 N000. t93 = PUTARG_REG; t29 N012. CALL ; t93 N000. IL_OFFSET IL offset: 0x25 N001. CNS_INT 0 N000. LCL_VAR_ADDR V03 loc0 N003. STORE_BLK N000. IL_OFFSET IL offset: 0x2d N001. t37 = V00 MEM N002. CNS_INT 16 field offset Fseq[m_Baselib] N003. t74 = ADD ; t37 N004. t38 = IND ; t74 N005. t35 = LCL_VAR_ADDR V03 loc0 N007. CNS_INT 40 field offset Fseq[Baselib] N008. t72 = ADD ; t35 N009. STORE_OBJ; t72,t38 N000. IL_OFFSET IL offset: 0x3a N001. t45 = V00 MEM N003. t76 = LEA(b+112); t45 N004. t46 = IND ; t76 N005. LCL_FLD_ADDR V03 loc0 [+0] Fseq[Tx] N007. STORE_BLK; t46 N000. IL_OFFSET IL offset: 0x47 N001. LCL_VAR_ADDR V03 loc0 N003. OBJ N000. PUTARG_STK [+0x00] N005. t79 = V02 MEM N000. t96 = PUTARG_REG; t79 N006. t80 = V02 MEM N000. t97 = PUTARG_REG; t80 N007. t78 = FIELD_LIST; t96,t97 N008. t53 = CALL ; t78 N010. V07 MEM; t53 N001. V07 MEM N002. RETURN buildIntervals second part ======== Int arg V00 in reg rdi NEW BLOCK BB01 DefList: { } N002 (???,???) [000081] ------------ * IL_OFFSET void IL offset: 0x0 REG NA DefList: { } N004 ( 2, 10) [000004] ------------ * CNS_INT(h) long 0x7f6678beb1c0 class REG NA Interval 0: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N004.t4. CNS_INT } N006 (???,???) [000088] ------------ * PUTARG_REG long REG rdi BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> Interval 1: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> DefList: { N006.t88. PUTARG_REG } N008 ( 16, 16) [000005] --C--------- * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG NA BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> Interval 2: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> DefList: { N008.t5. CALL } N010 ( 20, 19) [000007] DA---------- * STORE_LCL_VAR ref V05 tmp1 NA REG NA BB01 regmask=[allInt] minReg=1 last> DefList: { } N012 ( 3, 2) [000008] ------------ * LCL_VAR ref V05 tmp1 NA REG NA Interval 3: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB01 regmask=[allInt] minReg=1> DefList: { N012.t8. LCL_VAR } N014 ( 4, 3) [000010] -c---------- * LEA(b+8) byref REG NA Contained DefList: { N012.t8. LCL_VAR } N016 ( 3, 4) [000003] ------------ * LCL_FLD int V02 arg2 [+8] Fseq[Version] NA REG NA Interval 4: int RefPositions {} physReg:NA Preferences=[allInt] LCL_FLD BB01 regmask=[allInt] minReg=1> DefList: { N012.t8. LCL_VAR; N016.t3. LCL_FLD } N018 (???,???) [000082] -A-XG------- * STOREIND int REG NA BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> DefList: { } N020 ( 2, 10) [000018] ------------ * CNS_INT(h) long 0x7f6678c127f0 class REG NA Interval 5: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N020.t18. CNS_INT } N022 (???,???) [000089] ------------ * PUTARG_REG long REG rdi BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> Interval 6: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> DefList: { N022.t89. PUTARG_REG } N024 ( 16, 16) [000019] --C--------- * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG NA BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> Interval 7: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> DefList: { N024.t19. CALL } N026 ( 20, 19) [000021] DA---------- * STORE_LCL_VAR ref V06 tmp2 NA REG NA BB01 regmask=[allInt] minReg=1 last> DefList: { } N028 ( 3, 2) [000022] ------------ * LCL_VAR ref V06 tmp2 NA REG NA Interval 8: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB01 regmask=[allInt] minReg=1> DefList: { N028.t22. LCL_VAR } N030 ( 4, 3) [000024] -c---------- * LEA(b+8) byref REG NA Contained DefList: { N028.t22. LCL_VAR } N032 ( 3, 4) [000017] ------------ * LCL_FLD long V02 arg2 [+0] Fseq[JobGroup] NA REG NA Interval 9: long RefPositions {} physReg:NA Preferences=[allInt] LCL_FLD BB01 regmask=[allInt] minReg=1> DefList: { N028.t22. LCL_VAR; N032.t17. LCL_FLD } N034 (???,???) [000083] -A-XG------- * STOREIND long REG NA BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> DefList: { } N036 ( 3, 2) [000013] ------------ * LCL_VAR ref V05 tmp1 NA REG NA Interval 10: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB01 regmask=[allInt] minReg=1> DefList: { N036.t13. LCL_VAR } N038 (???,???) [000090] ------------ * PUTARG_REG ref REG rsi BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> Interval 11: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> DefList: { N038.t90. PUTARG_REG } N040 ( 3, 2) [000027] ------------ * LCL_VAR ref V06 tmp2 NA REG NA Interval 12: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB01 regmask=[allInt] minReg=1> DefList: { N038.t90. PUTARG_REG; N040.t27. LCL_VAR } N042 (???,???) [000091] ------------ * PUTARG_REG ref REG rdx BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> Interval 13: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdx] minReg=1> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed> DefList: { N038.t90. PUTARG_REG; N042.t91. PUTARG_REG } N044 ( 2, 10) [000065] ------------ * CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] REG NA Interval 14: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N038.t90. PUTARG_REG; N042.t91. PUTARG_REG; N044.t65. CNS_INT } N046 ( 4, 12) [000066] n---G------- * IND ref REG NA BB01 regmask=[allInt] minReg=1 last> Interval 15: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB01 regmask=[allInt] minReg=1> DefList: { N038.t90. PUTARG_REG; N042.t91. PUTARG_REG; N046.t66. IND } N048 (???,???) [000092] ----G------- * PUTARG_REG ref REG rdi BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> Interval 16: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> DefList: { N038.t90. PUTARG_REG; N042.t91. PUTARG_REG; N048.t92. PUTARG_REG } N050 ( 36, 32) [000029] --CXG------- * CALL ref System.String.Format REG NA BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> Interval 17: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> DefList: { N050.t29. CALL } N052 (???,???) [000093] --CXG------- * PUTARG_REG ref REG rdi BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> Interval 18: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> DefList: { N052.t93. PUTARG_REG } N054 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log REG NA BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> DefList: { } N056 (???,???) [000084] ------------ * IL_OFFSET void IL offset: 0x25 REG NA DefList: { } N058 ( 1, 1) [000033] -c---------- * CNS_INT int 0 REG NA Contained DefList: { } N060 (???,???) [000094] Dc-----N---- * LCL_VAR_ADDR byref V03 loc0 NA REG NA Contained DefList: { } N062 ( 5, 4) [000034] sA---------- * STORE_BLK struct (init) (Unroll) REG NA Interval 19: float RefPositions {} physReg:NA Preferences=[allFloat] STORE_BLK BB01 regmask=[allFloat] minReg=1> STORE_BLK BB01 regmask=[allFloat] minReg=1 last> DefList: { } N064 (???,???) [000085] ------------ * IL_OFFSET void IL offset: 0x2d REG NA DefList: { } N066 ( 3, 2) [000037] ------------ * LCL_VAR byref V00 this NA REG NA Interval 20: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB01 regmask=[allInt] minReg=1> DefList: { N066.t37. LCL_VAR } N068 ( 1, 1) [000073] -c---------- * CNS_INT long 16 field offset Fseq[m_Baselib] REG NA Contained DefList: { N066.t37. LCL_VAR } N070 ( 5, 4) [000074] ------------ * ADD byref REG NA BB01 regmask=[allInt] minReg=1 last> Interval 21: byref RefPositions {} physReg:NA Preferences=[allInt] ADD BB01 regmask=[allInt] minReg=1> Assigning related to DefList: { N070.t74. ADD } N072 ( 8, 6) [000038] *c-XG------- * IND struct REG NA Contained DefList: { N070.t74. ADD } N074 ( 3, 2) [000035] U------N---- * LCL_VAR_ADDR byref V03 loc0 NA REG NA Interval 22: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR_ADDR BB01 regmask=[allInt] minReg=1> DefList: { N070.t74. ADD; N074.t35. LCL_VAR_ADDR } N076 ( 1, 1) [000071] -c---------- * CNS_INT long 40 field offset Fseq[Baselib] REG NA Contained DefList: { N070.t74. ADD; N074.t35. LCL_VAR_ADDR } N078 ( 5, 5) [000072] ------------ * ADD byref REG NA BB01 regmask=[allInt] minReg=1 last> Interval 23: byref RefPositions {} physReg:NA Preferences=[allInt] ADD BB01 regmask=[allInt] minReg=1> Assigning related to DefList: { N070.t74. ADD; N078.t72. ADD } N080 ( 11, 9) [000041] nA-XG------- * STORE_OBJ struct (copy) (RepInstr) REG NA Interval 24: int RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rcx] minReg=1> STORE_OBJ BB01 regmask=[rcx] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> STORE_OBJ BB01 regmask=[rcx] minReg=1 last fixed> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> BB01 regmask=[mm0] minReg=1> BB01 regmask=[mm1] minReg=1> BB01 regmask=[mm2] minReg=1> BB01 regmask=[mm3] minReg=1> BB01 regmask=[mm4] minReg=1> BB01 regmask=[mm5] minReg=1> BB01 regmask=[mm6] minReg=1> BB01 regmask=[mm7] minReg=1> BB01 regmask=[mm8] minReg=1> BB01 regmask=[mm9] minReg=1> BB01 regmask=[mm10] minReg=1> BB01 regmask=[mm11] minReg=1> BB01 regmask=[mm12] minReg=1> BB01 regmask=[mm13] minReg=1> BB01 regmask=[mm14] minReg=1> BB01 regmask=[mm15] minReg=1> DefList: { } N082 (???,???) [000086] ------------ * IL_OFFSET void IL offset: 0x3a REG NA DefList: { } N084 ( 3, 2) [000045] ------------ * LCL_VAR byref V00 this NA REG NA Interval 25: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB01 regmask=[allInt] minReg=1> DefList: { N084.t45. LCL_VAR } N086 ( 5, 4) [000076] -c---------- * LEA(b+112) byref REG NA Contained DefList: { N084.t45. LCL_VAR } N088 ( 8, 6) [000046] *c-XG------- * IND struct REG NA Contained DefList: { N084.t45. LCL_VAR } N090 ( 3, 4) [000043] Uc-----N---- * LCL_FLD_ADDR byref V03 loc0 [+0] Fseq[Tx] NA REG NA Contained DefList: { N084.t45. LCL_VAR } N092 ( 6, 7) [000049] nA-XG------- * STORE_BLK struct (copy) (Unroll) REG NA Interval 26: int RefPositions {} physReg:NA Preferences=[allInt] STORE_BLK BB01 regmask=[allInt] minReg=1> Interval 27: float RefPositions {} physReg:NA Preferences=[allFloat] STORE_BLK BB01 regmask=[allFloat] minReg=1> BB01 regmask=[allInt] minReg=1 last> STORE_BLK BB01 regmask=[allInt] minReg=1 last> STORE_BLK BB01 regmask=[allFloat] minReg=1 last> DefList: { } N094 (???,???) [000087] ------------ * IL_OFFSET void IL offset: 0x47 REG NA DefList: { } N096 ( 3, 2) [000051] -c-----N---- * LCL_VAR_ADDR byref V03 loc0 NA REG NA Contained DefList: { } N098 ( 9, 7) [000057] nc---------- * OBJ struct REG NA Contained DefList: { } N100 (???,???) [000095] ------------ * PUTARG_STK [+0x00] void (12 slots) (RepInstr) REG NA Interval 28: int RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_STK BB01 regmask=[rdi] minReg=1 fixed> Interval 29: int RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rcx] minReg=1> PUTARG_STK BB01 regmask=[rcx] minReg=1 fixed> Interval 30: int RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rsi] minReg=1> PUTARG_STK BB01 regmask=[rsi] minReg=1 fixed> PUTARG_STK BB01 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rsi] minReg=1 last fixed> DefList: { } N102 ( 3, 4) [000079] ------------ * LCL_FLD long V02 arg2 [+0] NA REG NA Interval 31: long RefPositions {} physReg:NA Preferences=[allInt] LCL_FLD BB01 regmask=[allInt] minReg=1> DefList: { N102.t79. LCL_FLD } N104 (???,???) [000096] ------------ * PUTARG_REG long REG rdi BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> Interval 32: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> DefList: { N104.t96. PUTARG_REG } N106 ( 3, 4) [000080] ------------ * LCL_FLD long V02 arg2 [+8] NA REG NA Interval 33: long RefPositions {} physReg:NA Preferences=[allInt] LCL_FLD BB01 regmask=[allInt] minReg=1> DefList: { N104.t96. PUTARG_REG; N106.t80. LCL_FLD } N108 (???,???) [000097] ------------ * PUTARG_REG long REG rsi BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> Interval 34: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> DefList: { N104.t96. PUTARG_REG; N108.t97. PUTARG_REG } N110 ( 6, 8) [000078] -c---------- * FIELD_LIST struct REG NA Contained DefList: { N104.t96. PUTARG_REG; N108.t97. PUTARG_REG } N112 ( 32, 21) [000053] --CXG------- * CALL struct Unity.Jobs.IJobExtensions.Schedule REG NA,NA BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> Interval 35: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rax] minReg=1> CALL[0] BB01 regmask=[rax] minReg=1 fixed> Interval 36: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdx] minReg=1> CALL[1] BB01 regmask=[rdx] minReg=1 fixed> DefList: { N112.t53. CALL; N112.t53. CALL } N114 ( 36, 24) [000060] DA-XG------- * STORE_LCL_VAR struct V07 tmp3 NA REG NA BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> DefList: { } N116 ( 3, 2) [000061] -c-----N---- * LCL_VAR struct V07 tmp3 NA REG NA Contained DefList: { } N118 ( 4, 3) [000062] ------------ * RETURN struct REG NA Linear scan intervals BEFORE VALIDATING INTERVALS: Interval 0: long (constant) RefPositions {#1@5 #3@6} physReg:NA Preferences=[rdi] Interval 1: long RefPositions {#5@7 #7@8} physReg:NA Preferences=[rdi] Interval 2: ref RefPositions {#18@9 #19@10} physReg:NA Preferences=[rax] Interval 3: ref RefPositions {#20@13 #22@18} physReg:NA Preferences=[allInt] Interval 4: int RefPositions {#21@17 #23@18} physReg:NA Preferences=[allInt] Interval 5: long (constant) RefPositions {#24@21 #26@22} physReg:NA Preferences=[rdi] Interval 6: long RefPositions {#28@23 #30@24} physReg:NA Preferences=[rdi] Interval 7: ref RefPositions {#41@25 #42@26} physReg:NA Preferences=[rax] Interval 8: ref RefPositions {#43@29 #45@34} physReg:NA Preferences=[allInt] Interval 9: long RefPositions {#44@33 #46@34} physReg:NA Preferences=[allInt] Interval 10: ref RefPositions {#47@37 #49@38} physReg:NA Preferences=[rsi] Interval 11: ref RefPositions {#51@39 #65@50} physReg:NA Preferences=[rsi] Interval 12: ref RefPositions {#52@41 #54@42} physReg:NA Preferences=[rdx] Interval 13: ref RefPositions {#56@43 #67@50} physReg:NA Preferences=[rdx] Interval 14: long (constant) RefPositions {#57@45 #58@46} physReg:NA Preferences=[allInt] Interval 15: ref RefPositions {#59@47 #61@48} physReg:NA Preferences=[rdi] Interval 16: ref RefPositions {#63@49 #69@50} physReg:NA Preferences=[rdi] Interval 17: ref (def-use conflict) RefPositions {#80@51 #82@52} physReg:NA Preferences=[rax rdi] Interval 18: ref RefPositions {#84@53 #86@54} physReg:NA Preferences=[rdi] Interval 19: float (INTERNAL) RefPositions {#96@62 #97@62} physReg:NA Preferences=[allFloat] Interval 20: byref RefPositions {#98@67 #99@70} physReg:NA Preferences=[allInt] RelatedInterval Interval 21: byref RefPositions {#100@71 #109@80} physReg:NA Preferences=[rsi] Interval 22: byref RefPositions {#101@75 #102@78} physReg:NA Preferences=[allInt] RelatedInterval Interval 23: byref RefPositions {#103@79 #107@80} physReg:NA Preferences=[rdi] Interval 24: int (INTERNAL) RefPositions {#105@80 #110@80} physReg:NA Preferences=[rcx] Interval 25: byref RefPositions {#136@85 #139@92} physReg:NA Preferences=[allInt] Interval 26: int (INTERNAL) RefPositions {#137@92 #140@92} physReg:NA Preferences=[allInt] Interval 27: float (INTERNAL) RefPositions {#138@92 #141@92} physReg:NA Preferences=[allFloat] Interval 28: int (INTERNAL) RefPositions {#143@100 #148@100} physReg:NA Preferences=[rdi] Interval 29: int (INTERNAL) RefPositions {#145@100 #149@100} physReg:NA Preferences=[rcx] Interval 30: int (INTERNAL) RefPositions {#147@100 #150@100} physReg:NA Preferences=[rsi] Interval 31: long RefPositions {#151@103 #153@104} physReg:NA Preferences=[rdi] Interval 32: long RefPositions {#155@105 #162@112} physReg:NA Preferences=[rdi] Interval 33: long RefPositions {#156@107 #158@108} physReg:NA Preferences=[rsi] Interval 34: long RefPositions {#160@109 #164@112} physReg:NA Preferences=[rsi] Interval 35: long RefPositions {#175@113 #178@114} physReg:NA Preferences=[rax] Interval 36: long RefPositions {#177@113 #179@114} physReg:NA Preferences=[rdx] ------------ REFPOSITIONS BEFORE VALIDATING INTERVALS: ------------ CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_FLD BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_FLD BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> LCL_VAR BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> BB01 regmask=[rdx] minReg=1> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> IND BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> STORE_BLK BB01 regmask=[allFloat] minReg=1> STORE_BLK BB01 regmask=[allFloat] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> ADD BB01 regmask=[rsi] minReg=1> LCL_VAR_ADDR BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> ADD BB01 regmask=[rdi] minReg=1> BB01 regmask=[rcx] minReg=1> STORE_OBJ BB01 regmask=[rcx] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> STORE_OBJ BB01 regmask=[rcx] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[mm0] minReg=1 last> BB01 regmask=[mm1] minReg=1 last> BB01 regmask=[mm2] minReg=1 last> BB01 regmask=[mm3] minReg=1 last> BB01 regmask=[mm4] minReg=1 last> BB01 regmask=[mm5] minReg=1 last> BB01 regmask=[mm6] minReg=1 last> BB01 regmask=[mm7] minReg=1 last> BB01 regmask=[mm8] minReg=1 last> BB01 regmask=[mm9] minReg=1 last> BB01 regmask=[mm10] minReg=1 last> BB01 regmask=[mm11] minReg=1 last> BB01 regmask=[mm12] minReg=1 last> BB01 regmask=[mm13] minReg=1 last> BB01 regmask=[mm14] minReg=1 last> BB01 regmask=[mm15] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1> STORE_BLK BB01 regmask=[allInt] minReg=1> STORE_BLK BB01 regmask=[allFloat] minReg=1> BB01 regmask=[allInt] minReg=1 last> STORE_BLK BB01 regmask=[allInt] minReg=1 last> STORE_BLK BB01 regmask=[allFloat] minReg=1 last> BB01 regmask=[rdi] minReg=1> PUTARG_STK BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rcx] minReg=1> PUTARG_STK BB01 regmask=[rcx] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> PUTARG_STK BB01 regmask=[rsi] minReg=1 fixed> PUTARG_STK BB01 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rsi] minReg=1 last fixed> LCL_FLD BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> LCL_FLD BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL[0] BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rdx] minReg=1> CALL[1] BB01 regmask=[rdx] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> TUPLE STYLE DUMP WITH REF POSITIONS Incoming Parameters: BB01 [000..04F) (return), preds={} succs={} ===== N002. IL_OFFSET IL offset: 0x0 N004. CNS_INT(h) 0x7f6678beb1c0 class Def:(#1) N006. PUTARG_REG Use:(#3) Fixed:rdi(#2) * Def:(#5) rdi N008. CALL help Use:(#7) Fixed:rdi(#6) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#18) rax N010. V05 MEM Use:(#19) * N012. V05 MEM Def:(#20) N014. LEA(b+8) N016. V02 MEM Def:(#21) N018. STOREIND Use:(#22) * Use:(#23) * N020. CNS_INT(h) 0x7f6678c127f0 class Def:(#24) N022. PUTARG_REG Use:(#26) Fixed:rdi(#25) * Def:(#28) rdi N024. CALL help Use:(#30) Fixed:rdi(#29) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#41) rax N026. V06 MEM Use:(#42) * N028. V06 MEM Def:(#43) N030. LEA(b+8) N032. V02 MEM Def:(#44) N034. STOREIND Use:(#45) * Use:(#46) * N036. V05 MEM Def:(#47) N038. PUTARG_REG Use:(#49) Fixed:rsi(#48) * Def:(#51) rsi N040. V06 MEM Def:(#52) N042. PUTARG_REG Use:(#54) Fixed:rdx(#53) * Def:(#56) rdx N044. CNS_INT(h) 0x640084D0 [ICON_STR_HDL] Def:(#57) N046. IND Use:(#58) * Def:(#59) N048. PUTARG_REG Use:(#61) Fixed:rdi(#60) * Def:(#63) rdi N050. CALL Use:(#65) Fixed:rsi(#64) * Use:(#67) Fixed:rdx(#66) * Use:(#69) Fixed:rdi(#68) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#80) rax N052. PUTARG_REG Use:(#82) Fixed:rdi(#81) * Def:(#84) rdi N054. CALL Use:(#86) Fixed:rdi(#85) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 N056. IL_OFFSET IL offset: 0x25 N058. CNS_INT 0 N060. LCL_VAR_ADDR V03 loc0 NA N062. STORE_BLK Def:(#96) Use:(#97) * N064. IL_OFFSET IL offset: 0x2d N066. V00 MEM Def:(#98) Pref: N068. CNS_INT 16 field offset Fseq[m_Baselib] N070. ADD Use:(#99) * Def:(#100) N072. IND N074. LCL_VAR_ADDR V03 loc0 NA Def:(#101) Pref: N076. CNS_INT 40 field offset Fseq[Baselib] N078. ADD Use:(#102) * Def:(#103) N080. STORE_OBJ Def:(#105) rcx Use:(#107) Fixed:rdi(#106) * Use:(#109) Fixed:rsi(#108) * Use:(#110) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 mm0 mm1 mm2 mm3 mm4 mm5 mm6 mm7 mm8 mm9 mm10 mm11 mm12 mm13 mm14 mm15 N082. IL_OFFSET IL offset: 0x3a N084. V00 MEM Def:(#136) N086. LEA(b+112) N088. IND N090. LCL_FLD_ADDR V03 loc0 [+0] Fseq[Tx] NA N092. STORE_BLK Def:(#137) Def:(#138) Use:(#139) * Use:(#140) * Use:(#141) * N094. IL_OFFSET IL offset: 0x47 N096. LCL_VAR_ADDR V03 loc0 NA N098. OBJ N100. PUTARG_STK [+0x00] Def:(#143) rdi Def:(#145) rcx Def:(#147) rsi Use:(#148) * Use:(#149) * Use:(#150) * N102. V02 MEM Def:(#151) N104. PUTARG_REG Use:(#153) Fixed:rdi(#152) * Def:(#155) rdi N106. V02 MEM Def:(#156) N108. PUTARG_REG Use:(#158) Fixed:rsi(#157) * Def:(#160) rsi N110. FIELD_LIST N112. CALL Use:(#162) Fixed:rdi(#161) * Use:(#164) Fixed:rsi(#163) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#175) rax Def:(#177) rdx N114. V07 MEM Use:(#178) * Use:(#179) * N116. V07 MEM N118. RETURN Linear scan intervals after buildIntervals: Interval 0: long (constant) RefPositions {#1@5 #3@6} physReg:NA Preferences=[rdi] Interval 1: long RefPositions {#5@7 #7@8} physReg:NA Preferences=[rdi] Interval 2: ref RefPositions {#18@9 #19@10} physReg:NA Preferences=[rax] Interval 3: ref RefPositions {#20@13 #22@18} physReg:NA Preferences=[allInt] Interval 4: int RefPositions {#21@17 #23@18} physReg:NA Preferences=[allInt] Interval 5: long (constant) RefPositions {#24@21 #26@22} physReg:NA Preferences=[rdi] Interval 6: long RefPositions {#28@23 #30@24} physReg:NA Preferences=[rdi] Interval 7: ref RefPositions {#41@25 #42@26} physReg:NA Preferences=[rax] Interval 8: ref RefPositions {#43@29 #45@34} physReg:NA Preferences=[allInt] Interval 9: long RefPositions {#44@33 #46@34} physReg:NA Preferences=[allInt] Interval 10: ref RefPositions {#47@37 #49@38} physReg:NA Preferences=[rsi] Interval 11: ref RefPositions {#51@39 #65@50} physReg:NA Preferences=[rsi] Interval 12: ref RefPositions {#52@41 #54@42} physReg:NA Preferences=[rdx] Interval 13: ref RefPositions {#56@43 #67@50} physReg:NA Preferences=[rdx] Interval 14: long (constant) RefPositions {#57@45 #58@46} physReg:NA Preferences=[allInt] Interval 15: ref RefPositions {#59@47 #61@48} physReg:NA Preferences=[rdi] Interval 16: ref RefPositions {#63@49 #69@50} physReg:NA Preferences=[rdi] Interval 17: ref (def-use conflict) RefPositions {#80@51 #82@52} physReg:NA Preferences=[rax rdi] Interval 18: ref RefPositions {#84@53 #86@54} physReg:NA Preferences=[rdi] Interval 19: float (INTERNAL) RefPositions {#96@62 #97@62} physReg:NA Preferences=[allFloat] Interval 20: byref RefPositions {#98@67 #99@70} physReg:NA Preferences=[allInt] RelatedInterval Interval 21: byref RefPositions {#100@71 #109@80} physReg:NA Preferences=[rsi] Interval 22: byref RefPositions {#101@75 #102@78} physReg:NA Preferences=[allInt] RelatedInterval Interval 23: byref RefPositions {#103@79 #107@80} physReg:NA Preferences=[rdi] Interval 24: int (INTERNAL) RefPositions {#105@80 #110@80} physReg:NA Preferences=[rcx] Interval 25: byref RefPositions {#136@85 #139@92} physReg:NA Preferences=[allInt] Interval 26: int (INTERNAL) RefPositions {#137@92 #140@92} physReg:NA Preferences=[allInt] Interval 27: float (INTERNAL) RefPositions {#138@92 #141@92} physReg:NA Preferences=[allFloat] Interval 28: int (INTERNAL) RefPositions {#143@100 #148@100} physReg:NA Preferences=[rdi] Interval 29: int (INTERNAL) RefPositions {#145@100 #149@100} physReg:NA Preferences=[rcx] Interval 30: int (INTERNAL) RefPositions {#147@100 #150@100} physReg:NA Preferences=[rsi] Interval 31: long RefPositions {#151@103 #153@104} physReg:NA Preferences=[rdi] Interval 32: long RefPositions {#155@105 #162@112} physReg:NA Preferences=[rdi] Interval 33: long RefPositions {#156@107 #158@108} physReg:NA Preferences=[rsi] Interval 34: long RefPositions {#160@109 #164@112} physReg:NA Preferences=[rsi] Interval 35: long RefPositions {#175@113 #178@114} physReg:NA Preferences=[rax] Interval 36: long RefPositions {#177@113 #179@114} physReg:NA Preferences=[rdx] *************** In LinearScan::allocateRegisters() Linear scan intervals before allocateRegisters: Interval 0: long (constant) RefPositions {#1@5 #3@6} physReg:NA Preferences=[rdi] Interval 1: long RefPositions {#5@7 #7@8} physReg:NA Preferences=[rdi] Interval 2: ref RefPositions {#18@9 #19@10} physReg:NA Preferences=[rax] Interval 3: ref RefPositions {#20@13 #22@18} physReg:NA Preferences=[allInt] Interval 4: int RefPositions {#21@17 #23@18} physReg:NA Preferences=[allInt] Interval 5: long (constant) RefPositions {#24@21 #26@22} physReg:NA Preferences=[rdi] Interval 6: long RefPositions {#28@23 #30@24} physReg:NA Preferences=[rdi] Interval 7: ref RefPositions {#41@25 #42@26} physReg:NA Preferences=[rax] Interval 8: ref RefPositions {#43@29 #45@34} physReg:NA Preferences=[allInt] Interval 9: long RefPositions {#44@33 #46@34} physReg:NA Preferences=[allInt] Interval 10: ref RefPositions {#47@37 #49@38} physReg:NA Preferences=[rsi] Interval 11: ref RefPositions {#51@39 #65@50} physReg:NA Preferences=[rsi] Interval 12: ref RefPositions {#52@41 #54@42} physReg:NA Preferences=[rdx] Interval 13: ref RefPositions {#56@43 #67@50} physReg:NA Preferences=[rdx] Interval 14: long (constant) RefPositions {#57@45 #58@46} physReg:NA Preferences=[allInt] Interval 15: ref RefPositions {#59@47 #61@48} physReg:NA Preferences=[rdi] Interval 16: ref RefPositions {#63@49 #69@50} physReg:NA Preferences=[rdi] Interval 17: ref (def-use conflict) RefPositions {#80@51 #82@52} physReg:NA Preferences=[rax rdi] Interval 18: ref RefPositions {#84@53 #86@54} physReg:NA Preferences=[rdi] Interval 19: float (INTERNAL) RefPositions {#96@62 #97@62} physReg:NA Preferences=[allFloat] Interval 20: byref RefPositions {#98@67 #99@70} physReg:NA Preferences=[allInt] RelatedInterval Interval 21: byref RefPositions {#100@71 #109@80} physReg:NA Preferences=[rsi] Interval 22: byref RefPositions {#101@75 #102@78} physReg:NA Preferences=[allInt] RelatedInterval Interval 23: byref RefPositions {#103@79 #107@80} physReg:NA Preferences=[rdi] Interval 24: int (INTERNAL) RefPositions {#105@80 #110@80} physReg:NA Preferences=[rcx] Interval 25: byref RefPositions {#136@85 #139@92} physReg:NA Preferences=[allInt] Interval 26: int (INTERNAL) RefPositions {#137@92 #140@92} physReg:NA Preferences=[allInt] Interval 27: float (INTERNAL) RefPositions {#138@92 #141@92} physReg:NA Preferences=[allFloat] Interval 28: int (INTERNAL) RefPositions {#143@100 #148@100} physReg:NA Preferences=[rdi] Interval 29: int (INTERNAL) RefPositions {#145@100 #149@100} physReg:NA Preferences=[rcx] Interval 30: int (INTERNAL) RefPositions {#147@100 #150@100} physReg:NA Preferences=[rsi] Interval 31: long RefPositions {#151@103 #153@104} physReg:NA Preferences=[rdi] Interval 32: long RefPositions {#155@105 #162@112} physReg:NA Preferences=[rdi] Interval 33: long RefPositions {#156@107 #158@108} physReg:NA Preferences=[rsi] Interval 34: long RefPositions {#160@109 #164@112} physReg:NA Preferences=[rsi] Interval 35: long RefPositions {#175@113 #178@114} physReg:NA Preferences=[rax] Interval 36: long RefPositions {#177@113 #179@114} physReg:NA Preferences=[rdx] ------------ REFPOSITIONS BEFORE ALLOCATION: ------------ CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_FLD BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_FLD BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> LCL_VAR BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> BB01 regmask=[rdx] minReg=1> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> IND BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> STORE_BLK BB01 regmask=[allFloat] minReg=1> STORE_BLK BB01 regmask=[allFloat] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> ADD BB01 regmask=[rsi] minReg=1> LCL_VAR_ADDR BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> ADD BB01 regmask=[rdi] minReg=1> BB01 regmask=[rcx] minReg=1> STORE_OBJ BB01 regmask=[rcx] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> STORE_OBJ BB01 regmask=[rcx] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[mm0] minReg=1 last> BB01 regmask=[mm1] minReg=1 last> BB01 regmask=[mm2] minReg=1 last> BB01 regmask=[mm3] minReg=1 last> BB01 regmask=[mm4] minReg=1 last> BB01 regmask=[mm5] minReg=1 last> BB01 regmask=[mm6] minReg=1 last> BB01 regmask=[mm7] minReg=1 last> BB01 regmask=[mm8] minReg=1 last> BB01 regmask=[mm9] minReg=1 last> BB01 regmask=[mm10] minReg=1 last> BB01 regmask=[mm11] minReg=1 last> BB01 regmask=[mm12] minReg=1 last> BB01 regmask=[mm13] minReg=1 last> BB01 regmask=[mm14] minReg=1 last> BB01 regmask=[mm15] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1> STORE_BLK BB01 regmask=[allInt] minReg=1> STORE_BLK BB01 regmask=[allFloat] minReg=1> BB01 regmask=[allInt] minReg=1 last> STORE_BLK BB01 regmask=[allInt] minReg=1 last> STORE_BLK BB01 regmask=[allFloat] minReg=1 last> BB01 regmask=[rdi] minReg=1> PUTARG_STK BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rcx] minReg=1> PUTARG_STK BB01 regmask=[rcx] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> PUTARG_STK BB01 regmask=[rsi] minReg=1 fixed> PUTARG_STK BB01 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rsi] minReg=1 last fixed> LCL_FLD BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> LCL_FLD BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL[0] BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rdx] minReg=1> CALL[1] BB01 regmask=[rdx] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> Allocating Registers -------------------- The following table has one or more rows for each RefPosition that is handled during allocation. The first column provides the basic information about the RefPosition, with its type (e.g. Def, Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the action taken during allocation (e.g. Alloc a new register, or Keep an existing one). The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which may increase during allocation, in which case additional columns will appear. Registers which are not marked modified have ---- in their column. --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ | | | | | | | | | | | 0.#0 BB1 PredBB0 | | | | | | | | | | | 5.#1 C0 Def Alloc rdi | | | | | |C0 a| | | | | 6.#2 rdi Fixd Keep rdi | | | | | |C0 a| | | | | 6.#3 C0 Use * Keep rdi | | | | | |C0 a| | | | | 7.#4 rdi Fixd Keep rdi | | | | | | | | | | | 7.#5 I1 Def Alloc rdi | | | | | |I1 a| | | | | 8.#6 rdi Fixd Keep rdi | | | | | |I1 a| | | | | 8.#7 I1 Use * Keep rdi | | | | | |I1 a| | | | | 9.#8 rax Kill Keep rax | | | | | | | | | | | 9.#9 rcx Kill Keep rcx | | | | | | | | | | | 9.#10 rdx Kill Keep rdx | | | | | | | | | | | 9.#11 rsi Kill Keep rsi | | | | | | | | | | | 9.#12 rdi Kill Keep rdi | | | | | | | | | | | 9.#13 r8 Kill Keep r8 | | | | | | | | | | | 9.#14 r9 Kill Keep r9 | | | | | | | | | | | 9.#15 r10 Kill Keep r10 | | | | | | | | | | | 9.#16 r11 Kill Keep r11 | | | | | | | | | | | 9.#17 rax Fixd Keep rax | | | | | | | | | | | 9.#18 I2 Def Alloc rax |I2 a| | | | | | | | | | 10.#19 I2 Use * Keep rax |I2 a| | | | | | | | | | 13.#20 I3 Def Alloc rdi | | | | | |I3 a| | | | | 17.#21 I4 Def Alloc rax |I4 a| | | | |I3 a| | | | | 18.#22 I3 Use * Keep rdi |I4 a| | | | |I3 a| | | | | 18.#23 I4 Use * Keep rax |I4 a| | | | |I3 a| | | | | 21.#24 C5 Def Alloc rdi | | | | | |C5 a| | | | | 22.#25 rdi Fixd Keep rdi | | | | | |C5 a| | | | | 22.#26 C5 Use * Keep rdi | | | | | |C5 a| | | | | 23.#27 rdi Fixd Keep rdi | | | | | | | | | | | 23.#28 I6 Def Alloc rdi | | | | | |I6 a| | | | | 24.#29 rdi Fixd Keep rdi | | | | | |I6 a| | | | | 24.#30 I6 Use * Keep rdi | | | | | |I6 a| | | | | 25.#31 rax Kill Keep rax | | | | | | | | | | | 25.#32 rcx Kill Keep rcx | | | | | | | | | | | 25.#33 rdx Kill Keep rdx | | | | | | | | | | | 25.#34 rsi Kill Keep rsi | | | | | | | | | | | 25.#35 rdi Kill Keep rdi | | | | | | | | | | | 25.#36 r8 Kill Keep r8 | | | | | | | | | | | 25.#37 r9 Kill Keep r9 | | | | | | | | | | | 25.#38 r10 Kill Keep r10 | | | | | | | | | | | 25.#39 r11 Kill Keep r11 | | | | | | | | | | | 25.#40 rax Fixd Keep rax | | | | | | | | | | | 25.#41 I7 Def Alloc rax |I7 a| | | | | | | | | | 26.#42 I7 Use * Keep rax |I7 a| | | | | | | | | | 29.#43 I8 Def Alloc rsi | | | | |I8 a| | | | | | 33.#44 I9 Def Alloc rdx | | |I9 a| |I8 a| | | | | | 34.#45 I8 Use * Keep rsi | | |I9 a| |I8 a| | | | | | 34.#46 I9 Use * Keep rdx | | |I9 a| |I8 a| | | | | | 37.#47 I10 Def Alloc rsi | | | | |I10a| | | | | | 38.#48 rsi Fixd Keep rsi | | | | |I10a| | | | | | 38.#49 I10 Use * Keep rsi | | | | |I10a| | | | | | 39.#50 rsi Fixd Keep rsi | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 39.#51 I11 Def Alloc rsi | | | | |I11a| | | | | | 41.#52 I12 Def Alloc rdx | | |I12a| |I11a| | | | | | 42.#53 rdx Fixd Keep rdx | | |I12a| |I11a| | | | | | 42.#54 I12 Use * Keep rdx | | |I12a| |I11a| | | | | | 43.#55 rdx Fixd Keep rdx | | | | |I11a| | | | | | 43.#56 I13 Def Alloc rdx | | |I13a| |I11a| | | | | | 45.#57 C14 Def Alloc rdi | | |I13a| |I11a|C14a| | | | | 46.#58 C14 Use * Keep rdi | | |I13a| |I11a|C14a| | | | | 47.#59 I15 Def Alloc rdi | | |I13a| |I11a|I15a| | | | | 48.#60 rdi Fixd Keep rdi | | |I13a| |I11a|I15a| | | | | 48.#61 I15 Use * Keep rdi | | |I13a| |I11a|I15a| | | | | 49.#62 rdi Fixd Keep rdi | | |I13a| |I11a| | | | | | 49.#63 I16 Def Alloc rdi | | |I13a| |I11a|I16a| | | | | 50.#64 rsi Fixd Keep rsi | | |I13a| |I11a|I16a| | | | | 50.#65 I11 Use * Keep rsi | | |I13a| |I11a|I16a| | | | | 50.#66 rdx Fixd Keep rdx | | |I13a| |I11a|I16a| | | | | 50.#67 I13 Use * Keep rdx | | |I13a| |I11a|I16a| | | | | 50.#68 rdi Fixd Keep rdi | | |I13a| |I11a|I16a| | | | | 50.#69 I16 Use * Keep rdi | | |I13a| |I11a|I16a| | | | | 51.#70 rax Kill Keep rax | | | | | | | | | | | 51.#71 rcx Kill Keep rcx | | | | | | | | | | | 51.#72 rdx Kill Keep rdx | | | | | | | | | | | 51.#73 rsi Kill Keep rsi | | | | | | | | | | | 51.#74 rdi Kill Keep rdi | | | | | | | | | | | 51.#75 r8 Kill Keep r8 | | | | | | | | | | | 51.#76 r9 Kill Keep r9 | | | | | | | | | | | 51.#77 r10 Kill Keep r10 | | | | | | | | | | | 51.#78 r11 Kill Keep r11 | | | | | | | | | | | 51.#79 rax Fixd Keep rax | | | | | | | | | | | 51.#80 I17 Def DUconflict | | | | | | | | | | | Case #6 need a copy | | | | | | | | | | | Alloc rax |I17a| | | | | | | | | | 52.#81 rdi Fixd Keep rdi |I17a| | | | | | | | | | 52.#82 I17 Use * Copy rdi |I17a| | | | |I17a| | | | | 53.#83 rdi Fixd Keep rdi | | | | | | | | | | | 53.#84 I18 Def Alloc rdi | | | | | |I18a| | | | | 54.#85 rdi Fixd Keep rdi | | | | | |I18a| | | | | 54.#86 I18 Use * Keep rdi | | | | | |I18a| | | | | 55.#87 rax Kill Keep rax | | | | | | | | | | | 55.#88 rcx Kill Keep rcx | | | | | | | | | | | 55.#89 rdx Kill Keep rdx | | | | | | | | | | | 55.#90 rsi Kill Keep rsi | | | | | | | | | | | 55.#91 rdi Kill Keep rdi | | | | | | | | | | | 55.#92 r8 Kill Keep r8 | | | | | | | | | | | 55.#93 r9 Kill Keep r9 | | | | | | | | | | | 55.#94 r10 Kill Keep r10 | | | | | | | | | | | 55.#95 r11 Kill Keep r11 | | | | | | | | | | | 62.#96 I19 Def Alloc mm0 | | | | | | | | | | | 62.#97 I19 Use * Keep mm0 | | | | | | | | | | | 67.#98 I20 Def Alloc rsi | | | | |I20a| | | | | | 70.#99 I20 Use * Keep rsi | | | | |I20a| | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 71.#100 I21 Def Alloc rsi | | | | |I21a| | | | | | 75.#101 I22 Def Alloc rdi | | | | |I21a|I22a| | | | | 78.#102 I22 Use * Keep rdi | | | | |I21a|I22a| | | | | 79.#103 I23 Def Alloc rdi | | | | |I21a|I23a| | | | | 80.#104 rcx Fixd Keep rcx | | | | |I21a|I23a| | | | | 80.#105 I24 Def Alloc rcx | |I24a| | |I21a|I23a| | | | | 80.#106 rdi Fixd Keep rdi | |I24a| | |I21a|I23a| | | | | 80.#107 I23 Use * Keep rdi | |I24a| | |I21a|I23a| | | | | 80.#108 rsi Fixd Keep rsi | |I24a| | |I21a|I23a| | | | | 80.#109 I21 Use * Keep rsi | |I24a| | |I21a|I23a| | | | | 80.#110 I24 Use * Keep rcx | |I24a| | |I21a|I23a| | | | | 81.#111 rax Kill Keep rax | | | | | | | | | | | 81.#112 rcx Kill Keep rcx | | | | | | | | | | | 81.#113 rdx Kill Keep rdx | | | | | | | | | | | 81.#114 rsi Kill Keep rsi | | | | | | | | | | | 81.#115 rdi Kill Keep rdi | | | | | | | | | | | 81.#116 r8 Kill Keep r8 | | | | | | | | | | | 81.#117 r9 Kill Keep r9 | | | | | | | | | | | 81.#118 r10 Kill Keep r10 | | | | | | | | | | | 81.#119 r11 Kill Keep r11 | | | | | | | | | | | 81.#120 mm0 Kill Keep mm0 | | | | | | | | | | | 81.#121 mm1 Kill Keep mm1 | | | | | | | | | | | 81.#122 mm2 Kill Keep mm2 | | | | | | | | | | | 81.#123 mm3 Kill Keep mm3 | | | | | | | | | | | 81.#124 mm4 Kill Keep mm4 | | | | | | | | | | | 81.#125 mm5 Kill Keep mm5 | | | | | | | | | | | 81.#126 mm6 Kill Keep mm6 | | | | | | | | | | | 81.#127 mm7 Kill Keep mm7 | | | | | | | | | | | 81.#128 mm8 Kill Keep mm8 | | | | | | | | | | | 81.#129 mm9 Kill Keep mm9 | | | | | | | | | | | 81.#130 mm10 Kill Keep mm10 | | | | | | | | | | | 81.#131 mm11 Kill Keep mm11 | | | | | | | | | | | 81.#132 mm12 Kill Keep mm12 | | | | | | | | | | | 81.#133 mm13 Kill Keep mm13 | | | | | | | | | | | 81.#134 mm14 Kill Keep mm14 | | | | | | | | | | | 81.#135 mm15 Kill Keep mm15 | | | | | | | | | | | 85.#136 I25 Def Alloc rdi | | | | | |I25a| | | | | 92.#137 I26 Def Alloc rsi | | | | |I26a|I25a| | | | | 92.#138 I27 Def Alloc mm0 | | | | |I26a|I25a| | | | | 92.#139 I25 Use * Keep rdi | | | | |I26a|I25a| | | | | 92.#140 I26 Use * Keep rsi | | | | |I26a|I25a| | | | | 92.#141 I27 Use * Keep mm0 | | | | |I26a|I25a| | | | | 100.#142 rdi Fixd Keep rdi | | | | | | | | | | | 100.#143 I28 Def Alloc rdi | | | | | |I28a| | | | | 100.#144 rcx Fixd Keep rcx | | | | | |I28a| | | | | 100.#145 I29 Def Alloc rcx | |I29a| | | |I28a| | | | | 100.#146 rsi Fixd Keep rsi | |I29a| | | |I28a| | | | | 100.#147 I30 Def Alloc rsi | |I29a| | |I30a|I28a| | | | | 100.#148 I28 Use * Keep rdi | |I29a| | |I30a|I28a| | | | | 100.#149 I29 Use * Keep rcx | |I29a| | |I30a|I28a| | | | | 100.#150 I30 Use * Keep rsi | |I29a| | |I30a|I28a| | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 103.#151 I31 Def Alloc rdi | | | | | |I31a| | | | | 104.#152 rdi Fixd Keep rdi | | | | | |I31a| | | | | 104.#153 I31 Use * Keep rdi | | | | | |I31a| | | | | 105.#154 rdi Fixd Keep rdi | | | | | | | | | | | 105.#155 I32 Def Alloc rdi | | | | | |I32a| | | | | 107.#156 I33 Def Alloc rsi | | | | |I33a|I32a| | | | | 108.#157 rsi Fixd Keep rsi | | | | |I33a|I32a| | | | | 108.#158 I33 Use * Keep rsi | | | | |I33a|I32a| | | | | 109.#159 rsi Fixd Keep rsi | | | | | |I32a| | | | | 109.#160 I34 Def Alloc rsi | | | | |I34a|I32a| | | | | 112.#161 rdi Fixd Keep rdi | | | | |I34a|I32a| | | | | 112.#162 I32 Use * Keep rdi | | | | |I34a|I32a| | | | | 112.#163 rsi Fixd Keep rsi | | | | |I34a|I32a| | | | | 112.#164 I34 Use * Keep rsi | | | | |I34a|I32a| | | | | 113.#165 rax Kill Keep rax | | | | | | | | | | | 113.#166 rcx Kill Keep rcx | | | | | | | | | | | 113.#167 rdx Kill Keep rdx | | | | | | | | | | | 113.#168 rsi Kill Keep rsi | | | | | | | | | | | 113.#169 rdi Kill Keep rdi | | | | | | | | | | | 113.#170 r8 Kill Keep r8 | | | | | | | | | | | 113.#171 r9 Kill Keep r9 | | | | | | | | | | | 113.#172 r10 Kill Keep r10 | | | | | | | | | | | 113.#173 r11 Kill Keep r11 | | | | | | | | | | | 113.#174 rax Fixd Keep rax | | | | | | | | | | | 113.#175 I35 Def Alloc rax |I35a| | | | | | | | | | 113.#176 rdx Fixd Keep rdx |I35a| | | | | | | | | | 113.#177 I36 Def Alloc rdx |I35a| |I36a| | | | | | | | 114.#178 I35 Use * Keep rax |I35a| |I36a| | | | | | | | 114.#179 I36 Use * Keep rdx | | | | | | | | | | | ------------ REFPOSITIONS AFTER ALLOCATION: ------------ CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rax] minReg=1 last> LCL_VAR BB01 regmask=[rdi] minReg=1> LCL_FLD BB01 regmask=[rax] minReg=1> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[rax] minReg=1 last> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rax] minReg=1 last> LCL_VAR BB01 regmask=[rsi] minReg=1> LCL_FLD BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> LCL_VAR BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> LCL_VAR BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> BB01 regmask=[rdx] minReg=1> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last> IND BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last move fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> STORE_BLK BB01 regmask=[mm0] minReg=1> STORE_BLK BB01 regmask=[mm0] minReg=1 last> LCL_VAR BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last> ADD BB01 regmask=[rsi] minReg=1> LCL_VAR_ADDR BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last> ADD BB01 regmask=[rdi] minReg=1> BB01 regmask=[rcx] minReg=1> STORE_OBJ BB01 regmask=[rcx] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> STORE_OBJ BB01 regmask=[rcx] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[mm0] minReg=1 last> BB01 regmask=[mm1] minReg=1 last> BB01 regmask=[mm2] minReg=1 last> BB01 regmask=[mm3] minReg=1 last> BB01 regmask=[mm4] minReg=1 last> BB01 regmask=[mm5] minReg=1 last> BB01 regmask=[mm6] minReg=1 last> BB01 regmask=[mm7] minReg=1 last> BB01 regmask=[mm8] minReg=1 last> BB01 regmask=[mm9] minReg=1 last> BB01 regmask=[mm10] minReg=1 last> BB01 regmask=[mm11] minReg=1 last> BB01 regmask=[mm12] minReg=1 last> BB01 regmask=[mm13] minReg=1 last> BB01 regmask=[mm14] minReg=1 last> BB01 regmask=[mm15] minReg=1 last> LCL_VAR BB01 regmask=[rdi] minReg=1> STORE_BLK BB01 regmask=[rsi] minReg=1> STORE_BLK BB01 regmask=[mm0] minReg=1> BB01 regmask=[rdi] minReg=1 last> STORE_BLK BB01 regmask=[rsi] minReg=1 last> STORE_BLK BB01 regmask=[mm0] minReg=1 last> BB01 regmask=[rdi] minReg=1> PUTARG_STK BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rcx] minReg=1> PUTARG_STK BB01 regmask=[rcx] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> PUTARG_STK BB01 regmask=[rsi] minReg=1 fixed> PUTARG_STK BB01 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rsi] minReg=1 last fixed> LCL_FLD BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> LCL_FLD BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL[0] BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rdx] minReg=1> CALL[1] BB01 regmask=[rdx] minReg=1 fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> Active intervals at end of allocation: Trees after linear scan register allocator (LSRA) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} N002 (???,???) [000081] ------------ IL_OFFSET void IL offset: 0x0 REG NA N004 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class REG rdi /--* t4 long N006 (???,???) [000088] ------------ t88 = * PUTARG_REG long REG rdi /--* t88 long arg0 in rdi N008 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG rax /--* t5 ref N010 ( 20, 19) [000007] DA---------- * STORE_LCL_VAR ref V05 tmp1 NA REG NA N012 ( 3, 2) [000008] ------------ t8 = LCL_VAR ref V05 tmp1 rdi REG rdi /--* t8 ref N014 ( 4, 3) [000010] -c---------- t10 = * LEA(b+8) byref REG NA N016 ( 3, 4) [000003] ------------ t3 = LCL_FLD int V02 arg2 [+8] Fseq[Version] rax REG rax /--* t10 byref +--* t3 int N018 (???,???) [000082] -A-XG------- * STOREIND int REG NA N020 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class REG rdi /--* t18 long N022 (???,???) [000089] ------------ t89 = * PUTARG_REG long REG rdi /--* t89 long arg0 in rdi N024 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG rax /--* t19 ref N026 ( 20, 19) [000021] DA---------- * STORE_LCL_VAR ref V06 tmp2 NA REG NA N028 ( 3, 2) [000022] ------------ t22 = LCL_VAR ref V06 tmp2 rsi REG rsi /--* t22 ref N030 ( 4, 3) [000024] -c---------- t24 = * LEA(b+8) byref REG NA N032 ( 3, 4) [000017] ------------ t17 = LCL_FLD long V02 arg2 [+0] Fseq[JobGroup] rdx REG rdx /--* t24 byref +--* t17 long N034 (???,???) [000083] -A-XG------- * STOREIND long REG NA N036 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V05 tmp1 rsi REG rsi /--* t13 ref N038 (???,???) [000090] ------------ t90 = * PUTARG_REG ref REG rsi N040 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V06 tmp2 rdx REG rdx /--* t27 ref N042 (???,???) [000091] ------------ t91 = * PUTARG_REG ref REG rdx N044 ( 2, 10) [000065] ------------ t65 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] REG rdi /--* t65 long N046 ( 4, 12) [000066] n---G------- t66 = * IND ref REG rdi /--* t66 ref N048 (???,???) [000092] ----G------- t92 = * PUTARG_REG ref REG rdi /--* t90 ref arg1 in rsi +--* t91 ref arg2 in rdx +--* t92 ref arg0 in rdi N050 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format REG rax /--* t29 ref [000098] --CXG------- t98 = * COPY ref REG rdi,NA /--* t98 ref N052 (???,???) [000093] --CXG------- t93 = * PUTARG_REG ref REG rdi /--* t93 ref arg0 in rdi N054 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log REG NA N056 (???,???) [000084] ------------ IL_OFFSET void IL offset: 0x25 REG NA N058 ( 1, 1) [000033] -c---------- t33 = CNS_INT int 0 REG NA N060 (???,???) [000094] Dc-----N---- t94 = LCL_VAR_ADDR byref V03 loc0 NA REG NA /--* t94 byref +--* t33 int N062 ( 5, 4) [000034] sA---------- * STORE_BLK struct (init) (Unroll) REG NA N064 (???,???) [000085] ------------ IL_OFFSET void IL offset: 0x2d REG NA N066 ( 3, 2) [000037] ------------ t37 = LCL_VAR byref V00 this rsi REG rsi N068 ( 1, 1) [000073] -c---------- t73 = CNS_INT long 16 field offset Fseq[m_Baselib] REG NA /--* t37 byref +--* t73 long N070 ( 5, 4) [000074] ------------ t74 = * ADD byref REG rsi /--* t74 byref N072 ( 8, 6) [000038] *c-XG------- t38 = * IND struct REG NA N074 ( 3, 2) [000035] U------N---- t35 = LCL_VAR_ADDR byref V03 loc0 rdi REG rdi N076 ( 1, 1) [000071] -c---------- t71 = CNS_INT long 40 field offset Fseq[Baselib] REG NA /--* t35 byref +--* t71 long N078 ( 5, 5) [000072] ------------ t72 = * ADD byref REG rdi /--* t72 byref +--* t38 struct N080 ( 11, 9) [000041] nA-XG------- * STORE_OBJ struct (copy) (RepInstr) REG NA N082 (???,???) [000086] ------------ IL_OFFSET void IL offset: 0x3a REG NA N084 ( 3, 2) [000045] ------------ t45 = LCL_VAR byref V00 this rdi REG rdi /--* t45 byref N086 ( 5, 4) [000076] -c---------- t76 = * LEA(b+112) byref REG NA /--* t76 byref N088 ( 8, 6) [000046] *c-XG------- t46 = * IND struct REG NA N090 ( 3, 4) [000043] Uc-----N---- t43 = LCL_FLD_ADDR byref V03 loc0 [+0] Fseq[Tx] NA REG NA /--* t43 byref +--* t46 struct N092 ( 6, 7) [000049] nA-XG------- * STORE_BLK struct (copy) (Unroll) REG NA N094 (???,???) [000087] ------------ IL_OFFSET void IL offset: 0x47 REG NA N096 ( 3, 2) [000051] -c-----N---- t51 = LCL_VAR_ADDR byref V03 loc0 NA REG NA /--* t51 byref N098 ( 9, 7) [000057] nc---------- t57 = * OBJ struct REG NA /--* t57 struct N100 (???,???) [000095] ------------ * PUTARG_STK [+0x00] void (12 slots) (RepInstr) REG NA N102 ( 3, 4) [000079] ------------ t79 = LCL_FLD long V02 arg2 [+0] rdi REG rdi /--* t79 long N104 (???,???) [000096] ------------ t96 = * PUTARG_REG long REG rdi N106 ( 3, 4) [000080] ------------ t80 = LCL_FLD long V02 arg2 [+8] rsi REG rsi /--* t80 long N108 (???,???) [000097] ------------ t97 = * PUTARG_REG long REG rsi /--* t96 long +--* t97 long N110 ( 6, 8) [000078] -c---------- t78 = * FIELD_LIST struct REG NA /--* t78 struct arg1 rdi,rsi N112 ( 32, 21) [000053] --CXG------- t53 = * CALL struct Unity.Jobs.IJobExtensions.Schedule REG rax,rdx /--* t53 struct N114 ( 36, 24) [000060] DA-XG------- * STORE_LCL_VAR struct V07 tmp3 NA REG NA N116 ( 3, 2) [000061] -c-----N---- t61 = LCL_VAR struct V07 tmp3 NA REG NA /--* t61 struct N118 ( 4, 3) [000062] ------------ * RETURN struct REG NA ------------------------------------------------------------------------------------------------------------------- Final allocation --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 0.#0 BB1 PredBB0 | | | | | | | | | | | 5.#1 C0 Def Alloc rdi | | | | | |C0 a| | | | | 6.#2 rdi Fixd Keep rdi | | | | | |C0 a| | | | | 6.#3 C0 Use * Keep rdi | | | | | |C0 i| | | | | 7.#4 rdi Fixd Keep rdi | | | | | | | | | | | 7.#5 I1 Def Alloc rdi | | | | | |I1 a| | | | | 8.#6 rdi Fixd Keep rdi | | | | | |I1 a| | | | | 8.#7 I1 Use * Keep rdi | | | | | |I1 i| | | | | 9.#8 rax Kill Keep rax | | | | | | | | | | | 9.#9 rcx Kill Keep rcx | | | | | | | | | | | 9.#10 rdx Kill Keep rdx | | | | | | | | | | | 9.#11 rsi Kill Keep rsi | | | | | | | | | | | 9.#12 rdi Kill Keep rdi | | | | | | | | | | | 9.#13 r8 Kill Keep r8 | | | | | | | | | | | 9.#14 r9 Kill Keep r9 | | | | | | | | | | | 9.#15 r10 Kill Keep r10 | | | | | | | | | | | 9.#16 r11 Kill Keep r11 | | | | | | | | | | | 9.#17 rax Fixd Keep rax | | | | | | | | | | | 9.#18 I2 Def Alloc rax |I2 a| | | | | | | | | | 10.#19 I2 Use * Keep rax |I2 i| | | | | | | | | | 13.#20 I3 Def Alloc rdi | | | | | |I3 a| | | | | 17.#21 I4 Def Alloc rax |I4 a| | | | |I3 a| | | | | 18.#22 I3 Use * Keep rdi |I4 a| | | | |I3 i| | | | | 18.#23 I4 Use * Keep rax |I4 i| | | | | | | | | | 21.#24 C5 Def Alloc rdi | | | | | |C5 a| | | | | 22.#25 rdi Fixd Keep rdi | | | | | |C5 a| | | | | 22.#26 C5 Use * Keep rdi | | | | | |C5 i| | | | | 23.#27 rdi Fixd Keep rdi | | | | | | | | | | | 23.#28 I6 Def Alloc rdi | | | | | |I6 a| | | | | 24.#29 rdi Fixd Keep rdi | | | | | |I6 a| | | | | 24.#30 I6 Use * Keep rdi | | | | | |I6 i| | | | | 25.#31 rax Kill Keep rax | | | | | | | | | | | 25.#32 rcx Kill Keep rcx | | | | | | | | | | | 25.#33 rdx Kill Keep rdx | | | | | | | | | | | 25.#34 rsi Kill Keep rsi | | | | | | | | | | | 25.#35 rdi Kill Keep rdi | | | | | | | | | | | 25.#36 r8 Kill Keep r8 | | | | | | | | | | | 25.#37 r9 Kill Keep r9 | | | | | | | | | | | 25.#38 r10 Kill Keep r10 | | | | | | | | | | | 25.#39 r11 Kill Keep r11 | | | | | | | | | | | 25.#40 rax Fixd Keep rax | | | | | | | | | | | 25.#41 I7 Def Alloc rax |I7 a| | | | | | | | | | 26.#42 I7 Use * Keep rax |I7 i| | | | | | | | | | 29.#43 I8 Def Alloc rsi | | | | |I8 a| | | | | | 33.#44 I9 Def Alloc rdx | | |I9 a| |I8 a| | | | | | 34.#45 I8 Use * Keep rsi | | |I9 a| |I8 i| | | | | | 34.#46 I9 Use * Keep rdx | | |I9 i| | | | | | | | 37.#47 I10 Def Alloc rsi | | | | |I10a| | | | | | 38.#48 rsi Fixd Keep rsi | | | | |I10a| | | | | | 38.#49 I10 Use * Keep rsi | | | | |I10i| | | | | | 39.#50 rsi Fixd Keep rsi | | | | | | | | | | | 39.#51 I11 Def Alloc rsi | | | | |I11a| | | | | | 41.#52 I12 Def Alloc rdx | | |I12a| |I11a| | | | | | 42.#53 rdx Fixd Keep rdx | | |I12a| |I11a| | | | | | 42.#54 I12 Use * Keep rdx | | |I12i| |I11a| | | | | | 43.#55 rdx Fixd Keep rdx | | | | |I11a| | | | | | 43.#56 I13 Def Alloc rdx | | |I13a| |I11a| | | | | | 45.#57 C14 Def Alloc rdi | | |I13a| |I11a|C14a| | | | | 46.#58 C14 Use * Keep rdi | | |I13a| |I11a|C14i| | | | | 47.#59 I15 Def Alloc rdi | | |I13a| |I11a|I15a| | | | | 48.#60 rdi Fixd Keep rdi | | |I13a| |I11a|I15a| | | | | 48.#61 I15 Use * Keep rdi | | |I13a| |I11a|I15i| | | | | 49.#62 rdi Fixd Keep rdi | | |I13a| |I11a| | | | | | 49.#63 I16 Def Alloc rdi | | |I13a| |I11a|I16a| | | | | 50.#64 rsi Fixd Keep rsi | | |I13a| |I11a|I16a| | | | | 50.#65 I11 Use * Keep rsi | | |I13a| |I11i|I16a| | | | | 50.#66 rdx Fixd Keep rdx | | |I13a| | |I16a| | | | | 50.#67 I13 Use * Keep rdx | | |I13i| | |I16a| | | | | 50.#68 rdi Fixd Keep rdi | | | | | |I16a| | | | | 50.#69 I16 Use * Keep rdi | | | | | |I16i| | | | | 51.#70 rax Kill Keep rax | | | | | | | | | | | 51.#71 rcx Kill Keep rcx | | | | | | | | | | | 51.#72 rdx Kill Keep rdx | | | | | | | | | | | 51.#73 rsi Kill Keep rsi | | | | | | | | | | | 51.#74 rdi Kill Keep rdi | | | | | | | | | | | 51.#75 r8 Kill Keep r8 | | | | | | | | | | | 51.#76 r9 Kill Keep r9 | | | | | | | | | | | 51.#77 r10 Kill Keep r10 | | | | | | | | | | | 51.#78 r11 Kill Keep r11 | | | | | | | | | | | 51.#79 rax Fixd Keep rax | | | | | | | | | | | 51.#80 I17 Def Alloc rax |I17a| | | | | | | | | | 52.#81 rdi Fixd Keep rdi |I17a| | | | | | | | | | Move rdi | | | | | |I17i| | | | | 53.#83 rdi Fixd Keep rdi | | | | | | | | | | | 53.#84 I18 Def Alloc rdi | | | | | |I18a| | | | | 54.#85 rdi Fixd Keep rdi | | | | | |I18a| | | | | 54.#86 I18 Use * Keep rdi | | | | | |I18i| | | | | 55.#87 rax Kill Keep rax | | | | | | | | | | | 55.#88 rcx Kill Keep rcx | | | | | | | | | | | 55.#89 rdx Kill Keep rdx | | | | | | | | | | | 55.#90 rsi Kill Keep rsi | | | | | | | | | | | 55.#91 rdi Kill Keep rdi | | | | | | | | | | | 55.#92 r8 Kill Keep r8 | | | | | | | | | | | 55.#93 r9 Kill Keep r9 | | | | | | | | | | | 55.#94 r10 Kill Keep r10 | | | | | | | | | | | 55.#95 r11 Kill Keep r11 | | | | | | | | | | | 62.#96 I19 Def Alloc mm0 | | | | | | | | | | | 62.#97 I19 Use * Keep mm0 | | | | | | | | | | | 67.#98 I20 Def Alloc rsi | | | | |I20a| | | | | | 70.#99 I20 Use * Keep rsi | | | | |I20i| | | | | | 71.#100 I21 Def Alloc rsi | | | | |I21a| | | | | | 75.#101 I22 Def Alloc rdi | | | | |I21a|I22a| | | | | 78.#102 I22 Use * Keep rdi | | | | |I21a|I22i| | | | | 79.#103 I23 Def Alloc rdi | | | | |I21a|I23a| | | | | 80.#104 rcx Fixd Keep rcx | | | | |I21a|I23a| | | | | 80.#105 I24 Def Alloc rcx | |I24a| | |I21a|I23a| | | | | 80.#106 rdi Fixd Keep rdi | |I24a| | |I21a|I23a| | | | | 80.#107 I23 Use * Keep rdi | |I24a| | |I21a|I23i| | | | | 80.#108 rsi Fixd Keep rsi | |I24a| | |I21a| | | | | | 80.#109 I21 Use * Keep rsi | |I24a| | |I21i| | | | | | 80.#110 I24 Use * Keep rcx | |I24i| | | | | | | | | 81.#111 rax Kill Keep rax | | | | | | | | | | | 81.#112 rcx Kill Keep rcx | | | | | | | | | | | 81.#113 rdx Kill Keep rdx | | | | | | | | | | | 81.#114 rsi Kill Keep rsi | | | | | | | | | | | 81.#115 rdi Kill Keep rdi | | | | | | | | | | | 81.#116 r8 Kill Keep r8 | | | | | | | | | | | 81.#117 r9 Kill Keep r9 | | | | | | | | | | | 81.#118 r10 Kill Keep r10 | | | | | | | | | | | 81.#119 r11 Kill Keep r11 | | | | | | | | | | | 81.#120 mm0 Kill Keep mm0 | | | | | | | | | | | 81.#121 mm1 Kill Keep mm1 | | | | | | | | | | | 81.#122 mm2 Kill Keep mm2 | | | | | | | | | | | 81.#123 mm3 Kill Keep mm3 | | | | | | | | | | | 81.#124 mm4 Kill Keep mm4 | | | | | | | | | | | 81.#125 mm5 Kill Keep mm5 | | | | | | | | | | | 81.#126 mm6 Kill Keep mm6 | | | | | | | | | | | 81.#127 mm7 Kill Keep mm7 | | | | | | | | | | | 81.#128 mm8 Kill Keep mm8 | | | | | | | | | | | 81.#129 mm9 Kill Keep mm9 | | | | | | | | | | | 81.#130 mm10 Kill Keep mm10 | | | | | | | | | | | 81.#131 mm11 Kill Keep mm11 | | | | | | | | | | | 81.#132 mm12 Kill Keep mm12 | | | | | | | | | | | 81.#133 mm13 Kill Keep mm13 | | | | | | | | | | | 81.#134 mm14 Kill Keep mm14 | | | | | | | | | | | 81.#135 mm15 Kill Keep mm15 | | | | | | | | | | | 85.#136 I25 Def Alloc rdi | | | | | |I25a| | | | | 92.#137 I26 Def Alloc rsi | | | | |I26a|I25a| | | | | 92.#138 I27 Def Alloc mm0 | | | | |I26a|I25a| | | | | 92.#139 I25 Use * Keep rdi | | | | |I26a|I25i| | | | | 92.#140 I26 Use * Keep rsi | | | | |I26i| | | | | | 92.#141 I27 Use * Keep mm0 | | | | | | | | | | | 100.#142 rdi Fixd Keep rdi | | | | | | | | | | | 100.#143 I28 Def Alloc rdi | | | | | |I28a| | | | | 100.#144 rcx Fixd Keep rcx | | | | | |I28a| | | | | 100.#145 I29 Def Alloc rcx | |I29a| | | |I28a| | | | | 100.#146 rsi Fixd Keep rsi | |I29a| | | |I28a| | | | | 100.#147 I30 Def Alloc rsi | |I29a| | |I30a|I28a| | | | | 100.#148 I28 Use * Keep rdi | |I29a| | |I30a|I28i| | | | | 100.#149 I29 Use * Keep rcx | |I29i| | |I30a| | | | | | 100.#150 I30 Use * Keep rsi | | | | |I30i| | | | | | 103.#151 I31 Def Alloc rdi | | | | | |I31a| | | | | 104.#152 rdi Fixd Keep rdi | | | | | |I31a| | | | | 104.#153 I31 Use * Keep rdi | | | | | |I31i| | | | | 105.#154 rdi Fixd Keep rdi | | | | | | | | | | | 105.#155 I32 Def Alloc rdi | | | | | |I32a| | | | | 107.#156 I33 Def Alloc rsi | | | | |I33a|I32a| | | | | 108.#157 rsi Fixd Keep rsi | | | | |I33a|I32a| | | | | 108.#158 I33 Use * Keep rsi | | | | |I33i|I32a| | | | | 109.#159 rsi Fixd Keep rsi | | | | | |I32a| | | | | 109.#160 I34 Def Alloc rsi | | | | |I34a|I32a| | | | | 112.#161 rdi Fixd Keep rdi | | | | |I34a|I32a| | | | | 112.#162 I32 Use * Keep rdi | | | | |I34a|I32i| | | | | 112.#163 rsi Fixd Keep rsi | | | | |I34a| | | | | | 112.#164 I34 Use * Keep rsi | | | | |I34i| | | | | | 113.#165 rax Kill Keep rax | | | | | | | | | | | 113.#166 rcx Kill Keep rcx | | | | | | | | | | | 113.#167 rdx Kill Keep rdx | | | | | | | | | | | 113.#168 rsi Kill Keep rsi | | | | | | | | | | | 113.#169 rdi Kill Keep rdi | | | | | | | | | | | 113.#170 r8 Kill Keep r8 | | | | | | | | | | | 113.#171 r9 Kill Keep r9 | | | | | | | | | | | 113.#172 r10 Kill Keep r10 | | | | | | | | | | | 113.#173 r11 Kill Keep r11 | | | | | | | | | | | 113.#174 rax Fixd Keep rax | | | | | | | | | | | 113.#175 I35 Def Alloc rax |I35a| | | | | | | | | | 113.#176 rdx Fixd Keep rdx |I35a| | | | | | | | | | 113.#177 I36 Def Alloc rdx |I35a| |I36a| | | | | | | | 114.#178 I35 Use * Keep rax |I35i| |I36a| | | | | | | | 114.#179 I36 Use * Keep rdx | | |I36i| | | | | | | | Recording the maximum number of concurrent spills: ---------- LSRA Stats ---------- BB01 [ 100]: SpillCount = 0, ResolutionMovs = 0, SplitEdges = 0, CopyReg = 1 Total Tracked Vars: 0 Total Reg Cand Vars: 0 Total number of Intervals: 36 Total number of RefPositions: 179 Total Spill Count: 0 Weighted: 0 Total CopyReg Count: 1 Weighted: 100 Total ResolutionMov Count: 0 Weighted: 0 Total number of split edges: 0 Total Number of spill temps created: 0 TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS Incoming Parameters: BB01 [000..04F) (return), preds={} succs={} ===== N002. IL_OFFSET IL offset: 0x0 N004. rdi = CNS_INT(h) 0x7f6678beb1c0 class N006. rdi = PUTARG_REG; rdi N008. rax = CALL help; rdi N010. V05 MEM; rax N012. rdi = V05 MEM N014. STK = LEA(b+8) ; rdi N016. rax = V02 MEM N018. STOREIND ; STK,rax N020. rdi = CNS_INT(h) 0x7f6678c127f0 class N022. rdi = PUTARG_REG; rdi N024. rax = CALL help; rdi N026. V06 MEM; rax N028. rsi = V06 MEM N030. STK = LEA(b+8) ; rsi N032. rdx = V02 MEM N034. STOREIND ; STK,rdx N036. rsi = V05 MEM N038. rsi = PUTARG_REG; rsi N040. rdx = V06 MEM N042. rdx = PUTARG_REG; rdx N044. rdi = CNS_INT(h) 0x640084D0 [ICON_STR_HDL] N046. rdi = IND ; rdi N048. rdi = PUTARG_REG; rdi N050. rax = CALL ; rsi,rdx,rdi N000. rdi = COPY ; rax N052. rdi = PUTARG_REG; rdi N054. CALL ; rdi N056. IL_OFFSET IL offset: 0x25 N058. CNS_INT 0 N060. LCL_VAR_ADDR V03 loc0 NA N062. STORE_BLK N064. IL_OFFSET IL offset: 0x2d N066. rsi = V00 MEM N068. CNS_INT 16 field offset Fseq[m_Baselib] N070. rsi = ADD ; rsi N072. STK = IND ; rsi N074. rdi = LCL_VAR_ADDR V03 loc0 rdi N076. CNS_INT 40 field offset Fseq[Baselib] N078. rdi = ADD ; rdi N080. STORE_OBJ; rdi,STK N082. IL_OFFSET IL offset: 0x3a N084. rdi = V00 MEM N086. STK = LEA(b+112); rdi N088. STK = IND ; STK N090. LCL_FLD_ADDR V03 loc0 [+0] Fseq[Tx] NA N092. STORE_BLK; STK N094. IL_OFFSET IL offset: 0x47 N096. LCL_VAR_ADDR V03 loc0 NA N098. OBJ N100. PUTARG_STK [+0x00] N102. rdi = V02 MEM N104. rdi = PUTARG_REG; rdi N106. rsi = V02 MEM N108. rsi = PUTARG_REG; rsi N110. STK = FIELD_LIST; rdi,rsi N112. rax,rdx = CALL ; STK N114. V07 MEM; rax,rdx N116. V07 MEM N118. RETURN *************** Finishing PHASE Linear scan register alloc *************** In genGenerateCode() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Generate code *************** In fgDebugCheckBBlist Finalizing stack frame Modified regs: [rax rcx rdx rsi rdi r8-r11 mm0-mm15] Callee-saved registers pushed: 0 [] *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT) Assign V00 this, size=8, stkOffs=-0x18 Assign V02 arg2, size=16, stkOffs=-0x28 Assign V03 loc0, size=96, stkOffs=-0x88 Assign V05 tmp1, size=8, stkOffs=-0x90 Assign V06 tmp2, size=8, stkOffs=-0x98 Assign V07 tmp3, size=16, stkOffs=-0xa8 Assign V04 OutArgs, size=96, stkOffs=-0x108 --- delta bump 8 for RA --- delta bump 8 for FP --- delta bump 0 for RBP frame --- virtual stack offset to actual stack offset delta is 16 -- V00 was -24, now -8 -- V01 was 0, now 16 -- V02 was -40, now -24 -- V03 was -136, now -120 -- V04 was -264, now -248 -- V05 was -144, now -128 -- V06 was -152, now -136 -- V07 was -168, now -152 ; Final local variable assignments ; ; V00 this [V00 ] ( 1, 1 ) byref -> [rbp-0x08] this ; V01 arg1 [V01 ] ( 1, 1 ) struct (56) [rbp+0x10] ; V02 arg2 [V02 ] ( 1, 1 ) struct (16) [rbp-0x18] do-not-enreg[SFA] multireg-arg ; V03 loc0 [V03 ] ( 1, 1 ) struct (96) [rbp-0x78] do-not-enreg[SFB] must-init ld-addr-op ; V04 OutArgs [V04 ] ( 1, 1 ) lclBlk (96) [rsp+0x00] "OutgoingArgSpace" ; V05 tmp1 [V05 ] ( 1, 1 ) ref -> [rbp-0x80] must-init "Reusable Box Helper" ; V06 tmp2 [V06 ] ( 1, 1 ) ref -> [rbp-0x88] must-init "Reusable Box Helper" ; V07 tmp3 [V07 ] ( 1, 1 ) struct (16) [rbp-0x98] multireg-ret "Return value temp for multireg return" ; ; Lcl frame size = 256 Setting stack level from -572662307 to 0 =============== Generating BB01 [000..04F) (return), preds={} succs={} flags=0x00000004.408b0020: i label target hascall gcsafe newobj LIR BB01 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap Liveness not changing: {} Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M38824_BB01: Label: IG02, GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Scope info: begin block BB01, IL range [000..04F) Scope info: opening scope, LVnum=0 [000..04F) Scope info: >> new scope, VarNum=0, tracked? no, VarIndex=0, bbLiveIn= {} Scope info: opening scope, LVnum=1 [000..04F) Scope info: >> new scope, VarNum=1, tracked? no, VarIndex=0, bbLiveIn= {} Scope info: opening scope, LVnum=2 [000..04F) Scope info: >> new scope, VarNum=2, tracked? no, VarIndex=0, bbLiveIn= {} Scope info: opening scope, LVnum=3 [000..04F) Scope info: >> new scope, VarNum=3, tracked? no, VarIndex=0, bbLiveIn= {} Scope info: open scopes = 0 (V00 this) [000..04F) 1 (V01 arg1) [000..04F) 2 (V02 arg2) [000..04F) 3 (V03 loc0) [000..04F) Added IP mapping: 0x0000 STACK_EMPTY (G_M38824_IG02,ins#0,ofs#0) label Generating: N002 (???,???) [000081] ------------ IL_OFFSET void IL offset: 0x0 REG NA Generating: N004 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class REG rdi IN0001: mov rdi, 0x7F6678BEB1C0 /--* t4 long Generating: N006 (???,???) [000088] ------------ t88 = * PUTARG_REG long REG rdi /--* t88 long arg0 in rdi Generating: N008 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG rax Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0002: call CORINFO_HELP_NEWSFAST GC regs: 00000000 {} => 00000001 {rax} /--* t5 ref Generating: N010 ( 20, 19) [000007] DA---------- * STORE_LCL_VAR ref V05 tmp1 NA REG NA GC regs: 00000001 {rax} => 00000000 {} IN0003: mov gword ptr [V05 rbp-80H], rax Generating: N012 ( 3, 2) [000008] ------------ t8 = LCL_VAR ref V05 tmp1 rdi REG rdi IN0004: mov rdi, gword ptr [V05 rbp-80H] GC regs: 00000000 {} => 00000080 {rdi} /--* t8 ref Generating: N014 ( 4, 3) [000010] -c---------- t10 = * LEA(b+8) byref REG NA Generating: N016 ( 3, 4) [000003] ------------ t3 = LCL_FLD int V02 arg2 [+8] Fseq[Version] rax REG rax IN0005: mov eax, dword ptr [V02+0x8 rbp-10H] /--* t10 byref +--* t3 int Generating: N018 (???,???) [000082] -A-XG------- * STOREIND int REG NA GC regs: 00000080 {rdi} => 00000000 {} IN0006: mov dword ptr [rdi+8], eax Generating: N020 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class REG rdi IN0007: mov rdi, 0x7F6678C127F0 /--* t18 long Generating: N022 (???,???) [000089] ------------ t89 = * PUTARG_REG long REG rdi /--* t89 long arg0 in rdi Generating: N024 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG rax Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0008: call CORINFO_HELP_NEWSFAST GC regs: 00000000 {} => 00000001 {rax} /--* t19 ref Generating: N026 ( 20, 19) [000021] DA---------- * STORE_LCL_VAR ref V06 tmp2 NA REG NA GC regs: 00000001 {rax} => 00000000 {} IN0009: mov gword ptr [V06 rbp-88H], rax Generating: N028 ( 3, 2) [000022] ------------ t22 = LCL_VAR ref V06 tmp2 rsi REG rsi IN000a: mov rsi, gword ptr [V06 rbp-88H] GC regs: 00000000 {} => 00000040 {rsi} /--* t22 ref Generating: N030 ( 4, 3) [000024] -c---------- t24 = * LEA(b+8) byref REG NA Generating: N032 ( 3, 4) [000017] ------------ t17 = LCL_FLD long V02 arg2 [+0] Fseq[JobGroup] rdx REG rdx IN000b: mov rdx, qword ptr [V02 rbp-18H] /--* t24 byref +--* t17 long Generating: N034 (???,???) [000083] -A-XG------- * STOREIND long REG NA GC regs: 00000040 {rsi} => 00000000 {} IN000c: mov qword ptr [rsi+8], rdx Generating: N036 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V05 tmp1 rsi REG rsi IN000d: mov rsi, gword ptr [V05 rbp-80H] GC regs: 00000000 {} => 00000040 {rsi} /--* t13 ref Generating: N038 (???,???) [000090] ------------ t90 = * PUTARG_REG ref REG rsi GC regs: 00000040 {rsi} => 00000000 {} GC regs: 00000000 {} => 00000040 {rsi} Generating: N040 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V06 tmp2 rdx REG rdx IN000e: mov rdx, gword ptr [V06 rbp-88H] GC regs: 00000040 {rsi} => 00000044 {rdx rsi} /--* t27 ref Generating: N042 (???,???) [000091] ------------ t91 = * PUTARG_REG ref REG rdx GC regs: 00000044 {rdx rsi} => 00000040 {rsi} GC regs: 00000040 {rsi} => 00000044 {rdx rsi} Generating: N044 ( 2, 10) [000065] ------------ t65 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] REG rdi IN000f: mov rdi, 0x7F66640084D0 /--* t65 long Generating: N046 ( 4, 12) [000066] n---G------- t66 = * IND ref REG rdi IN0010: mov rdi, gword ptr [rdi] GC regs: 00000044 {rdx rsi} => 000000C4 {rdx rsi rdi} /--* t66 ref Generating: N048 (???,???) [000092] ----G------- t92 = * PUTARG_REG ref REG rdi GC regs: 000000C4 {rdx rsi rdi} => 00000044 {rdx rsi} GC regs: 00000044 {rdx rsi} => 000000C4 {rdx rsi rdi} /--* t90 ref arg1 in rsi +--* t91 ref arg2 in rdx +--* t92 ref arg0 in rdi Generating: N050 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format REG rax GC regs: 000000C4 {rdx rsi rdi} => 00000084 {rdx rdi} GC regs: 00000084 {rdx rdi} => 00000080 {rdi} GC regs: 00000080 {rdi} => 00000000 {} Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0011: call System.String:Format(System.String,System.Object,System.Object):System.String GC regs: 00000000 {} => 00000001 {rax} /--* t29 ref Generating: [000098] --CXG------- t98 = * COPY ref REG rdi,NA /--* t98 ref Generating: N052 (???,???) [000093] --CXG------- t93 = * PUTARG_REG ref REG rdi GC regs: 00000001 {rax} => 00000000 {} IN0012: mov rdi, rax GC regs: 00000000 {} => 00000080 {rdi} GC regs: 00000080 {rdi} => 00000000 {} GC regs: 00000000 {} => 00000080 {rdi} /--* t93 ref arg0 in rdi Generating: N054 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log REG NA GC regs: 00000080 {rdi} => 00000000 {} Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0013: call UnityEngine.Debug:Log(System.Object) Added IP mapping: 0x0025 STACK_EMPTY (G_M38824_IG02,ins#19,ofs#103) Generating: N056 (???,???) [000084] ------------ IL_OFFSET void IL offset: 0x25 REG NA Generating: N058 ( 1, 1) [000033] -c---------- t33 = CNS_INT int 0 REG NA Generating: N060 (???,???) [000094] Dc-----N---- t94 = LCL_VAR_ADDR byref V03 loc0 NA REG NA /--* t94 byref +--* t33 int Generating: N062 ( 5, 4) [000034] sA---------- * STORE_BLK struct (init) (Unroll) REG NA IN0014: vxorps xmm0, xmm0 IN0015: vmovdqu xmmword ptr [V03 rbp-78H], xmm0 IN0016: vmovdqu xmmword ptr [V03+0x10 rbp-68H], xmm0 IN0017: vmovdqu xmmword ptr [V03+0x20 rbp-58H], xmm0 IN0018: vmovdqu xmmword ptr [V03+0x30 rbp-48H], xmm0 IN0019: vmovdqu xmmword ptr [V03+0x40 rbp-38H], xmm0 IN001a: vmovdqu xmmword ptr [V03+0x50 rbp-28H], xmm0 Added IP mapping: 0x002D STACK_EMPTY (G_M38824_IG02,ins#26,ofs#144) Generating: N064 (???,???) [000085] ------------ IL_OFFSET void IL offset: 0x2d REG NA Generating: N066 ( 3, 2) [000037] ------------ t37 = LCL_VAR byref V00 this rsi REG rsi IN001b: mov rsi, bword ptr [V00 rbp-08H] Byref regs: 00000000 {} => 00000040 {rsi} Generating: N068 ( 1, 1) [000073] -c---------- t73 = CNS_INT long 16 field offset Fseq[m_Baselib] REG NA /--* t37 byref +--* t73 long Generating: N070 ( 5, 4) [000074] ------------ t74 = * ADD byref REG rsi Byref regs: 00000040 {rsi} => 00000000 {} IN001c: add rsi, 16 Byref regs: 00000000 {} => 00000040 {rsi} /--* t74 byref Generating: N072 ( 8, 6) [000038] *c-XG------- t38 = * IND struct REG NA Generating: N074 ( 3, 2) [000035] U------N---- t35 = LCL_VAR_ADDR byref V03 loc0 rdi REG rdi IN001d: lea rdi, bword ptr [V03 rbp-78H] Byref regs: 00000040 {rsi} => 000000C0 {rsi rdi} Generating: N076 ( 1, 1) [000071] -c---------- t71 = CNS_INT long 40 field offset Fseq[Baselib] REG NA /--* t35 byref +--* t71 long Generating: N078 ( 5, 5) [000072] ------------ t72 = * ADD byref REG rdi Byref regs: 000000C0 {rsi rdi} => 00000040 {rsi} IN001e: add rdi, 40 Byref regs: 00000040 {rsi} => 000000C0 {rsi rdi} /--* t72 byref +--* t38 struct Generating: N080 ( 11, 9) [000041] nA-XG------- * STORE_OBJ struct (copy) (RepInstr) REG NA Byref regs: 000000C0 {rsi rdi} => 00000040 {rsi} Byref regs: 00000040 {rsi} => 00000000 {} Byref regs: 00000000 {} => 00000040 {rsi} Byref regs: 00000040 {rsi} => 000000C0 {rsi rdi} NoGC Call: savedSet=0000F0C8 {rbx rsi rdi r12 r13 r14 r15} Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=000000C0 {rsi rdi} IN001f: call CORINFO_HELP_ASSIGN_BYREF IN0020: mov ecx, 6 IN0021: rep movsq Byref regs: 000000C0 {rsi rdi} => 00000080 {rdi} Byref regs: 00000080 {rdi} => 00000000 {} Added IP mapping: 0x003A STACK_EMPTY (G_M38824_IG02,ins#33,ofs#173) Generating: N082 (???,???) [000086] ------------ IL_OFFSET void IL offset: 0x3a REG NA Generating: N084 ( 3, 2) [000045] ------------ t45 = LCL_VAR byref V00 this rdi REG rdi IN0022: mov rdi, bword ptr [V00 rbp-08H] Byref regs: 00000000 {} => 00000080 {rdi} /--* t45 byref Generating: N086 ( 5, 4) [000076] -c---------- t76 = * LEA(b+112) byref REG NA /--* t76 byref Generating: N088 ( 8, 6) [000046] *c-XG------- t46 = * IND struct REG NA Generating: N090 ( 3, 4) [000043] Uc-----N---- t43 = LCL_FLD_ADDR byref V03 loc0 [+0] Fseq[Tx] NA REG NA /--* t43 byref +--* t46 struct Generating: N092 ( 6, 7) [000049] nA-XG------- * STORE_BLK struct (copy) (Unroll) REG NA Byref regs: 00000080 {rdi} => 00000000 {} IN0023: vmovdqu xmm0, xmmword ptr [rdi+112] IN0024: vmovdqu xmmword ptr [V03 rbp-78H], xmm0 IN0025: vmovdqu xmm0, xmmword ptr [rdi+128] IN0026: vmovdqu xmmword ptr [V03+0x10 rbp-68H], xmm0 IN0027: mov rsi, qword ptr [rdi+144] IN0028: mov qword ptr [V03+0x20 rbp-58H], rsi Added IP mapping: 0x0047 STACK_EMPTY (G_M38824_IG02,ins#40,ofs#215) Generating: N094 (???,???) [000087] ------------ IL_OFFSET void IL offset: 0x47 REG NA Generating: N096 ( 3, 2) [000051] -c-----N---- t51 = LCL_VAR_ADDR byref V03 loc0 NA REG NA /--* t51 byref Generating: N098 ( 9, 7) [000057] nc---------- t57 = * OBJ struct REG NA /--* t57 struct Generating: N100 (???,???) [000095] ------------ * PUTARG_STK [+0x00] void (12 slots) (RepInstr) REG NA IN0029: lea rdi, [V04 rsp] IN002a: lea rsi, [V03 rbp-78H] IN002b: mov ecx, 5 IN002c: rep movsq IN002d: mov rcx, gword ptr [rsi] IN002e: mov gword ptr [V04+0x28 rsp+28H], rcx IN002f: add rsi, 8 IN0030: add rdi, 8 IN0031: mov ecx, 6 IN0032: rep movsq Generating: N102 ( 3, 4) [000079] ------------ t79 = LCL_FLD long V02 arg2 [+0] rdi REG rdi IN0033: mov rdi, qword ptr [V02 rbp-18H] /--* t79 long Generating: N104 (???,???) [000096] ------------ t96 = * PUTARG_REG long REG rdi Generating: N106 ( 3, 4) [000080] ------------ t80 = LCL_FLD long V02 arg2 [+8] rsi REG rsi IN0034: mov rsi, qword ptr [V02+0x8 rbp-10H] /--* t80 long Generating: N108 (???,???) [000097] ------------ t97 = * PUTARG_REG long REG rsi /--* t96 long +--* t97 long Generating: N110 ( 6, 8) [000078] -c---------- t78 = * FIELD_LIST struct REG NA /--* t78 struct arg1 rdi,rsi Generating: N112 ( 32, 21) [000053] --CXG------- t53 = * CALL struct Unity.Jobs.IJobExtensions.Schedule REG rax,rdx Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0035: call Unity.Jobs.IJobExtensions:Schedule(FlushSendJob,Unity.Jobs.JobHandle):Unity.Jobs.JobHandle /--* t53 struct Generating: N114 ( 36, 24) [000060] DA-XG------- * STORE_LCL_VAR struct V07 tmp3 NA REG NA IN0036: mov qword ptr [V07 rbp-98H], rax IN0037: mov qword ptr [V07+0x8 rbp-90H], rdx Generating: N116 ( 3, 2) [000061] -c-----N---- t61 = LCL_VAR struct V07 tmp3 NA REG NA /--* t61 struct Generating: N118 ( 4, 3) [000062] ------------ * RETURN struct REG NA **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 IN0038: mov rax, qword ptr [V07 rbp-98H] IN0039: mov rdx, qword ptr [V07+0x8 rbp-90H] Scope info: end block BB01, IL range [000..04F) Scope info: ending scope, LVnum=0 [000..04F) Scope info: ending scope, LVnum=1 [000..04F) Scope info: ending scope, LVnum=2 [000..04F) Scope info: ending scope, LVnum=3 [000..04F) Scope info: open scopes = Added IP mapping: EPILOG STACK_EMPTY (G_M38824_IG02,ins#57,ofs#296) label Reserving epilog IG for block BB01 G_M38824_IG02: ; offs=000000H, funclet=00, bbWeight=1 *************** After placeholder IG creation G_M38824_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M38824_IG02: ; offs=000000H, size=0128H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M38824_IG03: ; epilog placeholder, next placeholder=, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder ; PrevGCVars= {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {} ; InitGCVars= {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} Liveness not changing: {} # compCycleEstimate = 190, compSizeEstimate = 157 Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this ; Final local variable assignments ; ; V00 this [V00 ] ( 1, 1 ) byref -> [rbp-0x08] this ; V01 arg1 [V01 ] ( 1, 1 ) struct (56) [rbp+0x10] ; V02 arg2 [V02 ] ( 1, 1 ) struct (16) [rbp-0x18] do-not-enreg[SFA] multireg-arg ; V03 loc0 [V03 ] ( 1, 1 ) struct (96) [rbp-0x78] do-not-enreg[SFB] must-init ld-addr-op ; V04 OutArgs [V04 ] ( 1, 1 ) lclBlk (96) [rsp+0x00] "OutgoingArgSpace" ; V05 tmp1 [V05 ] ( 1, 1 ) ref -> [rbp-0x80] must-init "Reusable Box Helper" ; V06 tmp2 [V06 ] ( 1, 1 ) ref -> [rbp-0x88] must-init "Reusable Box Helper" ; V07 tmp3 [V07 ] ( 1, 1 ) struct (16) [rbp-0x98] multireg-ret "Return value temp for multireg return" ; ; Lcl frame size = 256 *************** Before prolog / epilog generation G_M38824_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M38824_IG02: ; offs=000000H, size=0128H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M38824_IG03: ; epilog placeholder, next placeholder=, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder ; PrevGCVars= {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {} ; InitGCVars= {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} *************** In genFnProlog() Added IP mapping to front: PROLOG STACK_EMPTY (G_M38824_IG01,ins#0,ofs#0) label __prolog: **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 Found 28 lvMustInit int-sized stack slots, frame offsets 136 through 24 IN003a: push rbp IN003b: sub rsp, 256 IN003c: vzeroupper IN003d: lea rbp, [rsp+100H] Notify VM instruction set (AVX2) must be supported. IN003e: xor rax, rax IN003f: mov qword ptr [rbp-88H], rax IN0040: vxorps xmm8, xmm8 IN0041: mov rax, -96 IN0042: vmovdqa xmmword ptr [rbp+rax-20H], xmm8 IN0043: vmovdqa xmmword ptr [rbp+rax-10H], xmm8 IN0044: vmovdqa xmmword ptr [rax+rbp], xmm8 IN0045: add rax, 48 IN0046: jne SHORT -5 instr IN0047: mov qword ptr [rbp-20H], rax *************** In genClearStackVec3ArgUpperBits() *************** In genFnPrologCalleeRegArgs() for int regs **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 IN0048: mov bword ptr [V00 rbp-08H], rdi IN0049: mov qword ptr [V02 rbp-18H], rsi IN004a: mov qword ptr [V02+0x8 rbp-10H], rdx *************** In genEnregisterIncomingStackArgs() G_M38824_IG01: ; offs=000000H, funclet=00, bbWeight=1 *************** In genFnEpilog() __epilog: gcVarPtrSetCur= {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {} IN004b: lea rsp, [rbp] IN004c: pop rbp IN004d: ret G_M38824_IG03: ; offs=000128H, funclet=00, bbWeight=1 0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs *************** After prolog / epilog generation G_M38824_IG01: ; func=00, offs=000000H, size=0055H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG G_M38824_IG02: ; offs=000055H, size=0128H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M38824_IG03: ; offs=00017DH, size=0006H, epilog, nogc, extend *************** In emitJumpDistBind() *************** Finishing PHASE Generate code *************** Starting PHASE Emit code Hot code size = 0x183 bytes Cold code size = 0x0 bytes reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0xa) *************** In emitEndCodeGen() Converting emitMaxStackDepth from bytes (0) to elements (0) *************************************************************************** Instructions as they come out of the scheduler G_M38824_IG01: ; func=00, offs=000000H, size=0055H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG IN003a: 000000 55 push rbp IN003b: 000001 4881EC00010000 sub rsp, 256 IN003c: 000008 C5F877 vzeroupper IN003d: 00000B 488DAC2400010000 lea rbp, [rsp+100H] IN003e: 000013 33C0 xor rax, rax IN003f: 000015 48898578FFFFFF mov qword ptr [rbp-88H], rax IN0040: 00001C C4413857C0 vxorps xmm8, xmm8 IN0041: 000021 48B8A0FFFFFFFFFFFFFF mov rax, -96 IN0042: 00002B C5797F4405E0 vmovdqa xmmword ptr [rbp+rax-20H], xmm8 (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN0043: 000031 C5797F4405F0 vmovdqa xmmword ptr [rbp+rax-10H], xmm8 (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN0044: 000037 C5797F0428 vmovdqa xmmword ptr [rax+rbp], xmm8 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN0045: 00003C 4883C030 add rax, 48 IN0046: 000040 75E9 jne SHORT -5 instr IN0047: 000042 488945E0 mov qword ptr [rbp-20H], rax IN0048: 000046 48897DF8 mov bword ptr [rbp-08H], rdi IN0049: 00004A 488975E8 mov qword ptr [rbp-18H], rsi IN004a: 00004E 488955F0 mov qword ptr [rbp-10H], rdx ;; bbWeight=1 PerfScore 12.83 G_M38824_IG02: ; func=00, offs=000055H, size=0128H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref Block predicted offs = 00000055, actual = 00000052 -> size adj = 3 IN0001: 000052 48BFC0B1BE78667F0000 mov rdi, 0x7F6678BEB1C0 New gcrReg live regs=00000001 {rax} ; Call at 005C [stk=0], GCvars=none, gcrefRegs=00000001 {rax}, byrefRegs=00000000 {} IN0002: 00005C E8CF8AE477 call CORINFO_HELP_NEWSFAST IN0003: 000061 48894580 mov gword ptr [rbp-80H], rax gcrReg +[rdi] IN0004: 000065 488B7D80 mov rdi, gword ptr [rbp-80H] gcrReg -[rax] IN0005: 000069 8B45F0 mov eax, dword ptr [rbp-10H] IN0006: 00006C 894708 mov dword ptr [rdi+8], eax gcrReg -[rdi] IN0007: 00006F 48BFF027C178667F0000 mov rdi, 0x7F6678C127F0 New gcrReg live regs=00000001 {rax} ; Call at 0079 [stk=0], GCvars=none, gcrefRegs=00000001 {rax}, byrefRegs=00000000 {} IN0008: 000079 E8B28AE477 call CORINFO_HELP_NEWSFAST IN0009: 00007E 48898578FFFFFF mov gword ptr [rbp-88H], rax gcrReg +[rsi] IN000a: 000085 488BB578FFFFFF mov rsi, gword ptr [rbp-88H] IN000b: 00008C 488B55E8 mov rdx, qword ptr [rbp-18H] IN000c: 000090 48895608 mov qword ptr [rsi+8], rdx IN000d: 000094 488B7580 mov rsi, gword ptr [rbp-80H] gcrReg +[rdx] IN000e: 000098 488B9578FFFFFF mov rdx, gword ptr [rbp-88H] IN000f: 00009F 48BFD0840064667F0000 mov rdi, 0x7F66640084D0 gcrReg +[rdi] IN0010: 0000A9 488B3F mov rdi, gword ptr [rdi] New gcrReg live regs=00000001 {rax} ; Call at 00AC [stk=0], GCvars=none, gcrefRegs=00000001 {rax}, byrefRegs=00000000 {} IN0011: 0000AC E8FF4EA7FE call System.String:Format(System.String,System.Object,System.Object):System.String gcrReg +[rdi] IN0012: 0000B1 488BF8 mov rdi, rax New gcrReg live regs=00000000 {} ; Call at 00B4 [stk=0], GCvars=none, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0013: 0000B4 E8573B4BFF call UnityEngine.Debug:Log(System.Object) IN0014: 0000B9 C5F857C0 vxorps xmm0, xmm0 (ECS:5, ACS:4) Instruction predicted size = 5, actual = 4 IN0015: 0000BD C5FA7F4588 vmovdqu xmmword ptr [rbp-78H], xmm0 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN0016: 0000C2 C5FA7F4598 vmovdqu xmmword ptr [rbp-68H], xmm0 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN0017: 0000C7 C5FA7F45A8 vmovdqu xmmword ptr [rbp-58H], xmm0 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN0018: 0000CC C5FA7F45B8 vmovdqu xmmword ptr [rbp-48H], xmm0 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN0019: 0000D1 C5FA7F45C8 vmovdqu xmmword ptr [rbp-38H], xmm0 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN001a: 0000D6 C5FA7F45D8 vmovdqu xmmword ptr [rbp-28H], xmm0 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 byrReg +[rsi] IN001b: 0000DB 488B75F8 mov rsi, bword ptr [rbp-08H] IN001c: 0000DF 4883C610 add rsi, 16 byrReg +[rdi] IN001d: 0000E3 488D7D88 lea rdi, bword ptr [rbp-78H] IN001e: 0000E7 4883C728 add rdi, 40 IN001f: 0000EB E83217FF77 call CORINFO_HELP_ASSIGN_BYREF IN0020: 0000F0 B906000000 mov ecx, 6 IN0021: 0000F5 F348A5 rep movsq IN0022: 0000F8 488B7DF8 mov rdi, bword ptr [rbp-08H] IN0023: 0000FC C5FA6F4770 vmovdqu xmm0, xmmword ptr [rdi+112] (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN0024: 000101 C5FA7F4588 vmovdqu xmmword ptr [rbp-78H], xmm0 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN0025: 000106 C5FA6F8780000000 vmovdqu xmm0, xmmword ptr [rdi+128] (ECS:9, ACS:8) Instruction predicted size = 9, actual = 8 IN0026: 00010E C5FA7F4598 vmovdqu xmmword ptr [rbp-68H], xmm0 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 byrReg -[rsi] IN0027: 000113 488BB790000000 mov rsi, qword ptr [rdi+144] IN0028: 00011A 488975A8 mov qword ptr [rbp-58H], rsi byrReg -[rdi] IN0029: 00011E 488D3C24 lea rdi, [rsp] IN002a: 000122 488D7588 lea rsi, [rbp-78H] IN002b: 000126 B905000000 mov ecx, 5 IN002c: 00012B F348A5 rep movsq gcrReg +[rcx] IN002d: 00012E 488B0E mov rcx, gword ptr [rsi] IN002e: 000131 48894C2428 mov gword ptr [rsp+28H], rcx IN002f: 000136 4883C608 add rsi, 8 IN0030: 00013A 4883C708 add rdi, 8 gcrReg -[rcx] IN0031: 00013E B906000000 mov ecx, 6 IN0032: 000143 F348A5 rep movsq IN0033: 000146 488B7DE8 mov rdi, qword ptr [rbp-18H] IN0034: 00014A 488B75F0 mov rsi, qword ptr [rbp-10H] ; Call at 014E [stk=0], GCvars=none, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0035: 00014E E8E5B9FFFF call Unity.Jobs.IJobExtensions:Schedule(FlushSendJob,Unity.Jobs.JobHandle):Unity.Jobs.JobHandle IN0036: 000153 48898568FFFFFF mov qword ptr [rbp-98H], rax IN0037: 00015A 48899570FFFFFF mov qword ptr [rbp-90H], rdx IN0038: 000161 488B8568FFFFFF mov rax, qword ptr [rbp-98H] IN0039: 000168 488B9570FFFFFF mov rdx, qword ptr [rbp-90H] ;; bbWeight=1 PerfScore 123.58 G_M38824_IG03: ; func=00, offs=00017DH, size=0006H, epilog, nogc, extend Block predicted offs = 0000017D, actual = 0000016F -> size adj = 14 IN004b: 00016F 488D6500 lea rsp, [rbp] IN004c: 000173 5D pop rbp IN004d: 000174 C3 ret ;; bbWeight=1 PerfScore 2.00Allocated method code size = 387 , actual size = 373 ; Total bytes of code 373, prolog size 70, PerfScore 177.12, (MethodHash=08be6857) for method Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this ; ============================================================ *************** After end code gen, before unwindEmit() G_M38824_IG01: ; func=00, offs=000000H, size=0052H, bbWeight=1 PerfScore 12.83, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc, isz <-- Prolog IG IN003a: 000000 push rbp IN003b: 000001 sub rsp, 256 IN003c: 000008 vzeroupper IN003d: 00000B lea rbp, [rsp+100H] IN003e: 000013 xor rax, rax IN003f: 000015 mov qword ptr [rbp-88H], rax IN0040: 00001C vxorps xmm8, xmm8 IN0041: 000021 mov rax, -96 IN0042: 00002B vmovdqa xmmword ptr [rbp+rax-20H], xmm8 IN0043: 000031 vmovdqa xmmword ptr [rbp+rax-10H], xmm8 IN0044: 000037 vmovdqa xmmword ptr [rax+rbp], xmm8 IN0045: 00003C add rax, 48 IN0046: 000040 jne SHORT -5 instr IN0047: 000042 mov qword ptr [rbp-20H], rax IN0048: 000046 mov bword ptr [V00 rbp-08H], rdi IN0049: 00004A mov qword ptr [V02 rbp-18H], rsi IN004a: 00004E mov qword ptr [V02+0x8 rbp-10H], rdx G_M38824_IG02: ; offs=000052H, size=011DH, bbWeight=1 PerfScore 123.58, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, isz IN0001: 000052 mov rdi, 0x7F6678BEB1C0 IN0002: 00005C call CORINFO_HELP_NEWSFAST IN0003: 000061 mov gword ptr [V05 rbp-80H], rax IN0004: 000065 mov rdi, gword ptr [V05 rbp-80H] IN0005: 000069 mov eax, dword ptr [V02+0x8 rbp-10H] IN0006: 00006C mov dword ptr [rdi+8], eax IN0007: 00006F mov rdi, 0x7F6678C127F0 IN0008: 000079 call CORINFO_HELP_NEWSFAST IN0009: 00007E mov gword ptr [V06 rbp-88H], rax IN000a: 000085 mov rsi, gword ptr [V06 rbp-88H] IN000b: 00008C mov rdx, qword ptr [V02 rbp-18H] IN000c: 000090 mov qword ptr [rsi+8], rdx IN000d: 000094 mov rsi, gword ptr [V05 rbp-80H] IN000e: 000098 mov rdx, gword ptr [V06 rbp-88H] IN000f: 00009F mov rdi, 0x7F66640084D0 IN0010: 0000A9 mov rdi, gword ptr [rdi] IN0011: 0000AC call System.String:Format(System.String,System.Object,System.Object):System.String IN0012: 0000B1 mov rdi, rax IN0013: 0000B4 call UnityEngine.Debug:Log(System.Object) IN0014: 0000B9 vxorps xmm0, xmm0 IN0015: 0000BD vmovdqu xmmword ptr [V03 rbp-78H], xmm0 IN0016: 0000C2 vmovdqu xmmword ptr [V03+0x10 rbp-68H], xmm0 IN0017: 0000C7 vmovdqu xmmword ptr [V03+0x20 rbp-58H], xmm0 IN0018: 0000CC vmovdqu xmmword ptr [V03+0x30 rbp-48H], xmm0 IN0019: 0000D1 vmovdqu xmmword ptr [V03+0x40 rbp-38H], xmm0 IN001a: 0000D6 vmovdqu xmmword ptr [V03+0x50 rbp-28H], xmm0 IN001b: 0000DB mov rsi, bword ptr [V00 rbp-08H] IN001c: 0000DF add rsi, 16 IN001d: 0000E3 lea rdi, bword ptr [V03 rbp-78H] IN001e: 0000E7 add rdi, 40 IN001f: 0000EB call CORINFO_HELP_ASSIGN_BYREF IN0020: 0000F0 mov ecx, 6 IN0021: 0000F5 rep movsq IN0022: 0000F8 mov rdi, bword ptr [V00 rbp-08H] IN0023: 0000FC vmovdqu xmm0, xmmword ptr [rdi+112] IN0024: 000101 vmovdqu xmmword ptr [V03 rbp-78H], xmm0 IN0025: 000106 vmovdqu xmm0, xmmword ptr [rdi+128] IN0026: 00010E vmovdqu xmmword ptr [V03+0x10 rbp-68H], xmm0 IN0027: 000113 mov rsi, qword ptr [rdi+144] IN0028: 00011A mov qword ptr [V03+0x20 rbp-58H], rsi IN0029: 00011E lea rdi, [V04 rsp] IN002a: 000122 lea rsi, [V03 rbp-78H] IN002b: 000126 mov ecx, 5 IN002c: 00012B rep movsq IN002d: 00012E mov rcx, gword ptr [rsi] IN002e: 000131 mov gword ptr [V04+0x28 rsp+28H], rcx IN002f: 000136 add rsi, 8 IN0030: 00013A add rdi, 8 IN0031: 00013E mov ecx, 6 IN0032: 000143 rep movsq IN0033: 000146 mov rdi, qword ptr [V02 rbp-18H] IN0034: 00014A mov rsi, qword ptr [V02+0x8 rbp-10H] IN0035: 00014E call Unity.Jobs.IJobExtensions:Schedule(FlushSendJob,Unity.Jobs.JobHandle):Unity.Jobs.JobHandle IN0036: 000153 mov qword ptr [V07 rbp-98H], rax IN0037: 00015A mov qword ptr [V07+0x8 rbp-90H], rdx IN0038: 000161 mov rax, qword ptr [V07 rbp-98H] IN0039: 000168 mov rdx, qword ptr [V07+0x8 rbp-90H] G_M38824_IG03: ; offs=00016FH, size=0006H, bbWeight=1 PerfScore 2.00, epilog, nogc, extend IN004b: 00016F lea rsp, [rbp] IN004c: 000173 pop rbp IN004d: 000174 ret *************** Finishing PHASE Emit code *************** Starting PHASE Emit GC+EH tables Unwind Info: >> Start offset : 0x000000 (not in unwind data) >> End offset : 0x000175 (not in unwind data) Version : 1 Flags : 0x00 SizeOfProlog : 0x08 CountOfUnwindCodes: 3 FrameRegister : none (0) FrameOffset : N/A (no FrameRegister) (Value=0) UnwindCodes : CodeOffset: 0x08 UnwindOp: UWOP_ALLOC_LARGE (1) OpInfo: 0 - Scaled small Size: 32 * 8 = 256 = 0x00100 CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5) allocUnwindInfo(pHotCode=0x00007F667A0D0730, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x175, unwindSize=0xa, pUnwindBlock=0x0000559EA55E7DBE, funKind=0 (main function)) *************** In genIPmappingGen() IP mapping count : 7 IL offs PROLOG : 0x00000000 ( STACK_EMPTY ) IL offs 0x0000 : 0x00000052 ( STACK_EMPTY ) IL offs 0x0025 : 0x000000B9 ( STACK_EMPTY ) IL offs 0x002D : 0x000000DB ( STACK_EMPTY ) IL offs 0x003A : 0x000000F8 ( STACK_EMPTY ) IL offs 0x0047 : 0x0000011E ( STACK_EMPTY ) IL offs EPILOG : 0x0000016F ( STACK_EMPTY ) *************** In genSetScopeInfo() VarLocInfo count is 7 *************** Variable debug info 7 live ranges 0( UNKNOWN) : From 00000000h to 00000052h, in rdi 1( UNKNOWN) : From 00000000h to 00000052h, in rsp[8] (1 slot) 2( UNKNOWN) : From 00000000h to 00000052h, in rsi 0( UNKNOWN) : From 00000052h to 0000016Fh, in rbp[-8] (1 slot) 1( UNKNOWN) : From 00000052h to 0000016Fh, in rbp[16] (1 slot) 2( UNKNOWN) : From 00000052h to 0000016Fh, in rbp[-24] (1 slot) 3( UNKNOWN) : From 00000052h to 0000016Fh, in rbp[-120] (1 slot) *************** In gcInfoBlockHdrSave() Set code length to 373. **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 Set ReturnKind to Scalar. Set stack base register to rbp. Set Outgoing stack arg area size to 96. Stack slot id for offset -8 (0xfffffff8) (frame) (byref, untracked) = 0. Stack slot id for offset 16 (0x10) (frame) (untracked) = 1. Stack slot id for offset -80 (0xffffffb0) (frame) (untracked) = 2. Stack slot id for offset -128 (0xffffff80) (frame) (untracked) = 3. Stack slot id for offset -136 (0xffffff78) (frame) (untracked) = 4. Defining 0 call sites: *************** Finishing PHASE Emit GC+EH tables Method code size: 373 Allocations for Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this (MethodHash=08be6857) count: 805, size: 64342, max = 2368 allocateMemory: 131072, nraUsed: 66832 Alloc'd bytes by kind: kind | size | pct ---------------------+------------+-------- AssertionProp | 0 | 0.00% ASTNode | 14048 | 21.83% InstDesc | 7224 | 11.23% ImpStack | 384 | 0.60% BasicBlock | 856 | 1.33% fgArgInfo | 576 | 0.90% fgArgInfoPtrArr | 160 | 0.25% FlowList | 0 | 0.00% TreeStatementList | 0 | 0.00% SiScope | 472 | 0.73% DominatorMemory | 0 | 0.00% LSRA | 2728 | 4.24% LSRA_Interval | 2960 | 4.60% LSRA_RefPosition | 11520 | 17.90% Reachability | 0 | 0.00% SSA | 0 | 0.00% ValueNumber | 0 | 0.00% LvaTable | 1920 | 2.98% UnwindInfo | 0 | 0.00% hashBv | 40 | 0.06% bitset | 232 | 0.36% FixedBitVect | 16 | 0.02% Generic | 1502 | 2.33% LocalAddressVisitor | 0 | 0.00% FieldSeqStore | 416 | 0.65% ZeroOffsetFieldMap | 136 | 0.21% ArrayInfoMap | 0 | 0.00% MemoryPhiArg | 0 | 0.00% CSE | 0 | 0.00% GC | 1556 | 2.42% CorTailCallInfo | 0 | 0.00% Inlining | 128 | 0.20% ArrayStack | 0 | 0.00% DebugInfo | 384 | 0.60% DebugOnly | 15004 | 23.32% Codegen | 1184 | 1.84% LoopOpt | 0 | 0.00% LoopHoist | 0 | 0.00% Unknown | 332 | 0.52% RangeCheck | 0 | 0.00% CopyProp | 0 | 0.00% SideEffects | 0 | 0.00% ObjectAllocator | 0 | 0.00% VariableLiveRanges | 0 | 0.00% ClassLayout | 564 | 0.88% TailMergeThrows | 0 | 0.00% EarlyProp | 0 | 0.00% ZeroInit | 0 | 0.00% ****** DONE compiling Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this ScheduleSend: version=0 jobgroup=21 ScheduleSend: version=0 jobgroup=45 RPCSystem: jobgroup=71 version=0 ****** START compiling Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this (MethodHash=853e07c9) Generating code for Unix x64 OPTIONS: Tier-0 compilation (set COMPlus_TieredCompilation=0 to disable) OPTIONS: compCodeOpt = BLENDED_CODE OPTIONS: compDbgCode = false OPTIONS: compDbgInfo = true OPTIONS: compDbgEnC = false OPTIONS: compProcedureSplitting = false OPTIONS: compProcedureSplittingEH = false IL to import: IL_0000 72 5f 11 00 70 ldstr 0x7000115F IL_0005 03 ldarg.1 IL_0006 7b 26 01 00 0a ldfld 0xA000126 IL_000b 8c 18 00 00 01 box 0x1000018 IL_0010 03 ldarg.1 IL_0011 7b 25 01 00 0a ldfld 0xA000125 IL_0016 8c 11 00 00 01 box 0x1000011 IL_001b 28 27 01 00 0a call 0xA000127 IL_0020 28 6b 00 00 0a call 0xA00006B IL_0025 7e d6 00 00 04 ldsfld 0x40000D6 IL_002a 02 ldarg.0 IL_002b 7b d7 00 00 04 ldfld 0x40000D7 IL_0030 6f 5d 01 00 0a callvirt 0xA00015D IL_0035 02 ldarg.0 IL_0036 7b d9 00 00 04 ldfld 0x40000D9 IL_003b 03 ldarg.1 IL_003c 6f c2 01 00 06 callvirt 0x60001C2 IL_0041 2a ret **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 'this' passed in register rdi **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 Arg #1 passed in register(s) firstEightByte: rsi, secondEightByte: rdx lvaGrabTemp returning 2 (V02 tmp0) (a long lifetime temp) called for OutgoingArgSpace. ; Initial local variable assignments ; ; V00 this byref this ; V01 arg1 struct ; V02 OutArgs lclBlk "OutgoingArgSpace" *************** In compInitDebuggingInfo() for Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this getVars() returned cVars = 0, extendOthers = true info.compVarScopesCount = 2 VarNum LVNum Name Beg End 0: 00h 00h V00 this 000h 042h 1: 01h 01h V01 arg1 000h 042h info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE ) *************** In fgFindBasicBlocks() for Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this Jump targets: none New Basic Block BB01 [0000] created. BB01 [000..042) CLFLG_MINOPT set for method Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this IL Code Size,Instr 66, 18, Basic Block count 1, Local Variable Num,Ref count 3, 5 for method Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this IL Code Size,Instr 66, 18, Basic Block count 1, Local Variable Num,Ref count 3, 5 for method Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this OPTIONS: opts.MinOpts() == true Basic block list for 'Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Pre-import *************** Finishing PHASE Pre-import *************** Starting PHASE Importation *************** In impImport() for Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this impImportBlockPending for BB01 Importing BB01 (PC=000) of 'Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' [ 0] 0 (0x000) ldstr 7000115F [ 1] 5 (0x005) ldarg.1 [ 2] 6 (0x006) ldfld 0A000126 [ 2] 11 (0x00b) box 01000018 Compiler::impImportAndPushBox -- handling BOX(value class) via inline allocate/copy sequence lvaGrabTemp returning 3 (V03 tmp1) called for Reusable Box Helper. STMT00000 (IL 0x000... ???) [000007] -A---------- * ASG ref [000006] D------N---- +--* LCL_VAR ref V03 tmp1 [000005] ------------ \--* ALLOCOBJ ref [000004] ------------ \--* CNS_INT(h) long 0x7f6678c127f0 class STMT00001 (IL ???... ???) [000012] -A--G------- * ASG long [000011] -------N---- +--* IND long [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V03 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ----G------- \--* FIELD long JobGroup [000002] ------------ \--* ADDR byref [000001] -------N---- \--* LCL_VAR struct V01 arg1 [ 2] 16 (0x010) ldarg.1 [ 3] 17 (0x011) ldfld 0A000125 [ 3] 22 (0x016) box 01000011 Compiler::impImportAndPushBox -- handling BOX(value class) via inline allocate/copy sequence lvaGrabTemp returning 4 (V04 tmp2) called for Reusable Box Helper. STMT00002 (IL ???... ???) [000021] -A---------- * ASG ref [000020] D------N---- +--* LCL_VAR ref V04 tmp2 [000019] ------------ \--* ALLOCOBJ ref [000018] ------------ \--* CNS_INT(h) long 0x7f6678beb1c0 class STMT00003 (IL ???... ???) [000026] -A--G------- * ASG int [000025] -------N---- +--* IND int [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V04 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ----G------- \--* FIELD int Version [000016] ------------ \--* ADDR byref [000015] -------N---- \--* LCL_VAR struct V01 arg1 [ 3] 27 (0x01b) call 0A000127 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 [ 1] 32 (0x020) call 0A00006B In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 STMT00004 (IL ???... ???) [000030] --C-G------- * CALL void UnityEngine.Debug.Log [000029] --C-G------- arg0 \--* CALL ref System.String.Format [000000] ------------ arg0 +--* CNS_STR ref [000014] ------------ arg1 +--* BOX ref [000013] ------------ | \--* LCL_VAR ref V03 tmp1 [000028] ------------ arg2 \--* BOX ref [000027] ------------ \--* LCL_VAR ref V04 tmp2 [ 0] 37 (0x025) ldsfld 040000D6 [ 1] 42 (0x02a) ldarg.0 [ 2] 43 (0x02b) ldfld 040000D7 [ 2] 48 (0x030) callvirt 0A00015D In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is ref, structSize is 0 [ 1] 53 (0x035) ldarg.0 [ 2] 54 (0x036) ldfld 040000D9 [ 2] 59 (0x03b) ldarg.1 [ 3] 60 (0x03c) callvirt 060001C2 In Compiler::impImportCall: opcode is callvirt, kind=2, callRetType is struct, structSize is 16 Calling impNormStructVal on: [000037] ------------ * LCL_VAR struct V01 arg1 resulting tree: [000040] n----------- * OBJ struct [000039] ------------ \--* ADDR byref [000037] -------N---- \--* LCL_VAR struct V01 arg1 Calling impNormStructVal on: [000036] ---XG------- * FIELD struct m_ParallelSendQueue [000035] ------------ \--* LCL_VAR byref V00 this resulting tree: [000042] ---XG------- * OBJ struct [000041] ---XG------- \--* ADDR byref [000036] ---XG--N---- \--* FIELD struct m_ParallelSendQueue [000035] ------------ \--* LCL_VAR byref V00 this **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 lvaGrabTemp returning 5 (V05 tmp3) called for Return value temp for multireg return. STMT00005 (IL 0x025... ???) [000045] -ACXG------- * ASG struct (copy) [000043] D------N---- +--* LCL_VAR struct V05 tmp3 [000038] --CXG------- \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA [000034] --CXG------- this in rdi +--* CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item [000031] ----G------- this in rdi | +--* FIELD ref s_NetworkInterfaces [000033] ---XG------- arg1 | \--* FIELD int m_NetworkInterfaceIndex [000032] ------------ | \--* LCL_VAR byref V00 this [000042] ---XG------- arg1 +--* OBJ struct [000041] ---XG------- | \--* ADDR byref [000036] ---XG--N---- | \--* FIELD struct m_ParallelSendQueue [000035] ------------ | \--* LCL_VAR byref V00 this [000040] n----------- arg2 \--* OBJ struct [000039] ------------ \--* ADDR byref [000037] -------N---- \--* LCL_VAR struct V01 arg1 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 [ 1] 65 (0x041) ret impFixupStructReturnType: retyping [000046] -------N---- * LCL_VAR struct V05 tmp3 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 STMT00006 (IL ???... ???) [000047] ------------ * RETURN struct [000046] -------N---- \--* LCL_VAR struct V05 tmp3 *************** Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) (return) i newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) (return), preds={} succs={} ***** BB01 STMT00000 (IL 0x000...0x041) [000007] -A---------- * ASG ref [000006] D------N---- +--* LCL_VAR ref V03 tmp1 [000005] ------------ \--* ALLOCOBJ ref [000004] ------------ \--* CNS_INT(h) long 0x7f6678c127f0 class ***** BB01 STMT00001 (IL ???... ???) [000012] -A--G------- * ASG long [000011] -------N---- +--* IND long [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V03 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ----G------- \--* FIELD long JobGroup [000002] ------------ \--* ADDR byref [000001] -------N---- \--* LCL_VAR struct V01 arg1 ***** BB01 STMT00002 (IL ???... ???) [000021] -A---------- * ASG ref [000020] D------N---- +--* LCL_VAR ref V04 tmp2 [000019] ------------ \--* ALLOCOBJ ref [000018] ------------ \--* CNS_INT(h) long 0x7f6678beb1c0 class ***** BB01 STMT00003 (IL ???... ???) [000026] -A--G------- * ASG int [000025] -------N---- +--* IND int [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V04 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ----G------- \--* FIELD int Version [000016] ------------ \--* ADDR byref [000015] -------N---- \--* LCL_VAR struct V01 arg1 ***** BB01 STMT00004 (IL ???... ???) [000030] --C-G------- * CALL void UnityEngine.Debug.Log [000029] --C-G------- arg0 \--* CALL ref System.String.Format [000000] ------------ arg0 +--* CNS_STR ref [000014] ------------ arg1 +--* BOX ref [000013] ------------ | \--* LCL_VAR ref V03 tmp1 [000028] ------------ arg2 \--* BOX ref [000027] ------------ \--* LCL_VAR ref V04 tmp2 ***** BB01 STMT00005 (IL 0x025... ???) [000045] -ACXG------- * ASG struct (copy) [000043] D------N---- +--* LCL_VAR struct V05 tmp3 [000038] --CXG------- \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA [000034] --CXG------- this in rdi +--* CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item [000031] ----G------- this in rdi | +--* FIELD ref s_NetworkInterfaces [000033] ---XG------- arg1 | \--* FIELD int m_NetworkInterfaceIndex [000032] ------------ | \--* LCL_VAR byref V00 this [000042] ---XG------- arg1 +--* OBJ struct [000041] ---XG------- | \--* ADDR byref [000036] ---XG--N---- | \--* FIELD struct m_ParallelSendQueue [000035] ------------ | \--* LCL_VAR byref V00 this [000040] n----------- arg2 \--* OBJ struct [000039] ------------ \--* ADDR byref [000037] -------N---- \--* LCL_VAR struct V01 arg1 ***** BB01 STMT00006 (IL ???... ???) [000047] ------------ * RETURN struct [000046] -------N---- \--* LCL_VAR struct V05 tmp3 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Indirect call transform -- no candidates to transform *************** Finishing PHASE Indirect call transform [no changes] *************** Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Finishing PHASE Expand patchpoints [no changes] *************** Starting PHASE Post-import *************** Finishing PHASE Post-import *************** Starting PHASE Morph - Init New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short) *************** In fgRemoveEmptyBlocks *************** Finishing PHASE Morph - Init *************** In fgDebugCheckBBlist *************** Starting PHASE Morph - Inlining *************** Finishing PHASE Morph - Inlining [no changes] *************** Starting PHASE Allocate Objects disabled, punting *************** Finishing PHASE Allocate Objects [no changes] *************** Starting PHASE Morph - Add internal blocks *************** After fgAddInternal() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) (return) i newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** Finishing PHASE Morph - Add internal blocks *************** Starting PHASE Remove empty try *************** In fgRemoveEmptyTry() No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty try [no changes] *************** Starting PHASE Remove empty finally No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty finally [no changes] *************** Starting PHASE Merge callfinally chains No EH in this method, nothing to merge. *************** Finishing PHASE Merge callfinally chains [no changes] *************** Starting PHASE Clone finally No EH in this method, no cloning. *************** Finishing PHASE Clone finally [no changes] *************** Starting PHASE Compute preds Renumbering the basic blocks for fgComputePred *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) (return) i newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** After renumbering the basic blocks =============== No blocks renumbered! *************** In fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) (return) i newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** After fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) (return) i label target newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Compute preds *************** Starting PHASE Morph - Promote Structs *************** In fgPromoteStructs() promotion opt flag not enabled *************** Finishing PHASE Morph - Promote Structs *************** Starting PHASE Morph - Structs/AddrExp *************** In fgMarkAddressExposedLocals() LocalAddressVisitor visiting statement: STMT00000 (IL 0x000...0x041) [000007] -AC--------- * ASG ref [000006] D------N---- +--* LCL_VAR ref V03 tmp1 [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000004] ------------ arg0 \--* CNS_INT(h) long 0x7f6678c127f0 class LocalAddressVisitor visiting statement: STMT00001 (IL ???... ???) [000012] -A--G------- * ASG long [000011] -------N---- +--* IND long [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V03 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ----G------- \--* FIELD long JobGroup [000002] ------------ \--* ADDR byref [000001] -------N---- \--* LCL_VAR struct V01 arg1 Local V01 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00001 (IL ???... ???) [000012] -A--G------- * ASG long [000011] -------N---- +--* IND long [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V03 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ------------ \--* LCL_FLD long V01 arg1 [+0] Fseq[JobGroup] LocalAddressVisitor visiting statement: STMT00002 (IL ???... ???) [000021] -AC--------- * ASG ref [000020] D------N---- +--* LCL_VAR ref V04 tmp2 [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000018] ------------ arg0 \--* CNS_INT(h) long 0x7f6678beb1c0 class LocalAddressVisitor visiting statement: STMT00003 (IL ???... ???) [000026] -A--G------- * ASG int [000025] -------N---- +--* IND int [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V04 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ----G------- \--* FIELD int Version [000016] ------------ \--* ADDR byref [000015] -------N---- \--* LCL_VAR struct V01 arg1 Local V01 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00003 (IL ???... ???) [000026] -A--G------- * ASG int [000025] -------N---- +--* IND int [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V04 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ------------ \--* LCL_FLD int V01 arg1 [+8] Fseq[Version] LocalAddressVisitor visiting statement: STMT00004 (IL ???... ???) [000030] --C-G------- * CALL void UnityEngine.Debug.Log [000029] --C-G------- arg0 \--* CALL ref System.String.Format [000000] ------------ arg0 +--* CNS_STR ref [000014] ------------ arg1 +--* BOX ref [000013] ------------ | \--* LCL_VAR ref V03 tmp1 [000028] ------------ arg2 \--* BOX ref [000027] ------------ \--* LCL_VAR ref V04 tmp2 LocalAddressVisitor visiting statement: STMT00005 (IL 0x025... ???) [000045] -ACXG------- * ASG struct (copy) [000043] D------N---- +--* LCL_VAR struct V05 tmp3 [000038] --CXG------- \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA [000034] --CXG------- this in rdi +--* CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item [000031] ----G------- this in rdi | +--* FIELD ref s_NetworkInterfaces [000033] ---XG------- arg1 | \--* FIELD int m_NetworkInterfaceIndex [000032] ------------ | \--* LCL_VAR byref V00 this [000042] ---XG------- arg1 +--* OBJ struct [000041] ---XG------- | \--* ADDR byref [000036] ---XG--N---- | \--* FIELD struct m_ParallelSendQueue [000035] ------------ | \--* LCL_VAR byref V00 this [000040] n----------- arg2 \--* OBJ struct [000039] ------------ \--* ADDR byref [000037] -------N---- \--* LCL_VAR struct V01 arg1 LocalAddressVisitor visiting statement: STMT00006 (IL ???... ???) [000047] ------------ * RETURN struct [000046] -------N---- \--* LCL_VAR struct V05 tmp3 *************** Finishing PHASE Morph - Structs/AddrExp *************** Starting PHASE Morph - ByRefs *************** Finishing PHASE Morph - ByRefs *************** Starting PHASE Morph - Global *************** In fgMorphBlocks() Morphing BB01 of 'Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' fgMorphTree BB01, STMT00000 (before) [000007] -AC--------- * ASG ref [000006] D------N---- +--* LCL_VAR ref V03 tmp1 [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000004] ------------ arg0 \--* CNS_INT(h) long 0x7f6678c127f0 class Initializing arg info for 5.CALL: ArgTable for 5.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 4.CNS_INT long (By ref), 1 reg: rdi, align=1] Morphing args for 5.CALL: argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000004] -----+------ * CNS_INT(h) long 0x7f6678c127f0 class Replaced with placeholder node: [000048] ----------L- * ARGPLACE long Shuffled argument table: rdi ArgTable for 5.CALL after fgMorphArgs: fgArgTabEntry[arg 0 4.CNS_INT long (By ref), 1 reg: rdi, align=1, lateArgInx=0, processed] fgMorphTree BB01, STMT00000 (after) [000007] -AC--+------ * ASG ref [000006] D----+-N---- +--* LCL_VAR ref V03 tmp1 [000005] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000004] -----+------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class fgMorphTree BB01, STMT00001 (before) [000012] -A--G------- * ASG long [000011] -------N---- +--* IND long [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V03 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ------------ \--* LCL_FLD long V01 arg1 [+0] Fseq[JobGroup] fgMorphTree BB01, STMT00002 (before) [000021] -AC--------- * ASG ref [000020] D------N---- +--* LCL_VAR ref V04 tmp2 [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000018] ------------ arg0 \--* CNS_INT(h) long 0x7f6678beb1c0 class Initializing arg info for 19.CALL: ArgTable for 19.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 18.CNS_INT long (By ref), 1 reg: rdi, align=1] Morphing args for 19.CALL: argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000018] -----+------ * CNS_INT(h) long 0x7f6678beb1c0 class Replaced with placeholder node: [000049] ----------L- * ARGPLACE long Shuffled argument table: rdi ArgTable for 19.CALL after fgMorphArgs: fgArgTabEntry[arg 0 18.CNS_INT long (By ref), 1 reg: rdi, align=1, lateArgInx=0, processed] fgMorphTree BB01, STMT00002 (after) [000021] -AC--+------ * ASG ref [000020] D----+-N---- +--* LCL_VAR ref V04 tmp2 [000019] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000018] -----+------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class fgMorphTree BB01, STMT00003 (before) [000026] -A--G------- * ASG int [000025] -------N---- +--* IND int [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V04 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ------------ \--* LCL_FLD int V01 arg1 [+8] Fseq[Version] fgMorphTree BB01, STMT00004 (before) [000030] --C-G------- * CALL void UnityEngine.Debug.Log [000029] --C-G------- arg0 \--* CALL ref System.String.Format [000000] ------------ arg0 +--* CNS_STR ref [000014] ------------ arg1 +--* BOX ref [000013] ------------ | \--* LCL_VAR ref V03 tmp1 [000028] ------------ arg2 \--* BOX ref [000027] ------------ \--* LCL_VAR ref V04 tmp2 Initializing arg info for 30.CALL: ArgTable for 30.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 29.CALL ref (By ref), 1 reg: rdi, align=1] Morphing args for 30.CALL: Initializing arg info for 29.CALL: ArgTable for 29.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 0.CNS_STR ref (By ref), 1 reg: rdi, align=1] fgArgTabEntry[arg 1 14.BOX ref (By ref), 1 reg: rsi, align=1] fgArgTabEntry[arg 2 28.BOX ref (By ref), 1 reg: rdx, align=1] Morphing args for 29.CALL: argSlots=3, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rsi'): ( 9, 6) [000014] ------------ * BOX ref ( 3, 2) [000013] ------------ \--* LCL_VAR ref V03 tmp1 Replaced with placeholder node: [000052] ----------L- * ARGPLACE ref Deferred argument ('rdx'): ( 9, 6) [000028] ------------ * BOX ref ( 3, 2) [000027] ------------ \--* LCL_VAR ref V04 tmp2 Replaced with placeholder node: [000053] ----------L- * ARGPLACE ref Deferred argument ('rdi'): ( 4, 12) [000051] n---G------- * IND ref ( 2, 10) [000050] ------------ \--* CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] Replaced with placeholder node: [000054] ----------L- * ARGPLACE ref Shuffled argument table: rsi rdx rdi ArgTable for 29.CALL after fgMorphArgs: fgArgTabEntry[arg 1 14.BOX ref (By ref), 1 reg: rsi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 2 28.BOX ref (By ref), 1 reg: rdx, align=1, lateArgInx=1, processed] fgArgTabEntry[arg 0 51.IND ref (By ref), 1 reg: rdi, align=1, lateArgInx=2, processed] argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000029] --CXG+------ * CALL ref System.String.Format ( 9, 6) [000014] ------------ arg1 in rsi +--* BOX ref ( 3, 2) [000013] ------------ | \--* LCL_VAR ref V03 tmp1 ( 9, 6) [000028] ------------ arg2 in rdx +--* BOX ref ( 3, 2) [000027] ------------ | \--* LCL_VAR ref V04 tmp2 ( 4, 12) [000051] n---G------- arg0 in rdi \--* IND ref ( 2, 10) [000050] ------------ \--* CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] Replaced with placeholder node: [000055] ----------L- * ARGPLACE ref Shuffled argument table: rdi ArgTable for 30.CALL after fgMorphArgs: fgArgTabEntry[arg 0 29.CALL ref (By ref), 1 reg: rdi, align=1, lateArgInx=0, processed] fgMorphTree BB01, STMT00004 (after) [000030] --CXG+------ * CALL void UnityEngine.Debug.Log [000029] --CXG+------ arg0 in rdi \--* CALL ref System.String.Format ( 9, 6) [000014] ------------ arg1 in rsi +--* BOX ref ( 3, 2) [000013] ------------ | \--* LCL_VAR ref V03 tmp1 ( 9, 6) [000028] ------------ arg2 in rdx +--* BOX ref ( 3, 2) [000027] ------------ | \--* LCL_VAR ref V04 tmp2 ( 4, 12) [000051] n---G------- arg0 in rdi \--* IND ref ( 2, 10) [000050] ------------ \--* CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] fgMorphTree BB01, STMT00005 (before) [000045] -ACXG------- * ASG struct (copy) [000043] D------N---- +--* LCL_VAR struct V05 tmp3 [000038] --CXG------- \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA [000034] --CXG------- this in rdi +--* CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item [000031] ----G------- this in rdi | +--* FIELD ref s_NetworkInterfaces [000033] ---XG------- arg1 | \--* FIELD int m_NetworkInterfaceIndex [000032] ------------ | \--* LCL_VAR byref V00 this [000042] ---XG------- arg1 +--* OBJ struct [000041] ---XG------- | \--* ADDR byref [000036] ---XG--N---- | \--* FIELD struct m_ParallelSendQueue [000035] ------------ | \--* LCL_VAR byref V00 this [000040] n----------- arg2 \--* OBJ struct [000039] ------------ \--* ADDR byref [000037] -------N---- \--* LCL_VAR struct V01 arg1 Initializing arg info for 38.CALL: **** getSystemVAmd64PassStructInRegisterDescriptor(0x79670b20 (Unity.Collections.NativeQueue`1[QueuedSendMessage]), ...) => passedInRegisters = false **** getSystemVAmd64PassStructInRegisterDescriptor(0x79670b20 (Unity.Collections.NativeQueue`1[QueuedSendMessage]), ...) => passedInRegisters = false **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 ArgTable for 38.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 34.CALL ref (By ref), 1 reg: rdi, align=1] fgArgTabEntry[arg 1 56.CNS_INT long (By ref), 1 reg: r11, align=1, isNonStandard] fgArgTabEntry[arg 2 42.OBJ struct (By value), numSlots=7, slotNum=0, align=1, isStruct] fgArgTabEntry[arg 3 40.OBJ struct (By value), 2 regs: rsi rdx, align=1, isStruct] Morphing args for 38.CALL: Initializing arg info for 34.CALL: ArgTable for 34.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 31.FIELD ref (By ref), 1 reg: rdi, align=1] fgArgTabEntry[arg 1 33.FIELD int (By ref), 1 reg: rsi, align=1] Morphing args for 34.CALL: Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000033] *--XG------- * IND int [000059] -----+------ \--* ADD byref [000032] -----+------ +--* LCL_VAR byref V00 this [000058] -----+------ \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] argSlots=2, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rsi'): ( 6, 5) [000033] *--XG------- * IND int ( 4, 3) [000059] -------N---- \--* ADD byref ( 3, 2) [000032] ------------ +--* LCL_VAR byref V00 this ( 1, 1) [000058] ------------ \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] Replaced with placeholder node: [000060] ----------L- * ARGPLACE int Deferred argument ('rdi'): ( 4, 12) [000031] n---G------- * IND ref ( 2, 10) [000057] ------------ \--* CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] Replaced with placeholder node: [000061] ----------L- * ARGPLACE ref Shuffled argument table: rsi rdi ArgTable for 34.CALL after fgMorphArgs: fgArgTabEntry[arg 1 33.IND int (By ref), 1 reg: rsi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 0 31.IND ref (By ref), 1 reg: rdi, align=1, lateArgInx=1, processed] Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000036] *--XG--N---- * IND struct [000063] -----+------ \--* ADD byref [000035] -----+------ +--* LCL_VAR byref V00 this [000062] -----+------ \--* CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] argSlots=10, preallocatedArgCount=7, nextSlotNum=7, outgoingArgSpaceSize=56 Sorting the arguments: Argument with 'side effect'... [000034] --CXG+------ * CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item ( 6, 5) [000033] *--XG------- arg1 in rsi +--* IND int ( 4, 3) [000059] -------N---- | \--* ADD byref ( 3, 2) [000032] ------------ | +--* LCL_VAR byref V00 this ( 1, 1) [000058] ------------ | \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] ( 4, 12) [000031] n---G------- this in rdi \--* IND ref ( 2, 10) [000057] ------------ \--* CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] lvaGrabTemp returning 6 (V06 tmp4) called for argument with side effect. Evaluate to a temp: [000065] -ACXG-----L- * ASG ref [000064] D------N---- +--* LCL_VAR ref V06 tmp4 [000034] --CXG+------ \--* CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item ( 6, 5) [000033] *--XG------- arg1 in rsi +--* IND int ( 4, 3) [000059] -------N---- | \--* ADD byref ( 3, 2) [000032] ------------ | +--* LCL_VAR byref V00 this ( 1, 1) [000058] ------------ | \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] ( 4, 12) [000031] n---G------- this in rdi \--* IND ref ( 2, 10) [000057] ------------ \--* CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] Deferred argument ('rsi'): ( 9, 7) [000040] n----------- * OBJ struct ( 3, 3) [000039] ------------ \--* ADDR byref ( 3, 2) [000037] -------N---- \--* LCL_VAR struct V01 arg1 Replaced with placeholder node: [000067] ----------L- * ARGPLACE struct => [clsHnd=795C7A00] Deferred argument ('r11'): [000056] -----+------ * CNS_INT(h) long 0x7f6678060338 ftn REG r11 Replaced with placeholder node: [000068] ----------L- * ARGPLACE long Shuffled argument table: rdi rsi r11 Multireg struct argument V01 : fgArgTabEntry[arg 3 40.OBJ struct (By value), 2 regs: rsi rdx, align=1, lateArgInx=1, processed, isStruct] Local V01 should not be enregistered because: was accessed as a local field Local V01 should not be enregistered because: was accessed as a local field fgMorphMultiregStructArg created tree: [000069] -c---------- * FIELD_LIST struct [000070] ------------ ofs 0 +--* LCL_FLD long V01 arg1 [+0] [000071] ------------ ofs 8 \--* LCL_FLD long V01 arg1 [+8] ArgTable for 38.CALL after fgMorphArgs: fgArgTabEntry[arg 0 66.LCL_VAR ref (By ref), 1 reg: rdi, align=1, lateArgInx=0, tmpNum=V06, isTmp, processed] fgArgTabEntry[arg 2 42.OBJ struct (By value), numSlots=7, slotNum=0, align=1, processed, isStruct] fgArgTabEntry[arg 3 69.FIELD_LIST struct (By value), 2 regs: rsi rdx, align=1, lateArgInx=1, processed, isStruct] fgArgTabEntry[arg 1 56.CNS_INT long (By ref), 1 reg: r11, align=1, lateArgInx=2, processed, isNonStandard] fgMorphCopyBlock: not morphing a multireg call return fgMorphTree BB01, STMT00005 (after) [000045] -ACXG+------ * ASG struct (copy) [000043] D----+-N---- +--* LCL_VAR struct V05 tmp3 [000038] --CXG+------ \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA [000065] -ACXG-----L- this SETUP +--* ASG ref [000064] D------N---- | +--* LCL_VAR ref V06 tmp4 [000034] --CXG+------ | \--* CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item ( 6, 5) [000033] *--XG------- arg1 in rsi | +--* IND int ( 4, 3) [000059] -------N---- | | \--* ADD byref ( 3, 2) [000032] ------------ | | +--* LCL_VAR byref V00 this ( 1, 1) [000058] ------------ | | \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] ( 4, 12) [000031] n---G------- this in rdi | \--* IND ref ( 2, 10) [000057] ------------ | \--* CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] ( 11, 8) [000042] ---XG------- arg2 out+00 +--* OBJ struct ( 5, 4) [000063] ------------ | \--* ADD byref ( 3, 2) [000035] ------------ | +--* LCL_VAR byref V00 this ( 1, 1) [000062] ------------ | \--* CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] [000066] ------------ this in rdi +--* LCL_VAR ref V06 tmp4 [000069] -c---------- arg3 rsi,rdx +--* FIELD_LIST struct [000070] ------------ ofs 0 | +--* LCL_FLD long V01 arg1 [+0] [000071] ------------ ofs 8 | \--* LCL_FLD long V01 arg1 [+8] [000056] -----+------ arg1 in r11 \--* CNS_INT(h) long 0x7f6678060338 ftn REG r11 fgMorphTree BB01, STMT00006 (before) [000047] ------------ * RETURN struct [000046] -------N---- \--* LCL_VAR struct V05 tmp3 *************** Finishing PHASE Morph - Global Trees after Morph - Global ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) (return), preds={} succs={} ***** BB01 STMT00000 (IL 0x000...0x041) [000007] -AC--+------ * ASG ref [000006] D----+-N---- +--* LCL_VAR ref V03 tmp1 [000005] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000004] -----+------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class ***** BB01 STMT00001 (IL ???... ???) [000012] -A-XG+------ * ASG long [000011] ---X-+-N---- +--* IND long [000010] -----+------ | \--* ADD byref [000008] -----+------ | +--* LCL_VAR ref V03 tmp1 [000009] -----+------ | \--* CNS_INT long 8 [000003] -----+------ \--* LCL_FLD long V01 arg1 [+0] Fseq[JobGroup] ***** BB01 STMT00002 (IL ???... ???) [000021] -AC--+------ * ASG ref [000020] D----+-N---- +--* LCL_VAR ref V04 tmp2 [000019] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000018] -----+------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class ***** BB01 STMT00003 (IL ???... ???) [000026] -A-XG+------ * ASG int [000025] ---X-+-N---- +--* IND int [000024] -----+------ | \--* ADD byref [000022] -----+------ | +--* LCL_VAR ref V04 tmp2 [000023] -----+------ | \--* CNS_INT long 8 [000017] -----+------ \--* LCL_FLD int V01 arg1 [+8] Fseq[Version] ***** BB01 STMT00004 (IL ???... ???) [000030] --CXG+------ * CALL void UnityEngine.Debug.Log [000029] --CXG+------ arg0 in rdi \--* CALL ref System.String.Format ( 9, 6) [000014] ------------ arg1 in rsi +--* BOX ref ( 3, 2) [000013] ------------ | \--* LCL_VAR ref V03 tmp1 ( 9, 6) [000028] ------------ arg2 in rdx +--* BOX ref ( 3, 2) [000027] ------------ | \--* LCL_VAR ref V04 tmp2 ( 4, 12) [000051] n---G------- arg0 in rdi \--* IND ref ( 2, 10) [000050] ------------ \--* CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] ***** BB01 STMT00005 (IL 0x025... ???) [000045] -ACXG+------ * ASG struct (copy) [000043] D----+-N---- +--* LCL_VAR struct V05 tmp3 [000038] --CXG+------ \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA [000065] -ACXG-----L- this SETUP +--* ASG ref [000064] D------N---- | +--* LCL_VAR ref V06 tmp4 [000034] --CXG+------ | \--* CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item ( 6, 5) [000033] *--XG------- arg1 in rsi | +--* IND int ( 4, 3) [000059] -------N---- | | \--* ADD byref ( 3, 2) [000032] ------------ | | +--* LCL_VAR byref V00 this ( 1, 1) [000058] ------------ | | \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] ( 4, 12) [000031] n---G------- this in rdi | \--* IND ref ( 2, 10) [000057] ------------ | \--* CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] ( 11, 8) [000042] ---XG------- arg2 out+00 +--* OBJ struct ( 5, 4) [000063] ------------ | \--* ADD byref ( 3, 2) [000035] ------------ | +--* LCL_VAR byref V00 this ( 1, 1) [000062] ------------ | \--* CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] [000066] ------------ this in rdi +--* LCL_VAR ref V06 tmp4 [000069] -c---------- arg3 rsi,rdx +--* FIELD_LIST struct [000070] ------------ ofs 0 | +--* LCL_FLD long V01 arg1 [+0] [000071] ------------ ofs 8 | \--* LCL_FLD long V01 arg1 [+8] [000056] -----+------ arg1 in r11 \--* CNS_INT(h) long 0x7f6678060338 ftn REG r11 ***** BB01 STMT00006 (IL ???... ???) [000047] -----+------ * RETURN struct [000046] -----+-N---- \--* LCL_VAR struct V05 tmp3 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE GS Cookie No GS security needed *************** Finishing PHASE GS Cookie *************** Starting PHASE Mark GC poll blocks *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** After renumbering the basic blocks =============== No blocks renumbered! *************** Finishing PHASE Mark GC poll blocks *************** Starting PHASE Compute edge weights (1, false) *************** In fgComputeBlockAndEdgeWeights() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- -- no profile data, so using default called count -- not optimizing, so not computing edge weights *************** Finishing PHASE Compute edge weights (1, false) *************** Starting PHASE Create EH funclets *************** In fgCreateFunclets() After fgCreateFunclets() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** Finishing PHASE Create EH funclets *************** Starting PHASE Mark local vars *************** In lvaMarkLocalVars() *** lvaComputeRefCounts *** *************** Finishing PHASE Mark local vars *************** Starting PHASE Find oper order *************** In fgFindOperOrder() *************** Finishing PHASE Find oper order *************** Starting PHASE Set block order *************** In fgSetBlockOrder() The biggest BB has 25 tree nodes *************** Finishing PHASE Set block order *************** Starting PHASE Insert GC Polls *************** Finishing PHASE Insert GC Polls [no changes] *************** Starting PHASE Determine first cold block *************** In fgDetermineFirstColdBlock() No procedure splitting will be done for this method *************** Finishing PHASE Determine first cold block Trees before Rationalize IR ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) (return), preds={} succs={} ***** BB01 STMT00000 (IL 0x000...0x041) N005 ( 20, 19) [000007] -AC-----R--- * ASG ref N004 ( 3, 2) [000006] D------N---- +--* LCL_VAR ref V03 tmp1 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class ***** BB01 STMT00001 (IL ???... ???) N006 ( 10, 10) [000012] -A-XG------- * ASG long N004 ( 6, 5) [000011] ---X---N---- +--* IND long N003 ( 4, 3) [000010] -------N---- | \--* ADD byref N001 ( 3, 2) [000008] ------------ | +--* LCL_VAR ref V03 tmp1 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD long V01 arg1 [+0] Fseq[JobGroup] ***** BB01 STMT00002 (IL ???... ???) N005 ( 20, 19) [000021] -AC-----R--- * ASG ref N004 ( 3, 2) [000020] D------N---- +--* LCL_VAR ref V04 tmp2 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class ***** BB01 STMT00003 (IL ???... ???) N006 ( 10, 10) [000026] -A-XG------- * ASG int N004 ( 6, 5) [000025] ---X---N---- +--* IND int N003 ( 4, 3) [000024] -------N---- | \--* ADD byref N001 ( 3, 2) [000022] ------------ | +--* LCL_VAR ref V04 tmp2 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD int V01 arg1 [+8] Fseq[Version] ***** BB01 STMT00004 (IL ???... ???) N012 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log N011 ( 36, 32) [000029] --CXG------- arg0 in rdi \--* CALL ref System.String.Format N006 ( 9, 6) [000014] ------------ arg1 in rsi +--* BOX ref N005 ( 3, 2) [000013] ------------ | \--* LCL_VAR ref V03 tmp1 N008 ( 9, 6) [000028] ------------ arg2 in rdx +--* BOX ref N007 ( 3, 2) [000027] ------------ | \--* LCL_VAR ref V04 tmp2 N010 ( 4, 12) [000051] n---G------- arg0 in rdi \--* IND ref N009 ( 2, 10) [000050] ------------ \--* CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] ***** BB01 STMT00005 (IL 0x025... ???) N025 ( 77, 70) [000045] -ACXG---R--- * ASG struct (copy) N024 ( 3, 2) [000043] D------N---- +--* LCL_VAR struct V05 tmp3 N023 ( 73, 67) [000038] --CXG------- \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA N011 ( 28, 28) [000065] -ACXG---R-L- this SETUP +--* ASG ref N010 ( 3, 2) [000064] D------N---- | +--* LCL_VAR ref V06 tmp4 N009 ( 24, 25) [000034] --CXG------- | \--* CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item N006 ( 6, 5) [000033] *--XG------- arg1 in rsi | +--* IND int N005 ( 4, 3) [000059] -------N---- | | \--* ADD byref N003 ( 3, 2) [000032] ------------ | | +--* LCL_VAR byref V00 this N004 ( 1, 1) [000058] ------------ | | \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] N008 ( 4, 12) [000031] n---G------- this in rdi | \--* IND ref N007 ( 2, 10) [000057] ------------ | \--* CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] N016 ( 11, 8) [000042] ---XG------- arg2 out+00 +--* OBJ struct N015 ( 5, 4) [000063] ------------ | \--* ADD byref N013 ( 3, 2) [000035] ------------ | +--* LCL_VAR byref V00 this N014 ( 1, 1) [000062] ------------ | \--* CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] N018 ( 3, 2) [000066] ------------ this in rdi +--* LCL_VAR ref V06 tmp4 N021 ( 6, 8) [000069] -c---------- arg3 rsi,rdx +--* FIELD_LIST struct N019 ( 3, 4) [000070] ------------ ofs 0 | +--* LCL_FLD long V01 arg1 [+0] N020 ( 3, 4) [000071] ------------ ofs 8 | \--* LCL_FLD long V01 arg1 [+8] N022 ( 2, 10) [000056] ------------ arg1 in r11 \--* CNS_INT(h) long 0x7f6678060338 ftn REG r11 ***** BB01 STMT00006 (IL ???... ???) N002 ( 4, 3) [000047] ------------ * RETURN struct N001 ( 3, 2) [000046] -------N---- \--* LCL_VAR struct V05 tmp3 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Rationalize IR rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 20, 19) [000007] DAC--------- * STORE_LCL_VAR ref V03 tmp1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 20, 19) [000021] DAC--------- * STORE_LCL_VAR ref V04 tmp2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N011 ( 28, 28) [000065] DACXG-----L- * STORE_LCL_VAR ref V06 tmp4 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N025 ( 77, 70) [000045] DACXG------- * STORE_LCL_VAR struct V05 tmp3 *************** Finishing PHASE Rationalize IR Trees after Rationalize IR ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) (return), preds={} succs={} [000072] ------------ IL_OFFSET void IL offset: 0x0 N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class /--* t4 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t5 ref N005 ( 20, 19) [000007] DA---------- * STORE_LCL_VAR ref V03 tmp1 N001 ( 3, 2) [000008] ------------ t8 = LCL_VAR ref V03 tmp1 N002 ( 1, 1) [000009] ------------ t9 = CNS_INT long 8 /--* t8 ref +--* t9 long N003 ( 4, 3) [000010] -------N---- t10 = * ADD byref N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD long V01 arg1 [+0] Fseq[JobGroup] /--* t10 byref +--* t3 long [000073] -A-XG------- * STOREIND long N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class /--* t18 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t19 ref N005 ( 20, 19) [000021] DA---------- * STORE_LCL_VAR ref V04 tmp2 N001 ( 3, 2) [000022] ------------ t22 = LCL_VAR ref V04 tmp2 N002 ( 1, 1) [000023] ------------ t23 = CNS_INT long 8 /--* t22 ref +--* t23 long N003 ( 4, 3) [000024] -------N---- t24 = * ADD byref N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD int V01 arg1 [+8] Fseq[Version] /--* t24 byref +--* t17 int [000074] -A-XG------- * STOREIND int N005 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V03 tmp1 N007 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V04 tmp2 N009 ( 2, 10) [000050] ------------ t50 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] /--* t50 long N010 ( 4, 12) [000051] n---G------- t51 = * IND ref /--* t13 ref arg1 in rsi +--* t27 ref arg2 in rdx +--* t51 ref arg0 in rdi N011 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format /--* t29 ref arg0 in rdi N012 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log [000075] ------------ IL_OFFSET void IL offset: 0x25 N003 ( 3, 2) [000032] ------------ t32 = LCL_VAR byref V00 this N004 ( 1, 1) [000058] ------------ t58 = CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] /--* t32 byref +--* t58 long N005 ( 4, 3) [000059] -------N---- t59 = * ADD byref /--* t59 byref N006 ( 6, 5) [000033] *--XG------- t33 = * IND int N007 ( 2, 10) [000057] ------------ t57 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] /--* t57 long N008 ( 4, 12) [000031] n---G------- t31 = * IND ref /--* t33 int arg1 in rsi +--* t31 ref this in rdi N009 ( 24, 25) [000034] --CXG------- t34 = * CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item /--* t34 ref N011 ( 28, 28) [000065] DA-XG-----L- * STORE_LCL_VAR ref V06 tmp4 N013 ( 3, 2) [000035] ------------ t35 = LCL_VAR byref V00 this N014 ( 1, 1) [000062] ------------ t62 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] /--* t35 byref +--* t62 long N015 ( 5, 4) [000063] ------------ t63 = * ADD byref /--* t63 byref N016 ( 11, 8) [000042] ---XG------- t42 = * OBJ struct N018 ( 3, 2) [000066] ------------ t66 = LCL_VAR ref V06 tmp4 N019 ( 3, 4) [000070] ------------ t70 = LCL_FLD long V01 arg1 [+0] N020 ( 3, 4) [000071] ------------ t71 = LCL_FLD long V01 arg1 [+8] /--* t70 long +--* t71 long N021 ( 6, 8) [000069] -c---------- t69 = * FIELD_LIST struct N022 ( 2, 10) [000056] ------------ t56 = CNS_INT(h) long 0x7f6678060338 ftn REG r11 /--* t42 struct arg2 out+00 +--* t66 ref this in rdi +--* t69 struct arg3 rsi,rdx +--* t56 long arg1 in r11 N023 ( 73, 67) [000038] --CXG------- t38 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA /--* t38 struct N025 ( 77, 70) [000045] DA-XG------- * STORE_LCL_VAR struct V05 tmp3 N001 ( 3, 2) [000046] -------N---- t46 = LCL_VAR struct V05 tmp3 /--* t46 struct N002 ( 4, 3) [000047] ------------ * RETURN struct ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Do 'simple' lowering outgoingArgSpaceSize 0 sufficient for call [000005], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000019], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000029], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000030], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000034], which needs 0 Bumping outgoingArgSpaceSize to 56 for call [000038] *************** Finishing PHASE Do 'simple' lowering *************** In fgDebugCheckBBlist Trees before Lowering nodeinfo ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) (return), preds={} succs={} [000072] ------------ IL_OFFSET void IL offset: 0x0 N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class /--* t4 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t5 ref N005 ( 20, 19) [000007] DA---------- * STORE_LCL_VAR ref V03 tmp1 N001 ( 3, 2) [000008] ------------ t8 = LCL_VAR ref V03 tmp1 N002 ( 1, 1) [000009] ------------ t9 = CNS_INT long 8 /--* t8 ref +--* t9 long N003 ( 4, 3) [000010] -------N---- t10 = * ADD byref N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD long V01 arg1 [+0] Fseq[JobGroup] /--* t10 byref +--* t3 long [000073] -A-XG------- * STOREIND long N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class /--* t18 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t19 ref N005 ( 20, 19) [000021] DA---------- * STORE_LCL_VAR ref V04 tmp2 N001 ( 3, 2) [000022] ------------ t22 = LCL_VAR ref V04 tmp2 N002 ( 1, 1) [000023] ------------ t23 = CNS_INT long 8 /--* t22 ref +--* t23 long N003 ( 4, 3) [000024] -------N---- t24 = * ADD byref N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD int V01 arg1 [+8] Fseq[Version] /--* t24 byref +--* t17 int [000074] -A-XG------- * STOREIND int N005 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V03 tmp1 N007 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V04 tmp2 N009 ( 2, 10) [000050] ------------ t50 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] /--* t50 long N010 ( 4, 12) [000051] n---G------- t51 = * IND ref /--* t13 ref arg1 in rsi +--* t27 ref arg2 in rdx +--* t51 ref arg0 in rdi N011 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format /--* t29 ref arg0 in rdi N012 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log [000075] ------------ IL_OFFSET void IL offset: 0x25 N003 ( 3, 2) [000032] ------------ t32 = LCL_VAR byref V00 this N004 ( 1, 1) [000058] ------------ t58 = CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] /--* t32 byref +--* t58 long N005 ( 4, 3) [000059] -------N---- t59 = * ADD byref /--* t59 byref N006 ( 6, 5) [000033] *--XG------- t33 = * IND int N007 ( 2, 10) [000057] ------------ t57 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] /--* t57 long N008 ( 4, 12) [000031] n---G------- t31 = * IND ref /--* t33 int arg1 in rsi +--* t31 ref this in rdi N009 ( 24, 25) [000034] --CXG------- t34 = * CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item /--* t34 ref N011 ( 28, 28) [000065] DA-XG-----L- * STORE_LCL_VAR ref V06 tmp4 N013 ( 3, 2) [000035] ------------ t35 = LCL_VAR byref V00 this N014 ( 1, 1) [000062] ------------ t62 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] /--* t35 byref +--* t62 long N015 ( 5, 4) [000063] ------------ t63 = * ADD byref /--* t63 byref N016 ( 11, 8) [000042] ---XG------- t42 = * OBJ struct N018 ( 3, 2) [000066] ------------ t66 = LCL_VAR ref V06 tmp4 N019 ( 3, 4) [000070] ------------ t70 = LCL_FLD long V01 arg1 [+0] N020 ( 3, 4) [000071] ------------ t71 = LCL_FLD long V01 arg1 [+8] /--* t70 long +--* t71 long N021 ( 6, 8) [000069] -c---------- t69 = * FIELD_LIST struct N022 ( 2, 10) [000056] ------------ t56 = CNS_INT(h) long 0x7f6678060338 ftn REG r11 /--* t42 struct arg2 out+00 +--* t66 ref this in rdi +--* t69 struct arg3 rsi,rdx +--* t56 long arg1 in r11 N023 ( 73, 67) [000038] --CXG------- t38 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA /--* t38 struct N025 ( 77, 70) [000045] DA-XG------- * STORE_LCL_VAR struct V05 tmp3 N001 ( 3, 2) [000046] -------N---- t46 = LCL_VAR struct V05 tmp3 /--* t46 struct N002 ( 4, 3) [000047] ------------ * RETURN struct ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Lowering nodeinfo lowering call (before): N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class /--* t4 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000048] ----------L- * ARGPLACE long late: ====== lowering arg : N002 ( 2, 10) [000004] ------------ * CNS_INT(h) long 0x7f6678c127f0 class new node is : [000076] ------------ * PUTARG_REG long REG rdi lowering call (after): N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class /--* t4 long [000076] ------------ t76 = * PUTARG_REG long REG rdi /--* t76 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST lowering store lcl var/field (before): N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class /--* t4 long [000076] ------------ t76 = * PUTARG_REG long REG rdi /--* t76 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t5 ref N005 ( 20, 19) [000007] DA---------- * STORE_LCL_VAR ref V03 tmp1 lowering store lcl var/field (after): N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class /--* t4 long [000076] ------------ t76 = * PUTARG_REG long REG rdi /--* t76 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t5 ref N005 ( 20, 19) [000007] DA---------- * STORE_LCL_VAR ref V03 tmp1 Addressing mode: Base N001 ( 3, 2) [000008] ------------ * LCL_VAR ref V03 tmp1 + 8 Removing unused node: N002 ( 1, 1) [000009] -c---------- * CNS_INT long 8 New addressing mode node: N003 ( 4, 3) [000010] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N001 ( 3, 2) [000008] ------------ t8 = LCL_VAR ref V03 tmp1 /--* t8 ref N003 ( 4, 3) [000010] ------------ t10 = * LEA(b+8) byref N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD long V01 arg1 [+0] Fseq[JobGroup] /--* t10 byref +--* t3 long [000073] -A-XG------- * STOREIND long lowering call (before): N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class /--* t18 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000049] ----------L- * ARGPLACE long late: ====== lowering arg : N002 ( 2, 10) [000018] ------------ * CNS_INT(h) long 0x7f6678beb1c0 class new node is : [000077] ------------ * PUTARG_REG long REG rdi lowering call (after): N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class /--* t18 long [000077] ------------ t77 = * PUTARG_REG long REG rdi /--* t77 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST lowering store lcl var/field (before): N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class /--* t18 long [000077] ------------ t77 = * PUTARG_REG long REG rdi /--* t77 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t19 ref N005 ( 20, 19) [000021] DA---------- * STORE_LCL_VAR ref V04 tmp2 lowering store lcl var/field (after): N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class /--* t18 long [000077] ------------ t77 = * PUTARG_REG long REG rdi /--* t77 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t19 ref N005 ( 20, 19) [000021] DA---------- * STORE_LCL_VAR ref V04 tmp2 Addressing mode: Base N001 ( 3, 2) [000022] ------------ * LCL_VAR ref V04 tmp2 + 8 Removing unused node: N002 ( 1, 1) [000023] -c---------- * CNS_INT long 8 New addressing mode node: N003 ( 4, 3) [000024] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N001 ( 3, 2) [000022] ------------ t22 = LCL_VAR ref V04 tmp2 /--* t22 ref N003 ( 4, 3) [000024] ------------ t24 = * LEA(b+8) byref N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD int V01 arg1 [+8] Fseq[Version] /--* t24 byref +--* t17 int [000074] -A-XG------- * STOREIND int lowering call (before): N005 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V03 tmp1 N007 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V04 tmp2 N009 ( 2, 10) [000050] ------------ t50 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] /--* t50 long N010 ( 4, 12) [000051] n---G------- t51 = * IND ref /--* t13 ref arg1 in rsi +--* t27 ref arg2 in rdx +--* t51 ref arg0 in rdi N011 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format objp: ====== args: ====== lowering arg : N002 ( 0, 0) [000054] ----------L- * ARGPLACE ref lowering arg : N003 ( 0, 0) [000052] ----------L- * ARGPLACE ref lowering arg : N004 ( 0, 0) [000053] ----------L- * ARGPLACE ref late: ====== lowering arg : N005 ( 3, 2) [000013] ------------ * LCL_VAR ref V03 tmp1 new node is : [000078] ------------ * PUTARG_REG ref REG rsi lowering arg : N007 ( 3, 2) [000027] ------------ * LCL_VAR ref V04 tmp2 new node is : [000079] ------------ * PUTARG_REG ref REG rdx lowering arg : N010 ( 4, 12) [000051] n---G------- * IND ref new node is : [000080] ----G------- * PUTARG_REG ref REG rdi lowering call (after): N005 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V03 tmp1 /--* t13 ref [000078] ------------ t78 = * PUTARG_REG ref REG rsi N007 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V04 tmp2 /--* t27 ref [000079] ------------ t79 = * PUTARG_REG ref REG rdx N009 ( 2, 10) [000050] ------------ t50 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] /--* t50 long N010 ( 4, 12) [000051] n---G------- t51 = * IND ref /--* t51 ref [000080] ----G------- t80 = * PUTARG_REG ref REG rdi /--* t78 ref arg1 in rsi +--* t79 ref arg2 in rdx +--* t80 ref arg0 in rdi N011 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format lowering call (before): N005 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V03 tmp1 /--* t13 ref [000078] ------------ t78 = * PUTARG_REG ref REG rsi N007 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V04 tmp2 /--* t27 ref [000079] ------------ t79 = * PUTARG_REG ref REG rdx N009 ( 2, 10) [000050] ------------ t50 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] /--* t50 long N010 ( 4, 12) [000051] n---G------- t51 = * IND ref /--* t51 ref [000080] ----G------- t80 = * PUTARG_REG ref REG rdi /--* t78 ref arg1 in rsi +--* t79 ref arg2 in rdx +--* t80 ref arg0 in rdi N011 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format /--* t29 ref arg0 in rdi N012 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000055] ----------L- * ARGPLACE ref late: ====== lowering arg : N011 ( 36, 32) [000029] --CXG------- * CALL ref System.String.Format new node is : [000081] --CXG------- * PUTARG_REG ref REG rdi lowering call (after): N005 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V03 tmp1 /--* t13 ref [000078] ------------ t78 = * PUTARG_REG ref REG rsi N007 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V04 tmp2 /--* t27 ref [000079] ------------ t79 = * PUTARG_REG ref REG rdx N009 ( 2, 10) [000050] ------------ t50 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] /--* t50 long N010 ( 4, 12) [000051] n---G------- t51 = * IND ref /--* t51 ref [000080] ----G------- t80 = * PUTARG_REG ref REG rdi /--* t78 ref arg1 in rsi +--* t79 ref arg2 in rdx +--* t80 ref arg0 in rdi N011 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format /--* t29 ref [000081] --CXG------- t81 = * PUTARG_REG ref REG rdi /--* t81 ref arg0 in rdi N012 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log Addressing mode: Base N003 ( 3, 2) [000032] ------------ * LCL_VAR byref V00 this + 16 Removing unused node: N004 ( 1, 1) [000058] -c---------- * CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] New addressing mode node: N005 ( 4, 3) [000059] ------------ * LEA(b+16) byref lowering call (before): N003 ( 3, 2) [000032] ------------ t32 = LCL_VAR byref V00 this /--* t32 byref N005 ( 4, 3) [000059] -c---------- t59 = * LEA(b+16) byref /--* t59 byref N006 ( 6, 5) [000033] *--XG------- t33 = * IND int N007 ( 2, 10) [000057] ------------ t57 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] /--* t57 long N008 ( 4, 12) [000031] n---G------- t31 = * IND ref /--* t33 int arg1 in rsi +--* t31 ref this in rdi N009 ( 24, 25) [000034] --CXG------- t34 = * CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item objp: ====== lowering arg : N001 ( 0, 0) [000061] ----------L- * ARGPLACE ref args: ====== lowering arg : N002 ( 0, 0) [000060] ----------L- * ARGPLACE int late: ====== lowering arg : N006 ( 6, 5) [000033] *--XG------- * IND int new node is : [000082] ---XG------- * PUTARG_REG int REG rsi lowering arg : N008 ( 4, 12) [000031] n---G------- * IND ref new node is : [000083] ----G------- * PUTARG_REG ref REG rdi results of lowering call: N001 ( 2, 10) [000084] ------------ t84 = CNS_INT(h) long 0x7f6678eeddf8 ftn /--* t84 long N002 ( 4, 12) [000085] ------------ t85 = * IND long lowering call (after): N003 ( 3, 2) [000032] ------------ t32 = LCL_VAR byref V00 this /--* t32 byref N005 ( 4, 3) [000059] -c---------- t59 = * LEA(b+16) byref /--* t59 byref N006 ( 6, 5) [000033] *--XG------- t33 = * IND int /--* t33 int [000082] ---XG------- t82 = * PUTARG_REG int REG rsi N007 ( 2, 10) [000057] ------------ t57 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] /--* t57 long N008 ( 4, 12) [000031] n---G------- t31 = * IND ref /--* t31 ref [000083] ----G------- t83 = * PUTARG_REG ref REG rdi N001 ( 2, 10) [000084] ------------ t84 = CNS_INT(h) long 0x7f6678eeddf8 ftn /--* t84 long N002 ( 4, 12) [000085] -c---------- t85 = * IND long REG NA /--* t82 int arg1 in rsi +--* t83 ref this in rdi +--* t85 long control expr N009 ( 24, 25) [000034] --CXG------- t34 = * CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item lowering store lcl var/field (before): N003 ( 3, 2) [000032] ------------ t32 = LCL_VAR byref V00 this /--* t32 byref N005 ( 4, 3) [000059] -c---------- t59 = * LEA(b+16) byref /--* t59 byref N006 ( 6, 5) [000033] *--XG------- t33 = * IND int /--* t33 int [000082] ---XG------- t82 = * PUTARG_REG int REG rsi N007 ( 2, 10) [000057] ------------ t57 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] /--* t57 long N008 ( 4, 12) [000031] n---G------- t31 = * IND ref /--* t31 ref [000083] ----G------- t83 = * PUTARG_REG ref REG rdi N001 ( 2, 10) [000084] ------------ t84 = CNS_INT(h) long 0x7f6678eeddf8 ftn /--* t84 long N002 ( 4, 12) [000085] -c---------- t85 = * IND long REG NA /--* t82 int arg1 in rsi +--* t83 ref this in rdi +--* t85 long control expr N009 ( 24, 25) [000034] --CXG------- t34 = * CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item /--* t34 ref N011 ( 28, 28) [000065] DA-XG-----L- * STORE_LCL_VAR ref V06 tmp4 lowering store lcl var/field (after): N003 ( 3, 2) [000032] ------------ t32 = LCL_VAR byref V00 this /--* t32 byref N005 ( 4, 3) [000059] -c---------- t59 = * LEA(b+16) byref /--* t59 byref N006 ( 6, 5) [000033] *--XG------- t33 = * IND int /--* t33 int [000082] ---XG------- t82 = * PUTARG_REG int REG rsi N007 ( 2, 10) [000057] ------------ t57 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] /--* t57 long N008 ( 4, 12) [000031] n---G------- t31 = * IND ref /--* t31 ref [000083] ----G------- t83 = * PUTARG_REG ref REG rdi N001 ( 2, 10) [000084] ------------ t84 = CNS_INT(h) long 0x7f6678eeddf8 ftn /--* t84 long N002 ( 4, 12) [000085] -c---------- t85 = * IND long REG NA /--* t82 int arg1 in rsi +--* t83 ref this in rdi +--* t85 long control expr N009 ( 24, 25) [000034] --CXG------- t34 = * CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item /--* t34 ref N011 ( 28, 28) [000065] DA-XG-----L- * STORE_LCL_VAR ref V06 tmp4 lowering call (before): N003 ( 3, 2) [000032] ------------ t32 = LCL_VAR byref V00 this /--* t32 byref N005 ( 4, 3) [000059] -c---------- t59 = * LEA(b+16) byref /--* t59 byref N006 ( 6, 5) [000033] *--XG------- t33 = * IND int /--* t33 int [000082] ---XG------- t82 = * PUTARG_REG int REG rsi N007 ( 2, 10) [000057] ------------ t57 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] /--* t57 long N008 ( 4, 12) [000031] n---G------- t31 = * IND ref /--* t31 ref [000083] ----G------- t83 = * PUTARG_REG ref REG rdi N001 ( 2, 10) [000084] ------------ t84 = CNS_INT(h) long 0x7f6678eeddf8 ftn /--* t84 long N002 ( 4, 12) [000085] -c---------- t85 = * IND long REG NA /--* t82 int arg1 in rsi +--* t83 ref this in rdi +--* t85 long control expr N009 ( 24, 25) [000034] --CXG------- t34 = * CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item /--* t34 ref N011 ( 28, 28) [000065] DA-XG-----L- * STORE_LCL_VAR ref V06 tmp4 N013 ( 3, 2) [000035] ------------ t35 = LCL_VAR byref V00 this N014 ( 1, 1) [000062] -c---------- t62 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] /--* t35 byref +--* t62 long N015 ( 5, 4) [000063] ------------ t63 = * ADD byref /--* t63 byref N016 ( 11, 8) [000042] ---XG------- t42 = * OBJ struct N018 ( 3, 2) [000066] ------------ t66 = LCL_VAR ref V06 tmp4 N019 ( 3, 4) [000070] ------------ t70 = LCL_FLD long V01 arg1 [+0] N020 ( 3, 4) [000071] ------------ t71 = LCL_FLD long V01 arg1 [+8] /--* t70 long +--* t71 long N021 ( 6, 8) [000069] -c---------- t69 = * FIELD_LIST struct N022 ( 2, 10) [000056] ------------ t56 = CNS_INT(h) long 0x7f6678060338 ftn REG r11 /--* t42 struct arg2 out+00 +--* t66 ref this in rdi +--* t69 struct arg3 rsi,rdx +--* t56 long arg1 in r11 N023 ( 73, 67) [000038] --CXG------- t38 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA objp: ====== lowering arg : N011 ( 28, 28) [000065] DA-XG-----L- * STORE_LCL_VAR ref V06 tmp4 args: ====== lowering arg : N012 ( 0, 0) [000068] ----------L- * ARGPLACE long lowering arg : N016 ( 11, 8) [000042] ---XG------- * OBJ struct new node is : [000086] ---XG------- * PUTARG_STK [+0x00] void (7 slots) lowering arg : N017 ( 0, 0) [000067] ----------L- * ARGPLACE struct => [clsHnd=795C7A00] late: ====== lowering arg : N018 ( 3, 2) [000066] ------------ * LCL_VAR ref V06 tmp4 new node is : [000087] ------------ * PUTARG_REG ref REG rdi lowering arg : N021 ( 6, 8) [000069] -c---------- * FIELD_LIST struct lowering arg : N022 ( 2, 10) [000056] ------------ * CNS_INT(h) long 0x7f6678060338 ftn REG r11 new node is : [000090] ------------ * PUTARG_REG long REG r11 results of lowering call: N001 ( 2, 10) [000091] ------------ t91 = CNS_INT(h) long 0x7f6678060338 ftn /--* t91 long N002 ( 4, 12) [000092] ------------ t92 = * IND long lowering call (after): N003 ( 3, 2) [000032] ------------ t32 = LCL_VAR byref V00 this /--* t32 byref N005 ( 4, 3) [000059] -c---------- t59 = * LEA(b+16) byref /--* t59 byref N006 ( 6, 5) [000033] *--XG------- t33 = * IND int /--* t33 int [000082] ---XG------- t82 = * PUTARG_REG int REG rsi N007 ( 2, 10) [000057] ------------ t57 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] /--* t57 long N008 ( 4, 12) [000031] n---G------- t31 = * IND ref /--* t31 ref [000083] ----G------- t83 = * PUTARG_REG ref REG rdi N001 ( 2, 10) [000084] ------------ t84 = CNS_INT(h) long 0x7f6678eeddf8 ftn /--* t84 long N002 ( 4, 12) [000085] -c---------- t85 = * IND long REG NA /--* t82 int arg1 in rsi +--* t83 ref this in rdi +--* t85 long control expr N009 ( 24, 25) [000034] --CXG------- t34 = * CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item /--* t34 ref N011 ( 28, 28) [000065] DA-XG-----L- * STORE_LCL_VAR ref V06 tmp4 N013 ( 3, 2) [000035] ------------ t35 = LCL_VAR byref V00 this N014 ( 1, 1) [000062] -c---------- t62 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] /--* t35 byref +--* t62 long N015 ( 5, 4) [000063] ------------ t63 = * ADD byref /--* t63 byref N016 ( 11, 8) [000042] -c-XG------- t42 = * OBJ struct /--* t42 struct [000086] ---XG------- * PUTARG_STK [+0x00] void (7 slots) (RepInstr) N018 ( 3, 2) [000066] ------------ t66 = LCL_VAR ref V06 tmp4 /--* t66 ref [000087] ------------ t87 = * PUTARG_REG ref REG rdi N019 ( 3, 4) [000070] ------------ t70 = LCL_FLD long V01 arg1 [+0] /--* t70 long [000088] ------------ t88 = * PUTARG_REG long REG rsi N020 ( 3, 4) [000071] ------------ t71 = LCL_FLD long V01 arg1 [+8] /--* t71 long [000089] ------------ t89 = * PUTARG_REG long REG rdx /--* t88 long +--* t89 long N021 ( 6, 8) [000069] -c---------- t69 = * FIELD_LIST struct N022 ( 2, 10) [000056] ------------ t56 = CNS_INT(h) long 0x7f6678060338 ftn REG r11 /--* t56 long [000090] ------------ t90 = * PUTARG_REG long REG r11 N001 ( 2, 10) [000091] ------------ t91 = CNS_INT(h) long 0x7f6678060338 ftn /--* t91 long N002 ( 4, 12) [000092] -c---------- t92 = * IND long REG NA /--* t87 ref this in rdi +--* t69 struct arg3 rsi,rdx +--* t90 long arg1 in r11 +--* t92 long control expr N023 ( 73, 67) [000038] --CXG------- t38 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA lowering store lcl var/field (before): N003 ( 3, 2) [000032] ------------ t32 = LCL_VAR byref V00 this /--* t32 byref N005 ( 4, 3) [000059] -c---------- t59 = * LEA(b+16) byref /--* t59 byref N006 ( 6, 5) [000033] *--XG------- t33 = * IND int /--* t33 int [000082] ---XG------- t82 = * PUTARG_REG int REG rsi N007 ( 2, 10) [000057] ------------ t57 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] /--* t57 long N008 ( 4, 12) [000031] n---G------- t31 = * IND ref /--* t31 ref [000083] ----G------- t83 = * PUTARG_REG ref REG rdi N001 ( 2, 10) [000084] ------------ t84 = CNS_INT(h) long 0x7f6678eeddf8 ftn /--* t84 long N002 ( 4, 12) [000085] -c---------- t85 = * IND long REG NA /--* t82 int arg1 in rsi +--* t83 ref this in rdi +--* t85 long control expr N009 ( 24, 25) [000034] --CXG------- t34 = * CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item /--* t34 ref N011 ( 28, 28) [000065] DA-XG-----L- * STORE_LCL_VAR ref V06 tmp4 N013 ( 3, 2) [000035] ------------ t35 = LCL_VAR byref V00 this N014 ( 1, 1) [000062] -c---------- t62 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] /--* t35 byref +--* t62 long N015 ( 5, 4) [000063] ------------ t63 = * ADD byref /--* t63 byref N016 ( 11, 8) [000042] -c-XG------- t42 = * OBJ struct /--* t42 struct [000086] ---XG------- * PUTARG_STK [+0x00] void (7 slots) (RepInstr) N018 ( 3, 2) [000066] ------------ t66 = LCL_VAR ref V06 tmp4 /--* t66 ref [000087] ------------ t87 = * PUTARG_REG ref REG rdi N019 ( 3, 4) [000070] ------------ t70 = LCL_FLD long V01 arg1 [+0] /--* t70 long [000088] ------------ t88 = * PUTARG_REG long REG rsi N020 ( 3, 4) [000071] ------------ t71 = LCL_FLD long V01 arg1 [+8] /--* t71 long [000089] ------------ t89 = * PUTARG_REG long REG rdx /--* t88 long +--* t89 long N021 ( 6, 8) [000069] -c---------- t69 = * FIELD_LIST struct N022 ( 2, 10) [000056] ------------ t56 = CNS_INT(h) long 0x7f6678060338 ftn REG r11 /--* t56 long [000090] ------------ t90 = * PUTARG_REG long REG r11 N001 ( 2, 10) [000091] ------------ t91 = CNS_INT(h) long 0x7f6678060338 ftn /--* t91 long N002 ( 4, 12) [000092] -c---------- t92 = * IND long REG NA /--* t87 ref this in rdi +--* t69 struct arg3 rsi,rdx +--* t90 long arg1 in r11 +--* t92 long control expr N023 ( 73, 67) [000038] --CXG------- t38 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA /--* t38 struct N025 ( 77, 70) [000045] DA-XG------- * STORE_LCL_VAR struct V05 tmp3 lowering store lcl var/field (after): N003 ( 3, 2) [000032] ------------ t32 = LCL_VAR byref V00 this /--* t32 byref N005 ( 4, 3) [000059] -c---------- t59 = * LEA(b+16) byref /--* t59 byref N006 ( 6, 5) [000033] *--XG------- t33 = * IND int /--* t33 int [000082] ---XG------- t82 = * PUTARG_REG int REG rsi N007 ( 2, 10) [000057] ------------ t57 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] /--* t57 long N008 ( 4, 12) [000031] n---G------- t31 = * IND ref /--* t31 ref [000083] ----G------- t83 = * PUTARG_REG ref REG rdi N001 ( 2, 10) [000084] ------------ t84 = CNS_INT(h) long 0x7f6678eeddf8 ftn /--* t84 long N002 ( 4, 12) [000085] -c---------- t85 = * IND long REG NA /--* t82 int arg1 in rsi +--* t83 ref this in rdi +--* t85 long control expr N009 ( 24, 25) [000034] --CXG------- t34 = * CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item /--* t34 ref N011 ( 28, 28) [000065] DA-XG-----L- * STORE_LCL_VAR ref V06 tmp4 N013 ( 3, 2) [000035] ------------ t35 = LCL_VAR byref V00 this N014 ( 1, 1) [000062] -c---------- t62 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] /--* t35 byref +--* t62 long N015 ( 5, 4) [000063] ------------ t63 = * ADD byref /--* t63 byref N016 ( 11, 8) [000042] -c-XG------- t42 = * OBJ struct /--* t42 struct [000086] ---XG------- * PUTARG_STK [+0x00] void (7 slots) (RepInstr) N018 ( 3, 2) [000066] ------------ t66 = LCL_VAR ref V06 tmp4 /--* t66 ref [000087] ------------ t87 = * PUTARG_REG ref REG rdi N019 ( 3, 4) [000070] ------------ t70 = LCL_FLD long V01 arg1 [+0] /--* t70 long [000088] ------------ t88 = * PUTARG_REG long REG rsi N020 ( 3, 4) [000071] ------------ t71 = LCL_FLD long V01 arg1 [+8] /--* t71 long [000089] ------------ t89 = * PUTARG_REG long REG rdx /--* t88 long +--* t89 long N021 ( 6, 8) [000069] -c---------- t69 = * FIELD_LIST struct N022 ( 2, 10) [000056] ------------ t56 = CNS_INT(h) long 0x7f6678060338 ftn REG r11 /--* t56 long [000090] ------------ t90 = * PUTARG_REG long REG r11 N001 ( 2, 10) [000091] ------------ t91 = CNS_INT(h) long 0x7f6678060338 ftn /--* t91 long N002 ( 4, 12) [000092] -c---------- t92 = * IND long REG NA /--* t87 ref this in rdi +--* t69 struct arg3 rsi,rdx +--* t90 long arg1 in r11 +--* t92 long control expr N023 ( 73, 67) [000038] --CXG------- t38 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA /--* t38 struct N025 ( 77, 70) [000045] DA-XG------- * STORE_LCL_VAR struct V05 tmp3 lowering GT_RETURN N002 ( 4, 3) [000047] ------------ * RETURN struct ============**** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 Lower has completed modifying nodes. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) (return), preds={} succs={} [000072] ------------ IL_OFFSET void IL offset: 0x0 N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class /--* t4 long [000076] ------------ t76 = * PUTARG_REG long REG rdi /--* t76 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t5 ref N005 ( 20, 19) [000007] DA---------- * STORE_LCL_VAR ref V03 tmp1 N001 ( 3, 2) [000008] ------------ t8 = LCL_VAR ref V03 tmp1 /--* t8 ref N003 ( 4, 3) [000010] -c---------- t10 = * LEA(b+8) byref N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD long V01 arg1 [+0] Fseq[JobGroup] /--* t10 byref +--* t3 long [000073] -A-XG------- * STOREIND long N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class /--* t18 long [000077] ------------ t77 = * PUTARG_REG long REG rdi /--* t77 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t19 ref N005 ( 20, 19) [000021] DA---------- * STORE_LCL_VAR ref V04 tmp2 N001 ( 3, 2) [000022] ------------ t22 = LCL_VAR ref V04 tmp2 /--* t22 ref N003 ( 4, 3) [000024] -c---------- t24 = * LEA(b+8) byref N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD int V01 arg1 [+8] Fseq[Version] /--* t24 byref +--* t17 int [000074] -A-XG------- * STOREIND int N005 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V03 tmp1 /--* t13 ref [000078] ------------ t78 = * PUTARG_REG ref REG rsi N007 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V04 tmp2 /--* t27 ref [000079] ------------ t79 = * PUTARG_REG ref REG rdx N009 ( 2, 10) [000050] ------------ t50 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] /--* t50 long N010 ( 4, 12) [000051] n---G------- t51 = * IND ref /--* t51 ref [000080] ----G------- t80 = * PUTARG_REG ref REG rdi /--* t78 ref arg1 in rsi +--* t79 ref arg2 in rdx +--* t80 ref arg0 in rdi N011 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format /--* t29 ref [000081] --CXG------- t81 = * PUTARG_REG ref REG rdi /--* t81 ref arg0 in rdi N012 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log [000075] ------------ IL_OFFSET void IL offset: 0x25 N003 ( 3, 2) [000032] ------------ t32 = LCL_VAR byref V00 this /--* t32 byref N005 ( 4, 3) [000059] -c---------- t59 = * LEA(b+16) byref /--* t59 byref N006 ( 6, 5) [000033] *--XG------- t33 = * IND int /--* t33 int [000082] ---XG------- t82 = * PUTARG_REG int REG rsi N007 ( 2, 10) [000057] ------------ t57 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] /--* t57 long N008 ( 4, 12) [000031] n---G------- t31 = * IND ref /--* t31 ref [000083] ----G------- t83 = * PUTARG_REG ref REG rdi N001 ( 2, 10) [000084] ------------ t84 = CNS_INT(h) long 0x7f6678eeddf8 ftn /--* t84 long N002 ( 4, 12) [000085] -c---------- t85 = * IND long REG NA /--* t82 int arg1 in rsi +--* t83 ref this in rdi +--* t85 long control expr N009 ( 24, 25) [000034] --CXG------- t34 = * CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item /--* t34 ref N011 ( 28, 28) [000065] DA-XG-----L- * STORE_LCL_VAR ref V06 tmp4 N013 ( 3, 2) [000035] ------------ t35 = LCL_VAR byref V00 this N014 ( 1, 1) [000062] -c---------- t62 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] /--* t35 byref +--* t62 long N015 ( 5, 4) [000063] ------------ t63 = * ADD byref /--* t63 byref N016 ( 11, 8) [000042] -c-XG------- t42 = * OBJ struct /--* t42 struct [000086] ---XG------- * PUTARG_STK [+0x00] void (7 slots) (RepInstr) N018 ( 3, 2) [000066] ------------ t66 = LCL_VAR ref V06 tmp4 /--* t66 ref [000087] ------------ t87 = * PUTARG_REG ref REG rdi N019 ( 3, 4) [000070] ------------ t70 = LCL_FLD long V01 arg1 [+0] /--* t70 long [000088] ------------ t88 = * PUTARG_REG long REG rsi N020 ( 3, 4) [000071] ------------ t71 = LCL_FLD long V01 arg1 [+8] /--* t71 long [000089] ------------ t89 = * PUTARG_REG long REG rdx /--* t88 long +--* t89 long N021 ( 6, 8) [000069] -c---------- t69 = * FIELD_LIST struct N022 ( 2, 10) [000056] ------------ t56 = CNS_INT(h) long 0x7f6678060338 ftn REG r11 /--* t56 long [000090] ------------ t90 = * PUTARG_REG long REG r11 N001 ( 2, 10) [000091] ------------ t91 = CNS_INT(h) long 0x7f6678060338 ftn /--* t91 long N002 ( 4, 12) [000092] -c---------- t92 = * IND long REG NA /--* t87 ref this in rdi +--* t69 struct arg3 rsi,rdx +--* t90 long arg1 in r11 +--* t92 long control expr N023 ( 73, 67) [000038] --CXG------- t38 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA /--* t38 struct N025 ( 77, 70) [000045] DA-XG------- * STORE_LCL_VAR struct V05 tmp3 N001 ( 3, 2) [000046] -c-----N---- t46 = LCL_VAR struct V05 tmp3 /--* t46 struct N002 ( 4, 3) [000047] ------------ * RETURN struct ------------------------------------------------------------------------------------------------------------------- *** lvaComputeRefCounts *** *************** In fgLocalVarLiveness() ; Initial local variable assignments ; ; V00 this byref this ; V01 arg1 struct do-not-enreg[SFA] multireg-arg ; V02 OutArgs lclBlk <56> "OutgoingArgSpace" ; V03 tmp1 ref "Reusable Box Helper" ; V04 tmp2 ref "Reusable Box Helper" ; V05 tmp3 struct multireg-ret "Return value temp for multireg return" ; V06 tmp4 ref "argument with side effect" In fgLocalVarLivenessInit *************** In fgPerBlockLocalVarLiveness() *************** In fgInterBlockLocalVarLiveness() *** lvaComputeRefCounts *** *************** Finishing PHASE Lowering nodeinfo Trees after Lowering nodeinfo ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) (return), preds={} succs={} [000072] ------------ IL_OFFSET void IL offset: 0x0 N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class /--* t4 long [000076] ------------ t76 = * PUTARG_REG long REG rdi /--* t76 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t5 ref N005 ( 20, 19) [000007] DA---------- * STORE_LCL_VAR ref V03 tmp1 N001 ( 3, 2) [000008] ------------ t8 = LCL_VAR ref V03 tmp1 /--* t8 ref N003 ( 4, 3) [000010] -c---------- t10 = * LEA(b+8) byref N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD long V01 arg1 [+0] Fseq[JobGroup] /--* t10 byref +--* t3 long [000073] -A-XG------- * STOREIND long N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class /--* t18 long [000077] ------------ t77 = * PUTARG_REG long REG rdi /--* t77 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t19 ref N005 ( 20, 19) [000021] DA---------- * STORE_LCL_VAR ref V04 tmp2 N001 ( 3, 2) [000022] ------------ t22 = LCL_VAR ref V04 tmp2 /--* t22 ref N003 ( 4, 3) [000024] -c---------- t24 = * LEA(b+8) byref N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD int V01 arg1 [+8] Fseq[Version] /--* t24 byref +--* t17 int [000074] -A-XG------- * STOREIND int N005 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V03 tmp1 /--* t13 ref [000078] ------------ t78 = * PUTARG_REG ref REG rsi N007 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V04 tmp2 /--* t27 ref [000079] ------------ t79 = * PUTARG_REG ref REG rdx N009 ( 2, 10) [000050] ------------ t50 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] /--* t50 long N010 ( 4, 12) [000051] n---G------- t51 = * IND ref /--* t51 ref [000080] ----G------- t80 = * PUTARG_REG ref REG rdi /--* t78 ref arg1 in rsi +--* t79 ref arg2 in rdx +--* t80 ref arg0 in rdi N011 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format /--* t29 ref [000081] --CXG------- t81 = * PUTARG_REG ref REG rdi /--* t81 ref arg0 in rdi N012 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log [000075] ------------ IL_OFFSET void IL offset: 0x25 N003 ( 3, 2) [000032] ------------ t32 = LCL_VAR byref V00 this /--* t32 byref N005 ( 4, 3) [000059] -c---------- t59 = * LEA(b+16) byref /--* t59 byref N006 ( 6, 5) [000033] *--XG------- t33 = * IND int /--* t33 int [000082] ---XG------- t82 = * PUTARG_REG int REG rsi N007 ( 2, 10) [000057] ------------ t57 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] /--* t57 long N008 ( 4, 12) [000031] n---G------- t31 = * IND ref /--* t31 ref [000083] ----G------- t83 = * PUTARG_REG ref REG rdi N001 ( 2, 10) [000084] ------------ t84 = CNS_INT(h) long 0x7f6678eeddf8 ftn /--* t84 long N002 ( 4, 12) [000085] -c---------- t85 = * IND long REG NA /--* t82 int arg1 in rsi +--* t83 ref this in rdi +--* t85 long control expr N009 ( 24, 25) [000034] --CXG------- t34 = * CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item /--* t34 ref N011 ( 28, 28) [000065] DA-XG-----L- * STORE_LCL_VAR ref V06 tmp4 N013 ( 3, 2) [000035] ------------ t35 = LCL_VAR byref V00 this N014 ( 1, 1) [000062] -c---------- t62 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] /--* t35 byref +--* t62 long N015 ( 5, 4) [000063] ------------ t63 = * ADD byref /--* t63 byref N016 ( 11, 8) [000042] -c-XG------- t42 = * OBJ struct /--* t42 struct [000086] ---XG------- * PUTARG_STK [+0x00] void (7 slots) (RepInstr) N018 ( 3, 2) [000066] ------------ t66 = LCL_VAR ref V06 tmp4 /--* t66 ref [000087] ------------ t87 = * PUTARG_REG ref REG rdi N019 ( 3, 4) [000070] ------------ t70 = LCL_FLD long V01 arg1 [+0] /--* t70 long [000088] ------------ t88 = * PUTARG_REG long REG rsi N020 ( 3, 4) [000071] ------------ t71 = LCL_FLD long V01 arg1 [+8] /--* t71 long [000089] ------------ t89 = * PUTARG_REG long REG rdx /--* t88 long +--* t89 long N021 ( 6, 8) [000069] -c---------- t69 = * FIELD_LIST struct N022 ( 2, 10) [000056] ------------ t56 = CNS_INT(h) long 0x7f6678060338 ftn REG r11 /--* t56 long [000090] ------------ t90 = * PUTARG_REG long REG r11 N001 ( 2, 10) [000091] ------------ t91 = CNS_INT(h) long 0x7f6678060338 ftn /--* t91 long N002 ( 4, 12) [000092] -c---------- t92 = * IND long REG NA /--* t87 ref this in rdi +--* t69 struct arg3 rsi,rdx +--* t90 long arg1 in r11 +--* t92 long control expr N023 ( 73, 67) [000038] --CXG------- t38 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA /--* t38 struct N025 ( 77, 70) [000045] DA-XG------- * STORE_LCL_VAR struct V05 tmp3 N001 ( 3, 2) [000046] -c-----N---- t46 = LCL_VAR struct V05 tmp3 /--* t46 struct N002 ( 4, 3) [000047] ------------ * RETURN struct ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Trees before Calculate stack level slots ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) (return), preds={} succs={} [000072] ------------ IL_OFFSET void IL offset: 0x0 N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class /--* t4 long [000076] ------------ t76 = * PUTARG_REG long REG rdi /--* t76 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t5 ref N005 ( 20, 19) [000007] DA---------- * STORE_LCL_VAR ref V03 tmp1 N001 ( 3, 2) [000008] ------------ t8 = LCL_VAR ref V03 tmp1 /--* t8 ref N003 ( 4, 3) [000010] -c---------- t10 = * LEA(b+8) byref N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD long V01 arg1 [+0] Fseq[JobGroup] /--* t10 byref +--* t3 long [000073] -A-XG------- * STOREIND long N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class /--* t18 long [000077] ------------ t77 = * PUTARG_REG long REG rdi /--* t77 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST /--* t19 ref N005 ( 20, 19) [000021] DA---------- * STORE_LCL_VAR ref V04 tmp2 N001 ( 3, 2) [000022] ------------ t22 = LCL_VAR ref V04 tmp2 /--* t22 ref N003 ( 4, 3) [000024] -c---------- t24 = * LEA(b+8) byref N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD int V01 arg1 [+8] Fseq[Version] /--* t24 byref +--* t17 int [000074] -A-XG------- * STOREIND int N005 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V03 tmp1 /--* t13 ref [000078] ------------ t78 = * PUTARG_REG ref REG rsi N007 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V04 tmp2 /--* t27 ref [000079] ------------ t79 = * PUTARG_REG ref REG rdx N009 ( 2, 10) [000050] ------------ t50 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] /--* t50 long N010 ( 4, 12) [000051] n---G------- t51 = * IND ref /--* t51 ref [000080] ----G------- t80 = * PUTARG_REG ref REG rdi /--* t78 ref arg1 in rsi +--* t79 ref arg2 in rdx +--* t80 ref arg0 in rdi N011 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format /--* t29 ref [000081] --CXG------- t81 = * PUTARG_REG ref REG rdi /--* t81 ref arg0 in rdi N012 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log [000075] ------------ IL_OFFSET void IL offset: 0x25 N003 ( 3, 2) [000032] ------------ t32 = LCL_VAR byref V00 this /--* t32 byref N005 ( 4, 3) [000059] -c---------- t59 = * LEA(b+16) byref /--* t59 byref N006 ( 6, 5) [000033] *--XG------- t33 = * IND int /--* t33 int [000082] ---XG------- t82 = * PUTARG_REG int REG rsi N007 ( 2, 10) [000057] ------------ t57 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] /--* t57 long N008 ( 4, 12) [000031] n---G------- t31 = * IND ref /--* t31 ref [000083] ----G------- t83 = * PUTARG_REG ref REG rdi N001 ( 2, 10) [000084] ------------ t84 = CNS_INT(h) long 0x7f6678eeddf8 ftn /--* t84 long N002 ( 4, 12) [000085] -c---------- t85 = * IND long REG NA /--* t82 int arg1 in rsi +--* t83 ref this in rdi +--* t85 long control expr N009 ( 24, 25) [000034] --CXG------- t34 = * CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item /--* t34 ref N011 ( 28, 28) [000065] DA-XG-----L- * STORE_LCL_VAR ref V06 tmp4 N013 ( 3, 2) [000035] ------------ t35 = LCL_VAR byref V00 this N014 ( 1, 1) [000062] -c---------- t62 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] /--* t35 byref +--* t62 long N015 ( 5, 4) [000063] ------------ t63 = * ADD byref /--* t63 byref N016 ( 11, 8) [000042] -c-XG------- t42 = * OBJ struct /--* t42 struct [000086] ---XG------- * PUTARG_STK [+0x00] void (7 slots) (RepInstr) N018 ( 3, 2) [000066] ------------ t66 = LCL_VAR ref V06 tmp4 /--* t66 ref [000087] ------------ t87 = * PUTARG_REG ref REG rdi N019 ( 3, 4) [000070] ------------ t70 = LCL_FLD long V01 arg1 [+0] /--* t70 long [000088] ------------ t88 = * PUTARG_REG long REG rsi N020 ( 3, 4) [000071] ------------ t71 = LCL_FLD long V01 arg1 [+8] /--* t71 long [000089] ------------ t89 = * PUTARG_REG long REG rdx /--* t88 long +--* t89 long N021 ( 6, 8) [000069] -c---------- t69 = * FIELD_LIST struct N022 ( 2, 10) [000056] ------------ t56 = CNS_INT(h) long 0x7f6678060338 ftn REG r11 /--* t56 long [000090] ------------ t90 = * PUTARG_REG long REG r11 N001 ( 2, 10) [000091] ------------ t91 = CNS_INT(h) long 0x7f6678060338 ftn /--* t91 long N002 ( 4, 12) [000092] -c---------- t92 = * IND long REG NA /--* t87 ref this in rdi +--* t69 struct arg3 rsi,rdx +--* t90 long arg1 in r11 +--* t92 long control expr N023 ( 73, 67) [000038] --CXG------- t38 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA /--* t38 struct N025 ( 77, 70) [000045] DA-XG------- * STORE_LCL_VAR struct V05 tmp3 N001 ( 3, 2) [000046] -c-----N---- t46 = LCL_VAR struct V05 tmp3 /--* t46 struct N002 ( 4, 3) [000047] ------------ * RETURN struct ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Calculate stack level slots Too many pushed arguments for an ESP based encoding, forcing an EBP frame *************** Finishing PHASE Calculate stack level slots [no changes] *************** Starting PHASE Linear scan register alloc Clearing modified regs. buildIntervals ======== ----------------- LIVENESS: ----------------- BB01 use def in out {} {} {} {} FP callee save candidate vars: None floatVarCount = 0; hasLoops = 0, singleExit = 1 TUPLE STYLE DUMP BEFORE LSRA LSRA Block Sequence: BB01( 1 ) BB01 [000..042) (return), preds={} succs={} ===== N000. IL_OFFSET IL offset: 0x0 N002. t4 = CNS_INT(h) 0x7f6678c127f0 class N000. t76 = PUTARG_REG; t4 N003. t5 = CALL help; t76 N005. V03 MEM; t5 N001. t8 = V03 MEM N003. t10 = LEA(b+8) ; t8 N005. t3 = V01 MEM N000. STOREIND ; t10,t3 N002. t18 = CNS_INT(h) 0x7f6678beb1c0 class N000. t77 = PUTARG_REG; t18 N003. t19 = CALL help; t77 N005. V04 MEM; t19 N001. t22 = V04 MEM N003. t24 = LEA(b+8) ; t22 N005. t17 = V01 MEM N000. STOREIND ; t24,t17 N005. t13 = V03 MEM N000. t78 = PUTARG_REG; t13 N007. t27 = V04 MEM N000. t79 = PUTARG_REG; t27 N009. t50 = CNS_INT(h) 0x64008A98 [ICON_STR_HDL] N010. t51 = IND ; t50 N000. t80 = PUTARG_REG; t51 N011. t29 = CALL ; t78,t79,t80 N000. t81 = PUTARG_REG; t29 N012. CALL ; t81 N000. IL_OFFSET IL offset: 0x25 N003. t32 = V00 MEM N005. t59 = LEA(b+16); t32 N006. t33 = IND ; t59 N000. t82 = PUTARG_REG; t33 N007. t57 = CNS_INT(h) 0x7f6664004668 static Fseq[s_NetworkInterfaces] N008. t31 = IND ; t57 N000. t83 = PUTARG_REG; t31 N001. t84 = CNS_INT(h) 0x7f6678eeddf8 ftn N002. t85 = IND ; t84 N009. t34 = CALL nullcheck; t82,t83,t85 N011. V06 MEM; t34 N013. t35 = V00 MEM N014. CNS_INT 56 field offset Fseq[m_ParallelSendQueue] N015. t63 = ADD ; t35 N016. t42 = OBJ ; t63 N000. PUTARG_STK [+0x00]; t42 N018. t66 = V06 MEM N000. t87 = PUTARG_REG; t66 N019. t70 = V01 MEM N000. t88 = PUTARG_REG; t70 N020. t71 = V01 MEM N000. t89 = PUTARG_REG; t71 N021. t69 = FIELD_LIST; t88,t89 N022. t56 = CNS_INT(h) 0x7f6678060338 ftn N000. t90 = PUTARG_REG; t56 N001. t91 = CNS_INT(h) 0x7f6678060338 ftn N002. t92 = IND ; t91 N023. t38 = CALLV stub; t87,t69,t90,t92 N025. V05 MEM; t38 N001. V05 MEM N002. RETURN buildIntervals second part ======== Int arg V00 in reg rdi NEW BLOCK BB01 DefList: { } N002 (???,???) [000072] ------------ * IL_OFFSET void IL offset: 0x0 REG NA DefList: { } N004 ( 2, 10) [000004] ------------ * CNS_INT(h) long 0x7f6678c127f0 class REG NA Interval 0: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N004.t4. CNS_INT } N006 (???,???) [000076] ------------ * PUTARG_REG long REG rdi BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> Interval 1: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> DefList: { N006.t76. PUTARG_REG } N008 ( 16, 16) [000005] --C--------- * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG NA BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> Interval 2: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> DefList: { N008.t5. CALL } N010 ( 20, 19) [000007] DA---------- * STORE_LCL_VAR ref V03 tmp1 NA REG NA BB01 regmask=[allInt] minReg=1 last> DefList: { } N012 ( 3, 2) [000008] ------------ * LCL_VAR ref V03 tmp1 NA REG NA Interval 3: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB01 regmask=[allInt] minReg=1> DefList: { N012.t8. LCL_VAR } N014 ( 4, 3) [000010] -c---------- * LEA(b+8) byref REG NA Contained DefList: { N012.t8. LCL_VAR } N016 ( 3, 4) [000003] ------------ * LCL_FLD long V01 arg1 [+0] Fseq[JobGroup] NA REG NA Interval 4: long RefPositions {} physReg:NA Preferences=[allInt] LCL_FLD BB01 regmask=[allInt] minReg=1> DefList: { N012.t8. LCL_VAR; N016.t3. LCL_FLD } N018 (???,???) [000073] -A-XG------- * STOREIND long REG NA BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> DefList: { } N020 ( 2, 10) [000018] ------------ * CNS_INT(h) long 0x7f6678beb1c0 class REG NA Interval 5: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N020.t18. CNS_INT } N022 (???,???) [000077] ------------ * PUTARG_REG long REG rdi BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> Interval 6: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> DefList: { N022.t77. PUTARG_REG } N024 ( 16, 16) [000019] --C--------- * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG NA BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> Interval 7: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> DefList: { N024.t19. CALL } N026 ( 20, 19) [000021] DA---------- * STORE_LCL_VAR ref V04 tmp2 NA REG NA BB01 regmask=[allInt] minReg=1 last> DefList: { } N028 ( 3, 2) [000022] ------------ * LCL_VAR ref V04 tmp2 NA REG NA Interval 8: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB01 regmask=[allInt] minReg=1> DefList: { N028.t22. LCL_VAR } N030 ( 4, 3) [000024] -c---------- * LEA(b+8) byref REG NA Contained DefList: { N028.t22. LCL_VAR } N032 ( 3, 4) [000017] ------------ * LCL_FLD int V01 arg1 [+8] Fseq[Version] NA REG NA Interval 9: int RefPositions {} physReg:NA Preferences=[allInt] LCL_FLD BB01 regmask=[allInt] minReg=1> DefList: { N028.t22. LCL_VAR; N032.t17. LCL_FLD } N034 (???,???) [000074] -A-XG------- * STOREIND int REG NA BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> DefList: { } N036 ( 3, 2) [000013] ------------ * LCL_VAR ref V03 tmp1 NA REG NA Interval 10: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB01 regmask=[allInt] minReg=1> DefList: { N036.t13. LCL_VAR } N038 (???,???) [000078] ------------ * PUTARG_REG ref REG rsi BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> Interval 11: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> DefList: { N038.t78. PUTARG_REG } N040 ( 3, 2) [000027] ------------ * LCL_VAR ref V04 tmp2 NA REG NA Interval 12: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB01 regmask=[allInt] minReg=1> DefList: { N038.t78. PUTARG_REG; N040.t27. LCL_VAR } N042 (???,???) [000079] ------------ * PUTARG_REG ref REG rdx BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> Interval 13: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdx] minReg=1> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed> DefList: { N038.t78. PUTARG_REG; N042.t79. PUTARG_REG } N044 ( 2, 10) [000050] ------------ * CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] REG NA Interval 14: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N038.t78. PUTARG_REG; N042.t79. PUTARG_REG; N044.t50. CNS_INT } N046 ( 4, 12) [000051] n---G------- * IND ref REG NA BB01 regmask=[allInt] minReg=1 last> Interval 15: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB01 regmask=[allInt] minReg=1> DefList: { N038.t78. PUTARG_REG; N042.t79. PUTARG_REG; N046.t51. IND } N048 (???,???) [000080] ----G------- * PUTARG_REG ref REG rdi BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> Interval 16: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> DefList: { N038.t78. PUTARG_REG; N042.t79. PUTARG_REG; N048.t80. PUTARG_REG } N050 ( 36, 32) [000029] --CXG------- * CALL ref System.String.Format REG NA BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> Interval 17: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> DefList: { N050.t29. CALL } N052 (???,???) [000081] --CXG------- * PUTARG_REG ref REG rdi BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> Interval 18: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> DefList: { N052.t81. PUTARG_REG } N054 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log REG NA BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> DefList: { } N056 (???,???) [000075] ------------ * IL_OFFSET void IL offset: 0x25 REG NA DefList: { } N058 ( 3, 2) [000032] ------------ * LCL_VAR byref V00 this NA REG NA Interval 19: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB01 regmask=[allInt] minReg=1> DefList: { N058.t32. LCL_VAR } N060 ( 4, 3) [000059] -c---------- * LEA(b+16) byref REG NA Contained DefList: { N058.t32. LCL_VAR } N062 ( 6, 5) [000033] *--XG------- * IND int REG NA BB01 regmask=[allInt] minReg=1 last> Interval 20: int RefPositions {} physReg:NA Preferences=[allInt] IND BB01 regmask=[allInt] minReg=1> DefList: { N062.t33. IND } N064 (???,???) [000082] ---XG------- * PUTARG_REG int REG rsi BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> Interval 21: int RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> DefList: { N064.t82. PUTARG_REG } N066 ( 2, 10) [000057] ------------ * CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] REG NA Interval 22: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N064.t82. PUTARG_REG; N066.t57. CNS_INT } N068 ( 4, 12) [000031] n---G------- * IND ref REG NA BB01 regmask=[allInt] minReg=1 last> Interval 23: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB01 regmask=[allInt] minReg=1> DefList: { N064.t82. PUTARG_REG; N068.t31. IND } N070 (???,???) [000083] ----G------- * PUTARG_REG ref REG rdi BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> Interval 24: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> DefList: { N064.t82. PUTARG_REG; N070.t83. PUTARG_REG } N072 ( 2, 10) [000084] ------------ * CNS_INT(h) long 0x7f6678eeddf8 ftn REG NA Interval 25: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N064.t82. PUTARG_REG; N070.t83. PUTARG_REG; N072.t84. CNS_INT } N074 ( 4, 12) [000085] -c---------- * IND long REG NA Contained DefList: { N064.t82. PUTARG_REG; N070.t83. PUTARG_REG; N072.t84. CNS_INT } N076 ( 24, 25) [000034] --CXG------- * CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item REG NA BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> Interval 26: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> DefList: { N076.t34. CALL } N078 ( 28, 28) [000065] DA-XG-----L- * STORE_LCL_VAR ref V06 tmp4 NA REG NA BB01 regmask=[allInt] minReg=1 last> DefList: { } N080 ( 3, 2) [000035] ------------ * LCL_VAR byref V00 this NA REG NA Interval 27: byref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB01 regmask=[allInt] minReg=1> DefList: { N080.t35. LCL_VAR } N082 ( 1, 1) [000062] -c---------- * CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] REG NA Contained DefList: { N080.t35. LCL_VAR } N084 ( 5, 4) [000063] ------------ * ADD byref REG NA BB01 regmask=[allInt] minReg=1 last> Interval 28: byref RefPositions {} physReg:NA Preferences=[allInt] ADD BB01 regmask=[allInt] minReg=1> Assigning related to DefList: { N084.t63. ADD } N086 ( 11, 8) [000042] -c-XG------- * OBJ struct REG NA Contained DefList: { N084.t63. ADD } N088 (???,???) [000086] ---XG------- * PUTARG_STK [+0x00] void (7 slots) (RepInstr) REG NA Interval 29: int RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_STK BB01 regmask=[rdi] minReg=1 fixed> Interval 30: int RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rcx] minReg=1> PUTARG_STK BB01 regmask=[rcx] minReg=1 fixed> Interval 31: int RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rsi] minReg=1> PUTARG_STK BB01 regmask=[rsi] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> PUTARG_STK BB01 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rsi] minReg=1 last fixed> DefList: { } N090 ( 3, 2) [000066] ------------ * LCL_VAR ref V06 tmp4 NA REG NA Interval 32: ref RefPositions {} physReg:NA Preferences=[allInt] LCL_VAR BB01 regmask=[allInt] minReg=1> DefList: { N090.t66. LCL_VAR } N092 (???,???) [000087] ------------ * PUTARG_REG ref REG rdi BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> Interval 33: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> DefList: { N092.t87. PUTARG_REG } N094 ( 3, 4) [000070] ------------ * LCL_FLD long V01 arg1 [+0] NA REG NA Interval 34: long RefPositions {} physReg:NA Preferences=[allInt] LCL_FLD BB01 regmask=[allInt] minReg=1> DefList: { N092.t87. PUTARG_REG; N094.t70. LCL_FLD } N096 (???,???) [000088] ------------ * PUTARG_REG long REG rsi BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> Interval 35: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> DefList: { N092.t87. PUTARG_REG; N096.t88. PUTARG_REG } N098 ( 3, 4) [000071] ------------ * LCL_FLD long V01 arg1 [+8] NA REG NA Interval 36: long RefPositions {} physReg:NA Preferences=[allInt] LCL_FLD BB01 regmask=[allInt] minReg=1> DefList: { N092.t87. PUTARG_REG; N096.t88. PUTARG_REG; N098.t71. LCL_FLD } N100 (???,???) [000089] ------------ * PUTARG_REG long REG rdx BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> Interval 37: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdx] minReg=1> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed> DefList: { N092.t87. PUTARG_REG; N096.t88. PUTARG_REG; N100.t89. PUTARG_REG } N102 ( 6, 8) [000069] -c---------- * FIELD_LIST struct REG NA Contained DefList: { N092.t87. PUTARG_REG; N096.t88. PUTARG_REG; N100.t89. PUTARG_REG } N104 ( 2, 10) [000056] ------------ * CNS_INT(h) long 0x7f6678060338 ftn REG r11 Interval 38: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[r11] minReg=1> CNS_INT BB01 regmask=[r11] minReg=1 fixed> DefList: { N092.t87. PUTARG_REG; N096.t88. PUTARG_REG; N100.t89. PUTARG_REG; N104.t56. CNS_INT } N106 (???,???) [000090] ------------ * PUTARG_REG long REG r11 BB01 regmask=[r11] minReg=1> BB01 regmask=[r11] minReg=1 last fixed> Interval 39: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[r11] minReg=1> PUTARG_REG BB01 regmask=[r11] minReg=1 fixed> DefList: { N092.t87. PUTARG_REG; N096.t88. PUTARG_REG; N100.t89. PUTARG_REG; N106.t90. PUTARG_REG } N108 ( 2, 10) [000091] ------------ * CNS_INT(h) long 0x7f6678060338 ftn REG NA Interval 40: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N092.t87. PUTARG_REG; N096.t88. PUTARG_REG; N100.t89. PUTARG_REG; N106.t90. PUTARG_REG; N108.t91. CNS_INT } N110 ( 4, 12) [000092] -c---------- * IND long REG NA Contained DefList: { N092.t87. PUTARG_REG; N096.t88. PUTARG_REG; N100.t89. PUTARG_REG; N106.t90. PUTARG_REG; N108.t91. CNS_INT } N112 ( 73, 67) [000038] --CXG------- * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend REG NA,NA BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> BB01 regmask=[r11] minReg=1> BB01 regmask=[r11] minReg=1 last fixed> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> Interval 41: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rax] minReg=1> CALL[0] BB01 regmask=[rax] minReg=1 fixed> Interval 42: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdx] minReg=1> CALL[1] BB01 regmask=[rdx] minReg=1 fixed> DefList: { N112.t38. CALL; N112.t38. CALL } N114 ( 77, 70) [000045] DA-XG------- * STORE_LCL_VAR struct V05 tmp3 NA REG NA BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> DefList: { } N116 ( 3, 2) [000046] -c-----N---- * LCL_VAR struct V05 tmp3 NA REG NA Contained DefList: { } N118 ( 4, 3) [000047] ------------ * RETURN struct REG NA Linear scan intervals BEFORE VALIDATING INTERVALS: Interval 0: long (constant) RefPositions {#1@5 #3@6} physReg:NA Preferences=[rdi] Interval 1: long RefPositions {#5@7 #7@8} physReg:NA Preferences=[rdi] Interval 2: ref RefPositions {#18@9 #19@10} physReg:NA Preferences=[rax] Interval 3: ref RefPositions {#20@13 #22@18} physReg:NA Preferences=[allInt] Interval 4: long RefPositions {#21@17 #23@18} physReg:NA Preferences=[allInt] Interval 5: long (constant) RefPositions {#24@21 #26@22} physReg:NA Preferences=[rdi] Interval 6: long RefPositions {#28@23 #30@24} physReg:NA Preferences=[rdi] Interval 7: ref RefPositions {#41@25 #42@26} physReg:NA Preferences=[rax] Interval 8: ref RefPositions {#43@29 #45@34} physReg:NA Preferences=[allInt] Interval 9: int RefPositions {#44@33 #46@34} physReg:NA Preferences=[allInt] Interval 10: ref RefPositions {#47@37 #49@38} physReg:NA Preferences=[rsi] Interval 11: ref RefPositions {#51@39 #65@50} physReg:NA Preferences=[rsi] Interval 12: ref RefPositions {#52@41 #54@42} physReg:NA Preferences=[rdx] Interval 13: ref RefPositions {#56@43 #67@50} physReg:NA Preferences=[rdx] Interval 14: long (constant) RefPositions {#57@45 #58@46} physReg:NA Preferences=[allInt] Interval 15: ref RefPositions {#59@47 #61@48} physReg:NA Preferences=[rdi] Interval 16: ref RefPositions {#63@49 #69@50} physReg:NA Preferences=[rdi] Interval 17: ref (def-use conflict) RefPositions {#80@51 #82@52} physReg:NA Preferences=[rax rdi] Interval 18: ref RefPositions {#84@53 #86@54} physReg:NA Preferences=[rdi] Interval 19: byref RefPositions {#96@59 #97@62} physReg:NA Preferences=[allInt] Interval 20: int RefPositions {#98@63 #100@64} physReg:NA Preferences=[rsi] Interval 21: int RefPositions {#102@65 #112@76} physReg:NA Preferences=[rsi] Interval 22: long (constant) RefPositions {#103@67 #104@68} physReg:NA Preferences=[allInt] Interval 23: ref RefPositions {#105@69 #107@70} physReg:NA Preferences=[rdi] Interval 24: ref RefPositions {#109@71 #114@76} physReg:NA Preferences=[rdi] Interval 25: long (constant) RefPositions {#110@73 #115@76} physReg:NA Preferences=[allInt] Interval 26: ref RefPositions {#126@77 #127@78} physReg:NA Preferences=[rax] Interval 27: byref RefPositions {#128@81 #129@84} physReg:NA Preferences=[allInt] RelatedInterval Interval 28: byref RefPositions {#130@85 #137@88} physReg:NA Preferences=[allInt] Interval 29: int (INTERNAL) RefPositions {#132@88 #138@88} physReg:NA Preferences=[rdi] Interval 30: int (INTERNAL) RefPositions {#134@88 #139@88} physReg:NA Preferences=[rcx] Interval 31: int (INTERNAL) RefPositions {#136@88 #140@88} physReg:NA Preferences=[rsi] Interval 32: ref RefPositions {#141@91 #143@92} physReg:NA Preferences=[rdi] Interval 33: ref RefPositions {#145@93 #164@112} physReg:NA Preferences=[rdi] Interval 34: long RefPositions {#146@95 #148@96} physReg:NA Preferences=[rsi] Interval 35: long RefPositions {#150@97 #166@112} physReg:NA Preferences=[rsi] Interval 36: long RefPositions {#151@99 #153@100} physReg:NA Preferences=[rdx] Interval 37: long RefPositions {#155@101 #168@112} physReg:NA Preferences=[rdx] Interval 38: long (constant) RefPositions {#157@105 #159@106} physReg:NA Preferences=[r11] Interval 39: long RefPositions {#161@107 #170@112} physReg:NA Preferences=[r11] Interval 40: long (constant) RefPositions {#162@109 #171@112} physReg:NA Preferences=[allInt] Interval 41: long RefPositions {#182@113 #185@114} physReg:NA Preferences=[rax] Interval 42: long RefPositions {#184@113 #186@114} physReg:NA Preferences=[rdx] ------------ REFPOSITIONS BEFORE VALIDATING INTERVALS: ------------ CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_FLD BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_FLD BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> LCL_VAR BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> BB01 regmask=[rdx] minReg=1> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> IND BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> IND BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> IND BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> ADD BB01 regmask=[allInt] minReg=1> BB01 regmask=[rdi] minReg=1> PUTARG_STK BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rcx] minReg=1> PUTARG_STK BB01 regmask=[rcx] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> PUTARG_STK BB01 regmask=[rsi] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> PUTARG_STK BB01 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rsi] minReg=1 last fixed> LCL_VAR BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> LCL_FLD BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> LCL_FLD BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> BB01 regmask=[rdx] minReg=1> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed> BB01 regmask=[r11] minReg=1> CNS_INT BB01 regmask=[r11] minReg=1 fixed> BB01 regmask=[r11] minReg=1> BB01 regmask=[r11] minReg=1 last fixed> BB01 regmask=[r11] minReg=1> PUTARG_REG BB01 regmask=[r11] minReg=1 fixed> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> BB01 regmask=[r11] minReg=1> BB01 regmask=[r11] minReg=1 last fixed> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL[0] BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rdx] minReg=1> CALL[1] BB01 regmask=[rdx] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> TUPLE STYLE DUMP WITH REF POSITIONS Incoming Parameters: BB01 [000..042) (return), preds={} succs={} ===== N002. IL_OFFSET IL offset: 0x0 N004. CNS_INT(h) 0x7f6678c127f0 class Def:(#1) N006. PUTARG_REG Use:(#3) Fixed:rdi(#2) * Def:(#5) rdi N008. CALL help Use:(#7) Fixed:rdi(#6) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#18) rax N010. V03 MEM Use:(#19) * N012. V03 MEM Def:(#20) N014. LEA(b+8) N016. V01 MEM Def:(#21) N018. STOREIND Use:(#22) * Use:(#23) * N020. CNS_INT(h) 0x7f6678beb1c0 class Def:(#24) N022. PUTARG_REG Use:(#26) Fixed:rdi(#25) * Def:(#28) rdi N024. CALL help Use:(#30) Fixed:rdi(#29) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#41) rax N026. V04 MEM Use:(#42) * N028. V04 MEM Def:(#43) N030. LEA(b+8) N032. V01 MEM Def:(#44) N034. STOREIND Use:(#45) * Use:(#46) * N036. V03 MEM Def:(#47) N038. PUTARG_REG Use:(#49) Fixed:rsi(#48) * Def:(#51) rsi N040. V04 MEM Def:(#52) N042. PUTARG_REG Use:(#54) Fixed:rdx(#53) * Def:(#56) rdx N044. CNS_INT(h) 0x64008A98 [ICON_STR_HDL] Def:(#57) N046. IND Use:(#58) * Def:(#59) N048. PUTARG_REG Use:(#61) Fixed:rdi(#60) * Def:(#63) rdi N050. CALL Use:(#65) Fixed:rsi(#64) * Use:(#67) Fixed:rdx(#66) * Use:(#69) Fixed:rdi(#68) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#80) rax N052. PUTARG_REG Use:(#82) Fixed:rdi(#81) * Def:(#84) rdi N054. CALL Use:(#86) Fixed:rdi(#85) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 N056. IL_OFFSET IL offset: 0x25 N058. V00 MEM Def:(#96) N060. LEA(b+16) N062. IND Use:(#97) * Def:(#98) N064. PUTARG_REG Use:(#100) Fixed:rsi(#99) * Def:(#102) rsi N066. CNS_INT(h) 0x7f6664004668 static Fseq[s_NetworkInterfaces] Def:(#103) N068. IND Use:(#104) * Def:(#105) N070. PUTARG_REG Use:(#107) Fixed:rdi(#106) * Def:(#109) rdi N072. CNS_INT(h) 0x7f6678eeddf8 ftn Def:(#110) N074. IND N076. CALL nullcheck Use:(#112) Fixed:rsi(#111) * Use:(#114) Fixed:rdi(#113) * Use:(#115) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#126) rax N078. V06 MEM Use:(#127) * N080. V00 MEM Def:(#128) Pref: N082. CNS_INT 56 field offset Fseq[m_ParallelSendQueue] N084. ADD Use:(#129) * Def:(#130) N086. OBJ N088. PUTARG_STK [+0x00] Def:(#132) rdi Def:(#134) rcx Def:(#136) rsi Use:(#137) * Use:(#138) * Use:(#139) * Use:(#140) * N090. V06 MEM Def:(#141) N092. PUTARG_REG Use:(#143) Fixed:rdi(#142) * Def:(#145) rdi N094. V01 MEM Def:(#146) N096. PUTARG_REG Use:(#148) Fixed:rsi(#147) * Def:(#150) rsi N098. V01 MEM Def:(#151) N100. PUTARG_REG Use:(#153) Fixed:rdx(#152) * Def:(#155) rdx N102. FIELD_LIST N104. CNS_INT(h) 0x7f6678060338 ftn Def:(#157) r11 N106. PUTARG_REG Use:(#159) Fixed:r11(#158) * Def:(#161) r11 N108. CNS_INT(h) 0x7f6678060338 ftn Def:(#162) N110. IND N112. CALLV stub Use:(#164) Fixed:rdi(#163) * Use:(#166) Fixed:rsi(#165) * Use:(#168) Fixed:rdx(#167) * Use:(#170) Fixed:r11(#169) * Use:(#171) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#182) rax Def:(#184) rdx N114. V05 MEM Use:(#185) * Use:(#186) * N116. V05 MEM N118. RETURN Linear scan intervals after buildIntervals: Interval 0: long (constant) RefPositions {#1@5 #3@6} physReg:NA Preferences=[rdi] Interval 1: long RefPositions {#5@7 #7@8} physReg:NA Preferences=[rdi] Interval 2: ref RefPositions {#18@9 #19@10} physReg:NA Preferences=[rax] Interval 3: ref RefPositions {#20@13 #22@18} physReg:NA Preferences=[allInt] Interval 4: long RefPositions {#21@17 #23@18} physReg:NA Preferences=[allInt] Interval 5: long (constant) RefPositions {#24@21 #26@22} physReg:NA Preferences=[rdi] Interval 6: long RefPositions {#28@23 #30@24} physReg:NA Preferences=[rdi] Interval 7: ref RefPositions {#41@25 #42@26} physReg:NA Preferences=[rax] Interval 8: ref RefPositions {#43@29 #45@34} physReg:NA Preferences=[allInt] Interval 9: int RefPositions {#44@33 #46@34} physReg:NA Preferences=[allInt] Interval 10: ref RefPositions {#47@37 #49@38} physReg:NA Preferences=[rsi] Interval 11: ref RefPositions {#51@39 #65@50} physReg:NA Preferences=[rsi] Interval 12: ref RefPositions {#52@41 #54@42} physReg:NA Preferences=[rdx] Interval 13: ref RefPositions {#56@43 #67@50} physReg:NA Preferences=[rdx] Interval 14: long (constant) RefPositions {#57@45 #58@46} physReg:NA Preferences=[allInt] Interval 15: ref RefPositions {#59@47 #61@48} physReg:NA Preferences=[rdi] Interval 16: ref RefPositions {#63@49 #69@50} physReg:NA Preferences=[rdi] Interval 17: ref (def-use conflict) RefPositions {#80@51 #82@52} physReg:NA Preferences=[rax rdi] Interval 18: ref RefPositions {#84@53 #86@54} physReg:NA Preferences=[rdi] Interval 19: byref RefPositions {#96@59 #97@62} physReg:NA Preferences=[allInt] Interval 20: int RefPositions {#98@63 #100@64} physReg:NA Preferences=[rsi] Interval 21: int RefPositions {#102@65 #112@76} physReg:NA Preferences=[rsi] Interval 22: long (constant) RefPositions {#103@67 #104@68} physReg:NA Preferences=[allInt] Interval 23: ref RefPositions {#105@69 #107@70} physReg:NA Preferences=[rdi] Interval 24: ref RefPositions {#109@71 #114@76} physReg:NA Preferences=[rdi] Interval 25: long (constant) RefPositions {#110@73 #115@76} physReg:NA Preferences=[allInt] Interval 26: ref RefPositions {#126@77 #127@78} physReg:NA Preferences=[rax] Interval 27: byref RefPositions {#128@81 #129@84} physReg:NA Preferences=[allInt] RelatedInterval Interval 28: byref RefPositions {#130@85 #137@88} physReg:NA Preferences=[allInt] Interval 29: int (INTERNAL) RefPositions {#132@88 #138@88} physReg:NA Preferences=[rdi] Interval 30: int (INTERNAL) RefPositions {#134@88 #139@88} physReg:NA Preferences=[rcx] Interval 31: int (INTERNAL) RefPositions {#136@88 #140@88} physReg:NA Preferences=[rsi] Interval 32: ref RefPositions {#141@91 #143@92} physReg:NA Preferences=[rdi] Interval 33: ref RefPositions {#145@93 #164@112} physReg:NA Preferences=[rdi] Interval 34: long RefPositions {#146@95 #148@96} physReg:NA Preferences=[rsi] Interval 35: long RefPositions {#150@97 #166@112} physReg:NA Preferences=[rsi] Interval 36: long RefPositions {#151@99 #153@100} physReg:NA Preferences=[rdx] Interval 37: long RefPositions {#155@101 #168@112} physReg:NA Preferences=[rdx] Interval 38: long (constant) RefPositions {#157@105 #159@106} physReg:NA Preferences=[r11] Interval 39: long RefPositions {#161@107 #170@112} physReg:NA Preferences=[r11] Interval 40: long (constant) RefPositions {#162@109 #171@112} physReg:NA Preferences=[allInt] Interval 41: long RefPositions {#182@113 #185@114} physReg:NA Preferences=[rax] Interval 42: long RefPositions {#184@113 #186@114} physReg:NA Preferences=[rdx] *************** In LinearScan::allocateRegisters() Linear scan intervals before allocateRegisters: Interval 0: long (constant) RefPositions {#1@5 #3@6} physReg:NA Preferences=[rdi] Interval 1: long RefPositions {#5@7 #7@8} physReg:NA Preferences=[rdi] Interval 2: ref RefPositions {#18@9 #19@10} physReg:NA Preferences=[rax] Interval 3: ref RefPositions {#20@13 #22@18} physReg:NA Preferences=[allInt] Interval 4: long RefPositions {#21@17 #23@18} physReg:NA Preferences=[allInt] Interval 5: long (constant) RefPositions {#24@21 #26@22} physReg:NA Preferences=[rdi] Interval 6: long RefPositions {#28@23 #30@24} physReg:NA Preferences=[rdi] Interval 7: ref RefPositions {#41@25 #42@26} physReg:NA Preferences=[rax] Interval 8: ref RefPositions {#43@29 #45@34} physReg:NA Preferences=[allInt] Interval 9: int RefPositions {#44@33 #46@34} physReg:NA Preferences=[allInt] Interval 10: ref RefPositions {#47@37 #49@38} physReg:NA Preferences=[rsi] Interval 11: ref RefPositions {#51@39 #65@50} physReg:NA Preferences=[rsi] Interval 12: ref RefPositions {#52@41 #54@42} physReg:NA Preferences=[rdx] Interval 13: ref RefPositions {#56@43 #67@50} physReg:NA Preferences=[rdx] Interval 14: long (constant) RefPositions {#57@45 #58@46} physReg:NA Preferences=[allInt] Interval 15: ref RefPositions {#59@47 #61@48} physReg:NA Preferences=[rdi] Interval 16: ref RefPositions {#63@49 #69@50} physReg:NA Preferences=[rdi] Interval 17: ref (def-use conflict) RefPositions {#80@51 #82@52} physReg:NA Preferences=[rax rdi] Interval 18: ref RefPositions {#84@53 #86@54} physReg:NA Preferences=[rdi] Interval 19: byref RefPositions {#96@59 #97@62} physReg:NA Preferences=[allInt] Interval 20: int RefPositions {#98@63 #100@64} physReg:NA Preferences=[rsi] Interval 21: int RefPositions {#102@65 #112@76} physReg:NA Preferences=[rsi] Interval 22: long (constant) RefPositions {#103@67 #104@68} physReg:NA Preferences=[allInt] Interval 23: ref RefPositions {#105@69 #107@70} physReg:NA Preferences=[rdi] Interval 24: ref RefPositions {#109@71 #114@76} physReg:NA Preferences=[rdi] Interval 25: long (constant) RefPositions {#110@73 #115@76} physReg:NA Preferences=[allInt] Interval 26: ref RefPositions {#126@77 #127@78} physReg:NA Preferences=[rax] Interval 27: byref RefPositions {#128@81 #129@84} physReg:NA Preferences=[allInt] RelatedInterval Interval 28: byref RefPositions {#130@85 #137@88} physReg:NA Preferences=[allInt] Interval 29: int (INTERNAL) RefPositions {#132@88 #138@88} physReg:NA Preferences=[rdi] Interval 30: int (INTERNAL) RefPositions {#134@88 #139@88} physReg:NA Preferences=[rcx] Interval 31: int (INTERNAL) RefPositions {#136@88 #140@88} physReg:NA Preferences=[rsi] Interval 32: ref RefPositions {#141@91 #143@92} physReg:NA Preferences=[rdi] Interval 33: ref RefPositions {#145@93 #164@112} physReg:NA Preferences=[rdi] Interval 34: long RefPositions {#146@95 #148@96} physReg:NA Preferences=[rsi] Interval 35: long RefPositions {#150@97 #166@112} physReg:NA Preferences=[rsi] Interval 36: long RefPositions {#151@99 #153@100} physReg:NA Preferences=[rdx] Interval 37: long RefPositions {#155@101 #168@112} physReg:NA Preferences=[rdx] Interval 38: long (constant) RefPositions {#157@105 #159@106} physReg:NA Preferences=[r11] Interval 39: long RefPositions {#161@107 #170@112} physReg:NA Preferences=[r11] Interval 40: long (constant) RefPositions {#162@109 #171@112} physReg:NA Preferences=[allInt] Interval 41: long RefPositions {#182@113 #185@114} physReg:NA Preferences=[rax] Interval 42: long RefPositions {#184@113 #186@114} physReg:NA Preferences=[rdx] ------------ REFPOSITIONS BEFORE ALLOCATION: ------------ CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_FLD BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_FLD BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> LCL_VAR BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> BB01 regmask=[rdx] minReg=1> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> IND BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> IND BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> IND BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> ADD BB01 regmask=[allInt] minReg=1> BB01 regmask=[rdi] minReg=1> PUTARG_STK BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rcx] minReg=1> PUTARG_STK BB01 regmask=[rcx] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> PUTARG_STK BB01 regmask=[rsi] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> PUTARG_STK BB01 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rsi] minReg=1 last fixed> LCL_VAR BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> LCL_FLD BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> LCL_FLD BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> BB01 regmask=[rdx] minReg=1> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed> BB01 regmask=[r11] minReg=1> CNS_INT BB01 regmask=[r11] minReg=1 fixed> BB01 regmask=[r11] minReg=1> BB01 regmask=[r11] minReg=1 last fixed> BB01 regmask=[r11] minReg=1> PUTARG_REG BB01 regmask=[r11] minReg=1 fixed> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> BB01 regmask=[r11] minReg=1> BB01 regmask=[r11] minReg=1 last fixed> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL[0] BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rdx] minReg=1> CALL[1] BB01 regmask=[rdx] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> Allocating Registers -------------------- The following table has one or more rows for each RefPosition that is handled during allocation. The first column provides the basic information about the RefPosition, with its type (e.g. Def, Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the action taken during allocation (e.g. Alloc a new register, or Keep an existing one). The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which may increase during allocation, in which case additional columns will appear. Registers which are not marked modified have ---- in their column. --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ | | | | | | | | | | | 0.#0 BB1 PredBB0 | | | | | | | | | | | 5.#1 C0 Def Alloc rdi | | | | | |C0 a| | | | | 6.#2 rdi Fixd Keep rdi | | | | | |C0 a| | | | | 6.#3 C0 Use * Keep rdi | | | | | |C0 a| | | | | 7.#4 rdi Fixd Keep rdi | | | | | | | | | | | 7.#5 I1 Def Alloc rdi | | | | | |I1 a| | | | | 8.#6 rdi Fixd Keep rdi | | | | | |I1 a| | | | | 8.#7 I1 Use * Keep rdi | | | | | |I1 a| | | | | 9.#8 rax Kill Keep rax | | | | | | | | | | | 9.#9 rcx Kill Keep rcx | | | | | | | | | | | 9.#10 rdx Kill Keep rdx | | | | | | | | | | | 9.#11 rsi Kill Keep rsi | | | | | | | | | | | 9.#12 rdi Kill Keep rdi | | | | | | | | | | | 9.#13 r8 Kill Keep r8 | | | | | | | | | | | 9.#14 r9 Kill Keep r9 | | | | | | | | | | | 9.#15 r10 Kill Keep r10 | | | | | | | | | | | 9.#16 r11 Kill Keep r11 | | | | | | | | | | | 9.#17 rax Fixd Keep rax | | | | | | | | | | | 9.#18 I2 Def Alloc rax |I2 a| | | | | | | | | | 10.#19 I2 Use * Keep rax |I2 a| | | | | | | | | | 13.#20 I3 Def Alloc rdi | | | | | |I3 a| | | | | 17.#21 I4 Def Alloc rax |I4 a| | | | |I3 a| | | | | 18.#22 I3 Use * Keep rdi |I4 a| | | | |I3 a| | | | | 18.#23 I4 Use * Keep rax |I4 a| | | | |I3 a| | | | | 21.#24 C5 Def Alloc rdi | | | | | |C5 a| | | | | 22.#25 rdi Fixd Keep rdi | | | | | |C5 a| | | | | 22.#26 C5 Use * Keep rdi | | | | | |C5 a| | | | | 23.#27 rdi Fixd Keep rdi | | | | | | | | | | | 23.#28 I6 Def Alloc rdi | | | | | |I6 a| | | | | 24.#29 rdi Fixd Keep rdi | | | | | |I6 a| | | | | 24.#30 I6 Use * Keep rdi | | | | | |I6 a| | | | | 25.#31 rax Kill Keep rax | | | | | | | | | | | 25.#32 rcx Kill Keep rcx | | | | | | | | | | | 25.#33 rdx Kill Keep rdx | | | | | | | | | | | 25.#34 rsi Kill Keep rsi | | | | | | | | | | | 25.#35 rdi Kill Keep rdi | | | | | | | | | | | 25.#36 r8 Kill Keep r8 | | | | | | | | | | | 25.#37 r9 Kill Keep r9 | | | | | | | | | | | 25.#38 r10 Kill Keep r10 | | | | | | | | | | | 25.#39 r11 Kill Keep r11 | | | | | | | | | | | 25.#40 rax Fixd Keep rax | | | | | | | | | | | 25.#41 I7 Def Alloc rax |I7 a| | | | | | | | | | 26.#42 I7 Use * Keep rax |I7 a| | | | | | | | | | 29.#43 I8 Def Alloc rsi | | | | |I8 a| | | | | | 33.#44 I9 Def Alloc rdx | | |I9 a| |I8 a| | | | | | 34.#45 I8 Use * Keep rsi | | |I9 a| |I8 a| | | | | | 34.#46 I9 Use * Keep rdx | | |I9 a| |I8 a| | | | | | 37.#47 I10 Def Alloc rsi | | | | |I10a| | | | | | 38.#48 rsi Fixd Keep rsi | | | | |I10a| | | | | | 38.#49 I10 Use * Keep rsi | | | | |I10a| | | | | | 39.#50 rsi Fixd Keep rsi | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 39.#51 I11 Def Alloc rsi | | | | |I11a| | | | | | 41.#52 I12 Def Alloc rdx | | |I12a| |I11a| | | | | | 42.#53 rdx Fixd Keep rdx | | |I12a| |I11a| | | | | | 42.#54 I12 Use * Keep rdx | | |I12a| |I11a| | | | | | 43.#55 rdx Fixd Keep rdx | | | | |I11a| | | | | | 43.#56 I13 Def Alloc rdx | | |I13a| |I11a| | | | | | 45.#57 C14 Def Alloc rdi | | |I13a| |I11a|C14a| | | | | 46.#58 C14 Use * Keep rdi | | |I13a| |I11a|C14a| | | | | 47.#59 I15 Def Alloc rdi | | |I13a| |I11a|I15a| | | | | 48.#60 rdi Fixd Keep rdi | | |I13a| |I11a|I15a| | | | | 48.#61 I15 Use * Keep rdi | | |I13a| |I11a|I15a| | | | | 49.#62 rdi Fixd Keep rdi | | |I13a| |I11a| | | | | | 49.#63 I16 Def Alloc rdi | | |I13a| |I11a|I16a| | | | | 50.#64 rsi Fixd Keep rsi | | |I13a| |I11a|I16a| | | | | 50.#65 I11 Use * Keep rsi | | |I13a| |I11a|I16a| | | | | 50.#66 rdx Fixd Keep rdx | | |I13a| |I11a|I16a| | | | | 50.#67 I13 Use * Keep rdx | | |I13a| |I11a|I16a| | | | | 50.#68 rdi Fixd Keep rdi | | |I13a| |I11a|I16a| | | | | 50.#69 I16 Use * Keep rdi | | |I13a| |I11a|I16a| | | | | 51.#70 rax Kill Keep rax | | | | | | | | | | | 51.#71 rcx Kill Keep rcx | | | | | | | | | | | 51.#72 rdx Kill Keep rdx | | | | | | | | | | | 51.#73 rsi Kill Keep rsi | | | | | | | | | | | 51.#74 rdi Kill Keep rdi | | | | | | | | | | | 51.#75 r8 Kill Keep r8 | | | | | | | | | | | 51.#76 r9 Kill Keep r9 | | | | | | | | | | | 51.#77 r10 Kill Keep r10 | | | | | | | | | | | 51.#78 r11 Kill Keep r11 | | | | | | | | | | | 51.#79 rax Fixd Keep rax | | | | | | | | | | | 51.#80 I17 Def DUconflict | | | | | | | | | | | Case #6 need a copy | | | | | | | | | | | Alloc rax |I17a| | | | | | | | | | 52.#81 rdi Fixd Keep rdi |I17a| | | | | | | | | | 52.#82 I17 Use * Copy rdi |I17a| | | | |I17a| | | | | 53.#83 rdi Fixd Keep rdi | | | | | | | | | | | 53.#84 I18 Def Alloc rdi | | | | | |I18a| | | | | 54.#85 rdi Fixd Keep rdi | | | | | |I18a| | | | | 54.#86 I18 Use * Keep rdi | | | | | |I18a| | | | | 55.#87 rax Kill Keep rax | | | | | | | | | | | 55.#88 rcx Kill Keep rcx | | | | | | | | | | | 55.#89 rdx Kill Keep rdx | | | | | | | | | | | 55.#90 rsi Kill Keep rsi | | | | | | | | | | | 55.#91 rdi Kill Keep rdi | | | | | | | | | | | 55.#92 r8 Kill Keep r8 | | | | | | | | | | | 55.#93 r9 Kill Keep r9 | | | | | | | | | | | 55.#94 r10 Kill Keep r10 | | | | | | | | | | | 55.#95 r11 Kill Keep r11 | | | | | | | | | | | 59.#96 I19 Def Alloc rsi | | | | |I19a| | | | | | 62.#97 I19 Use * Keep rsi | | | | |I19a| | | | | | 63.#98 I20 Def Alloc rsi | | | | |I20a| | | | | | 64.#99 rsi Fixd Keep rsi | | | | |I20a| | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 64.#100 I20 Use * Keep rsi | | | | |I20a| | | | | | 65.#101 rsi Fixd Keep rsi | | | | | | | | | | | 65.#102 I21 Def Alloc rsi | | | | |I21a| | | | | | 67.#103 C22 Def Alloc rdi | | | | |I21a|C22a| | | | | 68.#104 C22 Use * Keep rdi | | | | |I21a|C22a| | | | | 69.#105 I23 Def Alloc rdi | | | | |I21a|I23a| | | | | 70.#106 rdi Fixd Keep rdi | | | | |I21a|I23a| | | | | 70.#107 I23 Use * Keep rdi | | | | |I21a|I23a| | | | | 71.#108 rdi Fixd Keep rdi | | | | |I21a| | | | | | 71.#109 I24 Def Alloc rdi | | | | |I21a|I24a| | | | | 73.#110 C25 Def Alloc rax |C25a| | | |I21a|I24a| | | | | 76.#111 rsi Fixd Keep rsi |C25a| | | |I21a|I24a| | | | | 76.#112 I21 Use * Keep rsi |C25a| | | |I21a|I24a| | | | | 76.#113 rdi Fixd Keep rdi |C25a| | | |I21a|I24a| | | | | 76.#114 I24 Use * Keep rdi |C25a| | | |I21a|I24a| | | | | 76.#115 C25 Use * Keep rax |C25a| | | |I21a|I24a| | | | | 77.#116 rax Kill Keep rax | | | | | | | | | | | 77.#117 rcx Kill Keep rcx | | | | | | | | | | | 77.#118 rdx Kill Keep rdx | | | | | | | | | | | 77.#119 rsi Kill Keep rsi | | | | | | | | | | | 77.#120 rdi Kill Keep rdi | | | | | | | | | | | 77.#121 r8 Kill Keep r8 | | | | | | | | | | | 77.#122 r9 Kill Keep r9 | | | | | | | | | | | 77.#123 r10 Kill Keep r10 | | | | | | | | | | | 77.#124 r11 Kill Keep r11 | | | | | | | | | | | 77.#125 rax Fixd Keep rax | | | | | | | | | | | 77.#126 I26 Def Alloc rax |I26a| | | | | | | | | | 78.#127 I26 Use * Keep rax |I26a| | | | | | | | | | 81.#128 I27 Def Alloc rdx | | |I27a| | | | | | | | 84.#129 I27 Use * Keep rdx | | |I27a| | | | | | | | 85.#130 I28 Def Alloc rdx | | |I28a| | | | | | | | 88.#131 rdi Fixd Keep rdi | | |I28a| | | | | | | | 88.#132 I29 Def Alloc rdi | | |I28a| | |I29a| | | | | 88.#133 rcx Fixd Keep rcx | | |I28a| | |I29a| | | | | 88.#134 I30 Def Alloc rcx | |I30a|I28a| | |I29a| | | | | 88.#135 rsi Fixd Keep rsi | |I30a|I28a| | |I29a| | | | | 88.#136 I31 Def Alloc rsi | |I30a|I28a| |I31a|I29a| | | | | 88.#137 I28 Use * Keep rdx | |I30a|I28a| |I31a|I29a| | | | | 88.#138 I29 Use * Keep rdi | |I30a|I28a| |I31a|I29a| | | | | 88.#139 I30 Use * Keep rcx | |I30a|I28a| |I31a|I29a| | | | | 88.#140 I31 Use * Keep rsi | |I30a|I28a| |I31a|I29a| | | | | 91.#141 I32 Def Alloc rdi | | | | | |I32a| | | | | 92.#142 rdi Fixd Keep rdi | | | | | |I32a| | | | | 92.#143 I32 Use * Keep rdi | | | | | |I32a| | | | | 93.#144 rdi Fixd Keep rdi | | | | | | | | | | | 93.#145 I33 Def Alloc rdi | | | | | |I33a| | | | | 95.#146 I34 Def Alloc rsi | | | | |I34a|I33a| | | | | 96.#147 rsi Fixd Keep rsi | | | | |I34a|I33a| | | | | 96.#148 I34 Use * Keep rsi | | | | |I34a|I33a| | | | | 97.#149 rsi Fixd Keep rsi | | | | | |I33a| | | | | 97.#150 I35 Def Alloc rsi | | | | |I35a|I33a| | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ 99.#151 I36 Def Alloc rdx | | |I36a| |I35a|I33a| | | | | 100.#152 rdx Fixd Keep rdx | | |I36a| |I35a|I33a| | | | | 100.#153 I36 Use * Keep rdx | | |I36a| |I35a|I33a| | | | | 101.#154 rdx Fixd Keep rdx | | | | |I35a|I33a| | | | | 101.#155 I37 Def Alloc rdx | | |I37a| |I35a|I33a| | | | | 105.#156 r11 Fixd Keep r11 | | |I37a| |I35a|I33a| | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 105.#157 C38 Def Alloc r11 | | |I37a| |I35a|I33a| | |C38a| | | 106.#158 r11 Fixd Keep r11 | | |I37a| |I35a|I33a| | |C38a| | | 106.#159 C38 Use * Keep r11 | | |I37a| |I35a|I33a| | |C38a| | | 107.#160 r11 Fixd Keep r11 | | |I37a| |I35a|I33a| | | | | | 107.#161 I39 Def Alloc r11 | | |I37a| |I35a|I33a| | |I39a| | | 109.#162 C40 Def Alloc rax |C40a| |I37a| |I35a|I33a| | |I39a| | | 112.#163 rdi Fixd Keep rdi |C40a| |I37a| |I35a|I33a| | |I39a| | | 112.#164 I33 Use * Keep rdi |C40a| |I37a| |I35a|I33a| | |I39a| | | 112.#165 rsi Fixd Keep rsi |C40a| |I37a| |I35a|I33a| | |I39a| | | 112.#166 I35 Use * Keep rsi |C40a| |I37a| |I35a|I33a| | |I39a| | | 112.#167 rdx Fixd Keep rdx |C40a| |I37a| |I35a|I33a| | |I39a| | | 112.#168 I37 Use * Keep rdx |C40a| |I37a| |I35a|I33a| | |I39a| | | 112.#169 r11 Fixd Keep r11 |C40a| |I37a| |I35a|I33a| | |I39a| | | 112.#170 I39 Use * Keep r11 |C40a| |I37a| |I35a|I33a| | |I39a| | | 112.#171 C40 Use * Keep rax |C40a| |I37a| |I35a|I33a| | |I39a| | | 113.#172 rax Kill Keep rax | | | | | | | | | | | | 113.#173 rcx Kill Keep rcx | | | | | | | | | | | | 113.#174 rdx Kill Keep rdx | | | | | | | | | | | | 113.#175 rsi Kill Keep rsi | | | | | | | | | | | | 113.#176 rdi Kill Keep rdi | | | | | | | | | | | | 113.#177 r8 Kill Keep r8 | | | | | | | | | | | | 113.#178 r9 Kill Keep r9 | | | | | | | | | | | | 113.#179 r10 Kill Keep r10 | | | | | | | | | | | | 113.#180 r11 Kill Keep r11 | | | | | | | | | | | | 113.#181 rax Fixd Keep rax | | | | | | | | | | | | 113.#182 I41 Def Alloc rax |I41a| | | | | | | | | | | 113.#183 rdx Fixd Keep rdx |I41a| | | | | | | | | | | 113.#184 I42 Def Alloc rdx |I41a| |I42a| | | | | | | | | 114.#185 I41 Use * Keep rax |I41a| |I42a| | | | | | | | | 114.#186 I42 Use * Keep rdx | | | | | | | | | | | | ------------ REFPOSITIONS AFTER ALLOCATION: ------------ CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rax] minReg=1 last> LCL_VAR BB01 regmask=[rdi] minReg=1> LCL_FLD BB01 regmask=[rax] minReg=1> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[rax] minReg=1 last> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rax] minReg=1 last> LCL_VAR BB01 regmask=[rsi] minReg=1> LCL_FLD BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> LCL_VAR BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> LCL_VAR BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> BB01 regmask=[rdx] minReg=1> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last> IND BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last move fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> LCL_VAR BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last> IND BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last> IND BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> CNS_INT BB01 regmask=[rax] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rax] minReg=1 last> LCL_VAR BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last> ADD BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdi] minReg=1> PUTARG_STK BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rcx] minReg=1> PUTARG_STK BB01 regmask=[rcx] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> PUTARG_STK BB01 regmask=[rsi] minReg=1 fixed> BB01 regmask=[rdx] minReg=1 last> PUTARG_STK BB01 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rsi] minReg=1 last fixed> LCL_VAR BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> LCL_FLD BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> LCL_FLD BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> BB01 regmask=[rdx] minReg=1> PUTARG_REG BB01 regmask=[rdx] minReg=1 fixed> BB01 regmask=[r11] minReg=1> CNS_INT BB01 regmask=[r11] minReg=1 fixed> BB01 regmask=[r11] minReg=1> BB01 regmask=[r11] minReg=1 last fixed> BB01 regmask=[r11] minReg=1> PUTARG_REG BB01 regmask=[r11] minReg=1 fixed> CNS_INT BB01 regmask=[rax] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rdx] minReg=1 last fixed> BB01 regmask=[r11] minReg=1> BB01 regmask=[r11] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL[0] BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rdx] minReg=1> CALL[1] BB01 regmask=[rdx] minReg=1 fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> Active intervals at end of allocation: Trees after linear scan register allocator (LSRA) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) (return), preds={} succs={} N002 (???,???) [000072] ------------ IL_OFFSET void IL offset: 0x0 REG NA N004 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class REG rdi /--* t4 long N006 (???,???) [000076] ------------ t76 = * PUTARG_REG long REG rdi /--* t76 long arg0 in rdi N008 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG rax /--* t5 ref N010 ( 20, 19) [000007] DA---------- * STORE_LCL_VAR ref V03 tmp1 NA REG NA N012 ( 3, 2) [000008] ------------ t8 = LCL_VAR ref V03 tmp1 rdi REG rdi /--* t8 ref N014 ( 4, 3) [000010] -c---------- t10 = * LEA(b+8) byref REG NA N016 ( 3, 4) [000003] ------------ t3 = LCL_FLD long V01 arg1 [+0] Fseq[JobGroup] rax REG rax /--* t10 byref +--* t3 long N018 (???,???) [000073] -A-XG------- * STOREIND long REG NA N020 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class REG rdi /--* t18 long N022 (???,???) [000077] ------------ t77 = * PUTARG_REG long REG rdi /--* t77 long arg0 in rdi N024 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG rax /--* t19 ref N026 ( 20, 19) [000021] DA---------- * STORE_LCL_VAR ref V04 tmp2 NA REG NA N028 ( 3, 2) [000022] ------------ t22 = LCL_VAR ref V04 tmp2 rsi REG rsi /--* t22 ref N030 ( 4, 3) [000024] -c---------- t24 = * LEA(b+8) byref REG NA N032 ( 3, 4) [000017] ------------ t17 = LCL_FLD int V01 arg1 [+8] Fseq[Version] rdx REG rdx /--* t24 byref +--* t17 int N034 (???,???) [000074] -A-XG------- * STOREIND int REG NA N036 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V03 tmp1 rsi REG rsi /--* t13 ref N038 (???,???) [000078] ------------ t78 = * PUTARG_REG ref REG rsi N040 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V04 tmp2 rdx REG rdx /--* t27 ref N042 (???,???) [000079] ------------ t79 = * PUTARG_REG ref REG rdx N044 ( 2, 10) [000050] ------------ t50 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] REG rdi /--* t50 long N046 ( 4, 12) [000051] n---G------- t51 = * IND ref REG rdi /--* t51 ref N048 (???,???) [000080] ----G------- t80 = * PUTARG_REG ref REG rdi /--* t78 ref arg1 in rsi +--* t79 ref arg2 in rdx +--* t80 ref arg0 in rdi N050 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format REG rax /--* t29 ref [000093] --CXG------- t93 = * COPY ref REG rdi,NA /--* t93 ref N052 (???,???) [000081] --CXG------- t81 = * PUTARG_REG ref REG rdi /--* t81 ref arg0 in rdi N054 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log REG NA N056 (???,???) [000075] ------------ IL_OFFSET void IL offset: 0x25 REG NA N058 ( 3, 2) [000032] ------------ t32 = LCL_VAR byref V00 this rsi REG rsi /--* t32 byref N060 ( 4, 3) [000059] -c---------- t59 = * LEA(b+16) byref REG NA /--* t59 byref N062 ( 6, 5) [000033] *--XG------- t33 = * IND int REG rsi /--* t33 int N064 (???,???) [000082] ---XG------- t82 = * PUTARG_REG int REG rsi N066 ( 2, 10) [000057] ------------ t57 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] REG rdi /--* t57 long N068 ( 4, 12) [000031] n---G------- t31 = * IND ref REG rdi /--* t31 ref N070 (???,???) [000083] ----G------- t83 = * PUTARG_REG ref REG rdi N072 ( 2, 10) [000084] ------------ t84 = CNS_INT(h) long 0x7f6678eeddf8 ftn REG rax /--* t84 long N074 ( 4, 12) [000085] -c---------- t85 = * IND long REG NA /--* t82 int arg1 in rsi +--* t83 ref this in rdi +--* t85 long control expr N076 ( 24, 25) [000034] --CXG------- t34 = * CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item REG rax /--* t34 ref N078 ( 28, 28) [000065] DA-XG-----L- * STORE_LCL_VAR ref V06 tmp4 NA REG NA N080 ( 3, 2) [000035] ------------ t35 = LCL_VAR byref V00 this rdx REG rdx N082 ( 1, 1) [000062] -c---------- t62 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] REG NA /--* t35 byref +--* t62 long N084 ( 5, 4) [000063] ------------ t63 = * ADD byref REG rdx /--* t63 byref N086 ( 11, 8) [000042] -c-XG------- t42 = * OBJ struct REG NA /--* t42 struct N088 (???,???) [000086] ---XG------- * PUTARG_STK [+0x00] void (7 slots) (RepInstr) REG NA N090 ( 3, 2) [000066] ------------ t66 = LCL_VAR ref V06 tmp4 rdi REG rdi /--* t66 ref N092 (???,???) [000087] ------------ t87 = * PUTARG_REG ref REG rdi N094 ( 3, 4) [000070] ------------ t70 = LCL_FLD long V01 arg1 [+0] rsi REG rsi /--* t70 long N096 (???,???) [000088] ------------ t88 = * PUTARG_REG long REG rsi N098 ( 3, 4) [000071] ------------ t71 = LCL_FLD long V01 arg1 [+8] rdx REG rdx /--* t71 long N100 (???,???) [000089] ------------ t89 = * PUTARG_REG long REG rdx /--* t88 long +--* t89 long N102 ( 6, 8) [000069] -c---------- t69 = * FIELD_LIST struct REG NA N104 ( 2, 10) [000056] ------------ t56 = CNS_INT(h) long 0x7f6678060338 ftn REG r11 /--* t56 long N106 (???,???) [000090] ------------ t90 = * PUTARG_REG long REG r11 N108 ( 2, 10) [000091] ------------ t91 = CNS_INT(h) long 0x7f6678060338 ftn REG rax /--* t91 long N110 ( 4, 12) [000092] -c---------- t92 = * IND long REG NA /--* t87 ref this in rdi +--* t69 struct arg3 rsi,rdx +--* t90 long arg1 in r11 +--* t92 long control expr N112 ( 73, 67) [000038] --CXG------- t38 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend REG rax,rdx /--* t38 struct N114 ( 77, 70) [000045] DA-XG------- * STORE_LCL_VAR struct V05 tmp3 NA REG NA N116 ( 3, 2) [000046] -c-----N---- t46 = LCL_VAR struct V05 tmp3 NA REG NA /--* t46 struct N118 ( 4, 3) [000047] ------------ * RETURN struct REG NA ------------------------------------------------------------------------------------------------------------------- Final allocation --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 0.#0 BB1 PredBB0 | | | | | | | | | | | | 5.#1 C0 Def Alloc rdi | | | | | |C0 a| | | | | | 6.#2 rdi Fixd Keep rdi | | | | | |C0 a| | | | | | 6.#3 C0 Use * Keep rdi | | | | | |C0 i| | | | | | 7.#4 rdi Fixd Keep rdi | | | | | | | | | | | | 7.#5 I1 Def Alloc rdi | | | | | |I1 a| | | | | | 8.#6 rdi Fixd Keep rdi | | | | | |I1 a| | | | | | 8.#7 I1 Use * Keep rdi | | | | | |I1 i| | | | | | 9.#8 rax Kill Keep rax | | | | | | | | | | | | 9.#9 rcx Kill Keep rcx | | | | | | | | | | | | 9.#10 rdx Kill Keep rdx | | | | | | | | | | | | 9.#11 rsi Kill Keep rsi | | | | | | | | | | | | 9.#12 rdi Kill Keep rdi | | | | | | | | | | | | 9.#13 r8 Kill Keep r8 | | | | | | | | | | | | 9.#14 r9 Kill Keep r9 | | | | | | | | | | | | 9.#15 r10 Kill Keep r10 | | | | | | | | | | | | 9.#16 r11 Kill Keep r11 | | | | | | | | | | | | 9.#17 rax Fixd Keep rax | | | | | | | | | | | | 9.#18 I2 Def Alloc rax |I2 a| | | | | | | | | | | 10.#19 I2 Use * Keep rax |I2 i| | | | | | | | | | | 13.#20 I3 Def Alloc rdi | | | | | |I3 a| | | | | | 17.#21 I4 Def Alloc rax |I4 a| | | | |I3 a| | | | | | 18.#22 I3 Use * Keep rdi |I4 a| | | | |I3 i| | | | | | 18.#23 I4 Use * Keep rax |I4 i| | | | | | | | | | | 21.#24 C5 Def Alloc rdi | | | | | |C5 a| | | | | | 22.#25 rdi Fixd Keep rdi | | | | | |C5 a| | | | | | 22.#26 C5 Use * Keep rdi | | | | | |C5 i| | | | | | 23.#27 rdi Fixd Keep rdi | | | | | | | | | | | | 23.#28 I6 Def Alloc rdi | | | | | |I6 a| | | | | | 24.#29 rdi Fixd Keep rdi | | | | | |I6 a| | | | | | 24.#30 I6 Use * Keep rdi | | | | | |I6 i| | | | | | 25.#31 rax Kill Keep rax | | | | | | | | | | | | 25.#32 rcx Kill Keep rcx | | | | | | | | | | | | 25.#33 rdx Kill Keep rdx | | | | | | | | | | | | 25.#34 rsi Kill Keep rsi | | | | | | | | | | | | 25.#35 rdi Kill Keep rdi | | | | | | | | | | | | 25.#36 r8 Kill Keep r8 | | | | | | | | | | | | 25.#37 r9 Kill Keep r9 | | | | | | | | | | | | 25.#38 r10 Kill Keep r10 | | | | | | | | | | | | 25.#39 r11 Kill Keep r11 | | | | | | | | | | | | 25.#40 rax Fixd Keep rax | | | | | | | | | | | | 25.#41 I7 Def Alloc rax |I7 a| | | | | | | | | | | 26.#42 I7 Use * Keep rax |I7 i| | | | | | | | | | | 29.#43 I8 Def Alloc rsi | | | | |I8 a| | | | | | | 33.#44 I9 Def Alloc rdx | | |I9 a| |I8 a| | | | | | | 34.#45 I8 Use * Keep rsi | | |I9 a| |I8 i| | | | | | | 34.#46 I9 Use * Keep rdx | | |I9 i| | | | | | | | | 37.#47 I10 Def Alloc rsi | | | | |I10a| | | | | | | 38.#48 rsi Fixd Keep rsi | | | | |I10a| | | | | | | 38.#49 I10 Use * Keep rsi | | | | |I10i| | | | | | | 39.#50 rsi Fixd Keep rsi | | | | | | | | | | | | 39.#51 I11 Def Alloc rsi | | | | |I11a| | | | | | | 41.#52 I12 Def Alloc rdx | | |I12a| |I11a| | | | | | | 42.#53 rdx Fixd Keep rdx | | |I12a| |I11a| | | | | | | 42.#54 I12 Use * Keep rdx | | |I12i| |I11a| | | | | | | 43.#55 rdx Fixd Keep rdx | | | | |I11a| | | | | | | 43.#56 I13 Def Alloc rdx | | |I13a| |I11a| | | | | | | 45.#57 C14 Def Alloc rdi | | |I13a| |I11a|C14a| | | | | | 46.#58 C14 Use * Keep rdi | | |I13a| |I11a|C14i| | | | | | 47.#59 I15 Def Alloc rdi | | |I13a| |I11a|I15a| | | | | | 48.#60 rdi Fixd Keep rdi | | |I13a| |I11a|I15a| | | | | | 48.#61 I15 Use * Keep rdi | | |I13a| |I11a|I15i| | | | | | 49.#62 rdi Fixd Keep rdi | | |I13a| |I11a| | | | | | | 49.#63 I16 Def Alloc rdi | | |I13a| |I11a|I16a| | | | | | 50.#64 rsi Fixd Keep rsi | | |I13a| |I11a|I16a| | | | | | 50.#65 I11 Use * Keep rsi | | |I13a| |I11i|I16a| | | | | | 50.#66 rdx Fixd Keep rdx | | |I13a| | |I16a| | | | | | 50.#67 I13 Use * Keep rdx | | |I13i| | |I16a| | | | | | 50.#68 rdi Fixd Keep rdi | | | | | |I16a| | | | | | 50.#69 I16 Use * Keep rdi | | | | | |I16i| | | | | | 51.#70 rax Kill Keep rax | | | | | | | | | | | | 51.#71 rcx Kill Keep rcx | | | | | | | | | | | | 51.#72 rdx Kill Keep rdx | | | | | | | | | | | | 51.#73 rsi Kill Keep rsi | | | | | | | | | | | | 51.#74 rdi Kill Keep rdi | | | | | | | | | | | | 51.#75 r8 Kill Keep r8 | | | | | | | | | | | | 51.#76 r9 Kill Keep r9 | | | | | | | | | | | | 51.#77 r10 Kill Keep r10 | | | | | | | | | | | | 51.#78 r11 Kill Keep r11 | | | | | | | | | | | | 51.#79 rax Fixd Keep rax | | | | | | | | | | | | 51.#80 I17 Def Alloc rax |I17a| | | | | | | | | | | 52.#81 rdi Fixd Keep rdi |I17a| | | | | | | | | | | Move rdi | | | | | |I17i| | | | | | 53.#83 rdi Fixd Keep rdi | | | | | | | | | | | | 53.#84 I18 Def Alloc rdi | | | | | |I18a| | | | | | 54.#85 rdi Fixd Keep rdi | | | | | |I18a| | | | | | 54.#86 I18 Use * Keep rdi | | | | | |I18i| | | | | | 55.#87 rax Kill Keep rax | | | | | | | | | | | | 55.#88 rcx Kill Keep rcx | | | | | | | | | | | | 55.#89 rdx Kill Keep rdx | | | | | | | | | | | | 55.#90 rsi Kill Keep rsi | | | | | | | | | | | | 55.#91 rdi Kill Keep rdi | | | | | | | | | | | | 55.#92 r8 Kill Keep r8 | | | | | | | | | | | | 55.#93 r9 Kill Keep r9 | | | | | | | | | | | | 55.#94 r10 Kill Keep r10 | | | | | | | | | | | | 55.#95 r11 Kill Keep r11 | | | | | | | | | | | | 59.#96 I19 Def Alloc rsi | | | | |I19a| | | | | | | 62.#97 I19 Use * Keep rsi | | | | |I19i| | | | | | | 63.#98 I20 Def Alloc rsi | | | | |I20a| | | | | | | 64.#99 rsi Fixd Keep rsi | | | | |I20a| | | | | | | 64.#100 I20 Use * Keep rsi | | | | |I20i| | | | | | | 65.#101 rsi Fixd Keep rsi | | | | | | | | | | | | 65.#102 I21 Def Alloc rsi | | | | |I21a| | | | | | | 67.#103 C22 Def Alloc rdi | | | | |I21a|C22a| | | | | | 68.#104 C22 Use * Keep rdi | | | | |I21a|C22i| | | | | | 69.#105 I23 Def Alloc rdi | | | | |I21a|I23a| | | | | | 70.#106 rdi Fixd Keep rdi | | | | |I21a|I23a| | | | | | 70.#107 I23 Use * Keep rdi | | | | |I21a|I23i| | | | | | 71.#108 rdi Fixd Keep rdi | | | | |I21a| | | | | | | 71.#109 I24 Def Alloc rdi | | | | |I21a|I24a| | | | | | 73.#110 C25 Def Alloc rax |C25a| | | |I21a|I24a| | | | | | 76.#111 rsi Fixd Keep rsi |C25a| | | |I21a|I24a| | | | | | 76.#112 I21 Use * Keep rsi |C25a| | | |I21i|I24a| | | | | | 76.#113 rdi Fixd Keep rdi |C25a| | | | |I24a| | | | | | 76.#114 I24 Use * Keep rdi |C25a| | | | |I24i| | | | | | 76.#115 C25 Use * Keep rax |C25i| | | | | | | | | | | 77.#116 rax Kill Keep rax | | | | | | | | | | | | 77.#117 rcx Kill Keep rcx | | | | | | | | | | | | 77.#118 rdx Kill Keep rdx | | | | | | | | | | | | 77.#119 rsi Kill Keep rsi | | | | | | | | | | | | 77.#120 rdi Kill Keep rdi | | | | | | | | | | | | 77.#121 r8 Kill Keep r8 | | | | | | | | | | | | 77.#122 r9 Kill Keep r9 | | | | | | | | | | | | 77.#123 r10 Kill Keep r10 | | | | | | | | | | | | 77.#124 r11 Kill Keep r11 | | | | | | | | | | | | 77.#125 rax Fixd Keep rax | | | | | | | | | | | | 77.#126 I26 Def Alloc rax |I26a| | | | | | | | | | | 78.#127 I26 Use * Keep rax |I26i| | | | | | | | | | | 81.#128 I27 Def Alloc rdx | | |I27a| | | | | | | | | 84.#129 I27 Use * Keep rdx | | |I27i| | | | | | | | | 85.#130 I28 Def Alloc rdx | | |I28a| | | | | | | | | 88.#131 rdi Fixd Keep rdi | | |I28a| | | | | | | | | 88.#132 I29 Def Alloc rdi | | |I28a| | |I29a| | | | | | 88.#133 rcx Fixd Keep rcx | | |I28a| | |I29a| | | | | | 88.#134 I30 Def Alloc rcx | |I30a|I28a| | |I29a| | | | | | 88.#135 rsi Fixd Keep rsi | |I30a|I28a| | |I29a| | | | | | 88.#136 I31 Def Alloc rsi | |I30a|I28a| |I31a|I29a| | | | | | 88.#137 I28 Use * Keep rdx | |I30a|I28i| |I31a|I29a| | | | | | 88.#138 I29 Use * Keep rdi | |I30a| | |I31a|I29i| | | | | | 88.#139 I30 Use * Keep rcx | |I30i| | |I31a| | | | | | | 88.#140 I31 Use * Keep rsi | | | | |I31i| | | | | | | 91.#141 I32 Def Alloc rdi | | | | | |I32a| | | | | | 92.#142 rdi Fixd Keep rdi | | | | | |I32a| | | | | | 92.#143 I32 Use * Keep rdi | | | | | |I32i| | | | | | 93.#144 rdi Fixd Keep rdi | | | | | | | | | | | | 93.#145 I33 Def Alloc rdi | | | | | |I33a| | | | | | 95.#146 I34 Def Alloc rsi | | | | |I34a|I33a| | | | | | 96.#147 rsi Fixd Keep rsi | | | | |I34a|I33a| | | | | | 96.#148 I34 Use * Keep rsi | | | | |I34i|I33a| | | | | | 97.#149 rsi Fixd Keep rsi | | | | | |I33a| | | | | | 97.#150 I35 Def Alloc rsi | | | | |I35a|I33a| | | | | | 99.#151 I36 Def Alloc rdx | | |I36a| |I35a|I33a| | | | | | 100.#152 rdx Fixd Keep rdx | | |I36a| |I35a|I33a| | | | | | 100.#153 I36 Use * Keep rdx | | |I36i| |I35a|I33a| | | | | | 101.#154 rdx Fixd Keep rdx | | | | |I35a|I33a| | | | | | 101.#155 I37 Def Alloc rdx | | |I37a| |I35a|I33a| | | | | | 105.#156 r11 Fixd Keep r11 | | |I37a| |I35a|I33a| | | | | | 105.#157 C38 Def Alloc r11 | | |I37a| |I35a|I33a| | |C38a| | | 106.#158 r11 Fixd Keep r11 | | |I37a| |I35a|I33a| | |C38a| | | 106.#159 C38 Use * Keep r11 | | |I37a| |I35a|I33a| | |C38i| | | 107.#160 r11 Fixd Keep r11 | | |I37a| |I35a|I33a| | | | | | 107.#161 I39 Def Alloc r11 | | |I37a| |I35a|I33a| | |I39a| | | 109.#162 C40 Def Alloc rax |C40a| |I37a| |I35a|I33a| | |I39a| | | 112.#163 rdi Fixd Keep rdi |C40a| |I37a| |I35a|I33a| | |I39a| | | 112.#164 I33 Use * Keep rdi |C40a| |I37a| |I35a|I33i| | |I39a| | | 112.#165 rsi Fixd Keep rsi |C40a| |I37a| |I35a| | | |I39a| | | 112.#166 I35 Use * Keep rsi |C40a| |I37a| |I35i| | | |I39a| | | 112.#167 rdx Fixd Keep rdx |C40a| |I37a| | | | | |I39a| | | 112.#168 I37 Use * Keep rdx |C40a| |I37i| | | | | |I39a| | | 112.#169 r11 Fixd Keep r11 |C40a| | | | | | | |I39a| | | 112.#170 I39 Use * Keep r11 |C40a| | | | | | | |I39i| | | 112.#171 C40 Use * Keep rax |C40i| | | | | | | | | | | 113.#172 rax Kill Keep rax | | | | | | | | | | | | 113.#173 rcx Kill Keep rcx | | | | | | | | | | | | 113.#174 rdx Kill Keep rdx | | | | | | | | | | | | 113.#175 rsi Kill Keep rsi | | | | | | | | | | | | 113.#176 rdi Kill Keep rdi | | | | | | | | | | | | 113.#177 r8 Kill Keep r8 | | | | | | | | | | | | 113.#178 r9 Kill Keep r9 | | | | | | | | | | | | 113.#179 r10 Kill Keep r10 | | | | | | | | | | | | 113.#180 r11 Kill Keep r11 | | | | | | | | | | | | 113.#181 rax Fixd Keep rax | | | | | | | | | | | | 113.#182 I41 Def Alloc rax |I41a| | | | | | | | | | | 113.#183 rdx Fixd Keep rdx |I41a| | | | | | | | | | | 113.#184 I42 Def Alloc rdx |I41a| |I42a| | | | | | | | | 114.#185 I41 Use * Keep rax |I41i| |I42a| | | | | | | | | 114.#186 I42 Use * Keep rdx | | |I42i| | | | | | | | | Recording the maximum number of concurrent spills: ---------- LSRA Stats ---------- BB01 [ 100]: SpillCount = 0, ResolutionMovs = 0, SplitEdges = 0, CopyReg = 1 Total Tracked Vars: 0 Total Reg Cand Vars: 0 Total number of Intervals: 42 Total number of RefPositions: 186 Total Spill Count: 0 Weighted: 0 Total CopyReg Count: 1 Weighted: 100 Total ResolutionMov Count: 0 Weighted: 0 Total number of split edges: 0 Total Number of spill temps created: 0 TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS Incoming Parameters: BB01 [000..042) (return), preds={} succs={} ===== N002. IL_OFFSET IL offset: 0x0 N004. rdi = CNS_INT(h) 0x7f6678c127f0 class N006. rdi = PUTARG_REG; rdi N008. rax = CALL help; rdi N010. V03 MEM; rax N012. rdi = V03 MEM N014. STK = LEA(b+8) ; rdi N016. rax = V01 MEM N018. STOREIND ; STK,rax N020. rdi = CNS_INT(h) 0x7f6678beb1c0 class N022. rdi = PUTARG_REG; rdi N024. rax = CALL help; rdi N026. V04 MEM; rax N028. rsi = V04 MEM N030. STK = LEA(b+8) ; rsi N032. rdx = V01 MEM N034. STOREIND ; STK,rdx N036. rsi = V03 MEM N038. rsi = PUTARG_REG; rsi N040. rdx = V04 MEM N042. rdx = PUTARG_REG; rdx N044. rdi = CNS_INT(h) 0x64008A98 [ICON_STR_HDL] N046. rdi = IND ; rdi N048. rdi = PUTARG_REG; rdi N050. rax = CALL ; rsi,rdx,rdi N000. rdi = COPY ; rax N052. rdi = PUTARG_REG; rdi N054. CALL ; rdi N056. IL_OFFSET IL offset: 0x25 N058. rsi = V00 MEM N060. STK = LEA(b+16); rsi N062. rsi = IND ; STK N064. rsi = PUTARG_REG; rsi N066. rdi = CNS_INT(h) 0x7f6664004668 static Fseq[s_NetworkInterfaces] N068. rdi = IND ; rdi N070. rdi = PUTARG_REG; rdi N072. rax = CNS_INT(h) 0x7f6678eeddf8 ftn N074. STK = IND ; rax N076. rax = CALL nullcheck; rsi,rdi,STK N078. V06 MEM; rax N080. rdx = V00 MEM N082. CNS_INT 56 field offset Fseq[m_ParallelSendQueue] N084. rdx = ADD ; rdx N086. STK = OBJ ; rdx N088. PUTARG_STK [+0x00]; STK N090. rdi = V06 MEM N092. rdi = PUTARG_REG; rdi N094. rsi = V01 MEM N096. rsi = PUTARG_REG; rsi N098. rdx = V01 MEM N100. rdx = PUTARG_REG; rdx N102. STK = FIELD_LIST; rsi,rdx N104. r11 = CNS_INT(h) 0x7f6678060338 ftn N106. r11 = PUTARG_REG; r11 N108. rax = CNS_INT(h) 0x7f6678060338 ftn N110. STK = IND ; rax N112. rax,rdx = CALLV stub; rdi,STK,r11,STK N114. V05 MEM; rax,rdx N116. V05 MEM N118. RETURN *************** Finishing PHASE Linear scan register alloc *************** In genGenerateCode() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Generate code *************** In fgDebugCheckBBlist Finalizing stack frame Modified regs: [rax rcx rdx rsi rdi r8-r11] Callee-saved registers pushed: 0 [] *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT) Assign V00 this, size=8, stkOffs=-0x18 Assign V01 arg1, size=16, stkOffs=-0x28 Assign V03 tmp1, size=8, stkOffs=-0x30 Assign V04 tmp2, size=8, stkOffs=-0x38 Assign V05 tmp3, size=16, stkOffs=-0x48 Assign V06 tmp4, size=8, stkOffs=-0x50 Assign V02 OutArgs, size=56, stkOffs=-0x88 --- delta bump 8 for RA --- delta bump 8 for FP --- delta bump 0 for RBP frame --- virtual stack offset to actual stack offset delta is 16 -- V00 was -24, now -8 -- V01 was -40, now -24 -- V02 was -136, now -120 -- V03 was -48, now -32 -- V04 was -56, now -40 -- V05 was -72, now -56 -- V06 was -80, now -64 ; Final local variable assignments ; ; V00 this [V00 ] ( 1, 1 ) byref -> [rbp-0x08] this ; V01 arg1 [V01 ] ( 1, 1 ) struct (16) [rbp-0x18] do-not-enreg[SFA] multireg-arg ; V02 OutArgs [V02 ] ( 1, 1 ) lclBlk (56) [rsp+0x00] "OutgoingArgSpace" ; V03 tmp1 [V03 ] ( 1, 1 ) ref -> [rbp-0x20] must-init "Reusable Box Helper" ; V04 tmp2 [V04 ] ( 1, 1 ) ref -> [rbp-0x28] must-init "Reusable Box Helper" ; V05 tmp3 [V05 ] ( 1, 1 ) struct (16) [rbp-0x38] multireg-ret "Return value temp for multireg return" ; V06 tmp4 [V06 ] ( 1, 1 ) ref -> [rbp-0x40] must-init "argument with side effect" ; ; Lcl frame size = 128 Setting stack level from -572662307 to 0 =============== Generating BB01 [000..042) (return), preds={} succs={} flags=0x00000004.408b0020: i label target hascall gcsafe newobj LIR BB01 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} + ByrefExposed + GcHeap Liveness not changing: {} Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M63542_BB01: Label: IG02, GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Scope info: begin block BB01, IL range [000..042) Scope info: opening scope, LVnum=0 [000..042) Scope info: >> new scope, VarNum=0, tracked? no, VarIndex=0, bbLiveIn= {} Scope info: opening scope, LVnum=1 [000..042) Scope info: >> new scope, VarNum=1, tracked? no, VarIndex=0, bbLiveIn= {} Scope info: open scopes = 0 (V00 this) [000..042) 1 (V01 arg1) [000..042) Added IP mapping: 0x0000 STACK_EMPTY (G_M63542_IG02,ins#0,ofs#0) label Generating: N002 (???,???) [000072] ------------ IL_OFFSET void IL offset: 0x0 REG NA Generating: N004 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class REG rdi IN0001: mov rdi, 0x7F6678C127F0 /--* t4 long Generating: N006 (???,???) [000076] ------------ t76 = * PUTARG_REG long REG rdi /--* t76 long arg0 in rdi Generating: N008 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG rax Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0002: call CORINFO_HELP_NEWSFAST GC regs: 00000000 {} => 00000001 {rax} /--* t5 ref Generating: N010 ( 20, 19) [000007] DA---------- * STORE_LCL_VAR ref V03 tmp1 NA REG NA GC regs: 00000001 {rax} => 00000000 {} IN0003: mov gword ptr [V03 rbp-20H], rax Generating: N012 ( 3, 2) [000008] ------------ t8 = LCL_VAR ref V03 tmp1 rdi REG rdi IN0004: mov rdi, gword ptr [V03 rbp-20H] GC regs: 00000000 {} => 00000080 {rdi} /--* t8 ref Generating: N014 ( 4, 3) [000010] -c---------- t10 = * LEA(b+8) byref REG NA Generating: N016 ( 3, 4) [000003] ------------ t3 = LCL_FLD long V01 arg1 [+0] Fseq[JobGroup] rax REG rax IN0005: mov rax, qword ptr [V01 rbp-18H] /--* t10 byref +--* t3 long Generating: N018 (???,???) [000073] -A-XG------- * STOREIND long REG NA GC regs: 00000080 {rdi} => 00000000 {} IN0006: mov qword ptr [rdi+8], rax Generating: N020 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class REG rdi IN0007: mov rdi, 0x7F6678BEB1C0 /--* t18 long Generating: N022 (???,???) [000077] ------------ t77 = * PUTARG_REG long REG rdi /--* t77 long arg0 in rdi Generating: N024 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG rax Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0008: call CORINFO_HELP_NEWSFAST GC regs: 00000000 {} => 00000001 {rax} /--* t19 ref Generating: N026 ( 20, 19) [000021] DA---------- * STORE_LCL_VAR ref V04 tmp2 NA REG NA GC regs: 00000001 {rax} => 00000000 {} IN0009: mov gword ptr [V04 rbp-28H], rax Generating: N028 ( 3, 2) [000022] ------------ t22 = LCL_VAR ref V04 tmp2 rsi REG rsi IN000a: mov rsi, gword ptr [V04 rbp-28H] GC regs: 00000000 {} => 00000040 {rsi} /--* t22 ref Generating: N030 ( 4, 3) [000024] -c---------- t24 = * LEA(b+8) byref REG NA Generating: N032 ( 3, 4) [000017] ------------ t17 = LCL_FLD int V01 arg1 [+8] Fseq[Version] rdx REG rdx IN000b: mov edx, dword ptr [V01+0x8 rbp-10H] /--* t24 byref +--* t17 int Generating: N034 (???,???) [000074] -A-XG------- * STOREIND int REG NA GC regs: 00000040 {rsi} => 00000000 {} IN000c: mov dword ptr [rsi+8], edx Generating: N036 ( 3, 2) [000013] ------------ t13 = LCL_VAR ref V03 tmp1 rsi REG rsi IN000d: mov rsi, gword ptr [V03 rbp-20H] GC regs: 00000000 {} => 00000040 {rsi} /--* t13 ref Generating: N038 (???,???) [000078] ------------ t78 = * PUTARG_REG ref REG rsi GC regs: 00000040 {rsi} => 00000000 {} GC regs: 00000000 {} => 00000040 {rsi} Generating: N040 ( 3, 2) [000027] ------------ t27 = LCL_VAR ref V04 tmp2 rdx REG rdx IN000e: mov rdx, gword ptr [V04 rbp-28H] GC regs: 00000040 {rsi} => 00000044 {rdx rsi} /--* t27 ref Generating: N042 (???,???) [000079] ------------ t79 = * PUTARG_REG ref REG rdx GC regs: 00000044 {rdx rsi} => 00000040 {rsi} GC regs: 00000040 {rsi} => 00000044 {rdx rsi} Generating: N044 ( 2, 10) [000050] ------------ t50 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] REG rdi IN000f: mov rdi, 0x7F6664008A98 /--* t50 long Generating: N046 ( 4, 12) [000051] n---G------- t51 = * IND ref REG rdi IN0010: mov rdi, gword ptr [rdi] GC regs: 00000044 {rdx rsi} => 000000C4 {rdx rsi rdi} /--* t51 ref Generating: N048 (???,???) [000080] ----G------- t80 = * PUTARG_REG ref REG rdi GC regs: 000000C4 {rdx rsi rdi} => 00000044 {rdx rsi} GC regs: 00000044 {rdx rsi} => 000000C4 {rdx rsi rdi} /--* t78 ref arg1 in rsi +--* t79 ref arg2 in rdx +--* t80 ref arg0 in rdi Generating: N050 ( 36, 32) [000029] --CXG------- t29 = * CALL ref System.String.Format REG rax GC regs: 000000C4 {rdx rsi rdi} => 00000084 {rdx rdi} GC regs: 00000084 {rdx rdi} => 00000080 {rdi} GC regs: 00000080 {rdi} => 00000000 {} Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0011: call System.String:Format(System.String,System.Object,System.Object):System.String GC regs: 00000000 {} => 00000001 {rax} /--* t29 ref Generating: [000093] --CXG------- t93 = * COPY ref REG rdi,NA /--* t93 ref Generating: N052 (???,???) [000081] --CXG------- t81 = * PUTARG_REG ref REG rdi GC regs: 00000001 {rax} => 00000000 {} IN0012: mov rdi, rax GC regs: 00000000 {} => 00000080 {rdi} GC regs: 00000080 {rdi} => 00000000 {} GC regs: 00000000 {} => 00000080 {rdi} /--* t81 ref arg0 in rdi Generating: N054 ( 50, 38) [000030] --CXG------- * CALL void UnityEngine.Debug.Log REG NA GC regs: 00000080 {rdi} => 00000000 {} Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0013: call UnityEngine.Debug:Log(System.Object) Added IP mapping: 0x0025 STACK_EMPTY (G_M63542_IG02,ins#19,ofs#94) Generating: N056 (???,???) [000075] ------------ IL_OFFSET void IL offset: 0x25 REG NA Generating: N058 ( 3, 2) [000032] ------------ t32 = LCL_VAR byref V00 this rsi REG rsi IN0014: mov rsi, bword ptr [V00 rbp-08H] Byref regs: 00000000 {} => 00000040 {rsi} /--* t32 byref Generating: N060 ( 4, 3) [000059] -c---------- t59 = * LEA(b+16) byref REG NA /--* t59 byref Generating: N062 ( 6, 5) [000033] *--XG------- t33 = * IND int REG rsi Byref regs: 00000040 {rsi} => 00000000 {} IN0015: mov esi, dword ptr [rsi+16] /--* t33 int Generating: N064 (???,???) [000082] ---XG------- t82 = * PUTARG_REG int REG rsi Generating: N066 ( 2, 10) [000057] ------------ t57 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] REG rdi IN0016: mov rdi, 0x7F6664004668 /--* t57 long Generating: N068 ( 4, 12) [000031] n---G------- t31 = * IND ref REG rdi IN0017: mov rdi, gword ptr [rdi] GC regs: 00000000 {} => 00000080 {rdi} /--* t31 ref Generating: N070 (???,???) [000083] ----G------- t83 = * PUTARG_REG ref REG rdi GC regs: 00000080 {rdi} => 00000000 {} GC regs: 00000000 {} => 00000080 {rdi} Generating: N072 ( 2, 10) [000084] ------------ t84 = CNS_INT(h) long 0x7f6678eeddf8 ftn REG rax IN0018: mov rax, 0x7F6678EEDDF8 /--* t84 long Generating: N074 ( 4, 12) [000085] -c---------- t85 = * IND long REG NA /--* t82 int arg1 in rsi +--* t83 ref this in rdi +--* t85 long control expr Generating: N076 ( 24, 25) [000034] --CXG------- t34 = * CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item REG rax GC regs: 00000080 {rdi} => 00000000 {} IN0019: cmp dword ptr [rdi], edi Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN001a: call gword ptr [rax]System.Collections.Generic.List`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this GC regs: 00000000 {} => 00000001 {rax} /--* t34 ref Generating: N078 ( 28, 28) [000065] DA-XG-----L- * STORE_LCL_VAR ref V06 tmp4 NA REG NA GC regs: 00000001 {rax} => 00000000 {} IN001b: mov gword ptr [V06 rbp-40H], rax Generating: N080 ( 3, 2) [000035] ------------ t35 = LCL_VAR byref V00 this rdx REG rdx IN001c: mov rdx, bword ptr [V00 rbp-08H] Byref regs: 00000000 {} => 00000004 {rdx} Generating: N082 ( 1, 1) [000062] -c---------- t62 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] REG NA /--* t35 byref +--* t62 long Generating: N084 ( 5, 4) [000063] ------------ t63 = * ADD byref REG rdx Byref regs: 00000004 {rdx} => 00000000 {} IN001d: add rdx, 56 Byref regs: 00000000 {} => 00000004 {rdx} /--* t63 byref Generating: N086 ( 11, 8) [000042] -c-XG------- t42 = * OBJ struct REG NA /--* t42 struct Generating: N088 (???,???) [000086] ---XG------- * PUTARG_STK [+0x00] void (7 slots) (RepInstr) REG NA Byref regs: 00000004 {rdx} => 00000000 {} IN001e: lea rdi, [V02 rsp] IN001f: mov rsi, rdx IN0020: mov rcx, gword ptr [rsi] IN0021: mov gword ptr [V02 rsp], rcx IN0022: add rsi, 8 IN0023: add rdi, 8 IN0024: mov ecx, 6 IN0025: rep movsq Generating: N090 ( 3, 2) [000066] ------------ t66 = LCL_VAR ref V06 tmp4 rdi REG rdi IN0026: mov rdi, gword ptr [V06 rbp-40H] GC regs: 00000000 {} => 00000080 {rdi} /--* t66 ref Generating: N092 (???,???) [000087] ------------ t87 = * PUTARG_REG ref REG rdi GC regs: 00000080 {rdi} => 00000000 {} GC regs: 00000000 {} => 00000080 {rdi} Generating: N094 ( 3, 4) [000070] ------------ t70 = LCL_FLD long V01 arg1 [+0] rsi REG rsi IN0027: mov rsi, qword ptr [V01 rbp-18H] /--* t70 long Generating: N096 (???,???) [000088] ------------ t88 = * PUTARG_REG long REG rsi Generating: N098 ( 3, 4) [000071] ------------ t71 = LCL_FLD long V01 arg1 [+8] rdx REG rdx IN0028: mov rdx, qword ptr [V01+0x8 rbp-10H] /--* t71 long Generating: N100 (???,???) [000089] ------------ t89 = * PUTARG_REG long REG rdx /--* t88 long +--* t89 long Generating: N102 ( 6, 8) [000069] -c---------- t69 = * FIELD_LIST struct REG NA Generating: N104 ( 2, 10) [000056] ------------ t56 = CNS_INT(h) long 0x7f6678060338 ftn REG r11 IN0029: mov r11, 0x7F6678060338 /--* t56 long Generating: N106 (???,???) [000090] ------------ t90 = * PUTARG_REG long REG r11 Generating: N108 ( 2, 10) [000091] ------------ t91 = CNS_INT(h) long 0x7f6678060338 ftn REG rax IN002a: mov rax, 0x7F6678060338 /--* t91 long Generating: N110 ( 4, 12) [000092] -c---------- t92 = * IND long REG NA /--* t87 ref this in rdi +--* t69 struct arg3 rsi,rdx +--* t90 long arg1 in r11 +--* t92 long control expr Generating: N112 ( 73, 67) [000038] --CXG------- t38 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend REG rax,rdx GC regs: 00000080 {rdi} => 00000000 {} Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN002b: call qword ptr [rax]Unity.Networking.Transport.INetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this /--* t38 struct Generating: N114 ( 77, 70) [000045] DA-XG------- * STORE_LCL_VAR struct V05 tmp3 NA REG NA IN002c: mov qword ptr [V05 rbp-38H], rax IN002d: mov qword ptr [V05+0x8 rbp-30H], rdx Generating: N116 ( 3, 2) [000046] -c-----N---- t46 = LCL_VAR struct V05 tmp3 NA REG NA /--* t46 struct Generating: N118 ( 4, 3) [000047] ------------ * RETURN struct REG NA **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 IN002e: mov rax, qword ptr [V05 rbp-38H] IN002f: mov rdx, qword ptr [V05+0x8 rbp-30H] Scope info: end block BB01, IL range [000..042) Scope info: ending scope, LVnum=0 [000..042) Scope info: ending scope, LVnum=1 [000..042) Scope info: open scopes = Added IP mapping: EPILOG STACK_EMPTY (G_M63542_IG02,ins#47,ofs#220) label Reserving epilog IG for block BB01 G_M63542_IG02: ; offs=000000H, funclet=00, bbWeight=1 *************** After placeholder IG creation G_M63542_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M63542_IG02: ; offs=000000H, size=00DCH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M63542_IG03: ; epilog placeholder, next placeholder=, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder ; PrevGCVars= {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {} ; InitGCVars= {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} Liveness not changing: {} # compCycleEstimate = 191, compSizeEstimate = 169 Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this ; Final local variable assignments ; ; V00 this [V00 ] ( 1, 1 ) byref -> [rbp-0x08] this ; V01 arg1 [V01 ] ( 1, 1 ) struct (16) [rbp-0x18] do-not-enreg[SFA] multireg-arg ; V02 OutArgs [V02 ] ( 1, 1 ) lclBlk (56) [rsp+0x00] "OutgoingArgSpace" ; V03 tmp1 [V03 ] ( 1, 1 ) ref -> [rbp-0x20] must-init "Reusable Box Helper" ; V04 tmp2 [V04 ] ( 1, 1 ) ref -> [rbp-0x28] must-init "Reusable Box Helper" ; V05 tmp3 [V05 ] ( 1, 1 ) struct (16) [rbp-0x38] multireg-ret "Return value temp for multireg return" ; V06 tmp4 [V06 ] ( 1, 1 ) ref -> [rbp-0x40] must-init "argument with side effect" ; ; Lcl frame size = 128 *************** Before prolog / epilog generation G_M63542_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M63542_IG02: ; offs=000000H, size=00DCH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M63542_IG03: ; epilog placeholder, next placeholder=, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder ; PrevGCVars= {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {} ; InitGCVars= {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} *************** In genFnProlog() Added IP mapping to front: PROLOG STACK_EMPTY (G_M63542_IG01,ins#0,ofs#0) label __prolog: **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 Found 6 lvMustInit int-sized stack slots, frame offsets 64 through 24 IN0030: push rbp IN0031: sub rsp, 128 IN0032: lea rbp, [rsp+80H] Notify VM instruction set (AVX2) must be supported. IN0033: vxorps xmm8, xmm8 IN0034: vmovdqa xmmword ptr [rbp-40H], xmm8 IN0035: vmovdqa xmmword ptr [rbp-30H], xmm8 IN0036: xor rax, rax IN0037: mov qword ptr [rbp-20H], rax *************** In genClearStackVec3ArgUpperBits() *************** In genFnPrologCalleeRegArgs() for int regs **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 IN0038: mov bword ptr [V00 rbp-08H], rdi IN0039: mov qword ptr [V01 rbp-18H], rsi IN003a: mov qword ptr [V01+0x8 rbp-10H], rdx *************** In genEnregisterIncomingStackArgs() G_M63542_IG01: ; offs=000000H, funclet=00, bbWeight=1 *************** In genFnEpilog() __epilog: gcVarPtrSetCur= {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {} IN003b: lea rsp, [rbp] IN003c: pop rbp IN003d: ret G_M63542_IG03: ; offs=0000DCH, funclet=00, bbWeight=1 0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs *************** After prolog / epilog generation G_M63542_IG01: ; func=00, offs=000000H, size=0033H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG G_M63542_IG02: ; offs=000033H, size=00DCH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref G_M63542_IG03: ; offs=00010FH, size=0006H, epilog, nogc, extend *************** In emitJumpDistBind() *************** Finishing PHASE Generate code *************** Starting PHASE Emit code Hot code size = 0x115 bytes Cold code size = 0x0 bytes reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0x8) *************** In emitEndCodeGen() Converting emitMaxStackDepth from bytes (0) to elements (0) *************************************************************************** Instructions as they come out of the scheduler G_M63542_IG01: ; func=00, offs=000000H, size=0033H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG IN0030: 000000 55 push rbp IN0031: 000001 4881EC80000000 sub rsp, 128 IN0032: 000008 488DAC2480000000 lea rbp, [rsp+80H] IN0033: 000010 C4413857C0 vxorps xmm8, xmm8 IN0034: 000015 C5797F45C0 vmovdqa xmmword ptr [rbp-40H], xmm8 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN0035: 00001A C5797F45D0 vmovdqa xmmword ptr [rbp-30H], xmm8 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN0036: 00001F 33C0 xor rax, rax IN0037: 000021 488945E0 mov qword ptr [rbp-20H], rax IN0038: 000025 48897DF8 mov bword ptr [rbp-08H], rdi IN0039: 000029 488975E8 mov qword ptr [rbp-18H], rsi IN003a: 00002D 488955F0 mov qword ptr [rbp-10H], rdx ;; bbWeight=1 PerfScore 8.33 G_M63542_IG02: ; func=00, offs=000033H, size=00DCH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref Block predicted offs = 00000033, actual = 00000031 -> size adj = 2 IN0001: 000031 48BFF027C178667F0000 mov rdi, 0x7F6678C127F0 New gcrReg live regs=00000001 {rax} ; Call at 003B [stk=0], GCvars=none, gcrefRegs=00000001 {rax}, byrefRegs=00000000 {} IN0002: 00003B E89078DF77 call CORINFO_HELP_NEWSFAST IN0003: 000040 488945E0 mov gword ptr [rbp-20H], rax gcrReg +[rdi] IN0004: 000044 488B7DE0 mov rdi, gword ptr [rbp-20H] gcrReg -[rax] IN0005: 000048 488B45E8 mov rax, qword ptr [rbp-18H] IN0006: 00004C 48894708 mov qword ptr [rdi+8], rax gcrReg -[rdi] IN0007: 000050 48BFC0B1BE78667F0000 mov rdi, 0x7F6678BEB1C0 New gcrReg live regs=00000001 {rax} ; Call at 005A [stk=0], GCvars=none, gcrefRegs=00000001 {rax}, byrefRegs=00000000 {} IN0008: 00005A E87178DF77 call CORINFO_HELP_NEWSFAST IN0009: 00005F 488945D8 mov gword ptr [rbp-28H], rax gcrReg +[rsi] IN000a: 000063 488B75D8 mov rsi, gword ptr [rbp-28H] IN000b: 000067 8B55F0 mov edx, dword ptr [rbp-10H] IN000c: 00006A 895608 mov dword ptr [rsi+8], edx IN000d: 00006D 488B75E0 mov rsi, gword ptr [rbp-20H] gcrReg +[rdx] IN000e: 000071 488B55D8 mov rdx, gword ptr [rbp-28H] IN000f: 000075 48BF988A0064667F0000 mov rdi, 0x7F6664008A98 gcrReg +[rdi] IN0010: 00007F 488B3F mov rdi, gword ptr [rdi] New gcrReg live regs=00000001 {rax} ; Call at 0082 [stk=0], GCvars=none, gcrefRegs=00000001 {rax}, byrefRegs=00000000 {} IN0011: 000082 E8C93CA2FE call System.String:Format(System.String,System.Object,System.Object):System.String gcrReg +[rdi] IN0012: 000087 488BF8 mov rdi, rax New gcrReg live regs=00000000 {} ; Call at 008A [stk=0], GCvars=none, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0013: 00008A E8212946FF call UnityEngine.Debug:Log(System.Object) byrReg +[rsi] IN0014: 00008F 488B75F8 mov rsi, bword ptr [rbp-08H] byrReg -[rsi] IN0015: 000093 8B7610 mov esi, dword ptr [rsi+16] IN0016: 000096 48BF68460064667F0000 mov rdi, 0x7F6664004668 gcrReg +[rdi] IN0017: 0000A0 488B3F mov rdi, gword ptr [rdi] IN0018: 0000A3 48B8F8DDEE78667F0000 mov rax, 0x7F6678EEDDF8 IN0019: 0000AD 393F cmp dword ptr [rdi], edi New gcrReg live regs=00000001 {rax} ; Call at 00AF [stk=0], GCvars=none, gcrefRegs=00000001 {rax}, byrefRegs=00000000 {} IN001a: 0000AF FF10 call gword ptr [rax]System.Collections.Generic.List`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this IN001b: 0000B1 488945C0 mov gword ptr [rbp-40H], rax byrReg +[rdx] IN001c: 0000B5 488B55F8 mov rdx, bword ptr [rbp-08H] IN001d: 0000B9 4883C238 add rdx, 56 IN001e: 0000BD 488D3C24 lea rdi, [rsp] byrReg +[rsi] IN001f: 0000C1 488BF2 mov rsi, rdx gcrReg +[rcx] IN0020: 0000C4 488B0E mov rcx, gword ptr [rsi] IN0021: 0000C7 48890C24 mov gword ptr [rsp], rcx IN0022: 0000CB 4883C608 add rsi, 8 IN0023: 0000CF 4883C708 add rdi, 8 gcrReg -[rcx] IN0024: 0000D3 B906000000 mov ecx, 6 IN0025: 0000D8 F348A5 rep movsq gcrReg +[rdi] IN0026: 0000DB 488B7DC0 mov rdi, gword ptr [rbp-40H] byrReg -[rsi] IN0027: 0000DF 488B75E8 mov rsi, qword ptr [rbp-18H] byrReg -[rdx] IN0028: 0000E3 488B55F0 mov rdx, qword ptr [rbp-10H] IN0029: 0000E7 49BB38030678667F0000 mov r11, 0x7F6678060338 gcrReg -[rax] IN002a: 0000F1 48B838030678667F0000 mov rax, 0x7F6678060338 New gcrReg live regs=00000000 {} ; Call at 00FB [stk=0], GCvars=none, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN002b: 0000FB FF10 call qword ptr [rax]Unity.Networking.Transport.INetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this IN002c: 0000FD 488945C8 mov qword ptr [rbp-38H], rax IN002d: 000101 488955D0 mov qword ptr [rbp-30H], rdx IN002e: 000105 488B45C8 mov rax, qword ptr [rbp-38H] IN002f: 000109 488B55D0 mov rdx, qword ptr [rbp-30H] ;; bbWeight=1 PerfScore 69.75 G_M63542_IG03: ; func=00, offs=00010FH, size=0006H, epilog, nogc, extend Block predicted offs = 0000010F, actual = 0000010D -> size adj = 2 IN003b: 00010D 488D6500 lea rsp, [rbp] IN003c: 000111 5D pop rbp IN003d: 000112 C3 ret ;; bbWeight=1 PerfScore 2.00Allocated method code size = 277 , actual size = 275 ; Total bytes of code 275, prolog size 37, PerfScore 107.78, (MethodHash=853e07c9) for method Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this ; ============================================================ *************** After end code gen, before unwindEmit() G_M63542_IG01: ; func=00, offs=000000H, size=0031H, bbWeight=1 PerfScore 8.33, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc, isz <-- Prolog IG IN0030: 000000 push rbp IN0031: 000001 sub rsp, 128 IN0032: 000008 lea rbp, [rsp+80H] IN0033: 000010 vxorps xmm8, xmm8 IN0034: 000015 vmovdqa xmmword ptr [rbp-40H], xmm8 IN0035: 00001A vmovdqa xmmword ptr [rbp-30H], xmm8 IN0036: 00001F xor rax, rax IN0037: 000021 mov qword ptr [rbp-20H], rax IN0038: 000025 mov bword ptr [V00 rbp-08H], rdi IN0039: 000029 mov qword ptr [V01 rbp-18H], rsi IN003a: 00002D mov qword ptr [V01+0x8 rbp-10H], rdx G_M63542_IG02: ; offs=000031H, size=00DCH, bbWeight=1 PerfScore 69.75, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref IN0001: 000031 mov rdi, 0x7F6678C127F0 IN0002: 00003B call CORINFO_HELP_NEWSFAST IN0003: 000040 mov gword ptr [V03 rbp-20H], rax IN0004: 000044 mov rdi, gword ptr [V03 rbp-20H] IN0005: 000048 mov rax, qword ptr [V01 rbp-18H] IN0006: 00004C mov qword ptr [rdi+8], rax IN0007: 000050 mov rdi, 0x7F6678BEB1C0 IN0008: 00005A call CORINFO_HELP_NEWSFAST IN0009: 00005F mov gword ptr [V04 rbp-28H], rax IN000a: 000063 mov rsi, gword ptr [V04 rbp-28H] IN000b: 000067 mov edx, dword ptr [V01+0x8 rbp-10H] IN000c: 00006A mov dword ptr [rsi+8], edx IN000d: 00006D mov rsi, gword ptr [V03 rbp-20H] IN000e: 000071 mov rdx, gword ptr [V04 rbp-28H] IN000f: 000075 mov rdi, 0x7F6664008A98 IN0010: 00007F mov rdi, gword ptr [rdi] IN0011: 000082 call System.String:Format(System.String,System.Object,System.Object):System.String IN0012: 000087 mov rdi, rax IN0013: 00008A call UnityEngine.Debug:Log(System.Object) IN0014: 00008F mov rsi, bword ptr [V00 rbp-08H] IN0015: 000093 mov esi, dword ptr [rsi+16] IN0016: 000096 mov rdi, 0x7F6664004668 IN0017: 0000A0 mov rdi, gword ptr [rdi] IN0018: 0000A3 mov rax, 0x7F6678EEDDF8 IN0019: 0000AD cmp dword ptr [rdi], edi IN001a: 0000AF call gword ptr [rax]System.Collections.Generic.List`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this IN001b: 0000B1 mov gword ptr [V06 rbp-40H], rax IN001c: 0000B5 mov rdx, bword ptr [V00 rbp-08H] IN001d: 0000B9 add rdx, 56 IN001e: 0000BD lea rdi, [V02 rsp] IN001f: 0000C1 mov rsi, rdx IN0020: 0000C4 mov rcx, gword ptr [rsi] IN0021: 0000C7 mov gword ptr [V02 rsp], rcx IN0022: 0000CB add rsi, 8 IN0023: 0000CF add rdi, 8 IN0024: 0000D3 mov ecx, 6 IN0025: 0000D8 rep movsq IN0026: 0000DB mov rdi, gword ptr [V06 rbp-40H] IN0027: 0000DF mov rsi, qword ptr [V01 rbp-18H] IN0028: 0000E3 mov rdx, qword ptr [V01+0x8 rbp-10H] IN0029: 0000E7 mov r11, 0x7F6678060338 IN002a: 0000F1 mov rax, 0x7F6678060338 IN002b: 0000FB call qword ptr [rax]Unity.Networking.Transport.INetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this IN002c: 0000FD mov qword ptr [V05 rbp-38H], rax IN002d: 000101 mov qword ptr [V05+0x8 rbp-30H], rdx IN002e: 000105 mov rax, qword ptr [V05 rbp-38H] IN002f: 000109 mov rdx, qword ptr [V05+0x8 rbp-30H] G_M63542_IG03: ; offs=00010DH, size=0006H, bbWeight=1 PerfScore 2.00, epilog, nogc, extend IN003b: 00010D lea rsp, [rbp] IN003c: 000111 pop rbp IN003d: 000112 ret *************** Finishing PHASE Emit code *************** Starting PHASE Emit GC+EH tables Unwind Info: >> Start offset : 0x000000 (not in unwind data) >> End offset : 0x000113 (not in unwind data) Version : 1 Flags : 0x00 SizeOfProlog : 0x08 CountOfUnwindCodes: 2 FrameRegister : none (0) FrameOffset : N/A (no FrameRegister) (Value=0) UnwindCodes : CodeOffset: 0x08 UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 15 * 8 + 8 = 128 = 0x80 CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5) allocUnwindInfo(pHotCode=0x00007F667A121990, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x113, unwindSize=0x8, pUnwindBlock=0x0000559EA667E620, funKind=0 (main function)) *************** In genIPmappingGen() IP mapping count : 4 IL offs PROLOG : 0x00000000 ( STACK_EMPTY ) IL offs 0x0000 : 0x00000031 ( STACK_EMPTY ) IL offs 0x0025 : 0x0000008F ( STACK_EMPTY ) IL offs EPILOG : 0x0000010D ( STACK_EMPTY ) *************** In genSetScopeInfo() VarLocInfo count is 4 *************** Variable debug info 4 live ranges 0( UNKNOWN) : From 00000000h to 00000031h, in rdi 1( UNKNOWN) : From 00000000h to 00000031h, in rsi 0( UNKNOWN) : From 00000031h to 0000010Dh, in rbp[-8] (1 slot) 1( UNKNOWN) : From 00000031h to 0000010Dh, in rbp[-24] (1 slot) *************** In gcInfoBlockHdrSave() Set code length to 275. **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 Set ReturnKind to Scalar. Set stack base register to rbp. Set Outgoing stack arg area size to 56. Stack slot id for offset -8 (0xfffffff8) (frame) (byref, untracked) = 0. Stack slot id for offset -32 (0xffffffe0) (frame) (untracked) = 1. Stack slot id for offset -40 (0xffffffd8) (frame) (untracked) = 2. Stack slot id for offset -64 (0xffffffc0) (frame) (untracked) = 3. Defining 0 call sites: *************** Finishing PHASE Emit GC+EH tables Method code size: 275 Allocations for Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this (MethodHash=853e07c9) count: 769, size: 61759, max = 2368 allocateMemory: 65536, nraUsed: 64224 Alloc'd bytes by kind: kind | size | pct ---------------------+------------+-------- AssertionProp | 0 | 0.00% ASTNode | 13272 | 21.49% InstDesc | 6064 | 9.82% ImpStack | 384 | 0.62% BasicBlock | 856 | 1.39% fgArgInfo | 864 | 1.40% fgArgInfoPtrArr | 192 | 0.31% FlowList | 0 | 0.00% TreeStatementList | 0 | 0.00% SiScope | 272 | 0.44% DominatorMemory | 0 | 0.00% LSRA | 2728 | 4.42% LSRA_Interval | 3440 | 5.57% LSRA_RefPosition | 11968 | 19.38% Reachability | 0 | 0.00% SSA | 0 | 0.00% ValueNumber | 0 | 0.00% LvaTable | 1920 | 3.11% UnwindInfo | 0 | 0.00% hashBv | 40 | 0.06% bitset | 232 | 0.38% FixedBitVect | 16 | 0.03% Generic | 1486 | 2.41% LocalAddressVisitor | 0 | 0.00% FieldSeqStore | 368 | 0.60% ZeroOffsetFieldMap | 40 | 0.06% ArrayInfoMap | 0 | 0.00% MemoryPhiArg | 0 | 0.00% CSE | 0 | 0.00% GC | 1576 | 2.55% CorTailCallInfo | 0 | 0.00% Inlining | 128 | 0.21% ArrayStack | 0 | 0.00% DebugInfo | 208 | 0.34% DebugOnly | 14023 | 22.71% Codegen | 1184 | 1.92% LoopOpt | 0 | 0.00% LoopHoist | 0 | 0.00% Unknown | 386 | 0.63% RangeCheck | 0 | 0.00% CopyProp | 0 | 0.00% SideEffects | 0 | 0.00% ObjectAllocator | 0 | 0.00% VariableLiveRanges | 0 | 0.00% ClassLayout | 112 | 0.18% TailMergeThrows | 0 | 0.00% EarlyProp | 0 | 0.00% ZeroInit | 0 | 0.00% ****** DONE compiling Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this ScheduleFlushSend: jobgroup=71 version=0 ScheduleSend: version=0 jobgroup=71 ScheduleSend: version=0 jobgroup=77 RPCSystem: jobgroup=103 version=0 ScheduleFlushSend: jobgroup=103 version=0 ScheduleSend: version=0 jobgroup=103 ScheduleSend: version=0 jobgroup=109 RPCSystem: jobgroup=135 version=0 ScheduleFlushSend: jobgroup=135 version=0 ScheduleSend: version=0 jobgroup=135 Streamed scene with 817ms latency from Data/EntityScenes/786e57b5191e248069790dde644d7e1a.0.entities DeserializeWorld can only be used on completely empty EntityManager. Please create a new empty World and use EntityManager.MoveEntitiesFrom to move the loaded entities into the destination world instead. at Unity.Entities.Serialization.SerializeUtility.EndDeserializeWorld(ExclusiveEntityTransaction manager, DotsSerializationReader dotsReader, WorldDeserializationStatus& status, Object[] unityObjects) in /home/kevinmv/dev/dots/Samples/Packages/com.unity.entities/Unity.Entities/Serialization/SerializeUtility.cs:line 535 at Unity.Entities.Serialization.SerializeUtility.DeserializeWorld(ExclusiveEntityTransaction manager, BinaryReader reader, Object[] unityObjects) in /home/kevinmv/dev/dots/Samples/Packages/com.unity.entities/Unity.Entities/Serialization/SerializeUtility.cs:line 747 at Unity.Scenes.AsyncLoadSceneOperation.AsyncLoadSceneJob.Execute() in /home/kevinmv/dev/dots/Samples/Packages/com.unity.entities/Unity.Scenes/AsyncLoadSceneOperation.cs:line 154 Error when processing 'AsyncLoadSceneJob(Data/EntityScenes/786e57b5191e248069790dde644d7e1a.0.entities)': DeserializeWorld can only be used on completely empty EntityManager. Please create a new empty World and use EntityManager.MoveEntitiesFrom to move the loaded entities into the destination world instead. ScheduleSend: version=0 jobgroup=146 RPCSystem: jobgroup=172 version=0 ScheduleFlushSend: jobgroup=172 version=0 ScheduleSend: version=0 jobgroup=172 ScheduleSend: version=0 jobgroup=178 RPCSystem: jobgroup=204 version=0 ScheduleFlushSend: jobgroup=204 version=0 ScheduleSend: version=0 jobgroup=204 ScheduleSend: version=0 jobgroup=210 RPCSystem: jobgroup=236 version=0 ScheduleFlushSend: jobgroup=236 version=0 ScheduleSend: version=0 jobgroup=236 ScheduleSend: version=0 jobgroup=242 RPCSystem: jobgroup=268 version=0 ScheduleFlushSend: jobgroup=268 version=0 ScheduleSend: version=0 jobgroup=268 ScheduleSend: version=0 jobgroup=274 RPCSystem: jobgroup=300 version=0 ScheduleFlushSend: jobgroup=300 version=0 ScheduleSend: version=0 jobgroup=300 ScheduleSend: version=0 jobgroup=306 RPCSystem: jobgroup=337 version=0 ScheduleFlushSend: jobgroup=337 version=0 ScheduleSend: version=0 jobgroup=337 ScheduleSend: version=0 jobgroup=343 RPCSystem: jobgroup=369 version=0 ScheduleFlushSend: jobgroup=369 version=0 ScheduleSend: version=0 jobgroup=369 ScheduleSend: version=0 jobgroup=375 RPCSystem: jobgroup=401 version=0 ScheduleFlushSend: jobgroup=401 version=0 ScheduleSend: version=0 jobgroup=401 ScheduleSend: version=0 jobgroup=407 RPCSystem: jobgroup=433 version=0 ScheduleFlushSend: jobgroup=433 version=0 ScheduleSend: version=0 jobgroup=433 ScheduleSend: version=0 jobgroup=439 RPCSystem: jobgroup=465 version=0 ScheduleFlushSend: jobgroup=465 version=0 ScheduleSend: version=0 jobgroup=465 ScheduleSend: version=0 jobgroup=471 RPCSystem: jobgroup=497 version=0 ScheduleFlushSend: jobgroup=497 version=0 ScheduleSend: version=0 jobgroup=497 ScheduleSend: version=0 jobgroup=503 RPCSystem: jobgroup=529 version=0 ScheduleFlushSend: jobgroup=529 version=0 ScheduleSend: version=0 jobgroup=529 ScheduleSend: version=0 jobgroup=535 RPCSystem: jobgroup=561 version=0 ScheduleFlushSend: jobgroup=561 version=0 ScheduleSend: version=0 jobgroup=561 ScheduleSend: version=0 jobgroup=567 RPCSystem: jobgroup=609 version=0 ScheduleFlushSend: jobgroup=609 version=0 ScheduleSend: version=0 jobgroup=609 ScheduleSend: version=0 jobgroup=615 RPCSystem: jobgroup=641 version=0 ScheduleFlushSend: jobgroup=641 version=0 ScheduleSend: version=0 jobgroup=641 ScheduleSend: version=0 jobgroup=647 RPCSystem: jobgroup=673 version=0 ScheduleFlushSend: jobgroup=673 version=0 ScheduleSend: version=0 jobgroup=673 ScheduleSend: version=0 jobgroup=679 RPCSystem: jobgroup=705 version=0 ScheduleFlushSend: jobgroup=705 version=0 ScheduleSend: version=0 jobgroup=705 ScheduleSend: version=0 jobgroup=711 RPCSystem: jobgroup=737 version=0 ScheduleFlushSend: jobgroup=737 version=0 ScheduleSend: version=0 jobgroup=737 ScheduleSend: version=0 jobgroup=743 RPCSystem: jobgroup=769 version=0 ScheduleFlushSend: jobgroup=769 version=0 ScheduleSend: version=0 jobgroup=769 ScheduleSend: version=0 jobgroup=775 RPCSystem: jobgroup=801 version=0 ScheduleFlushSend: jobgroup=801 version=0 ScheduleSend: version=0 jobgroup=801 ScheduleSend: version=0 jobgroup=807 RPCSystem: jobgroup=833 version=0 ScheduleFlushSend: jobgroup=833 version=0 ScheduleSend: version=0 jobgroup=833 ScheduleSend: version=0 jobgroup=839 RPCSystem: jobgroup=870 version=0 ScheduleFlushSend: jobgroup=870 version=0 ScheduleSend: version=0 jobgroup=870 ScheduleSend: version=0 jobgroup=876 RPCSystem: jobgroup=902 version=0 ScheduleFlushSend: jobgroup=902 version=0 ScheduleSend: version=0 jobgroup=902 ScheduleSend: version=0 jobgroup=908 RPCSystem: jobgroup=934 version=0 ScheduleFlushSend: jobgroup=934 version=0 ScheduleSend: version=0 jobgroup=934 ScheduleSend: version=0 jobgroup=940 RPCSystem: jobgroup=966 version=0 ScheduleFlushSend: jobgroup=966 version=0 ScheduleSend: version=0 jobgroup=966 ScheduleSend: version=0 jobgroup=972 RPCSystem: jobgroup=998 version=0 ScheduleFlushSend: jobgroup=998 version=0 ScheduleSend: version=0 jobgroup=998 ScheduleSend: version=0 jobgroup=1004 RPCSystem: jobgroup=1030 version=0 ScheduleFlushSend: jobgroup=1030 version=0 ScheduleSend: version=0 jobgroup=1030 ScheduleSend: version=0 jobgroup=1036 RPCSystem: jobgroup=1062 version=0 ScheduleFlushSend: jobgroup=1062 version=0 ScheduleSend: version=0 jobgroup=1062 ScheduleSend: version=0 jobgroup=1068 RPCSystem: jobgroup=1094 version=0 ScheduleFlushSend: jobgroup=1094 version=0 ScheduleSend: version=0 jobgroup=1094 ScheduleSend: version=0 jobgroup=1100 RPCSystem: jobgroup=1142 version=0 ScheduleFlushSend: jobgroup=1142 version=0 ScheduleSend: version=0 jobgroup=1142 ScheduleSend: version=0 jobgroup=1148 RPCSystem: jobgroup=1174 version=0 ScheduleFlushSend: jobgroup=1174 version=0 ScheduleSend: version=0 jobgroup=1174 ScheduleSend: version=0 jobgroup=1180 RPCSystem: jobgroup=1206 version=0 ScheduleFlushSend: jobgroup=1206 version=0 ScheduleSend: version=0 jobgroup=1206 ScheduleSend: version=0 jobgroup=1212 RPCSystem: jobgroup=1238 version=0 ScheduleFlushSend: jobgroup=1238 version=0 ScheduleSend: version=0 jobgroup=1238 ScheduleSend: version=0 jobgroup=1244 RPCSystem: jobgroup=1270 version=0 ScheduleFlushSend: jobgroup=1270 version=0 ScheduleSend: version=0 jobgroup=1270 ScheduleSend: version=0 jobgroup=1276 RPCSystem: jobgroup=1302 version=0 ScheduleFlushSend: jobgroup=1302 version=0 ScheduleSend: version=0 jobgroup=1302 ScheduleSend: version=0 jobgroup=1308 RPCSystem: jobgroup=1334 version=0 ScheduleFlushSend: jobgroup=1334 version=0 ScheduleSend: version=0 jobgroup=1334 ScheduleSend: version=0 jobgroup=1340 RPCSystem: jobgroup=1366 version=0 ScheduleFlushSend: jobgroup=1366 version=0 ScheduleSend: version=0 jobgroup=1366 ScheduleSend: version=0 jobgroup=1372 RPCSystem: jobgroup=1403 version=0 ScheduleFlushSend: jobgroup=1403 version=0 ScheduleSend: version=0 jobgroup=1403 ScheduleSend: version=0 jobgroup=1409 RPCSystem: jobgroup=1435 version=0 ScheduleFlushSend: jobgroup=1435 version=0 ScheduleSend: version=0 jobgroup=1435 ScheduleSend: version=0 jobgroup=1441 RPCSystem: jobgroup=1467 version=0 ScheduleFlushSend: jobgroup=1467 version=0 ScheduleSend: version=0 jobgroup=1467 ScheduleSend: version=0 jobgroup=1473 RPCSystem: jobgroup=1499 version=0 ScheduleFlushSend: jobgroup=1499 version=0 ScheduleSend: version=0 jobgroup=1499 ScheduleSend: version=0 jobgroup=1505 RPCSystem: jobgroup=1531 version=0 ScheduleFlushSend: jobgroup=1531 version=0 ScheduleSend: version=0 jobgroup=1531 ScheduleSend: version=0 jobgroup=1537 RPCSystem: jobgroup=1563 version=0 ScheduleFlushSend: jobgroup=1563 version=0 ScheduleSend: version=0 jobgroup=1563 ScheduleSend: version=0 jobgroup=1569 RPCSystem: jobgroup=1595 version=0 ScheduleFlushSend: jobgroup=1595 version=0 ScheduleSend: version=0 jobgroup=1595 ScheduleSend: version=0 jobgroup=1601 RPCSystem: jobgroup=1627 version=0 ScheduleFlushSend: jobgroup=1627 version=0 ScheduleSend: version=0 jobgroup=1627 ScheduleSend: version=0 jobgroup=1633 RPCSystem: jobgroup=1675 version=0 ScheduleFlushSend: jobgroup=1675 version=0 ScheduleSend: version=0 jobgroup=1675 ScheduleSend: version=0 jobgroup=1681 RPCSystem: jobgroup=1707 version=0 ScheduleFlushSend: jobgroup=1707 version=0 ScheduleSend: version=0 jobgroup=1707 ScheduleSend: version=0 jobgroup=1713 RPCSystem: jobgroup=1739 version=0 ScheduleFlushSend: jobgroup=1739 version=0 ScheduleSend: version=0 jobgroup=1739 ScheduleSend: version=0 jobgroup=1745 RPCSystem: jobgroup=1771 version=0 ScheduleFlushSend: jobgroup=1771 version=0 ScheduleSend: version=0 jobgroup=1771 ScheduleSend: version=0 jobgroup=1777 RPCSystem: jobgroup=1803 version=0 ScheduleFlushSend: jobgroup=1803 version=0 ScheduleSend: version=0 jobgroup=1803 ScheduleSend: version=0 jobgroup=1809 RPCSystem: jobgroup=1835 version=0 ScheduleFlushSend: jobgroup=1835 version=0 ScheduleSend: version=0 jobgroup=1835 ScheduleSend: version=0 jobgroup=1841 RPCSystem: jobgroup=1867 version=0 ScheduleFlushSend: jobgroup=1867 version=0 ScheduleSend: version=0 jobgroup=1867 ScheduleSend: version=0 jobgroup=1873 RPCSystem: jobgroup=1899 version=0 ScheduleFlushSend: jobgroup=1899 version=0 ScheduleSend: version=0 jobgroup=1899 ****** START compiling Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this (MethodHash=08be6857) Generating code for Unix x64 OPTIONS: Tier-1 compilation OPTIONS: compCodeOpt = FAST_CODE OPTIONS: compDbgCode = false OPTIONS: compDbgInfo = true OPTIONS: compDbgEnC = false OPTIONS: compProcedureSplitting = false OPTIONS: compProcedureSplittingEH = false IL to import: IL_0000 72 bb 0f 00 70 ldstr 0x70000FBB IL_0005 04 ldarg.2 IL_0006 7b 25 01 00 0a ldfld 0xA000125 IL_000b 8c 11 00 00 01 box 0x1000011 IL_0010 04 ldarg.2 IL_0011 7b 26 01 00 0a ldfld 0xA000126 IL_0016 8c 18 00 00 01 box 0x1000018 IL_001b 28 27 01 00 0a call 0xA000127 IL_0020 28 6b 00 00 0a call 0xA00006B IL_0025 12 00 ldloca.s 0x0 IL_0027 fe 15 35 00 00 02 initobj 0x2000035 IL_002d 12 00 ldloca.s 0x0 IL_002f 02 ldarg.0 IL_0030 7b ab 00 00 04 ldfld 0x40000AB IL_0035 7d bb 00 00 04 stfld 0x40000BB IL_003a 12 00 ldloca.s 0x0 IL_003c 02 ldarg.0 IL_003d 7b ad 00 00 04 ldfld 0x40000AD IL_0042 7d ba 00 00 04 stfld 0x40000BA IL_0047 06 ldloc.0 IL_0048 04 ldarg.2 IL_0049 28 11 00 00 2b call 0x2B000011 IL_004e 2a ret **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 'this' passed in register rdi **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x79670b20 (Unity.Collections.NativeQueue`1[QueuedSendMessage]), ...) => passedInRegisters = false **** getSystemVAmd64PassStructInRegisterDescriptor(0x79670b20 (Unity.Collections.NativeQueue`1[QueuedSendMessage]), ...) => passedInRegisters = false **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 Arg #2 passed in register(s) firstEightByte: rsi, secondEightByte: rdx lvaGrabTemp returning 4 (V04 tmp0) (a long lifetime temp) called for OutgoingArgSpace. ; Initial local variable assignments ; ; V00 this byref this ; V01 arg1 struct ; V02 arg2 struct ; V03 loc0 struct ; V04 OutArgs lclBlk "OutgoingArgSpace" *************** In compInitDebuggingInfo() for Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this getVars() returned cVars = 0, extendOthers = true info.compVarScopesCount = 4 VarNum LVNum Name Beg End 0: 00h 00h V00 this 000h 04Fh 1: 01h 01h V01 arg1 000h 04Fh 2: 02h 02h V02 arg2 000h 04Fh 3: 03h 03h V03 loc0 000h 04Fh info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE ) *************** In fgFindBasicBlocks() for Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this Jump targets: none New Basic Block BB01 [0000] created. BB01 [000..04F) IL Code Size,Instr 79, 23, Basic Block count 1, Local Variable Num,Ref count 5, 9 for method Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this OPTIONS: opts.MinOpts() == false Basic block list for 'Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Pre-import *************** Finishing PHASE Pre-import *************** Starting PHASE Importation *************** In impImport() for Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this impImportBlockPending for BB01 Importing BB01 (PC=000) of 'Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' [ 0] 0 (0x000) ldstr 70000FBB [ 1] 5 (0x005) ldarg.2 [ 2] 6 (0x006) ldfld 0A000125 [ 2] 11 (0x00b) box 01000011 Compiler::impImportAndPushBox -- handling BOX(value class) via inline allocate/copy sequence lvaGrabTemp returning 5 (V05 tmp1) called for Single-def Box Helper. Marking V05 as a single def local lvaSetClass: setting class for V05 to (00007F6678BEB1C0) System.UInt32 [exact] STMT00000 (IL 0x000... ???) [000007] -A---------- * ASG ref [000006] D------N---- +--* LCL_VAR ref V05 tmp1 [000005] ------------ \--* ALLOCOBJ ref [000004] ------------ \--* CNS_INT(h) long 0x7f6678beb1c0 class STMT00001 (IL ???... ???) [000012] -A--G------- * ASG int [000011] -------N---- +--* IND int [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V05 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ----G------- \--* FIELD int Version [000002] ------------ \--* ADDR byref [000001] -------N---- \--* LCL_VAR struct V02 arg2 [ 2] 16 (0x010) ldarg.2 [ 3] 17 (0x011) ldfld 0A000126 [ 3] 22 (0x016) box 01000018 Compiler::impImportAndPushBox -- handling BOX(value class) via inline allocate/copy sequence lvaGrabTemp returning 6 (V06 tmp2) called for Single-def Box Helper. Marking V06 as a single def local lvaSetClass: setting class for V06 to (00007F6678C127F0) System.IntPtr [exact] STMT00002 (IL ???... ???) [000021] -A---------- * ASG ref [000020] D------N---- +--* LCL_VAR ref V06 tmp2 [000019] ------------ \--* ALLOCOBJ ref [000018] ------------ \--* CNS_INT(h) long 0x7f6678c127f0 class STMT00003 (IL ???... ???) [000026] -A--G------- * ASG long [000025] -------N---- +--* IND long [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V06 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ----G------- \--* FIELD long JobGroup [000016] ------------ \--* ADDR byref [000015] -------N---- \--* LCL_VAR struct V02 arg2 [ 3] 27 (0x01b) call 0A000127 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 STMT00004 (IL ???... ???) [000029] I-C-G------- * CALL ref System.String.Format (exactContextHnd=0x00007F6678C469A9) [000000] ------------ arg0 +--* CNS_STR ref [000014] ------------ arg1 +--* BOX ref [000013] ------------ | \--* LCL_VAR ref V05 tmp1 [000028] ------------ arg2 \--* BOX ref [000027] ------------ \--* LCL_VAR ref V06 tmp2 [ 1] 32 (0x020) call 0A00006B In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 STMT00005 (IL ???... ???) [000031] I-C-G------- * CALL void UnityEngine.Debug.Log (exactContextHnd=0x00007F66798F3CD1) [000030] --C--------- arg0 \--* RET_EXPR ref (inl return from call [000029]) [ 0] 37 (0x025) ldloca.s 0 [ 1] 39 (0x027) initobj 02000035 STMT00006 (IL 0x025... ???) [000035] IA---------- * ASG struct (init) [000032] D------N---- +--* LCL_VAR struct V03 loc0 [000034] ------------ \--* CNS_INT int 0 [ 0] 45 (0x02d) ldloca.s 0 [ 1] 47 (0x02f) ldarg.0 [ 2] 48 (0x030) ldfld 040000AB [ 2] 53 (0x035) stfld 040000BB STMT00007 (IL 0x02D... ???) [000043] -A-XG------- * ASG struct (copy) [000042] ------------ +--* OBJ struct [000041] ------------ | \--* ADDR byref [000040] -------N---- | \--* FIELD struct Baselib [000037] ------------ | \--* ADDR byref [000036] -------N---- | \--* LCL_VAR struct V03 loc0 [000039] ---XG------- \--* FIELD struct m_Baselib [000038] ------------ \--* LCL_VAR byref V00 this [ 0] 58 (0x03a) ldloca.s 0 [ 1] 60 (0x03c) ldarg.0 [ 2] 61 (0x03d) ldfld 040000AD [ 2] 66 (0x042) stfld 040000BA STMT00008 (IL 0x03A... ???) [000051] -A-XG------- * ASG struct (copy) [000050] ------------ +--* BLK struct [000049] ------------ | \--* ADDR byref [000048] -------N---- | \--* FIELD struct Tx [000045] ------------ | \--* ADDR byref [000044] -------N---- | \--* LCL_VAR struct V03 loc0 [000047] ---XG------- \--* FIELD struct m_PayloadsTx [000046] ------------ \--* LCL_VAR byref V00 this [ 0] 71 (0x047) ldloc.0 [ 1] 72 (0x048) ldarg.2 [ 2] 73 (0x049) call 2B000011 (Implicit Tail call: prefixFlags |= PREFIX_TAILCALL_IMPLICIT) In Compiler::impImportCall: opcode is call, kind=0, callRetType is struct, structSize is 16 Calling impNormStructVal on: [000053] ------------ * LCL_VAR struct V02 arg2 resulting tree: [000056] n----------- * OBJ struct [000055] ------------ \--* ADDR byref [000053] -------N---- \--* LCL_VAR struct V02 arg2 Calling impNormStructVal on: [000052] ------------ * LCL_VAR struct V03 loc0 resulting tree: [000058] n----------- * OBJ struct [000057] ------------ \--* ADDR byref [000052] -------N---- \--* LCL_VAR struct V03 loc0 GTF_CALL_M_IMPLICIT_TAILCALL set for call [000054] INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' for 'Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' calling 'Unity.Jobs.IJobExtensions:Schedule(FlushSendJob,Unity.Jobs.JobHandle):Unity.Jobs.JobHandle' INLINER: Marking Unity.Jobs.IJobExtensions:Schedule(FlushSendJob,Unity.Jobs.JobHandle):Unity.Jobs.JobHandle as NOINLINE because of too many il bytes INLINER: during 'impMarkInlineCandidate' result 'failed this callee' reason 'too many il bytes' **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 [ 1] 78 (0x04e) ret impFixupStructReturnType: retyping [000054] --C-G------- * CALL struct Unity.Jobs.IJobExtensions.Schedule,NA [000058] n----------- arg0 +--* OBJ struct [000057] ------------ | \--* ADDR byref [000052] -------N---- | \--* LCL_VAR struct V03 loc0 [000056] n----------- arg1 \--* OBJ struct [000055] ------------ \--* ADDR byref [000053] -------N---- \--* LCL_VAR struct V02 arg2 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 STMT00009 (IL 0x047... ???) [000059] --C-G------- * RETURN struct [000054] --C-G------- \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA [000058] n----------- arg0 +--* OBJ struct [000057] ------------ | \--* ADDR byref [000052] -------N---- | \--* LCL_VAR struct V03 loc0 [000056] n----------- arg1 \--* OBJ struct [000055] ------------ \--* ADDR byref [000053] -------N---- \--* LCL_VAR struct V02 arg2 *************** Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} ***** BB01 STMT00000 (IL 0x000...0x028) [000007] -A---------- * ASG ref [000006] D------N---- +--* LCL_VAR ref V05 tmp1 [000005] ------------ \--* ALLOCOBJ ref [000004] ------------ \--* CNS_INT(h) long 0x7f6678beb1c0 class ***** BB01 STMT00001 (IL ???... ???) [000012] -A--G------- * ASG int [000011] -------N---- +--* IND int [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V05 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ----G------- \--* FIELD int Version [000002] ------------ \--* ADDR byref [000001] -------N---- \--* LCL_VAR struct V02 arg2 ***** BB01 STMT00002 (IL ???... ???) [000021] -A---------- * ASG ref [000020] D------N---- +--* LCL_VAR ref V06 tmp2 [000019] ------------ \--* ALLOCOBJ ref [000018] ------------ \--* CNS_INT(h) long 0x7f6678c127f0 class ***** BB01 STMT00003 (IL ???... ???) [000026] -A--G------- * ASG long [000025] -------N---- +--* IND long [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V06 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ----G------- \--* FIELD long JobGroup [000016] ------------ \--* ADDR byref [000015] -------N---- \--* LCL_VAR struct V02 arg2 ***** BB01 STMT00004 (IL ???... ???) [000029] I-C-G------- * CALL ref System.String.Format (exactContextHnd=0x00007F6678C469A9) [000000] ------------ arg0 +--* CNS_STR ref [000014] ------------ arg1 +--* BOX ref [000013] ------------ | \--* LCL_VAR ref V05 tmp1 [000028] ------------ arg2 \--* BOX ref [000027] ------------ \--* LCL_VAR ref V06 tmp2 ***** BB01 STMT00005 (IL ???... ???) [000031] I-C-G------- * CALL void UnityEngine.Debug.Log (exactContextHnd=0x00007F66798F3CD1) [000030] --C--------- arg0 \--* RET_EXPR ref (inl return from call [000029]) ***** BB01 STMT00006 (IL 0x025... ???) [000035] IA---------- * ASG struct (init) [000032] D------N---- +--* LCL_VAR struct V03 loc0 [000034] ------------ \--* CNS_INT int 0 ***** BB01 STMT00007 (IL 0x02D...0x035) [000043] -A-XG------- * ASG struct (copy) [000042] ------------ +--* OBJ struct [000041] ------------ | \--* ADDR byref [000040] -------N---- | \--* FIELD struct Baselib [000037] ------------ | \--* ADDR byref [000036] -------N---- | \--* LCL_VAR struct V03 loc0 [000039] ---XG------- \--* FIELD struct m_Baselib [000038] ------------ \--* LCL_VAR byref V00 this ***** BB01 STMT00008 (IL 0x03A...0x042) [000051] -A-XG------- * ASG struct (copy) [000050] ------------ +--* BLK struct [000049] ------------ | \--* ADDR byref [000048] -------N---- | \--* FIELD struct Tx [000045] ------------ | \--* ADDR byref [000044] -------N---- | \--* LCL_VAR struct V03 loc0 [000047] ---XG------- \--* FIELD struct m_PayloadsTx [000046] ------------ \--* LCL_VAR byref V00 this ***** BB01 STMT00009 (IL 0x047...0x04E) [000059] --C-G------- * RETURN struct [000054] --C-G------- \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA [000058] n----------- arg0 +--* OBJ struct [000057] ------------ | \--* ADDR byref [000052] -------N---- | \--* LCL_VAR struct V03 loc0 [000056] n----------- arg1 \--* OBJ struct [000055] ------------ \--* ADDR byref [000053] -------N---- \--* LCL_VAR struct V02 arg2 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Indirect call transform -- no candidates to transform *************** Finishing PHASE Indirect call transform [no changes] *************** Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Finishing PHASE Expand patchpoints [no changes] *************** Starting PHASE Post-import *************** Finishing PHASE Post-import *************** Starting PHASE Morph - Init New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short) *************** In fgRemoveEmptyBlocks *************** Finishing PHASE Morph - Init *************** In fgDebugCheckBBlist *************** Starting PHASE Morph - Inlining Expanding INLINE_CANDIDATE in statement STMT00004 in BB01: STMT00004 (IL ???... ???) [000029] I-C-G------- * CALL ref System.String.Format (exactContextHnd=0x00007F6678C469A9) [000000] ------------ arg0 +--* CNS_STR ref [000014] ------------ arg1 +--* BOX ref [000013] ------------ | \--* LCL_VAR ref V05 tmp1 [000028] ------------ arg2 \--* BOX ref [000027] ------------ \--* LCL_VAR ref V06 tmp2 Argument #0: is a constant [000000] ------------ * CNS_STR ref Argument #1: [000014] ------------ * BOX ref [000013] ------------ \--* LCL_VAR ref V05 tmp1 Argument #2: [000028] ------------ * BOX ref [000027] ------------ \--* LCL_VAR ref V06 tmp2 INLINER: inlineInfo.tokenLookupContextHandle for System.String:Format(System.String,System.Object,System.Object):System.String set to 0x00007F6678C469A9: Invoking compiler for the inlinee method System.String:Format(System.String,System.Object,System.Object):System.String : IL to import: IL_0000 14 ldnull IL_0001 02 ldarg.0 IL_0002 03 ldarg.1 IL_0003 04 ldarg.2 IL_0004 73 12 12 00 06 newobj 0x6001212 IL_0009 28 df 06 00 06 call 0x60006DF IL_000e 2a ret INLINER impTokenLookupContextHandle for System.String:Format(System.String,System.Object,System.Object):System.String is 0x00007F6678C469A9. *************** In fgFindBasicBlocks() for System.String:Format(System.String,System.Object,System.Object):System.String Jump targets: none New Basic Block BB02 [0001] created. BB02 [000..00F) Basic block list for 'System.String:Format(System.String,System.Object,System.Object):System.String' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB02 [0001] 1 1 [000..00F) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000029] Starting PHASE Pre-import *************** Inline @[000029] Finishing PHASE Pre-import *************** Inline @[000029] Starting PHASE Importation *************** In impImport() for System.String:Format(System.String,System.Object,System.Object):System.String impImportBlockPending for BB02 Importing BB02 (PC=000) of 'System.String:Format(System.String,System.Object,System.Object):System.String' [ 0] 0 (0x000) ldnull [ 1] 1 (0x001) ldarg.0 [ 2] 2 (0x002) ldarg.1 lvaGrabTemp returning 7 (V07 tmp3) called for Inlining Arg. Marked V07 as a single def temp lvaSetClass: setting class for V07 to (00007F6678BEB1C0) System.UInt32 [exact] [ 3] 3 (0x003) ldarg.2 lvaGrabTemp returning 8 (V08 tmp4) called for Inlining Arg. Marked V08 as a single def temp lvaSetClass: setting class for V08 to (00007F6678C127F0) System.IntPtr [exact] [ 4] 4 (0x004) newobj lvaGrabTemp returning 9 (V09 tmp5) called for NewObj constructor temp. Suppressing zero-init for V09 -- expect to zero in prolog 06001212 In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0 [000066] I-C-G------- * CALL void System.ParamsArray..ctor (exactContextHnd=0x00007F6679A59E79) [000065] ------------ this in rdi +--* ADDR byref [000064] -------N---- | \--* LCL_VAR struct V09 tmp5 [000062] ------------ arg1 +--* LCL_VAR ref V07 tmp3 [000063] ------------ arg2 \--* LCL_VAR ref V08 tmp4 [ 3] 9 (0x009) call 060006DF In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 Calling impNormStructVal on: [000067] ------------ * LCL_VAR struct V09 tmp5 resulting tree: [000070] n----------- * OBJ struct [000069] ------------ \--* ADDR byref [000067] -------N---- \--* LCL_VAR struct V09 tmp5 [000068] I-C-G------- * CALL ref System.String.FormatHelper (exactContextHnd=0x00007F6678C469A9) [000060] ------------ arg0 +--* CNS_INT ref null [000061] ------------ arg1 +--* CNS_STR ref [000070] n----------- arg2 \--* OBJ struct [000069] ------------ \--* ADDR byref [000067] -------N---- \--* LCL_VAR struct V09 tmp5 [ 1] 14 (0x00e) ret Inlinee Return expression (before normalization) => [000071] --C--------- * RET_EXPR ref (inl return from call [000068]) Inlinee Return expression (after normalization) => [000071] --C--------- * RET_EXPR ref (inl return from call [000068]) *************** Inline @[000029] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB02 [0001] 1 1 [000..00F) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB02 [000..00F) (return), preds={} succs={} ***** BB02 [000066] I-C-G------- * CALL void System.ParamsArray..ctor (exactContextHnd=0x00007F6679A59E79) [000065] ------------ this in rdi +--* ADDR byref [000064] -------N---- | \--* LCL_VAR struct V09 tmp5 [000062] ------------ arg1 +--* LCL_VAR ref V07 tmp3 [000063] ------------ arg2 \--* LCL_VAR ref V08 tmp4 ***** BB02 [000068] I-C-G------- * CALL ref System.String.FormatHelper (exactContextHnd=0x00007F6678C469A9) [000060] ------------ arg0 +--* CNS_INT ref null [000061] ------------ arg1 +--* CNS_STR ref [000070] n----------- arg2 \--* OBJ struct [000069] ------------ \--* ADDR byref [000067] -------N---- \--* LCL_VAR struct V09 tmp5 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000029] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000029] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000029] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000029] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000029] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000029] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000029] ----------- Arguments setup: Inlinee method body: STMT00010 (IL ???... ???) [000066] I-C-G------- * CALL void System.ParamsArray..ctor (exactContextHnd=0x00007F6679A59E79) [000065] ------------ this in rdi +--* ADDR byref [000064] -------N---- | \--* LCL_VAR struct V09 tmp5 [000014] ------------ arg1 +--* BOX ref [000013] ------------ | \--* LCL_VAR ref V05 tmp1 [000028] ------------ arg2 \--* BOX ref [000027] ------------ \--* LCL_VAR ref V06 tmp2 STMT00011 (IL ???... ???) [000068] I-C-G------- * CALL ref System.String.FormatHelper (exactContextHnd=0x00007F6678C469A9) [000060] ------------ arg0 +--* CNS_INT ref null [000061] ------------ arg1 +--* CNS_STR ref [000070] n----------- arg2 \--* OBJ struct [000069] ------------ \--* ADDR byref [000067] -------N---- \--* LCL_VAR struct V09 tmp5 fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000029] is [000071] --C--------- * RET_EXPR ref (inl return from call [000068]) Successfully inlined System.String:Format(System.String,System.Object,System.Object):System.String (15 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' calling 'System.String:Format(System.String,System.Object,System.Object):System.String' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement STMT00010 in BB01: STMT00010 (IL ???... ???) [000066] I-C-G------- * CALL void System.ParamsArray..ctor (exactContextHnd=0x00007F6679A59E79) [000065] ------------ this in rdi +--* ADDR byref [000064] -------N---- | \--* LCL_VAR struct V09 tmp5 [000014] ------------ arg1 +--* BOX ref [000013] ------------ | \--* LCL_VAR ref V05 tmp1 [000028] ------------ arg2 \--* BOX ref [000027] ------------ \--* LCL_VAR ref V06 tmp2 thisArg: is a constant is byref to a struct local [000065] ------------ * ADDR byref [000064] -------N---- \--* LCL_VAR struct V09 tmp5 Argument #1: [000014] ------------ * BOX ref [000013] ------------ \--* LCL_VAR ref V05 tmp1 Argument #2: [000028] ------------ * BOX ref [000027] ------------ \--* LCL_VAR ref V06 tmp2 INLINER: inlineInfo.tokenLookupContextHandle for System.ParamsArray:.ctor(System.Object,System.Object):this set to 0x00007F6679A59E79: Invoking compiler for the inlinee method System.ParamsArray:.ctor(System.Object,System.Object):this : IL to import: IL_0000 02 ldarg.0 IL_0001 03 ldarg.1 IL_0002 7d 36 04 00 04 stfld 0x4000436 IL_0007 02 ldarg.0 IL_0008 04 ldarg.2 IL_0009 7d 37 04 00 04 stfld 0x4000437 IL_000e 02 ldarg.0 IL_000f 14 ldnull IL_0010 7d 38 04 00 04 stfld 0x4000438 IL_0015 02 ldarg.0 IL_0016 7e 34 04 00 04 ldsfld 0x4000434 IL_001b 7d 39 04 00 04 stfld 0x4000439 IL_0020 2a ret INLINER impTokenLookupContextHandle for System.ParamsArray:.ctor(System.Object,System.Object):this is 0x00007F6679A59E79. *************** In fgFindBasicBlocks() for System.ParamsArray:.ctor(System.Object,System.Object):this weight= 69 : state 226 [ ldarg.0 -> ldarg.1 -> stfld ] weight= 98 : state 228 [ ldarg.0 -> ldarg.2 -> stfld ] weight= 10 : state 3 [ ldarg.0 ] weight= 7 : state 21 [ ldnull ] weight= 31 : state 111 [ stfld ] weight= 10 : state 3 [ ldarg.0 ] weight=159 : state 112 [ ldsfld ] weight= 31 : state 111 [ stfld ] weight= 19 : state 42 [ ret ] multiplier in instance constructors increased to 1.5. multiplier in methods of promotable struct increased to 4.5. Inline candidate is mostly loads and stores. Multiplier increased to 7.5. Inline candidate callsite is boring. Multiplier increased to 8.8. calleeNativeSizeEstimate=434 callsiteNativeSizeEstimate=145 benefit multiplier=8.8 threshold=1276 Native estimate for function size is within threshold for inlining 43.4 <= 127.6 (multiplier = 8.8) Jump targets: none New Basic Block BB03 [0002] created. BB03 [000..021) Basic block list for 'System.ParamsArray:.ctor(System.Object,System.Object):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB03 [0002] 1 1 [000..021) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000066] Starting PHASE Pre-import *************** Inline @[000066] Finishing PHASE Pre-import *************** Inline @[000066] Starting PHASE Importation *************** In impImport() for System.ParamsArray:.ctor(System.Object,System.Object):this impImportBlockPending for BB03 Importing BB03 (PC=000) of 'System.ParamsArray:.ctor(System.Object,System.Object):this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldarg.1 lvaGrabTemp returning 10 (V10 tmp6) called for Inlining Arg. Marked V10 as a single def temp lvaSetClass: setting class for V10 to (00007F6678BEB1C0) System.UInt32 [exact] [ 2] 2 (0x002) stfld 04000436 [000077] -A---------- * ASG ref [000076] -------N---- +--* FIELD ref _arg0 [000073] ------------ | \--* ADDR byref [000074] -------N---- | \--* LCL_VAR struct V09 tmp5 [000075] ------------ \--* LCL_VAR ref V10 tmp6 [ 0] 7 (0x007) ldarg.0 [ 1] 8 (0x008) ldarg.2 lvaGrabTemp returning 11 (V11 tmp7) called for Inlining Arg. Marked V11 as a single def temp lvaSetClass: setting class for V11 to (00007F6678C127F0) System.IntPtr [exact] [ 2] 9 (0x009) stfld 04000437 [000082] -A---------- * ASG ref [000081] -------N---- +--* FIELD ref _arg1 [000078] ------------ | \--* ADDR byref [000079] -------N---- | \--* LCL_VAR struct V09 tmp5 [000080] ------------ \--* LCL_VAR ref V11 tmp7 [ 0] 14 (0x00e) ldarg.0 [ 1] 15 (0x00f) ldnull [ 2] 16 (0x010) stfld 04000438 [000087] -A---------- * ASG ref [000086] -------N---- +--* FIELD ref _arg2 [000083] ------------ | \--* ADDR byref [000084] -------N---- | \--* LCL_VAR struct V09 tmp5 [000085] ------------ \--* CNS_INT ref null [ 0] 21 (0x015) ldarg.0 [ 1] 22 (0x016) ldsfld 04000434 [ 2] 27 (0x01b) stfld 04000439 [000092] -A--G------- * ASG ref [000091] -------N---- +--* FIELD ref _args [000088] ------------ | \--* ADDR byref [000089] -------N---- | \--* LCL_VAR struct V09 tmp5 [000090] ----G------- \--* FIELD ref s_twoArgArray [ 0] 32 (0x020) ret *************** Inline @[000066] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB03 [0002] 1 1 [000..021) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB03 [000..021) (return), preds={} succs={} ***** BB03 [000077] -A---------- * ASG ref [000076] -------N---- +--* FIELD ref _arg0 [000073] ------------ | \--* ADDR byref [000074] -------N---- | \--* LCL_VAR struct V09 tmp5 [000075] ------------ \--* LCL_VAR ref V10 tmp6 ***** BB03 [000082] -A---------- * ASG ref [000081] -------N---- +--* FIELD ref _arg1 [000078] ------------ | \--* ADDR byref [000079] -------N---- | \--* LCL_VAR struct V09 tmp5 [000080] ------------ \--* LCL_VAR ref V11 tmp7 ***** BB03 [000087] -A---------- * ASG ref [000086] -------N---- +--* FIELD ref _arg2 [000083] ------------ | \--* ADDR byref [000084] -------N---- | \--* LCL_VAR struct V09 tmp5 [000085] ------------ \--* CNS_INT ref null ***** BB03 [000092] -A--G------- * ASG ref [000091] -------N---- +--* FIELD ref _args [000088] ------------ | \--* ADDR byref [000089] -------N---- | \--* LCL_VAR struct V09 tmp5 [000090] ----G------- \--* FIELD ref s_twoArgArray ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000066] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000066] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000066] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000066] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000066] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000066] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000066] ----------- Arguments setup: Inlinee method body: STMT00012 (IL ???... ???) [000077] -A---------- * ASG ref [000076] -------N---- +--* FIELD ref _arg0 [000073] ------------ | \--* ADDR byref [000074] -------N---- | \--* LCL_VAR struct V09 tmp5 [000014] ------------ \--* BOX ref [000013] ------------ \--* LCL_VAR ref V05 tmp1 STMT00013 (IL ???... ???) [000082] -A---------- * ASG ref [000081] -------N---- +--* FIELD ref _arg1 [000078] ------------ | \--* ADDR byref [000079] -------N---- | \--* LCL_VAR struct V09 tmp5 [000028] ------------ \--* BOX ref [000027] ------------ \--* LCL_VAR ref V06 tmp2 STMT00014 (IL ???... ???) [000087] -A---------- * ASG ref [000086] -------N---- +--* FIELD ref _arg2 [000083] ------------ | \--* ADDR byref [000084] -------N---- | \--* LCL_VAR struct V09 tmp5 [000085] ------------ \--* CNS_INT ref null STMT00015 (IL ???... ???) [000092] -A--G------- * ASG ref [000091] -------N---- +--* FIELD ref _args [000088] ------------ | \--* ADDR byref [000089] -------N---- | \--* LCL_VAR struct V09 tmp5 [000090] ----G------- \--* FIELD ref s_twoArgArray fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.ParamsArray:.ctor(System.Object,System.Object):this (33 IL bytes) (depth 2) [profitable inline] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'profitable inline' for 'Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' calling 'System.ParamsArray:.ctor(System.Object,System.Object):this' INLINER: during 'fgInline' result 'success' reason 'profitable inline' Expanding INLINE_CANDIDATE in statement STMT00011 in BB01: STMT00011 (IL ???... ???) [000068] I-C-G------- * CALL ref System.String.FormatHelper (exactContextHnd=0x00007F6678C469A9) [000060] ------------ arg0 +--* CNS_INT ref null [000061] ------------ arg1 +--* CNS_STR ref [000070] n----------- arg2 \--* OBJ struct [000069] ------------ \--* ADDR byref [000067] -------N---- \--* LCL_VAR struct V09 tmp5 Argument #0: is a constant [000060] ------------ * CNS_INT ref null Argument #1: is a constant [000061] ------------ * CNS_STR ref Argument #2: [000070] n----------- * OBJ struct [000069] ------------ \--* ADDR byref [000067] -------N---- \--* LCL_VAR struct V09 tmp5 INLINER: inlineInfo.tokenLookupContextHandle for System.String:FormatHelper(System.IFormatProvider,System.String,System.ParamsArray):System.String set to 0x00007F6678C469A9: Invoking compiler for the inlinee method System.String:FormatHelper(System.IFormatProvider,System.String,System.ParamsArray):System.String : IL to import: IL_0000 03 ldarg.1 IL_0001 2d 0b brtrue.s 11 (IL_000e) IL_0003 72 d5 08 00 70 ldstr 0x700008D5 IL_0008 73 db 09 00 06 newobj 0x60009DB IL_000d 7a throw IL_000e 20 00 02 00 00 ldc.i4 0x200 IL_0013 e0 conv.u IL_0014 fe 0f localloc IL_0016 20 00 01 00 00 ldc.i4 0x100 IL_001b 73 01 00 00 0a newobj 0xA000001 IL_0020 0b stloc.1 IL_0021 12 00 ldloca.s 0x0 IL_0023 07 ldloc.1 IL_0024 28 b4 2f 00 06 call 0x6002FB4 IL_0029 12 00 ldloca.s 0x0 IL_002b 03 ldarg.1 IL_002c 6f 50 06 00 06 callvirt 0x6000650 IL_0031 0f 02 ldarga.s 0x2 IL_0033 28 15 12 00 06 call 0x6001215 IL_0038 1e ldc.i4.8 IL_0039 5a mul IL_003a 58 add IL_003b 28 b8 2f 00 06 call 0x6002FB8 IL_0040 12 00 ldloca.s 0x0 IL_0042 02 ldarg.0 IL_0043 03 ldarg.1 IL_0044 04 ldarg.2 IL_0045 28 b2 2f 00 06 call 0x6002FB2 IL_004a 12 00 ldloca.s 0x0 IL_004c fe 16 70 03 00 02 constrained. 0x2000370 IL_0052 6f 63 04 00 06 callvirt 0x6000463 IL_0057 2a ret INLINER impTokenLookupContextHandle for System.String:FormatHelper(System.IFormatProvider,System.String,System.ParamsArray):System.String is 0x00007F6678C469A9. *************** In fgFindBasicBlocks() for System.String:FormatHelper(System.IFormatProvider,System.String,System.ParamsArray):System.String weight= 16 : state 4 [ ldarg.1 ] weight= 25 : state 45 [ brtrue.s ] weight= 66 : state 102 [ ldstr ] weight=227 : state 103 [ newobj ] weight=210 : state 108 [ throw ] weight= 38 : state 33 [ ldc.i4 ] weight=-36 : state 165 [ conv.u ] weight=347 : state 176 [ localloc ] weight= 38 : state 33 [ ldc.i4 ] weight=227 : state 103 [ newobj ] weight= 34 : state 12 [ stloc.1 ] weight= 61 : state 19 [ ldloca.s ] weight= 9 : state 8 [ ldloc.1 ] weight= 79 : state 40 [ call ] weight= 61 : state 19 [ ldloca.s ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight= 77 : state 16 [ ldarga.s ] weight= 79 : state 40 [ call ] weight= 42 : state 31 [ ldc.i4.8 ] weight= -9 : state 78 [ mul ] weight=-12 : state 76 [ add ] weight= 79 : state 40 [ call ] weight= 61 : state 19 [ ldloca.s ] weight= 10 : state 3 [ ldarg.0 ] weight= 16 : state 4 [ ldarg.1 ] weight= 35 : state 5 [ ldarg.2 ] weight= 79 : state 40 [ call ] weight= 61 : state 19 [ ldloca.s ] weight=161 : state 190 [ constrained -> callvirt ] weight= 19 : state 42 [ ret ] Inline candidate looks like a wrapper method. Multiplier increased to 1. Inline candidate has an arg that feeds a constant test. Multiplier increased to 2. Inline candidate has const arg that feeds a conditional. Multiplier increased to 5. Inline candidate callsite is boring. Multiplier increased to 6.3. calleeNativeSizeEstimate=2199 callsiteNativeSizeEstimate=205 benefit multiplier=6.3 threshold=1291 Native estimate for function size exceeds threshold for inlining 219.9 > 129.1 (multiplier = 6.3) Inline expansion aborted, inline not profitable Inlining [000068] failed, so bashing STMT00011 to NOP INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' calling 'System.String:FormatHelper(System.IFormatProvider,System.String,System.ParamsArray):System.String' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Expanding INLINE_CANDIDATE in statement STMT00005 in BB01: STMT00005 (IL ???... ???) [000031] I-C-G------- * CALL void UnityEngine.Debug.Log (exactContextHnd=0x00007F66798F3CD1) [000030] --C--------- arg0 \--* RET_EXPR ref (inl return from call [000071]) Argument #0: has global refs has side effects [000068] --C-G------- * CALL ref System.String.FormatHelper [000060] ------------ arg0 +--* CNS_INT ref null [000061] ------------ arg1 +--* CNS_STR ref [000070] n----------- arg2 \--* OBJ struct [000069] ------------ \--* ADDR byref [000067] -------N---- \--* LCL_VAR struct V09 tmp5 INLINER: inlineInfo.tokenLookupContextHandle for UnityEngine.Debug:Log(System.Object) set to 0x00007F66798F3CD1: Invoking compiler for the inlinee method UnityEngine.Debug:Log(System.Object) : IL to import: IL_0000 19 ldc.i4.3 IL_0001 02 ldarg.0 IL_0002 28 09 00 00 06 call 0x6000009 IL_0007 2a ret INLINER impTokenLookupContextHandle for UnityEngine.Debug:Log(System.Object) is 0x00007F66798F3CD1. *************** In fgFindBasicBlocks() for UnityEngine.Debug:Log(System.Object) Jump targets: none New Basic Block BB04 [0003] created. BB04 [000..008) Basic block list for 'UnityEngine.Debug:Log(System.Object)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB04 [0003] 1 1 [000..008) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000031] Starting PHASE Pre-import *************** Inline @[000031] Finishing PHASE Pre-import *************** Inline @[000031] Starting PHASE Importation *************** In impImport() for UnityEngine.Debug:Log(System.Object) impImportBlockPending for BB04 Importing BB04 (PC=000) of 'UnityEngine.Debug:Log(System.Object)' [ 0] 0 (0x000) ldc.i4.3 3 [ 1] 1 (0x001) ldarg.0 lvaGrabTemp returning 12 (V12 tmp8) called for Inlining Arg. Marked V12 as a single def temp lvaSetClass: setting class for V12 to (00007F6678C469A8) System.String [ 2] 2 (0x002) call 06000009 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000097] I-C-G------- * CALL void UnityEngine.Debug.ProcessAndLogInternal (exactContextHnd=0x00007F66798F3CD1) [000095] ------------ arg0 +--* CNS_INT int 3 [000096] ------------ arg1 \--* LCL_VAR ref V12 tmp8 [ 0] 7 (0x007) ret *************** Inline @[000031] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB04 [0003] 1 1 [000..008) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB04 [000..008) (return), preds={} succs={} ***** BB04 [000097] I-C-G------- * CALL void UnityEngine.Debug.ProcessAndLogInternal (exactContextHnd=0x00007F66798F3CD1) [000095] ------------ arg0 +--* CNS_INT int 3 [000096] ------------ arg1 \--* LCL_VAR ref V12 tmp8 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000031] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000031] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000031] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000031] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000031] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000031] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000031] ----------- Arguments setup: STMT00017 (IL ???... ???) [000099] -AC-G------- * ASG ref [000098] D------N---- +--* LCL_VAR ref V12 tmp8 [000068] --C-G------- \--* CALL ref System.String.FormatHelper [000060] ------------ arg0 +--* CNS_INT ref null [000061] ------------ arg1 +--* CNS_STR ref [000070] n----------- arg2 \--* OBJ struct [000069] ------------ \--* ADDR byref [000067] -------N---- \--* LCL_VAR struct V09 tmp5 Inlinee method body: STMT00016 (IL ???... ???) [000097] I-C-G------- * CALL void UnityEngine.Debug.ProcessAndLogInternal (exactContextHnd=0x00007F66798F3CD1) [000095] ------------ arg0 +--* CNS_INT int 3 [000096] ------------ arg1 \--* LCL_VAR ref V12 tmp8 fgInlineAppendStatements: no gc ref inline locals. Successfully inlined UnityEngine.Debug:Log(System.Object) (8 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' calling 'UnityEngine.Debug:Log(System.Object)' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement STMT00016 in BB01: STMT00016 (IL ???... ???) [000097] I-C-G------- * CALL void UnityEngine.Debug.ProcessAndLogInternal (exactContextHnd=0x00007F66798F3CD1) [000095] ------------ arg0 +--* CNS_INT int 3 [000096] ------------ arg1 \--* LCL_VAR ref V12 tmp8 Argument #0: is a constant [000095] ------------ * CNS_INT int 3 Argument #1: is a local var [000096] ------------ * LCL_VAR ref V12 tmp8 INLINER: inlineInfo.tokenLookupContextHandle for UnityEngine.Debug:ProcessAndLogInternal(int,System.Object) set to 0x00007F66798F3CD1: Invoking compiler for the inlinee method UnityEngine.Debug:ProcessAndLogInternal(int,System.Object) : IL to import: IL_0000 03 ldarg.1 IL_0001 12 00 ldloca.s 0x0 IL_0003 12 01 ldloca.s 0x1 IL_0005 28 08 00 00 06 call 0x6000008 IL_000a 02 ldarg.0 IL_000b 06 ldloc.0 IL_000c 28 24 00 00 06 call 0x6000024 IL_0011 07 ldloc.1 IL_0012 02 ldarg.0 IL_0013 28 cb 01 00 06 call 0x60001CB IL_0018 06 ldloc.0 IL_0019 28 0f 00 00 0a call 0xA00000F IL_001e 2a ret INLINER impTokenLookupContextHandle for UnityEngine.Debug:ProcessAndLogInternal(int,System.Object) is 0x00007F66798F3CD1. *************** In fgFindBasicBlocks() for UnityEngine.Debug:ProcessAndLogInternal(int,System.Object) weight= 16 : state 4 [ ldarg.1 ] weight= 61 : state 19 [ ldloca.s ] weight= 61 : state 19 [ ldloca.s ] weight= 79 : state 40 [ call ] weight= 10 : state 3 [ ldarg.0 ] weight= 12 : state 7 [ ldloc.0 ] weight= 79 : state 40 [ call ] weight= 9 : state 8 [ ldloc.1 ] weight= 10 : state 3 [ ldarg.0 ] weight= 79 : state 40 [ call ] weight= 12 : state 7 [ ldloc.0 ] weight= 79 : state 40 [ call ] weight= 19 : state 42 [ ret ] Inline candidate looks like a wrapper method. Multiplier increased to 1. Inline candidate callsite is boring. Multiplier increased to 2.3. calleeNativeSizeEstimate=526 callsiteNativeSizeEstimate=115 benefit multiplier=2.3 threshold=264 Native estimate for function size exceeds threshold for inlining 52.6 > 26.4 (multiplier = 2.3) Inline expansion aborted, inline not profitable INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' calling 'UnityEngine.Debug:ProcessAndLogInternal(int,System.Object)' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' **************** Inline Tree Inlines into 06000102 Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this [1 IL=0027 TR=000029 060006D8] [below ALWAYS_INLINE size] System.String:Format(System.String,System.Object,System.Object):System.String [2 IL=0004 TR=000066 06001212] [profitable inline] System.ParamsArray:.ctor(System.Object,System.Object):this [0 IL=0009 TR=000068 060006DF] [FAILED: unprofitable inline] System.String:FormatHelper(System.IFormatProvider,System.String,System.ParamsArray):System.String [3 IL=0032 TR=000031 0600000A] [below ALWAYS_INLINE size] UnityEngine.Debug:Log(System.Object) [0 IL=0002 TR=000097 06000009] [FAILED: unprofitable inline] UnityEngine.Debug:ProcessAndLogInternal(int,System.Object) [0 IL=0009 TR=000068 060006DF] [FAILED: unprofitable inline] System.String:FormatHelper(System.IFormatProvider,System.String,System.ParamsArray):System.String [0 IL=0073 TR=000054 06000133] [FAILED: too many il bytes] Unity.Jobs.IJobExtensions:Schedule(FlushSendJob,Unity.Jobs.JobHandle):Unity.Jobs.JobHandle Budget: initialTime=297, finalTime=367, initialBudget=2970, currentBudget=2970 Budget: initialSize=1932, finalSize=2221 *************** Finishing PHASE Morph - Inlining Trees after Morph - Inlining ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} ***** BB01 STMT00000 (IL 0x000...0x028) [000007] -A---------- * ASG ref [000006] D------N---- +--* LCL_VAR ref V05 tmp1 [000005] ------------ \--* ALLOCOBJ ref [000004] ------------ \--* CNS_INT(h) long 0x7f6678beb1c0 class ***** BB01 STMT00001 (IL ???... ???) [000012] -A--G------- * ASG int [000011] -------N---- +--* IND int [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V05 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ----G------- \--* FIELD int Version [000002] ------------ \--* ADDR byref [000001] -------N---- \--* LCL_VAR struct V02 arg2 ***** BB01 STMT00002 (IL ???... ???) [000021] -A---------- * ASG ref [000020] D------N---- +--* LCL_VAR ref V06 tmp2 [000019] ------------ \--* ALLOCOBJ ref [000018] ------------ \--* CNS_INT(h) long 0x7f6678c127f0 class ***** BB01 STMT00003 (IL ???... ???) [000026] -A--G------- * ASG long [000025] -------N---- +--* IND long [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V06 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ----G------- \--* FIELD long JobGroup [000016] ------------ \--* ADDR byref [000015] -------N---- \--* LCL_VAR struct V02 arg2 ***** BB01 STMT00012 (IL ???... ???) [000077] -A---------- * ASG ref [000076] -------N---- +--* FIELD ref _arg0 [000073] ------------ | \--* ADDR byref [000074] -------N---- | \--* LCL_VAR struct V09 tmp5 [000014] ------------ \--* BOX ref [000013] ------------ \--* LCL_VAR ref V05 tmp1 ***** BB01 STMT00013 (IL ???... ???) [000082] -A---------- * ASG ref [000081] -------N---- +--* FIELD ref _arg1 [000078] ------------ | \--* ADDR byref [000079] -------N---- | \--* LCL_VAR struct V09 tmp5 [000028] ------------ \--* BOX ref [000027] ------------ \--* LCL_VAR ref V06 tmp2 ***** BB01 STMT00014 (IL ???... ???) [000087] -A---------- * ASG ref [000086] -------N---- +--* FIELD ref _arg2 [000083] ------------ | \--* ADDR byref [000084] -------N---- | \--* LCL_VAR struct V09 tmp5 [000085] ------------ \--* CNS_INT ref null ***** BB01 STMT00015 (IL ???... ???) [000092] -A--G------- * ASG ref [000091] -------N---- +--* FIELD ref _args [000088] ------------ | \--* ADDR byref [000089] -------N---- | \--* LCL_VAR struct V09 tmp5 [000090] ----G------- \--* FIELD ref s_twoArgArray ***** BB01 STMT00017 (IL ???... ???) [000099] -AC-G------- * ASG ref [000098] D------N---- +--* LCL_VAR ref V12 tmp8 [000068] --C-G------- \--* CALL ref System.String.FormatHelper [000060] ------------ arg0 +--* CNS_INT ref null [000061] ------------ arg1 +--* CNS_STR ref [000070] n----------- arg2 \--* OBJ struct [000069] ------------ \--* ADDR byref [000067] -------N---- \--* LCL_VAR struct V09 tmp5 ***** BB01 STMT00016 (IL ???... ???) [000097] --C-G------- * CALL void UnityEngine.Debug.ProcessAndLogInternal [000095] ------------ arg0 +--* CNS_INT int 3 [000096] ------------ arg1 \--* LCL_VAR ref V12 tmp8 ***** BB01 STMT00006 (IL 0x025... ???) [000035] IA---------- * ASG struct (init) [000032] D------N---- +--* LCL_VAR struct V03 loc0 [000034] ------------ \--* CNS_INT int 0 ***** BB01 STMT00007 (IL 0x02D...0x035) [000043] -A-XG------- * ASG struct (copy) [000042] ------------ +--* OBJ struct [000041] ------------ | \--* ADDR byref [000040] -------N---- | \--* FIELD struct Baselib [000037] ------------ | \--* ADDR byref [000036] -------N---- | \--* LCL_VAR struct V03 loc0 [000039] ---XG------- \--* FIELD struct m_Baselib [000038] ------------ \--* LCL_VAR byref V00 this ***** BB01 STMT00008 (IL 0x03A...0x042) [000051] -A-XG------- * ASG struct (copy) [000050] ------------ +--* BLK struct [000049] ------------ | \--* ADDR byref [000048] -------N---- | \--* FIELD struct Tx [000045] ------------ | \--* ADDR byref [000044] -------N---- | \--* LCL_VAR struct V03 loc0 [000047] ---XG------- \--* FIELD struct m_PayloadsTx [000046] ------------ \--* LCL_VAR byref V00 this ***** BB01 STMT00009 (IL 0x047...0x04E) [000059] --C-G------- * RETURN struct [000054] --C-G------- \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA [000058] n----------- arg0 +--* OBJ struct [000057] ------------ | \--* ADDR byref [000052] -------N---- | \--* LCL_VAR struct V03 loc0 [000056] n----------- arg1 \--* OBJ struct [000055] ------------ \--* ADDR byref [000053] -------N---- \--* LCL_VAR struct V02 arg2 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Allocate Objects disabled, punting *************** Finishing PHASE Allocate Objects [no changes] *************** Starting PHASE Morph - Add internal blocks *************** After fgAddInternal() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** Finishing PHASE Morph - Add internal blocks *************** Starting PHASE Remove empty try *************** In fgRemoveEmptyTry() No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty try [no changes] *************** Starting PHASE Remove empty finally No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty finally [no changes] *************** Starting PHASE Merge callfinally chains No EH in this method, nothing to merge. *************** Finishing PHASE Merge callfinally chains [no changes] *************** Starting PHASE Clone finally No EH in this method, no cloning. *************** Finishing PHASE Clone finally [no changes] *************** Starting PHASE Compute preds Renumbering the basic blocks for fgComputePred *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** After renumbering the basic blocks =============== No blocks renumbered! New BlockSet epoch 2, # of blocks (including unused BB00): 2, bitset array size: 1 (short) *************** In fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** After fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Compute preds *************** Starting PHASE Merge throw blocks *************** In fgTailMergeThrows Method does not have multiple noreturn calls. *************** Finishing PHASE Merge throw blocks [no changes] *************** Starting PHASE Update flow graph early pass *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Finishing PHASE Update flow graph early pass *************** Starting PHASE Morph - Promote Structs *************** In fgPromoteStructs() lvaTable before fgPromoteStructs ; Initial local variable assignments ; ; V00 this byref this ; V01 arg1 struct ; V02 arg2 struct ; V03 loc0 struct ld-addr-op ; V04 OutArgs lclBlk "OutgoingArgSpace" ; V05 tmp1 ref class-hnd exact "Single-def Box Helper" ; V06 tmp2 ref class-hnd exact "Single-def Box Helper" ; V07 tmp3 ref class-hnd exact "Inlining Arg" ; V08 tmp4 ref class-hnd exact "Inlining Arg" ; V09 tmp5 struct "NewObj constructor temp" ; V10 tmp6 ref class-hnd exact "Inlining Arg" ; V11 tmp7 ref class-hnd exact "Inlining Arg" ; V12 tmp8 ref class-hnd "Inlining Arg" Not promoting promotable struct local V02, because lvIsParam is true and #fields = 2. Promoting struct local V09 (System.ParamsArray): lvaGrabTemp returning 13 (V13 tmp9) (a long lifetime temp) called for field V09._arg0 (fldOffset=0x0). lvaGrabTemp returning 14 (V14 tmp10) (a long lifetime temp) called for field V09._arg1 (fldOffset=0x8). lvaGrabTemp returning 15 (V15 tmp11) (a long lifetime temp) called for field V09._arg2 (fldOffset=0x10). lvaGrabTemp returning 16 (V16 tmp12) (a long lifetime temp) called for field V09._args (fldOffset=0x18). lvaTable after fgPromoteStructs ; Initial local variable assignments ; ; V00 this byref this ; V01 arg1 struct ; V02 arg2 struct ; V03 loc0 struct ld-addr-op ; V04 OutArgs lclBlk "OutgoingArgSpace" ; V05 tmp1 ref class-hnd exact "Single-def Box Helper" ; V06 tmp2 ref class-hnd exact "Single-def Box Helper" ; V07 tmp3 ref class-hnd exact "Inlining Arg" ; V08 tmp4 ref class-hnd exact "Inlining Arg" ; V09 tmp5 struct "NewObj constructor temp" ; V10 tmp6 ref class-hnd exact "Inlining Arg" ; V11 tmp7 ref class-hnd exact "Inlining Arg" ; V12 tmp8 ref class-hnd "Inlining Arg" ; V13 tmp9 ref V09._arg0(offs=0x00) P-INDEP "field V09._arg0 (fldOffset=0x0)" ; V14 tmp10 ref V09._arg1(offs=0x08) P-INDEP "field V09._arg1 (fldOffset=0x8)" ; V15 tmp11 ref V09._arg2(offs=0x10) P-INDEP "field V09._arg2 (fldOffset=0x10)" ; V16 tmp12 ref V09._args(offs=0x18) P-INDEP "field V09._args (fldOffset=0x18)" *************** Finishing PHASE Morph - Promote Structs *************** Starting PHASE Morph - Structs/AddrExp *************** In fgMarkAddressExposedLocals() LocalAddressVisitor visiting statement: STMT00000 (IL 0x000...0x028) [000007] -AC--------- * ASG ref [000006] D------N---- +--* LCL_VAR ref V05 tmp1 [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000004] ------------ arg0 \--* CNS_INT(h) long 0x7f6678beb1c0 class LocalAddressVisitor visiting statement: STMT00001 (IL ???... ???) [000012] -A--G------- * ASG int [000011] -------N---- +--* IND int [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V05 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ----G------- \--* FIELD int Version [000002] ------------ \--* ADDR byref [000001] -------N---- \--* LCL_VAR struct V02 arg2 Local V02 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00001 (IL ???... ???) [000012] -A--G------- * ASG int [000011] -------N---- +--* IND int [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V05 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ------------ \--* LCL_FLD int V02 arg2 [+8] Fseq[Version] LocalAddressVisitor visiting statement: STMT00002 (IL ???... ???) [000021] -AC--------- * ASG ref [000020] D------N---- +--* LCL_VAR ref V06 tmp2 [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000018] ------------ arg0 \--* CNS_INT(h) long 0x7f6678c127f0 class LocalAddressVisitor visiting statement: STMT00003 (IL ???... ???) [000026] -A--G------- * ASG long [000025] -------N---- +--* IND long [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V06 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ----G------- \--* FIELD long JobGroup [000016] ------------ \--* ADDR byref [000015] -------N---- \--* LCL_VAR struct V02 arg2 Local V02 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00003 (IL ???... ???) [000026] -A--G------- * ASG long [000025] -------N---- +--* IND long [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V06 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ------------ \--* LCL_FLD long V02 arg2 [+0] Fseq[JobGroup] LocalAddressVisitor visiting statement: STMT00012 (IL ???... ???) [000077] -A---------- * ASG ref [000076] -------N---- +--* FIELD ref _arg0 [000073] ------------ | \--* ADDR byref [000074] -------N---- | \--* LCL_VAR struct(P) V09 tmp5 | \--* ref V09._arg0 (offs=0x00) -> V13 tmp9 | \--* ref V09._arg1 (offs=0x08) -> V14 tmp10 | \--* ref V09._arg2 (offs=0x10) -> V15 tmp11 | \--* ref V09._args (offs=0x18) -> V16 tmp12 [000014] ------------ \--* BOX ref [000013] ------------ \--* LCL_VAR ref V05 tmp1 Replacing the field in promoted struct with local var V13 LocalAddressVisitor modified statement: STMT00012 (IL ???... ???) [000077] -A---------- * ASG ref [000076] D------N---- +--* LCL_VAR ref V13 tmp9 [000014] ------------ \--* BOX ref [000013] ------------ \--* LCL_VAR ref V05 tmp1 LocalAddressVisitor visiting statement: STMT00013 (IL ???... ???) [000082] -A---------- * ASG ref [000081] -------N---- +--* FIELD ref _arg1 [000078] ------------ | \--* ADDR byref [000079] -------N---- | \--* LCL_VAR struct(P) V09 tmp5 | \--* ref V09._arg0 (offs=0x00) -> V13 tmp9 | \--* ref V09._arg1 (offs=0x08) -> V14 tmp10 | \--* ref V09._arg2 (offs=0x10) -> V15 tmp11 | \--* ref V09._args (offs=0x18) -> V16 tmp12 [000028] ------------ \--* BOX ref [000027] ------------ \--* LCL_VAR ref V06 tmp2 Replacing the field in promoted struct with local var V14 LocalAddressVisitor modified statement: STMT00013 (IL ???... ???) [000082] -A---------- * ASG ref [000081] D------N---- +--* LCL_VAR ref V14 tmp10 [000028] ------------ \--* BOX ref [000027] ------------ \--* LCL_VAR ref V06 tmp2 LocalAddressVisitor visiting statement: STMT00014 (IL ???... ???) [000087] -A---------- * ASG ref [000086] -------N---- +--* FIELD ref _arg2 [000083] ------------ | \--* ADDR byref [000084] -------N---- | \--* LCL_VAR struct(P) V09 tmp5 | \--* ref V09._arg0 (offs=0x00) -> V13 tmp9 | \--* ref V09._arg1 (offs=0x08) -> V14 tmp10 | \--* ref V09._arg2 (offs=0x10) -> V15 tmp11 | \--* ref V09._args (offs=0x18) -> V16 tmp12 [000085] ------------ \--* CNS_INT ref null Replacing the field in promoted struct with local var V15 LocalAddressVisitor modified statement: STMT00014 (IL ???... ???) [000087] -A---------- * ASG ref [000086] D------N---- +--* LCL_VAR ref V15 tmp11 [000085] ------------ \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00015 (IL ???... ???) [000092] -A--G------- * ASG ref [000091] -------N---- +--* FIELD ref _args [000088] ------------ | \--* ADDR byref [000089] -------N---- | \--* LCL_VAR struct(P) V09 tmp5 | \--* ref V09._arg0 (offs=0x00) -> V13 tmp9 | \--* ref V09._arg1 (offs=0x08) -> V14 tmp10 | \--* ref V09._arg2 (offs=0x10) -> V15 tmp11 | \--* ref V09._args (offs=0x18) -> V16 tmp12 [000090] ----G------- \--* FIELD ref s_twoArgArray Replacing the field in promoted struct with local var V16 LocalAddressVisitor modified statement: STMT00015 (IL ???... ???) [000092] -A--G------- * ASG ref [000091] D------N---- +--* LCL_VAR ref V16 tmp12 [000090] ----G------- \--* FIELD ref s_twoArgArray LocalAddressVisitor visiting statement: STMT00017 (IL ???... ???) [000099] -AC-G------- * ASG ref [000098] D------N---- +--* LCL_VAR ref V12 tmp8 [000068] --C-G------- \--* CALL ref System.String.FormatHelper [000060] ------------ arg0 +--* CNS_INT ref null [000061] ------------ arg1 +--* CNS_STR ref [000070] n----------- arg2 \--* OBJ struct [000069] ------------ \--* ADDR byref [000067] -------N---- \--* LCL_VAR struct(P) V09 tmp5 \--* ref V09._arg0 (offs=0x00) -> V13 tmp9 \--* ref V09._arg1 (offs=0x08) -> V14 tmp10 \--* ref V09._arg2 (offs=0x10) -> V15 tmp11 \--* ref V09._args (offs=0x18) -> V16 tmp12 LocalAddressVisitor visiting statement: STMT00016 (IL ???... ???) [000097] --C-G------- * CALL void UnityEngine.Debug.ProcessAndLogInternal [000095] ------------ arg0 +--* CNS_INT int 3 [000096] ------------ arg1 \--* LCL_VAR ref V12 tmp8 LocalAddressVisitor visiting statement: STMT00006 (IL 0x025... ???) [000035] IA---------- * ASG struct (init) [000032] D------N---- +--* LCL_VAR struct V03 loc0 [000034] ------------ \--* CNS_INT int 0 LocalAddressVisitor visiting statement: STMT00007 (IL 0x02D...0x035) [000043] -A-XG------- * ASG struct (copy) [000042] ------------ +--* OBJ struct [000041] ------------ | \--* ADDR byref [000040] -------N---- | \--* FIELD struct Baselib [000037] ------------ | \--* ADDR byref [000036] -------N---- | \--* LCL_VAR struct V03 loc0 [000039] ---XG------- \--* FIELD struct m_Baselib [000038] ------------ \--* LCL_VAR byref V00 this LocalAddressVisitor visiting statement: STMT00008 (IL 0x03A...0x042) [000051] -A-XG------- * ASG struct (copy) [000050] ------------ +--* BLK struct [000049] ------------ | \--* ADDR byref [000048] -------N---- | \--* FIELD struct Tx [000045] ------------ | \--* ADDR byref [000044] -------N---- | \--* LCL_VAR struct V03 loc0 [000047] ---XG------- \--* FIELD struct m_PayloadsTx [000046] ------------ \--* LCL_VAR byref V00 this LocalAddressVisitor visiting statement: STMT00009 (IL 0x047...0x04E) [000059] --C-G------- * RETURN struct [000054] --C-G------- \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA [000058] n----------- arg0 +--* OBJ struct [000057] ------------ | \--* ADDR byref [000052] -------N---- | \--* LCL_VAR struct V03 loc0 [000056] n----------- arg1 \--* OBJ struct [000055] ------------ \--* ADDR byref [000053] -------N---- \--* LCL_VAR struct V02 arg2 *************** Finishing PHASE Morph - Structs/AddrExp *************** Starting PHASE Morph - ByRefs *************** Finishing PHASE Morph - ByRefs *************** Starting PHASE Morph - Global *************** In fgMorphBlocks() Morphing BB01 of 'Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' fgMorphTree BB01, STMT00000 (before) [000007] -AC--------- * ASG ref [000006] D------N---- +--* LCL_VAR ref V05 tmp1 [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000004] ------------ arg0 \--* CNS_INT(h) long 0x7f6678beb1c0 class Initializing arg info for 5.CALL: ArgTable for 5.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 4.CNS_INT long (By ref), 1 reg: rdi, align=1] Morphing args for 5.CALL: argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000004] -----+------ * CNS_INT(h) long 0x7f6678beb1c0 class Replaced with placeholder node: [000101] ----------L- * ARGPLACE long Shuffled argument table: rdi ArgTable for 5.CALL after fgMorphArgs: fgArgTabEntry[arg 0 4.CNS_INT long (By ref), 1 reg: rdi, align=1, lateArgInx=0, processed] fgMorphTree BB01, STMT00000 (after) [000007] -AC--+------ * ASG ref [000006] D----+-N---- +--* LCL_VAR ref V05 tmp1 [000005] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000004] -----+------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class fgMorphTree BB01, STMT00001 (before) [000012] -A--G------- * ASG int [000011] -------N---- +--* IND int [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V05 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ------------ \--* LCL_FLD int V02 arg2 [+8] Fseq[Version] GenTreeNode creates assertion: [000011] ---X---N---- * IND int In BB01 New Local Constant Assertion: V05 != null index=#01, mask= fgMorphTree BB01, STMT00002 (before) [000021] -AC--------- * ASG ref [000020] D------N---- +--* LCL_VAR ref V06 tmp2 [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000018] ------------ arg0 \--* CNS_INT(h) long 0x7f6678c127f0 class Initializing arg info for 19.CALL: ArgTable for 19.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 18.CNS_INT long (By ref), 1 reg: rdi, align=1] Morphing args for 19.CALL: argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000018] -----+------ * CNS_INT(h) long 0x7f6678c127f0 class Replaced with placeholder node: [000102] ----------L- * ARGPLACE long Shuffled argument table: rdi ArgTable for 19.CALL after fgMorphArgs: fgArgTabEntry[arg 0 18.CNS_INT long (By ref), 1 reg: rdi, align=1, lateArgInx=0, processed] fgMorphTree BB01, STMT00002 (after) [000021] -AC--+------ * ASG ref [000020] D----+-N---- +--* LCL_VAR ref V06 tmp2 [000019] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000018] -----+------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class fgMorphTree BB01, STMT00003 (before) [000026] -A--G------- * ASG long [000025] -------N---- +--* IND long [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V06 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ------------ \--* LCL_FLD long V02 arg2 [+0] Fseq[JobGroup] GenTreeNode creates assertion: [000025] ---X---N---- * IND long In BB01 New Local Constant Assertion: V06 != null index=#02, mask= fgMorphTree BB01, STMT00012 (before) [000077] -A---------- * ASG ref [000076] D------N---- +--* LCL_VAR ref V13 tmp9 [000014] ------------ \--* BOX ref [000013] ------------ \--* LCL_VAR ref V05 tmp1 fgMorphTree BB01, STMT00013 (before) [000082] -A---------- * ASG ref [000081] D------N---- +--* LCL_VAR ref V14 tmp10 [000028] ------------ \--* BOX ref [000027] ------------ \--* LCL_VAR ref V06 tmp2 fgMorphTree BB01, STMT00014 (before) [000087] -A---------- * ASG ref [000086] D------N---- +--* LCL_VAR ref V15 tmp11 [000085] ------------ \--* CNS_INT ref null GenTreeNode creates assertion: [000087] -A---------- * ASG ref In BB01 New Local Constant Assertion: V15 == null index=#03, mask= fgMorphTree BB01, STMT00015 (before) [000092] -A--G------- * ASG ref [000091] D------N---- +--* LCL_VAR ref V16 tmp12 [000090] ----G------- \--* FIELD ref s_twoArgArray fgMorphTree BB01, STMT00015 (after) [000092] -A--G+------ * ASG ref [000091] D----+-N---- +--* LCL_VAR ref V16 tmp12 [000090] n---G+------ \--* IND ref [000103] -----+------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] fgMorphTree BB01, STMT00017 (before) [000099] -AC-G------- * ASG ref [000098] D------N---- +--* LCL_VAR ref V12 tmp8 [000068] --C-G------- \--* CALL ref System.String.FormatHelper [000060] ------------ arg0 +--* CNS_INT ref null [000061] ------------ arg1 +--* CNS_STR ref [000070] n----------- arg2 \--* OBJ struct [000069] ------------ \--* ADDR byref [000067] -------N---- \--* LCL_VAR struct(P) V09 tmp5 \--* ref V09._arg0 (offs=0x00) -> V13 tmp9 \--* ref V09._arg1 (offs=0x08) -> V14 tmp10 \--* ref V09._arg2 (offs=0x10) -> V15 tmp11 \--* ref V09._args (offs=0x18) -> V16 tmp12 Initializing arg info for 68.CALL: **** getSystemVAmd64PassStructInRegisterDescriptor(0x79a59e78 (System.ParamsArray), ...) => passedInRegisters = false **** getSystemVAmd64PassStructInRegisterDescriptor(0x79a59e78 (System.ParamsArray), ...) => passedInRegisters = false ArgTable for 68.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 60.CNS_INT ref (By ref), 1 reg: rdi, align=1] fgArgTabEntry[arg 1 61.CNS_STR ref (By ref), 1 reg: rsi, align=1] fgArgTabEntry[arg 2 70.OBJ struct (By value), numSlots=4, slotNum=0, align=1, isStruct] Morphing args for 68.CALL: argSlots=6, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rsi'): ( 4, 12) [000105] n---G------- * IND ref ( 2, 10) [000104] ------------ \--* CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] Replaced with placeholder node: [000106] ----------L- * ARGPLACE ref Deferred argument ('rdi'): [000060] -----+------ * CNS_INT ref null Replaced with placeholder node: [000107] ----------L- * ARGPLACE ref Shuffled argument table: rsi rdi ArgTable for 68.CALL after fgMorphArgs: fgArgTabEntry[arg 2 108.FIELD_LIST struct (By value), numSlots=4, slotNum=0, align=1, processed, isStruct] fgArgTabEntry[arg 1 105.IND ref (By ref), 1 reg: rsi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 0 60.CNS_INT ref (By ref), 1 reg: rdi, align=1, lateArgInx=1, processed] fgMorphTree BB01, STMT00017 (after) [000099] -ACXG+------ * ASG ref [000098] D----+-N---- +--* LCL_VAR ref V12 tmp8 [000068] --CXG+------ \--* CALL ref System.String.FormatHelper [000108] -c---------- arg2 out+00 +--* FIELD_LIST struct [000109] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp9 [000110] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp10 [000111] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp11 [000112] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp12 ( 4, 12) [000105] n---G------- arg1 in rsi +--* IND ref ( 2, 10) [000104] ------------ | \--* CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] [000060] -----+------ arg0 in rdi \--* CNS_INT ref null fgMorphTree BB01, STMT00016 (before) [000097] --C-G------- * CALL void UnityEngine.Debug.ProcessAndLogInternal [000095] ------------ arg0 +--* CNS_INT int 3 [000096] ------------ arg1 \--* LCL_VAR ref V12 tmp8 Initializing arg info for 97.CALL: ArgTable for 97.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 95.CNS_INT int (By ref), 1 reg: rdi, align=1] fgArgTabEntry[arg 1 96.LCL_VAR ref (By ref), 1 reg: rsi, align=1] Morphing args for 97.CALL: argSlots=2, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rsi'): [000096] -----+------ * LCL_VAR ref V12 tmp8 Replaced with placeholder node: [000113] ----------L- * ARGPLACE ref Deferred argument ('rdi'): [000095] -----+------ * CNS_INT int 3 Replaced with placeholder node: [000114] ----------L- * ARGPLACE int Shuffled argument table: rsi rdi ArgTable for 97.CALL after fgMorphArgs: fgArgTabEntry[arg 1 96.LCL_VAR ref (By ref), 1 reg: rsi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 0 95.CNS_INT int (By ref), 1 reg: rdi, align=1, lateArgInx=1, processed] fgMorphTree BB01, STMT00016 (after) [000097] --CXG+------ * CALL void UnityEngine.Debug.ProcessAndLogInternal [000096] -----+------ arg1 in rsi +--* LCL_VAR ref V12 tmp8 [000095] -----+------ arg0 in rdi \--* CNS_INT int 3 fgMorphTree BB01, STMT00006 (before) [000035] IA---------- * ASG struct (init) [000032] D------N---- +--* LCL_VAR struct V03 loc0 [000034] ------------ \--* CNS_INT int 0 fgMorphBlkNode for dst tree, before: [000032] D----+-N---- * LCL_VAR struct V03 loc0 fgMorphBlkNode after: [000032] D----+-N---- * LCL_VAR struct V03 loc0 fgMorphInitBlock: Local V03 should not be enregistered because: written in a block op GenTreeNode creates assertion: [000035] IA---------- * ASG struct (init) In BB01 New Local Constant Assertion: V03 == 0 index=#04, mask= fgMorphTree BB01, STMT00007 (before) [000043] -A-XG------- * ASG struct (copy) [000042] ------------ +--* OBJ struct [000041] ------------ | \--* ADDR byref [000040] -------N---- | \--* FIELD struct Baselib [000037] ------------ | \--* ADDR byref [000036] -------N---- | \--* LCL_VAR struct V03 loc0 [000039] ---XG------- \--* FIELD struct m_Baselib [000038] ------------ \--* LCL_VAR byref V00 this Local V03 should not be enregistered because: was accessed as a local field Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000036] -----+-N---- * LCL_FLD struct V03 loc0 [+40] Fseq[Baselib] Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000039] *--XG------- * IND struct [000118] -----+------ \--* ADD byref [000038] -----+------ +--* LCL_VAR byref V00 this [000117] -----+------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] fgMorphCopyBlock: fgMorphBlkNode for dst tree, before: [000042] n----+------ * OBJ struct [000041] -----+------ \--* ADDR byref [000036] U----+-N---- \--* LCL_FLD struct V03 loc0 [+40] Fseq[Baselib] fgMorphBlkNode after: [000042] n----+------ * OBJ struct [000041] -----+------ \--* ADDR byref [000036] U----+-N---- \--* LCL_FLD struct V03 loc0 [+40] Fseq[Baselib] fgMorphBlkNode for src tree, before: [000039] *--XG+------ * IND struct [000118] -----+------ \--* ADD byref [000038] -----+------ +--* LCL_VAR byref V00 this [000117] -----+------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] fgMorphBlkNode after: [000039] *--XG+------ * IND struct [000118] -----+------ \--* ADD byref [000038] -----+------ +--* LCL_VAR byref V00 this [000117] -----+------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] block assignment to morph: [000043] -A-XG------- * ASG struct (copy) [000042] n----+------ +--* OBJ struct [000041] -----+------ | \--* ADDR byref [000036] U----+-N---- | \--* LCL_FLD struct V03 loc0 [+40] Fseq[Baselib] [000039] *--XG+------ \--* IND struct [000118] -----+------ \--* ADD byref [000038] -----+------ +--* LCL_VAR byref V00 this [000117] -----+------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] The assignment [000043] using V03 removes: Constant Assertion: V03 == 0 with no promoted structs this requires a CopyBlock. Local V03 should not be enregistered because: written in a block op fgMorphCopyBlock (after): [000043] -A-XG------- * ASG struct (copy) [000042] n----+------ +--* OBJ struct [000041] -----+------ | \--* ADDR byref [000036] U----+-N---- | \--* LCL_FLD struct V03 loc0 [+40] Fseq[Baselib] [000039] *--XG+------ \--* IND struct [000118] -----+------ \--* ADD byref [000038] -----+------ +--* LCL_VAR byref V00 this [000117] -----+------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] fgMorphTree BB01, STMT00007 (after) [000043] -A-XG+------ * ASG struct (copy) [000042] n----+------ +--* OBJ struct [000041] -----+------ | \--* ADDR byref [000036] U----+-N---- | \--* LCL_FLD struct V03 loc0 [+40] Fseq[Baselib] [000039] *--XG+------ \--* IND struct [000118] -----+------ \--* ADD byref [000038] -----+------ +--* LCL_VAR byref V00 this [000117] -----+------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] fgMorphTree BB01, STMT00008 (before) [000051] -A-XG------- * ASG struct (copy) [000050] ------------ +--* BLK struct [000049] ------------ | \--* ADDR byref [000048] -------N---- | \--* FIELD struct Tx [000045] ------------ | \--* ADDR byref [000044] -------N---- | \--* LCL_VAR struct V03 loc0 [000047] ---XG------- \--* FIELD struct m_PayloadsTx [000046] ------------ \--* LCL_VAR byref V00 this Before calling fgAddFieldSeqForZeroOffset: [000048] *------N---- * IND struct [000045] ------------ \--* ADDR byref [000044] -------N---- \--* LCL_VAR struct V03 loc0 fgAddFieldSeqForZeroOffset for Fseq[Tx] addr (Before) [000045] ------------ ADDR byref (After) [000045] ------------ ADDR byref Zero Fseq[Tx] Local V03 should not be enregistered because: was accessed as a local field Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000044] -----+-N---- * LCL_FLD struct V03 loc0 [+0] Fseq[Tx] Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000047] *--XG------- * IND struct [000120] -----+------ \--* ADD byref [000046] -----+------ +--* LCL_VAR byref V00 this [000119] -----+------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] fgMorphCopyBlock: fgMorphBlkNode for dst tree, before: [000050] n----+------ * BLK struct [000049] -----+------ \--* ADDR byref [000044] U----+-N---- \--* LCL_FLD struct V03 loc0 [+0] Fseq[Tx] fgMorphBlkNode after: [000050] n----+------ * BLK struct [000049] -----+------ \--* ADDR byref [000044] U----+-N---- \--* LCL_FLD struct V03 loc0 [+0] Fseq[Tx] fgMorphBlkNode for src tree, before: [000047] *--XG+------ * IND struct [000120] -----+------ \--* ADD byref [000046] -----+------ +--* LCL_VAR byref V00 this [000119] -----+------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] fgMorphBlkNode after: [000047] *--XG+------ * IND struct [000120] -----+------ \--* ADD byref [000046] -----+------ +--* LCL_VAR byref V00 this [000119] -----+------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] block assignment to morph: [000051] -A-XG------- * ASG struct (copy) [000050] n----+------ +--* BLK struct [000049] -----+------ | \--* ADDR byref [000044] U----+-N---- | \--* LCL_FLD struct V03 loc0 [+0] Fseq[Tx] [000047] *--XG+------ \--* IND struct [000120] -----+------ \--* ADD byref [000046] -----+------ +--* LCL_VAR byref V00 this [000119] -----+------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] with no promoted structs this requires a CopyBlock. Local V03 should not be enregistered because: written in a block op fgMorphCopyBlock (after): [000051] -A-XG------- * ASG struct (copy) [000050] n----+------ +--* BLK struct [000049] -----+------ | \--* ADDR byref [000044] U----+-N---- | \--* LCL_FLD struct V03 loc0 [+0] Fseq[Tx] [000047] *--XG+------ \--* IND struct [000120] -----+------ \--* ADD byref [000046] -----+------ +--* LCL_VAR byref V00 this [000119] -----+------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] fgMorphTree BB01, STMT00008 (after) [000051] -A-XG+------ * ASG struct (copy) [000050] n----+------ +--* BLK struct [000049] -----+------ | \--* ADDR byref [000044] U----+-N---- | \--* LCL_FLD struct V03 loc0 [+0] Fseq[Tx] [000047] *--XG+------ \--* IND struct [000120] -----+------ \--* ADD byref [000046] -----+------ +--* LCL_VAR byref V00 this [000119] -----+------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] fgMorphTree BB01, STMT00009 (before) [000059] --C-G------- * RETURN struct [000054] --C-G------- \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA [000058] n----------- arg0 +--* OBJ struct [000057] ------------ | \--* ADDR byref [000052] -------N---- | \--* LCL_VAR struct V03 loc0 [000056] n----------- arg1 \--* OBJ struct [000055] ------------ \--* ADDR byref [000053] -------N---- \--* LCL_VAR struct V02 arg2 Rejecting tail call in morph for call [000054]: Local address taken V03 lvaGrabTemp returning 17 (V17 tmp13) (a long lifetime temp) called for Return value temp for multi-reg return (rejected tail call).. Initializing arg info for 54.CALL: **** getSystemVAmd64PassStructInRegisterDescriptor(0x7a0b9088 (FlushSendJob), ...) => passedInRegisters = false **** getSystemVAmd64PassStructInRegisterDescriptor(0x7a0b9088 (FlushSendJob), ...) => passedInRegisters = false **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 ArgTable for 54.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 58.OBJ struct (By value), numSlots=12, slotNum=0, align=1, isStruct] fgArgTabEntry[arg 1 56.OBJ struct (By value), 2 regs: rdi rsi, align=1, isStruct] Morphing args for 54.CALL: argSlots=14, preallocatedArgCount=12, nextSlotNum=12, outgoingArgSpaceSize=96 Sorting the arguments: Deferred argument ('rdi'): ( 9, 7) [000056] n----------- * OBJ struct ( 3, 3) [000055] ------------ \--* ADDR byref ( 3, 2) [000053] -------N---- \--* LCL_VAR struct V02 arg2 Replaced with placeholder node: [000123] ----------L- * ARGPLACE struct => [clsHnd=795C7A00] Shuffled argument table: rdi Local V03 should not be enregistered because: it is a struct arg Multireg struct argument V02 : fgArgTabEntry[arg 1 56.OBJ struct (By value), 2 regs: rdi rsi, align=1, lateArgInx=0, processed, isStruct] Local V02 should not be enregistered because: was accessed as a local field Local V02 should not be enregistered because: was accessed as a local field fgMorphMultiregStructArg created tree: [000124] -c---------- * FIELD_LIST struct [000125] ------------ ofs 0 +--* LCL_FLD long V02 arg2 [+0] [000126] ------------ ofs 8 \--* LCL_FLD long V02 arg2 [+8] ArgTable for 54.CALL after fgMorphArgs: fgArgTabEntry[arg 0 58.OBJ struct (By value), numSlots=12, slotNum=0, align=1, processed, isStruct] fgArgTabEntry[arg 1 124.FIELD_LIST struct (By value), 2 regs: rdi rsi, align=1, lateArgInx=0, processed, isStruct] fgMorphCopyBlock: not morphing a multireg call return Inserting assignment of a multi-reg call result to a temp: STMT00018 (IL 0x047... ???) [000122] -ACXG+------ * ASG struct (copy) [000121] D----+-N---- +--* LCL_VAR struct V17 tmp13 [000054] --CXG+------ \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA ( 9, 7) [000058] n----------- arg0 out+00 +--* OBJ struct ( 3, 3) [000057] ------------ | \--* ADDR byref ( 3, 2) [000052] -------N---- | \--* LCL_VAR struct V03 loc0 [000124] -c---------- arg1 rdi,rsi \--* FIELD_LIST struct [000125] ------------ ofs 0 +--* LCL_FLD long V02 arg2 [+0] [000126] ------------ ofs 8 \--* LCL_FLD long V02 arg2 [+8] fgMorphTree BB01, STMT00009 (after) [000059] ----G+------ * RETURN struct [000127] -----+-N---- \--* LCL_VAR struct V17 tmp13 *************** Finishing PHASE Morph - Global Trees after Morph - Global ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} ***** BB01 STMT00000 (IL 0x000...0x028) [000007] -AC--+------ * ASG ref [000006] D----+-N---- +--* LCL_VAR ref V05 tmp1 [000005] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000004] -----+------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class ***** BB01 STMT00001 (IL ???... ???) [000012] -A-XG+------ * ASG int [000011] ---X-+-N---- +--* IND int [000010] -----+------ | \--* ADD byref [000008] -----+------ | +--* LCL_VAR ref V05 tmp1 [000009] -----+------ | \--* CNS_INT long 8 [000003] -----+------ \--* LCL_FLD int V02 arg2 [+8] Fseq[Version] ***** BB01 STMT00002 (IL ???... ???) [000021] -AC--+------ * ASG ref [000020] D----+-N---- +--* LCL_VAR ref V06 tmp2 [000019] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000018] -----+------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class ***** BB01 STMT00003 (IL ???... ???) [000026] -A-XG+------ * ASG long [000025] ---X-+-N---- +--* IND long [000024] -----+------ | \--* ADD byref [000022] -----+------ | +--* LCL_VAR ref V06 tmp2 [000023] -----+------ | \--* CNS_INT long 8 [000017] -----+------ \--* LCL_FLD long V02 arg2 [+0] Fseq[JobGroup] ***** BB01 STMT00012 (IL ???... ???) [000077] -A---+------ * ASG ref [000076] D----+-N---- +--* LCL_VAR ref V13 tmp9 [000014] -----+------ \--* BOX ref [000013] -----+------ \--* LCL_VAR ref V05 tmp1 ***** BB01 STMT00013 (IL ???... ???) [000082] -A---+------ * ASG ref [000081] D----+-N---- +--* LCL_VAR ref V14 tmp10 [000028] -----+------ \--* BOX ref [000027] -----+------ \--* LCL_VAR ref V06 tmp2 ***** BB01 STMT00014 (IL ???... ???) [000087] -A---+------ * ASG ref [000086] D----+-N---- +--* LCL_VAR ref V15 tmp11 [000085] -----+------ \--* CNS_INT ref null ***** BB01 STMT00015 (IL ???... ???) [000092] -A--G+------ * ASG ref [000091] D----+-N---- +--* LCL_VAR ref V16 tmp12 [000090] n---G+------ \--* IND ref [000103] -----+------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] ***** BB01 STMT00017 (IL ???... ???) [000099] -ACXG+------ * ASG ref [000098] D----+-N---- +--* LCL_VAR ref V12 tmp8 [000068] --CXG+------ \--* CALL ref System.String.FormatHelper [000108] -c---------- arg2 out+00 +--* FIELD_LIST struct [000109] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp9 [000110] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp10 [000111] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp11 [000112] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp12 ( 4, 12) [000105] n---G------- arg1 in rsi +--* IND ref ( 2, 10) [000104] ------------ | \--* CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] [000060] -----+------ arg0 in rdi \--* CNS_INT ref null ***** BB01 STMT00016 (IL ???... ???) [000097] --CXG+------ * CALL void UnityEngine.Debug.ProcessAndLogInternal [000096] -----+------ arg1 in rsi +--* LCL_VAR ref V12 tmp8 [000095] -----+------ arg0 in rdi \--* CNS_INT int 3 ***** BB01 STMT00006 (IL 0x025... ???) [000035] IA---+------ * ASG struct (init) [000032] D----+-N---- +--* LCL_VAR struct V03 loc0 [000034] -----+------ \--* CNS_INT int 0 ***** BB01 STMT00007 (IL 0x02D...0x035) [000043] -A-XG+------ * ASG struct (copy) [000042] n----+------ +--* OBJ struct [000041] -----+------ | \--* ADDR byref [000036] U----+-N---- | \--* LCL_FLD struct V03 loc0 [+40] Fseq[Baselib] [000039] *--XG+------ \--* IND struct [000118] -----+------ \--* ADD byref [000038] -----+------ +--* LCL_VAR byref V00 this [000117] -----+------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] ***** BB01 STMT00008 (IL 0x03A...0x042) [000051] -A-XG+------ * ASG struct (copy) [000050] n----+------ +--* BLK struct [000049] -----+------ | \--* ADDR byref [000044] U----+-N---- | \--* LCL_FLD struct V03 loc0 [+0] Fseq[Tx] [000047] *--XG+------ \--* IND struct [000120] -----+------ \--* ADD byref [000046] -----+------ +--* LCL_VAR byref V00 this [000119] -----+------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] ***** BB01 STMT00018 (IL 0x047... ???) [000122] -ACXG+------ * ASG struct (copy) [000121] D----+-N---- +--* LCL_VAR struct V17 tmp13 [000054] --CXG+------ \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA ( 9, 7) [000058] n----------- arg0 out+00 +--* OBJ struct ( 3, 3) [000057] ------------ | \--* ADDR byref ( 3, 2) [000052] -------N---- | \--* LCL_VAR struct V03 loc0 [000124] -c---------- arg1 rdi,rsi \--* FIELD_LIST struct [000125] ------------ ofs 0 +--* LCL_FLD long V02 arg2 [+0] [000126] ------------ ofs 8 \--* LCL_FLD long V02 arg2 [+8] ***** BB01 STMT00009 (IL 0x047...0x04E) [000059] ----G+------ * RETURN struct [000127] -----+-N---- \--* LCL_VAR struct V17 tmp13 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE GS Cookie No GS security needed *************** Finishing PHASE GS Cookie *************** Starting PHASE Mark GC poll blocks *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** After renumbering the basic blocks =============== No blocks renumbered! *************** Finishing PHASE Mark GC poll blocks *************** Starting PHASE Compute edge weights (1, false) *************** In fgComputeBlockAndEdgeWeights() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- -- no profile data, so using default called count fgComputeEdgeWeights() was able to compute exact edge weights for all of the 0 edges, using 1 passes. *************** Finishing PHASE Compute edge weights (1, false) *************** Starting PHASE Create EH funclets *************** In fgCreateFunclets() After fgCreateFunclets() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** Finishing PHASE Create EH funclets *************** Starting PHASE Optimize layout *************** In optOptimizeLayout() *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize layout *************** Starting PHASE Compute blocks reachability *************** In fgComputeReachability *************** In fgDebugCheckBBlist Renumbering the basic blocks for fgComputeReachability pass #1 *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** After renumbering the basic blocks =============== No blocks renumbered! Enter blocks: BB01 After computing reachability sets: ------------------------------------------------ BBnum Reachable by ------------------------------------------------ BB01 : BB01 After computing reachability: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgComputeDoms *************** In fgDebugCheckBBlist Dominator computation start blocks (those blocks with no incoming edges): BB01 ------------------------------------------------ BBnum Dominated by ------------------------------------------------ BB01: BB01 Inside fgBuildDomTree After computing the Dominance Tree: After numbering the dominator tree: BB01: pre=01, post=01 *************** Finishing PHASE Compute blocks reachability *************** Starting PHASE Optimize loops *************** In optOptimizeLoops() *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize loops *************** Starting PHASE Clone loops *************** In optCloneLoops() *************** Finishing PHASE Clone loops *************** Starting PHASE Unroll loops *************** Finishing PHASE Unroll loops *************** Starting PHASE Mark local vars *************** In lvaMarkLocalVars() *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** *** marking local variables in block BB01 (weight=1 ) STMT00000 (IL 0x000...0x028) [000007] -AC--+------ * ASG ref [000006] D----+-N---- +--* LCL_VAR ref V05 tmp1 [000005] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000004] -----+------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class New refCnts for V05: refCnt = 1, refCntWtd = 2 STMT00001 (IL ???... ???) [000012] -A-XG+------ * ASG int [000011] ---X-+-N---- +--* IND int [000010] -----+------ | \--* ADD byref [000008] -----+------ | +--* LCL_VAR ref V05 tmp1 [000009] -----+------ | \--* CNS_INT long 8 [000003] -----+------ \--* LCL_FLD int V02 arg2 [+8] Fseq[Version] New refCnts for V05: refCnt = 2, refCntWtd = 4 New refCnts for V02: refCnt = 1, refCntWtd = 1 STMT00002 (IL ???... ???) [000021] -AC--+------ * ASG ref [000020] D----+-N---- +--* LCL_VAR ref V06 tmp2 [000019] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000018] -----+------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class New refCnts for V06: refCnt = 1, refCntWtd = 2 STMT00003 (IL ???... ???) [000026] -A-XG+------ * ASG long [000025] ---X-+-N---- +--* IND long [000024] -----+------ | \--* ADD byref [000022] -----+------ | +--* LCL_VAR ref V06 tmp2 [000023] -----+------ | \--* CNS_INT long 8 [000017] -----+------ \--* LCL_FLD long V02 arg2 [+0] Fseq[JobGroup] New refCnts for V06: refCnt = 2, refCntWtd = 4 New refCnts for V02: refCnt = 2, refCntWtd = 2 STMT00012 (IL ???... ???) [000077] -A---+------ * ASG ref [000076] D----+-N---- +--* LCL_VAR ref V13 tmp9 [000014] -----+------ \--* BOX ref [000013] -----+------ \--* LCL_VAR ref V05 tmp1 New refCnts for V13: refCnt = 1, refCntWtd = 1 New refCnts for V05: refCnt = 3, refCntWtd = 6 STMT00013 (IL ???... ???) [000082] -A---+------ * ASG ref [000081] D----+-N---- +--* LCL_VAR ref V14 tmp10 [000028] -----+------ \--* BOX ref [000027] -----+------ \--* LCL_VAR ref V06 tmp2 New refCnts for V14: refCnt = 1, refCntWtd = 1 New refCnts for V06: refCnt = 3, refCntWtd = 6 STMT00014 (IL ???... ???) [000087] -A---+------ * ASG ref [000086] D----+-N---- +--* LCL_VAR ref V15 tmp11 [000085] -----+------ \--* CNS_INT ref null New refCnts for V15: refCnt = 1, refCntWtd = 1 STMT00015 (IL ???... ???) [000092] -A--G+------ * ASG ref [000091] D----+-N---- +--* LCL_VAR ref V16 tmp12 [000090] n---G+------ \--* IND ref [000103] -----+------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] New refCnts for V16: refCnt = 1, refCntWtd = 1 STMT00017 (IL ???... ???) [000099] -ACXG+------ * ASG ref [000098] D----+-N---- +--* LCL_VAR ref V12 tmp8 [000068] --CXG+------ \--* CALL ref System.String.FormatHelper [000108] -c---------- arg2 out+00 +--* FIELD_LIST struct [000109] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp9 [000110] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp10 [000111] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp11 [000112] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp12 ( 4, 12) [000105] n---G------- arg1 in rsi +--* IND ref ( 2, 10) [000104] ------------ | \--* CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] [000060] -----+------ arg0 in rdi \--* CNS_INT ref null New refCnts for V12: refCnt = 1, refCntWtd = 2 New refCnts for V13: refCnt = 2, refCntWtd = 2 New refCnts for V14: refCnt = 2, refCntWtd = 2 New refCnts for V15: refCnt = 2, refCntWtd = 2 New refCnts for V16: refCnt = 2, refCntWtd = 2 STMT00016 (IL ???... ???) [000097] --CXG+------ * CALL void UnityEngine.Debug.ProcessAndLogInternal [000096] -----+------ arg1 in rsi +--* LCL_VAR ref V12 tmp8 [000095] -----+------ arg0 in rdi \--* CNS_INT int 3 New refCnts for V12: refCnt = 2, refCntWtd = 4 STMT00006 (IL 0x025... ???) [000035] IA---+------ * ASG struct (init) [000032] D----+-N---- +--* LCL_VAR struct V03 loc0 [000034] -----+------ \--* CNS_INT int 0 New refCnts for V03: refCnt = 1, refCntWtd = 1 STMT00007 (IL 0x02D...0x035) [000043] -A-XG+------ * ASG struct (copy) [000042] n----+------ +--* OBJ struct [000041] -----+------ | \--* ADDR byref [000036] U----+-N---- | \--* LCL_FLD struct V03 loc0 [+40] Fseq[Baselib] [000039] *--XG+------ \--* IND struct [000118] -----+------ \--* ADD byref [000038] -----+------ +--* LCL_VAR byref V00 this [000117] -----+------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] New refCnts for V03: refCnt = 2, refCntWtd = 2 New refCnts for V00: refCnt = 1, refCntWtd = 1 STMT00008 (IL 0x03A...0x042) [000051] -A-XG+------ * ASG struct (copy) [000050] n----+------ +--* BLK struct [000049] -----+------ | \--* ADDR byref [000044] U----+-N---- | \--* LCL_FLD struct V03 loc0 [+0] Fseq[Tx] [000047] *--XG+------ \--* IND struct [000120] -----+------ \--* ADD byref [000046] -----+------ +--* LCL_VAR byref V00 this [000119] -----+------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] New refCnts for V03: refCnt = 3, refCntWtd = 3 New refCnts for V00: refCnt = 2, refCntWtd = 2 STMT00018 (IL 0x047... ???) [000122] -ACXG+------ * ASG struct (copy) [000121] D----+-N---- +--* LCL_VAR struct V17 tmp13 [000054] --CXG+------ \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA ( 9, 7) [000058] n----------- arg0 out+00 +--* OBJ struct ( 3, 3) [000057] ------------ | \--* ADDR byref ( 3, 2) [000052] -------N---- | \--* LCL_VAR struct V03 loc0 [000124] -c---------- arg1 rdi,rsi \--* FIELD_LIST struct [000125] ------------ ofs 0 +--* LCL_FLD long V02 arg2 [+0] [000126] ------------ ofs 8 \--* LCL_FLD long V02 arg2 [+8] New refCnts for V17: refCnt = 1, refCntWtd = 1 New refCnts for V03: refCnt = 4, refCntWtd = 4 New refCnts for V02: refCnt = 3, refCntWtd = 3 New refCnts for V02: refCnt = 4, refCntWtd = 4 STMT00009 (IL 0x047...0x04E) [000059] ----G+------ * RETURN struct [000127] -----+-N---- \--* LCL_VAR struct V17 tmp13 New refCnts for V17: refCnt = 2, refCntWtd = 2 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 3, refCntWtd = 3 New refCnts for V00: refCnt = 4, refCntWtd = 4 New refCnts for V02: refCnt = 5, refCntWtd = 5 New refCnts for V02: refCnt = 6, refCntWtd = 6 *************** In optAddCopies() *************** Finishing PHASE Mark local vars *************** Starting PHASE Optimize bools *************** In optOptimizeBools() *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize bools *************** Starting PHASE Find oper order *************** In fgFindOperOrder() *************** Finishing PHASE Find oper order *************** Starting PHASE Set block order *************** In fgSetBlockOrder() The biggest BB has 13 tree nodes *************** Finishing PHASE Set block order Trees before Build SSA representation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} ***** BB01 STMT00000 (IL 0x000...0x028) N005 ( 16, 16) [000007] -AC-----R--- * ASG ref N004 ( 1, 1) [000006] D------N---- +--* LCL_VAR ref V05 tmp1 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class ***** BB01 STMT00001 (IL ???... ???) N006 ( 8, 9) [000012] -A-XG------- * ASG int N004 ( 4, 4) [000011] ---X---N---- +--* IND int N003 ( 2, 2) [000010] -------N---- | \--* ADD byref N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V05 tmp1 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD int V02 arg2 [+8] Fseq[Version] ***** BB01 STMT00002 (IL ???... ???) N005 ( 16, 16) [000021] -AC-----R--- * ASG ref N004 ( 1, 1) [000020] D------N---- +--* LCL_VAR ref V06 tmp2 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class ***** BB01 STMT00003 (IL ???... ???) N006 ( 8, 9) [000026] -A-XG------- * ASG long N004 ( 4, 4) [000025] ---X---N---- +--* IND long N003 ( 2, 2) [000024] -------N---- | \--* ADD byref N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V06 tmp2 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD long V02 arg2 [+0] Fseq[JobGroup] ***** BB01 STMT00012 (IL ???... ???) N004 ( 11, 8) [000077] -A------R--- * ASG ref N003 ( 3, 2) [000076] D------N---- +--* LCL_VAR ref V13 tmp9 N002 ( 7, 5) [000014] ------------ \--* BOX ref N001 ( 1, 1) [000013] ------------ \--* LCL_VAR ref V05 tmp1 ***** BB01 STMT00013 (IL ???... ???) N004 ( 11, 8) [000082] -A------R--- * ASG ref N003 ( 3, 2) [000081] D------N---- +--* LCL_VAR ref V14 tmp10 N002 ( 7, 5) [000028] ------------ \--* BOX ref N001 ( 1, 1) [000027] ------------ \--* LCL_VAR ref V06 tmp2 ***** BB01 STMT00014 (IL ???... ???) N003 ( 5, 4) [000087] -A------R--- * ASG ref N002 ( 3, 2) [000086] D------N---- +--* LCL_VAR ref V15 tmp11 N001 ( 1, 1) [000085] ------------ \--* CNS_INT ref null ***** BB01 STMT00015 (IL ???... ???) N004 ( 8, 15) [000092] -A--G---R--- * ASG ref N003 ( 3, 2) [000091] D------N---- +--* LCL_VAR ref V16 tmp12 N002 ( 4, 12) [000090] n---G------- \--* IND ref N001 ( 2, 10) [000103] ------------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] ***** BB01 STMT00017 (IL ???... ???) N013 ( 34, 28) [000099] -ACXG---R--- * ASG ref N012 ( 1, 1) [000098] D------N---- +--* LCL_VAR ref V12 tmp8 N011 ( 34, 28) [000068] --CXG------- \--* CALL ref System.String.FormatHelper N007 ( 12, 8) [000108] -c---------- arg2 out+00 +--* FIELD_LIST struct N003 ( 3, 2) [000109] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp9 N004 ( 3, 2) [000110] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp10 N005 ( 3, 2) [000111] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp11 N006 ( 3, 2) [000112] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp12 N009 ( 4, 12) [000105] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000104] ------------ | \--* CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] N010 ( 1, 1) [000060] ------------ arg0 in rdi \--* CNS_INT ref null ***** BB01 STMT00016 (IL ???... ???) N005 ( 16, 9) [000097] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal N003 ( 1, 1) [000096] ------------ arg1 in rsi +--* LCL_VAR ref V12 tmp8 N004 ( 1, 1) [000095] ------------ arg0 in rdi \--* CNS_INT int 3 ***** BB01 STMT00006 (IL 0x025... ???) N003 ( 5, 4) [000035] IA------R--- * ASG struct (init) N002 ( 3, 2) [000032] D------N---- +--* LCL_VAR struct V03 loc0 N001 ( 1, 1) [000034] ------------ \--* CNS_INT int 0 ***** BB01 STMT00007 (IL 0x02D...0x035) N008 ( 16, 15) [000043] -A-XG---R--- * ASG struct (copy) N007 ( 9, 9) [000042] n----------- +--* OBJ struct N006 ( 3, 5) [000041] ------------ | \--* ADDR byref N005 ( 3, 4) [000036] U------N---- | \--* LCL_FLD struct V03 loc0 [+40] Fseq[Baselib] N004 ( 6, 5) [000039] *--XG------- \--* IND struct N003 ( 3, 3) [000118] ------------ \--* ADD byref N001 ( 1, 1) [000038] ------------ +--* LCL_VAR byref V00 this N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] ***** BB01 STMT00008 (IL 0x03A...0x042) N008 ( 13, 13) [000051] -A-XG---R--- * ASG struct (copy) N007 ( 6, 7) [000050] n----------- +--* BLK struct N006 ( 3, 5) [000049] ------------ | \--* ADDR byref N005 ( 3, 4) [000044] U------N---- | \--* LCL_FLD struct V03 loc0 [+0] Fseq[Tx] N004 ( 6, 5) [000047] *--XG------- \--* IND struct N003 ( 3, 3) [000120] ------------ \--* ADD byref N001 ( 1, 1) [000046] ------------ +--* LCL_VAR byref V00 this N002 ( 1, 1) [000119] ------------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] ***** BB01 STMT00018 (IL 0x047... ???) N010 ( 36, 24) [000122] -ACXG---R--- * ASG struct (copy) N009 ( 3, 2) [000121] D------N---- +--* LCL_VAR struct V17 tmp13 N008 ( 32, 21) [000054] --CXG------- \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA N003 ( 9, 7) [000058] n----------- arg0 out+00 +--* OBJ struct N002 ( 3, 3) [000057] ------------ | \--* ADDR byref N001 ( 3, 2) [000052] -------N---- | \--* LCL_VAR struct V03 loc0 N007 ( 6, 8) [000124] -c---------- arg1 rdi,rsi \--* FIELD_LIST struct N005 ( 3, 4) [000125] ------------ ofs 0 +--* LCL_FLD long V02 arg2 [+0] N006 ( 3, 4) [000126] ------------ ofs 8 \--* LCL_FLD long V02 arg2 [+8] ***** BB01 STMT00009 (IL 0x047...0x04E) N002 ( 4, 3) [000059] ----G------- * RETURN struct N001 ( 3, 2) [000127] -------N---- \--* LCL_VAR struct V17 tmp13 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Build SSA representation *************** In SsaBuilder::Build() [SsaBuilder] Max block count is 2. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty [SsaBuilder] Topologically sorted the graph. [SsaBuilder::ComputeImmediateDom] Inside fgBuildDomTree After computing the Dominance Tree: *************** In fgLocalVarLiveness() In fgLocalVarLivenessInit Local V01 should not be enregistered because: it is a struct Local V02 should not be enregistered because: it is a struct Local V03 should not be enregistered because: it is a struct Local V17 should not be enregistered because: it is a struct Tracked variable (11 out of 18) table: V02 arg2 [struct]: refCnt = 6, refCntWtd = 6 V00 this [ byref]: refCnt = 4, refCntWtd = 4 V05 tmp1 [ ref]: refCnt = 3, refCntWtd = 6 V06 tmp2 [ ref]: refCnt = 3, refCntWtd = 6 V03 loc0 [struct]: refCnt = 4, refCntWtd = 4 V12 tmp8 [ ref]: refCnt = 2, refCntWtd = 4 V13 tmp9 [ ref]: refCnt = 2, refCntWtd = 2 V14 tmp10 [ ref]: refCnt = 2, refCntWtd = 2 V15 tmp11 [ ref]: refCnt = 2, refCntWtd = 2 V16 tmp12 [ ref]: refCnt = 2, refCntWtd = 2 V17 tmp13 [struct]: refCnt = 2, refCntWtd = 2 *************** In fgPerBlockLocalVarLiveness() BB01 USE(2)={V02 V00 } + ByrefExposed + GcHeap DEF(9)={ V05 V06 V03 V12 V13 V14 V15 V16 V17} + ByrefExposed* + GcHeap* ** Memory liveness computed, GcHeap states and ByrefExposed states match *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (2)={V02 V00} + ByrefExposed + GcHeap OUT(0)={ } *************** In optRemoveRedundantZeroInits() *************** In SsaBuilder::InsertPhiFunctions() Inserting phi functions: *************** In SsaBuilder::RenameVariables() After fgSsaBuild: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} ***** BB01 STMT00000 (IL 0x000...0x028) N005 ( 16, 16) [000007] -AC-----R--- * ASG ref N004 ( 1, 1) [000006] D------N---- +--* LCL_VAR ref V05 tmp1 d:2 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class ***** BB01 STMT00001 (IL ???... ???) N006 ( 8, 9) [000012] -A-XG------- * ASG int N004 ( 4, 4) [000011] D--X---N---- +--* IND int N003 ( 2, 2) [000010] -------N---- | \--* ADD byref N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V05 tmp1 u:2 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD int V02 arg2 u:1[+8] Fseq[Version] ***** BB01 STMT00002 (IL ???... ???) N005 ( 16, 16) [000021] -AC-----R--- * ASG ref N004 ( 1, 1) [000020] D------N---- +--* LCL_VAR ref V06 tmp2 d:2 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class ***** BB01 STMT00003 (IL ???... ???) N006 ( 8, 9) [000026] -A-XG------- * ASG long N004 ( 4, 4) [000025] D--X---N---- +--* IND long N003 ( 2, 2) [000024] -------N---- | \--* ADD byref N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V06 tmp2 u:2 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD long V02 arg2 u:1[+0] Fseq[JobGroup] ***** BB01 STMT00012 (IL ???... ???) N004 ( 11, 8) [000077] -A------R--- * ASG ref N003 ( 3, 2) [000076] D------N---- +--* LCL_VAR ref V13 tmp9 d:2 N002 ( 7, 5) [000014] ------------ \--* BOX ref N001 ( 1, 1) [000013] ------------ \--* LCL_VAR ref V05 tmp1 u:2 (last use) ***** BB01 STMT00013 (IL ???... ???) N004 ( 11, 8) [000082] -A------R--- * ASG ref N003 ( 3, 2) [000081] D------N---- +--* LCL_VAR ref V14 tmp10 d:2 N002 ( 7, 5) [000028] ------------ \--* BOX ref N001 ( 1, 1) [000027] ------------ \--* LCL_VAR ref V06 tmp2 u:2 (last use) ***** BB01 STMT00014 (IL ???... ???) N003 ( 5, 4) [000087] -A------R--- * ASG ref N002 ( 3, 2) [000086] D------N---- +--* LCL_VAR ref V15 tmp11 d:2 N001 ( 1, 1) [000085] ------------ \--* CNS_INT ref null ***** BB01 STMT00015 (IL ???... ???) N004 ( 8, 15) [000092] -A--G---R--- * ASG ref N003 ( 3, 2) [000091] D------N---- +--* LCL_VAR ref V16 tmp12 d:2 N002 ( 4, 12) [000090] n---G------- \--* IND ref N001 ( 2, 10) [000103] ------------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] ***** BB01 STMT00017 (IL ???... ???) N013 ( 34, 28) [000099] -ACXG---R--- * ASG ref N012 ( 1, 1) [000098] D------N---- +--* LCL_VAR ref V12 tmp8 d:2 N011 ( 34, 28) [000068] --CXG------- \--* CALL ref System.String.FormatHelper N007 ( 12, 8) [000108] -c---------- arg2 out+00 +--* FIELD_LIST struct N003 ( 3, 2) [000109] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp9 u:2 (last use) N004 ( 3, 2) [000110] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp10 u:2 (last use) N005 ( 3, 2) [000111] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp11 u:2 (last use) N006 ( 3, 2) [000112] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp12 u:2 (last use) N009 ( 4, 12) [000105] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000104] ------------ | \--* CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] N010 ( 1, 1) [000060] ------------ arg0 in rdi \--* CNS_INT ref null ***** BB01 STMT00016 (IL ???... ???) N005 ( 16, 9) [000097] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal N003 ( 1, 1) [000096] ------------ arg1 in rsi +--* LCL_VAR ref V12 tmp8 u:2 (last use) N004 ( 1, 1) [000095] ------------ arg0 in rdi \--* CNS_INT int 3 ***** BB01 STMT00006 (IL 0x025... ???) N003 ( 5, 4) [000035] IA------R--- * ASG struct (init) N002 ( 3, 2) [000032] D------N---- +--* LCL_VAR struct V03 loc0 d:2 N001 ( 1, 1) [000034] ------------ \--* CNS_INT int 0 ***** BB01 STMT00007 (IL 0x02D...0x035) N008 ( 16, 15) [000043] -A-XG---R--- * ASG struct (copy) N007 ( 9, 9) [000042] n----------- +--* OBJ struct N006 ( 3, 5) [000041] ------------ | \--* ADDR byref N005 ( 3, 4) [000036] U------N---- | \--* LCL_FLD struct V03 loc0 ud:2->3[+40] Fseq[Baselib] N004 ( 6, 5) [000039] *--XG------- \--* IND struct N003 ( 3, 3) [000118] ------------ \--* ADD byref N001 ( 1, 1) [000038] ------------ +--* LCL_VAR byref V00 this u:1 N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] ***** BB01 STMT00008 (IL 0x03A...0x042) N008 ( 13, 13) [000051] -A-XG---R--- * ASG struct (copy) N007 ( 6, 7) [000050] n----------- +--* BLK struct N006 ( 3, 5) [000049] ------------ | \--* ADDR byref N005 ( 3, 4) [000044] U------N---- | \--* LCL_FLD struct V03 loc0 ud:3->4[+0] Fseq[Tx] N004 ( 6, 5) [000047] *--XG------- \--* IND struct N003 ( 3, 3) [000120] ------------ \--* ADD byref N001 ( 1, 1) [000046] ------------ +--* LCL_VAR byref V00 this u:1 (last use) N002 ( 1, 1) [000119] ------------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] ***** BB01 STMT00018 (IL 0x047... ???) N010 ( 36, 24) [000122] -ACXG---R--- * ASG struct (copy) N009 ( 3, 2) [000121] D------N---- +--* LCL_VAR struct V17 tmp13 d:2 N008 ( 32, 21) [000054] --CXG------- \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA N003 ( 9, 7) [000058] n----------- arg0 out+00 +--* OBJ struct N002 ( 3, 3) [000057] ------------ | \--* ADDR byref N001 ( 3, 2) [000052] -------N---- | \--* LCL_VAR struct V03 loc0 u:4 (last use) N007 ( 6, 8) [000124] -c---------- arg1 rdi,rsi \--* FIELD_LIST struct N005 ( 3, 4) [000125] ------------ ofs 0 +--* LCL_FLD long V02 arg2 u:1[+0] N006 ( 3, 4) [000126] ------------ ofs 8 \--* LCL_FLD long V02 arg2 u:1[+8] (last use) ***** BB01 STMT00009 (IL 0x047...0x04E) N002 ( 4, 3) [000059] ----G------- * RETURN struct N001 ( 3, 2) [000127] -------N---- \--* LCL_VAR struct V17 tmp13 u:2 (last use) ------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Build SSA representation Trees after Build SSA representation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} ***** BB01 STMT00000 (IL 0x000...0x028) N005 ( 16, 16) [000007] -AC-----R--- * ASG ref N004 ( 1, 1) [000006] D------N---- +--* LCL_VAR ref V05 tmp1 d:2 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class ***** BB01 STMT00001 (IL ???... ???) N006 ( 8, 9) [000012] -A-XG------- * ASG int N004 ( 4, 4) [000011] D--X---N---- +--* IND int N003 ( 2, 2) [000010] -------N---- | \--* ADD byref N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V05 tmp1 u:2 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD int V02 arg2 u:1[+8] Fseq[Version] ***** BB01 STMT00002 (IL ???... ???) N005 ( 16, 16) [000021] -AC-----R--- * ASG ref N004 ( 1, 1) [000020] D------N---- +--* LCL_VAR ref V06 tmp2 d:2 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class ***** BB01 STMT00003 (IL ???... ???) N006 ( 8, 9) [000026] -A-XG------- * ASG long N004 ( 4, 4) [000025] D--X---N---- +--* IND long N003 ( 2, 2) [000024] -------N---- | \--* ADD byref N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V06 tmp2 u:2 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD long V02 arg2 u:1[+0] Fseq[JobGroup] ***** BB01 STMT00012 (IL ???... ???) N004 ( 11, 8) [000077] -A------R--- * ASG ref N003 ( 3, 2) [000076] D------N---- +--* LCL_VAR ref V13 tmp9 d:2 N002 ( 7, 5) [000014] ------------ \--* BOX ref N001 ( 1, 1) [000013] ------------ \--* LCL_VAR ref V05 tmp1 u:2 (last use) ***** BB01 STMT00013 (IL ???... ???) N004 ( 11, 8) [000082] -A------R--- * ASG ref N003 ( 3, 2) [000081] D------N---- +--* LCL_VAR ref V14 tmp10 d:2 N002 ( 7, 5) [000028] ------------ \--* BOX ref N001 ( 1, 1) [000027] ------------ \--* LCL_VAR ref V06 tmp2 u:2 (last use) ***** BB01 STMT00014 (IL ???... ???) N003 ( 5, 4) [000087] -A------R--- * ASG ref N002 ( 3, 2) [000086] D------N---- +--* LCL_VAR ref V15 tmp11 d:2 N001 ( 1, 1) [000085] ------------ \--* CNS_INT ref null ***** BB01 STMT00015 (IL ???... ???) N004 ( 8, 15) [000092] -A--G---R--- * ASG ref N003 ( 3, 2) [000091] D------N---- +--* LCL_VAR ref V16 tmp12 d:2 N002 ( 4, 12) [000090] n---G------- \--* IND ref N001 ( 2, 10) [000103] ------------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] ***** BB01 STMT00017 (IL ???... ???) N013 ( 34, 28) [000099] -ACXG---R--- * ASG ref N012 ( 1, 1) [000098] D------N---- +--* LCL_VAR ref V12 tmp8 d:2 N011 ( 34, 28) [000068] --CXG------- \--* CALL ref System.String.FormatHelper N007 ( 12, 8) [000108] -c---------- arg2 out+00 +--* FIELD_LIST struct N003 ( 3, 2) [000109] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp9 u:2 (last use) N004 ( 3, 2) [000110] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp10 u:2 (last use) N005 ( 3, 2) [000111] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp11 u:2 (last use) N006 ( 3, 2) [000112] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp12 u:2 (last use) N009 ( 4, 12) [000105] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000104] ------------ | \--* CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] N010 ( 1, 1) [000060] ------------ arg0 in rdi \--* CNS_INT ref null ***** BB01 STMT00016 (IL ???... ???) N005 ( 16, 9) [000097] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal N003 ( 1, 1) [000096] ------------ arg1 in rsi +--* LCL_VAR ref V12 tmp8 u:2 (last use) N004 ( 1, 1) [000095] ------------ arg0 in rdi \--* CNS_INT int 3 ***** BB01 STMT00006 (IL 0x025... ???) N003 ( 5, 4) [000035] IA------R--- * ASG struct (init) N002 ( 3, 2) [000032] D------N---- +--* LCL_VAR struct V03 loc0 d:2 N001 ( 1, 1) [000034] ------------ \--* CNS_INT int 0 ***** BB01 STMT00007 (IL 0x02D...0x035) N008 ( 16, 15) [000043] -A-XG---R--- * ASG struct (copy) N007 ( 9, 9) [000042] n----------- +--* OBJ struct N006 ( 3, 5) [000041] ------------ | \--* ADDR byref N005 ( 3, 4) [000036] U------N---- | \--* LCL_FLD struct V03 loc0 ud:2->3[+40] Fseq[Baselib] N004 ( 6, 5) [000039] *--XG------- \--* IND struct N003 ( 3, 3) [000118] ------------ \--* ADD byref N001 ( 1, 1) [000038] ------------ +--* LCL_VAR byref V00 this u:1 N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] ***** BB01 STMT00008 (IL 0x03A...0x042) N008 ( 13, 13) [000051] -A-XG---R--- * ASG struct (copy) N007 ( 6, 7) [000050] n----------- +--* BLK struct N006 ( 3, 5) [000049] ------------ | \--* ADDR byref N005 ( 3, 4) [000044] U------N---- | \--* LCL_FLD struct V03 loc0 ud:3->4[+0] Fseq[Tx] N004 ( 6, 5) [000047] *--XG------- \--* IND struct N003 ( 3, 3) [000120] ------------ \--* ADD byref N001 ( 1, 1) [000046] ------------ +--* LCL_VAR byref V00 this u:1 (last use) N002 ( 1, 1) [000119] ------------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] ***** BB01 STMT00018 (IL 0x047... ???) N010 ( 36, 24) [000122] -ACXG---R--- * ASG struct (copy) N009 ( 3, 2) [000121] D------N---- +--* LCL_VAR struct V17 tmp13 d:2 N008 ( 32, 21) [000054] --CXG------- \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA N003 ( 9, 7) [000058] n----------- arg0 out+00 +--* OBJ struct N002 ( 3, 3) [000057] ------------ | \--* ADDR byref N001 ( 3, 2) [000052] -------N---- | \--* LCL_VAR struct V03 loc0 u:4 (last use) N007 ( 6, 8) [000124] -c---------- arg1 rdi,rsi \--* FIELD_LIST struct N005 ( 3, 4) [000125] ------------ ofs 0 +--* LCL_FLD long V02 arg2 u:1[+0] N006 ( 3, 4) [000126] ------------ ofs 8 \--* LCL_FLD long V02 arg2 u:1[+8] (last use) ***** BB01 STMT00009 (IL 0x047...0x04E) N002 ( 4, 3) [000059] ----G------- * RETURN struct N001 ( 3, 2) [000127] -------N---- \--* LCL_VAR struct V17 tmp13 u:2 (last use) ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Early Value Propagation *************** In optEarlyProp() After optEarlyProp: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} ***** BB01 STMT00000 (IL 0x000...0x028) N005 ( 16, 16) [000007] -AC-----R--- * ASG ref N004 ( 1, 1) [000006] D------N---- +--* LCL_VAR ref V05 tmp1 d:2 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class ***** BB01 STMT00001 (IL ???... ???) N006 ( 8, 9) [000012] -A-XG------- * ASG int N004 ( 4, 4) [000011] D--X---N---- +--* IND int N003 ( 2, 2) [000010] -------N---- | \--* ADD byref N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V05 tmp1 u:2 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD int V02 arg2 u:1[+8] Fseq[Version] ***** BB01 STMT00002 (IL ???... ???) N005 ( 16, 16) [000021] -AC-----R--- * ASG ref N004 ( 1, 1) [000020] D------N---- +--* LCL_VAR ref V06 tmp2 d:2 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class ***** BB01 STMT00003 (IL ???... ???) N006 ( 8, 9) [000026] -A-XG------- * ASG long N004 ( 4, 4) [000025] D--X---N---- +--* IND long N003 ( 2, 2) [000024] -------N---- | \--* ADD byref N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V06 tmp2 u:2 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD long V02 arg2 u:1[+0] Fseq[JobGroup] ***** BB01 STMT00012 (IL ???... ???) N004 ( 11, 8) [000077] -A------R--- * ASG ref N003 ( 3, 2) [000076] D------N---- +--* LCL_VAR ref V13 tmp9 d:2 N002 ( 7, 5) [000014] ------------ \--* BOX ref N001 ( 1, 1) [000013] ------------ \--* LCL_VAR ref V05 tmp1 u:2 (last use) ***** BB01 STMT00013 (IL ???... ???) N004 ( 11, 8) [000082] -A------R--- * ASG ref N003 ( 3, 2) [000081] D------N---- +--* LCL_VAR ref V14 tmp10 d:2 N002 ( 7, 5) [000028] ------------ \--* BOX ref N001 ( 1, 1) [000027] ------------ \--* LCL_VAR ref V06 tmp2 u:2 (last use) ***** BB01 STMT00014 (IL ???... ???) N003 ( 5, 4) [000087] -A------R--- * ASG ref N002 ( 3, 2) [000086] D------N---- +--* LCL_VAR ref V15 tmp11 d:2 N001 ( 1, 1) [000085] ------------ \--* CNS_INT ref null ***** BB01 STMT00015 (IL ???... ???) N004 ( 8, 15) [000092] -A--G---R--- * ASG ref N003 ( 3, 2) [000091] D------N---- +--* LCL_VAR ref V16 tmp12 d:2 N002 ( 4, 12) [000090] n---G------- \--* IND ref N001 ( 2, 10) [000103] ------------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] ***** BB01 STMT00017 (IL ???... ???) N013 ( 34, 28) [000099] -ACXG---R--- * ASG ref N012 ( 1, 1) [000098] D------N---- +--* LCL_VAR ref V12 tmp8 d:2 N011 ( 34, 28) [000068] --CXG------- \--* CALL ref System.String.FormatHelper N007 ( 12, 8) [000108] -c---------- arg2 out+00 +--* FIELD_LIST struct N003 ( 3, 2) [000109] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp9 u:2 (last use) N004 ( 3, 2) [000110] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp10 u:2 (last use) N005 ( 3, 2) [000111] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp11 u:2 (last use) N006 ( 3, 2) [000112] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp12 u:2 (last use) N009 ( 4, 12) [000105] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000104] ------------ | \--* CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] N010 ( 1, 1) [000060] ------------ arg0 in rdi \--* CNS_INT ref null ***** BB01 STMT00016 (IL ???... ???) N005 ( 16, 9) [000097] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal N003 ( 1, 1) [000096] ------------ arg1 in rsi +--* LCL_VAR ref V12 tmp8 u:2 (last use) N004 ( 1, 1) [000095] ------------ arg0 in rdi \--* CNS_INT int 3 ***** BB01 STMT00006 (IL 0x025... ???) N003 ( 5, 4) [000035] IA------R--- * ASG struct (init) N002 ( 3, 2) [000032] D------N---- +--* LCL_VAR struct V03 loc0 d:2 N001 ( 1, 1) [000034] ------------ \--* CNS_INT int 0 ***** BB01 STMT00007 (IL 0x02D...0x035) N008 ( 16, 15) [000043] -A-XG---R--- * ASG struct (copy) N007 ( 9, 9) [000042] n----------- +--* OBJ struct N006 ( 3, 5) [000041] ------------ | \--* ADDR byref N005 ( 3, 4) [000036] U------N---- | \--* LCL_FLD struct V03 loc0 ud:2->3[+40] Fseq[Baselib] N004 ( 6, 5) [000039] *--XG------- \--* IND struct N003 ( 3, 3) [000118] ------------ \--* ADD byref N001 ( 1, 1) [000038] ------------ +--* LCL_VAR byref V00 this u:1 N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] ***** BB01 STMT00008 (IL 0x03A...0x042) N008 ( 13, 13) [000051] -A-XG---R--- * ASG struct (copy) N007 ( 6, 7) [000050] n----------- +--* BLK struct N006 ( 3, 5) [000049] ------------ | \--* ADDR byref N005 ( 3, 4) [000044] U------N---- | \--* LCL_FLD struct V03 loc0 ud:3->4[+0] Fseq[Tx] N004 ( 6, 5) [000047] *--XG------- \--* IND struct N003 ( 3, 3) [000120] ------------ \--* ADD byref N001 ( 1, 1) [000046] ------------ +--* LCL_VAR byref V00 this u:1 (last use) N002 ( 1, 1) [000119] ------------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] ***** BB01 STMT00018 (IL 0x047... ???) N010 ( 36, 24) [000122] -ACXG---R--- * ASG struct (copy) N009 ( 3, 2) [000121] D------N---- +--* LCL_VAR struct V17 tmp13 d:2 N008 ( 32, 21) [000054] --CXG------- \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA N003 ( 9, 7) [000058] n----------- arg0 out+00 +--* OBJ struct N002 ( 3, 3) [000057] ------------ | \--* ADDR byref N001 ( 3, 2) [000052] -------N---- | \--* LCL_VAR struct V03 loc0 u:4 (last use) N007 ( 6, 8) [000124] -c---------- arg1 rdi,rsi \--* FIELD_LIST struct N005 ( 3, 4) [000125] ------------ ofs 0 +--* LCL_FLD long V02 arg2 u:1[+0] N006 ( 3, 4) [000126] ------------ ofs 8 \--* LCL_FLD long V02 arg2 u:1[+8] (last use) ***** BB01 STMT00009 (IL 0x047...0x04E) N002 ( 4, 3) [000059] ----G------- * RETURN struct N001 ( 3, 2) [000127] -------N---- \--* LCL_VAR struct V17 tmp13 u:2 (last use) ------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Early Value Propagation *************** Starting PHASE Do value numbering *************** In fgValueNumber() Memory Initial Value in BB01 is: $100 The SSA definition for ByrefExposed (#1) at start of BB01 is $100 {InitVal($42)} The SSA definition for GcHeap (#1) at start of BB01 is $100 {InitVal($42)} ***** BB01, STMT00000(before) N005 ( 16, 16) [000007] -AC-----R--- * ASG ref N004 ( 1, 1) [000006] D------N---- +--* LCL_VAR ref V05 tmp1 d:2 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class N001 [000101] ARGPLACE => $140 {140} N002 [000004] CNS_INT(h) 0x7f6678beb1c0 class => $180 {Hnd const: 0x00007F6678BEB1C0} VN of ARGPLACE tree [000101] updated to $180 {Hnd const: 0x00007F6678BEB1C0} N003 [000005] CALL help => $200 {JitNew($180, $1c0)} N004 [000006] LCL_VAR V05 tmp1 d:2 => $200 {JitNew($180, $1c0)} N005 [000007] ASG => $200 {JitNew($180, $1c0)} ***** BB01, STMT00000(after) N005 ( 16, 16) [000007] -AC-----R--- * ASG ref $200 N004 ( 1, 1) [000006] D------N---- +--* LCL_VAR ref V05 tmp1 d:2 $200 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class $180 --------- ***** BB01, STMT00001(before) N006 ( 8, 9) [000012] -A-XG------- * ASG int N004 ( 4, 4) [000011] D--X---N---- +--* IND int N003 ( 2, 2) [000010] -------N---- | \--* ADD byref N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V05 tmp1 u:2 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD int V02 arg2 u:1[+8] Fseq[Version] N001 [000008] LCL_VAR V05 tmp1 u:2 => $200 {JitNew($180, $1c0)} N002 [000009] CNS_INT 8 => $240 {LngCns: 8} N003 [000010] ADD => $280 {ADD($200, $240)} VNApplySelectors: VNForHandle(Version) is $181, fieldType is int VNForMapSelect($c0, $181):int returns $2c0 {$c0[$181]} VNApplySelectors: VNForHandle(Version) is $181, fieldType is int VNForMapSelect($c0, $181):int returns $2c0 {$c0[$181]} N005 [000003] LCL_FLD V02 arg2 u:1[+8] Fseq[Version] => $2c0 {$c0[$181]} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000012] to VN: $1c2. N006 [000012] ASG => $VN.Void ***** BB01, STMT00001(after) N006 ( 8, 9) [000012] -A-XG------- * ASG int $VN.Void N004 ( 4, 4) [000011] D--X---N---- +--* IND int $2c0 N003 ( 2, 2) [000010] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V05 tmp1 u:2 $200 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD int V02 arg2 u:1[+8] Fseq[Version] $2c0 --------- ***** BB01, STMT00002(before) N005 ( 16, 16) [000021] -AC-----R--- * ASG ref N004 ( 1, 1) [000020] D------N---- +--* LCL_VAR ref V06 tmp2 d:2 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class N001 [000102] ARGPLACE => $141 {141} N002 [000018] CNS_INT(h) 0x7f6678c127f0 class => $182 {Hnd const: 0x00007F6678C127F0} VN of ARGPLACE tree [000102] updated to $182 {Hnd const: 0x00007F6678C127F0} N003 [000019] CALL help => $201 {JitNew($182, $1c3)} N004 [000020] LCL_VAR V06 tmp2 d:2 => $201 {JitNew($182, $1c3)} N005 [000021] ASG => $201 {JitNew($182, $1c3)} ***** BB01, STMT00002(after) N005 ( 16, 16) [000021] -AC-----R--- * ASG ref $201 N004 ( 1, 1) [000020] D------N---- +--* LCL_VAR ref V06 tmp2 d:2 $201 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class $182 --------- ***** BB01, STMT00003(before) N006 ( 8, 9) [000026] -A-XG------- * ASG long N004 ( 4, 4) [000025] D--X---N---- +--* IND long N003 ( 2, 2) [000024] -------N---- | \--* ADD byref N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V06 tmp2 u:2 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD long V02 arg2 u:1[+0] Fseq[JobGroup] N001 [000022] LCL_VAR V06 tmp2 u:2 => $201 {JitNew($182, $1c3)} N002 [000023] CNS_INT 8 => $240 {LngCns: 8} N003 [000024] ADD => $281 {ADD($201, $240)} VNApplySelectors: VNForHandle(JobGroup) is $183, fieldType is long VNForMapSelect($c0, $183):long returns $300 {$c0[$183]} VNApplySelectors: VNForHandle(JobGroup) is $183, fieldType is long VNForMapSelect($c0, $183):long returns $300 {$c0[$183]} N005 [000017] LCL_FLD V02 arg2 u:1[+0] Fseq[JobGroup] => $300 {$c0[$183]} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000026] to VN: $1c5. N006 [000026] ASG => $VN.Void ***** BB01, STMT00003(after) N006 ( 8, 9) [000026] -A-XG------- * ASG long $VN.Void N004 ( 4, 4) [000025] D--X---N---- +--* IND long $300 N003 ( 2, 2) [000024] -------N---- | \--* ADD byref $281 N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V06 tmp2 u:2 $201 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD long V02 arg2 u:1[+0] Fseq[JobGroup] $300 --------- ***** BB01, STMT00012(before) N004 ( 11, 8) [000077] -A------R--- * ASG ref N003 ( 3, 2) [000076] D------N---- +--* LCL_VAR ref V13 tmp9 d:2 N002 ( 7, 5) [000014] ------------ \--* BOX ref N001 ( 1, 1) [000013] ------------ \--* LCL_VAR ref V05 tmp1 u:2 (last use) N001 [000013] LCL_VAR V05 tmp1 u:2 (last use) => $200 {JitNew($180, $1c0)} N002 [000014] BOX => $200 {JitNew($180, $1c0)} N003 [000076] LCL_VAR V13 tmp9 d:2 => $200 {JitNew($180, $1c0)} N004 [000077] ASG => $200 {JitNew($180, $1c0)} ***** BB01, STMT00012(after) N004 ( 11, 8) [000077] -A------R--- * ASG ref $200 N003 ( 3, 2) [000076] D------N---- +--* LCL_VAR ref V13 tmp9 d:2 $200 N002 ( 7, 5) [000014] ------------ \--* BOX ref $200 N001 ( 1, 1) [000013] ------------ \--* LCL_VAR ref V05 tmp1 u:2 (last use) $200 --------- ***** BB01, STMT00013(before) N004 ( 11, 8) [000082] -A------R--- * ASG ref N003 ( 3, 2) [000081] D------N---- +--* LCL_VAR ref V14 tmp10 d:2 N002 ( 7, 5) [000028] ------------ \--* BOX ref N001 ( 1, 1) [000027] ------------ \--* LCL_VAR ref V06 tmp2 u:2 (last use) N001 [000027] LCL_VAR V06 tmp2 u:2 (last use) => $201 {JitNew($182, $1c3)} N002 [000028] BOX => $201 {JitNew($182, $1c3)} N003 [000081] LCL_VAR V14 tmp10 d:2 => $201 {JitNew($182, $1c3)} N004 [000082] ASG => $201 {JitNew($182, $1c3)} ***** BB01, STMT00013(after) N004 ( 11, 8) [000082] -A------R--- * ASG ref $201 N003 ( 3, 2) [000081] D------N---- +--* LCL_VAR ref V14 tmp10 d:2 $201 N002 ( 7, 5) [000028] ------------ \--* BOX ref $201 N001 ( 1, 1) [000027] ------------ \--* LCL_VAR ref V06 tmp2 u:2 (last use) $201 --------- ***** BB01, STMT00014(before) N003 ( 5, 4) [000087] -A------R--- * ASG ref N002 ( 3, 2) [000086] D------N---- +--* LCL_VAR ref V15 tmp11 d:2 N001 ( 1, 1) [000085] ------------ \--* CNS_INT ref null N001 [000085] CNS_INT null => $VN.Null N002 [000086] LCL_VAR V15 tmp11 d:2 => $VN.Null N003 [000087] ASG => $VN.Null ***** BB01, STMT00014(after) N003 ( 5, 4) [000087] -A------R--- * ASG ref $VN.Null N002 ( 3, 2) [000086] D------N---- +--* LCL_VAR ref V15 tmp11 d:2 $VN.Null N001 ( 1, 1) [000085] ------------ \--* CNS_INT ref null $VN.Null --------- ***** BB01, STMT00015(before) N004 ( 8, 15) [000092] -A--G---R--- * ASG ref N003 ( 3, 2) [000091] D------N---- +--* LCL_VAR ref V16 tmp12 d:2 N002 ( 4, 12) [000090] n---G------- \--* IND ref N001 ( 2, 10) [000103] ------------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] N001 [000103] CNS_INT(h) 0x7f6663fff340 static Fseq[s_twoArgArray] => $184 {Hnd const: 0x00007F6663FFF340} N002 [000090] IND => N003 [000091] LCL_VAR V16 tmp12 d:2 => N004 [000092] ASG => ***** BB01, STMT00015(after) N004 ( 8, 15) [000092] -A--G---R--- * ASG ref N003 ( 3, 2) [000091] D------N---- +--* LCL_VAR ref V16 tmp12 d:2 N002 ( 4, 12) [000090] n---G------- \--* IND ref N001 ( 2, 10) [000103] ------------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 --------- ***** BB01, STMT00017(before) N013 ( 34, 28) [000099] -ACXG---R--- * ASG ref N012 ( 1, 1) [000098] D------N---- +--* LCL_VAR ref V12 tmp8 d:2 N011 ( 34, 28) [000068] --CXG------- \--* CALL ref System.String.FormatHelper N007 ( 12, 8) [000108] -c---------- arg2 out+00 +--* FIELD_LIST struct N003 ( 3, 2) [000109] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp9 u:2 (last use) N004 ( 3, 2) [000110] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp10 u:2 (last use) N005 ( 3, 2) [000111] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp11 u:2 (last use) N006 ( 3, 2) [000112] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp12 u:2 (last use) N009 ( 4, 12) [000105] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000104] ------------ | \--* CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] N010 ( 1, 1) [000060] ------------ arg0 in rdi \--* CNS_INT ref null N001 [000107] ARGPLACE => $1cb {1cb} N002 [000106] ARGPLACE => $1cc {1cc} N003 [000109] LCL_VAR V13 tmp9 u:2 (last use) => $200 {JitNew($180, $1c0)} N004 [000110] LCL_VAR V14 tmp10 u:2 (last use) => $201 {JitNew($182, $1c3)} N005 [000111] LCL_VAR V15 tmp11 u:2 (last use) => $VN.Null N006 [000112] LCL_VAR V16 tmp12 u:2 (last use) => N007 [000108] FIELD_LIST => $380 {380} N008 [000104] CNS_INT(h) 0x640084D0 [ICON_STR_HDL] => $185 {Hnd const: 0x00007F66640084D0} N009 [000105] IND => N010 [000060] CNS_INT null => $VN.Null VN of ARGPLACE tree [000107] updated to $VN.Null VN of ARGPLACE tree [000106] updated to fgCurMemoryVN[GcHeap] assigned for CALL at [000068] to VN: $1cf. N011 [000068] CALL => $1ce {1ce} N012 [000098] LCL_VAR V12 tmp8 d:2 => $1ce {1ce} N013 [000099] ASG => $1ce {1ce} ***** BB01, STMT00017(after) N013 ( 34, 28) [000099] -ACXG---R--- * ASG ref $1ce N012 ( 1, 1) [000098] D------N---- +--* LCL_VAR ref V12 tmp8 d:2 $1ce N011 ( 34, 28) [000068] --CXG------- \--* CALL ref System.String.FormatHelper $1ce N007 ( 12, 8) [000108] -c---------- arg2 out+00 +--* FIELD_LIST struct $380 N003 ( 3, 2) [000109] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp9 u:2 (last use) $200 N004 ( 3, 2) [000110] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp10 u:2 (last use) $201 N005 ( 3, 2) [000111] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp11 u:2 (last use) $VN.Null N006 ( 3, 2) [000112] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp12 u:2 (last use) N009 ( 4, 12) [000105] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000104] ------------ | \--* CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] $185 N010 ( 1, 1) [000060] ------------ arg0 in rdi \--* CNS_INT ref null $VN.Null --------- ***** BB01, STMT00016(before) N005 ( 16, 9) [000097] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal N003 ( 1, 1) [000096] ------------ arg1 in rsi +--* LCL_VAR ref V12 tmp8 u:2 (last use) N004 ( 1, 1) [000095] ------------ arg0 in rdi \--* CNS_INT int 3 N001 [000114] ARGPLACE => $3c0 {3c0} N002 [000113] ARGPLACE => $1d1 {1d1} N003 [000096] LCL_VAR V12 tmp8 u:2 (last use) => $1ce {1ce} N004 [000095] CNS_INT 3 => $44 {IntCns 3} VN of ARGPLACE tree [000114] updated to $44 {IntCns 3} VN of ARGPLACE tree [000113] updated to $1ce {1ce} fgCurMemoryVN[GcHeap] assigned for CALL at [000097] to VN: $1d2. N005 [000097] CALL => $VN.Void ***** BB01, STMT00016(after) N005 ( 16, 9) [000097] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void N003 ( 1, 1) [000096] ------------ arg1 in rsi +--* LCL_VAR ref V12 tmp8 u:2 (last use) $1ce N004 ( 1, 1) [000095] ------------ arg0 in rdi \--* CNS_INT int 3 $44 --------- ***** BB01, STMT00006(before) N003 ( 5, 4) [000035] IA------R--- * ASG struct (init) N002 ( 3, 2) [000032] D------N---- +--* LCL_VAR struct V03 loc0 d:2 N001 ( 1, 1) [000034] ------------ \--* CNS_INT int 0 N001 [000034] CNS_INT 0 => $40 {IntCns 0} N003 [000035] ASG V03/2 => $VN.ZeroMap N003 [000035] ASG => $VN.Void ***** BB01, STMT00006(after) N003 ( 5, 4) [000035] IA------R--- * ASG struct (init) $VN.Void N002 ( 3, 2) [000032] D------N---- +--* LCL_VAR struct V03 loc0 d:2 N001 ( 1, 1) [000034] ------------ \--* CNS_INT int 0 $40 --------- ***** BB01, STMT00007(before) N008 ( 16, 15) [000043] -A-XG---R--- * ASG struct (copy) N007 ( 9, 9) [000042] n----------- +--* OBJ struct N006 ( 3, 5) [000041] ------------ | \--* ADDR byref N005 ( 3, 4) [000036] U------N---- | \--* LCL_FLD struct V03 loc0 ud:2->3[+40] Fseq[Baselib] N004 ( 6, 5) [000039] *--XG------- \--* IND struct N003 ( 3, 3) [000118] ------------ \--* ADD byref N001 ( 1, 1) [000038] ------------ +--* LCL_VAR byref V00 this u:1 N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] N001 [000038] LCL_VAR V00 this u:1 => $80 {InitVal($40)} N002 [000117] CNS_INT 16 field offset Fseq[m_Baselib] => $241 {LngCns: 16} N003 [000118] ADD => $282 {ADD($80, $241)} N004 [000039] IND => VNApplySelectors: VNForHandle(Baselib) is $186, fieldType is struct, size = 56 VNForMapSelect($1, $186):struct returns $VN.ZeroMap *** Mismatched types in VNApplySelectorsTypeCheck (indType is TYP_STRUCT) VNApplySelectors: VNForHandle(Baselib) is $186, fieldType is struct, size = 56 VNForMapSelect($1, $186):struct returns $VN.ZeroMap *** Mismatched types in VNApplySelectorsTypeCheck (indType is TYP_STRUCT) N005 [000036] LCL_FLD V03 loc0 ud:2->3[+40] Fseq[Baselib] => FieldSeq {Baselib} is $203 N006 [000041] ADDR => $283 {PtrToLoc($44, $203)} Tree [000043] assigned VN to local var V03/3: new uniq $384 {384} N008 [000043] ASG => $VN.Void ***** BB01, STMT00007(after) N008 ( 16, 15) [000043] -A-XG---R--- * ASG struct (copy) $VN.Void N007 ( 9, 9) [000042] n----------- +--* OBJ struct N006 ( 3, 5) [000041] ------------ | \--* ADDR byref $283 N005 ( 3, 4) [000036] U------N---- | \--* LCL_FLD struct V03 loc0 ud:2->3[+40] Fseq[Baselib] N004 ( 6, 5) [000039] *--XG------- \--* IND struct N003 ( 3, 3) [000118] ------------ \--* ADD byref $282 N001 ( 1, 1) [000038] ------------ +--* LCL_VAR byref V00 this u:1 $80 N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] $241 --------- ***** BB01, STMT00008(before) N008 ( 13, 13) [000051] -A-XG---R--- * ASG struct (copy) N007 ( 6, 7) [000050] n----------- +--* BLK struct N006 ( 3, 5) [000049] ------------ | \--* ADDR byref N005 ( 3, 4) [000044] U------N---- | \--* LCL_FLD struct V03 loc0 ud:3->4[+0] Fseq[Tx] N004 ( 6, 5) [000047] *--XG------- \--* IND struct N003 ( 3, 3) [000120] ------------ \--* ADD byref N001 ( 1, 1) [000046] ------------ +--* LCL_VAR byref V00 this u:1 (last use) N002 ( 1, 1) [000119] ------------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] N001 [000046] LCL_VAR V00 this u:1 (last use) => $80 {InitVal($40)} N002 [000119] CNS_INT 112 field offset Fseq[m_PayloadsTx] => $242 {LngCns: 112} N003 [000120] ADD => $284 {ADD($80, $242)} N004 [000047] IND => VNApplySelectors: VNForHandle(Tx) is $187, fieldType is struct, size = 40 VNForMapSelect($384, $187):struct returns $404 {$384[$187]} VNApplySelectors: VNForHandle(Tx) is $187, fieldType is struct, size = 40 VNForMapSelect($384, $187):struct returns $404 {$384[$187]} N005 [000044] LCL_FLD V03 loc0 ud:3->4[+0] Fseq[Tx] => $404 {$384[$187]} FieldSeq {Tx} is $204 N006 [000049] ADDR => $285 {PtrToLoc($44, $204)} Tree [000051] assigned VN to local var V03/4: new uniq $387 {387} N008 [000051] ASG => $VN.Void ***** BB01, STMT00008(after) N008 ( 13, 13) [000051] -A-XG---R--- * ASG struct (copy) $VN.Void N007 ( 6, 7) [000050] n----------- +--* BLK struct N006 ( 3, 5) [000049] ------------ | \--* ADDR byref $285 N005 ( 3, 4) [000044] U------N---- | \--* LCL_FLD struct V03 loc0 ud:3->4[+0] Fseq[Tx] $404 N004 ( 6, 5) [000047] *--XG------- \--* IND struct N003 ( 3, 3) [000120] ------------ \--* ADD byref $284 N001 ( 1, 1) [000046] ------------ +--* LCL_VAR byref V00 this u:1 (last use) $80 N002 ( 1, 1) [000119] ------------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] $242 --------- ***** BB01, STMT00018(before) N010 ( 36, 24) [000122] -ACXG---R--- * ASG struct (copy) N009 ( 3, 2) [000121] D------N---- +--* LCL_VAR struct V17 tmp13 d:2 N008 ( 32, 21) [000054] --CXG------- \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA N003 ( 9, 7) [000058] n----------- arg0 out+00 +--* OBJ struct N002 ( 3, 3) [000057] ------------ | \--* ADDR byref N001 ( 3, 2) [000052] -------N---- | \--* LCL_VAR struct V03 loc0 u:4 (last use) N007 ( 6, 8) [000124] -c---------- arg1 rdi,rsi \--* FIELD_LIST struct N005 ( 3, 4) [000125] ------------ ofs 0 +--* LCL_FLD long V02 arg2 u:1[+0] N006 ( 3, 4) [000126] ------------ ofs 8 \--* LCL_FLD long V02 arg2 u:1[+8] (last use) N001 [000052] LCL_VAR V03 loc0 u:4 (last use) => $387 {387} N002 [000057] ADDR => $286 {PtrToLoc($44, $0)} N003 [000058] OBJ => $388 {388} N004 [000123] ARGPLACE => $389 {389} N005 [000125] LCL_FLD V02 arg2 u:1[+0] => $142 {142} N006 [000126] LCL_FLD V02 arg2 u:1[+8] (last use) => $143 {143} N007 [000124] FIELD_LIST => $38a {38a} VN of ARGPLACE tree [000123] updated to $38a {38a} fgCurMemoryVN[GcHeap] assigned for CALL at [000054] to VN: $1d5. N008 [000054] CALL => $38b {38b} Tree [000122] assigned VN to local var V17/2: new uniq $38e {38e} N010 [000122] ASG => $VN.Void ***** BB01, STMT00018(after) N010 ( 36, 24) [000122] -ACXG---R--- * ASG struct (copy) $VN.Void N009 ( 3, 2) [000121] D------N---- +--* LCL_VAR struct V17 tmp13 d:2 N008 ( 32, 21) [000054] --CXG------- \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA $38b N003 ( 9, 7) [000058] n----------- arg0 out+00 +--* OBJ struct $388 N002 ( 3, 3) [000057] ------------ | \--* ADDR byref $286 N001 ( 3, 2) [000052] -------N---- | \--* LCL_VAR struct V03 loc0 u:4 (last use) $387 N007 ( 6, 8) [000124] -c---------- arg1 rdi,rsi \--* FIELD_LIST struct $38a N005 ( 3, 4) [000125] ------------ ofs 0 +--* LCL_FLD long V02 arg2 u:1[+0] $142 N006 ( 3, 4) [000126] ------------ ofs 8 \--* LCL_FLD long V02 arg2 u:1[+8] (last use) $143 --------- ***** BB01, STMT00009(before) N002 ( 4, 3) [000059] ----G------- * RETURN struct N001 ( 3, 2) [000127] -------N---- \--* LCL_VAR struct V17 tmp13 u:2 (last use) N001 [000127] LCL_VAR V17 tmp13 u:2 (last use) => $38e {38e} N002 [000059] RETURN => $38f {38f} ***** BB01, STMT00009(after) N002 ( 4, 3) [000059] ----G------- * RETURN struct $38f N001 ( 3, 2) [000127] -------N---- \--* LCL_VAR struct V17 tmp13 u:2 (last use) $38e finish(BB01). *************** Finishing PHASE Do value numbering *************** Starting PHASE Hoist loop code *************** Finishing PHASE Hoist loop code *************** Starting PHASE VN based copy prop *************** In optVnCopyProp() Copy Assertion for BB01 curSsaName stack: { } Live vars: {V00 V02} => {V00 V02 V05} Live vars: {V00 V02 V05} => {V00 V02 V05 V06} Live vars: {V00 V02 V05 V06} => {V00 V02 V06} Live vars: {V00 V02 V06} => {V00 V02 V06 V13} Live vars: {V00 V02 V06 V13} => {V00 V02 V13} Live vars: {V00 V02 V13} => {V00 V02 V13 V14} Live vars: {V00 V02 V13 V14} => {V00 V02 V13 V14 V15} Live vars: {V00 V02 V13 V14 V15} => {V00 V02 V13 V14 V15 V16} Live vars: {V00 V02 V13 V14 V15 V16} => {V00 V02 V14 V15 V16} Live vars: {V00 V02 V14 V15 V16} => {V00 V02 V15 V16} Live vars: {V00 V02 V15 V16} => {V00 V02 V16} Live vars: {V00 V02 V16} => {V00 V02} Live vars: {V00 V02} => {V00 V02 V12} Live vars: {V00 V02 V12} => {V00 V02} Live vars: {V00 V02} => {V00 V02 V03} Live vars: {V00 V02 V03} => {V02 V03} Live vars: {V02 V03} => {V02} Live vars: {V02} => {} Live vars: {} => {V17} Live vars: {V17} => {} *************** Finishing PHASE VN based copy prop *************** Starting PHASE Optimize Valnum CSEs *************** In optOptimizeCSEs() Blocks/Trees at start of optOptimizeCSE phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} ***** BB01 STMT00000 (IL 0x000...0x028) N005 ( 16, 16) [000007] -AC-----R--- * ASG ref $200 N004 ( 1, 1) [000006] D------N---- +--* LCL_VAR ref V05 tmp1 d:2 $200 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class $180 ***** BB01 STMT00001 (IL ???... ???) N006 ( 8, 9) [000012] -A-XG------- * ASG int $VN.Void N004 ( 4, 4) [000011] D--X---N---- +--* IND int $2c0 N003 ( 2, 2) [000010] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V05 tmp1 u:2 $200 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD int V02 arg2 u:1[+8] Fseq[Version] $2c0 ***** BB01 STMT00002 (IL ???... ???) N005 ( 16, 16) [000021] -AC-----R--- * ASG ref $201 N004 ( 1, 1) [000020] D------N---- +--* LCL_VAR ref V06 tmp2 d:2 $201 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class $182 ***** BB01 STMT00003 (IL ???... ???) N006 ( 8, 9) [000026] -A-XG------- * ASG long $VN.Void N004 ( 4, 4) [000025] D--X---N---- +--* IND long $300 N003 ( 2, 2) [000024] -------N---- | \--* ADD byref $281 N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V06 tmp2 u:2 $201 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD long V02 arg2 u:1[+0] Fseq[JobGroup] $300 ***** BB01 STMT00012 (IL ???... ???) N004 ( 11, 8) [000077] -A------R--- * ASG ref $200 N003 ( 3, 2) [000076] D------N---- +--* LCL_VAR ref V13 tmp9 d:2 $200 N002 ( 7, 5) [000014] ------------ \--* BOX ref $200 N001 ( 1, 1) [000013] ------------ \--* LCL_VAR ref V05 tmp1 u:2 (last use) $200 ***** BB01 STMT00013 (IL ???... ???) N004 ( 11, 8) [000082] -A------R--- * ASG ref $201 N003 ( 3, 2) [000081] D------N---- +--* LCL_VAR ref V14 tmp10 d:2 $201 N002 ( 7, 5) [000028] ------------ \--* BOX ref $201 N001 ( 1, 1) [000027] ------------ \--* LCL_VAR ref V06 tmp2 u:2 (last use) $201 ***** BB01 STMT00014 (IL ???... ???) N003 ( 5, 4) [000087] -A------R--- * ASG ref $VN.Null N002 ( 3, 2) [000086] D------N---- +--* LCL_VAR ref V15 tmp11 d:2 $VN.Null N001 ( 1, 1) [000085] ------------ \--* CNS_INT ref null $VN.Null ***** BB01 STMT00015 (IL ???... ???) N004 ( 8, 15) [000092] -A--G---R--- * ASG ref N003 ( 3, 2) [000091] D------N---- +--* LCL_VAR ref V16 tmp12 d:2 N002 ( 4, 12) [000090] n---G------- \--* IND ref N001 ( 2, 10) [000103] ------------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 ***** BB01 STMT00017 (IL ???... ???) N013 ( 34, 28) [000099] -ACXG---R--- * ASG ref $1ce N012 ( 1, 1) [000098] D------N---- +--* LCL_VAR ref V12 tmp8 d:2 $1ce N011 ( 34, 28) [000068] --CXG------- \--* CALL ref System.String.FormatHelper $1ce N007 ( 12, 8) [000108] -c---------- arg2 out+00 +--* FIELD_LIST struct $380 N003 ( 3, 2) [000109] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp9 u:2 (last use) $200 N004 ( 3, 2) [000110] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp10 u:2 (last use) $201 N005 ( 3, 2) [000111] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp11 u:2 (last use) $VN.Null N006 ( 3, 2) [000112] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp12 u:2 (last use) N009 ( 4, 12) [000105] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000104] ------------ | \--* CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] $185 N010 ( 1, 1) [000060] ------------ arg0 in rdi \--* CNS_INT ref null $VN.Null ***** BB01 STMT00016 (IL ???... ???) N005 ( 16, 9) [000097] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void N003 ( 1, 1) [000096] ------------ arg1 in rsi +--* LCL_VAR ref V12 tmp8 u:2 (last use) $1ce N004 ( 1, 1) [000095] ------------ arg0 in rdi \--* CNS_INT int 3 $44 ***** BB01 STMT00006 (IL 0x025... ???) N003 ( 5, 4) [000035] IA------R--- * ASG struct (init) $VN.Void N002 ( 3, 2) [000032] D------N---- +--* LCL_VAR struct V03 loc0 d:2 N001 ( 1, 1) [000034] ------------ \--* CNS_INT int 0 $40 ***** BB01 STMT00007 (IL 0x02D...0x035) N008 ( 16, 15) [000043] -A-XG---R--- * ASG struct (copy) $VN.Void N007 ( 9, 9) [000042] n----------- +--* OBJ struct N006 ( 3, 5) [000041] ------------ | \--* ADDR byref $283 N005 ( 3, 4) [000036] U------N---- | \--* LCL_FLD struct V03 loc0 ud:2->3[+40] Fseq[Baselib] N004 ( 6, 5) [000039] *--XG------- \--* IND struct N003 ( 3, 3) [000118] ------------ \--* ADD byref $282 N001 ( 1, 1) [000038] ------------ +--* LCL_VAR byref V00 this u:1 $80 N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] $241 ***** BB01 STMT00008 (IL 0x03A...0x042) N008 ( 13, 13) [000051] -A-XG---R--- * ASG struct (copy) $VN.Void N007 ( 6, 7) [000050] n----------- +--* BLK struct N006 ( 3, 5) [000049] ------------ | \--* ADDR byref $285 N005 ( 3, 4) [000044] U------N---- | \--* LCL_FLD struct V03 loc0 ud:3->4[+0] Fseq[Tx] $404 N004 ( 6, 5) [000047] *--XG------- \--* IND struct N003 ( 3, 3) [000120] ------------ \--* ADD byref $284 N001 ( 1, 1) [000046] ------------ +--* LCL_VAR byref V00 this u:1 (last use) $80 N002 ( 1, 1) [000119] ------------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] $242 ***** BB01 STMT00018 (IL 0x047... ???) N010 ( 36, 24) [000122] -ACXG---R--- * ASG struct (copy) $VN.Void N009 ( 3, 2) [000121] D------N---- +--* LCL_VAR struct V17 tmp13 d:2 N008 ( 32, 21) [000054] --CXG------- \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA $38b N003 ( 9, 7) [000058] n----------- arg0 out+00 +--* OBJ struct $388 N002 ( 3, 3) [000057] ------------ | \--* ADDR byref $286 N001 ( 3, 2) [000052] -------N---- | \--* LCL_VAR struct V03 loc0 u:4 (last use) $387 N007 ( 6, 8) [000124] -c---------- arg1 rdi,rsi \--* FIELD_LIST struct $38a N005 ( 3, 4) [000125] ------------ ofs 0 +--* LCL_FLD long V02 arg2 u:1[+0] $142 N006 ( 3, 4) [000126] ------------ ofs 8 \--* LCL_FLD long V02 arg2 u:1[+8] (last use) $143 ***** BB01 STMT00009 (IL 0x047...0x04E) N002 ( 4, 3) [000059] ----G------- * RETURN struct $38f N001 ( 3, 2) [000127] -------N---- \--* LCL_VAR struct V17 tmp13 u:2 (last use) $38e ------------------------------------------------------------------------------------------------------------------- *************** In optOptimizeValnumCSEs() *************** Finishing PHASE Optimize Valnum CSEs *************** Starting PHASE Assertion prop *************** In optAssertionPropMain() Blocks/Trees at start of phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} ***** BB01 STMT00000 (IL 0x000...0x028) N005 ( 16, 16) [000007] -AC-----R--- * ASG ref $200 N004 ( 1, 1) [000006] D------N---- +--* LCL_VAR ref V05 tmp1 d:2 $200 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class $180 ***** BB01 STMT00001 (IL ???... ???) N006 ( 8, 9) [000012] -A-XG------- * ASG int $VN.Void N004 ( 4, 4) [000011] D--X---N---- +--* IND int $2c0 N003 ( 2, 2) [000010] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V05 tmp1 u:2 $200 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD int V02 arg2 u:1[+8] Fseq[Version] $2c0 ***** BB01 STMT00002 (IL ???... ???) N005 ( 16, 16) [000021] -AC-----R--- * ASG ref $201 N004 ( 1, 1) [000020] D------N---- +--* LCL_VAR ref V06 tmp2 d:2 $201 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class $182 ***** BB01 STMT00003 (IL ???... ???) N006 ( 8, 9) [000026] -A-XG------- * ASG long $VN.Void N004 ( 4, 4) [000025] D--X---N---- +--* IND long $300 N003 ( 2, 2) [000024] -------N---- | \--* ADD byref $281 N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V06 tmp2 u:2 $201 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD long V02 arg2 u:1[+0] Fseq[JobGroup] $300 ***** BB01 STMT00012 (IL ???... ???) N004 ( 11, 8) [000077] -A------R--- * ASG ref $200 N003 ( 3, 2) [000076] D------N---- +--* LCL_VAR ref V13 tmp9 d:2 $200 N002 ( 7, 5) [000014] ------------ \--* BOX ref $200 N001 ( 1, 1) [000013] ------------ \--* LCL_VAR ref V05 tmp1 u:2 (last use) $200 ***** BB01 STMT00013 (IL ???... ???) N004 ( 11, 8) [000082] -A------R--- * ASG ref $201 N003 ( 3, 2) [000081] D------N---- +--* LCL_VAR ref V14 tmp10 d:2 $201 N002 ( 7, 5) [000028] ------------ \--* BOX ref $201 N001 ( 1, 1) [000027] ------------ \--* LCL_VAR ref V06 tmp2 u:2 (last use) $201 ***** BB01 STMT00014 (IL ???... ???) N003 ( 5, 4) [000087] -A------R--- * ASG ref $VN.Null N002 ( 3, 2) [000086] D------N---- +--* LCL_VAR ref V15 tmp11 d:2 $VN.Null N001 ( 1, 1) [000085] ------------ \--* CNS_INT ref null $VN.Null ***** BB01 STMT00015 (IL ???... ???) N004 ( 8, 15) [000092] -A--G---R--- * ASG ref N003 ( 3, 2) [000091] D------N---- +--* LCL_VAR ref V16 tmp12 d:2 N002 ( 4, 12) [000090] n---G------- \--* IND ref N001 ( 2, 10) [000103] ------------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 ***** BB01 STMT00017 (IL ???... ???) N013 ( 34, 28) [000099] -ACXG---R--- * ASG ref $1ce N012 ( 1, 1) [000098] D------N---- +--* LCL_VAR ref V12 tmp8 d:2 $1ce N011 ( 34, 28) [000068] --CXG------- \--* CALL ref System.String.FormatHelper $1ce N007 ( 12, 8) [000108] -c---------- arg2 out+00 +--* FIELD_LIST struct $380 N003 ( 3, 2) [000109] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp9 u:2 (last use) $200 N004 ( 3, 2) [000110] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp10 u:2 (last use) $201 N005 ( 3, 2) [000111] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp11 u:2 (last use) $VN.Null N006 ( 3, 2) [000112] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp12 u:2 (last use) N009 ( 4, 12) [000105] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000104] ------------ | \--* CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] $185 N010 ( 1, 1) [000060] ------------ arg0 in rdi \--* CNS_INT ref null $VN.Null ***** BB01 STMT00016 (IL ???... ???) N005 ( 16, 9) [000097] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void N003 ( 1, 1) [000096] ------------ arg1 in rsi +--* LCL_VAR ref V12 tmp8 u:2 (last use) $1ce N004 ( 1, 1) [000095] ------------ arg0 in rdi \--* CNS_INT int 3 $44 ***** BB01 STMT00006 (IL 0x025... ???) N003 ( 5, 4) [000035] IA------R--- * ASG struct (init) $VN.Void N002 ( 3, 2) [000032] D------N---- +--* LCL_VAR struct V03 loc0 d:2 N001 ( 1, 1) [000034] ------------ \--* CNS_INT int 0 $40 ***** BB01 STMT00007 (IL 0x02D...0x035) N008 ( 16, 15) [000043] -A-XG---R--- * ASG struct (copy) $VN.Void N007 ( 9, 9) [000042] n----------- +--* OBJ struct N006 ( 3, 5) [000041] ------------ | \--* ADDR byref $283 N005 ( 3, 4) [000036] U------N---- | \--* LCL_FLD struct V03 loc0 ud:2->3[+40] Fseq[Baselib] N004 ( 6, 5) [000039] *--XG------- \--* IND struct N003 ( 3, 3) [000118] ------------ \--* ADD byref $282 N001 ( 1, 1) [000038] ------------ +--* LCL_VAR byref V00 this u:1 $80 N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] $241 ***** BB01 STMT00008 (IL 0x03A...0x042) N008 ( 13, 13) [000051] -A-XG---R--- * ASG struct (copy) $VN.Void N007 ( 6, 7) [000050] n----------- +--* BLK struct N006 ( 3, 5) [000049] ------------ | \--* ADDR byref $285 N005 ( 3, 4) [000044] U------N---- | \--* LCL_FLD struct V03 loc0 ud:3->4[+0] Fseq[Tx] $404 N004 ( 6, 5) [000047] *--XG------- \--* IND struct N003 ( 3, 3) [000120] ------------ \--* ADD byref $284 N001 ( 1, 1) [000046] ------------ +--* LCL_VAR byref V00 this u:1 (last use) $80 N002 ( 1, 1) [000119] ------------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] $242 ***** BB01 STMT00018 (IL 0x047... ???) N010 ( 36, 24) [000122] -ACXG---R--- * ASG struct (copy) $VN.Void N009 ( 3, 2) [000121] D------N---- +--* LCL_VAR struct V17 tmp13 d:2 N008 ( 32, 21) [000054] --CXG------- \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA $38b N003 ( 9, 7) [000058] n----------- arg0 out+00 +--* OBJ struct $388 N002 ( 3, 3) [000057] ------------ | \--* ADDR byref $286 N001 ( 3, 2) [000052] -------N---- | \--* LCL_VAR struct V03 loc0 u:4 (last use) $387 N007 ( 6, 8) [000124] -c---------- arg1 rdi,rsi \--* FIELD_LIST struct $38a N005 ( 3, 4) [000125] ------------ ofs 0 +--* LCL_FLD long V02 arg2 u:1[+0] $142 N006 ( 3, 4) [000126] ------------ ofs 8 \--* LCL_FLD long V02 arg2 u:1[+8] (last use) $143 ***** BB01 STMT00009 (IL 0x047...0x04E) N002 ( 4, 3) [000059] ----G------- * RETURN struct $38f N001 ( 3, 2) [000127] -------N---- \--* LCL_VAR struct V17 tmp13 u:2 (last use) $38e ------------------------------------------------------------------------------------------------------------------- VN based non-null prop in BB01: N004 ( 4, 4) [000011] D--X---N---- * IND int $2c0 optVNAssertionPropCurStmt morphed tree: N006 ( 8, 9) [000012] -A--GO------ * ASG int $VN.Void N004 ( 4, 4) [000011] n----O-N---- +--* IND int $2c0 N003 ( 2, 2) [000010] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V05 tmp1 u:2 $200 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD int V02 arg2 u:1[+8] Fseq[Version] $2c0 GenTreeNode creates assertion: N004 ( 4, 4) [000011] n----O-N---- * IND int $2c0 In BB01 New Global Constant Assertion: (512, 0) ($200,$0) V05.02 != null index=#01, mask= VN based non-null prop in BB01: N004 ( 4, 4) [000025] D--X---N---- * IND long $300 optVNAssertionPropCurStmt morphed tree: N006 ( 8, 9) [000026] -A--GO------ * ASG long $VN.Void N004 ( 4, 4) [000025] n----O-N---- +--* IND long $300 N003 ( 2, 2) [000024] -------N---- | \--* ADD byref $281 N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V06 tmp2 u:2 $201 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD long V02 arg2 u:1[+0] Fseq[JobGroup] $300 GenTreeNode creates assertion: N004 ( 4, 4) [000025] n----O-N---- * IND long $300 In BB01 New Global Constant Assertion: (513, 0) ($201,$0) V06.02 != null index=#02, mask= After constant propagation on [000111]: STMT00017 (IL ???... ???) N013 ( 34, 28) [000099] -ACXG---R--- * ASG ref $1ce N012 ( 1, 1) [000098] D------N---- +--* LCL_VAR ref V12 tmp8 d:2 $1ce N011 ( 34, 28) [000068] --CXG------- \--* CALL ref System.String.FormatHelper $1ce N007 ( 12, 8) [000108] -c---------- arg2 out+00 +--* FIELD_LIST struct $380 N003 ( 3, 2) [000109] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp9 u:2 (last use) $200 N004 ( 3, 2) [000110] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp10 u:2 (last use) $201 [000128] ------------ ofs 16 | +--* CNS_INT ref null $VN.Null N006 ( 3, 2) [000112] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp12 u:2 (last use) N009 ( 4, 12) [000105] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000104] ------------ | \--* CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] $185 N010 ( 1, 1) [000060] ------------ arg0 in rdi \--* CNS_INT ref null $VN.Null ReMorphing args for 68.CALL: argSlots=6, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 ArgTable for 68.CALL after fgMorphArgs: fgArgTabEntry[arg 2 108.FIELD_LIST struct (By value), numSlots=4, slotNum=0, align=1, processed, isStruct] fgArgTabEntry[arg 1 105.IND ref (By ref), 1 reg: rsi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 0 60.CNS_INT ref (By ref), 1 reg: rdi, align=1, lateArgInx=1, processed] optVNAssertionPropCurStmt morphed tree: N013 ( 32, 27) [000099] -ACXG---R--- * ASG ref $1ce N012 ( 1, 1) [000098] D------N---- +--* LCL_VAR ref V12 tmp8 d:2 $1ce N011 ( 32, 27) [000068] --CXG------- \--* CALL ref System.String.FormatHelper $1ce N007 ( 10, 7) [000108] -c---------- arg2 out+00 +--* FIELD_LIST struct $380 N003 ( 3, 2) [000109] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp9 u:2 (last use) $200 N004 ( 3, 2) [000110] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp10 u:2 (last use) $201 N005 ( 1, 1) [000128] ------------ ofs 16 | +--* CNS_INT ref null $VN.Null N006 ( 3, 2) [000112] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp12 u:2 (last use) N009 ( 4, 12) [000105] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000104] ------------ | \--* CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] $185 N010 ( 1, 1) [000060] ------------ arg0 in rdi \--* CNS_INT ref null $VN.Null GenTreeNode creates assertion: N004 ( 6, 5) [000039] *--XG------- * IND struct In BB01 New Global Constant Assertion: (128, 0) ($80,$0) Value_Number {InitVal($40)} is not 0 index=#03, mask= BB01 valueGen = AssertionPropCallback::StartMerge: BB01 in -> AssertionPropCallback::EndMerge : BB01 in -> AssertionPropCallback::Changed : BB01 before out -> ; after out -> ; jumpDest before out -> ; jumpDest after out -> ; BB01 valueIn = valueOut = Propagating assertions for BB01, stmt STMT00000, tree [000101], tree -> 0 Propagating assertions for BB01, stmt STMT00000, tree [000004], tree -> 0 Propagating assertions for BB01, stmt STMT00000, tree [000005], tree -> 0 Propagating assertions for BB01, stmt STMT00000, tree [000006], tree -> 0 Propagating assertions for BB01, stmt STMT00000, tree [000007], tree -> 0 Propagating assertions for BB01, stmt STMT00001, tree [000008], tree -> 0 Propagating assertions for BB01, stmt STMT00001, tree [000009], tree -> 0 Propagating assertions for BB01, stmt STMT00001, tree [000010], tree -> 0 Propagating assertions for BB01, stmt STMT00001, tree [000011], tree -> 1 Propagating assertions for BB01, stmt STMT00001, tree [000003], tree -> 0 Propagating assertions for BB01, stmt STMT00001, tree [000012], tree -> 0 Propagating assertions for BB01, stmt STMT00002, tree [000102], tree -> 0 Propagating assertions for BB01, stmt STMT00002, tree [000018], tree -> 0 Propagating assertions for BB01, stmt STMT00002, tree [000019], tree -> 0 Propagating assertions for BB01, stmt STMT00002, tree [000020], tree -> 0 Propagating assertions for BB01, stmt STMT00002, tree [000021], tree -> 0 Propagating assertions for BB01, stmt STMT00003, tree [000022], tree -> 0 Propagating assertions for BB01, stmt STMT00003, tree [000023], tree -> 0 Propagating assertions for BB01, stmt STMT00003, tree [000024], tree -> 0 Propagating assertions for BB01, stmt STMT00003, tree [000025], tree -> 2 Propagating assertions for BB01, stmt STMT00003, tree [000017], tree -> 0 Propagating assertions for BB01, stmt STMT00003, tree [000026], tree -> 0 Propagating assertions for BB01, stmt STMT00012, tree [000013], tree -> 0 Propagating assertions for BB01, stmt STMT00012, tree [000014], tree -> 0 Propagating assertions for BB01, stmt STMT00012, tree [000076], tree -> 0 Propagating assertions for BB01, stmt STMT00012, tree [000077], tree -> 0 Propagating assertions for BB01, stmt STMT00013, tree [000027], tree -> 0 Propagating assertions for BB01, stmt STMT00013, tree [000028], tree -> 0 Propagating assertions for BB01, stmt STMT00013, tree [000081], tree -> 0 Propagating assertions for BB01, stmt STMT00013, tree [000082], tree -> 0 Propagating assertions for BB01, stmt STMT00014, tree [000085], tree -> 0 Propagating assertions for BB01, stmt STMT00014, tree [000086], tree -> 0 Propagating assertions for BB01, stmt STMT00014, tree [000087], tree -> 0 Propagating assertions for BB01, stmt STMT00015, tree [000103], tree -> 0 Propagating assertions for BB01, stmt STMT00015, tree [000090], tree -> 0 Propagating assertions for BB01, stmt STMT00015, tree [000091], tree -> 0 Propagating assertions for BB01, stmt STMT00015, tree [000092], tree -> 0 Propagating assertions for BB01, stmt STMT00017, tree [000107], tree -> 0 Propagating assertions for BB01, stmt STMT00017, tree [000106], tree -> 0 Propagating assertions for BB01, stmt STMT00017, tree [000109], tree -> 0 Propagating assertions for BB01, stmt STMT00017, tree [000110], tree -> 0 Propagating assertions for BB01, stmt STMT00017, tree [000128], tree -> 0 Propagating assertions for BB01, stmt STMT00017, tree [000112], tree -> 0 Propagating assertions for BB01, stmt STMT00017, tree [000108], tree -> 0 Propagating assertions for BB01, stmt STMT00017, tree [000104], tree -> 0 Propagating assertions for BB01, stmt STMT00017, tree [000105], tree -> 0 Propagating assertions for BB01, stmt STMT00017, tree [000060], tree -> 0 Propagating assertions for BB01, stmt STMT00017, tree [000068], tree -> 0 Propagating assertions for BB01, stmt STMT00017, tree [000098], tree -> 0 Propagating assertions for BB01, stmt STMT00017, tree [000099], tree -> 0 Propagating assertions for BB01, stmt STMT00016, tree [000114], tree -> 0 Propagating assertions for BB01, stmt STMT00016, tree [000113], tree -> 0 Propagating assertions for BB01, stmt STMT00016, tree [000096], tree -> 0 Propagating assertions for BB01, stmt STMT00016, tree [000095], tree -> 0 Propagating assertions for BB01, stmt STMT00016, tree [000097], tree -> 0 Propagating assertions for BB01, stmt STMT00006, tree [000034], tree -> 0 Propagating assertions for BB01, stmt STMT00006, tree [000032], tree -> 0 Propagating assertions for BB01, stmt STMT00006, tree [000035], tree -> 0 Propagating assertions for BB01, stmt STMT00007, tree [000038], tree -> 0 Propagating assertions for BB01, stmt STMT00007, tree [000117], tree -> 0 Propagating assertions for BB01, stmt STMT00007, tree [000118], tree -> 0 Propagating assertions for BB01, stmt STMT00007, tree [000039], tree -> 3 Propagating assertions for BB01, stmt STMT00007, tree [000036], tree -> 0 Propagating assertions for BB01, stmt STMT00007, tree [000041], tree -> 0 Propagating assertions for BB01, stmt STMT00007, tree [000042], tree -> 0 Propagating assertions for BB01, stmt STMT00007, tree [000043], tree -> 0 Propagating assertions for BB01, stmt STMT00008, tree [000046], tree -> 0 Propagating assertions for BB01, stmt STMT00008, tree [000119], tree -> 0 Propagating assertions for BB01, stmt STMT00008, tree [000120], tree -> 0 Propagating assertions for BB01, stmt STMT00008, tree [000047], tree -> 3 Non-null prop for index #03 in BB01: N004 ( 6, 5) [000047] *--XG------- * IND struct Propagating assertions for BB01, stmt STMT00008, tree [000044], tree -> 0 Propagating assertions for BB01, stmt STMT00008, tree [000049], tree -> 0 Propagating assertions for BB01, stmt STMT00008, tree [000050], tree -> 0 Propagating assertions for BB01, stmt STMT00008, tree [000051], tree -> 0 Re-morphing this stmt: STMT00008 (IL 0x03A...0x042) N008 ( 13, 13) [000051] -A-XG---R--- * ASG struct (copy) $VN.Void N007 ( 6, 7) [000050] n----------- +--* BLK struct N006 ( 3, 5) [000049] ------------ | \--* ADDR byref $285 N005 ( 3, 4) [000044] U------N---- | \--* LCL_FLD struct V03 loc0 ud:3->4[+0] Fseq[Tx] $404 N004 ( 6, 5) [000047] *---GO------ \--* IND struct N003 ( 3, 3) [000120] ------------ \--* ADD byref $284 N001 ( 1, 1) [000046] ------------ +--* LCL_VAR byref V00 this u:1 (last use) $80 N002 ( 1, 1) [000119] ------------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] $242 fgMorphCopyBlock: fgMorphBlkNode for dst tree, before: N007 ( 6, 7) [000050] n----------- * BLK struct N006 ( 3, 5) [000049] ------------ \--* ADDR byref $285 N005 ( 3, 4) [000044] U------N---- \--* LCL_FLD struct V03 loc0 ud:3->4[+0] Fseq[Tx] $404 fgMorphBlkNode after: N007 ( 6, 7) [000050] n----------- * BLK struct N006 ( 3, 5) [000049] ------------ \--* ADDR byref $285 N005 ( 3, 4) [000044] U------N---- \--* LCL_FLD struct V03 loc0 ud:3->4[+0] Fseq[Tx] $404 fgMorphBlkNode for src tree, before: N004 ( 6, 5) [000047] *---GO------ * IND struct N003 ( 3, 3) [000120] ------------ \--* ADD byref $284 N001 ( 1, 1) [000046] ------------ +--* LCL_VAR byref V00 this u:1 (last use) $80 N002 ( 1, 1) [000119] ------------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] $242 fgMorphBlkNode after: N004 ( 6, 5) [000047] *---GO------ * IND struct N003 ( 3, 3) [000120] ------------ \--* ADD byref $284 N001 ( 1, 1) [000046] ------------ +--* LCL_VAR byref V00 this u:1 (last use) $80 N002 ( 1, 1) [000119] ------------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] $242 block assignment to morph: N008 ( 13, 13) [000051] -A--GO--R--- * ASG struct (copy) $VN.Void N007 ( 6, 7) [000050] n----------- +--* BLK struct N006 ( 3, 5) [000049] ------------ | \--* ADDR byref $285 N005 ( 3, 4) [000044] U------N---- | \--* LCL_FLD struct V03 loc0 ud:3->4[+0] Fseq[Tx] $404 N004 ( 6, 5) [000047] *---GO------ \--* IND struct N003 ( 3, 3) [000120] ------------ \--* ADD byref $284 N001 ( 1, 1) [000046] ------------ +--* LCL_VAR byref V00 this u:1 (last use) $80 N002 ( 1, 1) [000119] ------------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] $242 with no promoted structs this requires a CopyBlock. Local V03 should not be enregistered because: written in a block op fgMorphCopyBlock (after): N008 ( 13, 13) [000051] -A--GO--R--- * ASG struct (copy) $VN.Void N007 ( 6, 7) [000050] n----------- +--* BLK struct N006 ( 3, 5) [000049] ------------ | \--* ADDR byref $285 N005 ( 3, 4) [000044] U------N---- | \--* LCL_FLD struct V03 loc0 ud:3->4[+0] Fseq[Tx] $404 N004 ( 6, 5) [000047] *---GO------ \--* IND struct N003 ( 3, 3) [000120] ------------ \--* ADD byref $284 N001 ( 1, 1) [000046] ------------ +--* LCL_VAR byref V00 this u:1 (last use) $80 N002 ( 1, 1) [000119] ------------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] $242 optAssertionPropMain morphed tree: N008 ( 13, 13) [000051] -A--GO--R--- * ASG struct (copy) $VN.Void N007 ( 6, 7) [000050] n----------- +--* BLK struct N006 ( 3, 5) [000049] ------------ | \--* ADDR byref $285 N005 ( 3, 4) [000044] U------N---- | \--* LCL_FLD struct V03 loc0 ud:3->4[+0] Fseq[Tx] $404 N004 ( 6, 5) [000047] *---GO------ \--* IND struct N003 ( 3, 3) [000120] ------------ \--* ADD byref $284 N001 ( 1, 1) [000046] ------------ +--* LCL_VAR byref V00 this u:1 (last use) $80 N002 ( 1, 1) [000119] ------------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] $242 Propagating assertions for BB01, stmt STMT00018, tree [000052], tree -> 0 Propagating assertions for BB01, stmt STMT00018, tree [000057], tree -> 0 Propagating assertions for BB01, stmt STMT00018, tree [000058], tree -> 0 Propagating assertions for BB01, stmt STMT00018, tree [000123], tree -> 0 Propagating assertions for BB01, stmt STMT00018, tree [000125], tree -> 0 Propagating assertions for BB01, stmt STMT00018, tree [000126], tree -> 0 Propagating assertions for BB01, stmt STMT00018, tree [000124], tree -> 0 Propagating assertions for BB01, stmt STMT00018, tree [000054], tree -> 0 Propagating assertions for BB01, stmt STMT00018, tree [000121], tree -> 0 Propagating assertions for BB01, stmt STMT00018, tree [000122], tree -> 0 Propagating assertions for BB01, stmt STMT00009, tree [000127], tree -> 0 Propagating assertions for BB01, stmt STMT00009, tree [000059], tree -> 0 *************** In fgDebugCheckBBlist *************** Finishing PHASE Assertion prop *************** Starting PHASE Optimize index checks *************** In OptimizeRangeChecks() Blocks/trees before phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} ***** BB01 STMT00000 (IL 0x000...0x028) N005 ( 16, 16) [000007] -AC-----R--- * ASG ref $200 N004 ( 1, 1) [000006] D------N---- +--* LCL_VAR ref V05 tmp1 d:2 $200 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class $180 ***** BB01 STMT00001 (IL ???... ???) N006 ( 8, 9) [000012] -A--GO------ * ASG int $VN.Void N004 ( 4, 4) [000011] n----O-N---- +--* IND int $2c0 N003 ( 2, 2) [000010] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V05 tmp1 u:2 $200 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD int V02 arg2 u:1[+8] Fseq[Version] $2c0 ***** BB01 STMT00002 (IL ???... ???) N005 ( 16, 16) [000021] -AC-----R--- * ASG ref $201 N004 ( 1, 1) [000020] D------N---- +--* LCL_VAR ref V06 tmp2 d:2 $201 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class $182 ***** BB01 STMT00003 (IL ???... ???) N006 ( 8, 9) [000026] -A--GO------ * ASG long $VN.Void N004 ( 4, 4) [000025] n----O-N---- +--* IND long $300 N003 ( 2, 2) [000024] -------N---- | \--* ADD byref $281 N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V06 tmp2 u:2 $201 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD long V02 arg2 u:1[+0] Fseq[JobGroup] $300 ***** BB01 STMT00012 (IL ???... ???) N004 ( 11, 8) [000077] -A------R--- * ASG ref $200 N003 ( 3, 2) [000076] D------N---- +--* LCL_VAR ref V13 tmp9 d:2 $200 N002 ( 7, 5) [000014] ------------ \--* BOX ref $200 N001 ( 1, 1) [000013] ------------ \--* LCL_VAR ref V05 tmp1 u:2 (last use) $200 ***** BB01 STMT00013 (IL ???... ???) N004 ( 11, 8) [000082] -A------R--- * ASG ref $201 N003 ( 3, 2) [000081] D------N---- +--* LCL_VAR ref V14 tmp10 d:2 $201 N002 ( 7, 5) [000028] ------------ \--* BOX ref $201 N001 ( 1, 1) [000027] ------------ \--* LCL_VAR ref V06 tmp2 u:2 (last use) $201 ***** BB01 STMT00014 (IL ???... ???) N003 ( 5, 4) [000087] -A------R--- * ASG ref $VN.Null N002 ( 3, 2) [000086] D------N---- +--* LCL_VAR ref V15 tmp11 d:2 $VN.Null N001 ( 1, 1) [000085] ------------ \--* CNS_INT ref null $VN.Null ***** BB01 STMT00015 (IL ???... ???) N004 ( 8, 15) [000092] -A--G---R--- * ASG ref N003 ( 3, 2) [000091] D------N---- +--* LCL_VAR ref V16 tmp12 d:2 N002 ( 4, 12) [000090] n---G------- \--* IND ref N001 ( 2, 10) [000103] ------------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 ***** BB01 STMT00017 (IL ???... ???) N013 ( 32, 27) [000099] -ACXG---R--- * ASG ref $1ce N012 ( 1, 1) [000098] D------N---- +--* LCL_VAR ref V12 tmp8 d:2 $1ce N011 ( 32, 27) [000068] --CXG------- \--* CALL ref System.String.FormatHelper $1ce N007 ( 10, 7) [000108] -c---------- arg2 out+00 +--* FIELD_LIST struct $380 N003 ( 3, 2) [000109] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp9 u:2 (last use) $200 N004 ( 3, 2) [000110] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp10 u:2 (last use) $201 N005 ( 1, 1) [000128] ------------ ofs 16 | +--* CNS_INT ref null $VN.Null N006 ( 3, 2) [000112] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp12 u:2 (last use) N009 ( 4, 12) [000105] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000104] ------------ | \--* CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] $185 N010 ( 1, 1) [000060] ------------ arg0 in rdi \--* CNS_INT ref null $VN.Null ***** BB01 STMT00016 (IL ???... ???) N005 ( 16, 9) [000097] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void N003 ( 1, 1) [000096] ------------ arg1 in rsi +--* LCL_VAR ref V12 tmp8 u:2 (last use) $1ce N004 ( 1, 1) [000095] ------------ arg0 in rdi \--* CNS_INT int 3 $44 ***** BB01 STMT00006 (IL 0x025... ???) N003 ( 5, 4) [000035] IA------R--- * ASG struct (init) $VN.Void N002 ( 3, 2) [000032] D------N---- +--* LCL_VAR struct V03 loc0 d:2 N001 ( 1, 1) [000034] ------------ \--* CNS_INT int 0 $40 ***** BB01 STMT00007 (IL 0x02D...0x035) N008 ( 16, 15) [000043] -A-XG---R--- * ASG struct (copy) $VN.Void N007 ( 9, 9) [000042] n----------- +--* OBJ struct N006 ( 3, 5) [000041] ------------ | \--* ADDR byref $283 N005 ( 3, 4) [000036] U------N---- | \--* LCL_FLD struct V03 loc0 ud:2->3[+40] Fseq[Baselib] N004 ( 6, 5) [000039] *--XG------- \--* IND struct N003 ( 3, 3) [000118] ------------ \--* ADD byref $282 N001 ( 1, 1) [000038] ------------ +--* LCL_VAR byref V00 this u:1 $80 N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] $241 ***** BB01 STMT00008 (IL 0x03A...0x042) N008 ( 13, 13) [000051] -A--GO--R--- * ASG struct (copy) $VN.Void N007 ( 6, 7) [000050] n----------- +--* BLK struct N006 ( 3, 5) [000049] ------------ | \--* ADDR byref $285 N005 ( 3, 4) [000044] U------N---- | \--* LCL_FLD struct V03 loc0 ud:3->4[+0] Fseq[Tx] $404 N004 ( 6, 5) [000047] *---GO------ \--* IND struct N003 ( 3, 3) [000120] ------------ \--* ADD byref $284 N001 ( 1, 1) [000046] ------------ +--* LCL_VAR byref V00 this u:1 (last use) $80 N002 ( 1, 1) [000119] ------------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] $242 ***** BB01 STMT00018 (IL 0x047... ???) N010 ( 36, 24) [000122] -ACXG---R--- * ASG struct (copy) $VN.Void N009 ( 3, 2) [000121] D------N---- +--* LCL_VAR struct V17 tmp13 d:2 N008 ( 32, 21) [000054] --CXG------- \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA $38b N003 ( 9, 7) [000058] n----------- arg0 out+00 +--* OBJ struct $388 N002 ( 3, 3) [000057] ------------ | \--* ADDR byref $286 N001 ( 3, 2) [000052] -------N---- | \--* LCL_VAR struct V03 loc0 u:4 (last use) $387 N007 ( 6, 8) [000124] -c---------- arg1 rdi,rsi \--* FIELD_LIST struct $38a N005 ( 3, 4) [000125] ------------ ofs 0 +--* LCL_FLD long V02 arg2 u:1[+0] $142 N006 ( 3, 4) [000126] ------------ ofs 8 \--* LCL_FLD long V02 arg2 u:1[+8] (last use) $143 ***** BB01 STMT00009 (IL 0x047...0x04E) N002 ( 4, 3) [000059] ----G------- * RETURN struct $38f N001 ( 3, 2) [000127] -------N---- \--* LCL_VAR struct V17 tmp13 u:2 (last use) $38e ------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Optimize index checks *************** Starting PHASE Insert GC Polls *************** Finishing PHASE Insert GC Polls [no changes] *************** Starting PHASE Determine first cold block *************** In fgDetermineFirstColdBlock() No procedure splitting will be done for this method *************** Finishing PHASE Determine first cold block Trees before Rationalize IR ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} ***** BB01 STMT00000 (IL 0x000...0x028) N005 ( 16, 16) [000007] -AC-----R--- * ASG ref $200 N004 ( 1, 1) [000006] D------N---- +--* LCL_VAR ref V05 tmp1 d:2 $200 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class $180 ***** BB01 STMT00001 (IL ???... ???) N006 ( 8, 9) [000012] -A--GO------ * ASG int $VN.Void N004 ( 4, 4) [000011] n----O-N---- +--* IND int $2c0 N003 ( 2, 2) [000010] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V05 tmp1 u:2 $200 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD int V02 arg2 u:1[+8] Fseq[Version] $2c0 ***** BB01 STMT00002 (IL ???... ???) N005 ( 16, 16) [000021] -AC-----R--- * ASG ref $201 N004 ( 1, 1) [000020] D------N---- +--* LCL_VAR ref V06 tmp2 d:2 $201 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class $182 ***** BB01 STMT00003 (IL ???... ???) N006 ( 8, 9) [000026] -A--GO------ * ASG long $VN.Void N004 ( 4, 4) [000025] n----O-N---- +--* IND long $300 N003 ( 2, 2) [000024] -------N---- | \--* ADD byref $281 N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V06 tmp2 u:2 $201 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD long V02 arg2 u:1[+0] Fseq[JobGroup] $300 ***** BB01 STMT00012 (IL ???... ???) N004 ( 11, 8) [000077] -A------R--- * ASG ref $200 N003 ( 3, 2) [000076] D------N---- +--* LCL_VAR ref V13 tmp9 d:2 $200 N002 ( 7, 5) [000014] ------------ \--* BOX ref $200 N001 ( 1, 1) [000013] ------------ \--* LCL_VAR ref V05 tmp1 u:2 (last use) $200 ***** BB01 STMT00013 (IL ???... ???) N004 ( 11, 8) [000082] -A------R--- * ASG ref $201 N003 ( 3, 2) [000081] D------N---- +--* LCL_VAR ref V14 tmp10 d:2 $201 N002 ( 7, 5) [000028] ------------ \--* BOX ref $201 N001 ( 1, 1) [000027] ------------ \--* LCL_VAR ref V06 tmp2 u:2 (last use) $201 ***** BB01 STMT00014 (IL ???... ???) N003 ( 5, 4) [000087] -A------R--- * ASG ref $VN.Null N002 ( 3, 2) [000086] D------N---- +--* LCL_VAR ref V15 tmp11 d:2 $VN.Null N001 ( 1, 1) [000085] ------------ \--* CNS_INT ref null $VN.Null ***** BB01 STMT00015 (IL ???... ???) N004 ( 8, 15) [000092] -A--G---R--- * ASG ref N003 ( 3, 2) [000091] D------N---- +--* LCL_VAR ref V16 tmp12 d:2 N002 ( 4, 12) [000090] n---G------- \--* IND ref N001 ( 2, 10) [000103] ------------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 ***** BB01 STMT00017 (IL ???... ???) N013 ( 32, 27) [000099] -ACXG---R--- * ASG ref $1ce N012 ( 1, 1) [000098] D------N---- +--* LCL_VAR ref V12 tmp8 d:2 $1ce N011 ( 32, 27) [000068] --CXG------- \--* CALL ref System.String.FormatHelper $1ce N007 ( 10, 7) [000108] -c---------- arg2 out+00 +--* FIELD_LIST struct $380 N003 ( 3, 2) [000109] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp9 u:2 (last use) $200 N004 ( 3, 2) [000110] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp10 u:2 (last use) $201 N005 ( 1, 1) [000128] ------------ ofs 16 | +--* CNS_INT ref null $VN.Null N006 ( 3, 2) [000112] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp12 u:2 (last use) N009 ( 4, 12) [000105] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000104] ------------ | \--* CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] $185 N010 ( 1, 1) [000060] ------------ arg0 in rdi \--* CNS_INT ref null $VN.Null ***** BB01 STMT00016 (IL ???... ???) N005 ( 16, 9) [000097] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void N003 ( 1, 1) [000096] ------------ arg1 in rsi +--* LCL_VAR ref V12 tmp8 u:2 (last use) $1ce N004 ( 1, 1) [000095] ------------ arg0 in rdi \--* CNS_INT int 3 $44 ***** BB01 STMT00006 (IL 0x025... ???) N003 ( 5, 4) [000035] IA------R--- * ASG struct (init) $VN.Void N002 ( 3, 2) [000032] D------N---- +--* LCL_VAR struct V03 loc0 d:2 N001 ( 1, 1) [000034] ------------ \--* CNS_INT int 0 $40 ***** BB01 STMT00007 (IL 0x02D...0x035) N008 ( 16, 15) [000043] -A-XG---R--- * ASG struct (copy) $VN.Void N007 ( 9, 9) [000042] n----------- +--* OBJ struct N006 ( 3, 5) [000041] ------------ | \--* ADDR byref $283 N005 ( 3, 4) [000036] U------N---- | \--* LCL_FLD struct V03 loc0 ud:2->3[+40] Fseq[Baselib] N004 ( 6, 5) [000039] *--XG------- \--* IND struct N003 ( 3, 3) [000118] ------------ \--* ADD byref $282 N001 ( 1, 1) [000038] ------------ +--* LCL_VAR byref V00 this u:1 $80 N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_Baselib] $241 ***** BB01 STMT00008 (IL 0x03A...0x042) N008 ( 13, 13) [000051] -A--GO--R--- * ASG struct (copy) $VN.Void N007 ( 6, 7) [000050] n----------- +--* BLK struct N006 ( 3, 5) [000049] ------------ | \--* ADDR byref $285 N005 ( 3, 4) [000044] U------N---- | \--* LCL_FLD struct V03 loc0 ud:3->4[+0] Fseq[Tx] $404 N004 ( 6, 5) [000047] *---GO------ \--* IND struct N003 ( 3, 3) [000120] ------------ \--* ADD byref $284 N001 ( 1, 1) [000046] ------------ +--* LCL_VAR byref V00 this u:1 (last use) $80 N002 ( 1, 1) [000119] ------------ \--* CNS_INT long 112 field offset Fseq[m_PayloadsTx] $242 ***** BB01 STMT00018 (IL 0x047... ???) N010 ( 36, 24) [000122] -ACXG---R--- * ASG struct (copy) $VN.Void N009 ( 3, 2) [000121] D------N---- +--* LCL_VAR struct V17 tmp13 d:2 N008 ( 32, 21) [000054] --CXG------- \--* CALL struct Unity.Jobs.IJobExtensions.Schedule,NA $38b N003 ( 9, 7) [000058] n----------- arg0 out+00 +--* OBJ struct $388 N002 ( 3, 3) [000057] ------------ | \--* ADDR byref $286 N001 ( 3, 2) [000052] -------N---- | \--* LCL_VAR struct V03 loc0 u:4 (last use) $387 N007 ( 6, 8) [000124] -c---------- arg1 rdi,rsi \--* FIELD_LIST struct $38a N005 ( 3, 4) [000125] ------------ ofs 0 +--* LCL_FLD long V02 arg2 u:1[+0] $142 N006 ( 3, 4) [000126] ------------ ofs 8 \--* LCL_FLD long V02 arg2 u:1[+8] (last use) $143 ***** BB01 STMT00009 (IL 0x047...0x04E) N002 ( 4, 3) [000059] ----G------- * RETURN struct $38f N001 ( 3, 2) [000127] -------N---- \--* LCL_VAR struct V17 tmp13 u:2 (last use) $38e ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Rationalize IR rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 16, 16) [000007] DAC--------- * STORE_LCL_VAR ref V05 tmp1 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 16, 16) [000021] DAC--------- * STORE_LCL_VAR ref V06 tmp2 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 11, 8) [000077] DA---------- * STORE_LCL_VAR ref V13 tmp9 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 11, 8) [000082] DA---------- * STORE_LCL_VAR ref V14 tmp10 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000087] DA---------- * STORE_LCL_VAR ref V15 tmp11 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 8, 15) [000092] DA--G------- * STORE_LCL_VAR ref V16 tmp12 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N013 ( 32, 27) [000099] DACXG------- * STORE_LCL_VAR ref V12 tmp8 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000035] DA---------- * STORE_LCL_VAR struct V03 loc0 d:2 Rewriting GT_ADDR(GT_LCL_FLD) to GT_LCL_FLD_ADDR: N005 ( 3, 4) [000036] U------N---- t36 = LCL_FLD_ADDR byref V03 loc0 ud:2->3[+40] Fseq[Baselib] Rewriting GT_ASG(OBJ(X), Y) to STORE_OBJ(X,Y): N001 ( 1, 1) [000038] ------------ t38 = LCL_VAR byref V00 this u:1 $80 N002 ( 1, 1) [000117] ------------ t117 = CNS_INT long 16 field offset Fseq[m_Baselib] $241 /--* t38 byref +--* t117 long N003 ( 3, 3) [000118] ------------ t118 = * ADD byref $282 /--* t118 byref N004 ( 6, 5) [000039] *--XG------- t39 = * IND struct N005 ( 3, 4) [000036] U------N---- t36 = LCL_FLD_ADDR byref V03 loc0 ud:2->3[+40] Fseq[Baselib] /--* t36 byref +--* t39 struct N007 ( 9, 9) [000042] nA-XG------- * STORE_OBJ struct (copy) Rewriting GT_ADDR(GT_LCL_FLD) to GT_LCL_FLD_ADDR: N005 ( 3, 4) [000044] U------N---- t44 = LCL_FLD_ADDR byref V03 loc0 ud:3->4[+0] Fseq[Tx] Rewriting GT_ASG(BLK(X), Y) to STORE_BLK(X,Y): N001 ( 1, 1) [000046] ------------ t46 = LCL_VAR byref V00 this u:1 (last use) $80 N002 ( 1, 1) [000119] ------------ t119 = CNS_INT long 112 field offset Fseq[m_PayloadsTx] $242 /--* t46 byref +--* t119 long N003 ( 3, 3) [000120] ------------ t120 = * ADD byref $284 /--* t120 byref N004 ( 6, 5) [000047] *---GO------ t47 = * IND struct N005 ( 3, 4) [000044] U------N---- t44 = LCL_FLD_ADDR byref V03 loc0 ud:3->4[+0] Fseq[Tx] /--* t44 byref +--* t47 struct N007 ( 6, 7) [000050] nA--GO------ * STORE_BLK struct (copy) Rewriting GT_ADDR(GT_LCL_VAR) to GT_LCL_VAR_ADDR: N001 ( 3, 2) [000052] -------N---- t52 = LCL_VAR_ADDR byref V03 loc0 u:4 (last use) rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N010 ( 36, 24) [000122] DACXG------- * STORE_LCL_VAR struct V17 tmp13 d:2 *************** Finishing PHASE Rationalize IR Trees after Rationalize IR ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} [000129] ------------ IL_OFFSET void IL offset: 0x0 N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class $180 /--* t4 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 /--* t5 ref N005 ( 16, 16) [000007] DA---------- * STORE_LCL_VAR ref V05 tmp1 d:2 N001 ( 1, 1) [000008] ------------ t8 = LCL_VAR ref V05 tmp1 u:2 $200 N002 ( 1, 1) [000009] ------------ t9 = CNS_INT long 8 $240 /--* t8 ref +--* t9 long N003 ( 2, 2) [000010] -------N---- t10 = * ADD byref $280 N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD int V02 arg2 u:1[+8] Fseq[Version] $2c0 /--* t10 byref +--* t3 int [000130] -A--GO------ * STOREIND int N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class $182 /--* t18 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 /--* t19 ref N005 ( 16, 16) [000021] DA---------- * STORE_LCL_VAR ref V06 tmp2 d:2 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V06 tmp2 u:2 $201 N002 ( 1, 1) [000023] ------------ t23 = CNS_INT long 8 $240 /--* t22 ref +--* t23 long N003 ( 2, 2) [000024] -------N---- t24 = * ADD byref $281 N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD long V02 arg2 u:1[+0] Fseq[JobGroup] $300 /--* t24 byref +--* t17 long [000131] -A--GO------ * STOREIND long N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR ref V05 tmp1 u:2 (last use) $200 /--* t13 ref N004 ( 11, 8) [000077] DA---------- * STORE_LCL_VAR ref V13 tmp9 d:2 N001 ( 1, 1) [000027] ------------ t27 = LCL_VAR ref V06 tmp2 u:2 (last use) $201 /--* t27 ref N004 ( 11, 8) [000082] DA---------- * STORE_LCL_VAR ref V14 tmp10 d:2 N001 ( 1, 1) [000085] ------------ t85 = CNS_INT ref null $VN.Null /--* t85 ref N003 ( 5, 4) [000087] DA---------- * STORE_LCL_VAR ref V15 tmp11 d:2 N001 ( 2, 10) [000103] ------------ t103 = CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 /--* t103 long N002 ( 4, 12) [000090] n---G------- t90 = * IND ref /--* t90 ref N004 ( 8, 15) [000092] DA--G------- * STORE_LCL_VAR ref V16 tmp12 d:2 N003 ( 3, 2) [000109] ------------ t109 = LCL_VAR ref V13 tmp9 u:2 (last use) $200 N004 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V14 tmp10 u:2 (last use) $201 N005 ( 1, 1) [000128] ------------ t128 = CNS_INT ref null $VN.Null N006 ( 3, 2) [000112] ------------ t112 = LCL_VAR ref V16 tmp12 u:2 (last use) /--* t109 ref +--* t110 ref +--* t128 ref +--* t112 ref N007 ( 10, 7) [000108] -c---------- t108 = * FIELD_LIST struct $380 N008 ( 2, 10) [000104] ------------ t104 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] $185 /--* t104 long N009 ( 4, 12) [000105] n---G------- t105 = * IND ref N010 ( 1, 1) [000060] ------------ t60 = CNS_INT ref null $VN.Null /--* t108 struct arg2 out+00 +--* t105 ref arg1 in rsi +--* t60 ref arg0 in rdi N011 ( 32, 27) [000068] --CXG------- t68 = * CALL ref System.String.FormatHelper $1ce /--* t68 ref N013 ( 32, 27) [000099] DA-XG------- * STORE_LCL_VAR ref V12 tmp8 d:2 N003 ( 1, 1) [000096] ------------ t96 = LCL_VAR ref V12 tmp8 u:2 (last use) $1ce N004 ( 1, 1) [000095] ------------ t95 = CNS_INT int 3 $44 /--* t96 ref arg1 in rsi +--* t95 int arg0 in rdi N005 ( 16, 9) [000097] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void [000132] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 1, 1) [000034] ------------ t34 = CNS_INT int 0 $40 /--* t34 int N003 ( 5, 4) [000035] DA---------- * STORE_LCL_VAR struct V03 loc0 d:2 [000133] ------------ IL_OFFSET void IL offset: 0x2d N001 ( 1, 1) [000038] ------------ t38 = LCL_VAR byref V00 this u:1 $80 N002 ( 1, 1) [000117] ------------ t117 = CNS_INT long 16 field offset Fseq[m_Baselib] $241 /--* t38 byref +--* t117 long N003 ( 3, 3) [000118] ------------ t118 = * ADD byref $282 /--* t118 byref N004 ( 6, 5) [000039] *--XG------- t39 = * IND struct N005 ( 3, 4) [000036] U------N---- t36 = LCL_FLD_ADDR byref V03 loc0 ud:2->3[+40] Fseq[Baselib] /--* t36 byref +--* t39 struct N007 ( 9, 9) [000042] nA-XG------- * STORE_OBJ struct (copy) [000134] ------------ IL_OFFSET void IL offset: 0x3a N001 ( 1, 1) [000046] ------------ t46 = LCL_VAR byref V00 this u:1 (last use) $80 N002 ( 1, 1) [000119] ------------ t119 = CNS_INT long 112 field offset Fseq[m_PayloadsTx] $242 /--* t46 byref +--* t119 long N003 ( 3, 3) [000120] ------------ t120 = * ADD byref $284 /--* t120 byref N004 ( 6, 5) [000047] *---GO------ t47 = * IND struct N005 ( 3, 4) [000044] U------N---- t44 = LCL_FLD_ADDR byref V03 loc0 ud:3->4[+0] Fseq[Tx] /--* t44 byref +--* t47 struct N007 ( 6, 7) [000050] nA--GO------ * STORE_BLK struct (copy) [000135] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000052] -------N---- t52 = LCL_VAR_ADDR byref V03 loc0 u:4 (last use) /--* t52 byref N003 ( 9, 7) [000058] n----------- t58 = * OBJ struct $388 N005 ( 3, 4) [000125] ------------ t125 = LCL_FLD long V02 arg2 u:1[+0] $142 N006 ( 3, 4) [000126] ------------ t126 = LCL_FLD long V02 arg2 u:1[+8] (last use) $143 /--* t125 long +--* t126 long N007 ( 6, 8) [000124] -c---------- t124 = * FIELD_LIST struct $38a /--* t58 struct arg0 out+00 +--* t124 struct arg1 rdi,rsi N008 ( 32, 21) [000054] --CXG------- t54 = * CALL struct Unity.Jobs.IJobExtensions.Schedule,NA $38b /--* t54 struct N010 ( 36, 24) [000122] DA-XG------- * STORE_LCL_VAR struct V17 tmp13 d:2 [000136] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000127] -------N---- t127 = LCL_VAR struct V17 tmp13 u:2 (last use) $38e /--* t127 struct N002 ( 4, 3) [000059] ----G------- * RETURN struct $38f ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Do 'simple' lowering outgoingArgSpaceSize 0 sufficient for call [000005], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000019], which needs 0 Bumping outgoingArgSpaceSize to 32 for call [000068] outgoingArgSpaceSize 32 sufficient for call [000097], which needs 0 Bumping outgoingArgSpaceSize to 96 for call [000054] *************** Finishing PHASE Do 'simple' lowering *************** In fgDebugCheckBBlist Trees before Lowering nodeinfo ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} [000129] ------------ IL_OFFSET void IL offset: 0x0 N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class $180 /--* t4 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 /--* t5 ref N005 ( 16, 16) [000007] DA---------- * STORE_LCL_VAR ref V05 tmp1 d:2 N001 ( 1, 1) [000008] ------------ t8 = LCL_VAR ref V05 tmp1 u:2 $200 N002 ( 1, 1) [000009] ------------ t9 = CNS_INT long 8 $240 /--* t8 ref +--* t9 long N003 ( 2, 2) [000010] -------N---- t10 = * ADD byref $280 N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD int V02 arg2 u:1[+8] Fseq[Version] $2c0 /--* t10 byref +--* t3 int [000130] -A--GO------ * STOREIND int N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class $182 /--* t18 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 /--* t19 ref N005 ( 16, 16) [000021] DA---------- * STORE_LCL_VAR ref V06 tmp2 d:2 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V06 tmp2 u:2 $201 N002 ( 1, 1) [000023] ------------ t23 = CNS_INT long 8 $240 /--* t22 ref +--* t23 long N003 ( 2, 2) [000024] -------N---- t24 = * ADD byref $281 N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD long V02 arg2 u:1[+0] Fseq[JobGroup] $300 /--* t24 byref +--* t17 long [000131] -A--GO------ * STOREIND long N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR ref V05 tmp1 u:2 (last use) $200 /--* t13 ref N004 ( 11, 8) [000077] DA---------- * STORE_LCL_VAR ref V13 tmp9 d:2 N001 ( 1, 1) [000027] ------------ t27 = LCL_VAR ref V06 tmp2 u:2 (last use) $201 /--* t27 ref N004 ( 11, 8) [000082] DA---------- * STORE_LCL_VAR ref V14 tmp10 d:2 N001 ( 1, 1) [000085] ------------ t85 = CNS_INT ref null $VN.Null /--* t85 ref N003 ( 5, 4) [000087] DA---------- * STORE_LCL_VAR ref V15 tmp11 d:2 N001 ( 2, 10) [000103] ------------ t103 = CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 /--* t103 long N002 ( 4, 12) [000090] n---G------- t90 = * IND ref /--* t90 ref N004 ( 8, 15) [000092] DA--G------- * STORE_LCL_VAR ref V16 tmp12 d:2 N003 ( 3, 2) [000109] ------------ t109 = LCL_VAR ref V13 tmp9 u:2 (last use) $200 N004 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V14 tmp10 u:2 (last use) $201 N005 ( 1, 1) [000128] ------------ t128 = CNS_INT ref null $VN.Null N006 ( 3, 2) [000112] ------------ t112 = LCL_VAR ref V16 tmp12 u:2 (last use) /--* t109 ref +--* t110 ref +--* t128 ref +--* t112 ref N007 ( 10, 7) [000108] -c---------- t108 = * FIELD_LIST struct $380 N008 ( 2, 10) [000104] ------------ t104 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] $185 /--* t104 long N009 ( 4, 12) [000105] n---G------- t105 = * IND ref N010 ( 1, 1) [000060] ------------ t60 = CNS_INT ref null $VN.Null /--* t108 struct arg2 out+00 +--* t105 ref arg1 in rsi +--* t60 ref arg0 in rdi N011 ( 32, 27) [000068] --CXG------- t68 = * CALL ref System.String.FormatHelper $1ce /--* t68 ref N013 ( 32, 27) [000099] DA-XG------- * STORE_LCL_VAR ref V12 tmp8 d:2 N003 ( 1, 1) [000096] ------------ t96 = LCL_VAR ref V12 tmp8 u:2 (last use) $1ce N004 ( 1, 1) [000095] ------------ t95 = CNS_INT int 3 $44 /--* t96 ref arg1 in rsi +--* t95 int arg0 in rdi N005 ( 16, 9) [000097] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void [000132] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 1, 1) [000034] ------------ t34 = CNS_INT int 0 $40 /--* t34 int N003 ( 5, 4) [000035] DA---------- * STORE_LCL_VAR struct V03 loc0 d:2 [000133] ------------ IL_OFFSET void IL offset: 0x2d N001 ( 1, 1) [000038] ------------ t38 = LCL_VAR byref V00 this u:1 $80 N002 ( 1, 1) [000117] ------------ t117 = CNS_INT long 16 field offset Fseq[m_Baselib] $241 /--* t38 byref +--* t117 long N003 ( 3, 3) [000118] ------------ t118 = * ADD byref $282 /--* t118 byref N004 ( 6, 5) [000039] *--XG------- t39 = * IND struct N005 ( 3, 4) [000036] U------N---- t36 = LCL_FLD_ADDR byref V03 loc0 ud:2->3[+40] Fseq[Baselib] /--* t36 byref +--* t39 struct N007 ( 9, 9) [000042] nA-XG------- * STORE_OBJ struct (copy) [000134] ------------ IL_OFFSET void IL offset: 0x3a N001 ( 1, 1) [000046] ------------ t46 = LCL_VAR byref V00 this u:1 (last use) $80 N002 ( 1, 1) [000119] ------------ t119 = CNS_INT long 112 field offset Fseq[m_PayloadsTx] $242 /--* t46 byref +--* t119 long N003 ( 3, 3) [000120] ------------ t120 = * ADD byref $284 /--* t120 byref N004 ( 6, 5) [000047] *---GO------ t47 = * IND struct N005 ( 3, 4) [000044] U------N---- t44 = LCL_FLD_ADDR byref V03 loc0 ud:3->4[+0] Fseq[Tx] /--* t44 byref +--* t47 struct N007 ( 6, 7) [000050] nA--GO------ * STORE_BLK struct (copy) [000135] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000052] -------N---- t52 = LCL_VAR_ADDR byref V03 loc0 u:4 (last use) /--* t52 byref N003 ( 9, 7) [000058] n----------- t58 = * OBJ struct $388 N005 ( 3, 4) [000125] ------------ t125 = LCL_FLD long V02 arg2 u:1[+0] $142 N006 ( 3, 4) [000126] ------------ t126 = LCL_FLD long V02 arg2 u:1[+8] (last use) $143 /--* t125 long +--* t126 long N007 ( 6, 8) [000124] -c---------- t124 = * FIELD_LIST struct $38a /--* t58 struct arg0 out+00 +--* t124 struct arg1 rdi,rsi N008 ( 32, 21) [000054] --CXG------- t54 = * CALL struct Unity.Jobs.IJobExtensions.Schedule,NA $38b /--* t54 struct N010 ( 36, 24) [000122] DA-XG------- * STORE_LCL_VAR struct V17 tmp13 d:2 [000136] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000127] -------N---- t127 = LCL_VAR struct V17 tmp13 u:2 (last use) $38e /--* t127 struct N002 ( 4, 3) [000059] ----G------- * RETURN struct $38f ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Lowering nodeinfo lowering call (before): N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class $180 /--* t4 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000101] ----------L- * ARGPLACE long $180 late: ====== lowering arg : N002 ( 2, 10) [000004] ------------ * CNS_INT(h) long 0x7f6678beb1c0 class $180 new node is : [000137] ------------ * PUTARG_REG long REG rdi lowering call (after): N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class $180 /--* t4 long [000137] ------------ t137 = * PUTARG_REG long REG rdi /--* t137 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 lowering store lcl var/field (before): N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class $180 /--* t4 long [000137] ------------ t137 = * PUTARG_REG long REG rdi /--* t137 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 /--* t5 ref N005 ( 16, 16) [000007] DA---------- * STORE_LCL_VAR ref V05 tmp1 d:2 lowering store lcl var/field (after): N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class $180 /--* t4 long [000137] ------------ t137 = * PUTARG_REG long REG rdi /--* t137 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 /--* t5 ref N005 ( 16, 16) [000007] DA---------- * STORE_LCL_VAR ref V05 tmp1 d:2 Addressing mode: Base N001 ( 1, 1) [000008] ------------ * LCL_VAR ref V05 tmp1 u:2 $200 + 8 Removing unused node: N002 ( 1, 1) [000009] -c---------- * CNS_INT ScheduleSend: version=0 jobgroup=1905 long 8 $240 New addressing mode node: N003 ( 2, 2) [000010] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N001 ( 1, 1) [000008] ------------ t8 = LCL_VAR ref V05 tmp1 u:2 $200 /--* t8 ref N003 ( 2, 2) [000010] ------------ t10 = * LEA(b+8) byref N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD int V02 arg2 u:1[+8] Fseq[Version] $2c0 /--* t10 byref +--* t3 int [000130] -A--GO------ * STOREIND int lowering call (before): N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class $182 /--* t18 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000102] ----------L- * ARGPLACE long $182 late: ====== lowering arg : N002 ( 2, 10) [000018] ------------ * CNS_INT(h) long 0x7f6678c127f0 class $182 new node is : [000138] ------------ * PUTARG_REG long REG rdi lowering call (after): N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class $182 /--* t18 long [000138] ------------ t138 = * PUTARG_REG long REG rdi /--* t138 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 lowering store lcl var/field (before): N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class $182 /--* t18 long [000138] ------------ t138 = * PUTARG_REG long REG rdi /--* t138 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 /--* t19 ref N005 ( 16, 16) [000021] DA---------- * STORE_LCL_VAR ref V06 tmp2 d:2 lowering store lcl var/field (after): N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class $182 /--* t18 long [000138] ------------ t138 = * PUTARG_REG long REG rdi /--* t138 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 /--* t19 ref N005 ( 16, 16) [000021] DA---------- * STORE_LCL_VAR ref V06 tmp2 d:2 Addressing mode: Base N001 ( 1, 1) [000022] ------------ * LCL_VAR ref V06 tmp2 u:2 $201 + 8 Removing unused node: N002 ( 1, 1) [000023] -c---------- * CNS_INT long 8 $240 New addressing mode node: N003 ( 2, 2) [000024] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V06 tmp2 u:2 $201 /--* t22 ref N003 ( 2, 2) [000024] ------------ t24 = * LEA(b+8) byref N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD long V02 arg2 u:1[+0] Fseq[JobGroup] $300 /--* t24 byref +--* t17 long [000131] -A--GO------ * STOREIND long lowering store lcl var/field (before): N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR ref V05 tmp1 u:2 (last use) $200 /--* t13 ref N004 ( 11, 8) [000077] DA---------- * STORE_LCL_VAR ref V13 tmp9 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR ref V05 tmp1 u:2 (last use) $200 /--* t13 ref N004 ( 11, 8) [000077] DA---------- * STORE_LCL_VAR ref V13 tmp9 d:2 lowering store lcl var/field (before): N001 ( 1, 1) [000027] ------------ t27 = LCL_VAR ref V06 tmp2 u:2 (last use) $201 /--* t27 ref N004 ( 11, 8) [000082] DA---------- * STORE_LCL_VAR ref V14 tmp10 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [000027] ------------ t27 = LCL_VAR ref V06 tmp2 u:2 (last use) $201 /--* t27 ref N004 ( 11, 8) [000082] DA---------- * STORE_LCL_VAR ref V14 tmp10 d:2 lowering store lcl var/field (before): N001 ( 1, 1) [000085] ------------ t85 = CNS_INT ref null $VN.Null /--* t85 ref N003 ( 5, 4) [000087] DA---------- * STORE_LCL_VAR ref V15 tmp11 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [000085] ------------ t85 = CNS_INT ref null $VN.Null /--* t85 ref N003 ( 5, 4) [000087] DA---------- * STORE_LCL_VAR ref V15 tmp11 d:2 lowering store lcl var/field (before): N001 ( 2, 10) [000103] ------------ t103 = CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 /--* t103 long N002 ( 4, 12) [000090] n---G------- t90 = * IND ref /--* t90 ref N004 ( 8, 15) [000092] DA--G------- * STORE_LCL_VAR ref V16 tmp12 d:2 lowering store lcl var/field (after): N001 ( 2, 10) [000103] ------------ t103 = CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 /--* t103 long N002 ( 4, 12) [000090] n---G------- t90 = * IND ref /--* t90 ref N004 ( 8, 15) [000092] DA--G------- * STORE_LCL_VAR ref V16 tmp12 d:2 lowering call (before): N003 ( 3, 2) [000109] ------------ t109 = LCL_VAR ref V13 tmp9 u:2 (last use) $200 N004 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V14 tmp10 u:2 (last use) $201 N005 ( 1, 1) [000128] ------------ t128 = CNS_INT ref null $VN.Null N006 ( 3, 2) [000112] ------------ t112 = LCL_VAR ref V16 tmp12 u:2 (last use) /--* t109 ref +--* t110 ref +--* t128 ref +--* t112 ref N007 ( 10, 7) [000108] -c---------- t108 = * FIELD_LIST struct $380 N008 ( 2, 10) [000104] ------------ t104 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] $185 /--* t104 long N009 ( 4, 12) [000105] n---G------- t105 = * IND ref N010 ( 1, 1) [000060] ------------ t60 = CNS_INT ref null $VN.Null /--* t108 struct arg2 out+00 +--* t105 ref arg1 in rsi +--* t60 ref arg0 in rdi N011 ( 32, 27) [000068] --CXG------- t68 = * CALL ref System.String.FormatHelper $1ce objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000107] ----------L- * ARGPLACE ref $VN.Null lowering arg : N002 ( 0, 0) [000106] ----------L- * ARGPLACE ref lowering arg : N007 ( 10, 7) [000108] -c---------- * FIELD_LIST struct $380 new node is : [000139] ------------ * PUTARG_STK [+0x00] void (4 slots) late: ====== lowering arg : N009 ( 4, 12) [000105] n---G------- * IND ref new node is : [000140] ----G------- * PUTARG_REG ref REG rsi lowering arg : N010 ( 1, 1) [000060] ------------ * CNS_INT ref null $VN.Null new node is : [000141] ------------ * PUTARG_REG ref REG rdi lowering call (after): N003 ( 3, 2) [000109] ------------ t109 = LCL_VAR ref V13 tmp9 u:2 (last use) $200 N004 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V14 tmp10 u:2 (last use) $201 N005 ( 1, 1) [000128] ------------ t128 = CNS_INT ref null $VN.Null N006 ( 3, 2) [000112] ------------ t112 = LCL_VAR ref V16 tmp12 u:2 (last use) /--* t109 ref +--* t110 ref +--* t128 ref +--* t112 ref N007 ( 10, 7) [000108] -c---------- t108 = * FIELD_LIST struct $380 /--* t108 struct [000139] ------------ * PUTARG_STK [+0x00] void (4 slots) N008 ( 2, 10) [000104] ------------ t104 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] $185 /--* t104 long N009 ( 4, 12) [000105] n---G------- t105 = * IND ref /--* t105 ref [000140] ----G------- t140 = * PUTARG_REG ref REG rsi N010 ( 1, 1) [000060] ------------ t60 = CNS_INT ref null $VN.Null /--* t60 ref [000141] ------------ t141 = * PUTARG_REG ref REG rdi /--* t140 ref arg1 in rsi +--* t141 ref arg0 in rdi N011 ( 32, 27) [000068] --CXG------- t68 = * CALL ref System.String.FormatHelper $1ce lowering store lcl var/field (before): N003 ( 3, 2) [000109] ------------ t109 = LCL_VAR ref V13 tmp9 u:2 (last use) $200 N004 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V14 tmp10 u:2 (last use) $201 N005 ( 1, 1) [000128] ------------ t128 = CNS_INT ref null $VN.Null N006 ( 3, 2) [000112] ------------ t112 = LCL_VAR ref V16 tmp12 u:2 (last use) /--* t109 ref +--* t110 ref +--* t128 ref +--* t112 ref N007 ( 10, 7) [000108] -c---------- t108 = * FIELD_LIST struct $380 /--* t108 struct [000139] ------------ * PUTARG_STK [+0x00] void (4 slots) N008 ( 2, 10) [000104] ------------ t104 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] $185 /--* t104 long N009 ( 4, 12) [000105] n---G------- t105 = * IND ref /--* t105 ref [000140] ----G------- t140 = * PUTARG_REG ref REG rsi N010 ( 1, 1) [000060] ------------ t60 = CNS_INT ref null $VN.Null /--* t60 ref [000141] ------------ t141 = * PUTARG_REG ref REG rdi /--* t140 ref arg1 in rsi +--* t141 ref arg0 in rdi N011 ( 32, 27) [000068] --CXG------- t68 = * CALL ref System.String.FormatHelper $1ce /--* t68 ref N013 ( 32, 27) [000099] DA-XG------- * STORE_LCL_VAR ref V12 tmp8 d:2 lowering store lcl var/field (after): N003 ( 3, 2) [000109] ------------ t109 = LCL_VAR ref V13 tmp9 u:2 (last use) $200 N004 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V14 tmp10 u:2 (last use) $201 N005 ( 1, 1) [000128] ------------ t128 = CNS_INT ref null $VN.Null N006 ( 3, 2) [000112] ------------ t112 = LCL_VAR ref V16 tmp12 u:2 (last use) /--* t109 ref +--* t110 ref +--* t128 ref +--* t112 ref N007 ( 10, 7) [000108] -c---------- t108 = * FIELD_LIST struct $380 /--* t108 struct [000139] ------------ * PUTARG_STK [+0x00] void (4 slots) N008 ( 2, 10) [000104] ------------ t104 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] $185 /--* t104 long N009 ( 4, 12) [000105] n---G------- t105 = * IND ref /--* t105 ref [000140] ----G------- t140 = * PUTARG_REG ref REG rsi N010 ( 1, 1) [000060] ------------ t60 = CNS_INT ref null $VN.Null /--* t60 ref [000141] ------------ t141 = * PUTARG_REG ref REG rdi /--* t140 ref arg1 in rsi +--* t141 ref arg0 in rdi N011 ( 32, 27) [000068] --CXG------- t68 = * CALL ref System.String.FormatHelper $1ce /--* t68 ref N013 ( 32, 27) [000099] DA-XG------- * STORE_LCL_VAR ref V12 tmp8 d:2 lowering call (before): N003 ( 1, 1) [000096] ------------ t96 = LCL_VAR ref V12 tmp8 u:2 (last use) $1ce N004 ( 1, 1) [000095] ------------ t95 = CNS_INT int 3 $44 /--* t96 ref arg1 in rsi +--* t95 int arg0 in rdi N005 ( 16, 9) [000097] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000114] ----------L- * ARGPLACE int $44 lowering arg : N002 ( 0, 0) [000113] ----------L- * ARGPLACE ref $1ce late: ====== lowering arg : N003 ( 1, 1) [000096] ------------ * LCL_VAR ref V12 tmp8 u:2 (last use) $1ce new node is : [000142] ------------ * PUTARG_REG ref REG rsi lowering arg : N004 ( 1, 1) [000095] ------------ * CNS_INT int 3 $44 new node is : [000143] ------------ * PUTARG_REG int REG rdi lowering call (after): N003 ( 1, 1) [000096] ------------ t96 = LCL_VAR ref V12 tmp8 u:2 (last use) $1ce /--* t96 ref [000142] ------------ t142 = * PUTARG_REG ref REG rsi N004 ( 1, 1) [000095] ------------ t95 = CNS_INT int 3 $44 /--* t95 int [000143] ------------ t143 = * PUTARG_REG int REG rdi /--* t142 ref arg1 in rsi +--* t143 int arg0 in rdi N005 ( 16, 9) [000097] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void lowering store lcl var/field (before): N001 ( 1, 1) [000034] ------------ t34 = CNS_INT int 0 $40 /--* t34 int N003 ( 5, 4) [000035] DA---------- * STORE_LCL_VAR struct V03 loc0 d:2 Addressing mode: Base N001 ( 1, 1) [000038] ------------ * LCL_VAR byref V00 this u:1 $80 + 16 Removing unused node: N002 ( 1, 1) [000117] -c---------- * CNS_INT long 16 field offset Fseq[m_Baselib] $241 New addressing mode node: N003 ( 3, 3) [000118] ------------ * LEA(b+16) byref Addressing mode: Base N001 ( 1, 1) [000046] ------------ * LCL_VAR byref V00 this u:1 (last use) $80 + 112 Removing unused node: N002 ( 1, 1) [000119] -c---------- * CNS_INT long 112 field offset Fseq[m_PayloadsTx] $242 New addressing mode node: N003 ( 3, 3) [000120] ------------ * LEA(b+112) byref lowering call (before): N001 ( 3, 2) [000052] -c-----N---- t52 = LCL_VAR_ADDR byref V03 loc0 u:4 (last use) /--* t52 byref N003 ( 9, 7) [000058] n----------- t58 = * OBJ struct $388 N005 ( 3, 4) [000125] ------------ t125 = LCL_FLD long V02 arg2 u:1[+0] $142 N006 ( 3, 4) [000126] ------------ t126 = LCL_FLD long V02 arg2 u:1[+8] (last use) $143 /--* t125 long +--* t126 long N007 ( 6, 8) [000124] -c---------- t124 = * FIELD_LIST struct $38a /--* t58 struct arg0 out+00 +--* t124 struct arg1 rdi,rsi N008 ( 32, 21) [000054] --CXG------- t54 = * CALL struct Unity.Jobs.IJobExtensions.Schedule,NA $38b objp: ====== args: ====== lowering arg : N003 ( 9, 7) [000058] n----------- * OBJ struct $388 new node is : [000145] ------------ * PUTARG_STK [+0x00] void (12 slots) lowering arg : N004 ( 0, 0) [000123] ----------L- * ARGPLACE struct => [clsHnd=795C7A00] $38a late: ====== lowering arg : N007 ( 6, 8) [000124] -c---------- * FIELD_LIST struct $38a lowering call (after): N001 ( 3, 2) [000052] -c-----N---- t52 = LCL_VAR_ADDR byref V03 loc0 u:4 (last use) /--* t52 byref N003 ( 9, 7) [000058] nc---------- t58 = * OBJ struct $388 /--* t58 struct [000145] ------------ * PUTARG_STK [+0x00] void (12 slots) (RepInstr) N005 ( 3, 4) [000125] ------------ t125 = LCL_FLD long V02 arg2 u:1[+0] $142 /--* t125 long [000146] ------------ t146 = * PUTARG_REG long REG rdi N006 ( 3, 4) [000126] ------------ t126 = LCL_FLD long V02 arg2 u:1[+8] (last use) $143 /--* t126 long [000147] ------------ t147 = * PUTARG_REG long REG rsi /--* t146 long +--* t147 long N007 ( 6, 8) [000124] -c---------- t124 = * FIELD_LIST struct $38a /--* t124 struct arg1 rdi,rsi N008 ( 32, 21) [000054] --CXG------- t54 = * CALL struct Unity.Jobs.IJobExtensions.Schedule,NA $38b lowering store lcl var/field (before): N001 ( 3, 2) [000052] -c-----N---- t52 = LCL_VAR_ADDR byref V03 loc0 u:4 (last use) /--* t52 byref N003 ( 9, 7) [000058] nc---------- t58 = * OBJ struct $388 /--* t58 struct [000145] ------------ * PUTARG_STK [+0x00] void (12 slots) (RepInstr) N005 ( 3, 4) [000125] ------------ t125 = LCL_FLD long V02 arg2 u:1[+0] $142 /--* t125 long [000146] ------------ t146 = * PUTARG_REG long REG rdi N006 ( 3, 4) [000126] ------------ t126 = LCL_FLD long V02 arg2 u:1[+8] (last use) $143 /--* t126 long [000147] ------------ t147 = * PUTARG_REG long REG rsi /--* t146 long +--* t147 long N007 ( 6, 8) [000124] -c---------- t124 = * FIELD_LIST struct $38a /--* t124 struct arg1 rdi,rsi N008 ( 32, 21) [000054] --CXG------- t54 = * CALL struct Unity.Jobs.IJobExtensions.Schedule,NA $38b /--* t54 struct N010 ( 36, 24) [000122] DA-XG------- * STORE_LCL_VAR struct V17 tmp13 d:2 lowering store lcl var/field (after): N001 ( 3, 2) [000052] -c-----N---- t52 = LCL_VAR_ADDR byref V03 loc0 u:4 (last use) /--* t52 byref N003 ( 9, 7) [000058] nc---------- t58 = * OBJ struct $388 /--* t58 struct [000145] ------------ * PUTARG_STK [+0x00] void (12 slots) (RepInstr) N005 ( 3, 4) [000125] ------------ t125 = LCL_FLD long V02 arg2 u:1[+0] $142 /--* t125 long [000146] ------------ t146 = * PUTARG_REG long REG rdi N006 ( 3, 4) [000126] ------------ t126 = LCL_FLD long V02 arg2 u:1[+8] (last use) $143 /--* t126 long [000147] ------------ t147 = * PUTARG_REG long REG rsi /--* t146 long +--* t147 long N007 ( 6, 8) [000124] -c---------- t124 = * FIELD_LIST struct $38a /--* t124 struct arg1 rdi,rsi N008 ( 32, 21) [000054] --CXG------- t54 = * CALL struct Unity.Jobs.IJobExtensions.Schedule,NA $38b /--* t54 struct N010 ( 36, 24) [000122] DA-XG------- * STORE_LCL_VAR struct V17 tmp13 d:2 lowering GT_RETURN N002 ( 4, 3) [000059] ----G------- * RETURN struct $38f ============**** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 Lower has completed modifying nodes. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} [000129] ------------ IL_OFFSET void IL offset: 0x0 N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class $180 /--* t4 long [000137] ------------ t137 = * PUTARG_REG long REG rdi /--* t137 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 /--* t5 ref N005 ( 16, 16) [000007] DA---------- * STORE_LCL_VAR ref V05 tmp1 d:2 N001 ( 1, 1) [000008] ------------ t8 = LCL_VAR ref V05 tmp1 u:2 $200 /--* t8 ref N003 ( 2, 2) [000010] -c---------- t10 = * LEA(b+8) byref N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD int V02 arg2 u:1[+8] Fseq[Version] $2c0 /--* t10 byref +--* t3 int [000130] -A--GO------ * STOREIND int N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class $182 /--* t18 long [000138] ------------ t138 = * PUTARG_REG long REG rdi /--* t138 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 /--* t19 ref N005 ( 16, 16) [000021] DA---------- * STORE_LCL_VAR ref V06 tmp2 d:2 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V06 tmp2 u:2 $201 /--* t22 ref N003 ( 2, 2) [000024] -c---------- t24 = * LEA(b+8) byref N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD long V02 arg2 u:1[+0] Fseq[JobGroup] $300 /--* t24 byref +--* t17 long [000131] -A--GO------ * STOREIND long N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR ref V05 tmp1 u:2 (last use) $200 /--* t13 ref N004 ( 11, 8) [000077] DA---------- * STORE_LCL_VAR ref V13 tmp9 d:2 N001 ( 1, 1) [000027] ------------ t27 = LCL_VAR ref V06 tmp2 u:2 (last use) $201 /--* t27 ref N004 ( 11, 8) [000082] DA---------- * STORE_LCL_VAR ref V14 tmp10 d:2 N001 ( 1, 1) [000085] ------------ t85 = CNS_INT ref null $VN.Null /--* t85 ref N003 ( 5, 4) [000087] DA---------- * STORE_LCL_VAR ref V15 tmp11 d:2 N001 ( 2, 10) [000103] ------------ t103 = CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 /--* t103 long N002 ( 4, 12) [000090] n---G------- t90 = * IND ref /--* t90 ref N004 ( 8, 15) [000092] DA--G------- * STORE_LCL_VAR ref V16 tmp12 d:2 N003 ( 3, 2) [000109] ------------ t109 = LCL_VAR ref V13 tmp9 u:2 (last use) $200 N004 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V14 tmp10 u:2 (last use) $201 N005 ( 1, 1) [000128] ------------ t128 = CNS_INT ref null $VN.Null N006 ( 3, 2) [000112] ------------ t112 = LCL_VAR ref V16 tmp12 u:2 (last use) /--* t109 ref +--* t110 ref +--* t128 ref +--* t112 ref N007 ( 10, 7) [000108] -c---------- t108 = * FIELD_LIST struct $380 /--* t108 struct [000139] ------------ * PUTARG_STK [+0x00] void (4 slots) N008 ( 2, 10) [000104] ------------ t104 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] $185 /--* t104 long N009 ( 4, 12) [000105] n---G------- t105 = * IND ref /--* t105 ref [000140] ----G------- t140 = * PUTARG_REG ref REG rsi N010 ( 1, 1) [000060] ------------ t60 = CNS_INT ref null $VN.Null /--* t60 ref [000141] ------------ t141 = * PUTARG_REG ref REG rdi /--* t140 ref arg1 in rsi +--* t141 ref arg0 in rdi N011 ( 32, 27) [000068] --CXG------- t68 = * CALL ref System.String.FormatHelper $1ce /--* t68 ref N013 ( 32, 27) [000099] DA-XG------- * STORE_LCL_VAR ref V12 tmp8 d:2 N003 ( 1, 1) [000096] ------------ t96 = LCL_VAR ref V12 tmp8 u:2 (last use) $1ce /--* t96 ref [000142] ------------ t142 = * PUTARG_REG ref REG rsi N004 ( 1, 1) [000095] ------------ t95 = CNS_INT int 3 $44 /--* t95 int [000143] ------------ t143 = * PUTARG_REG int REG rdi /--* t142 ref arg1 in rsi +--* t143 int arg0 in rdi N005 ( 16, 9) [000097] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void [000132] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 1, 1) [000034] -c---------- t34 = CNS_INT int 0 $40 [000144] Dc-----N---- t144 = LCL_VAR_ADDR byref V03 loc0 /--* t144 byref +--* t34 int N003 ( 5, 4) [000035] sA---------- * STORE_BLK struct (init) (Unroll) [000133] ------------ IL_OFFSET void IL offset: 0x2d N001 ( 1, 1) [000038] ------------ t38 = LCL_VAR byref V00 this u:1 $80 /--* t38 byref N003 ( 3, 3) [000118] -c---------- t118 = * LEA(b+16) byref /--* t118 byref N004 ( 6, 5) [000039] *c-XG------- t39 = * IND struct N005 ( 3, 4) [000036] Uc-----N---- t36 = LCL_FLD_ADDR byref V03 loc0 ud:2->3[+40] Fseq[Baselib] /--* t36 byref +--* t39 struct N007 ( 9, 9) [000042] nA-XG------- * STORE_BLK struct (copy) (Unroll) [000134] ------------ IL_OFFSET void IL offset: 0x3a N001 ( 1, 1) [000046] ------------ t46 = LCL_VAR byref V00 this u:1 (last use) $80 /--* t46 byref N003 ( 3, 3) [000120] -c---------- t120 = * LEA(b+112) byref /--* t120 byref N004 ( 6, 5) [000047] *c--GO------ t47 = * IND struct N005 ( 3, 4) [000044] Uc-----N---- t44 = LCL_FLD_ADDR byref V03 loc0 ud:3->4[+0] Fseq[Tx] /--* t44 byref +--* t47 struct N007 ( 6, 7) [000050] nA--GO------ * STORE_BLK struct (copy) (Unroll) [000135] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000052] -c-----N---- t52 = LCL_VAR_ADDR byref V03 loc0 u:4 (last use) /--* t52 byref N003 ( 9, 7) [000058] nc---------- t58 = * OBJ struct $388 /--* t58 struct [000145] ------------ * PUTARG_STK [+0x00] void (12 slots) (RepInstr) N005 ( 3, 4) [000125] ------------ t125 = LCL_FLD long V02 arg2 u:1[+0] $142 /--* t125 long [000146] ------------ t146 = * PUTARG_REG long REG rdi N006 ( 3, 4) [000126] ------------ t126 = LCL_FLD long V02 arg2 u:1[+8] (last use) $143 /--* t126 long [000147] ------------ t147 = * PUTARG_REG long REG rsi /--* t146 long +--* t147 long N007 ( 6, 8) [000124] -c---------- t124 = * FIELD_LIST struct $38a /--* t124 struct arg1 rdi,rsi N008 ( 32, 21) [000054] --CXG------- t54 = * CALL struct Unity.Jobs.IJobExtensions.Schedule,NA $38b /--* t54 struct N010 ( 36, 24) [000122] DA-XG------- * STORE_LCL_VAR struct V17 tmp13 d:2 [000136] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000127] -c-----N---- t127 = LCL_VAR struct V17 tmp13 u:2 (last use) $38e /--* t127 struct N002 ( 4, 3) [000059] ----G------- * RETURN struct $38f ------------------------------------------------------------------------------------------------------------------- *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V05: refCnt = 1, refCntWtd = 2 New refCnts for V05: refCnt = 2, refCntWtd = 4 New refCnts for V02: refCnt = 1, refCntWtd = 1 New refCnts for V06: refCnt = 1, refCntWtd = 2 New refCnts for V06: refCnt = 2, refCntWtd = 4 New refCnts for V02: refCnt = 2, refCntWtd = 2 New refCnts for V05: refCnt = 3, refCntWtd = 6 New refCnts for V13: refCnt = 1, refCntWtd = 1 New refCnts for V06: refCnt = 3, refCntWtd = 6 New refCnts for V14: refCnt = 1, refCntWtd = 1 New refCnts for V15: refCnt = 1, refCntWtd = 1 New refCnts for V16: refCnt = 1, refCntWtd = 1 New refCnts for V13: refCnt = 2, refCntWtd = 2 New refCnts for V14: refCnt = 2, refCntWtd = 2 New refCnts for V16: refCnt = 2, refCntWtd = 2 New refCnts for V12: refCnt = 1, refCntWtd = 2 New refCnts for V12: refCnt = 2, refCntWtd = 4 New refCnts for V03: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 1, refCntWtd = 1 New refCnts for V03: refCnt = 2, refCntWtd = 2 New refCnts for V00: refCnt = 2, refCntWtd = 2 New refCnts for V03: refCnt = 3, refCntWtd = 3 New refCnts for V03: refCnt = 4, refCntWtd = 4 New refCnts for V02: refCnt = 3, refCntWtd = 3 New refCnts for V02: refCnt = 4, refCntWtd = 4 New refCnts for V17: refCnt = 1, refCntWtd = 1 New refCnts for V17: refCnt = 2, refCntWtd = 2 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 3, refCntWtd = 3 New refCnts for V00: refCnt = 4, refCntWtd = 4 New refCnts for V02: refCnt = 5, refCntWtd = 5 New refCnts for V02: refCnt = 6, refCntWtd = 6 *************** In fgLocalVarLiveness() ; Initial local variable assignments ; ; V00 this byref this ; V01 arg1 struct do-not-enreg[S] ; V02 arg2 struct do-not-enreg[SFA] multireg-arg ; V03 loc0 struct do-not-enreg[SFB] ld-addr-op ; V04 OutArgs lclBlk <96> "OutgoingArgSpace" ; V05 tmp1 ref class-hnd exact "Single-def Box Helper" ; V06 tmp2 ref class-hnd exact "Single-def Box Helper" ; V07 tmp3 ref class-hnd exact "Inlining Arg" ; V08 tmp4 ref class-hnd exact "Inlining Arg" ; V09 tmp5 struct "NewObj constructor temp" ; V10 tmp6 ref class-hnd exact "Inlining Arg" ; V11 tmp7 ref class-hnd exact "Inlining Arg" ; V12 tmp8 ref class-hnd "Inlining Arg" ; V13 tmp9 ref V09._arg0(offs=0x00) P-INDEP "field V09._arg0 (fldOffset=0x0)" ; V14 tmp10 ref V09._arg1(offs=0x08) P-INDEP "field V09._arg1 (fldOffset=0x8)" ; V15 tmp11 ref V09._arg2(offs=0x10) P-INDEP "field V09._arg2 (fldOffset=0x10)" ; V16 tmp12 ref V09._args(offs=0x18) P-INDEP "field V09._args (fldOffset=0x18)" ; V17 tmp13 struct do-not-enreg[SR] multireg-ret "Return value temp for multi-reg return (rejected tail call)." In fgLocalVarLivenessInit Local V01 should not be enregistered because: it is a struct Local V02 should not be enregistered because: it is a struct Local V03 should not be enregistered because: it is a struct Local V17 should not be enregistered because: it is a struct Tracked variable (11 out of 18) table: V02 arg2 [struct]: refCnt = 6, refCntWtd = 6 V00 this [ byref]: refCnt = 4, refCntWtd = 4 V05 tmp1 [ ref]: refCnt = 3, refCntWtd = 6 V06 tmp2 [ ref]: refCnt = 3, refCntWtd = 6 V03 loc0 [struct]: refCnt = 4, refCntWtd = 4 V12 tmp8 [ ref]: refCnt = 2, refCntWtd = 4 V13 tmp9 [ ref]: refCnt = 2, refCntWtd = 2 V14 tmp10 [ ref]: refCnt = 2, refCntWtd = 2 V16 tmp12 [ ref]: refCnt = 2, refCntWtd = 2 V17 tmp13 [struct]: refCnt = 2, refCntWtd = 2 V15 tmp11 [ ref]: refCnt = 1, refCntWtd = 1 *************** In fgPerBlockLocalVarLiveness() BB01 USE(2)={V02 V00 } + ByrefExposed + GcHeap DEF(9)={ V05 V06 V03 V12 V13 V14 V16 V17 V15} + ByrefExposed* + GcHeap* ** Memory liveness computed, GcHeap states and ByrefExposed states match *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (2)={V02 V00} + ByrefExposed + GcHeap OUT(0)={ } Removing dead store: N003 ( 5, 4) [000087] DA---------- * STORE_LCL_VAR ref V15 tmp11 d:2 (last use) Removing dead node: N001 ( 1, 1) [000085] ------------ * CNS_INT ref null $VN.Null *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V05: refCnt = 1, refCntWtd = 2 New refCnts for V05: refCnt = 2, refCntWtd = 4 New refCnts for V02: refCnt = 1, refCntWtd = 1 New refCnts for V06: refCnt = 1, refCntWtd = 2 New refCnts for V06: refCnt = 2, refCntWtd = 4 New refCnts for V02: refCnt = 2, refCntWtd = 2 New refCnts for V05: refCnt = 3, refCntWtd = 6 New refCnts for V13: refCnt = 1, refCntWtd = 1 New refCnts for V06: refCnt = 3, refCntWtd = 6 New refCnts for V14: refCnt = 1, refCntWtd = 1 New refCnts for V16: refCnt = 1, refCntWtd = 1 New refCnts for V13: refCnt = 2, refCntWtd = 2 New refCnts for V14: refCnt = 2, refCntWtd = 2 New refCnts for V16: refCnt = 2, refCntWtd = 2 New refCnts for V12: refCnt = 1, refCntWtd = 2 New refCnts for V12: refCnt = 2, refCntWtd = 4 New refCnts for V03: refCnt = 1, refCntWtd = 1 New refCnts for V00: refCnt = 1, refCntWtd = 1 New refCnts for V03: refCnt = 2, refCntWtd = 2 New refCnts for V00: refCnt = 2, refCntWtd = 2 New refCnts for V03: refCnt = 3, refCntWtd = 3 New refCnts for V03: refCnt = 4, refCntWtd = 4 New refCnts for V02: refCnt = 3, refCntWtd = 3 New refCnts for V02: refCnt = 4, refCntWtd = 4 New refCnts for V17: refCnt = 1, refCntWtd = 1 New refCnts for V17: refCnt = 2, refCntWtd = 2 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 3, refCntWtd = 3 New refCnts for V00: refCnt = 4, refCntWtd = 4 New refCnts for V02: refCnt = 5, refCntWtd = 5 New refCnts for V02: refCnt = 6, refCntWtd = 6 *************** Finishing PHASE Lowering nodeinfo Trees after Lowering nodeinfo ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} [000129] ------------ IL_OFFSET void IL offset: 0x0 N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class $180 /--* t4 long [000137] ------------ t137 = * PUTARG_REG long REG rdi /--* t137 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 /--* t5 ref N005 ( 16, 16) [000007] DA---------- * STORE_LCL_VAR ref V05 tmp1 d:2 N001 ( 1, 1) [000008] ------------ t8 = LCL_VAR ref V05 tmp1 u:2 $200 /--* t8 ref N003 ( 2, 2) [000010] -c---------- t10 = * LEA(b+8) byref N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD int V02 arg2 u:1[+8] Fseq[Version] $2c0 /--* t10 byref +--* t3 int [000130] -A--GO------ * STOREIND int N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class $182 /--* t18 long [000138] ------------ t138 = * PUTARG_REG long REG rdi /--* t138 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 /--* t19 ref N005 ( 16, 16) [000021] DA---------- * STORE_LCL_VAR ref V06 tmp2 d:2 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V06 tmp2 u:2 $201 /--* t22 ref N003 ( 2, 2) [000024] -c---------- t24 = * LEA(b+8) byref N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD long V02 arg2 u:1[+0] Fseq[JobGroup] $300 /--* t24 byref +--* t17 long [000131] -A--GO------ * STOREIND long N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR ref V05 tmp1 u:2 (last use) $200 /--* t13 ref N004 ( 11, 8) [000077] DA---------- * STORE_LCL_VAR ref V13 tmp9 d:2 N001 ( 1, 1) [000027] ------------ t27 = LCL_VAR ref V06 tmp2 u:2 (last use) $201 /--* t27 ref N004 ( 11, 8) [000082] DA---------- * STORE_LCL_VAR ref V14 tmp10 d:2 N001 ( 2, 10) [000103] ------------ t103 = CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 /--* t103 long N002 ( 4, 12) [000090] n---G------- t90 = * IND ref /--* t90 ref N004 ( 8, 15) [000092] DA--G------- * STORE_LCL_VAR ref V16 tmp12 d:2 N003 ( 3, 2) [000109] ------------ t109 = LCL_VAR ref V13 tmp9 u:2 (last use) $200 N004 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V14 tmp10 u:2 (last use) $201 N005 ( 1, 1) [000128] ------------ t128 = CNS_INT ref null $VN.Null N006 ( 3, 2) [000112] ------------ t112 = LCL_VAR ref V16 tmp12 u:2 (last use) /--* t109 ref +--* t110 ref +--* t128 ref +--* t112 ref N007 ( 10, 7) [000108] -c---------- t108 = * FIELD_LIST struct $380 /--* t108 struct [000139] ------------ * PUTARG_STK [+0x00] void (4 slots) N008 ( 2, 10) [000104] ------------ t104 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] $185 /--* t104 long N009 ( 4, 12) [000105] n---G------- t105 = * IND ref /--* t105 RPCSystem: jobgroup=1936 version=0 ref [000140] ----G------- t140 = * PUTARG_REG ref REG rsi N010 ( 1, 1) [000060] ------------ t60 = CNS_INT ref null $VN.Null /--* t60 ref [000141] ------------ t141 = * PUTARG_REG ref REG rdi /--* t140 ref arg1 in rsi +--* t141 ref arg0 in rdi N011 ( 32, 27) [000068] --CXG------- t68 = * CALL ref System.String.FormatHelper $1ce /--* t68 ref N013 ( 32, 27) [000099] DA-XG------- * STORE_LCL_VAR ref V12 tmp8 d:2 N003 ( 1, 1) [000096] ------------ t96 = LCL_VAR ref V12 tmp8 u:2 (last use) $1ce /--* t96 ref [000142] ------------ t142 = * PUTARG_REG ref REG rsi N004 ( 1, 1) [000095] ------------ t95 = CNS_INT int 3 $44 /--* t95 int [000143] ------------ t143 = * PUTARG_REG int REG rdi /--* t142 ref arg1 in rsi +--* t143 int arg0 in rdi N005 ( 16, 9) [000097] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void [000132] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 1, 1) [000034] -c---------- t34 = CNS_INT int 0 $40 [000144] Dc-----N---- t144 = LCL_VAR_ADDR byref V03 loc0 /--* t144 byref +--* t34 int N003 ( 5, 4) [000035] sA---------- * STORE_BLK struct (init) (Unroll) [000133] ------------ IL_OFFSET void IL offset: 0x2d N001 ( 1, 1) [000038] ------------ t38 = LCL_VAR byref V00 this u:1 $80 /--* t38 byref N003 ( 3, 3) [000118] -c---------- t118 = * LEA(b+16) byref /--* t118 byref N004 ( 6, 5) [000039] *c-XG------- t39 = * IND struct N005 ( 3, 4) [000036] Uc-----N---- t36 = LCL_FLD_ADDR byref V03 loc0 ud:2->3[+40] Fseq[Baselib] /--* t36 byref +--* t39 struct N007 ( 9, 9) [000042] nA-XG------- * STORE_BLK struct (copy) (Unroll) [000134] ------------ IL_OFFSET void IL offset: 0x3a N001 ( 1, 1) [000046] ------------ t46 = LCL_VAR byref V00 this u:1 (last use) $80 /--* t46 byref N003 ( 3, 3) [000120] -c---------- t120 = * LEA(b+112) byref /--* t120 byref N004 ( 6, 5) [000047] *c--GO------ t47 = * IND struct N005 ( 3, 4) [000044] Uc-----N---- t44 = LCL_FLD_ADDR byref V03 loc0 ud:3->4[+0] Fseq[Tx] /--* t44 byref +--* t47 struct N007 ( 6, 7) [000050] nA--GO------ * STORE_BLK struct (copy) (Unroll) [000135] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000052] -c-----N---- t52 = LCL_VAR_ADDR byref V03 loc0 u:4 (last use) /--* t52 byref N003 ( 9, 7) [000058] nc---------- t58 = * OBJ struct $388 /--* t58 struct [000145] ------------ * PUTARG_STK [+0x00] void (12 slots) (RepInstr) N005 ( 3, 4) [000125] ------------ t125 = LCL_FLD long V02 arg2 u:1[+0] $142 /--* t125 long [000146] ------------ t146 = * PUTARG_REG long REG rdi N006 ( 3, 4) [000126] ------------ t126 = LCL_FLD long V02 arg2 u:1[+8] (last use) $143 /--* t126 long [000147] ------------ t147 = * PUTARG_REG long REG rsi /--* t146 long +--* t147 long N007 ( 6, 8) [000124] -c---------- t124 = * FIELD_LIST struct $38a /--* t124 struct arg1 rdi,rsi N008 ( 32, 21) [000054] --CXG------- t54 = * CALL struct Unity.Jobs.IJobExtensions.Schedule,NA $38b /--* t54 struct N010 ( 36, 24) [000122] DA-XG------- * STORE_LCL_VAR struct V17 tmp13 d:2 [000136] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000127] -c-----N---- t127 = LCL_VAR struct V17 tmp13 u:2 (last use) $38e /--* t127 struct N002 ( 4, 3) [000059] ----G------- * RETURN struct $38f ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Trees before Calculate stack level slots ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} [000129] ------------ IL_OFFSET void IL offset: 0x0 N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class $180 /--* t4 long [000137] ------------ t137 = * PUTARG_REG long REG rdi /--* t137 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 /--* t5 ref N005 ( 16, 16) [000007] DA---------- * STORE_LCL_VAR ref V05 tmp1 d:2 N001 ( 1, 1) [000008] ------------ t8 = LCL_VAR ref V05 tmp1 u:2 $200 /--* t8 ref N003 ( 2, 2) [000010] -c---------- t10 = * LEA(b+8) byref N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD int V02 arg2 u:1[+8] Fseq[Version] $2c0 /--* t10 byref +--* t3 int [000130] -A--GO------ * STOREIND int N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class $182 /--* t18 long [000138] ------------ t138 = * PUTARG_REG long REG rdi /--* t138 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 /--* t19 ref N005 ( 16, 16) [000021] DA---------- * STORE_LCL_VAR ref V06 tmp2 d:2 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V06 tmp2 u:2 $201 /--* t22 ref N003 ( 2, 2) [000024] -c---------- t24 = * LEA(b+8) byref N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD long V02 arg2 u:1[+0] Fseq[JobGroup] $300 /--* t24 byref +--* t17 long [000131] -A--GO------ * STOREIND long N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR ref V05 tmp1 u:2 (last use) $200 /--* t13 ref N004 ( 11, 8) [000077] DA---------- * STORE_LCL_VAR ref V13 tmp9 d:2 N001 ( 1, 1) [000027] ------------ t27 = LCL_VAR ref V06 tmp2 u:2 (last use) $201 /--* t27 ref N004 ( 11, 8) [000082] DA---------- * STORE_LCL_VAR ref V14 tmp10 d:2 N001 ( 2, 10) [000103] ------------ t103 = CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 /--* t103 long N002 ( 4, 12) [000090] n---G------- t90 = * IND ref /--* t90 ref N004 ( 8, 15) [000092] DA--G------- * STORE_LCL_VAR ref V16 tmp12 d:2 N003 ( 3, 2) [000109] ------------ t109 = LCL_VAR ref V13 tmp9 u:2 (last use) $200 N004 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V14 tmp10 u:2 (last use) $201 N005 ( 1, 1) [000128] ------------ t128 = CNS_INT ref null $VN.Null N006 ( 3, 2) [000112] ------------ t112 = LCL_VAR ref V16 tmp12 u:2 (last use) /--* t109 ref +--* t110 ref +--* t128 ref +--* t112 ref N007 ( 10, 7) [000108] -c---------- t108 = * FIELD_LIST struct $380 /--* t108 struct [000139] ------------ * PUTARG_STK [+0x00] void (4 slots) N008 ( 2, 10) [000104] ------------ t104 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] $185 /--* t104 long N009 ( 4, 12) [000105] n---G------- t105 = * IND ref /--* t105 ref [000140] ----G------- t140 = * PUTARG_REG ref REG rsi N010 ( 1, 1) [000060] ------------ t60 = CNS_INT ref null $VN.Null /--* t60 ref [000141] ------------ t141 = * PUTARG_REG ref REG rdi /--* t140 ref arg1 in rsi +--* t141 ref arg0 in rdi N011 ( 32, 27) [000068] --CXG------- t68 = * CALL ref System.String.FormatHelper $1ce /--* t68 ref N013 ( 32, 27) [000099] DA-XG------- * STORE_LCL_VAR ref V12 tmp8 d:2 N003 ( 1, 1) [000096] ------------ t96 = LCL_VAR ref V12 tmp8 u:2 (last use) $1ce /--* t96 ref [000142] ------------ t142 = * PUTARG_REG ref REG rsi N004 ( 1, 1) [000095] ------------ t95 = CNS_INT int 3 $44 /--* t95 int [000143] ------------ t143 = * PUTARG_REG int REG rdi /--* t142 ref arg1 in rsi +--* t143 int arg0 in rdi N005 ( 16, 9) [000097] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void [000132] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 1, 1) [000034] -c---------- t34 = CNS_INT int 0 $40 [000144] Dc-----N---- t144 = LCL_VAR_ADDR byref V03 loc0 /--* t144 byref +--* t34 int N003 ( 5, 4) [000035] sA---------- * STORE_BLK struct (init) (Unroll) [000133] ------------ IL_OFFSET void IL offset: 0x2d N001 ( 1, 1) [000038] ------------ t38 = LCL_VAR byref V00 this u:1 $80 /--* t38 byref N003 ( 3, 3) [000118] -c---------- t118 = * LEA(b+16) byref /--* t118 byref N004 ( 6, 5) [000039] *c-XG------- t39 = * IND struct N005 ( 3, 4) [000036] Uc-----N---- t36 = LCL_FLD_ADDR byref V03 loc0 ud:2->3[+40] Fseq[Baselib] /--* t36 byref +--* t39 struct N007 ( 9, 9) [000042] nA-XG------- * STORE_BLK struct (copy) (Unroll) [000134] ------------ IL_OFFSET void IL offset: 0x3a N001 ( 1, 1) [000046] ------------ t46 = LCL_VAR byref V00 this u:1 (last use) $80 /--* t46 byref N003 ( 3, 3) [000120] -c---------- t120 = * LEA(b+112) byref /--* t120 byref N004 ( 6, 5) [000047] *c--GO------ t47 = * IND struct N005 ( 3, 4) [000044] Uc-----N---- t44 = LCL_FLD_ADDR byref V03 loc0 ud:3->4[+0] Fseq[Tx] /--* t44 byref +--* t47 struct N007 ( 6, 7) [000050] nA--GO------ * STORE_BLK struct (copy) (Unroll) [000135] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000052] -c-----N---- t52 = LCL_VAR_ADDR byref V03 loc0 u:4 (last use) /--* t52 byref N003 ( 9, 7) [000058] nc---------- t58 = * OBJ struct $388 /--* t58 struct [000145] ------------ * PUTARG_STK [+0x00] void (12 slots) (RepInstr) N005 ( 3, 4) [000125] ------------ t125 = LCL_FLD long V02 arg2 u:1[+0] $142 /--* t125 long [000146] ------------ t146 = * PUTARG_REG long REG rdi N006 ( 3, 4) [000126] ------------ t126 = LCL_FLD long V02 arg2 u:1[+8] (last use) $143 /--* t126 long [000147] ------------ t147 = * PUTARG_REG long REG rsi /--* t146 long +--* t147 long N007 ( 6, 8) [000124] -c---------- t124 = * FIELD_LIST struct $38a /--* t124 struct arg1 rdi,rsi N008 ( 32, 21) [000054] --CXG------- t54 = * CALL struct Unity.Jobs.IJobExtensions.Schedule,NA $38b /--* t54 struct N010 ( 36, 24) [000122] DA-XG------- * STORE_LCL_VAR struct V17 tmp13 d:2 [000136] ------------ IL_OFFSET void IL offset: 0x47 N001 ( 3, 2) [000127] -c-----N---- t127 = LCL_VAR struct V17 tmp13 u:2 (last use) $38e /--* t127 struct N002 ( 4, 3) [000059] ----G------- * RETURN struct $38f ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Calculate stack level slots Too many pushed arguments for an ESP based encoding, forcing an EBP frame *************** Finishing PHASE Calculate stack level slots [no changes] *************** Starting PHASE Linear scan register alloc Clearing modified regs. buildIntervals ======== ----------------- LIVENESS: ----------------- BB01 use def in out {V00 V02} {V03 V05 V06 V12 V13 V14 V15 V16 V17} {V00 V02} {} Interval 0: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 0: (V00) byref RefPositions {} physReg:NA Preferences=[allInt] Local V02 should not be enregistered because: it is a struct Local V03 should not be enregistered because: it is a struct Interval 1: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 1: (V05) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 2: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 2: (V06) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 3: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 3: (V12) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 4: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 4: (V13) ref (field) RefPositions {} physReg:NA Preferences=[allInt] Interval 5: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 5: (V14) ref (field) RefPositions {} physReg:NA Preferences=[allInt] Interval 6: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 6: (V16) ref (field) RefPositions {} physReg:NA Preferences=[allInt] Local V17 should not be enregistered because: it is a struct FP callee save candidate vars: None floatVarCount = 0; hasLoops = 0, singleExit = 1 TUPLE STYLE DUMP BEFORE LSRA LSRA Block Sequence: BB01( 1 ) BB01 [000..04F) (return), preds={} succs={} ===== N000. IL_OFFSET IL offset: 0x0 N002. t4 = CNS_INT(h) 0x7f6678beb1c0 class N000. t137 = PUTARG_REG; t4 N003. t5 = CALL help; t137 N005. V05(t7); t5 N001. V05(t8) N003. t10 = LEA(b+8) ; t8 N005. t3 = V02 MEM N000. STOREIND ; t10,t3 N002. t18 = CNS_INT(h) 0x7f6678c127f0 class N000. t138 = PUTARG_REG; t18 N003. t19 = CALL help; t138 N005. V06(t21); t19 N001. V06(t22) N003. t24 = LEA(b+8) ; t22 N005. t17 = V02 MEM N000. STOREIND ; t24,t17 N001. V05(t13*) N004. V13(t77); t13* N001. V06(t27*) N004. V14(t82); t27* N001. t103 = CNS_INT(h) 0x7f6663fff340 static Fseq[s_twoArgArray] N002. t90 = IND ; t103 N004. V16(t92); t90 N003. V13(t109*) N004. V14(t110*) N005. t128 = CNS_INT null N006. V16(t112*) N007. t108 = FIELD_LIST; t109*,t110*,t128,t112* N000. PUTARG_STK [+0x00]; t108 N008. t104 = CNS_INT(h) 0x640084D0 [ICON_STR_HDL] N009. t105 = IND ; t104 N000. t140 = PUTARG_REG; t105 N010. t60 = CNS_INT null N000. t141 = PUTARG_REG; t60 N011. t68 = CALL ; t140,t141 N013. V12(t99); t68 N003. V12(t96*) N000. t142 = PUTARG_REG; t96* N004. t95 = CNS_INT 3 N000. t143 = PUTARG_REG; t95 N005. CALL ; t142,t143 N000. IL_OFFSET IL offset: 0x25 N001. CNS_INT 0 N000. LCL_VAR_ADDR V03 loc0 N003. STORE_BLK N000. IL_OFFSET IL offset: 0x2d N001. V00(t38) N003. t118 = LEA(b+16); t38 N004. t39 = IND ; t118 N005. LCL_FLD_ADDR V03 loc0 ud:2->3[+40] Fseq[Baselib] N007. STORE_BLK; t39 N000. IL_OFFSET IL offset: 0x3a N001. V00(t46*) N003. t120 = LEA(b+112); t46* N004. t47 = IND ; t120 N005. LCL_FLD_ADDR V03 loc0 ud:3->4[+0] Fseq[Tx] N007. STORE_BLK; t47 N000. IL_OFFSET IL offset: 0x47 N001. LCL_VAR_ADDR V03 loc0 u:4 (last use) N003. OBJ N000. PUTARG_STK [+0x00] N005. t125 = V02 MEM N000. t146 = PUTARG_REG; t125 N006. t126 = V02 MEM N000. t147 = PUTARG_REG; t126 N007. t124 = FIELD_LIST; t146,t147 N008. t54 = CALL ; t124 N010. V17 MEM; t54 N000. IL_OFFSET IL offset: 0x47 N001. V17 MEM N002. RETURN buildIntervals second part ======== Int arg V00 in reg rdi BB00 regmask=[rdi] minReg=1 fixed> NEW BLOCK BB01 DefList: { } N003 (???,???) [000129] ------------ * IL_OFFSET void IL offset: 0x0 REG NA DefList: { } N005 ( 2, 10) [000004] ------------ * CNS_INT(h) long 0x7f6678beb1c0 class REG NA $180 Interval 7: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N005.t4. CNS_INT } N007 (???,???) [000137] ------------ * PUTARG_REG long REG rdi BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> Interval 8: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> DefList: { N007.t137. PUTARG_REG } N009 ( 16, 16) [000005] --C--------- * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG NA $200 BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> Interval 9: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> DefList: { N009.t5. CALL } N011 ( 16, 16) [000007] DA---------- * STORE_LCL_VAR ref V05 tmp1 d:2 NA REG NA BB01 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N013 ( 1, 1) [000008] ------------ * LCL_VAR ref V05 tmp1 u:2 NA REG NA $200 DefList: { } N015 ( 2, 2) [000010] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N017 ( 3, 4) [000003] ------------ * LCL_FLD int V02 arg2 u:1[+8] Fseq[Version] NA REG NA $2c0 Interval 10: int RefPositions {} physReg:NA Preferences=[allInt] LCL_FLD BB01 regmask=[allInt] minReg=1> DefList: { N017.t3. LCL_FLD } N019 (???,???) [000130] -A--GO------ * STOREIND int REG NA LCL_VAR BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> DefList: { } N021 ( 2, 10) [000018] ------------ * CNS_INT(h) long 0x7f6678c127f0 class REG NA $182 Interval 11: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N021.t18. CNS_INT } N023 (???,???) [000138] ------------ * PUTARG_REG long REG rdi BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> Interval 12: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> DefList: { N023.t138. PUTARG_REG } N025 ( 16, 16) [000019] --C--------- * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG NA $201 BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> Interval 13: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> DefList: { N025.t19. CALL } N027 ( 16, 16) [000021] DA---------- * STORE_LCL_VAR ref V06 tmp2 d:2 NA REG NA BB01 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N029 ( 1, 1) [000022] ------------ * LCL_VAR ref V06 tmp2 u:2 NA REG NA $201 DefList: { } N031 ( 2, 2) [000024] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N033 ( 3, 4) [000017] ------------ * LCL_FLD long V02 arg2 u:1[+0] Fseq[JobGroup] NA REG NA $300 Interval 14: long RefPositions {} physReg:NA Preferences=[allInt] LCL_FLD BB01 regmask=[allInt] minReg=1> DefList: { N033.t17. LCL_FLD } N035 (???,???) [000131] -A--GO------ * STOREIND long REG NA LCL_VAR BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> DefList: { } N037 ( 1, 1) [000013] ------------ * LCL_VAR ref V05 tmp1 u:2 NA (last use) REG NA $200 DefList: { } N039 ( 11, 8) [000077] DA---------- * STORE_LCL_VAR ref V13 tmp9 d:2 NA REG NA LCL_VAR BB01 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N041 ( 1, 1) [000027] ------------ * LCL_VAR ref V06 tmp2 u:2 NA (last use) REG NA $201 DefList: { } N043 ( 11, 8) [000082] DA---------- * STORE_LCL_VAR ref V14 tmp10 d:2 NA REG NA LCL_VAR BB01 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N045 ( 2, 10) [000103] ------------ * CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] REG NA $184 Interval 15: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N045.t103. CNS_INT } N047 ( 4, 12) [000090] n---G------- * IND ref REG NA BB01 regmask=[allInt] minReg=1 last> Interval 16: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB01 regmask=[allInt] minReg=1> DefList: { N047.t90. IND } N049 ( 8, 15) [000092] DA--G------- * STORE_LCL_VAR ref V16 tmp12 d:2 NA REG NA BB01 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N051 ( 3, 2) [000109] ------------ * LCL_VAR ref V13 tmp9 u:2 NA (last use) REG NA $200 DefList: { } N053 ( 3, 2) [000110] ------------ * LCL_VAR ref V14 tmp10 u:2 NA (last use) REG NA $201 DefList: { } N055 ( 1, 1) [000128] ------------ * CNS_INT ref null REG NA $VN.Null Interval 17: ref RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N055.t128. CNS_INT } N057 ( 3, 2) [000112] ------------ * LCL_VAR ref V16 tmp12 u:2 NA (last use) REG NA DefList: { N055.t128. CNS_INT } N059 ( 10, 7) [000108] -c---------- * FIELD_LIST struct REG NA $380 Contained DefList: { N055.t128. CNS_INT } N061 (???,???) [000139] ------------ * PUTARG_STK [+0x00] void (4 slots) REG NA LCL_VAR BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N063 ( 2, 10) [000104] ------------ * CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] REG NA $185 Interval 18: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N063.t104. CNS_INT } N065 ( 4, 12) [000105] n---G------- * IND ref REG NA BB01 regmask=[allInt] minReg=1 last> Interval 19: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB01 regmask=[allInt] minReg=1> DefList: { N065.t105. IND } N067 (???,???) [000140]ScheduleFlushSend: jobgroup=1936 version=0 ----G------- * PUTARG_REG ref REG rsi BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> Interval 20: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> DefList: { N067.t140. PUTARG_REG } N069 ( 1, 1) [000060] ------------ * CNS_INT ref null REG NA $VN.Null Interval 21: ref RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N067.t140. PUTARG_REG; N069.t60. CNS_INT } N071 (???,???) [000141] ------------ * PUTARG_REG ref REG rdi BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> Interval 22: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> DefList: { N067.t140. PUTARG_REG; N071.t141. PUTARG_REG } N073 ( 32, 27) [000068] --CXG------- * CALL ref System.String.FormatHelper REG NA $1ce BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> Interval 23: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> DefList: { N073.t68. CALL } N075 ( 32, 27) [000099] DA-XG------- * STORE_LCL_VAR ref V12 tmp8 d:2 NA REG NA BB01 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N077 ( 1, 1) [000096] ------------ * LCL_VAR ref V12 tmp8 u:2 NA (last use) REG NA $1ce DefList: { } N079 (???,???) [000142] ------------ * PUTARG_REG ref REG rsi BB01 regmask=[rsi] minReg=1> LCL_VAR BB01 regmask=[rsi] minReg=1 last fixed> Interval 24: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> DefList: { N079.t142. PUTARG_REG } N081 ( 1, 1) [000095] ------------ * CNS_INT int 3 REG NA $44 Interval 25: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N079.t142. PUTARG_REG; N081.t95. CNS_INT } N083 (???,???) [000143] ------------ * PUTARG_REG int REG rdi BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> Interval 26: int RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> DefList: { N079.t142. PUTARG_REG; N083.t143. PUTARG_REG } N085 ( 16, 9) [000097] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal REG NA $VN.Void BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> DefList: { } N087 (???,???) [000132] ------------ * IL_OFFSET void IL offset: 0x25 REG NA DefList: { } N089 ( 1, 1) [000034] -c---------- * CNS_INT int 0 REG NA $40 Contained DefList: { } N091 (???,???) [000144] Dc-----N---- * LCL_VAR_ADDR byref V03 loc0 NA REG NA Contained DefList: { } N093 ( 5, 4) [000035] sA---------- * STORE_BLK struct (init) (Unroll) REG NA Interval 27: float RefPositions {} physReg:NA Preferences=[allFloat] STORE_BLK BB01 regmask=[allFloat] minReg=1> STORE_BLK BB01 regmask=[allFloat] minReg=1 last> DefList: { } N095 (???,???) [000133] ------------ * IL_OFFSET void IL offset: 0x2d REG NA DefList: { } N097 ( 1, 1) [000038] ------------ * LCL_VAR byref V00 this u:1 NA REG NA $80 DefList: { } N099 ( 3, 3) [000118] -c---------- * LEA(b+16) byref REG NA Contained DefList: { } N101 ( 6, 5) [000039] *c-XG------- * IND struct REG NA Contained DefList: { } N103 ( 3, 4) [000036] Uc-----N---- * LCL_FLD_ADDR byref V03 loc0 ud:2->3[+40] Fseq[Baselib] NA REG NA Contained DefList: { } N105 ( 9, 9) [000042] nA-XG------- * STORE_BLK struct (copy) (Unroll) REG NA Interval 28: int RefPositions {} physReg:NA Preferences=[allInt] STORE_BLK BB01 regmask=[allInt] minReg=1> Interval 29: float RefPositions {} physReg:NA Preferences=[allFloat] STORE_BLK BB01 regmask=[allFloat] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> STORE_BLK BB01 regmask=[allInt] minReg=1 last> STORE_BLK BB01 regmask=[allFloat] minReg=1 last> DefList: { } N107 (???,???) [000134] ------------ * IL_OFFSET void IL offset: 0x3a REG NA DefList: { } N109 ( 1, 1) [000046] ------------ * LCL_VAR byref V00 this u:1 NA (last use) REG NA $80 DefList: { } N111 ( 3, 3) [000120] -c---------- * LEA(b+112) byref REG NA Contained DefList: { } N113 ( 6, 5) [000047] *c--GO------ * IND struct REG NA Contained DefList: { } N115 ( 3, 4) [000044] Uc-----N---- * LCL_FLD_ADDR byref V03 loc0 ud:3->4[+0] Fseq[Tx] NA REG NA Contained DefList: { } N117 ( 6, 7) [000050] nA--GO------ * STORE_BLK struct (copy) (Unroll) REG NA Interval 30: int RefPositions {} physReg:NA Preferences=[allInt] STORE_BLK BB01 regmask=[allInt] minReg=1> Interval 31: float RefPositions {} physReg:NA Preferences=[allFloat] STORE_BLK BB01 regmask=[allFloat] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> STORE_BLK BB01 regmask=[allInt] minReg=1 last> STORE_BLK BB01 regmask=[allFloat] minReg=1 last> DefList: { } N119 (???,???) [000135] ------------ * IL_OFFSET void IL offset: 0x47 REG NA DefList: { } N121 ( 3, 2) [000052] -c-----N---- * LCL_VAR_ADDR byref V03 loc0 u:4 NA (last use) REG NA Contained DefList: { } N123 ( 9, 7) [000058] nc---------- * OBJ struct REG NA $388 Contained DefList: { } N125 (???,???) [000145] ------------ * PUTARG_STK [+0x00] void (12 slots) (RepInstr) REG NA Interval 32: int RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_STK BB01 regmask=[rdi] minReg=1 fixed> Interval 33: int RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rcx] minReg=1> PUTARG_STK BB01 regmask=[rcx] minReg=1 fixed> Interval 34: int RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rsi] minReg=1> PUTARG_STK BB01 regmask=[rsi] minReg=1 fixed> PUTARG_STK BB01 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rsi] minReg=1 last fixed> DefList: { } N127 ( 3, 4) [000125] ------------ * LCL_FLD long V02 arg2 u:1[+0] NA REG NA $142 Interval 35: long RefPositions {} physReg:NA Preferences=[allInt] LCL_FLD BB01 regmask=[allInt] minReg=1> DefList: { N127.t125. LCL_FLD } N129 (???,???) [000146] ------------ * PUTARG_REG long REG rdi BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> Interval 36: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> DefList: { N129.t146. PUTARG_REG } N131 ( 3, 4) [000126] ------------ * LCL_FLD long V02 arg2 u:1[+8] NA (last use) REG NA $143 Interval 37: long RefPositions {} physReg:NA Preferences=[allInt] LCL_FLD BB01 regmask=[allInt] minReg=1> DefList: { N129.t146. PUTARG_REG; N131.t126. LCL_FLD } N133 (???,???) [000147] ------------ * PUTARG_REG long REG rsi BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> Interval 38: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> DefList: { N129.t146. PUTARG_REG; N133.t147. PUTARG_REG } N135 ( 6, 8) [000124] -c---------- * FIELD_LIST struct REG NA $38a Contained DefList: { N129.t146. PUTARG_REG; N133.t147. PUTARG_REG } N137 ( 32, 21) [000054] --CXG------- * CALL struct Unity.Jobs.IJobExtensions.Schedule REG NA,NA $38b BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> Interval 39: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rax] minReg=1> CALL[0] BB01 regmask=[rax] minReg=1 fixed> Interval 40: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdx] minReg=1> CALL[1] BB01 regmask=[rdx] minReg=1 fixed> DefList: { N137.t54. CALL; N137.t54. CALL } N139 ( 36, 24) [000122] DA-XG------- * STORE_LCL_VAR struct V17 tmp13 d:2 NA REG NA BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> DefList: { } N141 (???,???) [000136] ------------ * IL_OFFSET void IL offset: 0x47 REG NA DefList: { } N143 ( 3, 2) [000127] -c-----N---- * LCL_VAR struct V17 tmp13 u:2 NA (last use) REG NA $38e Contained DefList: { } N145 ( 4, 3) [000059] ----G------- * RETURN struct REG NA $38f CHECKING LAST USES for BB01, liveout={} ============================== use: {V00 V02} def: {V03 V05 V06 V12 V13 V14 V15 V16 V17} Linear scan intervals BEFORE VALIDATING INTERVALS: Interval 0: (V00) byref RefPositions {#0@0 #117@105 #122@117} physReg:rdi Preferences=[rbx r12-r15] Interval 1: (V05) ref RefPositions {#21@12 #23@19 #48@39} physReg:NA Preferences=[rbx r12-r15] RelatedInterval Interval 2: (V06) ref RefPositions {#44@28 #46@35 #50@43} physReg:NA Preferences=[allInt] RelatedInterval Interval 3: (V12) ref RefPositions {#90@76 #92@79} physReg:NA Preferences=[rsi] Interval 4: (V13) ref (field) RefPositions {#49@40 #58@61} physReg:NA Preferences=[allInt] Interval 5: (V14) ref (field) RefPositions {#51@44 #59@61} physReg:NA Preferences=[allInt] Interval 6: (V16) ref (field) RefPositions {#56@50 #61@61} physReg:NA Preferences=[allInt] Interval 7: long (constant) RefPositions {#2@6 #4@7} physReg:NA Preferences=[rdi] Interval 8: long RefPositions {#6@8 #8@9} physReg:NA Preferences=[rdi] Interval 9: ref RefPositions {#19@10 #20@11} physReg:NA Preferences=[rax] RelatedInterval Interval 10: int RefPositions {#22@18 #24@19} physReg:NA Preferences=[allInt] Interval 11: long (constant) RefPositions {#25@22 #27@23} physReg:NA Preferences=[rdi] Interval 12: long RefPositions {#29@24 #31@25} physReg:NA Preferences=[rdi] Interval 13: ref RefPositions {#42@26 #43@27} physReg:NA Preferences=[rax] RelatedInterval Interval 14: long RefPositions {#45@34 #47@35} physReg:NA Preferences=[allInt] Interval 15: long (constant) RefPositions {#52@46 #53@47} physReg:NA Preferences=[allInt] Interval 16: ref RefPositions {#54@48 #55@49} physReg:NA Preferences=[allInt] RelatedInterval Interval 17: ref (constant) RefPositions {#57@56 #60@61} physReg:NA Preferences=[allInt] Interval 18: long (constant) RefPositions {#62@64 #63@65} physReg:NA Preferences=[allInt] Interval 19: ref RefPositions {#64@66 #66@67} physReg:NA Preferences=[rsi] Interval 20: ref RefPositions {#68@68 #75@73} physReg:NA Preferences=[rsi] Interval 21: ref (constant) RefPositions {#69@70 #71@71} physReg:NA Preferences=[rdi] Interval 22: ref RefPositions {#73@72 #77@73} physReg:NA Preferences=[rdi] Interval 23: ref RefPositions {#88@74 #89@75} physReg:NA Preferences=[rax] RelatedInterval Interval 24: ref RefPositions {#94@80 #101@85} physReg:NA Preferences=[rsi] Interval 25: int (constant) RefPositions {#95@82 #97@83} physReg:NA Preferences=[rdi] Interval 26: int RefPositions {#99@84 #103@85} physReg:NA Preferences=[rdi] Interval 27: float (INTERNAL) RefPositions {#113@93 #114@93} physReg:NA Preferences=[allFloat] Interval 28: int (INTERNAL) RefPositions {#115@105 #118@105} physReg:NA Preferences=[allInt] Interval 29: float (INTERNAL) RefPositions {#116@105 #119@105} physReg:NA Preferences=[allFloat] Interval 30: int (INTERNAL) RefPositions {#120@117 #123@117} physReg:NA Preferences=[allInt] Interval 31: float (INTERNAL) RefPositions {#121@117 #124@117} physReg:NA Preferences=[allFloat] Interval 32: int (INTERNAL) RefPositions {#126@125 #131@125} physReg:NA Preferences=[rdi] Interval 33: int (INTERNAL) RefPositions {#128@125 #132@125} physReg:NA Preferences=[rcx] Interval 34: int (INTERNAL) RefPositions {#130@125 #133@125} physReg:NA Preferences=[rsi] Interval 35: long RefPositions {#134@128 #136@129} physReg:NA Preferences=[rdi] Interval 36: long RefPositions {#138@130 #145@137} physReg:NA Preferences=[rdi] Interval 37: long RefPositions {#139@132 #141@133} physReg:NA Preferences=[rsi] Interval 38: long RefPositions {#143@134 #147@137} physReg:NA Preferences=[rsi] Interval 39: long RefPositions {#158@138 #161@139} physReg:NA Preferences=[rax] Interval 40: long RefPositions {#160@138 #162@139} physReg:NA Preferences=[rdx] ------------ REFPOSITIONS BEFORE VALIDATING INTERVALS: ------------ BB00 regmask=[rdi] minReg=1 fixed regOptional> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_FLD BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_FLD BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> IND BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> CNS_INT BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1 last> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> IND BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> BB01 regmask=[rsi] minReg=1> LCL_VAR BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> STORE_BLK BB01 regmask=[allFloat] minReg=1> STORE_BLK BB01 regmask=[allFloat] minReg=1 last> STORE_BLK BB01 regmask=[allInt] minReg=1> STORE_BLK BB01 regmask=[allFloat] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> STORE_BLK BB01 regmask=[allInt] minReg=1 last> STORE_BLK BB01 regmask=[allFloat] minReg=1 last> STORE_BLK BB01 regmask=[allInt] minReg=1> STORE_BLK BB01 regmask=[allFloat] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> STORE_BLK BB01 regmask=[allInt] minReg=1 last> STORE_BLK BB01 regmask=[allFloat] minReg=1 last> BB01 regmask=[rdi] minReg=1> PUTARG_STK BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rcx] minReg=1> PUTARG_STK BB01 regmask=[rcx] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> PUTARG_STK BB01 regmask=[rsi] minReg=1 fixed> PUTARG_STK BB01 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rsi] minReg=1 last fixed> LCL_FLD BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> LCL_FLD BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL[0] BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rdx] minReg=1> CALL[1] BB01 regmask=[rdx] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> ----------------- BB00 regmask=[rdi] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[rsi] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> TUPLE STYLE DUMP WITH REF POSITIONS Incoming Parameters: V00 BB01 [000..04F) (return), preds={} succs={} ===== N003. IL_OFFSET IL offset: 0x0 N005. CNS_INT(h) 0x7f6678beb1c0 class Def:(#2) N007. PUTARG_REG Use:(#4) Fixed:rdi(#3) * Def:(#6) rdi N009. CALL help Use:(#8) Fixed:rdi(#7) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#19) rax Pref: N011. V05(L1) Use:(#20) * Def:(#21) Pref: N013. V05(L1) N015. LEA(b+8) N017. V02 MEM Def:(#22) N019. STOREIND Use:(#23) Use:(#24) * N021. CNS_INT(h) 0x7f6678c127f0 class Def:(#25) N023. PUTARG_REG Use:(#27) Fixed:rdi(#26) * Def:(#29) rdi N025. CALL help Use:(#31) Fixed:rdi(#30) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#42) rax Pref: N027. V06(L2) Use:(#43) * Def:(#44) Pref: N029. V06(L2) N031. LEA(b+8) N033. V02 MEM Def:(#45) N035. STOREIND Use:(#46) Use:(#47) * N037. V05(L1) N039. V13(L4) Use:(#48) * Def:(#49) N041. V06(L2) N043. V14(L5) Use:(#50) * Def:(#51) N045. CNS_INT(h) 0x7f6663fff340 static Fseq[s_twoArgArray] Def:(#52) N047. IND Use:(#53) * Def:(#54) Pref: N049. V16(L6) Use:(#55) * Def:(#56) N051. V13(L4) N053. V14(L5) N055. CNS_INT null Def:(#57) N057. V16(L6) N059. FIELD_LIST N061. PUTARG_STK [+0x00] Use:(#58) * Use:(#59) * Use:(#60) * Use:(#61) * N063. CNS_INT(h) 0x640084D0 [ICON_STR_HDL] Def:(#62) N065. IND Use:(#63) * Def:(#64) N067. PUTARG_REG Use:(#66) Fixed:rsi(#65) * Def:(#68) rsi N069. CNS_INT null Def:(#69) N071. PUTARG_REG Use:(#71) Fixed:rdi(#70) * Def:(#73) rdi N073. CALL Use:(#75) Fixed:rsi(#74) * Use:(#77) Fixed:rdi(#76) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#88) rax Pref: N075. V12(L3) Use:(#89) * Def:(#90) N077. V12(L3) N079. PUTARG_REG Use:(#92) Fixed:rsi(#91) * Def:(#94) rsi N081. CNS_INT 3 Def:(#95) N083. PUTARG_REG Use:(#97) Fixed:rdi(#96) * Def:(#99) rdi N085. CALL Use:(#101) Fixed:rsi(#100) * Use:(#103) Fixed:rdi(#102) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 N087. IL_OFFSET IL offset: 0x25 N089. CNS_INT 0 N091. LCL_VAR_ADDR V03 loc0 NA N093. STORE_BLK Def:(#113) Use:(#114) * N095. IL_OFFSET IL offset: 0x2d N097. V00(L0) N099. LEA(b+16) N101. IND N103. LCL_FLD_ADDR V03 loc0 ud:2->3[+40] Fseq[Baselib] NA N105. STORE_BLK Def:(#115) Def:(#116) Use:(#117) Use:(#118) * Use:(#119) * N107. IL_OFFSET IL offset: 0x3a N109. V00(L0) N111. LEA(b+112) N113. IND N115. LCL_FLD_ADDR V03 loc0 ud:3->4[+0] Fseq[Tx] NA N117. STORE_BLK Def:(#120) Def:(#121) Use:(#122) * Use:(#123) * Use:(#124) * N119. IL_OFFSET IL offset: 0x47 N121. LCL_VAR_ADDR V03 loc0 u:4 NA (last use) N123. OBJ N125. PUTARG_STK [+0x00] Def:(#126) rdi Def:(#128) rcx Def:(#130) rsi Use:(#131) * Use:(#132) * Use:(#133) * N127. V02 MEM Def:(#134) N129. PUTARG_REG Use:(#136) Fixed:rdi(#135) * Def:(#138) rdi N131. V02 MEM Def:(#139) N133. PUTARG_REG Use:(#141) Fixed:rsi(#140) * Def:(#143) rsi N135. FIELD_LIST N137. CALL Use:(#145) Fixed:rdi(#144) * Use:(#147) Fixed:rsi(#146) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#158) rax Def:(#160) rdx N139. V17 MEM Use:(#161) * Use:(#162) * N141. IL_OFFSET IL offset: 0x47 N143. V17 MEM N145. RETURN Linear scan intervals after buildIntervals: Interval 0: (V00) byref RefPositions {#0@0 #117@105 #122@117} physReg:rdi Preferences=[rbx r12-r15] Interval 1: (V05) ref RefPositions {#21@12 #23@19 ScheduleSend: version=0 jobgroup=1936 #48@39} physReg:NA Preferences=[rbx r12-r15] RelatedInterval Interval 2: (V06) ref RefPositions {#44@28 #46@35 #50@43} physReg:NA Preferences=[allInt] RelatedInterval Interval 3: (V12) ref RefPositions {#90@76 #92@79} physReg:NA Preferences=[rsi] Interval 4: (V13) ref (field) RefPositions {#49@40 #58@61} physReg:NA Preferences=[allInt] Interval 5: (V14) ref (field) RefPositions {#51@44 #59@61} physReg:NA Preferences=[allInt] Interval 6: (V16) ref (field) RefPositions {#56@50 #61@61} physReg:NA Preferences=[allInt] Interval 7: long (constant) RefPositions {#2@6 #4@7} physReg:NA Preferences=[rdi] Interval 8: long RefPositions {#6@8 #8@9} physReg:NA Preferences=[rdi] Interval 9: ref RefPositions {#19@10 #20@11} physReg:NA Preferences=[rax] RelatedInterval Interval 10: int RefPositions {#22@18 #24@19} physReg:NA Preferences=[allInt] Interval 11: long (constant) RefPositions {#25@22 #27@23} physReg:NA Preferences=[rdi] Interval 12: long RefPositions {#29@24 #31@25} physReg:NA Preferences=[rdi] Interval 13: ref RefPositions {#42@26 #43@27} physReg:NA Preferences=[rax] RelatedInterval Interval 14: long RefPositions {#45@34 #47@35} physReg:NA Preferences=[allInt] Interval 15: long (constant) RefPositions {#52@46 #53@47} physReg:NA Preferences=[allInt] Interval 16: ref RefPositions {#54@48 #55@49} physReg:NA Preferences=[allInt] RelatedInterval Interval 17: ref (constant) RefPositions {#57@56 #60@61} physReg:NA Preferences=[allInt] Interval 18: long (constant) RefPositions {#62@64 #63@65} physReg:NA Preferences=[allInt] Interval 19: ref RefPositions {#64@66 #66@67} physReg:NA Preferences=[rsi] Interval 20: ref RefPositions {#68@68 #75@73} physReg:NA Preferences=[rsi] Interval 21: ref (constant) RefPositions {#69@70 #71@71} physReg:NA Preferences=[rdi] Interval 22: ref RefPositions {#73@72 #77@73} physReg:NA Preferences=[rdi] Interval 23: ref RefPositions {#88@74 #89@75} physReg:NA Preferences=[rax] RelatedInterval Interval 24: ref RefPositions {#94@80 #101@85} physReg:NA Preferences=[rsi] Interval 25: int (constant) RefPositions {#95@82 #97@83} physReg:NA Preferences=[rdi] Interval 26: int RefPositions {#99@84 #103@85} physReg:NA Preferences=[rdi] Interval 27: float (INTERNAL) RefPositions {#113@93 #114@93} physReg:NA Preferences=[allFloat] Interval 28: int (INTERNAL) RefPositions {#115@105 #118@105} physReg:NA Preferences=[allInt] Interval 29: float (INTERNAL) RefPositions {#116@105 #119@105} physReg:NA Preferences=[allFloat] Interval 30: int (INTERNAL) RefPositions {#120@117 #123@117} physReg:NA Preferences=[allInt] Interval 31: float (INTERNAL) RefPositions {#121@117 #124@117} physReg:NA Preferences=[allFloat] Interval 32: int (INTERNAL) RefPositions {#126@125 #131@125} physReg:NA Preferences=[rdi] Interval 33: int (INTERNAL) RefPositions {#128@125 #132@125} physReg:NA Preferences=[rcx] Interval 34: int (INTERNAL) RefPositions {#130@125 #133@125} physReg:NA Preferences=[rsi] Interval 35: long RefPositions {#134@128 #136@129} physReg:NA Preferences=[rdi] Interval 36: long RefPositions {#138@130 #145@137} physReg:NA Preferences=[rdi] Interval 37: long RefPositions {#139@132 #141@133} physReg:NA Preferences=[rsi] Interval 38: long RefPositions {#143@134 #147@137} physReg:NA Preferences=[rsi] Interval 39: long RefPositions {#158@138 #161@139} physReg:NA Preferences=[rax] Interval 40: long RefPositions {#160@138 #162@139} physReg:NA Preferences=[rdx] *************** In LinearScan::allocateRegisters() Linear scan intervals before allocateRegisters: Interval 0: (V00) byref RefPositions {#0@0 #117@105 #122@117} physReg:rdi Preferences=[rbx r12-r15] Interval 1: (V05) ref RefPositions {#21@12 #23@19 #48@39} physReg:NA Preferences=[rbx r12-r15] RelatedInterval Interval 2: (V06) ref RefPositions {#44@28 #46@35 #50@43} physReg:NA Preferences=[allInt] RelatedInterval Interval 3: (V12) ref RefPositions {#90@76 #92@79} physReg:NA Preferences=[rsi] Interval 4: (V13) ref (field) RefPositions {#49@40 #58@61} physReg:NA Preferences=[allInt] Interval 5: (V14) ref (field) RefPositions {#51@44 #59@61} physReg:NA Preferences=[allInt] Interval 6: (V16) ref (field) RefPositions {#56@50 #61@61} physReg:NA Preferences=[allInt] Interval 7: long (constant) RefPositions {#2@6 #4@7} physReg:NA Preferences=[rdi] Interval 8: long RefPositions {#6@8 #8@9} physReg:NA Preferences=[rdi] Interval 9: ref RefPositions {#19@10 #20@11} physReg:NA Preferences=[rax] RelatedInterval Interval 10: int RefPositions {#22@18 #24@19} physReg:NA Preferences=[allInt] Interval 11: long (constant) RefPositions {#25@22 #27@23} physReg:NA Preferences=[rdi] Interval 12: long RefPositions {#29@24 #31@25} physReg:NA Preferences=[rdi] Interval 13: ref RefPositions {#42@26 #43@27} physReg:NA Preferences=[rax] RelatedInterval Interval 14: long RefPositions {#45@34 #47@35} physReg:NA Preferences=[allInt] Interval 15: long (constant) RefPositions {#52@46 #53@47} physReg:NA Preferences=[allInt] Interval 16: ref RefPositions {#54@48 #55@49} physReg:NA Preferences=[allInt] RelatedInterval Interval 17: ref (constant) RefPositions {#57@56 #60@61} physReg:NA Preferences=[allInt] Interval 18: long (constant) RefPositions {#62@64 #63@65} physReg:NA Preferences=[allInt] Interval 19: ref RefPositions {#64@66 #66@67} physReg:NA Preferences=[rsi] Interval 20: ref RefPositions {#68@68 #75@73} physReg:NA Preferences=[rsi] Interval 21: ref (constant) RefPositions {#69@70 #71@71} physReg:NA Preferences=[rdi] Interval 22: ref RefPositions {#73@72 #77@73} physReg:NA Preferences=[rdi] Interval 23: ref RefPositions {#88@74 #89@75} physReg:NA Preferences=[rax] RelatedInterval Interval 24: ref RefPositions {#94@80 #101@85} physReg:NA Preferences=[rsi] Interval 25: int (constant) RefPositions {#95@82 #97@83} physReg:NA Preferences=[rdi] Interval 26: int RefPositions {#99@84 #103@85} physReg:NA Preferences=[rdi] Interval 27: float (INTERNAL) RefPositions {#113@93 #114@93} physReg:NA Preferences=[allFloat] Interval 28: int (INTERNAL) RefPositions {#115@105 #118@105} physReg:NA Preferences=[allInt] Interval 29: float (INTERNAL) RefPositions {#116@105 #119@105} physReg:NA Preferences=[allFloat] Interval 30: int (INTERNAL) RefPositions {#120@117 #123@117} physReg:NA Preferences=[allInt] Interval 31: float (INTERNAL) RefPositions {#121@117 #124@117} physReg:NA Preferences=[allFloat] Interval 32: int (INTERNAL) RefPositions {#126@125 #131@125} physReg:NA Preferences=[rdi] Interval 33: int (INTERNAL) RefPositions {#128@125 #132@125} physReg:NA Preferences=[rcx] Interval 34: int (INTERNAL) RefPositions {#130@125 #133@125} physReg:NA Preferences=[rsi] Interval 35: long RefPositions {#134@128 #136@129} physReg:NA Preferences=[rdi] Interval 36: long RefPositions {#138@130 #145@137} physReg:NA Preferences=[rdi] Interval 37: long RefPositions {#139@132 #141@133} physReg:NA Preferences=[rsi] Interval 38: long RefPositions {#143@134 #147@137} physReg:NA Preferences=[rsi] Interval 39: long RefPositions {#158@138 #161@139} physReg:NA Preferences=[rax] Interval 40: long RefPositions {#160@138 #162@139} physReg:NA Preferences=[rdx] ------------ REFPOSITIONS BEFORE ALLOCATION: ------------ BB00 regmask=[rdi] minReg=1 fixed regOptional> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_FLD BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_FLD BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> IND BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> CNS_INT BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1 last> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> IND BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> BB01 regmask=[rsi] minReg=1> LCL_VAR BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> STORE_BLK BB01 regmask=[allFloat] minReg=1> STORE_BLK BB01 regmask=[allFloat] minReg=1 last> STORE_BLK BB01 regmask=[allInt] minReg=1> STORE_BLK BB01 regmask=[allFloat] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> STORE_BLK BB01 regmask=[allInt] minReg=1 last> STORE_BLK BB01 regmask=[allFloat] minReg=1 last> STORE_BLK BB01 regmask=[allInt] minReg=1> STORE_BLK BB01 regmask=[allFloat] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> STORE_BLK BB01 regmask=[allInt] minReg=1 last> STORE_BLK BB01 regmask=[allFloat] minReg=1 last> BB01 regmask=[rdi] minReg=1> PUTARG_STK BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rcx] minReg=1> PUTARG_STK BB01 regmask=[rcx] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> PUTARG_STK BB01 regmask=[rsi] minReg=1 fixed> PUTARG_STK BB01 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rsi] minReg=1 last fixed> LCL_FLD BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> LCL_FLD BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL[0] BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rdx] minReg=1> CALL[1] BB01 regmask=[rdx] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> VAR REFPOSITIONS BEFORE ALLOCATION --- V00 (Interval 0) BB00 regmask=[rdi] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> --- V01 --- V02 --- V03 --- V04 --- V05 (Interval 1) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> --- V06 (Interval 2) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> --- V07 --- V08 --- V09 --- V10 --- V11 --- V12 (Interval 3) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[rsi] minReg=1 last fixed> --- V13 (Interval 4) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> --- V14 (Interval 5) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> --- V15 --- V16 (Interval 6) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> --- V17 Allocating Registers -------------------- The following table has one or more rows for each RefPosition that is handled during allocation. The first column provides the basic information about the RefPosition, with its type (e.g. Def, Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the action taken during allocation (e.g. Alloc a new register, or Keep an existing one). The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which may increase during allocation, in which case additional columns will appear. Registers which are not marked modified have ---- in their column. --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ | | | | | |V0 a| | | | | 0.#0 V0 Parm Alloc rbx | | | |V0 a| | | | | | | 1.#1 BB1 PredBB0 | | | |V0 a| | | | | | | 6.#2 C7 Def Alloc rdi | | | |V0 a| |C7 a| | | | | 7.#3 rdi Fixd Keep rdi | | | |V0 a| |C7 a| | | | | 7.#4 C7 Use * Keep rdi | | | |V0 a| |C7 a| | | | | 8.#5 rdi Fixd Keep rdi | | | |V0 a| | | | | | | 8.#6 I8 Def Alloc rdi | | | |V0 a| |I8 a| | | | | 9.#7 rdi Fixd Keep rdi | | | |V0 a| |I8 a| | | | | 9.#8 I8 Use * Keep rdi | | | |V0 a| |I8 a| | | | | 10.#9 rax Kill Keep rax | | | |V0 a| | | | | | | 10.#10 rcx Kill Keep rcx | | | |V0 a| | | | | | | 10.#11 rdx Kill Keep rdx | | | |V0 a| | | | | | | 10.#12 rsi Kill Keep rsi | | | |V0 a| | | | | | | 10.#13 rdi Kill Keep rdi | | | |V0 a| | | | | | | 10.#14 r8 Kill Keep r8 | | | |V0 a| | | | | | | 10.#15 r9 Kill Keep r9 | | | |V0 a| | | | | | | 10.#16 r10 Kill Keep r10 | | | |V0 a| | | | | | | 10.#17 r11 Kill Keep r11 | | | |V0 a| | | | | | | 10.#18 rax Fixd Keep rax | | | |V0 a| | | | | | | 10.#19 I9 Def Alloc rax |I9 a| | |V0 a| | | | | | | 11.#20 I9 Use * Keep rax |I9 a| | |V0 a| | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 12.#21 V5 Def Alloc r14 | | | |V0 a| | | | | | |V5 a| 18.#22 I10 Def Alloc rdi | | | |V0 a| |I10a| | | | |V5 a| 19.#23 V5 Use Keep r14 | | | |V0 a| |I10a| | | | |V5 a| 19.#24 I10 Use * Keep rdi | | | |V0 a| |I10a| | | | |V5 a| 22.#25 C11 Def Alloc rdi | | | |V0 a| |C11a| | | | |V5 a| 23.#26 rdi Fixd Keep rdi | | | |V0 a| |C11a| | | | |V5 a| 23.#27 C11 Use * Keep rdi | | | |V0 a| |C11a| | | | |V5 a| 24.#28 rdi Fixd Keep rdi | | | |V0 a| | | | | | |V5 a| 24.#29 I12 Def Alloc rdi | | | |V0 a| |I12a| | | | |V5 a| 25.#30 rdi Fixd Keep rdi | | | |V0 a| |I12a| | | | |V5 a| 25.#31 I12 Use * Keep rdi | | | |V0 a| |I12a| | | | |V5 a| 26.#32 rax Kill Keep rax | | | |V0 a| | | | | | |V5 a| 26.#33 rcx Kill Keep rcx | | | |V0 a| | | | | | |V5 a| 26.#34 rdx Kill Keep rdx | | | |V0 a| | | | | | |V5 a| 26.#35 rsi Kill Keep rsi | | | |V0 a| | | | | | |V5 a| 26.#36 rdi Kill Keep rdi | | | |V0 a| | | | | | |V5 a| 26.#37 r8 Kill Keep r8 | | | |V0 a| | | | | | |V5 a| 26.#38 r9 Kill Keep r9 | | | |V0 a| | | | | | |V5 a| 26.#39 r10 Kill Keep r10 | | | |V0 a| | | | | | |V5 a| 26.#40 r11 Kill Keep r11 | | | |V0 a| | | | | | |V5 a| 26.#41 rax Fixd Keep rax | | | |V0 a| | | | | | |V5 a| 26.#42 I13 Def Alloc rax |I13a| | |V0 a| | | | | | |V5 a| 27.#43 I13 Use * Keep rax |I13a| | |V0 a| | | | | | |V5 a| 28.#44 V6 Def Alloc rax |V6 a| | |V0 a| | | | | | |V5 a| 34.#45 I14 Def Alloc rsi |V6 a| | |V0 a|I14a| | | | | |V5 a| 35.#46 V6 Use Keep rax |V6 a| | |V0 a|I14a| | | | | |V5 a| 35.#47 I14 Use * Keep rsi |V6 a| | |V0 a|I14a| | | | | |V5 a| 39.#48 V5 Use * Keep r14 |V6 a| | |V0 a| | | | | | |V5 a| 40.#49 V13 Def Alloc r14 |V6 a| | |V0 a| | | | | | |V13a| 43.#50 V6 Use * Keep rax |V6 a| | |V0 a| | | | | | |V13a| 44.#51 V14 Def Alloc rax |V14a| | |V0 a| | | | | | |V13a| 46.#52 C15 Def Alloc rsi |V14a| | |V0 a|C15a| | | | | |V13a| 47.#53 C15 Use * Keep rsi |V14a| | |V0 a|C15a| | | | | |V13a| 48.#54 I16 Def Alloc rsi |V14a| | |V0 a|I16a| | | | | |V13a| 49.#55 I16 Use * Keep rsi |V14a| | |V0 a|I16a| | | | | |V13a| 50.#56 V16 Def Alloc rsi |V14a| | |V0 a|V16a| | | | | |V13a| 56.#57 C17 Def Alloc rdi |V14a| | |V0 a|V16a|C17a| | | | |V13a| 61.#58 V13 Use * Keep r14 |V14a| | |V0 a|V16a|C17a| | | | |V13a| 61.#59 V14 Use * Keep rax |V14a| | |V0 a|V16a|C17a| | | | |V13a| 61.#60 C17 Use * Keep rdi |V14a| | |V0 a|V16a|C17a| | | | |V13a| 61.#61 V16 Use * Keep rsi |V14a| | |V0 a|V16a|C17a| | | | |V13a| 64.#62 C18 Def Alloc rsi | | | |V0 a|C18a|C17i| | | | | | 65.#63 C18 Use * Keep rsi | | | |V0 a|C18a|C17i| | | | | | 66.#64 I19 Def Alloc rsi | | | |V0 a|I19a|C17i| | | | | | 67.#65 rsi Fixd Keep rsi | | | |V0 a|I19a|C17i| | | | | | 67.#66 I19 Use * Keep rsi | | | |V0 a|I19a|C17i| | | | | | 68.#67 rsi Fixd Keep rsi | | | |V0 a| |C17i| | | | | | 68.#68 I20 Def Alloc rsi | | | |V0 a|I20a|C17i| | | | | | 70.#69 C21 Def Reuse rdi | | | |V0 a|I20a|C21a| | | | | | 71.#70 rdi Fixd Keep rdi | | | |V0 a|I20a|C21a| | | | | | 71.#71 C21 Use * Keep rdi | | | |V0 a|I20a|C21a| | | | | | 72.#72 rdi Fixd Keep rdi | | | |V0 a|I20a| | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 72.#73 I22 Def Alloc rdi | | | |V0 a|I20a|I22a| | | | | | 73.#74 rsi Fixd Keep rsi | | | |V0 a|I20a|I22a| | | | | | 73.#75 I20 Use * Keep rsi | | | |V0 a|I20a|I22a| | | | | | 73.#76 rdi Fixd Keep rdi | | | |V0 a|I20a|I22a| | | | | | 73.#77 I22 Use * Keep rdi | | | |V0 a|I20a|I22a| | | | | | 74.#78 rax Kill Keep rax | | | |V0 a| | | | | | | | 74.#79 rcx Kill Keep rcx | | | |V0 a| | | | | | | | 74.#80 rdx Kill Keep rdx | | | |V0 a| | | | | | | | 74.#81 rsi Kill Keep rsi | | | |V0 a| | | | | | | | 74.#82 rdi Kill Keep rdi | | | |V0 a| | | | | | | | 74.#83 r8 Kill Keep r8 | | | |V0 a| | | | | | | | 74.#84 r9 Kill Keep r9 | | | |V0 a| | | | | | | | 74.#85 r10 Kill Keep r10 | | | |V0 a| | | | | | | | 74.#86 r11 Kill Keep r11 | | | |V0 a| | | | | | | | 74.#87 rax Fixd Keep rax | | | |V0 a| | | | | | | | 74.#88 I23 Def Alloc rax |I23a| | |V0 a| | | | | | | | 75.#89 I23 Use * Keep rax |I23a| | |V0 a| | | | | | | | 76.#90 V12 Def Alloc rsi | | | |V0 a|V12a| | | | | | | 79.#91 rsi Fixd Keep rsi | | | |V0 a|V12a| | | | | | | 79.#92 V12 Use * Keep rsi | | | |V0 a|V12a| | | | | | | 80.#93 rsi Fixd Keep rsi | | | |V0 a| | | | | | | | 80.#94 I24 Def Alloc rsi | | | |V0 a|I24a| | | | | | | 82.#95 C25 Def Alloc rdi | | | |V0 a|I24a|C25a| | | | | | 83.#96 rdi Fixd Keep rdi | | | |V0 a|I24a|C25a| | | | | | 83.#97 C25 Use * Keep rdi | | | |V0 a|I24a|C25a| | | | | | 84.#98 rdi Fixd Keep rdi | | | |V0 a|I24a| | | | | | | 84.#99 I26 Def Alloc rdi | | | |V0 a|I24a|I26a| | | | | | 85.#100 rsi Fixd Keep rsi | | | |V0 a|I24a|I26a| | | | | | 85.#101 I24 Use * Keep rsi | | | |V0 a|I24a|I26a| | | | | | 85.#102 rdi Fixd Keep rdi | | | |V0 a|I24a|I26a| | | | | | 85.#103 I26 Use * Keep rdi | | | |V0 a|I24a|I26a| | | | | | 86.#104 rax Kill Keep rax | | | |V0 a| | | | | | | | 86.#105 rcx Kill Keep rcx | | | |V0 a| | | | | | | | 86.#106 rdx Kill Keep rdx | | | |V0 a| | | | | | | | 86.#107 rsi Kill Keep rsi | | | |V0 a| | | | | | | | 86.#108 rdi Kill Keep rdi | | | |V0 a| | | | | | | | 86.#109 r8 Kill Keep r8 | | | |V0 a| | | | | | | | 86.#110 r9 Kill Keep r9 | | | |V0 a| | | | | | | | 86.#111 r10 Kill Keep r10 | | | |V0 a| | | | | | | | 86.#112 r11 Kill Keep r11 | | | |V0 a| | | | | | | | 93.#113 I27 Def Alloc mm0 | | | |V0 a| | | | | | | | 93.#114 I27 Use * Keep mm0 | | | |V0 a| | | | | | | | 105.#115 I28 Def Alloc rdi | | | |V0 a| |I28a| | | | | | 105.#116 I29 Def Alloc mm0 | | | |V0 a| |I28a| | | | | | 105.#117 V0 Use Keep rbx | | | |V0 a| |I28a| | | | | | 105.#118 I28 Use * Keep rdi | | | |V0 a| |I28a| | | | | | 105.#119 I29 Use * Keep mm0 | | | |V0 a| |I28a| | | | | | 117.#120 I30 Def Alloc rdi | | | |V0 a| |I30a| | | | | | 117.#121 I31 Def Alloc mm0 | | | |V0 a| |I30a| | | | | | 117.#122 V0 Use * Keep rbx | | | |V0 a| |I30a| | | | | | 117.#123 I30 Use * Keep rdi | | | |V0 a| |I30a| | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 117.#124 I31 Use * Keep mm0 | | | |V0 a| |I30a| | | | | | 125.#125 rdi Fixd Keep rdi | | | | | | | | | | | | 125.#126 I32 Def Alloc rdi | | | | | |I32a| | | | | | 125.#127 rcx Fixd Keep rcx | | | | | |I32a| | | | | | 125.#128 I33 Def Alloc rcx | |I33a| | | |I32a| | | | | | 125.#129 rsi Fixd Keep rsi | |I33a| | | |I32a| | | | | | 125.#130 I34 Def Alloc rsi | |I33a| | |I34a|I32a| | | | | | 125.#131 I32 Use * Keep rdi | |I33a| | |I34a|I32a| | | | | | 125.#132 I33 Use * Keep rcx | |I33a| | |I34a|I32a| | | | | | 125.#133 I34 Use * Keep rsi | |I33a| | |I34a|I32a| | | | | | 128.#134 I35 Def Alloc rdi | | | | | |I35a| | | | | | 129.#135 rdi Fixd Keep rdi | | | | | |I35a| | | | | | 129.#136 I35 Use * Keep rdi | | | | | |I35a| | | | | | 130.#137 rdi Fixd Keep rdi | | | | | | | | | | | | 130.#138 I36 Def Alloc rdi | | | | | |I36a| | | | | | 132.#139 I37 Def Alloc rsi | | | | |I37a|I36a| | | | | | 133.#140 rsi Fixd Keep rsi | | | | |I37a|I36a| | | | | | 133.#141 I37 Use * Keep rsi | | | | |I37a|I36a| | | | | | 134.#142 rsi Fixd Keep rsi | | | | | |I36a| | | | | | 134.#143 I38 Def Alloc rsi | | | | |I38a|I36a| | | | | | 137.#144 rdi Fixd Keep rdi | | | | |I38a|I36a| | | | | | 137.#145 I36 Use * Keep rdi | | | | |I38a|I36a| | | | | | 137.#146 rsi Fixd Keep rsi | | | | |I38a|I36a| | | | | | 137.#147 I38 Use * Keep rsi | | | | |I38a|I36a| | | | | | 138.#148 rax Kill Keep rax | | | | | | | | | | | | 138.#149 rcx Kill Keep rcx | | | | | | | | | | | | 138.#150 rdx Kill Keep rdx | | | | | | | | | | | | 138.#151 rsi Kill Keep rsi | | | | | | | | | | | | 138.#152 rdi Kill Keep rdi | | | | | | | | | | | | 138.#153 r8 Kill Keep r8 | | | | | | | | | | | | 138.#154 r9 Kill Keep r9 | | | | | | | | | | | | 138.#155 r10 Kill Keep r10 | | | | | | | | | | | | 138.#156 r11 Kill Keep r11 | | | | | | | | | | | | 138.#157 rax Fixd Keep rax | | | | | | | | | | | | 138.#158 I39 Def Alloc rax |I39a| | | | | | | | | | | 138.#159 rdx Fixd Keep rdx |I39a| | | | | | | | | | | 138.#160 I40 Def Alloc rdx |I39a| |I40a| | | | | | | | | 139.#161 I39 Use * Keep rax |I39a| |I40a| | | | | | | | | 139.#162 I40 Use * Keep rdx | | | | | | | | | | | | ------------ REFPOSITIONS AFTER ALLOCATION: ------------ BB00 regmask=[rbx] minReg=1 fixed regOptional> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB01 regmask=[r14] minReg=1> LCL_FLD BB01 regmask=[rdi] minReg=1> LCL_VAR BB01 regmask=[r14] minReg=1> BB01 regmask=[rdi] minReg=1 last> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB01 regmask=[rax] minReg=1> LCL_FLD BB01 regmask=[rsi] minReg=1> LCL_VAR BB01 regmask=[rax] minReg=1> BB01 regmask=[rsi] minReg=1 last> LCL_VAR BB01 regmask=[r14] minReg=1 last> STORE_LCL_VAR BB01 regmask=[r14] minReg=1> LCL_VAR BB01 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB01 regmask=[rax] minReg=1> CNS_INT BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last> IND BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last> STORE_LCL_VAR BB01 regmask=[rsi] minReg=1> CNS_INT BB01 regmask=[rdi] minReg=1> LCL_VAR BB01 regmask=[r14] minReg=1 last> LCL_VAR BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> LCL_VAR BB01 regmask=[rsi] minReg=1 last> CNS_INT BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last> IND BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> LCL_VAR BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> STORE_BLK BB01 regmask=[mm0] minReg=1> STORE_BLK BB01 regmask=[mm0] minReg=1 last> STORE_BLK BB01 regmask=[rdi] minReg=1> STORE_BLK BB01 regmask=[mm0] minReg=1> LCL_VAR BB01 regmask=[rbx] minReg=1> STORE_BLK BB01 regmask=[rdi] minReg=1 last> STORE_BLK BB01 regmask=[mm0] minReg=1 last> STORE_BLK BB01 regmask=[rdi] minReg=1> STORE_BLK BB01 regmask=[mm0] minReg=1> LCL_VAR BB01 regmask=[rbx] minReg=1 last> STORE_BLK BB01 regmask=[rdi] minReg=1 last> STORE_BLK BB01 regmask=[mm0] minReg=1 last> BB01 regmask=[rdi] minReg=1> PUTARG_STK BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rcx] minReg=1> PUTARG_STK BB01 regmask=[rcx] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> PUTARG_STK BB01 regmask=[rsi] minReg=1 fixed> PUTARG_STK BB01 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB01 regmask=[rsi] minReg=1 last fixed> LCL_FLD BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> LCL_FLD BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL[0] BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rdx] minReg=1> CALL[1] BB01 regmask=[rdx] minReg=1 fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> VAR REFPOSITIONS AFTER ALLOCATION --- V00 (Interval 0) BB00 regmask=[rbx] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[rbx] minReg=1> LCL_VAR BB01 regmask=[rbx] minReg=1 last> --- V01 --- V02 --- V03 --- V04 --- V05 (Interval 1) STORE_LCL_VAR BB01 regmask=[r14] minReg=1> LCL_VAR BB01 regmask=[r14] minReg=1> LCL_VAR BB01 regmask=[r14] minReg=1 last> --- V06 (Interval 2) STORE_LCL_VAR BB01 regmask=[rax] minReg=1> LCL_VAR BB01 regmask=[rax] minReg=1> LCL_VAR BB01 regmask=[rax] minReg=1 last> --- V07 --- V08 --- V09 --- V10 --- V11 --- V12 (Interval 3) STORE_LCL_VAR BB01 regmask=[rsi] minReg=1> LCL_VAR BB01 regmask=[rsi] minReg=1 last fixed> --- V13 (Interval 4) STORE_LCL_VAR BB01 regmask=[r14] minReg=1> LCL_VAR BB01 regmask=[r14] minReg=1 last> --- V14 (Interval 5) STORE_LCL_VAR BB01 regmask=[rax] minReg=1> LCL_VAR BB01 regmask=[rax] minReg=1 last> --- V15 --- V16 (Interval 6) STORE_LCL_VAR BB01 regmask=[rsi] minReg=1> LCL_VAR BB01 regmask=[rsi] minReg=1 last> --- V17 Active intervals at end of allocation: ----------------------- RESOLVING BB BOUNDARIES ----------------------- Resolution Candidates: {V00} Has NoCritical Edges Prior to Resolution BB01 use def in out {V00 V02} {V03 V05 V06 V12 V13 V14 V15 V16 V17} {V00 V02} {} Var=Reg beg of BB01: V00=rbx Var=Reg end of BB01: none RESOLVING EDGES Set V00 argument initial register to rbx Trees after linear scan register allocator (LSRA) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..04F) (return), preds={} succs={} N003 (???,???) [000129] ------------ IL_OFFSET void IL offset: 0x0 REG NA N005 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class REG rdi $180 /--* t4 long N007 (???,???) [000137] ------------ t137 = * PUTARG_REG long REG rdi /--* t137 long arg0 in rdi N009 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG rax $200 /--* t5 ref N011 ( 16, 16) [000007] DA---------- * STORE_LCL_VAR ref V05 tmp1 d:2 r14 REG r14 N013 ( 1, 1) [000008] ------------ t8 = LCL_VAR ref V05 tmp1 u:2 r14 REG r14 $200 /--* t8 ref N015 ( 2, 2) [000010] -c---------- t10 = * LEA(b+8) byref REG NA N017 ( 3, 4) [000003] ------------ t3 = LCL_FLD int V02 arg2 u:1[+8] Fseq[Version] rdi REG rdi $2c0 /--* t10 byref +--* t3 int N019 (???,???) [000130] -A--GO------ * STOREIND int REG NA N021 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class REG rdi $182 /--* t18 long N023 (???,???) [000138] ------------ t138 = * PUTARG_REG long REG rdi /--* t138 long arg0 in rdi N025 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG rax $201 /--* t19 ref N027 ( 16, 16) [000021] DA---------- * STORE_LCL_VAR ref V06 tmp2 d:2 rax REG rax N029 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V06 tmp2 u:2 rax REG rax $201 /--* t22 ref N031 ( 2, 2) [000024] -c---------- t24 = * LEA(b+8) byref REG NA N033 ( 3, 4) [000017] ------------ t17 = LCL_FLD long V02 arg2 u:1[+0] Fseq[JobGroup] rsi REG rsi $300 /--* t24 byref +--* t17 long N035 (???,???) [000131] -A--GO------ * STOREIND long REG NA N037 ( 1, 1) [000013] ------------ t13 = LCL_VAR ref V05 tmp1 u:2 r14 (last use) REG r14 $200 /--* t13 ref N039 ( 11, 8) [000077] DA---------- * STORE_LCL_VAR ref V13 tmp9 d:2 r14 REG r14 N041 ( 1, 1) [000027] ------------ t27 = LCL_VAR ref V06 tmp2 u:2 rax (last use) REG rax $201 /--* t27 ref N043 ( 11, 8) [000082] DA---------- * STORE_LCL_VAR ref V14 tmp10 d:2 rax REG rax N045 ( 2, 10) [000103] ------------ t103 = CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] REG rsi $184 /--* t103 long N047 ( 4, 12) [000090] n---G------- t90 = * IND ref REG rsi /--* t90 ref N049 ( 8, 15) [000092] DA--G------- * STORE_LCL_VAR ref V16 tmp12 d:2 rsi REG rsi N051 ( 3, 2) [000109] ------------ t109 = LCL_VAR ref V13 tmp9 u:2 r14 (last use) REG r14 $200 N053 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V14 tmp10 u:2 rax (last use) REG rax $201 N055 ( 1, 1) [000128] ------------ t128 = CNS_INT ref null REG rdi $VN.Null N057 ( 3, 2) [000112] ------------ t112 = LCL_VAR ref V16 tmp12 u:2 rsi (last use) REG rsi /--* t109 ref +--* t110 ref +--* t128 ref +--* t112 ref N059 ( 10, 7) [000108] -c---------- t108 = * FIELD_LIST struct REG NA $380 /--* t108 struct N061 (???,???) [000139] ------------ * PUTARG_STK [+0x00] void (4 slots) REG NA N063 ( 2, 10) [000104] ------------ t104 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] REG rsi $185 /--* t104 long N065 ( 4, 12) [000105] n---G------- t105 = * IND ref REG rsi /--* t105 ref N067 (???,???) [000140] ----G------- t140 = * PUTARG_REG ref REG rsi N069 ( 1, 1) [000060] ------------ t60 = CNS_INT ref null reuse reg val REG rdi $VN.Null /--* t60 ref N071 (???,???) [000141] ------------ t141 = * PUTARG_REG ref REG rdi /--* t140 ref arg1 in rsi +--* t141 ref arg0 in rdi N073 ( 32, 27) [000068] --CXG------- t68 = * CALL ref System.String.FormatHelper REG rax $1ce /--* t68 ref N075 ( 32, 27) [000099] DA-XG------- * STORE_LCL_VAR ref V12 tmp8 d:2 rsi REG rsi N077 ( 1, 1) [000096] ------------ t96 = LCL_VAR ref V12 tmp8 u:2 rsi (last use) REG rsi $1ce /--* t96 ref N079 (???,???) [000142] ------------ t142 = * PUTARG_REG ref REG rsi N081 ( 1, 1) [000095] ------------ t95 = CNS_INT int 3 REG rdi $44 /--* t95 int N083 (???,???) [000143] ------------ t143 = * PUTARG_REG int REG rdi /--* t142 ref arg1 in rsi +--* t143 int arg0 in rdi N085 ( 16, 9) [000097] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal REG NA $VN.Void N087 (???,???) [000132] ------------ IL_OFFSET void IL offset: 0x25 REG NA N089 ( 1, 1) [000034] -c---------- t34 = CNS_INT int 0 REG NA $40 N091 (???,???) [000144] Dc-----N---- t144 = LCL_VAR_ADDR byref V03 loc0 NA REG NA /--* t144 byref +--* t34 int N093 ( 5, 4) [000035] sA---------- * STORE_BLK struct (init) (Unroll) REG NA N095 (???,???) [000133] ------------ IL_OFFSET void IL offset: 0x2d REG NA N097 ( 1, 1) [000038] ------------ t38 = LCL_VAR byref V00 this u:1 rbx REG rbx $80 /--* t38 byref N099 ( 3, 3) [000118] -c---------- t118 = * LEA(b+16) byref REG NA /--* t118 byref N101 ( 6, 5) [000039] *c-XG------- t39 = * IND struct REG NA N103 ( 3, 4) [000036] Uc-----N---- t36 = LCL_FLD_ADDR byref V03 loc0 ud:2->3[+40] Fseq[Baselib] NA REG NA /--* t36 byref +--* t39 struct N105 ( 9, 9) [000042] nA-XG------- * STORE_BLK struct (copy) (Unroll) REG NA N107 (???,???) [000134] ------------ IL_OFFSET void IL offset: 0x3a REG NA N109 ( 1, 1) [000046] ------------ t46 = LCL_VAR byref V00 this u:1 rbx (last use) REG rbx $80 /--* t46 byref N111 ( 3, 3) [000120] -c---------- t120 = * LEA(b+112) byref REG NA /--* t120 byref N113 ( 6, 5) [000047] *c--GO------ t47 = * IND struct REG NA N115 ( 3, 4) [000044] Uc-----N---- t44 = LCL_FLD_ADDR byref V03 loc0 ud:3->4[+0] Fseq[Tx] NA REG NA /--* t44 byref +--* t47 struct N117 ( 6, 7) [000050] nA--GO------ * STORE_BLK struct (copy) (Unroll) REG NA N119 (???,???) [000135] ------------ IL_OFFSET void IL offset: 0x47 REG NA N121 ( 3, 2) [000052] -c-----N---- t52 = LCL_VAR_ADDR byref V03 loc0 u:4 NA (last use) REG NA /--* t52 byref N123 ( 9, 7) [000058] nc---------- t58 = * OBJ struct REG NA $388 /--* t58 struct N125 (???,???) [000145] ------------ * PUTARG_STK [+0x00] void (12 slots) (RepInstr) REG NA N127 ( 3, 4) [000125] ------------ t125 = LCL_FLD long V02 arg2 u:1[+0] rdi REG rdi $142 /--* t125 long N129 (???,???) [000146] ------------ t146 = * PUTARG_REG long REG rdi N131 ( 3, 4) [000126] ------------ t126 = LCL_FLD long V02 arg2 u:1[+8] rsi (last use) REG rsi $143 /--* t126 long N133 (???,???) [000147] ------------ t147 = * PUTARG_REG long REG rsi /--* t146 long +--* t147 long N135 ( 6, 8) [000124] -c---------- t124 = * FIELD_LIST struct REG NA $38a /--* t124 struct arg1 rdi,rsi N137 ( 32, 21) [000054] --CXG------- t54 = * CALL struct Unity.Jobs.IJobExtensions.Schedule REG rax,rdx $38b /--* t54 struct N139 ( 36, 24) [000122] DA-XG------- * STORE_LCL_VAR struct V17 tmp13 d:2 NA REG NA N141 (???,???) [000136] ------------ IL_OFFSET void IL offset: 0x47 REG NA N143 ( 3, 2) [000127] -c-----N---- t127 = LCL_VAR struct V17 tmp13 u:2 NA (last use) REG NA $38e /--* t127 struct N145 ( 4, 3) [000059] ----G------- * RETURN struct REG NA $38f ------------------------------------------------------------------------------------------------------------------- Final allocation --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 0.#0 V0 Parm Alloc rbx | | | |V0 a| | | | | | | | 1.#1 BB1 PredBB0 | | | |V0 a| | | | | | | | 6.#2 C7 Def Alloc rdi | | | |V0 a| |C7 a| | | | | | 7.#3 rdi Fixd Keep rdi | | | |V0 a| |C7 a| | | | | | 7.#4 C7 Use * Keep rdi | | | |V0 a| |C7 i| | | | | | 8.#5 rdi Fixd Keep rdi | | | |V0 a| | | | | | | | 8.#6 I8 Def Alloc rdi | | | |V0 a| |I8 a| | | | | | 9.#7 rdi Fixd Keep rdi | | | |V0 a| |I8 a| | | | | | 9.#8 I8 Use * Keep rdi | | | |V0 a| |I8 i| | | | | | 10.#9 rax Kill Keep rax | | | |V0 a| | | | | | | | 10.#10 rcx Kill Keep rcx | | | |V0 a| | | | | | | | 10.#11 rdx Kill Keep rdx | | | |V0 a| | | | | | | | 10.#12 rsi Kill Keep rsi | | | |V0 a| | | | | | | | 10.#13 rdi Kill Keep rdi | | | |V0 a| | | | | | | | 10.#14 r8 Kill Keep r8 | | | |V0 a| | | | | | | | 10.#15 r9 Kill Keep r9 | | | |V0 a| | | | | | | | 10.#16 r10 Kill Keep r10 | | | |V0 a| | | | | | | | 10.#17 r11 Kill Keep r11 | | | |V0 a| | | | | | | | 10.#18 rax Fixd Keep rax | | | |V0 a| | | | | | | | 10.#19 I9 Def Alloc rax |I9 a| | |V0 a| | | | | | | | 11.#20 I9 Use * Keep rax |I9 i| | |V0 a| | | | | | | | 12.#21 V5 Def Alloc r14 | | | |V0 a| | | | | | |V5 a| 18.#22 I10 Def Alloc rdi | | | |V0 a| |I10a| | | | |V5 a| 19.#23 V5 Use Keep r14 | | | |V0 a| |I10a| | | | |V5 a| 19.#24 I10 Use * Keep rdi | | | |V0 a| |I10i| | | | |V5 a| 22.#25 C11 Def Alloc rdi | | | |V0 a| |C11a| | | | |V5 a| 23.#26 rdi Fixd Keep rdi | | | |V0 a| |C11a| | | | |V5 a| 23.#27 C11 Use * Keep rdi | | | |V0 a| |C11i| | | | |V5 a| 24.#28 rdi Fixd Keep rdi | | | |V0 a| | | | | | |V5 a| 24.#29 I12 Def Alloc rdi | | | |V0 a| |I12a| | | | |V5 a| 25.#30 rdi Fixd Keep rdi | | | |V0 a| |I12a| | | | |V5 a| 25.#31 I12 Use * Keep rdi | | | |V0 a| |I12i| | | | |V5 a| 26.#32 rax Kill Keep rax | | | |V0 a| | | | | | |V5 a| 26.#33 rcx Kill Keep rcx | | | |V0 a| | | | | | |V5 a| 26.#34 rdx Kill Keep rdx | | | |V0 a| | | | | | |V5 a| 26.#35 rsi Kill Keep rsi | | | |V0 a| | | | | | |V5 a| 26.#36 rdi Kill Keep rdi | | | |V0 a| | | | | | |V5 a| 26.#37 r8 Kill Keep r8 | | | |V0 a| | | | | | |V5 a| 26.#38 r9 Kill Keep r9 | | | |V0 a| | | | | | |V5 a| 26.#39 r10 Kill Keep r10 | | | |V0 a| | | | | | |V5 a| 26.#40 r11 Kill Keep r11 | | | |V0 a| | | | | | |V5 a| 26.#41 rax Fixd Keep rax | | | |V0 a| | | | | | |V5 a| 26.#42 I13 Def Alloc rax |I13a| | |V0 a| | | | | | |V5 a| 27.#43 I13 Use * Keep rax |I13i| | |V0 a| | | | | | |V5 a| 28.#44 V6 Def Alloc rax |V6 a| | |V0 a| | | | | | |V5 a| 34.#45 I14 Def Alloc rsi |V6 a| | |V0 a|I14a| | | | | |V5 a| 35.#46 V6 Use Keep rax |V6 a| | |V0 a|I14a| | | | | |V5 a| 35.#47 I14 Use * Keep rsi |V6 a| | |V0 a|I14i| | | | | |V5 a| 39.#48 V5 Use * Keep r14 |V6 a| | |V0 a| | | | | | |V5 i| 40.#49 V13 Def Alloc r14 |V6 a| | |V0 a| | | | | | |V13a| 43.#50 V6 Use * Keep rax |V6 i| | |V0 a| | | | | | |V13a| 44.#51 V14 Def Alloc rax |V14a| | |V0 a| | | | | | |V13a| 46.#52 C15 Def Alloc rsi |V14a| | |V0 a|C15a| | | | | |V13a| 47.#53 C15 Use * Keep rsi |V14a| | |V0 a|C15i| | | | | |V13a| 48.#54 I16 Def Alloc rsi |V14a| | |V0 a|I16a| | | | | |V13a| 49.#55 I16 Use * Keep rsi |V14a| | |V0 a|I16i| | | | | |V13a| 50.#56 V16 Def Alloc rsi |V14a| | |V0 a|V16a| | | | | |V13a| 56.#57 C17 Def Alloc rdi |V14a| | |V0 a|V16a|C17a| | | | |V13a| 61.#58 V13 Use * Keep r14 |V14a| | |V0 a|V16a|C17a| | | | |V13i| 61.#59 V14 Use * Keep rax |V14i| | |V0 a|V16a|C17a| | | | | | 61.#60 C17 Use * Keep rdi | | | |V0 a|V16a|C17i| | | | | | 61.#61 V16 Use * Keep rsi | | | |V0 a|V16i| | | | | | | 64.#62 C18 Def Alloc rsi | | | |V0 a|C18a| | | | | | | 65.#63 C18 Use * Keep rsi | | | |V0 a|C18i| | | | | | | 66.#64 I19 Def Alloc rsi | | | |V0 a|I19a| | | | | | | 67.#65 rsi Fixd Keep rsi | | | |V0 a|I19a| | | | | | | 67.#66 I19 Use * Keep rsi | | | |V0 a|I19i| | | | | | | 68.#67 rsi Fixd Keep rsi | | | |V0 a| | | | | | | | 68.#68 I20 Def Alloc rsi | | | |V0 a|I20a| | | | | | | 70.#69 C21 Def Reuse rdi | | | |V0 a|I20a|C21a| | | | | | 71.#70 rdi Fixd Keep rdi | | | |V0 a|I20a|C21a| | | | | | 71.#71 C21 Use * Keep rdi | | | |V0 a|I20a|C21i| | | | | | 72.#72 rdi Fixd Keep rdi | | | |V0 a|I20a| | | | | | | 72.#73 I22 Def Alloc rdi | | | |V0 a|I20a|I22a| | | | | | 73.#74 rsi Fixd Keep rsi | | | |V0 a|I20a|I22a| | | | | | 73.#75 I20 Use * Keep rsi | | | |V0 a|I20i|I22a| | | | | | 73.#76 rdi Fixd Keep rdi | | | |V0 a| |I22a| | | | | | 73.#77 I22 Use * Keep rdi | | | |V0 a| |I22i| | | | | | 74.#78 rax Kill Keep rax | | | |V0 a| | | | | | | | 74.#79 rcx Kill Keep rcx | | | |V0 a| | | | | | | | 74.#80 rdx Kill Keep rdx | | | |V0 a| | | | | | | | 74.#81 rsi Kill Keep rsi | | | |V0 a| | | | | | | | 74.#82 rdi Kill Keep rdi | | | |V0 a| | | | | | | | 74.#83 r8 Kill Keep r8 | | | |V0 a| | | | | | | | 74.#84 r9 Kill Keep r9 | | | |V0 a| | | | | | | | 74.#85 r10 Kill Keep r10 | | | |V0 a| | | | | | | | 74.#86 r11 Kill Keep r11 | | | |V0 a| | | | | | | | 74.#87 rax Fixd Keep rax | | | |V0 a| | | | | | | | 74.#88 I23 Def Alloc rax |I23a| | |V0 a| | | | | | | | 75.#89 I23 Use * Keep rax |I23i| | |V0 a| | | | | | | | 76.#90 V12 Def Alloc rsi | | | |V0 a|V12a| | | | | | | 79.#91 rsi Fixd Keep rsi | | | |V0 a|V12a| | | | | | | 79.#92 V12 Use * Keep rsi | | | |V0 a|V12i| | | | | | | 80.#93 rsi Fixd Keep rsi | | | |V0 a| | | | | | | | 80.#94 I24 Def Alloc rsi | | | |V0 a|I24a| | | | | | | 82.#95 C25 Def Alloc rdi | | | |V0 a|I24a|C25a| | | | | | 83.#96 rdi Fixd Keep rdi | | | |V0 a|I24a|C25a| | | | | | 83.#97 C25 Use * Keep rdi | | | |V0 a|I24a|C25i| | | | | | 84.#98 rdi Fixd Keep rdi | | | |V0 a|I24a| | | | | | | 84.#99 I26 Def Alloc rdi | | | |V0 a|I24a|I26a| | | | | | 85.#100 rsi Fixd Keep rsi | | | |V0 a|I24a|I26a| | | | | | 85.#101 I24 Use * Keep rsi | | | |V0 a|I24i|I26a| | | | | | 85.#102 rdi Fixd Keep rdi | | | |V0 a| |I26a| | | | | | 85.#103 I26 Use * Keep rdi | | | |V0 a| |I26i| | | | | | 86.#104 rax Kill Keep rax | | | |V0 a| | | | | | | | 86.#105 rcx Kill Keep rcx | | | |V0 a| | | | | | | | 86.#106 rdx Kill Keep rdx | | | |V0 a| | | | | | | | 86.#107 rsi Kill Keep rsi | | | |V0 a| | | | | | | | 86.#108 rdi Kill Keep rdi | | | |V0 a| | | | | | | | 86.#109 r8 Kill Keep r8 | | | |V0 a| | | | | | | | 86.#110 r9 Kill Keep r9 | | | |V0 a| | | | | | | | 86.#111 r10 Kill Keep r10 | | | |V0 a| | | | | | | | 86.#112 r11 Kill Keep r11 | | | |V0 a| | | | | | | | 93.#113 I27 Def Alloc mm0 | | | |V0 a| | | | | | | | 93.#114 I27 Use * Keep mm0 | | | |V0 a| | | | | | | | 105.#115 I28 Def Alloc rdi | | | |V0 a| |I28a| | | | | | 105.#116 I29 Def Alloc mm0 | | | |V0 a| |I28a| | | | | | 105.#117 V0 Use Keep rbx | | | |V0 a| |I28a| | | | | | 105.#118 I28 Use * Keep rdi | | | |V0 a| |I28i| | | | | | 105.#119 I29 Use * Keep mm0 | | | |V0 a| | | | | | | | 117.#120 I30 Def Alloc rdi | | | |V0 a| |I30a| | | | | | 117.#121 I31 Def Alloc mm0 | | | |V0 a| |I30a| | | | | | 117.#122 V0 Use * Keep rbx | | | |V0 i| |I30a| | | | | | 117.#123 I30 Use * Keep rdi | | | | | |I30i| | | | | | 117.#124 I31 Use * Keep mm0 | | | | | | | | | | | | 125.#125 rdi Fixd Keep rdi | | | | | | | | | | | | 125.#126 I32 Def Alloc rdi | | | | | |I32a| | | | | | 125.#127 rcx Fixd Keep rcx | | | | | |I32a| | | | | | 125.#128 I33 Def Alloc rcx | |I33a| | | |I32a| | | | | | 125.#129 rsi Fixd Keep rsi | |I33a| | | |I32a| | | | | | 125.#130 I34 Def Alloc rsi | |I33a| | |I34a|I32a| | | | | | 125.#131 I32 Use * Keep rdi | |I33a| | |I34a|I32i| | | | | | 125.#132 I33 Use * Keep rcx | |I33i| | |I34a| | | | | | | 125.#133 I34 Use * Keep rsi | | | | |I34i| | | | | | | 128.#134 I35 Def Alloc rdi | | | | | |I35a| | | | | | 129.#135 rdi Fixd Keep rdi | | | | | |I35a| | | | | | 129.#136 I35 Use * Keep rdi | | | | | |I35i| | | | | | 130.#137 rdi Fixd Keep rdi | | | | | | | | | | | | 130.#138 I36 Def Alloc rdi | | | | | |I36a| | | | | | 132.#139 I37 Def Alloc rsi | | | | |I37a|I36a| | | | | | 133.#140 rsi Fixd Keep rsi | | | | |I37a|I36a| | | | | | 133.#141 I37 Use * Keep rsi | | | | |I37i|I36a| | | | | | 134.#142 rsi Fixd Keep rsi | | | | | |I36a| | | | | | 134.#143 I38 Def Alloc rsi | | | | |I38a|I36a| | | | | | 137.#144 rdi Fixd Keep rdi | | | | |I38a|I36a| | | | | | 137.#145 I36 Use * Keep rdi | | | | |I38a|I36i| | | | | | 137.#146 rsi Fixd Keep rsi | | | | |I38a| | | | | | | 137.#147 I38 Use * Keep rsi | | | | |I38i| | | | | | | 138.#148 rax Kill Keep rax | | | | | | | | | | | | 138.#149 rcx Kill Keep rcx | | | | | | | | | | | | 138.#150 rdx Kill Keep rdx | | | | | | | | | | | | 138.#151 rsi Kill Keep rsi | | | | | | | | | | | | 138.#152 rdi Kill Keep rdi | | | | | | | | | | | | 138.#153 r8 Kill Keep r8 | | | | | | | | | | | | 138.#154 r9 Kill Keep r9 | | | | | | | | | | | | 138.#155 r10 Kill Keep r10 | | | | | | | | | | | | 138.#156 r11 Kill Keep r11 | | | | | | | | | | | | 138.#157 rax Fixd Keep rax | | | | | | | | | | | | 138.#158 I39 Def Alloc rax |I39a| | | | | | | | | | | 138.#159 rdx Fixd Keep rdx |I39a| | | | | | | | | | | 138.#160 I40 Def Alloc rdx |I39a| |I40a| | | | | | | | | 139.#161 I39 Use * Keep rax |I39i| |I40a| | | | | | | | | 139.#162 I40 Use * Keep rdx | | |I40i| | | | | | | | | Recording the maximum number of concurrent spills: ---------- LSRA Stats ---------- Total Tracked Vars: 11 Total Reg Cand Vars: 7 Total number of Intervals: 40 Total number of RefPositions: 162 Total Spill Count: 0 Weighted: 0 Total CopyReg Count: 0 Weighted: 0 Total ResolutionMov Count: 0 Weighted: 0 Total number of split edges: 0 Total Number of spill temps created: 0 TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS Incoming Parameters: V00(rdi=>rbx) BB01 [000..04F) (return), preds={} succs={} ===== N003. IL_OFFSET IL offset: 0x0 N005. rdi = CNS_INT(h) 0x7f6678beb1c0 class N007. rdi = PUTARG_REG; rdi N009. rax = CALL help; rdi * N011. V05(r14); rax N013. V05(r14) N015. STK = LEA(b+8) ; r14 N017. rdi = V02 MEM N019. STOREIND ; STK,rdi N021. rdi = CNS_INT(h) 0x7f6678c127f0 class N023. rdi = PUTARG_REG; rdi N025. rax = CALL help; rdi * N027. V06(rax); rax N029. V06(rax) N031. STK = LEA(b+8) ; rax N033. rsi = V02 MEM N035. STOREIND ; STK,rsi N037. V05(r14*) * N039. V13(r14); r14* N041. V06(rax*) * N043. V14(rax); rax* N045. rsi = CNS_INT(h) 0x7f6663fff340 static Fseq[s_twoArgArray] N047. rsi = IND ; rsi * N049. V16(rsi); rsi N051. V13(r14*) N053. V14(rax*) N055. rdi = CNS_INT null N057. V16(rsi*) N059. STK = FIELD_LIST; r14*,rax*,rdi,rsi* N061. PUTARG_STK [+0x00]; STK N063. rsi = CNS_INT(h) 0x640084D0 [ICON_STR_HDL] N065. rsi = IND ; rsi N067. rsi = PUTARG_REG; rsi N069. rdi = CNS_INT null reuse reg val N071. rdi = PUTARG_REG; rdi N073. rax = CALL ; rsi,rdi * N075. V12(rsi); rax N077. V12(rsi*) N079. rsi = PUTARG_REG; rsi* N081. rdi = CNS_INT 3 N083. rdi = PUTARG_REG; rdi N085. CALL ; rsi,rdi N087. IL_OFFSET IL offset: 0x25 N089. CNS_INT 0 N091. LCL_VAR_ADDR V03 loc0 NA N093. STORE_BLK N095. IL_OFFSET IL offset: 0x2d N097. V00(rbx) N099. STK = LEA(b+16); rbx N101. STK = IND ; STK N103. LCL_FLD_ADDR V03 loc0 ud:2->3[+40] Fseq[Baselib] NA N105. STORE_BLK; STK N107. IL_OFFSET IL offset: 0x3a N109. V00(rbx*) N111. STK = LEA(b+112); rbx* N113. STK = IND ; STK N115. LCL_FLD_ADDR V03 loc0 ud:3->4[+0] Fseq[Tx] NA N117. STORE_BLK; STK N119. IL_OFFSET IL offset: 0x47 N121. LCL_VAR_ADDR V03 loc0 u:4 NA (last use) N123. OBJ N125. PUTARG_STK [+0x00] N127. rdi = V02 MEM N129. rdi = PUTARG_REG; rdi N131. rsi = V02 MEM N133. rsi = PUTARG_REG; rsi N135. STK = FIELD_LIST; rdi,rsi N137. rax,rdx = CALL ; STK N139. V17 MEM; rax,rdx N141. IL_OFFSET IL offset: 0x47 N143. V17 MEM N145. RETURN Var=Reg end of BB01: none *************** Finishing PHASE Linear scan register alloc *************** In genGenerateCode() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..04F) (return) i label target hascall gcsafe newobj LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Generate code *************** In fgDebugCheckBBlist Finalizing stack frame Recording Var Locations at start of BB01 V00(rbx) Modified regs: [rax rcx rdx rbx rsi rdi r8-r11 r14 mm0] Callee-saved registers pushed: 2 [rbx r14] *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT) Assign V02 arg2, size=16, stkOffs=-0x30 Assign V03 loc0, size=96, stkOffs=-0x90 Assign V17 tmp13, size=16, stkOffs=-0xa0 Assign V04 OutArgs, size=96, stkOffs=-0x100 --- delta bump 8 for RA --- delta bump 8 for FP --- delta bump 0 for RBP frame --- virtual stack offset to actual stack offset delta is 16 -- V00 was 0, now 16 -- V01 was 0, now 16 -- V02 was -48, now -32 -- V03 was -144, now -128 -- V04 was -256, now -240 -- V17 was -160, now -144 ; Final local variable assignments ; ; V00 this [V00,T01] ( 4, 4 ) byref -> rbx this ;* V01 arg1 [V01 ] ( 0, 0 ) struct (56) zero-ref do-not-enreg[S] ; V02 arg2 [V02,T00] ( 6, 6 ) struct (16) [rbp-0x20] do-not-enreg[SFA] multireg-arg ; V03 loc0 [V03,T04] ( 4, 4 ) struct (96) [rbp-0x80] do-not-enreg[SFB] must-init ld-addr-op ; V04 OutArgs [V04 ] ( 1, 1 ) lclBlk (96) [rsp+0x00] "OutgoingArgSpace" ; V05 tmp1 [V05,T02] ( 3, 6 ) ref -> r14 class-hnd exact "Single-def Box Helper" ; V06 tmp2 [V06,T03] ( 3, 6 ) ref -> rax class-hnd exact "Single-def Box Helper" ;* V07 tmp3 [V07 ] ( 0, 0 ) ref -> zero-ref class-hnd exact "Inlining Arg" ;* V08 tmp4 [V08 ] ( 0, 0 ) ref -> zero-ref class-hnd exact "Inlining Arg" ;* V09 tmp5 [V09 ] ( 0, 0 ) struct (32) zero-ref "NewObj constructor temp" ;* V10 tmp6 [V10 ] ( 0, 0 ) ref -> zero-ref class-hnd exact "Inlining Arg" ;* V11 tmp7 [V11 ] ( 0, 0 ) ref -> zero-ref class-hnd exact "Inlining Arg" ; V12 tmp8 [V12,T05] ( 2, 4 ) ref -> rsi class-hnd "Inlining Arg" ; V13 tmp9 [V13,T06] ( 2, 2 ) ref -> r14 V09._arg0(offs=0x00) P-INDEP "field V09._arg0 (fldOffset=0x0)" ; V14 tmp10 [V14,T07] ( 2, 2 ) ref -> rax V09._arg1(offs=0x08) P-INDEP "field V09._arg1 (fldOffset=0x8)" ;* V15 tmp11 [V15,T10] ( 0, 0 ) ref -> zero-ref V09._arg2(offs=0x10) P-INDEP "field V09._arg2 (fldOffset=0x10)" ; V16 tmp12 [V16,T08] ( 2, 2 ) ref -> rsi V09._args(offs=0x18) P-INDEP "field V09._args (fldOffset=0x18)" ; V17 tmp13 [V17,T09] ( 2, 2 ) struct (16) [rbp-0x90] do-not-enreg[SR] multireg-ret "Return value temp for multi-reg return (rejected tail call)." ; ; Lcl frame size = 224 Setting stack level from -572662307 to 0 =============== Generating BB01 [000..04F) (return), preds={} succs={} flags=0x00000004.408b0020: i label target hascall gcsafe newobj LIR BB01 IN (2)={V02 V00} + ByrefExposed + GcHeap OUT(0)={ } Recording Var Locations at start of BB01 V00(rbx) Change life {} -> {V00 V02} V00 in reg rbx is becoming live [------] Live regs: 00000000 {} => 00000008 {rbx} Live regs: (unchanged) 00000008 {rbx} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000008 {rbx} L_M38824_BB01: Label: IG02, GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000008 {rbx} Scope info: begin block BB01, IL range [000..04F) Scope info: open scopes = 2 (V02 arg2) [000..04F) 0 (V00 this) [000..04F) Added IP mapping: 0x0000 STACK_EMPTY (G_M38824_IG02,ins#0,ofs#0) label Generating: N003 (???,???) [000129] ------------ IL_OFFSET void IL offset: 0x0 REG NA Generating: N005 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678beb1c0 class REG rdi $180 IN0001: mov rdi, 0x7F6678BEB1C0 /--* t4 long Generating: N007 (???,???) [000137] ------------ t137 = * PUTARG_REG long REG rdi /--* t137 long arg0 in rdi Generating: N009 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG rax $200 Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000008 {rbx} IN0002: call CORINFO_HELP_NEWSFAST GC regs: 00000000 {} => 00000001 {rax} /--* t5 ref Generating: N011 ( 16, 16) [000007] DA---------- * STORE_LCL_VAR ref V05 tmp1 d:2 r14 REG r14 GC regs: 00000001 {rax} => 00000000 {} IN0003: mov r14, rax V05 in reg r14 is becoming live [000007] Live regs: 00000008 {rbx} => 00004008 {rbx r14} Live vars: {V00 V02} => {V00 V02 V05} GC regs: 00000000 {} => 00004000 {r14} Generating: N013 ( 1, 1) [000008] ------------ t8 = LCL_VAR ref V05 tmp1 u:2 r14 REG r14 $200 /--* t8 ref Generating: N015 ( 2, 2) [000010] -c---------- t10 = * LEA(b+8) byref REG NA Generating: N017 ( 3, 4) [000003] ------------ t3 = LCL_FLD int V02 arg2 u:1[+8] Fseq[Version] rdi REG rdi $2c0 IN0004: mov edi, dword ptr [V02+0x8 rbp-18H] /--* t10 byref +--* t3 int Generating: N019 (???,???) [000130] -A--GO------ * STOREIND int REG NA IN0005: mov dword ptr [r14+8], edi Generating: N021 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678c127f0 class REG rdi $182 IN0006: mov rdi, 0x7F6678C127F0 /--* t18 long Generating: N023 (???,???) [000138] ------------ t138 = * PUTARG_REG long REG rdi /--* t138 long arg0 in rdi Generating: N025 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG rax $201 Call: GCvars= {}, gcrefRegs=00004000 {r14}, byrefRegs=00000008 {rbx} IN0007: call CORINFO_HELP_NEWSFAST GC regs: 00004000 {r14} => 00004001 {rax r14} /--* t19 ref Generating: N027 ( 16, 16) [000021] DA---------- * STORE_LCL_VAR ref V06 tmp2 d:2 rax REG rax GC regs: 00004001 {rax r14} => 00004000 {r14} V06 in reg rax is becoming live [000021] Live regs: 00004008 {rbx r14} => 00004009 {rax rbx r14} Live vars: {V00 V02 V05} => {V00 V02 V05 V06} GC regs: 00004000 {r14} => 00004001 {rax r14} Generating: N029 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V06 tmp2 u:2 rax REG rax $201 /--* t22 ref Generating: N031 ( 2, 2) [000024] -c---------- t24 = * LEA(b+8) byref REG NA Generating: N033 ( 3, 4) [000017] ------------ t17 = LCL_FLD long V02 arg2 u:1[+0] Fseq[JobGroup] rsi REG rsi $300 IN0008: mov rsi, qword ptr [V02 rbp-20H] /--* t24 byref +--* t17 long Generating: N035 (???,???) [000131] -A--GO------ * STOREIND long REG NA IN0009: mov qword ptr [rax+8], rsi Generating: N037 ( 1, 1) [000013] ------------ t13 = LCL_VAR ref V05 tmp1 u:2 r14 (last use) REG r14 $200 /--* t13 ref Generating: N039 ( 11, 8) [000077] DA---------- * STORE_LCL_VAR ref V13 tmp9 d:2 r14 REG r14 V05 in reg r14 is becoming dead [000013] Live regs: 00004009 {rax rbx r14} => 00000009 {rax rbx} Live vars: {V00 V02 V05 V06} => {V00 V02 V06} GC regs: 00004001 {rax r14} => 00000001 {rax} V13 in reg r14 is becoming live [000077] Live regs: 00000009 {rax rbx} => 00004009 {rax rbx r14} Live vars: {V00 V02 V06} => {V00 V02 V06 V13} GC regs: 00000001 {rax} => 00004001 {rax r14} Generating: N041 ( 1, 1) [000027] ------------ t27 = LCL_VAR ref V06 tmp2 u:2 rax (last use) REG rax $201 /--* t27 ref Generating: N043 ( 11, 8) [000082] DA---------- * STORE_LCL_VAR ref V14 tmp10 d:2 rax REG rax V06 in reg rax is becoming dead [000027] Live regs: 00004009 {rax rbx r14} => 00004008 {rbx r14} Live vars: {V00 V02 V06 V13} => {V00 V02 V13} GC regs: 00004001 {rax r14} => 00004000 {r14} V14 in reg rax is becoming live [000082] Live regs: 00004008 {rbx r14} => 00004009 {rax rbx r14} Live vars: {V00 V02 V13} => {V00 V02 V13 V14} GC regs: 00004000 {r14} => 00004001 {rax r14} Generating: N045 ( 2, 10) [000103] ------------ t103 = CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] REG rsi $184 IN000a: mov rsi, 0x7F6663FFF340 /--* t103 long Generating: N047 ( 4, 12) [000090] n---G------- t90 = * IND ref REG rsi IN000b: mov rsi, gword ptr [rsi] GC regs: 00004001 {rax r14} => 00004041 {rax rsi r14} /--* t90 ref Generating: N049 ( 8, 15) [000092] DA--G------- * STORE_LCL_VAR ref V16 tmp12 d:2 rsi REG rsi GC regs: 00004041 {rax rsi r14} => 00004001 {rax r14} V16 in reg rsi is becoming live [000092] Live regs: 00004009 {rax rbx r14} => 00004049 {rax rbx rsi r14} Live vars: {V00 V02 V13 V14} => {V00 V02 V13 V14 V16} GC regs: 00004001 {rax r14} => 00004041 {rax rsi r14} Generating: N051 ( 3, 2) [000109] ------------ t109 = LCL_VAR ref V13 tmp9 u:2 r14 (last use) REG r14 $200 Generating: N053 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V14 tmp10 u:2 rax (last use) REG rax $201 Generating: N055 ( 1, 1) [000128] ------------ t128 = CNS_INT ref null REG rdi $VN.Null IN000c: xor rdi, rdi GC regs: 00004041 {rax rsi r14} => 000040C1 {rax rsi rdi r14} Generating: N057 ( 3, 2) [000112] ------------ t112 = LCL_VAR ref V16 tmp12 u:2 rsi (last use) REG rsi /--* t109 ref +--* t110 ref +--* t128 ref +--* t112 ref Generating: N059 ( 10, 7) [000108] -c---------- t108 = * FIELD_LIST struct REG NA $380 /--* t108 struct Generating: N061 (???,???) [000139] ------------ * PUTARG_STK [+0x00] void (4 slots) REG NA V13 in reg r14 is becoming dead [000109] Live regs: 00004049 {rax rbx rsi r14} => 00000049 {rax rbx rsi} Live vars: {V00 V02 V13 V14 V16} => {V00 V02 V14 V16} GC regs: 000040C1 {rax rsi rdi r14} => 000000C1 {rax rsi rdi} IN000d: mov gword ptr [V04 rsp], r14 V14 in reg rax is becoming dead [000110] Live regs: 00000049 {rax rbx rsi} => 00000048 {rbx rsi} Live vars: {V00 V02 V14 V16} => {V00 V02 V16} GC regs: 000000C1 {rax rsi rdi} => 000000C0 {rsi rdi} IN000e: mov gword ptr [V04+0x8 rsp+08H], rax GC regs: 000000C0 {rsi rdi} => 00000040 {rsi} IN000f: mov gword ptr [V04+0x10 rsp+10H], rdi V16 in reg rsi is becoming dead [000112] Live regs: 00000048 {rbx rsi} => 00000008 {rbx} Live vars: {V00 V02 V16} => {V00 V02} GC regs: 00000040 {rsi} => 00000000 {} IN0010: mov gword ptr [V04+0x18 rsp+18H], rsi Generating: N063 ( 2, 10) [000104] ------------ t104 = CNS_INT(h) long 0x640084D0 [ICON_STR_HDL] REG rsi $185 IN0011: mov rsi, 0x7F66640084D0 /--* t104 long Generating: N065 ( 4, 12) [000105] n---G------- t105 = * IND ref REG rsi IN0012: mov rsi, gword ptr [rsi] GC regs: 00000000 {} => 00000040 {rsi} /--* t105 ref Generating: N067 (???,???) [000140] ----G------- t140 = * PUTARG_REG ref REG rsi GC regs: 00000040 {rsi} => 00000000 {} GC regs: 00000000 {} => 00000040 {rsi} Generating: N069 ( 1, 1) [000060] ------------ t60 = CNS_INT ref null reuse reg val REG rdi $VN.Null TreeNode is marked ReuseReg /--* t60 ref Generating: N071 (???,???) [000141] ------------ t141 = * PUTARG_REG ref REG rdi GC regs: 00000040 {rsi} => 000000C0 {rsi rdi} /--* t140 ref arg1 in rsi +--* t141 ref arg0 in rdi Generating: N073 ( 32, 27) [000068] --CXG------- t68 = * CALL ref System.String.FormatHelper REG rax $1ce GC regs: 000000C0 {rsi rdi} => 00000080 {rdi} GC regs: 00000080 {rdi} => 00000000 {} Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000008 {rbx} IN0013: call System.String:FormatHelper(System.IFormatProvider,System.String,System.ParamsArray):System.String GC regs: 00000000 {} => 00000001 {rax} /--* t68 ref Generating: N075 ( 32, 27) [000099] DA-XG------- * STORE_LCL_VAR ref V12 tmp8 d:2 rsi REG rsi GC regs: 00000001 {rax} => 00000000 {} IN0014: mov rsi, rax V12 in reg rsi is becoming live [000099] Live regs: 00000008 {rbx} => 00000048 {rbx rsi} Live vars: {V00 V02} => {V00 V02 V12} GC regs: 00000000 {} => 00000040 {rsi} Generating: N077 ( 1, 1) [000096] ------------ t96 = LCL_VAR ref V12 tmp8 u:2 rsi (last use) REG rsi $1ce /--* t96 ref Generating: N079 (???,???) [000142] ------------ t142 = * PUTARG_REG ref REG rsi V12 in reg rsi is becoming dead [000096] Live regs: 00000048 {rbx rsi} => 00000008 {rbx} Live vars: {V00 V02 V12} => {V00 V02} GC regs: 00000040 {rsi} => 00000000 {} GC regs: 00000000 {} => 00000040 {rsi} Generating: N081 ( 1, 1) [000095] ------------ t95 = CNS_INT int 3 REG rdi $44 IN0015: mov edi, 3 /--* t95 int Generating: N083 (???,???) [000143] ------------ t143 = * PUTARG_REG int REG rdi /--* t142 ref arg1 in rsi +--* t143 int arg0 in rdi Generating: N085 ( 16, 9) [000097] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal REG NA $VN.Void GC regs: 00000040 {rsi} => 00000000 {} Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000008 {rbx} IN0016: call UnityEngine.Debug:ProcessAndLogInternal(int,System.Object) Added IP mapping: 0x0025 STACK_EMPTY (G_M38824_IG02,ins#22,ofs#113) Generating: N087 (???,???) [000132] ------------ IL_OFFSET void IL offset: 0x25 REG NA Generating: N089 ( 1, 1) [000034] -c---------- t34 = CNS_INT int 0 REG NA $40 Generating: N091 (???,???) [000144] Dc-----N---- t144 = LCL_VAR_ADDR byref V03 loc0 NA REG NA /--* t144 byref +--* t34 int Generating: N093 ( 5, 4) [000035] sA---------- * STORE_BLK struct (init) (Unroll) REG NA IN0017: vxorps xmm0, xmm0 IN0018: vmovdqu xmmword ptr [V03 rbp-80H], xmm0 IN0019: vmovdqu xmmword ptr [V03+0x10 rbp-70H], xmm0 IN001a: vmovdqu xmmword ptr [V03+0x20 rbp-60H], xmm0 IN001b: vmovdqu xmmword ptr [V03+0x30 rbp-50H], xmm0 IN001c: vmovdqu xmmword ptr [V03+0x40 rbp-40H], xmm0 IN001d: vmovdqu xmmword ptr [V03+0x50 rbp-30H], xmm0 Added IP mapping: 0x002D STACK_EMPTY (G_M38824_IG02,ins#29,ofs#154) Generating: N095 (???,???) [000133] ------------ IL_OFFSET void IL offset: 0x2d REG NA Generating: N097 ( 1, 1) [000038] ------------ t38 = LCL_VAR byref V00 this u:1 rbx REG rbx $80 /--* t38 byref Generating: N099 ( 3, 3) [000118] -c---------- t118 = * LEA(b+16) byref REG NA /--* t118 byref Generating: N101 ( 6, 5) [000039] *c-XG------- t39 = * IND struct REG NA Generating: N103 ( 3, 4) [000036] Uc-----N---- t36 = LCL_FLD_ADDR byref V03 loc0 ud:2->3[+40] Fseq[Baselib] NA REG NA /--* t36 byref +--* t39 struct Generating: N105 ( 9, 9) [000042] nA-XG------- * STORE_BLK struct (copy) (Unroll) REG NA G_M38824_IG02: ; offs=000000H, funclet=00, bbWeight=1 IN001e: vmovdqu xmm0, xmmword ptr [rbx+16] IN001f: vmovdqu xmmword ptr [V03+0x28 rbp-58H], xmm0 IN0020: vmovdqu xmm0, xmmword ptr [rbx+32] IN0021: vmovdqu xmmword ptr [V03+0x38 rbp-48H], xmm0 IN0022: vmovdqu xmm0, xmmword ptr [rbx+48] IN0023: vmovdqu xmmword ptr [V03+0x48 rbp-38H], xmm0 IN0024: mov rdi, qword ptr [rbx+64] IN0025: mov qword ptr [V03+0x58 rbp-28H], rdi Added IP mapping: 0x003A STACK_EMPTY (G_M38824_IG03,ins#8,ofs#44) Generating: N107 (???,???) [000134] ------------ IL_OFFSET void IL offset: 0x3a REG NA Generating: N109 ( 1, 1) [000046] ------------ t46 = LCL_VAR byref V00 this u:1 rbx (last use) REG rbx $80 /--* t46 byref Generating: N111 ( 3, 3) [000120] -c---------- t120 = * LEA(b+112) byref REG NA /--* t120 byref Generating: N113 ( 6, 5) [000047] *c--GO------ t47 = * IND struct REG NA Generating: N115 ( 3, 4) [000044] Uc-----N---- t44 = LCL_FLD_ADDR byref V03 loc0 ud:3->4[+0] Fseq[Tx] NA REG NA /--* t44 byref +--* t47 struct Generating: N117 ( 6, 7) [000050] nA--GO------ * STORE_BLK struct (copy) (Unroll) REG NA V00 in reg rbx is becoming dead [000046] Live regs: 00000008 {rbx} => 00000000 {} Live vars: {V00 V02} => {V02} Byref regs: 00000008 {rbx} => 00000000 {} G_M38824_IG03: ; offs=00009AH, funclet=00, bbWeight=1 IN0026: vmovdqu xmm0, xmmword ptr [rbx+112] IN0027: vmovdqu xmmword ptr [V03 rbp-80H], xmm0 IN0028: vmovdqu xmm0, xmmword ptr [rbx+128] IN0029: vmovdqu xmmword ptr [V03+0x10 rbp-70H], xmm0 IN002a: mov rdi, qword ptr [rbx+144] IN002b: mov qword ptr [V03+0x20 rbp-60H], rdi Added IP mapping: 0x0047 STACK_EMPTY (G_M38824_IG04,ins#6,ofs#38) Generating: N119 (???,???) [000135] ------------ IL_OFFSET void IL offset: 0x47 REG NA Generating: N121 ( 3, 2) [000052] -c-----N---- t52 = LCL_VAR_ADDR byref V03 loc0 u:4 NA (last use) REG NA /--* t52 byref Generating: N123 ( 9, 7) [000058] nc---------- t58 = * OBJ struct REG NA $388 /--* t58 struct Generating: N125 (???,???) [000145] ------------ * PUTARG_STK [+0x00] void (12 slots) (RepInstr) REG NA IN002c: lea rdi, [V04 rsp] IN002d: lea rsi, [V03 rbp-80H] IN002e: mov ecx, 5 IN002f: rep movsq IN0030: mov rcx, gword ptr [rsi] IN0031: mov gword ptr [V04+0x28 rsp+28H], rcx IN0032: add rsi, 8 IN0033: add rdi, 8 IN0034: mov ecx, 6 IN0035: rep movsq Generating: N127 ( 3, 4) [000125] ------------ t125 = LCL_FLD long V02 arg2 u:1[+0] rdi REG rdi $142 IN0036: mov rdi, qword ptr [V02 rbp-20H] /--* t125 long Generating: N129 (???,???) [000146] ------------ t146 = * PUTARG_REG long REG rdi Generating: N131 ( 3, 4) [000126] ------------ t126 = LCL_FLD long V02 arg2 u:1[+8] rsi (last use) REG rsi $143 IN0037: mov rsi, qword ptr [V02+0x8 rbp-18H] Live vars: {V02} => {} /--* t126 long Generating: N133 (???,???) [000147] ------------ t147 = * PUTARG_REG long REG rsi /--* t146 long +--* t147 long Generating: N135 ( 6, 8) [000124] -c---------- t124 = * FIELD_LIST struct REG NA $38a /--* t124 struct arg1 rdi,rsi Generating: N137 ( 32, 21) [000054] --CXG------- t54 = * CALL struct Unity.Jobs.IJobExtensions.Schedule REG rax,rdx $38b Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0038: call Unity.Jobs.IJobExtensions:Schedule(FlushSendJob,Unity.Jobs.JobHandle):Unity.Jobs.JobHandle /--* t54 struct Generating: N139 ( 36, 24) [000122] DA-XG------- * STORE_LCL_VAR struct V17 tmp13 d:2 NA REG NA IN0039: mov qword ptr [V17 rbp-90H], rax IN003a: mov qword ptr [V17+0x8 rbp-88H], rdx Live vars: {} => {V17} genIPmappingAdd: ignoring duplicate IL offset 0x47 Generating: N141 (???,???) [000136] ------------ IL_OFFSET void IL offset: 0x47 REG NA Generating: N143 ( 3, 2) [000127] -c-----N---- t127 = LCL_VAR struct V17 tmp13 u:2 NA (last use) REG NA $38e /--* t127 struct Generating: N145 ( 4, 3) [000059] ----G------- * RETURN struct REG NA $38f Live vars: {V17} => {} **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 IN003b: mov rax, qword ptr [V17 rbp-90H] IN003c: mov rdx, qword ptr [V17+0x8 rbp-88H] Scope info: end block BB01, IL range [000..04F) Scope info: ending scope, LVnum=0 [000..04F) Scope info: ending scope, LVnum=1 [000..04F) siEndScope: Failed to end scope for V01 Scope info: ending scope, LVnum=2 [000..04F) Scope info: ending scope, LVnum=3 [000..04F) Scope info: open scopes = Added IP mapping: EPILOG STACK_EMPTY (G_M38824_IG04,ins#23,ofs#119) label Reserving epilog IG for block BB01 G_M38824_IG04: ; offs=0000C6H, funclet=00, bbWeight=1 *************** After placeholder IG creation G_M38824_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M38824_IG02: ; offs=000000H, size=009AH, gcrefRegs=00000000 {}, byrefRegs=00000008 {rbx}, byref G_M38824_IG03: ; offs=00009AH, size=002CH, nogc, extend G_M38824_IG04: ; offs=0000C6H, size=0077H, extend G_M38824_IG05: ; epilog placeholder, next placeholder=, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder ; PrevGCVars= {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {} ; InitGCVars= {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000008 {rbx} Liveness not changing: {} # compCycleEstimate = 205, compSizeEstimate = 180 Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this ; Final local variable assignments ; ; V00 this [V00,T01] ( 4, 4 ) byref -> rbx this ;* V01 arg1 [V01 ] ( 0, 0 ) struct (56) zero-ref do-not-enreg[S] ; V02 arg2 [V02,T00] ( 6, 6 ) struct (16) [rbp-0x20] do-not-enreg[SFA] multireg-arg ; V03 loc0 [V03,T04] ( 4, 4 ) struct (96) [rbp-0x80] do-not-enreg[SFB] must-init ld-addr-op ; V04 OutArgs [V04 ] ( 1, 1 ) lclBlk (96) [rsp+0x00] "OutgoingArgSpace" ; V05 tmp1 [V05,T02] ( 3, 6 ) ref -> r14 class-hnd exact "Single-def Box Helper" ; V06 tmp2 [V06,T03] ( 3, 6 ) ref -> rax class-hnd exact "Single-def Box Helper" ;* V07 tmp3 [V07 ] ( 0, 0 ) ref -> zero-ref class-hnd exact "Inlining Arg" ;* V08 tmp4 [V08 ] ( 0, 0 ) ref -> zero-ref class-hnd exact "Inlining Arg" ;* V09 tmp5 [V09 ] ( 0, 0 ) struct (32) zero-ref "NewObj constructor temp" ;* V10 tmp6 [V10 ] ( 0, 0 ) ref -> zero-ref class-hnd exact "Inlining Arg" ;* V11 tmp7 [V11 ] ( 0, 0 ) ref -> zero-ref class-hnd exact "Inlining Arg" ; V12 tmp8 [V12,T05] ( 2, 4 ) ref -> rsi class-hnd "Inlining Arg" ; V13 tmp9 [V13,T06] ( 2, 2 ) ref -> r14 V09._arg0(offs=0x00) P-INDEP "field V09._arg0 (fldOffset=0x0)" ; V14 tmp10 [V14,T07] ( 2, 2 ) ref -> rax V09._arg1(offs=0x08) P-INDEP "field V09._arg1 (fldOffset=0x8)" ;* V15 tmp11 [V15,T10] ( 0, 0 ) ref -> zero-ref V09._arg2(offs=0x10) P-INDEP "field V09._arg2 (fldOffset=0x10)" ; V16 tmp12 [V16,T08] ( 2, 2 ) ref -> rsi V09._args(offs=0x18) P-INDEP "field V09._args (fldOffset=0x18)" ; V17 tmp13 [V17,T09] ( 2, 2 ) struct (16) [rbp-0x90] do-not-enreg[SR] multireg-ret "Return value temp for multi-reg return (rejected tail call)." ; ; Lcl frame size = 224 *************** Before prolog / epilog generation G_M38824_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M38824_IG02: ; offs=000000H, size=009AH, gcrefRegs=00000000 {}, byrefRegs=00000008 {rbx}, byref G_M38824_IG03: ; offs=00009AH, size=002CH, nogc, extend G_M38824_IG04: ; offs=0000C6H, size=0077H, extend G_M38824_IG05: ; epilog placeholder, next placeholder=, BB01 [0000], epilog, extend <-- First placeholder <-- Last placeholder ; PrevGCVars= {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000000 {} ; InitGCVars= {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000008 {rbx} Recording Var Locations at start of BB01 V00(rbx) *************** In genFnProlog() Added IP mapping to front: PROLOG STACK_EMPTY (G_M38824_IG01,ins#0,ofs#0) label __prolog: **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 Found 24 lvMustInit int-sized stack slots, frame offsets 128 through 32 IN003d: push rbp IN003e: push r14 IN003f: push rbx IN0040: sub rsp, 224 IN0041: vzeroupper IN0042: lea rbp, [rsp+F0H] Notify VM instruction set (AVX2) must be supported. IN0043: vxorps xmm8, xmm8 IN0044: mov rax, -96 IN0045: vmovdqa xmmword ptr [rbp+rax-20H], xmm8 IN0046: vmovdqa xmmword ptr [rbp+rax-10H], xmm8 IN0047: vmovdqa xmmword ptr [rax+rbp], xmm8 IN0048: add rax, 48 IN0049: jne SHORT -5 instr *************** In genClearStackVec3ArgUpperBits() *************** In genFnPrologCalleeRegArgs() for int regs **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 IN004a: mov qword ptr [V02 rbp-20H], rsi IN004b: mov qword ptr [V02+0x8 rbp-18H], rdx IN004c: mov rbx, rdi *************** In genEnregisterIncomingStackArgs() G_M38824_IG01: ; offs=000000H, funclet=00, bbWeight=1 *************** In genFnEpilog() __epilog: gcVarPtrSetCur= {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000008 {rbx} IN004d: lea rsp, [rbp-10H] IN004e: pop rbx IN004f: pop r14 IN0050: pop rbp IN0051: ret G_M38824_IG05: ; offs=00013DH, funclet=00, bbWeight=1 0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs *************** After prolog / epilog generation G_M38824_IG01: ; func=00, offs=000000H, size=004AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG G_M38824_IG02: ; offs=00004AH, size=009AH, gcrefRegs=00000000 {}, byrefRegs=00000008 {rbx}, byref G_M38824_IG03: ; offs=0000E4H, size=002CH, nogc, extend G_M38824_IG04: ; offs=000110H, size=0077H, extend G_M38824_IG05: ; offs=000187H, size=0009H, epilog, nogc, extend *************** In emitJumpDistBind() *************** Finishing PHASE Generate code *************** Starting PHASE Emit code Hot code size = 0x190 bytes Cold code size = 0x0 bytes reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0xe) *************** In emitEndCodeGen() Converting emitMaxStackDepth from bytes (0) to elements (0) *************************************************************************** Instructions as they come out of the scheduler G_M38824_IG01: ; func=00, offs=000000H, size=004AH, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG IN003d: 000000 55 push rbp IN003e: 000001 4156 push r14 IN003f: 000003 53 push rbx IN0040: 000004 4881ECE0000000 sub rsp, 224 IN0041: 00000B C5F877 vzeroupper IN0042: 00000E 488DAC24F0000000 lea rbp, [rsp+F0H] IN0043: 000016 C4413857C0 vxorps xmm8, xmm8 IN0044: 00001B 48B8A0FFFFFFFFFFFFFF mov rax, -96 IN0045: 000025 C5797F4405E0 vmovdqa xmmword ptr [rbp+rax-20H], xmm8 (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN0046: 00002B C5797F4405F0 vmovdqa xmmword ptr [rbp+rax-10H], xmm8 (ECS:7, ACS:6) Instruction predicted size = 7, actual = 6 IN0047: 000031 C5797F0428 vmovdqa xmmword ptr [rax+rbp], xmm8 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN0048: 000036 4883C030 add rax, 48 IN0049: 00003A 75E9 jne SHORT -5 instr IN004a: 00003C 488975E0 mov qword ptr [rbp-20H], rsi IN004b: 000040 488955E8 mov qword ptr [rbp-18H], rdx byrReg +[rbx] IN004c: 000044 488BDF mov rbx, rdi ;; bbWeight=1 PerfScore 11.83 G_M38824_IG02: ; func=00, offs=00004AH, size=009AH, gcrefRegs=00000000 {}, byrefRegs=00000008 {rbx}, byref Block predicted offs = 0000004A, actual = 00000047 -> size adj = 3 IN0001: 000047 48BFC0B1BE78667F0000 mov rdi, 0x7F6678BEB1C0 New gcrReg live regs=00000001 {rax} ; Call at 0051 [stk=0], GCvars=none, gcrefRegs=00000001 {rax}, byrefRegs=00000008 {rbx} IN0002: 000051 E86ABA6C77 call CORINFO_HELP_NEWSFAST gcrReg +[r14] IN0003: 000056 4C8BF0 mov r14, rax IN0004: 000059 8B7DE8 mov edi, dword ptr [rbp-18H] IN0005: 00005C 41897E08 mov dword ptr [r14+8], edi IN0006: 000060 48BFF027C178667F0000 mov rdi, 0x7F6678C127F0 ; Call at 006A [stk=0], GCvars=none, gcrefRegs=00004001 {rax r14}, byrefRegs=00000008 {rbx} IN0007: 00006A E851BA6C77 call CORINFO_HELP_NEWSFAST IN0008: 00006F 488B75E0 mov rsi, qword ptr [rbp-20H] IN0009: 000073 48897008 mov qword ptr [rax+8], rsi IN000a: 000077 48BE40F3FF63667F0000 mov rsi, 0x7F6663FFF340 gcrReg +[rsi] IN000b: 000081 488B36 mov rsi, gword ptr [rsi] gcrReg +[rdi] IN000c: 000084 33FF xor rdi, rdi IN000d: 000086 4C893424 mov gword ptr [rsp], r14 IN000e: 00008A 4889442408 mov gword ptr [rsp+08H], rax IN000f: 00008F 48897C2410 mov gword ptr [rsp+10H], rdi IN0010: 000094 4889742418 mov gword ptr [rsp+18H], rsi gcrReg -[rsi] IN0011: 000099 48BED0840064667F0000 mov rsi, 0x7F66640084D0 gcrReg +[rsi] IN0012: 0000A3 488B36 mov rsi, gword ptr [rsi] New gcrReg live regs=00000001 {rax} ; Call at 00A6 [stk=0], GCvars=none, gcrefRegs=00000001 {rax}, byrefRegs=00000008 {rbx} IN0013: 0000A6 E8CD7E2FFE call System.String:FormatHelper(System.IFormatProvider,System.String,System.ParamsArray):System.String gcrReg +[rsi] IN0014: 0000AB 488BF0 mov rsi, rax IN0015: 0000AE BF03000000 mov edi, 3 New gcrReg live regs=00000000 {} ; Call at 00B3 [stk=0], GCvars=none, gcrefRegs=00000000 {}, byrefRegs=00000008 {rbx} IN0016: 0000B3 E8E06AD3FE call UnityEngine.Debug:ProcessAndLogInternal(int,System.Object) IN0017: 0000B8 C5F857C0 vxorps xmm0, xmm0 (ECS:5, ACS:4) Instruction predicted size = 5, actual = 4 IN0018: 0000BC C5FA7F4580 vmovdqu xmmword ptr [rbp-80H], xmm0 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN0019: 0000C1 C5FA7F4590 vmovdqu xmmword ptr [rbp-70H], xmm0 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN001a: 0000C6 C5FA7F45A0 vmovdqu xmmword ptr [rbp-60H], xmm0 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN001b: 0000CB C5FA7F45B0 vmovdqu xmmword ptr [rbp-50H], xmm0 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN001c: 0000D0 C5FA7F45C0 vmovdqu xmmword ptr [rbp-40H], xmm0 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN001d: 0000D5 C5FA7F45D0 vmovdqu xmmword ptr [rbp-30H], xmm0 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 ;; bbWeight=1 PerfScore 24.33 G_M38824_IG03: ; func=00, offs=0000E4H, size=002CH, nogc, extend Block predicted offs = 000000E4, actual = 000000DA -> size adj = 10 IN001e: 0000DA C5FA6F4310 vmovdqu xmm0, xmmword ptr [rbx+16] (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN001f: 0000DF C5FA7F45A8 vmovdqu xmmword ptr [rbp-58H], xmm0 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN0020: 0000E4 C5FA6F4320 vmovdqu xmm0, xmmword ptr [rbx+32] (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN0021: 0000E9 C5FA7F45B8 vmovdqu xmmword ptr [rbp-48H], xmm0 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN0022: 0000EE C5FA6F4330 vmovdqu xmm0, xmmword ptr [rbx+48] (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN0023: 0000F3 C5FA7F45C8 vmovdqu xmmword ptr [rbp-38H], xmm0 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN0024: 0000F8 488B7B40 mov rdi, qword ptr [rbx+64] IN0025: 0000FC 48897DD8 mov qword ptr [rbp-28H], rdi ;; bbWeight=1 PerfScore 12.00 G_M38824_IG04: ; func=00, offs=000110H, size=0077H, extend Block predicted offs = 00000110, actual = 00000100 -> size adj = 16 IN0026: 000100 C5FA6F4370 vmovdqu xmm0, xmmword ptr [rbx+112] (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN0027: 000105 C5FA7F4580 vmovdqu xmmword ptr [rbp-80H], xmm0 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN0028: 00010A C5FA6F8380000000 vmovdqu xmm0, xmmword ptr [rbx+128] (ECS:9, ACS:8) Instruction predicted size = 9, actual = 8 IN0029: 000112 C5FA7F4590 vmovdqu xmmword ptr [rbp-70H], xmm0 (ECS:6, ACS:5) Instruction predicted size = 6, actual = 5 IN002a: 000117 488BBB90000000 mov rdi, qword ptr [rbx+144] IN002b: 00011E 48897DA0 mov qword ptr [rbp-60H], rdi IN002c: 000122 488D3C24 lea rdi, [rsp] IN002d: 000126 488D7580 lea rsi, [rbp-80H] IN002e: 00012A B905000000 mov ecx, 5 IN002f: 00012F F348A5 rep movsq gcrReg +[rcx] IN0030: 000132 488B0E mov rcx, gword ptr [rsi] IN0031: 000135 48894C2428 mov gword ptr [rsp+28H], rcx IN0032: 00013A 4883C608 add rsi, 8 IN0033: 00013E 4883C708 add rdi, 8 gcrReg -[rcx] IN0034: 000142 B906000000 mov ecx, 6 IN0035: 000147 F348A5 rep movsq IN0036: 00014A 488B7DE0 mov rdi, qword ptr [rbp-20H] IN0037: 00014E 488B75E8 mov rsi, qword ptr [rbp-18H] New byrReg live regs=00000000 {} ; Call at 0152 [stk=0], GCvars=none, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0038: 000152 E871E987FF call Unity.Jobs.IJobExtensions:Schedule(FlushSendJob,Unity.Jobs.JobHandle):Unity.Jobs.JobHandle IN0039: 000157 48898570FFFFFF mov qword ptr [rbp-90H], rax IN003a: 00015E 48899578FFFFFF mov qword ptr [rbp-88H], rdx IN003b: 000165 488B8570FFFFFF mov rax, qword ptr [rbp-90H] IN003c: 00016C 488B9578FFFFFF mov rdx, qword ptr [rbp-88H] ;; bbWeight=1 PerfScore 71.00 G_M38824_IG05: ; func=00, offs=000187H, size=0009H, epilog, nogc, extend Block predicted offs = 00000187, actual = 00000173 -> size adj = 20 IN004d: 000173 488D65F0 lea rsp, [rbp-10H] IN004e: 000177 5B pop rbx IN004f: 000178 415E pop r14 IN0050: 00017A 5D pop rbp IN0051: 00017B C3 ret ;; bbWeight=1 PerfScore 3.00Allocated method code size = 400 , actual size = 380 ; Total bytes of code 380, prolog size 60, PerfScore 162.17, (MethodHash=08be6857) for method Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this ; ============================================================ *************** After end code gen, before unwindEmit() G_M38824_IG01: ; func=00, offs=000000H, size=0047H, bbWeight=1 PerfScore 11.83, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc, isz <-- Prolog IG IN003d: 000000 push rbp IN003e: 000001 push r14 IN003f: 000003 push rbx IN0040: 000004 sub rsp, 224 IN0041: 00000B vzeroupper IN0042: 00000E lea rbp, [rsp+F0H] IN0043: 000016 vxorps xmm8, xmm8 IN0044: 00001B mov rax, -96 IN0045: 000025 vmovdqa xmmword ptr [rbp+rax-20H], xmm8 IN0046: 00002B vmovdqa xmmword ptr [rbp+rax-10H], xmm8 IN0047: 000031 vmovdqa xmmword ptr [rax+rbp], xmm8 IN0048: 000036 add rax, 48 IN0049: 00003A jne SHORT -5 instr IN004a: 00003C mov qword ptr [V02 rbp-20H], rsi IN004b: 000040 mov qword ptr [V02+0x8 rbp-18H], rdx IN004c: 000044 mov rbx, rdi G_M38824_IG02: ; offs=000047H, size=0093H, bbWeight=1 PerfScore 24.33, gcrefRegs=00000000 {}, byrefRegs=00000008 {rbx}, byref, isz IN0001: 000047 mov rdi, 0x7F6678BEB1C0 IN0002: 000051 call CORINFO_HELP_NEWSFAST IN0003: 000056 mov r14, rax IN0004: 000059 mov edi, dword ptr [V02+0x8 rbp-18H] IN0005: 00005C mov dword ptr [r14+8], edi IN0006: 000060 mov rdi, 0x7F6678C127F0 IN0007: 00006A call CORINFO_HELP_NEWSFAST IN0008: 00006F mov rsi, qword ptr [V02 rbp-20H] IN0009: 000073 mov qword ptr [rax+8], rsi IN000a: 000077 mov rsi, 0x7F6663FFF340 IN000b: 000081 mov rsi, gword ptr [rsi] IN000c: 000084 xor rdi, rdi IN000d: 000086 mov gword ptr [V04 rsp], r14 IN000e: 00008A mov gword ptr [V04+0x8 rsp+08H], rax IN000f: 00008F mov gword ptr [V04+0x10 rsp+10H], rdi IN0010: 000094 mov gword ptr [V04+0x18 rsp+18H], rsi IN0011: 000099 mov rsi, 0x7F66640084D0 IN0012: 0000A3 mov rsi, gword ptr [rsi] IN0013: 0000A6 call System.String:FormatHelper(System.IFormatProvider,System.String,System.ParamsArray):System.String IN0014: 0000AB mov rsi, rax IN0015: 0000AE mov edi, 3 IN0016: 0000B3 call UnityEngine.Debug:ProcessAndLogInternal(int,System.Object) IN0017: 0000B8 vxorps xmm0, xmm0 IN0018: 0000BC vmovdqu xmmword ptr [V03 rbp-80H], xmm0 IN0019: 0000C1 vmovdqu xmmword ptr [V03+0x10 rbp-70H], xmm0 IN001a: 0000C6 vmovdqu xmmword ptr [V03+0x20 rbp-60H], xmm0 IN001b: 0000CB vmovdqu xmmword ptr [V03+0x30 rbp-50H], xmm0 IN001c: 0000D0 vmovdqu xmmword ptr [V03+0x40 rbp-40H], xmm0 IN001d: 0000D5 vmovdqu xmmword ptr [V03+0x50 rbp-30H], xmm0 G_M38824_IG03: ; offs=0000DAH, size=0026H, bbWeight=1 PerfScore 12.00, nogc, isz, extend IN001e: 0000DA vmovdqu xmm0, xmmword ptr [rbx+16] IN001f: 0000DF vmovdqu xmmword ptr [V03+0x28 rbp-58H], xmm0 IN0020: 0000E4 vmovdqu xmm0, xmmword ptr [rbx+32] IN0021: 0000E9 vmovdqu xmmword ptr [V03+0x38 rbp-48H], xmm0 IN0022: 0000EE vmovdqu xmm0, xmmword ptr [rbx+48] IN0023: 0000F3 vmovdqu xmmword ptr [V03+0x48 rbp-38H], xmm0 IN0024: 0000F8 mov rdi, qword ptr [rbx+64] IN0025: 0000FC mov qword ptr [V03+0x58 rbp-28H], rdi G_M38824_IG04: ; offs=000100H, size=0073H, bbWeight=1 PerfScore 71.00, isz, extend IN0026: 000100 vmovdqu xmm0, xmmword ptr [rbx+112] IN0027: 000105 vmovdqu xmmword ptr [V03 rbp-80H], xmm0 IN0028: 00010A vmovdqu xmm0, xmmword ptr [rbx+128] IN0029: 000112 vmovdqu xmmword ptr [V03+0x10 rbp-70H], xmm0 IN002a: 000117 mov rdi, qword ptr [rbx+144] IN002b: 00011E mov qword ptr [V03+0x20 rbp-60H], rdi IN002c: 000122 lea rdi, [V04 rsp] IN002d: 000126 lea rsi, [V03 rbp-80H] IN002e: 00012A mov ecx, 5 IN002f: 00012F rep movsq IN0030: 000132 mov rcx, gword ptr [rsi] IN0031: 000135 mov gword ptr [V04+0x28 rsp+28H], rcx IN0032: 00013A add rsi, 8 IN0033: 00013E add rdi, 8 IN0034: 000142 mov ecx, 6 IN0035: 000147 rep movsq IN0036: 00014A mov rdi, qword ptr [V02 rbp-20H] IN0037: 00014E mov rsi, qword ptr [V02+0x8 rbp-18H] IN0038: 000152 call Unity.Jobs.IJobExtensions:Schedule(FlushSendJob,Unity.Jobs.JobHandle):Unity.Jobs.JobHandle IN0039: 000157 mov qword ptr [V17 rbp-90H], rax IN003a: 00015E mov qword ptr [V17+0x8 rbp-88H], rdx IN003b: 000165 mov rax, qword ptr [V17 rbp-90H] IN003c: 00016C mov rdx, qword ptr [V17+0x8 rbp-88H] G_M38824_IG05: ; offs=000173H, size=0009H, bbWeight=1 PerfScore 3.00, epilog, nogc, extend IN004d: 000173 lea rsp, [rbp-10H] IN004e: 000177 pop rbx IN004f: 000178 pop r14 IN0050: 00017A pop rbp IN0051: 00017B ret *************** Finishing PHASE Emit code *************** Starting PHASE Emit GC+EH tables Unwind Info: >> Start offset : 0x000000 (not in unwind data) >> End offset : 0x00017c (not in unwind data) Version : 1 Flags : 0x00 SizeOfProlog : 0x0B CountOfUnwindCodes: 5 FrameRegister : none (0) FrameOffset : N/A (no FrameRegister) (Value=0) UnwindCodes : CodeOffset: 0x0B UnwindOp: UWOP_ALLOC_LARGE (1) OpInfo: 0 - Scaled small Size: 28 * 8 = 224 = 0x000E0 CodeOffset: 0x04 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbx (3) CodeOffset: 0x03 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r14 (14) CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5) allocUnwindInfo(pHotCode=0x00007F667A84D7A0, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x17c, unwindSize=0xe, pUnwindBlock=0x0000559EA62E4D8A, funKind=0 (main function)) *************** In genIPmappingGen() IP mapping count : 7 IL offs PROLOG : 0x00000000 ( STACK_EMPTY ) IL offs 0x0000 : 0x00000047 ( STACK_EMPTY ) IL offs 0x0025 : 0x000000B8 ( STACK_EMPTY ) IL offs 0x002D : 0x000000DA ( STACK_EMPTY ) IL offs 0x003A : 0x00000100 ( STACK_EMPTY ) IL offs 0x0047 : 0x00000122 ( STACK_EMPTY ) IL offs EPILOG : 0x00000173 ( STACK_EMPTY ) *************** In genSetScopeInfo() VarLocInfo count is 5 *************** Variable debug info 5 live ranges 0( UNKNOWN) : From 00000000h to 00000047h, in rdi 1( UNKNOWN) : From 00000000h to 00000047h, in rsp[8] (1 slot) 2( UNKNOWN) : From 00000000h to 00000047h, in rsi 0( UNKNOWN) : From 00000047h to 00000100h, in rbx 2( UNKNOWN) : From 00000047h to 00000152h, in rbp[-32] (1 slot) *************** In gcInfoBlockHdrSave() Set code length to 380. **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 Set ReturnKind to Scalar. Set stack base register to rbp. Set Outgoing stack arg area size to 96. Stack slot id for offset -88 (0xffffffa8) (frame) (untracked) = 0. Register slot id for reg rbx (byref) = 1. Register slot id for reg r14 = 2. Set state of slot 1 at instr offset 0x51 to Live. Set state of slot 1 at instr offset 0x56 to Dead. Set state of slot 1 at instr offset 0x6a to Live. Set state of slot 2 at instr offset 0x6a to Live. Set state of slot 1 at instr offset 0x6f to Dead. Set state of slot 2 at instr offset 0x6f to Dead. Set state of slot 1 at instr offset 0xa6 to Live. Set state of slot 1 at instr offset 0xab to Dead. Set state of slot 1 at instr offset 0xb3 to Live. Set state of slot 1 at instr offset 0xb8 to Dead. Defining 5 call sites: Offset 0x51, size 5. Offset 0x6a, size 5. Offset 0xa6, size 5. Offset 0xb3, size 5. Offset 0x152, size 5. *************** Finishing PHASE Emit GC+EH tables Method code size: 380 Allocations for Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this (MethodHash=08be6857) count: 1656, size: 135421, max = 3072 allocateMemory: 262144, nraUsed: 140912 Alloc'd bytes by kind: kind | size | pct ---------------------+------------+-------- AssertionProp | 6460 | 4.77% ASTNode | 22112 | 16.33% InstDesc | 7728 | 5.71% ImpStack | 384 | 0.28% BasicBlock | 1696 | 1.25% fgArgInfo | 648 | 0.48% fgArgInfoPtrArr | 192 | 0.14% FlowList | 0 | 0.00% TreeStatementList | 0 | 0.00% SiScope | 432 | 0.32% DominatorMemory | 96 | 0.07% LSRA | 2908 | 2.15% LSRA_Interval | 3280 | 2.42% LSRA_RefPosition | 10432 | 7.70% Reachability | 16 | 0.01% SSA | 1168 | 0.86% ValueNumber | 14434 | 10.66% LvaTable | 4992 | 3.69% UnwindInfo | 0 | 0.00% hashBv | 40 | 0.03% bitset | 368 | 0.27% FixedBitVect | 68 | 0.05% Generic | 3442 | 2.54% LocalAddressVisitor | 0 | 0.00% FieldSeqStore | 648 | 0.48% ZeroOffsetFieldMap | 256 | 0.19% ArrayInfoMap | 40 | 0.03% MemoryPhiArg | 0 | 0.00% CSE | 2144 | 1.58% GC | 2641 | 1.95% CorTailCallInfo | 0 | 0.00% Inlining | 3880 | 2.87% ArrayStack | 0 | 0.00% DebugInfo | 384 | 0.28% DebugOnly | 39988 | 29.53% Codegen | 1184 | 0.87% LoopOpt | 0 | 0.00% LoopHoist | 0 | 0.00% Unknown | 524 | 0.39% RangeCheck | 0 | 0.00% CopyProp | 1376 | 1.02% SideEffects | 0 | 0.00% ObjectAllocator | 0 | 0.00% VariableLiveRanges | 0 | 0.00% ClassLayout | 628 | 0.46% TailMergeThrows | 0 | 0.00% EarlyProp | 0 | 0.00% ZeroInit | 832 | 0.61% ****** DONE compiling Unity.Networking.Transport.BaselibNetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this ScheduleSend: version=0 jobgroup=1942 RPCSystem: jobgroup=1968 version=0 ScheduleFlushSend: jobgroup=1968 version=0 ScheduleSend: version=0 jobgroup=1968 ScheduleSend: version=0 jobgroup=1974 RPCSystem: jobgroup=2000 version=0 ScheduleFlushSend: jobgroup=2000 version=0 ScheduleSend: version=0 jobgroup=2000 ScheduleSend: version=0 jobgroup=2006 RPCSystem: jobgroup=2032 version=0 ScheduleFlushSend: jobgroup=2032 version=0 ScheduleSend: version=0 jobgroup=2032 ScheduleSend: version=0 jobgroup=2038 RPCSystem: jobgroup=2064 version=0 ScheduleFlushSend: jobgroup=2064 version=0 ScheduleSend: version=0 jobgroup=2064 ScheduleSend: version=0 jobgroup=2070 RPCSystem: jobgroup=2096 version=0 ScheduleFlushSend: jobgroup=2096 version=0 ScheduleSend: version=0 jobgroup=2096 ScheduleSend: version=0 jobgroup=2102 RPCSystem: jobgroup=2128 version=0 ScheduleFlushSend: jobgroup=2128 version=0 ScheduleSend: version=0 jobgroup=2128 ScheduleSend: version=0 jobgroup=2134 RPCSystem: jobgroup=2160 version=0 ScheduleFlushSend: jobgroup=2160 version=0 ScheduleSend: version=0 jobgroup=2160 ScheduleSend: version=0 jobgroup=2166 RPCSystem: jobgroup=2208 version=0 ScheduleFlushSend: jobgroup=2208 version=0 ScheduleSend: version=0 jobgroup=2208 ScheduleSend: version=0 jobgroup=2214 RPCSystem: jobgroup=2240 version=0 ScheduleFlushSend: jobgroup=2240 version=0 ScheduleSend: version=0 jobgroup=2240 ScheduleSend: version=0 jobgroup=2246 RPCSystem: jobgroup=2272 version=0 ScheduleFlushSend: jobgroup=2272 version=0 ScheduleSend: version=0 jobgroup=2272 ScheduleSend: version=0 jobgroup=2278 RPCSystem: jobgroup=2304 version=0 ScheduleFlushSend: jobgroup=2304 version=0 ScheduleSend: version=0 jobgroup=2304 ScheduleSend: version=0 jobgroup=2310 RPCSystem: jobgroup=2336 version=0 ScheduleFlushSend: jobgroup=2336 version=0 ScheduleSend: version=0 jobgroup=2336 ScheduleSend: version=0 jobgroup=2342 RPCSystem: jobgroup=2368 version=0 ScheduleFlushSend: jobgroup=2368 version=0 ScheduleSend: version=0 jobgroup=2368 ScheduleSend: version=0 jobgroup=2374 RPCSystem: jobgroup=2400 version=0 ScheduleFlushSend: jobgroup=2400 version=0 ScheduleSend: version=0 jobgroup=2400 ScheduleSend: version=0 jobgroup=2406 RPCSystem: jobgroup=2432 version=0 ScheduleFlushSend: jobgroup=2432 version=0 ScheduleSend: version=0 jobgroup=2432 ScheduleSend: version=0 jobgroup=2438 RPCSystem: jobgroup=2469 version=0 ScheduleFlushSend: jobgroup=2469 version=0 ScheduleSend: version=0 jobgroup=2469 ScheduleSend: version=0 jobgroup=2475 RPCSystem: jobgroup=2501 version=0 ScheduleFlushSend: jobgroup=2501 version=0 ScheduleSend: version=0 jobgroup=2501 ScheduleSend: version=0 jobgroup=2507 RPCSystem: jobgroup=2533 version=0 ScheduleFlushSend: jobgroup=2533 version=0 ScheduleSend: version=0 jobgroup=2533 ScheduleSend: version=0 jobgroup=2539 RPCSystem: jobgroup=2565 version=0 ScheduleFlushSend: jobgroup=2565 version=0 ScheduleSend: version=0 jobgroup=2565 ScheduleSend: version=0 jobgroup=2571 RPCSystem: jobgroup=2597 version=0 ScheduleFlushSend: jobgroup=2597 version=0 ScheduleSend: version=0 jobgroup=2597 ScheduleSend: version=0 jobgroup=2603 RPCSystem: jobgroup=2629 version=0 ScheduleFlushSend: jobgroup=2629 version=0 ScheduleSend: version=0 jobgroup=2629 ScheduleSend: version=0 jobgroup=2635 RPCSystem: jobgroup=2661 version=0 ScheduleFlushSend: jobgroup=2661 version=0 ScheduleSend: version=0 jobgroup=2661 ScheduleSend: version=0 jobgroup=2667 RPCSystem: jobgroup=2693 version=0 ScheduleFlushSend: jobgroup=2693 version=0 ScheduleSend: version=0 jobgroup=2693 ScheduleSend: version=0 jobgroup=2699 RPCSystem: jobgroup=2741 version=0 ScheduleFlushSend: jobgroup=2741 version=0 ScheduleSend: version=0 jobgroup=2741 ScheduleSend: version=0 jobgroup=2747 RPCSystem: jobgroup=2773 version=0 ScheduleFlushSend: jobgroup=2773 version=0 ScheduleSend: version=0 jobgroup=2773 ScheduleSend: version=0 jobgroup=2779 RPCSystem: jobgroup=2805 version=0 ScheduleFlushSend: jobgroup=2805 version=0 ScheduleSend: version=0 jobgroup=2805 ScheduleSend: version=0 jobgroup=2811 RPCSystem: jobgroup=2837 version=0 ScheduleFlushSend: jobgroup=2837 version=0 ScheduleSend: version=0 jobgroup=2837 ScheduleSend: version=0 jobgroup=2843 RPCSystem: jobgroup=2869 version=0 ScheduleFlushSend: jobgroup=2869 version=0 ScheduleSend: version=0 jobgroup=2869 ScheduleSend: version=0 jobgroup=2875 RPCSystem: jobgroup=2901 version=0 ScheduleFlushSend: jobgroup=2901 version=0 ScheduleSend: version=0 jobgroup=2901 ScheduleSend: version=0 jobgroup=2907 RPCSystem: jobgroup=2933 version=0 ScheduleFlushSend: jobgroup=2933 version=0 ScheduleSend: version=0 jobgroup=2933 ScheduleSend: version=0 jobgroup=2939 RPCSystem: jobgroup=2965 version=0 ScheduleFlushSend: jobgroup=2965 version=0 ScheduleSend: version=0 jobgroup=2965 ScheduleSend: version=0 jobgroup=2971 RPCSystem: jobgroup=3002 version=0 ScheduleFlushSend: jobgroup=3002 version=0 ScheduleSend: version=0 jobgroup=3002 ScheduleSend: version=0 jobgroup=3008 RPCSystem: jobgroup=3034 version=0 ScheduleFlushSend: jobgroup=3034 version=0 ScheduleSend: version=0 jobgroup=3034 ScheduleSend: version=0 jobgroup=3040 RPCSystem: jobgroup=3066 version=0 ScheduleFlushSend: jobgroup=3066 version=0 ScheduleSend: version=0 jobgroup=3066 ScheduleSend: version=0 jobgroup=3072 RPCSystem: jobgroup=3098 version=0 ScheduleFlushSend: jobgroup=3098 version=0 ScheduleSend: version=0 jobgroup=3098 ScheduleSend: version=0 jobgroup=3104 RPCSystem: jobgroup=3130 version=0 ScheduleFlushSend: jobgroup=3130 version=0 ScheduleSend: version=0 jobgroup=3130 ScheduleSend: version=0 jobgroup=3136 RPCSystem: jobgroup=3162 version=0 ScheduleFlushSend: jobgroup=3162 version=0 ScheduleSend: version=0 jobgroup=3162 ScheduleSend: version=0 jobgroup=3168 RPCSystem: jobgroup=3194 version=0 ScheduleFlushSend: jobgroup=3194 version=0 ScheduleSend: version=0 jobgroup=3194 ScheduleSend: version=0 jobgroup=3200 RPCSystem: jobgroup=3226 version=0 ScheduleFlushSend: jobgroup=3226 version=0 ScheduleSend: version=0 jobgroup=3226 ScheduleSend: version=0 jobgroup=3232 RPCSystem: jobgroup=3274 version=0 ScheduleFlushSend: jobgroup=3274 version=0 ScheduleSend: version=0 jobgroup=3274 ScheduleSend: version=0 jobgroup=3280 RPCSystem: jobgroup=3306 version=0 ScheduleFlushSend: jobgroup=3306 version=0 ScheduleSend: version=0 jobgroup=3306 ScheduleSend: version=0 jobgroup=3312 RPCSystem: jobgroup=3338 version=0 ScheduleFlushSend: jobgroup=3338 version=0 ScheduleSend: version=0 jobgroup=3338 ScheduleSend: version=0 jobgroup=3344 RPCSystem: jobgroup=3370 version=0 ScheduleFlushSend: jobgroup=3370 version=0 ScheduleSend: version=0 jobgroup=3370 ScheduleSend: version=0 jobgroup=3376 RPCSystem: jobgroup=3402 version=0 ScheduleFlushSend: jobgroup=3402 version=0 ScheduleSend: version=0 jobgroup=3402 ScheduleSend: version=0 jobgroup=3408 RPCSystem: jobgroup=3434 version=0 ScheduleFlushSend: jobgroup=3434 version=0 ScheduleSend: version=0 jobgroup=3434 ****** START compiling Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this (MethodHash=853e07c9) Generating code for Unix x64 OPTIONS: Tier-1 compilation OPTIONS: compCodeOpt = FAST_CODE OPTIONS: compDbgCode = false OPTIONS: compDbgInfo = true OPTIONS: compDbgEnC = false OPTIONS: compProcedureSplitting = false OPTIONS: compProcedureSplittingEH = false IL to import: IL_0000 72 5f 11 00 70 ldstr 0x7000115F IL_0005 03 ldarg.1 IL_0006 7b 26 01 00 0a ldfld 0xA000126 IL_000b 8c 18 00 00 01 box 0x1000018 IL_0010 03 ldarg.1 IL_0011 7b 25 01 00 0a ldfld 0xA000125 IL_0016 8c 11 00 00 01 box 0x1000011 IL_001b 28 27 01 00 0a call 0xA000127 IL_0020 28 6b 00 00 0a call 0xA00006B IL_0025 7e d6 00 00 04 ldsfld 0x40000D6 IL_002a 02 ldarg.0 IL_002b 7b d7 00 00 04 ldfld 0x40000D7 IL_0030 6f 5d 01 00 0a callvirt 0xA00015D IL_0035 02 ldarg.0 IL_0036 7b d9 00 00 04 ldfld 0x40000D9 IL_003b 03 ldarg.1 IL_003c 6f c2 01 00 06 callvirt 0x60001C2 IL_0041 2a ret **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 'this' passed in register rdi **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 Arg #1 passed in register(s) firstEightByte: rsi, secondEightByte: rdx lvaGrabTemp returning 2 (V02 tmp0) (a long lifetime temp) called for OutgoingArgSpace. ; Initial local variable assignments ; ; V00 this byref this ; V01 arg1 struct ; V02 OutArgs lclBlk "OutgoingArgSpace" *************** In compInitDebuggingInfo() for Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this getVars() returned cVars = 0, extendOthers = true info.compVarScopesCount = 2 VarNum LVNum Name Beg End 0: 00h 00h V00 this 000h 042h 1: 01h 01h V01 arg1 000h 042h info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE ) *************** In fgFindBasicBlocks() for Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this Jump targets: none New Basic Block BB01 [0000] created. BB01 [000..042) IL Code Size,Instr 66, 18, Basic Block count 1, Local Variable Num,Ref count 3, 5 for method Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this OPTIONS: opts.MinOpts() == false Basic block list for 'Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Pre-import *************** Finishing PHASE Pre-import *************** Starting PHASE Importation *************** In impImport() for Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this impImportBlockPending for BB01 Importing BB01 (PC=000) of 'Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' [ 0] 0 (0x000) ldstr 7000115F [ 1] 5 (0x005) ldarg.1 [ 2] 6 (0x006) ldfld 0A000126 [ 2] 11 (0x00b) box 01000018 Compiler::impImportAndPushBox -- handling BOX(value class) via inline allocate/copy sequence lvaGrabTemp returning 3 (V03 tmp1) called for Single-def Box Helper. Marking V03 as a single def local lvaSetClass: setting class for V03 to (00007F6678C127F0) System.IntPtr [exact] STMT00000 (IL 0x000... ???) [000007] -A---------- * ASG ref [000006] D------N---- +--* LCL_VAR ref V03 tmp1 [000005] ------------ \--* ALLOCOBJ ref [000004] ------------ \--* CNS_INT(h) long 0x7f6678c127f0 class STMT00001 (IL ???... ???) [000012] -A--G------- * ASG long [000011] -------N---- +--* IND long [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V03 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ----G------- \--* FIELD long JobGroup [000002] ------------ \--* ADDR byref [000001] -------N---- \--* LCL_VAR struct V01 arg1 [ 2] 16 (0x010) ldarg.1 [ 3] 17 (0x011) ldfld 0A000125 [ 3] 22 (0x016) box 01000011 Compiler::impImportAndPushBox -- handling BOX(value class) via inline allocate/copy sequence lvaGrabTemp returning 4 (V04 tmp2) called for Single-def Box Helper. Marking V04 as a single def local lvaSetClass: setting class for V04 to (00007F6678BEB1C0) System.UInt32 [exact] STMT00002 (IL ???... ???) [000021] -A---------- * ASG ref [000020] D------N---- +--* LCL_VAR ref V04 tmp2 [000019] ------------ \--* ALLOCOBJ ref [000018] ------------ \--* CNS_INT(h) long 0x7f6678beb1c0 class STMT00003 (IL ???... ???) [000026] -A--G------- * ASG int [000025] -------N---- +--* IND int [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V04 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ----G------- \--* FIELD int Version [000016] ------------ \--* ADDR byref [000015] -------N---- \--* LCL_VAR struct V01 arg1 [ 3] 27 (0x01b) call 0A000127 In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 STMT00004 (IL ???... ???) [000029] I-C-G------- * CALL ref System.String.Format (exactContextHnd=0x00007F6678C469A9) [000000] ------------ arg0 +--* CNS_STR ref [000014] ------------ arg1 +--* BOX ref [000013] ------------ | \--* LCL_VAR ref V03 tmp1 [000028] ------------ arg2 \--* BOX ref [000027] ------------ \--* LCL_VAR ref V04 tmp2 [ 1] 32 (0x020) call 0A00006B In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 STMT00005 (IL ???... ???) [000031] I-C-G------- * CALL void UnityEngine.Debug.Log (exactContextHnd=0x00007F66798F3CD1) [000030] --C--------- arg0 \--* RET_EXPR ref (inl return from call [000029]) [ 0] 37 (0x025) ldsfld 040000D6 [ 1] 42 (0x02a) ldarg.0 [ 2] 43 (0x02b) ldfld 040000D7 [ 2] 48 (0x030) callvirt 0A00015D In Compiler::impImportCall: opcode is callvirt, kind=0, callRetType is ref, structSize is 0 STMT00006 (IL 0x025... ???) [000035] I-CXG------- * CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item (exactContextHnd=0x00007F6679BF3B09) [000032] ----G------- this in rdi +--* FIELD ref s_NetworkInterfaces [000034] ---XG------- arg1 \--* FIELD int m_NetworkInterfaceIndex [000033] ------------ \--* LCL_VAR byref V00 this [ 1] 53 (0x035) ldarg.0 [ 2] 54 (0x036) ldfld 040000D9 [ 2] 59 (0x03b) ldarg.1 [ 3] 60 (0x03c) callvirt 060001C2 (Implicit Tail call: prefixFlags |= PREFIX_TAILCALL_IMPLICIT) In Compiler::impImportCall: opcode is callvirt, kind=2, callRetType is struct, structSize is 16 Calling impNormStructVal on: [000039] ------------ * LCL_VAR struct V01 arg1 resulting tree: [000042] n----------- * OBJ struct [000041] ------------ \--* ADDR byref [000039] -------N---- \--* LCL_VAR struct V01 arg1 Calling impNormStructVal on: [000038] ---XG------- * FIELD struct m_ParallelSendQueue [000037] ------------ \--* LCL_VAR byref V00 this resulting tree: [000044] ---XG------- * OBJ struct [000043] ---XG------- \--* ADDR byref [000038] ---XG--N---- \--* FIELD struct m_ParallelSendQueue [000037] ------------ \--* LCL_VAR byref V00 this impDevirtualizeCall: Trying to devirtualize interface call: class for 'this' is Unity.Networking.Transport.INetworkInterface (attrib 00200400) base method is Unity.Networking.Transport.INetworkInterface::ScheduleSend No unique implementor of interface 00007F6679BF0D40 (Unity.Networking.Transport.INetworkInterface), sorry GTF_CALL_M_IMPLICIT_TAILCALL set for call [000040] INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' calling 'Unity.Networking.Transport.INetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 [ 1] 65 (0x041) ret impFixupStructReturnType: retyping [000040] --CXG------- * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA [000036] --C--------- this in rdi +--* RET_EXPR ref (inl return from call [000035]) [000044] ---XG------- arg1 +--* OBJ struct [000043] ---XG------- | \--* ADDR byref [000038] ---XG--N---- | \--* FIELD struct m_ParallelSendQueue [000037] ------------ | \--* LCL_VAR byref V00 this [000042] n----------- arg2 \--* OBJ struct [000041] ------------ \--* ADDR byref [000039] -------N---- \--* LCL_VAR struct V01 arg1 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 STMT00007 (IL ???... ???) [000045] --CXG------- * RETURN struct [000040] --CXG------- \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA [000036] --C--------- this in rdi +--* RET_EXPR ref (inl return from call [000035]) [000044] ---XG------- arg1 +--* OBJ struct [000043] ---XG------- | \--* ADDR byref [000038] ---XG--N---- | \--* FIELD struct m_ParallelSendQueue [000037] ------------ | \--* LCL_VAR byref V00 this [000042] n----------- arg2 \--* OBJ struct [000041] ------------ \--* ADDR byref [000039] -------N---- \--* LCL_VAR struct V01 arg1 *************** Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) (return) i newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) (return), preds={} succs={} ***** BB01 STMT00000 (IL 0x000...0x041) [000007] -A---------- * ASG ref [000006] D------N---- +--* LCL_VAR ref V03 tmp1 [000005] ------------ \--* ALLOCOBJ ref [000004] ------------ \--* CNS_INT(h) long 0x7f6678c127f0 class ***** BB01 STMT00001 (IL ???... ???) [000012] -A--G------- * ASG long [000011] -------N---- +--* IND long [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V03 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ----G------- \--* FIELD long JobGroup [000002] ------------ \--* ADDR byref [000001] -------N---- \--* LCL_VAR struct V01 arg1 ***** BB01 STMT00002 (IL ???... ???) [000021] -A---------- * ASG ref [000020] D------N---- +--* LCL_VAR ref V04 tmp2 [000019] ------------ \--* ALLOCOBJ ref [000018] ------------ \--* CNS_INT(h) long 0x7f6678beb1c0 class ***** BB01 STMT00003 (IL ???... ???) [000026] -A--G------- * ASG int [000025] -------N---- +--* IND int [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V04 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ----G------- \--* FIELD int Version [000016] ------------ \--* ADDR byref [000015] -------N---- \--* LCL_VAR struct V01 arg1 ***** BB01 STMT00004 (IL ???... ???) [000029] I-C-G------- * CALL ref System.String.Format (exactContextHnd=0x00007F6678C469A9) [000000] ------------ arg0 +--* CNS_STR ref [000014] ------------ arg1 +--* BOX ref [000013] ------------ | \--* LCL_VAR ref V03 tmp1 [000028] ------------ arg2 \--* BOX ref [000027] ------------ \--* LCL_VAR ref V04 tmp2 ***** BB01 STMT00005 (IL ???... ???) [000031] I-C-G------- * CALL void UnityEngine.Debug.Log (exactContextHnd=0x00007F66798F3CD1) [000030] --C--------- arg0 \--* RET_EXPR ref (inl return from call [000029]) ***** BB01 STMT00006 (IL 0x025... ???) [000035] I-CXG------- * CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item (exactContextHnd=0x00007F6679BF3B09) [000032] ----G------- this in rdi +--* FIELD ref s_NetworkInterfaces [000034] ---XG------- arg1 \--* FIELD int m_NetworkInterfaceIndex [000033] ------------ \--* LCL_VAR byref V00 this ***** BB01 STMT00007 (IL ???... ???) [000045] --CXG------- * RETURN struct [000040] --CXG------- \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA [000036] --C--------- this in rdi +--* RET_EXPR ref (inl return from call [000035]) [000044] ---XG------- arg1 +--* OBJ struct [000043] ---XG------- | \--* ADDR byref [000038] ---XG--N---- | \--* FIELD struct m_ParallelSendQueue [000037] ------------ | \--* LCL_VAR byref V00 this [000042] n----------- arg2 \--* OBJ struct [000041] ------------ \--* ADDR byref [000039] -------N---- \--* LCL_VAR struct V01 arg1 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Indirect call transform -- no candidates to transform *************** Finishing PHASE Indirect call transform [no changes] *************** Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Finishing PHASE Expand patchpoints [no changes] *************** Starting PHASE Post-import *************** Finishing PHASE Post-import *************** Starting PHASE Morph - Init New BlockSet epoch 1, # of blocks (including unused BB00): 2, bitset array size: 1 (short) *************** In fgRemoveEmptyBlocks *************** Finishing PHASE Morph - Init *************** In fgDebugCheckBBlist *************** Starting PHASE Morph - Inlining Expanding INLINE_CANDIDATE in statement STMT00004 in BB01: STMT00004 (IL ???... ???) [000029] I-C-G------- * CALL ref System.String.Format (exactContextHnd=0x00007F6678C469A9) [000000] ------------ arg0 +--* CNS_STR ref [000014] ------------ arg1 +--* BOX ref [000013] ------------ | \--* LCL_VAR ref V03 tmp1 [000028] ------------ arg2 \--* BOX ref [000027] ------------ \--* LCL_VAR ref V04 tmp2 Argument #0: is a constant [000000] ------------ * CNS_STR ref Argument #1: [000014] ------------ * BOX ref [000013] ------------ \--* LCL_VAR ref V03 tmp1 Argument #2: [000028] ------------ * BOX ref [000027] ------------ \--* LCL_VAR ref V04 tmp2 INLINER: inlineInfo.tokenLookupContextHandle for System.String:Format(System.String,System.Object,System.Object):System.String set to 0x00007F6678C469A9: Invoking compiler for the inlinee method System.String:Format(System.String,System.Object,System.Object):System.String : IL to import: IL_0000 14 ldnull IL_0001 02 ldarg.0 IL_0002 03 ldarg.1 IL_0003 04 ldarg.2 IL_0004 73 12 12 00 06 newobj 0x6001212 IL_0009 28 df 06 00 06 call 0x60006DF IL_000e 2a ret INLINER impTokenLookupContextHandle for System.String:Format(System.String,System.Object,System.Object):System.String is 0x00007F6678C469A9. *************** In fgFindBasicBlocks() for System.String:Format(System.String,System.Object,System.Object):System.String Jump targets: none New Basic Block BB02 [0001] created. BB02 [000..00F) Basic block list for 'System.String:Format(System.String,System.Object,System.Object):System.String' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB02 [0001] 1 1 [000..00F) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000029] Starting PHASE Pre-import *************** Inline @[000029] Finishing PHASE Pre-import *************** Inline @[000029] Starting PHASE Importation *************** In impImport() for System.String:Format(System.String,System.Object,System.Object):System.String impImportBlockPending for BB02 Importing BB02 (PC=000) of 'System.String:Format(System.String,System.Object,System.Object):System.String' [ 0] 0 (0x000) ldnull [ 1] 1 (0x001) ldarg.0 [ 2] 2 (0x002) ldarg.1 lvaGrabTemp returning 5 (V05 tmp3) called for Inlining Arg. Marked V05 as a single def temp lvaSetClass: setting class for V05 to (00007F6678C127F0) System.IntPtr [exact] [ 3] 3 (0x003) ldarg.2 lvaGrabTemp returning 6 (V06 tmp4) called for Inlining Arg. Marked V06 as a single def temp lvaSetClass: setting class for V06 to (00007F6678BEB1C0) System.UInt32 [exact] [ 4] 4 (0x004) newobj lvaGrabTemp returning 7 (V07 tmp5) called for NewObj constructor temp. Suppressing zero-init for V07 -- expect to zero in prolog 06001212 In Compiler::impImportCall: opcode is newobj, kind=0, callRetType is void, structSize is 0 [000052] I-C-G------- * CALL void System.ParamsArray..ctor (exactContextHnd=0x00007F6679A59E79) [000051] ------------ this in rdi +--* ADDR byref [000050] -------N---- | \--* LCL_VAR struct V07 tmp5 [000048] ------------ arg1 +--* LCL_VAR ref V05 tmp3 [000049] ------------ arg2 \--* LCL_VAR ref V06 tmp4 [ 3] 9 (0x009) call 060006DF In Compiler::impImportCall: opcode is call, kind=0, callRetType is ref, structSize is 0 Calling impNormStructVal on: [000053] ------------ * LCL_VAR struct V07 tmp5 resulting tree: [000056] n----------- * OBJ struct [000055] ------------ \--* ADDR byref [000053] -------N---- \--* LCL_VAR struct V07 tmp5 [000054] I-C-G------- * CALL ref System.String.FormatHelper (exactContextHnd=0x00007F6678C469A9) [000046] ------------ arg0 +--* CNS_INT ref null [000047] ------------ arg1 +--* CNS_STR ref [000056] n----------- arg2 \--* OBJ struct [000055] ------------ \--* ADDR byref [000053] -------N---- \--* LCL_VAR struct V07 tmp5 [ 1] 14 (0x00e) ret Inlinee Return expression (before normalization) => [000057] --C--------- * RET_EXPR ref (inl return from call [000054]) Inlinee Return expression (after normalization) => [000057] --C--------- * RET_EXPR ref (inl return from call [000054]) *************** Inline @[000029] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB02 [0001] 1 1 [000..00F) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB02 [000..00F) (return), preds={} succs={} ***** BB02 [000052] I-C-G------- * CALL void System.ParamsArray..ctor (exactContextHnd=0x00007F6679A59E79) [000051] ------------ this in rdi +--* ADDR byref [000050] -------N---- | \--* LCL_VAR struct V07 tmp5 [000048] ------------ arg1 +--* LCL_VAR ref V05 tmp3 [000049] ------------ arg2 \--* LCL_VAR ref V06 tmp4 ***** BB02 [000054] I-C-G------- * CALL ref System.String.FormatHelper (exactContextHnd=0x00007F6678C469A9) [000046] ------------ arg0 +--* CNS_INT ref null [000047] ------------ arg1 +--* CNS_STR ref [000056] n----------- arg2 \--* OBJ struct [000055] ------------ \--* ADDR byref [000053] -------N---- \--* LCL_VAR struct V07 tmp5 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000029] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000029] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000029] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000029] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000029] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000029] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000029] ----------- Arguments setup: Inlinee method body: STMT00008 (IL ???... ???) [000052] I-C-G------- * CALL void System.ParamsArray..ctor (exactContextHnd=0x00007F6679A59E79) [000051] ------------ this in rdi +--* ADDR byref [000050] -------N---- | \--* LCL_VAR struct V07 tmp5 [000014] ------------ arg1 +--* BOX ref [000013] ------------ | \--* LCL_VAR ref V03 tmp1 [000028] ------------ arg2 \--* BOX ref [000027] ------------ \--* LCL_VAR ref V04 tmp2 STMT00009 (IL ???... ???) [000054] I-C-G------- * CALL ref System.String.FormatHelper (exactContextHnd=0x00007F6678C469A9) [000046] ------------ arg0 +--* CNS_INT ref null [000047] ------------ arg1 +--* CNS_STR ref [000056] n----------- arg2 \--* OBJ struct [000055] ------------ \--* ADDR byref [000053] -------N---- \--* LCL_VAR struct V07 tmp5 fgInlineAppendStatements: no gc ref inline locals. Return expression for call at [000029] is [000057] --C--------- * RET_EXPR ref (inl return from call [000054]) Successfully inlined System.String:Format(System.String,System.Object,System.Object):System.String (15 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' calling 'System.String:Format(System.String,System.Object,System.Object):System.String' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement STMT00008 in BB01: STMT00008 (IL ???... ???) [000052] I-C-G------- * CALL void System.ParamsArray..ctor (exactContextHnd=0x00007F6679A59E79) [000051] ------------ this in rdi +--* ADDR byref [000050] -------N---- | \--* LCL_VAR struct V07 tmp5 [000014] ------------ arg1 +--* BOX ref [000013] ------------ | \--* LCL_VAR ref V03 tmp1 [000028] ------------ arg2 \--* BOX ref [000027] ------------ \--* LCL_VAR ref V04 tmp2 thisArg: is a constant is byref to a struct local [000051] ------------ * ADDR byref [000050] -------N---- \--* LCL_VAR struct V07 tmp5 Argument #1: [000014] ------------ * BOX ref [000013] ------------ \--* LCL_VAR ref V03 tmp1 Argument #2: [000028] ------------ * BOX ref [000027] ------------ \--* LCL_VAR ref V04 tmp2 INLINER: inlineInfo.tokenLookupContextHandle for System.ParamsArray:.ctor(System.Object,System.Object):this set to 0x00007F6679A59E79: Invoking compiler for the inlinee method System.ParamsArray:.ctor(System.Object,System.Object):this : IL to import: IL_0000 02 ldarg.0 IL_0001 03 ldarg.1 IL_0002 7d 36 04 00 04 stfld 0x4000436 IL_0007 02 ldarg.0 IL_0008 04 ldarg.2 IL_0009 7d 37 04 00 04 stfld 0x4000437 IL_000e 02 ldarg.0 IL_000f 14 ldnull IL_0010 7d 38 04 00 04 stfld 0x4000438 IL_0015 02 ldarg.0 IL_0016 7e 34 04 00 04 ldsfld 0x4000434 IL_001b 7d 39 04 00 04 stfld 0x4000439 IL_0020 2a ret INLINER impTokenLookupContextHandle for System.ParamsArray:.ctor(System.Object,System.Object):this is 0x00007F6679A59E79. *************** In fgFindBasicBlocks() for System.ParamsArray:.ctor(System.Object,System.Object):this weight= 69 : state 226 [ ldarg.0 -> ldarg.1 -> stfld ] weight= 98 : state 228 [ ldarg.0 -> ldarg.2 -> stfld ] weight= 10 : state 3 [ ldarg.0 ] weight= 7 : state 21 [ ldnull ] weight= 31 : state 111 [ stfld ] weight= 10 : state 3 [ ldarg.0 ] weight=159 : state 112 [ ldsfld ] weight= 31 : state 111 [ stfld ] weight= 19 : state 42 [ ret ] multiplier in instance constructors increased to 1.5. multiplier in methods of promotable struct increased to 4.5. Inline candidate is mostly loads and stores. Multiplier increased to 7.5. Inline candidate callsite is boring. Multiplier increased to 8.8. calleeNativeSizeEstimate=434 callsiteNativeSizeEstimate=145 benefit multiplier=8.8 threshold=1276 Native estimate for function size is within threshold for inlining 43.4 <= 127.6 (multiplier = 8.8) Jump targets: none New Basic Block BB03 [0002] created. BB03 [000..021) Basic block list for 'System.ParamsArray:.ctor(System.Object,System.Object):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB03 [0002] 1 1 [000..021) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000052] Starting PHASE Pre-import *************** Inline @[000052] Finishing PHASE Pre-import *************** Inline @[000052] Starting PHASE Importation *************** In impImport() for System.ParamsArray:.ctor(System.Object,System.Object):this impImportBlockPending for BB03 Importing BB03 (PC=000) of 'System.ParamsArray:.ctor(System.Object,System.Object):this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldarg.1 lvaGrabTemp returning 8 (V08 tmp6) called for Inlining Arg. Marked V08 as a single def temp lvaSetClass: setting class for V08 to (00007F6678C127F0) System.IntPtr [exact] [ 2] 2 (0x002) stfld 04000436 [000063] -A---------- * ASG ref [000062] -------N---- +--* FIELD ref _arg0 [000059] ------------ | \--* ADDR byref [000060] -------N---- | \--* LCL_VAR struct V07 tmp5 [000061] ------------ \--* LCL_VAR ref V08 tmp6 [ 0] 7 (0x007) ldarg.0 [ 1] 8 (0x008) ldarg.2 lvaGrabTemp returning 9 (V09 tmp7) called for Inlining Arg. Marked V09 as a single def temp lvaSetClass: setting class for V09 to (00007F6678BEB1C0) System.UInt32 [exact] [ 2] 9 (0x009) stfld 04000437 [000068] -A---------- * ASG ref [000067] -------N---- +--* FIELD ref _arg1 [000064] ------------ | \--* ADDR byref [000065] -------N---- | \--* LCL_VAR struct V07 tmp5 [000066] ------------ \--* LCL_VAR ref V09 tmp7 [ 0] 14 (0x00e) ldarg.0 [ 1] 15 (0x00f) ldnull [ 2] 16 (0x010) stfld 04000438 [000073] -A---------- * ASG ref [000072] -------N---- +--* FIELD ref _arg2 [000069] ------------ | \--* ADDR byref [000070] -------N---- | \--* LCL_VAR struct V07 tmp5 [000071] ------------ \--* CNS_INT ref null [ 0] 21 (0x015) ldarg.0 [ 1] 22 (0x016) ldsfld 04000434 [ 2] 27 (0x01b) stfld 04000439 [000078] -A--G------- * ASG ref [000077] -------N---- +--* FIELD ref _args [000074] ------------ | \--* ADDR byref [000075] -------N---- | \--* LCL_VAR struct V07 tmp5 [000076] ----G------- \--* FIELD ref s_twoArgArray [ 0] 32 (0x020) ret *************** Inline @[000052] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB03 [0002] 1 1 [000..021) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB03 [000..021) (return), preds={} succs={} ***** BB03 [000063] -A---------- * ASG ref [000062] -------N---- +--* FIELD ref _arg0 [000059] ------------ | \--* ADDR byref [000060] -------N---- | \--* LCL_VAR struct V07 tmp5 [000061] ------------ \--* LCL_VAR ref V08 tmp6 ***** BB03 [000068] -A---------- * ASG ref [000067] -------N---- +--* FIELD ref _arg1 [000064] ------------ | \--* ADDR byref [000065] -------N---- | \--* LCL_VAR struct V07 tmp5 [000066] ------------ \--* LCL_VAR ref V09 tmp7 ***** BB03 [000073] -A---------- * ASG ref [000072] -------N---- +--* FIELD ref _arg2 [000069] ------------ | \--* ADDR byref [000070] -------N---- | \--* LCL_VAR struct V07 tmp5 [000071] ------------ \--* CNS_INT ref null ***** BB03 [000078] -A--G------- * ASG ref [000077] -------N---- +--* FIELD ref _args [000074] ------------ | \--* ADDR byref [000075] -------N---- | \--* LCL_VAR struct V07 tmp5 [000076] ----G------- \--* FIELD ref s_twoArgArray ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000052] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000052] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000052] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000052] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000052] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000052] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000052] ----------- Arguments setup: Inlinee method body: STMT00010 (IL ???... ???) [000063] -A---------- * ASG ref [000062] -------N---- +--* FIELD ref _arg0 [000059] ------------ | \--* ADDR byref [000060] -------N---- | \--* LCL_VAR struct V07 tmp5 [000014] ------------ \--* BOX ref [000013] ------------ \--* LCL_VAR ref V03 tmp1 STMT00011 (IL ???... ???) [000068] -A---------- * ASG ref [000067] -------N---- +--* FIELD ref _arg1 [000064] ------------ | \--* ADDR byref [000065] -------N---- | \--* LCL_VAR struct V07 tmp5 [000028] ------------ \--* BOX ref [000027] ------------ \--* LCL_VAR ref V04 tmp2 STMT00012 (IL ???... ???) [000073] -A---------- * ASG ref [000072] -------N---- +--* FIELD ref _arg2 [000069] ------------ | \--* ADDR byref [000070] -------N---- | \--* LCL_VAR struct V07 tmp5 [000071] ------------ \--* CNS_INT ref null STMT00013 (IL ???... ???) [000078] -A--G------- * ASG ref [000077] -------N---- +--* FIELD ref _args [000074] ------------ | \--* ADDR byref [000075] -------N---- | \--* LCL_VAR struct V07 tmp5 [000076] ----G------- \--* FIELD ref s_twoArgArray fgInlineAppendStatements: no gc ref inline locals. Successfully inlined System.ParamsArray:.ctor(System.Object,System.Object):this (33 IL bytes) (depth 2) [profitable inline] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'profitable inline' for 'Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' calling 'System.ParamsArray:.ctor(System.Object,System.Object):this' INLINER: during 'fgInline' result 'success' reason 'profitable inline' Expanding INLINE_CANDIDATE in statement STMT00009 in BB01: STMT00009 (IL ???... ???) [000054] I-C-G------- * CALL ref System.String.FormatHelper (exactContextHnd=0x00007F6678C469A9) [000046] ------------ arg0 +--* CNS_INT ref null [000047] ------------ arg1 +--* CNS_STR ref [000056] n----------- arg2 \--* OBJ struct [000055] ------------ \--* ADDR byref [000053] -------N---- \--* LCL_VAR struct V07 tmp5 Argument #0: is a constant [000046] ------------ * CNS_INT ref null Argument #1: is a constant [000047] ------------ * CNS_STR ref Argument #2: [000056] n----------- * OBJ struct [000055] ------------ \--* ADDR byref [000053] -------N---- \--* LCL_VAR struct V07 tmp5 INLINER: inlineInfo.tokenLookupContextHandle for System.String:FormatHelper(System.IFormatProvider,System.String,System.ParamsArray):System.String set to 0x00007F6678C469A9: Invoking compiler for the inlinee method System.String:FormatHelper(System.IFormatProvider,System.String,System.ParamsArray):System.String : IL to import: IL_0000 03 ldarg.1 IL_0001 2d 0b brtrue.s 11 (IL_000e) IL_0003 72 d5 08 00 70 ldstr 0x700008D5 IL_0008 73 db 09 00 06 newobj 0x60009DB IL_000d 7a throw IL_000e 20 00 02 00 00 ldc.i4 0x200 IL_0013 e0 conv.u IL_0014 fe 0f localloc IL_0016 20 00 01 00 00 ldc.i4 0x100 IL_001b 73 01 00 00 0a newobj 0xA000001 IL_0020 0b stloc.1 IL_0021 12 00 ldloca.s 0x0 IL_0023 07 ldloc.1 IL_0024 28 b4 2f 00 06 call 0x6002FB4 IL_0029 12 00 ldloca.s 0x0 IL_002b 03 ldarg.1 IL_002c 6f 50 06 00 06 callvirt 0x6000650 IL_0031 0f 02 ldarga.s 0x2 IL_0033 28 15 12 00 06 call 0x6001215 IL_0038 1e ldc.i4.8 IL_0039 5a mul IL_003a 58 add IL_003b 28 b8 2f 00 06 call 0x6002FB8 IL_0040 12 00 ldloca.s 0x0 IL_0042 02 ldarg.0 IL_0043 03 ldarg.1 IL_0044 04 ldarg.2 IL_0045 28 b2 2f 00 06 call 0x6002FB2 IL_004a 12 00 ldloca.s 0x0 IL_004c fe 16 70 03 00 02 constrained. 0x2000370 IL_0052 6f 63 04 00 06 callvirt 0x6000463 IL_0057 2a ret INLINER impTokenLookupContextHandle for System.String:FormatHelper(System.IFormatProvider,System.String,System.ParamsArray):System.String is 0x00007F6678C469A9. *************** In fgFindBasicBlocks() for System.String:FormatHelper(System.IFormatProvider,System.String,System.ParamsArray):System.String weight= 16 : state 4 [ ldarg.1 ] weight= 25 : state 45 [ brtrue.s ] weight= 66 : state 102 [ ldstr ] weight=227 : state 103 [ newobj ] weight=210 : state 108 [ throw ] weight= 38 : state 33 [ ldc.i4 ] weight=-36 : state 165 [ conv.u ] weight=347 : state 176 [ localloc ] weight= 38 : state 33 [ ldc.i4 ] weight=227 : state 103 [ newobj ] weight= 34 : state 12 [ stloc.1 ] weight= 61 : state 19 [ ldloca.s ] weight= 9 : state 8 [ ldloc.1 ] weight= 79 : state 40 [ call ] weight= 61 : state 19 [ ldloca.s ] weight= 16 : state 4 [ ldarg.1 ] weight= 83 : state 99 [ callvirt ] weight= 77 : state 16 [ ldarga.s ] weight= 79 : state 40 [ call ] weight= 42 : state 31 [ ldc.i4.8 ] weight= -9 : state 78 [ mul ] weight=-12 : state 76 [ add ] weight= 79 : state 40 [ call ] weight= 61 : state 19 [ ldloca.s ] weight= 10 : state 3 [ ldarg.0 ] weight= 16 : state 4 [ ldarg.1 ] weight= 35 : state 5 [ ldarg.2 ] weight= 79 : state 40 [ call ] weight= 61 : state 19 [ ldloca.s ] weight=161 : state 190 [ constrained -> callvirt ] weight= 19 : state 42 [ ret ] Inline candidate looks like a wrapper method. Multiplier increased to 1. Inline candidate has an arg that feeds a constant test. Multiplier increased to 2. Inline candidate has const arg that feeds a conditional. Multiplier increased to 5. Inline candidate callsite is boring. Multiplier increased to 6.3. calleeNativeSizeEstimate=2199 callsiteNativeSizeEstimate=205 benefit multiplier=6.3 threshold=1291 Native estimate for function size exceeds threshold for inlining 219.9 > 129.1 (multiplier = 6.3) Inline expansion aborted, inline not profitable Inlining [000054] failed, so bashing STMT00009 to NOP INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' calling 'System.String:FormatHelper(System.IFormatProvider,System.String,System.ParamsArray):System.String' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Expanding INLINE_CANDIDATE in statement STMT00005 in BB01: STMT00005 (IL ???... ???) [000031] I-C-G------- * CALL void UnityEngine.Debug.Log (exactContextHnd=0x00007F66798F3CD1) [000030] --C--------- arg0 \--* RET_EXPR ref (inl return from call [000057]) Argument #0: has global refs has side effects [000054] --C-G------- * CALL ref System.String.FormatHelper [000046] ------------ arg0 +--* CNS_INT ref null [000047] ------------ arg1 +--* CNS_STR ref [000056] n----------- arg2 \--* OBJ struct [000055] ------------ \--* ADDR byref [000053] -------N---- \--* LCL_VAR struct V07 tmp5 INLINER: inlineInfo.tokenLookupContextHandle for UnityEngine.Debug:Log(System.Object) set to 0x00007F66798F3CD1: Invoking compiler for the inlinee method UnityEngine.Debug:Log(System.Object) : IL to import: IL_0000 19 ldc.i4.3 IL_0001 02 ldarg.0 IL_0002 28 09 00 00 06 call 0x6000009 IL_0007 2a ret INLINER impTokenLookupContextHandle for UnityEngine.Debug:Log(System.Object) is 0x00007F66798F3CD1. *************** In fgFindBasicBlocks() for UnityEngine.Debug:Log(System.Object) Jump targets: none New Basic Block BB04 [0003] created. BB04 [000..008) Basic block list for 'UnityEngine.Debug:Log(System.Object)' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB04 [0003] 1 1 [000..008) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000031] Starting PHASE Pre-import *************** Inline @[000031] Finishing PHASE Pre-import *************** Inline @[000031] Starting PHASE Importation *************** In impImport() for UnityEngine.Debug:Log(System.Object) impImportBlockPending for BB04 Importing BB04 (PC=000) of 'UnityEngine.Debug:Log(System.Object)' [ 0] 0 (0x000) ldc.i4.3 3 [ 1] 1 (0x001) ldarg.0 lvaGrabTemp returning 10 (V10 tmp8) called for Inlining Arg. Marked V10 as a single def temp lvaSetClass: setting class for V10 to (00007F6678C469A8) System.String [ 2] 2 (0x002) call 06000009 In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000083] I-C-G------- * CALL void UnityEngine.Debug.ProcessAndLogInternal (exactContextHnd=0x00007F66798F3CD1) [000081] ------------ arg0 +--* CNS_INT int 3 [000082] ------------ arg1 \--* LCL_VAR ref V10 tmp8 [ 0] 7 (0x007) ret *************** Inline @[000031] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB04 [0003] 1 1 [000..008) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB04 [000..008) (return), preds={} succs={} ***** BB04 [000083] I-C-G------- * CALL void UnityEngine.Debug.ProcessAndLogInternal (exactContextHnd=0x00007F66798F3CD1) [000081] ------------ arg0 +--* CNS_INT int 3 [000082] ------------ arg1 \--* LCL_VAR ref V10 tmp8 ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000031] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000031] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000031] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000031] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000031] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000031] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000031] ----------- Arguments setup: STMT00015 (IL ???... ???) [000085] -AC-G------- * ASG ref [000084] D------N---- +--* LCL_VAR ref V10 tmp8 [000054] --C-G------- \--* CALL ref System.String.FormatHelper [000046] ------------ arg0 +--* CNS_INT ref null [000047] ------------ arg1 +--* CNS_STR ref [000056] n----------- arg2 \--* OBJ struct [000055] ------------ \--* ADDR byref [000053] -------N---- \--* LCL_VAR struct V07 tmp5 Inlinee method body: STMT00014 (IL ???... ???) [000083] I-C-G------- * CALL void UnityEngine.Debug.ProcessAndLogInternal (exactContextHnd=0x00007F66798F3CD1) [000081] ------------ arg0 +--* CNS_INT int 3 [000082] ------------ arg1 \--* LCL_VAR ref V10 tmp8 fgInlineAppendStatements: no gc ref inline locals. Successfully inlined UnityEngine.Debug:Log(System.Object) (8 IL bytes) (depth 1) [below ALWAYS_INLINE size] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' for 'Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' calling 'UnityEngine.Debug:Log(System.Object)' INLINER: during 'fgInline' result 'success' reason 'below ALWAYS_INLINE size' Expanding INLINE_CANDIDATE in statement STMT00014 in BB01: STMT00014 (IL ???... ???) [000083] I-C-G------- * CALL void UnityEngine.Debug.ProcessAndLogInternal (exactContextHnd=0x00007F66798F3CD1) [000081] ------------ arg0 +--* CNS_INT int 3 [000082] ------------ arg1 \--* LCL_VAR ref V10 tmp8 Argument #0: is a constant [000081] ------------ * CNS_INT int 3 Argument #1: is a local var [000082] ------------ * LCL_VAR ref V10 tmp8 INLINER: inlineInfo.tokenLookupContextHandle for UnityEngine.Debug:ProcessAndLogInternal(int,System.Object) set to 0x00007F66798F3CD1: Invoking compiler for the inlinee method UnityEngine.Debug:ProcessAndLogInternal(int,System.Object) : IL to import: IL_0000 03 ldarg.1 IL_0001 12 00 ldloca.s 0x0 IL_0003 12 01 ldloca.s 0x1 IL_0005 28 08 00 00 06 call 0x6000008 IL_000a 02 ldarg.0 IL_000b 06 ldloc.0 IL_000c 28 24 00 00 06 call 0x6000024 IL_0011 07 ldloc.1 IL_0012 02 ldarg.0 IL_0013 28 cb 01 00 06 call 0x60001CB IL_0018 06 ldloc.0 IL_0019 28 0f 00 00 0a call 0xA00000F IL_001e 2a ret INLINER impTokenLookupContextHandle for UnityEngine.Debug:ProcessAndLogInternal(int,System.Object) is 0x00007F66798F3CD1. *************** In fgFindBasicBlocks() for UnityEngine.Debug:ProcessAndLogInternal(int,System.Object) weight= 16 : state 4 [ ldarg.1 ] weight= 61 : state 19 [ ldloca.s ] weight= 61 : state 19 [ ldloca.s ] weight= 79 : state 40 [ call ] weight= 10 : state 3 [ ldarg.0 ] weight= 12 : state 7 [ ldloc.0 ] weight= 79 : state 40 [ call ] weight= 9 : state 8 [ ldloc.1 ] weight= 10 : state 3 [ ldarg.0 ] weight= 79 : state 40 [ call ] weight= 12 : state 7 [ ldloc.0 ] weight= 79 : state 40 [ call ] weight= 19 : state 42 [ ret ] Inline candidate looks like a wrapper method. Multiplier increased to 1. Inline candidate callsite is boring. Multiplier increased to 2.3. calleeNativeSizeEstimate=526 callsiteNativeSizeEstimate=115 benefit multiplier=2.3 threshold=264 Native estimate for function size exceeds threshold for inlining 52.6 > 26.4 (multiplier = 2.3) Inline expansion aborted, inline not profitable INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' for 'Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' calling 'UnityEngine.Debug:ProcessAndLogInternal(int,System.Object)' INLINER: during 'fgInline' result 'failed this call site' reason 'unprofitable inline' Expanding INLINE_CANDIDATE in statement STMT00006 in BB01: STMT00006 (IL 0x025... ???) [000035] I-CXG------- * CALL nullcheck ref System.Collections.Generic.List`1[__Canon][System.__Canon].get_Item (exactContextHnd=0x00007F6679BF3B09) [000032] ----G------- this in rdi +--* FIELD ref s_NetworkInterfaces [000034] ---XG------- arg1 \--* FIELD int m_NetworkInterfaceIndex [000033] ------------ \--* LCL_VAR byref V00 this thisArg: has global refs [000032] ----G------- * FIELD ref s_NetworkInterfaces Argument #1: has global refs has side effects [000034] ---XG------- * FIELD int m_NetworkInterfaceIndex [000033] ------------ \--* LCL_VAR byref V00 this INLINER: inlineInfo.tokenLookupContextHandle for System.Collections.Generic.List`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this set to 0x00007F6679BF3B09: Invoking compiler for the inlinee method System.Collections.Generic.List`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this : IL to import: IL_0000 03 ldarg.1 IL_0001 02 ldarg.0 IL_0002 7b 3e 0c 00 0a ldfld 0xA000C3E IL_0007 37 05 blt.un.s 5 (IL_000e) IL_0009 28 ab 17 00 06 call 0x60017AB IL_000e 02 ldarg.0 IL_000f 7b 3d 0c 00 0a ldfld 0xA000C3D IL_0014 03 ldarg.1 IL_0015 a3 18 00 00 1b ldelem 0x1B000018 IL_001a 2a ret INLINER impTokenLookupContextHandle for System.Collections.Generic.List`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this is 0x00007F6679BF3B09. *************** In fgFindBasicBlocks() for System.Collections.Generic.List`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this weight= 16 : state 4 [ ldarg.1 ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight=-63 : state 55 [ blt.un.s ] weight= 79 : state 40 [ call ] weight= 31 : state 191 [ ldarg.0 -> ldfld ] weight= 16 : state 4 [ ldarg.1 ] weight= 65 : state 140 [ ldelem ] weight= 19 : state 42 [ ret ] Inline candidate is mostly loads and stores. Multiplier increased to 3. Inline candidate callsite is boring. Multiplier increased to 4.3. calleeNativeSizeEstimate=194 callsiteNativeSizeEstimate=115 benefit multiplier=4.3 threshold=494 Native estimate for function size is within threshold for inlining 19.4 <= 49.4 (multiplier = 4.3) Jump targets: IL_000e New Basic Block BB05 [0004] created. BB05 [000..009) New Basic Block BB06 [0005] created. BB06 [009..00E) New Basic Block BB07 [0006] created. BB07 [00E..01B) Basic block list for 'System.Collections.Generic.List`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB05 [0004] 1 1 [000..009)-> BB07 ( cond ) BB06 [0005] 1 1 [009..00E) BB07 [0006] 2 1 [00E..01B) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Inline @[000035] Starting PHASE Pre-import *************** Inline @[000035] Finishing PHASE Pre-import *************** Inline @[000035] Starting PHASE Importation *************** In impImport() for System.Collections.Generic.List`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this impImportBlockPending for BB05 Importing BB05 (PC=000) of 'System.Collections.Generic.List`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this' [ 0] 0 (0x000) ldarg.1 lvaGrabTemp returning 11 (V11 tmp9) called for Inlining Arg. [ 1] 1 (0x001) ldarg.0 lvaGrabTemp returning 12 (V12 tmp10) called for Inlining Arg. Marked V12 as a single def temp Querying runtime about current class of field Unity.Networking.Transport.NetworkDriver.s_NetworkInterfaces (declared as System.Collections.Generic.List`1[[Unity.Networking.Transport.INetworkInterface, Unity.Networking.Transport, Version=0.0.0.0, Culture=neutral, PublicKeyToken=null]]) Field's current class not available lvaSetClass: setting class for V12 to (00007F6679BF3B08) System.Collections.Generic.List`1[[Unity.Networking.Transport.INetworkInterface, Unity.Networking.Transport, Version=0.0.0.0, Culture=neutral, PublicKeyToken=null]] [ 2] 2 (0x002) ldfld 0A000C3E [ 2] 7 (0x007) blt.un.s [000091] ---XG------- * JTRUE void [000090] N--XG----U-- \--* LT int [000087] ------------ +--* LCL_VAR int V11 tmp9 [000089] ---XG------- \--* FIELD int _size [000088] ------------ \--* LCL_VAR ref V12 tmp10 impImportBlockPending for BB06 impImportBlockPending for BB07 Importing BB07 (PC=014) of 'System.Collections.Generic.List`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this' [ 0] 14 (0x00e) ldarg.0 [ 1] 15 (0x00f) ldfld 0A000C3D [ 1] 20 (0x014) ldarg.1 [ 2] 21 (0x015) ldelem 1B000018 [ 1] 26 (0x01a) ret Inlinee Return expression (before normalization) => [000095] ---XG------- * INDEX ref [000093] ---XG------- +--* FIELD ref _items [000092] ------------ | \--* LCL_VAR ref V12 tmp10 [000094] ------------ \--* LCL_VAR int V11 tmp9 Inlinee Return expression (after normalization) => [000095] ---XG------- * INDEX ref [000093] ---XG------- +--* FIELD ref _items [000092] ------------ | \--* LCL_VAR ref V12 tmp10 [000094] ------------ \--* LCL_VAR int V11 tmp9 Importing BB06 (PC=009) of 'System.Collections.Generic.List`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this' [ 0] 9 (0x009) call 060017AB In Compiler::impImportCall: opcode is call, kind=0, callRetType is void, structSize is 0 [000096] I-C-G------- * CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException (exactContextHnd=0x00007F66793893D9) impImportBlockPending for BB07 ** Note: inlinee IL was partially imported -- imported 14 of 27 bytes of method IL *************** Inline @[000035] Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB05 [0004] 1 1 [000..009)-> BB07 ( cond ) i BB06 [0005] 1 1 [009..00E) i BB07 [0006] 2 1 [00E..01B) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB05 [000..009) -> BB07 (cond), preds={} succs={BB06,BB07} ***** BB05 [000091] ---XG------- * JTRUE void [000090] N--XG----U-- \--* LT int [000087] ------------ +--* LCL_VAR int V11 tmp9 [000089] ---XG------- \--* FIELD int _size [000088] ------------ \--* LCL_VAR ref V12 tmp10 ------------ BB06 [009..00E), preds={} succs={BB07} ***** BB06 [000096] I-C-G------- * CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException (exactContextHnd=0x00007F66793893D9) ------------ BB07 [00E..01B) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Inline @[000035] Starting PHASE Indirect call transform -- no candidates to transform *************** Inline @[000035] Finishing PHASE Indirect call transform [no changes] *************** Inline @[000035] Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Inline @[000035] Finishing PHASE Expand patchpoints [no changes] *************** Inline @[000035] Starting PHASE Post-import *************** In fgRemoveEmptyBlocks *************** Inline @[000035] Finishing PHASE Post-import ----------- Statements (and blocks) added due to the inlining of call [000035] ----------- Arguments setup: STMT00018 (IL 0x025... ???) [000098] -A--G------- * ASG ref [000097] D------N---- +--* LCL_VAR ref V12 tmp10 [000032] ----G------- \--* FIELD ref s_NetworkInterfaces STMT00019 (IL 0x025... ???) [000100] -A-XG------- * ASG int [000099] D------N---- +--* LCL_VAR int V11 tmp9 [000034] ---XG------- \--* FIELD int m_NetworkInterfaceIndex [000033] ------------ \--* LCL_VAR byref V00 this Inlinee method body:New Basic Block BB08 [0007] created. Convert bbJumpKind of BB07 to BBJ_NONE fgInlineAppendStatements: no gc ref inline locals. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB05 [0004] 1 1 [025..026)-> BB07 ( cond ) i BB06 [0005] 1 0.50 [025..026) i BB07 [0006] 2 1 [025..026) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB05 [025..026) -> BB07 (cond), preds={} succs={BB06,BB07} ***** BB05 STMT00016 (IL 0x025... ???) [000091] ---XG------- * JTRUE void [000090] N--XG----U-- \--* LT int [000087] ------------ +--* LCL_VAR int V11 tmp9 [000089] ---XG------- \--* FIELD int _size [000088] ------------ \--* LCL_VAR ref V12 tmp10 ------------ BB06 [025..026), preds={} succs={BB07} ***** BB06 STMT00017 (IL 0x025... ???) [000096] I-C-G------- * CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException (exactContextHnd=0x00007F66793893D9) ------------ BB07 [025..026), preds={} succs={BB08} ------------------------------------------------------------------------------------------------------------------- Return expression for call at [000035] is [000095] ---XG------- * INDEX ref [000093] ---XG------- +--* FIELD ref _items [000092] ------------ | \--* LCL_VAR ref V12 tmp10 [000094] ------------ \--* LCL_VAR int V11 tmp9 Successfully inlined System.Collections.Generic.List`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this (27 IL bytes) (depth 1) [profitable inline] -------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'success' reason 'profitable inline' for 'Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' calling 'System.Collections.Generic.List`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this' INLINER: during 'fgInline' result 'success' reason 'profitable inline' Querying runtime about current class of field Unity.Networking.Transport.NetworkDriver.s_NetworkInterfaces (declared as System.Collections.Generic.List`1[[Unity.Networking.Transport.INetworkInterface, Unity.Networking.Transport, Version=0.0.0.0, Culture=neutral, PublicKeyToken=null]]) Field's current class not available Expanding INLINE_CANDIDATE in statement STMT00017 in BB06: STMT00017 (IL 0x025... ???) [000096] I-C-G------- * CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException (exactContextHnd=0x00007F66793893D9) INLINER: inlineInfo.tokenLookupContextHandle for System.ThrowHelper:ThrowArgumentOutOfRange_IndexException() set to 0x00007F66793893D9: Invoking compiler for the inlinee method System.ThrowHelper:ThrowArgumentOutOfRange_IndexException() : IL to import: IL_0000 1f 15 ldc.i4.s 0x15 IL_0002 16 ldc.i4.0 IL_0003 28 e0 17 00 06 call 0x60017E0 IL_0008 7a throw INLINER impTokenLookupContextHandle for System.ThrowHelper:ThrowArgumentOutOfRange_IndexException() is 0x00007F66793893D9. *************** In fgFindBasicBlocks() for System.ThrowHelper:ThrowArgumentOutOfRange_IndexException() Jump targets: none New Basic Block BB09 [0008] created. BB09 [000..009) Basic block list for 'System.ThrowHelper:ThrowArgumentOutOfRange_IndexException()' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB09 [0008] 1 0 [000..009) (throw ) rare ----------------------------------------------------------------------------------------------------------------------------------------- INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' for 'Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' calling 'System.ThrowHelper:ThrowArgumentOutOfRange_IndexException()' INLINER: during 'fgInline' result 'failed this callee' reason 'does not return' Replacing the return expression placeholder [000036] with [000095] [000036] --C--------- * RET_EXPR ref (inl return from call [000095]) Inserting the inline return expression [000095] ---XG------- * INDEX ref [000093] ---XG------- +--* FIELD ref _items [000092] ------------ | \--* LCL_VAR ref V12 tmp10 [000094] ------------ \--* LCL_VAR int V11 tmp9 **** Late devirt opportunity [000040] --CXG------- * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA [000095] ---XG------- this in rdi +--* INDEX ref [000093] ---XG------- | +--* FIELD ref _items [000092] ------------ | | \--* LCL_VAR ref V12 tmp10 [000094] ------------ | \--* LCL_VAR int V11 tmp9 [000044] ---XG------- arg1 +--* OBJ struct [000043] ---XG------- | \--* ADDR byref [000038] ---XG--N---- | \--* FIELD struct m_ParallelSendQueue [000037] ------------ | \--* LCL_VAR byref V00 this [000042] n----------- arg2 \--* OBJ struct [000041] ------------ \--* ADDR byref [000039] -------N---- \--* LCL_VAR struct V01 arg1 Querying runtime about current class of field System.Collections.Generic.List`1[System.__Canon]._items (declared as System.__Canon[]) Field's current class not available impDevirtualizeCall: Trying to devirtualize interface call: class for 'this' is System.__Canon (attrib 20020000) base method is Unity.Networking.Transport.INetworkInterface::ScheduleSend --- base class is interface --- no derived method, sorry **************** Inline Tree Inlines into 06000149 Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this [1 IL=0027 TR=000029 060006D8] [below ALWAYS_INLINE size] System.String:Format(System.String,System.Object,System.Object):System.String [2 IL=0004 TR=000052 06001212] [profitable inline] System.ParamsArray:.ctor(System.Object,System.Object):this [0 IL=0009 TR=000054 060006DF] [FAILED: unprofitable inline] System.String:FormatHelper(System.IFormatProvider,System.String,System.ParamsArray):System.String [3 IL=0032 TR=000031 0600000A] [below ALWAYS_INLINE size] UnityEngine.Debug:Log(System.Object) [0 IL=0002 TR=000083 06000009] [FAILED: unprofitable inline] UnityEngine.Debug:ProcessAndLogInternal(int,System.Object) [0 IL=0009 TR=000054 060006DF] [FAILED: unprofitable inline] System.String:FormatHelper(System.IFormatProvider,System.String,System.ParamsArray):System.String [4 IL=0048 TR=000035 0600606C] [profitable inline] System.Collections.Generic.List`1[__Canon][System.__Canon]:get_Item(int):System.__Canon:this [0 IL=0009 TR=000096 060017AB] [FAILED: does not return] System.ThrowHelper:ThrowArgumentOutOfRange_IndexException() [0 IL=0060 TR=000040 060001C2] [FAILED: target not direct] Unity.Networking.Transport.INetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this Budget: initialTime=258, finalTime=342, initialBudget=2580, currentBudget=2580 Budget: initialSize=1636, finalSize=2004 *************** Finishing PHASE Morph - Inlining Trees after Morph - Inlining ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) i newobj BB05 [0004] 1 1 [025..026)-> BB07 ( cond ) i BB06 [0005] 1 0.50 [025..026) i BB07 [0006] 2 1 [025..026) i BB08 [0007] 1 1 [???..???) (return) internal newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042), preds={} succs={BB05} ***** BB01 STMT00000 (IL 0x000...0x041) [000007] -A---------- * ASG ref [000006] D------N---- +--* LCL_VAR ref V03 tmp1 [000005] ------------ \--* ALLOCOBJ ref [000004] ------------ \--* CNS_INT(h) long 0x7f6678c127f0 class ***** BB01 STMT00001 (IL ???... ???) [000012] -A--G------- * ASG long [000011] -------N---- +--* IND long [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V03 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ----G------- \--* FIELD long JobGroup [000002] ------------ \--* ADDR byref [000001] -------N---- \--* LCL_VAR struct V01 arg1 ***** BB01 STMT00002 (IL ???... ???) [000021] -A---------- * ASG ref [000020] D------N---- +--* LCL_VAR ref V04 tmp2 [000019] ------------ \--* ALLOCOBJ ref [000018] ------------ \--* CNS_INT(h) long 0x7f6678beb1c0 class ***** BB01 STMT00003 (IL ???... ???) [000026] -A--G------- * ASG int [000025] -------N---- +--* IND int [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V04 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ----G------- \--* FIELD int Version [000016] ------------ \--* ADDR byref [000015] -------N---- \--* LCL_VAR struct V01 arg1 ***** BB01 STMT00010 (IL ???... ???) [000063] -A---------- * ASG ref [000062] -------N---- +--* FIELD ref _arg0 [000059] ------------ | \--* ADDR byref [000060] -------N---- | \--* LCL_VAR struct V07 tmp5 [000014] ------------ \--* BOX ref [000013] ------------ \--* LCL_VAR ref V03 tmp1 ***** BB01 STMT00011 (IL ???... ???) [000068] -A---------- * ASG ref [000067] -------N---- +--* FIELD ref _arg1 [000064] ------------ | \--* ADDR byref [000065] -------N---- | \--* LCL_VAR struct V07 tmp5 [000028] ------------ \--* BOX ref [000027] ------------ \--* LCL_VAR ref V04 tmp2 ***** BB01 STMT00012 (IL ???... ???) [000073] -A---------- * ASG ref [000072] -------N---- +--* FIELD ref _arg2 [000069] ------------ | \--* ADDR byref [000070] -------N---- | \--* LCL_VAR struct V07 tmp5 [000071] ------------ \--* CNS_INT ref null ***** BB01 STMT00013 (IL ???... ???) [000078] -A--G------- * ASG ref [000077] -------N---- +--* FIELD ref _args [000074] ------------ | \--* ADDR byref [000075] -------N---- | \--* LCL_VAR struct V07 tmp5 [000076] ----G------- \--* FIELD ref s_twoArgArray ***** BB01 STMT00015 (IL ???... ???) [000085] -AC-G------- * ASG ref [000084] D------N---- +--* LCL_VAR ref V10 tmp8 [000054] --C-G------- \--* CALL ref System.String.FormatHelper [000046] ------------ arg0 +--* CNS_INT ref null [000047] ------------ arg1 +--* CNS_STR ref [000056] n----------- arg2 \--* OBJ struct [000055] ------------ \--* ADDR byref [000053] -------N---- \--* LCL_VAR struct V07 tmp5 ***** BB01 STMT00014 (IL ???... ???) [000083] --C-G------- * CALL void UnityEngine.Debug.ProcessAndLogInternal [000081] ------------ arg0 +--* CNS_INT int 3 [000082] ------------ arg1 \--* LCL_VAR ref V10 tmp8 ***** BB01 STMT00018 (IL 0x025... ???) [000098] -A--G------- * ASG ref [000097] D------N---- +--* LCL_VAR ref V12 tmp10 [000032] ----G------- \--* FIELD ref s_NetworkInterfaces ***** BB01 STMT00019 (IL 0x025... ???) [000100] -A-XG------- * ASG int [000099] D------N---- +--* LCL_VAR int V11 tmp9 [000034] ---XG------- \--* FIELD int m_NetworkInterfaceIndex [000033] ------------ \--* LCL_VAR byref V00 this ------------ BB05 [025..026) -> BB07 (cond), preds={} succs={BB06,BB07} ***** BB05 STMT00016 (IL 0x025... ???) [000091] ---XG------- * JTRUE void [000090] N--XG----U-- \--* LT int [000087] ------------ +--* LCL_VAR int V11 tmp9 [000089] ---XG------- \--* FIELD int _size [000088] ------------ \--* LCL_VAR ref V12 tmp10 ------------ BB06 [025..026), preds={} succs={BB07} ***** BB06 STMT00017 (IL 0x025... ???) [000096] --C-G------- * CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException ------------ BB07 [025..026), preds={} succs={BB08} ------------ BB08 [???..???) (return), preds={} succs={} ***** BB08 STMT00007 (IL ???... ???) [000045] --CXG------- * RETURN struct [000040] --CXG------- \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA [000095] ---XG------- this in rdi +--* INDEX ref [000093] ---XG------- | +--* FIELD ref _items [000092] ------------ | | \--* LCL_VAR ref V12 tmp10 [000094] ------------ | \--* LCL_VAR int V11 tmp9 [000044] ---XG------- arg1 +--* OBJ struct [000043] ---XG------- | \--* ADDR byref [000038] ---XG--N---- | \--* FIELD struct m_ParallelSendQueue [000037] ------------ | \--* LCL_VAR byref V00 this [000042] n----------- arg2 \--* OBJ struct [000041] ------------ \--* ADDR byref [000039] -------N---- \--* LCL_VAR struct V01 arg1 ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Allocate Objects disabled, punting *************** Finishing PHASE Allocate Objects [no changes] *************** Starting PHASE Morph - Add internal blocks *************** After fgAddInternal() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) i newobj BB05 [0004] 1 1 [025..026)-> BB07 ( cond ) i BB06 [0005] 1 0.50 [025..026) i BB07 [0006] 2 1 [025..026) i BB08 [0007] 1 1 [???..???) (return) internal newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** Finishing PHASE Morph - Add internal blocks *************** Starting PHASE Remove empty try *************** In fgRemoveEmptyTry() No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty try [no changes] *************** Starting PHASE Remove empty finally No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty finally [no changes] *************** Starting PHASE Merge callfinally chains No EH in this method, nothing to merge. *************** Finishing PHASE Merge callfinally chains [no changes] *************** Starting PHASE Clone finally No EH in this method, no cloning. *************** Finishing PHASE Clone finally [no changes] *************** Starting PHASE Compute preds Renumbering the basic blocks for fgComputePred *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) i newobj BB05 [0004] 1 1 [025..026)-> BB07 ( cond ) i BB06 [0005] 1 0.50 [025..026) i BB07 [0006] 2 1 [025..026) i BB08 [0007] 1 1 [???..???) (return) internal newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB05 to BB02 Renumber BB06 to BB03 Renumber BB07 to BB04 Renumber BB08 to BB05 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) i newobj BB02 [0004] 1 1 [025..026)-> BB04 ( cond ) i BB03 [0005] 1 0.50 [025..026) i BB04 [0006] 2 1 [025..026) i BB05 [0007] 1 1 [???..???) (return) internal newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 2, # of blocks (including unused BB00): 6, bitset array size: 1 (short) *************** In fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) i newobj BB02 [0004] 1 1 [025..026)-> BB04 ( cond ) i BB03 [0005] 1 0.50 [025..026) i BB04 [0006] 2 1 [025..026) i BB05 [0007] 1 1 [???..???) (return) internal newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** After fgComputePreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) i label target newobj BB02 [0004] 1 BB01 1 [025..026)-> BB04 ( cond ) i BB03 [0005] 1 BB02 0.50 [025..026) i BB04 [0006] 2 BB02,BB03 1 [025..026) i label target BB05 [0007] 1 BB04 1 [???..???) (return) internal newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Compute preds *************** Starting PHASE Merge throw blocks *************** In fgTailMergeThrows Method does not have multiple noreturn calls. *************** Finishing PHASE Merge throw blocks [no changes] *************** Starting PHASE Update flow graph early pass *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042) i label target newobj BB02 [0004] 1 BB01 1 [025..026)-> BB04 ( cond ) i BB03 [0005] 1 BB02 0.50 [025..026) i BB04 [0006] 2 BB02,BB03 1 [025..026) i label target BB05 [0007] 1 BB04 1 [???..???) (return) internal newobj ----------------------------------------------------------------------------------------------------------------------------------------- Compacting blocks BB01 and BB02: *************** In fgDebugCheckBBlist Compacting blocks BB04 and BB05: *************** In fgDebugCheckBBlist After updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB04 ( cond ) i label target newobj BB03 [0005] 1 BB01 0.50 [025..026) i BB04 [0006] 2 BB01,BB03 1 [025..026) (return) i label target newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** Finishing PHASE Update flow graph early pass *************** Starting PHASE Morph - Promote Structs *************** In fgPromoteStructs() lvaTable before fgPromoteStructs ; Initial local variable assignments ; ; V00 this byref this ; V01 arg1 struct ; V02 OutArgs lclBlk "OutgoingArgSpace" ; V03 tmp1 ref class-hnd exact "Single-def Box Helper" ; V04 tmp2 ref class-hnd exact "Single-def Box Helper" ; V05 tmp3 ref class-hnd exact "Inlining Arg" ; V06 tmp4 ref class-hnd exact "Inlining Arg" ; V07 tmp5 struct "NewObj constructor temp" ; V08 tmp6 ref class-hnd exact "Inlining Arg" ; V09 tmp7 ref class-hnd exact "Inlining Arg" ; V10 tmp8 ref class-hnd "Inlining Arg" ; V11 tmp9 int "Inlining Arg" ; V12 tmp10 ref class-hnd "Inlining Arg" Not promoting promotable struct local V01, because lvIsParam is true and #fields = 2. Promoting struct local V07 (System.ParamsArray): lvaGrabTemp returning 13 (V13 tmp11) (a long lifetime temp) called for field V07._arg0 (fldOffset=0x0). lvaGrabTemp returning 14 (V14 tmp12) (a long lifetime temp) called for field V07._arg1 (fldOffset=0x8). lvaGrabTemp returning 15 (V15 tmp13) (a long lifetime temp) called for field V07._arg2 (fldOffset=0x10). lvaGrabTemp returning 16 (V16 tmp14) (a long lifetime temp) called for field V07._args (fldOffset=0x18). lvaTable after fgPromoteStructs ; Initial local variable assignments ; ; V00 this byref this ; V01 arg1 struct ; V02 OutArgs lclBlk "OutgoingArgSpace" ; V03 tmp1 ref class-hnd exact "Single-def Box Helper" ; V04 tmp2 ref class-hnd exact "Single-def Box Helper" ; V05 tmp3 ref class-hnd exact "Inlining Arg" ; V06 tmp4 ref class-hnd exact "Inlining Arg" ; V07 tmp5 struct "NewObj constructor temp" ; V08 tmp6 ref class-hnd exact "Inlining Arg" ; V09 tmp7 ref class-hnd exact "Inlining Arg" ; V10 tmp8 ref class-hnd "Inlining Arg" ; V11 tmp9 int "Inlining Arg" ; V12 tmp10 ref class-hnd "Inlining Arg" ; V13 tmp11 ref V07._arg0(offs=0x00) P-INDEP "field V07._arg0 (fldOffset=0x0)" ; V14 tmp12 ref V07._arg1(offs=0x08) P-INDEP "field V07._arg1 (fldOffset=0x8)" ; V15 tmp13 ref V07._arg2(offs=0x10) P-INDEP "field V07._arg2 (fldOffset=0x10)" ; V16 tmp14 ref V07._args(offs=0x18) P-INDEP "field V07._args (fldOffset=0x18)" *************** Finishing PHASE Morph - Promote Structs *************** Starting PHASE Morph - Structs/AddrExp *************** In fgMarkAddressExposedLocals() LocalAddressVisitor visiting statement: STMT00000 (IL 0x000...0x041) [000007] -AC--------- * ASG ref [000006] D------N---- +--* LCL_VAR ref V03 tmp1 [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000004] ------------ arg0 \--* CNS_INT(h) long 0x7f6678c127f0 class LocalAddressVisitor visiting statement: STMT00001 (IL ???... ???) [000012] -A--G------- * ASG long [000011] -------N---- +--* IND long [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V03 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ----G------- \--* FIELD long JobGroup [000002] ------------ \--* ADDR byref [000001] -------N---- \--* LCL_VAR struct V01 arg1 Local V01 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00001 (IL ???... ???) [000012] -A--G------- * ASG long [000011] -------N---- +--* IND long [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V03 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ------------ \--* LCL_FLD long V01 arg1 [+0] Fseq[JobGroup] LocalAddressVisitor visiting statement: STMT00002 (IL ???... ???) [000021] -AC--------- * ASG ref [000020] D------N---- +--* LCL_VAR ref V04 tmp2 [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000018] ------------ arg0 \--* CNS_INT(h) long 0x7f6678beb1c0 class LocalAddressVisitor visiting statement: STMT00003 (IL ???... ???) [000026] -A--G------- * ASG int [000025] -------N---- +--* IND int [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V04 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ----G------- \--* FIELD int Version [000016] ------------ \--* ADDR byref [000015] -------N---- \--* LCL_VAR struct V01 arg1 Local V01 should not be enregistered because: was accessed as a local field LocalAddressVisitor modified statement: STMT00003 (IL ???... ???) [000026] -A--G------- * ASG int [000025] -------N---- +--* IND int [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V04 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ------------ \--* LCL_FLD int V01 arg1 [+8] Fseq[Version] LocalAddressVisitor visiting statement: STMT00010 (IL ???... ???) [000063] -A---------- * ASG ref [000062] -------N---- +--* FIELD ref _arg0 [000059] ------------ | \--* ADDR byref [000060] -------N---- | \--* LCL_VAR struct(P) V07 tmp5 | \--* ref V07._arg0 (offs=0x00) -> V13 tmp11 | \--* ref V07._arg1 (offs=0x08) -> V14 tmp12 | \--* ref V07._arg2 (offs=0x10) -> V15 tmp13 | \--* ref V07._args (offs=0x18) -> V16 tmp14 [000014] ------------ \--* BOX ref [000013] ------------ \--* LCL_VAR ref V03 tmp1 Replacing the field in promoted struct with local var V13 LocalAddressVisitor modified statement: STMT00010 (IL ???... ???) [000063] -A---------- * ASG ref [000062] D------N---- +--* LCL_VAR ref V13 tmp11 [000014] ------------ \--* BOX ref [000013] ------------ \--* LCL_VAR ref V03 tmp1 LocalAddressVisitor visiting statement: STMT00011 (IL ???... ???) [000068] -A---------- * ASG ref [000067] -------N---- +--* FIELD ref _arg1 [000064] ------------ | \--* ADDR byref [000065] -------N---- | \--* LCL_VAR struct(P) V07 tmp5 | \--* ref V07._arg0 (offs=0x00) -> V13 tmp11 | \--* ref V07._arg1 (offs=0x08) -> V14 tmp12 | \--* ref V07._arg2 (offs=0x10) -> V15 tmp13 | \--* ref V07._args (offs=0x18) -> V16 tmp14 [000028] ------------ \--* BOX ref [000027] ------------ \--* LCL_VAR ref V04 tmp2 Replacing the field in promoted struct with local var V14 LocalAddressVisitor modified statement: STMT00011 (IL ???... ???) [000068] -A---------- * ASG ref [000067] D------N---- +--* LCL_VAR ref V14 tmp12 [000028] ------------ \--* BOX ref [000027] ------------ \--* LCL_VAR ref V04 tmp2 LocalAddressVisitor visiting statement: STMT00012 (IL ???... ???) [000073] -A---------- * ASG ref [000072] -------N---- +--* FIELD ref _arg2 [000069] ------------ | \--* ADDR byref [000070] -------N---- | \--* LCL_VAR struct(P) V07 tmp5 | \--* ref V07._arg0 (offs=0x00) -> V13 tmp11 | \--* ref V07._arg1 (offs=0x08) -> V14 tmp12 | \--* ref V07._arg2 (offs=0x10) -> V15 tmp13 | \--* ref V07._args (offs=0x18) -> V16 tmp14 [000071] ------------ \--* CNS_INT ref null Replacing the field in promoted struct with local var V15 LocalAddressVisitor modified statement: STMT00012 (IL ???... ???) [000073] -A---------- * ASG ref [000072] D------N---- +--* LCL_VAR ref V15 tmp13 [000071] ------------ \--* CNS_INT ref null LocalAddressVisitor visiting statement: STMT00013 (IL ???... ???) [000078] -A--G------- * ASG ref [000077] -------N---- +--* FIELD ref _args [000074] ------------ | \--* ADDR byref [000075] -------N---- | \--* LCL_VAR struct(P) V07 tmp5 | \--* ref V07._arg0 (offs=0x00) -> V13 tmp11 | \--* ref V07._arg1 (offs=0x08) -> V14 tmp12 | \--* ref V07._arg2 (offs=0x10) -> V15 tmp13 | \--* ref V07._args (offs=0x18) -> V16 tmp14 [000076] ----G------- \--* FIELD ref s_twoArgArray Replacing the field in promoted struct with local var V16 LocalAddressVisitor modified statement: STMT00013 (IL ???... ???) [000078] -A--G------- * ASG ref [000077] D------N---- +--* LCL_VAR ref V16 tmp14 [000076] ----G------- \--* FIELD ref s_twoArgArray LocalAddressVisitor visiting statement: STMT00015 (IL ???... ???) [000085] -AC-G------- * ASG ref [000084] D------N---- +--* LCL_VAR ref V10 tmp8 [000054] --C-G------- \--* CALL ref System.String.FormatHelper [000046] ------------ arg0 +--* CNS_INT ref null [000047] ------------ arg1 +--* CNS_STR ref [000056] n----------- arg2 \--* OBJ struct [000055] ------------ \--* ADDR byref [000053] -------N---- \--* LCL_VAR struct(P) V07 tmp5 \--* ref V07._arg0 (offs=0x00) -> V13 tmp11 \--* ref V07._arg1 (offs=0x08) -> V14 tmp12 \--* ref V07._arg2 (offs=0x10) -> V15 tmp13 \--* ref V07._args (offs=0x18) -> V16 tmp14 LocalAddressVisitor visiting statement: STMT00014 (IL ???... ???) [000083] --C-G------- * CALL void UnityEngine.Debug.ProcessAndLogInternal [000081] ------------ arg0 +--* CNS_INT int 3 [000082] ------------ arg1 \--* LCL_VAR ref V10 tmp8 LocalAddressVisitor visiting statement: STMT00018 (IL 0x025... ???) [000098] -A--G------- * ASG ref [000097] D------N---- +--* LCL_VAR ref V12 tmp10 [000032] ----G------- \--* FIELD ref s_NetworkInterfaces LocalAddressVisitor visiting statement: STMT00019 (IL 0x025... ???) [000100] -A-XG------- * ASG int [000099] D------N---- +--* LCL_VAR int V11 tmp9 [000034] ---XG------- \--* FIELD int m_NetworkInterfaceIndex [000033] ------------ \--* LCL_VAR byref V00 this LocalAddressVisitor visiting statement: STMT00016 (IL 0x025... ???) [000091] ---XG------- * JTRUE void [000090] N--XG----U-- \--* LT int [000087] ------------ +--* LCL_VAR int V11 tmp9 [000089] ---XG------- \--* FIELD int _size [000088] ------------ \--* LCL_VAR ref V12 tmp10 LocalAddressVisitor visiting statement: STMT00017 (IL 0x025... ???) [000096] --C-G------- * CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException LocalAddressVisitor visiting statement: STMT00007 (IL ???... ???) [000045] --CXG------- * RETURN struct [000040] --CXG------- \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA [000095] ---XG------- this in rdi +--* INDEX ref [000093] ---XG------- | +--* FIELD ref _items [000092] ------------ | | \--* LCL_VAR ref V12 tmp10 [000094] ------------ | \--* LCL_VAR int V11 tmp9 [000044] ---XG------- arg1 +--* OBJ struct [000043] ---XG------- | \--* ADDR byref [000038] ---XG--N---- | \--* FIELD struct m_ParallelSendQueue [000037] ------------ | \--* LCL_VAR byref V00 this [000042] n----------- arg2 \--* OBJ struct [000041] ------------ \--* ADDR byref [000039] -------N---- \--* LCL_VAR struct V01 arg1 *************** Finishing PHASE Morph - Structs/AddrExp *************** Starting PHASE Morph - ByRefs *************** Finishing PHASE Morph - ByRefs *************** Starting PHASE Morph - Global *************** In fgMorphBlocks() Morphing BB01 of 'Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' fgMorphTree BB01, STMT00000 (before) [000007] -AC--------- * ASG ref [000006] D------N---- +--* LCL_VAR ref V03 tmp1 [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000004] ------------ arg0 \--* CNS_INT(h) long 0x7f6678c127f0 class Initializing arg info for 5.CALL: ArgTable for 5.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 4.CNS_INT long (By ref), 1 reg: rdi, align=1] Morphing args for 5.CALL: argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000004] -----+------ * CNS_INT(h) long 0x7f6678c127f0 class Replaced with placeholder node: [000102] ----------L- * ARGPLACE long Shuffled argument table: rdi ArgTable for 5.CALL after fgMorphArgs: fgArgTabEntry[arg 0 4.CNS_INT long (By ref), 1 reg: rdi, align=1, lateArgInx=0, processed] fgMorphTree BB01, STMT00000 (after) [000007] -AC--+------ * ASG ref [000006] D----+-N---- +--* LCL_VAR ref V03 tmp1 [000005] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000004] -----+------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class fgMorphTree BB01, STMT00001 (before) [000012] -A--G------- * ASG long [000011] -------N---- +--* IND long [000010] ------------ | \--* ADD byref [000008] ------------ | +--* LCL_VAR ref V03 tmp1 [000009] ------------ | \--* CNS_INT long 8 [000003] ------------ \--* LCL_FLD long V01 arg1 [+0] Fseq[JobGroup] GenTreeNode creates assertion: [000011] ---X---N---- * IND long In BB01 New Local Constant Assertion: V03 != null index=#01, mask= fgMorphTree BB01, STMT00002 (before) [000021] -AC--------- * ASG ref [000020] D------N---- +--* LCL_VAR ref V04 tmp2 [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000018] ------------ arg0 \--* CNS_INT(h) long 0x7f6678beb1c0 class Initializing arg info for 19.CALL: ArgTable for 19.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 18.CNS_INT long (By ref), 1 reg: rdi, align=1] Morphing args for 19.CALL: argSlots=1, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rdi'): [000018] -----+------ * CNS_INT(h) long 0x7f6678beb1c0 class Replaced with placeholder node: [000103] ----------L- * ARGPLACE long Shuffled argument table: rdi ArgTable for 19.CALL after fgMorphArgs: fgArgTabEntry[arg 0 18.CNS_INT long (By ref), 1 reg: rdi, align=1, lateArgInx=0, processed] fgMorphTree BB01, STMT00002 (after) [000021] -AC--+------ * ASG ref [000020] D----+-N---- +--* LCL_VAR ref V04 tmp2 [000019] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000018] -----+------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class fgMorphTree BB01, STMT00003 (before) [000026] -A--G------- * ASG int [000025] -------N---- +--* IND int [000024] ------------ | \--* ADD byref [000022] ------------ | +--* LCL_VAR ref V04 tmp2 [000023] ------------ | \--* CNS_INT long 8 [000017] ------------ \--* LCL_FLD int V01 arg1 [+8] Fseq[Version] GenTreeNode creates assertion: [000025] ---X---N---- * IND int In BB01 New Local Constant Assertion: V04 != null index=#02, mask= fgMorphTree BB01, STMT00010 (before) [000063] -A---------- * ASG ref [000062] D------N---- +--* LCL_VAR ref V13 tmp11 [000014] ------------ \--* BOX ref [000013] ------------ \--* LCL_VAR ref V03 tmp1 fgMorphTree BB01, STMT00011 (before) [000068] -A---------- * ASG ref [000067] D------N---- +--* LCL_VAR ref V14 tmp12 [000028] ------------ \--* BOX ref [000027] ------------ \--* LCL_VAR ref V04 tmp2 fgMorphTree BB01, STMT00012 (before) [000073] -A---------- * ASG ref [000072] D------N---- +--* LCL_VAR ref V15 tmp13 [000071] ------------ \--* CNS_INT ref null GenTreeNode creates assertion: [000073] -A---------- * ASG ref In BB01 New Local Constant Assertion: V15 == null index=#03, mask= fgMorphTree BB01, STMT00013 (before) [000078] -A--G------- * ASG ref [000077] D------N---- +--* LCL_VAR ref V16 tmp14 [000076] ----G------- \--* FIELD ref s_twoArgArray fgMorphTree BB01, STMT00013 (after) [000078] -A--G+------ * ASG ref [000077] D----+-N---- +--* LCL_VAR ref V16 tmp14 [000076] n---G+------ \--* IND ref [000104] -----+------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] fgMorphTree BB01, STMT00015 (before) [000085] -AC-G------- * ASG ref [000084] D------N---- +--* LCL_VAR ref V10 tmp8 [000054] --C-G------- \--* CALL ref System.String.FormatHelper [000046] ------------ arg0 +--* CNS_INT ref null [000047] ------------ arg1 +--* CNS_STR ref [000056] n----------- arg2 \--* OBJ struct [000055] ------------ \--* ADDR byref [000053] -------N---- \--* LCL_VAR struct(P) V07 tmp5 \--* ref V07._arg0 (offs=0x00) -> V13 tmp11 \--* ref V07._arg1 (offs=0x08) -> V14 tmp12 \--* ref V07._arg2 (offs=0x10) -> V15 tmp13 \--* ref V07._args (offs=0x18) -> V16 tmp14 Initializing arg info for 54.CALL: **** getSystemVAmd64PassStructInRegisterDescriptor(0x79a59e78 (System.ParamsArray), ...) => passedInRegisters = false **** getSystemVAmd64PassStructInRegisterDescriptor(0x79a59e78 (System.ParamsArray), ...) => passedInRegisters = false ArgTable for 54.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 46.CNS_INT ref (By ref), 1 reg: rdi, align=1] fgArgTabEntry[arg 1 47.CNS_STR ref (By ref), 1 reg: rsi, align=1] fgArgTabEntry[arg 2 56.OBJ struct (By value), numSlots=4, slotNum=0, align=1, isStruct] Morphing args for 54.CALL: argSlots=6, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 Sorting the arguments: Deferred argument ('rsi'): ( 4, 12) [000106] n---G------- * IND ref ( 2, 10) [000105] ------------ \--* CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] Replaced with placeholder node: [000107] ----------L- * ARGPLACE ref Deferred argument ('rdi'): [000046] -----+------ * CNS_INT ref null Replaced with placeholder node: [000108] ----------L- * ARGPLACE ref Shuffled argument table: rsi rdi ArgTable for 54.CALL after fgMorphArgs: fgArgTabEntry[arg 2 109.FIELD_LIST struct (By value), numSlots=4, slotNum=0, align=1, processed, isStruct] fgArgTabEntry[arg 1 106.IND ref (By ref), 1 reg: rsi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 0 46.CNS_INT ref (By ref), 1 reg: rdi, align=1, lateArgInx=1, processed] fgMorphTree BB01, STMT00015 (after) [000085] -ACXG+------ * ASG ref [000084] D----+-N---- +--* LCL_VAR ref V10 tmp8 [000054] --CXG+------ \--* CALL ref System.String.FormatHelper [000109] -c---------- arg2 out+00 +--* FIELD_LIST struct [000110] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp11 [000111] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp12 [000112] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp13 [000113] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp14 ( 4, 12) [000106] n---G------- arg1 in rsi +--* IND ref ( 2, 10) [000105] ------------ | \--* CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] [000046] -----+------ arg0 in rdi \--* CNS_INT ref null fgMorphTree BB01, STMT00014 (before) [000083] --C-G------- * CALL void UnityEngine.Debug.ProcessAndLogInternal [000081] ------------ arg0 +--* CNS_INT int 3 [000082] ------------ arg1 \--* LCL_VAR ref V10 tmp8 Initializing arg info for 83.CALL: ArgTable for 83.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 81.CNS_INT int (By ref), 1 reg: rdi, align=1] fgArgTabEntry[arg 1 82.LCL_VAR ref (By ref), 1 reg: rsi, align=1] Morphing args for 83.CALL: argSlots=2, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 Sorting the arguments: Deferred argument ('rsi'): [000082] -----+------ * LCL_VAR ref V10 tmp8 Replaced with placeholder node: [000114] ----------L- * ARGPLACE ref Deferred argument ('rdi'): [000081] -----+------ * CNS_INT int 3 Replaced with placeholder node: [000115] ----------L- * ARGPLACE int Shuffled argument table: rsi rdi ArgTable for 83.CALL after fgMorphArgs: fgArgTabEntry[arg 1 82.LCL_VAR ref (By ref), 1 reg: rsi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 0 81.CNS_INT int (By ref), 1 reg: rdi, align=1, lateArgInx=1, processed] fgMorphTree BB01, STMT00014 (after) [000083] --CXG+------ * CALL void UnityEngine.Debug.ProcessAndLogInternal [000082] -----+------ arg1 in rsi +--* LCL_VAR ref V10 tmp8 [000081] -----+------ arg0 in rdi \--* CNS_INT int 3 fgMorphTree BB01, STMT00018 (before) [000098] -A--G------- * ASG ref [000097] D------N---- +--* LCL_VAR ref V12 tmp10 [000032] ----G------- \--* FIELD ref s_NetworkInterfaces fgMorphTree BB01, STMT00018 (after) [000098] -A--G+------ * ASG ref [000097] D----+-N---- +--* LCL_VAR ref V12 tmp10 [000032] n---G+------ \--* IND ref [000116] -----+------ \--* CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] fgMorphTree BB01, STMT00019 (before) [000100] -A-XG------- * ASG int [000099] D------N---- +--* LCL_VAR int V11 tmp9 [000034] ---XG------- \--* FIELD int m_NetworkInterfaceIndex [000033] ------------ \--* LCL_VAR byref V00 this Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000034] *--XG------- * IND int [000118] -----+------ \--* ADD byref [000033] -----+------ +--* LCL_VAR byref V00 this [000117] -----+------ \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] GenTreeNode creates assertion: [000100] -A-XG------- * ASG int In BB01 New Local Subrange Assertion: V11 in [-2147483648..2147483647] index=#04, mask= fgMorphTree BB01, STMT00019 (after) [000100] -A-XG+------ * ASG int [000099] D----+-N---- +--* LCL_VAR int V11 tmp9 [000034] *--XG+------ \--* IND int [000118] -----+------ \--* ADD byref [000033] -----+------ +--* LCL_VAR byref V00 this [000117] -----+------ \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] fgMorphTree BB01, STMT00016 (before) [000091] ---XG------- * JTRUE void [000090] N--XG----U-- \--* LT int [000087] ------------ +--* LCL_VAR int V11 tmp9 [000089] ---XG------- \--* FIELD int _size [000088] ------------ \--* LCL_VAR ref V12 tmp10 Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000089] ---XG------- * IND int [000120] -----+------ \--* ADD byref [000088] -----+------ +--* LCL_VAR ref V12 tmp10 [000119] -----+------ \--* CNS_INT long 16 field offset Fseq[_size] GenTreeNode creates assertion: [000089] ---XG------- * IND int In BB01 New Local Constant Assertion: V12 != null index=#05, mask= fgMorphTree BB01, STMT00016 (after) [000091] ---XG+------ * JTRUE void [000090] N--XG+-N-U-- \--* LT int [000087] -----+------ +--* LCL_VAR int V11 tmp9 [000089] ---XG+------ \--* IND int [000120] -----+------ \--* ADD byref [000088] -----+------ +--* LCL_VAR ref V12 tmp10 [000119] -----+------ \--* CNS_INT long 16 field offset Fseq[_size] Morphing BB03 of 'Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' fgMorphTree BB03, STMT00017 (before) [000096] --C-G------- * CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException Initializing arg info for 96.CALL: ArgTable for 96.CALL after fgInitArgInfo: Morphing args for 96.CALL: argSlots=0, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 ArgTable for 96.CALL after fgMorphArgs: Converting BB03 to BBJ_THROW Morphing BB04 of 'Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this' fgMorphTree BB04, STMT00007 (before) [000045] --CXG------- * RETURN struct [000040] --CXG------- \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA [000095] ---XG------- this in rdi +--* INDEX ref [000093] ---XG------- | +--* FIELD ref _items [000092] ------------ | | \--* LCL_VAR ref V12 tmp10 [000094] ------------ | \--* LCL_VAR int V11 tmp9 [000044] ---XG------- arg1 +--* OBJ struct [000043] ---XG------- | \--* ADDR byref [000038] ---XG--N---- | \--* FIELD struct m_ParallelSendQueue [000037] ------------ | \--* LCL_VAR byref V00 this [000042] n----------- arg2 \--* OBJ struct [000041] ------------ \--* ADDR byref [000039] -------N---- \--* LCL_VAR struct V01 arg1 Initializing arg info for 40.CALL: **** getSystemVAmd64PassStructInRegisterDescriptor(0x79670b20 (Unity.Collections.NativeQueue`1[QueuedSendMessage]), ...) => passedInRegisters = false **** getSystemVAmd64PassStructInRegisterDescriptor(0x79670b20 (Unity.Collections.NativeQueue`1[QueuedSendMessage]), ...) => passedInRegisters = false **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 ArgTable for 40.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 95.INDEX ref (By ref), 1 reg: rdi, align=1] fgArgTabEntry[arg 1 121.CNS_INT long (By ref), 1 reg: r11, align=1, isNonStandard] fgArgTabEntry[arg 2 44.OBJ struct (By value), numSlots=7, slotNum=0, align=1, isStruct] fgArgTabEntry[arg 3 42.OBJ struct (By value), 2 regs: rsi rdx, align=1, isStruct] [Fast tailcall decision]: Will not fast tailcall (Not enough incoming arg space) Rejecting tail call in morph for call [000040]: Not enough incoming arg space lvaGrabTemp returning 17 (V17 tmp15) (a long lifetime temp) called for Return value temp for multi-reg return (rejected tail call).. Initializing arg info for 40.CALL: **** getSystemVAmd64PassStructInRegisterDescriptor(0x79670b20 (Unity.Collections.NativeQueue`1[QueuedSendMessage]), ...) => passedInRegisters = false **** getSystemVAmd64PassStructInRegisterDescriptor(0x79670b20 (Unity.Collections.NativeQueue`1[QueuedSendMessage]), ...) => passedInRegisters = false **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 ArgTable for 40.CALL after fgInitArgInfo: fgArgTabEntry[arg 0 95.INDEX ref (By ref), 1 reg: rdi, align=1] fgArgTabEntry[arg 1 124.CNS_INT long (By ref), 1 reg: r11, align=1, isNonStandard] fgArgTabEntry[arg 2 121.CNS_INT long (By ref), 1 reg: rsi, align=1] fgArgTabEntry[arg 3 44.OBJ struct (By value), numSlots=7, slotNum=0, align=1, isStruct] fgArgTabEntry[arg 4 42.OBJ struct (By value), 2 regs: rdx rcx, align=1, isStruct] Morphing args for 40.CALL: lvaGrabTemp returning 18 (V18 tmp16) called for arr expr. Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000093] ---XG------- * IND ref [000141] -----+------ \--* ADD byref [000092] -----+------ +--* LCL_VAR ref V12 tmp10 [000140] -----+------ \--* CNS_INT long 8 field offset Fseq[_items] GenTreeNode creates assertion: [000093] ---XG------- * IND ref In BB04 New Local Constant Assertion: V12 != null index=#01, mask= GenTreeNode creates assertion: [000130] ---X-------- * ARR_LENGTH int In BB04 New Local Constant Assertion: V18 != null index=#02, mask= Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000038] *--XG--N---- * IND struct [000143] -----+------ \--* ADD byref [000037] -----+------ +--* LCL_VAR byref V00 this [000142] -----+------ \--* CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] argSlots=11, preallocatedArgCount=7, nextSlotNum=7, outgoingArgSpaceSize=56 Sorting the arguments: Argument with 'side effect'... [000139] -A-XG+------ * COMMA ref [000126] -A-XG+------ +--* ASG ref [000125] D----+-N---- | +--* LCL_VAR ref V18 tmp16 [000093] ---XG+------ | \--* IND ref [000141] -----+------ | \--* ADD byref [000092] -----+------ | +--* LCL_VAR ref V12 tmp10 [000140] -----+------ | \--* CNS_INT long 8 field offset Fseq[_items] [000138] ---XG+------ \--* COMMA ref [000131] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000094] -----+------ | +--* LCL_VAR int V11 tmp9 [000130] ---X-+------ | \--* ARR_LENGTH int [000127] -----+------ | \--* LCL_VAR ref V18 tmp16 [000095] a---G+------ \--* IND ref [000137] -----+------ \--* ADD byref [000128] -----+------ +--* LCL_VAR ref V18 tmp16 [000136] -----+------ \--* ADD long [000134] -----+------ +--* LSH long [000132] -----+------ | +--* CAST long <- int [000129] i----+------ | | \--* LCL_VAR int V11 tmp9 [000133] -----+-N---- | \--* CNS_INT long 3 [000135] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] lvaGrabTemp returning 19 (V19 tmp17) called for argument with side effect. Evaluate to a temp: [000145] -A-XG-----L- * ASG ref [000144] D------N---- +--* LCL_VAR ref V19 tmp17 [000139] -A-XG+------ \--* COMMA ref [000126] -A-XG+------ +--* ASG ref [000125] D----+-N---- | +--* LCL_VAR ref V18 tmp16 [000093] ---XG+------ | \--* IND ref [000141] -----+------ | \--* ADD byref [000092] -----+------ | +--* LCL_VAR ref V12 tmp10 [000140] -----+------ | \--* CNS_INT long 8 field offset Fseq[_items] [000138] ---XG+------ \--* COMMA ref [000131] ---X-+------ +--* ARR_BOUNDS_CHECK_Rng void [000094] -----+------ | +--* LCL_VAR int V11 tmp9 [000130] ---X-+------ | \--* ARR_LENGTH int [000127] -----+------ | \--* LCL_VAR ref V18 tmp16 [000095] a---G+------ \--* IND ref [000137] -----+------ \--* ADD byref [000128] -----+------ +--* LCL_VAR ref V18 tmp16 [000136] -----+------ \--* ADD long [000134] -----+------ +--* LSH long [000132] -----+------ | +--* CAST long <- int [000129] i----+------ | | \--* LCL_VAR int V11 tmp9 [000133] -----+-N---- | \--* CNS_INT long 3 [000135] -----+------ \--* CNS_INT long 16 Fseq[#FirstElem] Deferred argument ('rdx'): ( 9, 7) [000042] n----------- * OBJ struct ( 3, 3) [000041] ------------ \--* ADDR byref ( 3, 2) [000039] -------N---- \--* LCL_VAR struct V01 arg1 Replaced with placeholder node: [000147] ----------L- * ARGPLACE struct => [clsHnd=795C7A00] Deferred argument ('r11'): [000124] -----+------ * CNS_INT(h) long 0x7f6678060518 ftn REG r11 Replaced with placeholder node: [000148] ----------L- * ARGPLACE long Deferred argument ('rsi'): [000121] -----+------ * CNS_INT(h) long 0x7f6678060518 ftn REG r11 Replaced with placeholder node: [000149] ----------L- * ARGPLACE long Shuffled argument table: rdi rdx r11 rsi Multireg struct argument V01 : fgArgTabEntry[arg 4 42.OBJ struct (By value), 2 regs: rdx rcx, align=1, lateArgInx=1, processed, isStruct] Local V01 should not be enregistered because: was accessed as a local field Local V01 should not be enregistered because: was accessed as a local field fgMorphMultiregStructArg created tree: [000150] -c---------- * FIELD_LIST struct [000151] ------------ ofs 0 +--* LCL_FLD long V01 arg1 [+0] [000152] ------------ ofs 8 \--* LCL_FLD long V01 arg1 [+8] ArgTable for 40.CALL after fgMorphArgs: fgArgTabEntry[arg 0 146.LCL_VAR ref (By ref), 1 reg: rdi, align=1, lateArgInx=0, tmpNum=V19, isTmp, processed] fgArgTabEntry[arg 3 44.OBJ struct (By value), numSlots=7, slotNum=0, align=1, processed, isStruct] fgArgTabEntry[arg 4 150.FIELD_LIST struct (By value), 2 regs: rdx rcx, align=1, lateArgInx=1, processed, isStruct] fgArgTabEntry[arg 1 124.CNS_INT long (By ref), 1 reg: r11, align=1, lateArgInx=2, processed, isNonStandard] fgArgTabEntry[arg 2 121.CNS_INT long (By ref), 1 reg: rsi, align=1, lateArgInx=3, processed] GenTreeNode creates assertion: [000040] -ACXG------- * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA In BB04 New Local Constant Assertion: V19 != null index=#03, mask= fgMorphCopyBlock: not morphing a multireg call return Inserting assignment of a multi-reg call result to a temp: STMT00020 (IL ???... ???) [000123] -ACXG+------ * ASG struct (copy) [000122] D----+-N---- +--* LCL_VAR struct V17 tmp15 [000040] -ACXG+------ \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA [000145] -A-XG-----L- this SETUP +--* ASG ref [000144] D------N---- | +--* LCL_VAR ref V19 tmp17 [000139] -A-XG+------ | \--* COMMA ref [000126] -A-XG+------ | +--* ASG ref [000125] D----+-N---- | | +--* LCL_VAR ref V18 tmp16 [000093] ---XG+------ | | \--* IND ref [000141] -----+------ | | \--* ADD byref [000092] -----+------ | | +--* LCL_VAR ref V12 tmp10 [000140] -----+------ | | \--* CNS_INT long 8 field offset Fseq[_items] [000138] ---XG+------ | \--* COMMA ref [000131] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000094] -----+------ | | +--* LCL_VAR int V11 tmp9 [000130] ---X-+------ | | \--* ARR_LENGTH int [000127] -----+------ | | \--* LCL_VAR ref V18 tmp16 [000095] a---G+------ | \--* IND ref [000137] -----+------ | \--* ADD byref [000128] -----+------ | +--* LCL_VAR ref V18 tmp16 [000136] -----+------ | \--* ADD long [000134] -----+------ | +--* LSH long [000132] -----+------ | | +--* CAST long <- int [000129] i----+------ | | | \--* LCL_VAR int V11 tmp9 [000133] -----+-N---- | | \--* CNS_INT long 3 [000135] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] ( 11, 8) [000044] ---XG------- arg3 out+00 +--* OBJ struct ( 5, 4) [000143] ------------ | \--* ADD byref ( 3, 2) [000037] ------------ | +--* LCL_VAR byref V00 this ( 1, 1) [000142] ------------ | \--* CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] [000146] ------------ this in rdi +--* LCL_VAR ref V19 tmp17 [000150] -c---------- arg4 rdx,rcx +--* FIELD_LIST struct [000151] ------------ ofs 0 | +--* LCL_FLD long V01 arg1 [+0] [000152] ------------ ofs 8 | \--* LCL_FLD long V01 arg1 [+8] [000124] -----+------ arg1 in r11 +--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 [000121] -----+------ arg2 in rsi \--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 fgMorphTree BB04, STMT00007 (after) [000045] ----G+------ * RETURN struct [000153] -----+-N---- \--* LCL_VAR struct V17 tmp15 *************** Finishing PHASE Morph - Global Trees after Morph - Global ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB04 ( cond ) i label target hascall gcsafe newobj BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare hascall gcsafe BB04 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) -> BB04 (cond), preds={} succs={BB03,BB04} ***** BB01 STMT00000 (IL 0x000...0x041) [000007] -AC--+------ * ASG ref [000006] D----+-N---- +--* LCL_VAR ref V03 tmp1 [000005] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000004] -----+------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class ***** BB01 STMT00001 (IL ???... ???) [000012] -A-XG+------ * ASG long [000011] ---X-+-N---- +--* IND long [000010] -----+------ | \--* ADD byref [000008] -----+------ | +--* LCL_VAR ref V03 tmp1 [000009] -----+------ | \--* CNS_INT long 8 [000003] -----+------ \--* LCL_FLD long V01 arg1 [+0] Fseq[JobGroup] ***** BB01 STMT00002 (IL ???... ???) [000021] -AC--+------ * ASG ref [000020] D----+-N---- +--* LCL_VAR ref V04 tmp2 [000019] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000018] -----+------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class ***** BB01 STMT00003 (IL ???... ???) [000026] -A-XG+------ * ASG int [000025] ---X-+-N---- +--* IND int [000024] -----+------ | \--* ADD byref [000022] -----+------ | +--* LCL_VAR ref V04 tmp2 [000023] -----+------ | \--* CNS_INT long 8 [000017] -----+------ \--* LCL_FLD int V01 arg1 [+8] Fseq[Version] ***** BB01 STMT00010 (IL ???... ???) [000063] -A---+------ * ASG ref [000062] D----+-N---- +--* LCL_VAR ref V13 tmp11 [000014] -----+------ \--* BOX ref [000013] -----+------ \--* LCL_VAR ref V03 tmp1 ***** BB01 STMT00011 (IL ???... ???) [000068] -A---+------ * ASG ref [000067] D----+-N---- +--* LCL_VAR ref V14 tmp12 [000028] -----+------ \--* BOX ref [000027] -----+------ \--* LCL_VAR ref V04 tmp2 ***** BB01 STMT00012 (IL ???... ???) [000073] -A---+------ * ASG ref [000072] D----+-N---- +--* LCL_VAR ref V15 tmp13 [000071] -----+------ \--* CNS_INT ref null ***** BB01 STMT00013 (IL ???... ???) [000078] -A--G+------ * ASG ref [000077] D----+-N---- +--* LCL_VAR ref V16 tmp14 [000076] n---G+------ \--* IND ref [000104] -----+------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] ***** BB01 STMT00015 (IL ???... ???) [000085] -ACXG+------ * ASG ref [000084] D----+-N---- +--* LCL_VAR ref V10 tmp8 [000054] --CXG+------ \--* CALL ref System.String.FormatHelper [000109] -c---------- arg2 out+00 +--* FIELD_LIST struct [000110] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp11 [000111] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp12 [000112] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp13 [000113] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp14 ( 4, 12) [000106] n---G------- arg1 in rsi +--* IND ref ( 2, 10) [000105] ------------ | \--* CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] [000046] -----+------ arg0 in rdi \--* CNS_INT ref null ***** BB01 STMT00014 (IL ???... ???) [000083] --CXG+------ * CALL void UnityEngine.Debug.ProcessAndLogInternal [000082] -----+------ arg1 in rsi +--* LCL_VAR ref V10 tmp8 [000081] -----+------ arg0 in rdi \--* CNS_INT int 3 ***** BB01 STMT00018 (IL 0x025... ???) [000098] -A--G+------ * ASG ref [000097] D----+-N---- +--* LCL_VAR ref V12 tmp10 [000032] n---G+------ \--* IND ref [000116] -----+------ \--* CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] ***** BB01 STMT00019 (IL 0x025... ???) [000100] -A-XG+------ * ASG int [000099] D----+-N---- +--* LCL_VAR int V11 tmp9 [000034] *--XG+------ \--* IND int [000118] -----+------ \--* ADD byref [000033] -----+------ +--* LCL_VAR byref V00 this [000117] -----+------ \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] ***** BB01 STMT00016 (IL 0x025... ???) [000091] ---XG+------ * JTRUE void [000090] N--XG+-N-U-- \--* LT int [000087] -----+------ +--* LCL_VAR int V11 tmp9 [000089] ---XG+------ \--* IND int [000120] -----+------ \--* ADD byref [000088] -----+------ +--* LCL_VAR ref V12 tmp10 [000119] -----+------ \--* CNS_INT long 16 field offset Fseq[_size] ------------ BB03 [025..026) (throw), preds={BB01} succs={} ***** BB03 STMT00017 (IL 0x025... ???) [000096] --CXG+------ * CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException ------------ BB04 [025..026) (return), preds={BB01} succs={} ***** BB04 STMT00020 (IL ???... ???) [000123] -ACXG+------ * ASG struct (copy) [000122] D----+-N---- +--* LCL_VAR struct V17 tmp15 [000040] -ACXG+------ \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA [000145] -A-XG-----L- this SETUP +--* ASG ref [000144] D------N---- | +--* LCL_VAR ref V19 tmp17 [000139] -A-XG+------ | \--* COMMA ref [000126] -A-XG+------ | +--* ASG ref [000125] D----+-N---- | | +--* LCL_VAR ref V18 tmp16 [000093] ---XG+------ | | \--* IND ref [000141] -----+------ | | \--* ADD byref [000092] -----+------ | | +--* LCL_VAR ref V12 tmp10 [000140] -----+------ | | \--* CNS_INT long 8 field offset Fseq[_items] [000138] ---XG+------ | \--* COMMA ref [000131] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000094] -----+------ | | +--* LCL_VAR int V11 tmp9 [000130] ---X-+------ | | \--* ARR_LENGTH int [000127] -----+------ | | \--* LCL_VAR ref V18 tmp16 [000095] a---G+------ | \--* IND ref [000137] -----+------ | \--* ADD byref [000128] -----+------ | +--* LCL_VAR ref V18 tmp16 [000136] -----+------ | \--* ADD long [000134] -----+------ | +--* LSH long [000132] -----+------ | | +--* CAST long <- int [000129] i----+------ | | | \--* LCL_VAR int V11 tmp9 [000133] -----+-N---- | | \--* CNS_INT long 3 [000135] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] ( 11, 8) [000044] ---XG------- arg3 out+00 +--* OBJ struct ( 5, 4) [000143] ------------ | \--* ADD byref ( 3, 2) [000037] ------------ | +--* LCL_VAR byref V00 this ( 1, 1) [000142] ------------ | \--* CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] [000146] ------------ this in rdi +--* LCL_VAR ref V19 tmp17 [000150] -c---------- arg4 rdx,rcx +--* FIELD_LIST struct [000151] ------------ ofs 0 | +--* LCL_FLD long V01 arg1 [+0] [000152] ------------ ofs 8 | \--* LCL_FLD long V01 arg1 [+8] [000124] -----+------ arg1 in r11 +--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 [000121] -----+------ arg2 in rsi \--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 ***** BB04 STMT00007 (IL ???... ???) [000045] ----G+------ * RETURN struct [000153] -----+-N---- \--* LCL_VAR struct V17 tmp15 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE GS Cookie No GS security needed *************** Finishing PHASE GS Cookie *************** Starting PHASE Mark GC poll blocks *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB04 ( cond ) i label target hascall gcsafe newobj BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare hascall gcsafe BB04 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB03 to BB02 Renumber BB04 to BB03 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj BB02 [0005] 1 BB01 0 [025..026) (throw ) i rare hascall gcsafe BB03 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 3, # of blocks (including unused BB00): 4, bitset array size: 1 (short) *************** Finishing PHASE Mark GC poll blocks *************** Starting PHASE Compute edge weights (1, false) *************** In fgComputeBlockAndEdgeWeights() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj BB02 [0005] 1 BB01 0 [025..026) (throw ) i rare hascall gcsafe BB03 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj ----------------------------------------------------------------------------------------------------------------------------------------- -- no profile data, so using default called count fgComputeEdgeWeights() was able to compute exact edge weights for all of the 2 edges, using 1 passes. Edge weights into BB02 :BB01 (0) Edge weights into BB03 :BB01 (100) *************** Finishing PHASE Compute edge weights (1, false) *************** Starting PHASE Create EH funclets *************** In fgCreateFunclets() After fgCreateFunclets() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj BB02 [0005] 1 BB01 0 [025..026) (throw ) i rare hascall gcsafe BB03 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** Finishing PHASE Create EH funclets *************** Starting PHASE Optimize layout *************** In optOptimizeLayout() *************** Exception Handling table is empty *************** In fgDebugCheckBBlist *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj BB02 [0005] 1 BB01 0 [025..026) (throw ) i rare hascall gcsafe BB03 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgExpandRarelyRunBlocks() *************** In fgReorderBlocks() Initial BasicBlocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj BB02 [0005] 1 BB01 0 [025..026) (throw ) i rare hascall gcsafe BB03 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj ----------------------------------------------------------------------------------------------------------------------------------------- Decided to reverse conditional branch at block BB01 branch to BB03 since it falls into a rarely run block Relocated rarely run block BB02 by reversing conditional jump at BB01 Relocated block [BB02..BB02] inserted after BB03 at the end of method After this change in fgReorderBlocks the BB graph is: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB02 ( cond ) i label target hascall gcsafe newobj BB03 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj BB02 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB02 ( cond ) i label target hascall gcsafe newobj BB03 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj BB02 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize layout *************** Starting PHASE Compute blocks reachability *************** In fgComputeReachability *************** In fgDebugCheckBBlist Renumbering the basic blocks for fgComputeReachability pass #1 *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB02 ( cond ) i label target hascall gcsafe newobj BB03 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj BB02 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty Renumber BB03 to BB02 Renumber BB02 to BB03 *************** After renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj BB02 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty New BlockSet epoch 4, # of blocks (including unused BB00): 4, bitset array size: 1 (short) Enter blocks: BB01 After computing reachability sets: ------------------------------------------------ BBnum Reachable by ------------------------------------------------ BB01 : BB01 BB02 : BB01 BB02 BB03 : BB01 BB03 After computing reachability: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj BB02 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgComputeDoms *************** In fgDebugCheckBBlist Dominator computation start blocks (those blocks with no incoming edges): BB01 ------------------------------------------------ BBnum Dominated by ------------------------------------------------ BB01: BB01 BB02: BB02 BB01 BB03: BB03 BB01 Inside fgBuildDomTree After computing the Dominance Tree: BB01 : BB03 BB02 After numbering the dominator tree: BB01: pre=01, post=03 BB02: pre=03, post=02 BB03: pre=02, post=01 *************** Finishing PHASE Compute blocks reachability *************** Starting PHASE Optimize loops *************** In optOptimizeLoops() *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize loops *************** Starting PHASE Clone loops *************** In optCloneLoops() *************** Finishing PHASE Clone loops *************** Starting PHASE Unroll loops *************** Finishing PHASE Unroll loops *************** Starting PHASE Mark local vars *************** In lvaMarkLocalVars() *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** *** marking local variables in block BB01 (weight=1 ) STMT00000 (IL 0x000...0x041) [000007] -AC--+------ * ASG ref [000006] D----+-N---- +--* LCL_VAR ref V03 tmp1 [000005] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000004] -----+------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class New refCnts for V03: refCnt = 1, refCntWtd = 2 STMT00001 (IL ???... ???) [000012] -A-XG+------ * ASG long [000011] ---X-+-N---- +--* IND long [000010] -----+------ | \--* ADD byref [000008] -----+------ | +--* LCL_VAR ref V03 tmp1 [000009] -----+------ | \--* CNS_INT long 8 [000003] -----+------ \--* LCL_FLD long V01 arg1 [+0] Fseq[JobGroup] New refCnts for V03: refCnt = 2, refCntWtd = 4 New refCnts for V01: refCnt = 1, refCntWtd = 1 STMT00002 (IL ???... ???) [000021] -AC--+------ * ASG ref [000020] D----+-N---- +--* LCL_VAR ref V04 tmp2 [000019] --C--+------ \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST [000018] -----+------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class New refCnts for V04: refCnt = 1, refCntWtd = 2 STMT00003 (IL ???... ???) [000026] -A-XG+------ * ASG int [000025] ---X-+-N---- +--* IND int [000024] -----+------ | \--* ADD byref [000022] -----+------ | +--* LCL_VAR ref V04 tmp2 [000023] -----+------ | \--* CNS_INT long 8 [000017] -----+------ \--* LCL_FLD int V01 arg1 [+8] Fseq[Version] New refCnts for V04: refCnt = 2, refCntWtd = 4 New refCnts for V01: refCnt = 2, refCntWtd = 2 STMT00010 (IL ???... ???) [000063] -A---+------ * ASG ref [000062] D----+-N---- +--* LCL_VAR ref V13 tmp11 [000014] -----+------ \--* BOX ref [000013] -----+------ \--* LCL_VAR ref V03 tmp1 New refCnts for V13: refCnt = 1, refCntWtd = 1 New refCnts for V03: refCnt = 3, refCntWtd = 6 STMT00011 (IL ???... ???) [000068] -A---+------ * ASG ref [000067] D----+-N---- +--* LCL_VAR ref V14 tmp12 [000028] -----+------ \--* BOX ref [000027] -----+------ \--* LCL_VAR ref V04 tmp2 New refCnts for V14: refCnt = 1, refCntWtd = 1 New refCnts for V04: refCnt = 3, refCntWtd = 6 STMT00012 (IL ???... ???) [000073] -A---+------ * ASG ref [000072] D----+-N---- +--* LCL_VAR ref V15 tmp13 [000071] -----+------ \--* CNS_INT ref null New refCnts for V15: refCnt = 1, refCntWtd = 1 STMT00013 (IL ???... ???) [000078] -A--G+------ * ASG ref [000077] D----+-N---- +--* LCL_VAR ref V16 tmp14 [000076] n---G+------ \--* IND ref [000104] -----+------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] New refCnts for V16: refCnt = 1, refCntWtd = 1 STMT00015 (IL ???... ???) [000085] -ACXG+------ * ASG ref [000084] D----+-N---- +--* LCL_VAR ref V10 tmp8 [000054] --CXG+------ \--* CALL ref System.String.FormatHelper [000109] -c---------- arg2 out+00 +--* FIELD_LIST struct [000110] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp11 [000111] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp12 [000112] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp13 [000113] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp14 ( 4, 12) [000106] n---G------- arg1 in rsi +--* IND ref ( 2, 10) [000105] ------------ | \--* CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] [000046] -----+------ arg0 in rdi \--* CNS_INT ref null New refCnts for V10: refCnt = 1, refCntWtd = 2 New refCnts for V13: refCnt = 2, refCntWtd = 2 New refCnts for V14: refCnt = 2, refCntWtd = 2 New refCnts for V15: refCnt = 2, refCntWtd = 2 New refCnts for V16: refCnt = 2, refCntWtd = 2 STMT00014 (IL ???... ???) [000083] --CXG+------ * CALL void UnityEngine.Debug.ProcessAndLogInternal [000082] -----+------ arg1 in rsi +--* LCL_VAR ref V10 tmp8 [000081] -----+------ arg0 in rdi \--* CNS_INT int 3 New refCnts for V10: refCnt = 2, refCntWtd = 4 STMT00018 (IL 0x025... ???) [000098] -A--G+------ * ASG ref [000097] D----+-N---- +--* LCL_VAR ref V12 tmp10 [000032] n---G+------ \--* IND ref [000116] -----+------ \--* CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] New refCnts for V12: refCnt = 1, refCntWtd = 2 STMT00019 (IL 0x025... ???) [000100] -A-XG+------ * ASG int [000099] D----+-N---- +--* LCL_VAR int V11 tmp9 [000034] *--XG+------ \--* IND int [000118] -----+------ \--* ADD byref [000033] -----+------ +--* LCL_VAR byref V00 this [000117] -----+------ \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] New refCnts for V11: refCnt = 1, refCntWtd = 2 New refCnts for V00: refCnt = 1, refCntWtd = 1 STMT00016 (IL 0x025... ???) [000091] ---XG+------ * JTRUE void [000090] N--XG+-N-U-- \--* GE int [000087] -----+------ +--* LCL_VAR int V11 tmp9 [000089] ---XG+------ \--* IND int [000120] -----+------ \--* ADD byref [000088] -----+------ +--* LCL_VAR ref V12 tmp10 [000119] -----+------ \--* CNS_INT long 16 field offset Fseq[_size] New refCnts for V11: refCnt = 2, refCntWtd = 4 New refCnts for V12: refCnt = 2, refCntWtd = 4 *** marking local variables in block BB02 (weight=1 ) STMT00020 (IL ???... ???) [000123] -ACXG+------ * ASG struct (copy) [000122] D----+-N---- +--* LCL_VAR struct V17 tmp15 [000040] -ACXG+------ \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA [000145] -A-XG-----L- this SETUP +--* ASG ref [000144] D------N---- | +--* LCL_VAR ref V19 tmp17 [000139] -A-XG+------ | \--* COMMA ref [000126] -A-XG+------ | +--* ASG ref [000125] D----+-N---- | | +--* LCL_VAR ref V18 tmp16 [000093] ---XG+------ | | \--* IND ref [000141] -----+------ | | \--* ADD byref [000092] -----+------ | | +--* LCL_VAR ref V12 tmp10 [000140] -----+------ | | \--* CNS_INT long 8 field offset Fseq[_items] [000138] ---XG+------ | \--* COMMA ref [000131] ---X-+------ | +--* ARR_BOUNDS_CHECK_Rng void [000094] -----+------ | | +--* LCL_VAR int V11 tmp9 [000130] ---X-+------ | | \--* ARR_LENGTH int [000127] -----+------ | | \--* LCL_VAR ref V18 tmp16 [000095] a---G+------ | \--* IND ref [000137] -----+------ | \--* ADD byref [000128] -----+------ | +--* LCL_VAR ref V18 tmp16 [000136] -----+------ | \--* ADD long [000134] -----+------ | +--* LSH long [000132] -----+------ | | +--* CAST long <- int [000129] i----+------ | | | \--* LCL_VAR int V11 tmp9 [000133] -----+-N---- | | \--* CNS_INT long 3 [000135] -----+------ | \--* CNS_INT long 16 Fseq[#FirstElem] ( 11, 8) [000044] ---XG------- arg3 out+00 +--* OBJ struct ( 5, 4) [000143] ------------ | \--* ADD byref ( 3, 2) [000037] ------------ | +--* LCL_VAR byref V00 this ( 1, 1) [000142] ------------ | \--* CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] [000146] ------------ this in rdi +--* LCL_VAR ref V19 tmp17 [000150] -c---------- arg4 rdx,rcx +--* FIELD_LIST struct [000151] ------------ ofs 0 | +--* LCL_FLD long V01 arg1 [+0] [000152] ------------ ofs 8 | \--* LCL_FLD long V01 arg1 [+8] [000124] -----+------ arg1 in r11 +--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 [000121] -----+------ arg2 in rsi \--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 New refCnts for V17: refCnt = 1, refCntWtd = 1 New refCnts for V19: refCnt = 1, refCntWtd = 2 New refCnts for V18: refCnt = 1, refCntWtd = 2 New refCnts for V12: refCnt = 3, refCntWtd = 6 New refCnts for V11: refCnt = 3, refCntWtd = 6 New refCnts for V18: refCnt = 2, refCntWtd = 4 New refCnts for V18: refCnt = 3, refCntWtd = 6 New refCnts for V11: refCnt = 4, refCntWtd = 8 New refCnts for V00: refCnt = 2, refCntWtd = 2 New refCnts for V19: refCnt = 2, refCntWtd = 4 New refCnts for V01: refCnt = 3, refCntWtd = 3 New refCnts for V01: refCnt = 4, refCntWtd = 4 STMT00007 (IL ???... ???) [000045] ----G+------ * RETURN struct [000153] -----+-N---- \--* LCL_VAR struct V17 tmp15 New refCnts for V17: refCnt = 2, refCntWtd = 2 *** marking local variables in block BB03 (weight=0 ) STMT00017 (IL 0x025... ???) [000096] --CXG+------ * CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 3, refCntWtd = 3 New refCnts for V00: refCnt = 4, refCntWtd = 4 New refCnts for V01: refCnt = 5, refCntWtd = 5 New refCnts for V01: refCnt = 6, refCntWtd = 6 *************** In optAddCopies() *************** Finishing PHASE Mark local vars *************** Starting PHASE Optimize bools *************** In optOptimizeBools() *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize bools *************** Starting PHASE Find oper order *************** In fgFindOperOrder() *************** Finishing PHASE Find oper order *************** Starting PHASE Set block order *************** In fgSetBlockOrder() The biggest BB has 39 tree nodes *************** Finishing PHASE Set block order Trees before Build SSA representation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj BB02 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 (IL 0x000...0x041) N005 ( 16, 16) [000007] -AC-----R--- * ASG ref N004 ( 1, 1) [000006] D------N---- +--* LCL_VAR ref V03 tmp1 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class ***** BB01 STMT00001 (IL ???... ???) N006 ( 8, 9) [000012] -A-XG------- * ASG long N004 ( 4, 4) [000011] ---X---N---- +--* IND long N003 ( 2, 2) [000010] -------N---- | \--* ADD byref N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V03 tmp1 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD long V01 arg1 [+0] Fseq[JobGroup] ***** BB01 STMT00002 (IL ???... ???) N005 ( 16, 16) [000021] -AC-----R--- * ASG ref N004 ( 1, 1) [000020] D------N---- +--* LCL_VAR ref V04 tmp2 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class ***** BB01 STMT00003 (IL ???... ???) N006 ( 8, 9) [000026] -A-XG------- * ASG int N004 ( 4, 4) [000025] ---X---N---- +--* IND int N003 ( 2, 2) [000024] -------N---- | \--* ADD byref N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V04 tmp2 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD int V01 arg1 [+8] Fseq[Version] ***** BB01 STMT00010 (IL ???... ???) N004 ( 11, 8) [000063] -A------R--- * ASG ref N003 ( 3, 2) [000062] D------N---- +--* LCL_VAR ref V13 tmp11 N002 ( 7, 5) [000014] ------------ \--* BOX ref N001 ( 1, 1) [000013] ------------ \--* LCL_VAR ref V03 tmp1 ***** BB01 STMT00011 (IL ???... ???) N004 ( 11, 8) [000068] -A------R--- * ASG ref N003 ( 3, 2) [000067] D------N---- +--* LCL_VAR ref V14 tmp12 N002 ( 7, 5) [000028] ------------ \--* BOX ref N001 ( 1, 1) [000027] ------------ \--* LCL_VAR ref V04 tmp2 ***** BB01 STMT00012 (IL ???... ???) N003 ( 5, 4) [000073] -A------R--- * ASG ref N002 ( 3, 2) [000072] D------N---- +--* LCL_VAR ref V15 tmp13 N001 ( 1, 1) [000071] ------------ \--* CNS_INT ref null ***** BB01 STMT00013 (IL ???... ???) N004 ( 8, 15) [000078] -A--G---R--- * ASG ref N003 ( 3, 2) [000077] D------N---- +--* LCL_VAR ref V16 tmp14 N002 ( 4, 12) [000076] n---G------- \--* IND ref N001 ( 2, 10) [000104] ------------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] ***** BB01 STMT00015 (IL ???... ???) N013 ( 34, 28) [000085] -ACXG---R--- * ASG ref N012 ( 1, 1) [000084] D------N---- +--* LCL_VAR ref V10 tmp8 N011 ( 34, 28) [000054] --CXG------- \--* CALL ref System.String.FormatHelper N007 ( 12, 8) [000109] -c---------- arg2 out+00 +--* FIELD_LIST struct N003 ( 3, 2) [000110] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp11 N004 ( 3, 2) [000111] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp12 N005 ( 3, 2) [000112] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp13 N006 ( 3, 2) [000113] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp14 N009 ( 4, 12) [000106] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000105] ------------ | \--* CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] N010 ( 1, 1) [000046] ------------ arg0 in rdi \--* CNS_INT ref null ***** BB01 STMT00014 (IL ???... ???) N005 ( 16, 9) [000083] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal N003 ( 1, 1) [000082] ------------ arg1 in rsi +--* LCL_VAR ref V10 tmp8 N004 ( 1, 1) [000081] ------------ arg0 in rdi \--* CNS_INT int 3 ***** BB01 STMT00018 (IL 0x025... ???) N004 ( 4, 12) [000098] -A--G---R--- * ASG ref N003 ( 1, 1) [000097] D------N---- +--* LCL_VAR ref V12 tmp10 N002 ( 4, 12) [000032] n---G------- \--* IND ref N001 ( 2, 10) [000116] ------------ \--* CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] ***** BB01 STMT00019 (IL 0x025... ???) N006 ( 4, 4) [000100] -A-XG---R--- * ASG int N005 ( 1, 1) [000099] D------N---- +--* LCL_VAR int V11 tmp9 N004 ( 4, 4) [000034] *--XG------- \--* IND int N003 ( 2, 2) [000118] -------N---- \--* ADD byref N001 ( 1, 1) [000033] ------------ +--* LCL_VAR byref V00 this N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] ***** BB01 STMT00016 (IL 0x025... ???) N007 ( 8, 8) [000091] ---XG------- * JTRUE void N006 ( 6, 6) [000090] N--XG--N-U-- \--* GE int N001 ( 1, 1) [000087] ------------ +--* LCL_VAR int V11 tmp9 N005 ( 4, 4) [000089] ---XG------- \--* IND int N004 ( 2, 2) [000120] -------N---- \--* ADD byref N002 ( 1, 1) [000088] ------------ +--* LCL_VAR ref V12 tmp10 N003 ( 1, 1) [000119] ------------ \--* CNS_INT long 16 field offset Fseq[_size] ------------ BB02 [025..026) (return), preds={BB01} succs={} ***** BB02 STMT00020 (IL ???... ???) N039 ( 65, 73) [000123] -ACXG---R--- * ASG struct (copy) N038 ( 3, 2) [000122] D------N---- +--* LCL_VAR struct V17 tmp15 N037 ( 61, 70) [000040] -ACXG------- \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA N023 ( 18, 22) [000145] -A-XG---R-L- this SETUP +--* ASG ref N022 ( 1, 1) [000144] D------N---- | +--* LCL_VAR ref V19 tmp17 N021 ( 18, 22) [000139] -A-XG------- | \--* COMMA ref N006 ( 4, 4) [000126] -A-XG---R--- | +--* ASG ref N005 ( 1, 1) [000125] D------N---- | | +--* LCL_VAR ref V18 tmp16 N004 ( 4, 4) [000093] ---XG------- | | \--* IND ref N003 ( 2, 2) [000141] -------N---- | | \--* ADD byref N001 ( 1, 1) [000092] ------------ | | +--* LCL_VAR ref V12 tmp10 N002 ( 1, 1) [000140] ------------ | | \--* CNS_INT long 8 field offset Fseq[_items] N020 ( 14, 18) [000138] ---XG------- | \--* COMMA ref N010 ( 8, 11) [000131] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [000094] ------------ | | +--* LCL_VAR int V11 tmp9 N009 ( 3, 3) [000130] ---X-------- | | \--* ARR_LENGTH int N008 ( 1, 1) [000127] ------------ | | \--* LCL_VAR ref V18 tmp16 N019 ( 6, 7) [000095] a---G------- | \--* IND ref N018 ( 5, 6) [000137] -------N---- | \--* ADD byref N011 ( 1, 1) [000128] ------------ | +--* LCL_VAR ref V18 tmp16 N017 ( 4, 5) [000136] -------N---- | \--* ADD long N015 ( 3, 4) [000134] -------N---- | +--* LSH long N013 ( 2, 3) [000132] ------------ | | +--* CAST long <- int N012 ( 1, 1) [000129] i----------- | | | \--* LCL_VAR int V11 tmp9 N014 ( 1, 1) [000133] -------N---- | | \--* CNS_INT long 3 N016 ( 1, 1) [000135] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N029 ( 9, 7) [000044] ---XG------- arg3 out+00 +--* OBJ struct N028 ( 3, 3) [000143] ------------ | \--* ADD byref N026 ( 1, 1) [000037] ------------ | +--* LCL_VAR byref V00 this N027 ( 1, 1) [000142] ------------ | \--* CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] N031 ( 1, 1) [000146] ------------ this in rdi +--* LCL_VAR ref V19 tmp17 N034 ( 6, 8) [000150] -c---------- arg4 rdx,rcx +--* FIELD_LIST struct N032 ( 3, 4) [000151] ------------ ofs 0 | +--* LCL_FLD long V01 arg1 [+0] N033 ( 3, 4) [000152] ------------ ofs 8 | \--* LCL_FLD long V01 arg1 [+8] N035 ( 2, 10) [000124] ------------ arg1 in r11 +--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 N036 ( 2, 10) [000121] ------------ arg2 in rsi \--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 ***** BB02 STMT00007 (IL ???... ???) N002 ( 4, 3) [000045] ----G------- * RETURN struct N001 ( 3, 2) [000153] -------N---- \--* LCL_VAR struct V17 tmp15 ------------ BB03 [025..026) (throw), preds={BB01} succs={} ***** BB03 STMT00017 (IL 0x025... ???) N001 ( 14, 5) [000096] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Build SSA representation *************** In SsaBuilder::Build() [SsaBuilder] Max block count is 4. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj BB02 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty [SsaBuilder] Topologically sorted the graph. [SsaBuilder::ComputeImmediateDom] Inside fgBuildDomTree After computing the Dominance Tree: BB01 : BB03 BB02 *************** In fgLocalVarLiveness() In fgLocalVarLivenessInit Local V01 should not be enregistered because: it is a struct Local V17 should not be enregistered because: it is a struct Tracked variable (14 out of 20) table: V01 arg1 [struct]: refCnt = 6, refCntWtd = 6 V11 tmp9 [ int]: refCnt = 4, refCntWtd = 8 V00 this [ byref]: refCnt = 4, refCntWtd = 4 V03 tmp1 [ ref]: refCnt = 3, refCntWtd = 6 V04 tmp2 [ ref]: refCnt = 3, refCntWtd = 6 V12 tmp10 [ ref]: refCnt = 3, refCntWtd = 6 V18 tmp16 [ ref]: refCnt = 3, refCntWtd = 6 V10 tmp8 [ ref]: refCnt = 2, refCntWtd = 4 V19 tmp17 [ ref]: refCnt = 2, refCntWtd = 4 V13 tmp11 [ ref]: refCnt = 2, refCntWtd = 2 V14 tmp12 [ ref]: refCnt = 2, refCntWtd = 2 V15 tmp13 [ ref]: refCnt = 2, refCntWtd = 2 V16 tmp14 [ ref]: refCnt = 2, refCntWtd = 2 V17 tmp15 [struct]: refCnt = 2, refCntWtd = 2 *************** In fgPerBlockLocalVarLiveness() BB01 USE(2)={V01 V00 } + ByrefExposed + GcHeap DEF(9)={ V11 V03 V04 V12 V10 V13 V14 V15 V16} + ByrefExposed* + GcHeap* BB02 USE(4)={V01 V11 V00 V12 } + ByrefExposed + GcHeap DEF(3)={ V18 V19 V17} + ByrefExposed* + GcHeap* BB03 USE(0)={} + ByrefExposed + GcHeap DEF(0)={} + ByrefExposed* + GcHeap* ** Memory liveness computed, GcHeap states and ByrefExposed states match *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (2)={V01 V00 } + ByrefExposed + GcHeap OUT(4)={V01 V11 V00 V12} + ByrefExposed + GcHeap BB02 IN (4)={V01 V11 V00 V12} + ByrefExposed + GcHeap OUT(0)={ } BB03 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} *************** In optRemoveRedundantZeroInits() *************** In SsaBuilder::InsertPhiFunctions() Inserting phi functions: *************** In SsaBuilder::RenameVariables() After fgSsaBuild: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj BB02 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 (IL 0x000...0x041) N005 ( 16, 16) [000007] -AC-----R--- * ASG ref N004 ( 1, 1) [000006] D------N---- +--* LCL_VAR ref V03 tmp1 d:2 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class ***** BB01 STMT00001 (IL ???... ???) N006 ( 8, 9) [000012] -A-XG------- * ASG long N004 ( 4, 4) [000011] D--X---N---- +--* IND long N003 ( 2, 2) [000010] -------N---- | \--* ADD byref N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V03 tmp1 u:2 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD long V01 arg1 u:1[+0] Fseq[JobGroup] ***** BB01 STMT00002 (IL ???... ???) N005 ( 16, 16) [000021] -AC-----R--- * ASG ref N004 ( 1, 1) [000020] D------N---- +--* LCL_VAR ref V04 tmp2 d:2 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class ***** BB01 STMT00003 (IL ???... ???) N006 ( 8, 9) [000026] -A-XG------- * ASG int N004 ( 4, 4) [000025] D--X---N---- +--* IND int N003 ( 2, 2) [000024] -------N---- | \--* ADD byref N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V04 tmp2 u:2 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD int V01 arg1 u:1[+8] Fseq[Version] ***** BB01 STMT00010 (IL ???... ???) N004 ( 11, 8) [000063] -A------R--- * ASG ref N003 ( 3, 2) [000062] D------N---- +--* LCL_VAR ref V13 tmp11 d:2 N002 ( 7, 5) [000014] ------------ \--* BOX ref N001 ( 1, 1) [000013] ------------ \--* LCL_VAR ref V03 tmp1 u:2 (last use) ***** BB01 STMT00011 (IL ???... ???) N004 ( 11, 8) [000068] -A------R--- * ASG ref N003 ( 3, 2) [000067] D------N---- +--* LCL_VAR ref V14 tmp12 d:2 N002 ( 7, 5) [000028] ------------ \--* BOX ref N001 ( 1, 1) [000027] ------------ \--* LCL_VAR ref V04 tmp2 u:2 (last use) ***** BB01 STMT00012 (IL ???... ???) N003 ( 5, 4) [000073] -A------R--- * ASG ref N002 ( 3, 2) [000072] D------N---- +--* LCL_VAR ref V15 tmp13 d:2 N001 ( 1, 1) [000071] ------------ \--* CNS_INT ref null ***** BB01 STMT00013 (IL ???... ???) N004 ( 8, 15) [000078] -A--G---R--- * ASG ref N003 ( 3, 2) [000077] D------N---- +--* LCL_VAR ref V16 tmp14 d:2 N002 ( 4, 12) [000076] n---G------- \--* IND ref N001 ( 2, 10) [000104] ------------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] ***** BB01 STMT00015 (IL ???... ???) N013 ( 34, 28) [000085] -ACXG---R--- * ASG ref N012 ( 1, 1) [000084] D------N---- +--* LCL_VAR ref V10 tmp8 d:2 N011 ( 34, 28) [000054] --CXG------- \--* CALL ref System.String.FormatHelper N007 ( 12, 8) [000109] -c---------- arg2 out+00 +--* FIELD_LIST struct N003 ( 3, 2) [000110] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp11 u:2 (last use) N004 ( 3, 2) [000111] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp12 u:2 (last use) N005 ( 3, 2) [000112] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp13 u:2 (last use) N006 ( 3, 2) [000113] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp14 u:2 (last use) N009 ( 4, 12) [000106] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000105] ------------ | \--* CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] N010 ( 1, 1) [000046] ------------ arg0 in rdi \--* CNS_INT ref null ***** BB01 STMT00014 (IL ???... ???) N005 ( 16, 9) [000083] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal N003 ( 1, 1) [000082] ------------ arg1 in rsi +--* LCL_VAR ref V10 tmp8 u:2 (last use) N004 ( 1, 1) [000081] ------------ arg0 in rdi \--* CNS_INT int 3 ***** BB01 STMT00018 (IL 0x025... ???) N004 ( 4, 12) [000098] -A--G---R--- * ASG ref N003 ( 1, 1) [000097] D------N---- +--* LCL_VAR ref V12 tmp10 d:2 N002 ( 4, 12) [000032] n---G------- \--* IND ref N001 ( 2, 10) [000116] ------------ \--* CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] ***** BB01 STMT00019 (IL 0x025... ???) N006 ( 4, 4) [000100] -A-XG---R--- * ASG int N005 ( 1, 1) [000099] D------N---- +--* LCL_VAR int V11 tmp9 d:2 N004 ( 4, 4) [000034] *--XG------- \--* IND int N003 ( 2, 2) [000118] -------N---- \--* ADD byref N001 ( 1, 1) [000033] ------------ +--* LCL_VAR byref V00 this u:1 N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] ***** BB01 STMT00016 (IL 0x025... ???) N007 ( 8, 8) [000091] ---XG------- * JTRUE void N006 ( 6, 6) [000090] N--XG--N-U-- \--* GE int N001 ( 1, 1) [000087] ------------ +--* LCL_VAR int V11 tmp9 u:2 N005 ( 4, 4) [000089] ---XG------- \--* IND int N004 ( 2, 2) [000120] -------N---- \--* ADD byref N002 ( 1, 1) [000088] ------------ +--* LCL_VAR ref V12 tmp10 u:2 N003 ( 1, 1) [000119] ------------ \--* CNS_INT long 16 field offset Fseq[_size] ------------ BB02 [025..026) (return), preds={BB01} succs={} ***** BB02 STMT00020 (IL ???... ???) N039 ( 65, 73) [000123] -ACXG---R--- * ASG struct (copy) N038 ( 3, 2) [000122] D------N---- +--* LCL_VAR struct V17 tmp15 d:2 N037 ( 61, 70) [000040] -ACXG------- \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA N023 ( 18, 22) [000145] -A-XG---R-L- this SETUP +--* ASG ref N022 ( 1, 1) [000144] D------N---- | +--* LCL_VAR ref V19 tmp17 d:2 N021 ( 18, 22) [000139] -A-XG------- | \--* COMMA ref N006 ( 4, 4) [000126] -A-XG---R--- | +--* ASG ref N005 ( 1, 1) [000125] D------N---- | | +--* LCL_VAR ref V18 tmp16 d:2 N004 ( 4, 4) [000093] ---XG------- | | \--* IND ref N003 ( 2, 2) [000141] -------N---- | | \--* ADD byref N001 ( 1, 1) [000092] ------------ | | +--* LCL_VAR ref V12 tmp10 u:2 (last use) N002 ( 1, 1) [000140] ------------ | | \--* CNS_INT long 8 field offset Fseq[_items] N020 ( 14, 18) [000138] ---XG------- | \--* COMMA ref N010 ( 8, 11) [000131] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [000094] ------------ | | +--* LCL_VAR int V11 tmp9 u:2 N009 ( 3, 3) [000130] ---X-------- | | \--* ARR_LENGTH int N008 ( 1, 1) [000127] ------------ | | \--* LCL_VAR ref V18 tmp16 u:2 N019 ( 6, 7) [000095] a---G------- | \--* IND ref N018 ( 5, 6) [000137] -------N---- | \--* ADD byref N011 ( 1, 1) [000128] ------------ | +--* LCL_VAR ref V18 tmp16 u:2 (last use) N017 ( 4, 5) [000136] -------N---- | \--* ADD long N015 ( 3, 4) [000134] -------N---- | +--* LSH long N013 ( 2, 3) [000132] ------------ | | +--* CAST long <- int N012 ( 1, 1) [000129] i----------- | | | \--* LCL_VAR int V11 tmp9 u:2 (last use) N014 ( 1, 1) [000133] -------N---- | | \--* CNS_INT long 3 N016 ( 1, 1) [000135] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N029 ( 9, 7) [000044] ---XG------- arg3 out+00 +--* OBJ struct N028 ( 3, 3) [000143] ------------ | \--* ADD byref N026 ( 1, 1) [000037] ------------ | +--* LCL_VAR byref V00 this u:1 (last use) N027 ( 1, 1) [000142] ------------ | \--* CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] N031 ( 1, 1) [000146] ------------ this in rdi +--* LCL_VAR ref V19 tmp17 u:2 (last use) N034 ( 6, 8) [000150] -c---------- arg4 rdx,rcx +--* FIELD_LIST struct N032 ( 3, 4) [000151] ------------ ofs 0 | +--* LCL_FLD long V01 arg1 u:1[+0] N033 ( 3, 4) [000152] ------------ ofs 8 | \--* LCL_FLD long V01 arg1 u:1[+8] (last use) N035 ( 2, 10) [000124] ------------ arg1 in r11 +--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 N036 ( 2, 10) [000121] ------------ arg2 in rsi \--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 ***** BB02 STMT00007 (IL ???... ???) N002 ( 4, 3) [000045] ----G------- * RETURN struct N001 ( 3, 2) [000153] -------N---- \--* LCL_VAR struct V17 tmp15 u:2 (last use) ------------ BB03 [025..026) (throw), preds={BB01} succs={} ***** BB03 STMT00017 (IL 0x025... ???) N001 ( 14, 5) [000096] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException ------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Build SSA representation Trees after Build SSA representation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj BB02 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 (IL 0x000...0x041) N005 ( 16, 16) [000007] -AC-----R--- * ASG ref N004 ( 1, 1) [000006] D------N---- +--* LCL_VAR ref V03 tmp1 d:2 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class ***** BB01 STMT00001 (IL ???... ???) N006 ( 8, 9) [000012] -A-XG------- * ASG long N004 ( 4, 4) [000011] D--X---N---- +--* IND long N003 ( 2, 2) [000010] -------N---- | \--* ADD byref N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V03 tmp1 u:2 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD long V01 arg1 u:1[+0] Fseq[JobGroup] ***** BB01 STMT00002 (IL ???... ???) N005 ( 16, 16) [000021] -AC-----R--- * ASG ref N004 ( 1, 1) [000020] D------N---- +--* LCL_VAR ref V04 tmp2 d:2 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class ***** BB01 STMT00003 (IL ???... ???) N006 ( 8, 9) [000026] -A-XG------- * ASG int N004 ( 4, 4) [000025] D--X---N---- +--* IND int N003 ( 2, 2) [000024] -------N---- | \--* ADD byref N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V04 tmp2 u:2 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD int V01 arg1 u:1[+8] Fseq[Version] ***** BB01 STMT00010 (IL ???... ???) N004 ( 11, 8) [000063] -A------R--- * ASG ref N003 ( 3, 2) [000062] D------N---- +--* LCL_VAR ref V13 tmp11 d:2 N002 ( 7, 5) [000014] ------------ \--* BOX ref N001 ( 1, 1) [000013] ------------ \--* LCL_VAR ref V03 tmp1 u:2 (last use) ***** BB01 STMT00011 (IL ???... ???) N004 ( 11, 8) [000068] -A------R--- * ASG ref N003 ( 3, 2) [000067] D------N---- +--* LCL_VAR ref V14 tmp12 d:2 N002 ( 7, 5) [000028] ------------ \--* BOX ref N001 ( 1, 1) [000027] ------------ \--* LCL_VAR ref V04 tmp2 u:2 (last use) ***** BB01 STMT00012 (IL ???... ???) N003 ( 5, 4) [000073] -A------R--- * ASG ref N002 ( 3, 2) [000072] D------N---- +--* LCL_VAR ref V15 tmp13 d:2 N001 ( 1, 1) [000071] ------------ \--* CNS_INT ref null ***** BB01 STMT00013 (IL ???... ???) N004 ( 8, 15) [000078] -A--G---R--- * ASG ref N003 ( 3, 2) [000077] D------N---- +--* LCL_VAR ref V16 tmp14 d:2 N002 ( 4, 12) [000076] n---G------- \--* IND ref N001 ( 2, 10) [000104] ------------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] ***** BB01 STMT00015 (IL ???... ???) N013 ( 34, 28) [000085] -ACXG---R--- * ASG ref N012 ( 1, 1) [000084] D------N---- +--* LCL_VAR ref V10 tmp8 d:2 N011 ( 34, 28) [000054] --CXG------- \--* CALL ref System.String.FormatHelper N007 ( 12, 8) [000109] -c---------- arg2 out+00 +--* FIELD_LIST struct N003 ( 3, 2) [000110] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp11 u:2 (last use) N004 ( 3, 2) [000111] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp12 u:2 (last use) N005 ( 3, 2) [000112] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp13 u:2 (last use) N006 ( 3, 2) [000113] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp14 u:2 (last use) N009 ( 4, 12) [000106] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000105] ------------ | \--* CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] N010 ( 1, 1) [000046] ------------ arg0 in rdi \--* CNS_INT ref null ***** BB01 STMT00014 (IL ???... ???) N005 ( 16, 9) [000083] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal N003 ( 1, 1) [000082] ------------ arg1 in rsi +--* LCL_VAR ref V10 tmp8 u:2 (last use) N004 ( 1, 1) [000081] ------------ arg0 in rdi \--* CNS_INT int 3 ***** BB01 STMT00018 (IL 0x025... ???) N004 ( 4, 12) [000098] -A--G---R--- * ASG ref N003 ( 1, 1) [000097] D------N---- +--* LCL_VAR ref V12 tmp10 d:2 N002 ( 4, 12) [000032] n---G------- \--* IND ref N001 ( 2, 10) [000116] ------------ \--* CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] ***** BB01 STMT00019 (IL 0x025... ???) N006 ( 4, 4) [000100] -A-XG---R--- * ASG int N005 ( 1, 1) [000099] D------N---- +--* LCL_VAR int V11 tmp9 d:2 N004 ( 4, 4) [000034] *--XG------- \--* IND int N003 ( 2, 2) [000118] -------N---- \--* ADD byref N001 ( 1, 1) [000033] ------------ +--* LCL_VAR byref V00 this u:1 N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] ***** BB01 STMT00016 (IL 0x025... ???) N007 ( 8, 8) [000091] ---XG------- * JTRUE void N006 ( 6, 6) [000090] N--XG--N-U-- \--* GE int N001 ( 1, 1) [000087] ------------ +--* LCL_VAR int V11 tmp9 u:2 N005 ( 4, 4) [000089] ---XG------- \--* IND int N004 ( 2, 2) [000120] -------N---- \--* ADD byref N002 ( 1, 1) [000088] ------------ +--* LCL_VAR ref V12 tmp10 u:2 N003 ( 1, 1) [000119] ------------ \--* CNS_INT long 16 field offset Fseq[_size] ------------ BB02 [025..026) (return), preds={BB01} succs={} ***** BB02 STMT00020 (IL ???... ???) N039 ( 65, 73) [000123] -ACXG---R--- * ASG struct (copy) N038 ( 3, 2) [000122] D------N---- +--* LCL_VAR struct V17 tmp15 d:2 N037 ( 61, 70) [000040] -ACXG------- \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA N023 ( 18, 22) [000145] -A-XG---R-L- this SETUP +--* ASG ref N022 ( 1, 1) [000144] D------N---- | +--* LCL_VAR ref V19 tmp17 d:2 N021 ( 18, 22) [000139] -A-XG------- | \--* COMMA ref N006 ( 4, 4) [000126] -A-XG---R--- | +--* ASG ref N005 ( 1, 1) [000125] D------N---- | | +--* LCL_VAR ref V18 tmp16 d:2 N004 ( 4, 4) [000093] ---XG------- | | \--* IND ref N003 ( 2, 2) [000141] -------N---- | | \--* ADD byref N001 ( 1, 1) [000092] ------------ | | +--* LCL_VAR ref V12 tmp10 u:2 (last use) N002 ( 1, 1) [000140] ------------ | | \--* CNS_INT long 8 field offset Fseq[_items] N020 ( 14, 18) [000138] ---XG------- | \--* COMMA ref N010 ( 8, 11) [000131] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [000094] ------------ | | +--* LCL_VAR int V11 tmp9 u:2 N009 ( 3, 3) [000130] ---X-------- | | \--* ARR_LENGTH int N008 ( 1, 1) [000127] ------------ | | \--* LCL_VAR ref V18 tmp16 u:2 N019 ( 6, 7) [000095] a---G------- | \--* IND ref N018 ( 5, 6) [000137] -------N---- | \--* ADD byref N011 ( 1, 1) [000128] ------------ | +--* LCL_VAR ref V18 tmp16 u:2 (last use) N017 ( 4, 5) [000136] -------N---- | \--* ADD long N015 ( 3, 4) [000134] -------N---- | +--* LSH long N013 ( 2, 3) [000132] ------------ | | +--* CAST long <- int N012 ( 1, 1) [000129] i----------- | | | \--* LCL_VAR int V11 tmp9 u:2 (last use) N014 ( 1, 1) [000133] -------N---- | | \--* CNS_INT long 3 N016 ( 1, 1) [000135] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N029 ( 9, 7) [000044] ---XG------- arg3 out+00 +--* OBJ struct N028 ( 3, 3) [000143] ------------ | \--* ADD byref N026 ( 1, 1) [000037] ------------ | +--* LCL_VAR byref V00 this u:1 (last use) N027 ( 1, 1) [000142] ------------ | \--* CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] N031 ( 1, 1) [000146] ------------ this in rdi +--* LCL_VAR ref V19 tmp17 u:2 (last use) N034 ( 6, 8) [000150] -c---------- arg4 rdx,rcx +--* FIELD_LIST struct N032 ( 3, 4) [000151] ------------ ofs 0 | +--* LCL_FLD long V01 arg1 u:1[+0] N033 ( 3, 4) [000152] ------------ ofs 8 | \--* LCL_FLD long V01 arg1 u:1[+8] (last use) N035 ( 2, 10) [000124] ------------ arg1 in r11 +--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 N036 ( 2, 10) [000121] ------------ arg2 in rsi \--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 ***** BB02 STMT00007 (IL ???... ???) N002 ( 4, 3) [000045] ----G------- * RETURN struct N001 ( 3, 2) [000153] -------N---- \--* LCL_VAR struct V17 tmp15 u:2 (last use) ------------ BB03 [025..026) (throw), preds={BB01} succs={} ***** BB03 STMT00017 (IL 0x025... ???) N001 ( 14, 5) [000096] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Early Value Propagation *************** In optEarlyProp() After optEarlyProp: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj BB02 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 (IL 0x000...0x041) N005 ( 16, 16) [000007] -AC-----R--- * ASG ref N004 ( 1, 1) [000006] D------N---- +--* LCL_VAR ref V03 tmp1 d:2 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class ***** BB01 STMT00001 (IL ???... ???) N006 ( 8, 9) [000012] -A-XG------- * ASG long N004 ( 4, 4) [000011] D--X---N---- +--* IND long N003 ( 2, 2) [000010] -------N---- | \--* ADD byref N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V03 tmp1 u:2 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD long V01 arg1 u:1[+0] Fseq[JobGroup] ***** BB01 STMT00002 (IL ???... ???) N005 ( 16, 16) [000021] -AC-----R--- * ASG ref N004 ( 1, 1) [000020] D------N---- +--* LCL_VAR ref V04 tmp2 d:2 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class ***** BB01 STMT00003 (IL ???... ???) N006 ( 8, 9) [000026] -A-XG------- * ASG int N004 ( 4, 4) [000025] D--X---N---- +--* IND int N003 ( 2, 2) [000024] -------N---- | \--* ADD byref N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V04 tmp2 u:2 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD int V01 arg1 u:1[+8] Fseq[Version] ***** BB01 STMT00010 (IL ???... ???) N004 ( 11, 8) [000063] -A------R--- * ASG ref N003 ( 3, 2) [000062] D------N---- +--* LCL_VAR ref V13 tmp11 d:2 N002 ( 7, 5) [000014] ------------ \--* BOX ref N001 ( 1, 1) [000013] ------------ \--* LCL_VAR ref V03 tmp1 u:2 (last use) ***** BB01 STMT00011 (IL ???... ???) N004 ( 11, 8) [000068] -A------R--- * ASG ref N003 ( 3, 2) [000067] D------N---- +--* LCL_VAR ref V14 tmp12 d:2 N002 ( 7, 5) [000028] ------------ \--* BOX ref N001 ( 1, 1) [000027] ------------ \--* LCL_VAR ref V04 tmp2 u:2 (last use) ***** BB01 STMT00012 (IL ???... ???) N003 ( 5, 4) [000073] -A------R--- * ASG ref N002 ( 3, 2) [000072] D------N---- +--* LCL_VAR ref V15 tmp13 d:2 N001 ( 1, 1) [000071] ------------ \--* CNS_INT ref null ***** BB01 STMT00013 (IL ???... ???) N004 ( 8, 15) [000078] -A--G---R--- * ASG ref N003 ( 3, 2) [000077] D------N---- +--* LCL_VAR ref V16 tmp14 d:2 N002 ( 4, 12) [000076] n---G------- \--* IND ref N001 ( 2, 10) [000104] ------------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] ***** BB01 STMT00015 (IL ???... ???) N013 ( 34, 28) [000085] -ACXG---R--- * ASG ref N012 ( 1, 1) [000084] D------N---- +--* LCL_VAR ref V10 tmp8 d:2 N011 ( 34, 28) [000054] --CXG------- \--* CALL ref System.String.FormatHelper N007 ( 12, 8) [000109] -c---------- arg2 out+00 +--* FIELD_LIST struct N003 ( 3, 2) [000110] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp11 u:2 (last use) N004 ( 3, 2) [000111] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp12 u:2 (last use) N005 ( 3, 2) [000112] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp13 u:2 (last use) N006 ( 3, 2) [000113] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp14 u:2 (last use) N009 ( 4, 12) [000106] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000105] ------------ | \--* CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] N010 ( 1, 1) [000046] ------------ arg0 in rdi \--* CNS_INT ref null ***** BB01 STMT00014 (IL ???... ???) N005 ( 16, 9) [000083] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal N003 ( 1, 1) [000082] ------------ arg1 in rsi +--* LCL_VAR ref V10 tmp8 u:2 (last use) N004 ( 1, 1) [000081] ------------ arg0 in rdi \--* CNS_INT int 3 ***** BB01 STMT00018 (IL 0x025... ???) N004 ( 4, 12) [000098] -A--G---R--- * ASG ref N003 ( 1, 1) [000097] D------N---- +--* LCL_VAR ref V12 tmp10 d:2 N002 ( 4, 12) [000032] n---G------- \--* IND ref N001 ( 2, 10) [000116] ------------ \--* CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] ***** BB01 STMT00019 (IL 0x025... ???) N006 ( 4, 4) [000100] -A-XG---R--- * ASG int N005 ( 1, 1) [000099] D------N---- +--* LCL_VAR int V11 tmp9 d:2 N004 ( 4, 4) [000034] *--XG------- \--* IND int N003 ( 2, 2) [000118] -------N---- \--* ADD byref N001 ( 1, 1) [000033] ------------ +--* LCL_VAR byref V00 this u:1 N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] ***** BB01 STMT00016 (IL 0x025... ???) N007 ( 8, 8) [000091] ---XG------- * JTRUE void N006 ( 6, 6) [000090] N--XG--N-U-- \--* GE int N001 ( 1, 1) [000087] ------------ +--* LCL_VAR int V11 tmp9 u:2 N005 ( 4, 4) [000089] ---XG------- \--* IND int N004 ( 2, 2) [000120] -------N---- \--* ADD byref N002 ( 1, 1) [000088] ------------ +--* LCL_VAR ref V12 tmp10 u:2 N003 ( 1, 1) [000119] ------------ \--* CNS_INT long 16 field offset Fseq[_size] ------------ BB02 [025..026) (return), preds={BB01} succs={} ***** BB02 STMT00020 (IL ???... ???) N039 ( 65, 73) [000123] -ACXG---R--- * ASG struct (copy) N038 ( 3, 2) [000122] D------N---- +--* LCL_VAR struct V17 tmp15 d:2 N037 ( 61, 70) [000040] -ACXG------- \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA N023 ( 18, 22) [000145] -A-XG---R-L- this SETUP +--* ASG ref N022 ( 1, 1) [000144] D------N---- | +--* LCL_VAR ref V19 tmp17 d:2 N021 ( 18, 22) [000139] -A-XG------- | \--* COMMA ref N006 ( 4, 4) [000126] -A-XG---R--- | +--* ASG ref N005 ( 1, 1) [000125] D------N---- | | +--* LCL_VAR ref V18 tmp16 d:2 N004 ( 4, 4) [000093] ---XG------- | | \--* IND ref N003 ( 2, 2) [000141] -------N---- | | \--* ADD byref N001 ( 1, 1) [000092] ------------ | | +--* LCL_VAR ref V12 tmp10 u:2 (last use) N002 ( 1, 1) [000140] ------------ | | \--* CNS_INT long 8 field offset Fseq[_items] N020 ( 14, 18) [000138] ---XG------- | \--* COMMA ref N010 ( 8, 11) [000131] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [000094] ------------ | | +--* LCL_VAR int V11 tmp9 u:2 N009 ( 3, 3) [000130] ---X-------- | | \--* ARR_LENGTH int N008 ( 1, 1) [000127] ------------ | | \--* LCL_VAR ref V18 tmp16 u:2 N019 ( 6, 7) [000095] a---G------- | \--* IND ref N018 ( 5, 6) [000137] -------N---- | \--* ADD byref N011 ( 1, 1) [000128] ------------ | +--* LCL_VAR ref V18 tmp16 u:2 (last use) N017 ( 4, 5) [000136] -------N---- | \--* ADD long N015 ( 3, 4) [000134] -------N---- | +--* LSH long N013 ( 2, 3) [000132] ------------ | | +--* CAST long <- int N012 ( 1, 1) [000129] i----------- | | | \--* LCL_VAR int V11 tmp9 u:2 (last use) N014 ( 1, 1) [000133] -------N---- | | \--* CNS_INT long 3 N016 ( 1, 1) [000135] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N029 ( 9, 7) [000044] ---XG------- arg3 out+00 +--* OBJ struct N028 ( 3, 3) [000143] ------------ | \--* ADD byref N026 ( 1, 1) [000037] ------------ | +--* LCL_VAR byref V00 this u:1 (last use) N027 ( 1, 1) [000142] ------------ | \--* CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] N031 ( 1, 1) [000146] ------------ this in rdi +--* LCL_VAR ref V19 tmp17 u:2 (last use) N034 ( 6, 8) [000150] -c---------- arg4 rdx,rcx +--* FIELD_LIST struct N032 ( 3, 4) [000151] ------------ ofs 0 | +--* LCL_FLD long V01 arg1 u:1[+0] N033 ( 3, 4) [000152] ------------ ofs 8 | \--* LCL_FLD long V01 arg1 u:1[+8] (last use) N035 ( 2, 10) [000124] ------------ arg1 in r11 +--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 N036 ( 2, 10) [000121] ------------ arg2 in rsi \--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 ***** BB02 STMT00007 (IL ???... ???) N002 ( 4, 3) [000045] ----G------- * RETURN struct N001 ( 3, 2) [000153] -------N---- \--* LCL_VAR struct V17 tmp15 u:2 (last use) ------------ BB03 [025..026) (throw), preds={BB01} succs={} ***** BB03 STMT00017 (IL 0x025... ???) N001 ( 14, 5) [000096] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException ------------------------------------------------------------------------------------------------------------------- *************** Finishing PHASE Early Value Propagation *************** Starting PHASE Do value numbering *************** In fgValueNumber() Memory Initial Value in BB01 is: $100 The SSA definition for ByrefExposed (#1) at start of BB01 is $100 {InitVal($42)} The SSA definition for GcHeap (#1) at start of BB01 is $100 {InitVal($42)} ***** BB01, STMT00000(before) N005 ( 16, 16) [000007] -AC-----R--- * ASG ref N004 ( 1, 1) [000006] D------N---- +--* LCL_VAR ref V03 tmp1 d:2 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class N001 [000102] ARGPLACE => $140 {140} N002 [000004] CNS_INT(h) 0x7f6678c127f0 class => $180 {Hnd const: 0x00007F6678C127F0} VN of ARGPLACE tree [000102] updated to $180 {Hnd const: 0x00007F6678C127F0} N003 [000005] CALL help => $200 {JitNew($180, $1c0)} N004 [000006] LCL_VAR V03 tmp1 d:2 => $200 {JitNew($180, $1c0)} N005 [000007] ASG => $200 {JitNew($180, $1c0)} ***** BB01, STMT00000(after) N005 ( 16, 16) [000007] -AC-----R--- * ASG ref $200 N004 ( 1, 1) [000006] D------N---- +--* LCL_VAR ref V03 tmp1 d:2 $200 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class $180 --------- ***** BB01, STMT00001(before) N006 ( 8, 9) [000012] -A-XG------- * ASG long N004 ( 4, 4) [000011] D--X---N---- +--* IND long N003 ( 2, 2) [000010] -------N---- | \--* ADD byref N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V03 tmp1 u:2 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD long V01 arg1 u:1[+0] Fseq[JobGroup] N001 [000008] LCL_VAR V03 tmp1 u:2 => $200 {JitNew($180, $1c0)} N002 [000009] CNS_INT 8 => $240 {LngCns: 8} N003 [000010] ADD => $280 {ADD($200, $240)} VNApplySelectors: VNForHandle(JobGroup) is $181, fieldType is long VNForMapSelect($c0, $181):long returns $2c0 {$c0[$181]} VNApplySelectors: VNForHandle(JobGroup) is $181, fieldType is long VNForMapSelect($c0, $181):long returns $2c0 {$c0[$181]} N005 [000003] LCL_FLD V01 arg1 u:1[+0] Fseq[JobGroup] => $2c0 {$c0[$181]} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000012] to VN: $1c2. N006 [000012] ASG => $VN.Void ***** BB01, STMT00001(after) N006 ( 8, 9) [000012] -A-XG------- * ASG long $VN.Void N004 ( 4, 4) [000011] D--X---N---- +--* IND long $2c0 N003 ( 2, 2) [000010] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V03 tmp1 u:2 $200 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD long V01 arg1 u:1[+0] Fseq[JobGroup] $2c0 --------- ***** BB01, STMT00002(before) N005 ( 16, 16) [000021] -AC-----R--- * ASG ref N004 ( 1, 1) [000020] D------N---- +--* LCL_VAR ref V04 tmp2 d:2 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class N001 [000103] ARGPLACE => $141 {141} N002 [000018] CNS_INT(h) 0x7f6678beb1c0 class => $182 {Hnd const: 0x00007F6678BEB1C0} VN of ARGPLACE tree [000103] updated to $182 {Hnd const: 0x00007F6678BEB1C0} N003 [000019] CALL help => $201 {JitNew($182, $1c3)} N004 [000020] LCL_VAR V04 tmp2 d:2 => $201 {JitNew($182, $1c3)} N005 [000021] ASG => $201 {JitNew($182, $1c3)} ***** BB01, STMT00002(after) N005 ( 16, 16) [000021] -AC-----R--- * ASG ref $201 N004 ( 1, 1) [000020] D------N---- +--* LCL_VAR ref V04 tmp2 d:2 $201 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class $182 --------- ***** BB01, STMT00003(before) N006 ( 8, 9) [000026] -A-XG------- * ASG int N004 ( 4, 4) [000025] D--X---N---- +--* IND int N003 ( 2, 2) [000024] -------N---- | \--* ADD byref N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V04 tmp2 u:2 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD int V01 arg1 u:1[+8] Fseq[Version] N001 [000022] LCL_VAR V04 tmp2 u:2 => $201 {JitNew($182, $1c3)} N002 [000023] CNS_INT 8 => $240 {LngCns: 8} N003 [000024] ADD => $281 {ADD($201, $240)} VNApplySelectors: VNForHandle(Version) is $183, fieldType is int VNForMapSelect($c0, $183):int returns $300 {$c0[$183]} VNApplySelectors: VNForHandle(Version) is $183, fieldType is int VNForMapSelect($c0, $183):int returns $300 {$c0[$183]} N005 [000017] LCL_FLD V01 arg1 u:1[+8] Fseq[Version] => $300 {$c0[$183]} fgCurMemoryVN[GcHeap] assigned for assign-of-IND at [000026] to VN: $1c5. N006 [000026] ASG => $VN.Void ***** BB01, STMT00003(after) N006 ( 8, 9) [000026] -A-XG------- * ASG int $VN.Void N004 ( 4, 4) [000025] D--X---N---- +--* IND int $300 N003 ( 2, 2) [000024] -------N---- | \--* ADD byref $281 N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V04 tmp2 u:2 $201 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD int V01 arg1 u:1[+8] Fseq[Version] $300 --------- ***** BB01, STMT00010(before) N004 ( 11, 8) [000063] -A------R--- * ASG ref N003 ( 3, 2) [000062] D------N---- +--* LCL_VAR ref V13 tmp11 d:2 N002 ( 7, 5) [000014] ------------ \--* BOX ref N001 ( 1, 1) [000013] ------------ \--* LCL_VAR ref V03 tmp1 u:2 (last use) N001 [000013] LCL_VAR V03 tmp1 u:2 (last use) => $200 {JitNew($180, $1c0)} N002 [000014] BOX => $200 {JitNew($180, $1c0)} N003 [000062] LCL_VAR V13 tmp11 d:2 => $200 {JitNew($180, $1c0)} N004 [000063] ASG => $200 {JitNew($180, $1c0)} ***** BB01, STMT00010(after) N004 ( 11, 8) [000063] -A------R--- * ASG ref $200 N003 ( 3, 2) [000062] D------N---- +--* LCL_VAR ref V13 tmp11 d:2 $200 N002 ( 7, 5) [000014] ------------ \--* BOX ref $200 N001 ( 1, 1) [000013] ------------ \--* LCL_VAR ref V03 tmp1 u:2 (last use) $200 --------- ***** BB01, STMT00011(before) N004 ( 11, 8) [000068] -A------R--- * ASG ref N003 ( 3, 2) [000067] D------N---- +--* LCL_VAR ref V14 tmp12 d:2 N002 ( 7, 5) [000028] ------------ \--* BOX ref N001 ( 1, 1) [000027] ------------ \--* LCL_VAR ref V04 tmp2 u:2 (last use) N001 [000027] LCL_VAR V04 tmp2 u:2 (last use) => $201 {JitNew($182, $1c3)} N002 [000028] BOX => $201 {JitNew($182, $1c3)} N003 [000067] LCL_VAR V14 tmp12 d:2 => $201 {JitNew($182, $1c3)} N004 [000068] ASG => $201 {JitNew($182, $1c3)} ***** BB01, STMT00011(after) N004 ( 11, 8) [000068] -A------R--- * ASG ref $201 N003 ( 3, 2) [000067] D------N---- +--* LCL_VAR ref V14 tmp12 d:2 $201 N002 ( 7, 5) [000028] ------------ \--* BOX ref $201 N001 ( 1, 1) [000027] ------------ \--* LCL_VAR ref V04 tmp2 u:2 (last use) $201 --------- ***** BB01, STMT00012(before) N003 ( 5, 4) [000073] -A------R--- * ASG ref N002 ( 3, 2) [000072] D------N---- +--* LCL_VAR ref V15 tmp13 d:2 N001 ( 1, 1) [000071] ------------ \--* CNS_INT ref null N001 [000071] CNS_INT null => $VN.Null N002 [000072] LCL_VAR V15 tmp13 d:2 => $VN.Null N003 [000073] ASG => $VN.Null ***** BB01, STMT00012(after) N003 ( 5, 4) [000073] -A------R--- * ASG ref $VN.Null N002 ( 3, 2) [000072] D------N---- +--* LCL_VAR ref V15 tmp13 d:2 $VN.Null N001 ( 1, 1) [000071] ------------ \--* CNS_INT ref null $VN.Null --------- ***** BB01, STMT00013(before) N004 ( 8, 15) [000078] -A--G---R--- * ASG ref N003 ( 3, 2) [000077] D------N---- +--* LCL_VAR ref V16 tmp14 d:2 N002 ( 4, 12) [000076] n---G------- \--* IND ref N001 ( 2, 10) [000104] ------------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] N001 [000104] CNS_INT(h) 0x7f6663fff340 static Fseq[s_twoArgArray] => $184 {Hnd const: 0x00007F6663FFF340} N002 [000076] IND => N003 [000077] LCL_VAR V16 tmp14 d:2 => N004 [000078] ASG => ***** BB01, STMT00013(after) N004 ( 8, 15) [000078] -A--G---R--- * ASG ref N003 ( 3, 2) [000077] D------N---- +--* LCL_VAR ref V16 tmp14 d:2 N002 ( 4, 12) [000076] n---G------- \--* IND ref N001 ( 2, 10) [000104] ------------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 --------- ***** BB01, STMT00015(before) N013 ( 34, 28) [000085] -ACXG---R--- * ASG ref N012 ( 1, 1) [000084] D------N---- +--* LCL_VAR ref V10 tmp8 d:2 N011 ( 34, 28) [000054] --CXG------- \--* CALL ref System.String.FormatHelper N007 ( 12, 8) [000109] -c---------- arg2 out+00 +--* FIELD_LIST struct N003 ( 3, 2) [000110] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp11 u:2 (last use) N004 ( 3, 2) [000111] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp12 u:2 (last use) N005 ( 3, 2) [000112] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp13 u:2 (last use) N006 ( 3, 2) [000113] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp14 u:2 (last use) N009 ( 4, 12) [000106] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000105] ------------ | \--* CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] N010 ( 1, 1) [000046] ------------ arg0 in rdi \--* CNS_INT ref null N001 [000108] ARGPLACE => $1cb {1cb} N002 [000107] ARGPLACE => $1cc {1cc} N003 [000110] LCL_VAR V13 tmp11 u:2 (last use) => $200 {JitNew($180, $1c0)} N004 [000111] LCL_VAR V14 tmp12 u:2 (last use) => $201 {JitNew($182, $1c3)} N005 [000112] LCL_VAR V15 tmp13 u:2 (last use) => $VN.Null N006 [000113] LCL_VAR V16 tmp14 u:2 (last use) => N007 [000109] FIELD_LIST => $380 {380} N008 [000105] CNS_INT(h) 0x64008A98 [ICON_STR_HDL] => $185 {Hnd const: 0x00007F6664008A98} N009 [000106] IND => N010 [000046] CNS_INT null => $VN.Null VN of ARGPLACE tree [000108] updated to $VN.Null VN of ARGPLACE tree [000107] updated to fgCurMemoryVN[GcHeap] assigned for CALL at [000054] to VN: $1cf. N011 [000054] CALL => $1ce {1ce} N012 [000084] LCL_VAR V10 tmp8 d:2 => $1ce {1ce} N013 [000085] ASG => $1ce {1ce} ***** BB01, STMT00015(after) N013 ( 34, 28) [000085] -ACXG---R--- * ASG ref $1ce N012 ( 1, 1) [000084] D------N---- +--* LCL_VAR ref V10 tmp8 d:2 $1ce N011 ( 34, 28) [000054] --CXG------- \--* CALL ref System.String.FormatHelper $1ce N007 ( 12, 8) [000109] -c---------- arg2 out+00 +--* FIELD_LIST struct $380 N003 ( 3, 2) [000110] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp11 u:2 (last use) $200 N004 ( 3, 2) [000111] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp12 u:2 (last use) $201 N005 ( 3, 2) [000112] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp13 u:2 (last use) $VN.Null N006 ( 3, 2) [000113] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp14 u:2 (last use) N009 ( 4, 12) [000106] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000105] ------------ | \--* CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] $185 N010 ( 1, 1) [000046] ------------ arg0 in rdi \--* CNS_INT ref null $VN.Null --------- ***** BB01, STMT00014(before) N005 ( 16, 9) [000083] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal N003 ( 1, 1) [000082] ------------ arg1 in rsi +--* LCL_VAR ref V10 tmp8 u:2 (last use) N004 ( 1, 1) [000081] ------------ arg0 in rdi \--* CNS_INT int 3 N001 [000115] ARGPLACE => $3c0 {3c0} N002 [000114] ARGPLACE => $1d1 {1d1} N003 [000082] LCL_VAR V10 tmp8 u:2 (last use) => $1ce {1ce} N004 [000081] CNS_INT 3 => $44 {IntCns 3} VN of ARGPLACE tree [000115] updated to $44 {IntCns 3} VN of ARGPLACE tree [000114] updated to $1ce {1ce} fgCurMemoryVN[GcHeap] assigned for CALL at [000083] to VN: $1d2. N005 [000083] CALL => $VN.Void ***** BB01, STMT00014(after) N005 ( 16, 9) [000083] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void N003 ( 1, 1) [000082] ------------ arg1 in rsi +--* LCL_VAR ref V10 tmp8 u:2 (last use) $1ce N004 ( 1, 1) [000081] ------------ arg0 in rdi \--* CNS_INT int 3 $44 --------- ***** BB01, STMT00018(before) N004 ( 4, 12) [000098] -A--G---R--- * ASG ref N003 ( 1, 1) [000097] D------N---- +--* LCL_VAR ref V12 tmp10 d:2 N002 ( 4, 12) [000032] n---G------- \--* IND ref N001 ( 2, 10) [000116] ------------ \--* CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] N001 [000116] CNS_INT(h) 0x7f6664004668 static Fseq[s_NetworkInterfaces] => $186 {Hnd const: 0x00007F6664004668} N002 [000032] IND => N003 [000097] LCL_VAR V12 tmp10 d:2 => N004 [000098] ASG => ***** BB01, STMT00018(after) N004 ( 4, 12) [000098] -A--G---R--- * ASG ref N003 ( 1, 1) [000097] D------N---- +--* LCL_VAR ref V12 tmp10 d:2 N002 ( 4, 12) [000032] n---G------- \--* IND ref N001 ( 2, 10) [000116] ------------ \--* CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] $186 --------- ***** BB01, STMT00019(before) N006 ( 4, 4) [000100] -A-XG---R--- * ASG int N005 ( 1, 1) [000099] D------N---- +--* LCL_VAR int V11 tmp9 d:2 N004 ( 4, 4) [000034] *--XG------- \--* IND int N003 ( 2, 2) [000118] -------N---- \--* ADD byref N001 ( 1, 1) [000033] ------------ +--* LCL_VAR byref V00 this u:1 N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] N001 [000033] LCL_VAR V00 this u:1 => $80 {InitVal($40)} N002 [000117] CNS_INT 16 field offset Fseq[m_NetworkInterfaceIndex] => $241 {LngCns: 16} N003 [000118] ADD => $282 {ADD($80, $241)} N004 [000034] IND => N005 [000099] LCL_VAR V11 tmp9 d:2 => N006 [000100] ASG => ***** BB01, STMT00019(after) N006 ( 4, 4) [000100] -A-XG---R--- * ASG int N005 ( 1, 1) [000099] D------N---- +--* LCL_VAR int V11 tmp9 d:2 N004 ( 4, 4) [000034] *--XG------- \--* IND int N003 ( 2, 2) [000118] -------N---- \--* ADD byref $282 N001 ( 1, 1) [000033] ------------ +--* LCL_VAR byref V00 this u:1 $80 N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] $241 --------- ***** BB01, STMT00016(before) N007 ( 8, 8) [000091] ---XG------- * JTRUE void N006 ( 6, 6) [000090] N--XG--N-U-- \--* GE int N001 ( 1, 1) [000087] ------------ +--* LCL_VAR int V11 tmp9 u:2 N005 ( 4, 4) [000089] ---XG------- \--* IND int N004 ( 2, 2) [000120] -------N---- \--* ADD byref N002 ( 1, 1) [000088] ------------ +--* LCL_VAR ref V12 tmp10 u:2 N003 ( 1, 1) [000119] ------------ \--* CNS_INT long 16 field offset Fseq[_size] N001 [000087] LCL_VAR V11 tmp9 u:2 => N002 [000088] LCL_VAR V12 tmp10 u:2 => N003 [000119] CNS_INT 16 field offset Fseq[_size] => $241 {LngCns: 16} N004 [000120] ADD => VNApplySelectors: VNForHandle(_size) is $187, fieldType is int VNForMapSelect($1d2, $187):int returns $303 {$1d2[$187]} VNForMapSelect($303, $342):int returns $304 {$303[$342]} N005 [000089] IND => N006 [000090] GE => ***** BB01, STMT00016(after) N007 ( 8, 8) [000091] ---XG------- * JTRUE void N006 ( 6, 6) [000090] N--XG--N-U-- \--* GE int N001 ( 1, 1) [000087] ------------ +--* LCL_VAR int V11 tmp9 u:2 N005 ( 4, 4) [000089] ---XG------- \--* IND int N004 ( 2, 2) [000120] -------N---- \--* ADD byref N002 ( 1, 1) [000088] ------------ +--* LCL_VAR ref V12 tmp10 u:2 N003 ( 1, 1) [000119] ------------ \--* CNS_INT long 16 field offset Fseq[_size] $241 finish(BB01). Succ(BB02). Not yet completed. All preds complete, adding to allDone. Succ(BB03). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#2) at start of BB03 is $1d2 {1d2} The SSA definition for GcHeap (#2) at start of BB03 is $1d2 {1d2} ***** BB03, STMT00017(before) N001 ( 14, 5) [000096] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException fgCurMemoryVN[GcHeap] assigned for CALL at [000096] to VN: $1d5. N001 [000096] CALL => $VN.Void ***** BB03, STMT00017(after) N001 ( 14, 5) [000096] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException $VN.Void finish(BB03). The SSA definition for ByrefExposed (#2) at start of BB02 is $1d2 {1d2} The SSA definition for GcHeap (#2) at start of BB02 is $1d2 {1d2} ***** BB02, STMT00020(before) N039 ( 65, 73) [000123] -ACXG---R--- * ASG struct (copy) N038 ( 3, 2) [000122] D------N---- +--* LCL_VAR struct V17 tmp15 d:2 N037 ( 61, 70) [000040] -ACXG------- \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA N023 ( 18, 22) [000145] -A-XG---R-L- this SETUP +--* ASG ref N022 ( 1, 1) [000144] D------N---- | +--* LCL_VAR ref V19 tmp17 d:2 N021 ( 18, 22) [000139] -A-XG------- | \--* COMMA ref N006 ( 4, 4) [000126] -A-XG---R--- | +--* ASG ref N005 ( 1, 1) [000125] D------N---- | | +--* LCL_VAR ref V18 tmp16 d:2 N004 ( 4, 4) [000093] ---XG------- | | \--* IND ref N003 ( 2, 2) [000141] -------N---- | | \--* ADD byref N001 ( 1, 1) [000092] ------------ | | +--* LCL_VAR ref V12 tmp10 u:2 (last use) N002 ( 1, 1) [000140] ------------ | | \--* CNS_INT long 8 field offset Fseq[_items] N020 ( 14, 18) [000138] ---XG------- | \--* COMMA ref N010 ( 8, 11) [000131] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [000094] ------------ | | +--* LCL_VAR int V11 tmp9 u:2 N009 ( 3, 3) [000130] ---X-------- | | \--* ARR_LENGTH int N008 ( 1, 1) [000127] ------------ | | \--* LCL_VAR ref V18 tmp16 u:2 N019 ( 6, 7) [000095] a---G------- | \--* IND ref N018 ( 5, 6) [000137] -------N---- | \--* ADD byref N011 ( 1, 1) [000128] ------------ | +--* LCL_VAR ref V18 tmp16 u:2 (last use) N017 ( 4, 5) [000136] -------N---- | \--* ADD long N015 ( 3, 4) [000134] -------N---- | +--* LSH long N013 ( 2, 3) [000132] ------------ | | +--* CAST long <- int N012 ( 1, 1) [000129] i----------- | | | \--* LCL_VAR int V11 tmp9 u:2 (last use) N014 ( 1, 1) [000133] -------N---- | | \--* CNS_INT long 3 N016 ( 1, 1) [000135] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] N029 ( 9, 7) [000044] ---XG------- arg3 out+00 +--* OBJ struct N028 ( 3, 3) [000143] ------------ | \--* ADD byref N026 ( 1, 1) [000037] ------------ | +--* LCL_VAR byref V00 this u:1 (last use) N027 ( 1, 1) [000142] ------------ | \--* CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] N031 ( 1, 1) [000146] ------------ this in rdi +--* LCL_VAR ref V19 tmp17 u:2 (last use) N034 ( 6, 8) [000150] -c---------- arg4 rdx,rcx +--* FIELD_LIST struct N032 ( 3, 4) [000151] ------------ ofs 0 | +--* LCL_FLD long V01 arg1 u:1[+0] N033 ( 3, 4) [000152] ------------ ofs 8 | \--* LCL_FLD long V01 arg1 u:1[+8] (last use) N035 ( 2, 10) [000124] ------------ arg1 in r11 +--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 N036 ( 2, 10) [000121] ------------ arg2 in rsi \--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 N001 [000092] LCL_VAR V12 tmp10 u:2 (last use) => N002 [000140] CNS_INT 8 field offset Fseq[_items] => $240 {LngCns: 8} N003 [000141] ADD => VNApplySelectors: VNForHandle(_items) is $188, fieldType is ref VNForMapSelect($1d2, $188):ref returns $205 {$1d2[$188]} VNForMapSelect($205, $342):ref returns $206 {$205[$342]} N004 [000093] IND => N005 [000125] LCL_VAR V18 tmp16 d:2 => N006 [000126] ASG => N007 [000094] LCL_VAR V11 tmp9 u:2 => N008 [000127] LCL_VAR V18 tmp16 u:2 => N009 [000130] ARR_LENGTH => N010 [000131] ARR_BOUNDS_CHECK_Rng => N011 [000128] LCL_VAR V18 tmp16 u:2 (last use) => N012 [000129] LCL_VAR V11 tmp9 u:2 (last use) => VNForCastOper(long) is $46 N013 [000132] CAST => N014 [000133] CNS_INT 3 => $242 {LngCns: 3} N015 [000134] LSH => N016 [000135] CNS_INT 16 Fseq[#FirstElem] => $241 {LngCns: 16} N017 [000136] ADD => N018 [000137] ADD => VNForHandle(arrElemType: ref) is $189 Relabeled IND_ARR_INDEX address node [000137] with l:$480: {PtrToArrElem($189, $206, $2c1, $0)} VNForMapSelect($1d2, $189):ref returns $215 {$1d2[$189]} VNForMapSelect($215, $206):ref returns $216 {$215[$206]} VNForMapSelect($216, $2c1):ref returns $217 {$216[$2c1]} hAtArrType $215 is MapSelect(curGcHeap($1d2), ref[]). hAtArrTypeAtArr $216 is MapSelect(hAtArrType($215), arr=$206). wholeElem $217 is MapSelect(hAtArrTypeAtArr($216), ind=$2c1). N019 [000095] IND => N020 [000138] COMMA => N021 [000139] COMMA => N022 [000144] LCL_VAR V19 tmp17 d:2 => N023 [000145] ASG => N024 [000148] ARGPLACE => $142 {142} N025 [000149] ARGPLACE => $143 {143} N026 [000037] LCL_VAR V00 this u:1 (last use) => $80 {InitVal($40)} N027 [000142] CNS_INT 56 field offset Fseq[m_ParallelSendQueue] => $245 {LngCns: 56} N028 [000143] ADD => $289 {ADD($80, $245)} N029 [000044] OBJ => N030 [000147] ARGPLACE => $383 {383} N031 [000146] LCL_VAR V19 tmp17 u:2 (last use) => N032 [000151] LCL_FLD V01 arg1 u:1[+0] => $144 {144} N033 [000152] LCL_FLD V01 arg1 u:1[+8] (last use) => $145 {145} N034 [000150] FIELD_LIST => $384 {384} N035 [000124] CNS_INT(h) 0x7f6678060518 ftn => $18a {Hnd const: 0x00007F6678060518} N036 [000121] CNS_INT(h) 0x7f6678060518 ftn => $18a {Hnd const: 0x00007F6678060518} VN of ARGPLACE tree [000148] updated to VN of ARGPLACE tree [000149] updated to $18a {Hnd const: 0x00007F6678060518} VN of ARGPLACE tree [000147] updated to fgCurMemoryVN[GcHeap] assigned for CALL at [000040] to VN: $1da. N037 [000040] CALLV stub => $385 {385} Tree [000123] assigned VN to local var V17/2: new uniq $388 {388} N039 [000123] ASG => $VN.Void ***** BB02, STMT00020(after) N039 ( 65, 73) [000123] -ACXG---R--- * ASG struct (copy) $VN.Void N038 ( 3, 2) [000122] D------N---- +--* LCL_VAR struct V17 tmp15 d:2 N037 ( 61, 70) [000040] -ACXG------- \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA $385 N023 ( 18, 22) [000145] -A-XG---R-L- this SETUP +--* ASG ref N022 ( 1, 1) [000144] D------N---- | +--* LCL_VAR ref V19 tmp17 d:2 N021 ( 18, 22) [000139] -A-XG------- | \--* COMMA ref N006 ( 4, 4) [000126] -A-XG---R--- | +--* ASG ref N005 ( 1, 1) [000125] D------N---- | | +--* LCL_VAR ref V18 tmp16 d:2 N004 ( 4, 4) [000093] ---XG------- | | \--* IND ref N003 ( 2, 2) [000141] -------N---- | | \--* ADD byref N001 ( 1, 1) [000092] ------------ | | +--* LCL_VAR ref V12 tmp10 u:2 (last use) N002 ( 1, 1) [000140] ------------ | | \--* CNS_INT long 8 field offset Fseq[_items] $240 N020 ( 14, 18) [000138] ---XG------- | \--* COMMA ref N010 ( 8, 11) [000131] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [000094] ------------ | | +--* LCL_VAR int V11 tmp9 u:2 N009 ( 3, 3) [000130] ---X-------- | | \--* ARR_LENGTH int N008 ( 1, 1) [000127] ------------ | | \--* LCL_VAR ref V18 tmp16 u:2 N019 ( 6, 7) [000095] a---G------- | \--* IND ref N018 ( 5, 6) [000137] -------N---- | \--* ADD byref $480 N011 ( 1, 1) [000128] ------------ | +--* LCL_VAR ref V18 tmp16 u:2 (last use) N017 ( 4, 5) [000136] -------N---- | \--* ADD long N015 ( 3, 4) [000134] -------N---- | +--* LSH long N013 ( 2, 3) [000132] ------------ | | +--* CAST long <- int N012 ( 1, 1) [000129] i----------- | | | \--* LCL_VAR int V11 tmp9 u:2 (last use) N014 ( 1, 1) [000133] -------N---- | | \--* CNS_INT long 3 $242 N016 ( 1, 1) [000135] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N029 ( 9, 7) [000044] ---XG------- arg3 out+00 +--* OBJ struct N028 ( 3, 3) [000143] ------------ | \--* ADD byref $289 N026 ( 1, 1) [000037] ------------ | +--* LCL_VAR byref V00 this u:1 (last use) $80 N027 ( 1, 1) [000142] ------------ | \--* CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] $245 N031 ( 1, 1) [000146] ------------ this in rdi +--* LCL_VAR ref V19 tmp17 u:2 (last use) N034 ( 6, 8) [000150] -c---------- arg4 rdx,rcx +--* FIELD_LIST struct $384 N032 ( 3, 4) [000151] ------------ ofs 0 | +--* LCL_FLD long V01 arg1 u:1[+0] $144 N033 ( 3, 4) [000152] ------------ ofs 8 | \--* LCL_FLD long V01 arg1 u:1[+8] (last use) $145 N035 ( 2, 10) [000124] ------------ arg1 in r11 +--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a N036 ( 2, 10) [000121] ------------ arg2 in rsi \--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a --------- ***** BB02, STMT00007(before) N002 ( 4, 3) [000045] ----G------- * RETURN struct N001 ( 3, 2) [000153] -------N---- \--* LCL_VAR struct V17 tmp15 u:2 (last use) N001 [000153] LCL_VAR V17 tmp15 u:2 (last use) => $388 {388} N002 [000045] RETURN => $389 {389} ***** BB02, STMT00007(after) N002 ( 4, 3) [000045] ----G------- * RETURN struct $389 N001 ( 3, 2) [000153] -------N---- \--* LCL_VAR struct V17 tmp15 u:2 (last use) $388 finish(BB02). *************** Finishing PHASE Do value numbering *************** Starting PHASE Hoist loop code *************** Finishing PHASE Hoist loop code *************** Starting PHASE VN based copy prop *************** In optVnCopyProp() Copy Assertion for BB01 curSsaName stack: { } Live vars: {V00 V01} => {V00 V01 V03} Live vars: {V00 V01 V03} => {V00 V01 V03 V04} Live vars: {V00 V01 V03 V04} => {V00 V01 V04} Live vars: {V00 V01 V04} => {V00 V01 V04 V13} Live vars: {V00 V01 V04 V13} => {V00 V01 V13} Live vars: {V00 V01 V13} => {V00 V01 V13 V14} Live vars: {V00 V01 V13 V14} => {V00 V01 V13 V14 V15} Live vars: {V00 V01 V13 V14 V15} => {V00 V01 V13 V14 V15 V16} Live vars: {V00 V01 V13 V14 V15 V16} => {V00 V01 V14 V15 V16} Live vars: {V00 V01 V14 V15 V16} => {V00 V01 V15 V16} Live vars: {V00 V01 V15 V16} => {V00 V01 V16} Live vars: {V00 V01 V16} => {V00 V01} Live vars: {V00 V01} => {V00 V01 V10} Live vars: {V00 V01 V10} => {V00 V01} Live vars: {V00 V01} => {V00 V01 V12} Live vars: {V00 V01 V12} => {V00 V01 V11 V12} Copy Assertion for BB03 curSsaName stack: { 0-[000033]:V00 3-[000006]:V03 4-[000020]:V04 10-[000084]:V10 11-[000099]:V11 12-[000097]:V12 13-[000062]:V13 14-[000067]:V14 15-[000072]:V15 16-[000077]:V16 } Copy Assertion for BB02 curSsaName stack: { 0-[000033]:V00 3-[000006]:V03 4-[000020]:V04 10-[000084]:V10 11-[000099]:V11 12-[000097]:V12 13-[000062]:V13 14-[000067]:V14 15-[000072]:V15 16-[000077]:V16 } Live vars: {V00 V01 V11 V12} => {V00 V01 V11} Live vars: {V00 V01 V11} => {V00 V01 V11 V18} Live vars: {V00 V01 V11 V18} => {V00 V01 V11} Live vars: {V00 V01 V11} => {V00 V01} Live vars: {V00 V01} => {V00 V01 V19} Live vars: {V00 V01 V19} => {V01 V19} Live vars: {V01 V19} => {V01} Live vars: {V01} => {} Live vars: {} => {V17} Live vars: {V17} => {} *************** Finishing PHASE VN based copy prop *************** Starting PHASE Optimize Valnum CSEs *************** In optOptimizeCSEs() Blocks/Trees at start of optOptimizeCSE phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj BB02 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 (IL 0x000...0x041) N005 ( 16, 16) [000007] -AC-----R--- * ASG ref $200 N004 ( 1, 1) [000006] D------N---- +--* LCL_VAR ref V03 tmp1 d:2 $200 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class $180 ***** BB01 STMT00001 (IL ???... ???) N006 ( 8, 9) [000012] -A-XG------- * ASG long $VN.Void N004 ( 4, 4) [000011] D--X---N---- +--* IND long $2c0 N003 ( 2, 2) [000010] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V03 tmp1 u:2 $200 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD long V01 arg1 u:1[+0] Fseq[JobGroup] $2c0 ***** BB01 STMT00002 (IL ???... ???) N005 ( 16, 16) [000021] -AC-----R--- * ASG ref $201 N004 ( 1, 1) [000020] D------N---- +--* LCL_VAR ref V04 tmp2 d:2 $201 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class $182 ***** BB01 STMT00003 (IL ???... ???) N006 ( 8, 9) [000026] -A-XG------- * ASG int $VN.Void N004 ( 4, 4) [000025] D--X---N---- +--* IND int $300 N003 ( 2, 2) [000024] -------N---- | \--* ADD byref $281 N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V04 tmp2 u:2 $201 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD int V01 arg1 u:1[+8] Fseq[Version] $300 ***** BB01 STMT00010 (IL ???... ???) N004 ( 11, 8) [000063] -A------R--- * ASG ref $200 N003 ( 3, 2) [000062] D------N---- +--* LCL_VAR ref V13 tmp11 d:2 $200 N002 ( 7, 5) [000014] ------------ \--* BOX ref $200 N001 ( 1, 1) [000013] ------------ \--* LCL_VAR ref V03 tmp1 u:2 (last use) $200 ***** BB01 STMT00011 (IL ???... ???) N004 ( 11, 8) [000068] -A------R--- * ASG ref $201 N003 ( 3, 2) [000067] D------N---- +--* LCL_VAR ref V14 tmp12 d:2 $201 N002 ( 7, 5) [000028] ------------ \--* BOX ref $201 N001 ( 1, 1) [000027] ------------ \--* LCL_VAR ref V04 tmp2 u:2 (last use) $201 ***** BB01 STMT00012 (IL ???... ???) N003 ( 5, 4) [000073] -A------R--- * ASG ref $VN.Null N002 ( 3, 2) [000072] D------N---- +--* LCL_VAR ref V15 tmp13 d:2 $VN.Null N001 ( 1, 1) [000071] ------------ \--* CNS_INT ref null $VN.Null ***** BB01 STMT00013 (IL ???... ???) N004 ( 8, 15) [000078] -A--G---R--- * ASG ref N003 ( 3, 2) [000077] D------N---- +--* LCL_VAR ref V16 tmp14 d:2 N002 ( 4, 12) [000076] n---G------- \--* IND ref N001 ( 2, 10) [000104] ------------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 ***** BB01 STMT00015 (IL ???... ???) N013 ( 34, 28) [000085] -ACXG---R--- * ASG ref $1ce N012 ( 1, 1) [000084] D------N---- +--* LCL_VAR ref V10 tmp8 d:2 $1ce N011 ( 34, 28) [000054] --CXG------- \--* CALL ref System.String.FormatHelper $1ce N007 ( 12, 8) [000109] -c---------- arg2 out+00 +--* FIELD_LIST struct $380 N003 ( 3, 2) [000110] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp11 u:2 (last use) $200 N004 ( 3, 2) [000111] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp12 u:2 (last use) $201 N005 ( 3, 2) [000112] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp13 u:2 (last use) $VN.Null N006 ( 3, 2) [000113] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp14 u:2 (last use) N009 ( 4, 12) [000106] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000105] ------------ | \--* CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] $185 N010 ( 1, 1) [000046] ------------ arg0 in rdi \--* CNS_INT ref null $VN.Null ***** BB01 STMT00014 (IL ???... ???) N005 ( 16, 9) [000083] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void N003 ( 1, 1) [000082] ------------ arg1 in rsi +--* LCL_VAR ref V10 tmp8 u:2 (last use) $1ce N004 ( 1, 1) [000081] ------------ arg0 in rdi \--* CNS_INT int 3 $44 ***** BB01 STMT00018 (IL 0x025... ???) N004 ( 4, 12) [000098] -A--G---R--- * ASG ref N003 ( 1, 1) [000097] D------N---- +--* LCL_VAR ref V12 tmp10 d:2 N002 ( 4, 12) [000032] n---G------- \--* IND ref N001 ( 2, 10) [000116] ------------ \--* CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] $186 ***** BB01 STMT00019 (IL 0x025... ???) N006 ( 4, 4) [000100] -A-XG---R--- * ASG int N005 ( 1, 1) [000099] D------N---- +--* LCL_VAR int V11 tmp9 d:2 N004 ( 4, 4) [000034] *--XG------- \--* IND int N003 ( 2, 2) [000118] -------N---- \--* ADD byref $282 N001 ( 1, 1) [000033] ------------ +--* LCL_VAR byref V00 this u:1 $80 N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] $241 ***** BB01 STMT00016 (IL 0x025... ???) N007 ( 8, 8) [000091] ---XG------- * JTRUE void N006 ( 6, 6) [000090] N--XG--N-U-- \--* GE int N001 ( 1, 1) [000087] ------------ +--* LCL_VAR int V11 tmp9 u:2 N005 ( 4, 4) [000089] ---XG------- \--* IND int N004 ( 2, 2) [000120] -------N---- \--* ADD byref N002 ( 1, 1) [000088] ------------ +--* LCL_VAR ref V12 tmp10 u:2 N003 ( 1, 1) [000119] ------------ \--* CNS_INT long 16 field offset Fseq[_size] $241 ------------ BB02 [025..026) (return), preds={BB01} succs={} ***** BB02 STMT00020 (IL ???... ???) N039 ( 65, 73) [000123] -ACXG---R--- * ASG struct (copy) $VN.Void N038 ( 3, 2) [000122] D------N---- +--* LCL_VAR struct V17 tmp15 d:2 N037 ( 61, 70) [000040] -ACXG------- \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA $385 N023 ( 18, 22) [000145] -A-XG---R-L- this SETUP +--* ASG ref N022 ( 1, 1) [000144] D------N---- | +--* LCL_VAR ref V19 tmp17 d:2 N021 ( 18, 22) [000139] -A-XG------- | \--* COMMA ref N006 ( 4, 4) [000126] -A-XG---R--- | +--* ASG ref N005 ( 1, 1) [000125] D------N---- | | +--* LCL_VAR ref V18 tmp16 d:2 N004 ( 4, 4) [000093] ---XG------- | | \--* IND ref N003 ( 2, 2) [000141] -------N---- | | \--* ADD byref N001 ( 1, 1) [000092] ------------ | | +--* LCL_VAR ref V12 tmp10 u:2 (last use) N002 ( 1, 1) [000140] ------------ | | \--* CNS_INT long 8 field offset Fseq[_items] $240 N020 ( 14, 18) [000138] ---XG------- | \--* COMMA ref N010 ( 8, 11) [000131] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [000094] ------------ | | +--* LCL_VAR int V11 tmp9 u:2 N009 ( 3, 3) [000130] ---X-------- | | \--* ARR_LENGTH int N008 ( 1, 1) [000127] ------------ | | \--* LCL_VAR ref V18 tmp16 u:2 N019 ( 6, 7) [000095] a---G------- | \--* IND ref N018 ( 5, 6) [000137] -------N---- | \--* ADD byref $480 N011 ( 1, 1) [000128] ------------ | +--* LCL_VAR ref V18 tmp16 u:2 (last use) N017 ( 4, 5) [000136] -------N---- | \--* ADD long N015 ( 3, 4) [000134] -------N---- | +--* LSH long N013 ( 2, 3) [000132] ------------ | | +--* CAST long <- int N012 ( 1, 1) [000129] i----------- | | | \--* LCL_VAR int V11 tmp9 u:2 (last use) N014 ( 1, 1) [000133] -------N---- | | \--* CNS_INT long 3 $242 N016 ( 1, 1) [000135] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N029 ( 9, 7) [000044] ---XG------- arg3 out+00 +--* OBJ struct N028 ( 3, 3) [000143] ------------ | \--* ADD byref $289 N026 ( 1, 1) [000037] ------------ | +--* LCL_VAR byref V00 this u:1 (last use) $80 N027 ( 1, 1) [000142] ------------ | \--* CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] $245 N031 ( 1, 1) [000146] ------------ this in rdi +--* LCL_VAR ref V19 tmp17 u:2 (last use) N034 ( 6, 8) [000150] -c---------- arg4 rdx,rcx +--* FIELD_LIST struct $384 N032 ( 3, 4) [000151] ------------ ofs 0 | +--* LCL_FLD long V01 arg1 u:1[+0] $144 N033 ( 3, 4) [000152] ------------ ofs 8 | \--* LCL_FLD long V01 arg1 u:1[+8] (last use) $145 N035 ( 2, 10) [000124] ------------ arg1 in r11 +--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a N036 ( 2, 10) [000121] ------------ arg2 in rsi \--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a ***** BB02 STMT00007 (IL ???... ???) N002 ( 4, 3) [000045] ----G------- * RETURN struct $389 N001 ( 3, 2) [000153] -------N---- \--* LCL_VAR struct V17 tmp15 u:2 (last use) $388 ------------ BB03 [025..026) (throw), preds={BB01} succs={} ***** BB03 STMT00017 (IL 0x025... ???) N001 ( 14, 5) [000096] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In optOptimizeValnumCSEs() *************** Finishing PHASE Optimize Valnum CSEs *************** Starting PHASE Assertion prop *************** In optAssertionPropMain() Blocks/Trees at start of phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj BB02 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 (IL 0x000...0x041) N005 ( 16, 16) [000007] -AC-----R--- * ASG ref $200 N004 ( 1, 1) [000006] D------N---- +--* LCL_VAR ref V03 tmp1 d:2 $200 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class $180 ***** BB01 STMT00001 (IL ???... ???) N006 ( 8, 9) [000012] -A-XG------- * ASG long $VN.Void N004 ( 4, 4) [000011] D--X---N---- +--* IND long $2c0 N003 ( 2, 2) [000010] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V03 tmp1 u:2 $200 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD long V01 arg1 u:1[+0] Fseq[JobGroup] $2c0 ***** BB01 STMT00002 (IL ???... ???) N005 ( 16, 16) [000021] -AC-----R--- * ASG ref $201 N004 ( 1, 1) [000020] D------N---- +--* LCL_VAR ref V04 tmp2 d:2 $201 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class $182 ***** BB01 STMT00003 (IL ???... ???) N006 ( 8, 9) [000026] -A-XG------- * ASG int $VN.Void N004 ( 4, 4) [000025] D--X---N---- +--* IND int $300 N003 ( 2, 2) [000024] -------N---- | \--* ADD byref $281 N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V04 tmp2 u:2 $201 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD int V01 arg1 u:1[+8] Fseq[Version] $300 ***** BB01 STMT00010 (IL ???... ???) N004 ( 11, 8) [000063] -A------R--- * ASG ref $200 N003 ( 3, 2) [000062] D------N---- +--* LCL_VAR ref V13 tmp11 d:2 $200 N002 ( 7, 5) [000014] ------------ \--* BOX ref $200 N001 ( 1, 1) [000013] ------------ \--* LCL_VAR ref V03 tmp1 u:2 (last use) $200 ***** BB01 STMT00011 (IL ???... ???) N004 ( 11, 8) [000068] -A------R--- * ASG ref $201 N003 ( 3, 2) [000067] D------N---- +--* LCL_VAR ref V14 tmp12 d:2 $201 N002 ( 7, 5) [000028] ------------ \--* BOX ref $201 N001 ( 1, 1) [000027] ------------ \--* LCL_VAR ref V04 tmp2 u:2 (last use) $201 ***** BB01 STMT00012 (IL ???... ???) N003 ( 5, 4) [000073] -A------R--- * ASG ref $VN.Null N002 ( 3, 2) [000072] D------N---- +--* LCL_VAR ref V15 tmp13 d:2 $VN.Null N001 ( 1, 1) [000071] ------------ \--* CNS_INT ref null $VN.Null ***** BB01 STMT00013 (IL ???... ???) N004 ( 8, 15) [000078] -A--G---R--- * ASG ref N003 ( 3, 2) [000077] D------N---- +--* LCL_VAR ref V16 tmp14 d:2 N002 ( 4, 12) [000076] n---G------- \--* IND ref N001 ( 2, 10) [000104] ------------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 ***** BB01 STMT00015 (IL ???... ???) N013 ( 34, 28) [000085] -ACXG---R--- * ASG ref $1ce N012 ( 1, 1) [000084] D------N---- +--* LCL_VAR ref V10 tmp8 d:2 $1ce N011 ( 34, 28) [000054] --CXG------- \--* CALL ref System.String.FormatHelper $1ce N007 ( 12, 8) [000109] -c---------- arg2 out+00 +--* FIELD_LIST struct $380 N003 ( 3, 2) [000110] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp11 u:2 (last use) $200 N004 ( 3, 2) [000111] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp12 u:2 (last use) $201 N005 ( 3, 2) [000112] ------------ ofs 16 | +--* LCL_VAR ref V15 tmp13 u:2 (last use) $VN.Null N006 ( 3, 2) [000113] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp14 u:2 (last use) N009 ( 4, 12) [000106] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000105] ------------ | \--* CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] $185 N010 ( 1, 1) [000046] ------------ arg0 in rdi \--* CNS_INT ref null $VN.Null ***** BB01 STMT00014 (IL ???... ???) N005 ( 16, 9) [000083] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void N003 ( 1, 1) [000082] ------------ arg1 in rsi +--* LCL_VAR ref V10 tmp8 u:2 (last use) $1ce N004 ( 1, 1) [000081] ------------ arg0 in rdi \--* CNS_INT int 3 $44 ***** BB01 STMT00018 (IL 0x025... ???) N004 ( 4, 12) [000098] -A--G---R--- * ASG ref N003 ( 1, 1) [000097] D------N---- +--* LCL_VAR ref V12 tmp10 d:2 N002 ( 4, 12) [000032] n---G------- \--* IND ref N001 ( 2, 10) [000116] ------------ \--* CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] $186 ***** BB01 STMT00019 (IL 0x025... ???) N006 ( 4, 4) [000100] -A-XG---R--- * ASG int N005 ( 1, 1) [000099] D------N---- +--* LCL_VAR int V11 tmp9 d:2 N004 ( 4, 4) [000034] *--XG------- \--* IND int N003 ( 2, 2) [000118] -------N---- \--* ADD byref $282 N001 ( 1, 1) [000033] ------------ +--* LCL_VAR byref V00 this u:1 $80 N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] $241 ***** BB01 STMT00016 (IL 0x025... ???) N007 ( 8, 8) [000091] ---XG------- * JTRUE void N006 ( 6, 6) [000090] N--XG--N-U-- \--* GE int N001 ( 1, 1) [000087] ------------ +--* LCL_VAR int V11 tmp9 u:2 N005 ( 4, 4) [000089] ---XG------- \--* IND int N004 ( 2, 2) [000120] -------N---- \--* ADD byref N002 ( 1, 1) [000088] ------------ +--* LCL_VAR ref V12 tmp10 u:2 N003 ( 1, 1) [000119] ------------ \--* CNS_INT long 16 field offset Fseq[_size] $241 ------------ BB02 [025..026) (return), preds={BB01} succs={} ***** BB02 STMT00020 (IL ???... ???) N039 ( 65, 73) [000123] -ACXG---R--- * ASG struct (copy) $VN.Void N038 ( 3, 2) [000122] D------N---- +--* LCL_VAR struct V17 tmp15 d:2 N037 ( 61, 70) [000040] -ACXG------- \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA $385 N023 ( 18, 22) [000145] -A-XG---R-L- this SETUP +--* ASG ref N022 ( 1, 1) [000144] D------N---- | +--* LCL_VAR ref V19 tmp17 d:2 N021 ( 18, 22) [000139] -A-XG------- | \--* COMMA ref N006 ( 4, 4) [000126] -A-XG---R--- | +--* ASG ref N005 ( 1, 1) [000125] D------N---- | | +--* LCL_VAR ref V18 tmp16 d:2 N004 ( 4, 4) [000093] ---XG------- | | \--* IND ref N003 ( 2, 2) [000141] -------N---- | | \--* ADD byref N001 ( 1, 1) [000092] ------------ | | +--* LCL_VAR ref V12 tmp10 u:2 (last use) N002 ( 1, 1) [000140] ------------ | | \--* CNS_INT long 8 field offset Fseq[_items] $240 N020 ( 14, 18) [000138] ---XG------- | \--* COMMA ref N010 ( 8, 11) [000131] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [000094] ------------ | | +--* LCL_VAR int V11 tmp9 u:2 N009 ( 3, 3) [000130] ---X-------- | | \--* ARR_LENGTH int N008 ( 1, 1) [000127] ------------ | | \--* LCL_VAR ref V18 tmp16 u:2 N019 ( 6, 7) [000095] a---G------- | \--* IND ref N018 ( 5, 6) [000137] -------N---- | \--* ADD byref $480 N011 ( 1, 1) [000128] ------------ | +--* LCL_VAR ref V18 tmp16 u:2 (last use) N017 ( 4, 5) [000136] -------N---- | \--* ADD long N015 ( 3, 4) [000134] -------N---- | +--* LSH long N013 ( 2, 3) [000132] ------------ | | +--* CAST long <- int N012 ( 1, 1) [000129] i----------- | | | \--* LCL_VAR int V11 tmp9 u:2 (last use) N014 ( 1, 1) [000133] -------N---- | | \--* CNS_INT long 3 $242 N016 ( 1, 1) [000135] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N029 ( 9, 7) [000044] ---XG------- arg3 out+00 +--* OBJ struct N028 ( 3, 3) [000143] ------------ | \--* ADD byref $289 N026 ( 1, 1) [000037] ------------ | +--* LCL_VAR byref V00 this u:1 (last use) $80 N027 ( 1, 1) [000142] ------------ | \--* CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] $245 N031 ( 1, 1) [000146] ------------ this in rdi +--* LCL_VAR ref V19 tmp17 u:2 (last use) N034 ( 6, 8) [000150] -c---------- arg4 rdx,rcx +--* FIELD_LIST struct $384 N032 ( 3, 4) [000151] ------------ ofs 0 | +--* LCL_FLD long V01 arg1 u:1[+0] $144 N033 ( 3, 4) [000152] ------------ ofs 8 | \--* LCL_FLD long V01 arg1 u:1[+8] (last use) $145 N035 ( 2, 10) [000124] ------------ arg1 in r11 +--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a N036 ( 2, 10) [000121] ------------ arg2 in rsi \--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a ***** BB02 STMT00007 (IL ???... ???) N002 ( 4, 3) [000045] ----G------- * RETURN struct $389 N001 ( 3, 2) [000153] -------N---- \--* LCL_VAR struct V17 tmp15 u:2 (last use) $388 ------------ BB03 [025..026) (throw), preds={BB01} succs={} ***** BB03 STMT00017 (IL 0x025... ???) N001 ( 14, 5) [000096] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException $VN.Void ------------------------------------------------------------------------------------------------------------------- VN based non-null prop in BB01: N004 ( 4, 4) [000011] D--X---N---- * IND long $2c0 optVNAssertionPropCurStmt morphed tree: N006 ( 8, 9) [000012] -A--GO------ * ASG long $VN.Void N004 ( 4, 4) [000011] n----O-N---- +--* IND long $2c0 N003 ( 2, 2) [000010] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V03 tmp1 u:2 $200 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD long V01 arg1 u:1[+0] Fseq[JobGroup] $2c0 GenTreeNode creates assertion: N004 ( 4, 4) [000011] n----O-N---- * IND long $2c0 In BB01 New Global Constant Assertion: (512, 0) ($200,$0) V03.02 != null index=#01, mask= VN based non-null prop in BB01: N004 ( 4, 4) [000025] D--X---N---- * IND int $300 optVNAssertionPropCurStmt morphed tree: N006 ( 8, 9) [000026] -A--GO------ * ASG int $VN.Void N004 ( 4, 4) [000025] n----O-N---- +--* IND int $300 N003 ( 2, 2) [000024] -------N---- | \--* ADD byref $281 N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V04 tmp2 u:2 $201 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD int V01 arg1 u:1[+8] Fseq[Version] $300 GenTreeNode creates assertion: N004 ( 4, 4) [000025] n----O-N---- * IND int $300 In BB01 New Global Constant Assertion: (513, 0) ($201,$0) V04.02 != null index=#02, mask= After constant propagation on [000112]: STMT00015 (IL ???... ???) N013 ( 34, 28) [000085] -ACXG---R--- * ASG ref $1ce N012 ( 1, 1) [000084] D------N---- +--* LCL_VAR ref V10 tmp8 d:2 $1ce N011 ( 34, 28) [000054] --CXG------- \--* CALL ref System.String.FormatHelper $1ce N007 ( 12, 8) [000109] -c---------- arg2 out+00 +--* FIELD_LIST struct $380 N003 ( 3, 2) [000110] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp11 u:2 (last use) $200 N004 ( 3, 2) [000111] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp12 u:2 (last use) $201 [000154] ------------ ofs 16 | +--* CNS_INT ref null $VN.Null N006 ( 3, 2) [000113] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp14 u:2 (last use) N009 ( 4, 12) [000106] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000105] ------------ | \--* CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] $185 N010 ( 1, 1) [000046] ------------ arg0 in rdi \--* CNS_INT ref null $VN.Null ReMorphing args for 54.CALL: argSlots=6, preallocatedArgCount=4, nextSlotNum=4, outgoingArgSpaceSize=32 ArgTable for 54.CALL after fgMorphArgs: fgArgTabEntry[arg 2 109.FIELD_LIST struct (By value), numSlots=4, slotNum=0, align=1, processed, isStruct] fgArgTabEntry[arg 1 106.IND ref (By ref), 1 reg: rsi, align=1, lateArgInx=0, processed] fgArgTabEntry[arg 0 46.CNS_INT ref (By ref), 1 reg: rdi, align=1, lateArgInx=1, processed] optVNAssertionPropCurStmt morphed tree: N013 ( 32, 27) [000085] -ACXG---R--- * ASG ref $1ce N012 ( 1, 1) [000084] D------N---- +--* LCL_VAR ref V10 tmp8 d:2 $1ce N011 ( 32, 27) [000054] --CXG------- \--* CALL ref System.String.FormatHelper $1ce N007 ( 10, 7) [000109] -c---------- arg2 out+00 +--* FIELD_LIST struct $380 N003 ( 3, 2) [000110] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp11 u:2 (last use) $200 N004 ( 3, 2) [000111] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp12 u:2 (last use) $201 N005 ( 1, 1) [000154] ------------ ofs 16 | +--* CNS_INT ref null $VN.Null N006 ( 3, 2) [000113] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp14 u:2 (last use) N009 ( 4, 12) [000106] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000105] ------------ | \--* CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] $185 N010 ( 1, 1) [000046] ------------ arg0 in rdi \--* CNS_INT ref null $VN.Null GenTreeNode creates assertion: N004 ( 4, 4) [000034] *--XG------- * IND int In BB01 New Global Constant Assertion: (128, 0) ($80,$0) Value_Number {InitVal($40)} is not 0 index=#03, mask= GenTreeNode creates assertion: N005 ( 4, 4) [000089] ---XG------- * IND int In BB01 New Global Constant Assertion: (467, 0) ($1d3,$0) V12.02 != null index=#04, mask= GenTreeNode creates assertion: N009 ( 3, 3) [000130] ---X-------- * ARR_LENGTH int In BB02 New Global Constant Assertion: (470, 0) ($1d6,$0) V18.02 != null index=#05, mask= GenTreeNode creates assertion: N010 ( 8, 11) [000131] ---X-------- * ARR_BOUNDS_CHECK_Rng void In BB02 New Global ArrBnds Assertion: (0, 0) ($0,$0) [idx: {3c1};len: {ARR_LENGTH($1d6)}] in range index=#06, mask= GenTreeNode creates assertion: N037 ( 61, 70) [000040] -ACXG------- * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA $385 In BB02 New Global Constant Assertion: (472, 0) ($1d8,$0) V19.02 != null index=#07, mask= BB01 valueGen = => BB03 valueGen = , BB02 valueGen = BB03 valueGen = AssertionPropCallback::StartMerge: BB01 in -> AssertionPropCallback::EndMerge : BB01 in -> AssertionPropCallback::Changed : BB01 before out -> ; after out -> ; jumpDest before out -> ; jumpDest after out -> ; AssertionPropCallback::StartMerge: BB02 in -> AssertionPropCallback::Merge : BB02 in -> , predBlock BB01 out -> AssertionPropCallback::EndMerge : BB02 in -> AssertionPropCallback::Changed : BB02 before out -> ; after out -> ; jumpDest before out -> ; jumpDest after out -> ; AssertionPropCallback::StartMerge: BB03 in -> AssertionPropCallback::Merge : BB03 in -> , predBlock BB01 out -> AssertionPropCallback::EndMerge : BB03 in -> AssertionPropCallback::Changed : BB03 before out -> ; after out -> ; jumpDest before out -> ; jumpDest after out -> ; BB01 valueIn = valueOut = => BB03 valueOut= BB02 valueIn = valueOut = BB03 valueIn = valueOut = Propagating assertions for BB01, stmt STMT00000, tree [000102], tree -> 0 Propagating assertions for BB01, stmt STMT00000, tree [000004], tree -> 0 Propagating assertions for BB01, stmt STMT00000, tree [000005], tree -> 0 Propagating assertions for BB01, stmt STMT00000, tree [000006], tree -> 0 Propagating assertions for BB01, stmt STMT00000, tree [000007], tree -> 0 Propagating assertions for BB01, stmt STMT00001, tree [000008], tree -> 0 Propagating assertions for BB01, stmt STMT00001, tree [000009], tree -> 0 Propagating assertions for BB01, stmt STMT00001, tree [000010], tree -> 0 Propagating assertions for BB01, stmt STMT00001, tree [000011], tree -> 1 Propagating assertions for BB01, stmt STMT00001, tree [000003], tree -> 0 Propagating assertions for BB01, stmt STMT00001, tree [000012], tree -> 0 Propagating assertions for BB01, stmt STMT00002, tree [000103], tree -> 0 Propagating assertions for BB01, stmt STMT00002, tree [000018], tree -> 0 Propagating assertions for BB01, stmt STMT00002, tree [000019], tree -> 0 Propagating assertions for BB01, stmt STMT00002, tree [000020], tree -> 0 Propagating assertions for BB01, stmt STMT00002, tree [000021], tree -> 0 Propagating assertions for BB01, stmt STMT00003, tree [000022], tree -> 0 Propagating assertions for BB01, stmt STMT00003, tree [000023], tree -> 0 Propagating assertions for BB01, stmt STMT00003, tree [000024], tree -> 0 Propagating assertions for BB01, stmt STMT00003, tree [000025], tree -> 2 Propagating assertions for BB01, stmt STMT00003, tree [000017], tree -> 0 Propagating assertions for BB01, stmt STMT00003, tree [000026], tree -> 0 Propagating assertions for BB01, stmt STMT00010, tree [000013], tree -> 0 Propagating assertions for BB01, stmt STMT00010, tree [000014], tree -> 0 Propagating assertions for BB01, stmt STMT00010, tree [000062], tree -> 0 Propagating assertions for BB01, stmt STMT00010, tree [000063], tree -> 0 Propagating assertions for BB01, stmt STMT00011, tree [000027], tree -> 0 Propagating assertions for BB01, stmt STMT00011, tree [000028], tree -> 0 Propagating assertions for BB01, stmt STMT00011, tree [000067], tree -> 0 Propagating assertions for BB01, stmt STMT00011, tree [000068], tree -> 0 Propagating assertions for BB01, stmt STMT00012, tree [000071], tree -> 0 Propagating assertions for BB01, stmt STMT00012, tree [000072], tree -> 0 Propagating assertions for BB01, stmt STMT00012, tree [000073], tree -> 0 Propagating assertions for BB01, stmt STMT00013, tree [000104], tree -> 0 Propagating assertions for BB01, stmt STMT00013, tree [000076], tree -> 0 Propagating assertions for BB01, stmt STMT00013, tree [000077], tree -> 0 Propagating assertions for BB01, stmt STMT00013, tree [000078], tree -> 0 Propagating assertions for BB01, stmt STMT00015, tree [000108], tree -> 0 Propagating assertions for BB01, stmt STMT00015, tree [000107], tree -> 0 Propagating assertions for BB01, stmt STMT00015, tree [000110], tree -> 0 Propagating assertions for BB01, stmt STMT00015, tree [000111], tree -> 0 Propagating assertions for BB01, stmt STMT00015, tree [000154], tree -> 0 Propagating assertions for BB01, stmt STMT00015, tree [000113], tree -> 0 Propagating assertions for BB01, stmt STMT00015, tree [000109], tree -> 0 Propagating assertions for BB01, stmt STMT00015, tree [000105], tree -> 0 Propagating assertions for BB01, stmt STMT00015, tree [000106], tree -> 0 Propagating assertions for BB01, stmt STMT00015, tree [000046], tree -> 0 Propagating assertions for BB01, stmt STMT00015, tree [000054], tree -> 0 Propagating assertions for BB01, stmt STMT00015, tree [000084], tree -> 0 Propagating assertions for BB01, stmt STMT00015, tree [000085], tree -> 0 Propagating assertions for BB01, stmt STMT00014, tree [000115], tree -> 0 Propagating assertions for BB01, stmt STMT00014, tree [000114], tree -> 0 Propagating assertions for BB01, stmt STMT00014, tree [000082], tree -> 0 Propagating assertions for BB01, stmt STMT00014, tree [000081], tree -> 0 Propagating assertions for BB01, stmt STMT00014, tree [000083], tree -> 0 Propagating assertions for BB01, stmt STMT00018, tree [000116], tree -> 0 Propagating assertions for BB01, stmt STMT00018, tree [000032], tree -> 0 Propagating assertions for BB01, stmt STMT00018, tree [000097], tree -> 0 Propagating assertions for BB01, stmt STMT00018, tree [000098], tree -> 0 Propagating assertions for BB01, stmt STMT00019, tree [000033], tree -> 0 Propagating assertions for BB01, stmt STMT00019, tree [000117], tree -> 0 Propagating assertions for BB01, stmt STMT00019, tree [000118], tree -> 0 Propagating assertions for BB01, stmt STMT00019, tree [000034], tree -> 3 Propagating assertions for BB01, stmt STMT00019, tree [000099], tree -> 0 Propagating assertions for BB01, stmt STMT00019, tree [000100], tree -> 0 Propagating assertions for BB01, stmt STMT00016, tree [000087], tree -> 0 Propagating assertions for BB01, stmt STMT00016, tree [000088], tree -> 0 Propagating assertions for BB01, stmt STMT00016, tree [000119], tree -> 0 Propagating assertions for BB01, stmt STMT00016, tree [000120], tree -> 0 Propagating assertions for BB01, stmt STMT00016, tree [000089], tree -> 4 Propagating assertions for BB01, stmt STMT00016, tree [000090], tree -> 0 Propagating assertions for BB01, stmt STMT00016, tree [000091], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000092], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000140], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000141], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000093], tree -> 4 Non-null prop for index #04 in BB02: N004 ( 4, 4) [000093] ---XG------- * IND ref Propagating assertions for BB02, stmt STMT00020, tree [000125], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000126], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000094], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000127], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000130], tree -> 5 Propagating assertions for BB02, stmt STMT00020, tree [000131], tree -> 6 Propagating assertions for BB02, stmt STMT00020, tree [000128], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000129], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000132], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000133], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000134], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000135], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000136], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000137], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000095], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000138], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000139], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000144], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000145], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000148], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000149], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000037], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000142], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000143], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000044], tree -> 3 Non-null prop for index #03 in BB02: N029 ( 9, 7) [000044] ---XG------- * OBJ struct Propagating assertions for BB02, stmt STMT00020, tree [000147], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000146], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000151], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000152], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000150], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000124], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000121], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000040], tree -> 7 Propagating assertions for BB02, stmt STMT00020, tree [000122], tree -> 0 Propagating assertions for BB02, stmt STMT00020, tree [000123], tree -> 0 Re-morphing this stmt: STMT00020 (IL ???... ???) N039 ( 65, 73) [000123] -ACXG---R--- * ASG struct (copy) $VN.Void N038 ( 3, 2) [000122] D------N---- +--* LCL_VAR struct V17 tmp15 d:2 N037 ( 61, 70) [000040] -ACXG------- \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA $385 N023 ( 18, 22) [000145] -A-XG---R-L- this SETUP +--* ASG ref N022 ( 1, 1) [000144] D------N---- | +--* LCL_VAR ref V19 tmp17 d:2 N021 ( 18, 22) [000139] -A-XG------- | \--* COMMA ref N006 ( 4, 4) [000126] -A-XG---R--- | +--* ASG ref N005 ( 1, 1) [000125] D------N---- | | +--* LCL_VAR ref V18 tmp16 d:2 N004 ( 4, 4) [000093] n---GO------ | | \--* IND ref N003 ( 2, 2) [000141] -------N---- | | \--* ADD byref N001 ( 1, 1) [000092] ------------ | | +--* LCL_VAR ref V12 tmp10 u:2 (last use) N002 ( 1, 1) [000140] ------------ | | \--* CNS_INT long 8 field offset Fseq[_items] $240 N020 ( 14, 18) [000138] ---XG------- | \--* COMMA ref N010 ( 8, 11) [000131] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [000094] ------------ | | +--* LCL_VAR int V11 tmp9 u:2 N009 ( 3, 3) [000130] ---X-------- | | \--* ARR_LENGTH int N008 ( 1, 1) [000127] ------------ | | \--* LCL_VAR ref V18 tmp16 u:2 N019 ( 6, 7) [000095] a---G------- | \--* IND ref N018 ( 5, 6) [000137] -------N---- | \--* ADD byref $480 N011 ( 1, 1) [000128] ------------ | +--* LCL_VAR ref V18 tmp16 u:2 (last use) N017 ( 4, 5) [000136] -------N---- | \--* ADD long N015 ( 3, 4) [000134] -------N---- | +--* LSH long N013 ( 2, 3) [000132] ------------ | | +--* CAST long <- int N012 ( 1, 1) [000129] i----------- | | | \--* LCL_VAR int V11 tmp9 u:2 (last use) N014 ( 1, 1) [000133] -------N---- | | \--* CNS_INT long 3 $242 N016 ( 1, 1) [000135] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N029 ( 9, 7) [000044] n---GO------ arg3 out+00 +--* OBJ struct N028 ( 3, 3) [000143] ------------ | \--* ADD byref $289 N026 ( 1, 1) [000037] ------------ | +--* LCL_VAR byref V00 this u:1 (last use) $80 N027 ( 1, 1) [000142] ------------ | \--* CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] $245 N031 ( 1, 1) [000146] ------------ this in rdi +--* LCL_VAR ref V19 tmp17 u:2 (last use) N034 ( 6, 8) [000150] -c---------- arg4 rdx,rcx +--* FIELD_LIST struct $384 N032 ( 3, 4) [000151] ------------ ofs 0 | +--* LCL_FLD long V01 arg1 u:1[+0] $144 N033 ( 3, 4) [000152] ------------ ofs 8 | \--* LCL_FLD long V01 arg1 u:1[+8] (last use) $145 N035 ( 2, 10) [000124] ------------ arg1 in r11 +--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a N036 ( 2, 10) [000121] ------------ arg2 in rsi \--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a ReMorphing args for 40.CALL: argSlots=11, preallocatedArgCount=7, nextSlotNum=7, outgoingArgSpaceSize=56 ArgTable for 40.CALL after fgMorphArgs: fgArgTabEntry[arg 0 146.LCL_VAR ref (By ref), 1 reg: rdi, align=1, lateArgInx=0, tmpNum=V19, isTmp, processed] fgArgTabEntry[arg 3 44.OBJ struct (By value), numSlots=7, slotNum=0, align=1, processed, isStruct] fgArgTabEntry[arg 4 150.FIELD_LIST struct (By value), 2 regs: rdx rcx, align=1, lateArgInx=1, processed, isStruct] fgArgTabEntry[arg 1 124.CNS_INT long (By ref), 1 reg: r11, align=1, lateArgInx=2, processed, isNonStandard] fgArgTabEntry[arg 2 121.CNS_INT long (By ref), 1 reg: rsi, align=1, lateArgInx=3, processed] fgMorphCopyBlock: not morphing a multireg call return optAssertionPropMain morphed tree: N039 ( 65, 73) [000123] -ACXGO--R--- * ASG struct (copy) $VN.Void N038 ( 3, 2) [000122] D------N---- +--* LCL_VAR struct V17 tmp15 d:2 N037 ( 61, 70) [000040] -ACXGO------ \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA $385 N023 ( 18, 22) [000145] -A-XGO--R-L- this SETUP +--* ASG ref N022 ( 1, 1) [000144] D------N---- | +--* LCL_VAR ref V19 tmp17 d:2 N021 ( 18, 22) [000139] -A-XGO------ | \--* COMMA ref N006 ( 4, 4) [000126] -A--GO--R--- | +--* ASG ref N005 ( 1, 1) [000125] D------N---- | | +--* LCL_VAR ref V18 tmp16 d:2 N004 ( 4, 4) [000093] n---GO------ | | \--* IND ref N003 ( 2, 2) [000141] -------N---- | | \--* ADD byref N001 ( 1, 1) [000092] ------------ | | +--* LCL_VAR ref V12 tmp10 u:2 (last use) N002 ( 1, 1) [000140] ------------ | | \--* CNS_INT long 8 field offset Fseq[_items] $240 N020 ( 14, 18) [000138] ---XG------- | \--* COMMA ref N010 ( 8, 11) [000131] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [000094] ------------ | | +--* LCL_VAR int V11 tmp9 u:2 N009 ( 3, 3) [000130] ---X-------- | | \--* ARR_LENGTH int N008 ( 1, 1) [000127] ------------ | | \--* LCL_VAR ref V18 tmp16 u:2 N019 ( 6, 7) [000095] a---G------- | \--* IND ref N018 ( 5, 6) [000137] -------N---- | \--* ADD byref $480 N011 ( 1, 1) [000128] ------------ | +--* LCL_VAR ref V18 tmp16 u:2 (last use) N017 ( 4, 5) [000136] -------N---- | \--* ADD long N015 ( 3, 4) [000134] -------N---- | +--* LSH long N013 ( 2, 3) [000132] ------------ | | +--* CAST long <- int N012 ( 1, 1) [000129] i----------- | | | \--* LCL_VAR int V11 tmp9 u:2 (last use) N014 ( 1, 1) [000133] -------N---- | | \--* CNS_INT long 3 $242 N016 ( 1, 1) [000135] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N029 ( 9, 7) [000044] n---GO------ arg3 out+00 +--* OBJ struct N028 ( 3, 3) [000143] ------------ | \--* ADD byref $289 N026 ( 1, 1) [000037] ------------ | +--* LCL_VAR byref V00 this u:1 (last use) $80 N027 ( 1, 1) [000142] ------------ | \--* CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] $245 N031 ( 1, 1) [000146] ------------ this in rdi +--* LCL_VAR ref V19 tmp17 u:2 (last use) N034 ( 6, 8) [000150] -c---------- arg4 rdx,rcx +--* FIELD_LIST struct $384 N032 ( 3, 4) [000151] ------------ ofs 0 | +--* LCL_FLD long V01 arg1 u:1[+0] $144 N033 ( 3, 4) [000152] ------------ ofs 8 | \--* LCL_FLD long V01 arg1 u:1[+8] (last use) $145 N035 ( 2, 10) [000124] ------------ arg1 in r11 +--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a N036 ( 2, 10) [000121] ------------ arg2 in rsi \--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a Propagating assertions for BB02, stmt STMT00007, tree [000153], tree -> 0 Propagating assertions for BB02, stmt STMT00007, tree [000045], tree -> 0 Propagating assertions for BB03, stmt STMT00017, tree [000096], tree -> 0 *************** In fgDebugCheckBBlist *************** Finishing PHASE Assertion prop *************** Starting PHASE Optimize index checks *************** In OptimizeRangeChecks() Blocks/trees before phase ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj BB02 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 (IL 0x000...0x041) N005 ( 16, 16) [000007] -AC-----R--- * ASG ref $200 N004 ( 1, 1) [000006] D------N---- +--* LCL_VAR ref V03 tmp1 d:2 $200 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class $180 ***** BB01 STMT00001 (IL ???... ???) N006 ( 8, 9) [000012] -A--GO------ * ASG long $VN.Void N004 ( 4, 4) [000011] n----O-N---- +--* IND long $2c0 N003 ( 2, 2) [000010] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V03 tmp1 u:2 $200 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD long V01 arg1 u:1[+0] Fseq[JobGroup] $2c0 ***** BB01 STMT00002 (IL ???... ???) N005 ( 16, 16) [000021] -AC-----R--- * ASG ref $201 N004 ( 1, 1) [000020] D------N---- +--* LCL_VAR ref V04 tmp2 d:2 $201 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class $182 ***** BB01 STMT00003 (IL ???... ???) N006 ( 8, 9) [000026] -A--GO------ * ASG int $VN.Void N004 ( 4, 4) [000025] n----O-N---- +--* IND int $300 N003 ( 2, 2) [000024] -------N---- | \--* ADD byref $281 N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V04 tmp2 u:2 $201 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD int V01 arg1 u:1[+8] Fseq[Version] $300 ***** BB01 STMT00010 (IL ???... ???) N004 ( 11, 8) [000063] -A------R--- * ASG ref $200 N003 ( 3, 2) [000062] D------N---- +--* LCL_VAR ref V13 tmp11 d:2 $200 N002 ( 7, 5) [000014] ------------ \--* BOX ref $200 N001 ( 1, 1) [000013] ------------ \--* LCL_VAR ref V03 tmp1 u:2 (last use) $200 ***** BB01 STMT00011 (IL ???... ???) N004 ( 11, 8) [000068] -A------R--- * ASG ref $201 N003 ( 3, 2) [000067] D------N---- +--* LCL_VAR ref V14 tmp12 d:2 $201 N002 ( 7, 5) [000028] ------------ \--* BOX ref $201 N001 ( 1, 1) [000027] ------------ \--* LCL_VAR ref V04 tmp2 u:2 (last use) $201 ***** BB01 STMT00012 (IL ???... ???) N003 ( 5, 4) [000073] -A------R--- * ASG ref $VN.Null N002 ( 3, 2) [000072] D------N---- +--* LCL_VAR ref V15 tmp13 d:2 $VN.Null N001 ( 1, 1) [000071] ------------ \--* CNS_INT ref null $VN.Null ***** BB01 STMT00013 (IL ???... ???) N004 ( 8, 15) [000078] -A--G---R--- * ASG ref N003 ( 3, 2) [000077] D------N---- +--* LCL_VAR ref V16 tmp14 d:2 N002 ( 4, 12) [000076] n---G------- \--* IND ref N001 ( 2, 10) [000104] ------------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 ***** BB01 STMT00015 (IL ???... ???) N013 ( 32, 27) [000085] -ACXG---R--- * ASG ref $1ce N012 ( 1, 1) [000084] D------N---- +--* LCL_VAR ref V10 tmp8 d:2 $1ce N011 ( 32, 27) [000054] --CXG------- \--* CALL ref System.String.FormatHelper $1ce N007 ( 10, 7) [000109] -c---------- arg2 out+00 +--* FIELD_LIST struct $380 N003 ( 3, 2) [000110] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp11 u:2 (last use) $200 N004 ( 3, 2) [000111] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp12 u:2 (last use) $201 N005 ( 1, 1) [000154] ------------ ofs 16 | +--* CNS_INT ref null $VN.Null N006 ( 3, 2) [000113] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp14 u:2 (last use) N009 ( 4, 12) [000106] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000105] ------------ | \--* CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] $185 N010 ( 1, 1) [000046] ------------ arg0 in rdi \--* CNS_INT ref null $VN.Null ***** BB01 STMT00014 (IL ???... ???) N005 ( 16, 9) [000083] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void N003 ( 1, 1) [000082] ------------ arg1 in rsi +--* LCL_VAR ref V10 tmp8 u:2 (last use) $1ce N004 ( 1, 1) [000081] ------------ arg0 in rdi \--* CNS_INT int 3 $44 ***** BB01 STMT00018 (IL 0x025... ???) N004 ( 4, 12) [000098] -A--G---R--- * ASG ref N003 ( 1, 1) [000097] D------N---- +--* LCL_VAR ref V12 tmp10 d:2 N002 ( 4, 12) [000032] n---G------- \--* IND ref N001 ( 2, 10) [000116] ------------ \--* CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] $186 ***** BB01 STMT00019 (IL 0x025... ???) N006 ( 4, 4) [000100] -A-XG---R--- * ASG int N005 ( 1, 1) [000099] D------N---- +--* LCL_VAR int V11 tmp9 d:2 N004 ( 4, 4) [000034] *--XG------- \--* IND int N003 ( 2, 2) [000118] -------N---- \--* ADD byref $282 N001 ( 1, 1) [000033] ------------ +--* LCL_VAR byref V00 this u:1 $80 N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] $241 ***** BB01 STMT00016 (IL 0x025... ???) N007 ( 8, 8) [000091] ---XG------- * JTRUE void N006 ( 6, 6) [000090] N--XG--N-U-- \--* GE int N001 ( 1, 1) [000087] ------------ +--* LCL_VAR int V11 tmp9 u:2 N005 ( 4, 4) [000089] ---XG------- \--* IND int N004 ( 2, 2) [000120] -------N---- \--* ADD byref N002 ( 1, 1) [000088] ------------ +--* LCL_VAR ref V12 tmp10 u:2 N003 ( 1, 1) [000119] ------------ \--* CNS_INT long 16 field offset Fseq[_size] $241 ------------ BB02 [025..026) (return), preds={BB01} succs={} ***** BB02 STMT00020 (IL ???... ???) N039 ( 65, 73) [000123] -ACXGO--R--- * ASG struct (copy) $VN.Void N038 ( 3, 2) [000122] D------N---- +--* LCL_VAR struct V17 tmp15 d:2 N037 ( 61, 70) [000040] -ACXGO------ \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA $385 N023 ( 18, 22) [000145] -A-XGO--R-L- this SETUP +--* ASG ref N022 ( 1, 1) [000144] D------N---- | +--* LCL_VAR ref V19 tmp17 d:2 N021 ( 18, 22) [000139] -A-XGO------ | \--* COMMA ref N006 ( 4, 4) [000126] -A--GO--R--- | +--* ASG ref N005 ( 1, 1) [000125] D------N---- | | +--* LCL_VAR ref V18 tmp16 d:2 N004 ( 4, 4) [000093] n---GO------ | | \--* IND ref N003 ( 2, 2) [000141] -------N---- | | \--* ADD byref N001 ( 1, 1) [000092] ------------ | | +--* LCL_VAR ref V12 tmp10 u:2 (last use) N002 ( 1, 1) [000140] ------------ | | \--* CNS_INT long 8 field offset Fseq[_items] $240 N020 ( 14, 18) [000138] ---XG------- | \--* COMMA ref N010 ( 8, 11) [000131] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [000094] ------------ | | +--* LCL_VAR int V11 tmp9 u:2 N009 ( 3, 3) [000130] ---X-------- | | \--* ARR_LENGTH int N008 ( 1, 1) [000127] ------------ | | \--* LCL_VAR ref V18 tmp16 u:2 N019 ( 6, 7) [000095] a---G------- | \--* IND ref N018 ( 5, 6) [000137] -------N---- | \--* ADD byref $480 N011 ( 1, 1) [000128] ------------ | +--* LCL_VAR ref V18 tmp16 u:2 (last use) N017 ( 4, 5) [000136] -------N---- | \--* ADD long N015 ( 3, 4) [000134] -------N---- | +--* LSH long N013 ( 2, 3) [000132] ------------ | | +--* CAST long <- int N012 ( 1, 1) [000129] i----------- | | | \--* LCL_VAR int V11 tmp9 u:2 (last use) N014 ( 1, 1) [000133] -------N---- | | \--* CNS_INT long 3 $242 N016 ( 1, 1) [000135] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N029 ( 9, 7) [000044] n---GO------ arg3 out+00 +--* OBJ struct N028 ( 3, 3) [000143] ------------ | \--* ADD byref $289 N026 ( 1, 1) [000037] ------------ | +--* LCL_VAR byref V00 this u:1 (last use) $80 N027 ( 1, 1) [000142] ------------ | \--* CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] $245 N031 ( 1, 1) [000146] ------------ this in rdi +--* LCL_VAR ref V19 tmp17 u:2 (last use) N034 ( 6, 8) [000150] -c---------- arg4 rdx,rcx +--* FIELD_LIST struct $384 N032 ( 3, 4) [000151] ------------ ofs 0 | +--* LCL_FLD long V01 arg1 u:1[+0] $144 N033 ( 3, 4) [000152] ------------ ofs 8 | \--* LCL_FLD long V01 arg1 u:1[+8] (last use) $145 N035 ( 2, 10) [000124] ------------ arg1 in r11 +--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a N036 ( 2, 10) [000121] ------------ arg2 in rsi \--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a ***** BB02 STMT00007 (IL ???... ???) N002 ( 4, 3) [000045] ----G------- * RETURN struct $389 N001 ( 3, 2) [000153] -------N---- \--* LCL_VAR struct V17 tmp15 u:2 (last use) $388 ------------ BB03 [025..026) (throw), preds={BB01} succs={} ***** BB03 STMT00017 (IL 0x025... ???) N001 ( 14, 5) [000096] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException $VN.Void ------------------------------------------------------------------------------------------------------------------- ArrSize for lengthVN:441 = 0 [RangeCheck::GetRange] BB02N007 ( 1, 1) [000094] ------------ * LCL_VAR int V11 tmp9 u:2 { ---------------------------------------------------- N006 ( 4, 4) [000100] -A-XG---R--- * ASG int N005 ( 1, 1) [000099] D------N---- +--* LCL_VAR int V11 tmp9 d:2 N004 ( 4, 4) [000034] *--XG------- \--* IND int N003 ( 2, 2) [000118] -------N---- \--* ADD byref $282 N001 ( 1, 1) [000033] ------------ +--* LCL_VAR byref V00 this u:1 $80 N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] $241 ---------------------------------------------------- [RangeCheck::GetRange] BB01N004 ( 4, 4) [000034] *--XG------- * IND int N003 ( 2, 2) [000118] -------N---- \--* ADD byref $282 N001 ( 1, 1) [000033] ------------ +--* LCL_VAR byref V00 this u:1 $80 N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] $241 { Computed Range [000034] => } Merge assertions from BB02: for assignment about [000099] done merging Merging assertions from pred edges of BB02 for op [000094] $3c1 Computed Range [000094] => } *************** Finishing PHASE Optimize index checks *************** Starting PHASE Insert GC Polls *************** Finishing PHASE Insert GC Polls [no changes] *************** Starting PHASE Determine first cold block *************** In fgDetermineFirstColdBlock() No procedure splitting will be done for this method *************** Finishing PHASE Determine first cold block Trees before Rationalize IR ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj BB02 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 (IL 0x000...0x041) N005 ( 16, 16) [000007] -AC-----R--- * ASG ref $200 N004 ( 1, 1) [000006] D------N---- +--* LCL_VAR ref V03 tmp1 d:2 $200 N003 ( 16, 16) [000005] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 N002 ( 2, 10) [000004] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678c127f0 class $180 ***** BB01 STMT00001 (IL ???... ???) N006 ( 8, 9) [000012] -A--GO------ * ASG long $VN.Void N004 ( 4, 4) [000011] n----O-N---- +--* IND long $2c0 N003 ( 2, 2) [000010] -------N---- | \--* ADD byref $280 N001 ( 1, 1) [000008] ------------ | +--* LCL_VAR ref V03 tmp1 u:2 $200 N002 ( 1, 1) [000009] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000003] ------------ \--* LCL_FLD long V01 arg1 u:1[+0] Fseq[JobGroup] $2c0 ***** BB01 STMT00002 (IL ???... ???) N005 ( 16, 16) [000021] -AC-----R--- * ASG ref $201 N004 ( 1, 1) [000020] D------N---- +--* LCL_VAR ref V04 tmp2 d:2 $201 N003 ( 16, 16) [000019] --C--------- \--* CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 N002 ( 2, 10) [000018] ------------ arg0 in rdi \--* CNS_INT(h) long 0x7f6678beb1c0 class $182 ***** BB01 STMT00003 (IL ???... ???) N006 ( 8, 9) [000026] -A--GO------ * ASG int $VN.Void N004 ( 4, 4) [000025] n----O-N---- +--* IND int $300 N003 ( 2, 2) [000024] -------N---- | \--* ADD byref $281 N001 ( 1, 1) [000022] ------------ | +--* LCL_VAR ref V04 tmp2 u:2 $201 N002 ( 1, 1) [000023] ------------ | \--* CNS_INT long 8 $240 N005 ( 3, 4) [000017] ------------ \--* LCL_FLD int V01 arg1 u:1[+8] Fseq[Version] $300 ***** BB01 STMT00010 (IL ???... ???) N004 ( 11, 8) [000063] -A------R--- * ASG ref $200 N003 ( 3, 2) [000062] D------N---- +--* LCL_VAR ref V13 tmp11 d:2 $200 N002 ( 7, 5) [000014] ------------ \--* BOX ref $200 N001 ( 1, 1) [000013] ------------ \--* LCL_VAR ref V03 tmp1 u:2 (last use) $200 ***** BB01 STMT00011 (IL ???... ???) N004 ( 11, 8) [000068] -A------R--- * ASG ref $201 N003 ( 3, 2) [000067] D------N---- +--* LCL_VAR ref V14 tmp12 d:2 $201 N002 ( 7, 5) [000028] ------------ \--* BOX ref $201 N001 ( 1, 1) [000027] ------------ \--* LCL_VAR ref V04 tmp2 u:2 (last use) $201 ***** BB01 STMT00012 (IL ???... ???) N003 ( 5, 4) [000073] -A------R--- * ASG ref $VN.Null N002 ( 3, 2) [000072] D------N---- +--* LCL_VAR ref V15 tmp13 d:2 $VN.Null N001 ( 1, 1) [000071] ------------ \--* CNS_INT ref null $VN.Null ***** BB01 STMT00013 (IL ???... ???) N004 ( 8, 15) [000078] -A--G---R--- * ASG ref N003 ( 3, 2) [000077] D------N---- +--* LCL_VAR ref V16 tmp14 d:2 N002 ( 4, 12) [000076] n---G------- \--* IND ref N001 ( 2, 10) [000104] ------------ \--* CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 ***** BB01 STMT00015 (IL ???... ???) N013 ( 32, 27) [000085] -ACXG---R--- * ASG ref $1ce N012 ( 1, 1) [000084] D------N---- +--* LCL_VAR ref V10 tmp8 d:2 $1ce N011 ( 32, 27) [000054] --CXG------- \--* CALL ref System.String.FormatHelper $1ce N007 ( 10, 7) [000109] -c---------- arg2 out+00 +--* FIELD_LIST struct $380 N003 ( 3, 2) [000110] ------------ ofs 0 | +--* LCL_VAR ref V13 tmp11 u:2 (last use) $200 N004 ( 3, 2) [000111] ------------ ofs 8 | +--* LCL_VAR ref V14 tmp12 u:2 (last use) $201 N005 ( 1, 1) [000154] ------------ ofs 16 | +--* CNS_INT ref null $VN.Null N006 ( 3, 2) [000113] ------------ ofs 24 | \--* LCL_VAR ref V16 tmp14 u:2 (last use) N009 ( 4, 12) [000106] n---G------- arg1 in rsi +--* IND ref N008 ( 2, 10) [000105] ------------ | \--* CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] $185 N010 ( 1, 1) [000046] ------------ arg0 in rdi \--* CNS_INT ref null $VN.Null ***** BB01 STMT00014 (IL ???... ???) N005 ( 16, 9) [000083] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void N003 ( 1, 1) [000082] ------------ arg1 in rsi +--* LCL_VAR ref V10 tmp8 u:2 (last use) $1ce N004 ( 1, 1) [000081] ------------ arg0 in rdi \--* CNS_INT int 3 $44 ***** BB01 STMT00018 (IL 0x025... ???) N004 ( 4, 12) [000098] -A--G---R--- * ASG ref N003 ( 1, 1) [000097] D------N---- +--* LCL_VAR ref V12 tmp10 d:2 N002 ( 4, 12) [000032] n---G------- \--* IND ref N001 ( 2, 10) [000116] ------------ \--* CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] $186 ***** BB01 STMT00019 (IL 0x025... ???) N006 ( 4, 4) [000100] -A-XG---R--- * ASG int N005 ( 1, 1) [000099] D------N---- +--* LCL_VAR int V11 tmp9 d:2 N004 ( 4, 4) [000034] *--XG------- \--* IND int N003 ( 2, 2) [000118] -------N---- \--* ADD byref $282 N001 ( 1, 1) [000033] ------------ +--* LCL_VAR byref V00 this u:1 $80 N002 ( 1, 1) [000117] ------------ \--* CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] $241 ***** BB01 STMT00016 (IL 0x025... ???) N007 ( 8, 8) [000091] ---XG------- * JTRUE void N006 ( 6, 6) [000090] N--XG--N-U-- \--* GE int N001 ( 1, 1) [000087] ------------ +--* LCL_VAR int V11 tmp9 u:2 N005 ( 4, 4) [000089] ---XG------- \--* IND int N004 ( 2, 2) [000120] -------N---- \--* ADD byref N002 ( 1, 1) [000088] ------------ +--* LCL_VAR ref V12 tmp10 u:2 N003 ( 1, 1) [000119] ------------ \--* CNS_INT long 16 field offset Fseq[_size] $241 ------------ BB02 [025..026) (return), preds={BB01} succs={} ***** BB02 STMT00020 (IL ???... ???) N039 ( 65, 73) [000123] -ACXGO--R--- * ASG struct (copy) $VN.Void N038 ( 3, 2) [000122] D------N---- +--* LCL_VAR struct V17 tmp15 d:2 N037 ( 61, 70) [000040] -ACXGO------ \--* CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA $385 N023 ( 18, 22) [000145] -A-XGO--R-L- this SETUP +--* ASG ref N022 ( 1, 1) [000144] D------N---- | +--* LCL_VAR ref V19 tmp17 d:2 N021 ( 18, 22) [000139] -A-XGO------ | \--* COMMA ref N006 ( 4, 4) [000126] -A--GO--R--- | +--* ASG ref N005 ( 1, 1) [000125] D------N---- | | +--* LCL_VAR ref V18 tmp16 d:2 N004 ( 4, 4) [000093] n---GO------ | | \--* IND ref N003 ( 2, 2) [000141] -------N---- | | \--* ADD byref N001 ( 1, 1) [000092] ------------ | | +--* LCL_VAR ref V12 tmp10 u:2 (last use) N002 ( 1, 1) [000140] ------------ | | \--* CNS_INT long 8 field offset Fseq[_items] $240 N020 ( 14, 18) [000138] ---XG------- | \--* COMMA ref N010 ( 8, 11) [000131] ---X-------- | +--* ARR_BOUNDS_CHECK_Rng void N007 ( 1, 1) [000094] ------------ | | +--* LCL_VAR int V11 tmp9 u:2 N009 ( 3, 3) [000130] ---X-------- | | \--* ARR_LENGTH int N008 ( 1, 1) [000127] ------------ | | \--* LCL_VAR ref V18 tmp16 u:2 N019 ( 6, 7) [000095] a---G------- | \--* IND ref N018 ( 5, 6) [000137] -------N---- | \--* ADD byref $480 N011 ( 1, 1) [000128] ------------ | +--* LCL_VAR ref V18 tmp16 u:2 (last use) N017 ( 4, 5) [000136] -------N---- | \--* ADD long N015 ( 3, 4) [000134] -------N---- | +--* LSH long N013 ( 2, 3) [000132] ------------ | | +--* CAST long <- int N012 ( 1, 1) [000129] i----------- | | | \--* LCL_VAR int V11 tmp9 u:2 (last use) N014 ( 1, 1) [000133] -------N---- | | \--* CNS_INT long 3 $242 N016 ( 1, 1) [000135] ------------ | \--* CNS_INT long 16 Fseq[#FirstElem] $241 N029 ( 9, 7) [000044] n---GO------ arg3 out+00 +--* OBJ struct N028 ( 3, 3) [000143] ------------ | \--* ADD byref $289 N026 ( 1, 1) [000037] ------------ | +--* LCL_VAR byref V00 this u:1 (last use) $80 N027 ( 1, 1) [000142] ------------ | \--* CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] $245 N031 ( 1, 1) [000146] ------------ this in rdi +--* LCL_VAR ref V19 tmp17 u:2 (last use) N034 ( 6, 8) [000150] -c---------- arg4 rdx,rcx +--* FIELD_LIST struct $384 N032 ( 3, 4) [000151] ------------ ofs 0 | +--* LCL_FLD long V01 arg1 u:1[+0] $144 N033 ( 3, 4) [000152] ------------ ofs 8 | \--* LCL_FLD long V01 arg1 u:1[+8] (last use) $145 N035 ( 2, 10) [000124] ------------ arg1 in r11 +--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a N036 ( 2, 10) [000121] ------------ arg2 in rsi \--* CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a ***** BB02 STMT00007 (IL ???... ???) N002 ( 4, 3) [000045] ----G------- * RETURN struct $389 N001 ( 3, 2) [000153] -------N---- \--* LCL_VAR struct V17 tmp15 u:2 (last use) $388 ------------ BB03 [025..026) (throw), preds={BB01} succs={} ***** BB03 STMT00017 (IL 0x025... ???) N001 ( 14, 5) [000096] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Rationalize IR rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 16, 16) [000007] DAC--------- * STORE_LCL_VAR ref V03 tmp1 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N005 ( 16, 16) [000021] DAC--------- * STORE_LCL_VAR ref V04 tmp2 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 11, 8) [000063] DA---------- * STORE_LCL_VAR ref V13 tmp11 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 11, 8) [000068] DA---------- * STORE_LCL_VAR ref V14 tmp12 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000073] DA---------- * STORE_LCL_VAR ref V15 tmp13 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 8, 15) [000078] DA--G------- * STORE_LCL_VAR ref V16 tmp14 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N013 ( 32, 27) [000085] DACXG------- * STORE_LCL_VAR ref V10 tmp8 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N004 ( 4, 12) [000098] DA--G------- * STORE_LCL_VAR ref V12 tmp10 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 4) [000100] DA-XG------- * STORE_LCL_VAR int V11 tmp9 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 4) [000126] DA--GO------ * STORE_LCL_VAR ref V18 tmp16 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N023 ( 18, 22) [000145] DA-XGO----L- * STORE_LCL_VAR ref V19 tmp17 d:2 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N039 ( 65, 73) [000123] DACXGO------ * STORE_LCL_VAR struct V17 tmp15 d:2 *************** Finishing PHASE Rationalize IR Trees after Rationalize IR ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj LIR BB02 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj LIR BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) -> BB03 (cond), preds={} succs={BB02,BB03} [000155] ------------ IL_OFFSET void IL offset: 0x0 N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class $180 /--* t4 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 /--* t5 ref N005 ( 16, 16) [000007] DA---------- * STORE_LCL_VAR ref V03 tmp1 d:2 N001 ( 1, 1) [000008] ------------ t8 = LCL_VAR ref V03 tmp1 u:2 $200 N002 ( 1, 1) [000009] ------------ t9 = CNS_INT long 8 $240 /--* t8 ref +--* t9 long N003 ( 2, 2) [000010] -------N---- t10 = * ADD byref $280 N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD long V01 arg1 u:1[+0] Fseq[JobGroup] $2c0 /--* t10 byref +--* t3 long [000156] -A--GO------ * STOREIND long N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class $182 /--* t18 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 /--* t19 ref N005 ( 16, 16) [000021] DA---------- * STORE_LCL_VAR ref V04 tmp2 d:2 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V04 tmp2 u:2 $201 N002 ( 1, 1) [000023] ------------ t23 = CNS_INT long 8 $240 /--* t22 ref +--* t23 long N003 ( 2, 2) [000024] -------N---- t24 = * ADD byref $281 N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD int V01 arg1 u:1[+8] Fseq[Version] $300 /--* t24 byref +--* t17 int [000157] -A--GO------ * STOREIND int N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR ref V03 tmp1 u:2 (last use) $200 /--* t13 ref N004 ( 11, 8) [000063] DA---------- * STORE_LCL_VAR ref V13 tmp11 d:2 N001 ( 1, 1) [000027] ------------ t27 = LCL_VAR ref V04 tmp2 u:2 (last use) $201 /--* t27 ref N004 ( 11, 8) [000068] DA---------- * STORE_LCL_VAR ref V14 tmp12 d:2 N001 ( 1, 1) [000071] ------------ t71 = CNS_INT ref null $VN.Null /--* t71 ref N003 ( 5, 4) [000073] DA---------- * STORE_LCL_VAR ref V15 tmp13 d:2 N001 ( 2, 10) [000104] ------------ t104 = CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 /--* t104 long N002 ( 4, 12) [000076] n---G------- t76 = * IND ref /--* t76 ref N004 ( 8, 15) [000078] DA--G------- * STORE_LCL_VAR ref V16 tmp14 d:2 N003 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V13 tmp11 u:2 (last use) $200 N004 ( 3, 2) [000111] ------------ t111 = LCL_VAR ref V14 tmp12 u:2 (last use) $201 N005 ( 1, 1) [000154] ------------ t154 = CNS_INT ref null $VN.Null N006 ( 3, 2) [000113] ------------ t113 = LCL_VAR ref V16 tmp14 u:2 (last use) /--* t110 ref +--* t111 ref +--* t154 ref +--* t113 ref N007 ( 10, 7) [000109] -c---------- t109 = * FIELD_LIST struct $380 N008 ( 2, 10) [000105] ------------ t105 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] $185 /--* t105 long N009 ( 4, 12) [000106] n---G------- t106 = * IND ref N010 ( 1, 1) [000046] ------------ t46 = CNS_INT ref null $VN.Null /--* t109 struct arg2 out+00 +--* t106 ref arg1 in rsi +--* t46 ref arg0 in rdi N011 ( 32, 27) [000054] --CXG------- t54 = * CALL ref System.String.FormatHelper $1ce /--* t54 ref N013 ( 32, 27) [000085] DA-XG------- * STORE_LCL_VAR ref V10 tmp8 d:2 N003 ( 1, 1) [000082] ------------ t82 = LCL_VAR ref V10 tmp8 u:2 (last use) $1ce N004 ( 1, 1) [000081] ------------ t81 = CNS_INT int 3 $44 /--* t82 ref arg1 in rsi +--* t81 int arg0 in rdi N005 ( 16, 9) [000083] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void [000158] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 2, 10) [000116] ------------ t116 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] $186 /--* t116 long N002 ( 4, 12) [000032] n---G------- t32 = * IND ref /--* t32 ref N004 ( 4, 12) [000098] DA--G------- * STORE_LCL_VAR ref V12 tmp10 d:2 [000159] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 1, 1) [000033] ------------ t33 = LCL_VAR byref V00 this u:1 $80 N002 ( 1, 1) [000117] ------------ t117 = CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] $241 /--* t33 byref +--* t117 long N003 ( 2, 2) [000118] -------N---- t118 = * ADD byref $282 /--* t118 byref N004 ( 4, 4) [000034] *--XG------- t34 = * IND int /--* t34 int N006 ( 4, 4) [000100] DA-XG------- * STORE_LCL_VAR int V11 tmp9 d:2 [000160] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 1, 1) [000087] ------------ t87 = LCL_VAR int V11 tmp9 u:2 N002 ( 1, 1) [000088] ------------ t88 = LCL_VAR ref V12 tmp10 u:2 N003 ( 1, 1) [000119] ------------ t119 = CNS_INT long 16 field offset Fseq[_size] $241 /--* t88 ref +--* t119 long N004 ( 2, 2) [000120] -------N---- t120 = * ADD byref /--* t120 byref N005 ( 4, 4) [000089] ---XG------- t89 = * IND int /--* t87 int +--* t89 int N006 ( 6, 6) [000090] N--XG--N-U-- t90 = * GE int /--* t90 int N007 ( 8, 8) [000091] ---XG------- * JTRUE void ------------ BB02 [025..026) (return), preds={BB01} succs={} N001 ( 1, 1) [000092] ------------ t92 = LCL_VAR ref V12 tmp10 u:2 (last use) N002 ( 1, 1) [000140] ------------ t140 = CNS_INT long 8 field offset Fseq[_items] $240 /--* t92 ref +--* t140 long N003 ( 2, 2) [000141] -------N---- t141 = * ADD byref /--* t141 byref N004 ( 4, 4) [000093] n---GO------ t93 = * IND ref /--* t93 ref N006 ( 4, 4) [000126] DA--GO------ * STORE_LCL_VAR ref V18 tmp16 d:2 N007 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V11 tmp9 u:2 N008 ( 1, 1) [000127] ------------ t127 = LCL_VAR ref V18 tmp16 u:2 /--* t127 ref N009 ( 3, 3) [000130] ---X-------- t130 = * ARR_LENGTH int /--* t94 int +--* t130 int N010 ( 8, 11) [000131] ---X-------- * ARR_BOUNDS_CHECK_Rng void N011 ( 1, 1) [000128] ------------ t128 = LCL_VAR ref V18 tmp16 u:2 (last use) N012 ( 1, 1) [000129] ------------ t129 = LCL_VAR int V11 tmp9 u:2 (last use) /--* t129 int N013 ( 2, 3) [000132] ------------ t132 = * CAST long <- int N014 ( 1, 1) [000133] -------N---- t133 = CNS_INT long 3 $242 /--* t132 long +--* t133 long N015 ( 3, 4) [000134] -------N---- t134 = * LSH long N016 ( 1, 1) [000135] ------------ t135 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t134 long +--* t135 long N017 ( 4, 5) [000136] -------N---- t136 = * ADD long /--* t128 ref +--* t136 long N018 ( 5, 6) [000137] -------N---- t137 = * ADD byref $480 /--* t137 byref N019 ( 6, 7) [000095] a---G------- t95 = * IND ref /--* t95 ref N023 ( 18, 22) [000145] DA-XGO----L- * STORE_LCL_VAR ref V19 tmp17 d:2 N026 ( 1, 1) [000037] ------------ t37 = LCL_VAR byref V00 this u:1 (last use) $80 N027 ( 1, 1) [000142] ------------ t142 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] $245 /--* t37 byref +--* t142 long N028 ( 3, 3) [000143] ------------ t143 = * ADD byref $289 /--* t143 byref N029 ( 9, 7) [000044] n---GO------ t44 = * OBJ struct N031 ( 1, 1) [000146] ------------ t146 = LCL_VAR ref V19 tmp17 u:2 (last use) N032 ( 3, 4) [000151] ------------ t151 = LCL_FLD long V01 arg1 u:1[+0] $144 N033 ( 3, 4) [000152] ------------ t152 = LCL_FLD long V01 arg1 u:1[+8] (last use) $145 /--* t151 long +--* t152 long N034 ( 6, 8) [000150] -c---------- t150 = * FIELD_LIST struct $384 N035 ( 2, 10) [000124] ------------ t124 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a N036 ( 2, 10) [000121] ------------ t121 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a /--* t44 struct arg3 out+00 +--* t146 ref this in rdi +--* t150 struct arg4 rdx,rcx +--* t124 long arg1 in r11 +--* t121 long arg2 in rsi N037 ( 61, 70) [000040] --CXGO------ t40 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA $385 /--* t40 struct N039 ( 65, 73) [000123] DA-XGO------ * STORE_LCL_VAR struct V17 tmp15 d:2 N001 ( 3, 2) [000153] -------N---- t153 = LCL_VAR struct V17 tmp15 u:2 (last use) $388 /--* t153 struct N002 ( 4, 3) [000045] ----G------- * RETURN struct $389 ------------ BB03 [025..026) (throw), preds={BB01} succs={} [000161] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 14, 5) [000096] --CXG------- CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Starting PHASE Do 'simple' lowering outgoingArgSpaceSize 0 sufficient for call [000005], which needs 0 outgoingArgSpaceSize 0 sufficient for call [000019], which needs 0 Bumping outgoingArgSpaceSize to 32 for call [000054] outgoingArgSpaceSize 32 sufficient for call [000083], which needs 0 *** Computing fgRngChkTarget for block BB02 fgNewBBinRegion(jumpKind=3, tryIndex=0, hndIndex=0, putInFilter=false, runRarely=true, insertAtEnd=true): inserting after BB03 New Basic Block BB04 [0008] created. fgAddCodeRef - Add BB in non-EH region for RNGCHK_FAIL, new block BB04 [0008] Initializing arg info for 164.CALL: ArgTable for 164.CALL after fgInitArgInfo: Morphing args for 164.CALL: argSlots=0, preallocatedArgCount=0, nextSlotNum=0, outgoingArgSpaceSize=0 ArgTable for 164.CALL after fgMorphArgs: Bumping outgoingArgSpaceSize to 56 for call [000040] outgoingArgSpaceSize 56 sufficient for call [000096], which needs 0 outgoingArgSpaceSize 56 sufficient for call [000164], which needs 0 After fgSimpleLowering() added some RngChk throw blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj LIR BB02 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj LIR BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe LIR BB04 [0008] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** Finishing PHASE Do 'simple' lowering *************** In fgDebugCheckBBlist Trees before Lowering nodeinfo ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj LIR BB02 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj LIR BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe LIR BB04 [0008] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) -> BB03 (cond), preds={} succs={BB02,BB03} [000155] ------------ IL_OFFSET void IL offset: 0x0 N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class $180 /--* t4 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 /--* t5 ref N005 ( 16, 16) [000007] DA---------- * STORE_LCL_VAR ref V03 tmp1 d:2 N001 ( 1, 1) [000008] ------------ t8 = LCL_VAR ref V03 tmp1 u:2 $200 N002 ( 1, 1) [000009] ------------ t9 = CNS_INT long 8 $240 /--* t8 ref +--* t9 long N003 ( 2, 2) [000010] -------N---- t10 = * ADD byref $280 N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD long V01 arg1 u:1[+0] Fseq[JobGroup] $2c0 /--* t10 byref +--* t3 long [000156] -A--GO------ * STOREIND long N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class $182 /--* t18 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 /--* t19 ref N005 ( 16, 16) [000021] DA---------- * STORE_LCL_VAR ref V04 tmp2 d:2 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V04 tmp2 u:2 $201 N002 ( 1, 1) [000023] ------------ t23 = CNS_INT long 8 $240 /--* t22 ref +--* t23 long N003 ( 2, 2) [000024] -------N---- t24 = * ADD byref $281 N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD int V01 arg1 u:1[+8] Fseq[Version] $300 /--* t24 byref +--* t17 int [000157] -A--GO------ * STOREIND int N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR ref V03 tmp1 u:2 (last use) $200 /--* t13 ref N004 ( 11, 8) [000063] DA---------- * STORE_LCL_VAR ref V13 tmp11 d:2 N001 ( 1, 1) [000027] ------------ t27 = LCL_VAR ref V04 tmp2 u:2 (last use) $201 /--* t27 ref N004 ( 11, 8) [000068] DA---------- * STORE_LCL_VAR ref V14 tmp12 d:2 N001 ( 1, 1) [000071] ------------ t71 = CNS_INT ref null $VN.Null /--* t71 ref N003 ( 5, 4) [000073] DA---------- * STORE_LCL_VAR ref V15 tmp13 d:2 N001 ( 2, 10) [000104] ------------ t104 = CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 /--* t104 long N002 ( 4, 12) [000076] n---G------- t76 = * IND ref /--* t76 ref N004 ( 8, 15) [000078] DA--G------- * STORE_LCL_VAR ref V16 tmp14 d:2 N003 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V13 tmp11 u:2 (last use) $200 N004 ( 3, 2) [000111] ------------ t111 = LCL_VAR ref V14 tmp12 u:2 (last use) $201 N005 ( 1, 1) [000154] ------------ t154 = CNS_INT ref null $VN.Null N006 ( 3, 2) [000113] ------------ t113 = LCL_VAR ref V16 tmp14 u:2 (last use) /--* t110 ref +--* t111 ref +--* t154 ref +--* t113 ref N007 ( 10, 7) [000109] -c---------- t109 = * FIELD_LIST struct $380 N008 ( 2, 10) [000105] ------------ t105 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] $185 /--* t105 long N009 ( 4, 12) [000106] n---G------- t106 = * IND ref N010 ( 1, 1) [000046] ------------ t46 = CNS_INT ref null $VN.Null /--* t109 struct arg2 out+00 +--* t106 ref arg1 in rsi +--* t46 ref arg0 in rdi N011 ( 32, 27) [000054] --CXG------- t54 = * CALL ref System.String.FormatHelper $1ce /--* t54 ref N013 ( 32, 27) [000085] DA-XG------- * STORE_LCL_VAR ref V10 tmp8 d:2 N003 ( 1, 1) [000082] ------------ t82 = LCL_VAR ref V10 tmp8 u:2 (last use) $1ce N004 ( 1, 1) [000081] ------------ t81 = CNS_INT int 3 $44 /--* t82 ref arg1 in rsi +--* t81 int arg0 in rdi N005 ( 16, 9) [000083] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void [000158] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 2, 10) [000116] ------------ t116 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] $186 /--* t116 long N002 ( 4, 12) [000032] n---G------- t32 = * IND ref /--* t32 ref N004 ( 4, 12) [000098] DA--G------- * STORE_LCL_VAR ref V12 tmp10 d:2 [000159] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 1, 1) [000033] ------------ t33 = LCL_VAR byref V00 this u:1 $80 N002 ( 1, 1) [000117] ------------ t117 = CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] $241 /--* t33 byref +--* t117 long N003 ( 2, 2) [000118] -------N---- t118 = * ADD byref $282 /--* t118 byref N004 ( 4, 4) [000034] *--XG------- t34 = * IND int /--* t34 int N006 ( 4, 4) [000100] DA-XG------- * STORE_LCL_VAR int V11 tmp9 d:2 [000160] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 1, 1) [000087] ------------ t87 = LCL_VAR int V11 tmp9 u:2 N002 ( 1, 1) [000088] ------------ t88 = LCL_VAR ref V12 tmp10 u:2 N003 ( 1, 1) [000119] ------------ t119 = CNS_INT long 16 field offset Fseq[_size] $241 /--* t88 ref +--* t119 long N004 ( 2, 2) [000120] -------N---- t120 = * ADD byref /--* t120 byref N005 ( 4, 4) [000089] ---XG------- t89 = * IND int /--* t87 int +--* t89 int N006 ( 6, 6) [000090] N--XG--N-U-- t90 = * GE int /--* t90 int N007 ( 8, 8) [000091] ---XG------- * JTRUE void ------------ BB02 [025..026) (return), preds={BB01} succs={} N001 ( 1, 1) [000092] ------------ t92 = LCL_VAR ref V12 tmp10 u:2 (last use) N002 ( 1, 1) [000140] ------------ t140 = CNS_INT long 8 field offset Fseq[_items] $240 /--* t92 ref +--* t140 long N003 ( 2, 2) [000141] -------N---- t141 = * ADD byref /--* t141 byref N004 ( 4, 4) [000093] n---GO------ t93 = * IND ref /--* t93 ref N006 ( 4, 4) [000126] DA--GO------ * STORE_LCL_VAR ref V18 tmp16 d:2 N007 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V11 tmp9 u:2 N008 ( 1, 1) [000127] ------------ t127 = LCL_VAR ref V18 tmp16 u:2 [000162] ------------ t162 = CNS_INT long 8 /--* t127 ref +--* t162 long [000163] ------------ t163 = * ADD ref /--* t163 ref N009 ( 3, 3) [000130] ---X-------- t130 = * IND int /--* t94 int +--* t130 int N010 ( 8, 11) [000131] ---X-------- * ARR_BOUNDS_CHECK_Rng void N011 ( 1, 1) [000128] ------------ t128 = LCL_VAR ref V18 tmp16 u:2 (last use) N012 ( 1, 1) [000129] ------------ t129 = LCL_VAR int V11 tmp9 u:2 (last use) /--* t129 int N013 ( 2, 3) [000132] ------------ t132 = * CAST long <- int N014 ( 1, 1) [000133] -------N---- t133 = CNS_INT long 3 $242 /--* t132 long +--* t133 long N015 ( 3, 4) [000134] -------N---- t134 = * LSH long N016 ( 1, 1) [000135] ------------ t135 = CNS_INT long 16 Fseq[#FirstElem] $241 /--* t134 long +--* t135 long N017 ( 4, 5) [000136] -------N---- t136 = * ADD long /--* t128 ref +--* t136 long N018 ( 5, 6) [000137] -------N---- t137 = * ADD byref $480 /--* t137 byref N019 ( 6, 7) [000095] a---G------- t95 = * IND ref /--* t95 ref N023 ( 18, 22) [000145] DA-XGO----L- * STORE_LCL_VAR ref V19 tmp17 d:2 N026 ( 1, 1) [000037] ------------ t37 = LCL_VAR byref V00 this u:1 (last use) $80 N027 ( 1, 1) [000142] ------------ t142 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] $245 /--* t37 byref +--* t142 long N028 ( 3, 3) [000143] ------------ t143 = * ADD byref $289 /--* t143 byref N029 ( 9, 7) [000044] n---GO------ t44 = * OBJ struct N031 ( 1, 1) [000146] ------------ t146 = LCL_VAR ref V19 tmp17 u:2 (last use) N032 ( 3, 4) [000151] ------------ t151 = LCL_FLD long V01 arg1 u:1[+0] $144 N033 ( 3, 4) [000152] ------------ t152 = LCL_FLD long V01 arg1 u:1[+8] (last use) $145 /--* t151 long +--* t152 long N034 ( 6, 8) [000150] -c---------- t150 = * FIELD_LIST struct $384 N035 ( 2, 10) [000124] ------------ t124 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a N036 ( 2, 10) [000121] ------------ t121 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a /--* t44 struct arg3 out+00 +--* t146 ref this in rdi +--* t150 struct arg4 rdx,rcx +--* t124 long arg1 in r11 +--* t121 long arg2 in rsi N037 ( 61, 70) [000040] --CXGO------ t40 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA $385 /--* t40 struct N039 ( 65, 73) [000123] DA-XGO------ * STORE_LCL_VAR struct V17 tmp15 d:2 N001 ( 3, 2) [000153] -------N---- t153 = LCL_VAR struct V17 tmp15 u:2 (last use) $388 /--* t153 struct N002 ( 4, 3) [000045] ----G------- * RETURN struct $389 ------------ BB03 [025..026) (throw), preds={BB01} succs={} [000161] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 14, 5) [000096] --CXG------- CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException $VN.Void ------------ BB04 [???..???) (throw), preds={} succs={} N001 ( 14, 5) [000164] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Lowering nodeinfo lowering call (before): N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class $180 /--* t4 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000102] ----------L- * ARGPLACE long $180 late: ====== lowering arg : N002 ( 2, 10) [000004] ------------ * CNS_INT(h) long 0x7f6678c127f0 class $180 new node is : [000165] ------------ * PUTARG_REG long REG rdi lowering call (after): N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class $180 /--* t4 long [000165] ------------ t165 = * PUTARG_REG long REG rdi /--* t165 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 lowering store lcl var/field (before): N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class $180 /--* t4 long [000165] ------------ t165 = * PUTARG_REG long REG rdi /--* t165 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 /--* t5 ref N005 ( 16, 16) [000007] DA---------- * STORE_LCL_VAR ref V03 tmp1 d:2 lowering store lcl var/field (after): N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class $180 /--* t4 long [000165] ------------ t165 = * PUTARG_REG long REG rdi /--* t165 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 /--* t5 ref N005 ( 16, 16) [000007] DA---------- * STORE_LCL_VAR ref V03 tmp1 d:2 Addressing mode: Base N001 ( 1, 1) [000008] ------------ * LCL_VAR ref V03 tmp1 u:2 $200 + 8 Removing unused node: N002 ( 1, 1) [000009] -c---------- * CNS_INT long 8 $240 New addressing mode node: N003 ( 2, 2) [000010] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N001 ( 1, 1) [000008] ------------ t8 = LCL_VAR ref V03 tmp1 u:2 $200 /--* t8 ref N003 ( 2, 2) [000010] ------------ t10 = * LEA(b+8) byref N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD long V01 arg1 u:1[+0] Fseq[JobGroup] $2c0 /--* t10 byref +--* t3 long [000156] -A--GO------ * STOREIND long lowering call (before): N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class $182 /--* t18 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000103] ----------L- * ARGPLACE long $182 late: ====== lowering arg : N002 ( 2, 10) [000018] ------------ * CNS_INT(h) long 0x7f6678beb1c0 class $182 new node is : [000166] ------------ * PUTARG_REG long REG rdi lowering call (after): N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class $182 /--* t18 long [000166] ------------ t166 = * PUTARG_REG long REG rdi /--* t166 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 lowering store lcl var/field (before): N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class $182 /--* t18 long [000166] ------------ t166 = * PUTARG_REG long REG rdi /--* t166 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 /--* t19 ref N005 ( 16, 16) [000021] DA---------- * STORE_LCL_VAR ref V04 tmp2 d:2 lowering store lcl var/field (after): N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class $182 /--* t18 long [000166] ------------ t166 = * PUTARG_REG long REG rdi /--* t166 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 /--* t19 ref N005 ( 16, 16) [000021] DA---------- * STORE_LCL_VAR ref V04 tmp2 d:2 Addressing mode: Base N001 ( 1, 1) [000022] ------------ * LCL_VAR ref V04 tmp2 u:2 $201 + 8 Removing unused node: N002 ( 1, 1) [000023] -c---------- * CNS_INT long 8 $240 New addressing mode node: N003 ( 2, 2) [000024] ------------ * LEA(b+8) byref Lower of StoreInd didn't mark the node as self contained for reason: 4 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V04 tmp2 u:2 $201 /--* t22 ref N003 ( 2, 2) [000024] ------------ t24 = * LEA(b+8) byref N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD int V01 arg1 u:1[+8] Fseq[Version] $300 /--* t24 byref +--* t17 int [000157] -A--GO------ * STOREIND int lowering store lcl var/field (before): N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR ref V03 tmp1 u:2 (last use) $200 /--* t13 ref N004 ( 11, 8) [000063] DA---------- * STORE_LCL_VAR ref V13 tmp11 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR ref V03 tmp1 u:2 (last use) $200 /--* t13 ref N004 ( 11, 8) [000063] DA---------- * STORE_LCL_VAR ref V13 tmp11 d:2 lowering store lcl var/field (before): N001 ( 1, 1) [000027] ------------ t27 = LCL_VAR ref V04 tmp2 u:2 (last use) $201 /--* t27 ref N004 ( 11, 8) [000068] DA---------- * STORE_LCL_VAR ref V14 tmp12 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [000027] ------------ t27 = LCL_VAR ref V04 tmp2 u:2 (last use) $201 /--* t27 ref N004 ( 11, 8) [000068] DA---------- * STORE_LCL_VAR ref V14 tmp12 d:2 lowering store lcl var/field (before): N001 ( 1, 1) [000071] ------------ t71 = CNS_INT ref null $VN.Null /--* t71 ref N003 ( 5, 4) [000073] DA---------- * STORE_LCL_VAR ref V15 tmp13 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [000071] ------------ t71 = CNS_INT ref null $VN.Null /--* t71 ref N003 ( 5, 4) [000073] DA---------- * STORE_LCL_VAR ref V15 tmp13 d:2 lowering store lcl var/field (before): N001 ( 2, 10) [000104] ------------ t104 = CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 /--* t104 long N002 ( 4, 12) [000076] n---G------- t76 = * IND ref /--* t76 ref N004 ( 8, 15) [000078] DA--G------- * STORE_LCL_VAR ref V16 tmp14 d:2 lowering store lcl var/field (after): N001 ( 2, 10) [000104] ------------ t104 = CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 /--* t104 long N002 ( 4, 12) [000076] n---G------- t76 = * IND ref /--* t76 ref N004 ( 8, 15) [000078] DA--G------- * STORE_LCL_VAR ref V16 tmp14 d:2 lowering call (before): N003 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V13 tmp11 u:2 (last use) $200 N004 ( 3, 2) [000111] ------------ t111 = LCL_VAR ref V14 tmp12 u:2 (last use) $201 N005 ( 1, 1) [000154] ------------ t154 = CNS_INT ref null $VN.Null N006 ( 3, 2) [000113] ------------ t113 = LCL_VAR ref V16 tmp14 u:2 (last use) /--* t110 ref +--* t111 ref +--* t154 ref +--* t113 ref N007 ( 10, 7) [000109] -c---------- t109 = * FIELD_LIST struct $380 N008 ( 2, 10) [000105] ------------ t105 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] $185 /--* t105 long N009 ( 4, 12) [000106] n---G------- t106 = * IND ref N010 ( 1, 1) [000046] ------------ t46 = CNS_INT ref null $VN.Null /--* t109 struct arg2 out+00 +--* t106 ref arg1 in rsi +--* t46 ref arg0 in rdi N011 ( 32, 27) [000054] --CXG------- t54 = * CALL ref System.String.FormatHelper $1ce objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000108] ----------L- * ARGPLACE ref $VN.Null lowering arg : N002 ( 0, 0) [000107] ----------L- * ARGPLACE ref lowering arg : N007 ( 10, 7) [000109] -c---------- * FIELD_LIST struct $380 new node is : [000167] ------------ * PUTARG_STK [+0x00] void (4 slots) late: ====== lowering arg : N009 ( 4, 12) [000106] n---G------- * IND ref new node is : [000168] ----G------- * PUTARG_REG ref REG rsi lowering arg : N010 ( 1, 1) [000046] ------------ * CNS_INT ref null $VN.Null new node is : [000169] ------------ * PUTARG_REG ref REG rdi lowering call (after): N003 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V13 tmp11 u:2 (last use) $200 N004 ( 3, 2) [000111] ------------ t111 = LCL_VAR ref V14 tmp12 u:2 (last use) $201 N005 ( 1, 1) [000154] ------------ t154 = CNS_INT ref null $VN.Null N006 ( 3, 2) [000113] ------------ t113 = LCL_VAR ref V16 tmp14 u:2 (last use) /--* t110 ref +--* t111 ref +--* t154 ref +--* t113 ref N007 ( 10, 7) [000109] -c---------- t109 = * FIELD_LIST struct $380 /--* t109 struct [000167] ------------ * PUTARG_STK [+0x00] void (4 slots) N008 ( 2, 10) [000105] ------------ t105 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] $185 /--* t105 long N009 ( 4, 12) [000106] n---G------- t106 = * IND ref /--* t106 ref [000168] ----G------- t168 = * PUTARG_REG ref REG rsi N010 ( 1, 1) [000046] ------------ t46 = CNS_INT ref null $VN.Null /--* t46 ref [000169] ------------ t169 = * PUTARG_REG ref REG rdi /--* t168 ref arg1 in rsi +--* t169 ref arg0 in rdi N011 ( 32, 27) [000054] --CXG------- t54 = * CALL ref System.String.FormatHelper $1ce lowering store lcl var/field (before): N003 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V13 tmp11 u:2 (last use) $200 N004 ( 3, 2) [000111] ------------ t111 = LCL_VAR ref V14 tmp12 u:2 (last use) $201 N005 ( 1, 1) [000154] ------------ t154 = CNS_INT ref null $VN.Null N006 ( 3, 2) [000113] ------------ t113 = LCL_VAR ref V16 tmp14 u:2 (last use) /--* t110 ref +--* t111 ref +--* t154 ref +--* t113 ref N007 ( 10, 7) [000109] -c---------- t109 = * FIELD_LIST struct $380 /--* t109 struct [000167] ------------ * PUTARG_STK [+0x00] void (4 slots) N008 ( 2, 10) [000105] ------------ t105 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] $185 /--* t105 long N009 ( 4, 12) [000106] n---G------- t106 = * IND ref /--* t106 ref [000168] ----G------- t168 = * PUTARG_REG ref REG rsi N010 ( 1, 1) [000046] ------------ t46 = CNS_INT ref null $VN.Null /--* t46 ref [000169] ------------ t169 = * PUTARG_REG ref REG rdi /--* t168 ref arg1 in rsi +--* t169 ref arg0 in rdi N011 ( 32, 27) [000054] --CXG------- t54 = * CALL ref System.String.FormatHelper $1ce /--* t54 ref N013 ( 32, 27) [000085] DA-XG------- * STORE_LCL_VAR ref V10 tmp8 d:2 lowering store lcl var/field (after): N003 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V13 tmp11 u:2 (last use) $200 N004 ( 3, 2) [000111] ------------ t111 = LCL_VAR ref V14 tmp12 u:2 (last use) $201 N005 ( 1, 1) [000154] ------------ t154 = CNS_INT ref null $VN.Null N006 ( 3, 2) [000113] ------------ t113 = LCL_VAR ref V16 tmp14 u:2 (last use) /--* t110 ref +--* t111 ref +--* t154 ref +--* t113 ref N007 ( 10, 7) [000109] -c---------- t109 = * FIELD_LIST struct $380 /--* t109 struct [000167] ------------ * PUTARG_STK [+0x00] void (4 slots) N008 ( 2, 10) [000105] ------------ t105 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] $185 /--* t105 long N009 ( 4, 12) [000106] n---G------- t106 = * IND ref /--* t106 ref [000168] ----G------- t168 = * PUTARG_REG ref REG rsi N010 ( 1, 1) [000046] ------------ t46 = CNS_INT ref null $VN.Null /--* t46 ref [000169] ------------ t169 = * PUTARG_REG ref REG rdi /--* t168 ref arg1 in rsi +--* t169 ref arg0 in rdi N011 ( 32, 27) [000054] --CXG------- t54 = * CALL ref System.String.FormatHelper $1ce /--* t54 ref N013 ( 32, 27) [000085] DA-XG------- * STORE_LCL_VAR ref V10 tmp8 d:2 lowering call (before): N003 ( 1, 1) [000082] ------------ t82 = LCL_VAR ref V10 tmp8 u:2 (last use) $1ce N004 ( 1, 1) [000081] ------------ t81 = CNS_INT int 3 $44 /--* t82 ref arg1 in rsi +--* t81 int arg0 in rdi N005 ( 16, 9) [000083] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void objp: ====== args: ====== lowering arg : N001 ( 0, 0) [000115] ----------L- * ARGPLACE int $44 lowering arg : N002 ( 0, 0) [000114] ----------L- * ARGPLACE ref $1ce late: ====== lowering arg : N003 ( 1, 1) [000082] ------------ * LCL_VAR ref V10 tmp8 u:2 (last use) $1ce new node is : [000170] ------------ * PUTARG_REG ref REG rsi lowering arg : N004 ( 1, 1) [000081] ------------ * CNS_INT int 3 $44 new node is : [000171] ------------ * PUTARG_REG int REG rdi lowering call (after): N003 ( 1, 1) [000082] ------------ t82 = LCL_VAR ref V10 tmp8 u:2 (last use) $1ce /--* t82 ref [000170] ------------ t170 = * PUTARG_REG ref REG rsi N004 ( 1, 1) [000081] ------------ t81 = CNS_INT int 3 $44 /--* t81 int [000171] ------------ t171 = * PUTARG_REG int REG rdi /--* t170 ref arg1 in rsi +--* t171 int arg0 in rdi N005 ( 16, 9) [000083] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void lowering store lcl var/field (before): N001 ( 2, 10) [000116] ------------ t116 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] $186 /--* t116 long N002 ( 4, 12) [000032] n---G------- t32 = * IND ref /--* t32 ref N004 ( 4, 12) [000098] DA--G------- * STORE_LCL_VAR ref V12 tmp10 d:2 lowering store lcl var/field (after): N001 ( 2, 10) [000116] ------------ t116 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] $186 /--* t116 long N002 ( 4, 12) [000032] n---G------- t32 = * IND ref /--* t32 ref N004 ( 4, 12) [000098] DA--G------- * STORE_LCL_VAR ref V12 tmp10 d:2 Addressing mode: Base N001 ( 1, 1) [000033] ------------ * LCL_VAR byref V00 this u:1 $80 + 16 Removing unused node: N002 ( 1, 1) [000117] -c---------- * CNS_INT long 16 field offset Fseq[m_NetworkInterfaceIndex] $241 New addressing mode node: N003 ( 2, 2) [000118] ------------ * LEA(b+16) byref lowering store lcl var/field (before): N001 ( 1, 1) [000033] ------------ t33 = LCL_VAR byref V00 this u:1 $80 /--* t33 byref N003 ( 2, 2) [000118] -c---------- t118 = * LEA(b+16) byref /--* t118 byref N004 ( 4, 4) [000034] *--XG------- t34 = * IND int /--* t34 int N006 ( 4, 4) [000100] DA-XG------- * STORE_LCL_VAR int V11 tmp9 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [000033] ------------ t33 = LCL_VAR byref V00 this u:1 $80 /--* t33 byref N003 ( 2, 2) [000118] -c---------- t118 = * LEA(b+16) byref /--* t118 byref N004 ( 4, 4) [000034] *--XG------- t34 = * IND int /--* t34 int N006 ( 4, 4) [000100] DA-XG------- * STORE_LCL_VAR int V11 tmp9 d:2 Addressing mode: Base N002 ( 1, 1) [000088] ------------ * LCL_VAR ref V12 tmp10 u:2 + 16 Removing unused node: N003 ( 1, 1) [000119] -c---------- * CNS_INT long 16 field offset Fseq[_size] $241 New addressing mode node: N004 ( 2, 2) [000120] ------------ * LEA(b+16) byref Addressing mode: Base N001 ( 1, 1) [000092] ------------ * LCL_VAR ref V12 tmp10 u:2 (last use) + 8 Removing unused node: N002 ( 1, 1) [000140] -c---------- * CNS_INT long 8 field offset Fseq[_items] $240 New addressing mode node: N003 ( 2, 2) [000141] ------------ * LEA(b+8) byref lowering store lcl var/field (before): N001 ( 1, 1) [000092] ------------ t92 = LCL_VAR ref V12 tmp10 u:2 (last use) /--* t92 ref N003 ( 2, 2) [000141] -c---------- t141 = * LEA(b+8) byref /--* t141 byref N004 ( 4, 4) [000093] n---GO------ t93 = * IND ref /--* t93 ref N006 ( 4, 4) [000126] DA--GO------ * STORE_LCL_VAR ref V18 tmp16 d:2 lowering store lcl var/field (after): N001 ( 1, 1) [000092] ------------ t92 = LCL_VAR ref V12 tmp10 u:2 (last use) /--* t92 ref N003 ( 2, 2) [000141] -c---------- t141 = * LEA(b+8) byref /--* t141 byref N004 ( 4, 4) [000093] n---GO------ t93 = * IND ref /--* t93 ref N006 ( 4, 4) [000126] DA--GO------ * STORE_LCL_VAR ref V18 tmp16 d:2 Addressing mode: Base N008 ( 1, 1) [000127] ------------ * LCL_VAR ref V18 tmp16 u:2 + 8 Removing unused node: [000162] -c---------- * CNS_INT long 8 New addressing mode node: [000163] ------------ * LEA(b+8) ref Addressing mode: Base N011 ( 1, 1) [000128] ------------ * LCL_VAR ref V18 tmp16 u:2 (last use) + Index * 8 + 16 N013 ( 2, 3) [000132] ------------ * CAST long <- int Removing unused node: N017 ( 4, 5) [000136] -------N---- * ADD long Removing unused node: N016 ( 1, 1) [000135] -c---------- * CNS_INT long 16 Fseq[#FirstElem] $241 Removing unused node: N015 ( 3, 4) [000134] -------N---- * LSH long Removing unused node: N014 ( 1, 1) [000133] -c-----N---- * CNS_INT long 3 $242 New addressing mode node: N018 ( 5, 6) [000137] ------------ * LEA(b+(i*8)+16) byref lowering store lcl var/field (before): N011 ( 1, 1) [000128] ------------ t128 = LCL_VAR ref V18 tmp16 u:2 (last use) N012 ( 1, 1) [000129] ------------ t129 = LCL_VAR int V11 tmp9 u:2 (last use) /--* t129 int N013 ( 2, 3) [000132] ------------ t132 = * CAST long <- int /--* t128 ref +--* t132 long N018 ( 5, 6) [000137] -c---------- t137 = * LEA(b+(i*8)+16) byref /--* t137 byref N019 ( 6, 7) [000095] a---G------- t95 = * IND ref /--* t95 ref N023 ( 18, 22) [000145] DA-XGO----L- * STORE_LCL_VAR ref V19 tmp17 d:2 lowering store lcl var/field (after): N011 ( 1, 1) [000128] ------------ t128 = LCL_VAR ref V18 tmp16 u:2 (last use) N012 ( 1, 1) [000129] ------------ t129 = LCL_VAR int V11 tmp9 u:2 (last use) /--* t129 int N013 ( 2, 3) [000132] ------------ t132 = * CAST long <- int /--* t128 ref +--* t132 long N018 ( 5, 6) [000137] -c---------- t137 = * LEA(b+(i*8)+16) byref /--* t137 byref N019 ( 6, 7) [000095] a---G------- t95 = * IND ref /--* t95 ref N023 ( 18, 22) [000145] DA-XGO----L- * STORE_LCL_VAR ref V19 tmp17 d:2 lowering call (before): N011 ( 1, 1) [000128] ------------ t128 = LCL_VAR ref V18 tmp16 u:2 (last use) N012 ( 1, 1) [000129] ------------ t129 = LCL_VAR int V11 tmp9 u:2 (last use) /--* t129 int N013 ( 2, 3) [000132] ------------ t132 = * CAST long <- int /--* t128 ref +--* t132 long N018 ( 5, 6) [000137] -c---------- t137 = * LEA(b+(i*8)+16) byref /--* t137 byref N019 ( 6, 7) [000095] a---G------- t95 = * IND ref /--* t95 ref N023 ( 18, 22) [000145] DA-XGO----L- * STORE_LCL_VAR ref V19 tmp17 d:2 N026 ( 1, 1) [000037] ------------ t37 = LCL_VAR byref V00 this u:1 (last use) $80 N027 ( 1, 1) [000142] -c---------- t142 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] $245 /--* t37 byref +--* t142 long N028 ( 3, 3) [000143] ------------ t143 = * ADD byref $289 /--* t143 byref N029 ( 9, 7) [000044] n---GO------ t44 = * OBJ struct N031 ( 1, 1) [000146] ------------ t146 = LCL_VAR ref V19 tmp17 u:2 (last use) N032 ( 3, 4) [000151] ------------ t151 = LCL_FLD long V01 arg1 u:1[+0] $144 N033 ( 3, 4) [000152] ------------ t152 = LCL_FLD long V01 arg1 u:1[+8] (last use) $145 /--* t151 long +--* t152 long N034 ( 6, 8) [000150] -c---------- t150 = * FIELD_LIST struct $384 N035 ( 2, 10) [000124] ------------ t124 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a N036 ( 2, 10) [000121] ------------ t121 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a /--* t44 struct arg3 out+00 +--* t146 ref this in rdi +--* t150 struct arg4 rdx,rcx +--* t124 long arg1 in r11 +--* t121 long arg2 in rsi N037 ( 61, 70) [000040] --CXGO------ t40 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA $385 objp: ====== lowering arg : N023 ( 18, 22) [000145] DA-XGO----L- * STORE_LCL_VAR ref V19 tmp17 d:2 args: ====== lowering arg : N024 ( 0, 0) [000148] ----------L- * ARGPLACE long lowering arg : N025 ( 0, 0) [000149] ----------L- * ARGPLACE long $18a lowering arg : N029 ( 9, 7) [000044] n---GO------ * OBJ struct new node is : [000172] ----GO------ * PUTARG_STK [+0x00] void (7 slots) lowering arg : N030 ( 0, 0) [000147] ----------L- * ARGPLACE struct => [clsHnd=795C7A00] late: ====== lowering arg : N031 ( 1, 1) [000146] ------------ * LCL_VAR ref V19 tmp17 u:2 (last use) new node is : [000173] ------------ * PUTARG_REG ref REG rdi lowering arg : N034 ( 6, 8) [000150] -c---------- * FIELD_LIST struct $384 lowering arg : N035 ( 2, 10) [000124] ------------ * CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a new node is : [000176] ------------ * PUTARG_REG long REG r11 lowering arg : N036 ( 2, 10) [000121] ------------ * CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a new node is : [000177] ------------ * PUTARG_REG long REG rsi results of lowering call: N001 ( 2, 10) [000178] ------------ t178 = CNS_INT(h) long 0x7f6678060518 ftn /--* t178 long N002 ( 4, 12) [000179] ------------ t179 = * IND long lowering call (after): N011 ( 1, 1) [000128] ------------ t128 = LCL_VAR ref V18 tmp16 u:2 (last use) N012 ( 1, 1) [000129] ------------ t129 = LCL_VAR int V11 tmp9 u:2 (last use) /--* t129 int N013 ( 2, 3) [000132] ------------ t132 = * CAST long <- int /--* t128 ref +--* t132 long N018 ( 5, 6) [000137] -c---------- t137 = * LEA(b+(i*8)+16) byref /--* t137 byref N019 ( 6, 7) [000095] a---G------- t95 = * IND ref /--* t95 ref N023 ( 18, 22) [000145] DA-XGO----L- * STORE_LCL_VAR ref V19 tmp17 d:2 N026 ( 1, 1) [000037] ------------ t37 = LCL_VAR byref V00 this u:1 (last use) $80 N027 ( 1, 1) [000142] -c---------- t142 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] $245 /--* t37 byref +--* t142 long N028 ( 3, 3) [000143] ------------ t143 = * ADD byref $289 /--* t143 byref N029 ( 9, 7) [000044] nc--GO------ t44 = * OBJ struct /--* t44 struct [000172] ----GO------ * PUTARG_STK [+0x00] void (7 slots) (RepInstr) N031 ( 1, 1) [000146] ------------ t146 = LCL_VAR ref V19 tmp17 u:2 (last use) /--* t146 ref [000173] ------------ t173 = * PUTARG_REG ref REG rdi N032 ( 3, 4) [000151] ------------ t151 = LCL_FLD long V01 arg1 u:1[+0] $144 /--* t151 long [000174] ------------ t174 = * PUTARG_REG long REG rdx N033 ( 3, 4) [000152] ------------ t152 = LCL_FLD long V01 arg1 u:1[+8] (last use) $145 /--* t152 long [000175] ------------ t175 = * PUTARG_REG long REG rcx /--* t174 long +--* t175 long N034 ( 6, 8) [000150] -c---------- t150 = * FIELD_LIST struct $384 N035 ( 2, 10) [000124] ------------ t124 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a /--* t124 long [000176] ------------ t176 = * PUTARG_REG long REG r11 N036 ( 2, 10) [000121] ------------ t121 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a /--* t121 long [000177] ------------ t177 = * PUTARG_REG long REG rsi N001 ( 2, 10) [000178] ------------ t178 = CNS_INT(h) long 0x7f6678060518 ftn /--* t178 long N002 ( 4, 12) [000179] -c---------- t179 = * IND long REG NA /--* t173 ref this in rdi +--* t150 struct arg4 rdx,rcx +--* t176 long arg1 in r11 +--* t177 long arg2 in rsi +--* t179 long control expr N037 ( 61, 70) [000040] --CXGO------ t40 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA $385 lowering store lcl var/field (before): N011 ( 1, 1) [000128] ------------ t128 = LCL_VAR ref V18 tmp16 u:2 (last use) N012 ( 1, 1) [000129] ------------ t129 = LCL_VAR int V11 tmp9 u:2 (last use) /--* t129 int N013 ( 2, 3) [000132] ------------ t132 = * CAST long <- int /--* t128 ref +--* t132 long N018 ( 5, 6) [000137] -c---------- t137 = * LEA(b+(i*8)+16) byref /--* t137 byref N019 ( 6, 7) [000095] a---G------- t95 = * IND ref /--* t95 ref N023 ( 18, 22) [000145] DA-XGO----L- * STORE_LCL_VAR ref V19 tmp17 d:2 N026 ( 1, 1) [000037] ------------ t37 = LCL_VAR byref V00 this u:1 (last use) $80 N027 ( 1, 1) [000142] -c---------- t142 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] $245 /--* t37 byref +--* t142 long N028 ( 3, 3) [000143] ------------ t143 = * ADD byref $289 /--* t143 byref N029 ( 9, 7) [000044] nc--GO------ t44 = * OBJ struct /--* t44 struct [000172] ----GO------ * PUTARG_STK [+0x00] void (7 slots) (RepInstr) N031 ( 1, 1) [000146] ------------ t146 = LCL_VAR ref V19 tmp17 u:2 (last use) /--* t146 ref [000173] ------------ t173 = * PUTARG_REG ref REG rdi N032 ( 3, 4) [000151] ------------ t151 = LCL_FLD long V01 arg1 u:1[+0] $144 /--* t151 long [000174] ------------ t174 = * PUTARG_REG long REG rdx N033 ( 3, 4) [000152] ------------ t152 = LCL_FLD long V01 arg1 u:1[+8] (last use) $145 /--* t152 long [000175] ------------ t175 = * PUTARG_REG long REG rcx /--* t174 long +--* t175 long N034 ( 6, 8) [000150] -c---------- t150 = * FIELD_LIST struct $384 N035 ( 2, 10) [000124] ------------ t124 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a /--* t124 long [000176] ------------ t176 = * PUTARG_REG long REG r11 N036 ( 2, 10) [000121] ------------ t121 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a /--* t121 long [000177] ------------ t177 = * PUTARG_REG long REG rsi N001 ( 2, 10) [000178] ------------ t178 = CNS_INT(h) long 0x7f6678060518 ftn /--* t178 long N002 ( 4, 12) [000179] -c---------- t179 = * IND long REG NA /--* t173 ref this in rdi +--* t150 struct arg4 rdx,rcx +--* t176 long arg1 in r11 +--* t177 long arg2 in rsi +--* t179 long control expr N037 ( 61, 70) [000040] --CXGO------ t40 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA $385 /--* t40 struct N039 ( 65, 73) [000123] DA-XGO------ * STORE_LCL_VAR struct V17 tmp15 d:2 lowering store lcl var/field (after): N011 ( 1, 1) [000128] ------------ t128 = LCL_VAR ref V18 tmp16 u:2 (last use) N012 ( 1, 1) [000129] ------------ t129 = LCL_VAR int V11 tmp9 u:2 (last use) /--* t129 int N013 ( 2, 3) [000132] ------------ t132 = * CAST long <- int /--* t128 ref +--* t132 long N018 ( 5, 6) [000137] -c---------- t137 = * LEA(b+(i*8)+16) byref /--* t137 byref N019 ( 6, 7) [000095] a---G------- t95 = * IND ref /--* t95 ref N023 ( 18, 22) [000145] DA-XGO----L- * STORE_LCL_VAR ref V19 tmp17 d:2 N026 ( 1, 1) [000037] ------------ t37 = LCL_VAR byref V00 this u:1 (last use) $80 N027 ( 1, 1) [000142] -c---------- t142 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] $245 /--* t37 byref +--* t142 long N028 ( 3, 3) [000143] ------------ t143 = * ADD byref $289 /--* t143 byref N029 ( 9, 7) [000044] nc--GO------ t44 = * OBJ struct /--* t44 struct [000172] ----GO------ * PUTARG_STK [+0x00] void (7 slots) (RepInstr) N031 ( 1, 1) [000146] ------------ t146 = LCL_VAR ref V19 tmp17 u:2 (last use) /--* t146 ref [000173] ------------ t173 = * PUTARG_REG ref REG rdi N032 ( 3, 4) [000151] ------------ t151 = LCL_FLD long V01 arg1 u:1[+0] $144 /--* t151 long [000174] ------------ t174 = * PUTARG_REG long REG rdx N033 ( 3, 4) [000152] ------------ t152 = LCL_FLD long V01 arg1 u:1[+8] (last use) $145 /--* t152 long [000175] ------------ t175 = * PUTARG_REG long REG rcx /--* t174 long +--* t175 long N034 ( 6, 8) [000150] -c---------- t150 = * FIELD_LIST struct $384 N035 ( 2, 10) [000124] ------------ t124 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a /--* t124 long [000176] ------------ t176 = * PUTARG_REG long REG r11 N036 ( 2, 10) [000121] ------------ t121 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a /--* t121 long [000177] ------------ t177 = * PUTARG_REG long REG rsi N001 ( 2, 10) [000178] ------------ t178 = CNS_INT(h) long 0x7f6678060518 ftn /--* t178 long N002 ( 4, 12) [000179] -c---------- t179 = * IND long REG NA /--* t173 ref this in rdi +--* t150 struct arg4 rdx,rcx +--* t176 long arg1 in r11 +--* t177 long arg2 in rsi +--* t179 long control expr N037 ( 61, 70) [000040] --CXGO------ t40 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA $385 /--* t40 struct N039 ( 65, 73) [000123] DA-XGO------ * STORE_LCL_VAR struct V17 tmp15 d:2 lowering GT_RETURN N002 ( 4, 3) [000045] ----G------- * RETURN struct $389 ============**** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 lowering call (before): N001 ( 14, 5) [000096] --CXG------- CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException $VN.Void objp: ====== args: ====== late: ====== lowering call (after): N001 ( 14, 5) [000096] --CXG------- CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException $VN.Void lowering call (before): N001 ( 14, 5) [000164] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL objp: ====== args: ====== late: ====== lowering call (after): N001 ( 14, 5) [000164] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL Lower has completed modifying nodes. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj LIR BB02 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj LIR BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe LIR BB04 [0008] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) -> BB03 (cond), preds={} succs={BB02,BB03} [000155] ------------ IL_OFFSET void IL offset: 0x0 N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class $180 /--* t4 long [000165] ------------ t165 = * PUTARG_REG long REG rdi /--* t165 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 /--* t5 ref N005 ( 16, 16) [000007] DA---------- * STORE_LCL_VAR ref V03 tmp1 d:2 N001 ( 1, 1) [000008] ------------ t8 = LCL_VAR ref V03 tmp1 u:2 $200 /--* t8 ref N003 ( 2, 2) [000010] -c---------- t10 = * LEA(b+8) byref N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD long V01 arg1 u:1[+0] Fseq[JobGroup] $2c0 /--* t10 byref +--* t3 long [000156] -A--GO------ * STOREIND long N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class $182 /--* t18 long [000166] ------------ t166 = * PUTARG_REG long REG rdi /--* t166 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 /--* t19 ref N005 ( 16, 16) [000021] DA---------- * STORE_LCL_VAR ref V04 tmp2 d:2 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V04 tmp2 u:2 $201 /--* t22 ref N003 ( 2, 2) [000024] -c---------- t24 = * LEA(b+8) byref N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD int V01 arg1 u:1[+8] Fseq[Version] $300 /--* t24 byref +--* t17 int [000157] -A--GO------ * STOREIND int N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR ref V03 tmp1 u:2 (last use) $200 /--* t13 ref N004 ( 11, 8) [000063] DA---------- * STORE_LCL_VAR ref V13 tmp11 d:2 N001 ( 1, 1) [000027] ------------ t27 = LCL_VAR ref V04 tmp2 u:2 (last use) $201 /--* t27 ref N004 ( 11, 8) [000068] DA---------- * STORE_LCL_VAR ref V14 tmp12 d:2 N001 ( 1, 1) [000071] ------------ t71 = CNS_INT ref null $VN.Null /--* t71 ref N003 ( 5, 4) [000073] DA---------- * STORE_LCL_VAR ref V15 tmp13 d:2 N001 ( 2, 10) [000104] ------------ t104 = CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 /--* t104 long N002 ( 4, 12) [000076] n---G------- t76 = * IND ref /--* t76 ref N004 ( 8, 15) [000078] DA--G------- * STORE_LCL_VAR ref V16 tmp14 d:2 N003 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V13 tmp11 u:2 (last use) $200 N004 ( 3, 2) [000111] ------------ t111 = LCL_VAR ref V14 tmp12 u:2 (last use) $201 N005 ( 1, 1) [000154] ------------ t154 = CNS_INT ref null $VN.Null N006 ( 3, 2) [000113] ------------ t113 = LCL_VAR ref V16 tmp14 u:2 (last use) /--* t110 ref +--* t111 ref +--* t154 ref +--* t113 ref N007 ( 10, 7) [000109] -c---------- t109 = * FIELD_LIST struct $380 /--* t109 struct [000167] ------------ * PUTARG_STK [+0x00] void (4 slots) N008 ( 2, 10) [000105] ------------ t105 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] $185 /--* t105 long N009 ( 4, 12) [000106] n---G------- t106 = * IND ref /--* t106 ref [000168] ----G------- t168 = * PUTARG_REG ref REG rsi N010 ( 1, 1) [000046] ------------ t46 = CNS_INT ref null $VN.Null /--* t46 ref [000169] ------------ t169 = * PUTARG_REG ref REG rdi /--* t168 ref arg1 in rsi +--* t169 ref arg0 in rdi N011 ( 32, 27) [000054] --CXG------- t54 = * CALL ref System.String.FormatHelper $1ce /--* t54 ref N013 ( 32, 27) [000085] DA-XG------- * STORE_LCL_VAR ref V10 tmp8 d:2 N003 ( 1, 1) [000082] ------------ t82 = LCL_VAR ref V10 tmp8 u:2 (last use) $1ce /--* t82 ref [000170] ------------ t170 = * PUTARG_REG ref REG rsi N004 ( 1, 1) [000081] ------------ t81 = CNS_INT int 3 $44 /--* t81 int [000171] ------------ t171 = * PUTARG_REG int REG rdi /--* t170 ref arg1 in rsi +--* t171 int arg0 in rdi N005 ( 16, 9) [000083] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void [000158] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 2, 10) [000116] ------------ t116 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] $186 /--* t116 long N002 ( 4, 12) [000032] n---G------- t32 = * IND ref /--* t32 ref N004 ( 4, 12) [000098] DA--G------- * STORE_LCL_VAR ref V12 tmp10 d:2 [000159] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 1, 1) [000033] ------------ t33 = LCL_VAR byref V00 this u:1 $80 /--* t33 byref N003 ( 2, 2) [000118] -c---------- t118 = * LEA(b+16) byref /--* t118 byref N004 ( 4, 4) [000034] *--XG------- t34 = * IND int /--* t34 int N006 ( 4, 4) [000100] DA-XG------- * STORE_LCL_VAR int V11 tmp9 d:2 [000160] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 1, 1) [000087] ------------ t87 = LCL_VAR int V11 tmp9 u:2 N002 ( 1, 1) [000088] ------------ t88 = LCL_VAR ref V12 tmp10 u:2 /--* t88 ref N004 ( 2, 2) [000120] -c---------- t120 = * LEA(b+16) byref /--* t120 byref N005 ( 4, 4) [000089] -c-XG------- t89 = * IND int /--* t87 int +--* t89 int N006 ( 6, 6) [000090] N--XG--N-U-- * GE void N007 ( 8, 8) [000091] ---XG------- * JTRUE void ------------ BB02 [025..026) (return), preds={BB01} succs={} N001 ( 1, 1) [000092] ------------ t92 = LCL_VAR ref V12 tmp10 u:2 (last use) /--* t92 ref N003 ( 2, 2) [000141] -c---------- t141 = * LEA(b+8) byref /--* t141 byref N004 ( 4, 4) [000093] n---GO------ t93 = * IND ref /--* t93 ref N006 ( 4, 4) [000126] DA--GO------ * STORE_LCL_VAR ref V18 tmp16 d:2 N007 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V11 tmp9 u:2 N008 ( 1, 1) [000127] ------------ t127 = LCL_VAR ref V18 tmp16 u:2 /--* t127 ref [000163] -c---------- t163 = * LEA(b+8) ref /--* t163 ref N009 ( 3, 3) [000130] -c-X-------- t130 = * IND int /--* t94 int +--* t130 int N010 ( 8, 11) [000131] ---X-------- * ARR_BOUNDS_CHECK_Rng void N011 ( 1, 1) [000128] ------------ t128 = LCL_VAR ref V18 tmp16 u:2 (last use) N012 ( 1, 1) [000129] ------------ t129 = LCL_VAR int V11 tmp9 u:2 (last use) /--* t129 int N013 ( 2, 3) [000132] ------------ t132 = * CAST long <- int /--* t128 ref +--* t132 long N018 ( 5, 6) [000137] -c---------- t137 = * LEA(b+(i*8)+16) byref /--* t137 byref N019 ( 6, 7) [000095] a---G------- t95 = * IND ref /--* t95 ref N023 ( 18, 22) [000145] DA-XGO----L- * STORE_LCL_VAR ref V19 tmp17 d:2 N026 ( 1, 1) [000037] ------------ t37 = LCL_VAR byref V00 this u:1 (last use) $80 N027 ( 1, 1) [000142] -c---------- t142 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] $245 /--* t37 byref +--* t142 long N028 ( 3, 3) [000143] ------------ t143 = * ADD byref $289 /--* t143 byref N029 ( 9, 7) [000044] nc--GO------ t44 = * OBJ struct /--* t44 struct [000172] ----GO------ * PUTARG_STK [+0x00] void (7 slots) (RepInstr) N031 ( 1, 1) [000146] ------------ t146 = LCL_VAR ref V19 tmp17 u:2 (last use) /--* t146 ref [000173] ------------ t173 = * PUTARG_REG ref REG rdi N032 ( 3, 4) [000151] ------------ t151 = LCL_FLD long V01 arg1 u:1[+0] $144 /--* t151 long [000174] ------------ t174 = * PUTARG_REG long REG rdx N033 ( 3, 4) [000152] ------------ t152 = LCL_FLD long V01 arg1 u:1[+8] (last use) $145 /--* t152 long [000175] ------------ t175 = * PUTARG_REG long REG rcx /--* t174 long +--* t175 long N034 ( 6, 8) [000150] -c---------- t150 = * FIELD_LIST struct $384 N035 ( 2, 10) [000124] ------------ t124 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a /--* t124 long [000176] ------------ t176 = * PUTARG_REG long REG r11 N036 ( 2, 10) [000121] ------------ t121 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a /--* t121 long [000177] ------------ t177 = * PUTARG_REG long REG rsi N001 ( 2, 10) [000178] ------------ t178 = CNS_INT(h) long 0x7f6678060518 ftn /--* t178 long N002 ( 4, 12) [000179] -c---------- t179 = * IND long REG NA /--* t173 ref this in rdi +--* t150 struct arg4 rdx,rcx +--* t176 long arg1 in r11 +--* t177 long arg2 in rsi +--* t179 long control expr N037 ( 61, 70) [000040] --CXGO------ t40 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA $385 /--* t40 struct N039 ( 65, 73) [000123] DA-XGO------ * STORE_LCL_VAR struct V17 tmp15 d:2 N001 ( 3, 2) [000153] -c-----N---- t153 = LCL_VAR struct V17 tmp15 u:2 (last use) $388 /--* t153 struct N002 ( 4, 3) [000045] ----G------- * RETURN struct $389 ------------ BB03 [025..026) (throw), preds={BB01} succs={} [000161] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 14, 5) [000096] --CXG------- CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException $VN.Void ------------ BB04 [???..???) (throw), preds={} succs={} N001 ( 14, 5) [000164] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL ------------------------------------------------------------------------------------------------------------------- *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V03: refCnt = 1, refCntWtd = 2 New refCnts for V03: refCnt = 2, refCntWtd = 4 New refCnts for V01: refCnt = 1, refCntWtd = 1 New refCnts for V04: refCnt = 1, refCntWtd = 2 New refCnts for V04: refCnt = 2, refCntWtd = 4 New refCnts for V01: refCnt = 2, refCntWtd = 2 New refCnts for V03: refCnt = 3, refCntWtd = 6 New refCnts for V13: refCnt = 1, refCntWtd = 1 New refCnts for V04: refCnt = 3, refCntWtd = 6 New refCnts for V14: refCnt = 1, refCntWtd = 1 New refCnts for V15: refCnt = 1, refCntWtd = 1 New refCnts for V16: refCnt = 1, refCntWtd = 1 New refCnts for V13: refCnt = 2, refCntWtd = 2 New refCnts for V14: refCnt = 2, refCntWtd = 2 New refCnts for V16: refCnt = 2, refCntWtd = 2 New refCnts for V10: refCnt = 1, refCntWtd = 2 New refCnts for V10: refCnt = 2, refCntWtd = 4 New refCnts for V12: refCnt = 1, refCntWtd = 2 New refCnts for V00: refCnt = 1, refCntWtd = 1 New refCnts for V11: refCnt = 1, refCntWtd = 2 New refCnts for V11: refCnt = 2, refCntWtd = 4 New refCnts for V12: refCnt = 2, refCntWtd = 4 New refCnts for V12: refCnt = 3, refCntWtd = 6 New refCnts for V18: refCnt = 1, refCntWtd = 2 New refCnts for V11: refCnt = 3, refCntWtd = 6 New refCnts for V18: refCnt = 2, refCntWtd = 4 New refCnts for V18: refCnt = 3, refCntWtd = 6 New refCnts for V11: refCnt = 4, refCntWtd = 8 New refCnts for V19: refCnt = 1, refCntWtd = 2 New refCnts for V00: refCnt = 2, refCntWtd = 2 New refCnts for V19: refCnt = 2, refCntWtd = 4 New refCnts for V01: refCnt = 3, refCntWtd = 3 New refCnts for V01: refCnt = 4, refCntWtd = 4 New refCnts for V17: refCnt = 1, refCntWtd = 1 New refCnts for V17: refCnt = 2, refCntWtd = 2 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 3, refCntWtd = 3 New refCnts for V00: refCnt = 4, refCntWtd = 4 New refCnts for V01: refCnt = 5, refCntWtd = 5 New refCnts for V01: refCnt = 6, refCntWtd = 6 *************** In fgLocalVarLiveness() ; Initial local variable assignments ; ; V00 this byref this ; V01 arg1 struct do-not-enreg[SFA] multireg-arg ; V02 OutArgs lclBlk <56> "OutgoingArgSpace" ; V03 tmp1 ref class-hnd exact "Single-def Box Helper" ; V04 tmp2 ref class-hnd exact "Single-def Box Helper" ; V05 tmp3 ref class-hnd exact "Inlining Arg" ; V06 tmp4 ref class-hnd exact "Inlining Arg" ; V07 tmp5 struct "NewObj constructor temp" ; V08 tmp6 ref class-hnd exact "Inlining Arg" ; V09 tmp7 ref class-hnd exact "Inlining Arg" ; V10 tmp8 ref class-hnd "Inlining Arg" ; V11 tmp9 int "Inlining Arg" ; V12 tmp10 ref class-hnd "Inlining Arg" ; V13 tmp11 ref V07._arg0(offs=0x00) P-INDEP "field V07._arg0 (fldOffset=0x0)" ; V14 tmp12 ref V07._arg1(offs=0x08) P-INDEP "field V07._arg1 (fldOffset=0x8)" ; V15 tmp13 ref V07._arg2(offs=0x10) P-INDEP "field V07._arg2 (fldOffset=0x10)" ; V16 tmp14 ref V07._args(offs=0x18) P-INDEP "field V07._args (fldOffset=0x18)" ; V17 tmp15 struct do-not-enreg[SR] multireg-ret "Return value temp for multi-reg return (rejected tail call)." ; V18 tmp16 ref "arr expr" ; V19 tmp17 ref "argument with side effect" In fgLocalVarLivenessInit Local V01 should not be enregistered because: it is a struct Local V17 should not be enregistered because: it is a struct Tracked variable (14 out of 20) table: V01 arg1 [struct]: refCnt = 6, refCntWtd = 6 V11 tmp9 [ int]: refCnt = 4, refCntWtd = 8 V00 this [ byref]: refCnt = 4, refCntWtd = 4 V03 tmp1 [ ref]: refCnt = 3, refCntWtd = 6 V04 tmp2 [ ref]: refCnt = 3, refCntWtd = 6 V12 tmp10 [ ref]: refCnt = 3, refCntWtd = 6 V18 tmp16 [ ref]: refCnt = 3, refCntWtd = 6 V10 tmp8 [ ref]: refCnt = 2, refCntWtd = 4 V19 tmp17 [ ref]: refCnt = 2, refCntWtd = 4 V13 tmp11 [ ref]: refCnt = 2, refCntWtd = 2 V14 tmp12 [ ref]: refCnt = 2, refCntWtd = 2 V16 tmp14 [ ref]: refCnt = 2, refCntWtd = 2 V17 tmp15 [struct]: refCnt = 2, refCntWtd = 2 V15 tmp13 [ ref]: refCnt = 1, refCntWtd = 1 *************** In fgPerBlockLocalVarLiveness() BB01 USE(2)={V01 V00 } + ByrefExposed + GcHeap DEF(9)={ V11 V03 V04 V12 V10 V13 V14 V16 V15} + ByrefExposed* + GcHeap* BB02 USE(4)={V01 V11 V00 V12 } + ByrefExposed + GcHeap DEF(3)={ V18 V19 V17} + ByrefExposed* + GcHeap* BB03 USE(0)={} + ByrefExposed + GcHeap DEF(0)={} + ByrefExposed* + GcHeap* BB04 USE(0)={} DEF(0)={} ** Memory liveness computed, GcHeap states and ByrefExposed states match *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (2)={V01 V00 } + ByrefExposed + GcHeap OUT(4)={V01 V11 V00 V12} + ByrefExposed + GcHeap BB02 IN (4)={V01 V11 V00 V12} + ByrefExposed + GcHeap OUT(0)={ } BB03 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} BB04 IN (0)={} OUT(0)={} Removing dead store: N003 ( 5, 4) [000073] DA---------- * STORE_LCL_VAR ref V15 tmp13 d:2 (last use) Removing dead node: N001 ( 1, 1) [000071] ------------ * CNS_INT ref null $VN.Null *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj LIR BB02 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj LIR BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe LIR BB04 [0008] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V03: refCnt = 1, refCntWtd = 2 New refCnts for V03: refCnt = 2, refCntWtd = 4 New refCnts for V01: refCnt = 1, refCntWtd = 1 New refCnts for V04: refCnt = 1, refCntWtd = 2 New refCnts for V04: refCnt = 2, refCntWtd = 4 New refCnts for V01: refCnt = 2, refCntWtd = 2 New refCnts for V03: refCnt = 3, refCntWtd = 6 New refCnts for V13: refCnt = 1, refCntWtd = 1 New refCnts for V04: refCnt = 3, refCntWtd = 6 New refCnts for V14: refCnt = 1, refCntWtd = 1 New refCnts for V16: refCnt = 1, refCntWtd = 1 New refCnts for V13: refCnt = 2, refCntWtd = 2 New refCnts for V14: refCnt = 2, refCntWtd = 2 New refCnts for V16: refCnt = 2, refCntWtd = 2 New refCnts for V10: refCnt = 1, refCntWtd = 2 New refCnts for V10: refCnt = 2, refCntWtd = 4 New refCnts for V12: refCnt = 1, refCntWtd = 2 New refCnts for V00: refCnt = 1, refCntWtd = 1 New refCnts for V11: refCnt = 1, refCntWtd = 2 New refCnts for V11: refCnt = 2, refCntWtd = 4 New refCnts for V12: refCnt = 2, refCntWtd = 4 New refCnts for V12: refCnt = 3, refCntWtd = 6 New refCnts for V18: refCnt = 1, refCntWtd = 2 New refCnts for V11: refCnt = 3, refCntWtd = 6 New refCnts for V18: refCnt = 2, refCntWtd = 4 New refCnts for V18: refCnt = 3, refCntWtd = 6 New refCnts for V11: refCnt = 4, refCntWtd = 8 New refCnts for V19: refCnt = 1, refCntWtd = 2 New refCnts for V00: refCnt = 2, refCntWtd = 2 New refCnts for V19: refCnt = 2, refCntWtd = 4 New refCnts for V01: refCnt = 3, refCntWtd = 3 New refCnts for V01: refCnt = 4, refCntWtd = 4 New refCnts for V17: refCnt = 1, refCntWtd = 1 New refCnts for V17: refCnt = 2, refCntWtd = 2 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 3, refCntWtd = 3 New refCnts for V00: refCnt = 4, refCntWtd = 4 New refCnts for V01: refCnt = 5, refCntWtd = 5 New refCnts for V01: refCnt = 6, refCntWtd = 6 *************** Finishing PHASE Lowering nodeinfo Trees after Lowering nodeinfo ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj LIR BB02 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj LIR BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe LIR BB04 [0008] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) -> BB03 (cond), preds={} succs={BB02,BB03} [000155] ------------ IL_OFFSET void IL offset: 0x0 N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class $180 /--* t4 long [000165] ------------ t165 = * PUTARG_REG long REG rdi /--* t165 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 /--* t5 ref N005 ( 16, 16) [000007] DA---------- * STORE_LCL_VAR ref V03 tmp1 d:2 N001 ( 1, 1) [000008] ------------ t8 = LCL_VAR ref V03 tmp1 u:2 $200 /--* t8 ref N003 ( 2, 2) [000010] -c---------- t10 = * LEA(b+8) byref N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD long V01 arg1 u:1[+0] Fseq[JobGroup] $2c0 /--* t10 byref +--* t3 long [000156] -A--GO------ * STOREIND long N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class $182 /--* t18 long [000166] ------------ t166 = * PUTARG_REG long REG rdi /--* t166 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 /--* t19 ref N005 ( 16, 16) [000021] DA---------- * STORE_LCL_VAR ref V04 tmp2 d:2 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V04 tmp2 u:2 $201 /--* t22 ref N003 ( 2, 2) [000024] -c---------- t24 = * LEA(b+8) byref N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD int V01 arg1 u:1[+8] Fseq[Version] $300 /--* t24 byref +--* t17 int [000157] -A--GO------ * STOREIND int N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR ref V03 tmp1 u:2 (last use) $200 /--* t13 ref N004 ( 11, 8) [000063] DA---------- * STORE_LCL_VAR ref V13 tmp11 d:2 N001 ( 1, 1) [000027] ------------ t27 = LCL_VAR ref V04 tmp2 u:2 (last use) $201 /--* t27 ref N004 ( 11, 8) [000068] DA---------- * STORE_LCL_VAR ref V14 tmp12 d:2 N001 ( 2, 10) [000104] ------------ t104 = CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 /--* t104 long N002 ( 4, 12) [000076] n---G------- t76 = * IND ref /--* t76 ref N004 ( 8, 15) [000078] DA--G------- * STORE_LCL_VAR ref V16 tmp14 d:2 N003 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V13 tmp11 u:2 (last use) $200 N004 ( 3, 2) [000111] ------------ t111 = LCL_VAR ref V14 tmp12 u:2 (last use) $201 N005 ( 1, 1) [000154] ------------ t154 = CNS_INT ref null $VN.Null N006 ( 3, 2) [000113] ------------ t113 = LCL_VAR ref V16 tmp14 u:2 (last use) /--* t110 ref +--* t111 ref +--* t154 ref +--* t113 ref N007 ( 10, 7) [000109] -c---------- t109 = * FIELD_LIST struct $380 /--* t109 struct [000167] ------------ * PUTARG_STK [+0x00] void (4 slots) N008 ( 2, 10) [000105] ------------ t105 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] $185 /--* t105 long N009 ( 4, 12) [000106] n---G------- t106 = * IND ref /--* t106 ref [000168] ----G------- t168 = * PUTARG_REG ref REG rsi N010 ( 1, 1) [000046] ------------ t46 = CNS_INT ref null $VN.Null /--* t46 ref [000169] ------------ t169 = * PUTARG_REG ref REG rdi /--* t168 ref arg1 in rsi +--* t169 ref arg0 in rdi N011 ( 32, 27) [000054] --CXG------- t54 = * CALL ref System.String.FormatHelper $1ce /--* t54 ref N013 ( 32, 27) [000085] DA-XG------- * STORE_LCL_VAR ref V10 tmp8 d:2 N003 ( 1, 1) [000082] ------------ t82 = LCL_VAR ref V10 tmp8 u:2 (last use) $1ce /--* t82 ref [000170] ------------ t170 = * PUTARG_REG ref REG rsi N004 ( 1, 1) [000081] ------------ t81 = CNS_INT int 3 $44 /--* t81 int [000171] ------------ t171 = * PUTARG_REG int REG rdi /--* t170 ref arg1 in rsi +--* t171 int arg0 in rdi N005 ( 16, 9) [000083] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void [000158] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 2, 10) [000116] ------------ t116 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] $186 /--* t116 long N002 ( 4, 12) [000032] n---G------- t32 = * IND ref /--* t32 ref N004 ( 4, 12) [000098] DA--G------- * STORE_LCL_VAR ref V12 tmp10 d:2 [000159] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 1, 1) [000033] ------------ t33 = LCL_VAR byref V00 this u:1 $80 /--* t33 byref N003 ( 2, 2) [000118] -c---------- t118 = * LEA(b+16) byref /--* t118 byref N004 ( 4, 4) [000034] *--XG------- t34 = * IND int /--* t34 int N006 ( 4, 4) [000100] DA-XG------- * STORE_LCL_VAR int V11 tmp9 d:2 [000160] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 1, 1) [000087] ------------ t87 = LCL_VAR int V11 tmp9 u:2 N002 ( 1, 1) [000088] ------------ t88 = LCL_VAR ref V12 tmp10 u:2 /--* t88 ref N004 ( 2, 2) [000120] -c---------- t120 = * LEA(b+16) byref /--* t120 byref N005 ( 4, 4) [000089] -c-XG------- t89 = * IND int /--* t87 int +--* t89 int N006 ( 6, 6) [000090] N--XG--N-U-- * GE void N007 ( 8, 8) [000091] ---XG------- * JTRUE void ------------ BB02 [025..026) (return), preds={BB01} succs={} N001 ( 1, 1) [000092] ------------ t92 = LCL_VAR ref V12 tmp10 u:2 (last use) /--* t92 ref N003 ( 2, 2) [000141] -c---------- t141 = * LEA(b+8) byref /--* t141 byref N004 ( 4, 4) [000093] n---GO------ t93 = * IND ref /--* t93 ref N006 ( 4, 4) [000126] DA--GO------ * STORE_LCL_VAR ref V18 tmp16 d:2 N007 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V11 tmp9 u:2 N008 ( 1, 1) [000127] ------------ t127 = LCL_VAR ref V18 tmp16 u:2 /--* t127 ref [000163] -c---------- t163 = * LEA(b+8) ref /--* t163 ref N009 ( 3, 3) [000130] -c-X-------- t130 = * IND int /--* t94 int +--* t130 int N010 ( 8, 11) [000131] ---X-------- * ARR_BOUNDS_CHECK_Rng void N011 ( 1, 1) [000128] ------------ t128 = LCL_VAR ref V18 tmp16 u:2 (last use) N012 ( 1, 1) [000129] ------------ t129 = LCL_VAR int V11 tmp9 u:2 (last use) /--* t129 int N013 ( 2, 3) [000132] ------------ t132 = * CAST long <- int /--* t128 ref +--* t132 long N018 ( 5, 6) [000137] -c---------- t137 = * LEA(b+(i*8)+16) byref /--* t137 byref N019 ( 6, 7) [000095] a---G------- t95 = * IND ref /--* t95 ref N023 ( 18, 22) [000145] DA-XGO----L- * STORE_LCL_VAR ref V19 tmp17 d:2 N026 ( 1, 1) [000037] ------------ t37 = LCL_VAR byref V00 this u:1 (last use) $80 N027 ( 1, 1) [000142] -c---------- t142 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] $245 /--* t37 byref +--* t142 long N028 ( 3, 3) [000143] ------------ t143 = * ADD byref $289 /--* t143 byref N029 ( 9, 7) [000044] nc--GO------ t44 = * OBJ struct /--* t44 struct [000172] ----GO------ * PUTARG_STK [+0x00] void (7 slots) (RepInstr) N031 ( 1, 1) [000146] ------------ t146 = LCL_VAR ref V19 tmp17 u:2 (last use) /--* t146 ref [000173] ------------ t173 = * PUTARG_REG ref REG rdi N032 ( 3, 4) [000151] ------------ t151 = LCL_FLD long V01 arg1 u:1[+0] $144 /--* t151 long [000174] ------------ t174 = * PUTARG_REG long REG rdx N033 ( 3, 4) [000152] ------------ t152 = LCL_FLD long V01 arg1 u:1[+8] (last use) $145 /--* t152 long [000175] ------------ t175 = * PUTARG_REG long REG rcx /--* t174 long +--* t175 long N034 ( 6, 8) [000150] -c---------- t150 = * FIELD_LIST struct $384 N035 ( 2, 10) [000124] ------------ t124 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a /--* t124 long [000176] ------------ t176 = * PUTARG_REG long REG r11 N036 ( 2, 10) [000121] ------------ t121 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a /--* t121 long [000177] ------------ t177 = * PUTARG_REG long REG rsi N001 ( 2, 10) [000178] ------------ t178 = CNS_INT(h) long 0x7f6678060518 ftn /--* t178 long N002 ( 4, 12) [000179] -c---------- t179 = * IND long REG NA /--* t173 ref this in rdi +--* t150 struct arg4 rdx,rcx +--* t176 long arg1 in r11 +--* t177 long arg2 in rsi +--* t179 long control expr N037 ( 61, 70) [000040] --CXGO------ t40 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA $385 /--* t40 struct N039 ( 65, 73) [000123] DA-XGO------ * STORE_LCL_VAR struct V17 tmp15 d:2 N001 ( 3, 2) [000153] -c-----N---- t153 = LCL_VAR struct V17 tmp15 u:2 (last use) $388 /--* t153 struct N002 ( 4, 3) [000045] ----G------- * RETURN struct $389 ------------ BB03 [025..026) (throw), preds={BB01} succs={} [000161] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 14, 5) [000096] --CXG------- CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException $VN.Void ------------ BB04 [???..???) (throw), preds={} succs={} N001 ( 14, 5) [000164] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist Trees before Calculate stack level slots ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj LIR BB02 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj LIR BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe LIR BB04 [0008] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) -> BB03 (cond), preds={} succs={BB02,BB03} [000155] ------------ IL_OFFSET void IL offset: 0x0 N002 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class $180 /--* t4 long [000165] ------------ t165 = * PUTARG_REG long REG rdi /--* t165 long arg0 in rdi N003 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $200 /--* t5 ref N005 ( 16, 16) [000007] DA---------- * STORE_LCL_VAR ref V03 tmp1 d:2 N001 ( 1, 1) [000008] ------------ t8 = LCL_VAR ref V03 tmp1 u:2 $200 /--* t8 ref N003 ( 2, 2) [000010] -c---------- t10 = * LEA(b+8) byref N005 ( 3, 4) [000003] ------------ t3 = LCL_FLD long V01 arg1 u:1[+0] Fseq[JobGroup] $2c0 /--* t10 byref +--* t3 long [000156] -A--GO------ * STOREIND long N002 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class $182 /--* t18 long [000166] ------------ t166 = * PUTARG_REG long REG rdi /--* t166 long arg0 in rdi N003 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST $201 /--* t19 ref N005 ( 16, 16) [000021] DA---------- * STORE_LCL_VAR ref V04 tmp2 d:2 N001 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V04 tmp2 u:2 $201 /--* t22 ref N003 ( 2, 2) [000024] -c---------- t24 = * LEA(b+8) byref N005 ( 3, 4) [000017] ------------ t17 = LCL_FLD int V01 arg1 u:1[+8] Fseq[Version] $300 /--* t24 byref +--* t17 int [000157] -A--GO------ * STOREIND int N001 ( 1, 1) [000013] ------------ t13 = LCL_VAR ref V03 tmp1 u:2 (last use) $200 /--* t13 ref N004 ( 11, 8) [000063] DA---------- * STORE_LCL_VAR ref V13 tmp11 d:2 N001 ( 1, 1) [000027] ------------ t27 = LCL_VAR ref V04 tmp2 u:2 (last use) $201 /--* t27 ref N004 ( 11, 8) [000068] DA---------- * STORE_LCL_VAR ref V14 tmp12 d:2 N001 ( 2, 10) [000104] ------------ t104 = CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] $184 /--* t104 long N002 ( 4, 12) [000076] n---G------- t76 = * IND ref /--* t76 ref N004 ( 8, 15) [000078] DA--G------- * STORE_LCL_VAR ref V16 tmp14 d:2 N003 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V13 tmp11 u:2 (last use) $200 N004 ( 3, 2) [000111] ------------ t111 = LCL_VAR ref V14 tmp12 u:2 (last use) $201 N005 ( 1, 1) [000154] ------------ t154 = CNS_INT ref null $VN.Null N006 ( 3, 2) [000113] ------------ t113 = LCL_VAR ref V16 tmp14 u:2 (last use) /--* t110 ref +--* t111 ref +--* t154 ref +--* t113 ref N007 ( 10, 7) [000109] -c---------- t109 = * FIELD_LIST struct $380 /--* t109 struct [000167] ------------ * PUTARG_STK [+0x00] void (4 slots) N008 ( 2, 10) [000105] ------------ t105 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] $185 /--* t105 long N009 ( 4, 12) [000106] n---G------- t106 = * IND ref /--* t106 ref [000168] ----G------- t168 = * PUTARG_REG ref REG rsi N010 ( 1, 1) [000046] ------------ t46 = CNS_INT ref null $VN.Null /--* t46 ref [000169] ------------ t169 = * PUTARG_REG ref REG rdi /--* t168 ref arg1 in rsi +--* t169 ref arg0 in rdi N011 ( 32, 27) [000054] --CXG------- t54 = * CALL ref System.String.FormatHelper $1ce /--* t54 ref N013 ( 32, 27) [000085] DA-XG------- * STORE_LCL_VAR ref V10 tmp8 d:2 N003 ( 1, 1) [000082] ------------ t82 = LCL_VAR ref V10 tmp8 u:2 (last use) $1ce /--* t82 ref [000170] ------------ t170 = * PUTARG_REG ref REG rsi N004 ( 1, 1) [000081] ------------ t81 = CNS_INT int 3 $44 /--* t81 int [000171] ------------ t171 = * PUTARG_REG int REG rdi /--* t170 ref arg1 in rsi +--* t171 int arg0 in rdi N005 ( 16, 9) [000083] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal $VN.Void [000158] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 2, 10) [000116] ------------ t116 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] $186 /--* t116 long N002 ( 4, 12) [000032] n---G------- t32 = * IND ref /--* t32 ref N004 ( 4, 12) [000098] DA--G------- * STORE_LCL_VAR ref V12 tmp10 d:2 [000159] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 1, 1) [000033] ------------ t33 = LCL_VAR byref V00 this u:1 $80 /--* t33 byref N003 ( 2, 2) [000118] -c---------- t118 = * LEA(b+16) byref /--* t118 byref N004 ( 4, 4) [000034] *--XG------- t34 = * IND int /--* t34 int N006 ( 4, 4) [000100] DA-XG------- * STORE_LCL_VAR int V11 tmp9 d:2 [000160] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 1, 1) [000087] ------------ t87 = LCL_VAR int V11 tmp9 u:2 N002 ( 1, 1) [000088] ------------ t88 = LCL_VAR ref V12 tmp10 u:2 /--* t88 ref N004 ( 2, 2) [000120] -c---------- t120 = * LEA(b+16) byref /--* t120 byref N005 ( 4, 4) [000089] -c-XG------- t89 = * IND int /--* t87 int +--* t89 int N006 ( 6, 6) [000090] N--XG--N-U-- * GE void N007 ( 8, 8) [000091] ---XG------- * JTRUE void ------------ BB02 [025..026) (return), preds={BB01} succs={} N001 ( 1, 1) [000092] ------------ t92 = LCL_VAR ref V12 tmp10 u:2 (last use) /--* t92 ref N003 ( 2, 2) [000141] -c---------- t141 = * LEA(b+8) byref /--* t141 byref N004 ( 4, 4) [000093] n---GO------ t93 = * IND ref /--* t93 ref N006 ( 4, 4) [000126] DA--GO------ * STORE_LCL_VAR ref V18 tmp16 d:2 N007 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V11 tmp9 u:2 N008 ( 1, 1) [000127] ------------ t127 = LCL_VAR ref V18 tmp16 u:2 /--* t127 ref [000163] -c---------- t163 = * LEA(b+8) ref /--* t163 ref N009 ( 3, 3) [000130] -c-X-------- t130 = * IND int /--* t94 int +--* t130 int N010 ( 8, 11) [000131] ---X-------- * ARR_BOUNDS_CHECK_Rng void N011 ( 1, 1) [000128] ------------ t128 = LCL_VAR ref V18 tmp16 u:2 (last use) N012 ( 1, 1) [000129] ------------ t129 = LCL_VAR int V11 tmp9 u:2 (last use) /--* t129 int N013 ( 2, 3) [000132] ------------ t132 = * CAST long <- int /--* t128 ref +--* t132 long N018 ( 5, 6) [000137] -c---------- t137 = * LEA(b+(i*8)+16) byref /--* t137 byref N019 ( 6, 7) [000095] a---G------- t95 = * IND ref /--* t95 ref N023 ( 18, 22) [000145] DA-XGO----L- * STORE_LCL_VAR ref V19 tmp17 d:2 N026 ( 1, 1) [000037] ------------ t37 = LCL_VAR byref V00 this u:1 (last use) $80 N027 ( 1, 1) [000142] -c---------- t142 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] $245 /--* t37 byref +--* t142 long N028 ( 3, 3) [000143] ------------ t143 = * ADD byref $289 /--* t143 byref N029 ( 9, 7) [000044] nc--GO------ t44 = * OBJ struct /--* t44 struct [000172] ----GO------ * PUTARG_STK [+0x00] void (7 slots) (RepInstr) N031 ( 1, 1) [000146] ------------ t146 = LCL_VAR ref V19 tmp17 u:2 (last use) /--* t146 ref [000173] ------------ t173 = * PUTARG_REG ref REG rdi N032 ( 3, 4) [000151] ------------ t151 = LCL_FLD long V01 arg1 u:1[+0] $144 /--* t151 long [000174] ------------ t174 = * PUTARG_REG long REG rdx N033 ( 3, 4) [000152] ------------ t152 = LCL_FLD long V01 arg1 u:1[+8] (last use) $145 /--* t152 long [000175] ------------ t175 = * PUTARG_REG long REG rcx /--* t174 long +--* t175 long N034 ( 6, 8) [000150] -c---------- t150 = * FIELD_LIST struct $384 N035 ( 2, 10) [000124] ------------ t124 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a /--* t124 long [000176] ------------ t176 = * PUTARG_REG long REG r11 N036 ( 2, 10) [000121] ------------ t121 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a /--* t121 long [000177] ------------ t177 = * PUTARG_REG long REG rsi N001 ( 2, 10) [000178] ------------ t178 = CNS_INT(h) long 0x7f6678060518 ftn /--* t178 long N002 ( 4, 12) [000179] -c---------- t179 = * IND long REG NA /--* t173 ref this in rdi +--* t150 struct arg4 rdx,rcx +--* t176 long arg1 in r11 +--* t177 long arg2 in rsi +--* t179 long control expr N037 ( 61, 70) [000040] --CXGO------ t40 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend,NA $385 /--* t40 struct N039 ( 65, 73) [000123] DA-XGO------ * STORE_LCL_VAR struct V17 tmp15 d:2 N001 ( 3, 2) [000153] -c-----N---- t153 = LCL_VAR struct V17 tmp15 u:2 (last use) $388 /--* t153 struct N002 ( 4, 3) [000045] ----G------- * RETURN struct $389 ------------ BB03 [025..026) (throw), preds={BB01} succs={} [000161] ------------ IL_OFFSET void IL offset: 0x25 N001 ( 14, 5) [000096] --CXG------- CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException $VN.Void ------------ BB04 [???..???) (throw), preds={} succs={} N001 ( 14, 5) [000164] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Calculate stack level slots Too many pushed arguments for an ESP based encoding, forcing an EBP frame *************** Finishing PHASE Calculate stack level slots [no changes] *************** Starting PHASE Linear scan register alloc Clearing modified regs. buildIntervals ======== ----------------- LIVENESS: ----------------- BB01 use def in out {V00 V01} {V03 V04 V10 V11 V12 V13 V14 V15 V16} {V00 V01} {V00 V01 V11 V12} BB02 use def in out {V00 V01 V11 V12} {V17 V18 V19} {V00 V01 V11 V12} {} BB03 use def in out {} {} {} {} BB04 use def in out {} {} {} {} Interval 0: byref RefPositions {} physReg:NA Preferences=[allInt] Interval 0: (V00) byref RefPositions {} physReg:NA Preferences=[allInt] Local V01 should not be enregistered because: it is a struct Interval 1: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 1: (V03) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 2: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 2: (V04) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 3: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 3: (V10) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 4: int RefPositions {} physReg:NA Preferences=[allInt] Interval 4: (V11) int RefPositions {} physReg:NA Preferences=[allInt] Interval 5: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 5: (V12) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 6: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 6: (V13) ref (field) RefPositions {} physReg:NA Preferences=[allInt] Interval 7: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 7: (V14) ref (field) RefPositions {} physReg:NA Preferences=[allInt] Interval 8: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 8: (V16) ref (field) RefPositions {} physReg:NA Preferences=[allInt] Local V17 should not be enregistered because: it is a struct Interval 9: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 9: (V18) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 10: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 10: (V19) ref RefPositions {} physReg:NA Preferences=[allInt] FP callee save candidate vars: None floatVarCount = 0; hasLoops = 0, singleExit = 1 TUPLE STYLE DUMP BEFORE LSRA New BlockSet epoch 5, # of blocks (including unused BB00): 5, bitset array size: 1 (short) LSRA Block Sequence: BB01( 1 ) BB02( 1 ) BB03( 0 ) BB04( 0 ) BB01 [000..042) -> BB03 (cond), preds={} succs={BB02,BB03} ===== N000. IL_OFFSET IL offset: 0x0 N002. t4 = CNS_INT(h) 0x7f6678c127f0 class N000. t165 = PUTARG_REG; t4 N003. t5 = CALL help; t165 N005. V03(t7); t5 N001. V03(t8) N003. t10 = LEA(b+8) ; t8 N005. t3 = V01 MEM N000. STOREIND ; t10,t3 N002. t18 = CNS_INT(h) 0x7f6678beb1c0 class N000. t166 = PUTARG_REG; t18 N003. t19 = CALL help; t166 N005. V04(t21); t19 N001. V04(t22) N003. t24 = LEA(b+8) ; t22 N005. t17 = V01 MEM N000. STOREIND ; t24,t17 N001. V03(t13*) N004. V13(t63); t13* N001. V04(t27*) N004. V14(t68); t27* N001. t104 = CNS_INT(h) 0x7f6663fff340 static Fseq[s_twoArgArray] N002. t76 = IND ; t104 N004. V16(t78); t76 N003. V13(t110*) N004. V14(t111*) N005. t154 = CNS_INT null N006. V16(t113*) N007. t109 = FIELD_LIST; t110*,t111*,t154,t113* N000. PUTARG_STK [+0x00]; t109 N008. t105 = CNS_INT(h) 0x64008A98 [ICON_STR_HDL] N009. t106 = IND ; t105 N000. t168 = PUTARG_REG; t106 N010. t46 = CNS_INT null N000. t169 = PUTARG_REG; t46 N011. t54 = CALL ; t168,t169 N013. V10(t85); t54 N003. V10(t82*) N000. t170 = PUTARG_REG; t82* N004. t81 = CNS_INT 3 N000. t171 = PUTARG_REG; t81 N005. CALL ; t170,t171 N000. IL_OFFSET IL offset: 0x25 N001. t116 = CNS_INT(h) 0x7f6664004668 static Fseq[s_NetworkInterfaces] N002. t32 = IND ; t116 N004. V12(t98); t32 N000. IL_OFFSET IL offset: 0x25 N001. V00(t33) N003. t118 = LEA(b+16); t33 N004. t34 = IND ; t118 N006. V11(t100); t34 N000. IL_OFFSET IL offset: 0x25 N001. V11(t87) N002. V12(t88) N004. t120 = LEA(b+16); t88 N005. t89 = IND ; t120 N006. GE ; t87,t89 N007. JTRUE BB02 [025..026) (return), preds={BB01} succs={} ===== N001. V12(t92*) N003. t141 = LEA(b+8) ; t92* N004. t93 = IND ; t141 N006. V18(t126); t93 N007. V11(t94) N008. V18(t127) N000. t163 = LEA(b+8) ; t127 N009. t130 = IND ; t163 N010. ARR_BOUNDS_CHECK_Rng; t94,t130 N011. V18(t128*) N012. V11(t129*) N013. t132 = CAST ; t129* N018. t137 = LEA(b+(i*8)+16); t128*,t132 N019. t95 = IND ; t137 N023. V19(t145); t95 N026. V00(t37*) N027. CNS_INT 56 field offset Fseq[m_ParallelSendQueue] N028. t143 = ADD ; t37* N029. t44 = OBJ ; t143 N000. PUTARG_STK [+0x00]; t44 N031. V19(t146*) N000. t173 = PUTARG_REG; t146* N032. t151 = V01 MEM N000. t174 = PUTARG_REG; t151 N033. t152 = V01 MEM N000. t175 = PUTARG_REG; t152 N034. t150 = FIELD_LIST; t174,t175 N035. t124 = CNS_INT(h) 0x7f6678060518 ftn N000. t176 = PUTARG_REG; t124 N036. t121 = CNS_INT(h) 0x7f6678060518 ftn N000. t177 = PUTARG_REG; t121 N001. t178 = CNS_INT(h) 0x7f6678060518 ftn N002. t179 = IND ; t178 N037. t40 = CALLV stub; t173,t150,t176,t177,t179 N039. V17 MEM; t40 N001. V17 MEM N002. RETURN BB03 [025..026) (throw), preds={BB01} succs={} ===== N000. IL_OFFSET IL offset: 0x25 N001. CALL BB04 [???..???) (throw), preds={} succs={} ===== N001. CALL help buildIntervals second part ======== Int arg V00 in reg rdi BB00 regmask=[rdi] minReg=1 fixed> NEW BLOCK BB01 DefList: { } N003 (???,???) [000155] ------------ * IL_OFFSET void IL offset: 0x0 REG NA DefList: { } N005 ( 2, 10) [000004] ------------ * CNS_INT(h) long 0x7f6678c127f0 class REG NA $180 Interval 11: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N005.t4. CNS_INT } N007 (???,???) [000165] ------------ * PUTARG_REG long REG rdi BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> Interval 12: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> DefList: { N007.t165. PUTARG_REG } N009 ( 16, 16) [000005] --C--------- * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG NA $200 BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> Interval 13: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> DefList: { N009.t5. CALL } N011 ( 16, 16) [000007] DA---------- * STORE_LCL_VAR ref V03 tmp1 d:2 NA REG NA BB01 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N013 ( 1, 1) [000008] ------------ * LCL_VAR ref V03 tmp1 u:2 NA REG NA $200 DefList: { } N015 ( 2, 2) [000010] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N017 ( 3, 4) [000003] ------------ * LCL_FLD long V01 arg1 u:1[+0] Fseq[JobGroup] NA REG NA $2c0 Interval 14: long RefPositions {} physReg:NA Preferences=[allInt] LCL_FLD BB01 regmask=[allInt] minReg=1> DefList: { N017.t3. LCL_FLD } N019 (???,???) [000156] -A--GO------ * STOREIND long REG NA LCL_VAR BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> DefList: { } N021 ( 2, 10) [000018] ------------ * CNS_INT(h) long 0x7f6678beb1c0 class REG NA $182 Interval 15: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N021.t18. CNS_INT } N023 (???,???) [000166] ------------ * PUTARG_REG long REG rdi BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> Interval 16: long RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> DefList: { N023.t166. PUTARG_REG } N025 ( 16, 16) [000019] --C--------- * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG NA $201 BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> Interval 17: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> DefList: { N025.t19. CALL } N027 ( 16, 16) [000021] DA---------- * STORE_LCL_VAR ref V04 tmp2 d:2 NA REG NA BB01 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N029 ( 1, 1) [000022] ------------ * LCL_VAR ref V04 tmp2 u:2 NA REG NA $201 DefList: { } N031 ( 2, 2) [000024] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N033 ( 3, 4) [000017] ------------ * LCL_FLD int V01 arg1 u:1[+8] Fseq[Version] NA REG NA $300 Interval 18: int RefPositions {} physReg:NA Preferences=[allInt] LCL_FLD BB01 regmask=[allInt] minReg=1> DefList: { N033.t17. LCL_FLD } N035 (???,???) [000157] -A--GO------ * STOREIND int REG NA LCL_VAR BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> DefList: { } N037 ( 1, 1) [000013] ------------ * LCL_VAR ref V03 tmp1 u:2 NA (last use) REG NA $200 DefList: { } N039 ( 11, 8) [000063] DA---------- * STORE_LCL_VAR ref V13 tmp11 d:2 NA REG NA LCL_VAR BB01 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N041 ( 1, 1) [000027] ------------ * LCL_VAR ref V04 tmp2 u:2 NA (last use) REG NA $201 DefList: { } N043 ( 11, 8) [000068] DA---------- * STORE_LCL_VAR ref V14 tmp12 d:2 NA REG NA LCL_VAR BB01 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N045 ( 2, 10) [000104] ------------ * CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] REG NA $184 Interval 19: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N045.t104. CNS_INT } N047 ( 4, 12) [000076] n---G------- * IND ref REG NA BB01 regmask=[allInt] minReg=1 last> Interval 20: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB01 regmask=[allInt] minReg=1> DefList: { N047.t76. IND } N049 ( 8, 15) [000078] DA--G------- * STORE_LCL_VAR ref V16 tmp14 d:2 NA REG NA BB01 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N051 ( 3, 2) [000110] ------------ * LCL_VAR ref V13 tmp11 u:2 NA (last use) REG NA $200 DefList: { } N053 ( 3, 2) [000111] ------------ * LCL_VAR ref V14 tmp12 u:2 NA (last use) REG NA $201 DefList: { } N055 ( 1, 1) [000154] ------------ * CNS_INT ref null REG NA $VN.Null Interval 21: ref RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N055.t154. CNS_INT } N057 ( 3, 2) [000113] ------------ * LCL_VAR ref V16 tmp14 u:2 NA (last use) REG NA DefList: { N055.t154. CNS_INT } N059 ( 10, 7) [000109] -c---------- * FIELD_LIST struct REG NA $380 Contained DefList: { N055.t154. CNS_INT } N061 (???,???) [000167] ------------ * PUTARG_STK [+0x00] void (4 slots) REG NA LCL_VAR BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N063 ( 2, 10) [000105] ------------ * CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] REG NA $185 Interval 22: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N063.t105. CNS_INT } N065 ( 4, 12) [000106] n---G------- * IND ref REG NA BB01 regmask=[allInt] minReg=1 last> Interval 23: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB01 regmask=[allInt] minReg=1> DefList: { N065.t106. IND } N067 (???,???) [000168] ----G------- * PUTARG_REG ref REG rsi BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> Interval 24: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> DefList: { N067.t168. PUTARG_REG } N069 ( 1, 1) [000046] ------------ * CNS_INT ref null REG NA $VN.Null Interval 25: ref RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N067.t168. PUTARG_REG; N069.t46. CNS_INT } N071 (???,???) [000169] ------------ * PUTARG_REG ref REG rdi BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> Interval 26: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> DefList: { N067.t168. PUTARG_REG; N071.t169. PUTARG_REG } N073 ( 32, 27) [000054] --CXG------- * CALL ref System.String.FormatHelper REG NA $1ce BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> Interval 27: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> DefList: { N073.t54. CALL } N075 ( 32, 27) [000085] DA-XG------- * STORE_LCL_VAR ref V10 tmp8 d:2 NA REG NA BB01 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N077 ( 1, 1) [000082] ------------ * LCL_VAR ref V10 tmp8 u:2 NA (last use) REG NA $1ce DefList: { } N079 (???,???) [000170] ------------ * PUTARG_REG ref REG rsi BB01 regmask=[rsi] minReg=1> LCL_VAR BB01 regmask=[rsi] minReg=1 last fixed> Interval 28: ref RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> DefList: { N079.t170. PUTARG_REG } N081 ( 1, 1) [000081] ------------ * CNS_INT int 3 REG NA $44 Interval 29: int RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N079.t170. PUTARG_REG; N081.t81. CNS_INT } N083 (???,???) [000171] ------------ * PUTARG_REG int REG rdi BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> Interval 30: int RefPositions {} physReg:NA Preferences=[allInt] BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> DefList: { N079.t170. PUTARG_REG; N083.t171. PUTARG_REG } N085 ( 16, 9) [000083] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal REG NA $VN.Void BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1> BB01 regmask=[rcx] minReg=1> BB01 regmask=[rdx] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[r8] minReg=1> BB01 regmask=[r9] minReg=1> BB01 regmask=[r10] minReg=1> BB01 regmask=[r11] minReg=1> DefList: { } N087 (???,???) [000158] ------------ * IL_OFFSET void IL offset: 0x25 REG NA DefList: { } N089 ( 2, 10) [000116] ------------ * CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] REG NA $186 Interval 31: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB01 regmask=[allInt] minReg=1> DefList: { N089.t116. CNS_INT } N091 ( 4, 12) [000032] n---G------- * IND ref REG NA BB01 regmask=[allInt] minReg=1 last> Interval 32: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB01 regmask=[allInt] minReg=1> DefList: { N091.t32. IND } N093 ( 4, 12) [000098] DA--G------- * STORE_LCL_VAR ref V12 tmp10 d:2 NA REG NA BB01 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N095 (???,???) [000159] ------------ * IL_OFFSET void IL offset: 0x25 REG NA DefList: { } N097 ( 1, 1) [000033] ------------ * LCL_VAR byref V00 this u:1 NA REG NA $80 DefList: { } N099 ( 2, 2) [000118] -c---------- * LEA(b+16) byref REG NA Contained DefList: { } N101 ( 4, 4) [000034] *--XG------- * IND int REG NA LCL_VAR BB01 regmask=[allInt] minReg=1 last> Interval 33: int RefPositions {} physReg:NA Preferences=[allInt] IND BB01 regmask=[allInt] minReg=1> DefList: { N101.t34. IND } N103 ( 4, 4) [000100] DA-XG------- * STORE_LCL_VAR int V11 tmp9 d:2 NA REG NA BB01 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N105 (???,???) [000160] ------------ * IL_OFFSET void IL offset: 0x25 REG NA DefList: { } N107 ( 1, 1) [000087] ------------ * LCL_VAR int V11 tmp9 u:2 NA REG NA DefList: { } N109 ( 1, 1) [000088] ------------ * LCL_VAR ref V12 tmp10 u:2 NA REG NA DefList: { } N111 ( 2, 2) [000120] -c---------- * LEA(b+16) byref REG NA Contained DefList: { } N113 ( 4, 4) [000089] -c-XG------- * IND int REG NA Contained DefList: { } N115 ( 6, 6) [000090] N--XG--N-U-- * GE void REG NA LCL_VAR BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1 last> DefList: { } N117 ( 8, 8) [000091] ---XG------- * JTRUE void REG NA CHECKING LAST USES for BB01, liveout={V00 V01 V11 V12} ============================== use: {V00 V01} def: {V03 V04 V10 V11 V12 V13 V14 V15 V16} NEW BLOCK BB02 Setting BB01 as the predecessor for determining incoming variable registers of BB02 DefList: { } N121 ( 1, 1) [000092] ------------ * LCL_VAR ref V12 tmp10 u:2 NA (last use) REG NA DefList: { } N123 ( 2, 2) [000141] -c---------- * LEA(b+8) byref REG NA Contained DefList: { } N125 ( 4, 4) [000093] n---GO------ * IND ref REG NA LCL_VAR BB02 regmask=[allInt] minReg=1 last> Interval 34: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB02 regmask=[allInt] minReg=1> DefList: { N125.t93. IND } N127 ( 4, 4) [000126] DA--GO------ * STORE_LCL_VAR ref V18 tmp16 d:2 NA REG NA BB02 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last> DefList: { } N129 ( 1, 1) [000094] ------------ * LCL_VAR int V11 tmp9 u:2 NA REG NA DefList: { } N131 ( 1, 1) [000127] ------------ * LCL_VAR ref V18 tmp16 u:2 NA REG NA DefList: { } N133 (???,???) [000163] -c---------- * LEA(b+8) ref REG NA Contained DefList: { } N135 ( 3, 3) [000130] -c-X-------- * IND int REG NA Contained DefList: { } N137 ( 8, 11) [000131] ---X-------- * ARR_BOUNDS_CHECK_Rng void REG NA LCL_VAR BB02 regmask=[allInt] minReg=1 last> LCL_VAR BB02 regmask=[allInt] minReg=1 last> DefList: { } N139 ( 1, 1) [000128] ------------ * LCL_VAR ref V18 tmp16 u:2 NA (last use) REG NA DefList: { } N141 ( 1, 1) [000129] ------------ * LCL_VAR int V11 tmp9 u:2 NA (last use) REG NA DefList: { } N143 ( 2, 3) [000132] ------------ * CAST long <- int REG NA LCL_VAR BB02 regmask=[allInt] minReg=1 last> Interval 35: long RefPositions {} physReg:NA Preferences=[allInt] CAST BB02 regmask=[allInt] minReg=1> DefList: { N143.t132. CAST } N145 ( 5, 6) [000137] -c---------- * LEA(b+(i*8)+16) byref REG NA Contained DefList: { N143.t132. CAST } N147 ( 6, 7) [000095] a---G------- * IND ref REG NA LCL_VAR BB02 regmask=[allInt] minReg=1 last> BB02 regmask=[allInt] minReg=1 last> Interval 36: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB02 regmask=[allInt] minReg=1> DefList: { N147.t95. IND } N149 ( 18, 22) [000145] DA-XGO----L- * STORE_LCL_VAR ref V19 tmp17 d:2 NA REG NA BB02 regmask=[allInt] minReg=1 last> Assigning related to STORE_LCL_VAR BB02 regmask=[allInt] minReg=1 last> DefList: { } N151 ( 1, 1) [000037] ------------ * LCL_VAR byref V00 this u:1 NA (last use) REG NA $80 DefList: { } N153 ( 1, 1) [000142] -c---------- * CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] REG NA $245 Contained DefList: { } N155 ( 3, 3) [000143] ------------ * ADD byref REG NA $289 LCL_VAR BB02 regmask=[allInt] minReg=1 last> Interval 37: byref RefPositions {} physReg:NA Preferences=[allInt] ADD BB02 regmask=[allInt] minReg=1> Assigning related to DefList: { N155.t143. ADD } N157 ( 9, 7) [000044] nc--GO------ * OBJ struct REG NA Contained DefList: { N155.t143. ADD } N159 (???,???) [000172] ----GO------ * PUTARG_STK [+0x00] void (7 slots) (RepInstr) REG NA Interval 38: int RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[rdi] minReg=1> PUTARG_STK BB02 regmask=[rdi] minReg=1 fixed> Interval 39: int RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[rcx] minReg=1> PUTARG_STK BB02 regmask=[rcx] minReg=1 fixed> Interval 40: int RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[rsi] minReg=1> PUTARG_STK BB02 regmask=[rsi] minReg=1 fixed> BB02 regmask=[allInt] minReg=1 last> PUTARG_STK BB02 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB02 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB02 regmask=[rsi] minReg=1 last fixed> DefList: { } N161 ( 1, 1) [000146] ------------ * LCL_VAR ref V19 tmp17 u:2 NA (last use) REG NA DefList: { } N163 (???,???) [000173] ------------ * PUTARG_REG ref REG rdi BB02 regmask=[rdi] minReg=1> LCL_VAR BB02 regmask=[rdi] minReg=1 last fixed> Interval 41: ref RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[rdi] minReg=1> PUTARG_REG BB02 regmask=[rdi] minReg=1 fixed> DefList: { N163.t173. PUTARG_REG } N165 ( 3, 4) [000151] ------------ * LCL_FLD long V01 arg1 u:1[+0] NA REG NA $144 Interval 42: long RefPositions {} physReg:NA Preferences=[allInt] LCL_FLD BB02 regmask=[allInt] minReg=1> DefList: { N163.t173. PUTARG_REG; N165.t151. LCL_FLD } N167 (???,???) [000174] ------------ * PUTARG_REG long REG rdx BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> Interval 43: long RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[rdx] minReg=1> PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed> DefList: { N163.t173. PUTARG_REG; N167.t174. PUTARG_REG } N169 ( 3, 4) [000152] ------------ * LCL_FLD long V01 arg1 u:1[+8] NA (last use) REG NA $145 Interval 44: long RefPositions {} physReg:NA Preferences=[allInt] LCL_FLD BB02 regmask=[allInt] minReg=1> DefList: { N163.t173. PUTARG_REG; N167.t174. PUTARG_REG; N169.t152. LCL_FLD } N171 (???,???) [000175] ------------ * PUTARG_REG long REG rcx BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> Interval 45: long RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[rcx] minReg=1> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed> DefList: { N163.t173. PUTARG_REG; N167.t174. PUTARG_REG; N171.t175. PUTARG_REG } N173 ( 6, 8) [000150] -c---------- * FIELD_LIST struct REG NA $384 Contained DefList: { N163.t173. PUTARG_REG; N167.t174. PUTARG_REG; N171.t175. PUTARG_REG } N175 ( 2, 10) [000124] ------------ * CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a Interval 46: long RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[r11] minReg=1> CNS_INT BB02 regmask=[r11] minReg=1 fixed> DefList: { N163.t173. PUTARG_REG; N167.t174. PUTARG_REG; N171.t175. PUTARG_REG; N175.t124. CNS_INT } N177 (???,???) [000176] ------------ * PUTARG_REG long REG r11 BB02 regmask=[r11] minReg=1> BB02 regmask=[r11] minReg=1 last fixed> Interval 47: long RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[r11] minReg=1> PUTARG_REG BB02 regmask=[r11] minReg=1 fixed> DefList: { N163.t173. PUTARG_REG; N167.t174. PUTARG_REG; N171.t175. PUTARG_REG; N177.t176. PUTARG_REG } N179 ( 2, 10) [000121] ------------ * CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a Interval 48: long RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[r11] minReg=1> CNS_INT BB02 regmask=[r11] minReg=1 fixed> DefList: { N163.t173. PUTARG_REG; N167.t174. PUTARG_REG; N171.t175. PUTARG_REG; N177.t176. PUTARG_REG; N179.t121. CNS_INT } N181 (???,???) [000177] ------------ * PUTARG_REG long REG rsi BB02 regmask=[rsi] minReg=1> BB02 regmask=[rsi] minReg=1 last fixed> Interval 49: long RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[rsi] minReg=1> PUTARG_REG BB02 regmask=[rsi] minReg=1 fixed> DefList: { N163.t173. PUTARG_REG; N167.t174. PUTARG_REG; N171.t175. PUTARG_REG; N177.t176. PUTARG_REG; N181.t177. PUTARG_REG } N183 ( 2, 10) [000178] ------------ * CNS_INT(h) long 0x7f6678060518 ftn REG NA Interval 50: long RefPositions {} physReg:NA Preferences=[allInt] CNS_INT BB02 regmask=[allInt] minReg=1> DefList: { N163.t173. PUTARG_REG; N167.t174. PUTARG_REG; N171.t175. PUTARG_REG; N177.t176. PUTARG_REG; N181.t177. PUTARG_REG; N183.t178. CNS_INT } N185 ( 4, 12) [000179] -c---------- * IND long REG NA Contained DefList: { N163.t173. PUTARG_REG; N167.t174. PUTARG_REG; N171.t175. PUTARG_REG; N177.t176. PUTARG_REG; N181.t177. PUTARG_REG; N183.t178. CNS_INT } N187 ( 61, 70) [000040] --CXGO------ * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend REG NA,NA $385 BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last fixed> BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> BB02 regmask=[r11] minReg=1> BB02 regmask=[r11] minReg=1 last fixed> BB02 regmask=[rsi] minReg=1> BB02 regmask=[rsi] minReg=1 last fixed> BB02 regmask=[allInt] minReg=1 last> BB02 regmask=[rax] minReg=1> BB02 regmask=[rcx] minReg=1> BB02 regmask=[rdx] minReg=1> BB02 regmask=[rsi] minReg=1> BB02 regmask=[rdi] minReg=1> BB02 regmask=[r8] minReg=1> BB02 regmask=[r9] minReg=1> BB02 regmask=[r10] minReg=1> BB02 regmask=[r11] minReg=1> Interval 51: long RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[rax] minReg=1> CALL[0] BB02 regmask=[rax] minReg=1 fixed> Interval 52: long RefPositions {} physReg:NA Preferences=[allInt] BB02 regmask=[rdx] minReg=1> CALL[1] BB02 regmask=[rdx] minReg=1 fixed> DefList: { N187.t40. CALL; N187.t40. CALL } N189 ( 65, 73) [000123] DA-XGO------ * STORE_LCL_VAR struct V17 tmp15 d:2 NA REG NA BB02 regmask=[allInt] minReg=1 last> BB02 regmask=[allInt] minReg=1 last> DefList: { } N191 ( 3, 2) [000153] -c-----N---- * LCL_VAR struct V17 tmp15 u:2 NA (last use) REG NA $388 Contained DefList: { } N193 ( 4, 3) [000045] ----G------- * RETURN struct REG NA $389 CHECKING LAST USES for BB02, liveout={} ============================== use: {V00 V01 V11 V12} def: {V17 V18 V19} NEW BLOCK BB03 Setting BB01 as the predecessor for determining incoming variable registers of BB03 firstColdLoc = 197 DefList: { } N197 (???,???) [000161] ------------ * IL_OFFSET void IL offset: 0x25 REG NA DefList: { } N199 ( 14, 5) [000096] --CXG------- * CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException REG NA $VN.Void BB03 regmask=[rax] minReg=1> BB03 regmask=[rcx] minReg=1> BB03 regmask=[rdx] minReg=1> BB03 regmask=[rsi] minReg=1> BB03 regmask=[rdi] minReg=1> BB03 regmask=[r8] minReg=1> BB03 regmask=[r9] minReg=1> BB03 regmask=[r10] minReg=1> BB03 regmask=[r11] minReg=1> CHECKING LAST USES for BB03, liveout={} ============================== use: {} def: {} NEW BLOCK BB04 No predecessor; Setting BB03 as the predecessor for determining incoming variable registers of BB04 DefList: { } N203 ( 14, 5) [000164] --CXG------- * CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL REG NA BB04 regmask=[rax] minReg=1> BB04 regmask=[rcx] minReg=1> BB04 regmask=[rdx] minReg=1> BB04 regmask=[rsi] minReg=1> BB04 regmask=[rdi] minReg=1> BB04 regmask=[r8] minReg=1> BB04 regmask=[r9] minReg=1> BB04 regmask=[r10] minReg=1> BB04 regmask=[r11] minReg=1> CHECKING LAST USES for BB04, liveout={} ============================== use: {} def: {} Linear scan intervals BEFORE VALIDATING INTERVALS: Interval 0: (V00) byref RefPositions {#0@0 #118@101 #138@155} physReg:rdi Preferences=[rbx r12-r15] RelatedInterval Interval 1: (V03) ref RefPositions {#21@12 #23@19 #48@39} physReg:NA Preferences=[rbx r12-r15] RelatedInterval Interval 2: (V04) ref RefPositions {#44@28 #46@35 #50@43} physReg:NA Preferences=[allInt] RelatedInterval Interval 3: (V10) ref RefPositions {#90@76 #92@79} physReg:NA Preferences=[rsi] Interval 4: (V11) int RefPositions {#121@104 #122@115 #129@137 #131@143} physReg:NA Preferences=[allInt] Interval 5: (V12) ref RefPositions {#117@94 #123@115 #125@125} physReg:NA Preferences=[allInt] Interval 6: (V13) ref (field) RefPositions {#49@40 #58@61} physReg:NA Preferences=[allInt] Interval 7: (V14) ref (field) RefPositions {#51@44 #59@61} physReg:NA Preferences=[allInt] Interval 8: (V16) ref (field) RefPositions {#56@50 #61@61} physReg:NA Preferences=[allInt] Interval 9: (V18) ref RefPositions {#128@128 #130@137 #133@147} physReg:NA Preferences=[allInt] Interval 10: (V19) ref RefPositions {#137@150 #151@163} physReg:NA Preferences=[rdi] Interval 11: long (constant) RefPositions {#2@6 #4@7} physReg:NA Preferences=[rdi] Interval 12: long RefPositions {#6@8 #8@9} physReg:NA Preferences=[rdi] Interval 13: ref RefPositions {#19@10 #20@11} physReg:NA Preferences=[rax] RelatedInterval Interval 14: long RefPositions {#22@18 #24@19} physReg:NA Preferences=[allInt] Interval 15: long (constant) RefPositions {#25@22 #27@23} physReg:NA Preferences=[rdi] Interval 16: long RefPositions {#29@24 #31@25} physReg:NA Preferences=[rdi] Interval 17: ref RefPositions {#42@26 #43@27} physReg:NA Preferences=[rax] RelatedInterval Interval 18: int RefPositions {#45@34 #47@35} physReg:NA Preferences=[allInt] Interval 19: long (constant) RefPositions {#52@46 #53@47} physReg:NA Preferences=[allInt] Interval 20: ref RefPositions {#54@48 #55@49} physReg:NA Preferences=[allInt] RelatedInterval Interval 21: ref (constant) RefPositions {#57@56 #60@61} physReg:NA Preferences=[allInt] Interval 22: long (constant) RefPositions {#62@64 #63@65} physReg:NA Preferences=[allInt] Interval 23: ref RefPositions {#64@66 #66@67} physReg:NA Preferences=[rsi] Interval 24: ref RefPositions {#68@68 #75@73} physReg:NA Preferences=[rsi] Interval 25: ref (constant) RefPositions {#69@70 #71@71} physReg:NA Preferences=[rdi] Interval 26: ref RefPositions {#73@72 #77@73} physReg:NA Preferences=[rdi] Interval 27: ref RefPositions {#88@74 #89@75} physReg:NA Preferences=[rax] RelatedInterval Interval 28: ref RefPositions {#94@80 #101@85} physReg:NA Preferences=[rsi] Interval 29: int (constant) RefPositions {#95@82 #97@83} physReg:NA Preferences=[rdi] Interval 30: int RefPositions {#99@84 #103@85} physReg:NA Preferences=[rdi] Interval 31: long (constant) RefPositions {#113@90 #114@91} physReg:NA Preferences=[allInt] Interval 32: ref RefPositions {#115@92 #116@93} physReg:NA Preferences=[allInt] RelatedInterval Interval 33: int RefPositions {#119@102 #120@103} physReg:NA Preferences=[allInt] RelatedInterval Interval 34: ref RefPositions {#126@126 #127@127} physReg:NA Preferences=[allInt] RelatedInterval Interval 35: long RefPositions {#132@144 #134@147} physReg:NA Preferences=[allInt] Interval 36: ref RefPositions {#135@148 #136@149} physReg:NA Preferences=[allInt] RelatedInterval Interval 37: byref RefPositions {#139@156 #146@159} physReg:NA Preferences=[allInt] Interval 38: int (INTERNAL) RefPositions {#141@159 #147@159} physReg:NA Preferences=[rdi] Interval 39: int (INTERNAL) RefPositions {#143@159 #148@159} physReg:NA Preferences=[rcx] Interval 40: int (INTERNAL) RefPositions {#145@159 #149@159} physReg:NA Preferences=[rsi] Interval 41: ref RefPositions {#153@164 #178@187} physReg:NA Preferences=[rdi] Interval 42: long RefPositions {#154@166 #156@167} physReg:NA Preferences=[rdx] Interval 43: long RefPositions {#158@168 #180@187} physReg:NA Preferences=[rdx] Interval 44: long RefPositions {#159@170 #161@171} physReg:NA Preferences=[rcx] Interval 45: long RefPositions {#163@172 #182@187} physReg:NA Preferences=[rcx] Interval 46: long (constant) RefPositions {#165@176 #167@177} physReg:NA Preferences=[r11] Interval 47: long RefPositions {#169@178 #184@187} physReg:NA Preferences=[r11] Interval 48: long (def-use conflict) (constant) RefPositions {#171@180 #173@181} physReg:NA Preferences=[rsi r11] Interval 49: long RefPositions {#175@182 #186@187} physReg:NA Preferences=[rsi] Interval 50: long (constant) RefPositions {#176@184 #187@187} physReg:NA Preferences=[allInt] Interval 51: long RefPositions {#198@188 #201@189} physReg:NA Preferences=[rax] Interval 52: long RefPositions {#200@188 #202@189} physReg:NA Preferences=[rdx] ------------ REFPOSITIONS BEFORE VALIDATING INTERVALS: ------------ BB00 regmask=[rdi] minReg=1 fixed regOptional> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_FLD BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_FLD BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> IND BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> CNS_INT BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1 last> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> IND BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> BB01 regmask=[rsi] minReg=1> LCL_VAR BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> IND BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> IND BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1 last> IND BB02 regmask=[allInt] minReg=1> BB02 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1 last> CAST BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1 last> BB02 regmask=[allInt] minReg=1 last> IND BB02 regmask=[allInt] minReg=1> BB02 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1 last> ADD BB02 regmask=[allInt] minReg=1> BB02 regmask=[rdi] minReg=1> PUTARG_STK BB02 regmask=[rdi] minReg=1 fixed> BB02 regmask=[rcx] minReg=1> PUTARG_STK BB02 regmask=[rcx] minReg=1 fixed> BB02 regmask=[rsi] minReg=1> PUTARG_STK BB02 regmask=[rsi] minReg=1 fixed> BB02 regmask=[allInt] minReg=1 last> PUTARG_STK BB02 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB02 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB02 regmask=[rsi] minReg=1 last fixed> BB02 regmask=[rdi] minReg=1> LCL_VAR BB02 regmask=[rdi] minReg=1 last fixed> BB02 regmask=[rdi] minReg=1> PUTARG_REG BB02 regmask=[rdi] minReg=1 fixed> LCL_FLD BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> BB02 regmask=[rdx] minReg=1> PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed> LCL_FLD BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> BB02 regmask=[rcx] minReg=1> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed> BB02 regmask=[r11] minReg=1> CNS_INT BB02 regmask=[r11] minReg=1 fixed> BB02 regmask=[r11] minReg=1> BB02 regmask=[r11] minReg=1 last fixed> BB02 regmask=[r11] minReg=1> PUTARG_REG BB02 regmask=[r11] minReg=1 fixed> BB02 regmask=[r11] minReg=1> CNS_INT BB02 regmask=[r11] minReg=1 fixed> BB02 regmask=[rsi] minReg=1> BB02 regmask=[rsi] minReg=1 last fixed> BB02 regmask=[rsi] minReg=1> PUTARG_REG BB02 regmask=[rsi] minReg=1 fixed> CNS_INT BB02 regmask=[allInt] minReg=1> BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last fixed> BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> BB02 regmask=[r11] minReg=1> BB02 regmask=[r11] minReg=1 last fixed> BB02 regmask=[rsi] minReg=1> BB02 regmask=[rsi] minReg=1 last fixed> BB02 regmask=[allInt] minReg=1 last> BB02 regmask=[rax] minReg=1 last> BB02 regmask=[rcx] minReg=1 last> BB02 regmask=[rdx] minReg=1 last> BB02 regmask=[rsi] minReg=1 last> BB02 regmask=[rdi] minReg=1 last> BB02 regmask=[r8] minReg=1 last> BB02 regmask=[r9] minReg=1 last> BB02 regmask=[r10] minReg=1 last> BB02 regmask=[r11] minReg=1 last> BB02 regmask=[rax] minReg=1> CALL[0] BB02 regmask=[rax] minReg=1 fixed> BB02 regmask=[rdx] minReg=1> CALL[1] BB02 regmask=[rdx] minReg=1 fixed> BB02 regmask=[allInt] minReg=1 last> BB02 regmask=[allInt] minReg=1 last> BB03 regmask=[rax] minReg=1 last> BB03 regmask=[rcx] minReg=1 last> BB03 regmask=[rdx] minReg=1 last> BB03 regmask=[rsi] minReg=1 last> BB03 regmask=[rdi] minReg=1 last> BB03 regmask=[r8] minReg=1 last> BB03 regmask=[r9] minReg=1 last> BB03 regmask=[r10] minReg=1 last> BB03 regmask=[r11] minReg=1 last> BB04 regmask=[rax] minReg=1 last> BB04 regmask=[rcx] minReg=1 last> BB04 regmask=[rdx] minReg=1 last> BB04 regmask=[rsi] minReg=1 last> BB04 regmask=[rdi] minReg=1 last> BB04 regmask=[r8] minReg=1 last> BB04 regmask=[r9] minReg=1 last> BB04 regmask=[r10] minReg=1 last> BB04 regmask=[r11] minReg=1 last> ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1 last> ----------------- BB00 regmask=[rdi] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[rsi] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[rdi] minReg=1 last fixed> ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> TUPLE STYLE DUMP WITH REF POSITIONS Incoming Parameters: V00 BB01 [000..042) -> BB03 (cond), preds={} succs={BB02,BB03} ===== N003. IL_OFFSET IL offset: 0x0 N005. CNS_INT(h) 0x7f6678c127f0 class Def:(#2) N007. PUTARG_REG Use:(#4) Fixed:rdi(#3) * Def:(#6) rdi N009. CALL help Use:(#8) Fixed:rdi(#7) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#19) rax Pref: N011. V03(L1) Use:(#20) * Def:(#21) Pref: N013. V03(L1) N015. LEA(b+8) N017. V01 MEM Def:(#22) N019. STOREIND Use:(#23) Use:(#24) * N021. CNS_INT(h) 0x7f6678beb1c0 class Def:(#25) N023. PUTARG_REG Use:(#27) Fixed:rdi(#26) * Def:(#29) rdi N025. CALL help Use:(#31) Fixed:rdi(#30) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#42) rax Pref: N027. V04(L2) Use:(#43) * Def:(#44) Pref: N029. V04(L2) N031. LEA(b+8) N033. V01 MEM Def:(#45) N035. STOREIND Use:(#46) Use:(#47) * N037. V03(L1) N039. V13(L6) Use:(#48) * Def:(#49) N041. V04(L2) N043. V14(L7) Use:(#50) * Def:(#51) N045. CNS_INT(h) 0x7f6663fff340 static Fseq[s_twoArgArray] Def:(#52) N047. IND Use:(#53) * Def:(#54) Pref: N049. V16(L8) Use:(#55) * Def:(#56) N051. V13(L6) N053. V14(L7) N055. CNS_INT null Def:(#57) N057. V16(L8) N059. FIELD_LIST N061. PUTARG_STK [+0x00] Use:(#58) * Use:(#59) * Use:(#60) * Use:(#61) * N063. CNS_INT(h) 0x64008A98 [ICON_STR_HDL] Def:(#62) N065. IND Use:(#63) * Def:(#64) N067. PUTARG_REG Use:(#66) Fixed:rsi(#65) * Def:(#68) rsi N069. CNS_INT null Def:(#69) N071. PUTARG_REG Use:(#71) Fixed:rdi(#70) * Def:(#73) rdi N073. CALL Use:(#75) Fixed:rsi(#74) * Use:(#77) Fixed:rdi(#76) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#88) rax Pref: N075. V10(L3) Use:(#89) * Def:(#90) N077. V10(L3) N079. PUTARG_REG Use:(#92) Fixed:rsi(#91) * Def:(#94) rsi N081. CNS_INT 3 Def:(#95) N083. PUTARG_REG Use:(#97) Fixed:rdi(#96) * Def:(#99) rdi N085. CALL Use:(#101) Fixed:rsi(#100) * Use:(#103) Fixed:rdi(#102) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 N087. IL_OFFSET IL offset: 0x25 N089. CNS_INT(h) 0x7f6664004668 static Fseq[s_NetworkInterfaces] Def:(#113) N091. IND Use:(#114) * Def:(#115) Pref: N093. V12(L5) Use:(#116) * Def:(#117) N095. IL_OFFSET IL offset: 0x25 N097. V00(L0) N099. LEA(b+16) N101. IND Use:(#118) Def:(#119) Pref: N103. V11(L4) Use:(#120) * Def:(#121) N105. IL_OFFSET IL offset: 0x25 N107. V11(L4) N109. V12(L5) N111. LEA(b+16) N113. IND N115. GE Use:(#122) Use:(#123) N117. JTRUE BB02 [025..026) (return), preds={BB01} succs={} ===== N121. V12(L5) N123. LEA(b+8) N125. IND Use:(#125) * Def:(#126) Pref: N127. V18(L9) Use:(#127) * Def:(#128) N129. V11(L4) N131. V18(L9) N133. LEA(b+8) N135. IND N137. ARR_BOUNDS_CHECK_Rng Use:(#129) Use:(#130) N139. V18(L9) N141. V11(L4) N143. CAST Use:(#131) * Def:(#132) N145. LEA(b+(i*8)+16) N147. IND Use:(#133) * Use:(#134) * Def:(#135) Pref: N149. V19(L10) Use:(#136) * Def:(#137) N151. V00(L0) N153. CNS_INT 56 field offset Fseq[m_ParallelSendQueue] N155. ADD Use:(#138) * Def:(#139) N157. OBJ N159. PUTARG_STK [+0x00] Def:(#141) rdi Def:(#143) rcx Def:(#145) rsi Use:(#146) * Use:(#147) * Use:(#148) * Use:(#149) * N161. V19(L10) N163. PUTARG_REG Use:(#151) Fixed:rdi(#150) * Def:(#153) rdi N165. V01 MEM Def:(#154) N167. PUTARG_REG Use:(#156) Fixed:rdx(#155) * Def:(#158) rdx N169. V01 MEM Def:(#159) N171. PUTARG_REG Use:(#161) Fixed:rcx(#160) * Def:(#163) rcx N173. FIELD_LIST N175. CNS_INT(h) 0x7f6678060518 ftn Def:(#165) r11 N177. PUTARG_REG Use:(#167) Fixed:r11(#166) * Def:(#169) r11 N179. CNS_INT(h) 0x7f6678060518 ftn Def:(#171) r11 N181. PUTARG_REG Use:(#173) Fixed:rsi(#172) * Def:(#175) rsi N183. CNS_INT(h) 0x7f6678060518 ftn Def:(#176) N185. IND N187. CALLV stub Use:(#178) Fixed:rdi(#177) * Use:(#180) Fixed:rdx(#179) * Use:(#182) Fixed:rcx(#181) * Use:(#184) Fixed:r11(#183) * Use:(#186) Fixed:rsi(#185) * Use:(#187) * Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Def:(#198) rax Def:(#200) rdx N189. V17 MEM Use:(#201) * Use:(#202) * N191. V17 MEM N193. RETURN BB03 [025..026) (throw), preds={BB01} succs={} ===== N197. IL_OFFSET IL offset: 0x25 N199. CALL Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 BB04 [???..???) (throw), preds={} succs={} ===== N203. CALL help Kill: rax rcx rdx rsi rdi r8 r9 r10 r11 Linear scan intervals after buildIntervals: Interval 0: (V00) byref RefPositions {#0@0 #118@101 #138@155} physReg:rdi Preferences=[rbx r12-r15] RelatedInterval Interval 1: (V03) ref RefPositions {#21@12 #23@19 #48@39} physReg:NA Preferences=[rbx r12-r15] RelatedInterval Interval 2: (V04) ref RefPositions {#44@28 #46@35 #50@43} physReg:NA Preferences=[allInt] RelatedInterval Interval 3: (V10) ref RefPositions {#90@76 #92@79} physReg:NA Preferences=[rsi] Interval 4: (V11) int RefPositions {#121@104 #122@115 #129@137 #131@143} physReg:NA Preferences=[allInt] Interval 5: (V12) ref RefPositions {#117@94 #123@115 #125@125} physReg:NA Preferences=[allInt] Interval 6: (V13) ref (field) RefPositions {#49@40 #58@61} physReg:NA Preferences=[allInt] Interval 7: (V14) ref (field) RefPositions {#51@44 #59@61} physReg:NA Preferences=[allInt] Interval 8: (V16) ref (field) RefPositions {#56@50 #61@61} physReg:NA Preferences=[allInt] Interval 9: (V18) ref RefPositions {#128@128 #130@137 #133@147} physReg:NA Preferences=[allInt] Interval 10: (V19) ref RefPositions {#137@150 #151@163} physReg:NA Preferences=[rdi] Interval 11: long (constant) RefPositions {#2@6 #4@7} physReg:NA Preferences=[rdi] Interval 12: long RefPositions {#6@8 #8@9} physReg:NA Preferences=[rdi] Interval 13: ref RefPositions {#19@10 #20@11} physReg:NA Preferences=[rax] RelatedInterval Interval 14: long RefPositions {#22@18 #24@19} physReg:NA Preferences=[allInt] Interval 15: long (constant) RefPositions {#25@22 #27@23} physReg:NA Preferences=[rdi] Interval 16: long RefPositions {#29@24 #31@25} physReg:NA Preferences=[rdi] Interval 17: ref RefPositions {#42@26 #43@27} physReg:NA Preferences=[rax] RelatedInterval Interval 18: int RefPositions {#45@34 #47@35} physReg:NA Preferences=[allInt] Interval 19: long (constant) RefPositions {#52@46 #53@47} physReg:NA Preferences=[allInt] Interval 20: ref RefPositions {#54@48 #55@49} physReg:NA Preferences=[allInt] RelatedInterval Interval 21: ref (constant) RefPositions {#57@56 #60@61} physReg:NA Preferences=[allInt] Interval 22: long (constant) RefPositions {#62@64 #63@65} physReg:NA Preferences=[allInt] Interval 23: ref RefPositions {#64@66 #66@67} physReg:NA Preferences=[rsi] Interval 24: ref RefPositions {#68@68 #75@73} physReg:NA Preferences=[rsi] Interval 25: ref (constant) RefPositions {#69@70 #71@71} physReg:NA Preferences=[rdi] Interval 26: ref RefPositions {#73@72 #77@73} physReg:NA Preferences=[rdi] Interval 27: ref RefPositions {#88@74 #89@75} physReg:NA Preferences=[rax] RelatedInterval Interval 28: ref RefPositions {#94@80 #101@85} physReg:NA Preferences=[rsi] Interval 29: int (constant) RefPositions {#95@82 #97@83} physReg:NA Preferences=[rdi] Interval 30: int RefPositions {#99@84 #103@85} physReg:NA Preferences=[rdi] Interval 31: long (constant) RefPositions {#113@90 #114@91} physReg:NA Preferences=[allInt] Interval 32: ref RefPositions {#115@92 #116@93} physReg:NA Preferences=[allInt] RelatedInterval Interval 33: int RefPositions {#119@102 #120@103} physReg:NA Preferences=[allInt] RelatedInterval Interval 34: ref RefPositions {#126@126 #127@127} physReg:NA Preferences=[allInt] RelatedInterval Interval 35: long RefPositions {#132@144 #134@147} physReg:NA Preferences=[allInt] Interval 36: ref RefPositions {#135@148 #136@149} physReg:NA Preferences=[allInt] RelatedInterval Interval 37: byref RefPositions {#139@156 #146@159} physReg:NA Preferences=[allInt] Interval 38: int (INTERNAL) RefPositions {#141@159 #147@159} physReg:NA Preferences=[rdi] Interval 39: int (INTERNAL) RefPositions {#143@159 #148@159} physReg:NA Preferences=[rcx] Interval 40: int (INTERNAL) RefPositions {#145@159 #149@159} physReg:NA Preferences=[rsi] Interval 41: ref RefPositions {#153@164 #178@187} physReg:NA Preferences=[rdi] Interval 42: long RefPositions {#154@166 #156@167} physReg:NA Preferences=[rdx] Interval 43: long RefPositions {#158@168 #180@187} physReg:NA Preferences=[rdx] Interval 44: long RefPositions {#159@170 #161@171} physReg:NA Preferences=[rcx] Interval 45: long RefPositions {#163@172 #182@187} physReg:NA Preferences=[rcx] Interval 46: long (constant) RefPositions {#165@176 #167@177} physReg:NA Preferences=[r11] Interval 47: long RefPositions {#169@178 #184@187} physReg:NA Preferences=[r11] Interval 48: long (def-use conflict) (constant) RefPositions {#171@180 #173@181} physReg:NA Preferences=[rsi r11] Interval 49: long RefPositions {#175@182 #186@187} physReg:NA Preferences=[rsi] Interval 50: long (constant) RefPositions {#176@184 #187@187} physReg:NA Preferences=[allInt] Interval 51: long RefPositions {#198@188 #201@189} physReg:NA Preferences=[rax] Interval 52: long RefPositions {#200@188 #202@189} physReg:NA Preferences=[rdx] *************** In LinearScan::allocateRegisters() Linear scan intervals before allocateRegisters: Interval 0: (V00) byref RefPositions {#0@0 #118@101 #138@155} physReg:rdi Preferences=[rbx r12-r15] RelatedInterval Interval 1: (V03) ref RefPositions {#21@12 #23@19 #48@39} physReg:NA Preferences=[rbx r12-r15] RelatedInterval Interval 2: (V04) ref RefPositions {#44@28 #46@35 #50@43} physReg:NA Preferences=[allInt] RelatedInterval Interval 3: (V10) ref RefPositions {#90@76 #92@79} physReg:NA Preferences=[rsi] Interval 4: (V11) int RefPositions {#121@104 #122@115 #129@137 #131@143} physReg:NA Preferences=[allInt] Interval 5: (V12) ref RefPositions {#117@94 #123@115 #125@125} physReg:NA Preferences=[allInt] Interval 6: (V13) ref (field) RefPositions {#49@40 #58@61} physReg:NA Preferences=[allInt] Interval 7: (V14) ref (field) RefPositions {#51@44 #59@61} physReg:NA Preferences=[allInt] Interval 8: (V16) ref (field) RefPositions {#56@50 #61@61} physReg:NA Preferences=[allInt] Interval 9: (V18) ref RefPositions {#128@128 #130@137 #133@147} physReg:NA Preferences=[allInt] Interval 10: (V19) ref RefPositions {#137@150 #151@163} physReg:NA Preferences=[rdi] Interval 11: long (constant) RefPositions {#2@6 #4@7} physReg:NA Preferences=[rdi] Interval 12: long RefPositions {#6@8 #8@9} physReg:NA Preferences=[rdi] Interval 13: ref RefPositions {#19@10 #20@11} physReg:NA Preferences=[rax] RelatedInterval Interval 14: long RefPositions {#22@18 #24@19} physReg:NA Preferences=[allInt] Interval 15: long (constant) RefPositions {#25@22 #27@23} physReg:NA Preferences=[rdi] Interval 16: long RefPositions {#29@24 #31@25} physReg:NA Preferences=[rdi] Interval 17: ref RefPositions {#42@26 #43@27} physReg:NA Preferences=[rax] RelatedInterval Interval 18: int RefPositions {#45@34 #47@35} physReg:NA Preferences=[allInt] Interval 19: long (constant) RefPositions {#52@46 #53@47} physReg:NA Preferences=[allInt] Interval 20: ref RefPositions {#54@48 #55@49} physReg:NA Preferences=[allInt] RelatedInterval Interval 21: ref (constant) RefPositions {#57@56 #60@61} physReg:NA Preferences=[allInt] Interval 22: long (constant) RefPositions {#62@64 #63@65} physReg:NA Preferences=[allInt] Interval 23: ref RefPositions {#64@66 #66@67} physReg:NA Preferences=[rsi] Interval 24: ref RefPositions {#68@68 #75@73} physReg:NA Preferences=[rsi] Interval 25: ref (constant) RefPositions {#69@70 #71@71} physReg:NA Preferences=[rdi] Interval 26: ref RefPositions {#73@72 #77@73} physReg:NA Preferences=[rdi] Interval 27: ref RefPositions {#88@74 #89@75} physReg:NA Preferences=[rax] RelatedInterval Interval 28: ref RefPositions {#94@80 #101@85} physReg:NA Preferences=[rsi] Interval 29: int (constant) RefPositions {#95@82 #97@83} physReg:NA Preferences=[rdi] Interval 30: int RefPositions {#99@84 #103@85} physReg:NA Preferences=[rdi] Interval 31: long (constant) RefPositions {#113@90 #114@91} physReg:NA Preferences=[allInt] Interval 32: ref RefPositions {#115@92 #116@93} physReg:NA Preferences=[allInt] RelatedInterval Interval 33: int RefPositions {#119@102 #120@103} physReg:NA Preferences=[allInt] RelatedInterval Interval 34: ref RefPositions {#126@126 #127@127} physReg:NA Preferences=[allInt] RelatedInterval Interval 35: long RefPositions {#132@144 #134@147} physReg:NA Preferences=[allInt] Interval 36: ref RefPositions {#135@148 #136@149} physReg:NA Preferences=[allInt] RelatedInterval Interval 37: byref RefPositions {#139@156 #146@159} physReg:NA Preferences=[allInt] Interval 38: int (INTERNAL) RefPositions {#141@159 #147@159} physReg:NA Preferences=[rdi] Interval 39: int (INTERNAL) RefPositions {#143@159 #148@159} physReg:NA Preferences=[rcx] Interval 40: int (INTERNAL) RefPositions {#145@159 #149@159} physReg:NA Preferences=[rsi] Interval 41: ref RefPositions {#153@164 #178@187} physReg:NA Preferences=[rdi] Interval 42: long RefPositions {#154@166 #156@167} physReg:NA Preferences=[rdx] Interval 43: long RefPositions {#158@168 #180@187} physReg:NA Preferences=[rdx] Interval 44: long RefPositions {#159@170 #161@171} physReg:NA Preferences=[rcx] Interval 45: long RefPositions {#163@172 #182@187} physReg:NA Preferences=[rcx] Interval 46: long (constant) RefPositions {#165@176 #167@177} physReg:NA Preferences=[r11] Interval 47: long RefPositions {#169@178 #184@187} physReg:NA Preferences=[r11] Interval 48: long (def-use conflict) (constant) RefPositions {#171@180 #173@181} physReg:NA Preferences=[rsi r11] Interval 49: long RefPositions {#175@182 #186@187} physReg:NA Preferences=[rsi] Interval 50: long (constant) RefPositions {#176@184 #187@187} physReg:NA Preferences=[allInt] Interval 51: long RefPositions {#198@188 #201@189} physReg:NA Preferences=[rax] Interval 52: long RefPositions {#200@188 #202@189} physReg:NA Preferences=[rdx] ------------ REFPOSITIONS BEFORE ALLOCATION: ------------ BB00 regmask=[rdi] minReg=1 fixed regOptional> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_FLD BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_FLD BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> IND BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> CNS_INT BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1 last> BB01 regmask=[allInt] minReg=1 last> LCL_VAR BB01 regmask=[allInt] minReg=1 last> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> IND BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> BB01 regmask=[rsi] minReg=1> LCL_VAR BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> CNS_INT BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> IND BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> IND BB01 regmask=[allInt] minReg=1> BB01 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1 last> IND BB02 regmask=[allInt] minReg=1> BB02 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1 last> CAST BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1 last> BB02 regmask=[allInt] minReg=1 last> IND BB02 regmask=[allInt] minReg=1> BB02 regmask=[allInt] minReg=1 last> STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1 last> ADD BB02 regmask=[allInt] minReg=1> BB02 regmask=[rdi] minReg=1> PUTARG_STK BB02 regmask=[rdi] minReg=1 fixed> BB02 regmask=[rcx] minReg=1> PUTARG_STK BB02 regmask=[rcx] minReg=1 fixed> BB02 regmask=[rsi] minReg=1> PUTARG_STK BB02 regmask=[rsi] minReg=1 fixed> BB02 regmask=[allInt] minReg=1 last> PUTARG_STK BB02 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB02 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB02 regmask=[rsi] minReg=1 last fixed> BB02 regmask=[rdi] minReg=1> LCL_VAR BB02 regmask=[rdi] minReg=1 last fixed> BB02 regmask=[rdi] minReg=1> PUTARG_REG BB02 regmask=[rdi] minReg=1 fixed> LCL_FLD BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> BB02 regmask=[rdx] minReg=1> PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed> LCL_FLD BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> BB02 regmask=[rcx] minReg=1> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed> BB02 regmask=[r11] minReg=1> CNS_INT BB02 regmask=[r11] minReg=1 fixed> BB02 regmask=[r11] minReg=1> BB02 regmask=[r11] minReg=1 last fixed> BB02 regmask=[r11] minReg=1> PUTARG_REG BB02 regmask=[r11] minReg=1 fixed> BB02 regmask=[r11] minReg=1> CNS_INT BB02 regmask=[r11] minReg=1 fixed> BB02 regmask=[rsi] minReg=1> BB02 regmask=[rsi] minReg=1 last fixed> BB02 regmask=[rsi] minReg=1> PUTARG_REG BB02 regmask=[rsi] minReg=1 fixed> CNS_INT BB02 regmask=[allInt] minReg=1> BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last fixed> BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> BB02 regmask=[r11] minReg=1> BB02 regmask=[r11] minReg=1 last fixed> BB02 regmask=[rsi] minReg=1> BB02 regmask=[rsi] minReg=1 last fixed> BB02 regmask=[allInt] minReg=1 last> BB02 regmask=[rax] minReg=1 last> BB02 regmask=[rcx] minReg=1 last> BB02 regmask=[rdx] minReg=1 last> BB02 regmask=[rsi] minReg=1 last> BB02 regmask=[rdi] minReg=1 last> BB02 regmask=[r8] minReg=1 last> BB02 regmask=[r9] minReg=1 last> BB02 regmask=[r10] minReg=1 last> BB02 regmask=[r11] minReg=1 last> BB02 regmask=[rax] minReg=1> CALL[0] BB02 regmask=[rax] minReg=1 fixed> BB02 regmask=[rdx] minReg=1> CALL[1] BB02 regmask=[rdx] minReg=1 fixed> BB02 regmask=[allInt] minReg=1 last> BB02 regmask=[allInt] minReg=1 last> BB03 regmask=[rax] minReg=1 last> BB03 regmask=[rcx] minReg=1 last> BB03 regmask=[rdx] minReg=1 last> BB03 regmask=[rsi] minReg=1 last> BB03 regmask=[rdi] minReg=1 last> BB03 regmask=[r8] minReg=1 last> BB03 regmask=[r9] minReg=1 last> BB03 regmask=[r10] minReg=1 last> BB03 regmask=[r11] minReg=1 last> BB04 regmask=[rax] minReg=1 last> BB04 regmask=[rcx] minReg=1 last> BB04 regmask=[rdx] minReg=1 last> BB04 regmask=[rsi] minReg=1 last> BB04 regmask=[rdi] minReg=1 last> BB04 regmask=[r8] minReg=1 last> BB04 regmask=[r9] minReg=1 last> BB04 regmask=[r10] minReg=1 last> BB04 regmask=[r11] minReg=1 last> VAR REFPOSITIONS BEFORE ALLOCATION --- V00 (Interval 0) BB00 regmask=[rdi] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1 last> --- V01 --- V02 --- V03 (Interval 1) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> --- V04 (Interval 2) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> --- V05 --- V06 --- V07 --- V08 --- V09 --- V10 (Interval 3) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[rsi] minReg=1 last fixed> --- V11 (Interval 4) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1 last> --- V12 (Interval 5) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1 last> --- V13 (Interval 6) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> --- V14 (Interval 7) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> --- V15 --- V16 (Interval 8) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1> LCL_VAR BB01 regmask=[allInt] minReg=1 last> --- V17 --- V18 (Interval 9) STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[allInt] minReg=1 last> --- V19 (Interval 10) STORE_LCL_VAR BB02 regmask=[allInt] minReg=1> LCL_VAR BB02 regmask=[rdi] minReg=1 last fixed> Allocating Registers -------------------- The following table has one or more rows for each RefPosition that is handled during allocation. The first column provides the basic information about the RefPosition, with its type (e.g. Def, Use, Fixd) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, and then the action taken during allocation (e.g. Alloc a new register, or Keep an existing one). The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is active, a 'p' if it is a large vector that has been partially spilled, and 'i'if it is inactive. Columns are only printed up to the last modifed register, which may increase during allocation, in which case additional columns will appear. Registers which are not marked modified have ---- in their column. --------------------------------+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 | --------------------------------+----+----+----+----+----+----+----+----+----+----+ | | | | | |V0 a| | | | | 0.#0 V0 Parm Alloc rbx | | | |V0 a| | | | | | | 1.#1 BB1 PredBB0 | | | |V0 a| | | | | | | 6.#2 C11 Def Alloc rdi | | | |V0 a| |C11a| | | | | 7.#3 rdi Fixd Keep rdi | | | |V0 a| |C11a| | | | | 7.#4 C11 Use * Keep rdi | | | |V0 a| |C11a| | | | | 8.#5 rdi Fixd Keep rdi | | | |V0 a| | | | | | | 8.#6 I12 Def Alloc rdi | | | |V0 a| |I12a| | | | | 9.#7 rdi Fixd Keep rdi | | | |V0 a| |I12a| | | | | 9.#8 I12 Use * Keep rdi | | | |V0 a| |I12a| | | | | 10.#9 rax Kill Keep rax | | | |V0 a| | | | | | | 10.#10 rcx Kill Keep rcx | | | |V0 a| | | | | | | 10.#11 rdx Kill Keep rdx | | | |V0 a| | | | | | | 10.#12 rsi Kill Keep rsi | | | |V0 a| | | | | | | 10.#13 rdi Kill Keep rdi | | | |V0 a| | | | | | | 10.#14 r8 Kill Keep r8 | | | |V0 a| | | | | | | 10.#15 r9 Kill Keep r9 | | | |V0 a| | | | | | | 10.#16 r10 Kill Keep r10 | | | |V0 a| | | | | | | 10.#17 r11 Kill Keep r11 | | | |V0 a| | | | | | | 10.#18 rax Fixd Keep rax | | | |V0 a| | | | | | | 10.#19 I13 Def Alloc rax |I13a| | |V0 a| | | | | | | 11.#20 I13 Use * Keep rax |I13a| | |V0 a| | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 12.#21 V3 Def Alloc r14 | | | |V0 a| | | | | | |V3 a| 18.#22 I14 Def Alloc rdi | | | |V0 a| |I14a| | | | |V3 a| 19.#23 V3 Use Keep r14 | | | |V0 a| |I14a| | | | |V3 a| 19.#24 I14 Use * Keep rdi | | | |V0 a| |I14a| | | | |V3 a| 22.#25 C15 Def Alloc rdi | | | |V0 a| |C15a| | | | |V3 a| 23.#26 rdi Fixd Keep rdi | | | |V0 a| |C15a| | | | |V3 a| 23.#27 C15 Use * Keep rdi | | | |V0 a| |C15a| | | | |V3 a| 24.#28 rdi Fixd Keep rdi | | | |V0 a| | | | | | |V3 a| 24.#29 I16 Def Alloc rdi | | | |V0 a| |I16a| | | | |V3 a| 25.#30 rdi Fixd Keep rdi | | | |V0 a| |I16a| | | | |V3 a| 25.#31 I16 Use * Keep rdi | | | |V0 a| |I16a| | | | |V3 a| 26.#32 rax Kill Keep rax | | | |V0 a| | | | | | |V3 a| 26.#33 rcx Kill Keep rcx | | | |V0 a| | | | | | |V3 a| 26.#34 rdx Kill Keep rdx | | | |V0 a| | | | | | |V3 a| 26.#35 rsi Kill Keep rsi | | | |V0 a| | | | | | |V3 a| 26.#36 rdi Kill Keep rdi | | | |V0 a| | | | | | |V3 a| 26.#37 r8 Kill Keep r8 | | | |V0 a| | | | | | |V3 a| 26.#38 r9 Kill Keep r9 | | | |V0 a| | | | | | |V3 a| 26.#39 r10 Kill Keep r10 | | | |V0 a| | | | | | |V3 a| 26.#40 r11 Kill Keep r11 | | | |V0 a| | | | | | |V3 a| 26.#41 rax Fixd Keep rax | | | |V0 a| | | | | | |V3 a| 26.#42 I17 Def Alloc rax |I17a| | |V0 a| | | | | | |V3 a| 27.#43 I17 Use * Keep rax |I17a| | |V0 a| | | | | | |V3 a| 28.#44 V4 Def Alloc rax |V4 a| | |V0 a| | | | | | |V3 a| 34.#45 I18 Def Alloc rsi |V4 a| | |V0 a|I18a| | | | | |V3 a| 35.#46 V4 Use Keep rax |V4 a| | |V0 a|I18a| | | | | |V3 a| 35.#47 I18 Use * Keep rsi |V4 a| | |V0 a|I18a| | | | | |V3 a| 39.#48 V3 Use * Keep r14 |V4 a| | |V0 a| | | | | | |V3 a| 40.#49 V13 Def Alloc r14 |V4 a| | |V0 a| | | | | | |V13a| 43.#50 V4 Use * Keep rax |V4 a| | |V0 a| | | | | | |V13a| 44.#51 V14 Def Alloc rax |V14a| | |V0 a| | | | | | |V13a| 46.#52 C19 Def Alloc rsi |V14a| | |V0 a|C19a| | | | | |V13a| 47.#53 C19 Use * Keep rsi |V14a| | |V0 a|C19a| | | | | |V13a| 48.#54 I20 Def Alloc rsi |V14a| | |V0 a|I20a| | | | | |V13a| 49.#55 I20 Use * Keep rsi |V14a| | |V0 a|I20a| | | | | |V13a| 50.#56 V16 Def Alloc rsi |V14a| | |V0 a|V16a| | | | | |V13a| 56.#57 C21 Def Alloc rdi |V14a| | |V0 a|V16a|C21a| | | | |V13a| 61.#58 V13 Use * Keep r14 |V14a| | |V0 a|V16a|C21a| | | | |V13a| 61.#59 V14 Use * Keep rax |V14a| | |V0 a|V16a|C21a| | | | |V13a| 61.#60 C21 Use * Keep rdi |V14a| | |V0 a|V16a|C21a| | | | |V13a| 61.#61 V16 Use * Keep rsi |V14a| | |V0 a|V16a|C21a| | | | |V13a| 64.#62 C22 Def Alloc rsi | | | |V0 a|C22a|C21i| | | | | | 65.#63 C22 Use * Keep rsi | | | |V0 a|C22a|C21i| | | | | | 66.#64 I23 Def Alloc rsi | | | |V0 a|I23a|C21i| | | | | | 67.#65 rsi Fixd Keep rsi | | | |V0 a|I23a|C21i| | | | | | 67.#66 I23 Use * Keep rsi | | | |V0 a|I23a|C21i| | | | | | 68.#67 rsi Fixd Keep rsi | | | |V0 a| |C21i| | | | | | 68.#68 I24 Def Alloc rsi | | | |V0 a|I24a|C21i| | | | | | 70.#69 C25 Def Reuse rdi | | | |V0 a|I24a|C25a| | | | | | 71.#70 rdi Fixd Keep rdi | | | |V0 a|I24a|C25a| | | | | | 71.#71 C25 Use * Keep rdi | | | |V0 a|I24a|C25a| | | | | | 72.#72 rdi Fixd Keep rdi | | | |V0 a|I24a| | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 72.#73 I26 Def Alloc rdi | | | |V0 a|I24a|I26a| | | | | | 73.#74 rsi Fixd Keep rsi | | | |V0 a|I24a|I26a| | | | | | 73.#75 I24 Use * Keep rsi | | | |V0 a|I24a|I26a| | | | | | 73.#76 rdi Fixd Keep rdi | | | |V0 a|I24a|I26a| | | | | | 73.#77 I26 Use * Keep rdi | | | |V0 a|I24a|I26a| | | | | | 74.#78 rax Kill Keep rax | | | |V0 a| | | | | | | | 74.#79 rcx Kill Keep rcx | | | |V0 a| | | | | | | | 74.#80 rdx Kill Keep rdx | | | |V0 a| | | | | | | | 74.#81 rsi Kill Keep rsi | | | |V0 a| | | | | | | | 74.#82 rdi Kill Keep rdi | | | |V0 a| | | | | | | | 74.#83 r8 Kill Keep r8 | | | |V0 a| | | | | | | | 74.#84 r9 Kill Keep r9 | | | |V0 a| | | | | | | | 74.#85 r10 Kill Keep r10 | | | |V0 a| | | | | | | | 74.#86 r11 Kill Keep r11 | | | |V0 a| | | | | | | | 74.#87 rax Fixd Keep rax | | | |V0 a| | | | | | | | 74.#88 I27 Def Alloc rax |I27a| | |V0 a| | | | | | | | 75.#89 I27 Use * Keep rax |I27a| | |V0 a| | | | | | | | 76.#90 V10 Def Alloc rsi | | | |V0 a|V10a| | | | | | | 79.#91 rsi Fixd Keep rsi | | | |V0 a|V10a| | | | | | | 79.#92 V10 Use * Keep rsi | | | |V0 a|V10a| | | | | | | 80.#93 rsi Fixd Keep rsi | | | |V0 a| | | | | | | | 80.#94 I28 Def Alloc rsi | | | |V0 a|I28a| | | | | | | 82.#95 C29 Def Alloc rdi | | | |V0 a|I28a|C29a| | | | | | 83.#96 rdi Fixd Keep rdi | | | |V0 a|I28a|C29a| | | | | | 83.#97 C29 Use * Keep rdi | | | |V0 a|I28a|C29a| | | | | | 84.#98 rdi Fixd Keep rdi | | | |V0 a|I28a| | | | | | | 84.#99 I30 Def Alloc rdi | | | |V0 a|I28a|I30a| | | | | | 85.#100 rsi Fixd Keep rsi | | | |V0 a|I28a|I30a| | | | | | 85.#101 I28 Use * Keep rsi | | | |V0 a|I28a|I30a| | | | | | 85.#102 rdi Fixd Keep rdi | | | |V0 a|I28a|I30a| | | | | | 85.#103 I30 Use * Keep rdi | | | |V0 a|I28a|I30a| | | | | | 86.#104 rax Kill Keep rax | | | |V0 a| | | | | | | | 86.#105 rcx Kill Keep rcx | | | |V0 a| | | | | | | | 86.#106 rdx Kill Keep rdx | | | |V0 a| | | | | | | | 86.#107 rsi Kill Keep rsi | | | |V0 a| | | | | | | | 86.#108 rdi Kill Keep rdi | | | |V0 a| | | | | | | | 86.#109 r8 Kill Keep r8 | | | |V0 a| | | | | | | | 86.#110 r9 Kill Keep r9 | | | |V0 a| | | | | | | | 86.#111 r10 Kill Keep r10 | | | |V0 a| | | | | | | | 86.#112 r11 Kill Keep r11 | | | |V0 a| | | | | | | | 90.#113 C31 Def Alloc rdi | | | |V0 a| |C31a| | | | | | 91.#114 C31 Use * Keep rdi | | | |V0 a| |C31a| | | | | | 92.#115 I32 Def Alloc rdi | | | |V0 a| |I32a| | | | | | 93.#116 I32 Use * Keep rdi | | | |V0 a| |I32a| | | | | | 94.#117 V12 Def Alloc rdi | | | |V0 a| |V12a| | | | | | 101.#118 V0 Use Keep rbx | | | |V0 a| |V12a| | | | | | 102.#119 I33 Def Alloc rsi | | | |V0 a|I33a|V12a| | | | | | 103.#120 I33 Use * Keep rsi | | | |V0 a|I33a|V12a| | | | | | 104.#121 V11 Def Alloc rsi | | | |V0 a|V11a|V12a| | | | | | 115.#122 V11 Use Keep rsi | | | |V0 a|V11a|V12a| | | | | | 115.#123 V12 Use Keep rdi | | | |V0 a|V11a|V12a| | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r12 |r13 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+ 119.#124 BB2 PredBB1 | | | |V0 a|V11a|V12a| | | | | | 125.#125 V12 Use * Keep rdi | | | |V0 a|V11a|V12a| | | | | | 126.#126 I34 Def Alloc rdi | | | |V0 a|V11a|I34a| | | | | | 127.#127 I34 Use * Keep rdi | | | |V0 a|V11a|I34a| | | | | | 128.#128 V18 Def Alloc rdi | | | |V0 a|V11a|V18a| | | | | | 137.#129 V11 Use Keep rsi | | | |V0 a|V11a|V18a| | | | | | 137.#130 V18 Use Keep rdi | | | |V0 a|V11a|V18a| | | | | | 143.#131 V11 Use * Keep rsi | | | |V0 a|V11a|V18a| | | | | | 144.#132 I35 Def Alloc rsi | | | |V0 a|I35a|V18a| | | | | | 147.#133 V18 Use * Keep rdi | | | |V0 a|I35a|V18a| | | | | | 147.#134 I35 Use * Keep rsi | | | |V0 a|I35a|V18a| | | | | | 148.#135 I36 Def Alloc rdi | | | |V0 a| |I36a| | | | | | 149.#136 I36 Use * Keep rdi | | | |V0 a| |I36a| | | | | | 150.#137 V19 Def Alloc rdi | | | |V0 a| |V19a| | | | | | 155.#138 V0 Use * Keep rbx | | | |V0 a| |V19a| | | | | | 156.#139 I37 Def Alloc rbx | | | |I37a| |V19a| | | | | | 159.#140 rdi Fixd Keep rdi | | | |I37a| |V19a| | | | | | 159.#141 I38 Def Spill rdi | | | |I37a| | | | | | | | Steal rdi | | | |I37a| |I38a| | | | | | 159.#142 rcx Fixd Keep rcx | | | |I37a| |I38a| | | | | | 159.#143 I39 Def Alloc rcx | |I39a| |I37a| |I38a| | | | | | 159.#144 rsi Fixd Keep rsi | |I39a| |I37a| |I38a| | | | | | 159.#145 I40 Def Alloc rsi | |I39a| |I37a|I40a|I38a| | | | | | 159.#146 I37 Use * Keep rbx | |I39a| |I37a|I40a|I38a| | | | | | 159.#147 I38 Use * Keep rdi | |I39a| |I37a|I40a|I38a| | | | | | 159.#148 I39 Use * Keep rcx | |I39a| |I37a|I40a|I38a| | | | | | 159.#149 I40 Use * Keep rsi | |I39a| |I37a|I40a|I38a| | | | | | 163.#150 rdi Fixd Keep rdi | | | | | | | | | | | | 163.#151 V19 Use * ReLod NA | | | | | | | | | | | | Alloc rdi | | | | | |V19a| | | | | | 164.#152 rdi Fixd Keep rdi | | | | | | | | | | | | 164.#153 I41 Def Alloc rdi | | | | | |I41a| | | | | | 166.#154 I42 Def Alloc rdx | | |I42a| | |I41a| | | | | | 167.#155 rdx Fixd Keep rdx | | |I42a| | |I41a| | | | | | 167.#156 I42 Use * Keep rdx | | |I42a| | |I41a| | | | | | 168.#157 rdx Fixd Keep rdx | | | | | |I41a| | | | | | 168.#158 I43 Def Alloc rdx | | |I43a| | |I41a| | | | | | 170.#159 I44 Def Alloc rcx | |I44a|I43a| | |I41a| | | | | | 171.#160 rcx Fixd Keep rcx | |I44a|I43a| | |I41a| | | | | | 171.#161 I44 Use * Keep rcx | |I44a|I43a| | |I41a| | | | | | 172.#162 rcx Fixd Keep rcx | | |I43a| | |I41a| | | | | | 172.#163 I45 Def Alloc rcx | |I45a|I43a| | |I41a| | | | | | 176.#164 r11 Fixd Keep r11 | |I45a|I43a| | |I41a| | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ 176.#165 C46 Def Alloc r11 | |I45a|I43a| | |I41a| | |C46a| | | | 177.#166 r11 Fixd Keep r11 | |I45a|I43a| | |I41a| | |C46a| | | | 177.#167 C46 Use * Keep r11 | |I45a|I43a| | |I41a| | |C46a| | | | 178.#168 r11 Fixd Keep r11 | |I45a|I43a| | |I41a| | | | | | | 178.#169 I47 Def Alloc r11 | |I45a|I43a| | |I41a| | |I47a| | | | 180.#170 r11 Fixd Keep r11 | |I45a|I43a| | |I41a| | |I47a| | | | 180.#171 C48 Def DUconflict | |I45a|I43a| | |I41a| | |I47a| | | | Case #6 need a copy | |I45a|I43a| | |I41a| | |I47a| | | | Spill r11 | |I45a|I43a| | |I41a| | | | | | | Steal r11 | |I45a|I43a| | |I41a| | |C48a| | | | 181.#172 rsi Fixd Keep rsi | |I45a|I43a| | |I41a| | |C48a| | | | 181.#173 C48 Use * Copy rsi | |I45a|I43a| |C48a|I41a| | |C48a| | | | 182.#174 rsi Fixd Keep rsi | |I45a|I43a| | |I41a| | |C48i| | | | 182.#175 I49 Def Alloc rsi | |I45a|I43a| |I49a|I41a| | |C48i| | | | 184.#176 C50 Def Alloc rax |C50a|I45a|I43a| |I49a|I41a| | |C48i| | | | 187.#177 rdi Fixd Keep rdi |C50a|I45a|I43a| |I49a|I41a| | |C48i| | | | 187.#178 I41 Use * Keep rdi |C50a|I45a|I43a| |I49a|I41a| | |C48i| | | | 187.#179 rdx Fixd Keep rdx |C50a|I45a|I43a| |I49a|I41a| | |C48i| | | | 187.#180 I43 Use * Keep rdx |C50a|I45a|I43a| |I49a|I41a| | |C48i| | | | 187.#181 rcx Fixd Keep rcx |C50a|I45a|I43a| |I49a|I41a| | |C48i| | | | 187.#182 I45 Use * Keep rcx |C50a|I45a|I43a| |I49a|I41a| | |C48i| | | | 187.#183 r11 Fixd Keep r11 |C50a|I45a|I43a| |I49a|I41a| | | | | | | 187.#184 I47 Use * ReLod NA |C50a|I45a|I43a| |I49a|I41a| | | | | | | Alloc r11 |C50a|I45a|I43a| |I49a|I41a| | |I47a| | | | 187.#185 rsi Fixd Keep rsi |C50a|I45a|I43a| |I49a|I41a| | |I47a| | | | 187.#186 I49 Use * Keep rsi |C50a|I45a|I43a| |I49a|I41a| | |I47a| | | | 187.#187 C50 Use * Keep rax |C50a|I45a|I43a| |I49a|I41a| | |I47a| | | | 188.#188 rax Kill Keep rax | | | | | | | | | | | | | 188.#189 rcx Kill Keep rcx | | | | | | | | | | | | | 188.#190 rdx Kill Keep rdx | | | | | | | | | | | | | 188.#191 rsi Kill Keep rsi | | | | | | | | | | | | | 188.#192 rdi Kill Keep rdi | | | | | | | | | | | | | 188.#193 r8 Kill Keep r8 | | | | | | | | | | | | | 188.#194 r9 Kill Keep r9 | | | | | | | | | | | | | 188.#195 r10 Kill Keep r10 | | | | | | | | | | | | | 188.#196 r11 Kill Keep r11 | | | | | | | | | | | | | 188.#197 rax Fixd Keep rax | | | | | | | | | | | | | 188.#198 I51 Def Alloc rax |I51a| | | | | | | | | | | | 188.#199 rdx Fixd Keep rdx |I51a| | | | | | | | | | | | 188.#200 I52 Def Alloc rdx |I51a| |I52a| | | | | | | | | | 189.#201 I51 Use * Keep rax |I51a| |I52a| | | | | | | | | | 189.#202 I52 Use * Keep rdx |I51a| |I52a| | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ 195.#203 BB3 PredBB1 | | | | | | | | | | | | | 200.#204 rax Kill Keep rax | | | | | | | | | | | | | 200.#205 rcx Kill Keep rcx | | | | | | | | | | | | | 200.#206 rdx Kill Keep rdx | | | | | | | | | | | | | 200.#207 rsi Kill Keep rsi | | | | | | | | | | | | | 200.#208 rdi Kill Keep rdi | | | | | | | | | | | | | 200.#209 r8 Kill Keep r8 | | | | | | | | | | | | | 200.#210 r9 Kill Keep r9 | | | | | | | | | | | | | 200.#211 r10 Kill Keep r10 | | | | | | | | | | | | | 200.#212 r11 Kill Keep r11 | | | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ 201.#213 BB4 PredBB3 | | | | | | | | | | | | | 204.#214 rax Kill Keep rax | | | | | | | | | | | | | 204.#215 rcx Kill Keep rcx | | | | | | | | | | | | | 204.#216 rdx Kill Keep rdx | | | | | | | | | | | | | 204.#217 rsi Kill Keep rsi | | | | | | | | | | | | | 204.#218 rdi Kill Keep rdi | | | | | | | | | | | | | 204.#219 r8 Kill Keep r8 | | | | | | | | | | | | | 204.#220 r9 Kill Keep r9 | | | | | | | | | | | | | 204.#221 r10 Kill Keep r10 | | | | | | | | | | | | | 204.#222 r11 Kill Keep r11 | | | | | | | | | | | | | ------------ REFPOSITIONS AFTER ALLOCATION: ------------ BB00 regmask=[rbx] minReg=1 fixed regOptional> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB01 regmask=[r14] minReg=1> LCL_FLD BB01 regmask=[rdi] minReg=1> LCL_VAR BB01 regmask=[r14] minReg=1> BB01 regmask=[rdi] minReg=1 last> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB01 regmask=[rax] minReg=1> LCL_FLD BB01 regmask=[rsi] minReg=1> LCL_VAR BB01 regmask=[rax] minReg=1> BB01 regmask=[rsi] minReg=1 last> LCL_VAR BB01 regmask=[r14] minReg=1 last> STORE_LCL_VAR BB01 regmask=[r14] minReg=1> LCL_VAR BB01 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB01 regmask=[rax] minReg=1> CNS_INT BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last> IND BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last> STORE_LCL_VAR BB01 regmask=[rsi] minReg=1> CNS_INT BB01 regmask=[rdi] minReg=1> LCL_VAR BB01 regmask=[r14] minReg=1 last> LCL_VAR BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> LCL_VAR BB01 regmask=[rsi] minReg=1 last> CNS_INT BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last> IND BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> BB01 regmask=[rax] minReg=1> CALL BB01 regmask=[rax] minReg=1 fixed> BB01 regmask=[rax] minReg=1 last> STORE_LCL_VAR BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1> LCL_VAR BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rsi] minReg=1> PUTARG_REG BB01 regmask=[rsi] minReg=1 fixed> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> PUTARG_REG BB01 regmask=[rdi] minReg=1 fixed> BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last fixed> BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last fixed> BB01 regmask=[rax] minReg=1 last> BB01 regmask=[rcx] minReg=1 last> BB01 regmask=[rdx] minReg=1 last> BB01 regmask=[rsi] minReg=1 last> BB01 regmask=[rdi] minReg=1 last> BB01 regmask=[r8] minReg=1 last> BB01 regmask=[r9] minReg=1 last> BB01 regmask=[r10] minReg=1 last> BB01 regmask=[r11] minReg=1 last> CNS_INT BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last> IND BB01 regmask=[rdi] minReg=1> BB01 regmask=[rdi] minReg=1 last> STORE_LCL_VAR BB01 regmask=[rdi] minReg=1> LCL_VAR BB01 regmask=[rbx] minReg=1> IND BB01 regmask=[rsi] minReg=1> BB01 regmask=[rsi] minReg=1 last> STORE_LCL_VAR BB01 regmask=[rsi] minReg=1> LCL_VAR BB01 regmask=[rsi] minReg=1> LCL_VAR BB01 regmask=[rdi] minReg=1> LCL_VAR BB02 regmask=[rdi] minReg=1 last> IND BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last> STORE_LCL_VAR BB02 regmask=[rdi] minReg=1> LCL_VAR BB02 regmask=[rsi] minReg=1> LCL_VAR BB02 regmask=[rdi] minReg=1> LCL_VAR BB02 regmask=[rsi] minReg=1 last> CAST BB02 regmask=[rsi] minReg=1> LCL_VAR BB02 regmask=[rdi] minReg=1 last> BB02 regmask=[rsi] minReg=1 last> IND BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last> STORE_LCL_VAR BB02 regmask=[rdi] minReg=1 spillAfter> LCL_VAR BB02 regmask=[rbx] minReg=1 last> ADD BB02 regmask=[rbx] minReg=1> BB02 regmask=[rdi] minReg=1> PUTARG_STK BB02 regmask=[rdi] minReg=1 fixed> BB02 regmask=[rcx] minReg=1> PUTARG_STK BB02 regmask=[rcx] minReg=1 fixed> BB02 regmask=[rsi] minReg=1> PUTARG_STK BB02 regmask=[rsi] minReg=1 fixed> BB02 regmask=[rbx] minReg=1 last> PUTARG_STK BB02 regmask=[rdi] minReg=1 last fixed> PUTARG_STK BB02 regmask=[rcx] minReg=1 last fixed> PUTARG_STK BB02 regmask=[rsi] minReg=1 last fixed> BB02 regmask=[rdi] minReg=1> LCL_VAR BB02 regmask=[rdi] minReg=1 last reload fixed> BB02 regmask=[rdi] minReg=1> PUTARG_REG BB02 regmask=[rdi] minReg=1 fixed> LCL_FLD BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> BB02 regmask=[rdx] minReg=1> PUTARG_REG BB02 regmask=[rdx] minReg=1 fixed> LCL_FLD BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> BB02 regmask=[rcx] minReg=1> PUTARG_REG BB02 regmask=[rcx] minReg=1 fixed> BB02 regmask=[r11] minReg=1> CNS_INT BB02 regmask=[r11] minReg=1 fixed> BB02 regmask=[r11] minReg=1> BB02 regmask=[r11] minReg=1 last fixed> BB02 regmask=[r11] minReg=1> PUTARG_REG BB02 regmask=[r11] minReg=1 spillAfter fixed> BB02 regmask=[r11] minReg=1> CNS_INT BB02 regmask=[r11] minReg=1 fixed> BB02 regmask=[rsi] minReg=1> BB02 regmask=[rsi] minReg=1 last move fixed> BB02 regmask=[rsi] minReg=1> PUTARG_REG BB02 regmask=[rsi] minReg=1 fixed> CNS_INT BB02 regmask=[rax] minReg=1> BB02 regmask=[rdi] minReg=1> BB02 regmask=[rdi] minReg=1 last fixed> BB02 regmask=[rdx] minReg=1> BB02 regmask=[rdx] minReg=1 last fixed> BB02 regmask=[rcx] minReg=1> BB02 regmask=[rcx] minReg=1 last fixed> BB02 regmask=[r11] minReg=1> BB02 regmask=[r11] minReg=1 last reload fixed> BB02 regmask=[rsi] minReg=1> BB02 regmask=[rsi] minReg=1 last fixed> BB02 regmask=[rax] minReg=1 last> BB02 regmask=[rax] minReg=1 last> BB02 regmask=[rcx] minReg=1 last> BB02 regmask=[rdx] minReg=1 last> BB02 regmask=[rsi] minReg=1 last> BB02 regmask=[rdi] minReg=1 last> BB02 regmask=[r8] minReg=1 last> BB02 regmask=[r9] minReg=1 last> BB02 regmask=[r10] minReg=1 last> BB02 regmask=[r11] minReg=1 last> BB02 regmask=[rax] minReg=1> CALL[0] BB02 regmask=[rax] minReg=1 fixed> BB02 regmask=[rdx] minReg=1> CALL[1] BB02 regmask=[rdx] minReg=1 fixed> BB02 regmask=[rax] minReg=1 last> BB02 regmask=[rdx] minReg=1 last> BB03 regmask=[rax] minReg=1 last> BB03 regmask=[rcx] minReg=1 last> BB03 regmask=[rdx] minReg=1 last> BB03 regmask=[rsi] minReg=1 last> BB03 regmask=[rdi] minReg=1 last> BB03 regmask=[r8] minReg=1 last> BB03 regmask=[r9] minReg=1 last> BB03 regmask=[r10] minReg=1 last> BB03 regmask=[r11] minReg=1 last> BB04 regmask=[rax] minReg=1 last> BB04 regmask=[rcx] minReg=1 last> BB04 regmask=[rdx] minReg=1 last> BB04 regmask=[rsi] minReg=1 last> BB04 regmask=[rdi] minReg=1 last> BB04 regmask=[r8] minReg=1 last> BB04 regmask=[r9] minReg=1 last> BB04 regmask=[r10] minReg=1 last> BB04 regmask=[r11] minReg=1 last> VAR REFPOSITIONS AFTER ALLOCATION --- V00 (Interval 0) BB00 regmask=[rbx] minReg=1 fixed regOptional> LCL_VAR BB01 regmask=[rbx] minReg=1> LCL_VAR BB02 regmask=[rbx] minReg=1 last> --- V01 --- V02 --- V03 (Interval 1) STORE_LCL_VAR BB01 regmask=[r14] minReg=1> LCL_VAR BB01 regmask=[r14] minReg=1> LCL_VAR BB01 regmask=[r14] minReg=1 last> --- V04 (Interval 2) STORE_LCL_VAR BB01 regmask=[rax] minReg=1> LCL_VAR BB01 regmask=[rax] minReg=1> LCL_VAR BB01 regmask=[rax] minReg=1 last> --- V05 --- V06 --- V07 --- V08 --- V09 --- V10 (Interval 3) STORE_LCL_VAR BB01 regmask=[rsi] minReg=1> LCL_VAR BB01 regmask=[rsi] minReg=1 last fixed> --- V11 (Interval 4) STORE_LCL_VAR BB01 regmask=[rsi] minReg=1> LCL_VAR BB01 regmask=[rsi] minReg=1> LCL_VAR BB02 regmask=[rsi] minReg=1> LCL_VAR BB02 regmask=[rsi] minReg=1 last> --- V12 (Interval 5) STORE_LCL_VAR BB01 regmask=[rdi] minReg=1> LCL_VAR BB01 regmask=[rdi] minReg=1> LCL_VAR BB02 regmask=[rdi] minReg=1 last> --- V13 (Interval 6) STORE_LCL_VAR BB01 regmask=[r14] minReg=1> LCL_VAR BB01 regmask=[r14] minReg=1 last> --- V14 (Interval 7) STORE_LCL_VAR BB01 regmask=[rax] minReg=1> LCL_VAR BB01 regmask=[rax] minReg=1 last> --- V15 --- V16 (Interval 8) STORE_LCL_VAR BB01 regmask=[rsi] minReg=1> LCL_VAR BB01 regmask=[rsi] minReg=1 last> --- V17 --- V18 (Interval 9) STORE_LCL_VAR BB02 regmask=[rdi] minReg=1> LCL_VAR BB02 regmask=[rdi] minReg=1> LCL_VAR BB02 regmask=[rdi] minReg=1 last> --- V19 (Interval 10) STORE_LCL_VAR BB02 regmask=[rdi] minReg=1 spillAfter> LCL_VAR BB02 regmask=[rdi] minReg=1 last reload fixed> Active intervals at end of allocation: Max spill for long is 1 Max spill for long is 1 ----------------------- RESOLVING BB BOUNDARIES ----------------------- Resolution Candidates: {V00 V11 V12} Has NoCritical Edges Prior to Resolution BB01 use def in out {V00 V01} {V03 V04 V10 V11 V12 V13 V14 V15 V16} {V00 V01} {V00 V01 V11 V12} Var=Reg beg of BB01: V00=rbx Var=Reg end of BB01: V11=rsi V00=rbx V12=rdi BB02 use def in out {V00 V01 V11 V12} {V17 V18 V19} {V00 V01 V11 V12} {} Var=Reg beg of BB02: V11=rsi V00=rbx V12=rdi Var=Reg end of BB02: none BB03 use def in out {} {} {} {} Var=Reg beg of BB03: none Var=Reg end of BB03: none BB04 use def in out {} {} {} {} Var=Reg beg of BB04: none Var=Reg end of BB04: none RESOLVING EDGES Set V00 argument initial register to rbx Trees after linear scan register allocator (LSRA) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj LIR BB02 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj LIR BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe LIR BB04 [0008] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..042) -> BB03 (cond), preds={} succs={BB02,BB03} N003 (???,???) [000155] ------------ IL_OFFSET void IL offset: 0x0 REG NA N005 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class REG rdi $180 /--* t4 long N007 (???,???) [000165] ------------ t165 = * PUTARG_REG long REG rdi /--* t165 long arg0 in rdi N009 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG rax $200 /--* t5 ref N011 ( 16, 16) [000007] DA---------- * STORE_LCL_VAR ref V03 tmp1 d:2 r14 REG r14 N013 ( 1, 1) [000008] ------------ t8 = LCL_VAR ref V03 tmp1 u:2 r14 REG r14 $200 /--* t8 ref N015 ( 2, 2) [000010] -c---------- t10 = * LEA(b+8) byref REG NA N017 ( 3, 4) [000003] ------------ t3 = LCL_FLD long V01 arg1 u:1[+0] Fseq[JobGroup] rdi REG rdi $2c0 /--* t10 byref +--* t3 long N019 (???,???) [000156] -A--GO------ * STOREIND long REG NA N021 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class REG rdi $182 /--* t18 long N023 (???,???) [000166] ------------ t166 = * PUTARG_REG long REG rdi /--* t166 long arg0 in rdi N025 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG rax $201 /--* t19 ref N027 ( 16, 16) [000021] DA---------- * STORE_LCL_VAR ref V04 tmp2 d:2 rax REG rax N029 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V04 tmp2 u:2 rax REG rax $201 /--* t22 ref N031 ( 2, 2) [000024] -c---------- t24 = * LEA(b+8) byref REG NA N033 ( 3, 4) [000017] ------------ t17 = LCL_FLD int V01 arg1 u:1[+8] Fseq[Version] rsi REG rsi $300 /--* t24 byref +--* t17 int N035 (???,???) [000157] -A--GO------ * STOREIND int REG NA N037 ( 1, 1) [000013] ------------ t13 = LCL_VAR ref V03 tmp1 u:2 r14 (last use) REG r14 $200 /--* t13 ref N039 ( 11, 8) [000063] DA---------- * STORE_LCL_VAR ref V13 tmp11 d:2 r14 REG r14 N041 ( 1, 1) [000027] ------------ t27 = LCL_VAR ref V04 tmp2 u:2 rax (last use) REG rax $201 /--* t27 ref N043 ( 11, 8) [000068] DA---------- * STORE_LCL_VAR ref V14 tmp12 d:2 rax REG rax N045 ( 2, 10) [000104] ------------ t104 = CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] REG rsi $184 /--* t104 long N047 ( 4, 12) [000076] n---G------- t76 = * IND ref REG rsi /--* t76 ref N049 ( 8, 15) [000078] DA--G------- * STORE_LCL_VAR ref V16 tmp14 d:2 rsi REG rsi N051 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V13 tmp11 u:2 r14 (last use) REG r14 $200 N053 ( 3, 2) [000111] ------------ t111 = LCL_VAR ref V14 tmp12 u:2 rax (last use) REG rax $201 N055 ( 1, 1) [000154] ------------ t154 = CNS_INT ref null REG rdi $VN.Null N057 ( 3, 2) [000113] ------------ t113 = LCL_VAR ref V16 tmp14 u:2 rsi (last use) REG rsi /--* t110 ref +--* t111 ref +--* t154 ref +--* t113 ref N059 ( 10, 7) [000109] -c---------- t109 = * FIELD_LIST struct REG NA $380 /--* t109 struct N061 (???,???) [000167] ------------ * PUTARG_STK [+0x00] void (4 slots) REG NA N063 ( 2, 10) [000105] ------------ t105 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] REG rsi $185 /--* t105 long N065 ( 4, 12) [000106] n---G------- t106 = * IND ref REG rsi /--* t106 ref N067 (???,???) [000168] ----G------- t168 = * PUTARG_REG ref REG rsi N069 ( 1, 1) [000046] ------------ t46 = CNS_INT ref null reuse reg val REG rdi $VN.Null /--* t46 ref N071 (???,???) [000169] ------------ t169 = * PUTARG_REG ref REG rdi /--* t168 ref arg1 in rsi +--* t169 ref arg0 in rdi N073 ( 32, 27) [000054] --CXG------- t54 = * CALL ref System.String.FormatHelper REG rax $1ce /--* t54 ref N075 ( 32, 27) [000085] DA-XG------- * STORE_LCL_VAR ref V10 tmp8 d:2 rsi REG rsi N077 ( 1, 1) [000082] ------------ t82 = LCL_VAR ref V10 tmp8 u:2 rsi (last use) REG rsi $1ce /--* t82 ref N079 (???,???) [000170] ------------ t170 = * PUTARG_REG ref REG rsi N081 ( 1, 1) [000081] ------------ t81 = CNS_INT int 3 REG rdi $44 /--* t81 int N083 (???,???) [000171] ------------ t171 = * PUTARG_REG int REG rdi /--* t170 ref arg1 in rsi +--* t171 int arg0 in rdi N085 ( 16, 9) [000083] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal REG NA $VN.Void N087 (???,???) [000158] ------------ IL_OFFSET void IL offset: 0x25 REG NA N089 ( 2, 10) [000116] ------------ t116 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] REG rdi $186 /--* t116 long N091 ( 4, 12) [000032] n---G------- t32 = * IND ref REG rdi /--* t32 ref N093 ( 4, 12) [000098] DA--G------- * STORE_LCL_VAR ref V12 tmp10 d:2 rdi REG rdi N095 (???,???) [000159] ------------ IL_OFFSET void IL offset: 0x25 REG NA N097 ( 1, 1) [000033] ------------ t33 = LCL_VAR byref V00 this u:1 rbx REG rbx $80 /--* t33 byref N099 ( 2, 2) [000118] -c---------- t118 = * LEA(b+16) byref REG NA /--* t118 byref N101 ( 4, 4) [000034] *--XG------- t34 = * IND int REG rsi /--* t34 int N103 ( 4, 4) [000100] DA-XG------- * STORE_LCL_VAR int V11 tmp9 d:2 rsi REG rsi N105 (???,???) [000160] ------------ IL_OFFSET void IL offset: 0x25 REG NA N107 ( 1, 1) [000087] ------------ t87 = LCL_VAR int V11 tmp9 u:2 rsi REG rsi N109 ( 1, 1) [000088] ------------ t88 = LCL_VAR ref V12 tmp10 u:2 rdi REG rdi /--* t88 ref N111 ( 2, 2) [000120] -c---------- t120 = * LEA(b+16) byref REG NA /--* t120 byref N113 ( 4, 4) [000089] -c-XG------- t89 = * IND int REG NA /--* t87 int +--* t89 int N115 ( 6, 6) [000090] N--XG--N-U-- * GE void REG NA N117 ( 8, 8) [000091] ---XG------- * JTRUE void REG NA ------------ BB02 [025..026) (return), preds={BB01} succs={} N121 ( 1, 1) [000092] ------------ t92 = LCL_VAR ref V12 tmp10 u:2 rdi (last use) REG rdi /--* t92 ref N123 ( 2, 2) [000141] -c---------- t141 = * LEA(b+8) byref REG NA /--* t141 byref N125 ( 4, 4) [000093] n---GO------ t93 = * IND ref REG rdi /--* t93 ref N127 ( 4, 4) [000126] DA--GO------ * STORE_LCL_VAR ref V18 tmp16 d:2 rdi REG rdi N129 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V11 tmp9 u:2 rsi REG rsi N131 ( 1, 1) [000127] ------------ t127 = LCL_VAR ref V18 tmp16 u:2 rdi REG rdi /--* t127 ref N133 (???,???) [000163] -c---------- t163 = * LEA(b+8) ref REG NA /--* t163 ref N135 ( 3, 3) [000130] -c-X-------- t130 = * IND int REG NA /--* t94 int +--* t130 int N137 ( 8, 11) [000131] ---X-------- * ARR_BOUNDS_CHECK_Rng void REG NA N139 ( 1, 1) [000128] ------------ t128 = LCL_VAR ref V18 tmp16 u:2 rdi (last use) REG rdi N141 ( 1, 1) [000129] ------------ t129 = LCL_VAR int V11 tmp9 u:2 rsi (last use) REG rsi /--* t129 int N143 ( 2, 3) [000132] ------------ t132 = * CAST long <- int REG rsi /--* t128 ref +--* t132 long N145 ( 5, 6) [000137] -c---------- t137 = * LEA(b+(i*8)+16) byref REG NA /--* t137 byref N147 ( 6, 7) [000095] a---G------- t95 = * IND ref REG rdi /--* t95 ref N149 ( 18, 22) [000145] DA-XGO----L- * STORE_LCL_VAR ref V19 tmp17 d:2 NA REG NA N151 ( 1, 1) [000037] ------------ t37 = LCL_VAR byref V00 this u:1 rbx (last use) REG rbx $80 N153 ( 1, 1) [000142] -c---------- t142 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] REG NA $245 /--* t37 byref +--* t142 long N155 ( 3, 3) [000143] ------------ t143 = * ADD byref REG rbx $289 /--* t143 byref N157 ( 9, 7) [000044] nc--GO------ t44 = * OBJ struct REG NA /--* t44 struct N159 (???,???) [000172] ----GO------ * PUTARG_STK [+0x00] void (7 slots) (RepInstr) REG NA N161 ( 1, 1) [000146] -----------z t146 = LCL_VAR ref V19 tmp17 u:2 rdi (last use) REG rdi /--* t146 ref N163 (???,???) [000173] ------------ t173 = * PUTARG_REG ref REG rdi N165 ( 3, 4) [000151] ------------ t151 = LCL_FLD long V01 arg1 u:1[+0] rdx REG rdx $144 /--* t151 long N167 (???,???) [000174] ------------ t174 = * PUTARG_REG long REG rdx N169 ( 3, 4) [000152] ------------ t152 = LCL_FLD long V01 arg1 u:1[+8] rcx (last use) REG rcx $145 /--* t152 long N171 (???,???) [000175] ------------ t175 = * PUTARG_REG long REG rcx /--* t174 long +--* t175 long N173 ( 6, 8) [000150] -c---------- t150 = * FIELD_LIST struct REG NA $384 N175 ( 2, 10) [000124] ------------ t124 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a /--* t124 long N177 (???,???) [000176] -----------Z t176 = * PUTARG_REG long REG r11 N179 ( 2, 10) [000121] ------------ t121 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a /--* t121 long [000180] ------------ t180 = * COPY long REG rsi /--* t180 long N181 (???,???) [000177] ------------ t177 = * PUTARG_REG long REG rsi N183 ( 2, 10) [000178] ------------ t178 = CNS_INT(h) long 0x7f6678060518 ftn REG rax /--* t178 long N185 ( 4, 12) [000179] -c---------- t179 = * IND long REG NA /--* t173 ref this in rdi +--* t150 struct arg4 rdx,rcx +--* t176 long arg1 in r11 +--* t177 long arg2 in rsi +--* t179 long control expr N187 ( 61, 70) [000040] --CXGO------ t40 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend REG rax,rdx $385 /--* t40 struct N189 ( 65, 73) [000123] DA-XGO------ * STORE_LCL_VAR struct V17 tmp15 d:2 NA REG NA N191 ( 3, 2) [000153] -c-----N---- t153 = LCL_VAR struct V17 tmp15 u:2 NA (last use) REG NA $388 /--* t153 struct N193 ( 4, 3) [000045] ----G------- * RETURN struct REG NA $389 ------------ BB03 [025..026) (throw), preds={BB01} succs={} N197 (???,???) [000161] ------------ IL_OFFSET void IL offset: 0x25 REG NA N199 ( 14, 5) [000096] --CXG------- CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException REG NA $VN.Void ------------ BB04 [???..???) (throw), preds={} succs={} N203 ( 14, 5) [000164] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL REG NA ------------------------------------------------------------------------------------------------------------------- Final allocation --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ 0.#0 V0 Parm Alloc rbx | | | |V0 a| | | | | | | | | 1.#1 BB1 PredBB0 | | | |V0 a| | | | | | | | | 6.#2 C11 Def Alloc rdi | | | |V0 a| |C11a| | | | | | | 7.#3 rdi Fixd Keep rdi | | | |V0 a| |C11a| | | | | | | 7.#4 C11 Use * Keep rdi | | | |V0 a| |C11i| | | | | | | 8.#5 rdi Fixd Keep rdi | | | |V0 a| | | | | | | | | 8.#6 I12 Def Alloc rdi | | | |V0 a| |I12a| | | | | | | 9.#7 rdi Fixd Keep rdi | | | |V0 a| |I12a| | | | | | | 9.#8 I12 Use * Keep rdi | | | |V0 a| |I12i| | | | | | | 10.#9 rax Kill Keep rax | | | |V0 a| | | | | | | | | 10.#10 rcx Kill Keep rcx | | | |V0 a| | | | | | | | | 10.#11 rdx Kill Keep rdx | | | |V0 a| | | | | | | | | 10.#12 rsi Kill Keep rsi | | | |V0 a| | | | | | | | | 10.#13 rdi Kill Keep rdi | | | |V0 a| | | | | | | | | 10.#14 r8 Kill Keep r8 | | | |V0 a| | | | | | | | | 10.#15 r9 Kill Keep r9 | | | |V0 a| | | | | | | | | 10.#16 r10 Kill Keep r10 | | | |V0 a| | | | | | | | | 10.#17 r11 Kill Keep r11 | | | |V0 a| | | | | | | | | 10.#18 rax Fixd Keep rax | | | |V0 a| | | | | | | | | 10.#19 I13 Def Alloc rax |I13a| | |V0 a| | | | | | | | | 11.#20 I13 Use * Keep rax |I13i| | |V0 a| | | | | | | | | 12.#21 V3 Def Alloc r14 | | | |V0 a| | | | | | | |V3 a| 1RPCSystem: jobgroup=3466 version=0 8.#22 I14 Def Alloc rdi | | | |V0 a| |I14a| | | | | |V3 a| 19.#23 V3 Use Keep r14 | | | |V0 a| |I14a| | | | | |V3 a| 19.#24 I14 Use * Keep rdi | | | |V0 a| |I14i| | | | | |V3 a| 22.#25 C15 Def Alloc rdi | | | |V0 a| |C15a| | | | | |V3 a| 23.#26 rdi Fixd Keep rdi | | | |V0 a| |C15a| | | | | |V3 a| 23.#27 C15 Use * Keep rdi | | | |V0 a| |C15i| | | | | |V3 a| 24.#28 rdi Fixd Keep rdi | | | |V0 a| | | | | | | |V3 a| 24.#29 I16 Def Alloc rdi | | | |V0 a| |I16a| | | | | |V3 a| 25.#30 rdi Fixd Keep rdi | | | |V0 a| |I16a| | | | | |V3 a| 25.#31 I16 Use * Keep rdi | | | |V0 a| |I16i| | | | | |V3 a| 26.#32 rax Kill Keep rax | | | |V0 a| | | | | | | |V3 a| 26.#33 rcx Kill Keep rcx | | | |V0 a| | | | | | | |V3 a| 26.#34 rdx Kill Keep rdx | | | |V0 a| | | | | | | |V3 a| 26.#35 rsi Kill Keep rsi | | | |V0 a| | | | | | | |V3 a| 26.#36 rdi Kill Keep rdi | | | |V0 a| | | | | | | |V3 a| 26.#37 r8 Kill Keep r8 | | | |V0 a| | | | | | | |V3 a| 26.#38 r9 Kill Keep r9 | | | |V0 a| | | | | | | |V3 a| 26.#39 r10 Kill Keep r10 | | | |V0 a| | | | | | | |V3 a| 26.#40 r11 Kill Keep r11 | | | |V0 a| | | | | | | |V3 a| 26.#41 rax Fixd Keep rax | | | |V0 a| | | | | | | |V3 a| 26.#42 I17 Def Alloc rax |I17a| | |V0 a| | | | | | | |V3 a| 27.#43 I17 Use * Keep rax |I17i| | |V0 a| | | | | | | |V3 a| 28.#44 V4 Def Alloc rax |V4 a| | |V0 a| | | | | | | |V3 a| 34.#45 I18 Def Alloc rsi |V4 a| | |V0 a|I18a| | | | | | |V3 a| 35.#46 V4 Use Keep rax |V4 a| | |V0 a|I18a| | | | | | |V3 a| 35.#47 I18 Use * Keep rsi |V4 a| | |V0 a|I18i| | | | | | |V3 a| 39.#48 V3 Use * Keep r14 |V4 a| | |V0 a| | | | | | | |V3 i| 40.#49 V13 Def Alloc r14 |V4 a| | |V0 a| | | | | | | |V13a| 43.#50 V4 Use * Keep rax |V4 i| | |V0 a| | | | | | | |V13a| 44.#51 V14 Def Alloc rax |V14a| | |V0 a| | | | | | | |V13a| 46.#52 C19 Def Alloc rsi |V14a| | |V0 a|C19a| | | | | | |V13a| 47.#53 C19 Use * Keep rsi |V14a| | |V0 a|C19i| | | | | | |V13a| 48.#54 I20 Def Alloc rsi |V14a| | |V0 a|I20a| | | | | | |V13a| 49.#55 I20 Use * Keep rsi |V14a| | |V0 a|I20i| | | | | | |V13a| 50.#56 V16 Def Alloc rsi |V14a| | |V0 a|V16a| | | | | | |V13a| 56.#57 C21 Def Alloc rdi |V14a| | |V0 a|V16a|C21a| | | | | |V13a| 61.#58 V13 Use * Keep r14 |V14a| | |V0 a|V16a|C21a| | | | | |V13i| 61.#59 V14 Use * Keep rax |V14i| | |V0 a|V16a|C21a| | | | | | | 61.#60 C21 Use * Keep rdi | | | |V0 a|V16a|C21i| | | | | | | 61.#61 V16 Use * Keep rsi | | | |V0 a|V16i| | | | | | | | 64.#62 C22 Def Alloc rsi | | | |V0 a|C22a| | | | | | | | 65.#63 C22 Use * Keep rsi | | | |V0 a|C22i| | | | | | | | 66.#64 I23 Def Alloc rsi | | | |V0 a|I23a| | | | | | | | 67.#65 rsi Fixd Keep rsi | | | |V0 a|I23a| | | | | | | | 67.#66 I23 Use * Keep rsi | | | |V0 a|I23i| | | | | | | | 68.#67 rsi Fixd Keep rsi | | | |V0 a| | | | | | | | | 68.#68 I24 Def Alloc rsi | | | |V0 a|I24a| | | | | | | | 70.#69 C25 Def Reuse rdi | | | |V0 a|I24a|C25a| | | | | | | 71.#70 rdi Fixd Keep rdi | | | |V0 a|I24a|C25a| | | | | | | 71.#71 C25 Use * Keep rdi | | | |V0 a|I24a|C25i| | | | | | | 72.#72 rdi Fixd Keep rdi | | | |V0 a|I24a| | | | | | | | 72.#73 I26 Def Alloc rdi | | | |V0 a|I24a|I26a| | | | | | | 73.#74 rsi Fixd Keep rsi | | | |V0 a|I24a|I26a| | | | | | | 73.#75 I24 Use * Keep rsi | | | |V0 a|I24i|I26a| | | | | | | 73.#76 rdi Fixd Keep rdi | | | |V0 a| |I26a| | | | | | | 73.#77 I26 Use * Keep rdi | | | |V0 a| |I26i| | | | | | | 74.#78 rax Kill Keep rax | | | |V0 a| | | | | | | | | 74.#79 rcx Kill Keep rcx | | | |V0 a| | | | | | | | | 74.#80 rdx Kill Keep rdx | | | |V0 a| | | | | | | | | 74.#81 rsi Kill Keep rsi | | | |V0 a| | | | | | | | | 74.#82 rdi Kill Keep rdi | | | |V0 a| | | | | | | | | 74.#83 r8 Kill Keep r8 | | | |V0 a| | | | | | | | | 74.#84 r9 Kill Keep r9 | | | |V0 a| | | | | | | | | 74.#85 r10 Kill Keep r10 | | | |V0 a| | | | | | | | | 74.#86 r11 Kill Keep r11 | | | |V0 a| | | | | | | | | 74.#87 rax Fixd Keep rax | | | |V0 a| | | | | | | | | 74.#88 I27 Def Alloc rax |I27a| | |V0 a| | | | | | | | | 75.#89 I27 Use * Keep rax |I27i| | |V0 a| | | | | | | | | 76.#90 V10 Def Alloc rsi | | | |V0 a|V10a| | | | | | | | 79.#91 rsi Fixd Keep rsi | | | |V0 a|V10a| | | | | | | | 79.#92 V10 Use * Keep rsi | | | |V0 a|V10i| | | | | | | | 80.#93 rsi Fixd Keep rsi | | | |V0 a| | | | | | | | | 80.#94 I28 Def Alloc rsi | | | |V0 a|I28a| | | | | | | | 82.#95 C29 Def Alloc rdi | | | |V0 a|I28a|C29a| | | | | | | 83.#96 rdi Fixd Keep rdi | | | |V0 a|I28a|C29a| | | | | | | 83.#97 C29 Use * Keep rdi | | | |V0 a|I28a|C29i| | | | | | | 84.#98 rdi Fixd Keep rdi | | | |V0 a|I28a| | | | | | | | 84.#99 I30 Def Alloc rdi | | | |V0 a|I28a|I30a| | | | | | | 85.#100 rsi Fixd Keep rsi | | | |V0 a|I28a|I30a| | | | | | | 85.#101 I28 Use * Keep rsi | | | |V0 a|I28i|I30a| | | | | | | 85.#102 rdi Fixd Keep rdi | | | |V0 a| |I30a| | | | | | | 85.#103 I30 Use * Keep rdi | | | |V0 a| |I30i| | | | | | | 86.#104 rax Kill Keep rax | | | |V0 a| | | | | | | | | 86.#105 rcx Kill Keep rcx | | | |V0 a| | | | | | | | | 86.#106 rdx Kill Keep rdx | | | |V0 a| | | | | | | | | 86.#107 rsi Kill Keep rsi | | | |V0 a| | | | | | | | | 86.#108 rdi Kill Keep rdi | | | |V0 a| | | | | | | | | 86.#109 r8 Kill Keep r8 | | | |V0 a| | | | | | | | | 86.#110 r9 Kill Keep r9 | | | |V0 a| | | | | | | | | 86.#111 r10 Kill Keep r10 | | | |V0 a| | | | | | | | | 86.#112 r11 Kill Keep r11 | | | |V0 a| | | | | | | | | 90.#113 C31 Def Alloc rdi | | | |V0 a| |C31a| | | | | | | 91.#114 C31 Use * Keep rdi | | | |V0 a| |C31i| | | | | | | 92.#115 I32 Def Alloc rdi | | | |V0 a| |I32a| | | | | | | 93.#116 I32 Use * Keep rdi | | | |V0 a| |I32i| | | | | | | 94.#117 V12 Def Alloc rdi | | | |V0 a| |V12a| | | | | | | 101.#118 V0 Use Keep rbx | | | |V0 a| |V12a| | | | | | | 102.#119 I33 Def Alloc rsi | | | |V0 a|I33a|V12a| | | | | | | 103.#120 I33 Use * Keep rsi | | | |V0 a|I33i|V12a| | | | | | | 104.#121 V11 Def Alloc rsi | | | |V0 a|V11a|V12a| | | | | | | 115.#122 V11 Use Keep rsi | | | |V0 a|V11a|V12a| | | | | | | 115.#123 V12 Use Keep rdi | | | |V0 a|V11a|V12a| | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ 119.#124 BB2 PredBB1 | | | |V0 a|V11a|V12a| | | | | | | 125.#125 V12 Use * Keep rdi | | | |V0 a|V11a|V12i| | | | | | | 126.#126 I34 Def Alloc rdi | | | |V0 a|V11a|I34a| | | | | | | 127.#127 I34 Use * Keep rdi | | | |V0 a|V11a|I34i| | | | | | | 128.#128 V18 Def Alloc rdi | | | |V0 a|V11a|V18a| | | | | | | 137.#129 V11 Use Keep rsi | | | |V0 a|V11a|V18a| | | | | | | 137.#130 V18 Use Keep rdi | | | |V0 a|V11a|V18a| | | | | | | 143.#131 V11 Use * Keep rsi | | | |V0 a|V11i|V18a| | | | | | | 144.#132 I35 Def Alloc rsi | | | |V0 a|I35a|V18a| | | | | | | 147.#133 V18 Use * Keep rdi | | | |V0 a|I35a|V18i| | | | | | | 147.#134 I35 Use * Keep rsi | | | |V0 a|I35i| | | | | | | | 148.#135 I36 Def Alloc rdi | | | |V0 a| |I36a| | | | | | | 149.#136 I36 Use * Keep rdi | | | |V0 a| |I36i| | | | | | | 150.#137 V19 Def Alloc rdi | | | |V0 a| | | | | | | | | Spill rdi | | | |V0 a| | | | | | | | | 155.#138 V0 Use * Keep rbx | | | |V0 i| | | | | | | | | 156.#139 I37 Def Alloc rbx | | | |I37a| | | | | | | | | 159.#140 rdi Fixd Keep rdi | | | |I37a| | | | | | | | | 159.#141 I38 Def Alloc rdi | | | |I37a| |I38a| | | | | | | 159.#142 rcx Fixd Keep rcx | | | |I37a| |I38a| | | | | | | 159.#143 I39 Def Alloc rcx | |I39a| |I37a| |I38a| | | | | | | 159.#144 rsi Fixd Keep rsi | |I39a| |I37a| |I38a| | | | | | | 159.#145 I40 Def Alloc rsi | |I39a| |I37a|I40a|I38a| | | | | | | 159.#146 I37 Use * Keep rbx | |I39a| |I37i|I40a|I38a| | | | | | | 159.#147 I38 Use * Keep rdi | |I39a| | |I40a|I38i| | | | | | | 159.#148 I39 Use * Keep rcx | |I39i| | |I40a| | | | | | | | 159.#149 I40 Use * Keep rsi | | | | |I40i| | | | | | | | 163.#150 rdi Fixd Keep rdi | | | | | | | | | | | | | 163.#151 V19 Use * ReLod rdi | | | | | |V19a| | | | | | | Keep rdi | | | | | |V19i| | | | | | | 164.#152 rdi Fixd Keep rdi | | | | | | | | | | | | | 164.#153 I41 Def Alloc rdi | | | | | |I41a| | | | | | | 166.#154 I42 Def Alloc rdx | | |I42a| | |I41a| | | | | | | 167.#155 rdx Fixd Keep rdx | | |I42a| | |I41a| | | | | | | 167.#156 I42 Use * Keep rdx | | |I42i| | |I41a| | | | | | | 168.#157 rdx Fixd Keep rdx | | | | | |I41a| | | | | | | 168.#158 I43 Def Alloc rdx | | |I43a| | |I41a| | | | | | | 170.#159 I44 Def Alloc rcx | |I44a|I43a| | |I41a| | | | | | | 171.#160 rcx Fixd Keep rcx | |I44a|I43a| | |I41a| | | | | | | 171.#161 I44 Use * Keep rcx | |I44i|I43a| | |I41a| | | | | | | 172.#162 rcx Fixd Keep rcx | | |I43a| | |I41a| | | | | | | 172.#163 I45 Def Alloc rcx | |I45a|I43a| | |I41a| | | | | | | 176.#164 r11 Fixd Keep r11 | |I45a|I43a| | |I41a| | | | | | | 176.#165 C46 Def Alloc r11 | |I45a|I43a| | |I41a| | |C46a| | | | 177.#166 r11 Fixd Keep r11 | |I45a|I43a| | |I41a| | |C46a| | | | 177.#167 C46 Use * Keep r11 | |I45a|I43a| | |I41a| | |C46i| | | | 178.#168 r11 Fixd Keep r11 | |I45a|I43a| | |I41a| | | | | | | 178.#169 I47 Def Alloc r11 | |I45a|I43a| | |I41a| | | | | | | Spill r11 | |I45a|I43a| | |I41a| | | | | | | 180.#170 r11 Fixd Keep r11 | |I45a|I43a| | |I41a| | | | | | | 180.#171 C48 Def Alloc r11 | |I45a|I43a| | |I41a| | |C48a| | | | 181.#172 rsi Fixd Keep rsi | |I45a|I43a| | |I41a| | |C48a| | | | Move rsi | |I45a|I43a| |C48i|I41a| | | | | | | 182.#174 rsi Fixd Keep rsi | |I45a|I43a| | |I41a| | | | | | | 182.#175 I49 Def Alloc rsi | |I45a|I43a| |I49a|I41a| | | | | | | 184.#176 C50 Def Alloc rax |C50a|I45a|I43a| |I49a|I41a| | | | | | | 187.#177 rdi Fixd Keep rdi |C50a|I45a|I43a| |I49a|I41a| | | | | | | 187.#178 I41 Use * Keep rdi |C50a|I45a|I43a| |I49a|I41i| | | | | | | 187.#179 rdx Fixd Keep rdx |C50a|I45a|I43a| |I49a| | | | | | | | 187.#180 I43 Use * Keep rdx |C50a|I45a|I43i| |I49a| | | | | | | | 187.#181 rcx Fixd Keep rcx |C50a|I45a| | |I49a| | | | | | | | 187.#182 I45 Use * Keep rcx |C50a|I45i| | |I49a| | | | | | | | 187.#183 r11 Fixd Keep r11 |C50a| | | |I49a| | | | | | | | 187.#184 I47 Use * ReLod r11 |C50a| | | |I49a| | | |I47a| | | | Keep r11 |C50a| | | |I49a| | | |I47i| | | | 187.#185 rsi Fixd Keep rsi |C50a| | | |I49a| | | | | | | | 187.#186 I49 Use * Keep rsi |C50a| | | |I49i| | | | | | | | 187.#187 C50 Use * Keep rax |C50i| | | | | | | | | | | | 188.#188 rax Kill Keep rax | | | | | | | | | | | | | 188.#189 rcx Kill Keep rcx | | | | | | | | | | | | | 188.#190 rdx Kill Keep rdx | | | | | | | | | | | | | 188.#191 rsi Kill Keep rsi | | | | | | | | | | | | | 188.#192 rdi Kill Keep rdi | | | | | | | | | | | | | 188.#193 r8 Kill Keep r8 | | | | | | | | | | | | | 188.#194 r9 Kill Keep r9 | | | | | | | | | | | | | 188.#195 r10 Kill Keep r10 | | | | | | | | | | | | | 188.#196 r11 Kill Keep r11 | | | | | | | | | | | | | 188.#197 rax Fixd Keep rax | | | | | | | | | | | | | 188.#198 I51 Def Alloc rax |I51a| | | | | | | | | | | | 188.#199 rdx Fixd Keep rdx |I51a| | | | | | | | | | | | 188.#200 I52 Def Alloc rdx |I51a| |I52a| | | | | | | | | | 189.#201 I51 Use * Keep rax |I51i| |I52a| | | | | | | | | | 189.#202 I52 Use * Keep rdx | | |I52i| | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ 195.#203 BB3 PredBB1 | | | | | | | | | | | | | 200.#204 rax Kill Keep rax | | | | | | | | | | | | | 200.#205 rcx Kill Keep rcx | | | | | | | | | | | | | 200.#206 rdx Kill Keep rdx | | | | | | | | | | | | | 200.#207 rsi Kill Keep rsi | | | | | | | | | | | | | 200.#208 rdi Kill Keep rdi | | | | | | | | | | | | | 200.#209 r8 Kill Keep r8 | | | | | | | | | | | | | 200.#210 r9 Kill Keep r9 | | | | | | | | | | | | | 200.#211 r10 Kill Keep r10 | | | | | | | | | | | | | 200.#212 r11 Kill Keep r11 | | | | | | | | | | | | | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ Loc RP# Name Type Action Reg |rax |rcx |rdx |rbx |rsi |rdi |r8 |r9 |r11 |r12 |r13 |r14 | --------------------------------+----+----+----+----+----+----+----+----+----+----+----+----+ 201.#213 BB4 PredBB3 | | | | | | | | | | | | | 204.#214 rax Kill Keep rax | | | | | | | | | | | | | 204.#215 rcx Kill Keep rcx | | | | | | | | | | | | | 204.#216 rdx Kill Keep rdx | | | | | | | | | | | | | 204.#217 rsi Kill Keep rsi | | | | | | | | | | | | | 204.#218 rdi Kill Keep rdi | | | | | | | | | | | | | 204.#219 r8 Kill Keep r8 | | | | | | | | | | | | | 204.#220 r9 Kill Keep r9 | | | | | | | | | | | | | 204.#221 r10 Kill Keep r10 | | | | | | | | | | | | | 204.#222 r11 Kill Keep r11 | | | | | | | | | | | | | Recording the maximum number of concurrent spills: long: 1 pre-allocated temp #1, slot 1, size = 8 ---------- LSRA Stats ---------- BB02 [ 100]: SpillCount = 2, ResolutionMovs = 0, SplitEdges = 0, CopyReg = 1 Total Tracked Vars: 14 Total Reg Cand Vars: 11 Total number of Intervals: 52 Total number of RefPositions: 222 Total Spill Count: 2 Weighted: 200 Total CopyReg Count: 1 Weighted: 100 Total ResolutionMov Count: 0 Weighted: 0 Total number of split edges: 0 Total Number of spill temps created: 1 TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS Incoming Parameters: V00(rdi=>rbx) BB01 [000..042) -> BB03 (cond), preds={} succs={BB02,BB03} ===== N003. IL_OFFSET IL offset: 0x0 N005. rdi = CNS_INT(h) 0x7f6678c127f0 class N007. rdi = PUTARG_REG; rdi N009. rax = CALL help; rdi * N011. V03(r14); rax N013. V03(r14) N015. STK = LEA(b+8) ; r14 N017. rdi = V01 MEM N019. STOREIND ; STK,rdi N021. rdi = CNS_INT(h) 0x7f6678beb1c0 class N023. rdi = PUTARG_REG; rdi N025. rax = CALL help; rdi * N027. V04(rax); rax N029. V04(rax) N031. STK = LEA(b+8) ; rax N033. rsi = V01 MEM N035. STOREIND ; STK,rsi N037. V03(r14*) * N039. V13(r14); r14* N041. V04(rax*) * N043. V14(rax); rax* N045. rsi = CNS_INT(h) 0x7f6663fff340 static Fseq[s_twoArgArray] N047. rsi = IND ; rsi * N049. V16(rsi); rsi N051. V13(r14*) N053. V14(rax*) N055. rdi = CNS_INT null N057. V16(rsi*) N059. STK = FIELD_LIST; r14*,rax*,rdi,rsi* N061. PUTARG_STK [+0x00]; STK N063. rsi = CNS_INT(h) 0x64008A98 [ICON_STR_HDL] N065. rsi = IND ; rsi N067. rsi = PUTARG_REG; rsi N069. rdi = CNS_INT null reuse reg val N071. rdi = PUTARG_REG; rdi N073. rax = CALL ; rsi,rdi * N075. V10(rsi); rax N077. V10(rsi*) N079. rsi = PUTARG_REG; rsi* N081. rdi = CNS_INT 3 N083. rdi = PUTARG_REG; rdi N085. CALL ; rsi,rdi N087. IL_OFFSET IL offset: 0x25 N089. rdi = CNS_INT(h) 0x7f6664004668 static Fseq[s_NetworkInterfaces] N091. rdi = IND ; rdi * N093. V12(rdi); rdi N095. IL_OFFSET IL offset: 0x25 N097. V00(rbx) N099. STK = LEA(b+16); rbx N101. rsi = IND ; STK * N103. V11(rsi); rsi N105. IL_OFFSET IL offset: 0x25 N107. V11(rsi) N109. V12(rdi) N111. STK = LEA(b+16); rdi N113. STK = IND ; STK N115. GE ; rsi,STK N117. JTRUE Var=Reg end of BB01: V11=rsi V00=rbx V12=rdi BB02 [025..026) (return), preds={BB01} succs={} ===== Predecessor for variable locations: BB01 Var=Reg beg of BB02: V11=rsi V00=rbx V12=rdi N121. V12(rdi*) N123. STK = LEA(b+8) ; rdi* N125. rdi = IND ; STK * N127. V18(rdi); rdi N129. V11(rsi) N131. V18(rdi) N133. STK = LEA(b+8) ; rdi N135. STK = IND ; STK N137. ARR_BOUNDS_CHECK_Rng; rsi,STK N139. V18(rdi*) N141. V11(rsi*) N143. rsi = CAST ; rsi* N145. STK = LEA(b+(i*8)+16); rdi*,rsi N147. rdi = IND ; STK N149. V19(STK); rdi N151. V00(rbx*) N153. CNS_INT 56 field offset Fseq[m_ParallelSendQueue] N155. rbx = ADD ; rbx* N157. STK = OBJ ; rbx N159. PUTARG_STK [+0x00]; STK N161. V19(rdi*)R N163. rdi = PUTARG_REG; rdi* N165. rdx = V01 MEM N167. rdx ScheduleFlushSend: jobgroup=3466 version=0 = PUTARG_REG; rdx N169. rcx = V01 MEM N171. rcx = PUTARG_REG; rcx N173. STK = FIELD_LIST; rdx,rcx N175. r11 = CNS_INT(h) 0x7f6678060518 ftn S N177. r11 = PUTARG_REG; r11 N179. r11 = CNS_INT(h) 0x7f6678060518 ftn N000. rsi = COPY ; r11 N181. rsi = PUTARG_REG; rsi N183. rax = CNS_INT(h) 0x7f6678060518 ftn N185. STK = IND ; rax N187. rax,rdx = CALLV stub; rdi,STK,r11,rsi,STK N189. V17 MEM; rax,rdx N191. V17 MEM N193. RETURN Var=Reg end of BB02: none BB03 [025..026) (throw), preds={BB01} succs={} ===== Predecessor for variable locations: BB01 Var=Reg beg of BB03: none N197. IL_OFFSET IL offset: 0x25 N199. CALL Var=Reg end of BB03: none BB04 [???..???) (throw), preds={} succs={} ===== Predecessor for variable locations: BB03 Var=Reg beg of BB04: none N203. CALL help Var=Reg end of BB04: none *************** Finishing PHASE Linear scan register alloc *************** In genGenerateCode() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..042)-> BB03 ( cond ) i label target hascall gcsafe newobj LIR BB02 [0006] 1 BB01 1 [025..026) (return) i label target hascall gcsafe idxlen newobj LIR BB03 [0005] 1 BB01 0 [025..026) (throw ) i rare label target hascall gcsafe LIR BB04 [0008] 0 0 [???..???) (throw ) keep i internal rare label target LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Generate code *************** In fgDebugCheckBBlist Finalizing stack frame Recording Var Locations at start of BB01 V00(rbx) Modified regs: [rax rcx rdx rbx rsi rdi r8-r11 r14] Callee-saved registers pushed: 2 [rbx r14] *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT) Assign V01 arg1, size=16, stkOffs=-0x30 Assign V17 tmp15, size=16, stkOffs=-0x40 Assign V19 tmp17, size=8, stkOffs=-0x48 Assign V02 OutArgs, size=56, stkOffs=-0x88 --- delta bump 8 for RA --- delta bump 8 for FP --- delta bump 0 for RBP frame --- virtual stack offset to actual stack offset delta is 16 -- V00 was 0, now 16 -- V01 was -48, now -32 -- V02 was -136, now -120 -- V17 was -64, now -48 -- V19 was -72, now -56 ; Final local variable assignments ; ; V00 this [V00,T02] ( 4, 4 ) byref -> rbx this ; V01 arg1 [V01,T00] ( 6, 6 ) struct (16) [rbp-0x20] do-not-enreg[SFA] multireg-arg ; V02 OutArgs [V02 ] ( 1, 1 ) lclBlk (56) [rsp+0x00] "OutgoingArgSpace" ; V03 tmp1 [V03,T03] ( 3, 6 ) ref -> r14 class-hnd exact "Single-def Box Helper" ; V04 tmp2 [V04,T04] ( 3, 6 ) ref -> rax class-hnd exact "Single-def Box Helper" ;* V05 tmp3 [V05 ] ( 0, 0 ) ref -> zero-ref class-hnd exact "Inlining Arg" ;* V06 tmp4 [V06 ] ( 0, 0 ) ref -> zero-ref class-hnd exact "Inlining Arg" ;* V07 tmp5 [V07 ] ( 0, 0 ) struct (32) zero-ref "NewObj constructor temp" ;* V08 tmp6 [V08 ] ( 0, 0 ) ref -> zero-ref class-hnd exact "Inlining Arg" ;* V09 tmp7 [V09 ] ( 0, 0 ) ref -> zero-ref class-hnd exact "Inlining Arg" ; V10 tmp8 [V10,T07] ( 2, 4 ) ref -> rsi class-hnd "Inlining Arg" ; V11 tmp9 [V11,T01] ( 4, 8 ) int -> rsi "Inlining Arg" ; V12 tmp10 [V12,T05] ( 3, 6 ) ref -> rdi class-hnd "Inlining Arg" ; V13 tmp11 [V13,T09] ( 2, 2 ) ref -> r14 V07._arg0(offs=0x00) P-INDEP "field V07._arg0 (fldOffset=0x0)" ; V14 tmp12 [V14,T10] ( 2, 2 ) ref -> rax V07._arg1(offs=0x08) P-INDEP "field V07._arg1 (fldOffset=0x8)" ;* V15 tmp13 [V15,T13] ( 0, 0 ) ref -> zero-ref V07._arg2(offs=0x10) P-INDEP "field V07._arg2 (fldOffset=0x10)" ; V16 tmp14 [V16,T11] ( 2, 2 ) ref -> rsi V07._args(offs=0x18) P-INDEP "field V07._args (fldOffset=0x18)" ; V17 tmp15 [V17,T12] ( 2, 2 ) struct (16) [rbp-0x30] do-not-enreg[SR] multireg-ret must-init "Return value temp for multi-reg return (rejected tail call)." ; V18 tmp16 [V18,T06] ( 3, 6 ) ref -> rdi "arr expr" ; V19 tmp17 [V19,T08] ( 2, 4 ) ref -> [rbp-0x38] "argument with side effect" ; TEMP_01 long -> [rbp-0x40] ; ; Lcl frame size = 112 Setting stack level from -572662307 to 0 =============== Generating BB01 [000..042) -> BB03 (cond), preds={} succs={BB02,BB03} flags=0x00000004.408b0020: i label target hascall gcsafe newobj LIR BB01 IN (2)={V01 V00 } + ByrefExposed + GcHeap OUT(4)={V01 V11 V00 V12} + ByrefExposed + GcHeap Recording Var Locations at start of BB01 V00(rbx) Change life {} -> {V00 V01} V00 in reg rbx is becoming live [------] Live regs: 00000000 {} => 00000008 {rbx} Live regs: (unchanged) 00000008 {rbx} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000008 {rbx} L_M63542_BB01: Label: IG02, GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000008 {rbx} Scope info: begin block BB01, IL range [000..042) Scope info: open scopes = 1 (V01 arg1) [000..042) 0 (V00 this) [000..042) Added IP mapping: 0x0000 STACK_EMPTY (G_M63542_IG02,ins#0,ofs#0) label Generating: N003 (???,???) [000155] ------------ IL_OFFSET void IL offset: 0x0 REG NA Generating: N005 ( 2, 10) [000004] ------------ t4 = CNS_INT(h) long 0x7f6678c127f0 class REG rdi $180 IN0001: mov rdi, 0x7F6678C127F0 /--* t4 long Generating: N007 (???,???) [000165] ------------ t165 = * PUTARG_REG long REG rdi /--* t165 long arg0 in rdi Generating: N009 ( 16, 16) [000005] --C--------- t5 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG rax $200 Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000008 {rbx} IN0002: call CORINFO_HELP_NEWSFAST GC regs: 00000000 {} => 00000001 {rax} /--* t5 ref Generating: N011 ( 16, 16) [000007] DA---------- * STORE_LCL_VAR ref V03 tmp1 d:2 r14 REG r14 GC regs: 00000001 {rax} => 00000000 {} IN0003: mov r14, rax V03 in reg r14 is becoming live [000007] Live regs: 00000008 {rbx} => 00004008 {rbx r14} Live vars: {V00 V01} => {V00 V01 V03} GC regs: 00000000 {} => 00004000 {r14} Generating: N013 ( 1, 1) [000008] ------------ t8 = LCL_VAR ref V03 tmp1 u:2 r14 REG r14 $200 /--* t8 ref Generating: N015 ( 2, 2) [000010] -c---------- t10 = * LEA(b+8) byref REG NA Generating: N017 ( 3, 4) [000003] ------------ t3 = LCL_FLD long V01 arg1 u:1[+0] Fseq[JobGroup] rdi REG rdi $2c0 IN0004: mov rdi, qword ptr [V01 rbp-20H] /--* t10 byref +--* t3 long Generating: N019 (???,???) [000156] -A--GO------ * STOREIND long REG NA IN0005: mov qword ptr [r14+8], rdi Generating: N021 ( 2, 10) [000018] ------------ t18 = CNS_INT(h) long 0x7f6678beb1c0 class REG rdi $182 IN0006: mov rdi, 0x7F6678BEB1C0 /--* t18 long Generating: N023 (???,???) [000166] ------------ t166 = * PUTARG_REG long REG rdi /--* t166 long arg0 in rdi Generating: N025 ( 16, 16) [000019] --C--------- t19 = * CALL help ref HELPER.CORINFO_HELP_NEWSFAST REG rax $201 Call: GCvars= {}, gcrefRegs=00004000 {r14}, byrefRegs=00000008 {rbx} IN0007: call CORINFO_HELP_NEWSFAST GC regs: 00004000 {r14} => 00004001 {rax r14} /--* t19 ref Generating: N027 ( 16, 16) [000021] DA---------- * STORE_LCL_VAR ref V04 tmp2 d:2 rax REG rax GC regs: 00004001 {rax r14} => 00004000 {r14} V04 in reg rax is becoming live [000021] Live regs: 00004008 {rbx r14} => 00004009 {rax rbx r14} Live vars: {V00 V01 V03} => {V00 V01 V03 V04} GC regs: 00004000 {r14} => 00004001 {rax r14} Generating: N029 ( 1, 1) [000022] ------------ t22 = LCL_VAR ref V04 tmp2 u:2 rax REG rax $201 /--* t22 ref Generating: N031 ( 2, 2) [000024] -c---------- t24 = * LEA(b+8) byref REG NA Generating: N033 ( 3, 4) [000017] ------------ t17 = LCL_FLD int V01 arg1 u:1[+8] Fseq[Version] rsi REG rsi $300 IN0008: mov esi, dword ptr [V01+0x8 rbp-18H] /--* t24 byref +--* t17 int Generating: N035 (???,???) [000157] -A--GO------ * STOREIND int REG NA IN0009: mov dword ptr [rax+8], esi Generating: N037 ( 1, 1) [000013] ------------ t13 = LCL_VAR ref V03 tmp1 u:2 r14 (last use) REG r14 $200 /--* t13 ref Generating: N039 ( 11, 8) [000063] DA---------- * STORE_LCL_VAR ref V13 tmp11 d:2 r14 REG r14 V03 in reg r14 is becoming dead [000013] Live regs: 00004009 {rax rbx r14} => 00000009 {rax rbx} Live vars: {V00 V01 V03 V04} => {V00 V01 V04} GC regs: 00004001 {rax r14} => 00000001 {rax} V13 in reg r14 is becoming live [000063] Live regs: 00000009 {rax rbx} => 00004009 {rax rbx r14} Live vars: {V00 V01 V04} => {V00 V01 V04 V13} GC regs: 00000001 {rax} => 00004001 {rax r14} Generating: N041 ( 1, 1) [000027] ------------ t27 = LCL_VAR ref V04 tmp2 u:2 rax (last use) REG rax $201 /--* t27 ref Generating: N043 ( 11, 8) [000068] DA---------- * STORE_LCL_VAR ref V14 tmp12 d:2 rax REG rax V04 in reg rax is becoming dead [000027] Live regs: 00004009 {rax rbx r14} => 00004008 {rbx r14} Live vars: {V00 V01 V04 V13} => {V00 V01 V13} GC regs: 00004001 {rax r14} => 00004000 {r14} V14 in reg rax is becoming live [000068] Live regs: 00004008 {rbx r14} => 00004009 {rax rbx r14} Live vars: {V00 V01 V13} => {V00 V01 V13 V14} GC regs: 00004000 {r14} => 00004001 {rax r14} Generating: N045 ( 2, 10) [000104] ------------ t104 = CNS_INT(h) long 0x7f6663fff340 static Fseq[s_twoArgArray] REG rsi $184 IN000a: mov rsi, 0x7F6663FFF340 /--* t104 long Generating: N047 ( 4, 12) [000076] n---G------- t76 = * IND ref REG rsi IN000b: mov rsi, gword ptr [rsi] GC regs: 00004001 {rax r14} => 00004041 {rax rsi r14} /--* t76 ref Generating: N049 ( 8, 15) [000078] DA--G------- * STORE_LCL_VAR ref V16 tmp14 d:2 rsi REG rsi GC regs: 00004041 {rax rsi r14} => 00004001 {rax r14} V16 in reg rsi is becoming live [000078] Live regs: 00004009 {rax rbx r14} => 00004049 {rax rbx rsi r14} Live vars: {V00 V01 V13 V14} => {V00 V01 V13 V14 V16} GC regs: 00004001 {rax r14} => 00004041 {rax rsi r14} Generating: N051 ( 3, 2) [000110] ------------ t110 = LCL_VAR ref V13 tmp11 u:2 r14 (last use) REG r14 $200 Generating: N053 ( 3, 2) [000111] ------------ t111 = LCL_VAR ref V14 tmp12 u:2 rax (last use) REG rax $201 Generating: N055 ( 1, 1) [000154] ------------ t154 = CNS_INT ref null REG rdi $VN.Null IN000c: xor rdi, rdi GC regs: 00004041 {rax rsi r14} => 000040C1 {rax rsi rdi r14} Generating: N057 ( 3, 2) [000113] ------------ t113 = LCL_VAR ref V16 tmp14 u:2 rsi (last use) REG rsi /--* t110 ref +--* t111 ref +--* t154 ref +--* t113 ref Generating: N059 ( 10, 7) [000109] -c---------- t109 = * FIELD_LIST struct REG NA $380 /--* t109 struct Generating: N061 (???,???) [000167] ------------ * PUTARG_STK [+0x00] void (4 slots) REG NA V13 in reg r14 is becoming dead [000110] Live regs: 00004049 {rax rbx rsi r14} => 00000049 {rax rbx rsi} Live vars: {V00 V01 V13 V14 V16} => {V00 V01 V14 V16} GC regs: 000040C1 {rax rsi rdi r14} => 000000C1 {rax rsi rdi} IN000d: mov gword ptr [V02 rsp], r14 V14 in reg rax is becoming dead [000111] Live regs: 00000049 {rax rbx rsi} => 00000048 {rbx rsi} Live vars: {V00 V01 V14 V16} => {V00 V01 V16} GC regs: 000000C1 {rax rsi rdi} => 000000C0 {rsi rdi} IN000e: mov gword ptr [V02+0x8 rsp+08H], rax GC regs: 000000C0 {rsi rdi} => 00000040 {rsi} IN000f: mov gword ptr [V02+0x10 rsp+10H], rdi V16 in reg rsi is becoming dead [000113] Live regs: 00000048 {rbx rsi} => 00000008 {rbx} Live vars: {V00 V01 V16} => {V00 V01} GC regs: 00000040 {rsi} => 00000000 {} IN0010: mov gword ptr [V02+0x18 rsp+18H], rsi Generating: N063 ( 2, 10) [000105] ------------ t105 = CNS_INT(h) long 0x64008A98 [ICON_STR_HDL] REG rsi $185 IN0011: mov rsi, 0x7F6664008A98 /--* t105 long Generating: N065 ( 4, 12) [000106] n---G------- t106 = * IND ref REG rsi IN0012: mov rsi, gword ptr [rsi] GC regs: 00000000 {} => 00000040 {rsi} /--* t106 ref Generating: N067 (???,???) [000168] ----G------- t168 = * PUTARG_REG ref REG rsi GC regs: 00000040 {rsi} => 00000000 {} GC regs: 00000000 {} => 00000040 {rsi} Generating: N069 ( 1, 1) [000046] ------------ t46 = CNS_INT ref null reuse reg val REG rdi $VN.Null TreeNode is marked ReuseReg /--* t46 ref Generating: N071 (???,???) [000169] ------------ t169 = * PUTARG_REG ref REG rdi GC regs: 00000040 {rsi} => 000000C0 {rsi rdi} /--* t168 ref arg1 in rsi +--* t169 ref arg0 in rdi Generating: N073 ( 32, 27) [000054] --CXG------- t54 = * CALL ref System.String.FormatHelper REG rax $1ce GC regs: 000000C0 {rsi rdi} => 00000080 {rdi} GC regs: 00000080 {rdi} => 00000000 {} Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000008 {rbx} IN0013: call System.String:FormatHelper(System.IFormatProvider,System.String,System.ParamsArray):System.String GC regs: 00000000 {} => 00000001 {rax} /--* t54 ref Generating: N075 ( 32, 27) [000085] DA-XG------- * STORE_LCL_VAR ref V10 tmp8 d:2 rsi REG rsi GC regs: 00000001 {rax} => 00000000 {} IN0014: mov rsi, rax V10 in reg rsi is becoming live [000085] Live regs: 00000008 {rbx} => 00000048 {rbx rsi} Live vars: {V00 V01} => {V00 V01 V10} GC regs: 00000000 {} => 00000040 {rsi} Generating: N077 ( 1, 1) [000082] ------------ t82 = LCL_VAR ref V10 tmp8 u:2 rsi (last use) REG rsi $1ce /--* t82 ref Generating: N079 (???,???) [000170] ------------ t170 = * PUTARG_REG ref REG rsi V10 in reg rsi is becoming dead [000082] Live regs: 00000048 {rbx rsi} => 00000008 {rbx} Live vars: {V00 V01 V10} => {V00 V01} GC regs: 00000040 {rsi} => 00000000 {} GC regs: 00000000 {} => 00000040 {rsi} Generating: N081 ( 1, 1) [000081] ------------ t81 = CNS_INT int 3 REG rdi $44 IN0015: mov edi, 3 /--* t81 int Generating: N083 (???,???) [000171] ------------ t171 = * PUTARG_REG int REG rdi /--* t170 ref arg1 in rsi +--* t171 int arg0 in rdi Generating: N085 ( 16, 9) [000083] --CXG------- * CALL void UnityEngine.Debug.ProcessAndLogInternal REG NA $VN.Void GC regs: 00000040 {rsi} => 00000000 {} Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000008 {rbx} IN0016: call UnityEngine.Debug:ProcessAndLogInternal(int,System.Object) Added IP mapping: 0x0025 STACK_EMPTY (G_M63542_IG02,ins#22,ofs#112) Generating: N087 (???,???) [000158] ------------ IL_OFFSET void IL offset: 0x25 REG NA Generating: N089 ( 2, 10) [000116] ------------ t116 = CNS_INT(h) long 0x7f6664004668 static Fseq[s_NetworkInterfaces] REG rdi $186 IN0017: mov rdi, 0x7F6664004668 /--* t116 long Generating: N091 ( 4, 12) [000032] n---G------- t32 = * IND ref REG rdi IN0018: mov rdi, gword ptr [rdi] GC regs: 00000000 {} => 00000080 {rdi} /--* t32 ref Generating: N093 ( 4, 12) [000098] DA--G------- * STORE_LCL_VAR ref V12 tmp10 d:2 rdi REG rdi GC regs: 00000080 {rdi} => 00000000 {} V12 in reg rdi is becoming live [000098] Live regs: 00000008 {rbx} => 00000088 {rbx rdi} Live vars: {V00 V01} => {V00 V01 V12} GC regs: 00000000 {} => 00000080 {rdi} genIPmappingAdd: ignoring duplicate IL offset 0x25 Generating: N095 (???,???) [000159] ------------ IL_OFFSET void IL offset: 0x25 REG NA Generating: N097 ( 1, 1) [000033] ------------ t33 = LCL_VAR byref V00 this u:1 rbx REG rbx $80 /--* t33 byref Generating: N099 ( 2, 2) [000118] -c---------- t118 = * LEA(b+16) byref REG NA /--* t118 byref Generating: N101 ( 4, 4) [000034] *--XG------- t34 = * IND int REG rsi IN0019: mov esi, dword ptr [rbx+16] /--* t34 int Generating: N103 ( 4, 4) [000100] DA-XG------- * STORE_LCL_VAR int V11 tmp9 d:2 rsi REG rsi V11 in reg rsi is becoming live [000100] Live regs: 00000088 {rbx rdi} => 000000C8 {rbx rsi rdi} Live vars: {V00 V01 V12} => {V00 V01 V11 V12} genIPmappingAdd: ignoring duplicate IL offset 0x25 Generating: N105 (???,???) [000160] ------------ IL_OFFSET void IL offset: 0x25 REG NA Generating: N107 ( 1, 1) [000087] ------------ t87 = LCL_VAR int V11 tmp9 u:2 rsi REG rsi Generating: N109 ( 1, 1) [000088] ------------ t88 = LCL_VAR ref V12 tmp10 u:2 rdi REG rdi /--* t88 ref Generating: N111 ( 2, 2) [000120] -c---------- t120 = * LEA(b+16) byref REG NA /--* t120 byref Generating: N113 ( 4, 4) [000089] -c-XG------- t89 = * IND int REG NA /--* t87 int +--* t89 int Generating: N115 ( 6, 6) [000090] N--XG--N-U-- * GE void REG NA IN001a: cmp esi, dword ptr [rdi+16] Generating: N117 ( 8, 8) [000091] ---XG------- * JTRUE void REG NA IN001b: jae L_M63542_BB03 Scope info: end block BB01, IL range [000..042) Scope info: ending scope, LVnum=0 [000..042) Scope info: ending scope, LVnum=1 [000..042) Scope info: open scopes = =============== Generating BB02 [025..026) (return), preds={BB01} succs={} flags=0x00000004.40ab0020: i label target hascall gcsafe idxlen newobj LIR BB02 IN (4)={V01 V11 V00 V12} + ByrefExposed + GcHeap OUT(0)={ } Recording Var Locations at start of BB02 V11(rsi) V00(rbx) V12(rdi) Liveness not changing: {V00 V01 V11 V12} Live regs: 00000000 {} => 000000C8 {rbx rsi rdi} GC regs: 00000000 {} => 00000080 {rdi} Byref regs: 00000000 {} => 00000008 {rbx} L_M63542_BB02: G_M63542_IG02: ; offs=000000H, funclet=00, bbWeight=1 Label: IG03, GCvars= {}, gcrefRegs=00000080 {rdi}, byrefRegs=00000008 {rbx} Scope info: begin block BB02, IL range [025..026) Scope info: open scopes = 1 (V01 arg1) [000..042) 0 (V00 this) [000..042) Generating: N121 ( 1, 1) [000092] ------------ t92 = LCL_VAR ref V12 tmp10 u:2 rdi (last use) REG rdi /--* t92 ref Generating: N123 ( 2, 2) [000141] -c---------- t141 = * LEA(b+8) byref REG NA /--* t141 byref Generating: N125 ( 4, 4) [000093] n---GO------ t93 = * IND ref REG rdi V12 in reg rdi is becoming dead [000092] Live regs: 000000C8 {rbx rsi rdi} => 00000048 {rbx rsi} Live vars: {V00 V01 V11 V12} => {V00 V01 V11} GC regs: 00000080 {rdi} => 00000000 {} IN001c: mov rdi, gword ptr [rdi+8] GC regs: 00000000 {} => 00000080 {rdi} /--* t93 ref Generating: N127 ( 4, 4) [000126] DA--GO------ * STORE_LCL_VAR ref V18 tmp16 d:2 rdi REG rdi GC regs: 00000080 {rdi} => 00000000 {} V18 in reg rdi is becoming live [000126] Live regs: 00000048 {rbx rsi} => 000000C8 {rbx rsi rdi} Live vars: {V00 V01 V11} => {V00 V01 V11 V18} GC regs: 00000000 {} => 00000080 {rdi} Generating: N129 ( 1, 1) [000094] ------------ t94 = LCL_VAR int V11 tmp9 u:2 rsi REG rsi Generating: N131 ( 1, 1) [000127] ------------ t127 = LCL_VAR ref V18 tmp16 u:2 rdi REG rdi /--* t127 ref Generating: N133 (???,???) [000163] -c---------- t163 = * LEA(b+8) ref REG NA /--* t163 ref Generating: N135 ( 3, 3) [000130] -c-X-------- t130 = * IND int REG NA /--* t94 int +--* t130 int Generating: N137 ( 8, 11) [000131] ---X-------- * ARR_BOUNDS_CHECK_Rng void REG NA IN001d: cmp esi, dword ptr [rdi+8] IN001e: jae L_M63542_BB04 Generating: N139 ( 1, 1) [000128] ------------ t128 = LCL_VAR ref V18 tmp16 u:2 rdi (last use) REG rdi Generating: N141 ( 1, 1) [000129] ------------ t129 = LCL_VAR int V11 tmp9 u:2 rsi (last use) REG rsi /--* t129 int Generating: N143 ( 2, 3) [000132] ------------ t132 = * CAST long <- int REG rsi V11 in reg rsi is becoming dead [000129] Live regs: 000000C8 {rbx rsi rdi} => 00000088 {rbx rdi} Live vars: {V00 V01 V11 V18} => {V00 V01 V18} IN001f: movsxd rsi, esi /--* t128 ref +--* t132 long Generating: N145 ( 5, 6) [000137] -c---------- t137 = * LEA(b+(i*8)+16) byref REG NA /--* t137 byref Generating: N147 ( 6, 7) [000095] a---G------- t95 = * IND ref REG rdi V18 in reg rdi is becoming dead [000128] Live regs: 00000088 {rbx rdi} => 00000008 {rbx} Live vars: {V00 V01 V18} => {V00 V01} GC regs: 00000080 {rdi} => 00000000 {} IN0020: mov rdi, gword ptr [rdi+8*rsi+16] GC regs: 00000000 {} => 00000080 {rdi} /--* t95 ref Generating: N149 ( 18, 22) [000145] DA-XGO----L- * STORE_LCL_VAR ref V19 tmp17 d:2 NA REG NA GC regs: 00000080 {rdi} => 00000000 {} IN0021: mov gword ptr [V19 rbp-38H], rdi Live vars: {V00 V01} => {V00 V01 V19} GCvars: {} => {V19} Generating: N151 ( 1, 1) [000037] ------------ t37 = LCL_VAR byref V00 this u:1 rbx (last use) REG rbx $80 Generating: N153 ( 1, 1) [000142] -c---------- t142 = CNS_INT long 56 field offset Fseq[m_ParallelSendQueue] REG NA $245 /--* t37 byref +--* t142 long Generating: N155 ( 3, 3) [000143] ------------ t143 = * ADD byref REG rbx $289 V00 in reg rbx is becoming dead [000037] Live regs: 00000008 {rbx} => 00000000 {} Live vars: {V00 V01 V19} => {V01 V19} Byref regs: 00000008 {rbx} => 00000000 {} IN0022: add rbx, 56 Byref regs: 00000000 {} => 00000008 {rbx} /--* t143 byref Generating: N157 ( 9, 7) [000044] nc--GO------ t44 = * OBJ struct REG NA /--* t44 struct Generating: N159 (???,???) [000172] ----GO------ * PUTARG_STK [+0x00] void (7 slots) (RepInstr) REG NA Byref regs: 00000008 {rbx} => 00000000 {} IN0023: lea rdi, [V02 rsp] IN0024: mov rsi, rbx IN0025: mov rcx, gword ptr [rsi] IN0026: mov gword ptr [V02 rsp], rcx IN0027: add rsi, 8 IN0028: add rdi, 8 IN0029: mov ecx, 6 IN002a: rep movsq Generating: N161 ( 1, 1) [000146] -----------z t146 = LCL_VAR ref V19 tmp17 u:2 rdi (last use) REG rdi ScheduleSend: version=0 jobgroup=3466 /--* t146 ref Generating: N163 (???,???) [000173] ------------ t173 = * PUTARG_REG ref REG rdi IN002b: mov rdi, gword ptr [V19 rbp-38H] Removing V19 from gcVarPtrSetCur V19 in reg rdi is becoming live [000146] Live regs: 00000000 {} => 00000080 {rdi} GC regs: 00000000 {} => 00000080 {rdi} V19 in reg rdi is becoming dead [000146] Live regs: 00000080 {rdi} => 00000000 {} Live vars: {V01 V19} => {V01} GC regs: 00000080 {rdi} => 00000000 {} GC regs: 00000000 {} => 00000080 {rdi} Generating: N165 ( 3, 4) [000151] ------------ t151 = LCL_FLD long V01 arg1 u:1[+0] rdx REG rdx $144 IN002c: mov rdx, qword ptr [V01 rbp-20H] /--* t151 long Generating: N167 (???,???) [000174] ------------ t174 = * PUTARG_REG long REG rdx Generating: N169 ( 3, 4) [000152] ------------ t152 = LCL_FLD long V01 arg1 u:1[+8] rcx (last use) REG rcx $145 IN002d: mov rcx, qword ptr [V01+0x8 rbp-18H] Live vars: {V01} => {} /--* t152 long Generating: N171 (???,???) [000175] ------------ t175 = * PUTARG_REG long REG rcx /--* t174 long +--* t175 long Generating: N173 ( 6, 8) [000150] -c---------- t150 = * FIELD_LIST struct REG NA $384 Generating: N175 ( 2, 10) [000124] ------------ t124 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a IN002e: mov r11, 0x7F6678060518 /--* t124 long Generating: N177 (???,???) [000176] -----------Z t176 = * PUTARG_REG long REG r11 reused temp #1, slot 1, size = 8 The register r11 spilled with [000176] IN002f: mov qword ptr [TEMP_01 rbp-40H], r11 Generating: N179 ( 2, 10) [000121] ------------ t121 = CNS_INT(h) long 0x7f6678060518 ftn REG r11 $18a IN0030: mov r11, 0x7F6678060518 /--* t121 long Generating: [000180] ------------ t180 = * COPY long REG rsi /--* t180 long Generating: N181 (???,???) [000177] ------------ t177 = * PUTARG_REG long REG rsi IN0031: mov rsi, r11 Generating: N183 ( 2, 10) [000178] ------------ t178 = CNS_INT(h) long 0x7f6678060518 ftn REG rax IN0032: mov rax, 0x7F6678060518 /--* t178 long Generating: N185 ( 4, 12) [000179] -c---------- t179 = * IND long REG NA /--* t173 ref this in rdi +--* t150 struct arg4 rdx,rcx +--* t176 long arg1 in r11 +--* t177 long arg2 in rsi +--* t179 long control expr Generating: N187 ( 61, 70) [000040] --CXGO------ t40 = * CALLV stub struct Unity.Networking.Transport.INetworkInterface.ScheduleSend REG rax,rdx $385 GC regs: 00000080 {rdi} => 00000000 {} Tree-Node marked unspilled from [000176] IN0033: mov r11, qword ptr [TEMP_01 rbp-40H] release temp #1, slot 1, size = 8 Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0034: call qword ptr [rax]Unity.Networking.Transport.INetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this /--* t40 struct Generating: N189 ( 65, 73) [000123] DA-XGO------ * STORE_LCL_VAR struct V17 tmp15 d:2 NA REG NA IN0035: mov qword ptr [V17 rbp-30H], rax IN0036: mov qword ptr [V17+0x8 rbp-28H], rdx Live vars: {} => {V17} Generating: N191 ( 3, 2) [000153] -c-----N---- t153 = LCL_VAR struct V17 tmp15 u:2 NA (last use) REG NA $388 /--* t153 struct Generating: N193 ( 4, 3) [000045] ----G------- * RETURN struct REG NA $389 Live vars: {V17} => {} **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 IN0037: mov rax, qword ptr [V17 rbp-30H] IN0038: mov rdx, qword ptr [V17+0x8 rbp-28H] Scope info: end block BB02, IL range [025..026) Scope info: open scopes = Added IP mapping: EPILOG STACK_EMPTY (G_M63542_IG03,ins#29,ofs#130) label Reserving epilog IG for block BB02 G_M63542_IG03: ; offs=000089H, funclet=00, bbWeight=1 *************** After placeholder IG creation G_M63542_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M63542_IG02: ; offs=000000H, size=0089H, gcrefRegs=00000000 {}, byrefRegs=00000008 {rbx}, byref G_M63542_IG03: ; offs=000089H, size=0082H, gcrefRegs=00000080 {rdi}, byrefRegs=00000008 {rbx}, byref G_M63542_IG04: ; epilog placeholder, next placeholder=, BB02 [0006], epilog, extend <-- First placeholder <-- Last placeholder ; PrevGCVars= {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000008 {rbx} ; InitGCVars= {}, InitGCrefRegs=00000080 {rdi}, InitByrefRegs=00000008 {rbx} G_M63542_IG05: ; offs=00020BH, size=0000H, gcrefRegs=00000000 {} <-- Current IG =============== Generating BB03 [025..026) (throw), preds={BB01} succs={} flags=0x00000004.400b1020: i rare label target hascall gcsafe LIR BB03 IN (0)={} + ByrefExposed + GcHeap OUT(0)={} Recording Var Locations at start of BB03 Liveness not changing: {} Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M63542_BB03: Label: IG05, GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Scope info: begin block BB03, IL range [025..026) Scope info: open scopes = Added IP mapping: 0x0025 STACK_EMPTY (G_M63542_IG05,ins#0,ofs#0) label Generating: N197 (???,???) [000161] ------------ IL_OFFSET void IL offset: 0x25 REG NA Generating: N199 ( 14, 5) [000096] --CXG------- CALL void System.ThrowHelper.ThrowArgumentOutOfRange_IndexException REG NA $VN.Void Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0039: call System.ThrowHelper:ThrowArgumentOutOfRange_IndexException() Scope info: end block BB03, IL range [025..026) Scope info: open scopes = IN003a: int3 =============== Generating BB04 [???..???) (throw), preds={} succs={} flags=0x00000000.40031070: keep i internal rare label target LIR BB04 IN (0)={} OUT(0)={} Recording Var Locations at start of BB04 Liveness not changing: {} Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M63542_BB04: G_M63542_IG05: ; offs=00020BH, funclet=00, bbWeight=0 Label: IG06, GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Scope info: begin block BB04, IL range [???..???) Scope info: ignoring block beginning Added IP mapping: NO_MAP STACK_EMPTY (G_M63542_IG06,ins#0,ofs#0) label Generating: N203 ( 14, 5) [000164] --CXG------- CALL help void HELPER.CORINFO_HELP_RNGCHKFAIL REG NA Call: GCvars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN003b: call CORINFO_HELP_RNGCHKFAIL Scope info: end block BB04, IL range [???..???) Scope info: ignoring block end IN003c: int3 Liveness not changing: {} 1 tmps used # compCycleEstimate = 230, compSizeEstimate = 226 Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this ; Final local variable assignments ; ; V00 this [V00,T02] ( 4, 4 ) byref -> rbx this ; V01 arg1 [V01,T00] ( 6, 6 ) struct (16) [rbp-0x20] do-not-enreg[SFA] multireg-arg ; V02 OutArgs [V02 ] ( 1, 1 ) lclBlk (56) [rsp+0x00] "OutgoingArgSpace" ; V03 tmp1 [V03,T03] ( 3, 6 ) ref -> r14 class-hnd exact "Single-def Box Helper" ; V04 tmp2 [V04,T04] ( 3, 6 ) ref -> rax class-hnd exact "Single-def Box Helper" ;* V05 tmp3 [V05 ] ( 0, 0 ) ref -> zero-ref class-hnd exact "Inlining Arg" ;* V06 tmp4 [V06 ] ( 0, 0 ) ref -> zero-ref class-hnd exact "Inlining Arg" ;* V07 tmp5 [V07 ] ( 0, 0 ) struct (32) zero-ref "NewObj constructor temp" ;* V08 tmp6 [V08 ] ( 0, 0 ) ref -> zero-ref class-hnd exact "Inlining Arg" ;* V09 tmp7 [V09 ] ( 0, 0 ) ref -> zero-ref class-hnd exact "Inlining Arg" ; V10 tmp8 [V10,T07] ( 2, 4 ) ref -> rsi class-hnd "Inlining Arg" ; V11 tmp9 [V11,T01] ( 4, 8 ) int -> rsi "Inlining Arg" ; V12 tmp10 [V12,T05] ( 3, 6 ) ref -> rdi class-hnd "Inlining Arg" ; V13 tmp11 [V13,T09] ( 2, 2 ) ref -> r14 V07._arg0(offs=0x00) P-INDEP "field V07._arg0 (fldOffset=0x0)" ; V14 tmp12 [V14,T10] ( 2, 2 ) ref -> rax V07._arg1(offs=0x08) P-INDEP "field V07._arg1 (fldOffset=0x8)" ;* V15 tmp13 [V15,T13] ( 0, 0 ) ref -> zero-ref V07._arg2(offs=0x10) P-INDEP "field V07._arg2 (fldOffset=0x10)" ; V16 tmp14 [V16,T11] ( 2, 2 ) ref -> rsi V07._args(offs=0x18) P-INDEP "field V07._args (fldOffset=0x18)" ; V17 tmp15 [V17,T12] ( 2, 2 ) struct (16) [rbp-0x30] do-not-enreg[SR] multireg-ret must-init "Return value temp for multi-reg return (rejected tail call)." ; V18 tmp16 [V18,T06] ( 3, 6 ) ref -> rdi "arr expr" ; V19 tmp17 [V19,T08] ( 2, 4 ) ref -> [rbp-0x38] "argument with side effect" ; TEMP_01 long -> [rbp-0x40] ; ; Lcl frame size = 112 *************** Before prolog / epilog generation G_M63542_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M63542_IG02: ; offs=000000H, size=0089H, gcrefRegs=00000000 {}, byrefRegs=00000008 {rbx}, byref G_M63542_IG03: ; offs=000089H, size=0082H, gcrefRegs=00000080 {rdi}, byrefRegs=00000008 {rbx}, byref G_M63542_IG04: ; epilog placeholder, next placeholder=, BB02 [0006], epilog, extend <-- First placeholder <-- Last placeholder ; PrevGCVars= {}, PrevGCrefRegs=00000000 {}, PrevByrefRegs=00000008 {rbx} ; InitGCVars= {}, InitGCrefRegs=00000080 {rdi}, InitByrefRegs=00000008 {rbx} G_M63542_IG05: ; offs=00020BH, size=0006H, gcVars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref G_M63542_IG06: ; offs=000211H, size=0000H, gcrefRegs=00000000 {} <-- Current IG Recording Var Locations at start of BB01 V00(rbx) G_M63542_IG06: ; offs=000211H, funclet=00, bbWeight=0 *************** In genFnProlog() Added IP mapping to front: PROLOG STACK_EMPTY (G_M63542_IG01,ins#0,ofs#0) label __prolog: **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 Found 4 lvMustInit int-sized stack slots, frame offsets 48 through 32 IN003d: push rbp IN003e: push r14 IN003f: push rbx IN0040: sub rsp, 112 IN0041: lea rbp, [rsp+80H] IN0042: xor rax, rax IN0043: mov qword ptr [V17 rbp-30H], rax IN0044: mov qword ptr [V17+0x8 rbp-28H], rax *************** In genClearStackVec3ArgUpperBits() *************** In genFnPrologCalleeRegArgs() for int regs **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 IN0045: mov qword ptr [V01 rbp-20H], rsi IN0046: mov qword ptr [V01+0x8 rbp-18H], rdx IN0047: mov rbx, rdi *************** In genEnregisterIncomingStackArgs() 1 tracked GC refs are at stack offsets -0038 ... FFFFFFD0 G_M63542_IG01: ; offs=000000H, funclet=00, bbWeight=1 *************** In genFnEpilog() __epilog: gcVarPtrSetCur= {}, gcRegGCrefSetCur=00000080 {rdi}, gcRegByrefSetCur=00000008 {rbx} IN0048: lea rsp, [rbp-10H] IN0049: pop rbx IN004a: pop r14 IN004b: pop rbp IN004c: ret G_M63542_IG04: ; offs=00010BH, funclet=00, bbWeight=1 0 prologs, 1 epilogs, 0 funclet prologs, 0 funclet epilogs *************** After prolog / epilog generation G_M63542_IG01: ; func=00, offs=000000H, size=0025H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG G_M63542_IG02: ; offs=000025H, size=0089H, gcrefRegs=00000000 {}, byrefRegs=00000008 {rbx}, byref G_M63542_IG03: ; offs=0000AEH, size=0082H, gcrefRegs=00000080 {rdi}, byrefRegs=00000008 {rbx}, byref G_M63542_IG04: ; offs=000130H, size=0009H, epilog, nogc, extend G_M63542_IG05: ; offs=000139H, size=0006H, gcVars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref G_M63542_IG06: ; offs=00013FH, size=0006H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref *************** In emitJumpDistBind() Binding: IN001b: 000000 jae L_M63542_BB03 Binding L_M63542_BB03 to G_M63542_IG05 Estimate of fwd jump [A640DDBC/027]: 00A8 -> 0139 = 008F Adjusted offset of BB03 from 00AE to 00AE Binding: IN001e: 000000 jae L_M63542_BB04 Binding L_M63542_BB04 to G_M63542_IG06 Estimate of fwd jump [A640E57C/030]: 00B5 -> 013F = 0088 *************** Finishing PHASE Generate code *************** Starting PHASE Emit code Hot code size = 0x145 bytes Cold code size = 0x0 bytes reserveUnwindInfo(isFunclet=FALSE, isColdCode=FALSE, unwindSize=0xc) *************** In emitEndCodeGen() Converting emitMaxStackDepth from bytes (0) to elements (0) *************************************************************************** Instructions as they come out of the scheduler G_M63542_IG01: ; func=00, offs=000000H, size=0025H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG IN003d: 000000 55 push rbp IN003e: 000001 4156 push r14 IN003f: 000003 53 push rbx IN0040: 000004 4883EC70 sub rsp, 112 IN0041: 000008 488DAC2480000000 lea rbp, [rsp+80H] IN0042: 000010 33C0 xor rax, rax IN0043: 000012 488945D0 mov qword ptr [rbp-30H], rax IN0044: 000016 488945D8 mov qword ptr [rbp-28H], rax IN0045: 00001A 488975E0 mov qword ptr [rbp-20H], rsi IN0046: 00001E 488955E8 mov qword ptr [rbp-18H], rdx byrReg +[rbx] IN0047: 000022 488BDF mov rbx, rdi ;; bbWeight=1 PerfScore 8.25 G_M63542_IG02: ; func=00, offs=000025H, size=0089H, gcrefRegs=00000000 {}, byrefRegs=00000008 {rbx}, byref IN0001: 000025 48BFF027C178667F0000 mov rdi, 0x7F6678C127F0 New gcrReg live regs=00000001 {rax} ; Call at 002F [stk=0], GCvars=none, gcrefRegs=00000001 {rax}, byrefRegs=00000008 {rbx} IN0002: 00002F E8DC065677 call CORINFO_HELP_NEWSFAST gcrReg +[r14] IN0003: 000034 4C8BF0 mov r14, rax IN0004: 000037 488B7DE0 mov rdi, qword ptr [rbp-20H] IN0005: 00003B 49897E08 mov qword ptr [r14+8], rdi IN0006: 00003F 48BFC0B1BE78667F0000 mov rdi, 0x7F6678BEB1C0 ; Call at 0049 [stk=0], GCvars=none, gcrefRegs=00004001 {rax r14}, byrefRegs=00000008 {rbx} IN0007: 000049 E8C2065677 call CORINFO_HELP_NEWSFAST IN0008: 00004E 8B75E8 mov esi, dword ptr [rbp-18H] IN0009: 000051 897008 mov dword ptr [rax+8], esi IN000a: 000054 48BE40F3FF63667F0000 mov rsi, 0x7F6663FFF340 gcrReg +[rsi] IN000b: 00005E 488B36 mov rsi, gword ptr [rsi] gcrReg +[rdi] IN000c: 000061 33FF xor rdi, rdi IN000d: 000063 4C893424 mov gword ptr [rsp], r14 IN000e: 000067 4889442408 mov gword ptr [rsp+08H], rax IN000f: 00006C 48897C2410 mov gword ptr [rsp+10H], rdi IN0010: 000071 4889742418 mov gword ptr [rsp+18H], rsi gcrReg -[rsi] IN0011: 000076 48BE988A0064667F0000 mov rsi, 0x7F6664008A98 gcrReg +[rsi] IN0012: 000080 488B36 mov rsi, gword ptr [rsi] New gcrReg live regs=00000001 {rax} ; Call at 0083 [stk=0], GCvars=none, gcrefRegs=00000001 {rax}, byrefRegs=00000008 {rbx} IN0013: 000083 E840CB18FE call System.String:FormatHelper(System.IFormatProvider,System.String,System.ParamsArray):System.String gcrReg +[rsi] IN0014: 000088 488BF0 mov rsi, rax IN0015: 00008B BF03000000 mov edi, 3 New gcrReg live regs=00000000 {} ; Call at 0090 [stk=0], GCvars=none, gcrefRegs=00000000 {}, byrefRegs=00000008 {rbx} IN0016: 000090 E853B7BCFE call UnityEngine.Debug:ProcessAndLogInternal(int,System.Object) IN0017: 000095 48BF68460064667F0000 mov rdi, 0x7F6664004668 gcrReg +[rdi] IN0018: 00009F 488B3F mov rdi, gword ptr [rdi] IN0019: 0000A2 8B7310 mov esi, dword ptr [rbx+16] IN001a: 0000A5 3B7710 cmp esi, dword ptr [rdi+16] IN001b: 0000A8 0F838B000000 jae G_M63542_IG05 ;; bbWeight=1 PerfScore 25.25 G_M63542_IG03: ; func=00, offs=0000AEH, size=0082H, gcrefRegs=00000080 {rdi}, byrefRegs=00000008 {rbx}, byref IN001c: 0000AE 488B7F08 mov rdi, gword ptr [rdi+8] IN001d: 0000B2 3B7708 cmp esi, dword ptr [rdi+8] IN001e: 0000B5 0F8384000000 jae G_M63542_IG06 IN001f: 0000BB 4863F6 movsxd rsi, esi IN0020: 0000BE 488B7CF710 mov rdi, gword ptr [rdi+8*rsi+16] [A640F2C0] gcr var born at [rbp-38H] IN0021: 0000C3 48897DC8 mov gword ptr [rbp-38H], rdi IN0022: 0000C7 4883C338 add rbx, 56 gcrReg -[rdi] IN0023: 0000CB 488D3C24 lea rdi, [rsp] byrReg +[rsi] IN0024: 0000CF 488BF3 mov rsi, rbx gcrReg +[rcx] IN0025: 0000D2 488B0E mov rcx, gword ptr [rsi] IN0026: 0000D5 48890C24 mov gword ptr [rsp], rcx IN0027: 0000D9 4883C608 add rsi, 8 IN0028: 0000DD 4883C708 add rdi, 8 gcrReg -[rcx] IN0029: 0000E1 B906000000 mov ecx, 6 IN002a: 0000E6 F348A5 rep movsq gcrReg +[rdi] IN002b: 0000E9 488B7DC8 mov rdi, gword ptr [rbp-38H] IN002c: 0000ED 488B55E0 mov rdx, qword ptr [rbp-20H] IN002d: 0000F1 488B4DE8 mov rcx, qword ptr [rbp-18H] IN002e: 0000F5 49BB18050678667F0000 mov r11, 0x7F6678060518 IN002f: 0000FF 4C895DC0 mov qword ptr [rbp-40H], r11 IN0030: 000103 49BB18050678667F0000 mov r11, 0x7F6678060518 byrReg -[rsi] IN0031: 00010D 498BF3 mov rsi, r11 IN0032: 000110 48B818050678667F0000 mov rax, 0x7F6678060518 IN0033: 00011A 4C8B5DC0 mov r11, qword ptr [rbp-40H] New GC ref live vars= {} [A640F2C0] gcr var died at [rbp-38H] New gcrReg live regs=00000000 {} New byrReg live regs=00000000 {} ; Call at 011E [stk=0], GCvars=none, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0034: 00011E FF10 call qword ptr [rax]Unity.Networking.Transport.INetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this IN0035: 000120 488945D0 mov qword ptr [rbp-30H], rax IN0036: 000124 488955D8 mov qword ptr [rbp-28H], rdx IN0037: 000128 488B45D0 mov rax, qword ptr [rbp-30H] IN0038: 00012C 488B55D8 mov rdx, qword ptr [rbp-28H] ;; bbWeight=1 PerfScore 51.00 G_M63542_IG04: ; func=00, offs=000130H, size=0009H, epilog, nogc, extend IN0048: 000130 488D65F0 lea rsp, [rbp-10H] IN0049: 000134 5B pop rbx IN004a: 000135 415E pop r14 IN004b: 000137 5D pop rbp IN004c: 000138 C3 ret ;; bbWeight=1 PerfScore 3.00 G_M63542_IG05: ; func=00, offs=000139H, size=0006H, gcVars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref ; Call at 0139 [stk=0], GCvars=none, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN0039: 000139 E862171BFE call System.ThrowHelper:ThrowArgumentOutOfRange_IndexException() IN003a: 00013E CC int3 ;; bbWeight=0 PerfScore 0.00 G_M63542_IG06: ; func=00, offs=00013FH, size=0006H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref ; Call at 013F [stk=0], GCvars=none, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN003b: 00013F E80C9D5677 call CORINFO_HELP_RNGCHKFAIL IN003c: 000144 CC int3 ;; bbWeight=0 PerfScore 0.00Allocated method code size = 325 , actual size = 325 ; Total bytes of code 325, prolog size 26, PerfScore 120.00, (MethodHash=853e07c9) for method Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this ; ============================================================ *************** After end code gen, before unwindEmit() G_M63542_IG01: ; func=00, offs=000000H, size=0025H, bbWeight=1 PerfScore 8.25, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, nogc <-- Prolog IG IN003d: 000000 push rbp IN003e: 000001 push r14 IN003f: 000003 push rbx IN0040: 000004 sub rsp, 112 IN0041: 000008 lea rbp, [rsp+80H] IN0042: 000010 xor rax, rax IN0043: 000012 mov qword ptr [V17 rbp-30H], rax IN0044: 000016 mov qword ptr [V17+0x8 rbp-28H], rax IN0045: 00001A mov qword ptr [V01 rbp-20H], rsi IN0046: 00001E mov qword ptr [V01+0x8 rbp-18H], rdx IN0047: 000022 mov rbx, rdi G_M63542_IG02: ; offs=000025H, size=0089H, bbWeight=1 PerfScore 25.25, gcrefRegs=00000000 {}, byrefRegs=00000008 {rbx}, byref IN0001: 000025 mov rdi, 0x7F6678C127F0 IN0002: 00002F call CORINFO_HELP_NEWSFAST IN0003: 000034 mov r14, rax IN0004: 000037 mov rdi, qword ptr [V01 rbp-20H] IN0005: 00003B mov qword ptr [r14+8], rdi IN0006: 00003F mov rdi, 0x7F6678BEB1C0 IN0007: 000049 call CORINFO_HELP_NEWSFAST IN0008: 00004E mov esi, dword ptr [V01+0x8 rbp-18H] IN0009: 000051 mov dword ptr [rax+8], esi IN000a: 000054 mov rsi, 0x7F6663FFF340 IN000b: 00005E mov rsi, gword ptr [rsi] IN000c: 000061 xor rdi, rdi IN000d: 000063 mov gword ptr [V02 rsp], r14 IN000e: 000067 mov gword ptr [V02+0x8 rsp+08H], rax IN000f: 00006C mov gword ptr [V02+0x10 rsp+10H], rdi IN0010: 000071 mov gword ptr [V02+0x18 rsp+18H], rsi IN0011: 000076 mov rsi, 0x7F6664008A98 IN0012: 000080 mov rsi, gword ptr [rsi] IN0013: 000083 call System.String:FormatHelper(System.IFormatProvider,System.String,System.ParamsArray):System.String IN0014: 000088 mov rsi, rax IN0015: 00008B mov edi, 3 IN0016: 000090 call UnityEngine.Debug:ProcessAndLogInternal(int,System.Object) IN0017: 000095 mov rdi, 0x7F6664004668 IN0018: 00009F mov rdi, gword ptr [rdi] IN0019: 0000A2 mov esi, dword ptr [rbx+16] IN001a: 0000A5 cmp esi, dword ptr [rdi+16] IN001b: 0000A8 jae G_M63542_IG05 G_M63542_IG03: ; offs=0000AEH, size=0082H, bbWeight=1 PerfScore 51.00, gcrefRegs=00000080 {rdi}, byrefRegs=00000008 {rbx}, byref IN001c: 0000AE mov rdi, gword ptr [rdi+8] IN001d: 0000B2 cmp esi, dword ptr [rdi+8] IN001e: 0000B5 jae G_M63542_IG06 IN001f: 0000BB movsxd rsi, esi IN0020: 0000BE mov rdi, gword ptr [rdi+8*rsi+16] IN0021: 0000C3 mov gword ptr [V19 rbp-38H], rdi IN0022: 0000C7 add rbx, 56 IN0023: 0000CB lea rdi, [V02 rsp] IN0024: 0000CF mov rsi, rbx IN0025: 0000D2 mov rcx, gword ptr [rsi] IN0026: 0000D5 mov gword ptr [V02 rsp], rcx IN0027: 0000D9 add rsi, 8 IN0028: 0000DD add rdi, 8 IN0029: 0000E1 mov ecx, 6 IN002a: 0000E6 rep movsq IN002b: 0000E9 mov rdi, gword ptr [V19 rbp-38H] IN002c: 0000ED mov rdx, qword ptr [V01 rbp-20H] IN002d: 0000F1 mov rcx, qword ptr [V01+0x8 rbp-18H] IN002e: 0000F5 mov r11, 0x7F6678060518 IN002f: 0000FF mov qword ptr [TEMP_01 rbp-40H], r11 IN0030: 000103 mov r11, 0x7F6678060518 IN0031: 00010D mov rsi, r11 IN0032: 000110 mov rax, 0x7F6678060518 IN0033: 00011A mov r11, qword ptr [TEMP_01 rbp-40H] IN0034: 00011E call qword ptr [rax]Unity.Networking.Transport.INetworkInterface:ScheduleSend(Unity.Collections.NativeQueue`1[QueuedSendMessage],Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this IN0035: 000120 mov qword ptr [V17 rbp-30H], rax IN0036: 000124 mov qword ptr [V17+0x8 rbp-28H], rdx IN0037: 000128 mov rax, qword ptr [V17 rbp-30H] IN0038: 00012C mov rdx, qword ptr [V17+0x8 rbp-28H] G_M63542_IG04: ; offs=000130H, size=0009H, bbWeight=1 PerfScore 3.00, epilog, nogc, extend IN0048: 000130 lea rsp, [rbp-10H] IN0049: 000134 pop rbx IN004a: 000135 pop r14 IN004b: 000137 pop rbp IN004c: 000138 ret G_M63542_IG05: ; offs=000139H, size=0006H, bbWeight=0 PerfScore 0.00, gcVars= {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref IN0039: 000139 call System.ThrowHelper:ThrowArgumentOutOfRange_IndexException() IN003a: 00013E int3 G_M63542_IG06: ; offs=00013FH, size=0006H, bbWeight=0 PerfScore 0.00, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref IN003b: 00013F call CORINFO_HELP_RNGCHKFAIL IN003c: 000144 int3 *************** Finishing PHASE Emit code *************** Starting PHASE Emit GC+EH tables Unwind Info: >> Start offset : 0x000000 (not in unwind data) >> End offset : 0x000145 (not in unwind data) Version : 1 Flags : 0x00 SizeOfProlog : 0x08 CountOfUnwindCodes: 4 FrameRegister : none (0) FrameOffset : N/A (no FrameRegister) (Value=0) UnwindCodes : CodeOffset: 0x08 UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 13 * 8 + 8 = 112 = 0x70 CodeOffset: 0x04 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbx (3) CodeOffset: 0x03 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: r14 (14) CodeOffset: 0x01 UnwindOp: UWOP_PUSH_NONVOL (0) OpInfo: rbp (5) allocUnwindInfo(pHotCode=0x00007F667A9B8B50, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x145, unwindSize=0xc, pUnwindBlock=0x0000559EA6649D8C, funKind=0 (main function)) *************** In genIPmappingGen() IP mapping count : 6 IL offs PROLOG : 0x00000000 ( STACK_EMPTY ) IL offs 0x0000 : 0x00000025 ( STACK_EMPTY ) IL offs 0x0025 : 0x00000095 ( STACK_EMPTY ) IL offs EPILOG : 0x00000130 ( STACK_EMPTY ) IL offs 0x0025 : 0x00000139 ( STACK_EMPTY ) IL offs NO_MAP : 0x0000013F ( STACK_EMPTY ) *************** In genSetScopeInfo() VarLocInfo count is 6 *************** Variable debug info 6 live ranges 0( UNKNOWN) : From 00000000h to 00000025h, in rdi 1( UNKNOWN) : From 00000000h to 00000025h, in rsi 0( UNKNOWN) : From 00000025h to 000000AEh, in rbx 1( UNKNOWN) : From 00000025h to 000000AEh, in rbp[-32] (1 slot) 0( UNKNOWN) : From 000000AEh to 000000C7h, in rbx 1( UNKNOWN) : From 000000AEh to 000000F5h, in rbp[-32] (1 slot) *************** In gcInfoBlockHdrSave() Set code length to 325. **** getSystemVAmd64PassStructInRegisterDescriptor(0x795c7a00 (Unity.Jobs.JobHandle), ...) => passedInRegisters = true eightByteCount = 2 eightByte #0 -- classification: Integer, byteSize: 8, byteOffset: 0 eightByte #1 -- classification: Integer, byteSize: 8, byteOffset: 8 Set ReturnKind to Scalar. Set stack base register to rbp. Set Outgoing stack arg area size to 56. Stack slot id for offset -56 (0xffffffc8) (frame) = 0. Register slot id for reg rbx (byref) = 1. Register slot id for reg r14 = 2. Set state of slot 0 at instr offset 0xc7 to Live. Set state of slot 0 at instr offset 0x11e to Dead. Set state of slot 1 at instr offset 0x2f to Live. Set state of slot 1 at instr offset 0x34 to Dead. Set state of slot 1 at instr offset 0x49 to Live. Set state of slot 2 at instr offset 0x49 to Live. Set state of slot 1 at instr offset 0x4e to Dead. Set state of slot 2 at instr offset 0x4e to Dead. Set state of slot 1 at instr offset 0x83 to Live. Set state of slot 1 at instr offset 0x88 to Dead. Set state of slot 1 at instr offset 0x90 to Live. Set state of slot 1 at instr offset 0x95 to Dead. Defining 7 call sites: Offset 0x2f, size 5. Offset 0x49, size 5. Offset 0x83, size 5. Offset 0x90, size 5. Offset 0x11e, size 2. Offset 0x139, size 5. Offset 0x13f, size 5. *************** Finishing PHASE Emit GC+EH tables Method code size: 325 Allocations for Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this (MethodHash=853e07c9) count: 2166, size: 168109, max = 3072 allocateMemory: 196608, nraUsed: 173936 Alloc'd bytes by kind: kind | size | pct ---------------------+------------+-------- AssertionProp | 6460 | 3.84% ASTNode | 26840 | 15.97% InstDesc | 7572 | 4.50% ImpStack | 384 | 0.23% BasicBlock | 3360 | 2.00% fgArgInfo | 1152 | 0.69% fgArgInfoPtrArr | 248 | 0.15% FlowList | 160 | 0.10% TreeStatementList | 0 | 0.00% SiScope | 512 | 0.30% DominatorMemory | 192 | 0.11% LSRA | 3252 | 1.93% LSRA_Interval | 4240 | 2.52% LSRA_RefPosition | 14272 | 8.49% Reachability | 16 | 0.01% SSA | 1488 | 0.89% ValueNumber | 20348 | 12.10% LvaTable | 5000 | 2.97% UnwindInfo | 0 | 0.00% hashBv | 120 | 0.07% bitset | 416 | 0.25% FixedBitVect | 84 | 0.05% Generic | 4170 | 2.48% LocalAddressVisitor | 0 | 0.00% FieldSeqStore | 744 | 0.44% ZeroOffsetFieldMap | 200 | 0.12% ArrayInfoMap | 192 | 0.11% MemoryPhiArg | 0 | 0.00% CSE | 2704 | 1.61% GC | 2779 | 1.65% CorTailCallInfo | 0 | 0.00% Inlining | 5152 | 3.06% ArrayStack | 256 | 0.15% DebugInfo | 272 | 0.16% DebugOnly | 49402 | 29.39% Codegen | 1184 | 0.70% LoopOpt | 0 | 0.00% LoopHoist | 0 | 0.00% Unknown | 866 | 0.52% RangeCheck | 1376 | 0.82% CopyProp | 1712 | 1.02% SideEffects | 0 | 0.00% ObjectAllocator | 0 | 0.00% VariableLiveRanges | 0 | 0.00% ClassLayout | 152 | 0.09% TailMergeThrows | 0 | 0.00% EarlyProp | 0 | 0.00% ZeroInit | 832 | 0.49% ****** DONE compiling Unity.Networking.Transport.NetworkDriver:ScheduleFlushSend(Unity.Jobs.JobHandle):Unity.Jobs.JobHandle:this ScheduleSend: version=0 jobgroup=3472 RPCSystem: jobgroup=3498 version=0 ScheduleFlushSend: jobgroup=3498 version=0 ScheduleSend: version=3498 jobgroup=140078077052184 The system Unity.NetCode.RpcSystem reads Unity.NetCode.NetworkStreamConnection via Unity.NetCode.RpcSystem/RpcErrorReportingJob but that type was not assigned to the Dependency property. To ensure correct behavior of other systems, the job or a dependency must be assigned to the Dependency property before returning from the OnUpdate method. at Unity.Entities.SystemBase.Update() in /home/kevinmv/dev/dots/Samples/Packages/com.unity.entities/Unity.Entities/SystemBase.cs:line 439 at Unity.Entities.ComponentSystemGroup.UpdateAllSystems() in /home/kevinmv/dev/dots/Samples/Packages/com.unity.entities/Unity.Entities/ComponentSystemGroup.cs:line 460 The system Unity.NetCode.RpcSystem reads Unity.NetCode.NetworkStreamConnection via Unity.NetCode.RpcSystem/RpcErrorReportingJob but that type was not assigned to the Dependency property. To ensure correct behavior of other systems, the job or a dependency must be assigned to the Dependency property before returning from the OnUpdate method. at Unity.Entities.SystemBase.Update() in /home/kevinmv/dev/dots/Samples/Packages/com.unity.entities/Unity.Entities/SystemBase.cs:line 439 at Unity.Entities.ComponentSystemGroup.UpdateAllSystems() in /home/kevinmv/dev/dots/Samples/Packages/com.unity.entities/Unity.Entities/ComponentSystemGroup.cs:line 460 at Unity.NetCode.ServerSimulationSystemGroup.OnUpdate() in /home/kevinmv/dev/netcode/com.unity.netcode/Runtime/ClientServerWorld/ServerSimulationSystemGroup.cs:line 75 at Unity.Entities.ComponentSystem.Update() in /home/kevinmv/dev/dots/Samples/Packages/com.unity.entities/Unity.Entities/ComponentSystem.cs:line 128 at Unity.Entities.ComponentSystemGroup.UpdateAllSystems() in /home/kevinmv/dev/dots/Samples/Packages/com.unity.entities/Unity.Entities/ComponentSystemGroup.cs:line 460 The system Unity.NetCode.RpcSystem reads Unity.NetCode.NetworkStreamConnection via Unity.NetCode.RpcSystem/RpcErrorReportingJob but that type was not assigned to the Dependency property. To ensure correct behavior of other systems, the job or a dependency must be assigned to the Dependency property before returning from the OnUpdate method. at Unity.Entities.SystemBase.Update() in /home/kevinmv/dev/dots/Samples/Packages/com.unity.entities/Unity.Entities/SystemBase.cs:line 439 at Unity.Entities.ComponentSystemGroup.UpdateAllSystems() in /home/kevinmv/dev/dots/Samples/Packages/com.unity.entities/Unity.Entities/ComponentSystemGroup.cs:line 460 at Unity.NetCode.ServerSimulationSystemGroup.OnUpdate() in /home/kevinmv/dev/netcode/com.unity.netcode/Runtime/ClientServerWorld/ServerSimulationSystemGroup.cs:line 75 at Unity.Entities.ComponentSystem.Update() in /home/kevinmv/dev/dots/Samples/Packages/com.unity.entities/Unity.Entities/ComponentSystem.cs:line 128 at Unity.Entities.ComponentSystemGroup.UpdateAllSystems() in /home/kevinmv/dev/dots/Samples/Packages/com.unity.entities/Unity.Entities/ComponentSystemGroup.cs:line 460 at Unity.Entities.ComponentSystem.Update() in /home/kevinmv/dev/dots/Samples/Packages/com.unity.entities/Unity.Entities/ComponentSystem.cs:line 128 at Unity.Entities.ComponentSystemGroup.UpdateAllSystems() in /home/kevinmv/dev/dots/Samples/Packages/com.unity.entities/Unity.Entities/ComponentSystemGroup.cs:line 460