diff --git a/boot/zephyr/CMakeLists.txt b/boot/zephyr/CMakeLists.txt
index a2a911e98..4362b296d 100644
--- a/boot/zephyr/CMakeLists.txt
+++ b/boot/zephyr/CMakeLists.txt
@@ -343,3 +343,9 @@ zephyr_library_sources(
   ${BOOT_DIR}/zephyr/arm_cleanup.c
 )
 endif()
+
+if(CONFIG_MCUBOOT_NRF_CLEANUP_PERIPHERAL)
+zephyr_library_sources(
+  ${BOOT_DIR}/zephyr/nrf_cleanup.c
+)
+endif()
diff --git a/boot/zephyr/include/nrf_cleanup.h b/boot/zephyr/include/nrf_cleanup.h
new file mode 100644
index 000000000..6b04cedfe
--- /dev/null
+++ b/boot/zephyr/include/nrf_cleanup.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2020 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+#ifndef H_NRF_CLEANUP_
+#define H_NRF_CLEANUP_
+
+/**
+ * Perform cleanup on some peripheral resources used by MCUBoot prior chainload
+ * the application.
+ *
+ * This function disables all RTC instances and UARTE instances.
+ * It Disables their interrupts signals as well.
+ */
+void nrf_cleanup_peripheral(void);
+
+#endif
diff --git a/boot/zephyr/main.c b/boot/zephyr/main.c
index bd96f6cc9..20129e050 100644
--- a/boot/zephyr/main.c
+++ b/boot/zephyr/main.c
@@ -123,6 +123,10 @@ K_SEM_DEFINE(boot_log_sem, 1, 1);
 #include <pm_config.h>
 #endif
 
+#if CONFIG_MCUBOOT_NRF_CLEANUP_PERIPHERAL
+#include <nrf_cleanup.h>
+#endif
+
 #ifdef CONFIG_SOC_FAMILY_NRF
 #include <helpers/nrfx_reset_reason.h>
 
@@ -242,7 +246,9 @@ static void do_boot(struct boot_rsp *rsp)
     }
 #endif
 #endif
-
+#if CONFIG_MCUBOOT_NRF_CLEANUP_PERIPHERAL
+    nrf_cleanup_peripheral();
+#endif
 #if CONFIG_MCUBOOT_CLEANUP_ARM_CORE
     cleanup_arm_nvic(); /* cleanup NVIC registers */
 
diff --git a/boot/zephyr/nrf_cleanup.c b/boot/zephyr/nrf_cleanup.c
new file mode 100644
index 000000000..5bab26b24
--- /dev/null
+++ b/boot/zephyr/nrf_cleanup.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2020 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+#include <hal/nrf_clock.h>
+#if defined(NRF_UARTE0) || defined(NRF_UARTE1)
+    #include <hal/nrf_uarte.h>
+#endif
+#if defined(NRF_RTC0) || defined(NRF_RTC1) || defined(NRF_RTC2)
+    #include <hal/nrf_rtc.h>
+#endif
+#if defined(NRF_PPI)
+    #include <hal/nrf_ppi.h>
+#endif
+#if defined(NRF_DPPIC)
+    #include <hal/nrf_dppi.h>
+#endif
+
+#include <string.h>
+
+#define NRF_UARTE_SUBSCRIBE_CONF_OFFS offsetof(NRF_UARTE_Type, SUBSCRIBE_STARTRX)
+#define NRF_UARTE_SUBSCRIBE_CONF_SIZE (offsetof(NRF_UARTE_Type, EVENTS_CTS) -\
+                                       NRF_UARTE_SUBSCRIBE_CONF_OFFS)
+
+#define NRF_UARTE_PUBLISH_CONF_OFFS offsetof(NRF_UARTE_Type, PUBLISH_CTS)
+#define NRF_UARTE_PUBLISH_CONF_SIZE (offsetof(NRF_UARTE_Type, SHORTS) -\
+                                     NRF_UARTE_PUBLISH_CONF_OFFS)
+
+#if defined(NRF_RTC0) || defined(NRF_RTC1) || defined(NRF_RTC2)
+static inline void nrf_cleanup_rtc(NRF_RTC_Type * rtc_reg)
+{
+    nrf_rtc_task_trigger(rtc_reg, NRF_RTC_TASK_STOP);
+    nrf_rtc_event_disable(rtc_reg, 0xFFFFFFFF);
+    nrf_rtc_int_disable(rtc_reg, 0xFFFFFFFF);
+}
+#endif
+
+static void nrf_cleanup_clock(void)
+{
+    nrf_clock_int_disable(NRF_CLOCK, 0xFFFFFFFF);
+}
+
+void nrf_cleanup_peripheral(void)
+{
+#if defined(NRF_RTC0)
+    nrf_cleanup_rtc(NRF_RTC0);
+#endif
+#if defined(NRF_RTC1)
+    nrf_cleanup_rtc(NRF_RTC1);
+#endif
+#if defined(NRF_RTC2)
+    nrf_cleanup_rtc(NRF_RTC2);
+#endif
+#if defined(NRF_UARTE0)
+    nrf_uarte_disable(NRF_UARTE0);
+    nrf_uarte_int_disable(NRF_UARTE0, 0xFFFFFFFF);
+#if defined(NRF_DPPIC)
+    /* Clear all SUBSCRIBE configurations. */
+    memset((uint8_t *)NRF_UARTE0 + NRF_UARTE_SUBSCRIBE_CONF_OFFS, 0, NRF_UARTE_SUBSCRIBE_CONF_SIZE);
+    /* Clear all PUBLISH configurations. */
+    memset((uint8_t *)NRF_UARTE0 + NRF_UARTE_PUBLISH_CONF_OFFS, 0, NRF_UARTE_PUBLISH_CONF_SIZE);
+#endif
+#endif
+#if defined(NRF_UARTE1)
+    nrf_uarte_disable(NRF_UARTE1);
+    nrf_uarte_int_disable(NRF_UARTE1, 0xFFFFFFFF);
+#if defined(NRF_DPPIC)
+    /* Clear all SUBSCRIBE configurations. */
+    memset((uint8_t *)NRF_UARTE1 + NRF_UARTE_SUBSCRIBE_CONF_OFFS, 0, NRF_UARTE_SUBSCRIBE_CONF_SIZE);
+    /* Clear all PUBLISH configurations. */
+    memset((uint8_t *)NRF_UARTE1 + NRF_UARTE_PUBLISH_CONF_OFFS, 0, NRF_UARTE_PUBLISH_CONF_SIZE);
+#endif
+#endif
+#if defined(NRF_PPI)
+    nrf_ppi_channels_disable_all(NRF_PPI);
+#endif
+#if defined(NRF_DPPIC)
+    nrf_dppi_channels_disable_all(NRF_DPPIC);
+#endif
+    nrf_cleanup_clock();
+}