From f5c84d671db102172808c4786f8aeac819a1b34d Mon Sep 17 00:00:00 2001 From: daquintero Date: Sat, 19 Oct 2024 15:24:25 +0200 Subject: [PATCH] Ok we're in a good state now --- .../07_full_flow_demo_electronic_photonic.py | 10 +++---- .../full_flow_demo/src/truth_table_module.v | 26 +++++++++---------- .../full_flow_demo/src/truth_table_module.v | 26 +++++++++---------- piel/file_system.py | 4 ++- 4 files changed, 33 insertions(+), 33 deletions(-) diff --git a/docs/examples/07_full_flow_demo_electronic_photonic/07_full_flow_demo_electronic_photonic.py b/docs/examples/07_full_flow_demo_electronic_photonic/07_full_flow_demo_electronic_photonic.py index fd2f2c43..b62c77ad 100644 --- a/docs/examples/07_full_flow_demo_electronic_photonic/07_full_flow_demo_electronic_photonic.py +++ b/docs/examples/07_full_flow_demo_electronic_photonic/07_full_flow_demo_electronic_photonic.py @@ -538,21 +538,19 @@ def create_switch_fabric(): # ## 3b. Digital Chip Implementation -component = piel.flows.get_latest_digital_run_component( +component = piel.flows.layout_truth_table( + truth_table=truth_table, module=full_flow_demo, ) -component.plot() -component = piel.flows.layout_truth_table( - truth_table=truth_table, +component = piel.flows.get_latest_digital_run_component( module=full_flow_demo, ) +component.plot() print("Truth Table Layout") component -# ### 4a. - # ## 4a. Driver-Amplfier Modelling # Now we will create a amplifier model using `sky130` components. diff --git a/docs/examples/07_full_flow_demo_electronic_photonic/full_flow_demo/full_flow_demo/src/truth_table_module.v b/docs/examples/07_full_flow_demo_electronic_photonic/full_flow_demo/full_flow_demo/src/truth_table_module.v index 19df173f..0c218fda 100644 --- a/docs/examples/07_full_flow_demo_electronic_photonic/full_flow_demo/full_flow_demo/src/truth_table_module.v +++ b/docs/examples/07_full_flow_demo_electronic_photonic/full_flow_demo/full_flow_demo/src/truth_table_module.v @@ -4,30 +4,30 @@ (* generator = "Amaranth" *) module top(bit_phase_0, bit_phase_1, input_fock_state_str); reg \$auto$verilog_backend.cc:2334:dump_module$1 = 0; - (* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:86" *) + (* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:86" *) output [4:0] bit_phase_0; reg [4:0] bit_phase_0; - (* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:86" *) + (* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:86" *) output [4:0] bit_phase_1; reg [4:0] bit_phase_1; - (* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:82" *) + (* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:82" *) input [2:0] input_fock_state_str; wire [2:0] input_fock_state_str; always @* begin if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end (* full_case = 32'd1 *) - (* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:112" *) + (* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:112" *) casez (input_fock_state_str) - /* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ + /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ 3'h4: bit_phase_0 = 5'h00; - /* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ + /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ 3'h1: bit_phase_0 = 5'h00; - /* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ + /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ 3'h2: bit_phase_0 = 5'h1f; - /* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:124" */ + /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:124" */ default: bit_phase_0 = 5'h00; endcase @@ -35,18 +35,18 @@ module top(bit_phase_0, bit_phase_1, input_fock_state_str); always @* begin if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end (* full_case = 32'd1 *) - (* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:112" *) + (* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:112" *) casez (input_fock_state_str) - /* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ + /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ 3'h4: bit_phase_1 = 5'h00; - /* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ + /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ 3'h1: bit_phase_1 = 5'h1f; - /* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ + /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ 3'h2: bit_phase_1 = 5'h00; - /* src = "/nix/store/yn7mrd354mznvdh68zaar4bndlbnnb26-python3.11-piel-0.0.56/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:124" */ + /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:124" */ default: bit_phase_1 = 5'h00; endcase diff --git a/docs/examples/07_full_flow_demo_electronic_photonic/full_flow_demo/src/truth_table_module.v b/docs/examples/07_full_flow_demo_electronic_photonic/full_flow_demo/src/truth_table_module.v index b88b72c6..24a4dd51 100644 --- a/docs/examples/07_full_flow_demo_electronic_photonic/full_flow_demo/src/truth_table_module.v +++ b/docs/examples/07_full_flow_demo_electronic_photonic/full_flow_demo/src/truth_table_module.v @@ -4,30 +4,30 @@ (* generator = "Amaranth" *) module top(bit_phase_0, bit_phase_1, input_fock_state_str); reg \$auto$verilog_backend.cc:2334:dump_module$1 = 0; - (* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:86" *) + (* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:86" *) output [4:0] bit_phase_0; reg [4:0] bit_phase_0; - (* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:86" *) + (* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:86" *) output [4:0] bit_phase_1; reg [4:0] bit_phase_1; - (* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:82" *) + (* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:82" *) input [2:0] input_fock_state_str; wire [2:0] input_fock_state_str; always @* begin if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end (* full_case = 32'd1 *) - (* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:112" *) + (* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:112" *) casez (input_fock_state_str) - /* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ + /* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ 3'h4: bit_phase_0 = 5'h00; - /* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ + /* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ 3'h1: bit_phase_0 = 5'h00; - /* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ + /* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ 3'h2: bit_phase_0 = 5'h1f; - /* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:124" */ + /* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:124" */ default: bit_phase_0 = 5'h00; endcase @@ -35,18 +35,18 @@ module top(bit_phase_0, bit_phase_1, input_fock_state_str); always @* begin if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end (* full_case = 32'd1 *) - (* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:112" *) + (* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:112" *) casez (input_fock_state_str) - /* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ + /* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ 3'h4: bit_phase_1 = 5'h00; - /* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ + /* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ 3'h1: bit_phase_1 = 5'h1f; - /* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ + /* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */ 3'h2: bit_phase_1 = 5'h00; - /* src = "/nix/store/li0p6589931jpjhq811qb8x0gyrv28pp-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:124" */ + /* src = "/nix/store/rh9r11mm76n6nb2dry46ir59a1y296s9-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:124" */ default: bit_phase_1 = 5'h00; endcase diff --git a/piel/file_system.py b/piel/file_system.py index 2d9fd7fc..e9bacf99 100644 --- a/piel/file_system.py +++ b/piel/file_system.py @@ -709,7 +709,9 @@ def verify_install_file(install_file_path: pathlib.Path): output_path = pathlib.Path(input_path.__file__) / ".." except Exception: # TODO FIX this hacked af - output_path = pathlib.Path(input_path.__path__[0]) + output_path_raw = pathlib.Path(input_path.__path__[0]) + output_directory_name = output_path_raw.name + output_path = output_path_raw / output_directory_name pass elif isinstance(input_path, os.PathLike): output_path = pathlib.Path(input_path)