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vivado.log
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#-----------------------------------------------------------
# Vivado v2020.2 (64-bit)
# SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
# Start of session at: Tue Jun 13 19:09:26 2023
# Process ID: 797084
# Current directory: /home/stud2020/0gurdak/Desktop/project_JOS_fn
# Command line: vivado ./project_frf.xpr
# Log file: /home/stud2020/0gurdak/Desktop/project_JOS_fn/vivado.log
# Journal file: /home/stud2020/0gurdak/Desktop/project_JOS_fn/vivado.jou
#-----------------------------------------------------------
start_gui
open_project ./project_frf.xpr
INFO: [Project 1-313] Project file moved from '/home/stud2020/0gurdak/Desktop/JOS/project_frf' since last save.
WARNING: [Project 1-312] File not found as '/home/stud2020/0gurdak/Desktop/project_f/project_1.ip_user_files/mem_init_files/tr_init.mem'; using path '/home/stud2020/0gurdak/Desktop/JOS/project_f/project_1.ip_user_files/mem_init_files/tr_init.mem' instead.
WARNING: [Project 1-312] File not found as '/home/stud2020/0gurdak/Desktop/project_f/project_1.srcs/sim_1/new/simple_receiver.sv'; using path '/home/stud2020/0gurdak/Desktop/JOS/project_f/project_1.srcs/sim_1/new/simple_receiver.sv' instead.
WARNING: [Project 1-312] File not found as '/home/stud2020/0gurdak/Desktop/project_f/project_1.srcs/sim_1/new/simple_transmitter.sv'; using path '/home/stud2020/0gurdak/Desktop/JOS/project_f/project_1.srcs/sim_1/new/simple_transmitter.sv' instead.
WARNING: [Project 1-312] File not found as '/home/stud2020/0gurdak/Desktop/project_f/uart_sim_behav.wcfg'; using path '/home/stud2020/0gurdak/Desktop/JOS/project_f/uart_sim_behav.wcfg' instead.
Scanning sources...
Finished scanning sources
WARNING: [Project 1-312] File not found as '/home/stud2020/0gurdak/Desktop/project_f/project_1.ip_user_files/mem_init_files/tr_init.mem'; using path '/home/stud2020/0gurdak/Desktop/JOS/project_f/project_1.ip_user_files/mem_init_files/tr_init.mem' instead.
WARNING: [Project 1-312] File not found as '/home/stud2020/0gurdak/Desktop/project_f/project_1.srcs/sim_1/new/simple_receiver.sv'; using path '/home/stud2020/0gurdak/Desktop/JOS/project_f/project_1.srcs/sim_1/new/simple_receiver.sv' instead.
WARNING: [Project 1-312] File not found as '/home/stud2020/0gurdak/Desktop/project_f/project_1.srcs/sim_1/new/simple_transmitter.sv'; using path '/home/stud2020/0gurdak/Desktop/JOS/project_f/project_1.srcs/sim_1/new/simple_transmitter.sv' instead.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/local/home/cadmgr/2020.2/data/ip'.
INFO: [IP_Flow 19-3899] Cannot get the environment domain name variable for the component vendor name. Setting the vendor name to 'user.org'.
update_compile_order -fileset sources_1
reset_run synth_1
launch_runs synth_1 -jobs 3
[Tue Jun 13 19:10:56 2023] Launched synth_1...
Run output will be captured here: /home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.runs/synth_1/runme.log
launch_simulation
Command: launch_simulation
INFO: [Vivado 12-5698] Checking validity of IPs in the design for the 'XSim' simulator...
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.sim/sim_1/behav/xsim'
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File '/local/home/cadmgr/xilinx/webpack/Vivado/2020.2/data/xsim/xsim.ini' copied to run dir:'/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.sim/sim_1/behav/xsim'
INFO: [SIM-utils-54] Inspecting design source files for 'uart_sim' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported '/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.sim/sim_1/behav/xsim/sin.mem'
INFO: [SIM-utils-43] Exported '/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.sim/sim_1/behav/xsim/tb_s_init.mem'
INFO: [SIM-utils-43] Exported '/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.sim/sim_1/behav/xsim/saw.mem'
INFO: [SIM-utils-43] Exported '/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.sim/sim_1/behav/xsim/triangle.mem'
INFO: [SIM-utils-43] Exported '/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.sim/sim_1/behav/xsim/abs_sin.mem'
INFO: [SIM-utils-43] Exported '/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.sim/sim_1/behav/xsim/tr_init.mem'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.sim/sim_1/behav/xsim'
xvlog --incr --relax -L uvm -prj uart_sim_vlog.prj
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/ROM_mem.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module ROM_mem
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/SPI_master.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module SPI_master
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/axi_master.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module axi_master
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/generator.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module generator
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/multiplekser.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module multiplekser
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/scaler.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module scaler
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/top.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module top
INFO: [VRFC 10-2458] undeclared symbol outsclk, assumed default net type wire [/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/top.sv:52]
INFO: [VRFC 10-2458] undeclared symbol outmosi, assumed default net type wire [/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/top.sv:53]
INFO: [VRFC 10-2458] undeclared symbol outsync, assumed default net type wire [/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/top.sv:54]
INFO: [VRFC 10-2458] undeclared symbol enable, assumed default net type wire [/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/top.sv:88]
INFO: [VRFC 10-2458] undeclared symbol s_axi_awvalid, assumed default net type wire [/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/top.sv:131]
INFO: [VRFC 10-2458] undeclared symbol s_axi_awready, assumed default net type wire [/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/top.sv:132]
INFO: [VRFC 10-2458] undeclared symbol s_axi_wvalid, assumed default net type wire [/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/top.sv:136]
INFO: [VRFC 10-2458] undeclared symbol s_axi_wready, assumed default net type wire [/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/top.sv:137]
INFO: [VRFC 10-2458] undeclared symbol s_axi_bvalid, assumed default net type wire [/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/top.sv:140]
INFO: [VRFC 10-2458] undeclared symbol s_axi_bready, assumed default net type wire [/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/top.sv:141]
INFO: [VRFC 10-2458] undeclared symbol s_axi_arvalid, assumed default net type wire [/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/top.sv:144]
INFO: [VRFC 10-2458] undeclared symbol s_axi_arready, assumed default net type wire [/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/top.sv:145]
INFO: [VRFC 10-2458] undeclared symbol s_axi_rvalid, assumed default net type wire [/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/top.sv:149]
INFO: [VRFC 10-2458] undeclared symbol s_axi_rready, assumed default net type wire [/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/top.sv:150]
INFO: [VRFC 10-2458] undeclared symbol rd, assumed default net type wire [/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/top.sv:162]
INFO: [VRFC 10-2458] undeclared symbol wr, assumed default net type wire [/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/top.sv:162]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sources_1/new/translator.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module translator
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sim_1/new/uart_sim.sv" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module uart_sim
INFO: [VRFC 10-2458] undeclared symbol rx, assumed default net type wire [/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sim_1/new/uart_sim.sv:31]
INFO: [VRFC 10-2458] undeclared symbol tx, assumed default net type wire [/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sim_1/new/uart_sim.sv:31]
INFO: [VRFC 10-2458] undeclared symbol fint, assumed default net type wire [/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sim_1/new/uart_sim.sv:38]
INFO: [VRFC 10-2263] Analyzing Verilog file "/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.sim/sim_1/behav/xsim/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
xvhdl --incr --relax -prj uart_sim_vhdl.prj
INFO: [VRFC 10-163] Analyzing VHDL file "/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.gen/sources_1/ip/axi_slave_uart_1/sim/axi_slave_uart.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'axi_slave_uart'
Waiting for jobs to finish...
No pending jobs, compilation finished.
INFO: [USF-XSim-69] 'compile' step finished in '3' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.sim/sim_1/behav/xsim'
xelab -wto fd48c32ecfe34bd7a2eed3a7187d8cc8 --incr --debug typical --relax --mt 8 -L xil_defaultlib -L axi_lite_ipif_v3_0_4 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_cdc_v1_0_2 -L axi_uartlite_v2_0_26 -L uvm -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot uart_sim_behav xil_defaultlib.uart_sim xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /local/home/cadmgr/2020.2/bin/unwrapped/lnx64.o/xelab -wto fd48c32ecfe34bd7a2eed3a7187d8cc8 --incr --debug typical --relax --mt 8 -L xil_defaultlib -L axi_lite_ipif_v3_0_4 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_cdc_v1_0_2 -L axi_uartlite_v2_0_26 -L uvm -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot uart_sim_behav xil_defaultlib.uart_sim xil_defaultlib.glbl -log elaborate.log
Using 8 slave threads.
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package std.standard
Compiling package std.textio
Compiling package ieee.std_logic_1164
Compiling package ieee.numeric_std
Compiling package ieee.std_logic_arith
Compiling package ieee.std_logic_unsigned
Compiling package axi_lite_ipif_v3_0_4.ipif_pkg
Compiling package synopsys.attributes
Compiling package ieee.std_logic_misc
Compiling package unisim.vcomponents
Compiling package ieee.vital_timing
Compiling package ieee.vital_primitives
Compiling package unisim.vpkg
Compiling package lib_pkg_v1_0_2.lib_pkg
Compiling module xil_defaultlib.generator_default
Compiling module xil_defaultlib.ROM_mem
Compiling module xil_defaultlib.ROM_mem(filename="abs_sin.mem")
Compiling module xil_defaultlib.ROM_mem(filename="triangle.mem")
Compiling module xil_defaultlib.ROM_mem(filename="saw.mem")
Compiling module xil_defaultlib.multiplekser
Compiling module xil_defaultlib.SPI_master(period=8,idle_time=15...
Compiling architecture rtl of entity axi_uartlite_v2_0_26.baudrate [\baudrate(c_ratio=27)\]
Compiling architecture fdre_v of entity unisim.FDRE [fdre_default]
Compiling architecture fdr_v of entity unisim.FDR [fdr_default]
Compiling architecture implementation of entity lib_cdc_v1_0_2.cdc_sync [\cdc_sync(c_mtbf_stages=4)\]
Compiling architecture imp of entity lib_srl_fifo_v1_0_2.cntr_incr_decr_addn_f [\cntr_incr_decr_addn_f(c_size=5,...]
Compiling architecture behavioral of entity lib_srl_fifo_v1_0_2.dynshreg_f [\dynshreg_f(c_depth=16,c_dwidth=...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_2.srl_fifo_rbu_f [\srl_fifo_rbu_f(c_dwidth=8,c_fam...]
Compiling architecture imp of entity lib_srl_fifo_v1_0_2.srl_fifo_f [\srl_fifo_f(c_dwidth=8,c_family=...]
Compiling architecture rtl of entity axi_uartlite_v2_0_26.uartlite_rx [\uartlite_rx(c_family="zynq")(1,...]
Compiling architecture rtl of entity axi_uartlite_v2_0_26.uartlite_tx [\uartlite_tx(c_family="zynq")(1,...]
Compiling architecture rtl of entity axi_uartlite_v2_0_26.uartlite_core [\uartlite_core(c_family="zynq",c...]
Compiling architecture imp of entity axi_lite_ipif_v3_0_4.pselect_f [\pselect_f(c_ab=2,c_aw=2,c_bar="...]
Compiling architecture imp of entity axi_lite_ipif_v3_0_4.pselect_f [\pselect_f(c_ab=2,c_aw=2,c_bar="...]
Compiling architecture imp of entity axi_lite_ipif_v3_0_4.pselect_f [\pselect_f(c_ab=2,c_aw=2,c_bar="...]
Compiling architecture imp of entity axi_lite_ipif_v3_0_4.pselect_f [\pselect_f(c_ab=2,c_aw=2,c_bar="...]
Compiling architecture imp of entity axi_lite_ipif_v3_0_4.address_decoder [\address_decoder(c_bus_awidth=4,...]
Compiling architecture imp of entity axi_lite_ipif_v3_0_4.slave_attachment [\slave_attachment(c_ard_addr_ran...]
Compiling architecture imp of entity axi_lite_ipif_v3_0_4.axi_lite_ipif [\axi_lite_ipif(c_s_axi_addr_widt...]
Compiling architecture rtl of entity axi_uartlite_v2_0_26.axi_uartlite [\axi_uartlite(c_family="zynq",c_...]
Compiling architecture axi_slave_uart_arch of entity xil_defaultlib.axi_slave_uart [axi_slave_uart_default]
Compiling module xil_defaultlib.axi_master(addrw=4)
Compiling module xil_defaultlib.translator
Compiling module xil_defaultlib.scaler
Compiling module xil_defaultlib.top_default
Compiling module xil_defaultlib.simple_transmitter(nb=8,deep=12,...
Compiling module xil_defaultlib.uart_sim
Compiling module xil_defaultlib.glbl
Built simulation snapshot uart_sim_behav
INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "uart_sim_behav -key {Behavioral:sim_1:Functional:uart_sim} -tclbatch {uart_sim.tcl} -view {/home/stud2020/0gurdak/Desktop/JOS/project_f/uart_sim_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2020.2
Time resolution is 1 ps
open_wave_config /home/stud2020/0gurdak/Desktop/JOS/project_f/uart_sim_behav.wcfg
source uart_sim.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
Start
INFO: [USF-XSim-96] XSim completed. Design snapshot 'uart_sim_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 7418.285 ; gain = 41.930 ; free physical = 6944 ; free virtual = 15162
run all
$finish called at time : 1 ms : File "/home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.srcs/sim_1/new/uart_sim.sv" Line 82
reset_run synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory /home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.runs/synth_1
launch_runs synth_1 -jobs 3
[Tue Jun 13 19:15:50 2023] Launched synth_1...
Run output will be captured here: /home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.runs/synth_1/runme.log
close_sim
INFO: [Simtcl 6-16] Simulation closed
reset_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-2266] Removing simulation data...
INFO: [Vivado 12-2267] Reset complete
launch_runs impl_1 -jobs 3
[Tue Jun 13 19:18:25 2023] Launched impl_1...
Run output will be captured here: /home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.runs/impl_1/runme.log
reset_run impl_1
reset_run synth_1
reset_simulation -simset sim_1 -mode behavioral
INFO: [Vivado 12-2266] Removing simulation data...
INFO: [Vivado 12-2267] Reset complete
close_project
open_project /home/stud2020/0gurdak/Desktop/project_JOS_fn/project_frf.xpr
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/local/home/cadmgr/2020.2/data/ip'.
update_compile_order -fileset sources_1
close_project
exit
INFO: [Common 17-206] Exiting Vivado at Tue Jun 13 19:53:41 2023...