Core(TM) i7-7567U

[antermin]

On 1.93.1:

$ corefreq-cli -s -n -m -n -B -n -M -n -C 1
Processor                             [Intel(R) Core(TM) i7-7567U CPU @ 3.50GHz]
|- Architecture                                                   [Kaby Lake/UY]
|- Vendor ID                                                      [GenuineIntel]
|- Microcode                                                        [0x000000f0]
|- Signature                                                           [  06_8E]
|- Stepping                                                            [      9]
|- Online CPU                                                          [  4/  4]
|- Base Clock                                                          [100.122]
|- Frequency            (MHz)                      Ratio                        
                 Min    400.49                    <   4 >                       
                 Max   3504.26                    <  35 >                       
|- Factory                                                             [100.000]
                       3500                       [  35 ]                       
|- Performance                                                                  
   |- P-State                                                                   
                 TGT    600.73                    <   6 >                       
|- Turbo Boost                                                         [ UNLOCK]
                  1C   4004.87                    <  40 >                       
                  2C   3904.75                    <  39 >                       
                  3C   3904.75                    <  39 >                       
                  4C   3904.75                    <  39 >                       
|- Uncore                                                              [ UNLOCK]
                 Min    400.49                    <   4 >                       
                 Max   3804.62                    <  38 >                       
|- TDP                                                           Level <  0:3  >
   |- Programmable                                                     [ UNLOCK]
   |- Configuration                                                    [ UNLOCK]
   |- Turbo Activation                                                 [ UNLOCK]
             Nominal   3504.26                    [  35 ]                       
              Level1    600.73                    [   6 ]                       
               Turbo   3404.14                    <  34 >                       
                                                                                
Instruction Set Extensions                                                      
|- 3DNow!/Ext [N/N]          ADX [Y]          AES [Y]  AVX/AVX2 [Y/Y] 
|- AVX512-F     [N]    AVX512-DQ [N]  AVX512-IFMA [N]   AVX512-PF [N] 
|- AVX512-ER    [N]    AVX512-CD [N]    AVX512-BW [N]   AVX512-VL [N] 
|- AVX512-VBMI  [N] AVX512-VBMI2 [N]  AVX512-VNNI [N]  AVX512-ALG [N] 
|- AVX512-VPOP  [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N] 
|- AVX512-BF16  [N] AVX-VNNI-VEX [N]      MOVDIRI [N]   MOVDIR64B [N] 
|- BMI1/BMI2  [Y/Y]         CLWB [N]      CLFLUSH [Y] CLFLUSH-OPT [Y] 
|- CLAC-STAC    [Y]         CMOV [Y]    CMPXCHG8B [Y]  CMPXCHG16B [Y] 
|- F16C         [Y]          FPU [Y]         FXSR [Y]   LAHF-SAHF [Y] 
|- MMX/Ext    [Y/N] MON/MWAITX [Y/N]        MOVBE [Y]   PCLMULQDQ [Y] 
|- POPCNT       [Y]       RDRAND [Y]       RDSEED [Y]      RDTSCP [Y] 
|- SEP          [Y]          SHA [N]          SSE [Y]        SSE2 [Y] 
|- SSE3         [Y]        SSSE3 [Y]  SSE4.1/4A [Y/N]      SSE4.2 [Y] 
|- SERIALIZE    [N]      SYSCALL [Y]        RDPID [N]         SGX [Y] 
|- VAES         [N]   VPCLMULQDQ [N]   PREFETCH/W [Y]       LZCNT [Y] 
                                                                                
Features                                                                        
|- 1 GB Pages Support                                      1GB-PAGES   [Capable]
|- Advanced Configuration & Power Interface                     ACPI   [Capable]
|- Advanced Programmable Interrupt Controller                   APIC   [Capable]
|- APIC Timer Invariance                                        ARAT   [Capable]
|- Core Multi-Processing                                  CMP Legacy   [Missing]
|- L1 Data Cache Context ID                                  CNXT-ID   [Missing]
|- Direct Cache Access                                           DCA   [Missing]
|- Debugging Extension                                            DE   [Capable]
|- Debug Store & Precise Event Based Sampling               DS, PEBS   [Capable]
|- CPL Qualified Debug Store                                  DS-CPL   [Capable]
|- 64-Bit Debug Store                                         DTES64   [Capable]
|- Fast Short REP CMPSB                                         FSRC   [Missing]
|- Fast Short REP MOVSB                                         FSRM   [Missing]
|- Fast Short REP STOSB                                         FSRS   [Missing]
|- Fast Zero-length REP MOVSB                                   FZRM   [Missing]
|- Fast-String Operation                                        ERMS   [Capable]
|- Fused Multiply Add                                     FMA | FMA4   [Capable]
|- Hardware Feedback Interface                                   HFI   [Missing]
|- Hardware Lock Elision                                         HLE   [Missing]
|- History Reset                                              HRESET   [Missing]
|- Hybrid part processor                                      HYBRID   [Missing]
|- Instruction Based Sampling                                    IBS   [Missing]
|- Instruction INVPCID                                       INVPCID   [Capable]
|- Long Mode 64 bits                                       IA64 | LM   [Capable]
|- Linear Address Masking                                        LAM   [Missing]
|- LightWeight Profiling                                         LWP   [Missing]
|- Machine-Check Architecture                                    MCA   [Capable]
|- Memory Protection Extensions                                  MPX   [Capable]
|- Model Specific Registers                                      MSR   [Capable]
|- Memory Type Range Registers                                  MTRR   [Capable]
|- OS-Enabled Ext. State Management                          OSXSAVE   [Capable]
|- Physical Address Extension                                    PAE   [Capable]
|- Page Attribute Table                                          PAT   [Capable]
|- Pending Break Enable                                          PBE   [Capable]
|- Platform Configuration                                    PCONFIG   [Missing]
|- Process Context Identifiers                                  PCID   [Capable]
|- Perfmon and Debug Capability                                 PDCM   [Capable]
|- Page Global Enable                                            PGE   [Capable]
|- Page Size Extension                                           PSE   [Capable]
|- 36-bit Page Size Extension                                  PSE36   [Capable]
|- Processor Serial Number                                       PSN   [Missing]
|- Resource Director Technology/PQE                            RDT-A   [Missing]
|- Resource Director Technology/PQM                            RDT-M   [Missing]
|- Restricted Transactional Memory                               RTM   [Missing]
|- Safer Mode Extensions                                         SMX   [Missing]
|- Self-Snoop                                                     SS   [Capable]
|- Supervisor-Mode Access Prevention                            SMAP   [Capable]
|- Supervisor-Mode Execution Prevention                         SMEP   [Capable]
|- Thread Director                                                TD   [Missing]
|- Time Stamp Counter                                            TSC [Invariant]
|- Time Stamp Counter Deadline                          TSC-DEADLINE   [Capable]
|- TSX Force Abort MSR Register                            TSX-ABORT   [Capable]
|- TSX Suspend Load Address Tracking                       TSX-LDTRK   [Missing]
|- User-Mode Instruction Prevention                             UMIP   [Missing]
|- Virtual Mode Extension                                        VME   [Capable]
|- Virtual Machine Extensions                                    VMX   [Capable]
|- Write Back & Do Not Invalidate Cache                     WBNOINVD   [Missing]
|- Extended xAPIC Support                                     x2APIC   [ x2APIC]
|- Execution Disable Bit Support                              XD-Bit   [Capable]
|- XSAVE/XSTOR States                                          XSAVE   [Capable]
|- xTPR Update Control                                          xTPR   [Capable]
Mitigation mechanisms                                                           
|- Indirect Branch Restricted Speculation                       IBRS   [Capable]
|- Indirect Branch Prediction Barrier                           IBPB   [Capable]
|- Single Thread Indirect Branch Predictor                     STIBP   [Capable]
|- Speculative Store Bypass Disable                             SSBD   [Capable]
|- Writeback & invalidate the L1 data cache                L1D-FLUSH   [Capable]
|- Hypervisor - No flush L1D on VM entry            L1DFL_VMENTRY_NO   [Capable]
|- Arch - Buffer Overwriting                                MD-CLEAR   [Capable]
|- Arch - No Rogue Data Cache Load                           RDCL_NO   [Capable]
|- Arch - Enhanced IBRS                                     IBRS_ALL   [Capable]
|- Arch - Return Stack Buffer Alternate                         RSBA   [ Enable]
|- Arch - No Speculative Store Bypass                         SSB_NO   [Capable]
|- Arch - No Microarchitectural Data Sampling                 MDS_NO   [Capable]
|- Arch - No TSX Asynchronous Abort                           TAA_NO   [Capable]
|- Arch - No Page Size Change MCE                     PSCHANGE_MC_NO   [Capable]
|- Arch - STLB QoS                                              STLB   [ Unable]
|- Arch - Functional Safety Island                              FuSa   [ Unable]
|- Arch - RSM in CPL0 only                                       RSM   [ Unable]
|- Arch - Split Locked Access Exception                         SPLA   [ Unable]
|- Arch - Snoop Filter QoS Mask                         SNOOP_FILTER   [ Unable]
|- Arch - No Fast Predictive Store Forwarding                   PSFD   [ Unable]
|- Arch - Data Operand Independent Timing Mode                 DOITM   [ Unable]
|- Arch - Not affected by SBDR or SSDP                  SBDR_SSDP_NO   [Capable]
|- Arch - No Fill Buffer Stale Data Propagator              FBSDP_NO   [Capable]
|- Arch - No Primary Stale Data Propagator                   PSDP_NO   [Capable]
|- Arch - Overwrite Fill Buffer values                      FB_CLEAR   [Capable]
|- Arch - Special Register Buffer Data Sampling                SRBDS   [Capable]
   |- RDRAND and RDSEED mitigation                             RNGDS   [Capable]
   |- Restricted Transactional Memory                            RTM   [Capable]
   |- Verify Segment for Writing instruction                    VERW   [Capable]
|- Arch - Restricted RSB Alternate                             RRSBA   [Capable]
|- Arch - No Branch Target Injection                          BHI_NO   [Capable]
|- Arch - Legacy xAPIC Disable                             XAPIC_DIS   [ Unable]
|- Arch - No Post-Barrier Return Stack Buffer               PBRSB_NO   [Capable]
|- Arch - IPRED disabled for CPL3                        IPRED_DIS_U   [ Unable]
|- Arch - IPRED disabled for CPL0/1/2                    IPRED_DIS_S   [ Unable]
|- Arch - RRSBA disabled for CPL3                        RRSBA_DIS_U   [ Unable]
|- Arch - RRSBA disabled for CPL0/1/2                    RRSBA_DIS_S   [ Unable]
|- Arch - BHI disabled for CPL0/1/2                        BHI_DIS_S   [ Unable]
|- No MXCSR Configuration Dependent Timing                   MCDT_NO   [ Unable]
Security Features                                                               
|- CPUID Key Locker                                               KL   [Missing]
|- AES Key Locker instructions                                AESKLE   [Missing]
|- AES Wide Key Locker instructions                          WIDE_KL   [Missing]
|- Software Guard SGX1 Extensions                               SGX1   [Missing]
|- Software Guard SGX2 Extensions                               SGX2   [Missing]
                                                                                
Technologies                                                                    
|- Data Cache Unit                                                              
   |- L1 Prefetcher                                                L1 HW   < ON>
   |- L1 IP Prefetcher                                          L1 HW IP   < ON>
   |- L2 Prefetcher                                                L2 HW   < ON>
   |- L2 Line Prefetcher                                        L2 HW CL   < ON>
|- System Management Mode                                       SMM-Dual   [ ON]
|- Hyper-Threading                                                   HTT   [ ON]
|- SpeedStep                                                        EIST   < ON>
|- Dynamic Acceleration                                              IDA   [ ON]
|- Turbo Boost                                                     TURBO   < ON>
|- Energy Efficiency Optimization                                    EEO   < ON>
|- Race To Halt Optimization                                         R2H   < ON>
|- Watchdog Timer                                                    TCO   <OFF>
|- Virtualization                                                    VMX   [ ON]
   |- I/O MMU                                                       VT-d   [ ON]
   |- Version                                                     [         1.0]
   |- Hypervisor                                                           [OFF]
   |- Vendor ID                                                   [         N/A]
                                                                                
Performance Monitoring                                                          
|- Version                                                        PM       [  4]
|- Counters:          General                   Fixed                           
|           {  4,  0,  0 } x 48 bits            3 x 48 bits                     
|- Enhanced Halt State                                           C1E       <OFF>
|- C1 Auto Demotion                                              C1A       < ON>
|- C3 Auto Demotion                                              C3A       < ON>
|- C1 UnDemotion                                                 C1U       < ON>
|- C3 UnDemotion                                                 C3U       < ON>
|- C6 Core Demotion                                              CC6       <OFF>
|- C6 Module Demotion                                            MC6       <OFF>
|- Legacy Frequency ID control                                   FID       [OFF]
|- Legacy Voltage ID control                                     VID       [OFF]
|- P-State Hardware Coordination Feedback                MPERF/APERF       [ ON]
|- Hardware Duty Cycling                                         HDC       < ON>
|- Package C-States                                                             
   |- Configuration Control                                   CONFIG   [ UNLOCK]
   |- Lowest C-State                                           LIMIT   <     C0>
   |- I/O MWAIT Redirection                                  IOMWAIT   <Disable>
   |- Max C-State Inclusion                                    RANGE   <     C8>
|- Core C-States                                                                
   |- C-States Base Address                                      BAR   [ 0x1814]
|- MONITOR/MWAIT                                                                
   |- State index:    #0    #1    #2    #3    #4    #5    #6    #7              
   |- Sub C-State:     0     2     1     2     4     1     1     1              
|- Core Cycles                                                         [Capable]
|- Instructions Retired                                                [Capable]
|- Reference Cycles                                                    [Capable]
|- Last Level Cache References                                         [Capable]
|- Last Level Cache Misses                                             [Capable]
|- Branch Instructions Retired                                         [Capable]
|- Branch Mispredicts Retired                                          [Capable]
|- Top-down slots Counter                                              [Capable]
|- Hardware-Controlled Performance States                        HWP       <OFF>
   |- Capabilities     Lowest      Efficient     Guaranteed        Highest      
   |- CPU #0       0.00 (  0)     0.00 (  0)     0.00 (  0)     0.00 (  0)      
   |- CPU #1       0.00 (  0)     0.00 (  0)     0.00 (  0)     0.00 (  0)      
   |- CPU #2       0.00 (  0)     0.00 (  0)     0.00 (  0)     0.00 (  0)      
   |- CPU #3       0.00 (  0)     0.00 (  0)     0.00 (  0)     0.00 (  0)      
                                                                                
Power, Current & Thermal                                                        
|- Temperature Offset:Junction                                 TjMax <  0:100 C>
|- Clock Modulation                                             ODCM   <Disable>
   |- DutyCycle                                                        [  0.00%]
|- Power Management                                         PWR MGMT   [   LOCK]
   |- Energy Policy                                        Bias Hint   <      6>
|- Digital Thermal Sensor                                        DTS   [Capable]
|- Power Limit Notification                                      PLN   [Capable]
|- Package Thermal Management                                    PTM   [Capable]
|- Thermal Monitor 1                                             TM1   [ Enable]
|- Thermal Monitor 2                                             TM2   [Capable]
|- Thermal Design Power                                          TDP   [   28 W]
   |- Minimum Power                                              Min   [Missing]
   |- Maximum Power                                              Max   [Missing]
|- Thermal Design Power                                      Package   < Enable>
   |- Power Limit                                                PL1   <   30 W>
   |- Time Window                                                TW1   <   28 s>
   |- Power Limit                                                PL2   <   37 W>
   |- Time Window                                                TW2   <   2 ms>
|- Thermal Design Power                                         Core   <Disable>
   |- Power Limit                                                PL1   <    0 W>
   |- Time Window                                                TW1   < 976 us>
|- Thermal Design Power                                       Uncore   <Disable>
   |- Power Limit                                                PL1   <    0 W>
   |- Time Window                                                TW1   < 976 us>
|- Thermal Design Power                                         DRAM   [Disable]
   |- Power Limit                                                PL1   [    0 W]
   |- Time Window                                                TW1   [ 976 us]
|- Thermal Design Power                                     Platform   <Disable>
   |- Power Limit                                                PL1   <    0 W>
   |- Time Window                                                TW1   <   28 s>
   |- Power Limit                                                PL2   <    0 W>
   |- Time Window                                                TW2   < 976 us>
|- Electrical Design Current                                     EDC   [Missing]
|- Thermal Design Current                                        TDC   [Missing]
|- Core Thermal Point                                                           
   |- DTS Threshold #1                                     Threshold   [Missing]
   |- DTS Threshold #2                                     Threshold   [Missing]
|- Package Thermal Point                                                        
   |- DTS Threshold #1                                     Threshold   [Missing]
   |- DTS Threshold #2                                     Threshold   [Missing]
|- Units                                                                        
   |- Power                                               watt   [  0.125000000]
   |- Energy                                             joule   [  0.000061035]
   |- Window                                            second   [  0.000976562]

CPU Pkg  Apic  Core/Thread  Caches      (w)rite-Back (i)nclusive              
 #   ID   ID    ID     ID  L1-Inst Way  L1-Data Way      L2  Way      L3  Way 
000:BSP    0     0      0    32768  8     32768  8    262144  4   4194304 16 i
001:  0    2     1      0    32768  8     32768  8    262144  4   4194304 16 i
002:  0    1     0      1    32768  8     32768  8    262144  4   4194304 16 i
003:  0    3     1      1    32768  8     32768  8    262144  4   4194304 16 i

[ 0] American Megatrends Inc.                                                   
[ 1] 5.12                                                                       
[ 2] 07/14/2019                                                                 
[ 3] Default string                                                             
[ 4] Default string                                                             
[ 5] Default string                                                             
[ 6] D---u---s---n-                                                             
[ 7] Default string                                                             
[ 8] Default string                                                             
[ 9] Default string                                                             
[10] SKYBAY                                                                     
[11] Default string                                                             
[12] D---u---s---n-                                                             
[13] Number Of Devices:2\Maximum Capacity:33554432 bytes                        
[14] ChannelA-DIMM0\BANK 0                                                      
[15] ChannelB-DIMM0\BANK 2                                                      
[16]                                                                            
[17]                                                                            
[18] SK Hynix                                                                   
[19] SK Hynix                                                                   
[20]                                                                            
[21]                                                                            
[22] HMA82GS6AFR8N-UH                                                           
[23] HMA82GS6AFR8N-UH                                                           
[24]                                                                            
[25]                                                                            

                            Union Point  [5904]                            
Controller #0                                                Dual Channel  
 Bus Rate  4000 MT/s      Bus Speed 4004 MT/s          DDR4 Speed 1333 MHz 
                                                                           
 Cha    CL  RCD   RP  RAS RRDs RRDl  FAW   WR RTPr WTPr  CWL CKE  CMD  GEAR
  #0    10   10   10   28   18    4   16   11    6   23    8   4   1T     0
  #1    10   10   10   28   18    4   16   11    6   23    8   4   1T     0
      sgRR dgRR drRR ddRR      sgRW dgRW drRW ddRW      sgWR dgWR drWR ddWR
  #0     4    4    6    7         8    8    8   10        20   16    5    6
  #1     4    4    7    7         8    8    8   10        19   16    5    6
      sgWW dgWW drWW ddWW                     REFI  RFC  XS   XP CPDED  ECC
  #0     4    4    7    7                     5200  234    0    0    4    0
  #1     4    4    7    7                     5200  234    0    0    4    0
                                                                           
 DIMM Geometry for channel #0                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    16    2     65536      1024          16384    HMA82GS6AFR8N-UH
       #1                                                                  
 DIMM Geometry for channel #1                                              
      Slot Bank Rank     Rows   Columns    Memory Size (MB)                
       #0    16    2     65536      1024          16384    HMA82GS6AFR8N-UH
       #1                                                                  

CPU Freq(MHz) VID  Vcore  TMP(C)    Accumulator       Energy(J)     Power(W)
000  473.24  8678  1.0593   35  000000000000000000    0.000000000   0.000000000
001  381.07     0  0.0000   34  000000000000000000    0.000000000   0.000000000
002  427.52     0  0.0000   35  000000000000000000    0.000000000   0.000000000
003  393.48     0  0.0000   34  000000000000000000    0.000000000   0.000000000

             Package[0]    Cores         Uncore        Memory        Platform
Energy(J):   5.207580566   2.434143066   0.000000000   1.074584961   0.000000000
Power(W) :   5.207580566   2.434143066   0.000000000   1.074584961   0.000000000

[cyring]

Most data appear accurate but I'm not sure about IMC timings.

Googleing HMA82GS6AFR8N-UH I'm finding those factory values with a CL of 17

But CoreFreq has decoded a CL of 10.

Can you please check and post the configured timings from BIOS or memtest86plus ?

[antermin]

BIOS reports CL 15 (15-15-15-35).

[cyring]

Got it from "7th Generation Intel® Processor Families for U/Y Platforms and 8th Generation Intel® Processor Family for U Quad Core Datasheet, Volume 2 of 2" Order Number: 334662-005

tCL: Holds DDR timing parameter tCL. Read command to data delay in DCLK cycles.
Supported range is 5-31.

Whenever I have clearly detected this architecture, I just have to add 5 to tCL.
Thing I won't do with first Skylake.

[cyring]

I have checked and down to Skylake I'm supposed to also add 5 !
So I now have doubt about results from the past, plus I don't have access to such hardware to conduct non regression tests.
Let me know if you have various Skylake, Kabylake, Coffee Lake, type S, H, U ?

[antermin]

Skylake, Kabylake, Coffee Lake, type S, H, U

I have Coffee Lake-U (i3-8109U).

Other CPUs I have belong to other architectures such as i5-5200U and i5-7600.

[cyring]

Skylake, Kabylake, Coffee Lake, type S, H, U

I have Coffee Lake-U (i3-8109U).

Other CPUs I have belong to other architectures such as i5-5200U and i5-7600.

Yes please, could you post the output of corefreq-cli -s -n -B -n -k -n -M based on latest develop branch.

[cyring]

For my current Tiger Lake Mobile timings are the same with datasheet,
Calculus issue seems limited to architectures from 6 to 8 generations.

[cyring]

Using latest commit, you can edit and change function SKL_IMC as below and you should get the primary timings fixed.

CoreFreq/corefreqd.c

Line 4393 in 0116ad7

void SKL_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))

void SKL_IMC(RO(SHM_STRUCT) *RO(Shm), RO(PROC) *RO(Proc))
{

	TIMING(mc, cha).tCL   = 5
			+ RO(Proc)->Uncore.MC[mc].Channel[cha].SKL.ODT.tCL;

	TIMING(mc, cha).tRCD  = 5
			+ RO(Proc)->Uncore.MC[mc].Channel[cha].SKL.Timing.tRP;

	TIMING(mc, cha).tRP   = 5
			+ RO(Proc)->Uncore.MC[mc].Channel[cha].SKL.Timing.tRP;

	TIMING(mc, cha).tRAS  = 7
			+ RO(Proc)->Uncore.MC[mc].Channel[cha].SKL.Timing.tRAS;

}

[cyring]

@svmlegacy Hello,
Based on latest develop branch, could you post the output of your Celeron(R) CPU G3900 using corefreq-cli -k -n -B -n -M

[antermin]

Using latest commit, you can edit and change function SKL_IMC as below and you should get the primary timings fixed.

Thanks, now it shows:

                            Union Point  [5904]                            
Controller #0                                                Dual Channel  
 Bus Rate  4000 MT/s      Bus Speed 4004 MT/s          DDR4 Speed 1333 MHz 
                                                                           
 Cha    CL  RCD   RP  RAS RRDs RRDl  FAW   WR RTPr WTPr  CWL CKE  CMD  GEAR
  #0    15   15   15   35   18    4   16   11    6   23    8   4   1T     0
  #1    15   15   15   35   18    4   16   11    6   23    8   4   1T     0
      sgRR dgRR drRR ddRR      sgRW dgRW drRW ddRW      sgWR dgWR drWR ddWR
  #0     4    4    6    7         8    8    8   10        20   16    5    6
  #1     4    4    7    7         8    8    8   10        19   16    5    6
      sgWW dgWW drWW ddWW                     REFI  RFC  XS   XP CPDED  ECC
  #0     4    4    7    7                     5200  234    0    0    4    0
  #1     4    4    7    7                     5200  234    0    0    4    0

[cyring]

Thanks, now it shows:

Thank you.

I'm OK to change tCL because datasheets specify that its first value within range is 5

But tRCD (which is tRP for SKL) and tRAS are out of their range:

CoreFreq/intel_reg.h

Line 3688 in 0116ad7

} SKL_IMC_CR_TC_PRE; /* Timing constraints to PRE commands */

To go further with source code:

• I need screenshots of BIOS timings to validate values.
  What about the other timings ?

• I will appreciate samples of SKL derivatives to be checked against BIOS.

[cyring]

@JohnAZoidberg Hello,

Based on latest develop branch, could you please post the output of your Core i5-8250U using corefreq-cli -k -n -B -n -M

... and check if the DDR timings are the same with BIOS (preferably screenshots of it) ?

[antermin]

What about the other timings?

This is all my BIOS shows regarding memory timings:

[cyring]

What about the other timings?

This is all my BIOS shows regarding memory timings:

Thanks a lot.
Can you post your Coffee Lake-U (i3-8109U) to check if the IMC timing values need exactly the same additions ?

[cyring]

Unsolved: regression risk on all Skylake decoders : Need large hardware scale testings : Postponed