Implementing I2C for AMD/SB-RMI queries [EPYC/Naples]

Author: cyring

amdmsr.h

@@ -183,85 +183,21 @@ enum {
 #define IS_HSMP_OOO(_rx) (_rx == HSMP_UNSPECIFIED			\
 			|| (_rx >= HSMP_FAIL_BGN && _rx <= HSMP_FAIL_END))
 
-/* Sources: PPR for AMD Family 17h					*/
-#define AMD_FCH_PM_CSTATE_EN	0x0000007e
-
-#define AMD_FCH_READ16(_data, _reg)					\
-({									\
-	__asm__ volatile						\
-	(								\
-		"movl	%1	,	%%eax"		"\n\t"		\
-		"movl	$0xcd6	,	%%edx"		"\n\t"		\
-		"outl	%%eax	,	%%dx"		"\n\t"		\
-		"movl	$0xcd7	,	%%edx"		"\n\t"		\
-		"inw	%%dx	,	%%ax"		"\n\t"		\
-		"movw	%%ax	,	%0"				\
-		: "=m"	(_data) 					\
-		: "i"	(_reg)						\
-		: "%rax", "%rdx", "memory"				\
-	);								\
-})
-
-#define AMD_FCH_WRITE16(_data, _reg)					\
-({									\
-	__asm__ volatile						\
-	(								\
-		"movl	%1	,	%%eax"		"\n\t"		\
-		"movl	$0xcd6	,	%%edx"		"\n\t"		\
-		"outl	%%eax	,	%%dx"		"\n\t"		\
-		"movw	%0	,	%%ax" 		"\n\t"		\
-		"movl	$0xcd7	,	%%edx"		"\n\t"		\
-		"outw	%%ax	,	%%dx"		"\n\t"		\
-		:							\
-		: "im"	(_data),					\
-		  "i"	(_reg)						\
-		: "%rax", "%rdx", "memory"				\
-	);								\
-})
-
-#define AMD_FCH_PM_Read16(IndexRegister, DataRegister)			\
-({									\
-	unsigned int tries = BIT_IO_RETRIES_COUNT;			\
-	unsigned char ret;						\
-    do {								\
-	ret = BIT_ATOM_TRYLOCK( BUS_LOCK,				\
-				PRIVATE(OF(AMD_FCH_LOCK)),		\
-				ATOMIC_SEED) ;				\
-	if (ret == 0) {							\
-		udelay(BIT_IO_DELAY_INTERVAL);				\
-	} else {							\
-		AMD_FCH_READ16(DataRegister.value, IndexRegister);	\
-									\
-		BIT_ATOM_UNLOCK(BUS_LOCK,				\
-				PRIVATE(OF(AMD_FCH_LOCK)),		\
-				ATOMIC_SEED);				\
-	}								\
-	tries--;							\
-    } while ( (tries != 0) && (ret != 1) );				\
-})
-
-#define AMD_FCH_PM_Write16(IndexRegister , DataRegister)		\
-({									\
-	unsigned int tries = BIT_IO_RETRIES_COUNT;			\
-	unsigned char ret;						\
-    do {								\
-	ret = BIT_ATOM_TRYLOCK( BUS_LOCK,				\
-				PRIVATE(OF(AMD_FCH_LOCK)),		\
-				ATOMIC_SEED );				\
-	if (ret == 0) {							\
-		udelay(BIT_IO_DELAY_INTERVAL);				\
-	} else {							\
-		AMD_FCH_WRITE16(DataRegister.value, IndexRegister);	\
-									\
-		BIT_ATOM_UNLOCK(BUS_LOCK,				\
-				PRIVATE(OF(AMD_FCH_LOCK)),		\
-				ATOMIC_SEED);				\
-	}								\
-	tries--;							\
-    } while ( (tries != 0) && (ret != 1) );				\
-})
+enum SBRMI_REGISTER {
+	SBRMI_REVISION	= 0x0,
+	SBRMI_CONTROL	= 0x1,
+	SBRMI_STATUS	= 0x2,
+	SBRMI_OUT_BOUND = 0x30,
+	SBRMI_IN_BOUND	= 0x38,
+	SBRMI_INTERRUPT = 0x40
+};
 
+enum SBRMI_FUNC {
+	SBRMI_RD_PKG_TDP= 0x1,	/* Package power cTDP[31:0] (mWatts)	*/
+	SBRMI_WR_PKG_TDP= 0x2,	/* SoC package power [31:0] (mWatts)	*/
+};
 
+/* Sources: BKDG for AMD Families 0Fh, 10h up to 16h			*/
 const struct {
 	unsigned int	MCF,
 			PCF[5];
@@ -1746,3 +1682,39 @@ typedef union
 		VID		: 32-24;	/*	Voltage ID	*/
 	};
 } AMD_17_CORE_VID;
+
+/* Sources: Advanced Platform Management Link (APML) Specification	*/
+typedef union
+{	/* I2C: address = 0x0						*/
+	unsigned char		value;
+	struct {
+		unsigned char
+		Revision	:  8-0;
+	};
+} AMD_SBRMI_REVISION;
+
+typedef union
+{	/* I2C: address = 0x1						*/
+	unsigned char		value;
+	struct {
+		unsigned char
+		AlertMask	:  1-0,
+		AraDis		:  2-1,
+		TimeoutDis	:  3-2,
+		BlkRWEn 	:  4-3,
+		SwAlertMask	:  5-4,
+		ReservedBits	:  7-5,
+		PECEn		:  8-7;
+	};
+} AMD_SBRMI_CONTROL;
+
+typedef union
+{	/* I2C: address = 0x2						*/
+	unsigned char		value;
+	struct {
+		unsigned char
+		AlertSts	:  1-0,
+		SwAlertSts	:  2-1,
+		ReservedBits	:  8-2;
+	};
+} AMD_SBRMI_STATUS;

corefreq-api.h

@@ -784,13 +784,18 @@ typedef struct
 	  } Uncore;
 	} Delta __attribute__ ((aligned (8)));
 
-	struct
+	union
 	{
-	    union {
-		UNCORE_GLOBAL_PERF_CONTROL Uncore_GlobalPerfControl;
-		UNCORE_PMON_GLOBAL_CONTROL Uncore_PMonGlobalControl;
-	    };
-		UNCORE_FIXED_PERF_CONTROL  Uncore_FixedPerfControl;
+	    struct {
+		union {
+			UNCORE_GLOBAL_PERF_CONTROL Uncore_GlobalPerfControl;
+			UNCORE_PMON_GLOBAL_CONTROL Uncore_PMonGlobalControl;
+		};
+			UNCORE_FIXED_PERF_CONTROL  Uncore_FixedPerfControl;
+	    } Intel;
+	    struct {
+		AMD_SBRMI_CONTROL	SBRMI_Control;
+	    } AMD;
 	} SaveArea;
 
 	FEATURES		Features;
@@ -886,6 +891,11 @@ typedef struct
 				Experimental,
 				HotPlug,
 				PCI;
+	    struct {
+		unsigned int	PFM	:  1-0,
+				I2C	:  2-1,
+				_pad32	: 32-2;
+	    };
 		KERNEL_DRIVER	Driver;
 	} Registration;
 

corefreq.h

@@ -463,6 +463,11 @@ typedef struct
 				Experimental,/* 0: Disable, 1: Enable	*/
 				HotPlug, /* < 0: Disable, Other: Enable */
 				PCI;	/*  < 0: Disable, other: Enable */
+	    struct {			/*  = 0: Disable, 1: Enable	*/
+		unsigned int	PFM	:  1-0,
+				I2C	:  2-1,
+				_pad32	: 32-2;
+	    };
 		KERNEL_DRIVER	Driver; /*0:Disable, 1:Enable, 2:Full-control*/
 	} Registration;
 

corefreqd.c

@@ -1753,6 +1753,8 @@ void Package_Update(SHM_STRUCT *Shm, RO(PROC) *RO(Proc), RW(PROC) *RW(Proc))
 	Shm->Registration.Experimental = RO(Proc)->Registration.Experimental;
 	Shm->Registration.HotPlug = RO(Proc)->Registration.HotPlug;
 	Shm->Registration.PCI = RO(Proc)->Registration.PCI;
+	Shm->Registration.PFM = RO(Proc)->Registration.PFM;
+	Shm->Registration.I2C = RO(Proc)->Registration.I2C;
 	BITSTOR(LOCKLESS, Shm->Registration.NMI, RO(Proc)->Registration.NMI);
 	Shm->Registration.Driver = RO(Proc)->Registration.Driver;
 	/* Copy the timer interval delay.				*/