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Hi "Crux",
From the openISP project tree structure, i see a "hardware".
**_hardware: is remained for the hardware implementation (Verilog/Chisel) of ISP algorithms and SoC._**
May I refer to the contents of this hardware directory?
( If can't give, it's all right. You have been very helpful to provide such a project for my reference. ^ ^ )
Thank you for considering my request.
chayi
The text was updated successfully, but these errors were encountered:
Hi "Crux",
From the openISP project tree structure, i see a "hardware".
**_hardware: is remained for the hardware implementation (Verilog/Chisel) of ISP algorithms and SoC._**
May I refer to the contents of this hardware directory?
( If can't give, it's all right. You have been very helpful to provide such a project for my reference. ^ ^ )
Thank you for considering my request.
chayi
Currently, I am busy with other stuffs and cannot spare time on the hardware implementation... Just leave this directory for further usage... I think I will upload some module codes once get it done...
Hi "Crux",
From the openISP project tree structure, i see a "hardware".
**_hardware: is remained for the hardware implementation (Verilog/Chisel) of ISP algorithms and SoC._**
May I refer to the contents of this hardware directory?
( If can't give, it's all right. You have been very helpful to provide such a project for my reference. ^ ^ )
Thank you for considering my request.
chayi
Currently, I am busy with other stuffs and cannot spare time on the hardware implementation... Just leave this directory for further usage... I think I will upload some module codes once get it done...
Got it, no problem, bro. Its all right. Thanks^ ^
best,
-chayi
Hi "Crux",
From the openISP project tree structure, i see a "hardware".
Thank you for considering my request.
chayi
The text was updated successfully, but these errors were encountered: