From 7847a2467d2ff743eaedae6ff1383c6b8854dbff Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 2 Nov 2020 17:27:42 -0800 Subject: [PATCH] Ignore PAUSE instructions when mcountinhibit.CY=1 Since we use the cycle counter to determine when to unpause, we shouldn't pause when the cycle counter doesn't count. --- src/main/scala/rocket/CSR.scala | 2 ++ src/main/scala/rocket/RocketCore.scala | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala index f5dd9ceaa8..517707b3dd 100644 --- a/src/main/scala/rocket/CSR.scala +++ b/src/main/scala/rocket/CSR.scala @@ -227,6 +227,7 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle val pmp = Vec(nPMPs, new PMP).asOutput val counters = Vec(nPerfCounters, new PerfCounterIO) val csrw_counter = UInt(OUTPUT, CSR.nCtr) + val inhibit_cycle = Output(Bool()) val inst = Vec(retireWidth, UInt(width = iLen)).asInput val trace = Vec(retireWidth, new TracedInstruction).asOutput val mcontext = Output(UInt(coreParams.mcontextWidth.W)) @@ -420,6 +421,7 @@ class CSRFile( val reg_vxrm = usingVector.option(Reg(UInt(io.vector.get.vxrm.getWidth.W))) val reg_mcountinhibit = RegInit(0.U((CSR.firstHPM + nPerfCounters).W)) + io.inhibit_cycle := reg_mcountinhibit(0) val reg_instret = WideCounter(64, io.retire, inhibit = reg_mcountinhibit(2)) val reg_cycle = if (enableCommitLog) WideCounter(64, io.retire, inhibit = reg_mcountinhibit(0)) else withClock(io.ungated_clock) { WideCounter(64, !io.csr_stall, inhibit = reg_mcountinhibit(0)) } diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala index 5b6fe61049..ee1749dbd7 100644 --- a/src/main/scala/rocket/RocketCore.scala +++ b/src/main/scala/rocket/RocketCore.scala @@ -853,7 +853,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) io.rocc.cmd.bits.rs2 := wb_reg_rs2 // gate the clock - val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0 || io.dmem.perf.release || take_pc + val unpause = csr.io.time(rocketParams.lgPauseCycles-1, 0) === 0 || csr.io.inhibit_cycle || io.dmem.perf.release || take_pc when (unpause) { id_reg_pause := false } io.cease := csr.io.status.cease && !clock_en_reg io.wfi := csr.io.status.wfi