From d4a20957744689881d0833b3c6c095c2118352a4 Mon Sep 17 00:00:00 2001 From: John Ingalls Date: Thu, 27 Aug 2020 14:28:03 -0700 Subject: [PATCH 1/3] consistent parameter names for API consistency: rename TLBConfig nEntries -> nWays; OMCaches keep nTLBEntries for backwards compatibility --- .../logicaltree/RocketLogicalTreeNode.scala | 2 ++ src/main/scala/diplomaticobjectmodel/model/OMCaches.scala | 2 ++ src/main/scala/rocket/TLB.scala | 6 +++--- src/main/scala/tile/L1Cache.scala | 2 +- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/main/scala/diplomaticobjectmodel/logicaltree/RocketLogicalTreeNode.scala b/src/main/scala/diplomaticobjectmodel/logicaltree/RocketLogicalTreeNode.scala index e159359592..58689ec262 100644 --- a/src/main/scala/diplomaticobjectmodel/logicaltree/RocketLogicalTreeNode.scala +++ b/src/main/scala/diplomaticobjectmodel/logicaltree/RocketLogicalTreeNode.scala @@ -30,6 +30,7 @@ class DCacheLogicalTreeNode(dcache: HellaCache, deviceOpt: Option[SimpleDevice], dataMemorySizeBytes = params.nSets * params.nWays * params.blockBytes, dataECC = params.dataECC.map(OMECC.fromString), tagECC = params.tagECC.map(OMECC.fromString), + nTLBEntries = params.nTLBSets * params.nTLBWays, nTLBSets = params.nTLBSets, nTLBWays = params.nTLBWays, memories = dcache.getOMSRAMs(), @@ -50,6 +51,7 @@ class ICacheLogicalTreeNode(icache: ICache, deviceOpt: Option[SimpleDevice], par dataMemorySizeBytes = params.nSets * params.nWays * params.blockBytes, dataECC = params.dataECC.map(OMECC.fromString), tagECC = params.tagECC.map(OMECC.fromString), + nTLBEntries = params.nTLBSets * params.nTLBWays, nTLBSets = params.nTLBSets, nTLBWays = params.nTLBWays, maxTimSize = params.nSets * (params.nWays-1) * params.blockBytes, diff --git a/src/main/scala/diplomaticobjectmodel/model/OMCaches.scala b/src/main/scala/diplomaticobjectmodel/model/OMCaches.scala index 687cd5a267..da10146169 100644 --- a/src/main/scala/diplomaticobjectmodel/model/OMCaches.scala +++ b/src/main/scala/diplomaticobjectmodel/model/OMCaches.scala @@ -25,6 +25,7 @@ case class OMICache( dataMemorySizeBytes: Int, dataECC: Option[OMECC], tagECC: Option[OMECC], + nTLBEntries: Int, nTLBSets: Int, nTLBWays: Int, maxTimSize: Int, @@ -41,6 +42,7 @@ case class OMDCache( dataMemorySizeBytes: Int, dataECC: Option[OMECC], tagECC: Option[OMECC], + nTLBEntries: Int, nTLBSets: Int, nTLBWays: Int, memories: Seq[OMSRAM], diff --git a/src/main/scala/rocket/TLB.scala b/src/main/scala/rocket/TLB.scala index 7a96e50fdc..8748016a49 100644 --- a/src/main/scala/rocket/TLB.scala +++ b/src/main/scala/rocket/TLB.scala @@ -146,7 +146,7 @@ class TLBEntry(val nSectors: Int, val superpage: Boolean, val superpageOnly: Boo case class TLBConfig( nSets: Int, - nEntries: Int, + nWays: Int, nSectors: Int = 4, nSuperpageEntries: Int = 4) @@ -162,7 +162,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: T val pageGranularityPMPs = pmpGranularity >= (1 << pgIdxBits) val vpn = io.req.bits.vaddr(vaddrBits-1, pgIdxBits) val memIdx = vpn.extract(cfg.nSectors.log2 + cfg.nSets.log2 - 1, cfg.nSectors.log2) - val sectored_entries = Reg(Vec(cfg.nSets, Vec(cfg.nEntries / cfg.nSectors, new TLBEntry(cfg.nSectors, false, false)))) + val sectored_entries = Reg(Vec(cfg.nSets, Vec(cfg.nWays / cfg.nSectors, new TLBEntry(cfg.nSectors, false, false)))) val superpage_entries = Reg(Vec(cfg.nSuperpageEntries, new TLBEntry(1, true, true))) val special_entry = (!pageGranularityPMPs).option(Reg(new TLBEntry(1, true, false))) def ordinary_entries = sectored_entries(memIdx) ++ superpage_entries @@ -324,7 +324,7 @@ class TLB(instruction: Boolean, lgMaxSize: Int, cfg: TLBConfig)(implicit edge: T val tlb_hit = real_hits.orR val tlb_miss = vm_enabled && !bad_va && !tlb_hit - val sectored_plru = new SetAssocLRU(cfg.nSets, cfg.nEntries, "plru") + val sectored_plru = new SetAssocLRU(cfg.nSets, sectored_entries(0).size, "plru") val superpage_plru = new PseudoLRU(superpage_entries.size) when (io.req.valid && vm_enabled) { when (sector_hits.orR) { sectored_plru.access(memIdx, OHToUInt(sector_hits)) } diff --git a/src/main/scala/tile/L1Cache.scala b/src/main/scala/tile/L1Cache.scala index 8862102ec9..c776ed3108 100644 --- a/src/main/scala/tile/L1Cache.scala +++ b/src/main/scala/tile/L1Cache.scala @@ -13,7 +13,7 @@ trait L1CacheParams { def nWays: Int def rowBits: Int def nTLBSets: Int - def nTLBWays: Int + def nTLBWays: Int def blockBytes: Int // TODO this is ignored in favor of p(CacheBlockBytes) in BaseTile } From b2d04e41d632d2c70c433f64fca56cae3c24bc8b Mon Sep 17 00:00:00 2001 From: John Ingalls Date: Thu, 27 Aug 2020 16:44:09 -0700 Subject: [PATCH 2/3] SetAssocLRU access(Seq) --- src/main/scala/util/Replacement.scala | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/main/scala/util/Replacement.scala b/src/main/scala/util/Replacement.scala index fa6c95a593..1d8910d9ee 100644 --- a/src/main/scala/util/Replacement.scala +++ b/src/main/scala/util/Replacement.scala @@ -56,6 +56,7 @@ abstract class SeqReplacementPolicy { abstract class SetAssocReplacementPolicy { def access(set: UInt, touch_way: UInt): Unit + def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]): Unit def way(set: UInt): UInt } @@ -301,6 +302,17 @@ class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocRepl state_vec(set) := logic.get_next_state(state_vec(set), touch_way) } + def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { + require(sets.size == touch_ways.size) + for (set <- 0 until n_sets) { + val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => + Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)} + when (set_touch_ways.map(_.valid).orR) { + state_vec(set) := logic.get_next_state(state_vec(set), set_touch_ways) + } + } + } + def way(set: UInt) = logic.get_replace_way(state_vec(set)) } From f196f8362775458af7004b48db206dd5dc6c876a Mon Sep 17 00:00:00 2001 From: John Ingalls Date: Thu, 27 Aug 2020 17:10:47 -0700 Subject: [PATCH 3/3] require message --- src/main/scala/util/Replacement.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/util/Replacement.scala b/src/main/scala/util/Replacement.scala index 1d8910d9ee..0bebb81ca2 100644 --- a/src/main/scala/util/Replacement.scala +++ b/src/main/scala/util/Replacement.scala @@ -303,7 +303,7 @@ class SetAssocLRU(n_sets: Int, n_ways: Int, policy: String) extends SetAssocRepl } def access(sets: Seq[UInt], touch_ways: Seq[Valid[UInt]]) = { - require(sets.size == touch_ways.size) + require(sets.size == touch_ways.size, "internal consistency check: should be same number of simultaneous updates for sets and touch_ways") for (set <- 0 until n_sets) { val set_touch_ways = (sets zip touch_ways).map { case (touch_set, touch_way) => Pipe(touch_way.valid && (touch_set === set.U), touch_way.bits, 0)}