From d7758df6feecd82e9168b21d61e72ac96c55a996 Mon Sep 17 00:00:00 2001 From: Bradley Morrell Date: Mon, 20 Jul 2020 14:24:54 -0700 Subject: [PATCH 1/8] added comment --- src/main/scala/amba/ahb/ToTL.scala | 1 + 1 file changed, 1 insertion(+) diff --git a/src/main/scala/amba/ahb/ToTL.scala b/src/main/scala/amba/ahb/ToTL.scala index a62b5c13fd..fec1fadc93 100644 --- a/src/main/scala/amba/ahb/ToTL.scala +++ b/src/main/scala/amba/ahb/ToTL.scala @@ -13,6 +13,7 @@ case class AHBToTLNode()(implicit valName: ValName) extends MixedAdapterNode(AHB dFn = { case mp => TLMasterPortParameters.v2( masters = mp.masters.map { m => + // This value should be constrained by a data width parameter that flows from masters to slaves // AHB fixed length transfer size maximum is 16384 = 1024 * 16 bits, hsize is capped at 111 = 1024 bit transfer size and hburst is capped at 111 = 16 beat burst TLMasterParameters.v2( name = m.name, From 73a58943bc9b994b246b82a6ca71693393b48cf8 Mon Sep 17 00:00:00 2001 From: Bradley Morrell Date: Mon, 20 Jul 2020 14:27:55 -0700 Subject: [PATCH 2/8] replaced with mincover --- src/main/scala/diplomacy/Parameters.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/diplomacy/Parameters.scala b/src/main/scala/diplomacy/Parameters.scala index a30dddfba9..1addb2711e 100644 --- a/src/main/scala/diplomacy/Parameters.scala +++ b/src/main/scala/diplomacy/Parameters.scala @@ -100,7 +100,7 @@ case class TransferSizes(min: Int, max: Int) // Not a union, because the result may contain sizes contained by neither term // NOT TO BE CONFUSED WITH COVERPOINTS - def cover(x: TransferSizes) = { + def mincover(x: TransferSizes) = { if (none) { x } else if (x.none) { From d4c418b228b63882506a9125816c690f82554b92 Mon Sep 17 00:00:00 2001 From: Bradley Morrell Date: Mon, 20 Jul 2020 14:30:00 -0700 Subject: [PATCH 3/8] shrinktransfer --- src/main/scala/tilelink/Fragmenter.scala | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/main/scala/tilelink/Fragmenter.scala b/src/main/scala/tilelink/Fragmenter.scala index dde122bf1a..dd143f02f5 100644 --- a/src/main/scala/tilelink/Fragmenter.scala +++ b/src/main/scala/tilelink/Fragmenter.scala @@ -60,14 +60,14 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( - acquireT = c.masters.map(_.emits.acquireT) .reduce(_ cover _), - acquireB = c.masters.map(_.emits.acquireB) .reduce(_ cover _), - arithmetic = c.masters.map(_.emits.arithmetic).reduce(_ cover _), - logical = c.masters.map(_.emits.logical) .reduce(_ cover _), - get = c.masters.map(_.emits.get) .reduce(_ cover _), - putFull = c.masters.map(_.emits.putFull) .reduce(_ cover _), - putPartial = c.masters.map(_.emits.putPartial).reduce(_ cover _), - hint = c.masters.map(_.emits.hint) .reduce(_ cover _) + acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ cover _)), + acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ cover _)), + arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ cover _)), + logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ cover _)), + get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ cover _)), + putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ cover _)), + putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ cover _)), + hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ cover _)) ) )) )}, From ea469ef0d3151b8558382d822edfba700ab26f97 Mon Sep 17 00:00:00 2001 From: Bradley Morrell Date: Mon, 20 Jul 2020 14:37:22 -0700 Subject: [PATCH 4/8] update --- src/main/scala/tilelink/Parameters.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/tilelink/Parameters.scala b/src/main/scala/tilelink/Parameters.scala index ba2e3a4d1f..2dea8a2c7c 100644 --- a/src/main/scala/tilelink/Parameters.scala +++ b/src/main/scala/tilelink/Parameters.scala @@ -306,7 +306,7 @@ class TLSlaveParameters private( def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, - setName: Option[String] = setName, + name: Option[String] = name, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, @@ -320,7 +320,7 @@ class TLSlaveParameters private( new TLSlaveParameters( nodePath = nodePath, resources = resources, - setName = setName, + setName = name, address = address, regionType = regionType, executable = executable, @@ -420,7 +420,7 @@ object TLSlaveParameters { address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), - setName: Option[String] = None, + name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, @@ -433,7 +433,7 @@ object TLSlaveParameters { new TLSlaveParameters( nodePath = nodePath, resources = resources, - setName = setName, + setName = name, address = address, regionType = regionType, executable = executable, From 323585ed55992a573b7d22a53286fbe5c0c46414 Mon Sep 17 00:00:00 2001 From: Bradley Morrell Date: Wed, 22 Jul 2020 12:43:40 -0700 Subject: [PATCH 5/8] changed name of cover --- src/main/scala/amba/axis/Parameters.scala | 4 +-- src/main/scala/diplomacy/Parameters.scala | 2 +- src/main/scala/tilelink/Fragmenter.scala | 16 +++++----- src/main/scala/tilelink/Parameters.scala | 36 +++++++++++------------ 4 files changed, 29 insertions(+), 29 deletions(-) diff --git a/src/main/scala/amba/axis/Parameters.scala b/src/main/scala/amba/axis/Parameters.scala index b58f280569..fbc1fd5a62 100644 --- a/src/main/scala/amba/axis/Parameters.scala +++ b/src/main/scala/amba/axis/Parameters.scala @@ -61,7 +61,7 @@ class AXISSlavePortParameters private ( beatBytes.foreach { b => require(isPow2(b)) } val endDestinationId = slaves.map(_.destinationId).max + 1 - val supportsCover = TransferSizes.cover(slaves.map(_.supportsSizes)) + val supportsCover = TransferSizes.mincover(slaves.map(_.supportsSizes)) def v1copy( slaves: Seq[AXISSlaveParameters] = slaves, @@ -146,7 +146,7 @@ class AXISMasterPortParameters private ( beatBytes.foreach { b => require(isPow2(b)) } val endSourceId = masters.map(_.sourceId.end).max - val emitsCover = TransferSizes.cover(masters.map(_.emitsSizes)) + val emitsCover = TransferSizes.mincover(masters.map(_.emitsSizes)) def v1copy( masters: Seq[AXISMasterParameters] = masters, diff --git a/src/main/scala/diplomacy/Parameters.scala b/src/main/scala/diplomacy/Parameters.scala index 1addb2711e..b846ade5ce 100644 --- a/src/main/scala/diplomacy/Parameters.scala +++ b/src/main/scala/diplomacy/Parameters.scala @@ -117,7 +117,7 @@ object TransferSizes { def apply(x: Int) = new TransferSizes(x) val none = new TransferSizes(0) - def cover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ cover _) + def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _) def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _) implicit def asBool(x: TransferSizes) = !x.none diff --git a/src/main/scala/tilelink/Fragmenter.scala b/src/main/scala/tilelink/Fragmenter.scala index dd143f02f5..d079f87129 100644 --- a/src/main/scala/tilelink/Fragmenter.scala +++ b/src/main/scala/tilelink/Fragmenter.scala @@ -60,14 +60,14 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)), requestFifo = true, emits = TLMasterToSlaveTransferSizes( - acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ cover _)), - acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ cover _)), - arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ cover _)), - logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ cover _)), - get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ cover _)), - putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ cover _)), - putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ cover _)), - hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ cover _)) + acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)), + acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)), + arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)), + logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)), + get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)), + putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)), + putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)), + hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _)) ) )) )}, diff --git a/src/main/scala/tilelink/Parameters.scala b/src/main/scala/tilelink/Parameters.scala index 2dea8a2c7c..6e469fe9e3 100644 --- a/src/main/scala/tilelink/Parameters.scala +++ b/src/main/scala/tilelink/Parameters.scala @@ -31,15 +31,15 @@ case class TLMasterToSlaveTransferSizes( putFull = putFull .intersect(rhs.putFull), putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint)) - def cover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( - acquireT = acquireT .cover(rhs.acquireT), - acquireB = acquireB .cover(rhs.acquireB), - arithmetic = arithmetic.cover(rhs.arithmetic), - logical = logical .cover(rhs.logical), - get = get .cover(rhs.get), - putFull = putFull .cover(rhs.putFull), - putPartial = putPartial.cover(rhs.putPartial), - hint = hint .cover(rhs.hint)) + def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes( + acquireT = acquireT .mincover(rhs.acquireT), + acquireB = acquireB .mincover(rhs.acquireB), + arithmetic = arithmetic.mincover(rhs.arithmetic), + logical = logical .mincover(rhs.logical), + get = get .mincover(rhs.get), + putFull = putFull .mincover(rhs.putFull), + putPartial = putPartial.mincover(rhs.putPartial), + hint = hint .mincover(rhs.hint)) // Reduce rendering to a simple yes/no per field override def toString = { def str(x: TransferSizes, flag: String) = if (x.none) "" else flag @@ -101,14 +101,14 @@ case class TLSlaveToMasterTransferSizes( putPartial = putPartial.intersect(rhs.putPartial), hint = hint .intersect(rhs.hint) ) - def cover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( - probe = probe .cover(rhs.probe), - arithmetic = arithmetic.cover(rhs.arithmetic), - logical = logical .cover(rhs.logical), - get = get .cover(rhs.get), - putFull = putFull .cover(rhs.putFull), - putPartial = putPartial.cover(rhs.putPartial), - hint = hint .cover(rhs.hint) + def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes( + probe = probe .mincover(rhs.probe), + arithmetic = arithmetic.mincover(rhs.arithmetic), + logical = logical .mincover(rhs.logical), + get = get .mincover(rhs.get), + putFull = putFull .mincover(rhs.putFull), + putPartial = putPartial.mincover(rhs.putPartial), + hint = hint .mincover(rhs.hint) ) // Reduce rendering to a simple yes/no per field override def toString = { @@ -570,7 +570,7 @@ class TLSlavePortParameters private( val allSupportHint = allSupports.hint // Operation supported by at least one outward Slaves - val anySupports = slaves.map(_.supports).reduce(_ cover _) + val anySupports = slaves.map(_.supports).reduce(_ mincover _) val anySupportAcquireT = !anySupports.acquireT.none val anySupportAcquireB = !anySupports.acquireB.none val anySupportArithmetic = !anySupports.arithmetic.none From d80cf778d1540d5ce06b908589b1bdbd0b0a3792 Mon Sep 17 00:00:00 2001 From: Bradley Morrell Date: Wed, 22 Jul 2020 12:56:07 -0700 Subject: [PATCH 6/8] bug fix --- src/main/scala/tilelink/Parameters.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/tilelink/Parameters.scala b/src/main/scala/tilelink/Parameters.scala index 6e469fe9e3..42299e7c62 100644 --- a/src/main/scala/tilelink/Parameters.scala +++ b/src/main/scala/tilelink/Parameters.scala @@ -306,7 +306,7 @@ class TLSlaveParameters private( def v2copy( nodePath: Seq[BaseNode] = nodePath, resources: Seq[Resource] = resources, - name: Option[String] = name, + name: Option[String] = setName, address: Seq[AddressSet] = address, regionType: RegionType.T = regionType, executable: Boolean = executable, From c022dcf16ac302b7e633a516688bc364f23c46c3 Mon Sep 17 00:00:00 2001 From: Bradley Morrell Date: Fri, 24 Jul 2020 13:22:48 -0700 Subject: [PATCH 7/8] Update Parameters.scala --- src/main/scala/tilelink/Parameters.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/tilelink/Parameters.scala b/src/main/scala/tilelink/Parameters.scala index 42299e7c62..ef2a092d80 100644 --- a/src/main/scala/tilelink/Parameters.scala +++ b/src/main/scala/tilelink/Parameters.scala @@ -420,7 +420,7 @@ object TLSlaveParameters { address: Seq[AddressSet], nodePath: Seq[BaseNode] = Seq(), resources: Seq[Resource] = Seq(), - name: Option[String] = None, + name: Option[String] = None, regionType: RegionType.T = RegionType.GET_EFFECTS, executable: Boolean = false, fifoId: Option[Int] = None, From e8f79b1287d0e05398646fb9dcf02c0ad1e555ce Mon Sep 17 00:00:00 2001 From: Bradley Morrell Date: Fri, 24 Jul 2020 13:36:08 -0700 Subject: [PATCH 8/8] mincover --- src/main/scala/amba/axis/Parameters.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/amba/axis/Parameters.scala b/src/main/scala/amba/axis/Parameters.scala index fbc1fd5a62..a353def75b 100644 --- a/src/main/scala/amba/axis/Parameters.scala +++ b/src/main/scala/amba/axis/Parameters.scala @@ -61,7 +61,7 @@ class AXISSlavePortParameters private ( beatBytes.foreach { b => require(isPow2(b)) } val endDestinationId = slaves.map(_.destinationId).max + 1 - val supportsCover = TransferSizes.mincover(slaves.map(_.supportsSizes)) + val supportsMinCover = TransferSizes.mincover(slaves.map(_.supportsSizes)) def v1copy( slaves: Seq[AXISSlaveParameters] = slaves, @@ -146,7 +146,7 @@ class AXISMasterPortParameters private ( beatBytes.foreach { b => require(isPow2(b)) } val endSourceId = masters.map(_.sourceId.end).max - val emitsCover = TransferSizes.mincover(masters.map(_.emitsSizes)) + val emitsMinCover = TransferSizes.mincover(masters.map(_.emitsSizes)) def v1copy( masters: Seq[AXISMasterParameters] = masters, @@ -272,7 +272,7 @@ class AXISEdgeParameters private ( require (!slave.reqContinuous || master.isContinuous, s"Slave port requires continuous stream data at ${sourceInfo}") val beatBytes = slave.beatBytes.getOrElse(master.beatBytes.get) - val transferSizes = master.emitsCover intersect slave.supportsCover + val transferSizes = master.emitsMinCover intersect slave.supportsMinCover val bundle = AXISBundleParameters.v1( idBits = log2Ceil(master.endSourceId),