From 6cf8294c71a6203834ca7e1c56608191d0e32208 Mon Sep 17 00:00:00 2001 From: Ernie Edgar Date: Tue, 3 Mar 2020 12:06:11 -0800 Subject: [PATCH] Qualify load and store watchpoints by instruction type --- src/main/scala/rocket/Breakpoint.scala | 10 ++++++---- src/main/scala/rocket/RocketCore.scala | 2 +- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/main/scala/rocket/Breakpoint.scala b/src/main/scala/rocket/Breakpoint.scala index 991acf08c6..2be5b7fb22 100644 --- a/src/main/scala/rocket/Breakpoint.scala +++ b/src/main/scala/rocket/Breakpoint.scala @@ -50,7 +50,8 @@ class BP(implicit p: Parameters) extends CoreBundle()(p) { class BPWatch (val n: Int) extends Bundle() { val valid = Vec(n, Bool()) - val dvalid = Vec(n, Bool()) + val rvalid = Vec(n, Bool()) + val wvalid = Vec(n, Bool()) val ivalid = Vec(n, Bool()) val action = UInt(3.W) } @@ -87,11 +88,12 @@ class BreakpointUnit(n: Int)(implicit val p: Parameters) extends Module with Has bpw.action := action bpw.valid(0) := false.B - bpw.dvalid(0) := false.B + bpw.rvalid(0) := false.B + bpw.wvalid(0) := false.B bpw.ivalid(0) := false.B - when (end && r && ri) { io.xcpt_ld := (action === 0.U); io.debug_ld := (action === 1.U); bpw.valid(0) := true.B; bpw.dvalid(0) := true.B } - when (end && w && wi) { io.xcpt_st := (action === 0.U); io.debug_st := (action === 1.U); bpw.valid(0) := true.B; bpw.dvalid(0) := true.B } + when (end && r && ri) { io.xcpt_ld := (action === 0.U); io.debug_ld := (action === 1.U); bpw.valid(0) := true.B; bpw.rvalid(0) := true.B } + when (end && w && wi) { io.xcpt_st := (action === 0.U); io.debug_st := (action === 1.U); bpw.valid(0) := true.B; bpw.wvalid(0) := true.B } when (end && x && xi) { io.xcpt_if := (action === 0.U); io.debug_if := (action === 1.U); bpw.valid(0) := true.B; bpw.ivalid(0) := true.B } (end || r, end || w, end || x) diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala index abdbdf93e2..16c2ee80b9 100644 --- a/src/main/scala/rocket/RocketCore.scala +++ b/src/main/scala/rocket/RocketCore.scala @@ -595,7 +595,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) wb_reg_raw_inst := mem_reg_raw_inst wb_reg_mem_size := mem_reg_mem_size wb_reg_pc := mem_reg_pc - wb_reg_wphit := mem_reg_wphit | bpu.io.bpwatch.map { bpw => bpw.dvalid(0) } + wb_reg_wphit := mem_reg_wphit | bpu.io.bpwatch.map { bpw => (bpw.rvalid(0) && mem_reg_load) || (bpw.wvalid(0) && mem_reg_store) } }