diff --git a/Makefrag b/Makefrag
index c29827fe4e1..295c6bcee6b 100644
--- a/Makefrag
+++ b/Makefrag
@@ -8,7 +8,12 @@ PROJECT ?= freechips.rocketchip.system
 CFG_PROJECT ?= $(PROJECT)
 CONFIG ?= DefaultConfig
 # TODO: For now must match rocketchip.Generator
-long_name = $(PROJECT).$(CONFIG)
+comma := ,
+space := $() $()
+splitConfigs := $(subst $(comma), ,$(CONFIG))
+configBases := $(foreach config,$(splitConfigs),$(lastword $(subst ., ,$(config))))
+CONFIG_STR := $(subst $(space),_,$(configBases))
+long_name = $(PROJECT).$(CONFIG_STR)
 
 VLSI_MEM_GEN ?= $(base_dir)/scripts/vlsi_mem_gen
 
diff --git a/emulator/Makefrag-verilator b/emulator/Makefrag-verilator
index d3b886b4e4e..5aa10e8805f 100644
--- a/emulator/Makefrag-verilator
+++ b/emulator/Makefrag-verilator
@@ -10,7 +10,7 @@ verilog = \
 
 $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
 	mkdir -p $(dir $@)
-	cd $(base_dir) && $(SBT) "runMain freechips.rocketchip.stage.RocketChipMain -td $(generated_dir) -T $(PROJECT).$(MODEL) -C $(CFG_PROJECT).$(CONFIG)"
+	cd $(base_dir) && $(SBT) "runMain freechips.rocketchip.stage.RocketChipMain -td $(generated_dir) -T $(PROJECT).$(MODEL) -C $(CONFIG)"
 
 %.v %.conf: %.fir $(FIRRTL_JAR)
 	mkdir -p $(dir $@)
diff --git a/regression/Makefile b/regression/Makefile
index 67983ad9e7f..3b660c9ccd5 100644
--- a/regression/Makefile
+++ b/regression/Makefile
@@ -46,22 +46,22 @@ endif
 
 ifeq ($(SUITE),RocketSuiteA)
 PROJECT=freechips.rocketchip.system
-CONFIGS=DefaultConfig
+CONFIGS=$(PROJECT).DefaultConfig
 endif
 
 ifeq ($(SUITE),RocketSuiteB)
 PROJECT=freechips.rocketchip.system
-CONFIGS=DefaultBufferlessConfig
+CONFIGS=$(PROJECT).DefaultBufferlessConfig
 endif
 
 ifeq ($(SUITE),RocketSuiteC)
 PROJECT=freechips.rocketchip.system
-CONFIGS=TinyConfig
+CONFIGS=$(PROJECT).TinyConfig
 endif
 
 ifeq ($(SUITE),UnittestSuite)
 PROJECT=freechips.rocketchip.unittest
-CONFIGS=AMBAUnitTestConfig TLSimpleUnitTestConfig TLWidthUnitTestConfig
+CONFIGS=$(PROJECT).AMBAUnitTestConfig $(PROJECT).TLSimpleUnitTestConfig $(PROJECT).TLWidthUnitTestConfig
 endif
 
 ifeq ($(SUITE), JtagDtmSuite)
@@ -69,13 +69,13 @@ PROJECT=freechips.rocketchip.system
 
 export JTAG_DTM_ENABLE_SBA ?= off
 ifeq ($(JTAG_DTM_ENABLE_SBA), off)
-CONFIGS_32=WithJtagDTMSystem_DefaultRV32Config
-CONFIGS_64=WithJtagDTMSystem_DefaultConfig
+CONFIGS_32=$(PROJECT).WithJtagDTMSystem,$(PROJECT).DefaultRV32Config
+CONFIGS_64=$(PROJECT).WithJtagDTMSystem,$(PROJECT).DefaultConfig
 endif
 
 ifeq ($(JTAG_DTM_ENABLE_SBA), on)
-CONFIGS_32=WithJtagDTMSystem_WithDebugSBASystem_DefaultRV32Config
-CONFIGS_64=WithJtagDTMSystem_WithDebugSBASystem_DefaultConfig
+CONFIGS_32=$(PROJECT).WithJtagDTMSystem,$(PROJECT).WithDebugSBASystem,$(PROJECT).DefaultRV32Config
+CONFIGS_64=$(PROJECT).WithJtagDTMSystem,$(PROJECT).WithDebugSBASystem,$(PROJECT).DefaultConfig
 endif
 
 CONFIGS += $(CONFIGS_32)
@@ -89,18 +89,18 @@ endif
 ifeq ($(SUITE), Miscellaneous)
 PROJECT=freechips.rocketchip.system
 CONFIGS=\
-	DefaultSmallConfig \
-	DualBankConfig \
-	DualChannelConfig \
-	DualChannelDualBankConfig \
-	RoccExampleConfig \
-	Edge128BitConfig \
-	Edge32BitConfig \
-	QuadChannelBenchmarkConfig \
-	EightChannelConfig \
-	DualCoreConfig \
-	MemPortOnlyConfig \
-	MMIOPortOnlyConfig
+	$(PROJECT).DefaultSmallConfig \
+	$(PROJECT).DualBankConfig \
+	$(PROJECT).DualChannelConfig \
+	$(PROJECT).DualChannelDualBankConfig \
+	$(PROJECT).RoccExampleConfig \
+	$(PROJECT).Edge128BitConfig \
+	$(PROJECT).Edge32BitConfig \
+	$(PROJECT).QuadChannelBenchmarkConfig \
+	$(PROJECT).EightChannelConfig \
+	$(PROJECT).DualCoreConfig \
+	$(PROJECT).MemPortOnlyConfig \
+	$(PROJECT).MMIOPortOnlyConfig
 endif
 
 # These are the named regression targets.  While it's expected you run them in
diff --git a/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala b/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala
index dc461f2e3b2..52aa7524fa0 100644
--- a/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala
+++ b/src/main/scala/stage/phases/GenerateTestSuiteMakefrags.scala
@@ -20,8 +20,6 @@ class GenerateTestSuiteMakefrags extends Phase with PreservesAll[Phase] with Has
     val targetDir = view[StageOptions](annotations).targetDir
     val fileName = s"${view[RocketChipOptions](annotations).longName}.d"
 
-    //addTestSuites(annotations)
-    //writeOutputFile(targetDir, fileName, TestGeneration.generateMakefrag)
     val makefrag =
       annotations
         .collect{ case a: RocketTestSuiteAnnotation => a.suite }
diff --git a/vsim/Makefrag b/vsim/Makefrag
index f28f192a210..278384769af 100644
--- a/vsim/Makefrag
+++ b/vsim/Makefrag
@@ -64,14 +64,14 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 # Build the simulator
 #--------------------------------------------------------------------
 
-simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)
+simv = $(sim_dir)/simv-$(PROJECT)-$(CONFIG_STR)
 $(simv) : $(sim_vsrcs) $(sim_csrcs)
 	cd $(sim_dir) && \
 	rm -rf csrc && \
 	$(VCS) $(VCS_OPTS) -o $(simv) \
 	-debug_pp \
 
-simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG)-debug
+simv_debug = $(sim_dir)/simv-$(PROJECT)-$(CONFIG_STR)-debug
 $(simv_debug) : $(sim_vsrcs) $(sim_csrcs)
 	cd $(sim_dir) && \
 	rm -rf csrc && \
diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog
index 887c613fbef..7a3e9669403 100644
--- a/vsim/Makefrag-verilog
+++ b/vsim/Makefrag-verilog
@@ -10,7 +10,7 @@ verilog = $(generated_dir)/$(long_name).v
 
 $(generated_dir)/%.fir $(generated_dir)/%.d: $(FIRRTL_JAR) $(chisel_srcs) $(bootrom_img)
 	mkdir -p $(dir $@)
-	cd $(base_dir) && $(SBT) "runMain freechips.rocketchip.stage.RocketChipMain -td $(generated_dir) -T $(PROJECT).$(MODEL) -C $(CFG_PROJECT).$(CONFIG)"
+	cd $(base_dir) && $(SBT) "runMain freechips.rocketchip.stage.RocketChipMain -td $(generated_dir) -T $(PROJECT).$(MODEL) -C $(CONFIG)"
 
 $(generated_dir)/%.v $(generated_dir)/%.conf: $(generated_dir)/%.fir $(FIRRTL_JAR)
 	mkdir -p $(dir $@)