From af6b81cbc28bf7e2149d26df299890239eeed48d Mon Sep 17 00:00:00 2001 From: phantom1003 Date: Wed, 11 May 2022 21:39:39 +0800 Subject: [PATCH] use CDE to specify the resource path of the clock gate --- src/main/scala/subsystem/Configs.scala | 4 ++++ src/main/scala/util/ClockGate.scala | 21 ++++++++++++++++----- 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala index 0d6471e111..ab13650601 100644 --- a/src/main/scala/subsystem/Configs.scala +++ b/src/main/scala/subsystem/Configs.scala @@ -330,6 +330,10 @@ class WithBootROMFile(bootROMFile: String) extends Config((site, here, up) => { case BootROMLocated(x) => up(BootROMLocated(x), site).map(_.copy(contentFileName = bootROMFile)) }) +class WithClockGateModel(file: String = "/vsrc/EICG_wrapper.v") extends Config((site, here, up) => { + case ClockGateModelFile => Some(file) +}) + class WithSynchronousRocketTiles extends Config((site, here, up) => { case RocketCrossingKey => up(RocketCrossingKey, site) map { r => r.copy(crossingType = SynchronousCrossing()) diff --git a/src/main/scala/util/ClockGate.scala b/src/main/scala/util/ClockGate.scala index acf6dd70cd..2908fa51c4 100644 --- a/src/main/scala/util/ClockGate.scala +++ b/src/main/scala/util/ClockGate.scala @@ -3,18 +3,29 @@ package freechips.rocketchip.util import chisel3._ -import chisel3.util.HasBlackBoxResource +import chisel3.util.{HasBlackBoxResource, HasBlackBoxPath} import freechips.rocketchip.config.{Field, Parameters} +import java.nio.file.{Files,Paths} + case object ClockGateImpl extends Field[() => ClockGate](() => new EICG_wrapper) +case object ClockGateModelFile extends Field[Option[String]](None) -abstract class ClockGate extends BlackBox { +abstract class ClockGate() extends BlackBox + with HasBlackBoxResource with HasBlackBoxPath { val io = IO(new Bundle{ val in = Input(Clock()) val test_en = Input(Bool()) val en = Input(Bool()) val out = Output(Clock()) }) + + def addVerilogResource(vsrc: String): Unit = { + if (Files.exists(Paths.get(vsrc))) + addPath(vsrc) + else + addResource(vsrc) + } } object ClockGate { @@ -24,6 +35,8 @@ object ClockGate { name: Option[String] = None)(implicit p: Parameters): Clock = { val cg = Module(p(ClockGateImpl)()) name.foreach(cg.suggestName(_)) + p(ClockGateModelFile).map(cg.addVerilogResource(_)) + cg.io.in := in cg.io.test_en := false.B cg.io.en := en @@ -38,6 +51,4 @@ object ClockGate { } // behavioral model of Integrated Clock Gating cell -class EICG_wrapper extends ClockGate with HasBlackBoxResource { - addResource("/vsrc/EICG_wrapper.v") -} +class EICG_wrapper extends ClockGate