From 0ffef27d3024500f80929200cd92f31528ca9391 Mon Sep 17 00:00:00 2001 From: Abhinay Kayastha Date: Tue, 4 Aug 2020 20:32:40 -0700 Subject: [PATCH 1/2] Change wrdata length to support xLen != fLen case --- src/main/scala/util/CoreMonitor.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/util/CoreMonitor.scala b/src/main/scala/util/CoreMonitor.scala index aa888441486..fef71294ee8 100644 --- a/src/main/scala/util/CoreMonitor.scala +++ b/src/main/scala/util/CoreMonitor.scala @@ -15,7 +15,7 @@ class CoreMonitorBundle(val xLen: Int) extends Bundle with Clocked { val valid = Bool() val pc = UInt(width = xLen.W) val wrdst = UInt(width = 5.W) - val wrdata = UInt(width = xLen.W) + val wrdata = UInt(width = 64.W) val wrenx = Bool() val wrenf = Bool() @deprecated("replace wren with wrenx or wrenf to specify integer or floating point","Rocket Chip 2020.05") From cde8768440041abe2d9068b4bbd28a6174509af0 Mon Sep 17 00:00:00 2001 From: Abhinay Kayastha Date: Thu, 6 Aug 2020 00:01:21 -0700 Subject: [PATCH 2/2] Add flen as CoreMonitorBundle parameter --- src/main/scala/rocket/RocketCore.scala | 4 ++-- src/main/scala/tile/FPU.scala | 2 +- src/main/scala/util/CoreMonitor.scala | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala index 725471ab80b..03c39098660 100644 --- a/src/main/scala/rocket/RocketCore.scala +++ b/src/main/scala/rocket/RocketCore.scala @@ -871,7 +871,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) val icache_blocked = !(io.imem.resp.valid || RegNext(io.imem.resp.valid)) csr.io.counters foreach { c => c.inc := RegNext(perfEvents.evaluate(c.eventSel)) } - val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen)) + val coreMonitorBundle = Wire(new CoreMonitorBundle(xLen, fLen)) coreMonitorBundle.clock := clock coreMonitorBundle.reset := reset @@ -934,7 +934,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) } // CoreMonitorBundle for late latency writes - val xrfWriteBundle = Wire(new CoreMonitorBundle(xLen)) + val xrfWriteBundle = Wire(new CoreMonitorBundle(xLen, fLen)) xrfWriteBundle.clock := clock xrfWriteBundle.reset := reset diff --git a/src/main/scala/tile/FPU.scala b/src/main/scala/tile/FPU.scala index 88ffd551488..199bf920fc6 100644 --- a/src/main/scala/tile/FPU.scala +++ b/src/main/scala/tile/FPU.scala @@ -732,7 +732,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) { val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid) // CoreMonitorBundle to monitor fp register file writes - val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen), DontCare)) + val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare)) frfWriteBundle.foreach { i => i.clock := clock i.reset := reset diff --git a/src/main/scala/util/CoreMonitor.scala b/src/main/scala/util/CoreMonitor.scala index fef71294ee8..0ffaaa772ff 100644 --- a/src/main/scala/util/CoreMonitor.scala +++ b/src/main/scala/util/CoreMonitor.scala @@ -7,7 +7,7 @@ import chisel3._ // this bundle is used to expose some internal core signals // to verification monitors which sample instruction commits -class CoreMonitorBundle(val xLen: Int) extends Bundle with Clocked { +class CoreMonitorBundle(val xLen: Int, val fLen: Int) extends Bundle with Clocked { val excpt = Bool() val priv_mode = UInt(width = 3.W) val hartid = UInt(width = xLen.W) @@ -15,7 +15,7 @@ class CoreMonitorBundle(val xLen: Int) extends Bundle with Clocked { val valid = Bool() val pc = UInt(width = xLen.W) val wrdst = UInt(width = 5.W) - val wrdata = UInt(width = 64.W) + val wrdata = UInt(width = (xLen max fLen).W) val wrenx = Bool() val wrenf = Bool() @deprecated("replace wren with wrenx or wrenf to specify integer or floating point","Rocket Chip 2020.05")