From 1db05c5c0bd145584d601f49ec4c70a382fcb931 Mon Sep 17 00:00:00 2001
From: John Ingalls <43973001+ingallsj@users.noreply.github.com>
Date: Wed, 28 Oct 2020 16:36:03 -0700
Subject: [PATCH] PTW do not count pte_hit/miss on L2TLB hits (#2688)

---
 src/main/scala/rocket/PTW.scala | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/rocket/PTW.scala b/src/main/scala/rocket/PTW.scala
index c66bb053a8..52d972562a 100644
--- a/src/main/scala/rocket/PTW.scala
+++ b/src/main/scala/rocket/PTW.scala
@@ -192,8 +192,11 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
 
     (hit && count < pgLevels-1, Mux1H(hits, data))
   }
+  val pte_hit = RegNext(false.B)
   io.dpath.perf.pte_miss := false
-  io.dpath.perf.pte_hit := false
+  io.dpath.perf.pte_hit := pte_hit && (state === s_req) && !io.dpath.perf.l2hit
+  assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)),
+    "PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event")
 
   val l2_refill = RegNext(false.B)
   l2_refill_wire := l2_refill
@@ -308,10 +311,9 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
     is (s_req) {
       when (pte_cache_hit) {
         count := count + 1
-        io.dpath.perf.pte_hit := true
+        pte_hit := true
       }.otherwise {
         next_state := Mux(io.mem.req.ready, s_wait1, s_req)
-        io.dpath.perf.pte_miss := io.mem.req.ready
       }
     }
     is (s_wait1) {
@@ -320,6 +322,7 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()(
     }
     is (s_wait2) {
       next_state := s_wait3
+      io.dpath.perf.pte_miss := true
       when (io.mem.s2_xcpt.ae.ld) {
         resp_ae := true
         next_state := s_ready