From 8f971bda47c3f6be41d22f6477b616dbc511ded0 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Tue, 25 Jun 2024 13:23:09 -0700 Subject: [PATCH] Emit FIRRTL bulk connects even for "input" wires --- .../src/main/scala/chisel3/internal/MonoConnect.scala | 2 +- src/test/scala/chiselTests/BulkConnectSpec.scala | 11 +++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/core/src/main/scala/chisel3/internal/MonoConnect.scala b/core/src/main/scala/chisel3/internal/MonoConnect.scala index 31d37b5d39c..ebc066a420b 100644 --- a/core/src/main/scala/chisel3/internal/MonoConnect.scala +++ b/core/src/main/scala/chisel3/internal/MonoConnect.scala @@ -296,7 +296,7 @@ private[chisel3] object MonoConnect { // CASE: Context is same module that both sink node and source node are in if ((context_mod == sink_mod) && (context_mod == source_mod)) { - sink.direction != Input + !sink_is_port || sink.direction != Input } // CASE: Context is same module as sink node and source node is in a child module diff --git a/src/test/scala/chiselTests/BulkConnectSpec.scala b/src/test/scala/chiselTests/BulkConnectSpec.scala index ba5a8668efa..c99c7548e48 100644 --- a/src/test/scala/chiselTests/BulkConnectSpec.scala +++ b/src/test/scala/chiselTests/BulkConnectSpec.scala @@ -112,4 +112,15 @@ class BulkConnectSpec extends ChiselPropSpec { chirrtl should include("connect out1[0], in1[1]") chirrtl should include("connect out1[1], in1[0]") } + + property("Chisel should emit FIRRTL bulk connect for \"input\" wires") { + class MyBundle extends Bundle { + val foo = Input(UInt(8.W)) + } + val chirrtl = ChiselStage.emitCHIRRTL(new Module { + val w1, w2 = Wire(new MyBundle) + w2 <> w1 + }) + chirrtl should include("connect w2, w1") + } }