From a2b692057df0d714f5d8031cf93b4b11f7b87252 Mon Sep 17 00:00:00 2001 From: Deborah Soung Date: Fri, 16 Feb 2024 13:47:54 -0800 Subject: [PATCH 1/3] remove extra bit from addr width --- src/main/scala/chisel3/util/SRAM.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/chisel3/util/SRAM.scala b/src/main/scala/chisel3/util/SRAM.scala index 9ffab068320..b69db7f4c64 100644 --- a/src/main/scala/chisel3/util/SRAM.scala +++ b/src/main/scala/chisel3/util/SRAM.scala @@ -104,7 +104,7 @@ class SRAMInterface[T <: Data]( s"SRAMInterface_${SRAM.portedness(numReadPorts, numWritePorts, numReadwritePorts)}${if (masked) "_masked" else ""}}_${tpe.typeName}" - val addrWidth = log2Up(memSize + 1) + val addrWidth = log2Up(memSize) val readPorts: Vec[MemoryReadPort[T]] = Vec(numReadPorts, new MemoryReadPort(tpe, addrWidth)) val writePorts: Vec[MemoryWritePort[T]] = Vec(numWritePorts, new MemoryWritePort(tpe, addrWidth, masked)) From 2486a2059386ab31949911288b3adc1e333c2da3 Mon Sep 17 00:00:00 2001 From: Deborah Soung Date: Fri, 16 Feb 2024 13:54:52 -0800 Subject: [PATCH 2/3] update test --- src/test/scala/chiselTests/util/SRAMSpec.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/test/scala/chiselTests/util/SRAMSpec.scala b/src/test/scala/chiselTests/util/SRAMSpec.scala index 7a45fa7158a..79974e1d1ea 100644 --- a/src/test/scala/chiselTests/util/SRAMSpec.scala +++ b/src/test/scala/chiselTests/util/SRAMSpec.scala @@ -35,7 +35,7 @@ class SRAMSpec extends ChiselFlatSpec { chirrtl should include("module Top :") chirrtl should include("smem sram_mem : UInt<8> [32]") chirrtl should include( - "wire sram : { readPorts : { flip address : UInt<6>, flip enable : UInt<1>, data : UInt<8>}[0], writePorts : { flip address : UInt<6>, flip enable : UInt<1>, flip data : UInt<8>}[0], readwritePorts : { flip address : UInt<6>, flip enable : UInt<1>, flip isWrite : UInt<1>, readData : UInt<8>, flip writeData : UInt<8>}[1]}" + "wire sram : { readPorts : { flip address : UInt<5>, flip enable : UInt<1>, data : UInt<8>}[0], writePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip data : UInt<8>}[0], readwritePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip isWrite : UInt<1>, readData : UInt<8>, flip writeData : UInt<8>}[1]}" ) val dummyAnno = annos.collectFirst { case DummyAnno(t) => (t.toString) } From b12ffd02f9b6d55c82bfad26fd2814203f6c0738 Mon Sep 17 00:00:00 2001 From: Deborah Soung Date: Fri, 16 Feb 2024 14:20:39 -0800 Subject: [PATCH 3/3] more test fixes --- src/test/scala/chiselTests/Mem.scala | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/test/scala/chiselTests/Mem.scala b/src/test/scala/chiselTests/Mem.scala index a854a0195c7..16330f2584c 100644 --- a/src/test/scala/chiselTests/Mem.scala +++ b/src/test/scala/chiselTests/Mem.scala @@ -529,10 +529,10 @@ class SRAMSpec extends ChiselFunSpec { val chirrtl = ChiselStage.emitCHIRRTL(new TestModule(1, 1), args = Array("--full-stacktrace")) chirrtl should include( - "writePorts : { flip address : UInt<6>, flip enable : UInt<1>, flip data : UInt<8>[3], flip mask : UInt<1>[3]}[1]" + "writePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip data : UInt<8>[3], flip mask : UInt<1>[3]}[1]" ) chirrtl should include( - "readwritePorts : { flip address : UInt<6>, flip enable : UInt<1>, flip isWrite : UInt<1>, readData : UInt<8>[3], flip writeData : UInt<8>[3], flip mask : UInt<1>[3]}[1]" + "readwritePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip isWrite : UInt<1>, readData : UInt<8>[3], flip writeData : UInt<8>[3], flip mask : UInt<1>[3]}[1]" ) for (i <- 0 until 3) { @@ -576,13 +576,13 @@ class SRAMSpec extends ChiselFunSpec { val wrIndexSuffix = if (i == 0) "" else s"_$i" chirrtl should include( - s"read mport mem_out_readPorts_${i}_data_MPORT = mem_mem[_mem_out_readPorts_${i}_data_T], readClocks[${i}]" + s"read mport mem_out_readPorts_${i}_data_MPORT = mem_mem[_mem_out_readPorts_${i}_data_WIRE], readClocks[${i}]" ) chirrtl should include( - s"write mport mem_MPORT${wrIndexSuffix} = mem_mem[_mem_T${wrIndexSuffix}], writeClocks[${i}]" + s"write mport mem_MPORT${wrIndexSuffix} = mem_mem[mem.writePorts[${i}].address], writeClocks[${i}]" ) chirrtl should include( - s"rdwr mport mem_out_readwritePorts_${i}_readData_MPORT = mem_mem[_mem_out_readwritePorts_${i}_readData_T], readwriteClocks[${i}]" + s"rdwr mport mem_out_readwritePorts_${i}_readData_MPORT = mem_mem[_mem_out_readwritePorts_${i}_readData_WIRE], readwriteClocks[${i}]" ) } }