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Please provide the steps to reproduce the problem:
Consider the following Chisel:
//>usingrepository"sonatype-s01:snapshots"//>usingscala"2.13.12"//>usingdep"org.chipsalliance::chisel:7.0.0-M1+133-2314926b-SNAPSHOT"//>usingplugin"org.chipsalliance:::chisel-plugin:7.0.0-M1+133-2314926b-SNAPSHOT"//>usingoptions"-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"importchisel3._importchisel3.experimental.Analogimportchisel3.experimental.hierarchy._// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._import_root_.circt.stage.ChiselStage@instantiable
classChildextendsRawModule {
@public valport=Wire(Analog(8.W))
}
classFooextendsModule {
valchild=Instantiate(newChild)
println(child.port)
}
objectMainextendsApp {
println(
ChiselStage.emitSystemVerilog(
gen =newFoo,
firtoolOpts =Array("-disable-all-randomization", "-strip-debug-info")
)
)
}
What is the current behavior?
If you run this, you'll get the following exception:
Exception in thread "main" chisel3.package$ChiselException: Analog can only be Ports and Wires, not 'CrossModuleBinding'
at ... ()
at Child$Childfresh$macro$2.port(chisel-example.scala:15)
at Foo.<init>(chisel-example.scala:20)
at Main$.$anonfun$new$1(chisel-example.scala:26)
at chisel3.Module$.evaluate(Module.scala:93)
at chisel3.Module$.do_apply(Module.scala:36)
at chisel3.stage.phases.Elaborate.$anonfun$transform$2(Elaborate.scala:53)
at chisel3.internal.Builder$.$anonfun$buildImpl$1(Builder.scala:1046)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:59)
at chisel3.internal.Builder$.buildImpl(Builder.scala:1040)
at chisel3.internal.Builder$.$anonfun$build$1(Builder.scala:1032)
at logger.Logger$.$anonfun$makeScope$4(Logger.scala:148)
at scala.util.DynamicVariable.withValue(DynamicVariable.scala:59)
at logger.Logger$.makeScope(Logger.scala:146)
at logger.Logger$.makeScope(Logger.scala:133)
at ... ()
at ... (Stack trace trimmed to user code only. Rerun with --full-stacktrace to see the full stack trace)
What is the expected behavior?
This should work, it probably just involves tweaking the implementation of bind in Analog.
Please tell us about your environment:
Other Information
What is the use case for changing the behavior?
The text was updated successfully, but these errors were encountered:
Type of issue: Bug Report
Please provide the steps to reproduce the problem:
Consider the following Chisel:
What is the current behavior?
If you run this, you'll get the following exception:
What is the expected behavior?
This should work, it probably just involves tweaking the implementation of
bind
inAnalog
.Please tell us about your environment:
Other Information
What is the use case for changing the behavior?
The text was updated successfully, but these errors were encountered: