From d64f37bea0a3c90f91996264895df80fb9aae9dd Mon Sep 17 00:00:00 2001
From: Jack Koenig <koenig@sifive.com>
Date: Thu, 18 Jan 2024 15:46:03 -0800
Subject: [PATCH] Make implicitClock and implicitReset protected

---
 core/src/main/scala/chisel3/Module.scala   | 12 ++++++------
 src/test/scala/chiselTests/ClockSpec.scala |  6 +++---
 src/test/scala/chiselTests/ResetSpec.scala |  6 +++---
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala
index 081b795310c..4cfa8dcea54 100644
--- a/core/src/main/scala/chisel3/Module.scala
+++ b/core/src/main/scala/chisel3/Module.scala
@@ -237,8 +237,8 @@ abstract class Module extends RawModule with ImplicitClock with ImplicitReset {
   final val reset: Reset = IO(Input(mkReset))(this._sourceInfo).suggestName("reset")
   // TODO add a way to memoize hasBeenReset iff it is used
 
-  override def implicitClock: Clock = clock
-  override def implicitReset: Reset = reset
+  override protected def implicitClock: Clock = clock
+  override protected def implicitReset: Reset = reset
 
   private[chisel3] def mkReset: Reset = {
     // Top module and compatibility mode use Bool for reset
@@ -278,7 +278,7 @@ abstract class Module extends RawModule with ImplicitClock with ImplicitReset {
   *   // Define a Clock value, it need not be called "implicitClock"
   *   val clk = IO(Input(Clock()))
   *   // Implement the virtual method to tell Chisel about this Clock value
-  *   override def implicitClock = clk
+  *   override protected def implicitClock = clk
   *   // Now we have a Clock to use in this RawModule
   *   val reg = Reg(UInt(8.W))
   * }
@@ -287,7 +287,7 @@ abstract class Module extends RawModule with ImplicitClock with ImplicitReset {
 trait ImplicitClock { self: RawModule =>
 
   /** Method that should point to the user-defined Clock */
-  def implicitClock: Clock
+  protected def implicitClock: Clock
 
   Builder.currentClock = Some(Delayed(implicitClock))
 }
@@ -304,7 +304,7 @@ trait ImplicitClock { self: RawModule =>
   *   // Define a Reset value, it need not be called "implicitReset"
   *   val rst = IO(Input(AsyncReset()))
   *   // Implement the virtual method to tell Chisel about this Reset value
-  *   override def implicitReset = clk
+  *   override protected def implicitReset = clk
   *   // Now we have a Reset to use in this RawModule
   *   // Registers also require a clock
   *   val clock = IO(Input(Clock()))
@@ -315,7 +315,7 @@ trait ImplicitClock { self: RawModule =>
 trait ImplicitReset { self: RawModule =>
 
   /** Method that should point to the user-defined Reset */
-  def implicitReset: Reset
+  protected def implicitReset: Reset
 
   Builder.currentReset = Some(Delayed(implicitReset))
 }
diff --git a/src/test/scala/chiselTests/ClockSpec.scala b/src/test/scala/chiselTests/ClockSpec.scala
index 026d376b563..7607a1db58e 100644
--- a/src/test/scala/chiselTests/ClockSpec.scala
+++ b/src/test/scala/chiselTests/ClockSpec.scala
@@ -40,7 +40,7 @@ class ClockSpec extends ChiselPropSpec {
       val in = IO(Input(UInt(8.W)))
       val out = IO(Output(UInt(8.W)))
       val gatedClock = (clock.asBool || gate).asClock
-      override def implicitClock = gatedClock
+      override protected def implicitClock = gatedClock
 
       val r = Reg(UInt(8.W))
       out := r
@@ -55,7 +55,7 @@ class ClockSpec extends ChiselPropSpec {
       val foo = IO(Input(Bool()))
       val in = IO(Input(UInt(8.W)))
       val out = IO(Output(UInt(8.W)))
-      override val implicitClock = (!foo).asClock
+      override protected val implicitClock = (!foo).asClock
 
       val r = Reg(UInt(8.W))
       out := r
@@ -70,7 +70,7 @@ class ClockSpec extends ChiselPropSpec {
         new RawModule with ImplicitClock {
           val r = Reg(UInt(8.W))
           val foo = IO(Input(Clock()))
-          override def implicitClock = foo
+          override protected def implicitClock = foo
         },
         args = Array("--throw-on-first-error")
       )
diff --git a/src/test/scala/chiselTests/ResetSpec.scala b/src/test/scala/chiselTests/ResetSpec.scala
index fd1aff09275..d040302a32c 100644
--- a/src/test/scala/chiselTests/ResetSpec.scala
+++ b/src/test/scala/chiselTests/ResetSpec.scala
@@ -108,7 +108,7 @@ class ResetSpec extends ChiselFlatSpec with Utils {
       val gate = IO(Input(Bool()))
       val in = IO(Input(UInt(8.W)))
       val out = IO(Output(UInt(8.W)))
-      override val implicitReset = reset.asBool || gate
+      override protected val implicitReset = reset.asBool || gate
       val r = RegInit(0.U)
       out := r
       r := in
@@ -121,7 +121,7 @@ class ResetSpec extends ChiselFlatSpec with Utils {
       val foo = IO(Input(Bool()))
       val in = IO(Input(UInt(8.W)))
       val out = IO(Output(UInt(8.W)))
-      override val implicitReset = !foo
+      override protected val implicitReset = !foo
 
       val clk = IO(Input(Clock()))
       val r = withClock(clk)(RegInit(0.U))
@@ -160,7 +160,7 @@ class ResetSpec extends ChiselFlatSpec with Utils {
         new RawModule with ImplicitReset {
           val r = Module.reset
           val foo = IO(Input(AsyncReset()))
-          override def implicitReset = foo
+          override protected def implicitReset = foo
         },
         args = Array("--throw-on-first-error")
       )