From a2ad31e6c5d87ff8143ad4d192ea13f63247d627 Mon Sep 17 00:00:00 2001
From: Aditya Naik <aditya.naik@sifive.com>
Date: Thu, 21 Jul 2022 16:33:00 -0700
Subject: [PATCH] Updates

---
 core/src/main/scala/chisel3/RawModule.scala    | 18 ++++++++----------
 .../main/scala/chisel3/internal/Builder.scala  |  4 ++--
 2 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala
index 8665e35e4a4..bc37b23428a 100644
--- a/core/src/main/scala/chisel3/RawModule.scala
+++ b/core/src/main/scala/chisel3/RawModule.scala
@@ -43,15 +43,13 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends
 
   val compileOptions = moduleCompileOptions
 
-  private[chisel3] def checkPorts(names: HashMap[HasId, String]): Unit = {
+  private[chisel3] def checkPorts(): Unit = {
     for (port <- getModulePorts) {
-      port._computeName(None, None).orElse(names.get(port)) match {
-        case Some(name) =>
-        case None =>
-          Builder.error(
-            s"Unable to name port $port in $this, " +
-              "try making it a public field of the Module"
-          )
+      if (port._computeName(None).isEmpty) {
+        Builder.error(
+          s"Unable to name port $port in $this, " +
+            "try making it a public field of the Module"
+        )
       }
     }
   }
@@ -61,7 +59,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends
     _closed = true
 
     // Ports get first naming priority, since they are part of a Module's IO spec
-    checkPorts(names)
+    checkPorts()
 
     // Now that elaboration is complete for this Module, we can finalize names
     for (id <- getIds) {
@@ -83,7 +81,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends
               case MemoryPortBinding(_, _) =>
                 id.forceName(default = "MPORT", _namespace)
               case PortBinding(_) =>
-                id.forceName(None, default = "PORT", _namespace, true, x => ModuleIO(this, x))
+                id.forceName(default = "PORT", _namespace, true, x => ModuleIO(this, x))
               case RegBinding(_, _) =>
                 id.forceName(default = "REG", _namespace)
               case WireBinding(_, _) =>
diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala
index a7fcf610e50..afb694ac1eb 100644
--- a/core/src/main/scala/chisel3/internal/Builder.scala
+++ b/core/src/main/scala/chisel3/internal/Builder.scala
@@ -192,14 +192,13 @@ private[chisel3] trait HasId extends InstanceId {
   // Will not do any naming if the reference already assigned.
   // (e.g. tried to suggest a name to part of a Record)
   private[chisel3] def forceName(
-    prefix:     Option[String],
     default:    => String,
     namespace:  Namespace,
     errorIfDup: Boolean = false,
     refBuilder: String => Arg = Ref(_)
   ): Unit =
     if (_ref.isEmpty) {
-      val candidate_name = _computeName(prefix, Some(default).filterNot(_ => errorIfDup)).get
+      val candidate_name = _computeName(Some(default).filterNot(_ => errorIfDup)).get
       val available_name = namespace.name(candidate_name)
       println(s"candidate: $candidate_name, available: $available_name")
       if (errorIfDup && (available_name != candidate_name)) {
@@ -209,6 +208,7 @@ private[chisel3] trait HasId extends InstanceId {
       // Clear naming prefix to free memory
       naming_prefix = Nil
     }
+
   private var _ref: Option[Arg] = None
   private[chisel3] def setRef(imm: Arg): Unit = setRef(imm, false)
   private[chisel3] def setRef(imm: Arg, force: Boolean): Unit = {