From 9f8287a53399c133a2bdb684e606b6331128c6bf Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Fri, 24 May 2024 12:03:39 -0700 Subject: [PATCH] Resolve backport conflicts --- core/src/main/scala/chisel3/RawModule.scala | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala index f8d79edd255..a5f60d8e840 100644 --- a/core/src/main/scala/chisel3/RawModule.scala +++ b/core/src/main/scala/chisel3/RawModule.scala @@ -210,19 +210,14 @@ abstract class RawModule extends BaseModule { case (false, true) => Connect(si, left.lref, ProbeRead(Node(right))) case (false, false) => (left, right) match { -<<<<<<< HEAD case (_: Property[_], _: Property[_]) => PropAssign(si, left.lref, Node(right)) - case (_, _) => Connect(si, left.lref, Node(right)) -======= - case (_: Property[_], _: Property[_]) => PropAssign(si, Node(left), Node(right)) // Use `connect lhs, read(probe(rhs))` if lhs is passive version of rhs. // This provides solution for this: https://github.com/chipsalliance/chisel/issues/3557 case (_, _) if !DataMirror.checkAlignmentTypeEquivalence(left, right) && DataMirror.checkAlignmentTypeEquivalence(left, Output(chiselTypeOf(right))) => Connect(si, Node(left), ProbeRead(ProbeExpr(Node(right)))) - case (_, _) => Connect(si, Node(left), Node(right)) ->>>>>>> 0dbedc315 (Fix boring tap of non-passive source from parent. (#4083)) + case (_, _) => Connect(si, left.lref, Node(right)) } } val secretCommands = if (_closed) {