diff --git a/src/integration/rtl/caliptra_top.sv b/src/integration/rtl/caliptra_top.sv
index 70713f359..223697994 100755
--- a/src/integration/rtl/caliptra_top.sv
+++ b/src/integration/rtl/caliptra_top.sv
@@ -42,6 +42,7 @@ module caliptra_top
     input logic                        jtag_tdi,    // JTAG tdi
     input logic                        jtag_trst_n, // JTAG Reset
     output logic                       jtag_tdo,    // JTAG TDO
+    output logic                       jtag_tdoEn,  // JTAG TDO enable
 
     //APB Interface
     input  logic [`CALIPTRA_APB_ADDR_WIDTH-1:0] PADDR,
@@ -492,8 +493,9 @@ el2_veer_wrapper rvtop (
     .jtag_tck               ( jtag_tck  ),
     .jtag_tms               ( jtag_tms  ),
     .jtag_tdi               ( jtag_tdi  ),
-    .jtag_trst_n            ( jtag_trst_n  ),
+    .jtag_trst_n            ( jtag_trst_n ),
     .jtag_tdo               ( jtag_tdo ),
+    .jtag_tdoEn             ( jtag_tdoEn ),
 
     //caliptra uncore jtag ports
    .cptra_uncore_dmi_reg_en      ( cptra_uncore_dmi_reg_en ),
diff --git a/src/integration/tb/caliptra_top_tb.sv b/src/integration/tb/caliptra_top_tb.sv
index 66de48009..18f0722ee 100755
--- a/src/integration/tb/caliptra_top_tb.sv
+++ b/src/integration/tb/caliptra_top_tb.sv
@@ -111,6 +111,7 @@ module caliptra_top_tb (
     logic                       jtag_tdi;    // JTAG tdi
     logic                       jtag_trst_n; // JTAG Reset
     logic                       jtag_tdo;    // JTAG TDO
+    logic                       jtag_tdoEn;  // JTAG TDO enable
     //APB Interface
     logic [`CALIPTRA_APB_ADDR_WIDTH-1:0] PADDR;
     logic [2:0]                          PPROT;
@@ -1079,6 +1080,7 @@ caliptra_top caliptra_top_dut (
     .jtag_tms(jtag_tms),
     .jtag_trst_n(jtag_trst_n),
     .jtag_tdo(jtag_tdo),
+    .jtag_tdoEn(jtag_tdoEn),
     
     .PADDR(PADDR),
     .PPROT(PPROT),
diff --git a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv
index ed10cc6da..1fca61c8a 100644
--- a/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv
+++ b/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/testbench/hdl_top.sv
@@ -108,6 +108,7 @@ import uvmf_base_pkg_hdl::*;
     logic                       jtag_tdi    = '0; // JTAG tdi
     logic                       jtag_trst_n = '0; // JTAG Reset
     logic                       jtag_tdo;    // JTAG TDO
+    logic                       jtag_tdoEn;  // JTAG TDO enable
 
     mbox_sram_req_t mbox_sram_req;
     mbox_sram_resp_t mbox_sram_resp;
@@ -196,6 +197,7 @@ import uvmf_base_pkg_hdl::*;
         .jtag_tms   (jtag_tms   ),
         .jtag_trst_n(jtag_trst_n),
         .jtag_tdo   (jtag_tdo   ),
+        .jtag_tdoEn (jtag_tdoEn ),
         
         .PADDR  (uvm_test_top_environment_soc_ifc_subenv_qvip_apb5_slave_subenv_qvip_hdl.apb5_master_0_PADDR      ),
         .PPROT  (3'b000/*FIXME*/                                                                                  ),
diff --git a/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv b/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv
index d7d1d3841..328aa20f1 100755
--- a/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv
+++ b/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv
@@ -305,7 +305,8 @@ import soc_ifc_pkg::*;
    input logic                             jtag_tdi,    // JTAG tdi
    input logic                             jtag_trst_n, // JTAG Reset
    output logic                            jtag_tdo,    // JTAG TDO
- 
+   output logic                            jtag_tdoEn,  // JTAG Test Data Output enable
+
    //caliptra uncore jtag ports
    output logic                            cptra_uncore_dmi_reg_en,
    output logic                            cptra_uncore_dmi_reg_wr_en,
@@ -404,7 +405,6 @@ import soc_ifc_pkg::*;
    logic [77:0]    iccm_rd_data_ecc;
 
    logic        core_rst_l;                         // Core reset including rst_l and dbg_rst_l
-   logic        jtag_tdoEn;
 
    logic        dccm_clk_override;
    logic        icm_clk_override;
@@ -719,7 +719,7 @@ import soc_ifc_pkg::*;
     .tms         (jtag_tms),        // Test mode select
     .tdi         (jtag_tdi),        // Test Data Input
     .tdo         (jtag_tdo),        // Test Data Output
-    .tdoEnable   (),
+    .tdoEnable   (jtag_tdoEn),      // Test Data Output enable
     // Processor Signals
     .core_rst_n  (dbg_rst_l),       // Debug reset, active low
     .core_clk    (clk),             // Core clock