From 0ab2fb210ba5afadb2908ec55f624446fcc884ce Mon Sep 17 00:00:00 2001 From: alaindargelas Date: Thu, 3 Oct 2024 18:32:19 -0700 Subject: [PATCH] Attribute support on nets --- include/Surelog/DesignCompile/CompileHelper.h | 3 +- src/DesignCompile/CompileHelper.cpp | 27 +- src/DesignCompile/CompileModule.cpp | 4 +- src/DesignCompile/CompilePackage.cpp | 2 +- src/DesignCompile/CompileProgram.cpp | 2 +- tests/AttributesNets/AttributesNets.log | 361 ++++++++++++++++++ tests/AttributesNets/AttributesNets.sl | 1 + tests/AttributesNets/dut.sv | 8 + .../tests/CoresSweRVMP/CoresSweRVMP.log | 12 +- third_party/tests/YosysIce40/YosysIce40.log | 2 +- third_party/tests/YosysVerx/YosysVerx.log | 2 +- third_party/tests/xgate/Xgate.log | 4 +- 12 files changed, 402 insertions(+), 26 deletions(-) create mode 100644 tests/AttributesNets/AttributesNets.log create mode 100644 tests/AttributesNets/AttributesNets.sl create mode 100644 tests/AttributesNets/dut.sv diff --git a/include/Surelog/DesignCompile/CompileHelper.h b/include/Surelog/DesignCompile/CompileHelper.h index 3e4d341ae8..f3d95dfb53 100644 --- a/include/Surelog/DesignCompile/CompileHelper.h +++ b/include/Surelog/DesignCompile/CompileHelper.h @@ -134,7 +134,8 @@ class CompileHelper final { bool compileNetDeclaration(DesignComponent* component, const FileContent* fC, NodeId id, bool interface, - CompileDesign* compileDesign); + CompileDesign* compileDesign, + UHDM::VectorOfattribute* attributes); bool compileDataDeclaration(DesignComponent* component, const FileContent* fC, NodeId id, bool interface, diff --git a/src/DesignCompile/CompileHelper.cpp b/src/DesignCompile/CompileHelper.cpp index 94ff787376..1ae3945df4 100644 --- a/src/DesignCompile/CompileHelper.cpp +++ b/src/DesignCompile/CompileHelper.cpp @@ -2039,7 +2039,8 @@ bool CompileHelper::compileAnsiPortDeclaration(DesignComponent* component, bool CompileHelper::compileNetDeclaration(DesignComponent* component, const FileContent* fC, NodeId id, bool interface, - CompileDesign* compileDesign) { + CompileDesign* compileDesign, + UHDM::VectorOfattribute* attributes) { /* n<> u<17> t p<18> l<27> n<> u<18> t p<22> c<17> s<21> l<27> @@ -2136,6 +2137,7 @@ bool CompileHelper::compileNetDeclaration(DesignComponent* component, if (portRef) portRef->setLowConn(sig); sig->setDelay(delay); sig->setStatic(); + sig->attributes(attributes); if (isSigned) sig->setSigned(); component->getSignals().push_back(sig); } @@ -4527,20 +4529,23 @@ std::vector* CompileHelper::compileAttributes( if (fC->Type(nodeId) == VObjectType::paAttribute_instance) { results = s.MakeAttributeVec(); while (fC->Type(nodeId) == VObjectType::paAttribute_instance) { - UHDM::attribute* attribute = s.MakeAttribute(); NodeId Attr_spec = fC->Child(nodeId); - NodeId Attr_name = fC->Child(Attr_spec); - const std::string_view name = fC->SymName(fC->Child(Attr_name)); - attribute->VpiName(name); - attribute->VpiParent(pexpr); - fC->populateCoreMembers(Attr_spec, Attr_spec, attribute); - results->push_back(attribute); - if (NodeId Constant_expression = fC->Sibling(Attr_name)) { - if (UHDM::expr* expr = (UHDM::expr*)compileExpression( + while (fC->Type(Attr_spec) == VObjectType::paAttr_spec) { + UHDM::attribute* attribute = s.MakeAttribute(); + NodeId Attr_name = fC->Child(Attr_spec); + const std::string_view name = fC->SymName(fC->Child(Attr_name)); + attribute->VpiName(name); + attribute->VpiParent(pexpr); + fC->populateCoreMembers(Attr_spec, Attr_spec, attribute); + results->push_back(attribute); + if (NodeId Constant_expression = fC->Sibling(Attr_name)) { + if (UHDM::expr* expr = (UHDM::expr*)compileExpression( component, fC, Constant_expression, compileDesign, Reduce::No, attribute)) { - attribute->VpiValue(expr->VpiValue()); + attribute->VpiValue(expr->VpiValue()); + } } + Attr_spec = fC->Sibling(Attr_spec); } nodeId = fC->Sibling(nodeId); } diff --git a/src/DesignCompile/CompileModule.cpp b/src/DesignCompile/CompileModule.cpp index 6e2f97292b..314cbfd1a3 100644 --- a/src/DesignCompile/CompileModule.cpp +++ b/src/DesignCompile/CompileModule.cpp @@ -618,7 +618,7 @@ bool CompileModule::collectModuleObjects_(CollectType collectType) { case VObjectType::paNet_declaration: { if (collectType != CollectType::DEFINITION) break; m_helper.compileNetDeclaration(m_module, fC, id, false, - m_compileDesign); + m_compileDesign, m_attributes); m_attributes = nullptr; break; } @@ -1091,7 +1091,7 @@ bool CompileModule::collectInterfaceObjects_(CollectType collectType) { case VObjectType::paNet_declaration: { if (collectType != CollectType::DEFINITION) break; m_helper.compileNetDeclaration(m_module, fC, id, true, - m_compileDesign); + m_compileDesign, m_attributes); m_attributes = nullptr; break; } diff --git a/src/DesignCompile/CompilePackage.cpp b/src/DesignCompile/CompilePackage.cpp index 7a27cc3102..fb3d1d88be 100644 --- a/src/DesignCompile/CompilePackage.cpp +++ b/src/DesignCompile/CompilePackage.cpp @@ -237,7 +237,7 @@ bool CompilePackage::collectObjects_(CollectType collectType, Reduce reduce) { case VObjectType::paNet_declaration: { if (collectType != CollectType::DEFINITION) break; m_helper.compileNetDeclaration(m_package, fC, id, false, - m_compileDesign); + m_compileDesign, m_attributes); m_attributes = nullptr; break; } diff --git a/src/DesignCompile/CompileProgram.cpp b/src/DesignCompile/CompileProgram.cpp index e25a3ae115..fd70961a8b 100644 --- a/src/DesignCompile/CompileProgram.cpp +++ b/src/DesignCompile/CompileProgram.cpp @@ -277,7 +277,7 @@ bool CompileProgram::collectObjects_(CollectType collectType) { case VObjectType::paNet_declaration: { if (collectType != CollectType::DEFINITION) break; m_helper.compileNetDeclaration(m_program, fC, id, false, - m_compileDesign); + m_compileDesign, m_attributes); m_attributes = nullptr; break; } diff --git a/tests/AttributesNets/AttributesNets.log b/tests/AttributesNets/AttributesNets.log new file mode 100644 index 0000000000..197a4e8a16 --- /dev/null +++ b/tests/AttributesNets/AttributesNets.log @@ -0,0 +1,361 @@ +[INF:CM0023] Creating log file "${SURELOG_DIR}/build/regression/AttributesNets/slpp_all/surelog.log". +AST_DEBUG_BEGIN +LIB: work +FILE: ${SURELOG_DIR}/tests/AttributesNets/dut.sv +n<> u<0> t<_INVALID_> f<0> l<0:0> +n<> u<1> t p<88> s<87> l<1:1> el<1:0> +n u<2> t p<6> s<3> l<1:1> el<1:7> +n u<3> t p<6> s<5> l<1:8> el<1:11> +n<> u<4> t p<5> l<1:12> el<1:12> +n<> u<5> t p<6> c<4> l<1:11> el<1:13> +n<> u<6> t p<85> c<2> s<35> l<1:1> el<1:14> +n u<7> t p<8> l<3:8> el<3:12> +n<> u<8> t p<9> c<7> l<3:8> el<3:12> +n<> u<9> t p<13> c<8> s<12> l<3:8> el<3:12> +n u<10> t p<11> l<3:15> el<3:23> +n<> u<11> t p<12> c<10> l<3:15> el<3:23> +n<> u<12> t p<13> c<11> l<3:15> el<3:23> +n<> u<13> t p<33> c<9> s<32> l<3:5> el<3:26> +n<> u<14> t p<29> s<25> l<3:27> el<3:31> +n<31> u<15> t p<16> l<3:39> el<3:41> +n<> u<16> t p<17> c<15> l<3:39> el<3:41> +n<> u<17> t p<18> c<16> l<3:39> el<3:41> +n<> u<18> t p<23> c<17> s<22> l<3:39> el<3:41> +n<0> u<19> t p<20> l<3:42> el<3:43> +n<> u<20> t p<21> c<19> l<3:42> el<3:43> +n<> u<21> t p<22> c<20> l<3:42> el<3:43> +n<> u<22> t p<23> c<21> l<3:42> el<3:43> +n<> u<23> t p<24> c<18> l<3:39> el<3:43> +n<> u<24> t p<25> c<23> l<3:38> el<3:44> +n<> u<25> t p<29> c<24> s<28> l<3:38> el<3:44> +n u<26> t p<27> l<3:47> el<3:58> +n<> u<27> t p<28> c<26> l<3:47> el<3:58> +n<> u<28> t p<29> c<27> l<3:47> el<3:58> +n<> u<29> t p<30> c<14> l<3:27> el<3:89> +n<> u<30> t p<31> c<29> l<3:27> el<3:89> +n<> u<31> t p<32> c<30> l<3:27> el<3:89> +n<> u<32> t p<33> c<31> l<3:27> el<3:89> +n<> u<33> t p<34> c<13> l<3:5> el<3:89> +n<> u<34> t p<35> c<33> l<3:5> el<3:89> +n<> u<35> t p<85> c<34> s<56> l<3:5> el<3:89> +n u<36> t p<37> l<4:8> el<4:17> +n<> u<37> t p<42> c<36> s<41> l<4:8> el<4:17> +n<"true"> u<38> t p<39> l<4:20> el<4:26> +n<> u<39> t p<40> c<38> l<4:20> el<4:26> +n<> u<40> t p<41> c<39> l<4:20> el<4:26> +n<> u<41> t p<42> c<40> l<4:20> el<4:26> +n<> u<42> t p<43> c<37> l<4:8> el<4:26> +n<> u<43> t p<54> c<42> s<53> l<4:5> el<4:29> +n<> u<44> t p<45> l<4:30> el<4:33> +n<> u<45> t p<49> c<44> s<48> l<4:30> el<4:33> +n u<46> t p<47> l<4:50> el<4:66> +n<> u<47> t p<48> c<46> l<4:50> el<4:66> +n<> u<48> t p<49> c<47> l<4:50> el<4:66> +n<> u<49> t p<50> c<45> l<4:30> el<4:67> +n<> u<50> t p<51> c<49> l<4:30> el<4:67> +n<> u<51> t p<52> c<50> l<4:30> el<4:67> +n<> u<52> t p<53> c<51> l<4:30> el<4:67> +n<> u<53> t p<54> c<52> l<4:30> el<4:67> +n<> u<54> t p<55> c<43> l<4:5> el<4:67> +n<> u<55> t p<56> c<54> l<4:5> el<4:67> +n<> u<56> t p<85> c<55> s<83> l<4:5> el<4:67> +n u<57> t p<58> l<5:8> el<5:16> +n<> u<58> t p<59> c<57> l<5:8> el<5:16> +n<> u<59> t p<60> c<58> l<5:8> el<5:16> +n<> u<60> t p<81> c<59> s<80> l<5:5> el<5:19> +n<> u<61> t p<72> s<71> l<5:20> el<5:23> +n u<62> t p<63> l<5:25> el<5:31> +n<> u<63> t p<64> c<62> l<5:25> el<5:31> +n<> u<64> t p<65> c<63> l<5:25> el<5:31> +n<> u<65> t p<70> c<64> s<69> l<5:25> el<5:31> +n<0> u<66> t p<67> l<5:32> el<5:33> +n<> u<67> t p<68> c<66> l<5:32> el<5:33> +n<> u<68> t p<69> c<67> l<5:32> el<5:33> +n<> u<69> t p<70> c<68> l<5:32> el<5:33> +n<> u<70> t p<71> c<65> l<5:25> el<5:33> +n<> u<71> t p<72> c<70> l<5:24> el<5:34> +n<> u<72> t p<76> c<61> s<75> l<5:20> el<5:34> +n u<73> t p<74> l<5:35> el<5:48> +n<> u<74> t p<75> c<73> l<5:35> el<5:48> +n<> u<75> t p<76> c<74> l<5:35> el<5:48> +n<> u<76> t p<77> c<72> l<5:20> el<5:49> +n<> u<77> t p<78> c<76> l<5:20> el<5:49> +n<> u<78> t p<79> c<77> l<5:20> el<5:49> +n<> u<79> t p<80> c<78> l<5:20> el<5:49> +n<> u<80> t p<81> c<79> l<5:20> el<5:49> +n<> u<81> t p<82> c<60> l<5:5> el<5:49> +n<> u<82> t p<83> c<81> l<5:5> el<5:49> +n<> u<83> t p<85> c<82> s<84> l<5:5> el<5:49> +n<> u<84> t p<85> l<7:1> el<7:10> +n<> u<85> t p<86> c<6> l<1:1> el<7:10> +n<> u<86> t p<87> c<85> l<1:1> el<7:10> +n<> u<87> t p<88> c<86> l<1:1> el<7:10> +n<> u<88> t c<1> l<1:1> el<9:1> +AST_DEBUG_END +[WRN:PA0205] ${SURELOG_DIR}/tests/AttributesNets/dut.sv:1:1: No timescale set for "top". +[INF:CP0300] Compilation... +[INF:CP0303] ${SURELOG_DIR}/tests/AttributesNets/dut.sv:1:1: Compile module "work@top". +[INF:EL0526] Design Elaboration... +[NTE:EL0503] ${SURELOG_DIR}/tests/AttributesNets/dut.sv:1:1: Top level module "work@top". +[NTE:EL0508] Nb Top level modules: 1. +[NTE:EL0509] Max instance depth: 1. +[NTE:EL0510] Nb instances: 1. +[NTE:EL0511] Nb leaf instances: 1. +[INF:UH0706] Creating UHDM Model... +=== UHDM Object Stats Begin (Non-Elaborated Model) === +attribute 4 +constant 10 +design 1 +logic_net 7 +logic_typespec 6 +module_inst 3 +range 6 +ref_obj 3 +ref_typespec 6 +=== UHDM Object Stats End === +[INF:UH0707] Elaborating UHDM... +=== UHDM Object Stats Begin (Elaborated Model) === +attribute 4 +constant 10 +design 1 +logic_net 7 +logic_typespec 6 +module_inst 3 +range 6 +ref_obj 3 +ref_typespec 6 +=== UHDM Object Stats End === +[INF:UH0708] Writing UHDM DB: ${SURELOG_DIR}/build/regression/AttributesNets/slpp_all/surelog.uhdm ... +[INF:UH0709] Writing UHDM Html Coverage: ${SURELOG_DIR}/build/regression/AttributesNets/slpp_all/checker/surelog.chk.html ... +[INF:UH0710] Loading UHDM DB: ${SURELOG_DIR}/build/regression/AttributesNets/slpp_all/surelog.uhdm ... +[INF:UH0711] Decompiling UHDM... +====== UHDM ======= +design: (work@top) +|vpiElaborated:1 +|vpiName:work@top +|uhdmallModules: +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AttributesNets/dut.sv, line:1:1, endln:7:10 + |vpiParent: + \_design: (work@top) + |vpiFullName:work@top + |vpiDefName:work@top + |vpiNet: + \_logic_net: (work@top.execute_RS1), line:3:47, endln:3:58 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AttributesNets/dut.sv, line:1:1, endln:7:10 + |vpiTypespec: + \_ref_typespec: (work@top.execute_RS1) + |vpiParent: + \_logic_net: (work@top.execute_RS1), line:3:47, endln:3:58 + |vpiFullName:work@top.execute_RS1 + |vpiActual: + \_logic_typespec: , line:3:27, endln:3:44 + |vpiName:execute_RS1 + |vpiFullName:work@top.execute_RS1 + |vpiNetType:1 + |vpiNet: + \_logic_net: (work@top.system_rsp_valid), line:4:50, endln:4:66 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AttributesNets/dut.sv, line:1:1, endln:7:10 + |vpiTypespec: + \_ref_typespec: (work@top.system_rsp_valid) + |vpiParent: + \_logic_net: (work@top.system_rsp_valid), line:4:50, endln:4:66 + |vpiFullName:work@top.system_rsp_valid + |vpiActual: + \_logic_typespec: , line:4:30, endln:4:33 + |vpiName:system_rsp_valid + |vpiFullName:work@top.system_rsp_valid + |vpiNetType:48 + |vpiNet: + \_logic_net: (work@top.fw_first_addr), line:5:35, endln:5:48 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AttributesNets/dut.sv, line:1:1, endln:7:10 + |vpiTypespec: + \_ref_typespec: (work@top.fw_first_addr) + |vpiParent: + \_logic_net: (work@top.fw_first_addr), line:5:35, endln:5:48 + |vpiFullName:work@top.fw_first_addr + |vpiActual: + \_logic_typespec: , line:5:20, endln:5:34 + |vpiName:fw_first_addr + |vpiFullName:work@top.fw_first_addr + |vpiNetType:48 + |vpiNet: + \_logic_net: (work@top.LGFLEN), line:5:25, endln:5:31 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AttributesNets/dut.sv, line:1:1, endln:7:10 + |vpiName:LGFLEN + |vpiFullName:work@top.LGFLEN + |vpiNetType:1 +|uhdmtopModules: +\_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AttributesNets/dut.sv, line:1:1, endln:7:10 + |vpiName:work@top + |vpiDefName:work@top + |vpiTop:1 + |vpiNet: + \_logic_net: (work@top.execute_RS1), line:3:47, endln:3:58 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AttributesNets/dut.sv, line:1:1, endln:7:10 + |vpiTypespec: + \_ref_typespec: (work@top.execute_RS1) + |vpiParent: + \_logic_net: (work@top.execute_RS1), line:3:47, endln:3:58 + |vpiFullName:work@top.execute_RS1 + |vpiActual: + \_logic_typespec: , line:3:27, endln:3:44 + |vpiName:execute_RS1 + |vpiFullName:work@top.execute_RS1 + |vpiNetType:1 + |vpiAttribute: + \_attribute: (keep), line:3:8, endln:3:12 + |vpiParent: + \_logic_net: (work@top.execute_RS1), line:3:47, endln:3:58 + |vpiName:keep + |vpiAttribute: + \_attribute: (syn_keep), line:3:15, endln:3:23 + |vpiParent: + \_logic_net: (work@top.execute_RS1), line:3:47, endln:3:58 + |vpiName:syn_keep + |vpiNet: + \_logic_net: (work@top.system_rsp_valid), line:4:50, endln:4:66 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AttributesNets/dut.sv, line:1:1, endln:7:10 + |vpiTypespec: + \_ref_typespec: (work@top.system_rsp_valid) + |vpiParent: + \_logic_net: (work@top.system_rsp_valid), line:4:50, endln:4:66 + |vpiFullName:work@top.system_rsp_valid + |vpiActual: + \_logic_typespec: , line:4:30, endln:4:33 + |vpiName:system_rsp_valid + |vpiFullName:work@top.system_rsp_valid + |vpiNetType:48 + |vpiAttribute: + \_attribute: (async_reg), line:4:8, endln:4:26 + |vpiParent: + \_logic_net: (work@top.system_rsp_valid), line:4:50, endln:4:66 + |vpiName:async_reg + |STRING:true + |vpiNet: + \_logic_net: (work@top.fw_first_addr), line:5:35, endln:5:48 + |vpiParent: + \_module_inst: work@top (work@top), file:${SURELOG_DIR}/tests/AttributesNets/dut.sv, line:1:1, endln:7:10 + |vpiTypespec: + \_ref_typespec: (work@top.fw_first_addr) + |vpiParent: + \_logic_net: (work@top.fw_first_addr), line:5:35, endln:5:48 + |vpiFullName:work@top.fw_first_addr + |vpiActual: + \_logic_typespec: , line:5:20, endln:5:34 + |vpiName:fw_first_addr + |vpiFullName:work@top.fw_first_addr + |vpiNetType:48 + |vpiAttribute: + \_attribute: (anyconst), line:5:8, endln:5:16 + |vpiParent: + \_logic_net: (work@top.fw_first_addr), line:5:35, endln:5:48 + |vpiName:anyconst + |vpiTopModule:1 +\_weaklyReferenced: +\_logic_typespec: , line:3:27, endln:3:44 + |vpiParent: + \_logic_net: (work@top.execute_RS1), line:3:47, endln:3:58 + |vpiRange: + \_range: , line:3:38, endln:3:44 + |vpiParent: + \_logic_typespec: , line:3:27, endln:3:44 + |vpiLeftRange: + \_constant: , line:3:39, endln:3:41 + |vpiParent: + \_range: , line:3:38, endln:3:44 + |vpiDecompile:31 + |vpiSize:64 + |UINT:31 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:3:42, endln:3:43 + |vpiParent: + \_range: , line:3:38, endln:3:44 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: , line:4:30, endln:4:33 + |vpiParent: + \_logic_net: (work@top.system_rsp_valid), line:4:50, endln:4:66 +\_logic_typespec: , line:5:20, endln:5:34 + |vpiParent: + \_logic_net: (work@top.fw_first_addr), line:5:35, endln:5:48 + |vpiRange: + \_range: , line:5:24, endln:5:34 + |vpiParent: + \_logic_typespec: , line:5:20, endln:5:34 + |vpiLeftRange: + \_ref_obj: (work@top.fw_first_addr.LGFLEN), line:5:25, endln:5:31 + |vpiParent: + \_range: , line:5:24, endln:5:34 + |vpiName:LGFLEN + |vpiFullName:work@top.fw_first_addr.LGFLEN + |vpiActual: + \_logic_net: (work@top.LGFLEN), line:5:25, endln:5:31 + |vpiRightRange: + \_constant: , line:5:32, endln:5:33 + |vpiParent: + \_range: , line:5:24, endln:5:34 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: , line:3:27, endln:3:44 + |vpiRange: + \_range: , line:3:38, endln:3:44 + |vpiParent: + \_logic_typespec: , line:3:27, endln:3:44 + |vpiLeftRange: + \_constant: , line:3:39, endln:3:41 + |vpiParent: + \_range: , line:3:38, endln:3:44 + |vpiDecompile:31 + |vpiSize:64 + |UINT:31 + |vpiConstType:9 + |vpiRightRange: + \_constant: , line:3:42, endln:3:43 + |vpiParent: + \_range: , line:3:38, endln:3:44 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +\_logic_typespec: , line:4:30, endln:4:33 +\_logic_typespec: , line:5:20, endln:5:34 + |vpiRange: + \_range: , line:5:24, endln:5:34 + |vpiParent: + \_logic_typespec: , line:5:20, endln:5:34 + |vpiLeftRange: + \_ref_obj: (LGFLEN), line:5:25, endln:5:31 + |vpiParent: + \_range: , line:5:24, endln:5:34 + |vpiName:LGFLEN + |vpiActual: + \_logic_net: (work@top.LGFLEN), line:5:25, endln:5:31 + |vpiRightRange: + \_constant: , line:5:32, endln:5:33 + |vpiParent: + \_range: , line:5:24, endln:5:34 + |vpiDecompile:0 + |vpiSize:64 + |UINT:0 + |vpiConstType:9 +=================== +[ FATAL] : 0 +[ SYNTAX] : 0 +[ ERROR] : 0 +[WARNING] : 1 +[ NOTE] : 5 + +============================== Begin RoundTrip Results ============================== +[roundtrip]: ${SURELOG_DIR}/tests/AttributesNets/dut.sv | ${SURELOG_DIR}/build/regression/AttributesNets/roundtrip/dut_000.sv | 3 | 7 | +============================== End RoundTrip Results ============================== diff --git a/tests/AttributesNets/AttributesNets.sl b/tests/AttributesNets/AttributesNets.sl new file mode 100644 index 0000000000..b461620aca --- /dev/null +++ b/tests/AttributesNets/AttributesNets.sl @@ -0,0 +1 @@ +-parse -d uhdm -d coveruhdm -elabuhdm -d ast dut.sv -nobuiltin diff --git a/tests/AttributesNets/dut.sv b/tests/AttributesNets/dut.sv new file mode 100644 index 0000000000..9cbdb2925b --- /dev/null +++ b/tests/AttributesNets/dut.sv @@ -0,0 +1,8 @@ +module top(); + + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + (* async_reg = "true" *) reg system_rsp_valid; + (* anyconst *) reg [LGFLEN:0] fw_first_addr; + +endmodule + diff --git a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log index 6baf190014..920c95b79f 100644 --- a/third_party/tests/CoresSweRVMP/CoresSweRVMP.log +++ b/third_party/tests/CoresSweRVMP/CoresSweRVMP.log @@ -64,13 +64,13 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; -- Configuring done -- Generating done -- Build files have been written to: ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess -[ 6%] Generating 10_lsu_bus_intf.sv +[ 6%] Generating 11_ifu_bp_ctl.sv [ 12%] Generating 12_beh_lib.sv -[ 18%] Generating 11_ifu_bp_ctl.sv +[ 18%] Generating 10_lsu_bus_intf.sv [ 25%] Generating 13_ifu_mem_ctl.sv [ 31%] Generating 14_mem_lib.sv -[ 37%] Generating 15_exu.sv -[ 43%] Generating 16_dec_decode_ctl.sv +[ 37%] Generating 16_dec_decode_ctl.sv +[ 43%] Generating 15_exu.sv [ 50%] Generating 1_lsu_stbuf.sv [ 56%] Generating 2_ahb_to_axi4.sv [ 62%] Generating 3_rvjtag_tap.sv @@ -78,8 +78,8 @@ Running: cd ${SURELOG_DIR}/build/regression/CoresSweRVMP/slpp_all/mp_preprocess; [ 75%] Generating 5_lsu_bus_buffer.sv [ 81%] Generating 6_dbg.sv [ 87%] Generating 7_axi4_to_ahb.sv -[ 93%] Generating 9_tb_top.sv -[100%] Generating 8_ifu_aln_ctl.sv +[ 93%] Generating 8_ifu_aln_ctl.sv +[100%] Generating 9_tb_top.sv [100%] Built target Parse Surelog parsing status: 0 [INF:PA0201] Parsing source file "${SURELOG_DIR}/third_party/UVM/1800.2-2017-1.0/src/uvm_pkg.sv". diff --git a/third_party/tests/YosysIce40/YosysIce40.log b/third_party/tests/YosysIce40/YosysIce40.log index b96d2513ed..6e82d53ae6 100644 --- a/third_party/tests/YosysIce40/YosysIce40.log +++ b/third_party/tests/YosysIce40/YosysIce40.log @@ -340,7 +340,7 @@ there are 5 more instances of this message. always 179 array_net 11 assignment 5212 -attribute 17 +attribute 26 begin 726 bit_select 3742 case_item 698 diff --git a/third_party/tests/YosysVerx/YosysVerx.log b/third_party/tests/YosysVerx/YosysVerx.log index 0df633efe4..455acbe35d 100644 --- a/third_party/tests/YosysVerx/YosysVerx.log +++ b/third_party/tests/YosysVerx/YosysVerx.log @@ -26,7 +26,7 @@ there are 9 more instances of this message. === UHDM Object Stats Begin (Non-Elaborated Model) === always 294 assignment 1779 -attribute 1 +attribute 2 begin 1073 bit_select 550 case_item 534 diff --git a/third_party/tests/xgate/Xgate.log b/third_party/tests/xgate/Xgate.log index 42fc9daab8..5cc40219c6 100644 --- a/third_party/tests/xgate/Xgate.log +++ b/third_party/tests/xgate/Xgate.log @@ -2748,7 +2748,7 @@ there are 1 more instances of this message. === UHDM Object Stats Begin (Non-Elaborated Model) === always 2621 assignment 5419 -attribute 26992 +attribute 27036 begin 170 bit_select 21649 case_item 84 @@ -2801,7 +2801,7 @@ unsupported_typespec 160 === UHDM Object Stats Begin (Elaborated Model) === always 5140 assignment 12976 -attribute 37115 +attribute 39678 begin 170 bit_select 40716 case_item 84