SerDes App for GateMate

* WORK IN PROGRESS * UNDER CONSTRUCTION *

WHILE THIS NOTICE IS PRESENT, DON'T EXPECT DESIGN, SIM, OR ANY OTHER FILE IN HERE 2BE DOIN' WHAT IT'S SAYIN'

Design a high-speed serial, memory-mapped Chip-to-Chip (C2C) Interconnect. The goal of such IP is to set the stage for creating compute clusters and Hyper Cubes made of GateMate FPGAs, all interconnected via SerDes, with our C2C layer on top of it.

References:

• Xilinx PG046 - Aurora 8B/10B
  • Xilinx SP002 - Aurora 8B/10B Protocol Spec
• BerkeleyLab ChitChat protocol
• LiteX IC Link
• Transputer-like?
• CologneChip SerDes example design and latest datasheet
• MesaBusProtocol
• Timing-aware/better PNR for this high-speed design:
  • Project Peppercorn
  • nextpnr for GateMate

Public Announcements

2025-02-21

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