From aae5252421a9570668313582fdb1830ec47d4491 Mon Sep 17 00:00:00 2001 From: Francesca Capel Date: Wed, 18 Apr 2018 11:10:13 +0200 Subject: [PATCH] Fix bug in trig_pixel output --- l2_trigger/cpp_code/v10/l2_trigger.cpp | 4 +- .../.autopilot/db/__ctype_info__.xml | 193 -- .../.autopilot/db/l2_trigger.adb.xml | 2180 ++++++++--------- .../.autopilot/db/l2_trigger.bind.adb.xml | 2180 ++++++++--------- .../.autopilot/db/l2_trigger.design.xml | 20 +- .../.autopilot/db/l2_trigger.pp.0.cpp | 4 +- .../db/l2_trigger.pp.0.cpp.ap-cdt.cpp | 4 +- .../db/l2_trigger.pp.0.cpp.ap-line.cpp | 4 +- .../.autopilot/db/l2_trigger.pragma.0.cpp | 4 +- .../.autopilot/db/l2_trigger.pragma.1.cpp | 4 +- .../.autopilot/db/l2_trigger.pragma.2.cpp | 4 +- .../.autopilot/db/l2_trigger.sched.adb.xml | 786 +++--- .../.autopilot/db/l2_trigger.sdaccel.xml | 19 +- .../.autopilot/db/l2_trigger.tbgen.tcl | 28 +- .../.autopilot/db/l2_trigger.verbose.bind.rpt | 963 ++++---- .../db/l2_trigger.verbose.bind.rpt.xml | 8 +- .../.autopilot/db/l2_trigger.verbose.rpt | 980 ++++---- .../.autopilot/db/l2_trigger.verbose.rpt.xml | 19 +- .../db/l2_trigger.verbose.sched.rpt | 294 ++- .../db/l2_trigger.verbose.sched.rpt.xml | 8 +- .../solution1/impl/verilog/extraction.tcl | 1462 ----------- .../solution1/impl/verilog/l2_trigger.v | 1745 ------------- .../solution1/impl/verilog/l2_trigger.xdc | 7 - .../impl/verilog/l2_trigger_CTRL_BUS_s_axi.v | 361 --- .../impl/verilog/l2_trigger_data_shift1.v | 77 - .../impl/verilog/l2_trigger_sum_overP1.v | 77 - l2_trigger/solution1/impl/verilog/project.xpr | 147 -- .../solution1/impl/verilog/run_vivado.tcl | 71 - .../solution1/impl/verilog/settings.tcl | 21 - l2_trigger/solution1/script.tcl | 2 +- .../syn/report/l2_trigger_csynth.rpt | 25 +- .../syn/report/l2_trigger_csynth.xml | 14 +- .../solution1/syn/systemc/l2_trigger.cpp | 589 +++-- l2_trigger/solution1/syn/systemc/l2_trigger.h | 162 +- l2_trigger/solution1/syn/verilog/l2_trigger.v | 337 ++- l2_trigger/solution1/syn/vhdl/l2_trigger.vhd | 455 ++-- 36 files changed, 4456 insertions(+), 8802 deletions(-) delete mode 100644 l2_trigger/solution1/.autopilot/db/__ctype_info__.xml delete mode 100644 l2_trigger/solution1/impl/verilog/extraction.tcl delete mode 100644 l2_trigger/solution1/impl/verilog/l2_trigger.v delete mode 100644 l2_trigger/solution1/impl/verilog/l2_trigger.xdc delete mode 100644 l2_trigger/solution1/impl/verilog/l2_trigger_CTRL_BUS_s_axi.v delete mode 100644 l2_trigger/solution1/impl/verilog/l2_trigger_data_shift1.v delete mode 100644 l2_trigger/solution1/impl/verilog/l2_trigger_sum_overP1.v delete mode 100644 l2_trigger/solution1/impl/verilog/project.xpr delete mode 100755 l2_trigger/solution1/impl/verilog/run_vivado.tcl delete mode 100644 l2_trigger/solution1/impl/verilog/settings.tcl diff --git a/l2_trigger/cpp_code/v10/l2_trigger.cpp b/l2_trigger/cpp_code/v10/l2_trigger.cpp index c36089b..fa646ae 100644 --- a/l2_trigger/cpp_code/v10/l2_trigger.cpp +++ b/l2_trigger/cpp_code/v10/l2_trigger.cpp @@ -108,7 +108,7 @@ void l2_trigger(STREAM_32 &in_stream, STREAM_64 &out_stream, uint16_t n_pixels_i *trig_data = 0x00000000; //store the triggered pixel - *trig_data = i*2; + *trig_pixel = i*2; //Block for 128 GTU itrig = 1; @@ -122,7 +122,7 @@ void l2_trigger(STREAM_32 &in_stream, STREAM_64 &out_stream, uint16_t n_pixels_i *trig_data = 0x00000000; //store the triggered pixel - *trig_data = (i*2) + 1; + *trig_pixel = (i*2) + 1; //Block for 128 GTU itrig = 1; diff --git a/l2_trigger/solution1/.autopilot/db/__ctype_info__.xml b/l2_trigger/solution1/.autopilot/db/__ctype_info__.xml deleted file mode 100644 index 6d66b2b..0000000 --- a/l2_trigger/solution1/.autopilot/db/__ctype_info__.xml +++ /dev/null @@ -1,193 +0,0 @@ - - -in_stream_V_data_V - -ap_int 32 -32 -32 - -0 -0 - - -in_stream_V_keep_V - -ap_uint 4 -4 -4 - -0 -0 - - -in_stream_V_strb_V - -ap_uint 4 -4 -4 - -0 -0 - - -in_stream_V_user_V - -ap_uint 2 -2 -2 - -0 -0 - - -in_stream_V_last_V - -ap_uint 1 -1 -1 - -0 -0 - - -in_stream_V_id_V - -ap_uint 5 -5 -5 - -0 -0 - - -in_stream_V_dest_V - -ap_uint 6 -6 -6 - -0 -0 - - -out_stream_V_data_V - -ap_int 64 -64 -64 - -0 -0 - - -out_stream_V_keep_V - -ap_uint 8 -8 -8 - -0 -0 - - -out_stream_V_strb_V - -ap_uint 8 -8 -8 - -0 -0 - - -out_stream_V_user_V - -ap_uint 2 -2 -2 - -0 -0 - - -out_stream_V_last_V - -ap_uint 1 -1 -1 - -0 -0 - - -out_stream_V_id_V - -ap_uint 5 -5 -5 - -0 -0 - - -out_stream_V_dest_V - -ap_uint 6 -6 -6 - -0 -0 - - -n_pixels_in_bus - -unsigned short -16 -16 - -0 -0 - - -N_BG - -unsigned char -8 -8 - -0 -0 - - -LOW_THRESH - -unsigned int -32 -32 - -0 -0 - - -trig_data - -unsigned int -32 -32 - -0 -0 - - -trig_pixel - -unsigned int -32 -32 - -0 -0 - - - diff --git a/l2_trigger/solution1/.autopilot/db/l2_trigger.adb.xml b/l2_trigger/solution1/.autopilot/db/l2_trigger.adb.xml index 185a7ac..3f12692 100644 --- a/l2_trigger/solution1/.autopilot/db/l2_trigger.adb.xml +++ b/l2_trigger/solution1/.autopilot/db/l2_trigger.adb.xml @@ -3,224 +3,212 @@ - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - + - - - - - - - - - - - - - - + + - - + + - - + + - - + + - - + + @@ -232,7 +220,7 @@ - + NULL @@ -247,7 +235,7 @@ arrayctor.loop1.preheader:0 call void (...)* @_ssdm_op_SpecBitsMap(i32* %in_str - + NULL @@ -262,7 +250,7 @@ arrayctor.loop1.preheader:1 call void (...)* @_ssdm_op_SpecBitsMap(i4* %in_stre - + NULL @@ -277,7 +265,7 @@ arrayctor.loop1.preheader:2 call void (...)* @_ssdm_op_SpecBitsMap(i4* %in_stre - + NULL @@ -292,7 +280,7 @@ arrayctor.loop1.preheader:3 call void (...)* @_ssdm_op_SpecBitsMap(i2* %in_stre - + NULL @@ -307,7 +295,7 @@ arrayctor.loop1.preheader:4 call void (...)* @_ssdm_op_SpecBitsMap(i1* %in_stre - + NULL @@ -322,7 +310,7 @@ arrayctor.loop1.preheader:5 call void (...)* @_ssdm_op_SpecBitsMap(i5* %in_stre - + NULL @@ -337,7 +325,7 @@ arrayctor.loop1.preheader:6 call void (...)* @_ssdm_op_SpecBitsMap(i6* %in_stre - + NULL @@ -352,7 +340,7 @@ arrayctor.loop1.preheader:7 call void (...)* @_ssdm_op_SpecBitsMap(i64* %out_st - + NULL @@ -367,7 +355,7 @@ arrayctor.loop1.preheader:8 call void (...)* @_ssdm_op_SpecBitsMap(i8* %out_str - + NULL @@ -382,7 +370,7 @@ arrayctor.loop1.preheader:9 call void (...)* @_ssdm_op_SpecBitsMap(i8* %out_str - + NULL @@ -397,7 +385,7 @@ arrayctor.loop1.preheader:10 call void (...)* @_ssdm_op_SpecBitsMap(i2* %out_st - + NULL @@ -412,7 +400,7 @@ arrayctor.loop1.preheader:11 call void (...)* @_ssdm_op_SpecBitsMap(i1* %out_st - + NULL @@ -427,7 +415,7 @@ arrayctor.loop1.preheader:12 call void (...)* @_ssdm_op_SpecBitsMap(i5* %out_st - + NULL @@ -442,7 +430,7 @@ arrayctor.loop1.preheader:13 call void (...)* @_ssdm_op_SpecBitsMap(i6* %out_st - + NULL @@ -457,7 +445,7 @@ arrayctor.loop1.preheader:14 call void (...)* @_ssdm_op_SpecBitsMap(i16 %n_pixe - + NULL @@ -472,7 +460,7 @@ arrayctor.loop1.preheader:15 call void (...)* @_ssdm_op_SpecBitsMap(i8 %N_BG), - + NULL @@ -487,7 +475,7 @@ arrayctor.loop1.preheader:16 call void (...)* @_ssdm_op_SpecBitsMap(i32 %LOW_TH - + NULL @@ -502,7 +490,7 @@ arrayctor.loop1.preheader:17 call void (...)* @_ssdm_op_SpecBitsMap(i32* %trig_ - + NULL @@ -517,7 +505,7 @@ arrayctor.loop1.preheader:18 call void (...)* @_ssdm_op_SpecBitsMap(i32* %trig_ - + NULL @@ -532,7 +520,7 @@ arrayctor.loop1.preheader:19 call void (...)* @_ssdm_op_SpecTopModule([11 x i8] - + s_axilite @@ -547,7 +535,7 @@ arrayctor.loop1.preheader:20 %LOW_THRESH_read = call i32 @_ssdm_op_Read.s_axili - + s_axilite @@ -562,7 +550,7 @@ arrayctor.loop1.preheader:21 %N_BG_read = call i8 @_ssdm_op_Read.s_axilite.i8(i - + s_axilite @@ -577,7 +565,7 @@ arrayctor.loop1.preheader:22 %n_pixels_in_bus_read = call i16 @_ssdm_op_Read.s_ - + RAM @@ -593,7 +581,7 @@ arrayctor.loop1.preheader:23 %sum_overP1 = alloca [1152 x i32], align 16 - + RAM @@ -609,7 +597,7 @@ arrayctor.loop1.preheader:24 %sum_overP2 = alloca [1152 x i32], align 16 - + RAM @@ -625,7 +613,7 @@ arrayctor.loop1.preheader:25 %sum_pix1 = alloca [1152 x i32], align 16 - + RAM @@ -641,7 +629,7 @@ arrayctor.loop1.preheader:26 %data_shift1 = alloca [9216 x i17], align 4 - + RAM @@ -657,7 +645,7 @@ arrayctor.loop1.preheader:27 %thresh1 = alloca [1152 x i32], align 16 - + RAM @@ -673,7 +661,7 @@ arrayctor.loop1.preheader:28 %sum_pix2 = alloca [1152 x i32], align 16 - + RAM @@ -689,7 +677,7 @@ arrayctor.loop1.preheader:29 %data_shift2 = alloca [9216 x i17], align 4 - + RAM @@ -705,7 +693,7 @@ arrayctor.loop1.preheader:30 %thresh2 = alloca [1152 x i32], align 16 - + NULL @@ -720,7 +708,7 @@ arrayctor.loop1.preheader:31 call void (...)* @_ssdm_op_SpecInterface(i32* %in_ - + NULL @@ -735,7 +723,7 @@ arrayctor.loop1.preheader:32 call void (...)* @_ssdm_op_SpecInterface(i32* %tri - + NULL @@ -750,7 +738,7 @@ arrayctor.loop1.preheader:33 call void (...)* @_ssdm_op_SpecInterface(i32* %tri - + NULL @@ -765,7 +753,7 @@ arrayctor.loop1.preheader:34 call void (...)* @_ssdm_op_SpecInterface(i64* %out - + NULL @@ -780,7 +768,7 @@ arrayctor.loop1.preheader:35 call void (...)* @_ssdm_op_SpecInterface(i16 %n_pi - + NULL @@ -795,7 +783,7 @@ arrayctor.loop1.preheader:36 %tmp_1 = zext i8 %N_BG_read to i32 - + NULL @@ -810,7 +798,7 @@ arrayctor.loop1.preheader:37 call void (...)* @_ssdm_op_SpecInterface(i8 %N_BG, - + NULL @@ -825,7 +813,7 @@ arrayctor.loop1.preheader:38 call void (...)* @_ssdm_op_SpecInterface(i32 %LOW_ - + NULL @@ -840,7 +828,7 @@ arrayctor.loop1.preheader:39 call void (...)* @_ssdm_op_SpecInterface(i32 0, [1 - + NULL @@ -855,7 +843,7 @@ arrayctor.loop1.preheader:40 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i3 - + NULL @@ -870,7 +858,7 @@ arrayctor.loop1.preheader:41 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i3 - + NULL @@ -885,7 +873,7 @@ arrayctor.loop1.preheader:42 %tmp_2 = call i15 @_ssdm_op_PartSelect.i15.i16.i32 - + NULL @@ -903,7 +891,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -918,7 +906,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -933,7 +921,7 @@ arrayctor.loop1.preheader:43 br label %0 - + Cmp @@ -948,7 +936,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -963,7 +951,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -978,7 +966,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -994,7 +982,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1010,7 +998,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM 0 @@ -1026,7 +1014,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1042,7 +1030,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM 0 @@ -1058,7 +1046,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1074,7 +1062,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM 0 @@ -1090,7 +1078,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1106,7 +1094,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM 0 @@ -1122,7 +1110,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1141,7 +1129,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1156,7 +1144,7 @@ arrayctor.loop1.preheader:43 br label %0 - + Cmp @@ -1171,7 +1159,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1186,7 +1174,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -1201,7 +1189,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1216,7 +1204,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1232,7 +1220,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1248,7 +1236,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1264,7 +1252,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1280,7 +1268,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -1296,7 +1284,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1315,7 +1303,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1330,7 +1318,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1345,7 +1333,7 @@ arrayctor.loop1.preheader:43 br label %0 - + Cmp @@ -1360,7 +1348,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -1375,7 +1363,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1390,7 +1378,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -1406,7 +1394,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1422,7 +1410,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1438,7 +1426,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1454,7 +1442,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM 0 @@ -1470,7 +1458,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM 0 @@ -1486,7 +1474,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1505,7 +1493,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AXI4Stream @@ -1520,7 +1508,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1535,7 +1523,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1554,7 +1542,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1569,7 +1557,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1584,7 +1572,7 @@ arrayctor.loop1.preheader:43 br label %0 - + Cmp @@ -1599,7 +1587,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -1614,7 +1602,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1629,7 +1617,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1645,7 +1633,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1661,7 +1649,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM 0 @@ -1677,7 +1665,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1693,7 +1681,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM 0 @@ -1709,7 +1697,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1728,7 +1716,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1743,7 +1731,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1758,7 +1746,7 @@ arrayctor.loop1.preheader:43 br label %0 - + Cmp @@ -1773,7 +1761,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1788,7 +1776,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -1803,7 +1791,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1821,7 +1809,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1836,7 +1824,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1851,7 +1839,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1866,7 +1854,7 @@ arrayctor.loop1.preheader:43 br label %0 - + Cmp @@ -1881,7 +1869,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -1896,7 +1884,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1911,7 +1899,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1927,7 +1915,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:0 %tmp_15 = zext - + NULL @@ -1943,7 +1931,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:8 %sum_pix1_addr_ - + RAM 0 @@ -1959,7 +1947,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:9 %sum_pix1_load_ - + NULL @@ -1975,7 +1963,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:13 %sum_pix2_addr - + RAM 0 @@ -1994,7 +1982,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:14 %sum_pix2_load - + NULL @@ -2009,7 +1997,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:1 %data_shift1_ad - + NULL @@ -2024,7 +2012,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:2 %data_shift2_ad - + AXI4Stream @@ -2039,7 +2027,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:3 %empty_12 = cal - + NULL @@ -2054,7 +2042,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:4 %tmp_data_V_2 = - + NULL @@ -2069,7 +2057,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:5 %tmp_16 = trunc - + NULL @@ -2084,7 +2072,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:6 %phitmp = call - + NULL @@ -2099,7 +2087,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:7 %tmp_17 = sext - + RAM 0 @@ -2114,7 +2102,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:9 %sum_pix1_load_ - + AddSub @@ -2129,7 +2117,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:10 %tmp_18 = add - + RAM 0 @@ -2144,7 +2132,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:11 store i32 %tmp - + NULL @@ -2159,7 +2147,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:12 %tmp_19 = sext - + RAM 0 @@ -2174,7 +2162,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:14 %sum_pix2_load - + AddSub @@ -2189,7 +2177,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:15 %tmp_20 = add - + RAM 0 @@ -2204,7 +2192,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:16 store i32 %tmp - + NULL @@ -2219,7 +2207,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:17 %sum_overP1_ad - + RAM 0 @@ -2234,7 +2222,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:18 store i32 0, i - + NULL @@ -2249,7 +2237,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:19 %sum_overP2_ad - + RAM 0 @@ -2264,7 +2252,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:20 store i32 0, i - + NULL @@ -2282,7 +2270,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2297,7 +2285,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2312,7 +2300,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2327,7 +2315,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2342,7 +2330,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2358,7 +2346,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2374,7 +2362,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2390,7 +2378,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2406,7 +2394,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + TAddSub @@ -2422,7 +2410,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + TAddSub @@ -2438,7 +2426,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2454,7 +2442,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2470,7 +2458,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2486,7 +2474,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2502,7 +2490,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2518,7 +2506,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2534,7 +2522,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2550,7 +2538,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2566,7 +2554,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2582,7 +2570,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2598,7 +2586,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2614,7 +2602,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2630,7 +2618,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2646,7 +2634,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2662,7 +2650,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2681,7 +2669,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2696,7 +2684,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2711,7 +2699,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AddSub @@ -2726,7 +2714,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2741,7 +2729,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2756,7 +2744,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2771,7 +2759,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2786,7 +2774,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + TAddSub @@ -2801,7 +2789,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + TAddSub @@ -2816,7 +2804,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2831,7 +2819,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2846,7 +2834,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2861,7 +2849,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2876,7 +2864,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2891,7 +2879,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2906,7 +2894,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2921,7 +2909,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2936,7 +2924,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AddSub @@ -2951,7 +2939,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2966,7 +2954,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2981,7 +2969,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AddSub @@ -2996,7 +2984,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -3011,7 +2999,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AddSub @@ -3026,7 +3014,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -3044,7 +3032,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -3059,7 +3047,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AddSub @@ -3074,7 +3062,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -3089,7 +3077,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -3104,7 +3092,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AddSub @@ -3119,7 +3107,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -3134,7 +3122,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -3149,7 +3137,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Cmp @@ -3164,7 +3152,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -3179,7 +3167,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -3195,7 +3183,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -3211,7 +3199,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Cmp @@ -3227,7 +3215,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Cmp @@ -3243,7 +3231,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -3259,7 +3247,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -3279,7 +3267,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -3294,7 +3282,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Cmp @@ -3309,7 +3297,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + LogicGate @@ -3324,7 +3312,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -3339,7 +3327,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -3354,33 +3342,13 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 ]]> - - - - - -NULL - - - - - - - - - - - - - + NULL - - + + + @@ -3391,11 +3359,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - - + + + @@ -3406,11 +3375,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - - + + + @@ -3421,25 +3391,44 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - - + + + + - + + + NULL - + + + + + + + + + + +NULL + + @@ -3452,12 +3441,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + - + NULL - + @@ -3468,14 +3457,11 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 ]]> - - - - + NULL - + @@ -3487,10 +3473,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3502,25 +3488,25 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + - + NULL - + @@ -3533,12 +3519,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + - + NULL - + @@ -3550,10 +3536,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3565,10 +3551,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Cmp - + @@ -3580,10 +3566,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AddSub - + @@ -3595,10 +3581,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3610,10 +3596,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3626,10 +3612,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3642,10 +3628,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 - + @@ -3658,10 +3644,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3674,10 +3660,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 - + @@ -3690,10 +3676,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3706,10 +3692,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3723,12 +3709,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + - + RAM 0 - + @@ -3740,10 +3726,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 - + @@ -3755,10 +3741,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3770,10 +3756,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AXI4Stream - + @@ -3785,10 +3771,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3800,10 +3786,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3816,12 +3802,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + - + NULL - + @@ -3833,10 +3819,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3848,10 +3834,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3863,10 +3849,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3878,10 +3864,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Mul - + @@ -3893,10 +3879,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Mul - + @@ -3909,12 +3895,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + - + RAM 0 - + @@ -3926,10 +3912,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 - + @@ -3941,10 +3927,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Cmp - + @@ -3956,10 +3942,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3972,12 +3958,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + - + RAM 0 - + @@ -3990,10 +3976,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -4006,10 +3992,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Cmp - + @@ -4021,10 +4007,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -4036,10 +4022,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 - + @@ -4052,10 +4038,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -4068,10 +4054,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -4087,1498 +4073,1498 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - - + + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/l2_trigger/solution1/.autopilot/db/l2_trigger.bind.adb.xml b/l2_trigger/solution1/.autopilot/db/l2_trigger.bind.adb.xml index 185a7ac..3f12692 100644 --- a/l2_trigger/solution1/.autopilot/db/l2_trigger.bind.adb.xml +++ b/l2_trigger/solution1/.autopilot/db/l2_trigger.bind.adb.xml @@ -3,224 +3,212 @@ - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - + - - - - - - - - - - - - - - + + - - + + - - + + - - + + - - + + @@ -232,7 +220,7 @@ - + NULL @@ -247,7 +235,7 @@ arrayctor.loop1.preheader:0 call void (...)* @_ssdm_op_SpecBitsMap(i32* %in_str - + NULL @@ -262,7 +250,7 @@ arrayctor.loop1.preheader:1 call void (...)* @_ssdm_op_SpecBitsMap(i4* %in_stre - + NULL @@ -277,7 +265,7 @@ arrayctor.loop1.preheader:2 call void (...)* @_ssdm_op_SpecBitsMap(i4* %in_stre - + NULL @@ -292,7 +280,7 @@ arrayctor.loop1.preheader:3 call void (...)* @_ssdm_op_SpecBitsMap(i2* %in_stre - + NULL @@ -307,7 +295,7 @@ arrayctor.loop1.preheader:4 call void (...)* @_ssdm_op_SpecBitsMap(i1* %in_stre - + NULL @@ -322,7 +310,7 @@ arrayctor.loop1.preheader:5 call void (...)* @_ssdm_op_SpecBitsMap(i5* %in_stre - + NULL @@ -337,7 +325,7 @@ arrayctor.loop1.preheader:6 call void (...)* @_ssdm_op_SpecBitsMap(i6* %in_stre - + NULL @@ -352,7 +340,7 @@ arrayctor.loop1.preheader:7 call void (...)* @_ssdm_op_SpecBitsMap(i64* %out_st - + NULL @@ -367,7 +355,7 @@ arrayctor.loop1.preheader:8 call void (...)* @_ssdm_op_SpecBitsMap(i8* %out_str - + NULL @@ -382,7 +370,7 @@ arrayctor.loop1.preheader:9 call void (...)* @_ssdm_op_SpecBitsMap(i8* %out_str - + NULL @@ -397,7 +385,7 @@ arrayctor.loop1.preheader:10 call void (...)* @_ssdm_op_SpecBitsMap(i2* %out_st - + NULL @@ -412,7 +400,7 @@ arrayctor.loop1.preheader:11 call void (...)* @_ssdm_op_SpecBitsMap(i1* %out_st - + NULL @@ -427,7 +415,7 @@ arrayctor.loop1.preheader:12 call void (...)* @_ssdm_op_SpecBitsMap(i5* %out_st - + NULL @@ -442,7 +430,7 @@ arrayctor.loop1.preheader:13 call void (...)* @_ssdm_op_SpecBitsMap(i6* %out_st - + NULL @@ -457,7 +445,7 @@ arrayctor.loop1.preheader:14 call void (...)* @_ssdm_op_SpecBitsMap(i16 %n_pixe - + NULL @@ -472,7 +460,7 @@ arrayctor.loop1.preheader:15 call void (...)* @_ssdm_op_SpecBitsMap(i8 %N_BG), - + NULL @@ -487,7 +475,7 @@ arrayctor.loop1.preheader:16 call void (...)* @_ssdm_op_SpecBitsMap(i32 %LOW_TH - + NULL @@ -502,7 +490,7 @@ arrayctor.loop1.preheader:17 call void (...)* @_ssdm_op_SpecBitsMap(i32* %trig_ - + NULL @@ -517,7 +505,7 @@ arrayctor.loop1.preheader:18 call void (...)* @_ssdm_op_SpecBitsMap(i32* %trig_ - + NULL @@ -532,7 +520,7 @@ arrayctor.loop1.preheader:19 call void (...)* @_ssdm_op_SpecTopModule([11 x i8] - + s_axilite @@ -547,7 +535,7 @@ arrayctor.loop1.preheader:20 %LOW_THRESH_read = call i32 @_ssdm_op_Read.s_axili - + s_axilite @@ -562,7 +550,7 @@ arrayctor.loop1.preheader:21 %N_BG_read = call i8 @_ssdm_op_Read.s_axilite.i8(i - + s_axilite @@ -577,7 +565,7 @@ arrayctor.loop1.preheader:22 %n_pixels_in_bus_read = call i16 @_ssdm_op_Read.s_ - + RAM @@ -593,7 +581,7 @@ arrayctor.loop1.preheader:23 %sum_overP1 = alloca [1152 x i32], align 16 - + RAM @@ -609,7 +597,7 @@ arrayctor.loop1.preheader:24 %sum_overP2 = alloca [1152 x i32], align 16 - + RAM @@ -625,7 +613,7 @@ arrayctor.loop1.preheader:25 %sum_pix1 = alloca [1152 x i32], align 16 - + RAM @@ -641,7 +629,7 @@ arrayctor.loop1.preheader:26 %data_shift1 = alloca [9216 x i17], align 4 - + RAM @@ -657,7 +645,7 @@ arrayctor.loop1.preheader:27 %thresh1 = alloca [1152 x i32], align 16 - + RAM @@ -673,7 +661,7 @@ arrayctor.loop1.preheader:28 %sum_pix2 = alloca [1152 x i32], align 16 - + RAM @@ -689,7 +677,7 @@ arrayctor.loop1.preheader:29 %data_shift2 = alloca [9216 x i17], align 4 - + RAM @@ -705,7 +693,7 @@ arrayctor.loop1.preheader:30 %thresh2 = alloca [1152 x i32], align 16 - + NULL @@ -720,7 +708,7 @@ arrayctor.loop1.preheader:31 call void (...)* @_ssdm_op_SpecInterface(i32* %in_ - + NULL @@ -735,7 +723,7 @@ arrayctor.loop1.preheader:32 call void (...)* @_ssdm_op_SpecInterface(i32* %tri - + NULL @@ -750,7 +738,7 @@ arrayctor.loop1.preheader:33 call void (...)* @_ssdm_op_SpecInterface(i32* %tri - + NULL @@ -765,7 +753,7 @@ arrayctor.loop1.preheader:34 call void (...)* @_ssdm_op_SpecInterface(i64* %out - + NULL @@ -780,7 +768,7 @@ arrayctor.loop1.preheader:35 call void (...)* @_ssdm_op_SpecInterface(i16 %n_pi - + NULL @@ -795,7 +783,7 @@ arrayctor.loop1.preheader:36 %tmp_1 = zext i8 %N_BG_read to i32 - + NULL @@ -810,7 +798,7 @@ arrayctor.loop1.preheader:37 call void (...)* @_ssdm_op_SpecInterface(i8 %N_BG, - + NULL @@ -825,7 +813,7 @@ arrayctor.loop1.preheader:38 call void (...)* @_ssdm_op_SpecInterface(i32 %LOW_ - + NULL @@ -840,7 +828,7 @@ arrayctor.loop1.preheader:39 call void (...)* @_ssdm_op_SpecInterface(i32 0, [1 - + NULL @@ -855,7 +843,7 @@ arrayctor.loop1.preheader:40 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i3 - + NULL @@ -870,7 +858,7 @@ arrayctor.loop1.preheader:41 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i3 - + NULL @@ -885,7 +873,7 @@ arrayctor.loop1.preheader:42 %tmp_2 = call i15 @_ssdm_op_PartSelect.i15.i16.i32 - + NULL @@ -903,7 +891,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -918,7 +906,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -933,7 +921,7 @@ arrayctor.loop1.preheader:43 br label %0 - + Cmp @@ -948,7 +936,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -963,7 +951,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -978,7 +966,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -994,7 +982,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1010,7 +998,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM 0 @@ -1026,7 +1014,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1042,7 +1030,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM 0 @@ -1058,7 +1046,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1074,7 +1062,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM 0 @@ -1090,7 +1078,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1106,7 +1094,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM 0 @@ -1122,7 +1110,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1141,7 +1129,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1156,7 +1144,7 @@ arrayctor.loop1.preheader:43 br label %0 - + Cmp @@ -1171,7 +1159,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1186,7 +1174,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -1201,7 +1189,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1216,7 +1204,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1232,7 +1220,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1248,7 +1236,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1264,7 +1252,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1280,7 +1268,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -1296,7 +1284,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1315,7 +1303,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1330,7 +1318,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1345,7 +1333,7 @@ arrayctor.loop1.preheader:43 br label %0 - + Cmp @@ -1360,7 +1348,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -1375,7 +1363,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1390,7 +1378,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -1406,7 +1394,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1422,7 +1410,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1438,7 +1426,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1454,7 +1442,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM 0 @@ -1470,7 +1458,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM 0 @@ -1486,7 +1474,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1505,7 +1493,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AXI4Stream @@ -1520,7 +1508,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1535,7 +1523,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1554,7 +1542,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1569,7 +1557,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1584,7 +1572,7 @@ arrayctor.loop1.preheader:43 br label %0 - + Cmp @@ -1599,7 +1587,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -1614,7 +1602,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1629,7 +1617,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1645,7 +1633,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1661,7 +1649,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM 0 @@ -1677,7 +1665,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1693,7 +1681,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM 0 @@ -1709,7 +1697,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1728,7 +1716,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1743,7 +1731,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1758,7 +1746,7 @@ arrayctor.loop1.preheader:43 br label %0 - + Cmp @@ -1773,7 +1761,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1788,7 +1776,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -1803,7 +1791,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1821,7 +1809,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1836,7 +1824,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1851,7 +1839,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1866,7 +1854,7 @@ arrayctor.loop1.preheader:43 br label %0 - + Cmp @@ -1881,7 +1869,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -1896,7 +1884,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1911,7 +1899,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1927,7 +1915,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:0 %tmp_15 = zext - + NULL @@ -1943,7 +1931,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:8 %sum_pix1_addr_ - + RAM 0 @@ -1959,7 +1947,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:9 %sum_pix1_load_ - + NULL @@ -1975,7 +1963,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:13 %sum_pix2_addr - + RAM 0 @@ -1994,7 +1982,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:14 %sum_pix2_load - + NULL @@ -2009,7 +1997,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:1 %data_shift1_ad - + NULL @@ -2024,7 +2012,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:2 %data_shift2_ad - + AXI4Stream @@ -2039,7 +2027,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:3 %empty_12 = cal - + NULL @@ -2054,7 +2042,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:4 %tmp_data_V_2 = - + NULL @@ -2069,7 +2057,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:5 %tmp_16 = trunc - + NULL @@ -2084,7 +2072,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:6 %phitmp = call - + NULL @@ -2099,7 +2087,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:7 %tmp_17 = sext - + RAM 0 @@ -2114,7 +2102,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:9 %sum_pix1_load_ - + AddSub @@ -2129,7 +2117,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:10 %tmp_18 = add - + RAM 0 @@ -2144,7 +2132,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:11 store i32 %tmp - + NULL @@ -2159,7 +2147,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:12 %tmp_19 = sext - + RAM 0 @@ -2174,7 +2162,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:14 %sum_pix2_load - + AddSub @@ -2189,7 +2177,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:15 %tmp_20 = add - + RAM 0 @@ -2204,7 +2192,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:16 store i32 %tmp - + NULL @@ -2219,7 +2207,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:17 %sum_overP1_ad - + RAM 0 @@ -2234,7 +2222,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:18 store i32 0, i - + NULL @@ -2249,7 +2237,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:19 %sum_overP2_ad - + RAM 0 @@ -2264,7 +2252,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:20 store i32 0, i - + NULL @@ -2282,7 +2270,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2297,7 +2285,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2312,7 +2300,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2327,7 +2315,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2342,7 +2330,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2358,7 +2346,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2374,7 +2362,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2390,7 +2378,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2406,7 +2394,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + TAddSub @@ -2422,7 +2410,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + TAddSub @@ -2438,7 +2426,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2454,7 +2442,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2470,7 +2458,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2486,7 +2474,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2502,7 +2490,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2518,7 +2506,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2534,7 +2522,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2550,7 +2538,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2566,7 +2554,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2582,7 +2570,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2598,7 +2586,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2614,7 +2602,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2630,7 +2618,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2646,7 +2634,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2662,7 +2650,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2681,7 +2669,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2696,7 +2684,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2711,7 +2699,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AddSub @@ -2726,7 +2714,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2741,7 +2729,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2756,7 +2744,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2771,7 +2759,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2786,7 +2774,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + TAddSub @@ -2801,7 +2789,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + TAddSub @@ -2816,7 +2804,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2831,7 +2819,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2846,7 +2834,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2861,7 +2849,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2876,7 +2864,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2891,7 +2879,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2906,7 +2894,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2921,7 +2909,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2936,7 +2924,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AddSub @@ -2951,7 +2939,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2966,7 +2954,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -2981,7 +2969,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AddSub @@ -2996,7 +2984,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -3011,7 +2999,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AddSub @@ -3026,7 +3014,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -3044,7 +3032,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -3059,7 +3047,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AddSub @@ -3074,7 +3062,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -3089,7 +3077,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -3104,7 +3092,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AddSub @@ -3119,7 +3107,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -3134,7 +3122,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -3149,7 +3137,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Cmp @@ -3164,7 +3152,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -3179,7 +3167,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -3195,7 +3183,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -3211,7 +3199,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Cmp @@ -3227,7 +3215,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Cmp @@ -3243,7 +3231,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -3259,7 +3247,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -3279,7 +3267,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 @@ -3294,7 +3282,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Cmp @@ -3309,7 +3297,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + LogicGate @@ -3324,7 +3312,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -3339,7 +3327,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -3354,33 +3342,13 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 ]]> - - - - - -NULL - - - - - - - - - - - - - + NULL - - + + + @@ -3391,11 +3359,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - - + + + @@ -3406,11 +3375,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - - + + + @@ -3421,25 +3391,44 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - - + + + + - + + + NULL - + + + + + + + + + + +NULL + + @@ -3452,12 +3441,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + - + NULL - + @@ -3468,14 +3457,11 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 ]]> - - - - + NULL - + @@ -3487,10 +3473,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3502,25 +3488,25 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + - + NULL - + @@ -3533,12 +3519,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + - + NULL - + @@ -3550,10 +3536,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3565,10 +3551,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Cmp - + @@ -3580,10 +3566,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AddSub - + @@ -3595,10 +3581,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3610,10 +3596,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3626,10 +3612,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3642,10 +3628,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 - + @@ -3658,10 +3644,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3674,10 +3660,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 - + @@ -3690,10 +3676,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3706,10 +3692,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3723,12 +3709,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + - + RAM 0 - + @@ -3740,10 +3726,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 - + @@ -3755,10 +3741,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3770,10 +3756,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AXI4Stream - + @@ -3785,10 +3771,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3800,10 +3786,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3816,12 +3802,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + - + NULL - + @@ -3833,10 +3819,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3848,10 +3834,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3863,10 +3849,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3878,10 +3864,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Mul - + @@ -3893,10 +3879,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Mul - + @@ -3909,12 +3895,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + - + RAM 0 - + @@ -3926,10 +3912,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 - + @@ -3941,10 +3927,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Cmp - + @@ -3956,10 +3942,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3972,12 +3958,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + - + RAM 0 - + @@ -3990,10 +3976,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -4006,10 +3992,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Cmp - + @@ -4021,10 +4007,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -4036,10 +4022,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM 0 - + @@ -4052,10 +4038,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -4068,10 +4054,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -4087,1498 +4073,1498 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + NULL - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - - + + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/l2_trigger/solution1/.autopilot/db/l2_trigger.design.xml b/l2_trigger/solution1/.autopilot/db/l2_trigger.design.xml index bc72261..4aaad71 100644 --- a/l2_trigger/solution1/.autopilot/db/l2_trigger.design.xml +++ b/l2_trigger/solution1/.autopilot/db/l2_trigger.design.xml @@ -66,10 +66,10 @@ 260 -88274558 +84080382 -260 ~ 88274558 +260 ~ 84080382 Loop 3.1 @@ -85,14 +85,14 @@ Loop 3.2 128 -256 ~ 88077952 +256 ~ 83883776 2 -688109 +655342 -2 ~ 688109 +2 ~ 655342 Loop 3.2.1 @@ -101,14 +101,14 @@ 32767 -0 ~ 688107 +0 ~ 655340 18 -21 +20 -18 ~ 21 +18 ~ 20 Loop 3.2.1.1 7 @@ -137,8 +137,8 @@ 58 4 -746 -1141 +744 +1173 diff --git a/l2_trigger/solution1/.autopilot/db/l2_trigger.pp.0.cpp b/l2_trigger/solution1/.autopilot/db/l2_trigger.pp.0.cpp index 765b826..ee14460 100644 --- a/l2_trigger/solution1/.autopilot/db/l2_trigger.pp.0.cpp +++ b/l2_trigger/solution1/.autopilot/db/l2_trigger.pp.0.cpp @@ -52362,7 +52362,7 @@ void l2_trigger(STREAM_32 &in_stream, STREAM_64 &out_stream, uint16_t n_pixels_i *trig_data = 0x00000000; //store the triggered pixel - *trig_data = i*2; + *trig_pixel = i*2; //Block for 128 GTU itrig = 1; @@ -52376,7 +52376,7 @@ void l2_trigger(STREAM_32 &in_stream, STREAM_64 &out_stream, uint16_t n_pixels_i *trig_data = 0x00000000; //store the triggered pixel - *trig_data = (i*2) + 1; + *trig_pixel = (i*2) + 1; //Block for 128 GTU itrig = 1; diff --git a/l2_trigger/solution1/.autopilot/db/l2_trigger.pp.0.cpp.ap-cdt.cpp b/l2_trigger/solution1/.autopilot/db/l2_trigger.pp.0.cpp.ap-cdt.cpp index 669b5a8..0512718 100644 --- a/l2_trigger/solution1/.autopilot/db/l2_trigger.pp.0.cpp.ap-cdt.cpp +++ b/l2_trigger/solution1/.autopilot/db/l2_trigger.pp.0.cpp.ap-cdt.cpp @@ -52569,7 +52569,7 @@ void l2_trigger(STREAM_32 &in_stream, STREAM_64 &out_stream, uint16_t n_pixels_i *trig_data = 0x00000000; #pragma empty_line //store the triggered pixel - *trig_data = i*2; + *trig_pixel = i*2; #pragma empty_line //Block for 128 GTU itrig = 1; @@ -52583,7 +52583,7 @@ void l2_trigger(STREAM_32 &in_stream, STREAM_64 &out_stream, uint16_t n_pixels_i *trig_data = 0x00000000; #pragma empty_line //store the triggered pixel - *trig_data = (i*2) + 1; + *trig_pixel = (i*2) + 1; #pragma empty_line //Block for 128 GTU itrig = 1; diff --git a/l2_trigger/solution1/.autopilot/db/l2_trigger.pp.0.cpp.ap-line.cpp b/l2_trigger/solution1/.autopilot/db/l2_trigger.pp.0.cpp.ap-line.cpp index 281d8a3..41b81b6 100644 --- a/l2_trigger/solution1/.autopilot/db/l2_trigger.pp.0.cpp.ap-line.cpp +++ b/l2_trigger/solution1/.autopilot/db/l2_trigger.pp.0.cpp.ap-line.cpp @@ -52362,7 +52362,7 @@ void l2_trigger(STREAM_32 &in_stream, STREAM_64 &out_stream, uint16_t n_pixels_i *trig_data = 0x00000000; #pragma empty_line //store the triggered pixel - *trig_data = i*2; + *trig_pixel = i*2; #pragma empty_line //Block for 128 GTU itrig = 1; @@ -52376,7 +52376,7 @@ void l2_trigger(STREAM_32 &in_stream, STREAM_64 &out_stream, uint16_t n_pixels_i *trig_data = 0x00000000; #pragma empty_line //store the triggered pixel - *trig_data = (i*2) + 1; + *trig_pixel = (i*2) + 1; #pragma empty_line //Block for 128 GTU itrig = 1; diff --git a/l2_trigger/solution1/.autopilot/db/l2_trigger.pragma.0.cpp b/l2_trigger/solution1/.autopilot/db/l2_trigger.pragma.0.cpp index f5553c3..41a533f 100644 --- a/l2_trigger/solution1/.autopilot/db/l2_trigger.pragma.0.cpp +++ b/l2_trigger/solution1/.autopilot/db/l2_trigger.pragma.0.cpp @@ -52569,7 +52569,7 @@ void l2_trigger(STREAM_32 &in_stream, STREAM_64 &out_stream, uint16_t n_pixels_i *trig_data = 0x00000000; //store the triggered pixel - *trig_data = i*2; + *trig_pixel = i*2; //Block for 128 GTU itrig = 1; @@ -52583,7 +52583,7 @@ void l2_trigger(STREAM_32 &in_stream, STREAM_64 &out_stream, uint16_t n_pixels_i *trig_data = 0x00000000; //store the triggered pixel - *trig_data = (i*2) + 1; + *trig_pixel = (i*2) + 1; //Block for 128 GTU itrig = 1; diff --git a/l2_trigger/solution1/.autopilot/db/l2_trigger.pragma.1.cpp b/l2_trigger/solution1/.autopilot/db/l2_trigger.pragma.1.cpp index 87fecbe..f021c12 100644 --- a/l2_trigger/solution1/.autopilot/db/l2_trigger.pragma.1.cpp +++ b/l2_trigger/solution1/.autopilot/db/l2_trigger.pragma.1.cpp @@ -52569,7 +52569,7 @@ _ssdm_op_SpecInterface(0, "s_axilite", 0, 0, 0, 0, "CTRL_BUS", "", "", 0, 0, 0, *trig_data = 0x00000000; //store the triggered pixel - *trig_data = i*2; + *trig_pixel = i*2; //Block for 128 GTU itrig = 1; @@ -52583,7 +52583,7 @@ _ssdm_op_SpecInterface(0, "s_axilite", 0, 0, 0, 0, "CTRL_BUS", "", "", 0, 0, 0, *trig_data = 0x00000000; //store the triggered pixel - *trig_data = (i*2) + 1; + *trig_pixel = (i*2) + 1; //Block for 128 GTU itrig = 1; diff --git a/l2_trigger/solution1/.autopilot/db/l2_trigger.pragma.2.cpp b/l2_trigger/solution1/.autopilot/db/l2_trigger.pragma.2.cpp index 8fcab9d..a0dee51 100644 --- a/l2_trigger/solution1/.autopilot/db/l2_trigger.pragma.2.cpp +++ b/l2_trigger/solution1/.autopilot/db/l2_trigger.pragma.2.cpp @@ -52616,7 +52616,7 @@ _ssdm_op_SpecInterface(0, "s_axilite", 0, 0, 0, 0, "CTRL_BUS", "", "", 0, 0, 0, *trig_data = 0x00000000; //store the triggered pixel - *trig_data = i*2; + *trig_pixel = i*2; //Block for 128 GTU itrig = 1; @@ -52630,7 +52630,7 @@ _ssdm_op_SpecInterface(0, "s_axilite", 0, 0, 0, 0, "CTRL_BUS", "", "", 0, 0, 0, *trig_data = 0x00000000; //store the triggered pixel - *trig_data = (i*2) + 1; + *trig_pixel = (i*2) + 1; //Block for 128 GTU itrig = 1; diff --git a/l2_trigger/solution1/.autopilot/db/l2_trigger.sched.adb.xml b/l2_trigger/solution1/.autopilot/db/l2_trigger.sched.adb.xml index b7dff9f..8ab46ca 100644 --- a/l2_trigger/solution1/.autopilot/db/l2_trigger.sched.adb.xml +++ b/l2_trigger/solution1/.autopilot/db/l2_trigger.sched.adb.xml @@ -3,224 +3,212 @@ - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - + - - - - - - - - - - - - - - + + - - + + - - + + - - + + - - + + @@ -232,7 +220,7 @@ - + NULL @@ -247,7 +235,7 @@ arrayctor.loop1.preheader:0 call void (...)* @_ssdm_op_SpecBitsMap(i32* %in_str - + NULL @@ -262,7 +250,7 @@ arrayctor.loop1.preheader:1 call void (...)* @_ssdm_op_SpecBitsMap(i4* %in_stre - + NULL @@ -277,7 +265,7 @@ arrayctor.loop1.preheader:2 call void (...)* @_ssdm_op_SpecBitsMap(i4* %in_stre - + NULL @@ -292,7 +280,7 @@ arrayctor.loop1.preheader:3 call void (...)* @_ssdm_op_SpecBitsMap(i2* %in_stre - + NULL @@ -307,7 +295,7 @@ arrayctor.loop1.preheader:4 call void (...)* @_ssdm_op_SpecBitsMap(i1* %in_stre - + NULL @@ -322,7 +310,7 @@ arrayctor.loop1.preheader:5 call void (...)* @_ssdm_op_SpecBitsMap(i5* %in_stre - + NULL @@ -337,7 +325,7 @@ arrayctor.loop1.preheader:6 call void (...)* @_ssdm_op_SpecBitsMap(i6* %in_stre - + NULL @@ -352,7 +340,7 @@ arrayctor.loop1.preheader:7 call void (...)* @_ssdm_op_SpecBitsMap(i64* %out_st - + NULL @@ -367,7 +355,7 @@ arrayctor.loop1.preheader:8 call void (...)* @_ssdm_op_SpecBitsMap(i8* %out_str - + NULL @@ -382,7 +370,7 @@ arrayctor.loop1.preheader:9 call void (...)* @_ssdm_op_SpecBitsMap(i8* %out_str - + NULL @@ -397,7 +385,7 @@ arrayctor.loop1.preheader:10 call void (...)* @_ssdm_op_SpecBitsMap(i2* %out_st - + NULL @@ -412,7 +400,7 @@ arrayctor.loop1.preheader:11 call void (...)* @_ssdm_op_SpecBitsMap(i1* %out_st - + NULL @@ -427,7 +415,7 @@ arrayctor.loop1.preheader:12 call void (...)* @_ssdm_op_SpecBitsMap(i5* %out_st - + NULL @@ -442,7 +430,7 @@ arrayctor.loop1.preheader:13 call void (...)* @_ssdm_op_SpecBitsMap(i6* %out_st - + NULL @@ -457,7 +445,7 @@ arrayctor.loop1.preheader:14 call void (...)* @_ssdm_op_SpecBitsMap(i16 %n_pixe - + NULL @@ -472,7 +460,7 @@ arrayctor.loop1.preheader:15 call void (...)* @_ssdm_op_SpecBitsMap(i8 %N_BG), - + NULL @@ -487,7 +475,7 @@ arrayctor.loop1.preheader:16 call void (...)* @_ssdm_op_SpecBitsMap(i32 %LOW_TH - + NULL @@ -502,7 +490,7 @@ arrayctor.loop1.preheader:17 call void (...)* @_ssdm_op_SpecBitsMap(i32* %trig_ - + NULL @@ -517,7 +505,7 @@ arrayctor.loop1.preheader:18 call void (...)* @_ssdm_op_SpecBitsMap(i32* %trig_ - + NULL @@ -532,7 +520,7 @@ arrayctor.loop1.preheader:19 call void (...)* @_ssdm_op_SpecTopModule([11 x i8] - + s_axilite @@ -547,7 +535,7 @@ arrayctor.loop1.preheader:20 %LOW_THRESH_read = call i32 @_ssdm_op_Read.s_axili - + s_axilite @@ -562,7 +550,7 @@ arrayctor.loop1.preheader:21 %N_BG_read = call i8 @_ssdm_op_Read.s_axilite.i8(i - + s_axilite @@ -577,7 +565,7 @@ arrayctor.loop1.preheader:22 %n_pixels_in_bus_read = call i16 @_ssdm_op_Read.s_ - + RAM @@ -592,7 +580,7 @@ arrayctor.loop1.preheader:23 %sum_overP1 = alloca [1152 x i32], align 16 - + RAM @@ -607,7 +595,7 @@ arrayctor.loop1.preheader:24 %sum_overP2 = alloca [1152 x i32], align 16 - + RAM @@ -622,7 +610,7 @@ arrayctor.loop1.preheader:25 %sum_pix1 = alloca [1152 x i32], align 16 - + RAM @@ -637,7 +625,7 @@ arrayctor.loop1.preheader:26 %data_shift1 = alloca [9216 x i17], align 4 - + RAM @@ -652,7 +640,7 @@ arrayctor.loop1.preheader:27 %thresh1 = alloca [1152 x i32], align 16 - + RAM @@ -667,7 +655,7 @@ arrayctor.loop1.preheader:28 %sum_pix2 = alloca [1152 x i32], align 16 - + RAM @@ -682,7 +670,7 @@ arrayctor.loop1.preheader:29 %data_shift2 = alloca [9216 x i17], align 4 - + RAM @@ -697,7 +685,7 @@ arrayctor.loop1.preheader:30 %thresh2 = alloca [1152 x i32], align 16 - + NULL @@ -712,7 +700,7 @@ arrayctor.loop1.preheader:31 call void (...)* @_ssdm_op_SpecInterface(i32* %in_ - + NULL @@ -727,7 +715,7 @@ arrayctor.loop1.preheader:32 call void (...)* @_ssdm_op_SpecInterface(i32* %tri - + NULL @@ -742,7 +730,7 @@ arrayctor.loop1.preheader:33 call void (...)* @_ssdm_op_SpecInterface(i32* %tri - + NULL @@ -757,7 +745,7 @@ arrayctor.loop1.preheader:34 call void (...)* @_ssdm_op_SpecInterface(i64* %out - + NULL @@ -772,7 +760,7 @@ arrayctor.loop1.preheader:35 call void (...)* @_ssdm_op_SpecInterface(i16 %n_pi - + NULL @@ -787,7 +775,7 @@ arrayctor.loop1.preheader:36 %tmp_1 = zext i8 %N_BG_read to i32 - + NULL @@ -802,7 +790,7 @@ arrayctor.loop1.preheader:37 call void (...)* @_ssdm_op_SpecInterface(i8 %N_BG, - + NULL @@ -817,7 +805,7 @@ arrayctor.loop1.preheader:38 call void (...)* @_ssdm_op_SpecInterface(i32 %LOW_ - + NULL @@ -832,7 +820,7 @@ arrayctor.loop1.preheader:39 call void (...)* @_ssdm_op_SpecInterface(i32 0, [1 - + NULL @@ -847,7 +835,7 @@ arrayctor.loop1.preheader:40 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i3 - + NULL @@ -862,7 +850,7 @@ arrayctor.loop1.preheader:41 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i3 - + NULL @@ -877,7 +865,7 @@ arrayctor.loop1.preheader:42 %tmp_2 = call i15 @_ssdm_op_PartSelect.i15.i16.i32 - + NULL @@ -895,7 +883,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -910,7 +898,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -925,7 +913,7 @@ arrayctor.loop1.preheader:43 br label %0 - + Cmp @@ -940,7 +928,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -955,7 +943,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -970,7 +958,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -986,7 +974,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1002,7 +990,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM @@ -1018,7 +1006,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1034,7 +1022,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM @@ -1050,7 +1038,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1066,7 +1054,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM @@ -1082,7 +1070,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1098,7 +1086,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM @@ -1114,7 +1102,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1133,7 +1121,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1148,7 +1136,7 @@ arrayctor.loop1.preheader:43 br label %0 - + Cmp @@ -1163,7 +1151,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1178,7 +1166,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -1193,7 +1181,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1208,7 +1196,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1224,7 +1212,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1240,7 +1228,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1256,7 +1244,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1272,7 +1260,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -1288,7 +1276,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1307,7 +1295,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1322,7 +1310,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1337,7 +1325,7 @@ arrayctor.loop1.preheader:43 br label %0 - + Cmp @@ -1352,7 +1340,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -1367,7 +1355,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1382,7 +1370,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -1398,7 +1386,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1414,7 +1402,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1430,7 +1418,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1446,7 +1434,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM @@ -1462,7 +1450,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM @@ -1478,7 +1466,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1497,7 +1485,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AXI4Stream @@ -1512,7 +1500,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1527,7 +1515,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1546,7 +1534,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1561,7 +1549,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1576,7 +1564,7 @@ arrayctor.loop1.preheader:43 br label %0 - + Cmp @@ -1591,7 +1579,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -1606,7 +1594,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1621,7 +1609,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1637,7 +1625,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1653,7 +1641,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM @@ -1669,7 +1657,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1685,7 +1673,7 @@ arrayctor.loop1.preheader:43 br label %0 - + RAM @@ -1701,7 +1689,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1720,7 +1708,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1735,7 +1723,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1750,7 +1738,7 @@ arrayctor.loop1.preheader:43 br label %0 - + Cmp @@ -1765,7 +1753,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1780,7 +1768,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -1795,7 +1783,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1813,7 +1801,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1828,7 +1816,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1843,7 +1831,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1858,7 +1846,7 @@ arrayctor.loop1.preheader:43 br label %0 - + Cmp @@ -1873,7 +1861,7 @@ arrayctor.loop1.preheader:43 br label %0 - + AddSub @@ -1888,7 +1876,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1903,7 +1891,7 @@ arrayctor.loop1.preheader:43 br label %0 - + NULL @@ -1919,7 +1907,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:0 %tmp_15 = zext - + NULL @@ -1935,7 +1923,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:8 %sum_pix1_addr_ - + RAM @@ -1951,7 +1939,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:9 %sum_pix1_load_ - + NULL @@ -1967,7 +1955,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:13 %sum_pix2_addr - + RAM @@ -1986,7 +1974,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:14 %sum_pix2_load - + NULL @@ -2001,7 +1989,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:1 %data_shift1_ad - + NULL @@ -2016,7 +2004,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:2 %data_shift2_ad - + AXI4Stream @@ -2031,7 +2019,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:3 %empty_12 = cal - + NULL @@ -2046,7 +2034,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:4 %tmp_data_V_2 = - + NULL @@ -2061,7 +2049,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:5 %tmp_16 = trunc - + NULL @@ -2076,7 +2064,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:6 %phitmp = call - + NULL @@ -2091,7 +2079,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:7 %tmp_17 = sext - + RAM @@ -2106,7 +2094,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:9 %sum_pix1_load_ - + AddSub @@ -2121,7 +2109,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:10 %tmp_18 = add - + RAM @@ -2136,7 +2124,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:11 store i32 %tmp - + NULL @@ -2151,7 +2139,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:12 %tmp_19 = sext - + RAM @@ -2166,7 +2154,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:14 %sum_pix2_load - + AddSub @@ -2181,7 +2169,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:15 %tmp_20 = add - + RAM @@ -2196,7 +2184,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:16 store i32 %tmp - + NULL @@ -2211,7 +2199,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:17 %sum_overP1_ad - + RAM @@ -2226,7 +2214,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:18 store i32 0, i - + NULL @@ -2241,7 +2229,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:19 %sum_overP2_ad - + RAM @@ -2256,7 +2244,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:20 store i32 0, i - + NULL @@ -2274,7 +2262,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2289,7 +2277,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2304,7 +2292,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2319,7 +2307,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2334,7 +2322,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2350,7 +2338,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2366,7 +2354,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2382,7 +2370,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2398,7 +2386,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + TAddSub @@ -2414,7 +2402,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + TAddSub @@ -2430,7 +2418,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2446,7 +2434,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2462,7 +2450,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2478,7 +2466,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -2494,7 +2482,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -2510,7 +2498,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -2526,7 +2514,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -2542,7 +2530,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2558,7 +2546,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -2574,7 +2562,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2590,7 +2578,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -2606,7 +2594,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -2622,7 +2610,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -2638,7 +2626,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2654,7 +2642,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -2673,7 +2661,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -2688,7 +2676,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2703,7 +2691,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AddSub @@ -2718,7 +2706,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2733,7 +2721,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2748,7 +2736,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2763,7 +2751,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2778,7 +2766,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + TAddSub @@ -2793,7 +2781,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + TAddSub @@ -2808,7 +2796,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2823,7 +2811,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2838,7 +2826,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2853,7 +2841,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -2868,7 +2856,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -2883,7 +2871,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -2898,7 +2886,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -2913,7 +2901,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -2928,7 +2916,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AddSub @@ -2943,7 +2931,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -2958,7 +2946,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -2973,7 +2961,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AddSub @@ -2988,7 +2976,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -3003,7 +2991,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AddSub @@ -3018,7 +3006,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -3036,7 +3024,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -3051,7 +3039,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AddSub @@ -3066,7 +3054,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -3081,7 +3069,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -3096,7 +3084,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AddSub @@ -3111,7 +3099,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -3126,7 +3114,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -3141,7 +3129,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Cmp @@ -3156,7 +3144,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -3171,7 +3159,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -3187,7 +3175,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -3203,7 +3191,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Cmp @@ -3219,7 +3207,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Cmp @@ -3235,7 +3223,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -3251,7 +3239,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -3271,7 +3259,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM @@ -3286,7 +3274,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Cmp @@ -3301,7 +3289,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + LogicGate @@ -3316,7 +3304,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -3331,7 +3319,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL @@ -3346,33 +3334,13 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 ]]> - - - - -NULL - - - - - - - - - - - - - - + NULL - - + + + @@ -3383,11 +3351,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - - + + + @@ -3398,11 +3367,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - - + + + @@ -3413,25 +3383,44 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - - + + + + - + + + NULL - + + + + + + + + + + +NULL + + @@ -3444,12 +3433,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + - + NULL - + @@ -3460,14 +3449,11 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 ]]> - - - - + NULL - + @@ -3479,10 +3465,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3494,25 +3480,25 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + - + NULL - + @@ -3525,12 +3511,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + - + NULL - + @@ -3542,10 +3528,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3557,10 +3543,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Cmp - + @@ -3572,10 +3558,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AddSub - + @@ -3587,10 +3573,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3602,10 +3588,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3618,10 +3604,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3634,10 +3620,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM - + @@ -3650,10 +3636,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3666,10 +3652,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM - + @@ -3682,10 +3668,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3698,10 +3684,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3715,12 +3701,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + - + RAM - + @@ -3732,10 +3718,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM - + @@ -3747,10 +3733,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3762,10 +3748,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + AXI4Stream - + @@ -3777,10 +3763,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3792,10 +3778,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3808,12 +3794,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + - + NULL - + @@ -3825,10 +3811,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3840,10 +3826,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3855,10 +3841,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3870,10 +3856,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Mul - + @@ -3885,10 +3871,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Mul - + @@ -3901,12 +3887,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + - + RAM - + @@ -3918,10 +3904,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM - + @@ -3933,10 +3919,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Cmp - + @@ -3948,10 +3934,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3964,12 +3950,12 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + - + RAM - + @@ -3982,10 +3968,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -3998,10 +3984,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + Cmp - + @@ -4013,10 +3999,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -4028,10 +4014,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + RAM - + @@ -4044,10 +4030,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + @@ -4060,10 +4046,10 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 - + NULL - + diff --git a/l2_trigger/solution1/.autopilot/db/l2_trigger.sdaccel.xml b/l2_trigger/solution1/.autopilot/db/l2_trigger.sdaccel.xml index 657ee3d..b1beb05 100644 --- a/l2_trigger/solution1/.autopilot/db/l2_trigger.sdaccel.xml +++ b/l2_trigger/solution1/.autopilot/db/l2_trigger.sdaccel.xml @@ -1,7 +1,7 @@
-Fri Apr 13 19:40:42 2018 +Wed Apr 18 11:09:40 2018 2016.2 (Build 1577090 on Thu Jun 02 16:59:10 MDT 2016) l2_trigger @@ -36,10 +36,10 @@ 0, 32767, 1, -, -, 0 ~ 32767, no 16, 262152, 2 ~ 32769, -, -, 8, no 0, 32767, 1, -, -, 0 ~ 32767, no -?, ?, 260 ~ 88274558, -, -, ?, no +?, ?, 260 ~ 84080382, -, -, ?, no 0, 32767, 1, -, -, 0 ~ 32767, no -256, 88077952, 2 ~ 688109, -, -, 128, no -0, 688107, 18 ~ 21, -, -, 0 ~ 32767, no +256, 83883776, 2 ~ 655342, -, -, 128, no +0, 655340, 18 ~ 20, -, -, 0 ~ 32767, no 14, 14, 2, -, -, 7, no 0, 163835, 5, -, -, 0 ~ 32767, no @@ -58,8 +58,8 @@ -, -, -, - 0, -, 110, 152 58, -, 0, 0 --, -, -, 528 --, -, 636, - +-, -, -, 560 +-, -, 634, - 530, 400, 157200, 78600 10, 1, ~0, 1 @@ -135,7 +135,7 @@ Name, LUT, Input Size, Bits, Total Bits -18, 23, 1, 23 +18, 21, 1, 211, 2, 1, 214, 5, 14, 7017, 4, 17, 68 @@ -165,13 +165,14 @@ 32, 4, 32, 12811, 4, 11, 4432, 4, 32, 128 -32, 5, 32, 160 +32, 3, 32, 96 +32, 4, 32, 128
 Name, FF, LUT, Bits, Const Bits32, 0, 32, 0 -22, 0, 22, 0 +20, 0, 20, 01, 0, 1, 014, 0, 14, 014, 0, 14, 0 diff --git a/l2_trigger/solution1/.autopilot/db/l2_trigger.tbgen.tcl b/l2_trigger/solution1/.autopilot/db/l2_trigger.tbgen.tcl index e407a87..806e137 100644 --- a/l2_trigger/solution1/.autopilot/db/l2_trigger.tbgen.tcl +++ b/l2_trigger/solution1/.autopilot/db/l2_trigger.tbgen.tcl @@ -1,22 +1,22 @@ set C_TypeInfoList {{ "l2_trigger" : [[], { "return": [[], "void"]} , [{"ExternC" : 0}], [ {"in_stream": [[], {"reference": "0"}] }, {"out_stream": [[], {"reference": "1"}] }, {"n_pixels_in_bus": [[],"2"] }, {"N_BG": [[],"3"] }, {"LOW_THRESH": [[],"4"] }, {"trig_data": [[],{ "pointer": {"scalar": "unsigned int"}}] }, {"trig_pixel": [[],{ "pointer": {"scalar": "unsigned int"}}] }],[],""], -"1": [ "STREAM_64", {"typedef": [[[],"5"],""]}], -"5": [ "stream >", {"hls_type": {"stream": [[[[],"6"]],"7"]}}], -"6": [ "ap_axis<64, 2, 5, 6>", {"struct": [[],[{"D":[[], {"scalar": { "int": 64}}]},{"U":[[], {"scalar": { "int": 2}}]},{"TI":[[], {"scalar": { "int": 5}}]},{"TD":[[], {"scalar": { "int": 6}}]}],[{ "data": [[], "8"]},{ "keep": [[], "9"]},{ "strb": [[], "9"]},{ "user": [[], "10"]},{ "last": [[], "11"]},{ "id": [[], "12"]},{ "dest": [[], "13"]}],""]}], -"9": [ "ap_uint<8>", {"hls_type": {"ap_uint": [[[[], {"scalar": { "int": 8}}]],""]}}], -"10": [ "ap_uint<2>", {"hls_type": {"ap_uint": [[[[], {"scalar": { "int": 2}}]],""]}}], -"11": [ "ap_uint<1>", {"hls_type": {"ap_uint": [[[[], {"scalar": { "int": 1}}]],""]}}], "2": [ "uint16_t", {"typedef": [[[], {"scalar": "unsigned short"}],""]}], "3": [ "uint8_t", {"typedef": [[[], {"scalar": "unsigned char"}],""]}], "4": [ "uint32_t", {"typedef": [[[], {"scalar": "unsigned int"}],""]}], -"0": [ "STREAM_32", {"typedef": [[[],"14"],""]}], -"14": [ "stream >", {"hls_type": {"stream": [[[[],"15"]],"7"]}}], -"15": [ "ap_axis<32, 2, 5, 6>", {"struct": [[],[{"D":[[], {"scalar": { "int": 32}}]},{"U":[[], {"scalar": { "int": 2}}]},{"TI":[[], {"scalar": { "int": 5}}]},{"TD":[[], {"scalar": { "int": 6}}]}],[{ "data": [[], "16"]},{ "keep": [[], "17"]},{ "strb": [[], "17"]},{ "user": [[], "10"]},{ "last": [[], "11"]},{ "id": [[], "12"]},{ "dest": [[], "13"]}],""]}], -"12": [ "ap_uint<5>", {"hls_type": {"ap_uint": [[[[], {"scalar": { "int": 5}}]],""]}}], -"8": [ "ap_int<64>", {"hls_type": {"ap_int": [[[[], {"scalar": { "int": 64}}]],""]}}], -"17": [ "ap_uint<4>", {"hls_type": {"ap_uint": [[[[], {"scalar": { "int": 4}}]],""]}}], -"13": [ "ap_uint<6>", {"hls_type": {"ap_uint": [[[[], {"scalar": { "int": 6}}]],""]}}], -"16": [ "ap_int<32>", {"hls_type": {"ap_int": [[[[], {"scalar": { "int": 32}}]],""]}}], +"1": [ "STREAM_64", {"typedef": [[[],"5"],""]}], +"5": [ "stream >", {"hls_type": {"stream": [[[[],"6"]],"7"]}}], +"0": [ "STREAM_32", {"typedef": [[[],"8"],""]}], +"8": [ "stream >", {"hls_type": {"stream": [[[[],"9"]],"7"]}}], +"9": [ "ap_axis<32, 2, 5, 6>", {"struct": [[],[{"D":[[], {"scalar": { "int": 32}}]},{"U":[[], {"scalar": { "int": 2}}]},{"TI":[[], {"scalar": { "int": 5}}]},{"TD":[[], {"scalar": { "int": 6}}]}],[{ "data": [[], "10"]},{ "keep": [[], "11"]},{ "strb": [[], "11"]},{ "user": [[], "12"]},{ "last": [[], "13"]},{ "id": [[], "14"]},{ "dest": [[], "15"]}],""]}], +"15": [ "ap_uint<6>", {"hls_type": {"ap_uint": [[[[], {"scalar": { "int": 6}}]],""]}}], +"11": [ "ap_uint<4>", {"hls_type": {"ap_uint": [[[[], {"scalar": { "int": 4}}]],""]}}], +"10": [ "ap_int<32>", {"hls_type": {"ap_int": [[[[], {"scalar": { "int": 32}}]],""]}}], +"12": [ "ap_uint<2>", {"hls_type": {"ap_uint": [[[[], {"scalar": { "int": 2}}]],""]}}], +"13": [ "ap_uint<1>", {"hls_type": {"ap_uint": [[[[], {"scalar": { "int": 1}}]],""]}}], +"14": [ "ap_uint<5>", {"hls_type": {"ap_uint": [[[[], {"scalar": { "int": 5}}]],""]}}], +"6": [ "ap_axis<64, 2, 5, 6>", {"struct": [[],[{"D":[[], {"scalar": { "int": 64}}]},{"U":[[], {"scalar": { "int": 2}}]},{"TI":[[], {"scalar": { "int": 5}}]},{"TD":[[], {"scalar": { "int": 6}}]}],[{ "data": [[], "16"]},{ "keep": [[], "17"]},{ "strb": [[], "17"]},{ "user": [[], "12"]},{ "last": [[], "13"]},{ "id": [[], "14"]},{ "dest": [[], "15"]}],""]}], +"17": [ "ap_uint<8>", {"hls_type": {"ap_uint": [[[[], {"scalar": { "int": 8}}]],""]}}], +"16": [ "ap_int<64>", {"hls_type": {"ap_int": [[[[], {"scalar": { "int": 64}}]],""]}}], "7": ["hls", ""] }} set moduleName l2_trigger diff --git a/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.bind.rpt b/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.bind.rpt index 4931e6d..7bc4311 100644 --- a/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.bind.rpt +++ b/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.bind.rpt @@ -3,7 +3,7 @@ ================================================================ == Vivado HLS Report for 'l2_trigger' ================================================================ -* Date: Fri Apr 13 19:40:42 2018 +* Date: Wed Apr 18 11:09:40 2018 * Version: 2016.2 (Build 1577090 on Thu Jun 02 16:59:10 MDT 2016) * Project: l2_trigger @@ -44,10 +44,10 @@ |- Loop 1 | 0| 32767| 1| -| -| 0 ~ 32767 | no | |- Loop 2 | 16| 262152| 2 ~ 32769 | -| -| 8| no | | + Loop 2.1 | 0| 32767| 1| -| -| 0 ~ 32767 | no | - |- Loop 3 | ?| ?| 260 ~ 88274558 | -| -| ?| no | + |- Loop 3 | ?| ?| 260 ~ 84080382 | -| -| ?| no | | + Loop 3.1 | 0| 32767| 1| -| -| 0 ~ 32767 | no | - | + Loop 3.2 | 256| 88077952| 2 ~ 688109 | -| -| 128| no | - | ++ Loop 3.2.1 | 0| 688107| 18 ~ 21 | -| -| 0 ~ 32767 | no | + | + Loop 3.2 | 256| 83883776| 2 ~ 655342 | -| -| 128| no | + | ++ Loop 3.2.1 | 0| 655340| 18 ~ 20 | -| -| 0 ~ 32767 | no | | +++ Loop 3.2.1.1 | 14| 14| 2| -| -| 7| no | | + Loop 3.3 | 0| 163835| 5| -| -| 0 ~ 32767 | no | +---------------------+-----+----------+----------------+-----------+-----------+-----------+----------+ @@ -78,7 +78,7 @@ IsGatedGlobalClock: 0 ============================================================ + Verbose Summary: Schedule ============================================================ -* Number of FSM states: 22 +* Number of FSM states: 20 * Pipeline: 0 * Dataflow Pipeline: 0 @@ -101,7 +101,7 @@ IsGatedGlobalClock: 0 6 / (!exitcond8) 7 --> 8 / (!exitcond) - 18 / (exitcond) + 16 / (exitcond) 8 --> 7 / (exitcond7) 9 / (!exitcond7) @@ -115,90 +115,86 @@ IsGatedGlobalClock: 0 12 --> 13 / (!tmp_25) 8 / (tmp_25 & !tmp_34) - 16 / (tmp_25 & tmp_34) + 15 / (tmp_25 & tmp_34) 13 --> 8 / (!or_cond) 14 / (or_cond) 14 --> - 15 / true + 8 / true 15 --> 8 / true 16 --> - 17 / true + 5 / (exitcond6) + 17 / (!exitcond6) 17 --> - 8 / true + 18 / true 18 --> - 5 / (exitcond6) - 19 / (!exitcond6) + 19 / true 19 --> 20 / true 20 --> - 21 / true -21 --> - 22 / true -22 --> - 18 / true + 16 / true * FSM state operations: : 2.38ns -ST_1: stg_23 [1/1] 0.00ns +ST_1: stg_21 [1/1] 0.00ns arrayctor.loop1.preheader:0 call void (...)* @_ssdm_op_SpecBitsMap(i32* %in_stream_V_data_V), !map !102 -ST_1: stg_24 [1/1] 0.00ns +ST_1: stg_22 [1/1] 0.00ns arrayctor.loop1.preheader:1 call void (...)* @_ssdm_op_SpecBitsMap(i4* %in_stream_V_keep_V), !map !106 -ST_1: stg_25 [1/1] 0.00ns +ST_1: stg_23 [1/1] 0.00ns arrayctor.loop1.preheader:2 call void (...)* @_ssdm_op_SpecBitsMap(i4* %in_stream_V_strb_V), !map !110 -ST_1: stg_26 [1/1] 0.00ns +ST_1: stg_24 [1/1] 0.00ns arrayctor.loop1.preheader:3 call void (...)* @_ssdm_op_SpecBitsMap(i2* %in_stream_V_user_V), !map !114 -ST_1: stg_27 [1/1] 0.00ns +ST_1: stg_25 [1/1] 0.00ns arrayctor.loop1.preheader:4 call void (...)* @_ssdm_op_SpecBitsMap(i1* %in_stream_V_last_V), !map !118 -ST_1: stg_28 [1/1] 0.00ns +ST_1: stg_26 [1/1] 0.00ns arrayctor.loop1.preheader:5 call void (...)* @_ssdm_op_SpecBitsMap(i5* %in_stream_V_id_V), !map !122 -ST_1: stg_29 [1/1] 0.00ns +ST_1: stg_27 [1/1] 0.00ns arrayctor.loop1.preheader:6 call void (...)* @_ssdm_op_SpecBitsMap(i6* %in_stream_V_dest_V), !map !126 -ST_1: stg_30 [1/1] 0.00ns +ST_1: stg_28 [1/1] 0.00ns arrayctor.loop1.preheader:7 call void (...)* @_ssdm_op_SpecBitsMap(i64* %out_stream_V_data_V), !map !130 -ST_1: stg_31 [1/1] 0.00ns +ST_1: stg_29 [1/1] 0.00ns arrayctor.loop1.preheader:8 call void (...)* @_ssdm_op_SpecBitsMap(i8* %out_stream_V_keep_V), !map !134 -ST_1: stg_32 [1/1] 0.00ns +ST_1: stg_30 [1/1] 0.00ns arrayctor.loop1.preheader:9 call void (...)* @_ssdm_op_SpecBitsMap(i8* %out_stream_V_strb_V), !map !138 -ST_1: stg_33 [1/1] 0.00ns +ST_1: stg_31 [1/1] 0.00ns arrayctor.loop1.preheader:10 call void (...)* @_ssdm_op_SpecBitsMap(i2* %out_stream_V_user_V), !map !142 -ST_1: stg_34 [1/1] 0.00ns +ST_1: stg_32 [1/1] 0.00ns arrayctor.loop1.preheader:11 call void (...)* @_ssdm_op_SpecBitsMap(i1* %out_stream_V_last_V), !map !146 -ST_1: stg_35 [1/1] 0.00ns +ST_1: stg_33 [1/1] 0.00ns arrayctor.loop1.preheader:12 call void (...)* @_ssdm_op_SpecBitsMap(i5* %out_stream_V_id_V), !map !150 -ST_1: stg_36 [1/1] 0.00ns +ST_1: stg_34 [1/1] 0.00ns arrayctor.loop1.preheader:13 call void (...)* @_ssdm_op_SpecBitsMap(i6* %out_stream_V_dest_V), !map !154 -ST_1: stg_37 [1/1] 0.00ns +ST_1: stg_35 [1/1] 0.00ns arrayctor.loop1.preheader:14 call void (...)* @_ssdm_op_SpecBitsMap(i16 %n_pixels_in_bus), !map !158 -ST_1: stg_38 [1/1] 0.00ns +ST_1: stg_36 [1/1] 0.00ns arrayctor.loop1.preheader:15 call void (...)* @_ssdm_op_SpecBitsMap(i8 %N_BG), !map !164 -ST_1: stg_39 [1/1] 0.00ns +ST_1: stg_37 [1/1] 0.00ns arrayctor.loop1.preheader:16 call void (...)* @_ssdm_op_SpecBitsMap(i32 %LOW_THRESH), !map !168 -ST_1: stg_40 [1/1] 0.00ns +ST_1: stg_38 [1/1] 0.00ns arrayctor.loop1.preheader:17 call void (...)* @_ssdm_op_SpecBitsMap(i32* %trig_data), !map !172 -ST_1: stg_41 [1/1] 0.00ns +ST_1: stg_39 [1/1] 0.00ns arrayctor.loop1.preheader:18 call void (...)* @_ssdm_op_SpecBitsMap(i32* %trig_pixel), !map !176 -ST_1: stg_42 [1/1] 0.00ns +ST_1: stg_40 [1/1] 0.00ns arrayctor.loop1.preheader:19 call void (...)* @_ssdm_op_SpecTopModule([11 x i8]* @l2_trigger_str) nounwind ST_1: LOW_THRESH_read [1/1] 1.00ns @@ -234,43 +230,43 @@ arrayctor.loop1.preheader:29 %data_shift2 = alloca [9216 x i17], align 4 ST_1: thresh2 [1/1] 2.38ns arrayctor.loop1.preheader:30 %thresh2 = alloca [1152 x i32], align 16 -ST_1: stg_54 [1/1] 0.00ns +ST_1: stg_52 [1/1] 0.00ns arrayctor.loop1.preheader:31 call void (...)* @_ssdm_op_SpecInterface(i32* %in_stream_V_data_V, i4* %in_stream_V_keep_V, i4* %in_stream_V_strb_V, i2* %in_stream_V_user_V, i1* %in_stream_V_last_V, i5* %in_stream_V_id_V, i6* %in_stream_V_dest_V, [5 x i8]* @p_str1804, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind -ST_1: stg_55 [1/1] 0.00ns +ST_1: stg_53 [1/1] 0.00ns arrayctor.loop1.preheader:32 call void (...)* @_ssdm_op_SpecInterface(i32* %trig_data, [8 x i8]* @p_str1806, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind -ST_1: stg_56 [1/1] 0.00ns +ST_1: stg_54 [1/1] 0.00ns arrayctor.loop1.preheader:33 call void (...)* @_ssdm_op_SpecInterface(i32* %trig_pixel, [8 x i8]* @p_str1806, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind -ST_1: stg_57 [1/1] 0.00ns +ST_1: stg_55 [1/1] 0.00ns arrayctor.loop1.preheader:34 call void (...)* @_ssdm_op_SpecInterface(i64* %out_stream_V_data_V, i8* %out_stream_V_keep_V, i8* %out_stream_V_strb_V, i2* %out_stream_V_user_V, i1* %out_stream_V_last_V, i5* %out_stream_V_id_V, i6* %out_stream_V_dest_V, [5 x i8]* @p_str1804, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind -ST_1: stg_58 [1/1] 0.00ns +ST_1: stg_56 [1/1] 0.00ns arrayctor.loop1.preheader:35 call void (...)* @_ssdm_op_SpecInterface(i16 %n_pixels_in_bus, [10 x i8]* @p_str1807, i32 0, i32 0, i32 0, i32 0, [9 x i8]* @p_str1808, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind ST_1: tmp_1 [1/1] 0.00ns arrayctor.loop1.preheader:36 %tmp_1 = zext i8 %N_BG_read to i32 -ST_1: stg_60 [1/1] 0.00ns +ST_1: stg_58 [1/1] 0.00ns arrayctor.loop1.preheader:37 call void (...)* @_ssdm_op_SpecInterface(i8 %N_BG, [10 x i8]* @p_str1807, i32 0, i32 0, i32 0, i32 0, [9 x i8]* @p_str1808, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind -ST_1: stg_61 [1/1] 0.00ns +ST_1: stg_59 [1/1] 0.00ns arrayctor.loop1.preheader:38 call void (...)* @_ssdm_op_SpecInterface(i32 %LOW_THRESH, [10 x i8]* @p_str1807, i32 0, i32 0, i32 0, i32 0, [9 x i8]* @p_str1808, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind -ST_1: stg_62 [1/1] 0.00ns +ST_1: stg_60 [1/1] 0.00ns arrayctor.loop1.preheader:39 call void (...)* @_ssdm_op_SpecInterface(i32 0, [10 x i8]* @p_str1807, i32 0, i32 0, i32 0, i32 0, [9 x i8]* @p_str1808, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind -ST_1: stg_63 [1/1] 0.00ns +ST_1: stg_61 [1/1] 0.00ns arrayctor.loop1.preheader:40 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 0) -ST_1: stg_64 [1/1] 0.00ns +ST_1: stg_62 [1/1] 0.00ns arrayctor.loop1.preheader:41 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_pixel, i32 0) ST_1: tmp_2 [1/1] 0.00ns arrayctor.loop1.preheader:42 %tmp_2 = call i15 @_ssdm_op_PartSelect.i15.i16.i32.i32(i16 %n_pixels_in_bus_read, i32 1, i32 15) -ST_1: stg_66 [1/1] 1.31ns +ST_1: stg_64 [1/1] 1.31ns arrayctor.loop1.preheader:43 br label %0 @@ -287,7 +283,7 @@ ST_2: exitcond2 [1/1] 1.85ns ST_2: i_5 [1/1] 1.60ns :3 %i_5 = add i15 %i, 1 -ST_2: stg_71 [1/1] 1.31ns +ST_2: stg_69 [1/1] 1.31ns :4 br i1 %exitcond2, label %.preheader84, label %1 ST_2: tmp_4 [1/1] 0.00ns @@ -296,28 +292,28 @@ ST_2: tmp_4 [1/1] 0.00ns ST_2: sum_pix1_addr [1/1] 0.00ns :1 %sum_pix1_addr = getelementptr inbounds [1152 x i32]* %sum_pix1, i64 0, i64 %tmp_4 -ST_2: stg_74 [1/1] 2.38ns +ST_2: stg_72 [1/1] 2.38ns :2 store i32 0, i32* %sum_pix1_addr, align 4 ST_2: sum_pix2_addr [1/1] 0.00ns :3 %sum_pix2_addr = getelementptr inbounds [1152 x i32]* %sum_pix2, i64 0, i64 %tmp_4 -ST_2: stg_76 [1/1] 2.38ns +ST_2: stg_74 [1/1] 2.38ns :4 store i32 0, i32* %sum_pix2_addr, align 4 ST_2: thresh1_addr [1/1] 0.00ns :5 %thresh1_addr = getelementptr inbounds [1152 x i32]* %thresh1, i64 0, i64 %tmp_4 -ST_2: stg_78 [1/1] 2.38ns +ST_2: stg_76 [1/1] 2.38ns :6 store i32 25500, i32* %thresh1_addr, align 4 ST_2: thresh2_addr [1/1] 0.00ns :7 %thresh2_addr = getelementptr inbounds [1152 x i32]* %thresh2, i64 0, i64 %tmp_4 -ST_2: stg_80 [1/1] 2.38ns +ST_2: stg_78 [1/1] 2.38ns :8 store i32 25500, i32* %thresh2_addr, align 4 -ST_2: stg_81 [1/1] 0.00ns +ST_2: stg_79 [1/1] 0.00ns :9 br label %0 @@ -334,7 +330,7 @@ ST_3: empty_7 [1/1] 0.00ns ST_3: kk_2 [1/1] 0.70ns .preheader84:3 %kk_2 = add i4 %kk, 1 -ST_3: stg_86 [1/1] 0.00ns +ST_3: stg_84 [1/1] 0.00ns .preheader84:4 br i1 %exitcond1, label %.preheader82, label %.preheader83.preheader ST_3: tmp_6 [1/1] 0.00ns @@ -352,7 +348,7 @@ ST_3: p_shl1_cast [1/1] 0.00ns ST_3: tmp_3 [1/1] 1.60ns .preheader83.preheader:4 %tmp_3 = add i15 %p_shl1_cast, %p_shl_cast -ST_3: stg_92 [1/1] 1.31ns +ST_3: stg_90 [1/1] 1.31ns .preheader83.preheader:5 br label %.preheader83 @@ -369,7 +365,7 @@ ST_4: exitcond9 [1/1] 1.85ns ST_4: i_6 [1/1] 1.60ns .preheader83:3 %i_6 = add i15 %i_1, 1 -ST_4: stg_97 [1/1] 0.00ns +ST_4: stg_95 [1/1] 0.00ns .preheader83:4 br i1 %exitcond9, label %.preheader84, label %2 ST_4: tmp_8 [1/1] 1.60ns @@ -384,13 +380,13 @@ ST_4: data_shift1_addr [1/1] 0.00ns ST_4: data_shift2_addr [1/1] 0.00ns :3 %data_shift2_addr = getelementptr [9216 x i17]* %data_shift2, i64 0, i64 %tmp_18_cast -ST_4: stg_102 [1/1] 2.38ns +ST_4: stg_100 [1/1] 2.38ns :4 store i17 0, i17* %data_shift1_addr, align 4 -ST_4: stg_103 [1/1] 2.38ns +ST_4: stg_101 [1/1] 2.38ns :5 store i17 0, i17* %data_shift2_addr, align 4 -ST_4: stg_104 [1/1] 0.00ns +ST_4: stg_102 [1/1] 0.00ns :6 br label %.preheader83 @@ -398,10 +394,10 @@ ST_4: stg_104 [1/1] 0.00ns ST_5: tmp [1/1] 0.00ns .preheader82:0 %tmp = call i1 @_ssdm_op_NbReadReq.axis.i32P.i4P.i4P.i2P.i1P.i5P.i6P(i32* %in_stream_V_data_V, i4* %in_stream_V_keep_V, i4* %in_stream_V_strb_V, i2* %in_stream_V_user_V, i1* %in_stream_V_last_V, i5* %in_stream_V_id_V, i6* %in_stream_V_dest_V, i32 1) -ST_5: stg_106 [1/1] 1.31ns +ST_5: stg_104 [1/1] 1.31ns .preheader82:1 br i1 %tmp, label %.preheader81, label %14 -ST_5: stg_107 [1/1] 0.00ns +ST_5: stg_105 [1/1] 0.00ns :0 ret void @@ -418,7 +414,7 @@ ST_6: exitcond8 [1/1] 1.85ns ST_6: i_7 [1/1] 1.60ns .preheader81:3 %i_7 = add i15 %i_2, 1 -ST_6: stg_112 [1/1] 1.31ns +ST_6: stg_110 [1/1] 1.31ns .preheader81:4 br i1 %exitcond8, label %.preheader80, label %3 ST_6: tmp_7 [1/1] 0.00ns @@ -427,16 +423,16 @@ ST_6: tmp_7 [1/1] 0.00ns ST_6: sum_pix1_addr_1 [1/1] 0.00ns :1 %sum_pix1_addr_1 = getelementptr inbounds [1152 x i32]* %sum_pix1, i64 0, i64 %tmp_7 -ST_6: stg_115 [1/1] 2.38ns +ST_6: stg_113 [1/1] 2.38ns :2 store i32 0, i32* %sum_pix1_addr_1, align 4 ST_6: sum_pix2_addr_1 [1/1] 0.00ns :3 %sum_pix2_addr_1 = getelementptr inbounds [1152 x i32]* %sum_pix2, i64 0, i64 %tmp_7 -ST_6: stg_117 [1/1] 2.38ns +ST_6: stg_115 [1/1] 2.38ns :4 store i32 0, i32* %sum_pix2_addr_1, align 4 -ST_6: stg_118 [1/1] 0.00ns +ST_6: stg_116 [1/1] 0.00ns :5 br label %.preheader81 @@ -456,7 +452,7 @@ ST_7: empty_10 [1/1] 0.00ns ST_7: tmp_5 [1/1] 1.40ns .preheader80:4 %tmp_5 = add i8 %k, 1 -ST_7: stg_124 [1/1] 1.31ns +ST_7: stg_122 [1/1] 1.31ns .preheader80:5 br i1 %exitcond, label %.preheader, label %.preheader79 @@ -476,7 +472,7 @@ ST_8: exitcond7 [1/1] 1.85ns ST_8: i_9 [1/1] 1.60ns .preheader79:4 %i_9 = add i15 %i_3, 1 -ST_8: stg_130 [1/1] 0.00ns +ST_8: stg_128 [1/1] 0.00ns .preheader79:5 br i1 %exitcond7, label %.preheader80, label %_ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit ST_8: tmp_15 [1/1] 0.00ns @@ -523,7 +519,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:9 %sum_pix1_load_ ST_9: tmp_18 [1/1] 2.00ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:10 %tmp_18 = add i32 %sum_pix1_load_1, %tmp_17 -ST_9: stg_145 [1/1] 2.38ns +ST_9: stg_143 [1/1] 2.38ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:11 store i32 %tmp_18, i32* %sum_pix1_addr_3, align 4 ST_9: tmp_19 [1/1] 0.00ns @@ -535,22 +531,22 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:14 %sum_pix2_load ST_9: tmp_20 [1/1] 2.00ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:15 %tmp_20 = add i32 %sum_pix2_load_1, %tmp_19 -ST_9: stg_149 [1/1] 2.38ns +ST_9: stg_147 [1/1] 2.38ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:16 store i32 %tmp_20, i32* %sum_pix2_addr_3, align 4 ST_9: sum_overP1_addr [1/1] 0.00ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:17 %sum_overP1_addr = getelementptr inbounds [1152 x i32]* %sum_overP1, i64 0, i64 %tmp_15 -ST_9: stg_151 [1/1] 2.38ns +ST_9: stg_149 [1/1] 2.38ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:18 store i32 0, i32* %sum_overP1_addr, align 4 ST_9: sum_overP2_addr [1/1] 0.00ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:19 %sum_overP2_addr = getelementptr inbounds [1152 x i32]* %sum_overP2, i64 0, i64 %tmp_15 -ST_9: stg_153 [1/1] 2.38ns +ST_9: stg_151 [1/1] 2.38ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:20 store i32 0, i32* %sum_overP2_addr, align 4 -ST_9: stg_154 [1/1] 1.31ns +ST_9: stg_152 [1/1] 1.31ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 @@ -564,7 +560,7 @@ ST_10: tmp_22 [1/1] 0.00ns ST_10: empty_13 [1/1] 0.00ns :2 %empty_13 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 7, i64 7, i64 7) -ST_10: stg_158 [1/1] 0.00ns +ST_10: stg_156 [1/1] 0.00ns :3 br i1 %tmp_22, label %6, label %5 ST_10: tmp_26 [1/1] 0.00ns @@ -609,13 +605,13 @@ ST_10: sum_overP2_load [2/2] 2.38ns ST_10: tmp_19_cast [1/1] 0.00ns :0 %tmp_19_cast = sext i16 %tmp_16 to i17 -ST_10: stg_173 [1/1] 2.38ns +ST_10: stg_171 [1/1] 2.38ns :1 store i17 %tmp_19_cast, i17* %data_shift1_addr_1, align 4 ST_10: tmp_21_cast [1/1] 0.00ns :2 %tmp_21_cast = sext i16 %phitmp to i17 -ST_10: stg_175 [1/1] 2.38ns +ST_10: stg_173 [1/1] 2.38ns :3 store i17 %tmp_21_cast, i17* %data_shift2_addr_1, align 4 ST_10: sum_overP1_load_1 [2/2] 2.38ns @@ -668,7 +664,7 @@ ST_11: data_shift1_addr_3 [1/1] 0.00ns ST_11: data_shift2_addr_3 [1/1] 0.00ns :20 %data_shift2_addr_3 = getelementptr [9216 x i17]* %data_shift2, i64 0, i64 %tmp_49_cast -ST_11: stg_192 [1/1] 2.38ns +ST_11: stg_190 [1/1] 2.38ns :21 store i17 %data_shift1_load, i17* %data_shift1_addr_3, align 4 ST_11: data_shift2_load [1/2] 2.38ns @@ -677,7 +673,7 @@ ST_11: data_shift2_load [1/2] 2.38ns ST_11: extLd1 [1/1] 0.00ns :23 %extLd1 = sext i17 %data_shift2_load to i32 -ST_11: stg_195 [1/1] 2.38ns +ST_11: stg_193 [1/1] 2.38ns :24 store i17 %data_shift2_load, i17* %data_shift2_addr_3, align 4 ST_11: sum_overP1_load [1/2] 2.38ns @@ -686,7 +682,7 @@ ST_11: sum_overP1_load [1/2] 2.38ns ST_11: tmp_29 [1/1] 2.00ns :26 %tmp_29 = add i32 %sum_overP1_load, %extLd -ST_11: stg_198 [1/1] 2.38ns +ST_11: stg_196 [1/1] 2.38ns :27 store i32 %tmp_29, i32* %sum_overP1_addr, align 4 ST_11: sum_overP2_load [1/2] 2.38ns @@ -695,13 +691,13 @@ ST_11: sum_overP2_load [1/2] 2.38ns ST_11: tmp_30 [1/1] 2.00ns :29 %tmp_30 = add i32 %sum_overP2_load, %extLd1 -ST_11: stg_201 [1/1] 2.38ns +ST_11: stg_199 [1/1] 2.38ns :30 store i32 %tmp_30, i32* %sum_overP2_addr, align 4 ST_11: kk_3 [1/1] 0.70ns :31 %kk_3 = add i4 %kk_1, -1 -ST_11: stg_203 [1/1] 0.00ns +ST_11: stg_201 [1/1] 0.00ns :32 br label %4 @@ -712,7 +708,7 @@ ST_12: sum_overP1_load_1 [1/2] 2.38ns ST_12: tmp_23 [1/1] 2.00ns :5 %tmp_23 = add i32 %tmp_17, %sum_overP1_load_1 -ST_12: stg_206 [1/1] 2.38ns +ST_12: stg_204 [1/1] 2.38ns :6 store i32 %tmp_23, i32* %sum_overP1_addr, align 4 ST_12: sum_overP2_load_1 [1/2] 2.38ns @@ -721,7 +717,7 @@ ST_12: sum_overP2_load_1 [1/2] 2.38ns ST_12: tmp_24 [1/1] 2.00ns :8 %tmp_24 = add i32 %tmp_19, %sum_overP2_load_1 -ST_12: stg_209 [1/1] 2.38ns +ST_12: stg_207 [1/1] 2.38ns :9 store i32 %tmp_24, i32* %sum_overP2_addr, align 4 ST_12: thresh1_load [1/2] 2.38ns @@ -730,7 +726,7 @@ ST_12: thresh1_load [1/2] 2.38ns ST_12: tmp_25 [1/1] 2.12ns :12 %tmp_25 = icmp ugt i32 %tmp_23, %thresh1_load -ST_12: stg_212 [1/1] 0.00ns +ST_12: stg_210 [1/1] 0.00ns :13 br i1 %tmp_25, label %7, label %9 ST_12: thresh2_addr_2 [1/1] 0.00ns @@ -745,10 +741,10 @@ ST_12: tmp_36 [1/1] 1.04ns ST_12: tmp_34 [1/1] 1.04ns :0 %tmp_34 = icmp eq i32 %itrig_1, 0 -ST_12: stg_217 [1/1] 0.00ns +ST_12: stg_215 [1/1] 0.00ns :1 br i1 %tmp_34, label %8, label %.preheader79 -ST_12: stg_218 [1/1] 0.00ns +ST_12: stg_216 [1/1] 0.00ns :0 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 1) @@ -762,166 +758,162 @@ ST_13: tmp_35 [1/1] 2.12ns ST_13: or_cond [1/1] 1.15ns :4 %or_cond = and i1 %tmp_35, %tmp_36 -ST_13: stg_222 [1/1] 0.00ns +ST_13: stg_220 [1/1] 0.00ns :5 br i1 %or_cond, label %10, label %.preheader79 -ST_13: stg_223 [1/1] 0.00ns +ST_13: stg_221 [1/1] 0.00ns :0 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 1) - - : 0.00ns -ST_14: stg_224 [1/1] 0.00ns -:1 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 0) - - - : 0.00ns -ST_15: tmp_38 [1/1] 0.00ns +ST_13: tmp_38 [1/1] 0.00ns :2 %tmp_38 = call i16 @_ssdm_op_BitConcatenate.i16.i15.i1(i15 %i_3, i1 false) -ST_15: tmp_39 [1/1] 0.00ns +ST_13: tmp_39 [1/1] 0.00ns :3 %tmp_39 = or i16 %tmp_38, 1 -ST_15: tmp_40_cast [1/1] 0.00ns +ST_13: tmp_40_cast [1/1] 0.00ns :4 %tmp_40_cast = zext i16 %tmp_39 to i32 -ST_15: stg_228 [1/1] 0.00ns -:5 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 %tmp_40_cast) +ST_13: stg_225 [1/1] 0.00ns +:5 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_pixel, i32 %tmp_40_cast) + + + : 0.00ns +ST_14: stg_226 [1/1] 0.00ns +:1 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 0) -ST_15: stg_229 [1/1] 0.00ns +ST_14: stg_227 [1/1] 0.00ns :6 br label %.preheader79 - : 0.00ns -ST_16: stg_230 [1/1] 0.00ns + : 0.00ns +ST_15: stg_228 [1/1] 0.00ns :1 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 0) - - : 0.00ns -ST_17: tmp_37 [1/1] 0.00ns +ST_15: tmp_37 [1/1] 0.00ns :2 %tmp_37 = call i16 @_ssdm_op_BitConcatenate.i16.i15.i1(i15 %i_3, i1 false) -ST_17: tmp_38_cast [1/1] 0.00ns +ST_15: tmp_38_cast [1/1] 0.00ns :3 %tmp_38_cast = zext i16 %tmp_37 to i32 -ST_17: stg_233 [1/1] 0.00ns -:4 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 %tmp_38_cast) +ST_15: stg_231 [1/1] 0.00ns +:4 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_pixel, i32 %tmp_38_cast) -ST_17: stg_234 [1/1] 0.00ns +ST_15: stg_232 [1/1] 0.00ns :5 br label %.preheader79 - : 2.38ns -ST_18: i_4 [1/1] 0.00ns + : 2.38ns +ST_16: i_4 [1/1] 0.00ns .preheader:0 %i_4 = phi i15 [ %i_8, %._crit_edge87 ], [ 0, %.preheader80 ] -ST_18: empty_14 [1/1] 0.00ns +ST_16: empty_14 [1/1] 0.00ns .preheader:1 %empty_14 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 0, i64 32767, i64 0) -ST_18: exitcond6 [1/1] 1.85ns +ST_16: exitcond6 [1/1] 1.85ns .preheader:2 %exitcond6 = icmp eq i15 %i_4, %tmp_2 -ST_18: i_8 [1/1] 1.60ns +ST_16: i_8 [1/1] 1.60ns .preheader:3 %i_8 = add i15 %i_4, 1 -ST_18: stg_239 [1/1] 0.00ns +ST_16: stg_237 [1/1] 0.00ns .preheader:4 br i1 %exitcond6, label %.preheader82, label %11 -ST_18: tmp_9 [1/1] 0.00ns +ST_16: tmp_9 [1/1] 0.00ns :0 %tmp_9 = zext i15 %i_4 to i64 -ST_18: sum_pix2_addr_2 [1/1] 0.00ns +ST_16: sum_pix2_addr_2 [1/1] 0.00ns :1 %sum_pix2_addr_2 = getelementptr inbounds [1152 x i32]* %sum_pix2, i64 0, i64 %tmp_9 -ST_18: sum_pix2_load [2/2] 2.38ns +ST_16: sum_pix2_load [2/2] 2.38ns :2 %sum_pix2_load = load i32* %sum_pix2_addr_2, align 4 -ST_18: sum_pix1_addr_2 [1/1] 0.00ns +ST_16: sum_pix1_addr_2 [1/1] 0.00ns :3 %sum_pix1_addr_2 = getelementptr inbounds [1152 x i32]* %sum_pix1, i64 0, i64 %tmp_9 -ST_18: sum_pix1_load [2/2] 2.38ns +ST_16: sum_pix1_load [2/2] 2.38ns :4 %sum_pix1_load = load i32* %sum_pix1_addr_2, align 4 -ST_18: thresh1_addr_1 [1/1] 0.00ns +ST_16: thresh1_addr_1 [1/1] 0.00ns :14 %thresh1_addr_1 = getelementptr inbounds [1152 x i32]* %thresh1, i64 0, i64 %tmp_9 -ST_18: thresh2_addr_1 [1/1] 0.00ns +ST_16: thresh2_addr_1 [1/1] 0.00ns :17 %thresh2_addr_1 = getelementptr inbounds [1152 x i32]* %thresh2, i64 0, i64 %tmp_9 - : 2.38ns -ST_19: sum_pix2_load [1/2] 2.38ns + : 2.38ns +ST_17: sum_pix2_load [1/2] 2.38ns :2 %sum_pix2_load = load i32* %sum_pix2_addr_2, align 4 -ST_19: sum_pix1_load [1/2] 2.38ns +ST_17: sum_pix1_load [1/2] 2.38ns :4 %sum_pix1_load = load i32* %sum_pix1_addr_2, align 4 -ST_19: tmp_data_V [1/1] 0.00ns +ST_17: tmp_data_V [1/1] 0.00ns :5 %tmp_data_V = call i64 @_ssdm_op_BitConcatenate.i64.i32.i32(i32 %sum_pix2_load, i32 %sum_pix1_load) -ST_19: stg_250 [1/1] 0.00ns +ST_17: stg_248 [1/1] 0.00ns :6 call void @_ssdm_op_Write.axis.volatile.i64P.i8P.i8P.i2P.i1P.i5P.i6P(i64* %out_stream_V_data_V, i8* %out_stream_V_keep_V, i8* %out_stream_V_strb_V, i2* %out_stream_V_user_V, i1* %out_stream_V_last_V, i5* %out_stream_V_id_V, i6* %out_stream_V_dest_V, i64 %tmp_data_V, i8 -1, i8 -1, i2 undef, i1 undef, i5 undef, i6 undef) -ST_19: tmp_10 [1/1] 0.00ns +ST_17: tmp_10 [1/1] 0.00ns :7 %tmp_10 = call i25 @_ssdm_op_PartSelect.i25.i32.i32.i32(i32 %sum_pix1_load, i32 7, i32 31) -ST_19: tmp_11 [1/1] 0.00ns +ST_17: tmp_11 [1/1] 0.00ns :10 %tmp_11 = call i25 @_ssdm_op_PartSelect.i25.i32.i32.i32(i32 %sum_pix2_load, i32 7, i32 31) - : 7.65ns -ST_20: sum_pixP1 [1/1] 0.00ns + : 7.65ns +ST_18: sum_pixP1 [1/1] 0.00ns :8 %sum_pixP1 = call i28 @_ssdm_op_BitConcatenate.i28.i25.i3(i25 %tmp_10, i3 0) -ST_20: sum_pixP1_cast [1/1] 0.00ns +ST_18: sum_pixP1_cast [1/1] 0.00ns :9 %sum_pixP1_cast = zext i28 %sum_pixP1 to i32 -ST_20: sum_pixP2 [1/1] 0.00ns +ST_18: sum_pixP2 [1/1] 0.00ns :11 %sum_pixP2 = call i28 @_ssdm_op_BitConcatenate.i28.i25.i3(i25 %tmp_11, i3 0) -ST_20: sum_pixP2_cast [1/1] 0.00ns +ST_18: sum_pixP2_cast [1/1] 0.00ns :12 %sum_pixP2_cast = zext i28 %sum_pixP2 to i32 -ST_20: tmp_12 [1/1] 7.65ns +ST_18: tmp_12 [1/1] 7.65ns :13 %tmp_12 = mul i32 %sum_pixP1_cast, %tmp_1 -ST_20: tmp_13 [1/1] 7.65ns +ST_18: tmp_13 [1/1] 7.65ns :16 %tmp_13 = mul i32 %sum_pixP2_cast, %tmp_1 - : 2.38ns -ST_21: stg_259 [1/1] 2.38ns + : 2.38ns +ST_19: stg_257 [1/1] 2.38ns :15 store i32 %tmp_12, i32* %thresh1_addr_1, align 4 -ST_21: stg_260 [1/1] 2.38ns +ST_19: stg_258 [1/1] 2.38ns :18 store i32 %tmp_13, i32* %thresh2_addr_1, align 4 -ST_21: tmp_14 [1/1] 2.12ns +ST_19: tmp_14 [1/1] 2.12ns :19 %tmp_14 = icmp ult i32 %tmp_12, %LOW_THRESH_read -ST_21: stg_262 [1/1] 0.00ns +ST_19: stg_260 [1/1] 0.00ns :20 br i1 %tmp_14, label %12, label %._crit_edge86 - : 2.38ns -ST_22: stg_263 [1/1] 2.38ns + : 2.38ns +ST_20: stg_261 [1/1] 2.38ns :0 store i32 %LOW_THRESH_read, i32* %thresh1_addr_1, align 4 -ST_22: stg_264 [1/1] 0.00ns +ST_20: stg_262 [1/1] 0.00ns :1 br label %._crit_edge86 -ST_22: tmp_21 [1/1] 2.12ns +ST_20: tmp_21 [1/1] 2.12ns ._crit_edge86:0 %tmp_21 = icmp ult i32 %tmp_13, %LOW_THRESH_read -ST_22: stg_266 [1/1] 0.00ns +ST_20: stg_264 [1/1] 0.00ns ._crit_edge86:1 br i1 %tmp_21, label %13, label %._crit_edge87 -ST_22: stg_267 [1/1] 2.38ns +ST_20: stg_265 [1/1] 2.38ns :0 store i32 %LOW_THRESH_read, i32* %thresh2_addr_1, align 4 -ST_22: stg_268 [1/1] 0.00ns +ST_20: stg_266 [1/1] 0.00ns :1 br label %._crit_edge87 -ST_22: stg_269 [1/1] 0.00ns +ST_20: stg_267 [1/1] 0.00ns ._crit_edge87:0 br label %.preheader @@ -963,241 +955,241 @@ Port [ trig_pixel]: wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; -stg_23 (specbitsmap ) [ 00000000000000000000000] -stg_24 (specbitsmap ) [ 00000000000000000000000] -stg_25 (specbitsmap ) [ 00000000000000000000000] -stg_26 (specbitsmap ) [ 00000000000000000000000] -stg_27 (specbitsmap ) [ 00000000000000000000000] -stg_28 (specbitsmap ) [ 00000000000000000000000] -stg_29 (specbitsmap ) [ 00000000000000000000000] -stg_30 (specbitsmap ) [ 00000000000000000000000] -stg_31 (specbitsmap ) [ 00000000000000000000000] -stg_32 (specbitsmap ) [ 00000000000000000000000] -stg_33 (specbitsmap ) [ 00000000000000000000000] -stg_34 (specbitsmap ) [ 00000000000000000000000] -stg_35 (specbitsmap ) [ 00000000000000000000000] -stg_36 (specbitsmap ) [ 00000000000000000000000] -stg_37 (specbitsmap ) [ 00000000000000000000000] -stg_38 (specbitsmap ) [ 00000000000000000000000] -stg_39 (specbitsmap ) [ 00000000000000000000000] -stg_40 (specbitsmap ) [ 00000000000000000000000] -stg_41 (specbitsmap ) [ 00000000000000000000000] -stg_42 (spectopmodule ) [ 00000000000000000000000] -LOW_THRESH_read (read ) [ 00111111111111111111111] -N_BG_read (read ) [ 00000000000000000000000] -n_pixels_in_bus_read (read ) [ 00000000000000000000000] -sum_overP1 (alloca ) [ 00111111111111111111111] -sum_overP2 (alloca ) [ 00111111111111111111111] -sum_pix1 (alloca ) [ 00111111111111111111111] -data_shift1 (alloca ) [ 00111111111111111111111] -thresh1 (alloca ) [ 00111111111111111111111] -sum_pix2 (alloca ) [ 00111111111111111111111] -data_shift2 (alloca ) [ 00111111111111111111111] -thresh2 (alloca ) [ 00111111111111111111111] -stg_54 (specinterface ) [ 00000000000000000000000] -stg_55 (specinterface ) [ 00000000000000000000000] -stg_56 (specinterface ) [ 00000000000000000000000] -stg_57 (specinterface ) [ 00000000000000000000000] -stg_58 (specinterface ) [ 00000000000000000000000] -tmp_1 (zext ) [ 00111111111111111111111] -stg_60 (specinterface ) [ 00000000000000000000000] -stg_61 (specinterface ) [ 00000000000000000000000] -stg_62 (specinterface ) [ 00000000000000000000000] -stg_63 (write ) [ 00000000000000000000000] -stg_64 (write ) [ 00000000000000000000000] -tmp_2 (partselect ) [ 00111111111111111111111] -stg_66 (br ) [ 01100000000000000000000] -i (phi ) [ 00100000000000000000000] -empty (speclooptripcount) [ 00000000000000000000000] -exitcond2 (icmp ) [ 00100000000000000000000] -i_5 (add ) [ 01100000000000000000000] -stg_71 (br ) [ 00111000000000000000000] -tmp_4 (zext ) [ 00000000000000000000000] -sum_pix1_addr (getelementptr ) [ 00000000000000000000000] -stg_74 (store ) [ 00000000000000000000000] -sum_pix2_addr (getelementptr ) [ 00000000000000000000000] -stg_76 (store ) [ 00000000000000000000000] -thresh1_addr (getelementptr ) [ 00000000000000000000000] -stg_78 (store ) [ 00000000000000000000000] -thresh2_addr (getelementptr ) [ 00000000000000000000000] -stg_80 (store ) [ 00000000000000000000000] -stg_81 (br ) [ 01100000000000000000000] -kk (phi ) [ 00010000000000000000000] -exitcond1 (icmp ) [ 00011000000000000000000] -empty_7 (speclooptripcount) [ 00000000000000000000000] -kk_2 (add ) [ 00111000000000000000000] -stg_86 (br ) [ 00000000000000000000000] -tmp_6 (bitconcatenate ) [ 00000000000000000000000] -p_shl_cast (zext ) [ 00000000000000000000000] -tmp_s (bitconcatenate ) [ 00000000000000000000000] -p_shl1_cast (zext ) [ 00000000000000000000000] -tmp_3 (add ) [ 00001000000000000000000] -stg_92 (br ) [ 00011000000000000000000] -i_1 (phi ) [ 00001000000000000000000] -empty_8 (speclooptripcount) [ 00000000000000000000000] -exitcond9 (icmp ) [ 00011000000000000000000] -i_6 (add ) [ 00011000000000000000000] -stg_97 (br ) [ 00111000000000000000000] -tmp_8 (add ) [ 00000000000000000000000] -tmp_18_cast (zext ) [ 00000000000000000000000] -data_shift1_addr (getelementptr ) [ 00000000000000000000000] -data_shift2_addr (getelementptr ) [ 00000000000000000000000] -stg_102 (store ) [ 00000000000000000000000] -stg_103 (store ) [ 00000000000000000000000] -stg_104 (br ) [ 00011000000000000000000] -tmp (nbreadreq ) [ 00000111111111111111111] -stg_106 (br ) [ 00000111111111111111111] -stg_107 (ret ) [ 00000000000000000000000] -i_2 (phi ) [ 00000010000000000000000] -empty_9 (speclooptripcount) [ 00000000000000000000000] -exitcond8 (icmp ) [ 00000111111111111111111] -i_7 (add ) [ 00000111111111111111111] -stg_112 (br ) [ 00000111111111111111111] -tmp_7 (zext ) [ 00000000000000000000000] -sum_pix1_addr_1 (getelementptr ) [ 00000000000000000000000] -stg_115 (store ) [ 00000000000000000000000] -sum_pix2_addr_1 (getelementptr ) [ 00000000000000000000000] -stg_117 (store ) [ 00000000000000000000000] -stg_118 (br ) [ 00000111111111111111111] -k (phi ) [ 00000001000000000000000] -itrig (phi ) [ 00000001111111111100000] -exitcond (icmp ) [ 00000111111111111111111] -empty_10 (speclooptripcount) [ 00000000000000000000000] -tmp_5 (add ) [ 00000111111111111111111] -stg_124 (br ) [ 00000111111111111111111] -i_3 (phi ) [ 00000000111100111100000] -itrig_1 (phi ) [ 00000111111111111111111] -empty_11 (speclooptripcount) [ 00000000000000000000000] -exitcond7 (icmp ) [ 00000111111111111111111] -i_9 (add ) [ 00000111111111111111111] -stg_130 (br ) [ 00000111111111111111111] -tmp_15 (zext ) [ 00000000011110000000000] -sum_pix1_addr_3 (getelementptr ) [ 00000000010000000000000] -sum_pix2_addr_3 (getelementptr ) [ 00000000010000000000000] -data_shift1_addr_1 (getelementptr ) [ 00000000001100000000000] -data_shift2_addr_1 (getelementptr ) [ 00000000001100000000000] -empty_12 (read ) [ 00000000000000000000000] -tmp_data_V_2 (extractvalue ) [ 00000000000000000000000] -tmp_16 (trunc ) [ 00000000001100000000000] -phitmp (partselect ) [ 00000000001100000000000] -tmp_17 (sext ) [ 00000000001110000000000] -sum_pix1_load_1 (load ) [ 00000000000000000000000] -tmp_18 (add ) [ 00000000000000000000000] -stg_145 (store ) [ 00000000000000000000000] -tmp_19 (sext ) [ 00000000001110000000000] -sum_pix2_load_1 (load ) [ 00000000000000000000000] -tmp_20 (add ) [ 00000000000000000000000] -stg_149 (store ) [ 00000000000000000000000] -sum_overP1_addr (getelementptr ) [ 00000000001110000000000] -stg_151 (store ) [ 00000000000000000000000] -sum_overP2_addr (getelementptr ) [ 00000000001110000000000] -stg_153 (store ) [ 00000000000000000000000] -stg_154 (br ) [ 00000111111111111111111] -kk_1 (phi ) [ 00000000001100000000000] -tmp_22 (bitselect ) [ 00000111111111111111111] -empty_13 (speclooptripcount) [ 00000000000000000000000] -stg_158 (br ) [ 00000000000000000000000] -tmp_26 (bitconcatenate ) [ 00000000000000000000000] -p_shl4_cast (sext ) [ 00000000000000000000000] -tmp_28 (bitconcatenate ) [ 00000000000000000000000] -p_shl5_cast (sext ) [ 00000000000000000000000] -tmp_31 (add ) [ 00000000000000000000000] -tmp_32 (add ) [ 00000000000000000000000] -tmp_45_cast (zext ) [ 00000000000000000000000] -data_shift1_addr_2 (getelementptr ) [ 00000000000100000000000] -data_shift2_addr_2 (getelementptr ) [ 00000000000100000000000] -tmp_19_cast (sext ) [ 00000000000000000000000] -stg_173 (store ) [ 00000000000000000000000] -tmp_21_cast (sext ) [ 00000000000000000000000] -stg_175 (store ) [ 00000000000000000000000] -thresh1_addr_2 (getelementptr ) [ 00000000000010000000000] -data_shift1_load (load ) [ 00000000000000000000000] -extLd (sext ) [ 00000000000000000000000] -tmp_27 (add ) [ 00000000000000000000000] -tmp_33 (bitconcatenate ) [ 00000000000000000000000] -p_shl2_cast (zext ) [ 00000000000000000000000] -tmp_40 (bitconcatenate ) [ 00000000000000000000000] -p_shl3_cast (zext ) [ 00000000000000000000000] -tmp_41 (add ) [ 00000000000000000000000] -tmp_42 (add ) [ 00000000000000000000000] -tmp_49_cast (zext ) [ 00000000000000000000000] -data_shift1_addr_3 (getelementptr ) [ 00000000000000000000000] -data_shift2_addr_3 (getelementptr ) [ 00000000000000000000000] -stg_192 (store ) [ 00000000000000000000000] -data_shift2_load (load ) [ 00000000000000000000000] -extLd1 (sext ) [ 00000000000000000000000] -stg_195 (store ) [ 00000000000000000000000] -sum_overP1_load (load ) [ 00000000000000000000000] -tmp_29 (add ) [ 00000000000000000000000] -stg_198 (store ) [ 00000000000000000000000] -sum_overP2_load (load ) [ 00000000000000000000000] -tmp_30 (add ) [ 00000000000000000000000] -stg_201 (store ) [ 00000000000000000000000] -kk_3 (add ) [ 00000111111111111111111] -stg_203 (br ) [ 00000111111111111111111] -sum_overP1_load_1 (load ) [ 00000000000000000000000] -tmp_23 (add ) [ 00000000000000000000000] -stg_206 (store ) [ 00000000000000000000000] -sum_overP2_load_1 (load ) [ 00000000000000000000000] -tmp_24 (add ) [ 00000000000001000000000] -stg_209 (store ) [ 00000000000000000000000] -thresh1_load (load ) [ 00000000000000000000000] -tmp_25 (icmp ) [ 00000111111111111111111] -stg_212 (br ) [ 00000000000000000000000] -thresh2_addr_2 (getelementptr ) [ 00000000000001000000000] -tmp_36 (icmp ) [ 00000000000001000000000] -tmp_34 (icmp ) [ 00000111111111111111111] -stg_217 (br ) [ 00000111111111111111111] -stg_218 (write ) [ 00000000000000000000000] -thresh2_load (load ) [ 00000000000000000000000] -tmp_35 (icmp ) [ 00000000000000000000000] -or_cond (and ) [ 00000111111111111111111] -stg_222 (br ) [ 00000111111111111111111] -stg_223 (write ) [ 00000000000000000000000] -stg_224 (write ) [ 00000000000000000000000] -tmp_38 (bitconcatenate ) [ 00000000000000000000000] -tmp_39 (or ) [ 00000000000000000000000] -tmp_40_cast (zext ) [ 00000000000000000000000] -stg_228 (write ) [ 00000000000000000000000] -stg_229 (br ) [ 00000111111111111111111] -stg_230 (write ) [ 00000000000000000000000] -tmp_37 (bitconcatenate ) [ 00000000000000000000000] -tmp_38_cast (zext ) [ 00000000000000000000000] -stg_233 (write ) [ 00000000000000000000000] -stg_234 (br ) [ 00000111111111111111111] -i_4 (phi ) [ 00000000000000000010000] -empty_14 (speclooptripcount) [ 00000000000000000000000] -exitcond6 (icmp ) [ 00000111111111111111111] -i_8 (add ) [ 00000111111111111111111] -stg_239 (br ) [ 00000000000000000000000] -tmp_9 (zext ) [ 00000000000000000000000] -sum_pix2_addr_2 (getelementptr ) [ 00000000000000000001000] -sum_pix1_addr_2 (getelementptr ) [ 00000000000000000001000] -thresh1_addr_1 (getelementptr ) [ 00000000000000000001111] -thresh2_addr_1 (getelementptr ) [ 00000000000000000001111] -sum_pix2_load (load ) [ 00000000000000000000000] -sum_pix1_load (load ) [ 00000000000000000000000] -tmp_data_V (bitconcatenate ) [ 00000000000000000000000] -stg_250 (write ) [ 00000000000000000000000] -tmp_10 (partselect ) [ 00000000000000000000100] -tmp_11 (partselect ) [ 00000000000000000000100] -sum_pixP1 (bitconcatenate ) [ 00000000000000000000000] -sum_pixP1_cast (zext ) [ 00000000000000000000000] -sum_pixP2 (bitconcatenate ) [ 00000000000000000000000] -sum_pixP2_cast (zext ) [ 00000000000000000000000] -tmp_12 (mul ) [ 00000000000000000000010] -tmp_13 (mul ) [ 00000000000000000000011] -stg_259 (store ) [ 00000000000000000000000] -stg_260 (store ) [ 00000000000000000000000] -tmp_14 (icmp ) [ 00000000000000000000001] -stg_262 (br ) [ 00000000000000000000000] -stg_263 (store ) [ 00000000000000000000000] -stg_264 (br ) [ 00000000000000000000000] -tmp_21 (icmp ) [ 00000111111111111111111] -stg_266 (br ) [ 00000000000000000000000] -stg_267 (store ) [ 00000000000000000000000] -stg_268 (br ) [ 00000000000000000000000] -stg_269 (br ) [ 00000111111111111111111] +stg_21 (specbitsmap ) [ 000000000000000000000] +stg_22 (specbitsmap ) [ 000000000000000000000] +stg_23 (specbitsmap ) [ 000000000000000000000] +stg_24 (specbitsmap ) [ 000000000000000000000] +stg_25 (specbitsmap ) [ 000000000000000000000] +stg_26 (specbitsmap ) [ 000000000000000000000] +stg_27 (specbitsmap ) [ 000000000000000000000] +stg_28 (specbitsmap ) [ 000000000000000000000] +stg_29 (specbitsmap ) [ 000000000000000000000] +stg_30 (specbitsmap ) [ 000000000000000000000] +stg_31 (specbitsmap ) [ 000000000000000000000] +stg_32 (specbitsmap ) [ 000000000000000000000] +stg_33 (specbitsmap ) [ 000000000000000000000] +stg_34 (specbitsmap ) [ 000000000000000000000] +stg_35 (specbitsmap ) [ 000000000000000000000] +stg_36 (specbitsmap ) [ 000000000000000000000] +stg_37 (specbitsmap ) [ 000000000000000000000] +stg_38 (specbitsmap ) [ 000000000000000000000] +stg_39 (specbitsmap ) [ 000000000000000000000] +stg_40 (spectopmodule ) [ 000000000000000000000] +LOW_THRESH_read (read ) [ 001111111111111111111] +N_BG_read (read ) [ 000000000000000000000] +n_pixels_in_bus_read (read ) [ 000000000000000000000] +sum_overP1 (alloca ) [ 001111111111111111111] +sum_overP2 (alloca ) [ 001111111111111111111] +sum_pix1 (alloca ) [ 001111111111111111111] +data_shift1 (alloca ) [ 001111111111111111111] +thresh1 (alloca ) [ 001111111111111111111] +sum_pix2 (alloca ) [ 001111111111111111111] +data_shift2 (alloca ) [ 001111111111111111111] +thresh2 (alloca ) [ 001111111111111111111] +stg_52 (specinterface ) [ 000000000000000000000] +stg_53 (specinterface ) [ 000000000000000000000] +stg_54 (specinterface ) [ 000000000000000000000] +stg_55 (specinterface ) [ 000000000000000000000] +stg_56 (specinterface ) [ 000000000000000000000] +tmp_1 (zext ) [ 001111111111111111111] +stg_58 (specinterface ) [ 000000000000000000000] +stg_59 (specinterface ) [ 000000000000000000000] +stg_60 (specinterface ) [ 000000000000000000000] +stg_61 (write ) [ 000000000000000000000] +stg_62 (write ) [ 000000000000000000000] +tmp_2 (partselect ) [ 001111111111111111111] +stg_64 (br ) [ 011000000000000000000] +i (phi ) [ 001000000000000000000] +empty (speclooptripcount) [ 000000000000000000000] +exitcond2 (icmp ) [ 001000000000000000000] +i_5 (add ) [ 011000000000000000000] +stg_69 (br ) [ 001110000000000000000] +tmp_4 (zext ) [ 000000000000000000000] +sum_pix1_addr (getelementptr ) [ 000000000000000000000] +stg_72 (store ) [ 000000000000000000000] +sum_pix2_addr (getelementptr ) [ 000000000000000000000] +stg_74 (store ) [ 000000000000000000000] +thresh1_addr (getelementptr ) [ 000000000000000000000] +stg_76 (store ) [ 000000000000000000000] +thresh2_addr (getelementptr ) [ 000000000000000000000] +stg_78 (store ) [ 000000000000000000000] +stg_79 (br ) [ 011000000000000000000] +kk (phi ) [ 000100000000000000000] +exitcond1 (icmp ) [ 000110000000000000000] +empty_7 (speclooptripcount) [ 000000000000000000000] +kk_2 (add ) [ 001110000000000000000] +stg_84 (br ) [ 000000000000000000000] +tmp_6 (bitconcatenate ) [ 000000000000000000000] +p_shl_cast (zext ) [ 000000000000000000000] +tmp_s (bitconcatenate ) [ 000000000000000000000] +p_shl1_cast (zext ) [ 000000000000000000000] +tmp_3 (add ) [ 000010000000000000000] +stg_90 (br ) [ 000110000000000000000] +i_1 (phi ) [ 000010000000000000000] +empty_8 (speclooptripcount) [ 000000000000000000000] +exitcond9 (icmp ) [ 000110000000000000000] +i_6 (add ) [ 000110000000000000000] +stg_95 (br ) [ 001110000000000000000] +tmp_8 (add ) [ 000000000000000000000] +tmp_18_cast (zext ) [ 000000000000000000000] +data_shift1_addr (getelementptr ) [ 000000000000000000000] +data_shift2_addr (getelementptr ) [ 000000000000000000000] +stg_100 (store ) [ 000000000000000000000] +stg_101 (store ) [ 000000000000000000000] +stg_102 (br ) [ 000110000000000000000] +tmp (nbreadreq ) [ 000001111111111111111] +stg_104 (br ) [ 000001111111111111111] +stg_105 (ret ) [ 000000000000000000000] +i_2 (phi ) [ 000000100000000000000] +empty_9 (speclooptripcount) [ 000000000000000000000] +exitcond8 (icmp ) [ 000001111111111111111] +i_7 (add ) [ 000001111111111111111] +stg_110 (br ) [ 000001111111111111111] +tmp_7 (zext ) [ 000000000000000000000] +sum_pix1_addr_1 (getelementptr ) [ 000000000000000000000] +stg_113 (store ) [ 000000000000000000000] +sum_pix2_addr_1 (getelementptr ) [ 000000000000000000000] +stg_115 (store ) [ 000000000000000000000] +stg_116 (br ) [ 000001111111111111111] +k (phi ) [ 000000010000000000000] +itrig (phi ) [ 000000011111111100000] +exitcond (icmp ) [ 000001111111111111111] +empty_10 (speclooptripcount) [ 000000000000000000000] +tmp_5 (add ) [ 000001111111111111111] +stg_122 (br ) [ 000001111111111111111] +i_3 (phi ) [ 000000001111010100000] +itrig_1 (phi ) [ 000001111111111111111] +empty_11 (speclooptripcount) [ 000000000000000000000] +exitcond7 (icmp ) [ 000001111111111111111] +i_9 (add ) [ 000001111111111111111] +stg_128 (br ) [ 000001111111111111111] +tmp_15 (zext ) [ 000000000111100000000] +sum_pix1_addr_3 (getelementptr ) [ 000000000100000000000] +sum_pix2_addr_3 (getelementptr ) [ 000000000100000000000] +data_shift1_addr_1 (getelementptr ) [ 000000000011000000000] +data_shift2_addr_1 (getelementptr ) [ 000000000011000000000] +empty_12 (read ) [ 000000000000000000000] +tmp_data_V_2 (extractvalue ) [ 000000000000000000000] +tmp_16 (trunc ) [ 000000000011000000000] +phitmp (partselect ) [ 000000000011000000000] +tmp_17 (sext ) [ 000000000011100000000] +sum_pix1_load_1 (load ) [ 000000000000000000000] +tmp_18 (add ) [ 000000000000000000000] +stg_143 (store ) [ 000000000000000000000] +tmp_19 (sext ) [ 000000000011100000000] +sum_pix2_load_1 (load ) [ 000000000000000000000] +tmp_20 (add ) [ 000000000000000000000] +stg_147 (store ) [ 000000000000000000000] +sum_overP1_addr (getelementptr ) [ 000000000011100000000] +stg_149 (store ) [ 000000000000000000000] +sum_overP2_addr (getelementptr ) [ 000000000011100000000] +stg_151 (store ) [ 000000000000000000000] +stg_152 (br ) [ 000001111111111111111] +kk_1 (phi ) [ 000000000011000000000] +tmp_22 (bitselect ) [ 000001111111111111111] +empty_13 (speclooptripcount) [ 000000000000000000000] +stg_156 (br ) [ 000000000000000000000] +tmp_26 (bitconcatenate ) [ 000000000000000000000] +p_shl4_cast (sext ) [ 000000000000000000000] +tmp_28 (bitconcatenate ) [ 000000000000000000000] +p_shl5_cast (sext ) [ 000000000000000000000] +tmp_31 (add ) [ 000000000000000000000] +tmp_32 (add ) [ 000000000000000000000] +tmp_45_cast (zext ) [ 000000000000000000000] +data_shift1_addr_2 (getelementptr ) [ 000000000001000000000] +data_shift2_addr_2 (getelementptr ) [ 000000000001000000000] +tmp_19_cast (sext ) [ 000000000000000000000] +stg_171 (store ) [ 000000000000000000000] +tmp_21_cast (sext ) [ 000000000000000000000] +stg_173 (store ) [ 000000000000000000000] +thresh1_addr_2 (getelementptr ) [ 000000000000100000000] +data_shift1_load (load ) [ 000000000000000000000] +extLd (sext ) [ 000000000000000000000] +tmp_27 (add ) [ 000000000000000000000] +tmp_33 (bitconcatenate ) [ 000000000000000000000] +p_shl2_cast (zext ) [ 000000000000000000000] +tmp_40 (bitconcatenate ) [ 000000000000000000000] +p_shl3_cast (zext ) [ 000000000000000000000] +tmp_41 (add ) [ 000000000000000000000] +tmp_42 (add ) [ 000000000000000000000] +tmp_49_cast (zext ) [ 000000000000000000000] +data_shift1_addr_3 (getelementptr ) [ 000000000000000000000] +data_shift2_addr_3 (getelementptr ) [ 000000000000000000000] +stg_190 (store ) [ 000000000000000000000] +data_shift2_load (load ) [ 000000000000000000000] +extLd1 (sext ) [ 000000000000000000000] +stg_193 (store ) [ 000000000000000000000] +sum_overP1_load (load ) [ 000000000000000000000] +tmp_29 (add ) [ 000000000000000000000] +stg_196 (store ) [ 000000000000000000000] +sum_overP2_load (load ) [ 000000000000000000000] +tmp_30 (add ) [ 000000000000000000000] +stg_199 (store ) [ 000000000000000000000] +kk_3 (add ) [ 000001111111111111111] +stg_201 (br ) [ 000001111111111111111] +sum_overP1_load_1 (load ) [ 000000000000000000000] +tmp_23 (add ) [ 000000000000000000000] +stg_204 (store ) [ 000000000000000000000] +sum_overP2_load_1 (load ) [ 000000000000000000000] +tmp_24 (add ) [ 000000000000010000000] +stg_207 (store ) [ 000000000000000000000] +thresh1_load (load ) [ 000000000000000000000] +tmp_25 (icmp ) [ 000001111111111111111] +stg_210 (br ) [ 000000000000000000000] +thresh2_addr_2 (getelementptr ) [ 000000000000010000000] +tmp_36 (icmp ) [ 000000000000010000000] +tmp_34 (icmp ) [ 000001111111111111111] +stg_215 (br ) [ 000001111111111111111] +stg_216 (write ) [ 000000000000000000000] +thresh2_load (load ) [ 000000000000000000000] +tmp_35 (icmp ) [ 000000000000000000000] +or_cond (and ) [ 000001111111111111111] +stg_220 (br ) [ 000001111111111111111] +stg_221 (write ) [ 000000000000000000000] +tmp_38 (bitconcatenate ) [ 000000000000000000000] +tmp_39 (or ) [ 000000000000000000000] +tmp_40_cast (zext ) [ 000000000000000000000] +stg_225 (write ) [ 000000000000000000000] +stg_226 (write ) [ 000000000000000000000] +stg_227 (br ) [ 000001111111111111111] +stg_228 (write ) [ 000000000000000000000] +tmp_37 (bitconcatenate ) [ 000000000000000000000] +tmp_38_cast (zext ) [ 000000000000000000000] +stg_231 (write ) [ 000000000000000000000] +stg_232 (br ) [ 000001111111111111111] +i_4 (phi ) [ 000000000000000010000] +empty_14 (speclooptripcount) [ 000000000000000000000] +exitcond6 (icmp ) [ 000001111111111111111] +i_8 (add ) [ 000001111111111111111] +stg_237 (br ) [ 000000000000000000000] +tmp_9 (zext ) [ 000000000000000000000] +sum_pix2_addr_2 (getelementptr ) [ 000000000000000001000] +sum_pix1_addr_2 (getelementptr ) [ 000000000000000001000] +thresh1_addr_1 (getelementptr ) [ 000000000000000001111] +thresh2_addr_1 (getelementptr ) [ 000000000000000001111] +sum_pix2_load (load ) [ 000000000000000000000] +sum_pix1_load (load ) [ 000000000000000000000] +tmp_data_V (bitconcatenate ) [ 000000000000000000000] +stg_248 (write ) [ 000000000000000000000] +tmp_10 (partselect ) [ 000000000000000000100] +tmp_11 (partselect ) [ 000000000000000000100] +sum_pixP1 (bitconcatenate ) [ 000000000000000000000] +sum_pixP1_cast (zext ) [ 000000000000000000000] +sum_pixP2 (bitconcatenate ) [ 000000000000000000000] +sum_pixP2_cast (zext ) [ 000000000000000000000] +tmp_12 (mul ) [ 000000000000000000010] +tmp_13 (mul ) [ 000000000000000000011] +stg_257 (store ) [ 000000000000000000000] +stg_258 (store ) [ 000000000000000000000] +tmp_14 (icmp ) [ 000000000000000000001] +stg_260 (br ) [ 000000000000000000000] +stg_261 (store ) [ 000000000000000000000] +stg_262 (br ) [ 000000000000000000000] +tmp_21 (icmp ) [ 000001111111111111111] +stg_264 (br ) [ 000000000000000000000] +stg_265 (store ) [ 000000000000000000000] +stg_266 (br ) [ 000000000000000000000] +stg_267 (br ) [ 000001111111111111111] @@ -2051,25 +2043,25 @@ stg_269 (br ) [ 00000111111111111111111] - + - + - + - + - + @@ -2110,7 +2102,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2131,7 +2123,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2156,7 +2148,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2181,7 +2173,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2206,7 +2198,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2231,7 +2223,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2269,7 +2261,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2281,7 +2273,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2384,7 +2376,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2409,7 +2401,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2500,7 +2492,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2513,7 +2505,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2526,7 +2518,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2539,7 +2531,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2791,7 +2783,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3508,13 +3500,13 @@ stg_269 (br ) [ 00000111111111111111111] - + - + @@ -3526,7 +3518,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3537,20 +3529,20 @@ stg_269 (br ) [ 00000111111111111111111] - + - + - + @@ -3561,7 +3553,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3573,7 +3565,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3585,7 +3577,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3596,7 +3588,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3609,7 +3601,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3623,7 +3615,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3637,7 +3629,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3650,7 +3642,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3661,7 +3653,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3674,7 +3666,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3685,7 +3677,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3697,7 +3689,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3709,7 +3701,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3721,7 +3713,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3733,7 +3725,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -4644,7 +4636,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -4654,7 +4646,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -4905,15 +4897,15 @@ stg_269 (br ) [ 00000111111111111111111] * FSMD analyzer results: - Output states: - Port: out_stream_V_data_V | {19 } - Port: out_stream_V_keep_V | {19 } - Port: out_stream_V_strb_V | {19 } - Port: out_stream_V_user_V | {19 } - Port: out_stream_V_last_V | {19 } - Port: out_stream_V_id_V | {19 } - Port: out_stream_V_dest_V | {19 } - Port: trig_data | {1 12 13 14 15 16 17 } - Port: trig_pixel | {1 } + Port: out_stream_V_data_V | {17 } + Port: out_stream_V_keep_V | {17 } + Port: out_stream_V_strb_V | {17 } + Port: out_stream_V_user_V | {17 } + Port: out_stream_V_last_V | {17 } + Port: out_stream_V_id_V | {17 } + Port: out_stream_V_dest_V | {17 } + Port: trig_data | {1 12 13 14 15 } + Port: trig_pixel | {1 13 15 } - Input state : Port: l2_trigger : in_stream_V_data_V | {5 9 } Port: l2_trigger : in_stream_V_keep_V | {5 9 } @@ -4930,20 +4922,20 @@ stg_269 (br ) [ 00000111111111111111111] State 2 exitcond2 : 1 i_5 : 1 - stg_71 : 2 + stg_69 : 2 tmp_4 : 1 sum_pix1_addr : 2 - stg_74 : 3 + stg_72 : 3 sum_pix2_addr : 2 - stg_76 : 3 + stg_74 : 3 thresh1_addr : 2 - stg_78 : 3 + stg_76 : 3 thresh2_addr : 2 - stg_80 : 3 + stg_78 : 3 State 3 exitcond1 : 1 kk_2 : 1 - stg_86 : 2 + stg_84 : 2 tmp_6 : 1 p_shl_cast : 2 tmp_s : 1 @@ -4952,31 +4944,31 @@ stg_269 (br ) [ 00000111111111111111111] State 4 exitcond9 : 1 i_6 : 1 - stg_97 : 2 + stg_95 : 2 tmp_8 : 1 tmp_18_cast : 2 data_shift1_addr : 3 data_shift2_addr : 3 - stg_102 : 4 - stg_103 : 4 + stg_100 : 4 + stg_101 : 4 State 5 State 6 exitcond8 : 1 i_7 : 1 - stg_112 : 2 + stg_110 : 2 tmp_7 : 1 sum_pix1_addr_1 : 2 - stg_115 : 3 + stg_113 : 3 sum_pix2_addr_1 : 2 - stg_117 : 3 + stg_115 : 3 State 7 exitcond : 1 tmp_5 : 1 - stg_124 : 2 + stg_122 : 2 State 8 exitcond7 : 1 i_9 : 1 - stg_130 : 2 + stg_128 : 2 tmp_15 : 1 sum_pix1_addr_3 : 2 sum_pix1_load_1 : 3 @@ -4987,15 +4979,15 @@ stg_269 (br ) [ 00000111111111111111111] phitmp : 1 tmp_17 : 2 tmp_18 : 3 - stg_145 : 4 + stg_143 : 4 tmp_19 : 2 tmp_20 : 3 - stg_149 : 4 + stg_147 : 4 + stg_149 : 1 stg_151 : 1 - stg_153 : 1 State 10 tmp_22 : 1 - stg_158 : 2 + stg_156 : 2 tmp_26 : 1 p_shl4_cast : 2 tmp_28 : 1 @@ -5007,8 +4999,8 @@ stg_269 (br ) [ 00000111111111111111111] data_shift2_addr_2 : 6 data_shift1_load : 7 data_shift2_load : 7 + stg_171 : 1 stg_173 : 1 - stg_175 : 1 thresh1_load : 1 State 11 extLd : 1 @@ -5021,39 +5013,37 @@ stg_269 (br ) [ 00000111111111111111111] tmp_49_cast : 5 data_shift1_addr_3 : 6 data_shift2_addr_3 : 6 - stg_192 : 7 + stg_190 : 7 extLd1 : 1 - stg_195 : 7 + stg_193 : 7 tmp_29 : 2 - stg_198 : 3 + stg_196 : 3 tmp_30 : 2 - stg_201 : 3 + stg_199 : 3 State 12 tmp_23 : 1 - stg_206 : 2 + stg_204 : 2 tmp_24 : 1 - stg_209 : 2 + stg_207 : 2 tmp_25 : 2 - stg_212 : 3 + stg_210 : 3 thresh2_load : 1 - stg_217 : 1 + stg_215 : 1 State 13 tmp_35 : 1 or_cond : 2 - stg_222 : 2 - State 14 - State 15 + stg_220 : 2 tmp_39 : 1 tmp_40_cast : 1 - stg_228 : 2 - State 16 - State 17 + stg_225 : 2 + State 14 + State 15 tmp_38_cast : 1 - stg_233 : 2 - State 18 + stg_231 : 2 + State 16 exitcond6 : 1 i_8 : 1 - stg_239 : 2 + stg_237 : 2 tmp_9 : 1 sum_pix2_addr_2 : 2 sum_pix2_load : 3 @@ -5061,20 +5051,20 @@ stg_269 (br ) [ 00000111111111111111111] sum_pix1_load : 3 thresh1_addr_1 : 2 thresh2_addr_1 : 2 - State 19 + State 17 tmp_data_V : 1 - stg_250 : 2 + stg_248 : 2 tmp_10 : 1 tmp_11 : 1 - State 20 + State 18 sum_pixP1_cast : 1 sum_pixP2_cast : 1 tmp_12 : 2 tmp_13 : 2 - State 21 - stg_262 : 1 - State 22 - stg_266 : 1 + State 19 + stg_260 : 1 + State 20 + stg_264 : 1 ============================================================ @@ -5131,8 +5121,8 @@ stg_269 (br ) [ 00000111111111111111111] | | empty_12_read_fu_246 | 0 | 0 | 0 | |----------|----------------------------------|---------|---------|---------| | | grp_write_fu_210 | 0 | 0 | 0 | -| write | stg_64_write_fu_218 | 0 | 0 | 0 | -| | stg_250_write_fu_265 | 0 | 0 | 0 | +| write | grp_write_fu_218 | 0 | 0 | 0 | +| | stg_248_write_fu_265 | 0 | 0 | 0 | |----------|----------------------------------|---------|---------|---------| | nbreadreq| tmp_nbreadreq_fu_226 | 0 | 0 | 0 | |----------|----------------------------------|---------|---------|---------| @@ -5266,7 +5256,8 @@ Memories: |-------------------|------|------|------|--------||---------||---------| | Comp | Pin | Size | BW | S x BW || Delay || LUT | |-------------------|------|------|------|--------||---------||---------| -| grp_write_fu_210 | p2 | 4 | 16 | 64 || 16 | +| grp_write_fu_210 | p2 | 2 | 1 | 2 | +| grp_write_fu_218 | p2 | 3 | 16 | 48 || 16 | | grp_access_fu_302 | p0 | 6 | 11 | 66 || 11 | | grp_access_fu_302 | p1 | 2 | 32 | 64 || 32 | | grp_access_fu_314 | p0 | 6 | 11 | 66 || 11 | @@ -5288,7 +5279,7 @@ Memories: | itrig_1_reg_587 | p0 | 2 | 32 | 64 || 32 | | kk_1_reg_610 | p0 | 2 | 4 | 8 || 4 | |-------------------|------|------|------|--------||---------||---------| -| Total | | | | 1248 || 28.763 || 419 | +| Total | | | | 1234 || 30.074 || 419 | |-------------------|------|------|------|--------||---------||---------| @@ -5299,8 +5290,8 @@ Memories: +-----------+--------+--------+--------+--------+--------+ | Function | - | 4 | - | 0 | 429 | | Memory | 58 | - | - | 0 | 0 | -|Multiplexer| - | - | 28 | - | 419 | +|Multiplexer| - | - | 30 | - | 419 | | Register | - | - | - | 814 | - | +-----------+--------+--------+--------+--------+--------+ -| Total | 58 | 4 | 28 | 814 | 848 | +| Total | 58 | 4 | 30 | 814 | 848 | +-----------+--------+--------+--------+--------+--------+ diff --git a/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.bind.rpt.xml b/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.bind.rpt.xml index aad8493..c5aa099 100644 --- a/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.bind.rpt.xml +++ b/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.bind.rpt.xml @@ -1,7 +1,7 @@
-Fri Apr 13 19:40:42 2018 +Wed Apr 18 11:09:40 2018 2016.2 (Build 1577090 on Thu Jun 02 16:59:10 MDT 2016) l2_trigger @@ -38,10 +38,10 @@ 0, 32767, 1, -, -, 0 ~ 32767, no 16, 262152, 2 ~ 32769, -, -, 8, no 0, 32767, 1, -, -, 0 ~ 32767, no -?, ?, 260 ~ 88274558, -, -, ?, no +?, ?, 260 ~ 84080382, -, -, ?, no 0, 32767, 1, -, -, 0 ~ 32767, no -256, 88077952, 2 ~ 688109, -, -, 128, no -0, 688107, 18 ~ 21, -, -, 0 ~ 32767, no +256, 83883776, 2 ~ 655342, -, -, 128, no +0, 655340, 18 ~ 20, -, -, 0 ~ 32767, no 14, 14, 2, -, -, 7, no 0, 163835, 5, -, -, 0 ~ 32767, no
diff --git a/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.rpt b/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.rpt index 238304f..49988e7 100644 --- a/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.rpt +++ b/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.rpt @@ -3,7 +3,7 @@ ================================================================ == Vivado HLS Report for 'l2_trigger' ================================================================ -* Date: Fri Apr 13 19:40:42 2018 +* Date: Wed Apr 18 11:09:40 2018 * Version: 2016.2 (Build 1577090 on Thu Jun 02 16:59:10 MDT 2016) * Project: l2_trigger @@ -44,10 +44,10 @@ |- Loop 1 | 0| 32767| 1| -| -| 0 ~ 32767 | no | |- Loop 2 | 16| 262152| 2 ~ 32769 | -| -| 8| no | | + Loop 2.1 | 0| 32767| 1| -| -| 0 ~ 32767 | no | - |- Loop 3 | ?| ?| 260 ~ 88274558 | -| -| ?| no | + |- Loop 3 | ?| ?| 260 ~ 84080382 | -| -| ?| no | | + Loop 3.1 | 0| 32767| 1| -| -| 0 ~ 32767 | no | - | + Loop 3.2 | 256| 88077952| 2 ~ 688109 | -| -| 128| no | - | ++ Loop 3.2.1 | 0| 688107| 18 ~ 21 | -| -| 0 ~ 32767 | no | + | + Loop 3.2 | 256| 83883776| 2 ~ 655342 | -| -| 128| no | + | ++ Loop 3.2.1 | 0| 655340| 18 ~ 20 | -| -| 0 ~ 32767 | no | | +++ Loop 3.2.1.1 | 14| 14| 2| -| -| 7| no | | + Loop 3.3 | 0| 163835| 5| -| -| 0 ~ 32767 | no | +---------------------+-----+----------+----------------+-----------+-----------+-----------+----------+ @@ -66,10 +66,10 @@ |FIFO | -| -| -| -| |Instance | 0| -| 110| 152| |Memory | 58| -| 0| 0| -|Multiplexer | -| -| -| 528| -|Register | -| -| 636| -| +|Multiplexer | -| -| -| 560| +|Register | -| -| 634| -| +-----------------+---------+-------+--------+-------+ -|Total | 58| 4| 746| 1141| +|Total | 58| 4| 744| 1173| +-----------------+---------+-------+--------+-------+ |Available | 530| 400| 157200| 78600| +-----------------+---------+-------+--------+-------+ @@ -158,7 +158,7 @@ +----------------------------------+----+-----------+-----+-----------+ | Name | LUT| Input Size| Bits| Total Bits| +----------------------------------+----+-----------+-----+-----------+ - |ap_NS_fsm | 18| 23| 1| 23| + |ap_NS_fsm | 18| 21| 1| 21| |ap_sig_ioackin_out_stream_TREADY | 1| 2| 1| 2| |data_shift1_address0 | 14| 5| 14| 70| |data_shift1_d0 | 17| 4| 17| 68| @@ -188,9 +188,10 @@ |thresh1_d0 | 32| 4| 32| 128| |thresh2_address0 | 11| 4| 11| 44| |thresh2_d0 | 32| 4| 32| 128| - |trig_data | 32| 5| 32| 160| + |trig_data | 32| 3| 32| 96| + |trig_pixel | 32| 4| 32| 128| +----------------------------------+----+-----------+-----+-----------+ - |Total | 528| 121| 511| 1797| + |Total | 560| 121| 543| 1859| +----------------------------------+----+-----------+-----+-----------+ * Register: @@ -198,7 +199,7 @@ | Name | FF | LUT| Bits| Const Bits| +----------------------------------+----+----+-----+-----------+ |LOW_THRESH_read_reg_1104 | 32| 0| 32| 0| - |ap_CS_fsm | 22| 0| 22| 0| + |ap_CS_fsm | 20| 0| 20| 0| |ap_reg_ioackin_out_stream_TREADY | 1| 0| 1| 0| |data_shift1_addr_1_reg_1206 | 14| 0| 14| 0| |data_shift2_addr_1_reg_1211 | 14| 0| 14| 0| @@ -238,7 +239,7 @@ |tmp_3_reg_1143 | 8| 0| 15| 7| |tmp_5_reg_1170 | 8| 0| 8| 0| +----------------------------------+----+----+-----+-----------+ - |Total | 636| 0| 716| 80| + |Total | 634| 0| 714| 80| +----------------------------------+----+----+-----+-----------+ @@ -320,7 +321,7 @@ IsGatedGlobalClock: 0 ============================================================ + Verbose Summary: Schedule ============================================================ -* Number of FSM states: 22 +* Number of FSM states: 20 * Pipeline: 0 * Dataflow Pipeline: 0 @@ -343,7 +344,7 @@ IsGatedGlobalClock: 0 6 / (!exitcond8) 7 --> 8 / (!exitcond) - 18 / (exitcond) + 16 / (exitcond) 8 --> 7 / (exitcond7) 9 / (!exitcond7) @@ -357,90 +358,86 @@ IsGatedGlobalClock: 0 12 --> 13 / (!tmp_25) 8 / (tmp_25 & !tmp_34) - 16 / (tmp_25 & tmp_34) + 15 / (tmp_25 & tmp_34) 13 --> 8 / (!or_cond) 14 / (or_cond) 14 --> - 15 / true + 8 / true 15 --> 8 / true 16 --> - 17 / true + 5 / (exitcond6) + 17 / (!exitcond6) 17 --> - 8 / true + 18 / true 18 --> - 5 / (exitcond6) - 19 / (!exitcond6) + 19 / true 19 --> 20 / true 20 --> - 21 / true -21 --> - 22 / true -22 --> - 18 / true + 16 / true * FSM state operations: : 2.38ns -ST_1: stg_23 [1/1] 0.00ns +ST_1: stg_21 [1/1] 0.00ns arrayctor.loop1.preheader:0 call void (...)* @_ssdm_op_SpecBitsMap(i32* %in_stream_V_data_V), !map !102 -ST_1: stg_24 [1/1] 0.00ns +ST_1: stg_22 [1/1] 0.00ns arrayctor.loop1.preheader:1 call void (...)* @_ssdm_op_SpecBitsMap(i4* %in_stream_V_keep_V), !map !106 -ST_1: stg_25 [1/1] 0.00ns +ST_1: stg_23 [1/1] 0.00ns arrayctor.loop1.preheader:2 call void (...)* @_ssdm_op_SpecBitsMap(i4* %in_stream_V_strb_V), !map !110 -ST_1: stg_26 [1/1] 0.00ns +ST_1: stg_24 [1/1] 0.00ns arrayctor.loop1.preheader:3 call void (...)* @_ssdm_op_SpecBitsMap(i2* %in_stream_V_user_V), !map !114 -ST_1: stg_27 [1/1] 0.00ns +ST_1: stg_25 [1/1] 0.00ns arrayctor.loop1.preheader:4 call void (...)* @_ssdm_op_SpecBitsMap(i1* %in_stream_V_last_V), !map !118 -ST_1: stg_28 [1/1] 0.00ns +ST_1: stg_26 [1/1] 0.00ns arrayctor.loop1.preheader:5 call void (...)* @_ssdm_op_SpecBitsMap(i5* %in_stream_V_id_V), !map !122 -ST_1: stg_29 [1/1] 0.00ns +ST_1: stg_27 [1/1] 0.00ns arrayctor.loop1.preheader:6 call void (...)* @_ssdm_op_SpecBitsMap(i6* %in_stream_V_dest_V), !map !126 -ST_1: stg_30 [1/1] 0.00ns +ST_1: stg_28 [1/1] 0.00ns arrayctor.loop1.preheader:7 call void (...)* @_ssdm_op_SpecBitsMap(i64* %out_stream_V_data_V), !map !130 -ST_1: stg_31 [1/1] 0.00ns +ST_1: stg_29 [1/1] 0.00ns arrayctor.loop1.preheader:8 call void (...)* @_ssdm_op_SpecBitsMap(i8* %out_stream_V_keep_V), !map !134 -ST_1: stg_32 [1/1] 0.00ns +ST_1: stg_30 [1/1] 0.00ns arrayctor.loop1.preheader:9 call void (...)* @_ssdm_op_SpecBitsMap(i8* %out_stream_V_strb_V), !map !138 -ST_1: stg_33 [1/1] 0.00ns +ST_1: stg_31 [1/1] 0.00ns arrayctor.loop1.preheader:10 call void (...)* @_ssdm_op_SpecBitsMap(i2* %out_stream_V_user_V), !map !142 -ST_1: stg_34 [1/1] 0.00ns +ST_1: stg_32 [1/1] 0.00ns arrayctor.loop1.preheader:11 call void (...)* @_ssdm_op_SpecBitsMap(i1* %out_stream_V_last_V), !map !146 -ST_1: stg_35 [1/1] 0.00ns +ST_1: stg_33 [1/1] 0.00ns arrayctor.loop1.preheader:12 call void (...)* @_ssdm_op_SpecBitsMap(i5* %out_stream_V_id_V), !map !150 -ST_1: stg_36 [1/1] 0.00ns +ST_1: stg_34 [1/1] 0.00ns arrayctor.loop1.preheader:13 call void (...)* @_ssdm_op_SpecBitsMap(i6* %out_stream_V_dest_V), !map !154 -ST_1: stg_37 [1/1] 0.00ns +ST_1: stg_35 [1/1] 0.00ns arrayctor.loop1.preheader:14 call void (...)* @_ssdm_op_SpecBitsMap(i16 %n_pixels_in_bus), !map !158 -ST_1: stg_38 [1/1] 0.00ns +ST_1: stg_36 [1/1] 0.00ns arrayctor.loop1.preheader:15 call void (...)* @_ssdm_op_SpecBitsMap(i8 %N_BG), !map !164 -ST_1: stg_39 [1/1] 0.00ns +ST_1: stg_37 [1/1] 0.00ns arrayctor.loop1.preheader:16 call void (...)* @_ssdm_op_SpecBitsMap(i32 %LOW_THRESH), !map !168 -ST_1: stg_40 [1/1] 0.00ns +ST_1: stg_38 [1/1] 0.00ns arrayctor.loop1.preheader:17 call void (...)* @_ssdm_op_SpecBitsMap(i32* %trig_data), !map !172 -ST_1: stg_41 [1/1] 0.00ns +ST_1: stg_39 [1/1] 0.00ns arrayctor.loop1.preheader:18 call void (...)* @_ssdm_op_SpecBitsMap(i32* %trig_pixel), !map !176 -ST_1: stg_42 [1/1] 0.00ns +ST_1: stg_40 [1/1] 0.00ns arrayctor.loop1.preheader:19 call void (...)* @_ssdm_op_SpecTopModule([11 x i8]* @l2_trigger_str) nounwind ST_1: LOW_THRESH_read [1/1] 1.00ns @@ -476,43 +473,43 @@ arrayctor.loop1.preheader:29 %data_shift2 = alloca [9216 x i17], align 4 ST_1: thresh2 [1/1] 2.38ns arrayctor.loop1.preheader:30 %thresh2 = alloca [1152 x i32], align 16 -ST_1: stg_54 [1/1] 0.00ns +ST_1: stg_52 [1/1] 0.00ns arrayctor.loop1.preheader:31 call void (...)* @_ssdm_op_SpecInterface(i32* %in_stream_V_data_V, i4* %in_stream_V_keep_V, i4* %in_stream_V_strb_V, i2* %in_stream_V_user_V, i1* %in_stream_V_last_V, i5* %in_stream_V_id_V, i6* %in_stream_V_dest_V, [5 x i8]* @p_str1804, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind -ST_1: stg_55 [1/1] 0.00ns +ST_1: stg_53 [1/1] 0.00ns arrayctor.loop1.preheader:32 call void (...)* @_ssdm_op_SpecInterface(i32* %trig_data, [8 x i8]* @p_str1806, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind -ST_1: stg_56 [1/1] 0.00ns +ST_1: stg_54 [1/1] 0.00ns arrayctor.loop1.preheader:33 call void (...)* @_ssdm_op_SpecInterface(i32* %trig_pixel, [8 x i8]* @p_str1806, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind -ST_1: stg_57 [1/1] 0.00ns +ST_1: stg_55 [1/1] 0.00ns arrayctor.loop1.preheader:34 call void (...)* @_ssdm_op_SpecInterface(i64* %out_stream_V_data_V, i8* %out_stream_V_keep_V, i8* %out_stream_V_strb_V, i2* %out_stream_V_user_V, i1* %out_stream_V_last_V, i5* %out_stream_V_id_V, i6* %out_stream_V_dest_V, [5 x i8]* @p_str1804, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind -ST_1: stg_58 [1/1] 0.00ns +ST_1: stg_56 [1/1] 0.00ns arrayctor.loop1.preheader:35 call void (...)* @_ssdm_op_SpecInterface(i16 %n_pixels_in_bus, [10 x i8]* @p_str1807, i32 0, i32 0, i32 0, i32 0, [9 x i8]* @p_str1808, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind ST_1: tmp_1 [1/1] 0.00ns arrayctor.loop1.preheader:36 %tmp_1 = zext i8 %N_BG_read to i32 -ST_1: stg_60 [1/1] 0.00ns +ST_1: stg_58 [1/1] 0.00ns arrayctor.loop1.preheader:37 call void (...)* @_ssdm_op_SpecInterface(i8 %N_BG, [10 x i8]* @p_str1807, i32 0, i32 0, i32 0, i32 0, [9 x i8]* @p_str1808, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind -ST_1: stg_61 [1/1] 0.00ns +ST_1: stg_59 [1/1] 0.00ns arrayctor.loop1.preheader:38 call void (...)* @_ssdm_op_SpecInterface(i32 %LOW_THRESH, [10 x i8]* @p_str1807, i32 0, i32 0, i32 0, i32 0, [9 x i8]* @p_str1808, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind -ST_1: stg_62 [1/1] 0.00ns +ST_1: stg_60 [1/1] 0.00ns arrayctor.loop1.preheader:39 call void (...)* @_ssdm_op_SpecInterface(i32 0, [10 x i8]* @p_str1807, i32 0, i32 0, i32 0, i32 0, [9 x i8]* @p_str1808, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind -ST_1: stg_63 [1/1] 0.00ns +ST_1: stg_61 [1/1] 0.00ns arrayctor.loop1.preheader:40 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 0) -ST_1: stg_64 [1/1] 0.00ns +ST_1: stg_62 [1/1] 0.00ns arrayctor.loop1.preheader:41 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_pixel, i32 0) ST_1: tmp_2 [1/1] 0.00ns arrayctor.loop1.preheader:42 %tmp_2 = call i15 @_ssdm_op_PartSelect.i15.i16.i32.i32(i16 %n_pixels_in_bus_read, i32 1, i32 15) -ST_1: stg_66 [1/1] 1.31ns +ST_1: stg_64 [1/1] 1.31ns arrayctor.loop1.preheader:43 br label %0 @@ -529,7 +526,7 @@ ST_2: exitcond2 [1/1] 1.85ns ST_2: i_5 [1/1] 1.60ns :3 %i_5 = add i15 %i, 1 -ST_2: stg_71 [1/1] 1.31ns +ST_2: stg_69 [1/1] 1.31ns :4 br i1 %exitcond2, label %.preheader84, label %1 ST_2: tmp_4 [1/1] 0.00ns @@ -538,28 +535,28 @@ ST_2: tmp_4 [1/1] 0.00ns ST_2: sum_pix1_addr [1/1] 0.00ns :1 %sum_pix1_addr = getelementptr inbounds [1152 x i32]* %sum_pix1, i64 0, i64 %tmp_4 -ST_2: stg_74 [1/1] 2.38ns +ST_2: stg_72 [1/1] 2.38ns :2 store i32 0, i32* %sum_pix1_addr, align 4 ST_2: sum_pix2_addr [1/1] 0.00ns :3 %sum_pix2_addr = getelementptr inbounds [1152 x i32]* %sum_pix2, i64 0, i64 %tmp_4 -ST_2: stg_76 [1/1] 2.38ns +ST_2: stg_74 [1/1] 2.38ns :4 store i32 0, i32* %sum_pix2_addr, align 4 ST_2: thresh1_addr [1/1] 0.00ns :5 %thresh1_addr = getelementptr inbounds [1152 x i32]* %thresh1, i64 0, i64 %tmp_4 -ST_2: stg_78 [1/1] 2.38ns +ST_2: stg_76 [1/1] 2.38ns :6 store i32 25500, i32* %thresh1_addr, align 4 ST_2: thresh2_addr [1/1] 0.00ns :7 %thresh2_addr = getelementptr inbounds [1152 x i32]* %thresh2, i64 0, i64 %tmp_4 -ST_2: stg_80 [1/1] 2.38ns +ST_2: stg_78 [1/1] 2.38ns :8 store i32 25500, i32* %thresh2_addr, align 4 -ST_2: stg_81 [1/1] 0.00ns +ST_2: stg_79 [1/1] 0.00ns :9 br label %0 @@ -576,7 +573,7 @@ ST_3: empty_7 [1/1] 0.00ns ST_3: kk_2 [1/1] 0.70ns .preheader84:3 %kk_2 = add i4 %kk, 1 -ST_3: stg_86 [1/1] 0.00ns +ST_3: stg_84 [1/1] 0.00ns .preheader84:4 br i1 %exitcond1, label %.preheader82, label %.preheader83.preheader ST_3: tmp_6 [1/1] 0.00ns @@ -594,7 +591,7 @@ ST_3: p_shl1_cast [1/1] 0.00ns ST_3: tmp_3 [1/1] 1.60ns .preheader83.preheader:4 %tmp_3 = add i15 %p_shl1_cast, %p_shl_cast -ST_3: stg_92 [1/1] 1.31ns +ST_3: stg_90 [1/1] 1.31ns .preheader83.preheader:5 br label %.preheader83 @@ -611,7 +608,7 @@ ST_4: exitcond9 [1/1] 1.85ns ST_4: i_6 [1/1] 1.60ns .preheader83:3 %i_6 = add i15 %i_1, 1 -ST_4: stg_97 [1/1] 0.00ns +ST_4: stg_95 [1/1] 0.00ns .preheader83:4 br i1 %exitcond9, label %.preheader84, label %2 ST_4: tmp_8 [1/1] 1.60ns @@ -626,13 +623,13 @@ ST_4: data_shift1_addr [1/1] 0.00ns ST_4: data_shift2_addr [1/1] 0.00ns :3 %data_shift2_addr = getelementptr [9216 x i17]* %data_shift2, i64 0, i64 %tmp_18_cast -ST_4: stg_102 [1/1] 2.38ns +ST_4: stg_100 [1/1] 2.38ns :4 store i17 0, i17* %data_shift1_addr, align 4 -ST_4: stg_103 [1/1] 2.38ns +ST_4: stg_101 [1/1] 2.38ns :5 store i17 0, i17* %data_shift2_addr, align 4 -ST_4: stg_104 [1/1] 0.00ns +ST_4: stg_102 [1/1] 0.00ns :6 br label %.preheader83 @@ -640,10 +637,10 @@ ST_4: stg_104 [1/1] 0.00ns ST_5: tmp [1/1] 0.00ns .preheader82:0 %tmp = call i1 @_ssdm_op_NbReadReq.axis.i32P.i4P.i4P.i2P.i1P.i5P.i6P(i32* %in_stream_V_data_V, i4* %in_stream_V_keep_V, i4* %in_stream_V_strb_V, i2* %in_stream_V_user_V, i1* %in_stream_V_last_V, i5* %in_stream_V_id_V, i6* %in_stream_V_dest_V, i32 1) -ST_5: stg_106 [1/1] 1.31ns +ST_5: stg_104 [1/1] 1.31ns .preheader82:1 br i1 %tmp, label %.preheader81, label %14 -ST_5: stg_107 [1/1] 0.00ns +ST_5: stg_105 [1/1] 0.00ns :0 ret void @@ -660,7 +657,7 @@ ST_6: exitcond8 [1/1] 1.85ns ST_6: i_7 [1/1] 1.60ns .preheader81:3 %i_7 = add i15 %i_2, 1 -ST_6: stg_112 [1/1] 1.31ns +ST_6: stg_110 [1/1] 1.31ns .preheader81:4 br i1 %exitcond8, label %.preheader80, label %3 ST_6: tmp_7 [1/1] 0.00ns @@ -669,16 +666,16 @@ ST_6: tmp_7 [1/1] 0.00ns ST_6: sum_pix1_addr_1 [1/1] 0.00ns :1 %sum_pix1_addr_1 = getelementptr inbounds [1152 x i32]* %sum_pix1, i64 0, i64 %tmp_7 -ST_6: stg_115 [1/1] 2.38ns +ST_6: stg_113 [1/1] 2.38ns :2 store i32 0, i32* %sum_pix1_addr_1, align 4 ST_6: sum_pix2_addr_1 [1/1] 0.00ns :3 %sum_pix2_addr_1 = getelementptr inbounds [1152 x i32]* %sum_pix2, i64 0, i64 %tmp_7 -ST_6: stg_117 [1/1] 2.38ns +ST_6: stg_115 [1/1] 2.38ns :4 store i32 0, i32* %sum_pix2_addr_1, align 4 -ST_6: stg_118 [1/1] 0.00ns +ST_6: stg_116 [1/1] 0.00ns :5 br label %.preheader81 @@ -698,7 +695,7 @@ ST_7: empty_10 [1/1] 0.00ns ST_7: tmp_5 [1/1] 1.40ns .preheader80:4 %tmp_5 = add i8 %k, 1 -ST_7: stg_124 [1/1] 1.31ns +ST_7: stg_122 [1/1] 1.31ns .preheader80:5 br i1 %exitcond, label %.preheader, label %.preheader79 @@ -718,7 +715,7 @@ ST_8: exitcond7 [1/1] 1.85ns ST_8: i_9 [1/1] 1.60ns .preheader79:4 %i_9 = add i15 %i_3, 1 -ST_8: stg_130 [1/1] 0.00ns +ST_8: stg_128 [1/1] 0.00ns .preheader79:5 br i1 %exitcond7, label %.preheader80, label %_ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit ST_8: tmp_15 [1/1] 0.00ns @@ -765,7 +762,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:9 %sum_pix1_load_ ST_9: tmp_18 [1/1] 2.00ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:10 %tmp_18 = add i32 %sum_pix1_load_1, %tmp_17 -ST_9: stg_145 [1/1] 2.38ns +ST_9: stg_143 [1/1] 2.38ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:11 store i32 %tmp_18, i32* %sum_pix1_addr_3, align 4 ST_9: tmp_19 [1/1] 0.00ns @@ -777,22 +774,22 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:14 %sum_pix2_load ST_9: tmp_20 [1/1] 2.00ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:15 %tmp_20 = add i32 %sum_pix2_load_1, %tmp_19 -ST_9: stg_149 [1/1] 2.38ns +ST_9: stg_147 [1/1] 2.38ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:16 store i32 %tmp_20, i32* %sum_pix2_addr_3, align 4 ST_9: sum_overP1_addr [1/1] 0.00ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:17 %sum_overP1_addr = getelementptr inbounds [1152 x i32]* %sum_overP1, i64 0, i64 %tmp_15 -ST_9: stg_151 [1/1] 2.38ns +ST_9: stg_149 [1/1] 2.38ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:18 store i32 0, i32* %sum_overP1_addr, align 4 ST_9: sum_overP2_addr [1/1] 0.00ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:19 %sum_overP2_addr = getelementptr inbounds [1152 x i32]* %sum_overP2, i64 0, i64 %tmp_15 -ST_9: stg_153 [1/1] 2.38ns +ST_9: stg_151 [1/1] 2.38ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:20 store i32 0, i32* %sum_overP2_addr, align 4 -ST_9: stg_154 [1/1] 1.31ns +ST_9: stg_152 [1/1] 1.31ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 @@ -806,7 +803,7 @@ ST_10: tmp_22 [1/1] 0.00ns ST_10: empty_13 [1/1] 0.00ns :2 %empty_13 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 7, i64 7, i64 7) -ST_10: stg_158 [1/1] 0.00ns +ST_10: stg_156 [1/1] 0.00ns :3 br i1 %tmp_22, label %6, label %5 ST_10: tmp_26 [1/1] 0.00ns @@ -851,13 +848,13 @@ ST_10: sum_overP2_load [2/2] 2.38ns ST_10: tmp_19_cast [1/1] 0.00ns :0 %tmp_19_cast = sext i16 %tmp_16 to i17 -ST_10: stg_173 [1/1] 2.38ns +ST_10: stg_171 [1/1] 2.38ns :1 store i17 %tmp_19_cast, i17* %data_shift1_addr_1, align 4 ST_10: tmp_21_cast [1/1] 0.00ns :2 %tmp_21_cast = sext i16 %phitmp to i17 -ST_10: stg_175 [1/1] 2.38ns +ST_10: stg_173 [1/1] 2.38ns :3 store i17 %tmp_21_cast, i17* %data_shift2_addr_1, align 4 ST_10: sum_overP1_load_1 [2/2] 2.38ns @@ -910,7 +907,7 @@ ST_11: data_shift1_addr_3 [1/1] 0.00ns ST_11: data_shift2_addr_3 [1/1] 0.00ns :20 %data_shift2_addr_3 = getelementptr [9216 x i17]* %data_shift2, i64 0, i64 %tmp_49_cast -ST_11: stg_192 [1/1] 2.38ns +ST_11: stg_190 [1/1] 2.38ns :21 store i17 %data_shift1_load, i17* %data_shift1_addr_3, align 4 ST_11: data_shift2_load [1/2] 2.38ns @@ -919,7 +916,7 @@ ST_11: data_shift2_load [1/2] 2.38ns ST_11: extLd1 [1/1] 0.00ns :23 %extLd1 = sext i17 %data_shift2_load to i32 -ST_11: stg_195 [1/1] 2.38ns +ST_11: stg_193 [1/1] 2.38ns :24 store i17 %data_shift2_load, i17* %data_shift2_addr_3, align 4 ST_11: sum_overP1_load [1/2] 2.38ns @@ -928,7 +925,7 @@ ST_11: sum_overP1_load [1/2] 2.38ns ST_11: tmp_29 [1/1] 2.00ns :26 %tmp_29 = add i32 %sum_overP1_load, %extLd -ST_11: stg_198 [1/1] 2.38ns +ST_11: stg_196 [1/1] 2.38ns :27 store i32 %tmp_29, i32* %sum_overP1_addr, align 4 ST_11: sum_overP2_load [1/2] 2.38ns @@ -937,13 +934,13 @@ ST_11: sum_overP2_load [1/2] 2.38ns ST_11: tmp_30 [1/1] 2.00ns :29 %tmp_30 = add i32 %sum_overP2_load, %extLd1 -ST_11: stg_201 [1/1] 2.38ns +ST_11: stg_199 [1/1] 2.38ns :30 store i32 %tmp_30, i32* %sum_overP2_addr, align 4 ST_11: kk_3 [1/1] 0.70ns :31 %kk_3 = add i4 %kk_1, -1 -ST_11: stg_203 [1/1] 0.00ns +ST_11: stg_201 [1/1] 0.00ns :32 br label %4 @@ -954,7 +951,7 @@ ST_12: sum_overP1_load_1 [1/2] 2.38ns ST_12: tmp_23 [1/1] 2.00ns :5 %tmp_23 = add i32 %tmp_17, %sum_overP1_load_1 -ST_12: stg_206 [1/1] 2.38ns +ST_12: stg_204 [1/1] 2.38ns :6 store i32 %tmp_23, i32* %sum_overP1_addr, align 4 ST_12: sum_overP2_load_1 [1/2] 2.38ns @@ -963,7 +960,7 @@ ST_12: sum_overP2_load_1 [1/2] 2.38ns ST_12: tmp_24 [1/1] 2.00ns :8 %tmp_24 = add i32 %tmp_19, %sum_overP2_load_1 -ST_12: stg_209 [1/1] 2.38ns +ST_12: stg_207 [1/1] 2.38ns :9 store i32 %tmp_24, i32* %sum_overP2_addr, align 4 ST_12: thresh1_load [1/2] 2.38ns @@ -972,7 +969,7 @@ ST_12: thresh1_load [1/2] 2.38ns ST_12: tmp_25 [1/1] 2.12ns :12 %tmp_25 = icmp ugt i32 %tmp_23, %thresh1_load -ST_12: stg_212 [1/1] 0.00ns +ST_12: stg_210 [1/1] 0.00ns :13 br i1 %tmp_25, label %7, label %9 ST_12: thresh2_addr_2 [1/1] 0.00ns @@ -987,10 +984,10 @@ ST_12: tmp_36 [1/1] 1.04ns ST_12: tmp_34 [1/1] 1.04ns :0 %tmp_34 = icmp eq i32 %itrig_1, 0 -ST_12: stg_217 [1/1] 0.00ns +ST_12: stg_215 [1/1] 0.00ns :1 br i1 %tmp_34, label %8, label %.preheader79 -ST_12: stg_218 [1/1] 0.00ns +ST_12: stg_216 [1/1] 0.00ns :0 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 1) @@ -1004,166 +1001,162 @@ ST_13: tmp_35 [1/1] 2.12ns ST_13: or_cond [1/1] 1.15ns :4 %or_cond = and i1 %tmp_35, %tmp_36 -ST_13: stg_222 [1/1] 0.00ns +ST_13: stg_220 [1/1] 0.00ns :5 br i1 %or_cond, label %10, label %.preheader79 -ST_13: stg_223 [1/1] 0.00ns +ST_13: stg_221 [1/1] 0.00ns :0 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 1) - - : 0.00ns -ST_14: stg_224 [1/1] 0.00ns -:1 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 0) - - - : 0.00ns -ST_15: tmp_38 [1/1] 0.00ns +ST_13: tmp_38 [1/1] 0.00ns :2 %tmp_38 = call i16 @_ssdm_op_BitConcatenate.i16.i15.i1(i15 %i_3, i1 false) -ST_15: tmp_39 [1/1] 0.00ns +ST_13: tmp_39 [1/1] 0.00ns :3 %tmp_39 = or i16 %tmp_38, 1 -ST_15: tmp_40_cast [1/1] 0.00ns +ST_13: tmp_40_cast [1/1] 0.00ns :4 %tmp_40_cast = zext i16 %tmp_39 to i32 -ST_15: stg_228 [1/1] 0.00ns -:5 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 %tmp_40_cast) +ST_13: stg_225 [1/1] 0.00ns +:5 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_pixel, i32 %tmp_40_cast) + + + : 0.00ns +ST_14: stg_226 [1/1] 0.00ns +:1 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 0) -ST_15: stg_229 [1/1] 0.00ns +ST_14: stg_227 [1/1] 0.00ns :6 br label %.preheader79 - : 0.00ns -ST_16: stg_230 [1/1] 0.00ns + : 0.00ns +ST_15: stg_228 [1/1] 0.00ns :1 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 0) - - : 0.00ns -ST_17: tmp_37 [1/1] 0.00ns +ST_15: tmp_37 [1/1] 0.00ns :2 %tmp_37 = call i16 @_ssdm_op_BitConcatenate.i16.i15.i1(i15 %i_3, i1 false) -ST_17: tmp_38_cast [1/1] 0.00ns +ST_15: tmp_38_cast [1/1] 0.00ns :3 %tmp_38_cast = zext i16 %tmp_37 to i32 -ST_17: stg_233 [1/1] 0.00ns -:4 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 %tmp_38_cast) +ST_15: stg_231 [1/1] 0.00ns +:4 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_pixel, i32 %tmp_38_cast) -ST_17: stg_234 [1/1] 0.00ns +ST_15: stg_232 [1/1] 0.00ns :5 br label %.preheader79 - : 2.38ns -ST_18: i_4 [1/1] 0.00ns + : 2.38ns +ST_16: i_4 [1/1] 0.00ns .preheader:0 %i_4 = phi i15 [ %i_8, %._crit_edge87 ], [ 0, %.preheader80 ] -ST_18: empty_14 [1/1] 0.00ns +ST_16: empty_14 [1/1] 0.00ns .preheader:1 %empty_14 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 0, i64 32767, i64 0) -ST_18: exitcond6 [1/1] 1.85ns +ST_16: exitcond6 [1/1] 1.85ns .preheader:2 %exitcond6 = icmp eq i15 %i_4, %tmp_2 -ST_18: i_8 [1/1] 1.60ns +ST_16: i_8 [1/1] 1.60ns .preheader:3 %i_8 = add i15 %i_4, 1 -ST_18: stg_239 [1/1] 0.00ns +ST_16: stg_237 [1/1] 0.00ns .preheader:4 br i1 %exitcond6, label %.preheader82, label %11 -ST_18: tmp_9 [1/1] 0.00ns +ST_16: tmp_9 [1/1] 0.00ns :0 %tmp_9 = zext i15 %i_4 to i64 -ST_18: sum_pix2_addr_2 [1/1] 0.00ns +ST_16: sum_pix2_addr_2 [1/1] 0.00ns :1 %sum_pix2_addr_2 = getelementptr inbounds [1152 x i32]* %sum_pix2, i64 0, i64 %tmp_9 -ST_18: sum_pix2_load [2/2] 2.38ns +ST_16: sum_pix2_load [2/2] 2.38ns :2 %sum_pix2_load = load i32* %sum_pix2_addr_2, align 4 -ST_18: sum_pix1_addr_2 [1/1] 0.00ns +ST_16: sum_pix1_addr_2 [1/1] 0.00ns :3 %sum_pix1_addr_2 = getelementptr inbounds [1152 x i32]* %sum_pix1, i64 0, i64 %tmp_9 -ST_18: sum_pix1_load [2/2] 2.38ns +ST_16: sum_pix1_load [2/2] 2.38ns :4 %sum_pix1_load = load i32* %sum_pix1_addr_2, align 4 -ST_18: thresh1_addr_1 [1/1] 0.00ns +ST_16: thresh1_addr_1 [1/1] 0.00ns :14 %thresh1_addr_1 = getelementptr inbounds [1152 x i32]* %thresh1, i64 0, i64 %tmp_9 -ST_18: thresh2_addr_1 [1/1] 0.00ns +ST_16: thresh2_addr_1 [1/1] 0.00ns :17 %thresh2_addr_1 = getelementptr inbounds [1152 x i32]* %thresh2, i64 0, i64 %tmp_9 - : 2.38ns -ST_19: sum_pix2_load [1/2] 2.38ns + : 2.38ns +ST_17: sum_pix2_load [1/2] 2.38ns :2 %sum_pix2_load = load i32* %sum_pix2_addr_2, align 4 -ST_19: sum_pix1_load [1/2] 2.38ns +ST_17: sum_pix1_load [1/2] 2.38ns :4 %sum_pix1_load = load i32* %sum_pix1_addr_2, align 4 -ST_19: tmp_data_V [1/1] 0.00ns +ST_17: tmp_data_V [1/1] 0.00ns :5 %tmp_data_V = call i64 @_ssdm_op_BitConcatenate.i64.i32.i32(i32 %sum_pix2_load, i32 %sum_pix1_load) -ST_19: stg_250 [1/1] 0.00ns +ST_17: stg_248 [1/1] 0.00ns :6 call void @_ssdm_op_Write.axis.volatile.i64P.i8P.i8P.i2P.i1P.i5P.i6P(i64* %out_stream_V_data_V, i8* %out_stream_V_keep_V, i8* %out_stream_V_strb_V, i2* %out_stream_V_user_V, i1* %out_stream_V_last_V, i5* %out_stream_V_id_V, i6* %out_stream_V_dest_V, i64 %tmp_data_V, i8 -1, i8 -1, i2 undef, i1 undef, i5 undef, i6 undef) -ST_19: tmp_10 [1/1] 0.00ns +ST_17: tmp_10 [1/1] 0.00ns :7 %tmp_10 = call i25 @_ssdm_op_PartSelect.i25.i32.i32.i32(i32 %sum_pix1_load, i32 7, i32 31) -ST_19: tmp_11 [1/1] 0.00ns +ST_17: tmp_11 [1/1] 0.00ns :10 %tmp_11 = call i25 @_ssdm_op_PartSelect.i25.i32.i32.i32(i32 %sum_pix2_load, i32 7, i32 31) - : 7.65ns -ST_20: sum_pixP1 [1/1] 0.00ns + : 7.65ns +ST_18: sum_pixP1 [1/1] 0.00ns :8 %sum_pixP1 = call i28 @_ssdm_op_BitConcatenate.i28.i25.i3(i25 %tmp_10, i3 0) -ST_20: sum_pixP1_cast [1/1] 0.00ns +ST_18: sum_pixP1_cast [1/1] 0.00ns :9 %sum_pixP1_cast = zext i28 %sum_pixP1 to i32 -ST_20: sum_pixP2 [1/1] 0.00ns +ST_18: sum_pixP2 [1/1] 0.00ns :11 %sum_pixP2 = call i28 @_ssdm_op_BitConcatenate.i28.i25.i3(i25 %tmp_11, i3 0) -ST_20: sum_pixP2_cast [1/1] 0.00ns +ST_18: sum_pixP2_cast [1/1] 0.00ns :12 %sum_pixP2_cast = zext i28 %sum_pixP2 to i32 -ST_20: tmp_12 [1/1] 7.65ns +ST_18: tmp_12 [1/1] 7.65ns :13 %tmp_12 = mul i32 %sum_pixP1_cast, %tmp_1 -ST_20: tmp_13 [1/1] 7.65ns +ST_18: tmp_13 [1/1] 7.65ns :16 %tmp_13 = mul i32 %sum_pixP2_cast, %tmp_1 - : 2.38ns -ST_21: stg_259 [1/1] 2.38ns + : 2.38ns +ST_19: stg_257 [1/1] 2.38ns :15 store i32 %tmp_12, i32* %thresh1_addr_1, align 4 -ST_21: stg_260 [1/1] 2.38ns +ST_19: stg_258 [1/1] 2.38ns :18 store i32 %tmp_13, i32* %thresh2_addr_1, align 4 -ST_21: tmp_14 [1/1] 2.12ns +ST_19: tmp_14 [1/1] 2.12ns :19 %tmp_14 = icmp ult i32 %tmp_12, %LOW_THRESH_read -ST_21: stg_262 [1/1] 0.00ns +ST_19: stg_260 [1/1] 0.00ns :20 br i1 %tmp_14, label %12, label %._crit_edge86 - : 2.38ns -ST_22: stg_263 [1/1] 2.38ns + : 2.38ns +ST_20: stg_261 [1/1] 2.38ns :0 store i32 %LOW_THRESH_read, i32* %thresh1_addr_1, align 4 -ST_22: stg_264 [1/1] 0.00ns +ST_20: stg_262 [1/1] 0.00ns :1 br label %._crit_edge86 -ST_22: tmp_21 [1/1] 2.12ns +ST_20: tmp_21 [1/1] 2.12ns ._crit_edge86:0 %tmp_21 = icmp ult i32 %tmp_13, %LOW_THRESH_read -ST_22: stg_266 [1/1] 0.00ns +ST_20: stg_264 [1/1] 0.00ns ._crit_edge86:1 br i1 %tmp_21, label %13, label %._crit_edge87 -ST_22: stg_267 [1/1] 2.38ns +ST_20: stg_265 [1/1] 2.38ns :0 store i32 %LOW_THRESH_read, i32* %thresh2_addr_1, align 4 -ST_22: stg_268 [1/1] 0.00ns +ST_20: stg_266 [1/1] 0.00ns :1 br label %._crit_edge87 -ST_22: stg_269 [1/1] 0.00ns +ST_20: stg_267 [1/1] 0.00ns ._crit_edge87:0 br label %.preheader @@ -1205,241 +1198,241 @@ Port [ trig_pixel]: wired=1; compound=0; hidden=0; nouse=0; global=0; static=0; -stg_23 (specbitsmap ) [ 00000000000000000000000] -stg_24 (specbitsmap ) [ 00000000000000000000000] -stg_25 (specbitsmap ) [ 00000000000000000000000] -stg_26 (specbitsmap ) [ 00000000000000000000000] -stg_27 (specbitsmap ) [ 00000000000000000000000] -stg_28 (specbitsmap ) [ 00000000000000000000000] -stg_29 (specbitsmap ) [ 00000000000000000000000] -stg_30 (specbitsmap ) [ 00000000000000000000000] -stg_31 (specbitsmap ) [ 00000000000000000000000] -stg_32 (specbitsmap ) [ 00000000000000000000000] -stg_33 (specbitsmap ) [ 00000000000000000000000] -stg_34 (specbitsmap ) [ 00000000000000000000000] -stg_35 (specbitsmap ) [ 00000000000000000000000] -stg_36 (specbitsmap ) [ 00000000000000000000000] -stg_37 (specbitsmap ) [ 00000000000000000000000] -stg_38 (specbitsmap ) [ 00000000000000000000000] -stg_39 (specbitsmap ) [ 00000000000000000000000] -stg_40 (specbitsmap ) [ 00000000000000000000000] -stg_41 (specbitsmap ) [ 00000000000000000000000] -stg_42 (spectopmodule ) [ 00000000000000000000000] -LOW_THRESH_read (read ) [ 00111111111111111111111] -N_BG_read (read ) [ 00000000000000000000000] -n_pixels_in_bus_read (read ) [ 00000000000000000000000] -sum_overP1 (alloca ) [ 00111111111111111111111] -sum_overP2 (alloca ) [ 00111111111111111111111] -sum_pix1 (alloca ) [ 00111111111111111111111] -data_shift1 (alloca ) [ 00111111111111111111111] -thresh1 (alloca ) [ 00111111111111111111111] -sum_pix2 (alloca ) [ 00111111111111111111111] -data_shift2 (alloca ) [ 00111111111111111111111] -thresh2 (alloca ) [ 00111111111111111111111] -stg_54 (specinterface ) [ 00000000000000000000000] -stg_55 (specinterface ) [ 00000000000000000000000] -stg_56 (specinterface ) [ 00000000000000000000000] -stg_57 (specinterface ) [ 00000000000000000000000] -stg_58 (specinterface ) [ 00000000000000000000000] -tmp_1 (zext ) [ 00111111111111111111111] -stg_60 (specinterface ) [ 00000000000000000000000] -stg_61 (specinterface ) [ 00000000000000000000000] -stg_62 (specinterface ) [ 00000000000000000000000] -stg_63 (write ) [ 00000000000000000000000] -stg_64 (write ) [ 00000000000000000000000] -tmp_2 (partselect ) [ 00111111111111111111111] -stg_66 (br ) [ 01100000000000000000000] -i (phi ) [ 00100000000000000000000] -empty (speclooptripcount) [ 00000000000000000000000] -exitcond2 (icmp ) [ 00100000000000000000000] -i_5 (add ) [ 01100000000000000000000] -stg_71 (br ) [ 00111000000000000000000] -tmp_4 (zext ) [ 00000000000000000000000] -sum_pix1_addr (getelementptr ) [ 00000000000000000000000] -stg_74 (store ) [ 00000000000000000000000] -sum_pix2_addr (getelementptr ) [ 00000000000000000000000] -stg_76 (store ) [ 00000000000000000000000] -thresh1_addr (getelementptr ) [ 00000000000000000000000] -stg_78 (store ) [ 00000000000000000000000] -thresh2_addr (getelementptr ) [ 00000000000000000000000] -stg_80 (store ) [ 00000000000000000000000] -stg_81 (br ) [ 01100000000000000000000] -kk (phi ) [ 00010000000000000000000] -exitcond1 (icmp ) [ 00011000000000000000000] -empty_7 (speclooptripcount) [ 00000000000000000000000] -kk_2 (add ) [ 00111000000000000000000] -stg_86 (br ) [ 00000000000000000000000] -tmp_6 (bitconcatenate ) [ 00000000000000000000000] -p_shl_cast (zext ) [ 00000000000000000000000] -tmp_s (bitconcatenate ) [ 00000000000000000000000] -p_shl1_cast (zext ) [ 00000000000000000000000] -tmp_3 (add ) [ 00001000000000000000000] -stg_92 (br ) [ 00011000000000000000000] -i_1 (phi ) [ 00001000000000000000000] -empty_8 (speclooptripcount) [ 00000000000000000000000] -exitcond9 (icmp ) [ 00011000000000000000000] -i_6 (add ) [ 00011000000000000000000] -stg_97 (br ) [ 00111000000000000000000] -tmp_8 (add ) [ 00000000000000000000000] -tmp_18_cast (zext ) [ 00000000000000000000000] -data_shift1_addr (getelementptr ) [ 00000000000000000000000] -data_shift2_addr (getelementptr ) [ 00000000000000000000000] -stg_102 (store ) [ 00000000000000000000000] -stg_103 (store ) [ 00000000000000000000000] -stg_104 (br ) [ 00011000000000000000000] -tmp (nbreadreq ) [ 00000111111111111111111] -stg_106 (br ) [ 00000111111111111111111] -stg_107 (ret ) [ 00000000000000000000000] -i_2 (phi ) [ 00000010000000000000000] -empty_9 (speclooptripcount) [ 00000000000000000000000] -exitcond8 (icmp ) [ 00000111111111111111111] -i_7 (add ) [ 00000111111111111111111] -stg_112 (br ) [ 00000111111111111111111] -tmp_7 (zext ) [ 00000000000000000000000] -sum_pix1_addr_1 (getelementptr ) [ 00000000000000000000000] -stg_115 (store ) [ 00000000000000000000000] -sum_pix2_addr_1 (getelementptr ) [ 00000000000000000000000] -stg_117 (store ) [ 00000000000000000000000] -stg_118 (br ) [ 00000111111111111111111] -k (phi ) [ 00000001000000000000000] -itrig (phi ) [ 00000001111111111100000] -exitcond (icmp ) [ 00000111111111111111111] -empty_10 (speclooptripcount) [ 00000000000000000000000] -tmp_5 (add ) [ 00000111111111111111111] -stg_124 (br ) [ 00000111111111111111111] -i_3 (phi ) [ 00000000111100111100000] -itrig_1 (phi ) [ 00000111111111111111111] -empty_11 (speclooptripcount) [ 00000000000000000000000] -exitcond7 (icmp ) [ 00000111111111111111111] -i_9 (add ) [ 00000111111111111111111] -stg_130 (br ) [ 00000111111111111111111] -tmp_15 (zext ) [ 00000000011110000000000] -sum_pix1_addr_3 (getelementptr ) [ 00000000010000000000000] -sum_pix2_addr_3 (getelementptr ) [ 00000000010000000000000] -data_shift1_addr_1 (getelementptr ) [ 00000000001100000000000] -data_shift2_addr_1 (getelementptr ) [ 00000000001100000000000] -empty_12 (read ) [ 00000000000000000000000] -tmp_data_V_2 (extractvalue ) [ 00000000000000000000000] -tmp_16 (trunc ) [ 00000000001100000000000] -phitmp (partselect ) [ 00000000001100000000000] -tmp_17 (sext ) [ 00000000001110000000000] -sum_pix1_load_1 (load ) [ 00000000000000000000000] -tmp_18 (add ) [ 00000000000000000000000] -stg_145 (store ) [ 00000000000000000000000] -tmp_19 (sext ) [ 00000000001110000000000] -sum_pix2_load_1 (load ) [ 00000000000000000000000] -tmp_20 (add ) [ 00000000000000000000000] -stg_149 (store ) [ 00000000000000000000000] -sum_overP1_addr (getelementptr ) [ 00000000001110000000000] -stg_151 (store ) [ 00000000000000000000000] -sum_overP2_addr (getelementptr ) [ 00000000001110000000000] -stg_153 (store ) [ 00000000000000000000000] -stg_154 (br ) [ 00000111111111111111111] -kk_1 (phi ) [ 00000000001100000000000] -tmp_22 (bitselect ) [ 00000111111111111111111] -empty_13 (speclooptripcount) [ 00000000000000000000000] -stg_158 (br ) [ 00000000000000000000000] -tmp_26 (bitconcatenate ) [ 00000000000000000000000] -p_shl4_cast (sext ) [ 00000000000000000000000] -tmp_28 (bitconcatenate ) [ 00000000000000000000000] -p_shl5_cast (sext ) [ 00000000000000000000000] -tmp_31 (add ) [ 00000000000000000000000] -tmp_32 (add ) [ 00000000000000000000000] -tmp_45_cast (zext ) [ 00000000000000000000000] -data_shift1_addr_2 (getelementptr ) [ 00000000000100000000000] -data_shift2_addr_2 (getelementptr ) [ 00000000000100000000000] -tmp_19_cast (sext ) [ 00000000000000000000000] -stg_173 (store ) [ 00000000000000000000000] -tmp_21_cast (sext ) [ 00000000000000000000000] -stg_175 (store ) [ 00000000000000000000000] -thresh1_addr_2 (getelementptr ) [ 00000000000010000000000] -data_shift1_load (load ) [ 00000000000000000000000] -extLd (sext ) [ 00000000000000000000000] -tmp_27 (add ) [ 00000000000000000000000] -tmp_33 (bitconcatenate ) [ 00000000000000000000000] -p_shl2_cast (zext ) [ 00000000000000000000000] -tmp_40 (bitconcatenate ) [ 00000000000000000000000] -p_shl3_cast (zext ) [ 00000000000000000000000] -tmp_41 (add ) [ 00000000000000000000000] -tmp_42 (add ) [ 00000000000000000000000] -tmp_49_cast (zext ) [ 00000000000000000000000] -data_shift1_addr_3 (getelementptr ) [ 00000000000000000000000] -data_shift2_addr_3 (getelementptr ) [ 00000000000000000000000] -stg_192 (store ) [ 00000000000000000000000] -data_shift2_load (load ) [ 00000000000000000000000] -extLd1 (sext ) [ 00000000000000000000000] -stg_195 (store ) [ 00000000000000000000000] -sum_overP1_load (load ) [ 00000000000000000000000] -tmp_29 (add ) [ 00000000000000000000000] -stg_198 (store ) [ 00000000000000000000000] -sum_overP2_load (load ) [ 00000000000000000000000] -tmp_30 (add ) [ 00000000000000000000000] -stg_201 (store ) [ 00000000000000000000000] -kk_3 (add ) [ 00000111111111111111111] -stg_203 (br ) [ 00000111111111111111111] -sum_overP1_load_1 (load ) [ 00000000000000000000000] -tmp_23 (add ) [ 00000000000000000000000] -stg_206 (store ) [ 00000000000000000000000] -sum_overP2_load_1 (load ) [ 00000000000000000000000] -tmp_24 (add ) [ 00000000000001000000000] -stg_209 (store ) [ 00000000000000000000000] -thresh1_load (load ) [ 00000000000000000000000] -tmp_25 (icmp ) [ 00000111111111111111111] -stg_212 (br ) [ 00000000000000000000000] -thresh2_addr_2 (getelementptr ) [ 00000000000001000000000] -tmp_36 (icmp ) [ 00000000000001000000000] -tmp_34 (icmp ) [ 00000111111111111111111] -stg_217 (br ) [ 00000111111111111111111] -stg_218 (write ) [ 00000000000000000000000] -thresh2_load (load ) [ 00000000000000000000000] -tmp_35 (icmp ) [ 00000000000000000000000] -or_cond (and ) [ 00000111111111111111111] -stg_222 (br ) [ 00000111111111111111111] -stg_223 (write ) [ 00000000000000000000000] -stg_224 (write ) [ 00000000000000000000000] -tmp_38 (bitconcatenate ) [ 00000000000000000000000] -tmp_39 (or ) [ 00000000000000000000000] -tmp_40_cast (zext ) [ 00000000000000000000000] -stg_228 (write ) [ 00000000000000000000000] -stg_229 (br ) [ 00000111111111111111111] -stg_230 (write ) [ 00000000000000000000000] -tmp_37 (bitconcatenate ) [ 00000000000000000000000] -tmp_38_cast (zext ) [ 00000000000000000000000] -stg_233 (write ) [ 00000000000000000000000] -stg_234 (br ) [ 00000111111111111111111] -i_4 (phi ) [ 00000000000000000010000] -empty_14 (speclooptripcount) [ 00000000000000000000000] -exitcond6 (icmp ) [ 00000111111111111111111] -i_8 (add ) [ 00000111111111111111111] -stg_239 (br ) [ 00000000000000000000000] -tmp_9 (zext ) [ 00000000000000000000000] -sum_pix2_addr_2 (getelementptr ) [ 00000000000000000001000] -sum_pix1_addr_2 (getelementptr ) [ 00000000000000000001000] -thresh1_addr_1 (getelementptr ) [ 00000000000000000001111] -thresh2_addr_1 (getelementptr ) [ 00000000000000000001111] -sum_pix2_load (load ) [ 00000000000000000000000] -sum_pix1_load (load ) [ 00000000000000000000000] -tmp_data_V (bitconcatenate ) [ 00000000000000000000000] -stg_250 (write ) [ 00000000000000000000000] -tmp_10 (partselect ) [ 00000000000000000000100] -tmp_11 (partselect ) [ 00000000000000000000100] -sum_pixP1 (bitconcatenate ) [ 00000000000000000000000] -sum_pixP1_cast (zext ) [ 00000000000000000000000] -sum_pixP2 (bitconcatenate ) [ 00000000000000000000000] -sum_pixP2_cast (zext ) [ 00000000000000000000000] -tmp_12 (mul ) [ 00000000000000000000010] -tmp_13 (mul ) [ 00000000000000000000011] -stg_259 (store ) [ 00000000000000000000000] -stg_260 (store ) [ 00000000000000000000000] -tmp_14 (icmp ) [ 00000000000000000000001] -stg_262 (br ) [ 00000000000000000000000] -stg_263 (store ) [ 00000000000000000000000] -stg_264 (br ) [ 00000000000000000000000] -tmp_21 (icmp ) [ 00000111111111111111111] -stg_266 (br ) [ 00000000000000000000000] -stg_267 (store ) [ 00000000000000000000000] -stg_268 (br ) [ 00000000000000000000000] -stg_269 (br ) [ 00000111111111111111111] +stg_21 (specbitsmap ) [ 000000000000000000000] +stg_22 (specbitsmap ) [ 000000000000000000000] +stg_23 (specbitsmap ) [ 000000000000000000000] +stg_24 (specbitsmap ) [ 000000000000000000000] +stg_25 (specbitsmap ) [ 000000000000000000000] +stg_26 (specbitsmap ) [ 000000000000000000000] +stg_27 (specbitsmap ) [ 000000000000000000000] +stg_28 (specbitsmap ) [ 000000000000000000000] +stg_29 (specbitsmap ) [ 000000000000000000000] +stg_30 (specbitsmap ) [ 000000000000000000000] +stg_31 (specbitsmap ) [ 000000000000000000000] +stg_32 (specbitsmap ) [ 000000000000000000000] +stg_33 (specbitsmap ) [ 000000000000000000000] +stg_34 (specbitsmap ) [ 000000000000000000000] +stg_35 (specbitsmap ) [ 000000000000000000000] +stg_36 (specbitsmap ) [ 000000000000000000000] +stg_37 (specbitsmap ) [ 000000000000000000000] +stg_38 (specbitsmap ) [ 000000000000000000000] +stg_39 (specbitsmap ) [ 000000000000000000000] +stg_40 (spectopmodule ) [ 000000000000000000000] +LOW_THRESH_read (read ) [ 001111111111111111111] +N_BG_read (read ) [ 000000000000000000000] +n_pixels_in_bus_read (read ) [ 000000000000000000000] +sum_overP1 (alloca ) [ 001111111111111111111] +sum_overP2 (alloca ) [ 001111111111111111111] +sum_pix1 (alloca ) [ 001111111111111111111] +data_shift1 (alloca ) [ 001111111111111111111] +thresh1 (alloca ) [ 001111111111111111111] +sum_pix2 (alloca ) [ 001111111111111111111] +data_shift2 (alloca ) [ 001111111111111111111] +thresh2 (alloca ) [ 001111111111111111111] +stg_52 (specinterface ) [ 000000000000000000000] +stg_53 (specinterface ) [ 000000000000000000000] +stg_54 (specinterface ) [ 000000000000000000000] +stg_55 (specinterface ) [ 000000000000000000000] +stg_56 (specinterface ) [ 000000000000000000000] +tmp_1 (zext ) [ 001111111111111111111] +stg_58 (specinterface ) [ 000000000000000000000] +stg_59 (specinterface ) [ 000000000000000000000] +stg_60 (specinterface ) [ 000000000000000000000] +stg_61 (write ) [ 000000000000000000000] +stg_62 (write ) [ 000000000000000000000] +tmp_2 (partselect ) [ 001111111111111111111] +stg_64 (br ) [ 011000000000000000000] +i (phi ) [ 001000000000000000000] +empty (speclooptripcount) [ 000000000000000000000] +exitcond2 (icmp ) [ 001000000000000000000] +i_5 (add ) [ 011000000000000000000] +stg_69 (br ) [ 001110000000000000000] +tmp_4 (zext ) [ 000000000000000000000] +sum_pix1_addr (getelementptr ) [ 000000000000000000000] +stg_72 (store ) [ 000000000000000000000] +sum_pix2_addr (getelementptr ) [ 000000000000000000000] +stg_74 (store ) [ 000000000000000000000] +thresh1_addr (getelementptr ) [ 000000000000000000000] +stg_76 (store ) [ 000000000000000000000] +thresh2_addr (getelementptr ) [ 000000000000000000000] +stg_78 (store ) [ 000000000000000000000] +stg_79 (br ) [ 011000000000000000000] +kk (phi ) [ 000100000000000000000] +exitcond1 (icmp ) [ 000110000000000000000] +empty_7 (speclooptripcount) [ 000000000000000000000] +kk_2 (add ) [ 001110000000000000000] +stg_84 (br ) [ 000000000000000000000] +tmp_6 (bitconcatenate ) [ 000000000000000000000] +p_shl_cast (zext ) [ 000000000000000000000] +tmp_s (bitconcatenate ) [ 000000000000000000000] +p_shl1_cast (zext ) [ 000000000000000000000] +tmp_3 (add ) [ 000010000000000000000] +stg_90 (br ) [ 000110000000000000000] +i_1 (phi ) [ 000010000000000000000] +empty_8 (speclooptripcount) [ 000000000000000000000] +exitcond9 (icmp ) [ 000110000000000000000] +i_6 (add ) [ 000110000000000000000] +stg_95 (br ) [ 001110000000000000000] +tmp_8 (add ) [ 000000000000000000000] +tmp_18_cast (zext ) [ 000000000000000000000] +data_shift1_addr (getelementptr ) [ 000000000000000000000] +data_shift2_addr (getelementptr ) [ 000000000000000000000] +stg_100 (store ) [ 000000000000000000000] +stg_101 (store ) [ 000000000000000000000] +stg_102 (br ) [ 000110000000000000000] +tmp (nbreadreq ) [ 000001111111111111111] +stg_104 (br ) [ 000001111111111111111] +stg_105 (ret ) [ 000000000000000000000] +i_2 (phi ) [ 000000100000000000000] +empty_9 (speclooptripcount) [ 000000000000000000000] +exitcond8 (icmp ) [ 000001111111111111111] +i_7 (add ) [ 000001111111111111111] +stg_110 (br ) [ 000001111111111111111] +tmp_7 (zext ) [ 000000000000000000000] +sum_pix1_addr_1 (getelementptr ) [ 000000000000000000000] +stg_113 (store ) [ 000000000000000000000] +sum_pix2_addr_1 (getelementptr ) [ 000000000000000000000] +stg_115 (store ) [ 000000000000000000000] +stg_116 (br ) [ 000001111111111111111] +k (phi ) [ 000000010000000000000] +itrig (phi ) [ 000000011111111100000] +exitcond (icmp ) [ 000001111111111111111] +empty_10 (speclooptripcount) [ 000000000000000000000] +tmp_5 (add ) [ 000001111111111111111] +stg_122 (br ) [ 000001111111111111111] +i_3 (phi ) [ 000000001111010100000] +itrig_1 (phi ) [ 000001111111111111111] +empty_11 (speclooptripcount) [ 000000000000000000000] +exitcond7 (icmp ) [ 000001111111111111111] +i_9 (add ) [ 000001111111111111111] +stg_128 (br ) [ 000001111111111111111] +tmp_15 (zext ) [ 000000000111100000000] +sum_pix1_addr_3 (getelementptr ) [ 000000000100000000000] +sum_pix2_addr_3 (getelementptr ) [ 000000000100000000000] +data_shift1_addr_1 (getelementptr ) [ 000000000011000000000] +data_shift2_addr_1 (getelementptr ) [ 000000000011000000000] +empty_12 (read ) [ 000000000000000000000] +tmp_data_V_2 (extractvalue ) [ 000000000000000000000] +tmp_16 (trunc ) [ 000000000011000000000] +phitmp (partselect ) [ 000000000011000000000] +tmp_17 (sext ) [ 000000000011100000000] +sum_pix1_load_1 (load ) [ 000000000000000000000] +tmp_18 (add ) [ 000000000000000000000] +stg_143 (store ) [ 000000000000000000000] +tmp_19 (sext ) [ 000000000011100000000] +sum_pix2_load_1 (load ) [ 000000000000000000000] +tmp_20 (add ) [ 000000000000000000000] +stg_147 (store ) [ 000000000000000000000] +sum_overP1_addr (getelementptr ) [ 000000000011100000000] +stg_149 (store ) [ 000000000000000000000] +sum_overP2_addr (getelementptr ) [ 000000000011100000000] +stg_151 (store ) [ 000000000000000000000] +stg_152 (br ) [ 000001111111111111111] +kk_1 (phi ) [ 000000000011000000000] +tmp_22 (bitselect ) [ 000001111111111111111] +empty_13 (speclooptripcount) [ 000000000000000000000] +stg_156 (br ) [ 000000000000000000000] +tmp_26 (bitconcatenate ) [ 000000000000000000000] +p_shl4_cast (sext ) [ 000000000000000000000] +tmp_28 (bitconcatenate ) [ 000000000000000000000] +p_shl5_cast (sext ) [ 000000000000000000000] +tmp_31 (add ) [ 000000000000000000000] +tmp_32 (add ) [ 000000000000000000000] +tmp_45_cast (zext ) [ 000000000000000000000] +data_shift1_addr_2 (getelementptr ) [ 000000000001000000000] +data_shift2_addr_2 (getelementptr ) [ 000000000001000000000] +tmp_19_cast (sext ) [ 000000000000000000000] +stg_171 (store ) [ 000000000000000000000] +tmp_21_cast (sext ) [ 000000000000000000000] +stg_173 (store ) [ 000000000000000000000] +thresh1_addr_2 (getelementptr ) [ 000000000000100000000] +data_shift1_load (load ) [ 000000000000000000000] +extLd (sext ) [ 000000000000000000000] +tmp_27 (add ) [ 000000000000000000000] +tmp_33 (bitconcatenate ) [ 000000000000000000000] +p_shl2_cast (zext ) [ 000000000000000000000] +tmp_40 (bitconcatenate ) [ 000000000000000000000] +p_shl3_cast (zext ) [ 000000000000000000000] +tmp_41 (add ) [ 000000000000000000000] +tmp_42 (add ) [ 000000000000000000000] +tmp_49_cast (zext ) [ 000000000000000000000] +data_shift1_addr_3 (getelementptr ) [ 000000000000000000000] +data_shift2_addr_3 (getelementptr ) [ 000000000000000000000] +stg_190 (store ) [ 000000000000000000000] +data_shift2_load (load ) [ 000000000000000000000] +extLd1 (sext ) [ 000000000000000000000] +stg_193 (store ) [ 000000000000000000000] +sum_overP1_load (load ) [ 000000000000000000000] +tmp_29 (add ) [ 000000000000000000000] +stg_196 (store ) [ 000000000000000000000] +sum_overP2_load (load ) [ 000000000000000000000] +tmp_30 (add ) [ 000000000000000000000] +stg_199 (store ) [ 000000000000000000000] +kk_3 (add ) [ 000001111111111111111] +stg_201 (br ) [ 000001111111111111111] +sum_overP1_load_1 (load ) [ 000000000000000000000] +tmp_23 (add ) [ 000000000000000000000] +stg_204 (store ) [ 000000000000000000000] +sum_overP2_load_1 (load ) [ 000000000000000000000] +tmp_24 (add ) [ 000000000000010000000] +stg_207 (store ) [ 000000000000000000000] +thresh1_load (load ) [ 000000000000000000000] +tmp_25 (icmp ) [ 000001111111111111111] +stg_210 (br ) [ 000000000000000000000] +thresh2_addr_2 (getelementptr ) [ 000000000000010000000] +tmp_36 (icmp ) [ 000000000000010000000] +tmp_34 (icmp ) [ 000001111111111111111] +stg_215 (br ) [ 000001111111111111111] +stg_216 (write ) [ 000000000000000000000] +thresh2_load (load ) [ 000000000000000000000] +tmp_35 (icmp ) [ 000000000000000000000] +or_cond (and ) [ 000001111111111111111] +stg_220 (br ) [ 000001111111111111111] +stg_221 (write ) [ 000000000000000000000] +tmp_38 (bitconcatenate ) [ 000000000000000000000] +tmp_39 (or ) [ 000000000000000000000] +tmp_40_cast (zext ) [ 000000000000000000000] +stg_225 (write ) [ 000000000000000000000] +stg_226 (write ) [ 000000000000000000000] +stg_227 (br ) [ 000001111111111111111] +stg_228 (write ) [ 000000000000000000000] +tmp_37 (bitconcatenate ) [ 000000000000000000000] +tmp_38_cast (zext ) [ 000000000000000000000] +stg_231 (write ) [ 000000000000000000000] +stg_232 (br ) [ 000001111111111111111] +i_4 (phi ) [ 000000000000000010000] +empty_14 (speclooptripcount) [ 000000000000000000000] +exitcond6 (icmp ) [ 000001111111111111111] +i_8 (add ) [ 000001111111111111111] +stg_237 (br ) [ 000000000000000000000] +tmp_9 (zext ) [ 000000000000000000000] +sum_pix2_addr_2 (getelementptr ) [ 000000000000000001000] +sum_pix1_addr_2 (getelementptr ) [ 000000000000000001000] +thresh1_addr_1 (getelementptr ) [ 000000000000000001111] +thresh2_addr_1 (getelementptr ) [ 000000000000000001111] +sum_pix2_load (load ) [ 000000000000000000000] +sum_pix1_load (load ) [ 000000000000000000000] +tmp_data_V (bitconcatenate ) [ 000000000000000000000] +stg_248 (write ) [ 000000000000000000000] +tmp_10 (partselect ) [ 000000000000000000100] +tmp_11 (partselect ) [ 000000000000000000100] +sum_pixP1 (bitconcatenate ) [ 000000000000000000000] +sum_pixP1_cast (zext ) [ 000000000000000000000] +sum_pixP2 (bitconcatenate ) [ 000000000000000000000] +sum_pixP2_cast (zext ) [ 000000000000000000000] +tmp_12 (mul ) [ 000000000000000000010] +tmp_13 (mul ) [ 000000000000000000011] +stg_257 (store ) [ 000000000000000000000] +stg_258 (store ) [ 000000000000000000000] +tmp_14 (icmp ) [ 000000000000000000001] +stg_260 (br ) [ 000000000000000000000] +stg_261 (store ) [ 000000000000000000000] +stg_262 (br ) [ 000000000000000000000] +tmp_21 (icmp ) [ 000001111111111111111] +stg_264 (br ) [ 000000000000000000000] +stg_265 (store ) [ 000000000000000000000] +stg_266 (br ) [ 000000000000000000000] +stg_267 (br ) [ 000001111111111111111] @@ -2293,25 +2286,25 @@ stg_269 (br ) [ 00000111111111111111111] - + - + - + - + - + @@ -2352,7 +2345,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2373,7 +2366,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2398,7 +2391,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2423,7 +2416,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2448,7 +2441,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2473,7 +2466,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2511,7 +2504,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2523,7 +2516,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2626,7 +2619,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2651,7 +2644,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2742,7 +2735,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2755,7 +2748,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2768,7 +2761,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -2781,7 +2774,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3033,7 +3026,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3750,13 +3743,13 @@ stg_269 (br ) [ 00000111111111111111111] - + - + @@ -3768,7 +3761,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3779,20 +3772,20 @@ stg_269 (br ) [ 00000111111111111111111] - + - + - + @@ -3803,7 +3796,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3815,7 +3808,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3827,7 +3820,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3838,7 +3831,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3851,7 +3844,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3865,7 +3858,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3879,7 +3872,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3892,7 +3885,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3903,7 +3896,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3916,7 +3909,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3927,7 +3920,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3939,7 +3932,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3951,7 +3944,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3963,7 +3956,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -3975,7 +3968,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -4886,7 +4879,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -4896,7 +4889,7 @@ stg_269 (br ) [ 00000111111111111111111] - + @@ -5147,15 +5140,15 @@ stg_269 (br ) [ 00000111111111111111111] * FSMD analyzer results: - Output states: - Port: out_stream_V_data_V | {19 } - Port: out_stream_V_keep_V | {19 } - Port: out_stream_V_strb_V | {19 } - Port: out_stream_V_user_V | {19 } - Port: out_stream_V_last_V | {19 } - Port: out_stream_V_id_V | {19 } - Port: out_stream_V_dest_V | {19 } - Port: trig_data | {1 12 13 14 15 16 17 } - Port: trig_pixel | {1 } + Port: out_stream_V_data_V | {17 } + Port: out_stream_V_keep_V | {17 } + Port: out_stream_V_strb_V | {17 } + Port: out_stream_V_user_V | {17 } + Port: out_stream_V_last_V | {17 } + Port: out_stream_V_id_V | {17 } + Port: out_stream_V_dest_V | {17 } + Port: trig_data | {1 12 13 14 15 } + Port: trig_pixel | {1 13 15 } - Input state : Port: l2_trigger : in_stream_V_data_V | {5 9 } Port: l2_trigger : in_stream_V_keep_V | {5 9 } @@ -5172,20 +5165,20 @@ stg_269 (br ) [ 00000111111111111111111] State 2 exitcond2 : 1 i_5 : 1 - stg_71 : 2 + stg_69 : 2 tmp_4 : 1 sum_pix1_addr : 2 - stg_74 : 3 + stg_72 : 3 sum_pix2_addr : 2 - stg_76 : 3 + stg_74 : 3 thresh1_addr : 2 - stg_78 : 3 + stg_76 : 3 thresh2_addr : 2 - stg_80 : 3 + stg_78 : 3 State 3 exitcond1 : 1 kk_2 : 1 - stg_86 : 2 + stg_84 : 2 tmp_6 : 1 p_shl_cast : 2 tmp_s : 1 @@ -5194,31 +5187,31 @@ stg_269 (br ) [ 00000111111111111111111] State 4 exitcond9 : 1 i_6 : 1 - stg_97 : 2 + stg_95 : 2 tmp_8 : 1 tmp_18_cast : 2 data_shift1_addr : 3 data_shift2_addr : 3 - stg_102 : 4 - stg_103 : 4 + stg_100 : 4 + stg_101 : 4 State 5 State 6 exitcond8 : 1 i_7 : 1 - stg_112 : 2 + stg_110 : 2 tmp_7 : 1 sum_pix1_addr_1 : 2 - stg_115 : 3 + stg_113 : 3 sum_pix2_addr_1 : 2 - stg_117 : 3 + stg_115 : 3 State 7 exitcond : 1 tmp_5 : 1 - stg_124 : 2 + stg_122 : 2 State 8 exitcond7 : 1 i_9 : 1 - stg_130 : 2 + stg_128 : 2 tmp_15 : 1 sum_pix1_addr_3 : 2 sum_pix1_load_1 : 3 @@ -5229,15 +5222,15 @@ stg_269 (br ) [ 00000111111111111111111] phitmp : 1 tmp_17 : 2 tmp_18 : 3 - stg_145 : 4 + stg_143 : 4 tmp_19 : 2 tmp_20 : 3 - stg_149 : 4 + stg_147 : 4 + stg_149 : 1 stg_151 : 1 - stg_153 : 1 State 10 tmp_22 : 1 - stg_158 : 2 + stg_156 : 2 tmp_26 : 1 p_shl4_cast : 2 tmp_28 : 1 @@ -5249,8 +5242,8 @@ stg_269 (br ) [ 00000111111111111111111] data_shift2_addr_2 : 6 data_shift1_load : 7 data_shift2_load : 7 + stg_171 : 1 stg_173 : 1 - stg_175 : 1 thresh1_load : 1 State 11 extLd : 1 @@ -5263,39 +5256,37 @@ stg_269 (br ) [ 00000111111111111111111] tmp_49_cast : 5 data_shift1_addr_3 : 6 data_shift2_addr_3 : 6 - stg_192 : 7 + stg_190 : 7 extLd1 : 1 - stg_195 : 7 + stg_193 : 7 tmp_29 : 2 - stg_198 : 3 + stg_196 : 3 tmp_30 : 2 - stg_201 : 3 + stg_199 : 3 State 12 tmp_23 : 1 - stg_206 : 2 + stg_204 : 2 tmp_24 : 1 - stg_209 : 2 + stg_207 : 2 tmp_25 : 2 - stg_212 : 3 + stg_210 : 3 thresh2_load : 1 - stg_217 : 1 + stg_215 : 1 State 13 tmp_35 : 1 or_cond : 2 - stg_222 : 2 - State 14 - State 15 + stg_220 : 2 tmp_39 : 1 tmp_40_cast : 1 - stg_228 : 2 - State 16 - State 17 + stg_225 : 2 + State 14 + State 15 tmp_38_cast : 1 - stg_233 : 2 - State 18 + stg_231 : 2 + State 16 exitcond6 : 1 i_8 : 1 - stg_239 : 2 + stg_237 : 2 tmp_9 : 1 sum_pix2_addr_2 : 2 sum_pix2_load : 3 @@ -5303,20 +5294,20 @@ stg_269 (br ) [ 00000111111111111111111] sum_pix1_load : 3 thresh1_addr_1 : 2 thresh2_addr_1 : 2 - State 19 + State 17 tmp_data_V : 1 - stg_250 : 2 + stg_248 : 2 tmp_10 : 1 tmp_11 : 1 - State 20 + State 18 sum_pixP1_cast : 1 sum_pixP2_cast : 1 tmp_12 : 2 tmp_13 : 2 - State 21 - stg_262 : 1 - State 22 - stg_266 : 1 + State 19 + stg_260 : 1 + State 20 + stg_264 : 1 ============================================================ @@ -5373,8 +5364,8 @@ stg_269 (br ) [ 00000111111111111111111] | | empty_12_read_fu_246 | 0 | 0 | 0 | |----------|----------------------------------|---------|---------|---------| | | grp_write_fu_210 | 0 | 0 | 0 | -| write | stg_64_write_fu_218 | 0 | 0 | 0 | -| | stg_250_write_fu_265 | 0 | 0 | 0 | +| write | grp_write_fu_218 | 0 | 0 | 0 | +| | stg_248_write_fu_265 | 0 | 0 | 0 | |----------|----------------------------------|---------|---------|---------| | nbreadreq| tmp_nbreadreq_fu_226 | 0 | 0 | 0 | |----------|----------------------------------|---------|---------|---------| @@ -5508,7 +5499,8 @@ Memories: |-------------------|------|------|------|--------||---------||---------| | Comp | Pin | Size | BW | S x BW || Delay || LUT | |-------------------|------|------|------|--------||---------||---------| -| grp_write_fu_210 | p2 | 4 | 16 | 64 || 16 | +| grp_write_fu_210 | p2 | 2 | 1 | 2 | +| grp_write_fu_218 | p2 | 3 | 16 | 48 || 16 | | grp_access_fu_302 | p0 | 6 | 11 | 66 || 11 | | grp_access_fu_302 | p1 | 2 | 32 | 64 || 32 | | grp_access_fu_314 | p0 | 6 | 11 | 66 || 11 | @@ -5530,7 +5522,7 @@ Memories: | itrig_1_reg_587 | p0 | 2 | 32 | 64 || 32 | | kk_1_reg_610 | p0 | 2 | 4 | 8 || 4 | |-------------------|------|------|------|--------||---------||---------| -| Total | | | | 1248 || 28.763 || 419 | +| Total | | | | 1234 || 30.074 || 419 | |-------------------|------|------|------|--------||---------||---------| @@ -5541,8 +5533,8 @@ Memories: +-----------+--------+--------+--------+--------+--------+ | Function | - | 4 | - | 0 | 429 | | Memory | 58 | - | - | 0 | 0 | -|Multiplexer| - | - | 28 | - | 419 | +|Multiplexer| - | - | 30 | - | 419 | | Register | - | - | - | 814 | - | +-----------+--------+--------+--------+--------+--------+ -| Total | 58 | 4 | 28 | 814 | 848 | +| Total | 58 | 4 | 30 | 814 | 848 | +-----------+--------+--------+--------+--------+--------+ diff --git a/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.rpt.xml b/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.rpt.xml index 0eb7057..14aab71 100644 --- a/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.rpt.xml +++ b/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.rpt.xml @@ -1,7 +1,7 @@
-Fri Apr 13 19:40:42 2018 +Wed Apr 18 11:09:40 2018 2016.2 (Build 1577090 on Thu Jun 02 16:59:10 MDT 2016) l2_trigger @@ -38,10 +38,10 @@ 0, 32767, 1, -, -, 0 ~ 32767, no 16, 262152, 2 ~ 32769, -, -, 8, no 0, 32767, 1, -, -, 0 ~ 32767, no -?, ?, 260 ~ 88274558, -, -, ?, no +?, ?, 260 ~ 84080382, -, -, ?, no 0, 32767, 1, -, -, 0 ~ 32767, no -256, 88077952, 2 ~ 688109, -, -, 128, no -0, 688107, 18 ~ 21, -, -, 0 ~ 32767, no +256, 83883776, 2 ~ 655342, -, -, 128, no +0, 655340, 18 ~ 20, -, -, 0 ~ 32767, no 14, 14, 2, -, -, 7, no 0, 163835, 5, -, -, 0 ~ 32767, no @@ -60,8 +60,8 @@ -, -, -, - 0, -, 110, 152 58, -, 0, 0 --, -, -, 528 --, -, 636, - +-, -, -, 560 +-, -, 634, - 530, 400, 157200, 78600 10, 1, ~0, 1 @@ -137,7 +137,7 @@ Name, LUT, Input Size, Bits, Total Bits -18, 23, 1, 23 +18, 21, 1, 211, 2, 1, 214, 5, 14, 7017, 4, 17, 68 @@ -167,13 +167,14 @@ 32, 4, 32, 12811, 4, 11, 4432, 4, 32, 128 -32, 5, 32, 160 +32, 3, 32, 96 +32, 4, 32, 128
 Name, FF, LUT, Bits, Const Bits32, 0, 32, 0 -22, 0, 22, 0 +20, 0, 20, 01, 0, 1, 014, 0, 14, 014, 0, 14, 0 diff --git a/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.sched.rpt b/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.sched.rpt index 40a753c..d336879 100644 --- a/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.sched.rpt +++ b/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.sched.rpt @@ -3,7 +3,7 @@ ================================================================ == Vivado HLS Report for 'l2_trigger' ================================================================ -* Date: Fri Apr 13 19:40:42 2018 +* Date: Wed Apr 18 11:09:39 2018 * Version: 2016.2 (Build 1577090 on Thu Jun 02 16:59:10 MDT 2016) * Project: l2_trigger @@ -44,10 +44,10 @@ |- Loop 1 | 0| 32767| 1| -| -| 0 ~ 32767 | no | |- Loop 2 | 16| 262152| 2 ~ 32769 | -| -| 8| no | | + Loop 2.1 | 0| 32767| 1| -| -| 0 ~ 32767 | no | - |- Loop 3 | ?| ?| 260 ~ 88274558 | -| -| ?| no | + |- Loop 3 | ?| ?| 260 ~ 84080382 | -| -| ?| no | | + Loop 3.1 | 0| 32767| 1| -| -| 0 ~ 32767 | no | - | + Loop 3.2 | 256| 88077952| 2 ~ 688109 | -| -| 128| no | - | ++ Loop 3.2.1 | 0| 688107| 18 ~ 21 | -| -| 0 ~ 32767 | no | + | + Loop 3.2 | 256| 83883776| 2 ~ 655342 | -| -| 128| no | + | ++ Loop 3.2.1 | 0| 655340| 18 ~ 20 | -| -| 0 ~ 32767 | no | | +++ Loop 3.2.1.1 | 14| 14| 2| -| -| 7| no | | + Loop 3.3 | 0| 163835| 5| -| -| 0 ~ 32767 | no | +---------------------+-----+----------+----------------+-----------+-----------+-----------+----------+ @@ -78,7 +78,7 @@ IsGatedGlobalClock: 0 ============================================================ + Verbose Summary: Schedule ============================================================ -* Number of FSM states: 22 +* Number of FSM states: 20 * Pipeline: 0 * Dataflow Pipeline: 0 @@ -101,7 +101,7 @@ IsGatedGlobalClock: 0 6 / (!exitcond8) 7 --> 8 / (!exitcond) - 18 / (exitcond) + 16 / (exitcond) 8 --> 7 / (exitcond7) 9 / (!exitcond7) @@ -115,90 +115,86 @@ IsGatedGlobalClock: 0 12 --> 13 / (!tmp_25) 8 / (tmp_25 & !tmp_34) - 16 / (tmp_25 & tmp_34) + 15 / (tmp_25 & tmp_34) 13 --> 8 / (!or_cond) 14 / (or_cond) 14 --> - 15 / true + 8 / true 15 --> 8 / true 16 --> - 17 / true + 5 / (exitcond6) + 17 / (!exitcond6) 17 --> - 8 / true + 18 / true 18 --> - 5 / (exitcond6) - 19 / (!exitcond6) + 19 / true 19 --> 20 / true 20 --> - 21 / true -21 --> - 22 / true -22 --> - 18 / true + 16 / true * FSM state operations: : 1.31ns -ST_1: stg_23 [1/1] 0.00ns +ST_1: stg_21 [1/1] 0.00ns arrayctor.loop1.preheader:0 call void (...)* @_ssdm_op_SpecBitsMap(i32* %in_stream_V_data_V), !map !102 -ST_1: stg_24 [1/1] 0.00ns +ST_1: stg_22 [1/1] 0.00ns arrayctor.loop1.preheader:1 call void (...)* @_ssdm_op_SpecBitsMap(i4* %in_stream_V_keep_V), !map !106 -ST_1: stg_25 [1/1] 0.00ns +ST_1: stg_23 [1/1] 0.00ns arrayctor.loop1.preheader:2 call void (...)* @_ssdm_op_SpecBitsMap(i4* %in_stream_V_strb_V), !map !110 -ST_1: stg_26 [1/1] 0.00ns +ST_1: stg_24 [1/1] 0.00ns arrayctor.loop1.preheader:3 call void (...)* @_ssdm_op_SpecBitsMap(i2* %in_stream_V_user_V), !map !114 -ST_1: stg_27 [1/1] 0.00ns +ST_1: stg_25 [1/1] 0.00ns arrayctor.loop1.preheader:4 call void (...)* @_ssdm_op_SpecBitsMap(i1* %in_stream_V_last_V), !map !118 -ST_1: stg_28 [1/1] 0.00ns +ST_1: stg_26 [1/1] 0.00ns arrayctor.loop1.preheader:5 call void (...)* @_ssdm_op_SpecBitsMap(i5* %in_stream_V_id_V), !map !122 -ST_1: stg_29 [1/1] 0.00ns +ST_1: stg_27 [1/1] 0.00ns arrayctor.loop1.preheader:6 call void (...)* @_ssdm_op_SpecBitsMap(i6* %in_stream_V_dest_V), !map !126 -ST_1: stg_30 [1/1] 0.00ns +ST_1: stg_28 [1/1] 0.00ns arrayctor.loop1.preheader:7 call void (...)* @_ssdm_op_SpecBitsMap(i64* %out_stream_V_data_V), !map !130 -ST_1: stg_31 [1/1] 0.00ns +ST_1: stg_29 [1/1] 0.00ns arrayctor.loop1.preheader:8 call void (...)* @_ssdm_op_SpecBitsMap(i8* %out_stream_V_keep_V), !map !134 -ST_1: stg_32 [1/1] 0.00ns +ST_1: stg_30 [1/1] 0.00ns arrayctor.loop1.preheader:9 call void (...)* @_ssdm_op_SpecBitsMap(i8* %out_stream_V_strb_V), !map !138 -ST_1: stg_33 [1/1] 0.00ns +ST_1: stg_31 [1/1] 0.00ns arrayctor.loop1.preheader:10 call void (...)* @_ssdm_op_SpecBitsMap(i2* %out_stream_V_user_V), !map !142 -ST_1: stg_34 [1/1] 0.00ns +ST_1: stg_32 [1/1] 0.00ns arrayctor.loop1.preheader:11 call void (...)* @_ssdm_op_SpecBitsMap(i1* %out_stream_V_last_V), !map !146 -ST_1: stg_35 [1/1] 0.00ns +ST_1: stg_33 [1/1] 0.00ns arrayctor.loop1.preheader:12 call void (...)* @_ssdm_op_SpecBitsMap(i5* %out_stream_V_id_V), !map !150 -ST_1: stg_36 [1/1] 0.00ns +ST_1: stg_34 [1/1] 0.00ns arrayctor.loop1.preheader:13 call void (...)* @_ssdm_op_SpecBitsMap(i6* %out_stream_V_dest_V), !map !154 -ST_1: stg_37 [1/1] 0.00ns +ST_1: stg_35 [1/1] 0.00ns arrayctor.loop1.preheader:14 call void (...)* @_ssdm_op_SpecBitsMap(i16 %n_pixels_in_bus), !map !158 -ST_1: stg_38 [1/1] 0.00ns +ST_1: stg_36 [1/1] 0.00ns arrayctor.loop1.preheader:15 call void (...)* @_ssdm_op_SpecBitsMap(i8 %N_BG), !map !164 -ST_1: stg_39 [1/1] 0.00ns +ST_1: stg_37 [1/1] 0.00ns arrayctor.loop1.preheader:16 call void (...)* @_ssdm_op_SpecBitsMap(i32 %LOW_THRESH), !map !168 -ST_1: stg_40 [1/1] 0.00ns +ST_1: stg_38 [1/1] 0.00ns arrayctor.loop1.preheader:17 call void (...)* @_ssdm_op_SpecBitsMap(i32* %trig_data), !map !172 -ST_1: stg_41 [1/1] 0.00ns +ST_1: stg_39 [1/1] 0.00ns arrayctor.loop1.preheader:18 call void (...)* @_ssdm_op_SpecBitsMap(i32* %trig_pixel), !map !176 -ST_1: stg_42 [1/1] 0.00ns +ST_1: stg_40 [1/1] 0.00ns arrayctor.loop1.preheader:19 call void (...)* @_ssdm_op_SpecTopModule([11 x i8]* @l2_trigger_str) nounwind ST_1: LOW_THRESH_read [1/1] 1.00ns @@ -234,43 +230,43 @@ arrayctor.loop1.preheader:29 %data_shift2 = alloca [9216 x i17], align 4 ST_1: thresh2 [1/1] 0.00ns arrayctor.loop1.preheader:30 %thresh2 = alloca [1152 x i32], align 16 -ST_1: stg_54 [1/1] 0.00ns +ST_1: stg_52 [1/1] 0.00ns arrayctor.loop1.preheader:31 call void (...)* @_ssdm_op_SpecInterface(i32* %in_stream_V_data_V, i4* %in_stream_V_keep_V, i4* %in_stream_V_strb_V, i2* %in_stream_V_user_V, i1* %in_stream_V_last_V, i5* %in_stream_V_id_V, i6* %in_stream_V_dest_V, [5 x i8]* @p_str1804, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind -ST_1: stg_55 [1/1] 0.00ns +ST_1: stg_53 [1/1] 0.00ns arrayctor.loop1.preheader:32 call void (...)* @_ssdm_op_SpecInterface(i32* %trig_data, [8 x i8]* @p_str1806, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind -ST_1: stg_56 [1/1] 0.00ns +ST_1: stg_54 [1/1] 0.00ns arrayctor.loop1.preheader:33 call void (...)* @_ssdm_op_SpecInterface(i32* %trig_pixel, [8 x i8]* @p_str1806, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind -ST_1: stg_57 [1/1] 0.00ns +ST_1: stg_55 [1/1] 0.00ns arrayctor.loop1.preheader:34 call void (...)* @_ssdm_op_SpecInterface(i64* %out_stream_V_data_V, i8* %out_stream_V_keep_V, i8* %out_stream_V_strb_V, i2* %out_stream_V_user_V, i1* %out_stream_V_last_V, i5* %out_stream_V_id_V, i6* %out_stream_V_dest_V, [5 x i8]* @p_str1804, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind -ST_1: stg_58 [1/1] 0.00ns +ST_1: stg_56 [1/1] 0.00ns arrayctor.loop1.preheader:35 call void (...)* @_ssdm_op_SpecInterface(i16 %n_pixels_in_bus, [10 x i8]* @p_str1807, i32 0, i32 0, i32 0, i32 0, [9 x i8]* @p_str1808, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind ST_1: tmp_1 [1/1] 0.00ns arrayctor.loop1.preheader:36 %tmp_1 = zext i8 %N_BG_read to i32 -ST_1: stg_60 [1/1] 0.00ns +ST_1: stg_58 [1/1] 0.00ns arrayctor.loop1.preheader:37 call void (...)* @_ssdm_op_SpecInterface(i8 %N_BG, [10 x i8]* @p_str1807, i32 0, i32 0, i32 0, i32 0, [9 x i8]* @p_str1808, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind -ST_1: stg_61 [1/1] 0.00ns +ST_1: stg_59 [1/1] 0.00ns arrayctor.loop1.preheader:38 call void (...)* @_ssdm_op_SpecInterface(i32 %LOW_THRESH, [10 x i8]* @p_str1807, i32 0, i32 0, i32 0, i32 0, [9 x i8]* @p_str1808, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind -ST_1: stg_62 [1/1] 0.00ns +ST_1: stg_60 [1/1] 0.00ns arrayctor.loop1.preheader:39 call void (...)* @_ssdm_op_SpecInterface(i32 0, [10 x i8]* @p_str1807, i32 0, i32 0, i32 0, i32 0, [9 x i8]* @p_str1808, [1 x i8]* @p_str1805, [1 x i8]* @p_str1805, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1805) nounwind -ST_1: stg_63 [1/1] 0.00ns +ST_1: stg_61 [1/1] 0.00ns arrayctor.loop1.preheader:40 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 0) -ST_1: stg_64 [1/1] 0.00ns +ST_1: stg_62 [1/1] 0.00ns arrayctor.loop1.preheader:41 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_pixel, i32 0) ST_1: tmp_2 [1/1] 0.00ns arrayctor.loop1.preheader:42 %tmp_2 = call i15 @_ssdm_op_PartSelect.i15.i16.i32.i32(i16 %n_pixels_in_bus_read, i32 1, i32 15) -ST_1: stg_66 [1/1] 1.31ns +ST_1: stg_64 [1/1] 1.31ns arrayctor.loop1.preheader:43 br label %0 @@ -287,7 +283,7 @@ ST_2: exitcond2 [1/1] 1.85ns ST_2: i_5 [1/1] 1.60ns :3 %i_5 = add i15 %i, 1 -ST_2: stg_71 [1/1] 1.31ns +ST_2: stg_69 [1/1] 1.31ns :4 br i1 %exitcond2, label %.preheader84, label %1 ST_2: tmp_4 [1/1] 0.00ns @@ -296,28 +292,28 @@ ST_2: tmp_4 [1/1] 0.00ns ST_2: sum_pix1_addr [1/1] 0.00ns :1 %sum_pix1_addr = getelementptr inbounds [1152 x i32]* %sum_pix1, i64 0, i64 %tmp_4 -ST_2: stg_74 [1/1] 2.38ns +ST_2: stg_72 [1/1] 2.38ns :2 store i32 0, i32* %sum_pix1_addr, align 4 ST_2: sum_pix2_addr [1/1] 0.00ns :3 %sum_pix2_addr = getelementptr inbounds [1152 x i32]* %sum_pix2, i64 0, i64 %tmp_4 -ST_2: stg_76 [1/1] 2.38ns +ST_2: stg_74 [1/1] 2.38ns :4 store i32 0, i32* %sum_pix2_addr, align 4 ST_2: thresh1_addr [1/1] 0.00ns :5 %thresh1_addr = getelementptr inbounds [1152 x i32]* %thresh1, i64 0, i64 %tmp_4 -ST_2: stg_78 [1/1] 2.38ns +ST_2: stg_76 [1/1] 2.38ns :6 store i32 25500, i32* %thresh1_addr, align 4 ST_2: thresh2_addr [1/1] 0.00ns :7 %thresh2_addr = getelementptr inbounds [1152 x i32]* %thresh2, i64 0, i64 %tmp_4 -ST_2: stg_80 [1/1] 2.38ns +ST_2: stg_78 [1/1] 2.38ns :8 store i32 25500, i32* %thresh2_addr, align 4 -ST_2: stg_81 [1/1] 0.00ns +ST_2: stg_79 [1/1] 0.00ns :9 br label %0 @@ -334,7 +330,7 @@ ST_3: empty_7 [1/1] 0.00ns ST_3: kk_2 [1/1] 0.70ns .preheader84:3 %kk_2 = add i4 %kk, 1 -ST_3: stg_86 [1/1] 0.00ns +ST_3: stg_84 [1/1] 0.00ns .preheader84:4 br i1 %exitcond1, label %.preheader82, label %.preheader83.preheader ST_3: tmp_6 [1/1] 0.00ns @@ -352,7 +348,7 @@ ST_3: p_shl1_cast [1/1] 0.00ns ST_3: tmp_3 [1/1] 1.60ns .preheader83.preheader:4 %tmp_3 = add i15 %p_shl1_cast, %p_shl_cast -ST_3: stg_92 [1/1] 1.31ns +ST_3: stg_90 [1/1] 1.31ns .preheader83.preheader:5 br label %.preheader83 @@ -369,7 +365,7 @@ ST_4: exitcond9 [1/1] 1.85ns ST_4: i_6 [1/1] 1.60ns .preheader83:3 %i_6 = add i15 %i_1, 1 -ST_4: stg_97 [1/1] 0.00ns +ST_4: stg_95 [1/1] 0.00ns .preheader83:4 br i1 %exitcond9, label %.preheader84, label %2 ST_4: tmp_8 [1/1] 1.60ns @@ -384,13 +380,13 @@ ST_4: data_shift1_addr [1/1] 0.00ns ST_4: data_shift2_addr [1/1] 0.00ns :3 %data_shift2_addr = getelementptr [9216 x i17]* %data_shift2, i64 0, i64 %tmp_18_cast -ST_4: stg_102 [1/1] 2.38ns +ST_4: stg_100 [1/1] 2.38ns :4 store i17 0, i17* %data_shift1_addr, align 4 -ST_4: stg_103 [1/1] 2.38ns +ST_4: stg_101 [1/1] 2.38ns :5 store i17 0, i17* %data_shift2_addr, align 4 -ST_4: stg_104 [1/1] 0.00ns +ST_4: stg_102 [1/1] 0.00ns :6 br label %.preheader83 @@ -398,10 +394,10 @@ ST_4: stg_104 [1/1] 0.00ns ST_5: tmp [1/1] 0.00ns .preheader82:0 %tmp = call i1 @_ssdm_op_NbReadReq.axis.i32P.i4P.i4P.i2P.i1P.i5P.i6P(i32* %in_stream_V_data_V, i4* %in_stream_V_keep_V, i4* %in_stream_V_strb_V, i2* %in_stream_V_user_V, i1* %in_stream_V_last_V, i5* %in_stream_V_id_V, i6* %in_stream_V_dest_V, i32 1) -ST_5: stg_106 [1/1] 1.31ns +ST_5: stg_104 [1/1] 1.31ns .preheader82:1 br i1 %tmp, label %.preheader81, label %14 -ST_5: stg_107 [1/1] 0.00ns +ST_5: stg_105 [1/1] 0.00ns :0 ret void @@ -418,7 +414,7 @@ ST_6: exitcond8 [1/1] 1.85ns ST_6: i_7 [1/1] 1.60ns .preheader81:3 %i_7 = add i15 %i_2, 1 -ST_6: stg_112 [1/1] 1.31ns +ST_6: stg_110 [1/1] 1.31ns .preheader81:4 br i1 %exitcond8, label %.preheader80, label %3 ST_6: tmp_7 [1/1] 0.00ns @@ -427,16 +423,16 @@ ST_6: tmp_7 [1/1] 0.00ns ST_6: sum_pix1_addr_1 [1/1] 0.00ns :1 %sum_pix1_addr_1 = getelementptr inbounds [1152 x i32]* %sum_pix1, i64 0, i64 %tmp_7 -ST_6: stg_115 [1/1] 2.38ns +ST_6: stg_113 [1/1] 2.38ns :2 store i32 0, i32* %sum_pix1_addr_1, align 4 ST_6: sum_pix2_addr_1 [1/1] 0.00ns :3 %sum_pix2_addr_1 = getelementptr inbounds [1152 x i32]* %sum_pix2, i64 0, i64 %tmp_7 -ST_6: stg_117 [1/1] 2.38ns +ST_6: stg_115 [1/1] 2.38ns :4 store i32 0, i32* %sum_pix2_addr_1, align 4 -ST_6: stg_118 [1/1] 0.00ns +ST_6: stg_116 [1/1] 0.00ns :5 br label %.preheader81 @@ -456,7 +452,7 @@ ST_7: empty_10 [1/1] 0.00ns ST_7: tmp_5 [1/1] 1.40ns .preheader80:4 %tmp_5 = add i8 %k, 1 -ST_7: stg_124 [1/1] 1.31ns +ST_7: stg_122 [1/1] 1.31ns .preheader80:5 br i1 %exitcond, label %.preheader, label %.preheader79 @@ -476,7 +472,7 @@ ST_8: exitcond7 [1/1] 1.85ns ST_8: i_9 [1/1] 1.60ns .preheader79:4 %i_9 = add i15 %i_3, 1 -ST_8: stg_130 [1/1] 0.00ns +ST_8: stg_128 [1/1] 0.00ns .preheader79:5 br i1 %exitcond7, label %.preheader80, label %_ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit ST_8: tmp_15 [1/1] 0.00ns @@ -523,7 +519,7 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:9 %sum_pix1_load_ ST_9: tmp_18 [1/1] 2.00ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:10 %tmp_18 = add i32 %sum_pix1_load_1, %tmp_17 -ST_9: stg_145 [1/1] 2.38ns +ST_9: stg_143 [1/1] 2.38ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:11 store i32 %tmp_18, i32* %sum_pix1_addr_3, align 4 ST_9: tmp_19 [1/1] 0.00ns @@ -535,22 +531,22 @@ _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:14 %sum_pix2_load ST_9: tmp_20 [1/1] 2.00ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:15 %tmp_20 = add i32 %sum_pix2_load_1, %tmp_19 -ST_9: stg_149 [1/1] 2.38ns +ST_9: stg_147 [1/1] 2.38ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:16 store i32 %tmp_20, i32* %sum_pix2_addr_3, align 4 ST_9: sum_overP1_addr [1/1] 0.00ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:17 %sum_overP1_addr = getelementptr inbounds [1152 x i32]* %sum_overP1, i64 0, i64 %tmp_15 -ST_9: stg_151 [1/1] 2.38ns +ST_9: stg_149 [1/1] 2.38ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:18 store i32 0, i32* %sum_overP1_addr, align 4 ST_9: sum_overP2_addr [1/1] 0.00ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:19 %sum_overP2_addr = getelementptr inbounds [1152 x i32]* %sum_overP2, i64 0, i64 %tmp_15 -ST_9: stg_153 [1/1] 2.38ns +ST_9: stg_151 [1/1] 2.38ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:20 store i32 0, i32* %sum_overP2_addr, align 4 -ST_9: stg_154 [1/1] 1.31ns +ST_9: stg_152 [1/1] 1.31ns _ZrsILi32ELb1EE11ap_int_baseIXT_EXT0_EXleT_Li64EEERKS1_i.exit:21 br label %4 @@ -564,7 +560,7 @@ ST_10: tmp_22 [1/1] 0.00ns ST_10: empty_13 [1/1] 0.00ns :2 %empty_13 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 7, i64 7, i64 7) -ST_10: stg_158 [1/1] 0.00ns +ST_10: stg_156 [1/1] 0.00ns :3 br i1 %tmp_22, label %6, label %5 ST_10: tmp_26 [1/1] 0.00ns @@ -609,13 +605,13 @@ ST_10: sum_overP2_load [2/2] 2.38ns ST_10: tmp_19_cast [1/1] 0.00ns :0 %tmp_19_cast = sext i16 %tmp_16 to i17 -ST_10: stg_173 [1/1] 2.38ns +ST_10: stg_171 [1/1] 2.38ns :1 store i17 %tmp_19_cast, i17* %data_shift1_addr_1, align 4 ST_10: tmp_21_cast [1/1] 0.00ns :2 %tmp_21_cast = sext i16 %phitmp to i17 -ST_10: stg_175 [1/1] 2.38ns +ST_10: stg_173 [1/1] 2.38ns :3 store i17 %tmp_21_cast, i17* %data_shift2_addr_1, align 4 ST_10: sum_overP1_load_1 [2/2] 2.38ns @@ -668,7 +664,7 @@ ST_11: data_shift1_addr_3 [1/1] 0.00ns ST_11: data_shift2_addr_3 [1/1] 0.00ns :20 %data_shift2_addr_3 = getelementptr [9216 x i17]* %data_shift2, i64 0, i64 %tmp_49_cast -ST_11: stg_192 [1/1] 2.38ns +ST_11: stg_190 [1/1] 2.38ns :21 store i17 %data_shift1_load, i17* %data_shift1_addr_3, align 4 ST_11: data_shift2_load [1/2] 2.38ns @@ -677,7 +673,7 @@ ST_11: data_shift2_load [1/2] 2.38ns ST_11: extLd1 [1/1] 0.00ns :23 %extLd1 = sext i17 %data_shift2_load to i32 -ST_11: stg_195 [1/1] 2.38ns +ST_11: stg_193 [1/1] 2.38ns :24 store i17 %data_shift2_load, i17* %data_shift2_addr_3, align 4 ST_11: sum_overP1_load [1/2] 2.38ns @@ -686,7 +682,7 @@ ST_11: sum_overP1_load [1/2] 2.38ns ST_11: tmp_29 [1/1] 2.00ns :26 %tmp_29 = add i32 %sum_overP1_load, %extLd -ST_11: stg_198 [1/1] 2.38ns +ST_11: stg_196 [1/1] 2.38ns :27 store i32 %tmp_29, i32* %sum_overP1_addr, align 4 ST_11: sum_overP2_load [1/2] 2.38ns @@ -695,13 +691,13 @@ ST_11: sum_overP2_load [1/2] 2.38ns ST_11: tmp_30 [1/1] 2.00ns :29 %tmp_30 = add i32 %sum_overP2_load, %extLd1 -ST_11: stg_201 [1/1] 2.38ns +ST_11: stg_199 [1/1] 2.38ns :30 store i32 %tmp_30, i32* %sum_overP2_addr, align 4 ST_11: kk_3 [1/1] 0.70ns :31 %kk_3 = add i4 %kk_1, -1 -ST_11: stg_203 [1/1] 0.00ns +ST_11: stg_201 [1/1] 0.00ns :32 br label %4 @@ -712,7 +708,7 @@ ST_12: sum_overP1_load_1 [1/2] 2.38ns ST_12: tmp_23 [1/1] 2.00ns :5 %tmp_23 = add i32 %tmp_17, %sum_overP1_load_1 -ST_12: stg_206 [1/1] 2.38ns +ST_12: stg_204 [1/1] 2.38ns :6 store i32 %tmp_23, i32* %sum_overP1_addr, align 4 ST_12: sum_overP2_load_1 [1/2] 2.38ns @@ -721,7 +717,7 @@ ST_12: sum_overP2_load_1 [1/2] 2.38ns ST_12: tmp_24 [1/1] 2.00ns :8 %tmp_24 = add i32 %tmp_19, %sum_overP2_load_1 -ST_12: stg_209 [1/1] 2.38ns +ST_12: stg_207 [1/1] 2.38ns :9 store i32 %tmp_24, i32* %sum_overP2_addr, align 4 ST_12: thresh1_load [1/2] 2.38ns @@ -730,7 +726,7 @@ ST_12: thresh1_load [1/2] 2.38ns ST_12: tmp_25 [1/1] 2.12ns :12 %tmp_25 = icmp ugt i32 %tmp_23, %thresh1_load -ST_12: stg_212 [1/1] 0.00ns +ST_12: stg_210 [1/1] 0.00ns :13 br i1 %tmp_25, label %7, label %9 ST_12: thresh2_addr_2 [1/1] 0.00ns @@ -745,10 +741,10 @@ ST_12: tmp_36 [1/1] 1.04ns ST_12: tmp_34 [1/1] 1.04ns :0 %tmp_34 = icmp eq i32 %itrig_1, 0 -ST_12: stg_217 [1/1] 0.00ns +ST_12: stg_215 [1/1] 0.00ns :1 br i1 %tmp_34, label %8, label %.preheader79 -ST_12: stg_218 [1/1] 0.00ns +ST_12: stg_216 [1/1] 0.00ns :0 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 1) @@ -762,166 +758,162 @@ ST_13: tmp_35 [1/1] 2.12ns ST_13: or_cond [1/1] 1.15ns :4 %or_cond = and i1 %tmp_35, %tmp_36 -ST_13: stg_222 [1/1] 0.00ns +ST_13: stg_220 [1/1] 0.00ns :5 br i1 %or_cond, label %10, label %.preheader79 -ST_13: stg_223 [1/1] 0.00ns +ST_13: stg_221 [1/1] 0.00ns :0 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 1) - - : 0.00ns -ST_14: stg_224 [1/1] 0.00ns -:1 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 0) - - - : 0.00ns -ST_15: tmp_38 [1/1] 0.00ns +ST_13: tmp_38 [1/1] 0.00ns :2 %tmp_38 = call i16 @_ssdm_op_BitConcatenate.i16.i15.i1(i15 %i_3, i1 false) -ST_15: tmp_39 [1/1] 0.00ns +ST_13: tmp_39 [1/1] 0.00ns :3 %tmp_39 = or i16 %tmp_38, 1 -ST_15: tmp_40_cast [1/1] 0.00ns +ST_13: tmp_40_cast [1/1] 0.00ns :4 %tmp_40_cast = zext i16 %tmp_39 to i32 -ST_15: stg_228 [1/1] 0.00ns -:5 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 %tmp_40_cast) +ST_13: stg_225 [1/1] 0.00ns +:5 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_pixel, i32 %tmp_40_cast) + + + : 0.00ns +ST_14: stg_226 [1/1] 0.00ns +:1 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 0) -ST_15: stg_229 [1/1] 0.00ns +ST_14: stg_227 [1/1] 0.00ns :6 br label %.preheader79 - : 0.00ns -ST_16: stg_230 [1/1] 0.00ns + : 0.00ns +ST_15: stg_228 [1/1] 0.00ns :1 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 0) - - : 0.00ns -ST_17: tmp_37 [1/1] 0.00ns +ST_15: tmp_37 [1/1] 0.00ns :2 %tmp_37 = call i16 @_ssdm_op_BitConcatenate.i16.i15.i1(i15 %i_3, i1 false) -ST_17: tmp_38_cast [1/1] 0.00ns +ST_15: tmp_38_cast [1/1] 0.00ns :3 %tmp_38_cast = zext i16 %tmp_37 to i32 -ST_17: stg_233 [1/1] 0.00ns -:4 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_data, i32 %tmp_38_cast) +ST_15: stg_231 [1/1] 0.00ns +:4 call void @_ssdm_op_Write.ap_ovld.volatile.i32P(i32* %trig_pixel, i32 %tmp_38_cast) -ST_17: stg_234 [1/1] 0.00ns +ST_15: stg_232 [1/1] 0.00ns :5 br label %.preheader79 - : 2.38ns -ST_18: i_4 [1/1] 0.00ns + : 2.38ns +ST_16: i_4 [1/1] 0.00ns .preheader:0 %i_4 = phi i15 [ %i_8, %._crit_edge87 ], [ 0, %.preheader80 ] -ST_18: empty_14 [1/1] 0.00ns +ST_16: empty_14 [1/1] 0.00ns .preheader:1 %empty_14 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 0, i64 32767, i64 0) -ST_18: exitcond6 [1/1] 1.85ns +ST_16: exitcond6 [1/1] 1.85ns .preheader:2 %exitcond6 = icmp eq i15 %i_4, %tmp_2 -ST_18: i_8 [1/1] 1.60ns +ST_16: i_8 [1/1] 1.60ns .preheader:3 %i_8 = add i15 %i_4, 1 -ST_18: stg_239 [1/1] 0.00ns +ST_16: stg_237 [1/1] 0.00ns .preheader:4 br i1 %exitcond6, label %.preheader82, label %11 -ST_18: tmp_9 [1/1] 0.00ns +ST_16: tmp_9 [1/1] 0.00ns :0 %tmp_9 = zext i15 %i_4 to i64 -ST_18: sum_pix2_addr_2 [1/1] 0.00ns +ST_16: sum_pix2_addr_2 [1/1] 0.00ns :1 %sum_pix2_addr_2 = getelementptr inbounds [1152 x i32]* %sum_pix2, i64 0, i64 %tmp_9 -ST_18: sum_pix2_load [2/2] 2.38ns +ST_16: sum_pix2_load [2/2] 2.38ns :2 %sum_pix2_load = load i32* %sum_pix2_addr_2, align 4 -ST_18: sum_pix1_addr_2 [1/1] 0.00ns +ST_16: sum_pix1_addr_2 [1/1] 0.00ns :3 %sum_pix1_addr_2 = getelementptr inbounds [1152 x i32]* %sum_pix1, i64 0, i64 %tmp_9 -ST_18: sum_pix1_load [2/2] 2.38ns +ST_16: sum_pix1_load [2/2] 2.38ns :4 %sum_pix1_load = load i32* %sum_pix1_addr_2, align 4 -ST_18: thresh1_addr_1 [1/1] 0.00ns +ST_16: thresh1_addr_1 [1/1] 0.00ns :14 %thresh1_addr_1 = getelementptr inbounds [1152 x i32]* %thresh1, i64 0, i64 %tmp_9 -ST_18: thresh2_addr_1 [1/1] 0.00ns +ST_16: thresh2_addr_1 [1/1] 0.00ns :17 %thresh2_addr_1 = getelementptr inbounds [1152 x i32]* %thresh2, i64 0, i64 %tmp_9 - : 2.38ns -ST_19: sum_pix2_load [1/2] 2.38ns + : 2.38ns +ST_17: sum_pix2_load [1/2] 2.38ns :2 %sum_pix2_load = load i32* %sum_pix2_addr_2, align 4 -ST_19: sum_pix1_load [1/2] 2.38ns +ST_17: sum_pix1_load [1/2] 2.38ns :4 %sum_pix1_load = load i32* %sum_pix1_addr_2, align 4 -ST_19: tmp_data_V [1/1] 0.00ns +ST_17: tmp_data_V [1/1] 0.00ns :5 %tmp_data_V = call i64 @_ssdm_op_BitConcatenate.i64.i32.i32(i32 %sum_pix2_load, i32 %sum_pix1_load) -ST_19: stg_250 [1/1] 0.00ns +ST_17: stg_248 [1/1] 0.00ns :6 call void @_ssdm_op_Write.axis.volatile.i64P.i8P.i8P.i2P.i1P.i5P.i6P(i64* %out_stream_V_data_V, i8* %out_stream_V_keep_V, i8* %out_stream_V_strb_V, i2* %out_stream_V_user_V, i1* %out_stream_V_last_V, i5* %out_stream_V_id_V, i6* %out_stream_V_dest_V, i64 %tmp_data_V, i8 -1, i8 -1, i2 undef, i1 undef, i5 undef, i6 undef) -ST_19: tmp_10 [1/1] 0.00ns +ST_17: tmp_10 [1/1] 0.00ns :7 %tmp_10 = call i25 @_ssdm_op_PartSelect.i25.i32.i32.i32(i32 %sum_pix1_load, i32 7, i32 31) -ST_19: tmp_11 [1/1] 0.00ns +ST_17: tmp_11 [1/1] 0.00ns :10 %tmp_11 = call i25 @_ssdm_op_PartSelect.i25.i32.i32.i32(i32 %sum_pix2_load, i32 7, i32 31) - : 7.65ns -ST_20: sum_pixP1 [1/1] 0.00ns + : 7.65ns +ST_18: sum_pixP1 [1/1] 0.00ns :8 %sum_pixP1 = call i28 @_ssdm_op_BitConcatenate.i28.i25.i3(i25 %tmp_10, i3 0) -ST_20: sum_pixP1_cast [1/1] 0.00ns +ST_18: sum_pixP1_cast [1/1] 0.00ns :9 %sum_pixP1_cast = zext i28 %sum_pixP1 to i32 -ST_20: sum_pixP2 [1/1] 0.00ns +ST_18: sum_pixP2 [1/1] 0.00ns :11 %sum_pixP2 = call i28 @_ssdm_op_BitConcatenate.i28.i25.i3(i25 %tmp_11, i3 0) -ST_20: sum_pixP2_cast [1/1] 0.00ns +ST_18: sum_pixP2_cast [1/1] 0.00ns :12 %sum_pixP2_cast = zext i28 %sum_pixP2 to i32 -ST_20: tmp_12 [1/1] 7.65ns +ST_18: tmp_12 [1/1] 7.65ns :13 %tmp_12 = mul i32 %sum_pixP1_cast, %tmp_1 -ST_20: tmp_13 [1/1] 7.65ns +ST_18: tmp_13 [1/1] 7.65ns :16 %tmp_13 = mul i32 %sum_pixP2_cast, %tmp_1 - : 2.38ns -ST_21: stg_259 [1/1] 2.38ns + : 2.38ns +ST_19: stg_257 [1/1] 2.38ns :15 store i32 %tmp_12, i32* %thresh1_addr_1, align 4 -ST_21: stg_260 [1/1] 2.38ns +ST_19: stg_258 [1/1] 2.38ns :18 store i32 %tmp_13, i32* %thresh2_addr_1, align 4 -ST_21: tmp_14 [1/1] 2.12ns +ST_19: tmp_14 [1/1] 2.12ns :19 %tmp_14 = icmp ult i32 %tmp_12, %LOW_THRESH_read -ST_21: stg_262 [1/1] 0.00ns +ST_19: stg_260 [1/1] 0.00ns :20 br i1 %tmp_14, label %12, label %._crit_edge86 - : 2.38ns -ST_22: stg_263 [1/1] 2.38ns + : 2.38ns +ST_20: stg_261 [1/1] 2.38ns :0 store i32 %LOW_THRESH_read, i32* %thresh1_addr_1, align 4 -ST_22: stg_264 [1/1] 0.00ns +ST_20: stg_262 [1/1] 0.00ns :1 br label %._crit_edge86 -ST_22: tmp_21 [1/1] 2.12ns +ST_20: tmp_21 [1/1] 2.12ns ._crit_edge86:0 %tmp_21 = icmp ult i32 %tmp_13, %LOW_THRESH_read -ST_22: stg_266 [1/1] 0.00ns +ST_20: stg_264 [1/1] 0.00ns ._crit_edge86:1 br i1 %tmp_21, label %13, label %._crit_edge87 -ST_22: stg_267 [1/1] 2.38ns +ST_20: stg_265 [1/1] 2.38ns :0 store i32 %LOW_THRESH_read, i32* %thresh2_addr_1, align 4 -ST_22: stg_268 [1/1] 0.00ns +ST_20: stg_266 [1/1] 0.00ns :1 br label %._crit_edge87 -ST_22: stg_269 [1/1] 0.00ns +ST_20: stg_267 [1/1] 0.00ns ._crit_edge87:0 br label %.preheader @@ -962,8 +954,6 @@ N/A State 18 State 19 State 20 - State 21 - State 22 ============================================================ diff --git a/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.sched.rpt.xml b/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.sched.rpt.xml index aad8493..30ace16 100644 --- a/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.sched.rpt.xml +++ b/l2_trigger/solution1/.autopilot/db/l2_trigger.verbose.sched.rpt.xml @@ -1,7 +1,7 @@
-Fri Apr 13 19:40:42 2018 +Wed Apr 18 11:09:39 2018 2016.2 (Build 1577090 on Thu Jun 02 16:59:10 MDT 2016) l2_trigger @@ -38,10 +38,10 @@ 0, 32767, 1, -, -, 0 ~ 32767, no 16, 262152, 2 ~ 32769, -, -, 8, no 0, 32767, 1, -, -, 0 ~ 32767, no -?, ?, 260 ~ 88274558, -, -, ?, no +?, ?, 260 ~ 84080382, -, -, ?, no 0, 32767, 1, -, -, 0 ~ 32767, no -256, 88077952, 2 ~ 688109, -, -, 128, no -0, 688107, 18 ~ 21, -, -, 0 ~ 32767, no +256, 83883776, 2 ~ 655342, -, -, 128, no +0, 655340, 18 ~ 20, -, -, 0 ~ 32767, no 14, 14, 2, -, -, 7, no 0, 163835, 5, -, -, 0 ~ 32767, no
diff --git a/l2_trigger/solution1/impl/verilog/extraction.tcl b/l2_trigger/solution1/impl/verilog/extraction.tcl deleted file mode 100644 index f902e48..0000000 --- a/l2_trigger/solution1/impl/verilog/extraction.tcl +++ /dev/null @@ -1,1462 +0,0 @@ -## ============================================================== -## File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -## Version: 2016.2 -## Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved. -## -## ============================================================== - -#---------------------------------------------------------------------------- -# extract_clk_period_sdc -# -# Opens the .sdc file to extract the contraint clock period -#---------------------------------------------------------------------------- -proc extract_clk_period_sdc {file_name} { - - set report_file [open $file_name r] - set report_buf [read -nonewline $report_file] - close $report_file - - # pattern for parsing .sdc file. - set prefix_sync {create_clock.*} - set prefix_comb {set_max_delay\s+} - set number {(\d+\.\d+)} - set key {-period\s+} - set clk_pattern_sync ${prefix_sync}${key}${number} - set clk_pattern_comb ${prefix_comb}${number} - if {[regexp $clk_pattern_sync $report_buf match actual]} { - return $actual - } elseif {[regexp $clk_pattern_comb $report_buf match actual]} { - return $actual - } - return "NA" -} - -#---------------------------------------------------------------------------- -# extract_clk_period_ucf -# -# Opens the .ucf file to extract the constraint clock period -#---------------------------------------------------------------------------- -proc extract_clk_period_ucf {file_name} { - - set report_file [open $file_name r] - set report_buf [read -nonewline $report_file] - close $report_file - - # pattern for parsing .ucf file. - set prefix {TIMESPEC.*} - set key_sync {PERIOD.*\s+} - set key_comb {FROM\s+PADS\s+TO\s+PADS\s+} - set number {(\d+\.\d+)} - set clk_pattern_sync ${prefix}${key_sync}${number} - set clk_pattern_comb ${prefix}${key_comb}${number} - if {[regexp $clk_pattern_sync $report_buf match actual]} { - return $actual - } elseif {[regexp $clk_pattern_comb $report_buf match actual]} { - return $actual - } - return "NA" -} - -#---------------------------------------------------------------------------- -# compile_reports_synxil -# dump ${top_module}.rpt and ${top_module}.result.rb for synplify flow -#---------------------------------------------------------------------------- -proc compile_reports_synxil {top_module language} { - set result_file [open ${top_module}.result w] - dump_report_synxil $top_module $result_file - close $result_file - - file mkdir ../report/${language} - report_copy ${top_module} "../report/${language}" - - set result_file [open ${top_module}.result.rb w] - dump_report_rb_synxil $top_module $result_file - close $result_file - - dump_report_synxil $top_module stdout -} - -#---------------------------------------------------------------------------- -# compile_reports_ise -# dump ${top_module}.rpt and ${top_module}.result.rb for ise flow -#---------------------------------------------------------------------------- -proc compile_reports_ise {top_module language} { - set result_file [open ${top_module}.result w] - dump_report $top_module $result_file - close $result_file - - file mkdir ../report/${language} - report_copy ${top_module} "../report/${language}" - - set result_file [open ${top_module}.result.rb w] - dump_report_rb $top_module $result_file - close $result_file - - # gen xml report - set result_file [open ${top_module}.result.xml w] - dump_report_xml $top_module $result_file - close $result_file - - # copy xml report - xmlreport_copy ${top_module} "../report/${language}" - - dump_report $top_module stdout -} - -#---------------------------------------------------------------------------- -# extract_area -# -# Open the ise flow report files to extract timing and resouce used in the design -#---------------------------------------------------------------------------- -proc extract_area {file_name file_name1 file_name2} { - - # ${module}_usage.xml - set report_file [open $file_name r] - set report_buf [read -nonewline $report_file] - close $report_file - - # ${module}.par - set report_file1 [open $file_name1 r] - set report_buf1 [read -nonewline $report_file1] - close $report_file1 - - # ${module}_map.mrp - set report_file2 [open $file_name2 r] - set report_buf2 [read -nonewline $report_file2] - close $report_file2 - - ################################################################################ - # patterns for parsing _usg.xml. - ################################################################################ - # SLICE pattern - set slice_pattern {.*PK_NUM_SLICES.+?value=\"(\d+)\".*} - set slice_pattern_v2p {.*NUM_SLICE.+?value=\"(\d+)\".*} - set slice_pattern_v5 {.*AGG_SLICE.+?value=\"(\d+)\".*} - set slice_pattern_101 {.*\"NUM_SLICE\".+?value=\"(\d+)\".*} - - # LUT pattern - set lut_pattern {.*PK_NUM_4_INPUT_LUTS.+?value=\"(\d+)\".*} - set lut_pattern_v2p {.*NUM_4_INPUT_LUT.+?value=\"(\d+)\".*} - set lut_part1 {.*NUM_BSFULL.+?value=\"(\d+)\".*} - set lut_part2 {.*NUM_BSLUTONLY.+?value=\"(\d+)\".*} - set lut_pattern_v5_backup {.*NUM_LOGIC_O6ONLY.+?value=\"(\d+)\".*} - - # FF pattern - set ff_pattern {.*PK_NUM_SLICE_FFS.+?value=\"(\d+)\".*} - set ff_pattern_v5 {.*NUM_SLICE_FF.+?value=\"(\d+)\".*} - - # MULT18/DSP48 pattern - set mult18_pattern {.*PK_NUM_XV2_MULTS.+?value=\"(\d+)\".*} - set mult18_pattern_101 {.*NUM_MULT18X18.+?value=\"(\d+)\".*} - set dsp48_pattern_v4 {.*PK_NUM_xv4_DSP48.+?value=\"(\d+)\".*} - set dsp48_pattern_v4_101 {.*NUM_DSP48.+?value=\"(\d+)\".*} - set dsp48_pattern_v5 {.*NUM_DSP48E.+?value=\"(\d+)\".*} - - # BRAM pattern - set bram_pattern_v2p {.*Number of BRAMs: +(\d+).*} - set bram_pattern_s3_s6_v4 {.*NUM_RAMB16.+?value=\"(\d+)\".*} - set bram_pattern_s6_9k {.*NUM_RAMB8BWER.+?value=\"(\d+)\".*} - set bram_pattern_v5_18k {.*NUM_RAMB18X2.+?value=\"(\d+)\".*} - set bram_pattern_v5_18k_upper {.*NUM_RAMB18X2_UPPER.+?value=\"(\d+)\".*} - set bram_pattern_v5_18k_lower {.*NUM_RAMB18X2_LOWER.+?value=\"(\d+)\".*} - set bram_pattern_v5_18k_sdp_upper {.*NUM_RAMB18X2SDP_UPPER.+?value=\"(\d+)\".*} - set bram_pattern_v5_18k_sdp_lower {.*NUM_RAMB18X2SDP_LOWER.+?value=\"(\d+)\".*} - set bram_pattern_v5_36k {.*NUM_RAMB36_EXP.+?value=\"(\d+)\".*} - set bram_pattern_v6_18k {.*NUM_RAMB18E1.+?value=\"(\d+)\".*} - set bram_pattern_v6_36k {.*NUM_RAMB36E1.+?value=\"(\d+)\".*} - - # LATCH pattern - set latch_pattern {.*Number used as Latches +(\d+).*} - - # SRL pattern - # s3, v4 - set srl_pattern_s3 {.*Number used as Shift registers: +(\d+).*} - # s6, v5, v6, v7 - set srl_pattern_s6 {.*Number used as Shift Register: +(\d+).*} - - # Init resource counters - set slice_count 0 - set lut_count 0 - set ff_count 0 - set mult_count 0 - set bram_count 0 - set latch_count 0 - set srl_count 0 - - # SLICE extraction - if {![regexp $slice_pattern $report_buf match_slice slice_count] && \ - ![regexp $slice_pattern_v5 $report_buf match_slice slice_count] && \ - ![regexp $slice_pattern_101 $report_buf match_slice slice_count] && \ - ![regexp $slice_pattern_v2p $report_buf match_slice slice_count] } { - set slice_count 0 - } - - # LUT extraction - if {![regexp $lut_pattern $report_buf match_lut lut_count] && \ - ![regexp $lut_pattern_v2p $report_buf match_lut lut_count]} { - if {[regexp $lut_part2 $report_buf match_lut lut_count1] && [regexp $lut_part1 $report_buf match_lut lut_count2] } { - set lut_count [expr $lut_count1+ $lut_count2] - } elseif {[regexp $lut_part2 $report_buf match_lut lut_count1] && ![regexp $lut_part1 $report_buf match_lut lut_count2]} { - set lut_count [expr $lut_count1] - } elseif {![regexp $lut_part2 $report_buf match_lut lut_count1] && [regexp $lut_part1 $report_buf match_lut lut_count2]} { - set lut_count [expr $lut_count2] - } elseif { ![regexp $lut_pattern_v5_backup $report_buf match_lut lut_count] } { - set lut_count 0 - } - } - - # FF extraction - if {![regexp $ff_pattern $report_buf match_ff ff_count] && \ - ![regexp $ff_pattern_v5 $report_buf match_ff ff_count]} { - set ff_count 0 - } - - # DSP extraction - if {![regexp $mult18_pattern $report_buf match_dsp mult_count] && \ - ![regexp $mult18_pattern_101 $report_buf match_dsp mult_count] && \ - ![regexp $dsp48_pattern_v4 $report_buf match_dsp mult_count] && \ - ![regexp $dsp48_pattern_v4_101 $report_buf match_dsp mult_count] && \ - ![regexp $dsp48_pattern_v5 $report_buf match_dsp mult_count]} { - set mult_count 0 - } - - # BRAM extraction - if {[regexp $bram_pattern_s3_s6_v4 $report_buf match_bram bram_count_18k] && [regexp $bram_pattern_s6_9k $report_buf match_bram bram_count_9k]} { - set bram_count [expr $bram_count_18k + $bram_count_9k] - } elseif {![regexp $bram_pattern_s3_s6_v4 $report_buf match_bram bram_count_18k] && [regexp $bram_pattern_s6_9k $report_buf match_bram bram_count_9k]} { - set bram_count $bram_count_9k - } elseif {[regexp $bram_pattern_s3_s6_v4 $report_buf match_bram bram_count_18k] && ![regexp $bram_pattern_s6_9k $report_buf match_bram bram_count_9k]} { - set bram_count $bram_count_18k - } else { - if {[regexp $bram_pattern_v6_18k $report_buf match_bram bram_count_18k] && [regexp $bram_pattern_v6_36k $report_buf match_bram bram_count_36k]} { - set bram_count [expr $bram_count_18k + 2*$bram_count_36k] - } elseif {[regexp $bram_pattern_v6_18k $report_buf match_bram bram_count_18k] && ![regexp $bram_pattern_v6_36k $report_buf match_bram bram_count_36k]} { - set bram_count $bram_count_18k - } elseif {![regexp $bram_pattern_v6_18k $report_buf match_bram bram_count_18k] && [regexp $bram_pattern_v6_36k $report_buf match_bram bram_count_36k]} { - set bram_count [expr 2*$bram_count_36k] - } else { - if {[regexp $bram_pattern_v5_18k $report_buf match_bram bram_count_18k] && [regexp $bram_pattern_v5_36k $report_buf match_bram bram_count_36k]} { - if {[regexp $bram_pattern_v5_18k_upper $report_buf match_bram bram_count_18k_upper] && [regexp $bram_pattern_v5_18k_lower $report_buf match_bram bram_count_18k_lower]} { - if {[regexp $bram_pattern_v5_18k_sdp_upper $report_buf match_bram bram_count_18k_sdp_upper] && [regexp $bram_pattern_v5_18k_sdp_lower $report_buf match_bram bram_count_18k_sdp_lower]} { - set bram_count [expr $bram_count_18k_sdp_upper + $bram_count_18k_sdp_lower + $bram_count_18k_upper + $bram_count_18k_lower + 2*$bram_count_36k] - } elseif {![regexp $bram_pattern_v5_18k_sdp_upper $report_buf match_bram bram_count_18k_sdp_upper] && [regexp $bram_pattern_v5_18k_sdp_lower $report_buf match_bram bram_count_18k_sdp_lower]} { - set bram_count [expr $bram_count_18k_sdp_lower + $bram_count_18k_upper + $bram_count_18k_lower + 2*$bram_count_36k] - } elseif {[regexp $bram_pattern_v5_18k_sdp_upper $report_buf match_bram bram_count_18k_sdp_upper] && ![regexp $bram_pattern_v5_18k_sdp_lower $report_buf match_bram bram_count_18k_sdp_lower]} { - set bram_count [expr $bram_count_18k_sdp_upper + $bram_count_18k_upper + $bram_count_18k_lower + 2*$bram_count_36k] - } else { - set bram_count [expr $bram_count_18k_upper + $bram_count_18k_lower + 2*$bram_count_36k] - } - } elseif {![regexp $bram_pattern_v5_18k_upper $report_buf match_bram bram_count_18k_upper] && [regexp $bram_pattern_v5_18k_lower $report_buf match_bram bram_count_18k_lower]} { - if {[regexp $bram_pattern_v5_18k_sdp_upper $report_buf match_bram bram_count_18k_sdp_upper] && [regexp $bram_pattern_v5_18k_sdp_lower $report_buf match_bram bram_count_18k_sdp_lower]} { - set bram_count [expr $bram_count_18k_sdp_upper + $bram_count_18k_sdp_lower + $bram_count_18k_lower + 2*$bram_count_36k] - } elseif {![regexp $bram_pattern_v5_18k_sdp_upper $report_buf match_bram bram_count_18k_sdp_upper] && [regexp $bram_pattern_v5_18k_sdp_lower $report_buf match_bram bram_count_18k_sdp_lower]} { - set bram_count [expr $bram_count_18k_sdp_lower + $bram_count_18k_lower + 2*$bram_count_36k] - } elseif {[regexp $bram_pattern_v5_18k_sdp_upper $report_buf match_bram bram_count_18k_sdp_upper] && ![regexp $bram_pattern_v5_18k_sdp_lower $report_buf match_bram bram_count_18k_sdp_lower]} { - set bram_count [expr $bram_count_18k_sdp_upper + $bram_count_18k_lower + 2*$bram_count_36k] - } else { - set bram_count [expr $bram_count_18k_lower + 2*$bram_count_36k] - } - } elseif {[regexp $bram_pattern_v5_18k_upper $report_buf match_bram bram_count_18k_upper] && ![regexp $bram_pattern_v5_18k_lower $report_buf match_bram bram_count_18k_lower]} { - if {[regexp $bram_pattern_v5_18k_sdp_upper $report_buf match_bram bram_count_18k_sdp_upper] && [regexp $bram_pattern_v5_18k_sdp_lower $report_buf match_bram bram_count_18k_sdp_lower]} { - set bram_count [expr $bram_count_18k_sdp_upper + $bram_count_18k_sdp_lower + $bram_count_18k_upper + 2*$bram_count_36k] - } elseif {![regexp $bram_pattern_v5_18k_sdp_upper $report_buf match_bram bram_count_18k_sdp_upper] && [regexp $bram_pattern_v5_18k_sdp_lower $report_buf match_bram bram_count_18k_sdp_lower]} { - set bram_count [expr $bram_count_18k_sdp_lower + $bram_count_18k_upper + 2*$bram_count_36k] - } elseif {[regexp $bram_pattern_v5_18k_sdp_upper $report_buf match_bram bram_count_18k_sdp_upper] && ![regexp $bram_pattern_v5_18k_sdp_lower $report_buf match_bram bram_count_18k_sdp_lower]} { - set bram_count [expr $bram_count_18k_sdp_upper + $bram_count_18k_upper + 2*$bram_count_36k] - } else { - set bram_count [expr $bram_count_18k_upper + 2*$bram_count_36k] - } - } else { - set bram_count [expr 2*$bram_count_36k] - } - } elseif {[regexp $bram_pattern_v5_18k $report_buf match_bram bram_count_18k] && ![regexp $bram_pattern_v5_36k $report_buf match_bram bram_count_36k]} { - if {[regexp $bram_pattern_v5_18k_upper $report_buf match_bram bram_count_18k_upper] && [regexp $bram_pattern_v5_18k_lower $report_buf match_bram bram_count_18k_lower]} { - if {[regexp $bram_pattern_v5_18k_sdp_upper $report_buf match_bram bram_count_18k_sdp_upper] && [regexp $bram_pattern_v5_18k_sdp_lower $report_buf match_bram bram_count_18k_sdp_lower]} { - set bram_count [expr $bram_count_18k_sdp_upper + $bram_count_18k_sdp_lower + $bram_count_18k_upper + $bram_count_18k_lower] - } elseif {![regexp $bram_pattern_v5_18k_sdp_upper $report_buf match_bram bram_count_18k_sdp_upper] && [regexp $bram_pattern_v5_18k_sdp_lower $report_buf match_bram bram_count_18k_sdp_lower]} { - set bram_count [expr $bram_count_18k_sdp_lower + $bram_count_18k_upper + $bram_count_18k_lower] - } elseif {[regexp $bram_pattern_v5_18k_sdp_upper $report_buf match_bram bram_count_18k_sdp_upper] && ![regexp $bram_pattern_v5_18k_sdp_lower $report_buf match_bram bram_count_18k_sdp_lower]} { - set bram_count [expr $bram_count_18k_sdp_upper + $bram_count_18k_upper + $bram_count_18k_lower] - } else { - set bram_count [expr $bram_count_18k_upper + $bram_count_18k_lower] - } - } elseif {![regexp $bram_pattern_v5_18k_upper $report_buf match_bram bram_count_18k_upper] && [regexp $bram_pattern_v5_18k_lower $report_buf match_bram bram_count_18k_lower]} { - if {[regexp $bram_pattern_v5_18k_sdp_upper $report_buf match_bram bram_count_18k_sdp_upper] && [regexp $bram_pattern_v5_18k_sdp_lower $report_buf match_bram bram_count_18k_sdp_lower]} { - set bram_count [expr $bram_count_18k_sdp_upper + $bram_count_18k_sdp_lower + $bram_count_18k_lower] - } elseif {![regexp $bram_pattern_v5_18k_sdp_upper $report_buf match_bram bram_count_18k_sdp_upper] && [regexp $bram_pattern_v5_18k_sdp_lower $report_buf match_bram bram_count_18k_sdp_lower]} { - set bram_count [expr $bram_count_18k_sdp_lower + $bram_count_18k_lower] - } elseif {[regexp $bram_pattern_v5_18k_sdp_upper $report_buf match_bram bram_count_18k_sdp_upper] && ![regexp $bram_pattern_v5_18k_sdp_lower $report_buf match_bram bram_count_18k_sdp_lower]} { - set bram_count [expr $bram_count_18k_sdp_upper + $bram_count_18k_lower] - } else { - set bram_count [expr $bram_count_18k_lower] - } - } elseif {[regexp $bram_pattern_v5_18k_upper $report_buf match_bram bram_count_18k_upper] && ![regexp $bram_pattern_v5_18k_lower $report_buf match_bram bram_count_18k_lower]} { - if {[regexp $bram_pattern_v5_18k_sdp_upper $report_buf match_bram bram_count_18k_sdp_upper] && [regexp $bram_pattern_v5_18k_sdp_lower $report_buf match_bram bram_count_18k_sdp_lower]} { - set bram_count [expr $bram_count_18k_sdp_upper + $bram_count_18k_sdp_lower + $bram_count_18k_upper] - } elseif {![regexp $bram_pattern_v5_18k_sdp_upper $report_buf match_bram bram_count_18k_sdp_upper] && [regexp $bram_pattern_v5_18k_sdp_lower $report_buf match_bram bram_count_18k_sdp_lower]} { - set bram_count [expr $bram_count_18k_sdp_lower + $bram_count_18k_upper] - } elseif {[regexp $bram_pattern_v5_18k_sdp_upper $report_buf match_bram bram_count_18k_sdp_upper] && ![regexp $bram_pattern_v5_18k_sdp_lower $report_buf match_bram bram_count_18k_sdp_lower]} { - set bram_count [expr $bram_count_18k_sdp_upper + $bram_count_18k_upper] - } else { - set bram_count [expr $bram_count_18k_upper] - } - } else { - set bram_count 0 - } - } elseif {![regexp $bram_pattern_v5_18k $report_buf match_bram bram_count_18k] && [regexp $bram_pattern_v5_36k $report_buf match_bram bram_count_36k]} { - set bram_count [expr 2*$bram_count_36k] - } else { - set bram_count 0 - } - } - } - - if {![regexp $latch_pattern $report_buf1 match_latch latch_count]} { - set latch_count 0 - } - - if {![regexp $srl_pattern_s3 $report_buf2 match_srl srl_count] && \ - ![regexp $srl_pattern_s6 $report_buf2 match_srl srl_count]} { - set srl_count 0 - } - - set return_value [list $slice_count $lut_count $ff_count $mult_count $bram_count $latch_count $srl_count] - return $return_value -} - -#---------------------------------------------------------------------------- -# extract_total -# -# Opens the .par and .syr file to extract available resources -#---------------------------------------------------------------------------- -proc extract_total {module} { - set s "" - # read .par - if {[file isfile ${module}.par]} { - set f [open ${module}.par r] - append s [read $f] - close $f - } - # read .syr - if {[file isfile ${module}.syr]} { - set f [open ${module}.syr r] - append s [read $f] - close $f - } - # patterns - set task { - slice { - {(?n)Number of occupied Slices.*out of\s+([0-9,]+)} {$value} - {(?n)Number of Slices.*out of\s+([0-9,]+)} {$value} - } - lut { - {(?n)Number of Slice LUTs.*out of\s+([0-9,]+)} {$value} - {(?n)Number of 4 input LUTs.*out of\s+([0-9,]+)} {$value} - } - ff { - {(?n)Number of Slice Registers.*out of\s+([0-9,]+)} {$value} - {(?n)Number of Slice Flip Flops.*out of\s+([0-9,]+)} {$value} - } - dsp { - {(?n)Number of (?:DSP|MULT).*out of\s+([0-9,]+)} {$value} - } - bram { - {(?n)Number of RAMB18X2.*out of\s+([0-9,]+)} {$value*2} - {(?n)Number of RAMB(?:16|18).*out of\s+([0-9,]+)} {$value} - {(?n)Number of RAMB36.*out of\s+([0-9,]+)} {$value*2} - } - } - # extract values - set ret "" - foreach {item rules} $task { - set match 0 - foreach {pat expression} $rules { - if {[regexp $pat $s m value]} { - set match 1 - set value [string map {, ""} $value] - set value [expr $expression] - break - } - } - if {!$match} { - set value "NA" - } - lappend ret $value - } - return $ret -} - -#---------------------------------------------------------------------------- -# extract_timing -# -# Opens the .twr file to extract the actual timing delay value -#---------------------------------------------------------------------------- -proc extract_timing {file_name} { - - set report_file [open $file_name r] - set report_buf [read -nonewline $report_file] - close $report_file - - # pattern for parsing .twr file. - set prefix {.*} - set number {.*?(\d+\.\d+)ns} - set key_sync "Minimum period:" - set key_comb "Maximum path delay" - set clk_pattern_sync ${prefix}${key_sync}${number} - set clk_pattern_comb ${prefix}${key_comb}${number} - if {[regexp $clk_pattern_sync $report_buf match actual]} { - return $actual - } elseif {[regexp $clk_pattern_comb $report_buf match actual]} { - return $actual - } - - return "NA" -} - -#---------------------------------------------------------------------------- -# dump_report_synxil -# -# Generate report for synplify flow -#---------------------------------------------------------------------------- -proc dump_report_synxil { module out } { - - set fl [open rev_syn/${module}.srr r] - set report_buf [read -nonewline $fl] - close $fl - set ver_pattern {^#Build: (Synplify|Synplify Pro) +(\S+) .*} - if {![regexp $ver_pattern $report_buf match_ver match_name ver]} { - set ver UNKNOWN - } - if {![string equal -nocase $ver "UNKNOWN"] } { - set ver [string range $ver 0 end-1] - } - - set dev_pattern {.*Mapping to part: (\S+)\n.*} - - if {![regexp $dev_pattern $report_buf match_dev device]} { - set device UNKNOWN - } else { - set dev_list [split $device "-"] - set dev [lindex $dev_list 0] - set dev "$dev[lindex $dev_list 2]-[lindex $dev_list 1]" - } - - set date [clock format [clock seconds]] - - ## Report area ### - - set area_results [extract_area ${module}_usage.xml ${module}.par ${module}_map.mrp] - puts $out "" - puts $out "" - puts $out "Implementation tool: $match_name $ver" - puts $out "Device target: $dev" - puts $out "Report date: $date" - puts $out "" - puts $out "" - - set x1 [format "%-10s %8d" SLICE: [lindex $area_results 0]] - set x2 [format "%-10s %8d" LUT: [lindex $area_results 1]] - set x3 [format "%-10s %8d" FF: [lindex $area_results 2]] - set x4 [format "%-10s %8d" DSP: [lindex $area_results 3]] - set x5 [format "%-10s %8d" BRAM: [lindex $area_results 4]] - set x7 [format "%-10s %8d" SRL: [lindex $area_results 6]] - set sdc_file [glob -nocomplain *.sdc] - set t2 [format "%2.3f" [extract_clk_period_sdc $sdc_file]] - set t1_tmp [extract_timing ${module}.twr] - if {$t1_tmp == "NA"} { - set t1 $t1_tmp - } else { - set t1 [format "%2.3f" $t1_tmp] - } - - puts $out "#=== Resource usage ===" - puts $out "$x1" - puts $out "$x2" - puts $out "$x3" - puts $out "$x4" - puts $out "$x5" - puts $out "$x7" - if {[lindex $area_results 5] != 0} { - set x6 [format "%-10s %8d" LATCH: [lindex $area_results 5]] - puts $out "$x6" - } - ## Report timing ### - puts $out "#=== Final timing ===" - puts $out "CP required: $t2" - puts $out "CP achieved: $t1" - if {$t1 == "NA"} { - puts $out "No Sequential Path" - } else { - if {[expr $t1 <= $t2]} { - puts $out "Timing met" - } else { - puts $out "Timing not met" - } - } -} - -## extract target clock from rpt file -proc extract_target_clock_rpt {module} { - set t2 "NA" - set fl [open ./report/${module}_timing_routed.rpt r] - set report_buf [read -nonewline $fl] - close $fl - set clk_pattern {Path\s+Group:\s+ap_clk.*?Requirement:\s+(\d+\.\d+)ns.*?} - if {![regexp $clk_pattern $report_buf match_clk t2]} { - #puts "DEBUG: using the old way to extract target clock" - set t2 [format "%2.3f" [extract_clk_period_sdc ${module}.xdc]] - } - #puts "DEBUG: matched clk is $t2" - return $t2 -} - -## extract target clock from twr file -proc extract_target_clock_twr {module} { - set t2 "NA" - set fl [open ./${module}.twr r] - set report_buf [read -nonewline $fl] - close $fl - set clk_pattern {.*?Requirement: +(\d+\.\d+)ns.*} - if {![regexp $clk_pattern $report_buf match_clk t2]} { - set t2 [format "%2.3f" [extract_clk_period_ucf ${module}.ucf]] - } - return $t2 -} - -#---------------------------------------------------------------------------- -# dump_report -# -# Generate report for ISE flow -#---------------------------------------------------------------------------- -proc dump_report { module out } { - - set fl [open ${module}.syr r] - set report_buf [read -nonewline $fl] - close $fl - set ver_pattern {.*Release +(\S+) .*} - if {![regexp $ver_pattern $report_buf match_ver ver]} { - set ver UNKNOWN - } - - set dev_pattern {.*Target Device +: (\S+)\n.*} - - if {![regexp $dev_pattern $report_buf match_dev device]} { - set device UNKNOWN - } else { - set dev_list [split $device "-"] - set dev [lindex $dev_list 0] - set dev "$dev[lindex $dev_list 2]-[lindex $dev_list 1]" - } - - set date [clock format [clock seconds]] - - ## Report area ### - - set area_results [extract_area ${module}_usage.xml ${module}.par ${module}_map.mrp] - puts $out "" - puts $out "" - puts $out "Implementation tool: Xilinx ISE$ver" - puts $out "Device target: $dev" - puts $out "Report date: $date" - puts $out "" - puts $out "" - - set x1 [format "%-10s %8d" SLICE: [lindex $area_results 0]] - set x2 [format "%-10s %8d" LUT: [lindex $area_results 1]] - set x3 [format "%-10s %8d" FF: [lindex $area_results 2]] - set x4 [format "%-10s %8d" DSP: [lindex $area_results 3]] - set x5 [format "%-10s %8d" BRAM: [lindex $area_results 4]] - set x7 [format "%-10s %8d" SRL: [lindex $area_results 6]] - set t2 [extract_target_clock_twr $module] - set t1_tmp [extract_timing ${module}.twr] - if {$t1_tmp == "NA"} { - set t1 $t1_tmp - } else { - set t1 [format "%2.3f" $t1_tmp] - } - - puts $out "#=== Resource usage ===" - puts $out "$x1" - puts $out "$x2" - puts $out "$x3" - puts $out "$x4" - puts $out "$x5" - puts $out "$x7" - if {[lindex $area_results 5] != 0} { - set x6 [format "%-10s %8d" LATCH: [lindex $area_results 5]] - puts $out "$x6" - } - ## Report timing ### - puts $out "#=== Final timing ===" - puts $out "CP required: $t2" - puts $out "CP achieved: $t1" - if {$t1 == "NA"} { - puts $out "No Sequential Path" - } else { - if {[expr $t1 <= $t2]} { - puts $out "Timing met" - } else { - puts $out "Timing not met" - } - } -} - -#---------------------------------------------------------------------------- -# dump_report_rb_synxil -# -# Generate ruby report for synplify flow -#---------------------------------------------------------------------------- -proc dump_report_rb_synxil { module out } { - - ## Report area ### - - set area_results [extract_area ${module}_usage.xml ${module}.par ${module}_map.mrp] - puts $out "\$Footmark = \"FPGA_Xilinx\"" - puts $out "\$Description = \"by ISE\"" - puts $out "" - puts $out "" - - puts $out "#=== Resource usage ===" - puts $out "\$SLICE = \"[lindex $area_results 0]\"" - puts $out "\$LUT = \"[lindex $area_results 1]\"" - puts $out "\$FF = \"[lindex $area_results 2]\"" - puts $out "\$DSP = \"[lindex $area_results 3]\"" - puts $out "\$BRAM =\"[lindex $area_results 4]\"" - puts $out "\$SRL =\"[lindex $area_results 6]\"" - - ## Report timing ### - puts $out "#=== Final timing ===" - set sdc_file [glob -nocomplain *.sdc] - set t2 [format "%2.3f" [extract_clk_period_sdc $sdc_file]] - set t1_tmp [extract_timing ${module}.twr] - if {$t1_tmp == "NA"} { - set t1 $t1_tmp - } else { - set t1 [format "%2.3f" $t1_tmp] - } - puts $out "\$TargetCP = \"$t2\"" - puts $out "\$CP = \"$t1\"" -} - -#---------------------------------------------------------------------------- -# dump_report_rb -# -# Generate ruby report for ISE flow -#---------------------------------------------------------------------------- -proc dump_report_rb { module out } { - - ## Report area ### - - set area_results [extract_area ${module}_usage.xml ${module}.par ${module}_map.mrp] - puts $out "\$Footmark = \"FPGA_Xilinx\"" - puts $out "\$Description = \"by ISE\"" - puts $out "" - puts $out "" - - puts $out "#=== Resource usage ===" - puts $out "\$SLICE = \"[lindex $area_results 0]\"" - puts $out "\$LUT = \"[lindex $area_results 1]\"" - puts $out "\$FF = \"[lindex $area_results 2]\"" - puts $out "\$DSP = \"[lindex $area_results 3]\"" - puts $out "\$BRAM =\"[lindex $area_results 4]\"" - puts $out "\$SRL =\"[lindex $area_results 6]\"" - - ## Report timing ### - puts $out "#=== Final timing ===" - set t2 [extract_target_clock_twr $module] - set t1_tmp [extract_timing ${module}.twr] - if {$t1_tmp == "NA"} { - set t1 $t1_tmp - } else { - set t1 [format "%2.3f" $t1_tmp] - } - puts $out "\$TargetCP = \"$t2\"" - puts $out "\$CP = \"$t1\"" -} - -#---------------------------------------------------------------------------- -# dump_report_xml -# -# Generate xml report -#---------------------------------------------------------------------------- -proc dump_report_xml { module out } { - # collect data - set area_results [extract_area ${module}_usage.xml ${module}.par ${module}_map.mrp] - set slice [lindex $area_results 0] - set lut [lindex $area_results 1] - set ff [lindex $area_results 2] - set dsp [lindex $area_results 3] - set bram [lindex $area_results 4] - set srl [lindex $area_results 6] - set area_total [extract_total $module] - set t_slice [lindex $area_total 0] - set t_lut [lindex $area_total 1] - set t_ff [lindex $area_total 2] - set t_dsp [lindex $area_total 3] - set t_bram [lindex $area_total 4] - set targetcp [extract_target_clock_twr $module] - set t1_tmp [extract_timing ${module}.twr] - if {$t1_tmp == "NA"} { - set achievedcp $t1_tmp - } else { - set achievedcp [format "%.3f" $t1_tmp] - } - # dump xml - puts $out "" - puts $out "" - puts $out "" - puts $out "" - puts $out "$slice" - puts $out "$lut" - puts $out "$ff" - puts $out "$dsp" - puts $out "$bram" - puts $out "$srl" - puts $out "" - puts $out "" - puts $out "$t_slice" - puts $out "$t_lut" - puts $out "$t_ff" - puts $out "$t_dsp" - puts $out "$t_bram" - puts $out "" - puts $out "" - puts $out "" - puts $out "" - puts $out "$targetcp" - puts $out "$achievedcp" - puts $out "" - puts $out "" - puts $out "" -} - -proc report_copy { module dir} { - set filename ${module}.result - if {[file exists $filename]} { - if {[file isdirectory $dir]} { - file copy -force $filename $dir/${module}_export.rpt - file delete -force ${module}.result - } - } -} - -proc xmlreport_copy {module dir} { - set filename ${module}.result.xml - if {[file exists $filename]} { - if {[file isdirectory $dir]} { - file copy -force $filename $dir/${module}_export.xml - file delete -force $filename - } - } -} - -proc invoke_coregen { {lang ""} } { - if { $lang == "" } { - set lang [file tail [pwd]] - } - - set ext ".vhd" - if { [string equal -nocase $lang "verilog"] } { - set ext ".v" - } - - set xco_files [glob -nocomplain *.xco] - set coe_files [glob -nocomplain *.coe] - - if { [llength $xco_files] == 0 } { - return - } - - set path [pwd] - if {[string match *\.* $path]} { - #puts "@W \[IMPL-253\] CoreGen currently could fail if there is a '.' in part of the path name, temporarily change the offending directory name by replacing '.' with '_'." - ::AESL_AUTOIMPLMSG::autoimplmsg_warn253 - } - - set coregen_dir "ap_coregen" - while {[file exists $coregen_dir] && ![file isdir $coregen_dir]} { - append coregen_dir "_" - } - file delete -force $coregen_dir - file mkdir $coregen_dir - foreach f [concat $xco_files $coe_files] { - file copy -force $f $coregen_dir - } - - # Enter coregen dir - cd $coregen_dir - - # Generate an empty coregen project - set project "project.cgp" - close [open $project w] - - foreach xco_file $xco_files { - puts "Generating IP ($xco_file) ..." - if {[catch {exec coregen -b $xco_file -p $project -intstyle silent >& log} err_msg]} { - puts stderr "Could not complete coregen: $err_msg\n" - exit 1 - } else { - puts stderr "$err_msg\n" - puts "Done" - puts "" - set ip_name [file root [file tail $xco_file]] - set rtl_file ${ip_name}${ext} - set ngc_file ${ip_name}.ngc - set mif_file ${ip_name}.mif - if {![file isfile $rtl_file] || ![file isfile $ngc_file]} { - #puts "@E \[IMPL-254\] IP generation did not complete as expected." - ::AESL_AUTOIMPLMSG::autoimplmsg_err254 - exit 1 - } else { - file copy -force $rtl_file .. - file copy -force $ngc_file .. - if {[file isfile $mif_file]} { - file copy -force $mif_file .. - } - } - } - } - - # Go back - cd .. -} - -#---------------------------------------------------------------------------- -# compile_reports_rodin -# dump ${top_module}.rpt and ${top_module}.result.rb for Rodin flow -#---------------------------------------------------------------------------- -proc compile_reports_rodin {top_module language device project solution} { - set result_file [open ${top_module}.result w] - dump_report_rodin $top_module $result_file $device $project $solution - close $result_file - - file mkdir ../report/${language} - report_copy ${top_module} "../report/${language}" - - set result_file [open ${top_module}.result.rb w] - dump_report_rodin_rb $top_module $result_file $device - close $result_file - - # gen xml report - set result_file [open ${top_module}.result.xml w] - dump_report_rodin_xml $top_module $result_file - close $result_file - - # copy xml report - xmlreport_copy ${top_module} "../report/${language}" - - dump_report_rodin $top_module stdout $device $project $solution -} - -#---------------------------------------------------------------------------- -# extract_area_rodin -# -# Open the Rodin flow report files to extract timing and resouce used in the design -#---------------------------------------------------------------------------- -proc extract_area_rodin { uti_file } { - - # ${module}.uti - set uti_fl [open $uti_file r] - set uti_rpt_buf [read -nonewline $uti_fl] - close $uti_fl - - ################################################################################ - # patterns for parsing utilization file - ################################################################################ - # SLICE pattern - set slice_pattern {.*(?:Slice)\s+\|\s+(\d+)\s+\|\s+\d+\s+\|\s+\d+.*} - # CLB pattern - set clb_pattern {.*(?:CLB)\s+\|\s+(\d+)\s+\|\s+\d+\s+\|\s+\d+.*} - # LUT pattern - set lut_pattern {.*(?:Slice|CLB) LUTs.+?(\d+).*} - # FF pattern - set ff_pattern {.*(?:Slice|CLB) Registers.+?(\d+).*} - # DSP pattern - set DSPs_pattern {.*(?:DSPs)\s+\|\s+(\d+)\s+\|\s+\d+\s+\|\s+\d+.*} - # BRAM pattern - set bram_pattern {.*RAMB18E\d only.+?(\d+).*} - set bram36_pattern {.*RAMB36E\d only.+?(\d+).*} - # FIFO pattern - set fifo_pattern {.*FIFO18E\d only.+?(\d+).*} - # LATCH pattern - set latch_pattern {.*Register as Latch.+?(\d+).*} - # SRL pattern - set srl_pattern {.*LUT as Shift Register.+?(\d+).*} - # URAM pattern - set URAM_pattern {.*(?:URAM)\s+\|\s+(\d+)\s+\|\s+\d+\s+\|\s+\d+.*} - - # Init resource counters - set slice_count 0 - set clb_count 0 - set lut_count 0 - set ff_count 0 - set mult_count 0 - set bram_count18 0 - set bram_count36 0 - set bram_count 0 - set latch_count 0 - set srl_count 0 - set uram_count 0 - - if {![regexp $slice_pattern $uti_rpt_buf match_slice slice_count] } { - set slice_count 0 - } - - if {![regexp $clb_pattern $uti_rpt_buf match_clb clb_count] } { - set clb_count 0 - } - - if {![regexp $lut_pattern $uti_rpt_buf match_lut lut_count] } { - set lut_count 0 - } - - if {![regexp $ff_pattern $uti_rpt_buf match_ff ff_count] } { - set ff_count 0 - } - - if {![regexp $DSPs_pattern $uti_rpt_buf match_mult mult_count] } { - set mult_count 0 - } - - if {![regexp $bram_pattern $uti_rpt_buf match_bram bram_count18] } { - set bram_count18 0 - } - if {![regexp $bram36_pattern $uti_rpt_buf match_bram bram_count36] } { - set bram_count36 0 - } - set bram_count [expr $bram_count18 + 2 * $bram_count36] - - if {![regexp $latch_pattern $uti_rpt_buf match_latch latch_count]} { - set latch_count 0 - } - - if {![regexp $srl_pattern $uti_rpt_buf match_srl srl_count]} { - set srl_count 0 - } - - if {![regexp $URAM_pattern $uti_rpt_buf match_uram uram_count] } { - set uram_count 0 - } - - set return_value [list $slice_count $lut_count $ff_count $mult_count $bram_count $latch_count $srl_count $clb_count $uram_count] - - return $return_value -} - -#---------------------------------------------------------------------------- -# extract_total_rodin -# -# Open the Rodin flow report files to extract timing and resouce used in the design -#---------------------------------------------------------------------------- -proc extract_total_rodin { uti_file } { - - # ${module}.uti - set uti_fl [open $uti_file r] - set uti_rpt_buf [read -nonewline $uti_fl] - close $uti_fl - - ################################################################################ - # patterns for parsing utilization file - ################################################################################ - # SLICE pattern - set slice_pattern {.*(?:Slice)\s+\|\s+\d+\s+\|\s+\d+\s+\|\s+(\d+).*} - # CLB pattern - set clb_pattern {.*(?:CLB)\s+\|\s+\d+\s+\|\s+\d+\s+\|\s+(\d+).*} - # LUT pattern - set lut_pattern {.*(?:Slice|CLB) LUTs\s+\|\s+\d+\s+\|\s+\d+\s+\|\s+(\d+).*} - # FF pattern - set ff_pattern {.*(?:Slice|CLB) Registers\s+\|\s+\d+\s+\|\s+\d+\s+\|\s+(\d+).*} - # DSP pattern - set DSPs_pattern {.*(?:DSPs)\s+\|\s+\d+\s+\|\s+\d+\s+\|\s+(\d+).*} - # BRAM pattern - set bram18_pattern {.*RAMB18\s+\|\s+\d+\s+\|\s+\d+\s+\|\s+(\d+).*} - # URAM pattern - set URAM_pattern {.*(?:URAM)\s+\|\s+\d+\s+\|\s+\d+\s+\|\s+(\d+).*} - - # Init resource counters - set slice_count 0 - set clb_count 0 - set lut_count 0 - set ff_count 0 - set dsp_count 0 - set bram_count18 0 - set uram_count 0 - - if {![regexp $slice_pattern $uti_rpt_buf match_slice slice_count] } { - set slice_count 0 - } - - if {![regexp $clb_pattern $uti_rpt_buf match_clb clb_count] } { - set clb_count 0 - } - - if {![regexp $lut_pattern $uti_rpt_buf match_lut lut_count] } { - set lut_count 0 - } - - if {![regexp $ff_pattern $uti_rpt_buf match_ff ff_count] } { - set ff_count 0 - } - - if {![regexp $DSPs_pattern $uti_rpt_buf match_dsp dsp_count] } { - set dsp_count 0 - } - - if {![regexp $bram18_pattern $uti_rpt_buf match_bram bram_count18] } { - set bram_count18 0 - } - - if {![regexp $URAM_pattern $uti_rpt_buf match_uram uram_count] } { - set uram_count 0 - } - - set return_value [list $slice_count $lut_count $ff_count $dsp_count $bram_count18 $clb_count $uram_count] - - return $return_value -} - -#---------------------------------------------------------------------------- -# extract_timing_rodin -# -# Opens the .rpt file to extract the actual timing delay value -#---------------------------------------------------------------------------- -proc extract_timing_rodin {file_name} { - - set report_file [open $file_name r] - set report_buf [read -nonewline $report_file] - close $report_file - - # pattern for parsing .rpt file. - set keywords {From\s+Clock:\s+ap_clk.*?To\s+Clock:\s+ap_clk} - set clk_pattern_sync_setup {.*?Setup.*?Worst\s+Slack\s+?(-?\d+\.\d+)ns,.*?$} - set clk_pattern_sync_hold {.*?Hold.*?Worst\s+Slack\s+?(-?\d+\.\d+)ns,.*?} - set clk_pattern_sync_pw {.*?PW.*?Worst\s+Slack\s+?(-?\d+\.\d+)ns,.*?} - if {[regexp ${keywords}${clk_pattern_sync_setup} $report_buf match setup_slack] && [regexp ${keywords}${clk_pattern_sync_pw} $report_buf match pw_slack]} { - if {[expr 2*$pw_slack] < $setup_slack} { - return [expr 2*$pw_slack] - } else { - #puts "DEBUG: slack is $setup_slack" - return $setup_slack - } - } - - return "NA" -} - -proc dump_report_rodin { module out device project solution } { - - set fl [open ./report/${module}_timing_routed.rpt r] - set report_buf [read -nonewline $fl] - close $fl - #set ver_pattern {.*Version : +(\S+) +(\S+) .*} - set ver_pattern {.*Version.*Vivado +(\S+) +(\S+) .*} - if {![regexp $ver_pattern $report_buf match_ver ver0 ver]} { - set ver UNKNOWN - } - - set dev $device - - set date [clock format [clock seconds]] - - ## Report area ### - - set area_results [extract_area_rodin ./report/${module}_utilization_routed.rpt] - puts $out "" - puts $out "" - puts $out "Implementation tool: Xilinx Vivado $ver0" - puts $out "Project: $project" - puts $out "Solution: $solution" - puts $out "Device target: $dev" - puts $out "Report date: $date" - puts $out "" - - set x1 [format "%-10s %8d" SLICE: [lindex $area_results 0]] - set x2 [format "%-10s %8d" LUT: [lindex $area_results 1]] - set x3 [format "%-10s %8d" FF: [lindex $area_results 2]] - set x4 [format "%-10s %8d" DSP: [lindex $area_results 3]] - set x5 [format "%-10s %8d" BRAM: [lindex $area_results 4]] - set x7 [format "%-10s %8d" SRL: [lindex $area_results 6]] - set x8 [format "%-10s %8d" CLB: [lindex $area_results 7]] - set x9 [format "%-10s %8d" URAM: [lindex $area_results 8]] - - set t2 [extract_target_clock_rpt $module] - set t1tmp0 [extract_timing_rodin ./report/${module}_timing_routed.rpt] - if { $t1tmp0 == "NA" } { - set t1 $t1tmp0 - } else { - set t1 [format "%2.3f" [expr $t2 - $t1tmp0]] - } - - puts $out "#=== Resource usage ===" - if {[lindex $area_results 7] != 0} { - puts $out "$x8" - } else { - puts $out "$x1" - } - puts $out "$x2" - puts $out "$x3" - puts $out "$x4" - puts $out "$x5" - puts $out "$x7" - if {[lindex $area_results 8] != 0} { - puts $out "$x9" - } - if {[lindex $area_results 5] != 0} { - set x6 [format "%-10s %8d" LATCH: [lindex $area_results 5]] - puts $out "$x6" - } - ## Report timing ### - puts $out "#=== Final timing ===" - puts $out "CP required: $t2" - puts $out "CP achieved: $t1" - if {$t1 == "NA"} { - puts $out "No Sequential Path" - } else { - if {[expr $t1 <= $t2]} { - puts $out "Timing met" - } else { - puts $out "Timing not met" - } - } -} - - -#---------------------------------------------------------------------------- -# dump_report_rodin_rb -# -# Generate rodin report -#---------------------------------------------------------------------------- -proc dump_report_rodin_rb { module out device} { - - ## Report area ### - - set area_results [extract_area_rodin ./report/${module}_utilization_routed.rpt] - puts $out "\$Footmark = \"FPGA_Xilinx\"" - puts $out "\$Description = \"by Vivado\"" - puts $out "" - puts $out "" - - puts $out "#=== Resource usage ===" - if {[lindex $area_results 7] != 0} { - puts $out "\$CLB = \"[lindex $area_results 7]\"" - } else { - puts $out "\$SLICE = \"[lindex $area_results 0]\"" - } - puts $out "\$LUT = \"[lindex $area_results 1]\"" - puts $out "\$FF = \"[lindex $area_results 2]\"" - puts $out "\$DSP = \"[lindex $area_results 3]\"" - puts $out "\$BRAM =\"[lindex $area_results 4]\"" - puts $out "\$SRL =\"[lindex $area_results 6]\"" - if {[lindex $area_results 8] != 0} { - puts $out "\$URAM = \"[lindex $area_results 8]\"" - } - - ## Report timing ### - puts $out "#=== Final timing ===" - set t2 [extract_target_clock_rpt $module] - set t1tmp0 [extract_timing_rodin ./report/${module}_timing_routed.rpt] - if { $t1tmp0 == "NA" } { - set t1 $t1tmp0 - } else { - set t1 [format "%2.3f" [expr $t2 - $t1tmp0]] - } - puts $out "\$TargetCP = \"$t2\"" - puts $out "\$CP = \"$t1\"" -} - -#---------------------------------------------------------------------------- -# dump_report_rodin_xml -# -# Generate rodin xml report -#---------------------------------------------------------------------------- -proc dump_report_rodin_xml { module out } { - - # collect data - set area_results [extract_area_rodin ./report/${module}_utilization_routed.rpt] - set slice [lindex $area_results 0] - set lut [lindex $area_results 1] - set ff [lindex $area_results 2] - set dsp [lindex $area_results 3] - set bram [lindex $area_results 4] - set srl [lindex $area_results 6] - set clb [lindex $area_results 7] - set uram [lindex $area_results 8] - set area_total [extract_total_rodin ./report/${module}_utilization_routed.rpt] - set t_slice [lindex $area_total 0] - set t_lut [lindex $area_total 1] - set t_ff [lindex $area_total 2] - set t_dsp [lindex $area_total 3] - set t_bram [lindex $area_total 4] - set t_clb [lindex $area_total 5] - set t_uram [lindex $area_total 6] - set targetcp [extract_target_clock_rpt $module] - set t1tmp0 [extract_timing_rodin ./report/${module}_timing_routed.rpt] - if { $t1tmp0 == "NA" } { - set achievedcp $t1tmp0 - } else { - set achievedcp [format "%2.3f" [expr $targetcp - $t1tmp0]] - } - # dump xml - puts $out "" - puts $out "" - puts $out "" - puts $out "" - if {$clb != 0} { - puts $out "$clb" - } else { - puts $out "$slice" - } - puts $out "$lut" - puts $out "$ff" - puts $out "$dsp" - puts $out "$bram" - if {$uram != 0} { - puts $out "$uram" - } - puts $out "$srl" - puts $out "" - puts $out "" - if {$t_clb != 0} { - puts $out "$t_clb" - } else { - puts $out "$t_slice" - } - puts $out "$t_lut" - puts $out "$t_ff" - puts $out "$t_dsp" - puts $out "$t_bram" - if {$t_uram != 0} { - puts $out "$t_uram" - } - puts $out "" - puts $out "" - puts $out "" - puts $out "" - puts $out "$targetcp" - puts $out "$achievedcp" - puts $out "" - puts $out "" - puts $out "" -} - -#---------------------------------------------------------------------------- -# compile_reports_dcp -# dump ${top_module}.rpt and ${top_module}.result.rb for dcp flow -#---------------------------------------------------------------------------- -proc compile_reports_dcp {top_module language device} { - set result_file [open ${top_module}.result w] - dump_report_dcp $top_module $result_file $device - close $result_file - - file mkdir ../report/${language} - report_copy ${top_module} "../report/${language}" - - set result_file [open ${top_module}.result.rb w] - dump_report_dcp_rb $top_module $result_file $device - close $result_file - - # gen xml report - set result_file [open ${top_module}.result.xml w] - dump_report_dcp_xml $top_module $result_file - close $result_file - - # copy xml report - xmlreport_copy ${top_module} "../report/${language}" - - dump_report_dcp $top_module stdout $device -} - -## extract target clock from rpt file -proc extract_target_clock_dcp {module} { - set t2 "NA" - set fl [open ./report/${module}_timing_synth.rpt r] - set report_buf [read -nonewline $fl] - close $fl - set clk_pattern {.*?Requirement: +(\d+\.\d+)ns.*} - if {![regexp $clk_pattern $report_buf match_clk t2]} { - set t2 [format "%2.3f" [extract_clk_period_sdc ${module}.xdc]] - } - return $t2 -} -#---------------------------------------------------------------------------- -# extract_timing_dcp -#---------------------------------------------------------------------------- -proc extract_timing_dcp {file_name} { - - set report_file [open $file_name r] - set report_buf [read -nonewline $report_file] - close $report_file - - set clk_pattern_met {.*?Slack +\(\S+?\) +: +(\d+\.\d+)ns.*} - set clk_pattern_violated {.*?Slack +\(\S+?\) +: +-(\d+\.\d+)ns.*} - if {[regexp ${clk_pattern_met} $report_buf match slack]} { - return $slack - } elseif {[regexp ${clk_pattern_violated} $report_buf match slack]} { - return [expr 0.0 - $slack] - } - return "NA" -} - -proc dump_report_dcp { module out device} { - - set fl [open ./report/${module}_timing_synth.rpt r] - set report_buf [read -nonewline $fl] - close $fl - #set ver_pattern {.*Version : +(\S+) +(\S+) .*} - set ver_pattern {.*Version.*Vivado +(\S+) +(\S+) .*} - if {![regexp $ver_pattern $report_buf match_ver ver0 ver]} { - set ver UNKNOWN - } - - set dev $device - - set date [clock format [clock seconds]] - - ## Report area ### - - set area_results [extract_area_rodin ./report/${module}_utilization_synth.rpt] - puts $out "" - puts $out "" - puts $out "Implementation tool: Xilinx Vivado $ver0" - puts $out "Device target: $dev" - puts $out "Report date: $date" - puts $out "" - - set x1 [format "%-10s %8d" SLICE: [lindex $area_results 0]] - set x2 [format "%-10s %8d" LUT: [lindex $area_results 1]] - set x3 [format "%-10s %8d" FF: [lindex $area_results 2]] - set x4 [format "%-10s %8d" DSP: [lindex $area_results 3]] - set x5 [format "%-10s %8d" BRAM: [lindex $area_results 4]] - set x7 [format "%-10s %8d" SRL: [lindex $area_results 6]] - set x8 [format "%-10s %8d" CLB: [lindex $area_results 7]] - - set t2 [extract_target_clock_dcp $module] - set t1tmp0 [extract_timing_dcp ./report/${module}_timing_synth.rpt] - if { $t1tmp0 == "NA" } { - set t1 $t1tmp0 - } else { - set t1 [format "%2.3f" [expr $t2 - $t1tmp0]] - } - - puts $out "#=== Resource usage ===" - if {[lindex $area_results 7] != 0} { - puts $out "$x8" - } else { - puts $out "$x1" - } - puts $out "$x2" - puts $out "$x3" - puts $out "$x4" - puts $out "$x5" - puts $out "$x7" - if {[lindex $area_results 5] != 0} { - set x6 [format "%-10s %8d" LATCH: [lindex $area_results 5]] - puts $out "$x6" - } - ## Report timing ### - puts $out "#=== Final timing ===" - puts $out "CP required: $t2" - puts $out "CP achieved: $t1" - if {$t1 == "NA"} { - puts $out "No Sequential Path" - } else { - if {[expr $t1 <= $t2]} { - puts $out "Timing met" - } else { - puts $out "Timing not met" - } - } -} - - -#---------------------------------------------------------------------------- -# dump_report_dcp_rb -# -# Generate dcp report -#---------------------------------------------------------------------------- -proc dump_report_dcp_rb { module out device} { - - ## Report area ### - set area_results [extract_area_rodin ./report/${module}_utilization_synth.rpt] - puts $out "\$Footmark = \"FPGA_Xilinx\"" - puts $out "\$Description = \"by Vivado\"" - puts $out "" - puts $out "" - - puts $out "#=== Resource usage ===" - if {[lindex $area_results 7] != 0} { - puts $out "\$CLB = \"[lindex $area_results 7]\"" - } else { - puts $out "\$SLICE = \"[lindex $area_results 0]\"" - } - puts $out "\$LUT = \"[lindex $area_results 1]\"" - puts $out "\$FF = \"[lindex $area_results 2]\"" - puts $out "\$DSP = \"[lindex $area_results 3]\"" - puts $out "\$BRAM =\"[lindex $area_results 4]\"" - puts $out "\$SRL =\"[lindex $area_results 6]\"" - - ## Report timing ### - puts $out "#=== Final timing ===" - set t2 [extract_target_clock_dcp $module] - set t1tmp0 [extract_timing_dcp ./report/${module}_timing_synth.rpt] - if { $t1tmp0 == "NA" } { - set t1 $t1tmp0 - } else { - set t1 [format "%2.3f" [expr $t2 - $t1tmp0]] - } - puts $out "\$TargetCP = \"$t2\"" - puts $out "\$CP = \"$t1\"" -} - -#---------------------------------------------------------------------------- -# dump_report_dcp_xml -# -# Generate dcp xml report -#---------------------------------------------------------------------------- -proc dump_report_dcp_xml { module out } { - - # collect data - set area_results [extract_area_rodin ./report/${module}_utilization_synth.rpt] - set slice [lindex $area_results 0] - set lut [lindex $area_results 1] - set ff [lindex $area_results 2] - set dsp [lindex $area_results 3] - set bram [lindex $area_results 4] - set srl [lindex $area_results 6] - set clb [lindex $area_results 7] - set targetcp [extract_target_clock_dcp $module] - set t1tmp0 [extract_timing_dcp ./report/${module}_timing_synth.rpt] - if { $t1tmp0 == "NA" } { - set achievedcp $t1tmp0 - } else { - set achievedcp [format "%2.3f" [expr $targetcp - $t1tmp0]] - } - # dump xml - puts $out "" - puts $out "" - puts $out "" - puts $out "" - if {$clb != 0} { - puts $out "$clb" - } else { - puts $out "$slice" - } - puts $out "$lut" - puts $out "$ff" - puts $out "$dsp" - puts $out "$bram" - puts $out "$srl" - puts $out "" - puts $out "" - puts $out "" - puts $out "" - puts $out "$targetcp" - puts $out "$achievedcp" - puts $out "" - puts $out "" - puts $out "" -} - -# vim:set ts=4 sw=4 et: - -# XSIP watermark, do not delete 67d7842dbbe25473c3c32b93c0da8047785f30d78e8a024de1b57352245f9689 diff --git a/l2_trigger/solution1/impl/verilog/l2_trigger.v b/l2_trigger/solution1/impl/verilog/l2_trigger.v deleted file mode 100644 index f6eee00..0000000 --- a/l2_trigger/solution1/impl/verilog/l2_trigger.v +++ /dev/null @@ -1,1745 +0,0 @@ -// ============================================================== -// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -// Version: 2016.2 -// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved. -// -// =========================================================== - -`timescale 1 ns / 1 ps - -(* CORE_GENERATION_INFO="l2_trigger,hls_ip_2016_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z030ffg676-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.650000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=58,HLS_SYN_DSP=4,HLS_SYN_FF=746,HLS_SYN_LUT=1141}" *) - -module l2_trigger ( - ap_clk, - ap_rst_n, - in_stream_TDATA, - in_stream_TVALID, - in_stream_TREADY, - in_stream_TKEEP, - in_stream_TSTRB, - in_stream_TUSER, - in_stream_TLAST, - in_stream_TID, - in_stream_TDEST, - out_stream_TDATA, - out_stream_TVALID, - out_stream_TREADY, - out_stream_TKEEP, - out_stream_TSTRB, - out_stream_TUSER, - out_stream_TLAST, - out_stream_TID, - out_stream_TDEST, - trig_data, - trig_data_ap_vld, - trig_pixel, - trig_pixel_ap_vld, - s_axi_CTRL_BUS_AWVALID, - s_axi_CTRL_BUS_AWREADY, - s_axi_CTRL_BUS_AWADDR, - s_axi_CTRL_BUS_WVALID, - s_axi_CTRL_BUS_WREADY, - s_axi_CTRL_BUS_WDATA, - s_axi_CTRL_BUS_WSTRB, - s_axi_CTRL_BUS_ARVALID, - s_axi_CTRL_BUS_ARREADY, - s_axi_CTRL_BUS_ARADDR, - s_axi_CTRL_BUS_RVALID, - s_axi_CTRL_BUS_RREADY, - s_axi_CTRL_BUS_RDATA, - s_axi_CTRL_BUS_RRESP, - s_axi_CTRL_BUS_BVALID, - s_axi_CTRL_BUS_BREADY, - s_axi_CTRL_BUS_BRESP, - interrupt -); - -parameter ap_ST_st1_fsm_0 = 22'b1; -parameter ap_ST_st2_fsm_1 = 22'b10; -parameter ap_ST_st3_fsm_2 = 22'b100; -parameter ap_ST_st4_fsm_3 = 22'b1000; -parameter ap_ST_st5_fsm_4 = 22'b10000; -parameter ap_ST_st6_fsm_5 = 22'b100000; -parameter ap_ST_st7_fsm_6 = 22'b1000000; -parameter ap_ST_st8_fsm_7 = 22'b10000000; -parameter ap_ST_st9_fsm_8 = 22'b100000000; -parameter ap_ST_st10_fsm_9 = 22'b1000000000; -parameter ap_ST_st11_fsm_10 = 22'b10000000000; -parameter ap_ST_st12_fsm_11 = 22'b100000000000; -parameter ap_ST_st13_fsm_12 = 22'b1000000000000; -parameter ap_ST_st14_fsm_13 = 22'b10000000000000; -parameter ap_ST_st15_fsm_14 = 22'b100000000000000; -parameter ap_ST_st16_fsm_15 = 22'b1000000000000000; -parameter ap_ST_st17_fsm_16 = 22'b10000000000000000; -parameter ap_ST_st18_fsm_17 = 22'b100000000000000000; -parameter ap_ST_st19_fsm_18 = 22'b1000000000000000000; -parameter ap_ST_st20_fsm_19 = 22'b10000000000000000000; -parameter ap_ST_st21_fsm_20 = 22'b100000000000000000000; -parameter ap_ST_st22_fsm_21 = 22'b1000000000000000000000; -parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000; -parameter ap_const_lv32_8 = 32'b1000; -parameter ap_const_lv32_12 = 32'b10010; -parameter C_S_AXI_CTRL_BUS_DATA_WIDTH = 32; -parameter ap_const_int64_8 = 8; -parameter C_S_AXI_CTRL_BUS_ADDR_WIDTH = 6; -parameter C_S_AXI_DATA_WIDTH = 32; -parameter ap_const_lv32_1 = 32'b1; -parameter ap_const_lv32_2 = 32'b10; -parameter ap_const_lv32_3 = 32'b11; -parameter ap_const_lv32_5 = 32'b101; -parameter ap_const_lv32_6 = 32'b110; -parameter ap_const_lv32_7 = 32'b111; -parameter ap_const_lv32_9 = 32'b1001; -parameter ap_const_lv32_A = 32'b1010; -parameter ap_const_lv32_B = 32'b1011; -parameter ap_const_lv32_11 = 32'b10001; -parameter ap_const_lv32_13 = 32'b10011; -parameter ap_const_lv32_14 = 32'b10100; -parameter ap_const_lv15_0 = 15'b000000000000000; -parameter ap_const_lv4_0 = 4'b0000; -parameter ap_const_lv32_4 = 32'b100; -parameter ap_const_lv8_0 = 8'b00000000; -parameter ap_const_lv32_E = 32'b1110; -parameter ap_const_lv32_C = 32'b1100; -parameter ap_const_lv32_10 = 32'b10000; -parameter ap_const_lv4_6 = 4'b110; -parameter ap_const_lv32_15 = 32'b10101; -parameter ap_const_lv32_D = 32'b1101; -parameter ap_const_lv32_F = 32'b1111; -parameter ap_const_lv8_FF = 8'b11111111; -parameter ap_const_lv2_0 = 2'b00; -parameter ap_const_lv5_0 = 5'b00000; -parameter ap_const_lv6_0 = 6'b000000; -parameter ap_const_lv32_639C = 32'b110001110011100; -parameter ap_const_lv17_0 = 17'b00000000000000000; -parameter ap_const_lv15_1 = 15'b1; -parameter ap_const_lv4_8 = 4'b1000; -parameter ap_const_lv4_1 = 4'b1; -parameter ap_const_lv10_0 = 10'b0000000000; -parameter ap_const_lv7_0 = 7'b0000000; -parameter ap_const_lv8_80 = 8'b10000000; -parameter ap_const_lv8_1 = 8'b1; -parameter ap_const_lv32_1F = 32'b11111; -parameter ap_const_lv4_F = 4'b1111; -parameter ap_const_lv16_1 = 16'b1; -parameter ap_const_lv3_0 = 3'b000; - -parameter C_S_AXI_CTRL_BUS_WSTRB_WIDTH = (C_S_AXI_CTRL_BUS_DATA_WIDTH / ap_const_int64_8); -parameter C_S_AXI_WSTRB_WIDTH = (C_S_AXI_DATA_WIDTH / ap_const_int64_8); - -input ap_clk; -input ap_rst_n; -input [31:0] in_stream_TDATA; -input in_stream_TVALID; -output in_stream_TREADY; -input [3:0] in_stream_TKEEP; -input [3:0] in_stream_TSTRB; -input [1:0] in_stream_TUSER; -input [0:0] in_stream_TLAST; -input [4:0] in_stream_TID; -input [5:0] in_stream_TDEST; -output [63:0] out_stream_TDATA; -output out_stream_TVALID; -input out_stream_TREADY; -output [7:0] out_stream_TKEEP; -output [7:0] out_stream_TSTRB; -output [1:0] out_stream_TUSER; -output [0:0] out_stream_TLAST; -output [4:0] out_stream_TID; -output [5:0] out_stream_TDEST; -output [31:0] trig_data; -output trig_data_ap_vld; -output [31:0] trig_pixel; -output trig_pixel_ap_vld; -input s_axi_CTRL_BUS_AWVALID; -output s_axi_CTRL_BUS_AWREADY; -input [C_S_AXI_CTRL_BUS_ADDR_WIDTH - 1 : 0] s_axi_CTRL_BUS_AWADDR; -input s_axi_CTRL_BUS_WVALID; -output s_axi_CTRL_BUS_WREADY; -input [C_S_AXI_CTRL_BUS_DATA_WIDTH - 1 : 0] s_axi_CTRL_BUS_WDATA; -input [C_S_AXI_CTRL_BUS_WSTRB_WIDTH - 1 : 0] s_axi_CTRL_BUS_WSTRB; -input s_axi_CTRL_BUS_ARVALID; -output s_axi_CTRL_BUS_ARREADY; -input [C_S_AXI_CTRL_BUS_ADDR_WIDTH - 1 : 0] s_axi_CTRL_BUS_ARADDR; -output s_axi_CTRL_BUS_RVALID; -input s_axi_CTRL_BUS_RREADY; -output [C_S_AXI_CTRL_BUS_DATA_WIDTH - 1 : 0] s_axi_CTRL_BUS_RDATA; -output [1:0] s_axi_CTRL_BUS_RRESP; -output s_axi_CTRL_BUS_BVALID; -input s_axi_CTRL_BUS_BREADY; -output [1:0] s_axi_CTRL_BUS_BRESP; -output interrupt; - -reg in_stream_TREADY; -reg out_stream_TVALID; -reg[31:0] trig_data; -reg trig_data_ap_vld; -reg trig_pixel_ap_vld; - -reg ap_rst_n_inv; -wire ap_start; -reg ap_done; -reg ap_idle; -(* fsm_encoding = "none" *) reg [21:0] ap_CS_fsm; -reg ap_sig_cseq_ST_st1_fsm_0; -reg ap_sig_39; -reg ap_ready; -wire [15:0] n_pixels_in_bus; -wire [7:0] N_BG; -wire [31:0] LOW_THRESH; -reg in_stream_TDATA_blk_n; -reg ap_sig_cseq_ST_st9_fsm_8; -reg ap_sig_77; -reg out_stream_TDATA_blk_n; -reg ap_sig_cseq_ST_st19_fsm_18; -reg ap_sig_85; -reg [31:0] LOW_THRESH_read_reg_1104; -wire [31:0] tmp_1_fu_639_p1; -reg [31:0] tmp_1_reg_1112; -reg [14:0] tmp_2_reg_1118; -wire [14:0] i_5_fu_658_p2; -reg ap_sig_cseq_ST_st2_fsm_1; -reg ap_sig_139; -wire [3:0] kk_2_fu_678_p2; -reg [3:0] kk_2_reg_1138; -reg ap_sig_cseq_ST_st3_fsm_2; -reg ap_sig_148; -wire [14:0] tmp_3_fu_708_p2; -reg [14:0] tmp_3_reg_1143; -wire [0:0] exitcond1_fu_672_p2; -wire [14:0] i_6_fu_719_p2; -reg ap_sig_cseq_ST_st4_fsm_3; -reg ap_sig_163; -wire [14:0] i_7_fu_741_p2; -reg ap_sig_cseq_ST_st6_fsm_5; -reg ap_sig_172; -wire [7:0] tmp_5_fu_759_p2; -reg [7:0] tmp_5_reg_1170; -reg ap_sig_cseq_ST_st7_fsm_6; -reg ap_sig_181; -wire [14:0] i_9_fu_770_p2; -reg [14:0] i_9_reg_1178; -reg ap_sig_cseq_ST_st8_fsm_7; -reg ap_sig_190; -wire [63:0] tmp_15_fu_776_p1; -reg [63:0] tmp_15_reg_1186; -wire [0:0] exitcond7_fu_765_p2; -reg [10:0] sum_pix1_addr_3_reg_1196; -reg [10:0] sum_pix2_addr_3_reg_1201; -reg [13:0] data_shift1_addr_1_reg_1206; -reg [13:0] data_shift2_addr_1_reg_1211; -wire [15:0] tmp_16_fu_786_p1; -reg [15:0] tmp_16_reg_1216; -wire [15:0] phitmp_fu_790_p4; -reg [15:0] phitmp_reg_1221; -wire signed [31:0] tmp_17_fu_800_p1; -reg signed [31:0] tmp_17_reg_1226; -wire signed [31:0] tmp_19_fu_811_p1; -reg signed [31:0] tmp_19_reg_1231; -reg [10:0] sum_overP1_addr_reg_1236; -reg [10:0] sum_overP2_addr_reg_1241; -reg ap_sig_cseq_ST_st10_fsm_9; -reg ap_sig_227; -wire [0:0] tmp_22_fu_822_p3; -wire [3:0] kk_3_fu_950_p2; -reg ap_sig_cseq_ST_st11_fsm_10; -reg ap_sig_245; -wire [31:0] tmp_24_fu_962_p2; -reg [31:0] tmp_24_reg_1269; -reg ap_sig_cseq_ST_st12_fsm_11; -reg ap_sig_254; -wire [0:0] tmp_25_fu_968_p2; -wire [0:0] grp_fu_633_p2; -reg [0:0] tmp_36_reg_1282; -wire [14:0] i_8_fu_1021_p2; -reg [14:0] i_8_reg_1296; -reg ap_sig_cseq_ST_st18_fsm_17; -reg ap_sig_270; -wire [0:0] exitcond6_fu_1016_p2; -reg [10:0] thresh1_addr_1_reg_1311; -reg [10:0] thresh2_addr_1_reg_1316; -reg [24:0] tmp_10_reg_1321; -reg ap_sig_ioackin_out_stream_TREADY; -reg [24:0] tmp_11_reg_1326; -wire [31:0] tmp_12_fu_1086_p2; -reg [31:0] tmp_12_reg_1331; -reg ap_sig_cseq_ST_st20_fsm_19; -reg ap_sig_298; -wire [31:0] tmp_13_fu_1091_p2; -reg [31:0] tmp_13_reg_1337; -wire [0:0] tmp_14_fu_1096_p2; -reg [0:0] tmp_14_reg_1343; -reg ap_sig_cseq_ST_st21_fsm_20; -reg ap_sig_309; -reg [10:0] sum_overP1_address0; -reg sum_overP1_ce0; -reg sum_overP1_we0; -reg [31:0] sum_overP1_d0; -wire [31:0] sum_overP1_q0; -reg [10:0] sum_overP2_address0; -reg sum_overP2_ce0; -reg sum_overP2_we0; -reg [31:0] sum_overP2_d0; -wire [31:0] sum_overP2_q0; -reg [10:0] sum_pix1_address0; -reg sum_pix1_ce0; -reg sum_pix1_we0; -reg [31:0] sum_pix1_d0; -wire [31:0] sum_pix1_q0; -reg [13:0] data_shift1_address0; -reg data_shift1_ce0; -reg data_shift1_we0; -reg [16:0] data_shift1_d0; -wire [16:0] data_shift1_q0; -reg [10:0] thresh1_address0; -reg thresh1_ce0; -reg thresh1_we0; -reg [31:0] thresh1_d0; -wire [31:0] thresh1_q0; -reg [10:0] sum_pix2_address0; -reg sum_pix2_ce0; -reg sum_pix2_we0; -reg [31:0] sum_pix2_d0; -wire [31:0] sum_pix2_q0; -reg [13:0] data_shift2_address0; -reg data_shift2_ce0; -reg data_shift2_we0; -reg [16:0] data_shift2_d0; -wire [16:0] data_shift2_q0; -reg [10:0] thresh2_address0; -reg thresh2_ce0; -reg thresh2_we0; -reg [31:0] thresh2_d0; -wire [31:0] thresh2_q0; -reg [14:0] i_reg_502; -wire [0:0] exitcond2_fu_653_p2; -reg [3:0] kk_reg_513; -wire [0:0] exitcond9_fu_714_p2; -reg [14:0] i_1_reg_524; -reg [14:0] i_2_reg_535; -wire [0:0] exitcond8_fu_736_p2; -reg ap_sig_cseq_ST_st5_fsm_4; -reg ap_sig_413; -wire [0:0] tmp_nbreadreq_fu_226_p9; -reg [7:0] k_reg_546; -reg [31:0] itrig_reg_557; -reg [14:0] i_3_reg_569; -wire [0:0] exitcond_fu_753_p2; -reg ap_sig_cseq_ST_st15_fsm_14; -reg ap_sig_439; -reg ap_sig_cseq_ST_st13_fsm_12; -reg ap_sig_446; -wire [0:0] or_cond_fu_979_p2; -reg ap_sig_cseq_ST_st17_fsm_16; -reg ap_sig_457; -reg [31:0] itrig_1_reg_587; -reg [3:0] kk_1_reg_610; -reg [14:0] i_4_reg_622; -reg ap_sig_cseq_ST_st22_fsm_21; -reg ap_sig_478; -wire [63:0] tmp_4_fu_664_p1; -wire [63:0] tmp_18_cast_fu_730_p1; -wire [63:0] tmp_7_fu_747_p1; -wire [63:0] tmp_45_cast_fu_866_p1; -wire [63:0] tmp_49_cast_fu_926_p1; -wire [63:0] tmp_9_fu_1027_p1; -reg ap_sig_cseq_ST_st14_fsm_13; -reg ap_sig_511; -wire [31:0] tmp_40_cast_fu_998_p1; -reg ap_sig_cseq_ST_st16_fsm_15; -reg ap_sig_520; -wire [31:0] tmp_38_cast_fu_1011_p1; -reg ap_reg_ioackin_out_stream_TREADY; -wire [31:0] tmp_18_fu_804_p2; -wire [31:0] tmp_20_fu_815_p2; -wire [0:0] tmp_21_fu_1100_p2; -wire signed [16:0] tmp_19_cast_fu_872_p1; -wire signed [16:0] tmp_21_cast_fu_876_p1; -wire [31:0] tmp_29_fu_936_p2; -wire [31:0] tmp_23_fu_956_p2; -wire [31:0] tmp_30_fu_943_p2; -wire [13:0] tmp_6_fu_684_p3; -wire [10:0] tmp_s_fu_696_p3; -wire [14:0] p_shl1_cast_fu_704_p1; -wire [14:0] p_shl_cast_fu_692_p1; -wire [14:0] tmp_8_fu_725_p2; -wire [13:0] tmp_26_fu_830_p3; -wire [10:0] tmp_28_fu_842_p3; -wire signed [14:0] p_shl5_cast_fu_850_p1; -wire signed [14:0] p_shl4_cast_fu_838_p1; -wire [14:0] tmp_31_fu_854_p2; -wire [14:0] tmp_32_fu_860_p2; -wire [3:0] tmp_27_fu_884_p2; -wire [13:0] tmp_33_fu_890_p3; -wire [10:0] tmp_40_fu_902_p3; -wire [14:0] p_shl3_cast_fu_910_p1; -wire [14:0] p_shl2_cast_fu_898_p1; -wire [14:0] tmp_41_fu_914_p2; -wire [14:0] tmp_42_fu_920_p2; -wire signed [31:0] extLd_fu_880_p1; -wire signed [31:0] extLd1_fu_932_p1; -wire [0:0] tmp_35_fu_974_p2; -wire [15:0] tmp_38_fu_984_p3; -wire [15:0] tmp_39_fu_992_p2; -wire [15:0] tmp_37_fu_1003_p3; -wire [27:0] sum_pixP1_fu_1064_p3; -wire [27:0] sum_pixP2_fu_1075_p3; -wire [27:0] tmp_12_fu_1086_p0; -wire [7:0] tmp_12_fu_1086_p1; -wire [27:0] tmp_13_fu_1091_p0; -wire [7:0] tmp_13_fu_1091_p1; -reg [21:0] ap_NS_fsm; -wire [31:0] tmp_12_fu_1086_p00; -wire [31:0] tmp_13_fu_1091_p00; - -// power-on initialization -initial begin -#0 ap_CS_fsm = 22'b1; -#0 ap_reg_ioackin_out_stream_TREADY = 1'b0; -end - -l2_trigger_CTRL_BUS_s_axi #( - .C_S_AXI_ADDR_WIDTH( C_S_AXI_CTRL_BUS_ADDR_WIDTH ), - .C_S_AXI_DATA_WIDTH( C_S_AXI_CTRL_BUS_DATA_WIDTH )) -l2_trigger_CTRL_BUS_s_axi_U( - .AWVALID(s_axi_CTRL_BUS_AWVALID), - .AWREADY(s_axi_CTRL_BUS_AWREADY), - .AWADDR(s_axi_CTRL_BUS_AWADDR), - .WVALID(s_axi_CTRL_BUS_WVALID), - .WREADY(s_axi_CTRL_BUS_WREADY), - .WDATA(s_axi_CTRL_BUS_WDATA), - .WSTRB(s_axi_CTRL_BUS_WSTRB), - .ARVALID(s_axi_CTRL_BUS_ARVALID), - .ARREADY(s_axi_CTRL_BUS_ARREADY), - .ARADDR(s_axi_CTRL_BUS_ARADDR), - .RVALID(s_axi_CTRL_BUS_RVALID), - .RREADY(s_axi_CTRL_BUS_RREADY), - .RDATA(s_axi_CTRL_BUS_RDATA), - .RRESP(s_axi_CTRL_BUS_RRESP), - .BVALID(s_axi_CTRL_BUS_BVALID), - .BREADY(s_axi_CTRL_BUS_BREADY), - .BRESP(s_axi_CTRL_BUS_BRESP), - .ACLK(ap_clk), - .ARESET(ap_rst_n_inv), - .ACLK_EN(1'b1), - .ap_start(ap_start), - .interrupt(interrupt), - .ap_ready(ap_ready), - .ap_done(ap_done), - .ap_idle(ap_idle), - .n_pixels_in_bus(n_pixels_in_bus), - .N_BG(N_BG), - .LOW_THRESH(LOW_THRESH) -); - -l2_trigger_sum_overP1 #( - .DataWidth( 32 ), - .AddressRange( 1152 ), - .AddressWidth( 11 )) -sum_overP1_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(sum_overP1_address0), - .ce0(sum_overP1_ce0), - .we0(sum_overP1_we0), - .d0(sum_overP1_d0), - .q0(sum_overP1_q0) -); - -l2_trigger_sum_overP1 #( - .DataWidth( 32 ), - .AddressRange( 1152 ), - .AddressWidth( 11 )) -sum_overP2_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(sum_overP2_address0), - .ce0(sum_overP2_ce0), - .we0(sum_overP2_we0), - .d0(sum_overP2_d0), - .q0(sum_overP2_q0) -); - -l2_trigger_sum_overP1 #( - .DataWidth( 32 ), - .AddressRange( 1152 ), - .AddressWidth( 11 )) -sum_pix1_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(sum_pix1_address0), - .ce0(sum_pix1_ce0), - .we0(sum_pix1_we0), - .d0(sum_pix1_d0), - .q0(sum_pix1_q0) -); - -l2_trigger_data_shift1 #( - .DataWidth( 17 ), - .AddressRange( 9216 ), - .AddressWidth( 14 )) -data_shift1_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(data_shift1_address0), - .ce0(data_shift1_ce0), - .we0(data_shift1_we0), - .d0(data_shift1_d0), - .q0(data_shift1_q0) -); - -l2_trigger_sum_overP1 #( - .DataWidth( 32 ), - .AddressRange( 1152 ), - .AddressWidth( 11 )) -thresh1_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(thresh1_address0), - .ce0(thresh1_ce0), - .we0(thresh1_we0), - .d0(thresh1_d0), - .q0(thresh1_q0) -); - -l2_trigger_sum_overP1 #( - .DataWidth( 32 ), - .AddressRange( 1152 ), - .AddressWidth( 11 )) -sum_pix2_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(sum_pix2_address0), - .ce0(sum_pix2_ce0), - .we0(sum_pix2_we0), - .d0(sum_pix2_d0), - .q0(sum_pix2_q0) -); - -l2_trigger_data_shift1 #( - .DataWidth( 17 ), - .AddressRange( 9216 ), - .AddressWidth( 14 )) -data_shift2_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(data_shift2_address0), - .ce0(data_shift2_ce0), - .we0(data_shift2_we0), - .d0(data_shift2_d0), - .q0(data_shift2_q0) -); - -l2_trigger_sum_overP1 #( - .DataWidth( 32 ), - .AddressRange( 1152 ), - .AddressWidth( 11 )) -thresh2_U( - .clk(ap_clk), - .reset(ap_rst_n_inv), - .address0(thresh2_address0), - .ce0(thresh2_ce0), - .we0(thresh2_we0), - .d0(thresh2_d0), - .q0(thresh2_q0) -); - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - ap_CS_fsm <= ap_ST_st1_fsm_0; - end else begin - ap_CS_fsm <= ap_NS_fsm; - end -end - -always @ (posedge ap_clk) begin - if (ap_rst_n_inv == 1'b1) begin - ap_reg_ioackin_out_stream_TREADY <= 1'b0; - end else begin - if (((1'b1 == ap_sig_cseq_ST_st19_fsm_18) & ~(1'b0 == ap_sig_ioackin_out_stream_TREADY))) begin - ap_reg_ioackin_out_stream_TREADY <= 1'b0; - end else if (((1'b1 == ap_sig_cseq_ST_st19_fsm_18) & (1'b1 == out_stream_TREADY))) begin - ap_reg_ioackin_out_stream_TREADY <= 1'b1; - end - end -end - -always @ (posedge ap_clk) begin - if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & (exitcond1_fu_672_p2 == 1'b0))) begin - i_1_reg_524 <= ap_const_lv15_0; - end else if (((1'b1 == ap_sig_cseq_ST_st4_fsm_3) & (1'b0 == exitcond9_fu_714_p2))) begin - i_1_reg_524 <= i_6_fu_719_p2; - end -end - -always @ (posedge ap_clk) begin - if (((1'b1 == ap_sig_cseq_ST_st5_fsm_4) & ~(1'b0 == tmp_nbreadreq_fu_226_p9))) begin - i_2_reg_535 <= ap_const_lv15_0; - end else if (((1'b1 == ap_sig_cseq_ST_st6_fsm_5) & (1'b0 == exitcond8_fu_736_p2))) begin - i_2_reg_535 <= i_7_fu_741_p2; - end -end - -always @ (posedge ap_clk) begin - if (((1'b1 == ap_sig_cseq_ST_st15_fsm_14) | ((1'b1 == ap_sig_cseq_ST_st13_fsm_12) & (1'b0 == or_cond_fu_979_p2)) | (1'b1 == ap_sig_cseq_ST_st17_fsm_16) | ((1'b1 == ap_sig_cseq_ST_st12_fsm_11) & (1'b0 == grp_fu_633_p2) & ~(1'b0 == tmp_25_fu_968_p2)))) begin - i_3_reg_569 <= i_9_reg_1178; - end else if (((1'b1 == ap_sig_cseq_ST_st7_fsm_6) & (1'b0 == exitcond_fu_753_p2))) begin - i_3_reg_569 <= ap_const_lv15_0; - end -end - -always @ (posedge ap_clk) begin - if (((1'b1 == ap_sig_cseq_ST_st7_fsm_6) & ~(1'b0 == exitcond_fu_753_p2))) begin - i_4_reg_622 <= ap_const_lv15_0; - end else if ((1'b1 == ap_sig_cseq_ST_st22_fsm_21)) begin - i_4_reg_622 <= i_8_reg_1296; - end -end - -always @ (posedge ap_clk) begin - if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & (1'b0 == exitcond2_fu_653_p2))) begin - i_reg_502 <= i_5_fu_658_p2; - end else if (((1'b1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == 1'b0))) begin - i_reg_502 <= ap_const_lv15_0; - end -end - -always @ (posedge ap_clk) begin - if ((((1'b1 == ap_sig_cseq_ST_st13_fsm_12) & (1'b0 == or_cond_fu_979_p2)) | ((1'b1 == ap_sig_cseq_ST_st12_fsm_11) & (1'b0 == grp_fu_633_p2) & ~(1'b0 == tmp_25_fu_968_p2)))) begin - itrig_1_reg_587 <= itrig_1_reg_587; - end else if (((1'b1 == ap_sig_cseq_ST_st15_fsm_14) | (1'b1 == ap_sig_cseq_ST_st17_fsm_16))) begin - itrig_1_reg_587 <= ap_const_lv32_1; - end else if (((1'b1 == ap_sig_cseq_ST_st7_fsm_6) & (1'b0 == exitcond_fu_753_p2))) begin - itrig_1_reg_587 <= itrig_reg_557; - end -end - -always @ (posedge ap_clk) begin - if (((1'b1 == ap_sig_cseq_ST_st8_fsm_7) & ~(1'b0 == exitcond7_fu_765_p2))) begin - itrig_reg_557 <= itrig_1_reg_587; - end else if (((1'b1 == ap_sig_cseq_ST_st6_fsm_5) & ~(1'b0 == exitcond8_fu_736_p2))) begin - itrig_reg_557 <= ap_const_lv32_0; - end -end - -always @ (posedge ap_clk) begin - if (((1'b1 == ap_sig_cseq_ST_st8_fsm_7) & ~(1'b0 == exitcond7_fu_765_p2))) begin - k_reg_546 <= tmp_5_reg_1170; - end else if (((1'b1 == ap_sig_cseq_ST_st6_fsm_5) & ~(1'b0 == exitcond8_fu_736_p2))) begin - k_reg_546 <= ap_const_lv8_0; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_sig_cseq_ST_st11_fsm_10)) begin - kk_1_reg_610 <= kk_3_fu_950_p2; - end else if (((1'b1 == ap_sig_cseq_ST_st9_fsm_8) & ~(in_stream_TVALID == 1'b0))) begin - kk_1_reg_610 <= ap_const_lv4_6; - end -end - -always @ (posedge ap_clk) begin - if (((1'b1 == ap_sig_cseq_ST_st4_fsm_3) & ~(1'b0 == exitcond9_fu_714_p2))) begin - kk_reg_513 <= kk_2_reg_1138; - end else if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & ~(1'b0 == exitcond2_fu_653_p2))) begin - kk_reg_513 <= ap_const_lv4_0; - end -end - -always @ (posedge ap_clk) begin - if (((1'b1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == 1'b0))) begin - LOW_THRESH_read_reg_1104 <= LOW_THRESH; - tmp_1_reg_1112[7 : 0] <= tmp_1_fu_639_p1[7 : 0]; - tmp_2_reg_1118 <= {{n_pixels_in_bus[ap_const_lv32_F : ap_const_lv32_1]}}; - end -end - -always @ (posedge ap_clk) begin - if (((1'b1 == ap_sig_cseq_ST_st9_fsm_8) & ~(in_stream_TVALID == 1'b0))) begin - data_shift1_addr_1_reg_1206 <= tmp_15_reg_1186; - data_shift2_addr_1_reg_1211 <= tmp_15_reg_1186; - phitmp_reg_1221 <= {{in_stream_TDATA[ap_const_lv32_1F : ap_const_lv32_10]}}; - sum_overP1_addr_reg_1236 <= tmp_15_reg_1186; - sum_overP2_addr_reg_1241 <= tmp_15_reg_1186; - tmp_16_reg_1216 <= tmp_16_fu_786_p1; - tmp_17_reg_1226 <= tmp_17_fu_800_p1; - tmp_19_reg_1231 <= tmp_19_fu_811_p1; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_sig_cseq_ST_st18_fsm_17)) begin - i_8_reg_1296 <= i_8_fu_1021_p2; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_sig_cseq_ST_st8_fsm_7)) begin - i_9_reg_1178 <= i_9_fu_770_p2; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_sig_cseq_ST_st3_fsm_2)) begin - kk_2_reg_1138 <= kk_2_fu_678_p2; - end -end - -always @ (posedge ap_clk) begin - if (((1'b1 == ap_sig_cseq_ST_st8_fsm_7) & (1'b0 == exitcond7_fu_765_p2))) begin - sum_pix1_addr_3_reg_1196 <= tmp_15_fu_776_p1; - sum_pix2_addr_3_reg_1201 <= tmp_15_fu_776_p1; - tmp_15_reg_1186[14 : 0] <= tmp_15_fu_776_p1[14 : 0]; - end -end - -always @ (posedge ap_clk) begin - if (((1'b1 == ap_sig_cseq_ST_st18_fsm_17) & (1'b0 == exitcond6_fu_1016_p2))) begin - thresh1_addr_1_reg_1311 <= tmp_9_fu_1027_p1; - thresh2_addr_1_reg_1316 <= tmp_9_fu_1027_p1; - end -end - -always @ (posedge ap_clk) begin - if (((1'b1 == ap_sig_cseq_ST_st19_fsm_18) & ~(1'b0 == ap_sig_ioackin_out_stream_TREADY))) begin - tmp_10_reg_1321 <= {{sum_pix1_q0[ap_const_lv32_1F : ap_const_lv32_7]}}; - tmp_11_reg_1326 <= {{sum_pix2_q0[ap_const_lv32_1F : ap_const_lv32_7]}}; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_sig_cseq_ST_st20_fsm_19)) begin - tmp_12_reg_1331 <= tmp_12_fu_1086_p2; - tmp_13_reg_1337 <= tmp_13_fu_1091_p2; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_sig_cseq_ST_st21_fsm_20)) begin - tmp_14_reg_1343 <= tmp_14_fu_1096_p2; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_sig_cseq_ST_st12_fsm_11)) begin - tmp_24_reg_1269 <= tmp_24_fu_962_p2; - end -end - -always @ (posedge ap_clk) begin - if (((1'b1 == ap_sig_cseq_ST_st12_fsm_11) & (1'b0 == tmp_25_fu_968_p2))) begin - tmp_36_reg_1282 <= grp_fu_633_p2; - end -end - -always @ (posedge ap_clk) begin - if (((1'b1 == ap_sig_cseq_ST_st3_fsm_2) & (exitcond1_fu_672_p2 == 1'b0))) begin - tmp_3_reg_1143[14 : 7] <= tmp_3_fu_708_p2[14 : 7]; - end -end - -always @ (posedge ap_clk) begin - if ((1'b1 == ap_sig_cseq_ST_st7_fsm_6)) begin - tmp_5_reg_1170 <= tmp_5_fu_759_p2; - end -end - -always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st5_fsm_4) & (1'b0 == tmp_nbreadreq_fu_226_p9))) begin - ap_done = 1'b1; - end else begin - ap_done = 1'b0; - end -end - -always @ (*) begin - if (((1'b0 == ap_start) & (1'b1 == ap_sig_cseq_ST_st1_fsm_0))) begin - ap_idle = 1'b1; - end else begin - ap_idle = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st5_fsm_4) & (1'b0 == tmp_nbreadreq_fu_226_p9))) begin - ap_ready = 1'b1; - end else begin - ap_ready = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_227) begin - ap_sig_cseq_ST_st10_fsm_9 = 1'b1; - end else begin - ap_sig_cseq_ST_st10_fsm_9 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_245) begin - ap_sig_cseq_ST_st11_fsm_10 = 1'b1; - end else begin - ap_sig_cseq_ST_st11_fsm_10 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_254) begin - ap_sig_cseq_ST_st12_fsm_11 = 1'b1; - end else begin - ap_sig_cseq_ST_st12_fsm_11 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_446) begin - ap_sig_cseq_ST_st13_fsm_12 = 1'b1; - end else begin - ap_sig_cseq_ST_st13_fsm_12 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_511) begin - ap_sig_cseq_ST_st14_fsm_13 = 1'b1; - end else begin - ap_sig_cseq_ST_st14_fsm_13 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_439) begin - ap_sig_cseq_ST_st15_fsm_14 = 1'b1; - end else begin - ap_sig_cseq_ST_st15_fsm_14 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_520) begin - ap_sig_cseq_ST_st16_fsm_15 = 1'b1; - end else begin - ap_sig_cseq_ST_st16_fsm_15 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_457) begin - ap_sig_cseq_ST_st17_fsm_16 = 1'b1; - end else begin - ap_sig_cseq_ST_st17_fsm_16 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_270) begin - ap_sig_cseq_ST_st18_fsm_17 = 1'b1; - end else begin - ap_sig_cseq_ST_st18_fsm_17 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_85) begin - ap_sig_cseq_ST_st19_fsm_18 = 1'b1; - end else begin - ap_sig_cseq_ST_st19_fsm_18 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_39) begin - ap_sig_cseq_ST_st1_fsm_0 = 1'b1; - end else begin - ap_sig_cseq_ST_st1_fsm_0 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_298) begin - ap_sig_cseq_ST_st20_fsm_19 = 1'b1; - end else begin - ap_sig_cseq_ST_st20_fsm_19 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_309) begin - ap_sig_cseq_ST_st21_fsm_20 = 1'b1; - end else begin - ap_sig_cseq_ST_st21_fsm_20 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_478) begin - ap_sig_cseq_ST_st22_fsm_21 = 1'b1; - end else begin - ap_sig_cseq_ST_st22_fsm_21 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_139) begin - ap_sig_cseq_ST_st2_fsm_1 = 1'b1; - end else begin - ap_sig_cseq_ST_st2_fsm_1 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_148) begin - ap_sig_cseq_ST_st3_fsm_2 = 1'b1; - end else begin - ap_sig_cseq_ST_st3_fsm_2 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_163) begin - ap_sig_cseq_ST_st4_fsm_3 = 1'b1; - end else begin - ap_sig_cseq_ST_st4_fsm_3 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_413) begin - ap_sig_cseq_ST_st5_fsm_4 = 1'b1; - end else begin - ap_sig_cseq_ST_st5_fsm_4 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_172) begin - ap_sig_cseq_ST_st6_fsm_5 = 1'b1; - end else begin - ap_sig_cseq_ST_st6_fsm_5 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_181) begin - ap_sig_cseq_ST_st7_fsm_6 = 1'b1; - end else begin - ap_sig_cseq_ST_st7_fsm_6 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_190) begin - ap_sig_cseq_ST_st8_fsm_7 = 1'b1; - end else begin - ap_sig_cseq_ST_st8_fsm_7 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_77) begin - ap_sig_cseq_ST_st9_fsm_8 = 1'b1; - end else begin - ap_sig_cseq_ST_st9_fsm_8 = 1'b0; - end -end - -always @ (*) begin - if ((1'b0 == ap_reg_ioackin_out_stream_TREADY)) begin - ap_sig_ioackin_out_stream_TREADY = out_stream_TREADY; - end else begin - ap_sig_ioackin_out_stream_TREADY = 1'b1; - end -end - -always @ (*) begin - if ((1'b1 == ap_sig_cseq_ST_st11_fsm_10)) begin - data_shift1_address0 = tmp_49_cast_fu_926_p1; - end else if (((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & ~(1'b0 == tmp_22_fu_822_p3))) begin - data_shift1_address0 = data_shift1_addr_1_reg_1206; - end else if ((1'b1 == ap_sig_cseq_ST_st4_fsm_3)) begin - data_shift1_address0 = tmp_18_cast_fu_730_p1; - end else if (((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & (1'b0 == tmp_22_fu_822_p3))) begin - data_shift1_address0 = tmp_45_cast_fu_866_p1; - end else begin - data_shift1_address0 = 'bx; - end -end - -always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st4_fsm_3) | ((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & (1'b0 == tmp_22_fu_822_p3)) | ((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & ~(1'b0 == tmp_22_fu_822_p3)) | (1'b1 == ap_sig_cseq_ST_st11_fsm_10))) begin - data_shift1_ce0 = 1'b1; - end else begin - data_shift1_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_sig_cseq_ST_st11_fsm_10)) begin - data_shift1_d0 = data_shift1_q0; - end else if (((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & ~(1'b0 == tmp_22_fu_822_p3))) begin - data_shift1_d0 = tmp_19_cast_fu_872_p1; - end else if ((1'b1 == ap_sig_cseq_ST_st4_fsm_3)) begin - data_shift1_d0 = ap_const_lv17_0; - end else begin - data_shift1_d0 = 'bx; - end -end - -always @ (*) begin - if ((((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & ~(1'b0 == tmp_22_fu_822_p3)) | (1'b1 == ap_sig_cseq_ST_st11_fsm_10) | ((1'b1 == ap_sig_cseq_ST_st4_fsm_3) & (1'b0 == exitcond9_fu_714_p2)))) begin - data_shift1_we0 = 1'b1; - end else begin - data_shift1_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_sig_cseq_ST_st11_fsm_10)) begin - data_shift2_address0 = tmp_49_cast_fu_926_p1; - end else if (((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & ~(1'b0 == tmp_22_fu_822_p3))) begin - data_shift2_address0 = data_shift2_addr_1_reg_1211; - end else if ((1'b1 == ap_sig_cseq_ST_st4_fsm_3)) begin - data_shift2_address0 = tmp_18_cast_fu_730_p1; - end else if (((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & (1'b0 == tmp_22_fu_822_p3))) begin - data_shift2_address0 = tmp_45_cast_fu_866_p1; - end else begin - data_shift2_address0 = 'bx; - end -end - -always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st4_fsm_3) | ((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & (1'b0 == tmp_22_fu_822_p3)) | ((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & ~(1'b0 == tmp_22_fu_822_p3)) | (1'b1 == ap_sig_cseq_ST_st11_fsm_10))) begin - data_shift2_ce0 = 1'b1; - end else begin - data_shift2_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_sig_cseq_ST_st11_fsm_10)) begin - data_shift2_d0 = data_shift2_q0; - end else if (((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & ~(1'b0 == tmp_22_fu_822_p3))) begin - data_shift2_d0 = tmp_21_cast_fu_876_p1; - end else if ((1'b1 == ap_sig_cseq_ST_st4_fsm_3)) begin - data_shift2_d0 = ap_const_lv17_0; - end else begin - data_shift2_d0 = 'bx; - end -end - -always @ (*) begin - if ((((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & ~(1'b0 == tmp_22_fu_822_p3)) | (1'b1 == ap_sig_cseq_ST_st11_fsm_10) | ((1'b1 == ap_sig_cseq_ST_st4_fsm_3) & (1'b0 == exitcond9_fu_714_p2)))) begin - data_shift2_we0 = 1'b1; - end else begin - data_shift2_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_sig_cseq_ST_st9_fsm_8)) begin - in_stream_TDATA_blk_n = in_stream_TVALID; - end else begin - in_stream_TDATA_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st9_fsm_8) & ~(in_stream_TVALID == 1'b0))) begin - in_stream_TREADY = 1'b1; - end else begin - in_stream_TREADY = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_sig_cseq_ST_st19_fsm_18)) begin - out_stream_TDATA_blk_n = out_stream_TREADY; - end else begin - out_stream_TDATA_blk_n = 1'b1; - end -end - -always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st19_fsm_18) & (1'b0 == ap_reg_ioackin_out_stream_TREADY))) begin - out_stream_TVALID = 1'b1; - end else begin - out_stream_TVALID = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_sig_cseq_ST_st9_fsm_8)) begin - sum_overP1_address0 = tmp_15_reg_1186; - end else if ((((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & (1'b0 == tmp_22_fu_822_p3)) | ((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & ~(1'b0 == tmp_22_fu_822_p3)) | (1'b1 == ap_sig_cseq_ST_st11_fsm_10) | (1'b1 == ap_sig_cseq_ST_st12_fsm_11))) begin - sum_overP1_address0 = sum_overP1_addr_reg_1236; - end else begin - sum_overP1_address0 = 'bx; - end -end - -always @ (*) begin - if ((((1'b1 == ap_sig_cseq_ST_st9_fsm_8) & ~(in_stream_TVALID == 1'b0)) | ((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & (1'b0 == tmp_22_fu_822_p3)) | ((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & ~(1'b0 == tmp_22_fu_822_p3)) | (1'b1 == ap_sig_cseq_ST_st11_fsm_10) | (1'b1 == ap_sig_cseq_ST_st12_fsm_11))) begin - sum_overP1_ce0 = 1'b1; - end else begin - sum_overP1_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_sig_cseq_ST_st12_fsm_11)) begin - sum_overP1_d0 = tmp_23_fu_956_p2; - end else if ((1'b1 == ap_sig_cseq_ST_st11_fsm_10)) begin - sum_overP1_d0 = tmp_29_fu_936_p2; - end else if ((1'b1 == ap_sig_cseq_ST_st9_fsm_8)) begin - sum_overP1_d0 = ap_const_lv32_0; - end else begin - sum_overP1_d0 = 'bx; - end -end - -always @ (*) begin - if ((((1'b1 == ap_sig_cseq_ST_st9_fsm_8) & ~(in_stream_TVALID == 1'b0)) | (1'b1 == ap_sig_cseq_ST_st11_fsm_10) | (1'b1 == ap_sig_cseq_ST_st12_fsm_11))) begin - sum_overP1_we0 = 1'b1; - end else begin - sum_overP1_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_sig_cseq_ST_st9_fsm_8)) begin - sum_overP2_address0 = tmp_15_reg_1186; - end else if ((((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & (1'b0 == tmp_22_fu_822_p3)) | ((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & ~(1'b0 == tmp_22_fu_822_p3)) | (1'b1 == ap_sig_cseq_ST_st11_fsm_10) | (1'b1 == ap_sig_cseq_ST_st12_fsm_11))) begin - sum_overP2_address0 = sum_overP2_addr_reg_1241; - end else begin - sum_overP2_address0 = 'bx; - end -end - -always @ (*) begin - if ((((1'b1 == ap_sig_cseq_ST_st9_fsm_8) & ~(in_stream_TVALID == 1'b0)) | ((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & (1'b0 == tmp_22_fu_822_p3)) | ((1'b1 == ap_sig_cseq_ST_st10_fsm_9) & ~(1'b0 == tmp_22_fu_822_p3)) | (1'b1 == ap_sig_cseq_ST_st11_fsm_10) | (1'b1 == ap_sig_cseq_ST_st12_fsm_11))) begin - sum_overP2_ce0 = 1'b1; - end else begin - sum_overP2_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_sig_cseq_ST_st12_fsm_11)) begin - sum_overP2_d0 = tmp_24_fu_962_p2; - end else if ((1'b1 == ap_sig_cseq_ST_st11_fsm_10)) begin - sum_overP2_d0 = tmp_30_fu_943_p2; - end else if ((1'b1 == ap_sig_cseq_ST_st9_fsm_8)) begin - sum_overP2_d0 = ap_const_lv32_0; - end else begin - sum_overP2_d0 = 'bx; - end -end - -always @ (*) begin - if ((((1'b1 == ap_sig_cseq_ST_st9_fsm_8) & ~(in_stream_TVALID == 1'b0)) | (1'b1 == ap_sig_cseq_ST_st11_fsm_10) | (1'b1 == ap_sig_cseq_ST_st12_fsm_11))) begin - sum_overP2_we0 = 1'b1; - end else begin - sum_overP2_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_sig_cseq_ST_st9_fsm_8)) begin - sum_pix1_address0 = sum_pix1_addr_3_reg_1196; - end else if ((1'b1 == ap_sig_cseq_ST_st6_fsm_5)) begin - sum_pix1_address0 = tmp_7_fu_747_p1; - end else if ((1'b1 == ap_sig_cseq_ST_st2_fsm_1)) begin - sum_pix1_address0 = tmp_4_fu_664_p1; - end else if ((1'b1 == ap_sig_cseq_ST_st18_fsm_17)) begin - sum_pix1_address0 = tmp_9_fu_1027_p1; - end else if ((1'b1 == ap_sig_cseq_ST_st8_fsm_7)) begin - sum_pix1_address0 = tmp_15_fu_776_p1; - end else begin - sum_pix1_address0 = 'bx; - end -end - -always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) | (1'b1 == ap_sig_cseq_ST_st6_fsm_5) | (1'b1 == ap_sig_cseq_ST_st8_fsm_7) | ((1'b1 == ap_sig_cseq_ST_st9_fsm_8) & ~(in_stream_TVALID == 1'b0)) | (1'b1 == ap_sig_cseq_ST_st18_fsm_17))) begin - sum_pix1_ce0 = 1'b1; - end else begin - sum_pix1_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_sig_cseq_ST_st9_fsm_8)) begin - sum_pix1_d0 = tmp_18_fu_804_p2; - end else if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) | (1'b1 == ap_sig_cseq_ST_st6_fsm_5))) begin - sum_pix1_d0 = ap_const_lv32_0; - end else begin - sum_pix1_d0 = 'bx; - end -end - -always @ (*) begin - if ((((1'b1 == ap_sig_cseq_ST_st9_fsm_8) & ~(in_stream_TVALID == 1'b0)) | ((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & (1'b0 == exitcond2_fu_653_p2)) | ((1'b1 == ap_sig_cseq_ST_st6_fsm_5) & (1'b0 == exitcond8_fu_736_p2)))) begin - sum_pix1_we0 = 1'b1; - end else begin - sum_pix1_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_sig_cseq_ST_st9_fsm_8)) begin - sum_pix2_address0 = sum_pix2_addr_3_reg_1201; - end else if ((1'b1 == ap_sig_cseq_ST_st6_fsm_5)) begin - sum_pix2_address0 = tmp_7_fu_747_p1; - end else if ((1'b1 == ap_sig_cseq_ST_st2_fsm_1)) begin - sum_pix2_address0 = tmp_4_fu_664_p1; - end else if ((1'b1 == ap_sig_cseq_ST_st18_fsm_17)) begin - sum_pix2_address0 = tmp_9_fu_1027_p1; - end else if ((1'b1 == ap_sig_cseq_ST_st8_fsm_7)) begin - sum_pix2_address0 = tmp_15_fu_776_p1; - end else begin - sum_pix2_address0 = 'bx; - end -end - -always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) | (1'b1 == ap_sig_cseq_ST_st6_fsm_5) | (1'b1 == ap_sig_cseq_ST_st8_fsm_7) | ((1'b1 == ap_sig_cseq_ST_st9_fsm_8) & ~(in_stream_TVALID == 1'b0)) | (1'b1 == ap_sig_cseq_ST_st18_fsm_17))) begin - sum_pix2_ce0 = 1'b1; - end else begin - sum_pix2_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_sig_cseq_ST_st9_fsm_8)) begin - sum_pix2_d0 = tmp_20_fu_815_p2; - end else if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) | (1'b1 == ap_sig_cseq_ST_st6_fsm_5))) begin - sum_pix2_d0 = ap_const_lv32_0; - end else begin - sum_pix2_d0 = 'bx; - end -end - -always @ (*) begin - if ((((1'b1 == ap_sig_cseq_ST_st9_fsm_8) & ~(in_stream_TVALID == 1'b0)) | ((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & (1'b0 == exitcond2_fu_653_p2)) | ((1'b1 == ap_sig_cseq_ST_st6_fsm_5) & (1'b0 == exitcond8_fu_736_p2)))) begin - sum_pix2_we0 = 1'b1; - end else begin - sum_pix2_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st21_fsm_20) | (1'b1 == ap_sig_cseq_ST_st22_fsm_21))) begin - thresh1_address0 = thresh1_addr_1_reg_1311; - end else if ((1'b1 == ap_sig_cseq_ST_st2_fsm_1)) begin - thresh1_address0 = tmp_4_fu_664_p1; - end else if ((1'b1 == ap_sig_cseq_ST_st10_fsm_9)) begin - thresh1_address0 = tmp_15_reg_1186; - end else begin - thresh1_address0 = 'bx; - end -end - -always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) | (1'b1 == ap_sig_cseq_ST_st10_fsm_9) | (1'b1 == ap_sig_cseq_ST_st21_fsm_20) | (1'b1 == ap_sig_cseq_ST_st22_fsm_21))) begin - thresh1_ce0 = 1'b1; - end else begin - thresh1_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_sig_cseq_ST_st22_fsm_21)) begin - thresh1_d0 = LOW_THRESH_read_reg_1104; - end else if ((1'b1 == ap_sig_cseq_ST_st21_fsm_20)) begin - thresh1_d0 = tmp_12_reg_1331; - end else if ((1'b1 == ap_sig_cseq_ST_st2_fsm_1)) begin - thresh1_d0 = ap_const_lv32_639C; - end else begin - thresh1_d0 = 'bx; - end -end - -always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st21_fsm_20) | ((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & (1'b0 == exitcond2_fu_653_p2)) | ((1'b1 == ap_sig_cseq_ST_st22_fsm_21) & ~(1'b0 == tmp_14_reg_1343)))) begin - thresh1_we0 = 1'b1; - end else begin - thresh1_we0 = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st21_fsm_20) | (1'b1 == ap_sig_cseq_ST_st22_fsm_21))) begin - thresh2_address0 = thresh2_addr_1_reg_1316; - end else if ((1'b1 == ap_sig_cseq_ST_st2_fsm_1)) begin - thresh2_address0 = tmp_4_fu_664_p1; - end else if ((1'b1 == ap_sig_cseq_ST_st12_fsm_11)) begin - thresh2_address0 = tmp_15_reg_1186; - end else begin - thresh2_address0 = 'bx; - end -end - -always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) | (1'b1 == ap_sig_cseq_ST_st12_fsm_11) | (1'b1 == ap_sig_cseq_ST_st21_fsm_20) | (1'b1 == ap_sig_cseq_ST_st22_fsm_21))) begin - thresh2_ce0 = 1'b1; - end else begin - thresh2_ce0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_sig_cseq_ST_st22_fsm_21)) begin - thresh2_d0 = LOW_THRESH_read_reg_1104; - end else if ((1'b1 == ap_sig_cseq_ST_st21_fsm_20)) begin - thresh2_d0 = tmp_13_reg_1337; - end else if ((1'b1 == ap_sig_cseq_ST_st2_fsm_1)) begin - thresh2_d0 = ap_const_lv32_639C; - end else begin - thresh2_d0 = 'bx; - end -end - -always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st21_fsm_20) | ((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & (1'b0 == exitcond2_fu_653_p2)) | ((1'b1 == ap_sig_cseq_ST_st22_fsm_21) & ~(1'b0 == tmp_21_fu_1100_p2)))) begin - thresh2_we0 = 1'b1; - end else begin - thresh2_we0 = 1'b0; - end -end - -always @ (*) begin - if ((1'b1 == ap_sig_cseq_ST_st17_fsm_16)) begin - trig_data = tmp_38_cast_fu_1011_p1; - end else if ((1'b1 == ap_sig_cseq_ST_st15_fsm_14)) begin - trig_data = tmp_40_cast_fu_998_p1; - end else if ((((1'b1 == ap_sig_cseq_ST_st12_fsm_11) & ~(1'b0 == tmp_25_fu_968_p2) & ~(1'b0 == grp_fu_633_p2)) | ((1'b1 == ap_sig_cseq_ST_st13_fsm_12) & ~(1'b0 == or_cond_fu_979_p2)))) begin - trig_data = ap_const_lv32_1; - end else if ((((1'b1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == 1'b0)) | (1'b1 == ap_sig_cseq_ST_st14_fsm_13) | (1'b1 == ap_sig_cseq_ST_st16_fsm_15))) begin - trig_data = ap_const_lv32_0; - end else begin - trig_data = 'bx; - end -end - -always @ (*) begin - if ((((1'b1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == 1'b0)) | (1'b1 == ap_sig_cseq_ST_st15_fsm_14) | (1'b1 == ap_sig_cseq_ST_st17_fsm_16) | ((1'b1 == ap_sig_cseq_ST_st12_fsm_11) & ~(1'b0 == tmp_25_fu_968_p2) & ~(1'b0 == grp_fu_633_p2)) | ((1'b1 == ap_sig_cseq_ST_st13_fsm_12) & ~(1'b0 == or_cond_fu_979_p2)) | (1'b1 == ap_sig_cseq_ST_st14_fsm_13) | (1'b1 == ap_sig_cseq_ST_st16_fsm_15))) begin - trig_data_ap_vld = 1'b1; - end else begin - trig_data_ap_vld = 1'b0; - end -end - -always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == 1'b0))) begin - trig_pixel_ap_vld = 1'b1; - end else begin - trig_pixel_ap_vld = 1'b0; - end -end - -always @ (*) begin - case (ap_CS_fsm) - ap_ST_st1_fsm_0 : begin - if (~(ap_start == 1'b0)) begin - ap_NS_fsm = ap_ST_st2_fsm_1; - end else begin - ap_NS_fsm = ap_ST_st1_fsm_0; - end - end - ap_ST_st2_fsm_1 : begin - if ((1'b0 == exitcond2_fu_653_p2)) begin - ap_NS_fsm = ap_ST_st2_fsm_1; - end else begin - ap_NS_fsm = ap_ST_st3_fsm_2; - end - end - ap_ST_st3_fsm_2 : begin - if ((exitcond1_fu_672_p2 == 1'b0)) begin - ap_NS_fsm = ap_ST_st4_fsm_3; - end else begin - ap_NS_fsm = ap_ST_st5_fsm_4; - end - end - ap_ST_st4_fsm_3 : begin - if ((1'b0 == exitcond9_fu_714_p2)) begin - ap_NS_fsm = ap_ST_st4_fsm_3; - end else begin - ap_NS_fsm = ap_ST_st3_fsm_2; - end - end - ap_ST_st5_fsm_4 : begin - if ((1'b0 == tmp_nbreadreq_fu_226_p9)) begin - ap_NS_fsm = ap_ST_st1_fsm_0; - end else begin - ap_NS_fsm = ap_ST_st6_fsm_5; - end - end - ap_ST_st6_fsm_5 : begin - if ((1'b0 == exitcond8_fu_736_p2)) begin - ap_NS_fsm = ap_ST_st6_fsm_5; - end else begin - ap_NS_fsm = ap_ST_st7_fsm_6; - end - end - ap_ST_st7_fsm_6 : begin - if (~(1'b0 == exitcond_fu_753_p2)) begin - ap_NS_fsm = ap_ST_st18_fsm_17; - end else begin - ap_NS_fsm = ap_ST_st8_fsm_7; - end - end - ap_ST_st8_fsm_7 : begin - if ((1'b0 == exitcond7_fu_765_p2)) begin - ap_NS_fsm = ap_ST_st9_fsm_8; - end else begin - ap_NS_fsm = ap_ST_st7_fsm_6; - end - end - ap_ST_st9_fsm_8 : begin - if (~(in_stream_TVALID == 1'b0)) begin - ap_NS_fsm = ap_ST_st10_fsm_9; - end else begin - ap_NS_fsm = ap_ST_st9_fsm_8; - end - end - ap_ST_st10_fsm_9 : begin - if (~(1'b0 == tmp_22_fu_822_p3)) begin - ap_NS_fsm = ap_ST_st12_fsm_11; - end else begin - ap_NS_fsm = ap_ST_st11_fsm_10; - end - end - ap_ST_st11_fsm_10 : begin - ap_NS_fsm = ap_ST_st10_fsm_9; - end - ap_ST_st12_fsm_11 : begin - if ((~(1'b0 == tmp_25_fu_968_p2) & ~(1'b0 == grp_fu_633_p2))) begin - ap_NS_fsm = ap_ST_st16_fsm_15; - end else if (((1'b0 == grp_fu_633_p2) & ~(1'b0 == tmp_25_fu_968_p2))) begin - ap_NS_fsm = ap_ST_st8_fsm_7; - end else begin - ap_NS_fsm = ap_ST_st13_fsm_12; - end - end - ap_ST_st13_fsm_12 : begin - if (~(1'b0 == or_cond_fu_979_p2)) begin - ap_NS_fsm = ap_ST_st14_fsm_13; - end else begin - ap_NS_fsm = ap_ST_st8_fsm_7; - end - end - ap_ST_st14_fsm_13 : begin - ap_NS_fsm = ap_ST_st15_fsm_14; - end - ap_ST_st15_fsm_14 : begin - ap_NS_fsm = ap_ST_st8_fsm_7; - end - ap_ST_st16_fsm_15 : begin - ap_NS_fsm = ap_ST_st17_fsm_16; - end - ap_ST_st17_fsm_16 : begin - ap_NS_fsm = ap_ST_st8_fsm_7; - end - ap_ST_st18_fsm_17 : begin - if ((1'b0 == exitcond6_fu_1016_p2)) begin - ap_NS_fsm = ap_ST_st19_fsm_18; - end else begin - ap_NS_fsm = ap_ST_st5_fsm_4; - end - end - ap_ST_st19_fsm_18 : begin - if (~(1'b0 == ap_sig_ioackin_out_stream_TREADY)) begin - ap_NS_fsm = ap_ST_st20_fsm_19; - end else begin - ap_NS_fsm = ap_ST_st19_fsm_18; - end - end - ap_ST_st20_fsm_19 : begin - ap_NS_fsm = ap_ST_st21_fsm_20; - end - ap_ST_st21_fsm_20 : begin - ap_NS_fsm = ap_ST_st22_fsm_21; - end - ap_ST_st22_fsm_21 : begin - ap_NS_fsm = ap_ST_st18_fsm_17; - end - default : begin - ap_NS_fsm = 'bx; - end - endcase -end - -always @ (*) begin - ap_rst_n_inv = ~ap_rst_n; -end - -always @ (*) begin - ap_sig_139 = (1'b1 == ap_CS_fsm[ap_const_lv32_1]); -end - -always @ (*) begin - ap_sig_148 = (1'b1 == ap_CS_fsm[ap_const_lv32_2]); -end - -always @ (*) begin - ap_sig_163 = (1'b1 == ap_CS_fsm[ap_const_lv32_3]); -end - -always @ (*) begin - ap_sig_172 = (1'b1 == ap_CS_fsm[ap_const_lv32_5]); -end - -always @ (*) begin - ap_sig_181 = (1'b1 == ap_CS_fsm[ap_const_lv32_6]); -end - -always @ (*) begin - ap_sig_190 = (1'b1 == ap_CS_fsm[ap_const_lv32_7]); -end - -always @ (*) begin - ap_sig_227 = (1'b1 == ap_CS_fsm[ap_const_lv32_9]); -end - -always @ (*) begin - ap_sig_245 = (1'b1 == ap_CS_fsm[ap_const_lv32_A]); -end - -always @ (*) begin - ap_sig_254 = (1'b1 == ap_CS_fsm[ap_const_lv32_B]); -end - -always @ (*) begin - ap_sig_270 = (1'b1 == ap_CS_fsm[ap_const_lv32_11]); -end - -always @ (*) begin - ap_sig_298 = (1'b1 == ap_CS_fsm[ap_const_lv32_13]); -end - -always @ (*) begin - ap_sig_309 = (1'b1 == ap_CS_fsm[ap_const_lv32_14]); -end - -always @ (*) begin - ap_sig_39 = (ap_CS_fsm[ap_const_lv32_0] == 1'b1); -end - -always @ (*) begin - ap_sig_413 = (1'b1 == ap_CS_fsm[ap_const_lv32_4]); -end - -always @ (*) begin - ap_sig_439 = (1'b1 == ap_CS_fsm[ap_const_lv32_E]); -end - -always @ (*) begin - ap_sig_446 = (1'b1 == ap_CS_fsm[ap_const_lv32_C]); -end - -always @ (*) begin - ap_sig_457 = (1'b1 == ap_CS_fsm[ap_const_lv32_10]); -end - -always @ (*) begin - ap_sig_478 = (1'b1 == ap_CS_fsm[ap_const_lv32_15]); -end - -always @ (*) begin - ap_sig_511 = (1'b1 == ap_CS_fsm[ap_const_lv32_D]); -end - -always @ (*) begin - ap_sig_520 = (1'b1 == ap_CS_fsm[ap_const_lv32_F]); -end - -always @ (*) begin - ap_sig_77 = (1'b1 == ap_CS_fsm[ap_const_lv32_8]); -end - -always @ (*) begin - ap_sig_85 = (1'b1 == ap_CS_fsm[ap_const_lv32_12]); -end - -assign exitcond1_fu_672_p2 = ((kk_reg_513 == ap_const_lv4_8) ? 1'b1 : 1'b0); - -assign exitcond2_fu_653_p2 = ((i_reg_502 == tmp_2_reg_1118) ? 1'b1 : 1'b0); - -assign exitcond6_fu_1016_p2 = ((i_4_reg_622 == tmp_2_reg_1118) ? 1'b1 : 1'b0); - -assign exitcond7_fu_765_p2 = ((i_3_reg_569 == tmp_2_reg_1118) ? 1'b1 : 1'b0); - -assign exitcond8_fu_736_p2 = ((i_2_reg_535 == tmp_2_reg_1118) ? 1'b1 : 1'b0); - -assign exitcond9_fu_714_p2 = ((i_1_reg_524 == tmp_2_reg_1118) ? 1'b1 : 1'b0); - -assign exitcond_fu_753_p2 = ((k_reg_546 == ap_const_lv8_80) ? 1'b1 : 1'b0); - -assign extLd1_fu_932_p1 = $signed(data_shift2_q0); - -assign extLd_fu_880_p1 = $signed(data_shift1_q0); - -assign grp_fu_633_p2 = ((itrig_1_reg_587 == ap_const_lv32_0) ? 1'b1 : 1'b0); - -assign i_5_fu_658_p2 = (i_reg_502 + ap_const_lv15_1); - -assign i_6_fu_719_p2 = (i_1_reg_524 + ap_const_lv15_1); - -assign i_7_fu_741_p2 = (i_2_reg_535 + ap_const_lv15_1); - -assign i_8_fu_1021_p2 = (i_4_reg_622 + ap_const_lv15_1); - -assign i_9_fu_770_p2 = (i_3_reg_569 + ap_const_lv15_1); - -assign kk_2_fu_678_p2 = (kk_reg_513 + ap_const_lv4_1); - -assign kk_3_fu_950_p2 = ($signed(kk_1_reg_610) + $signed(ap_const_lv4_F)); - -assign or_cond_fu_979_p2 = (tmp_35_fu_974_p2 & tmp_36_reg_1282); - -assign out_stream_TDATA = {{sum_pix2_q0}, {sum_pix1_q0}}; - -assign out_stream_TDEST = ap_const_lv6_0; - -assign out_stream_TID = ap_const_lv5_0; - -assign out_stream_TKEEP = ap_const_lv8_FF; - -assign out_stream_TLAST = 1'b0; - -assign out_stream_TSTRB = ap_const_lv8_FF; - -assign out_stream_TUSER = ap_const_lv2_0; - -assign p_shl1_cast_fu_704_p1 = tmp_s_fu_696_p3; - -assign p_shl2_cast_fu_898_p1 = tmp_33_fu_890_p3; - -assign p_shl3_cast_fu_910_p1 = tmp_40_fu_902_p3; - -assign p_shl4_cast_fu_838_p1 = $signed(tmp_26_fu_830_p3); - -assign p_shl5_cast_fu_850_p1 = $signed(tmp_28_fu_842_p3); - -assign p_shl_cast_fu_692_p1 = tmp_6_fu_684_p3; - -assign phitmp_fu_790_p4 = {{in_stream_TDATA[ap_const_lv32_1F : ap_const_lv32_10]}}; - -assign sum_pixP1_fu_1064_p3 = {{tmp_10_reg_1321}, {ap_const_lv3_0}}; - -assign sum_pixP2_fu_1075_p3 = {{tmp_11_reg_1326}, {ap_const_lv3_0}}; - -assign tmp_12_fu_1086_p0 = tmp_12_fu_1086_p00; - -assign tmp_12_fu_1086_p00 = sum_pixP1_fu_1064_p3; - -assign tmp_12_fu_1086_p1 = tmp_1_reg_1112; - -assign tmp_12_fu_1086_p2 = (tmp_12_fu_1086_p0 * tmp_12_fu_1086_p1); - -assign tmp_13_fu_1091_p0 = tmp_13_fu_1091_p00; - -assign tmp_13_fu_1091_p00 = sum_pixP2_fu_1075_p3; - -assign tmp_13_fu_1091_p1 = tmp_1_reg_1112; - -assign tmp_13_fu_1091_p2 = (tmp_13_fu_1091_p0 * tmp_13_fu_1091_p1); - -assign tmp_14_fu_1096_p2 = ((tmp_12_reg_1331 < LOW_THRESH_read_reg_1104) ? 1'b1 : 1'b0); - -assign tmp_15_fu_776_p1 = i_3_reg_569; - -assign tmp_16_fu_786_p1 = in_stream_TDATA[15:0]; - -assign tmp_17_fu_800_p1 = $signed(tmp_16_fu_786_p1); - -assign tmp_18_cast_fu_730_p1 = tmp_8_fu_725_p2; - -assign tmp_18_fu_804_p2 = ($signed(sum_pix1_q0) + $signed(tmp_17_fu_800_p1)); - -assign tmp_19_cast_fu_872_p1 = $signed(tmp_16_reg_1216); - -assign tmp_19_fu_811_p1 = $signed(phitmp_fu_790_p4); - -assign tmp_1_fu_639_p1 = N_BG; - -assign tmp_20_fu_815_p2 = ($signed(sum_pix2_q0) + $signed(tmp_19_fu_811_p1)); - -assign tmp_21_cast_fu_876_p1 = $signed(phitmp_reg_1221); - -assign tmp_21_fu_1100_p2 = ((tmp_13_reg_1337 < LOW_THRESH_read_reg_1104) ? 1'b1 : 1'b0); - -assign tmp_22_fu_822_p3 = kk_1_reg_610[ap_const_lv32_3]; - -assign tmp_23_fu_956_p2 = ($signed(tmp_17_reg_1226) + $signed(sum_overP1_q0)); - -assign tmp_24_fu_962_p2 = ($signed(tmp_19_reg_1231) + $signed(sum_overP2_q0)); - -assign tmp_25_fu_968_p2 = ((tmp_23_fu_956_p2 > thresh1_q0) ? 1'b1 : 1'b0); - -assign tmp_26_fu_830_p3 = {{kk_1_reg_610}, {ap_const_lv10_0}}; - -assign tmp_27_fu_884_p2 = (kk_1_reg_610 + ap_const_lv4_1); - -assign tmp_28_fu_842_p3 = {{kk_1_reg_610}, {ap_const_lv7_0}}; - -assign tmp_29_fu_936_p2 = ($signed(sum_overP1_q0) + $signed(extLd_fu_880_p1)); - -assign tmp_30_fu_943_p2 = ($signed(sum_overP2_q0) + $signed(extLd1_fu_932_p1)); - -assign tmp_31_fu_854_p2 = ($signed(p_shl5_cast_fu_850_p1) + $signed(p_shl4_cast_fu_838_p1)); - -assign tmp_32_fu_860_p2 = (tmp_31_fu_854_p2 + i_3_reg_569); - -assign tmp_33_fu_890_p3 = {{tmp_27_fu_884_p2}, {ap_const_lv10_0}}; - -assign tmp_35_fu_974_p2 = ((tmp_24_reg_1269 > thresh2_q0) ? 1'b1 : 1'b0); - -assign tmp_37_fu_1003_p3 = {{i_3_reg_569}, {1'b0}}; - -assign tmp_38_cast_fu_1011_p1 = tmp_37_fu_1003_p3; - -assign tmp_38_fu_984_p3 = {{i_3_reg_569}, {1'b0}}; - -assign tmp_39_fu_992_p2 = (tmp_38_fu_984_p3 | ap_const_lv16_1); - -assign tmp_3_fu_708_p2 = (p_shl1_cast_fu_704_p1 + p_shl_cast_fu_692_p1); - -assign tmp_40_cast_fu_998_p1 = tmp_39_fu_992_p2; - -assign tmp_40_fu_902_p3 = {{tmp_27_fu_884_p2}, {ap_const_lv7_0}}; - -assign tmp_41_fu_914_p2 = (p_shl3_cast_fu_910_p1 + p_shl2_cast_fu_898_p1); - -assign tmp_42_fu_920_p2 = (tmp_41_fu_914_p2 + i_3_reg_569); - -assign tmp_45_cast_fu_866_p1 = tmp_32_fu_860_p2; - -assign tmp_49_cast_fu_926_p1 = tmp_42_fu_920_p2; - -assign tmp_4_fu_664_p1 = i_reg_502; - -assign tmp_5_fu_759_p2 = (k_reg_546 + ap_const_lv8_1); - -assign tmp_6_fu_684_p3 = {{kk_reg_513}, {ap_const_lv10_0}}; - -assign tmp_7_fu_747_p1 = i_2_reg_535; - -assign tmp_8_fu_725_p2 = (tmp_3_reg_1143 + i_1_reg_524); - -assign tmp_9_fu_1027_p1 = i_4_reg_622; - -assign tmp_nbreadreq_fu_226_p9 = in_stream_TVALID; - -assign tmp_s_fu_696_p3 = {{kk_reg_513}, {ap_const_lv7_0}}; - -assign trig_pixel = ap_const_lv32_0; - -always @ (posedge ap_clk) begin - tmp_1_reg_1112[31:8] <= 24'b000000000000000000000000; - tmp_3_reg_1143[6:0] <= 7'b0000000; - tmp_15_reg_1186[63:15] <= 49'b0000000000000000000000000000000000000000000000000; -end - -endmodule //l2_trigger diff --git a/l2_trigger/solution1/impl/verilog/l2_trigger.xdc b/l2_trigger/solution1/impl/verilog/l2_trigger.xdc deleted file mode 100644 index 32a1cf2..0000000 --- a/l2_trigger/solution1/impl/verilog/l2_trigger.xdc +++ /dev/null @@ -1,7 +0,0 @@ -create_clock -name ap_clk -period 10.000 -waveform {0.000 5.000} [get_ports ap_clk] -set_property HD.CLK_SRC BUFGCTRL_X0Y0 [get_ports ap_clk] - -#set_input_delay 0 -clock CLK [all_inputs] -#set_output_delay 0 -clock CLK [all_outputs] - - diff --git a/l2_trigger/solution1/impl/verilog/l2_trigger_CTRL_BUS_s_axi.v b/l2_trigger/solution1/impl/verilog/l2_trigger_CTRL_BUS_s_axi.v deleted file mode 100644 index 9f66b9f..0000000 --- a/l2_trigger/solution1/impl/verilog/l2_trigger_CTRL_BUS_s_axi.v +++ /dev/null @@ -1,361 +0,0 @@ -// ============================================================== -// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -// Version: 2016.2 -// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved. -// -// ============================================================== - -`timescale 1ns/1ps -module l2_trigger_CTRL_BUS_s_axi -#(parameter - C_S_AXI_ADDR_WIDTH = 6, - C_S_AXI_DATA_WIDTH = 32 -)( - // axi4 lite slave signals - input wire ACLK, - input wire ARESET, - input wire ACLK_EN, - input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR, - input wire AWVALID, - output wire AWREADY, - input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA, - input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB, - input wire WVALID, - output wire WREADY, - output wire [1:0] BRESP, - output wire BVALID, - input wire BREADY, - input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR, - input wire ARVALID, - output wire ARREADY, - output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA, - output wire [1:0] RRESP, - output wire RVALID, - input wire RREADY, - output wire interrupt, - // user signals - output wire ap_start, - input wire ap_done, - input wire ap_ready, - input wire ap_idle, - output wire [15:0] n_pixels_in_bus, - output wire [7:0] N_BG, - output wire [31:0] LOW_THRESH -); -//------------------------Address Info------------------- -// 0x00 : Control signals -// bit 0 - ap_start (Read/Write/COH) -// bit 1 - ap_done (Read/COR) -// bit 2 - ap_idle (Read) -// bit 3 - ap_ready (Read) -// bit 7 - auto_restart (Read/Write) -// others - reserved -// 0x04 : Global Interrupt Enable Register -// bit 0 - Global Interrupt Enable (Read/Write) -// others - reserved -// 0x08 : IP Interrupt Enable Register (Read/Write) -// bit 0 - Channel 0 (ap_done) -// bit 1 - Channel 1 (ap_ready) -// others - reserved -// 0x0c : IP Interrupt Status Register (Read/TOW) -// bit 0 - Channel 0 (ap_done) -// bit 1 - Channel 1 (ap_ready) -// others - reserved -// 0x10 : Data signal of n_pixels_in_bus -// bit 15~0 - n_pixels_in_bus[15:0] (Read/Write) -// others - reserved -// 0x14 : reserved -// 0x18 : Data signal of N_BG -// bit 7~0 - N_BG[7:0] (Read/Write) -// others - reserved -// 0x1c : reserved -// 0x20 : Data signal of LOW_THRESH -// bit 31~0 - LOW_THRESH[31:0] (Read/Write) -// 0x24 : reserved -// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake) - -//------------------------Parameter---------------------- -localparam - ADDR_AP_CTRL = 6'h00, - ADDR_GIE = 6'h04, - ADDR_IER = 6'h08, - ADDR_ISR = 6'h0c, - ADDR_N_PIXELS_IN_BUS_DATA_0 = 6'h10, - ADDR_N_PIXELS_IN_BUS_CTRL = 6'h14, - ADDR_N_BG_DATA_0 = 6'h18, - ADDR_N_BG_CTRL = 6'h1c, - ADDR_LOW_THRESH_DATA_0 = 6'h20, - ADDR_LOW_THRESH_CTRL = 6'h24, - WRIDLE = 2'd0, - WRDATA = 2'd1, - WRRESP = 2'd2, - RDIDLE = 2'd0, - RDDATA = 2'd1, - ADDR_BITS = 6; - -//------------------------Local signal------------------- - reg [1:0] wstate; - reg [1:0] wnext; - reg [ADDR_BITS-1:0] waddr; - wire [31:0] wmask; - wire aw_hs; - wire w_hs; - reg [1:0] rstate; - reg [1:0] rnext; - reg [31:0] rdata; - wire ar_hs; - wire [ADDR_BITS-1:0] raddr; - // internal registers - wire int_ap_idle; - wire int_ap_ready; - reg int_ap_done; - reg int_ap_start; - reg int_auto_restart; - reg int_gie; - reg [1:0] int_ier; - reg [1:0] int_isr; - reg [15:0] int_n_pixels_in_bus; - reg [7:0] int_N_BG; - reg [31:0] int_LOW_THRESH; - -//------------------------Instantiation------------------ - -//------------------------AXI write fsm------------------ -assign AWREADY = (wstate == WRIDLE); -assign WREADY = (wstate == WRDATA); -assign BRESP = 2'b00; // OKAY -assign BVALID = (wstate == WRRESP); -assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} }; -assign aw_hs = AWVALID & AWREADY; -assign w_hs = WVALID & WREADY; - -// wstate -always @(posedge ACLK) begin - if (ARESET) - wstate <= WRIDLE; - else if (ACLK_EN) - wstate <= wnext; -end - -// wnext -always @(*) begin - case (wstate) - WRIDLE: - if (AWVALID) - wnext = WRDATA; - else - wnext = WRIDLE; - WRDATA: - if (WVALID) - wnext = WRRESP; - else - wnext = WRDATA; - WRRESP: - if (BREADY) - wnext = WRIDLE; - else - wnext = WRRESP; - default: - wnext = WRIDLE; - endcase -end - -// waddr -always @(posedge ACLK) begin - if (ACLK_EN) begin - if (aw_hs) - waddr <= AWADDR[ADDR_BITS-1:0]; - end -end - -//------------------------AXI read fsm------------------- -assign ARREADY = (rstate == RDIDLE); -assign RDATA = rdata; -assign RRESP = 2'b00; // OKAY -assign RVALID = (rstate == RDDATA); -assign ar_hs = ARVALID & ARREADY; -assign raddr = ARADDR[ADDR_BITS-1:0]; - -// rstate -always @(posedge ACLK) begin - if (ARESET) - rstate <= RDIDLE; - else if (ACLK_EN) - rstate <= rnext; -end - -// rnext -always @(*) begin - case (rstate) - RDIDLE: - if (ARVALID) - rnext = RDDATA; - else - rnext = RDIDLE; - RDDATA: - if (RREADY & RVALID) - rnext = RDIDLE; - else - rnext = RDDATA; - default: - rnext = RDIDLE; - endcase -end - -// rdata -always @(posedge ACLK) begin - if (ACLK_EN) begin - if (ar_hs) begin - rdata <= 1'b0; - case (raddr) - ADDR_AP_CTRL: begin - rdata[0] <= int_ap_start; - rdata[1] <= int_ap_done; - rdata[2] <= int_ap_idle; - rdata[3] <= int_ap_ready; - rdata[7] <= int_auto_restart; - end - ADDR_GIE: begin - rdata <= int_gie; - end - ADDR_IER: begin - rdata <= int_ier; - end - ADDR_ISR: begin - rdata <= int_isr; - end - ADDR_N_PIXELS_IN_BUS_DATA_0: begin - rdata <= int_n_pixels_in_bus[15:0]; - end - ADDR_N_BG_DATA_0: begin - rdata <= int_N_BG[7:0]; - end - ADDR_LOW_THRESH_DATA_0: begin - rdata <= int_LOW_THRESH[31:0]; - end - endcase - end - end -end - - -//------------------------Register logic----------------- -assign interrupt = int_gie & (|int_isr); -assign ap_start = int_ap_start; -assign int_ap_idle = ap_idle; -assign int_ap_ready = ap_ready; -assign n_pixels_in_bus = int_n_pixels_in_bus; -assign N_BG = int_N_BG; -assign LOW_THRESH = int_LOW_THRESH; -// int_ap_start -always @(posedge ACLK) begin - if (ARESET) - int_ap_start <= 1'b0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0]) - int_ap_start <= 1'b1; - else if (int_ap_ready) - int_ap_start <= int_auto_restart; // clear on handshake/auto restart - end -end - -// int_ap_done -always @(posedge ACLK) begin - if (ARESET) - int_ap_done <= 1'b0; - else if (ACLK_EN) begin - if (ap_done) - int_ap_done <= 1'b1; - else if (ar_hs && raddr == ADDR_AP_CTRL) - int_ap_done <= 1'b0; // clear on read - end -end - -// int_auto_restart -always @(posedge ACLK) begin - if (ARESET) - int_auto_restart <= 1'b0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0]) - int_auto_restart <= WDATA[7]; - end -end - -// int_gie -always @(posedge ACLK) begin - if (ARESET) - int_gie <= 1'b0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_GIE && WSTRB[0]) - int_gie <= WDATA[0]; - end -end - -// int_ier -always @(posedge ACLK) begin - if (ARESET) - int_ier <= 1'b0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_IER && WSTRB[0]) - int_ier <= WDATA[1:0]; - end -end - -// int_isr[0] -always @(posedge ACLK) begin - if (ARESET) - int_isr[0] <= 1'b0; - else if (ACLK_EN) begin - if (int_ier[0] & ap_done) - int_isr[0] <= 1'b1; - else if (w_hs && waddr == ADDR_ISR && WSTRB[0]) - int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write - end -end - -// int_isr[1] -always @(posedge ACLK) begin - if (ARESET) - int_isr[1] <= 1'b0; - else if (ACLK_EN) begin - if (int_ier[1] & ap_ready) - int_isr[1] <= 1'b1; - else if (w_hs && waddr == ADDR_ISR && WSTRB[0]) - int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write - end -end - -// int_n_pixels_in_bus[15:0] -always @(posedge ACLK) begin - if (ARESET) - int_n_pixels_in_bus[15:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_N_PIXELS_IN_BUS_DATA_0) - int_n_pixels_in_bus[15:0] <= (WDATA[31:0] & wmask) | (int_n_pixels_in_bus[15:0] & ~wmask); - end -end - -// int_N_BG[7:0] -always @(posedge ACLK) begin - if (ARESET) - int_N_BG[7:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_N_BG_DATA_0) - int_N_BG[7:0] <= (WDATA[31:0] & wmask) | (int_N_BG[7:0] & ~wmask); - end -end - -// int_LOW_THRESH[31:0] -always @(posedge ACLK) begin - if (ARESET) - int_LOW_THRESH[31:0] <= 0; - else if (ACLK_EN) begin - if (w_hs && waddr == ADDR_LOW_THRESH_DATA_0) - int_LOW_THRESH[31:0] <= (WDATA[31:0] & wmask) | (int_LOW_THRESH[31:0] & ~wmask); - end -end - - -//------------------------Memory logic------------------- - -endmodule diff --git a/l2_trigger/solution1/impl/verilog/l2_trigger_data_shift1.v b/l2_trigger/solution1/impl/verilog/l2_trigger_data_shift1.v deleted file mode 100644 index 10fb2b2..0000000 --- a/l2_trigger/solution1/impl/verilog/l2_trigger_data_shift1.v +++ /dev/null @@ -1,77 +0,0 @@ -// ============================================================== -// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -// Version: 2016.2 -// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved. -// -// ============================================================== - -`timescale 1 ns / 1 ps -module l2_trigger_data_shift1_ram (addr0, ce0, d0, we0, q0, clk); - -parameter DWIDTH = 17; -parameter AWIDTH = 14; -parameter MEM_SIZE = 9216; - -input[AWIDTH-1:0] addr0; -input ce0; -input[DWIDTH-1:0] d0; -input we0; -output reg[DWIDTH-1:0] q0; -input clk; - -(* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; - - - - -always @(posedge clk) -begin - if (ce0) - begin - if (we0) - begin - ram[addr0] <= d0; - q0 <= d0; - end - else - q0 <= ram[addr0]; - end -end - - -endmodule - - -`timescale 1 ns / 1 ps -module l2_trigger_data_shift1( - reset, - clk, - address0, - ce0, - we0, - d0, - q0); - -parameter DataWidth = 32'd17; -parameter AddressRange = 32'd9216; -parameter AddressWidth = 32'd14; -input reset; -input clk; -input[AddressWidth - 1:0] address0; -input ce0; -input we0; -input[DataWidth - 1:0] d0; -output[DataWidth - 1:0] q0; - - - -l2_trigger_data_shift1_ram l2_trigger_data_shift1_ram_U( - .clk( clk ), - .addr0( address0 ), - .ce0( ce0 ), - .d0( d0 ), - .we0( we0 ), - .q0( q0 )); - -endmodule - diff --git a/l2_trigger/solution1/impl/verilog/l2_trigger_sum_overP1.v b/l2_trigger/solution1/impl/verilog/l2_trigger_sum_overP1.v deleted file mode 100644 index 5fcc1ac..0000000 --- a/l2_trigger/solution1/impl/verilog/l2_trigger_sum_overP1.v +++ /dev/null @@ -1,77 +0,0 @@ -// ============================================================== -// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -// Version: 2016.2 -// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved. -// -// ============================================================== - -`timescale 1 ns / 1 ps -module l2_trigger_sum_overP1_ram (addr0, ce0, d0, we0, q0, clk); - -parameter DWIDTH = 32; -parameter AWIDTH = 11; -parameter MEM_SIZE = 1152; - -input[AWIDTH-1:0] addr0; -input ce0; -input[DWIDTH-1:0] d0; -input we0; -output reg[DWIDTH-1:0] q0; -input clk; - -(* ram_style = "block" *)reg [DWIDTH-1:0] ram[MEM_SIZE-1:0]; - - - - -always @(posedge clk) -begin - if (ce0) - begin - if (we0) - begin - ram[addr0] <= d0; - q0 <= d0; - end - else - q0 <= ram[addr0]; - end -end - - -endmodule - - -`timescale 1 ns / 1 ps -module l2_trigger_sum_overP1( - reset, - clk, - address0, - ce0, - we0, - d0, - q0); - -parameter DataWidth = 32'd32; -parameter AddressRange = 32'd1152; -parameter AddressWidth = 32'd11; -input reset; -input clk; -input[AddressWidth - 1:0] address0; -input ce0; -input we0; -input[DataWidth - 1:0] d0; -output[DataWidth - 1:0] q0; - - - -l2_trigger_sum_overP1_ram l2_trigger_sum_overP1_ram_U( - .clk( clk ), - .addr0( address0 ), - .ce0( ce0 ), - .d0( d0 ), - .we0( we0 ), - .q0( q0 )); - -endmodule - diff --git a/l2_trigger/solution1/impl/verilog/project.xpr b/l2_trigger/solution1/impl/verilog/project.xpr deleted file mode 100644 index a952982..0000000 --- a/l2_trigger/solution1/impl/verilog/project.xpr +++ /dev/null @@ -1,147 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Vivado Synthesis Defaults - - - - - - - - Default settings for Implementation. - - - - - - - - - - - - - - diff --git a/l2_trigger/solution1/impl/verilog/run_vivado.tcl b/l2_trigger/solution1/impl/verilog/run_vivado.tcl deleted file mode 100755 index 1d37a5e..0000000 --- a/l2_trigger/solution1/impl/verilog/run_vivado.tcl +++ /dev/null @@ -1,71 +0,0 @@ -## ============================================================== -## File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -## Version: 2016.2 -## Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved. -## -## ============================================================== - -# -# define some helpful variables, dirs, etc. -# -source ./settings.tcl -source ./extraction.tcl - -set projectName l2_trigger -set solutionName solution1 -set targetPart ${device}${package}${speed} -set outputBaseName $top_module -set outputDir ./report -file mkdir $outputDir - -# create project -create_project project . -part $targetPart -force -set_property target_language $language [current_project] - - -# setup design sources and constraints -set hdlfs [glob -nocomplain ./*.vhd ./*.v] -if {$hdlfs != "" } { - add_files -norecurse $hdlfs -} -set xdcfs [glob -nocomplain ./*.xdc] -if {$xdcfs != "" } { - add_files -fileset constrs_1 -norecurse $xdcfs -} - -# vivado scripts to generate IP -set tclfiles [glob -nocomplain *_ip.tcl] -if { $tclfiles != ""} { - foreach file $tclfiles { - source $file - } -} - -# properties setting -if { $add_io_buffers == "false" } { - set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value {-no_iobuf -mode out_of_context} -objects [get_runs synth_1] -} - -# XPM library support -set_param project.defaultXPMLibraries {XPM_MEMORY} -# launch run synth -launch_runs synth_1 -wait_on_run synth_1 -open_run synth_1 -# write a few files and reports after synthesis -report_utilization -file $outputDir/${outputBaseName}_utilization_synth.rpt -report_timing -file $outputDir/${outputBaseName}_timing_synth.rpt - -# launch run impl -set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1] -launch_runs impl_1 -wait_on_run impl_1 -open_run impl_1 -# write a few files and reports after route -report_timing_summary -file $outputDir/${outputBaseName}_timing_routed.rpt -report_utilization -file $outputDir/${outputBaseName}_utilization_routed.rpt - -if { [catch { compile_reports_rodin $top_module $language $targetPart $projectName $solutionName } err] } { - puts "@E \[IMPL-251\] Errors occured while compiling report: $err" - exit 1 -} diff --git a/l2_trigger/solution1/impl/verilog/settings.tcl b/l2_trigger/solution1/impl/verilog/settings.tcl deleted file mode 100644 index 4eb7344..0000000 --- a/l2_trigger/solution1/impl/verilog/settings.tcl +++ /dev/null @@ -1,21 +0,0 @@ -# ============================================================== -# File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -# Version: 2016.2 -# Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved. -# -# ============================================================== - -# -# Settings for Vivado implementation flow -# -set top_module l2_trigger -set language verilog -set family zynq -set device xc7z030 -set package ffg676 -set speed -2 -set clock ap_clk -set fsm_ext "off" - -# For customizing the implementation flow -set add_io_buffers false ;# true|false diff --git a/l2_trigger/solution1/script.tcl b/l2_trigger/solution1/script.tcl index a7e324c..dba2672 100644 --- a/l2_trigger/solution1/script.tcl +++ b/l2_trigger/solution1/script.tcl @@ -5,8 +5,8 @@ ############################################################ open_project l2_trigger set_top l2_trigger -add_files l2_trigger/cpp_code/v10/l2_trigger.cpp add_files l2_trigger/cpp_code/v10/l2_trigger.h +add_files l2_trigger/cpp_code/v10/l2_trigger.cpp add_files -tb l2_trigger/cpp_code/v10/l2_trigger_test.cpp open_solution "solution1" set_part {xc7z030ffg676-2} -tool vivado diff --git a/l2_trigger/solution1/syn/report/l2_trigger_csynth.rpt b/l2_trigger/solution1/syn/report/l2_trigger_csynth.rpt index 141198c..f5fd281 100644 --- a/l2_trigger/solution1/syn/report/l2_trigger_csynth.rpt +++ b/l2_trigger/solution1/syn/report/l2_trigger_csynth.rpt @@ -3,7 +3,7 @@ ================================================================ == Vivado HLS Report for 'l2_trigger' ================================================================ -* Date: Fri Apr 13 19:40:42 2018 +* Date: Wed Apr 18 11:09:40 2018 * Version: 2016.2 (Build 1577090 on Thu Jun 02 16:59:10 MDT 2016) * Project: l2_trigger @@ -44,10 +44,10 @@ |- Loop 1 | 0| 32767| 1| -| -| 0 ~ 32767 | no | |- Loop 2 | 16| 262152| 2 ~ 32769 | -| -| 8| no | | + Loop 2.1 | 0| 32767| 1| -| -| 0 ~ 32767 | no | - |- Loop 3 | ?| ?| 260 ~ 88274558 | -| -| ?| no | + |- Loop 3 | ?| ?| 260 ~ 84080382 | -| -| ?| no | | + Loop 3.1 | 0| 32767| 1| -| -| 0 ~ 32767 | no | - | + Loop 3.2 | 256| 88077952| 2 ~ 688109 | -| -| 128| no | - | ++ Loop 3.2.1 | 0| 688107| 18 ~ 21 | -| -| 0 ~ 32767 | no | + | + Loop 3.2 | 256| 83883776| 2 ~ 655342 | -| -| 128| no | + | ++ Loop 3.2.1 | 0| 655340| 18 ~ 20 | -| -| 0 ~ 32767 | no | | +++ Loop 3.2.1.1 | 14| 14| 2| -| -| 7| no | | + Loop 3.3 | 0| 163835| 5| -| -| 0 ~ 32767 | no | +---------------------+-----+----------+----------------+-----------+-----------+-----------+----------+ @@ -66,10 +66,10 @@ |FIFO | -| -| -| -| |Instance | 0| -| 110| 152| |Memory | 58| -| 0| 0| -|Multiplexer | -| -| -| 528| -|Register | -| -| 636| -| +|Multiplexer | -| -| -| 560| +|Register | -| -| 634| -| +-----------------+---------+-------+--------+-------+ -|Total | 58| 4| 746| 1141| +|Total | 58| 4| 744| 1173| +-----------------+---------+-------+--------+-------+ |Available | 530| 400| 157200| 78600| +-----------------+---------+-------+--------+-------+ @@ -158,7 +158,7 @@ +----------------------------------+----+-----------+-----+-----------+ | Name | LUT| Input Size| Bits| Total Bits| +----------------------------------+----+-----------+-----+-----------+ - |ap_NS_fsm | 18| 23| 1| 23| + |ap_NS_fsm | 18| 21| 1| 21| |ap_sig_ioackin_out_stream_TREADY | 1| 2| 1| 2| |data_shift1_address0 | 14| 5| 14| 70| |data_shift1_d0 | 17| 4| 17| 68| @@ -188,9 +188,10 @@ |thresh1_d0 | 32| 4| 32| 128| |thresh2_address0 | 11| 4| 11| 44| |thresh2_d0 | 32| 4| 32| 128| - |trig_data | 32| 5| 32| 160| + |trig_data | 32| 3| 32| 96| + |trig_pixel | 32| 4| 32| 128| +----------------------------------+----+-----------+-----+-----------+ - |Total | 528| 121| 511| 1797| + |Total | 560| 121| 543| 1859| +----------------------------------+----+-----------+-----+-----------+ * Register: @@ -198,7 +199,7 @@ | Name | FF | LUT| Bits| Const Bits| +----------------------------------+----+----+-----+-----------+ |LOW_THRESH_read_reg_1104 | 32| 0| 32| 0| - |ap_CS_fsm | 22| 0| 22| 0| + |ap_CS_fsm | 20| 0| 20| 0| |ap_reg_ioackin_out_stream_TREADY | 1| 0| 1| 0| |data_shift1_addr_1_reg_1206 | 14| 0| 14| 0| |data_shift2_addr_1_reg_1211 | 14| 0| 14| 0| @@ -238,7 +239,7 @@ |tmp_3_reg_1143 | 8| 0| 15| 7| |tmp_5_reg_1170 | 8| 0| 8| 0| +----------------------------------+----+----+-----+-----------+ - |Total | 636| 0| 716| 80| + |Total | 634| 0| 714| 80| +----------------------------------+----+----+-----+-----------+ diff --git a/l2_trigger/solution1/syn/report/l2_trigger_csynth.xml b/l2_trigger/solution1/syn/report/l2_trigger_csynth.xml index 0ab0a15..479b9e8 100644 --- a/l2_trigger/solution1/syn/report/l2_trigger_csynth.xml +++ b/l2_trigger/solution1/syn/report/l2_trigger_csynth.xml @@ -79,7 +79,7 @@ 260 -88274558 +84080382 @@ -102,13 +102,13 @@ 256 -88077952 +83883776 2 -688109 +655342 @@ -121,13 +121,13 @@ 0 -688107 +655340 18 -21 +20 @@ -160,8 +160,8 @@ 58 4 -746 -1141 +744 +1173 530 diff --git a/l2_trigger/solution1/syn/systemc/l2_trigger.cpp b/l2_trigger/solution1/syn/systemc/l2_trigger.cpp index 1546da1..3f5c09d 100644 --- a/l2_trigger/solution1/syn/systemc/l2_trigger.cpp +++ b/l2_trigger/solution1/syn/systemc/l2_trigger.cpp @@ -14,32 +14,30 @@ namespace ap_rtl { const sc_logic l2_trigger::ap_const_logic_1 = sc_dt::Log_1; const sc_logic l2_trigger::ap_const_logic_0 = sc_dt::Log_0; -const sc_lv<22> l2_trigger::ap_ST_st1_fsm_0 = "1"; -const sc_lv<22> l2_trigger::ap_ST_st2_fsm_1 = "10"; -const sc_lv<22> l2_trigger::ap_ST_st3_fsm_2 = "100"; -const sc_lv<22> l2_trigger::ap_ST_st4_fsm_3 = "1000"; -const sc_lv<22> l2_trigger::ap_ST_st5_fsm_4 = "10000"; -const sc_lv<22> l2_trigger::ap_ST_st6_fsm_5 = "100000"; -const sc_lv<22> l2_trigger::ap_ST_st7_fsm_6 = "1000000"; -const sc_lv<22> l2_trigger::ap_ST_st8_fsm_7 = "10000000"; -const sc_lv<22> l2_trigger::ap_ST_st9_fsm_8 = "100000000"; -const sc_lv<22> l2_trigger::ap_ST_st10_fsm_9 = "1000000000"; -const sc_lv<22> l2_trigger::ap_ST_st11_fsm_10 = "10000000000"; -const sc_lv<22> l2_trigger::ap_ST_st12_fsm_11 = "100000000000"; -const sc_lv<22> l2_trigger::ap_ST_st13_fsm_12 = "1000000000000"; -const sc_lv<22> l2_trigger::ap_ST_st14_fsm_13 = "10000000000000"; -const sc_lv<22> l2_trigger::ap_ST_st15_fsm_14 = "100000000000000"; -const sc_lv<22> l2_trigger::ap_ST_st16_fsm_15 = "1000000000000000"; -const sc_lv<22> l2_trigger::ap_ST_st17_fsm_16 = "10000000000000000"; -const sc_lv<22> l2_trigger::ap_ST_st18_fsm_17 = "100000000000000000"; -const sc_lv<22> l2_trigger::ap_ST_st19_fsm_18 = "1000000000000000000"; -const sc_lv<22> l2_trigger::ap_ST_st20_fsm_19 = "10000000000000000000"; -const sc_lv<22> l2_trigger::ap_ST_st21_fsm_20 = "100000000000000000000"; -const sc_lv<22> l2_trigger::ap_ST_st22_fsm_21 = "1000000000000000000000"; +const sc_lv<20> l2_trigger::ap_ST_st1_fsm_0 = "1"; +const sc_lv<20> l2_trigger::ap_ST_st2_fsm_1 = "10"; +const sc_lv<20> l2_trigger::ap_ST_st3_fsm_2 = "100"; +const sc_lv<20> l2_trigger::ap_ST_st4_fsm_3 = "1000"; +const sc_lv<20> l2_trigger::ap_ST_st5_fsm_4 = "10000"; +const sc_lv<20> l2_trigger::ap_ST_st6_fsm_5 = "100000"; +const sc_lv<20> l2_trigger::ap_ST_st7_fsm_6 = "1000000"; +const sc_lv<20> l2_trigger::ap_ST_st8_fsm_7 = "10000000"; +const sc_lv<20> l2_trigger::ap_ST_st9_fsm_8 = "100000000"; +const sc_lv<20> l2_trigger::ap_ST_st10_fsm_9 = "1000000000"; +const sc_lv<20> l2_trigger::ap_ST_st11_fsm_10 = "10000000000"; +const sc_lv<20> l2_trigger::ap_ST_st12_fsm_11 = "100000000000"; +const sc_lv<20> l2_trigger::ap_ST_st13_fsm_12 = "1000000000000"; +const sc_lv<20> l2_trigger::ap_ST_st14_fsm_13 = "10000000000000"; +const sc_lv<20> l2_trigger::ap_ST_st15_fsm_14 = "100000000000000"; +const sc_lv<20> l2_trigger::ap_ST_st16_fsm_15 = "1000000000000000"; +const sc_lv<20> l2_trigger::ap_ST_st17_fsm_16 = "10000000000000000"; +const sc_lv<20> l2_trigger::ap_ST_st18_fsm_17 = "100000000000000000"; +const sc_lv<20> l2_trigger::ap_ST_st19_fsm_18 = "1000000000000000000"; +const sc_lv<20> l2_trigger::ap_ST_st20_fsm_19 = "10000000000000000000"; const sc_lv<32> l2_trigger::ap_const_lv32_0 = "00000000000000000000000000000000"; const sc_lv<1> l2_trigger::ap_const_lv1_1 = "1"; const sc_lv<32> l2_trigger::ap_const_lv32_8 = "1000"; -const sc_lv<32> l2_trigger::ap_const_lv32_12 = "10010"; +const sc_lv<32> l2_trigger::ap_const_lv32_10 = "10000"; const int l2_trigger::C_S_AXI_DATA_WIDTH = "100000"; const sc_lv<32> l2_trigger::ap_const_lv32_1 = "1"; const sc_lv<32> l2_trigger::ap_const_lv32_2 = "10"; @@ -51,20 +49,18 @@ const sc_lv<32> l2_trigger::ap_const_lv32_7 = "111"; const sc_lv<32> l2_trigger::ap_const_lv32_9 = "1001"; const sc_lv<32> l2_trigger::ap_const_lv32_A = "1010"; const sc_lv<32> l2_trigger::ap_const_lv32_B = "1011"; +const sc_lv<32> l2_trigger::ap_const_lv32_F = "1111"; const sc_lv<32> l2_trigger::ap_const_lv32_11 = "10001"; -const sc_lv<32> l2_trigger::ap_const_lv32_13 = "10011"; -const sc_lv<32> l2_trigger::ap_const_lv32_14 = "10100"; +const sc_lv<32> l2_trigger::ap_const_lv32_12 = "10010"; const sc_lv<15> l2_trigger::ap_const_lv15_0 = "000000000000000"; const sc_lv<4> l2_trigger::ap_const_lv4_0 = "0000"; const sc_lv<32> l2_trigger::ap_const_lv32_4 = "100"; const sc_lv<8> l2_trigger::ap_const_lv8_0 = "00000000"; -const sc_lv<32> l2_trigger::ap_const_lv32_E = "1110"; +const sc_lv<32> l2_trigger::ap_const_lv32_D = "1101"; const sc_lv<32> l2_trigger::ap_const_lv32_C = "1100"; -const sc_lv<32> l2_trigger::ap_const_lv32_10 = "10000"; +const sc_lv<32> l2_trigger::ap_const_lv32_E = "1110"; const sc_lv<4> l2_trigger::ap_const_lv4_6 = "110"; -const sc_lv<32> l2_trigger::ap_const_lv32_15 = "10101"; -const sc_lv<32> l2_trigger::ap_const_lv32_D = "1101"; -const sc_lv<32> l2_trigger::ap_const_lv32_F = "1111"; +const sc_lv<32> l2_trigger::ap_const_lv32_13 = "10011"; const sc_lv<8> l2_trigger::ap_const_lv8_FF = "11111111"; const sc_lv<2> l2_trigger::ap_const_lv2_0 = "00"; const sc_lv<5> l2_trigger::ap_const_lv5_0 = "00000"; @@ -197,137 +193,125 @@ l2_trigger::l2_trigger(sc_module_name name) : sc_module(name), mVcdFile(0) { SC_METHOD(thread_ap_rst_n_inv); sensitive << ( ap_rst_n ); - SC_METHOD(thread_ap_sig_139); - sensitive << ( ap_CS_fsm ); - - SC_METHOD(thread_ap_sig_148); - sensitive << ( ap_CS_fsm ); - - SC_METHOD(thread_ap_sig_163); + SC_METHOD(thread_ap_sig_137); sensitive << ( ap_CS_fsm ); - SC_METHOD(thread_ap_sig_172); + SC_METHOD(thread_ap_sig_146); sensitive << ( ap_CS_fsm ); - SC_METHOD(thread_ap_sig_181); + SC_METHOD(thread_ap_sig_161); sensitive << ( ap_CS_fsm ); - SC_METHOD(thread_ap_sig_190); + SC_METHOD(thread_ap_sig_170); sensitive << ( ap_CS_fsm ); - SC_METHOD(thread_ap_sig_227); + SC_METHOD(thread_ap_sig_179); sensitive << ( ap_CS_fsm ); - SC_METHOD(thread_ap_sig_245); + SC_METHOD(thread_ap_sig_188); sensitive << ( ap_CS_fsm ); - SC_METHOD(thread_ap_sig_254); + SC_METHOD(thread_ap_sig_225); sensitive << ( ap_CS_fsm ); - SC_METHOD(thread_ap_sig_270); + SC_METHOD(thread_ap_sig_243); sensitive << ( ap_CS_fsm ); - SC_METHOD(thread_ap_sig_298); + SC_METHOD(thread_ap_sig_252); sensitive << ( ap_CS_fsm ); - SC_METHOD(thread_ap_sig_309); + SC_METHOD(thread_ap_sig_268); sensitive << ( ap_CS_fsm ); - SC_METHOD(thread_ap_sig_39); + SC_METHOD(thread_ap_sig_296); sensitive << ( ap_CS_fsm ); - SC_METHOD(thread_ap_sig_413); + SC_METHOD(thread_ap_sig_307); sensitive << ( ap_CS_fsm ); - SC_METHOD(thread_ap_sig_439); + SC_METHOD(thread_ap_sig_37); sensitive << ( ap_CS_fsm ); - SC_METHOD(thread_ap_sig_446); + SC_METHOD(thread_ap_sig_411); sensitive << ( ap_CS_fsm ); - SC_METHOD(thread_ap_sig_457); + SC_METHOD(thread_ap_sig_437); sensitive << ( ap_CS_fsm ); - SC_METHOD(thread_ap_sig_478); + SC_METHOD(thread_ap_sig_444); sensitive << ( ap_CS_fsm ); - SC_METHOD(thread_ap_sig_511); + SC_METHOD(thread_ap_sig_455); sensitive << ( ap_CS_fsm ); - SC_METHOD(thread_ap_sig_520); + SC_METHOD(thread_ap_sig_476); sensitive << ( ap_CS_fsm ); - SC_METHOD(thread_ap_sig_77); + SC_METHOD(thread_ap_sig_75); sensitive << ( ap_CS_fsm ); - SC_METHOD(thread_ap_sig_85); + SC_METHOD(thread_ap_sig_83); sensitive << ( ap_CS_fsm ); SC_METHOD(thread_ap_sig_cseq_ST_st10_fsm_9); - sensitive << ( ap_sig_227 ); + sensitive << ( ap_sig_225 ); SC_METHOD(thread_ap_sig_cseq_ST_st11_fsm_10); - sensitive << ( ap_sig_245 ); + sensitive << ( ap_sig_243 ); SC_METHOD(thread_ap_sig_cseq_ST_st12_fsm_11); - sensitive << ( ap_sig_254 ); + sensitive << ( ap_sig_252 ); SC_METHOD(thread_ap_sig_cseq_ST_st13_fsm_12); - sensitive << ( ap_sig_446 ); + sensitive << ( ap_sig_444 ); SC_METHOD(thread_ap_sig_cseq_ST_st14_fsm_13); - sensitive << ( ap_sig_511 ); + sensitive << ( ap_sig_437 ); SC_METHOD(thread_ap_sig_cseq_ST_st15_fsm_14); - sensitive << ( ap_sig_439 ); + sensitive << ( ap_sig_455 ); SC_METHOD(thread_ap_sig_cseq_ST_st16_fsm_15); - sensitive << ( ap_sig_520 ); + sensitive << ( ap_sig_268 ); SC_METHOD(thread_ap_sig_cseq_ST_st17_fsm_16); - sensitive << ( ap_sig_457 ); + sensitive << ( ap_sig_83 ); SC_METHOD(thread_ap_sig_cseq_ST_st18_fsm_17); - sensitive << ( ap_sig_270 ); + sensitive << ( ap_sig_296 ); SC_METHOD(thread_ap_sig_cseq_ST_st19_fsm_18); - sensitive << ( ap_sig_85 ); + sensitive << ( ap_sig_307 ); SC_METHOD(thread_ap_sig_cseq_ST_st1_fsm_0); - sensitive << ( ap_sig_39 ); + sensitive << ( ap_sig_37 ); SC_METHOD(thread_ap_sig_cseq_ST_st20_fsm_19); - sensitive << ( ap_sig_298 ); - - SC_METHOD(thread_ap_sig_cseq_ST_st21_fsm_20); - sensitive << ( ap_sig_309 ); - - SC_METHOD(thread_ap_sig_cseq_ST_st22_fsm_21); - sensitive << ( ap_sig_478 ); + sensitive << ( ap_sig_476 ); SC_METHOD(thread_ap_sig_cseq_ST_st2_fsm_1); - sensitive << ( ap_sig_139 ); + sensitive << ( ap_sig_137 ); SC_METHOD(thread_ap_sig_cseq_ST_st3_fsm_2); - sensitive << ( ap_sig_148 ); + sensitive << ( ap_sig_146 ); SC_METHOD(thread_ap_sig_cseq_ST_st4_fsm_3); - sensitive << ( ap_sig_163 ); + sensitive << ( ap_sig_161 ); SC_METHOD(thread_ap_sig_cseq_ST_st5_fsm_4); - sensitive << ( ap_sig_413 ); + sensitive << ( ap_sig_411 ); SC_METHOD(thread_ap_sig_cseq_ST_st6_fsm_5); - sensitive << ( ap_sig_172 ); + sensitive << ( ap_sig_170 ); SC_METHOD(thread_ap_sig_cseq_ST_st7_fsm_6); - sensitive << ( ap_sig_181 ); + sensitive << ( ap_sig_179 ); SC_METHOD(thread_ap_sig_cseq_ST_st8_fsm_7); - sensitive << ( ap_sig_190 ); + sensitive << ( ap_sig_188 ); SC_METHOD(thread_ap_sig_cseq_ST_st9_fsm_8); - sensitive << ( ap_sig_77 ); + sensitive << ( ap_sig_75 ); SC_METHOD(thread_ap_sig_ioackin_out_stream_TREADY); sensitive << ( out_stream_TREADY ); @@ -406,7 +390,7 @@ l2_trigger::l2_trigger(sc_module_name name) : sc_module(name), mVcdFile(0) { SC_METHOD(thread_exitcond6_fu_1016_p2); sensitive << ( tmp_2_reg_1118 ); - sensitive << ( ap_sig_cseq_ST_st18_fsm_17 ); + sensitive << ( ap_sig_cseq_ST_st16_fsm_15 ); sensitive << ( i_4_reg_622 ); SC_METHOD(thread_exitcond7_fu_765_p2); @@ -473,34 +457,34 @@ l2_trigger::l2_trigger(sc_module_name name) : sc_module(name), mVcdFile(0) { sensitive << ( tmp_35_fu_974_p2 ); SC_METHOD(thread_out_stream_TDATA); - sensitive << ( ap_sig_cseq_ST_st19_fsm_18 ); + sensitive << ( ap_sig_cseq_ST_st17_fsm_16 ); sensitive << ( sum_pix1_q0 ); sensitive << ( sum_pix2_q0 ); SC_METHOD(thread_out_stream_TDATA_blk_n); sensitive << ( out_stream_TREADY ); - sensitive << ( ap_sig_cseq_ST_st19_fsm_18 ); + sensitive << ( ap_sig_cseq_ST_st17_fsm_16 ); SC_METHOD(thread_out_stream_TDEST); - sensitive << ( ap_sig_cseq_ST_st19_fsm_18 ); + sensitive << ( ap_sig_cseq_ST_st17_fsm_16 ); SC_METHOD(thread_out_stream_TID); - sensitive << ( ap_sig_cseq_ST_st19_fsm_18 ); + sensitive << ( ap_sig_cseq_ST_st17_fsm_16 ); SC_METHOD(thread_out_stream_TKEEP); - sensitive << ( ap_sig_cseq_ST_st19_fsm_18 ); + sensitive << ( ap_sig_cseq_ST_st17_fsm_16 ); SC_METHOD(thread_out_stream_TLAST); - sensitive << ( ap_sig_cseq_ST_st19_fsm_18 ); + sensitive << ( ap_sig_cseq_ST_st17_fsm_16 ); SC_METHOD(thread_out_stream_TSTRB); - sensitive << ( ap_sig_cseq_ST_st19_fsm_18 ); + sensitive << ( ap_sig_cseq_ST_st17_fsm_16 ); SC_METHOD(thread_out_stream_TUSER); - sensitive << ( ap_sig_cseq_ST_st19_fsm_18 ); + sensitive << ( ap_sig_cseq_ST_st17_fsm_16 ); SC_METHOD(thread_out_stream_TVALID); - sensitive << ( ap_sig_cseq_ST_st19_fsm_18 ); + sensitive << ( ap_sig_cseq_ST_st17_fsm_16 ); sensitive << ( ap_reg_ioackin_out_stream_TREADY ); SC_METHOD(thread_p_shl1_cast_fu_704_p1); @@ -591,7 +575,7 @@ l2_trigger::l2_trigger(sc_module_name name) : sc_module(name), mVcdFile(0) { sensitive << ( ap_sig_cseq_ST_st8_fsm_7 ); sensitive << ( tmp_15_fu_776_p1 ); sensitive << ( sum_pix1_addr_3_reg_1196 ); - sensitive << ( ap_sig_cseq_ST_st18_fsm_17 ); + sensitive << ( ap_sig_cseq_ST_st16_fsm_15 ); sensitive << ( tmp_4_fu_664_p1 ); sensitive << ( tmp_7_fu_747_p1 ); sensitive << ( tmp_9_fu_1027_p1 ); @@ -602,7 +586,7 @@ l2_trigger::l2_trigger(sc_module_name name) : sc_module(name), mVcdFile(0) { sensitive << ( ap_sig_cseq_ST_st2_fsm_1 ); sensitive << ( ap_sig_cseq_ST_st6_fsm_5 ); sensitive << ( ap_sig_cseq_ST_st8_fsm_7 ); - sensitive << ( ap_sig_cseq_ST_st18_fsm_17 ); + sensitive << ( ap_sig_cseq_ST_st16_fsm_15 ); SC_METHOD(thread_sum_pix1_d0); sensitive << ( ap_sig_cseq_ST_st9_fsm_8 ); @@ -625,7 +609,7 @@ l2_trigger::l2_trigger(sc_module_name name) : sc_module(name), mVcdFile(0) { sensitive << ( ap_sig_cseq_ST_st8_fsm_7 ); sensitive << ( tmp_15_fu_776_p1 ); sensitive << ( sum_pix2_addr_3_reg_1201 ); - sensitive << ( ap_sig_cseq_ST_st18_fsm_17 ); + sensitive << ( ap_sig_cseq_ST_st16_fsm_15 ); sensitive << ( tmp_4_fu_664_p1 ); sensitive << ( tmp_7_fu_747_p1 ); sensitive << ( tmp_9_fu_1027_p1 ); @@ -636,7 +620,7 @@ l2_trigger::l2_trigger(sc_module_name name) : sc_module(name), mVcdFile(0) { sensitive << ( ap_sig_cseq_ST_st2_fsm_1 ); sensitive << ( ap_sig_cseq_ST_st6_fsm_5 ); sensitive << ( ap_sig_cseq_ST_st8_fsm_7 ); - sensitive << ( ap_sig_cseq_ST_st18_fsm_17 ); + sensitive << ( ap_sig_cseq_ST_st16_fsm_15 ); SC_METHOD(thread_sum_pix2_d0); sensitive << ( ap_sig_cseq_ST_st9_fsm_8 ); @@ -663,61 +647,61 @@ l2_trigger::l2_trigger(sc_module_name name) : sc_module(name), mVcdFile(0) { sensitive << ( tmp_15_reg_1186 ); sensitive << ( ap_sig_cseq_ST_st10_fsm_9 ); sensitive << ( thresh1_addr_1_reg_1311 ); - sensitive << ( ap_sig_cseq_ST_st21_fsm_20 ); - sensitive << ( ap_sig_cseq_ST_st22_fsm_21 ); + sensitive << ( ap_sig_cseq_ST_st19_fsm_18 ); + sensitive << ( ap_sig_cseq_ST_st20_fsm_19 ); sensitive << ( tmp_4_fu_664_p1 ); SC_METHOD(thread_thresh1_ce0); sensitive << ( ap_sig_cseq_ST_st2_fsm_1 ); sensitive << ( ap_sig_cseq_ST_st10_fsm_9 ); - sensitive << ( ap_sig_cseq_ST_st21_fsm_20 ); - sensitive << ( ap_sig_cseq_ST_st22_fsm_21 ); + sensitive << ( ap_sig_cseq_ST_st19_fsm_18 ); + sensitive << ( ap_sig_cseq_ST_st20_fsm_19 ); SC_METHOD(thread_thresh1_d0); sensitive << ( LOW_THRESH_read_reg_1104 ); sensitive << ( ap_sig_cseq_ST_st2_fsm_1 ); sensitive << ( tmp_12_reg_1331 ); - sensitive << ( ap_sig_cseq_ST_st21_fsm_20 ); - sensitive << ( ap_sig_cseq_ST_st22_fsm_21 ); + sensitive << ( ap_sig_cseq_ST_st19_fsm_18 ); + sensitive << ( ap_sig_cseq_ST_st20_fsm_19 ); SC_METHOD(thread_thresh1_we0); sensitive << ( ap_sig_cseq_ST_st2_fsm_1 ); sensitive << ( tmp_14_reg_1343 ); - sensitive << ( ap_sig_cseq_ST_st21_fsm_20 ); + sensitive << ( ap_sig_cseq_ST_st19_fsm_18 ); sensitive << ( exitcond2_fu_653_p2 ); - sensitive << ( ap_sig_cseq_ST_st22_fsm_21 ); + sensitive << ( ap_sig_cseq_ST_st20_fsm_19 ); SC_METHOD(thread_thresh2_address0); sensitive << ( ap_sig_cseq_ST_st2_fsm_1 ); sensitive << ( tmp_15_reg_1186 ); sensitive << ( ap_sig_cseq_ST_st12_fsm_11 ); sensitive << ( thresh2_addr_1_reg_1316 ); - sensitive << ( ap_sig_cseq_ST_st21_fsm_20 ); - sensitive << ( ap_sig_cseq_ST_st22_fsm_21 ); + sensitive << ( ap_sig_cseq_ST_st19_fsm_18 ); + sensitive << ( ap_sig_cseq_ST_st20_fsm_19 ); sensitive << ( tmp_4_fu_664_p1 ); SC_METHOD(thread_thresh2_ce0); sensitive << ( ap_sig_cseq_ST_st2_fsm_1 ); sensitive << ( ap_sig_cseq_ST_st12_fsm_11 ); - sensitive << ( ap_sig_cseq_ST_st21_fsm_20 ); - sensitive << ( ap_sig_cseq_ST_st22_fsm_21 ); + sensitive << ( ap_sig_cseq_ST_st19_fsm_18 ); + sensitive << ( ap_sig_cseq_ST_st20_fsm_19 ); SC_METHOD(thread_thresh2_d0); sensitive << ( LOW_THRESH_read_reg_1104 ); sensitive << ( ap_sig_cseq_ST_st2_fsm_1 ); sensitive << ( tmp_13_reg_1337 ); - sensitive << ( ap_sig_cseq_ST_st21_fsm_20 ); - sensitive << ( ap_sig_cseq_ST_st22_fsm_21 ); + sensitive << ( ap_sig_cseq_ST_st19_fsm_18 ); + sensitive << ( ap_sig_cseq_ST_st20_fsm_19 ); SC_METHOD(thread_thresh2_we0); sensitive << ( ap_sig_cseq_ST_st2_fsm_1 ); - sensitive << ( ap_sig_cseq_ST_st21_fsm_20 ); + sensitive << ( ap_sig_cseq_ST_st19_fsm_18 ); sensitive << ( exitcond2_fu_653_p2 ); - sensitive << ( ap_sig_cseq_ST_st22_fsm_21 ); + sensitive << ( ap_sig_cseq_ST_st20_fsm_19 ); sensitive << ( tmp_21_fu_1100_p2 ); SC_METHOD(thread_tmp_12_fu_1086_p0); - sensitive << ( ap_sig_cseq_ST_st20_fsm_19 ); + sensitive << ( ap_sig_cseq_ST_st18_fsm_17 ); sensitive << ( tmp_12_fu_1086_p00 ); SC_METHOD(thread_tmp_12_fu_1086_p00); @@ -725,14 +709,14 @@ l2_trigger::l2_trigger(sc_module_name name) : sc_module(name), mVcdFile(0) { SC_METHOD(thread_tmp_12_fu_1086_p1); sensitive << ( tmp_1_reg_1112 ); - sensitive << ( ap_sig_cseq_ST_st20_fsm_19 ); + sensitive << ( ap_sig_cseq_ST_st18_fsm_17 ); SC_METHOD(thread_tmp_12_fu_1086_p2); sensitive << ( tmp_12_fu_1086_p0 ); sensitive << ( tmp_12_fu_1086_p1 ); SC_METHOD(thread_tmp_13_fu_1091_p0); - sensitive << ( ap_sig_cseq_ST_st20_fsm_19 ); + sensitive << ( ap_sig_cseq_ST_st18_fsm_17 ); sensitive << ( tmp_13_fu_1091_p00 ); SC_METHOD(thread_tmp_13_fu_1091_p00); @@ -740,7 +724,7 @@ l2_trigger::l2_trigger(sc_module_name name) : sc_module(name), mVcdFile(0) { SC_METHOD(thread_tmp_13_fu_1091_p1); sensitive << ( tmp_1_reg_1112 ); - sensitive << ( ap_sig_cseq_ST_st20_fsm_19 ); + sensitive << ( ap_sig_cseq_ST_st18_fsm_17 ); SC_METHOD(thread_tmp_13_fu_1091_p2); sensitive << ( tmp_13_fu_1091_p0 ); @@ -749,7 +733,7 @@ l2_trigger::l2_trigger(sc_module_name name) : sc_module(name), mVcdFile(0) { SC_METHOD(thread_tmp_14_fu_1096_p2); sensitive << ( LOW_THRESH_read_reg_1104 ); sensitive << ( tmp_12_reg_1331 ); - sensitive << ( ap_sig_cseq_ST_st21_fsm_20 ); + sensitive << ( ap_sig_cseq_ST_st19_fsm_18 ); SC_METHOD(thread_tmp_15_fu_776_p1); sensitive << ( i_3_reg_569 ); @@ -786,7 +770,7 @@ l2_trigger::l2_trigger(sc_module_name name) : sc_module(name), mVcdFile(0) { SC_METHOD(thread_tmp_21_fu_1100_p2); sensitive << ( LOW_THRESH_read_reg_1104 ); sensitive << ( tmp_13_reg_1337 ); - sensitive << ( ap_sig_cseq_ST_st22_fsm_21 ); + sensitive << ( ap_sig_cseq_ST_st20_fsm_19 ); SC_METHOD(thread_tmp_22_fu_822_p3); sensitive << ( kk_1_reg_610 ); @@ -904,14 +888,10 @@ l2_trigger::l2_trigger(sc_module_name name) : sc_module(name), mVcdFile(0) { sensitive << ( ap_sig_cseq_ST_st12_fsm_11 ); sensitive << ( tmp_25_fu_968_p2 ); sensitive << ( grp_fu_633_p2 ); - sensitive << ( ap_sig_cseq_ST_st15_fsm_14 ); + sensitive << ( ap_sig_cseq_ST_st14_fsm_13 ); sensitive << ( ap_sig_cseq_ST_st13_fsm_12 ); sensitive << ( or_cond_fu_979_p2 ); - sensitive << ( ap_sig_cseq_ST_st17_fsm_16 ); - sensitive << ( ap_sig_cseq_ST_st14_fsm_13 ); - sensitive << ( tmp_40_cast_fu_998_p1 ); - sensitive << ( ap_sig_cseq_ST_st16_fsm_15 ); - sensitive << ( tmp_38_cast_fu_1011_p1 ); + sensitive << ( ap_sig_cseq_ST_st15_fsm_14 ); SC_METHOD(thread_trig_data_ap_vld); sensitive << ( ap_start ); @@ -919,20 +899,26 @@ l2_trigger::l2_trigger(sc_module_name name) : sc_module(name), mVcdFile(0) { sensitive << ( ap_sig_cseq_ST_st12_fsm_11 ); sensitive << ( tmp_25_fu_968_p2 ); sensitive << ( grp_fu_633_p2 ); - sensitive << ( ap_sig_cseq_ST_st15_fsm_14 ); + sensitive << ( ap_sig_cseq_ST_st14_fsm_13 ); sensitive << ( ap_sig_cseq_ST_st13_fsm_12 ); sensitive << ( or_cond_fu_979_p2 ); - sensitive << ( ap_sig_cseq_ST_st17_fsm_16 ); - sensitive << ( ap_sig_cseq_ST_st14_fsm_13 ); - sensitive << ( ap_sig_cseq_ST_st16_fsm_15 ); + sensitive << ( ap_sig_cseq_ST_st15_fsm_14 ); SC_METHOD(thread_trig_pixel); sensitive << ( ap_start ); sensitive << ( ap_sig_cseq_ST_st1_fsm_0 ); + sensitive << ( ap_sig_cseq_ST_st13_fsm_12 ); + sensitive << ( or_cond_fu_979_p2 ); + sensitive << ( ap_sig_cseq_ST_st15_fsm_14 ); + sensitive << ( tmp_40_cast_fu_998_p1 ); + sensitive << ( tmp_38_cast_fu_1011_p1 ); SC_METHOD(thread_trig_pixel_ap_vld); sensitive << ( ap_start ); sensitive << ( ap_sig_cseq_ST_st1_fsm_0 ); + sensitive << ( ap_sig_cseq_ST_st13_fsm_12 ); + sensitive << ( or_cond_fu_979_p2 ); + sensitive << ( ap_sig_cseq_ST_st15_fsm_14 ); SC_METHOD(thread_ap_NS_fsm); sensitive << ( ap_start ); @@ -957,7 +943,7 @@ l2_trigger::l2_trigger(sc_module_name name) : sc_module(name), mVcdFile(0) { SC_THREAD(thread_ap_var_for_const0); - ap_CS_fsm = "0000000000000000000001"; + ap_CS_fsm = "00000000000000000001"; ap_reg_ioackin_out_stream_TREADY = SC_LOGIC_0; static int apTFileNum = 0; stringstream apTFilenSS; @@ -1017,45 +1003,45 @@ l2_trigger::l2_trigger(sc_module_name name) : sc_module(name), mVcdFile(0) { sc_trace(mVcdFile, ap_idle, "ap_idle"); sc_trace(mVcdFile, ap_CS_fsm, "ap_CS_fsm"); sc_trace(mVcdFile, ap_sig_cseq_ST_st1_fsm_0, "ap_sig_cseq_ST_st1_fsm_0"); - sc_trace(mVcdFile, ap_sig_39, "ap_sig_39"); + sc_trace(mVcdFile, ap_sig_37, "ap_sig_37"); sc_trace(mVcdFile, ap_ready, "ap_ready"); sc_trace(mVcdFile, n_pixels_in_bus, "n_pixels_in_bus"); sc_trace(mVcdFile, N_BG, "N_BG"); sc_trace(mVcdFile, LOW_THRESH, "LOW_THRESH"); sc_trace(mVcdFile, in_stream_TDATA_blk_n, "in_stream_TDATA_blk_n"); sc_trace(mVcdFile, ap_sig_cseq_ST_st9_fsm_8, "ap_sig_cseq_ST_st9_fsm_8"); - sc_trace(mVcdFile, ap_sig_77, "ap_sig_77"); + sc_trace(mVcdFile, ap_sig_75, "ap_sig_75"); sc_trace(mVcdFile, out_stream_TDATA_blk_n, "out_stream_TDATA_blk_n"); - sc_trace(mVcdFile, ap_sig_cseq_ST_st19_fsm_18, "ap_sig_cseq_ST_st19_fsm_18"); - sc_trace(mVcdFile, ap_sig_85, "ap_sig_85"); + sc_trace(mVcdFile, ap_sig_cseq_ST_st17_fsm_16, "ap_sig_cseq_ST_st17_fsm_16"); + sc_trace(mVcdFile, ap_sig_83, "ap_sig_83"); sc_trace(mVcdFile, LOW_THRESH_read_reg_1104, "LOW_THRESH_read_reg_1104"); sc_trace(mVcdFile, tmp_1_fu_639_p1, "tmp_1_fu_639_p1"); sc_trace(mVcdFile, tmp_1_reg_1112, "tmp_1_reg_1112"); sc_trace(mVcdFile, tmp_2_reg_1118, "tmp_2_reg_1118"); sc_trace(mVcdFile, i_5_fu_658_p2, "i_5_fu_658_p2"); sc_trace(mVcdFile, ap_sig_cseq_ST_st2_fsm_1, "ap_sig_cseq_ST_st2_fsm_1"); - sc_trace(mVcdFile, ap_sig_139, "ap_sig_139"); + sc_trace(mVcdFile, ap_sig_137, "ap_sig_137"); sc_trace(mVcdFile, kk_2_fu_678_p2, "kk_2_fu_678_p2"); sc_trace(mVcdFile, kk_2_reg_1138, "kk_2_reg_1138"); sc_trace(mVcdFile, ap_sig_cseq_ST_st3_fsm_2, "ap_sig_cseq_ST_st3_fsm_2"); - sc_trace(mVcdFile, ap_sig_148, "ap_sig_148"); + sc_trace(mVcdFile, ap_sig_146, "ap_sig_146"); sc_trace(mVcdFile, tmp_3_fu_708_p2, "tmp_3_fu_708_p2"); sc_trace(mVcdFile, tmp_3_reg_1143, "tmp_3_reg_1143"); sc_trace(mVcdFile, exitcond1_fu_672_p2, "exitcond1_fu_672_p2"); sc_trace(mVcdFile, i_6_fu_719_p2, "i_6_fu_719_p2"); sc_trace(mVcdFile, ap_sig_cseq_ST_st4_fsm_3, "ap_sig_cseq_ST_st4_fsm_3"); - sc_trace(mVcdFile, ap_sig_163, "ap_sig_163"); + sc_trace(mVcdFile, ap_sig_161, "ap_sig_161"); sc_trace(mVcdFile, i_7_fu_741_p2, "i_7_fu_741_p2"); sc_trace(mVcdFile, ap_sig_cseq_ST_st6_fsm_5, "ap_sig_cseq_ST_st6_fsm_5"); - sc_trace(mVcdFile, ap_sig_172, "ap_sig_172"); + sc_trace(mVcdFile, ap_sig_170, "ap_sig_170"); sc_trace(mVcdFile, tmp_5_fu_759_p2, "tmp_5_fu_759_p2"); sc_trace(mVcdFile, tmp_5_reg_1170, "tmp_5_reg_1170"); sc_trace(mVcdFile, ap_sig_cseq_ST_st7_fsm_6, "ap_sig_cseq_ST_st7_fsm_6"); - sc_trace(mVcdFile, ap_sig_181, "ap_sig_181"); + sc_trace(mVcdFile, ap_sig_179, "ap_sig_179"); sc_trace(mVcdFile, i_9_fu_770_p2, "i_9_fu_770_p2"); sc_trace(mVcdFile, i_9_reg_1178, "i_9_reg_1178"); sc_trace(mVcdFile, ap_sig_cseq_ST_st8_fsm_7, "ap_sig_cseq_ST_st8_fsm_7"); - sc_trace(mVcdFile, ap_sig_190, "ap_sig_190"); + sc_trace(mVcdFile, ap_sig_188, "ap_sig_188"); sc_trace(mVcdFile, tmp_15_fu_776_p1, "tmp_15_fu_776_p1"); sc_trace(mVcdFile, tmp_15_reg_1186, "tmp_15_reg_1186"); sc_trace(mVcdFile, exitcond7_fu_765_p2, "exitcond7_fu_765_p2"); @@ -1074,22 +1060,22 @@ l2_trigger::l2_trigger(sc_module_name name) : sc_module(name), mVcdFile(0) { sc_trace(mVcdFile, sum_overP1_addr_reg_1236, "sum_overP1_addr_reg_1236"); sc_trace(mVcdFile, sum_overP2_addr_reg_1241, "sum_overP2_addr_reg_1241"); sc_trace(mVcdFile, ap_sig_cseq_ST_st10_fsm_9, "ap_sig_cseq_ST_st10_fsm_9"); - sc_trace(mVcdFile, ap_sig_227, "ap_sig_227"); + sc_trace(mVcdFile, ap_sig_225, "ap_sig_225"); sc_trace(mVcdFile, tmp_22_fu_822_p3, "tmp_22_fu_822_p3"); sc_trace(mVcdFile, kk_3_fu_950_p2, "kk_3_fu_950_p2"); sc_trace(mVcdFile, ap_sig_cseq_ST_st11_fsm_10, "ap_sig_cseq_ST_st11_fsm_10"); - sc_trace(mVcdFile, ap_sig_245, "ap_sig_245"); + sc_trace(mVcdFile, ap_sig_243, "ap_sig_243"); sc_trace(mVcdFile, tmp_24_fu_962_p2, "tmp_24_fu_962_p2"); sc_trace(mVcdFile, tmp_24_reg_1269, "tmp_24_reg_1269"); sc_trace(mVcdFile, ap_sig_cseq_ST_st12_fsm_11, "ap_sig_cseq_ST_st12_fsm_11"); - sc_trace(mVcdFile, ap_sig_254, "ap_sig_254"); + sc_trace(mVcdFile, ap_sig_252, "ap_sig_252"); sc_trace(mVcdFile, tmp_25_fu_968_p2, "tmp_25_fu_968_p2"); sc_trace(mVcdFile, grp_fu_633_p2, "grp_fu_633_p2"); sc_trace(mVcdFile, tmp_36_reg_1282, "tmp_36_reg_1282"); sc_trace(mVcdFile, i_8_fu_1021_p2, "i_8_fu_1021_p2"); sc_trace(mVcdFile, i_8_reg_1296, "i_8_reg_1296"); - sc_trace(mVcdFile, ap_sig_cseq_ST_st18_fsm_17, "ap_sig_cseq_ST_st18_fsm_17"); - sc_trace(mVcdFile, ap_sig_270, "ap_sig_270"); + sc_trace(mVcdFile, ap_sig_cseq_ST_st16_fsm_15, "ap_sig_cseq_ST_st16_fsm_15"); + sc_trace(mVcdFile, ap_sig_268, "ap_sig_268"); sc_trace(mVcdFile, exitcond6_fu_1016_p2, "exitcond6_fu_1016_p2"); sc_trace(mVcdFile, thresh1_addr_1_reg_1311, "thresh1_addr_1_reg_1311"); sc_trace(mVcdFile, thresh2_addr_1_reg_1316, "thresh2_addr_1_reg_1316"); @@ -1098,14 +1084,14 @@ l2_trigger::l2_trigger(sc_module_name name) : sc_module(name), mVcdFile(0) { sc_trace(mVcdFile, tmp_11_reg_1326, "tmp_11_reg_1326"); sc_trace(mVcdFile, tmp_12_fu_1086_p2, "tmp_12_fu_1086_p2"); sc_trace(mVcdFile, tmp_12_reg_1331, "tmp_12_reg_1331"); - sc_trace(mVcdFile, ap_sig_cseq_ST_st20_fsm_19, "ap_sig_cseq_ST_st20_fsm_19"); - sc_trace(mVcdFile, ap_sig_298, "ap_sig_298"); + sc_trace(mVcdFile, ap_sig_cseq_ST_st18_fsm_17, "ap_sig_cseq_ST_st18_fsm_17"); + sc_trace(mVcdFile, ap_sig_296, "ap_sig_296"); sc_trace(mVcdFile, tmp_13_fu_1091_p2, "tmp_13_fu_1091_p2"); sc_trace(mVcdFile, tmp_13_reg_1337, "tmp_13_reg_1337"); sc_trace(mVcdFile, tmp_14_fu_1096_p2, "tmp_14_fu_1096_p2"); sc_trace(mVcdFile, tmp_14_reg_1343, "tmp_14_reg_1343"); - sc_trace(mVcdFile, ap_sig_cseq_ST_st21_fsm_20, "ap_sig_cseq_ST_st21_fsm_20"); - sc_trace(mVcdFile, ap_sig_309, "ap_sig_309"); + sc_trace(mVcdFile, ap_sig_cseq_ST_st19_fsm_18, "ap_sig_cseq_ST_st19_fsm_18"); + sc_trace(mVcdFile, ap_sig_307, "ap_sig_307"); sc_trace(mVcdFile, sum_overP1_address0, "sum_overP1_address0"); sc_trace(mVcdFile, sum_overP1_ce0, "sum_overP1_ce0"); sc_trace(mVcdFile, sum_overP1_we0, "sum_overP1_we0"); @@ -1154,35 +1140,31 @@ l2_trigger::l2_trigger(sc_module_name name) : sc_module(name), mVcdFile(0) { sc_trace(mVcdFile, i_2_reg_535, "i_2_reg_535"); sc_trace(mVcdFile, exitcond8_fu_736_p2, "exitcond8_fu_736_p2"); sc_trace(mVcdFile, ap_sig_cseq_ST_st5_fsm_4, "ap_sig_cseq_ST_st5_fsm_4"); - sc_trace(mVcdFile, ap_sig_413, "ap_sig_413"); + sc_trace(mVcdFile, ap_sig_411, "ap_sig_411"); sc_trace(mVcdFile, tmp_nbreadreq_fu_226_p9, "tmp_nbreadreq_fu_226_p9"); sc_trace(mVcdFile, k_reg_546, "k_reg_546"); sc_trace(mVcdFile, itrig_reg_557, "itrig_reg_557"); sc_trace(mVcdFile, i_3_reg_569, "i_3_reg_569"); sc_trace(mVcdFile, exitcond_fu_753_p2, "exitcond_fu_753_p2"); - sc_trace(mVcdFile, ap_sig_cseq_ST_st15_fsm_14, "ap_sig_cseq_ST_st15_fsm_14"); - sc_trace(mVcdFile, ap_sig_439, "ap_sig_439"); + sc_trace(mVcdFile, ap_sig_cseq_ST_st14_fsm_13, "ap_sig_cseq_ST_st14_fsm_13"); + sc_trace(mVcdFile, ap_sig_437, "ap_sig_437"); sc_trace(mVcdFile, ap_sig_cseq_ST_st13_fsm_12, "ap_sig_cseq_ST_st13_fsm_12"); - sc_trace(mVcdFile, ap_sig_446, "ap_sig_446"); + sc_trace(mVcdFile, ap_sig_444, "ap_sig_444"); sc_trace(mVcdFile, or_cond_fu_979_p2, "or_cond_fu_979_p2"); - sc_trace(mVcdFile, ap_sig_cseq_ST_st17_fsm_16, "ap_sig_cseq_ST_st17_fsm_16"); - sc_trace(mVcdFile, ap_sig_457, "ap_sig_457"); + sc_trace(mVcdFile, ap_sig_cseq_ST_st15_fsm_14, "ap_sig_cseq_ST_st15_fsm_14"); + sc_trace(mVcdFile, ap_sig_455, "ap_sig_455"); sc_trace(mVcdFile, itrig_1_reg_587, "itrig_1_reg_587"); sc_trace(mVcdFile, kk_1_reg_610, "kk_1_reg_610"); sc_trace(mVcdFile, i_4_reg_622, "i_4_reg_622"); - sc_trace(mVcdFile, ap_sig_cseq_ST_st22_fsm_21, "ap_sig_cseq_ST_st22_fsm_21"); - sc_trace(mVcdFile, ap_sig_478, "ap_sig_478"); + sc_trace(mVcdFile, ap_sig_cseq_ST_st20_fsm_19, "ap_sig_cseq_ST_st20_fsm_19"); + sc_trace(mVcdFile, ap_sig_476, "ap_sig_476"); sc_trace(mVcdFile, tmp_4_fu_664_p1, "tmp_4_fu_664_p1"); sc_trace(mVcdFile, tmp_18_cast_fu_730_p1, "tmp_18_cast_fu_730_p1"); sc_trace(mVcdFile, tmp_7_fu_747_p1, "tmp_7_fu_747_p1"); sc_trace(mVcdFile, tmp_45_cast_fu_866_p1, "tmp_45_cast_fu_866_p1"); sc_trace(mVcdFile, tmp_49_cast_fu_926_p1, "tmp_49_cast_fu_926_p1"); sc_trace(mVcdFile, tmp_9_fu_1027_p1, "tmp_9_fu_1027_p1"); - sc_trace(mVcdFile, ap_sig_cseq_ST_st14_fsm_13, "ap_sig_cseq_ST_st14_fsm_13"); - sc_trace(mVcdFile, ap_sig_511, "ap_sig_511"); sc_trace(mVcdFile, tmp_40_cast_fu_998_p1, "tmp_40_cast_fu_998_p1"); - sc_trace(mVcdFile, ap_sig_cseq_ST_st16_fsm_15, "ap_sig_cseq_ST_st16_fsm_15"); - sc_trace(mVcdFile, ap_sig_520, "ap_sig_520"); sc_trace(mVcdFile, tmp_38_cast_fu_1011_p1, "tmp_38_cast_fu_1011_p1"); sc_trace(mVcdFile, ap_reg_ioackin_out_stream_TREADY, "ap_reg_ioackin_out_stream_TREADY"); sc_trace(mVcdFile, tmp_18_fu_804_p2, "tmp_18_fu_804_p2"); @@ -1265,10 +1247,10 @@ void l2_trigger::thread_ap_clk_no_reset_() { if ( ap_rst_n_inv.read() == ap_const_logic_1) { ap_reg_ioackin_out_stream_TREADY = ap_const_logic_0; } else { - if (((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st19_fsm_18.read()) && + if (((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st17_fsm_16.read()) && !esl_seteq<1,1,1>(ap_const_logic_0, ap_sig_ioackin_out_stream_TREADY.read())))) { ap_reg_ioackin_out_stream_TREADY = ap_const_logic_0; - } else if (((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st19_fsm_18.read()) && + } else if (((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st17_fsm_16.read()) && esl_seteq<1,1,1>(ap_const_logic_1, out_stream_TREADY.read())))) { ap_reg_ioackin_out_stream_TREADY = ap_const_logic_1; } @@ -1287,10 +1269,10 @@ void l2_trigger::thread_ap_clk_no_reset_() { esl_seteq<1,1,1>(ap_const_lv1_0, exitcond8_fu_736_p2.read()))) { i_2_reg_535 = i_7_fu_741_p2.read(); } - if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st15_fsm_14.read()) || + if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st14_fsm_13.read()) || (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st13_fsm_12.read()) && esl_seteq<1,1,1>(ap_const_lv1_0, or_cond_fu_979_p2.read())) || - esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st17_fsm_16.read()) || + esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st15_fsm_14.read()) || (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st12_fsm_11.read()) && esl_seteq<1,1,1>(ap_const_lv1_0, grp_fu_633_p2.read()) && !esl_seteq<1,1,1>(ap_const_lv1_0, tmp_25_fu_968_p2.read())))) { @@ -1302,7 +1284,7 @@ void l2_trigger::thread_ap_clk_no_reset_() { if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st7_fsm_6.read()) && !esl_seteq<1,1,1>(ap_const_lv1_0, exitcond_fu_753_p2.read()))) { i_4_reg_622 = ap_const_lv15_0; - } else if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st22_fsm_21.read())) { + } else if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st20_fsm_19.read())) { i_4_reg_622 = i_8_reg_1296.read(); } if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st2_fsm_1.read()) && @@ -1318,8 +1300,8 @@ void l2_trigger::thread_ap_clk_no_reset_() { esl_seteq<1,1,1>(ap_const_lv1_0, grp_fu_633_p2.read()) && !esl_seteq<1,1,1>(ap_const_lv1_0, tmp_25_fu_968_p2.read())))) { itrig_1_reg_587 = itrig_1_reg_587.read(); - } else if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st15_fsm_14.read()) || - esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st17_fsm_16.read()))) { + } else if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st14_fsm_13.read()) || + esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st15_fsm_14.read()))) { itrig_1_reg_587 = ap_const_lv32_1; } else if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st7_fsm_6.read()) && esl_seteq<1,1,1>(ap_const_lv1_0, exitcond_fu_753_p2.read()))) { @@ -1367,7 +1349,7 @@ void l2_trigger::thread_ap_clk_no_reset_() { tmp_17_reg_1226 = tmp_17_fu_800_p1.read(); tmp_19_reg_1231 = tmp_19_fu_811_p1.read(); } - if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st18_fsm_17.read())) { + if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st16_fsm_15.read())) { i_8_reg_1296 = i_8_fu_1021_p2.read(); } if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st8_fsm_7.read())) { @@ -1381,19 +1363,19 @@ void l2_trigger::thread_ap_clk_no_reset_() { sum_pix2_addr_3_reg_1201 = (sc_lv<11>) (tmp_15_fu_776_p1.read()); tmp_15_reg_1186 = tmp_15_fu_776_p1.read(); } - if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st18_fsm_17.read()) && esl_seteq<1,1,1>(ap_const_lv1_0, exitcond6_fu_1016_p2.read()))) { + if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st16_fsm_15.read()) && esl_seteq<1,1,1>(ap_const_lv1_0, exitcond6_fu_1016_p2.read()))) { thresh1_addr_1_reg_1311 = (sc_lv<11>) (tmp_9_fu_1027_p1.read()); thresh2_addr_1_reg_1316 = (sc_lv<11>) (tmp_9_fu_1027_p1.read()); } - if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st19_fsm_18.read()) && !esl_seteq<1,1,1>(ap_const_logic_0, ap_sig_ioackin_out_stream_TREADY.read()))) { + if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st17_fsm_16.read()) && !esl_seteq<1,1,1>(ap_const_logic_0, ap_sig_ioackin_out_stream_TREADY.read()))) { tmp_10_reg_1321 = sum_pix1_q0.read().range(31, 7); tmp_11_reg_1326 = sum_pix2_q0.read().range(31, 7); } - if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st20_fsm_19.read())) { + if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st18_fsm_17.read())) { tmp_12_reg_1331 = tmp_12_fu_1086_p2.read(); tmp_13_reg_1337 = tmp_13_fu_1091_p2.read(); } - if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st21_fsm_20.read())) { + if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st19_fsm_18.read())) { tmp_14_reg_1343 = tmp_14_fu_1096_p2.read(); } if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st12_fsm_11.read())) { @@ -1441,96 +1423,88 @@ void l2_trigger::thread_ap_rst_n_inv() { ap_rst_n_inv = (sc_logic) (~ap_rst_n.read()); } -void l2_trigger::thread_ap_sig_139() { - ap_sig_139 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(1, 1)); -} - -void l2_trigger::thread_ap_sig_148() { - ap_sig_148 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(2, 2)); -} - -void l2_trigger::thread_ap_sig_163() { - ap_sig_163 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(3, 3)); +void l2_trigger::thread_ap_sig_137() { + ap_sig_137 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(1, 1)); } -void l2_trigger::thread_ap_sig_172() { - ap_sig_172 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(5, 5)); +void l2_trigger::thread_ap_sig_146() { + ap_sig_146 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(2, 2)); } -void l2_trigger::thread_ap_sig_181() { - ap_sig_181 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(6, 6)); +void l2_trigger::thread_ap_sig_161() { + ap_sig_161 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(3, 3)); } -void l2_trigger::thread_ap_sig_190() { - ap_sig_190 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(7, 7)); +void l2_trigger::thread_ap_sig_170() { + ap_sig_170 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(5, 5)); } -void l2_trigger::thread_ap_sig_227() { - ap_sig_227 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(9, 9)); +void l2_trigger::thread_ap_sig_179() { + ap_sig_179 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(6, 6)); } -void l2_trigger::thread_ap_sig_245() { - ap_sig_245 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(10, 10)); +void l2_trigger::thread_ap_sig_188() { + ap_sig_188 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(7, 7)); } -void l2_trigger::thread_ap_sig_254() { - ap_sig_254 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(11, 11)); +void l2_trigger::thread_ap_sig_225() { + ap_sig_225 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(9, 9)); } -void l2_trigger::thread_ap_sig_270() { - ap_sig_270 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(17, 17)); +void l2_trigger::thread_ap_sig_243() { + ap_sig_243 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(10, 10)); } -void l2_trigger::thread_ap_sig_298() { - ap_sig_298 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(19, 19)); +void l2_trigger::thread_ap_sig_252() { + ap_sig_252 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(11, 11)); } -void l2_trigger::thread_ap_sig_309() { - ap_sig_309 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(20, 20)); +void l2_trigger::thread_ap_sig_268() { + ap_sig_268 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(15, 15)); } -void l2_trigger::thread_ap_sig_39() { - ap_sig_39 = esl_seteq<1,1,1>(ap_CS_fsm.read().range(0, 0), ap_const_lv1_1); +void l2_trigger::thread_ap_sig_296() { + ap_sig_296 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(17, 17)); } -void l2_trigger::thread_ap_sig_413() { - ap_sig_413 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(4, 4)); +void l2_trigger::thread_ap_sig_307() { + ap_sig_307 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(18, 18)); } -void l2_trigger::thread_ap_sig_439() { - ap_sig_439 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(14, 14)); +void l2_trigger::thread_ap_sig_37() { + ap_sig_37 = esl_seteq<1,1,1>(ap_CS_fsm.read().range(0, 0), ap_const_lv1_1); } -void l2_trigger::thread_ap_sig_446() { - ap_sig_446 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(12, 12)); +void l2_trigger::thread_ap_sig_411() { + ap_sig_411 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(4, 4)); } -void l2_trigger::thread_ap_sig_457() { - ap_sig_457 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(16, 16)); +void l2_trigger::thread_ap_sig_437() { + ap_sig_437 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(13, 13)); } -void l2_trigger::thread_ap_sig_478() { - ap_sig_478 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(21, 21)); +void l2_trigger::thread_ap_sig_444() { + ap_sig_444 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(12, 12)); } -void l2_trigger::thread_ap_sig_511() { - ap_sig_511 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(13, 13)); +void l2_trigger::thread_ap_sig_455() { + ap_sig_455 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(14, 14)); } -void l2_trigger::thread_ap_sig_520() { - ap_sig_520 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(15, 15)); +void l2_trigger::thread_ap_sig_476() { + ap_sig_476 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(19, 19)); } -void l2_trigger::thread_ap_sig_77() { - ap_sig_77 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(8, 8)); +void l2_trigger::thread_ap_sig_75() { + ap_sig_75 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(8, 8)); } -void l2_trigger::thread_ap_sig_85() { - ap_sig_85 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(18, 18)); +void l2_trigger::thread_ap_sig_83() { + ap_sig_83 = esl_seteq<1,1,1>(ap_const_lv1_1, ap_CS_fsm.read().range(16, 16)); } void l2_trigger::thread_ap_sig_cseq_ST_st10_fsm_9() { - if (ap_sig_227.read()) { + if (ap_sig_225.read()) { ap_sig_cseq_ST_st10_fsm_9 = ap_const_logic_1; } else { ap_sig_cseq_ST_st10_fsm_9 = ap_const_logic_0; @@ -1538,7 +1512,7 @@ void l2_trigger::thread_ap_sig_cseq_ST_st10_fsm_9() { } void l2_trigger::thread_ap_sig_cseq_ST_st11_fsm_10() { - if (ap_sig_245.read()) { + if (ap_sig_243.read()) { ap_sig_cseq_ST_st11_fsm_10 = ap_const_logic_1; } else { ap_sig_cseq_ST_st11_fsm_10 = ap_const_logic_0; @@ -1546,7 +1520,7 @@ void l2_trigger::thread_ap_sig_cseq_ST_st11_fsm_10() { } void l2_trigger::thread_ap_sig_cseq_ST_st12_fsm_11() { - if (ap_sig_254.read()) { + if (ap_sig_252.read()) { ap_sig_cseq_ST_st12_fsm_11 = ap_const_logic_1; } else { ap_sig_cseq_ST_st12_fsm_11 = ap_const_logic_0; @@ -1554,7 +1528,7 @@ void l2_trigger::thread_ap_sig_cseq_ST_st12_fsm_11() { } void l2_trigger::thread_ap_sig_cseq_ST_st13_fsm_12() { - if (ap_sig_446.read()) { + if (ap_sig_444.read()) { ap_sig_cseq_ST_st13_fsm_12 = ap_const_logic_1; } else { ap_sig_cseq_ST_st13_fsm_12 = ap_const_logic_0; @@ -1562,7 +1536,7 @@ void l2_trigger::thread_ap_sig_cseq_ST_st13_fsm_12() { } void l2_trigger::thread_ap_sig_cseq_ST_st14_fsm_13() { - if (ap_sig_511.read()) { + if (ap_sig_437.read()) { ap_sig_cseq_ST_st14_fsm_13 = ap_const_logic_1; } else { ap_sig_cseq_ST_st14_fsm_13 = ap_const_logic_0; @@ -1570,7 +1544,7 @@ void l2_trigger::thread_ap_sig_cseq_ST_st14_fsm_13() { } void l2_trigger::thread_ap_sig_cseq_ST_st15_fsm_14() { - if (ap_sig_439.read()) { + if (ap_sig_455.read()) { ap_sig_cseq_ST_st15_fsm_14 = ap_const_logic_1; } else { ap_sig_cseq_ST_st15_fsm_14 = ap_const_logic_0; @@ -1578,7 +1552,7 @@ void l2_trigger::thread_ap_sig_cseq_ST_st15_fsm_14() { } void l2_trigger::thread_ap_sig_cseq_ST_st16_fsm_15() { - if (ap_sig_520.read()) { + if (ap_sig_268.read()) { ap_sig_cseq_ST_st16_fsm_15 = ap_const_logic_1; } else { ap_sig_cseq_ST_st16_fsm_15 = ap_const_logic_0; @@ -1586,7 +1560,7 @@ void l2_trigger::thread_ap_sig_cseq_ST_st16_fsm_15() { } void l2_trigger::thread_ap_sig_cseq_ST_st17_fsm_16() { - if (ap_sig_457.read()) { + if (ap_sig_83.read()) { ap_sig_cseq_ST_st17_fsm_16 = ap_const_logic_1; } else { ap_sig_cseq_ST_st17_fsm_16 = ap_const_logic_0; @@ -1594,7 +1568,7 @@ void l2_trigger::thread_ap_sig_cseq_ST_st17_fsm_16() { } void l2_trigger::thread_ap_sig_cseq_ST_st18_fsm_17() { - if (ap_sig_270.read()) { + if (ap_sig_296.read()) { ap_sig_cseq_ST_st18_fsm_17 = ap_const_logic_1; } else { ap_sig_cseq_ST_st18_fsm_17 = ap_const_logic_0; @@ -1602,7 +1576,7 @@ void l2_trigger::thread_ap_sig_cseq_ST_st18_fsm_17() { } void l2_trigger::thread_ap_sig_cseq_ST_st19_fsm_18() { - if (ap_sig_85.read()) { + if (ap_sig_307.read()) { ap_sig_cseq_ST_st19_fsm_18 = ap_const_logic_1; } else { ap_sig_cseq_ST_st19_fsm_18 = ap_const_logic_0; @@ -1610,7 +1584,7 @@ void l2_trigger::thread_ap_sig_cseq_ST_st19_fsm_18() { } void l2_trigger::thread_ap_sig_cseq_ST_st1_fsm_0() { - if (ap_sig_39.read()) { + if (ap_sig_37.read()) { ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1; } else { ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0; @@ -1618,31 +1592,15 @@ void l2_trigger::thread_ap_sig_cseq_ST_st1_fsm_0() { } void l2_trigger::thread_ap_sig_cseq_ST_st20_fsm_19() { - if (ap_sig_298.read()) { + if (ap_sig_476.read()) { ap_sig_cseq_ST_st20_fsm_19 = ap_const_logic_1; } else { ap_sig_cseq_ST_st20_fsm_19 = ap_const_logic_0; } } -void l2_trigger::thread_ap_sig_cseq_ST_st21_fsm_20() { - if (ap_sig_309.read()) { - ap_sig_cseq_ST_st21_fsm_20 = ap_const_logic_1; - } else { - ap_sig_cseq_ST_st21_fsm_20 = ap_const_logic_0; - } -} - -void l2_trigger::thread_ap_sig_cseq_ST_st22_fsm_21() { - if (ap_sig_478.read()) { - ap_sig_cseq_ST_st22_fsm_21 = ap_const_logic_1; - } else { - ap_sig_cseq_ST_st22_fsm_21 = ap_const_logic_0; - } -} - void l2_trigger::thread_ap_sig_cseq_ST_st2_fsm_1() { - if (ap_sig_139.read()) { + if (ap_sig_137.read()) { ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1; } else { ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0; @@ -1650,7 +1608,7 @@ void l2_trigger::thread_ap_sig_cseq_ST_st2_fsm_1() { } void l2_trigger::thread_ap_sig_cseq_ST_st3_fsm_2() { - if (ap_sig_148.read()) { + if (ap_sig_146.read()) { ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_1; } else { ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_0; @@ -1658,7 +1616,7 @@ void l2_trigger::thread_ap_sig_cseq_ST_st3_fsm_2() { } void l2_trigger::thread_ap_sig_cseq_ST_st4_fsm_3() { - if (ap_sig_163.read()) { + if (ap_sig_161.read()) { ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_1; } else { ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_0; @@ -1666,7 +1624,7 @@ void l2_trigger::thread_ap_sig_cseq_ST_st4_fsm_3() { } void l2_trigger::thread_ap_sig_cseq_ST_st5_fsm_4() { - if (ap_sig_413.read()) { + if (ap_sig_411.read()) { ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_1; } else { ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_0; @@ -1674,7 +1632,7 @@ void l2_trigger::thread_ap_sig_cseq_ST_st5_fsm_4() { } void l2_trigger::thread_ap_sig_cseq_ST_st6_fsm_5() { - if (ap_sig_172.read()) { + if (ap_sig_170.read()) { ap_sig_cseq_ST_st6_fsm_5 = ap_const_logic_1; } else { ap_sig_cseq_ST_st6_fsm_5 = ap_const_logic_0; @@ -1682,7 +1640,7 @@ void l2_trigger::thread_ap_sig_cseq_ST_st6_fsm_5() { } void l2_trigger::thread_ap_sig_cseq_ST_st7_fsm_6() { - if (ap_sig_181.read()) { + if (ap_sig_179.read()) { ap_sig_cseq_ST_st7_fsm_6 = ap_const_logic_1; } else { ap_sig_cseq_ST_st7_fsm_6 = ap_const_logic_0; @@ -1690,7 +1648,7 @@ void l2_trigger::thread_ap_sig_cseq_ST_st7_fsm_6() { } void l2_trigger::thread_ap_sig_cseq_ST_st8_fsm_7() { - if (ap_sig_190.read()) { + if (ap_sig_188.read()) { ap_sig_cseq_ST_st8_fsm_7 = ap_const_logic_1; } else { ap_sig_cseq_ST_st8_fsm_7 = ap_const_logic_0; @@ -1698,7 +1656,7 @@ void l2_trigger::thread_ap_sig_cseq_ST_st8_fsm_7() { } void l2_trigger::thread_ap_sig_cseq_ST_st9_fsm_8() { - if (ap_sig_77.read()) { + if (ap_sig_75.read()) { ap_sig_cseq_ST_st9_fsm_8 = ap_const_logic_1; } else { ap_sig_cseq_ST_st9_fsm_8 = ap_const_logic_0; @@ -1915,7 +1873,7 @@ void l2_trigger::thread_out_stream_TDATA() { } void l2_trigger::thread_out_stream_TDATA_blk_n() { - if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st19_fsm_18.read())) { + if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st17_fsm_16.read())) { out_stream_TDATA_blk_n = out_stream_TREADY.read(); } else { out_stream_TDATA_blk_n = ap_const_logic_1; @@ -1947,7 +1905,7 @@ void l2_trigger::thread_out_stream_TUSER() { } void l2_trigger::thread_out_stream_TVALID() { - if (((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st19_fsm_18.read()) && + if (((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st17_fsm_16.read()) && esl_seteq<1,1,1>(ap_const_logic_0, ap_reg_ioackin_out_stream_TREADY.read())))) { out_stream_TVALID = ap_const_logic_1; } else { @@ -2096,7 +2054,7 @@ void l2_trigger::thread_sum_pix1_address0() { sum_pix1_address0 = (sc_lv<11>) (tmp_7_fu_747_p1.read()); } else if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st2_fsm_1.read())) { sum_pix1_address0 = (sc_lv<11>) (tmp_4_fu_664_p1.read()); - } else if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st18_fsm_17.read())) { + } else if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st16_fsm_15.read())) { sum_pix1_address0 = (sc_lv<11>) (tmp_9_fu_1027_p1.read()); } else if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st8_fsm_7.read())) { sum_pix1_address0 = (sc_lv<11>) (tmp_15_fu_776_p1.read()); @@ -2111,7 +2069,7 @@ void l2_trigger::thread_sum_pix1_ce0() { esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st8_fsm_7.read()) || (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st9_fsm_8.read()) && !esl_seteq<1,1,1>(in_stream_TVALID.read(), ap_const_logic_0)) || - esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st18_fsm_17.read()))) { + esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st16_fsm_15.read()))) { sum_pix1_ce0 = ap_const_logic_1; } else { sum_pix1_ce0 = ap_const_logic_0; @@ -2149,7 +2107,7 @@ void l2_trigger::thread_sum_pix2_address0() { sum_pix2_address0 = (sc_lv<11>) (tmp_7_fu_747_p1.read()); } else if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st2_fsm_1.read())) { sum_pix2_address0 = (sc_lv<11>) (tmp_4_fu_664_p1.read()); - } else if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st18_fsm_17.read())) { + } else if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st16_fsm_15.read())) { sum_pix2_address0 = (sc_lv<11>) (tmp_9_fu_1027_p1.read()); } else if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st8_fsm_7.read())) { sum_pix2_address0 = (sc_lv<11>) (tmp_15_fu_776_p1.read()); @@ -2164,7 +2122,7 @@ void l2_trigger::thread_sum_pix2_ce0() { esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st8_fsm_7.read()) || (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st9_fsm_8.read()) && !esl_seteq<1,1,1>(in_stream_TVALID.read(), ap_const_logic_0)) || - esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st18_fsm_17.read()))) { + esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st16_fsm_15.read()))) { sum_pix2_ce0 = ap_const_logic_1; } else { sum_pix2_ce0 = ap_const_logic_0; @@ -2204,8 +2162,8 @@ void l2_trigger::thread_sum_pixP2_fu_1075_p3() { } void l2_trigger::thread_thresh1_address0() { - if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st21_fsm_20.read()) || - esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st22_fsm_21.read()))) { + if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st19_fsm_18.read()) || + esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st20_fsm_19.read()))) { thresh1_address0 = thresh1_addr_1_reg_1311.read(); } else if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st2_fsm_1.read())) { thresh1_address0 = (sc_lv<11>) (tmp_4_fu_664_p1.read()); @@ -2219,8 +2177,8 @@ void l2_trigger::thread_thresh1_address0() { void l2_trigger::thread_thresh1_ce0() { if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st2_fsm_1.read()) || esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st10_fsm_9.read()) || - esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st21_fsm_20.read()) || - esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st22_fsm_21.read()))) { + esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st19_fsm_18.read()) || + esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st20_fsm_19.read()))) { thresh1_ce0 = ap_const_logic_1; } else { thresh1_ce0 = ap_const_logic_0; @@ -2228,9 +2186,9 @@ void l2_trigger::thread_thresh1_ce0() { } void l2_trigger::thread_thresh1_d0() { - if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st22_fsm_21.read())) { + if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st20_fsm_19.read())) { thresh1_d0 = LOW_THRESH_read_reg_1104.read(); - } else if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st21_fsm_20.read())) { + } else if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st19_fsm_18.read())) { thresh1_d0 = tmp_12_reg_1331.read(); } else if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st2_fsm_1.read())) { thresh1_d0 = ap_const_lv32_639C; @@ -2240,10 +2198,10 @@ void l2_trigger::thread_thresh1_d0() { } void l2_trigger::thread_thresh1_we0() { - if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st21_fsm_20.read()) || + if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st19_fsm_18.read()) || (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st2_fsm_1.read()) && esl_seteq<1,1,1>(ap_const_lv1_0, exitcond2_fu_653_p2.read())) || - (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st22_fsm_21.read()) && + (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st20_fsm_19.read()) && !esl_seteq<1,1,1>(ap_const_lv1_0, tmp_14_reg_1343.read())))) { thresh1_we0 = ap_const_logic_1; } else { @@ -2252,8 +2210,8 @@ void l2_trigger::thread_thresh1_we0() { } void l2_trigger::thread_thresh2_address0() { - if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st21_fsm_20.read()) || - esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st22_fsm_21.read()))) { + if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st19_fsm_18.read()) || + esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st20_fsm_19.read()))) { thresh2_address0 = thresh2_addr_1_reg_1316.read(); } else if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st2_fsm_1.read())) { thresh2_address0 = (sc_lv<11>) (tmp_4_fu_664_p1.read()); @@ -2267,8 +2225,8 @@ void l2_trigger::thread_thresh2_address0() { void l2_trigger::thread_thresh2_ce0() { if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st2_fsm_1.read()) || esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st12_fsm_11.read()) || - esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st21_fsm_20.read()) || - esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st22_fsm_21.read()))) { + esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st19_fsm_18.read()) || + esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st20_fsm_19.read()))) { thresh2_ce0 = ap_const_logic_1; } else { thresh2_ce0 = ap_const_logic_0; @@ -2276,9 +2234,9 @@ void l2_trigger::thread_thresh2_ce0() { } void l2_trigger::thread_thresh2_d0() { - if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st22_fsm_21.read())) { + if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st20_fsm_19.read())) { thresh2_d0 = LOW_THRESH_read_reg_1104.read(); - } else if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st21_fsm_20.read())) { + } else if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st19_fsm_18.read())) { thresh2_d0 = tmp_13_reg_1337.read(); } else if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st2_fsm_1.read())) { thresh2_d0 = ap_const_lv32_639C; @@ -2288,10 +2246,10 @@ void l2_trigger::thread_thresh2_d0() { } void l2_trigger::thread_thresh2_we0() { - if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st21_fsm_20.read()) || + if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st19_fsm_18.read()) || (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st2_fsm_1.read()) && esl_seteq<1,1,1>(ap_const_lv1_0, exitcond2_fu_653_p2.read())) || - (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st22_fsm_21.read()) && + (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st20_fsm_19.read()) && !esl_seteq<1,1,1>(ap_const_lv1_0, tmp_21_fu_1100_p2.read())))) { thresh2_we0 = ap_const_logic_1; } else { @@ -2508,20 +2466,16 @@ void l2_trigger::thread_tmp_s_fu_696_p3() { } void l2_trigger::thread_trig_data() { - if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st17_fsm_16.read())) { - trig_data = tmp_38_cast_fu_1011_p1.read(); - } else if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st15_fsm_14.read())) { - trig_data = tmp_40_cast_fu_998_p1.read(); - } else if (((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st12_fsm_11.read()) && - !esl_seteq<1,1,1>(ap_const_lv1_0, tmp_25_fu_968_p2.read()) && - !esl_seteq<1,1,1>(ap_const_lv1_0, grp_fu_633_p2.read())) || - (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st13_fsm_12.read()) && - !esl_seteq<1,1,1>(ap_const_lv1_0, or_cond_fu_979_p2.read())))) { + if (((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st12_fsm_11.read()) && + !esl_seteq<1,1,1>(ap_const_lv1_0, tmp_25_fu_968_p2.read()) && + !esl_seteq<1,1,1>(ap_const_lv1_0, grp_fu_633_p2.read())) || + (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st13_fsm_12.read()) && + !esl_seteq<1,1,1>(ap_const_lv1_0, or_cond_fu_979_p2.read())))) { trig_data = ap_const_lv32_1; } else if (((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st1_fsm_0.read()) && !esl_seteq<1,1,1>(ap_start.read(), ap_const_logic_0)) || esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st14_fsm_13.read()) || - esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st16_fsm_15.read()))) { + esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st15_fsm_14.read()))) { trig_data = ap_const_lv32_0; } else { trig_data = (sc_lv<32>) ("XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"); @@ -2531,15 +2485,13 @@ void l2_trigger::thread_trig_data() { void l2_trigger::thread_trig_data_ap_vld() { if (((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st1_fsm_0.read()) && !esl_seteq<1,1,1>(ap_start.read(), ap_const_logic_0)) || + esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st14_fsm_13.read()) || esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st15_fsm_14.read()) || - esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st17_fsm_16.read()) || (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st12_fsm_11.read()) && !esl_seteq<1,1,1>(ap_const_lv1_0, tmp_25_fu_968_p2.read()) && !esl_seteq<1,1,1>(ap_const_lv1_0, grp_fu_633_p2.read())) || (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st13_fsm_12.read()) && - !esl_seteq<1,1,1>(ap_const_lv1_0, or_cond_fu_979_p2.read())) || - esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st14_fsm_13.read()) || - esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st16_fsm_15.read()))) { + !esl_seteq<1,1,1>(ap_const_lv1_0, or_cond_fu_979_p2.read())))) { trig_data_ap_vld = ap_const_logic_1; } else { trig_data_ap_vld = ap_const_logic_0; @@ -2547,12 +2499,25 @@ void l2_trigger::thread_trig_data_ap_vld() { } void l2_trigger::thread_trig_pixel() { - trig_pixel = ap_const_lv32_0; + if (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st15_fsm_14.read())) { + trig_pixel = tmp_38_cast_fu_1011_p1.read(); + } else if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st13_fsm_12.read()) && + !esl_seteq<1,1,1>(ap_const_lv1_0, or_cond_fu_979_p2.read()))) { + trig_pixel = tmp_40_cast_fu_998_p1.read(); + } else if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st1_fsm_0.read()) && + !esl_seteq<1,1,1>(ap_start.read(), ap_const_logic_0))) { + trig_pixel = ap_const_lv32_0; + } else { + trig_pixel = (sc_lv<32>) ("XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"); + } } void l2_trigger::thread_trig_pixel_ap_vld() { - if ((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st1_fsm_0.read()) && - !esl_seteq<1,1,1>(ap_start.read(), ap_const_logic_0))) { + if (((esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st1_fsm_0.read()) && + !esl_seteq<1,1,1>(ap_start.read(), ap_const_logic_0)) || + esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st15_fsm_14.read()) || + (esl_seteq<1,1,1>(ap_const_logic_1, ap_sig_cseq_ST_st13_fsm_12.read()) && + !esl_seteq<1,1,1>(ap_const_lv1_0, or_cond_fu_979_p2.read())))) { trig_pixel_ap_vld = ap_const_logic_1; } else { trig_pixel_ap_vld = ap_const_logic_0; @@ -2605,7 +2570,7 @@ void l2_trigger::thread_ap_NS_fsm() { break; case 64 : if (!esl_seteq<1,1,1>(ap_const_lv1_0, exitcond_fu_753_p2.read())) { - ap_NS_fsm = ap_ST_st18_fsm_17; + ap_NS_fsm = ap_ST_st16_fsm_15; } else { ap_NS_fsm = ap_ST_st8_fsm_7; } @@ -2636,7 +2601,7 @@ void l2_trigger::thread_ap_NS_fsm() { break; case 2048 : if ((!esl_seteq<1,1,1>(ap_const_lv1_0, tmp_25_fu_968_p2.read()) && !esl_seteq<1,1,1>(ap_const_lv1_0, grp_fu_633_p2.read()))) { - ap_NS_fsm = ap_ST_st16_fsm_15; + ap_NS_fsm = ap_ST_st15_fsm_14; } else if ((esl_seteq<1,1,1>(ap_const_lv1_0, grp_fu_633_p2.read()) && !esl_seteq<1,1,1>(ap_const_lv1_0, tmp_25_fu_968_p2.read()))) { ap_NS_fsm = ap_ST_st8_fsm_7; } else { @@ -2651,42 +2616,36 @@ void l2_trigger::thread_ap_NS_fsm() { } break; case 8192 : - ap_NS_fsm = ap_ST_st15_fsm_14; + ap_NS_fsm = ap_ST_st8_fsm_7; break; case 16384 : ap_NS_fsm = ap_ST_st8_fsm_7; break; case 32768 : - ap_NS_fsm = ap_ST_st17_fsm_16; - break; - case 65536 : - ap_NS_fsm = ap_ST_st8_fsm_7; - break; - case 131072 : if (esl_seteq<1,1,1>(ap_const_lv1_0, exitcond6_fu_1016_p2.read())) { - ap_NS_fsm = ap_ST_st19_fsm_18; + ap_NS_fsm = ap_ST_st17_fsm_16; } else { ap_NS_fsm = ap_ST_st5_fsm_4; } break; - case 262144 : + case 65536 : if (!esl_seteq<1,1,1>(ap_const_logic_0, ap_sig_ioackin_out_stream_TREADY.read())) { - ap_NS_fsm = ap_ST_st20_fsm_19; + ap_NS_fsm = ap_ST_st18_fsm_17; } else { - ap_NS_fsm = ap_ST_st19_fsm_18; + ap_NS_fsm = ap_ST_st17_fsm_16; } break; - case 524288 : - ap_NS_fsm = ap_ST_st21_fsm_20; + case 131072 : + ap_NS_fsm = ap_ST_st19_fsm_18; break; - case 1048576 : - ap_NS_fsm = ap_ST_st22_fsm_21; + case 262144 : + ap_NS_fsm = ap_ST_st20_fsm_19; break; - case 2097152 : - ap_NS_fsm = ap_ST_st18_fsm_17; + case 524288 : + ap_NS_fsm = ap_ST_st16_fsm_15; break; default : - ap_NS_fsm = (sc_lv<22>) ("XXXXXXXXXXXXXXXXXXXXXX"); + ap_NS_fsm = (sc_lv<20>) ("XXXXXXXXXXXXXXXXXXXX"); break; } } diff --git a/l2_trigger/solution1/syn/systemc/l2_trigger.h b/l2_trigger/solution1/syn/systemc/l2_trigger.h index e5a36e3..29dc058 100644 --- a/l2_trigger/solution1/syn/systemc/l2_trigger.h +++ b/l2_trigger/solution1/syn/systemc/l2_trigger.h @@ -89,47 +89,47 @@ struct l2_trigger : public sc_module { sc_signal< sc_logic > ap_start; sc_signal< sc_logic > ap_done; sc_signal< sc_logic > ap_idle; - sc_signal< sc_lv<22> > ap_CS_fsm; + sc_signal< sc_lv<20> > ap_CS_fsm; sc_signal< sc_logic > ap_sig_cseq_ST_st1_fsm_0; - sc_signal< bool > ap_sig_39; + sc_signal< bool > ap_sig_37; sc_signal< sc_logic > ap_ready; sc_signal< sc_lv<16> > n_pixels_in_bus; sc_signal< sc_lv<8> > N_BG; sc_signal< sc_lv<32> > LOW_THRESH; sc_signal< sc_logic > in_stream_TDATA_blk_n; sc_signal< sc_logic > ap_sig_cseq_ST_st9_fsm_8; - sc_signal< bool > ap_sig_77; + sc_signal< bool > ap_sig_75; sc_signal< sc_logic > out_stream_TDATA_blk_n; - sc_signal< sc_logic > ap_sig_cseq_ST_st19_fsm_18; - sc_signal< bool > ap_sig_85; + sc_signal< sc_logic > ap_sig_cseq_ST_st17_fsm_16; + sc_signal< bool > ap_sig_83; sc_signal< sc_lv<32> > LOW_THRESH_read_reg_1104; sc_signal< sc_lv<32> > tmp_1_fu_639_p1; sc_signal< sc_lv<32> > tmp_1_reg_1112; sc_signal< sc_lv<15> > tmp_2_reg_1118; sc_signal< sc_lv<15> > i_5_fu_658_p2; sc_signal< sc_logic > ap_sig_cseq_ST_st2_fsm_1; - sc_signal< bool > ap_sig_139; + sc_signal< bool > ap_sig_137; sc_signal< sc_lv<4> > kk_2_fu_678_p2; sc_signal< sc_lv<4> > kk_2_reg_1138; sc_signal< sc_logic > ap_sig_cseq_ST_st3_fsm_2; - sc_signal< bool > ap_sig_148; + sc_signal< bool > ap_sig_146; sc_signal< sc_lv<15> > tmp_3_fu_708_p2; sc_signal< sc_lv<15> > tmp_3_reg_1143; sc_signal< sc_lv<1> > exitcond1_fu_672_p2; sc_signal< sc_lv<15> > i_6_fu_719_p2; sc_signal< sc_logic > ap_sig_cseq_ST_st4_fsm_3; - sc_signal< bool > ap_sig_163; + sc_signal< bool > ap_sig_161; sc_signal< sc_lv<15> > i_7_fu_741_p2; sc_signal< sc_logic > ap_sig_cseq_ST_st6_fsm_5; - sc_signal< bool > ap_sig_172; + sc_signal< bool > ap_sig_170; sc_signal< sc_lv<8> > tmp_5_fu_759_p2; sc_signal< sc_lv<8> > tmp_5_reg_1170; sc_signal< sc_logic > ap_sig_cseq_ST_st7_fsm_6; - sc_signal< bool > ap_sig_181; + sc_signal< bool > ap_sig_179; sc_signal< sc_lv<15> > i_9_fu_770_p2; sc_signal< sc_lv<15> > i_9_reg_1178; sc_signal< sc_logic > ap_sig_cseq_ST_st8_fsm_7; - sc_signal< bool > ap_sig_190; + sc_signal< bool > ap_sig_188; sc_signal< sc_lv<64> > tmp_15_fu_776_p1; sc_signal< sc_lv<64> > tmp_15_reg_1186; sc_signal< sc_lv<1> > exitcond7_fu_765_p2; @@ -148,22 +148,22 @@ struct l2_trigger : public sc_module { sc_signal< sc_lv<11> > sum_overP1_addr_reg_1236; sc_signal< sc_lv<11> > sum_overP2_addr_reg_1241; sc_signal< sc_logic > ap_sig_cseq_ST_st10_fsm_9; - sc_signal< bool > ap_sig_227; + sc_signal< bool > ap_sig_225; sc_signal< sc_lv<1> > tmp_22_fu_822_p3; sc_signal< sc_lv<4> > kk_3_fu_950_p2; sc_signal< sc_logic > ap_sig_cseq_ST_st11_fsm_10; - sc_signal< bool > ap_sig_245; + sc_signal< bool > ap_sig_243; sc_signal< sc_lv<32> > tmp_24_fu_962_p2; sc_signal< sc_lv<32> > tmp_24_reg_1269; sc_signal< sc_logic > ap_sig_cseq_ST_st12_fsm_11; - sc_signal< bool > ap_sig_254; + sc_signal< bool > ap_sig_252; sc_signal< sc_lv<1> > tmp_25_fu_968_p2; sc_signal< sc_lv<1> > grp_fu_633_p2; sc_signal< sc_lv<1> > tmp_36_reg_1282; sc_signal< sc_lv<15> > i_8_fu_1021_p2; sc_signal< sc_lv<15> > i_8_reg_1296; - sc_signal< sc_logic > ap_sig_cseq_ST_st18_fsm_17; - sc_signal< bool > ap_sig_270; + sc_signal< sc_logic > ap_sig_cseq_ST_st16_fsm_15; + sc_signal< bool > ap_sig_268; sc_signal< sc_lv<1> > exitcond6_fu_1016_p2; sc_signal< sc_lv<11> > thresh1_addr_1_reg_1311; sc_signal< sc_lv<11> > thresh2_addr_1_reg_1316; @@ -172,14 +172,14 @@ struct l2_trigger : public sc_module { sc_signal< sc_lv<25> > tmp_11_reg_1326; sc_signal< sc_lv<32> > tmp_12_fu_1086_p2; sc_signal< sc_lv<32> > tmp_12_reg_1331; - sc_signal< sc_logic > ap_sig_cseq_ST_st20_fsm_19; - sc_signal< bool > ap_sig_298; + sc_signal< sc_logic > ap_sig_cseq_ST_st18_fsm_17; + sc_signal< bool > ap_sig_296; sc_signal< sc_lv<32> > tmp_13_fu_1091_p2; sc_signal< sc_lv<32> > tmp_13_reg_1337; sc_signal< sc_lv<1> > tmp_14_fu_1096_p2; sc_signal< sc_lv<1> > tmp_14_reg_1343; - sc_signal< sc_logic > ap_sig_cseq_ST_st21_fsm_20; - sc_signal< bool > ap_sig_309; + sc_signal< sc_logic > ap_sig_cseq_ST_st19_fsm_18; + sc_signal< bool > ap_sig_307; sc_signal< sc_lv<11> > sum_overP1_address0; sc_signal< sc_logic > sum_overP1_ce0; sc_signal< sc_logic > sum_overP1_we0; @@ -228,35 +228,31 @@ struct l2_trigger : public sc_module { sc_signal< sc_lv<15> > i_2_reg_535; sc_signal< sc_lv<1> > exitcond8_fu_736_p2; sc_signal< sc_logic > ap_sig_cseq_ST_st5_fsm_4; - sc_signal< bool > ap_sig_413; + sc_signal< bool > ap_sig_411; sc_signal< sc_lv<1> > tmp_nbreadreq_fu_226_p9; sc_signal< sc_lv<8> > k_reg_546; sc_signal< sc_lv<32> > itrig_reg_557; sc_signal< sc_lv<15> > i_3_reg_569; sc_signal< sc_lv<1> > exitcond_fu_753_p2; - sc_signal< sc_logic > ap_sig_cseq_ST_st15_fsm_14; - sc_signal< bool > ap_sig_439; + sc_signal< sc_logic > ap_sig_cseq_ST_st14_fsm_13; + sc_signal< bool > ap_sig_437; sc_signal< sc_logic > ap_sig_cseq_ST_st13_fsm_12; - sc_signal< bool > ap_sig_446; + sc_signal< bool > ap_sig_444; sc_signal< sc_lv<1> > or_cond_fu_979_p2; - sc_signal< sc_logic > ap_sig_cseq_ST_st17_fsm_16; - sc_signal< bool > ap_sig_457; + sc_signal< sc_logic > ap_sig_cseq_ST_st15_fsm_14; + sc_signal< bool > ap_sig_455; sc_signal< sc_lv<32> > itrig_1_reg_587; sc_signal< sc_lv<4> > kk_1_reg_610; sc_signal< sc_lv<15> > i_4_reg_622; - sc_signal< sc_logic > ap_sig_cseq_ST_st22_fsm_21; - sc_signal< bool > ap_sig_478; + sc_signal< sc_logic > ap_sig_cseq_ST_st20_fsm_19; + sc_signal< bool > ap_sig_476; sc_signal< sc_lv<64> > tmp_4_fu_664_p1; sc_signal< sc_lv<64> > tmp_18_cast_fu_730_p1; sc_signal< sc_lv<64> > tmp_7_fu_747_p1; sc_signal< sc_lv<64> > tmp_45_cast_fu_866_p1; sc_signal< sc_lv<64> > tmp_49_cast_fu_926_p1; sc_signal< sc_lv<64> > tmp_9_fu_1027_p1; - sc_signal< sc_logic > ap_sig_cseq_ST_st14_fsm_13; - sc_signal< bool > ap_sig_511; sc_signal< sc_lv<32> > tmp_40_cast_fu_998_p1; - sc_signal< sc_logic > ap_sig_cseq_ST_st16_fsm_15; - sc_signal< bool > ap_sig_520; sc_signal< sc_lv<32> > tmp_38_cast_fu_1011_p1; sc_signal< sc_logic > ap_reg_ioackin_out_stream_TREADY; sc_signal< sc_lv<32> > tmp_18_fu_804_p2; @@ -297,37 +293,35 @@ struct l2_trigger : public sc_module { sc_signal< sc_lv<8> > tmp_12_fu_1086_p1; sc_signal< sc_lv<28> > tmp_13_fu_1091_p0; sc_signal< sc_lv<8> > tmp_13_fu_1091_p1; - sc_signal< sc_lv<22> > ap_NS_fsm; + sc_signal< sc_lv<20> > ap_NS_fsm; sc_signal< sc_lv<32> > tmp_12_fu_1086_p00; sc_signal< sc_lv<32> > tmp_13_fu_1091_p00; static const sc_logic ap_const_logic_1; static const sc_logic ap_const_logic_0; - static const sc_lv<22> ap_ST_st1_fsm_0; - static const sc_lv<22> ap_ST_st2_fsm_1; - static const sc_lv<22> ap_ST_st3_fsm_2; - static const sc_lv<22> ap_ST_st4_fsm_3; - static const sc_lv<22> ap_ST_st5_fsm_4; - static const sc_lv<22> ap_ST_st6_fsm_5; - static const sc_lv<22> ap_ST_st7_fsm_6; - static const sc_lv<22> ap_ST_st8_fsm_7; - static const sc_lv<22> ap_ST_st9_fsm_8; - static const sc_lv<22> ap_ST_st10_fsm_9; - static const sc_lv<22> ap_ST_st11_fsm_10; - static const sc_lv<22> ap_ST_st12_fsm_11; - static const sc_lv<22> ap_ST_st13_fsm_12; - static const sc_lv<22> ap_ST_st14_fsm_13; - static const sc_lv<22> ap_ST_st15_fsm_14; - static const sc_lv<22> ap_ST_st16_fsm_15; - static const sc_lv<22> ap_ST_st17_fsm_16; - static const sc_lv<22> ap_ST_st18_fsm_17; - static const sc_lv<22> ap_ST_st19_fsm_18; - static const sc_lv<22> ap_ST_st20_fsm_19; - static const sc_lv<22> ap_ST_st21_fsm_20; - static const sc_lv<22> ap_ST_st22_fsm_21; + static const sc_lv<20> ap_ST_st1_fsm_0; + static const sc_lv<20> ap_ST_st2_fsm_1; + static const sc_lv<20> ap_ST_st3_fsm_2; + static const sc_lv<20> ap_ST_st4_fsm_3; + static const sc_lv<20> ap_ST_st5_fsm_4; + static const sc_lv<20> ap_ST_st6_fsm_5; + static const sc_lv<20> ap_ST_st7_fsm_6; + static const sc_lv<20> ap_ST_st8_fsm_7; + static const sc_lv<20> ap_ST_st9_fsm_8; + static const sc_lv<20> ap_ST_st10_fsm_9; + static const sc_lv<20> ap_ST_st11_fsm_10; + static const sc_lv<20> ap_ST_st12_fsm_11; + static const sc_lv<20> ap_ST_st13_fsm_12; + static const sc_lv<20> ap_ST_st14_fsm_13; + static const sc_lv<20> ap_ST_st15_fsm_14; + static const sc_lv<20> ap_ST_st16_fsm_15; + static const sc_lv<20> ap_ST_st17_fsm_16; + static const sc_lv<20> ap_ST_st18_fsm_17; + static const sc_lv<20> ap_ST_st19_fsm_18; + static const sc_lv<20> ap_ST_st20_fsm_19; static const sc_lv<32> ap_const_lv32_0; static const sc_lv<1> ap_const_lv1_1; static const sc_lv<32> ap_const_lv32_8; - static const sc_lv<32> ap_const_lv32_12; + static const sc_lv<32> ap_const_lv32_10; static const int C_S_AXI_DATA_WIDTH; static const sc_lv<32> ap_const_lv32_1; static const sc_lv<32> ap_const_lv32_2; @@ -339,20 +333,18 @@ struct l2_trigger : public sc_module { static const sc_lv<32> ap_const_lv32_9; static const sc_lv<32> ap_const_lv32_A; static const sc_lv<32> ap_const_lv32_B; + static const sc_lv<32> ap_const_lv32_F; static const sc_lv<32> ap_const_lv32_11; - static const sc_lv<32> ap_const_lv32_13; - static const sc_lv<32> ap_const_lv32_14; + static const sc_lv<32> ap_const_lv32_12; static const sc_lv<15> ap_const_lv15_0; static const sc_lv<4> ap_const_lv4_0; static const sc_lv<32> ap_const_lv32_4; static const sc_lv<8> ap_const_lv8_0; - static const sc_lv<32> ap_const_lv32_E; + static const sc_lv<32> ap_const_lv32_D; static const sc_lv<32> ap_const_lv32_C; - static const sc_lv<32> ap_const_lv32_10; + static const sc_lv<32> ap_const_lv32_E; static const sc_lv<4> ap_const_lv4_6; - static const sc_lv<32> ap_const_lv32_15; - static const sc_lv<32> ap_const_lv32_D; - static const sc_lv<32> ap_const_lv32_F; + static const sc_lv<32> ap_const_lv32_13; static const sc_lv<8> ap_const_lv8_FF; static const sc_lv<2> ap_const_lv2_0; static const sc_lv<5> ap_const_lv5_0; @@ -377,28 +369,26 @@ struct l2_trigger : public sc_module { void thread_ap_idle(); void thread_ap_ready(); void thread_ap_rst_n_inv(); - void thread_ap_sig_139(); - void thread_ap_sig_148(); - void thread_ap_sig_163(); - void thread_ap_sig_172(); - void thread_ap_sig_181(); - void thread_ap_sig_190(); - void thread_ap_sig_227(); - void thread_ap_sig_245(); - void thread_ap_sig_254(); - void thread_ap_sig_270(); - void thread_ap_sig_298(); - void thread_ap_sig_309(); - void thread_ap_sig_39(); - void thread_ap_sig_413(); - void thread_ap_sig_439(); - void thread_ap_sig_446(); - void thread_ap_sig_457(); - void thread_ap_sig_478(); - void thread_ap_sig_511(); - void thread_ap_sig_520(); - void thread_ap_sig_77(); - void thread_ap_sig_85(); + void thread_ap_sig_137(); + void thread_ap_sig_146(); + void thread_ap_sig_161(); + void thread_ap_sig_170(); + void thread_ap_sig_179(); + void thread_ap_sig_188(); + void thread_ap_sig_225(); + void thread_ap_sig_243(); + void thread_ap_sig_252(); + void thread_ap_sig_268(); + void thread_ap_sig_296(); + void thread_ap_sig_307(); + void thread_ap_sig_37(); + void thread_ap_sig_411(); + void thread_ap_sig_437(); + void thread_ap_sig_444(); + void thread_ap_sig_455(); + void thread_ap_sig_476(); + void thread_ap_sig_75(); + void thread_ap_sig_83(); void thread_ap_sig_cseq_ST_st10_fsm_9(); void thread_ap_sig_cseq_ST_st11_fsm_10(); void thread_ap_sig_cseq_ST_st12_fsm_11(); @@ -411,8 +401,6 @@ struct l2_trigger : public sc_module { void thread_ap_sig_cseq_ST_st19_fsm_18(); void thread_ap_sig_cseq_ST_st1_fsm_0(); void thread_ap_sig_cseq_ST_st20_fsm_19(); - void thread_ap_sig_cseq_ST_st21_fsm_20(); - void thread_ap_sig_cseq_ST_st22_fsm_21(); void thread_ap_sig_cseq_ST_st2_fsm_1(); void thread_ap_sig_cseq_ST_st3_fsm_2(); void thread_ap_sig_cseq_ST_st4_fsm_3(); diff --git a/l2_trigger/solution1/syn/verilog/l2_trigger.v b/l2_trigger/solution1/syn/verilog/l2_trigger.v index f6eee00..c8791bf 100644 --- a/l2_trigger/solution1/syn/verilog/l2_trigger.v +++ b/l2_trigger/solution1/syn/verilog/l2_trigger.v @@ -7,7 +7,7 @@ `timescale 1 ns / 1 ps -(* CORE_GENERATION_INFO="l2_trigger,hls_ip_2016_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z030ffg676-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.650000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=58,HLS_SYN_DSP=4,HLS_SYN_FF=746,HLS_SYN_LUT=1141}" *) +(* CORE_GENERATION_INFO="l2_trigger,hls_ip_2016_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z030ffg676-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.650000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=58,HLS_SYN_DSP=4,HLS_SYN_FF=744,HLS_SYN_LUT=1173}" *) module l2_trigger ( ap_clk, @@ -54,31 +54,29 @@ module l2_trigger ( interrupt ); -parameter ap_ST_st1_fsm_0 = 22'b1; -parameter ap_ST_st2_fsm_1 = 22'b10; -parameter ap_ST_st3_fsm_2 = 22'b100; -parameter ap_ST_st4_fsm_3 = 22'b1000; -parameter ap_ST_st5_fsm_4 = 22'b10000; -parameter ap_ST_st6_fsm_5 = 22'b100000; -parameter ap_ST_st7_fsm_6 = 22'b1000000; -parameter ap_ST_st8_fsm_7 = 22'b10000000; -parameter ap_ST_st9_fsm_8 = 22'b100000000; -parameter ap_ST_st10_fsm_9 = 22'b1000000000; -parameter ap_ST_st11_fsm_10 = 22'b10000000000; -parameter ap_ST_st12_fsm_11 = 22'b100000000000; -parameter ap_ST_st13_fsm_12 = 22'b1000000000000; -parameter ap_ST_st14_fsm_13 = 22'b10000000000000; -parameter ap_ST_st15_fsm_14 = 22'b100000000000000; -parameter ap_ST_st16_fsm_15 = 22'b1000000000000000; -parameter ap_ST_st17_fsm_16 = 22'b10000000000000000; -parameter ap_ST_st18_fsm_17 = 22'b100000000000000000; -parameter ap_ST_st19_fsm_18 = 22'b1000000000000000000; -parameter ap_ST_st20_fsm_19 = 22'b10000000000000000000; -parameter ap_ST_st21_fsm_20 = 22'b100000000000000000000; -parameter ap_ST_st22_fsm_21 = 22'b1000000000000000000000; +parameter ap_ST_st1_fsm_0 = 20'b1; +parameter ap_ST_st2_fsm_1 = 20'b10; +parameter ap_ST_st3_fsm_2 = 20'b100; +parameter ap_ST_st4_fsm_3 = 20'b1000; +parameter ap_ST_st5_fsm_4 = 20'b10000; +parameter ap_ST_st6_fsm_5 = 20'b100000; +parameter ap_ST_st7_fsm_6 = 20'b1000000; +parameter ap_ST_st8_fsm_7 = 20'b10000000; +parameter ap_ST_st9_fsm_8 = 20'b100000000; +parameter ap_ST_st10_fsm_9 = 20'b1000000000; +parameter ap_ST_st11_fsm_10 = 20'b10000000000; +parameter ap_ST_st12_fsm_11 = 20'b100000000000; +parameter ap_ST_st13_fsm_12 = 20'b1000000000000; +parameter ap_ST_st14_fsm_13 = 20'b10000000000000; +parameter ap_ST_st15_fsm_14 = 20'b100000000000000; +parameter ap_ST_st16_fsm_15 = 20'b1000000000000000; +parameter ap_ST_st17_fsm_16 = 20'b10000000000000000; +parameter ap_ST_st18_fsm_17 = 20'b100000000000000000; +parameter ap_ST_st19_fsm_18 = 20'b1000000000000000000; +parameter ap_ST_st20_fsm_19 = 20'b10000000000000000000; parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000; parameter ap_const_lv32_8 = 32'b1000; -parameter ap_const_lv32_12 = 32'b10010; +parameter ap_const_lv32_10 = 32'b10000; parameter C_S_AXI_CTRL_BUS_DATA_WIDTH = 32; parameter ap_const_int64_8 = 8; parameter C_S_AXI_CTRL_BUS_ADDR_WIDTH = 6; @@ -92,20 +90,18 @@ parameter ap_const_lv32_7 = 32'b111; parameter ap_const_lv32_9 = 32'b1001; parameter ap_const_lv32_A = 32'b1010; parameter ap_const_lv32_B = 32'b1011; +parameter ap_const_lv32_F = 32'b1111; parameter ap_const_lv32_11 = 32'b10001; -parameter ap_const_lv32_13 = 32'b10011; -parameter ap_const_lv32_14 = 32'b10100; +parameter ap_const_lv32_12 = 32'b10010; parameter ap_const_lv15_0 = 15'b000000000000000; parameter ap_const_lv4_0 = 4'b0000; parameter ap_const_lv32_4 = 32'b100; parameter ap_const_lv8_0 = 8'b00000000; -parameter ap_const_lv32_E = 32'b1110; +parameter ap_const_lv32_D = 32'b1101; parameter ap_const_lv32_C = 32'b1100; -parameter ap_const_lv32_10 = 32'b10000; +parameter ap_const_lv32_E = 32'b1110; parameter ap_const_lv4_6 = 4'b110; -parameter ap_const_lv32_15 = 32'b10101; -parameter ap_const_lv32_D = 32'b1101; -parameter ap_const_lv32_F = 32'b1111; +parameter ap_const_lv32_13 = 32'b10011; parameter ap_const_lv8_FF = 8'b11111111; parameter ap_const_lv2_0 = 2'b00; parameter ap_const_lv5_0 = 5'b00000; @@ -174,53 +170,54 @@ reg in_stream_TREADY; reg out_stream_TVALID; reg[31:0] trig_data; reg trig_data_ap_vld; +reg[31:0] trig_pixel; reg trig_pixel_ap_vld; reg ap_rst_n_inv; wire ap_start; reg ap_done; reg ap_idle; -(* fsm_encoding = "none" *) reg [21:0] ap_CS_fsm; +(* fsm_encoding = "none" *) reg [19:0] ap_CS_fsm; reg ap_sig_cseq_ST_st1_fsm_0; -reg ap_sig_39; +reg ap_sig_37; reg ap_ready; wire [15:0] n_pixels_in_bus; wire [7:0] N_BG; wire [31:0] LOW_THRESH; reg in_stream_TDATA_blk_n; reg ap_sig_cseq_ST_st9_fsm_8; -reg ap_sig_77; +reg ap_sig_75; reg out_stream_TDATA_blk_n; -reg ap_sig_cseq_ST_st19_fsm_18; -reg ap_sig_85; +reg ap_sig_cseq_ST_st17_fsm_16; +reg ap_sig_83; reg [31:0] LOW_THRESH_read_reg_1104; wire [31:0] tmp_1_fu_639_p1; reg [31:0] tmp_1_reg_1112; reg [14:0] tmp_2_reg_1118; wire [14:0] i_5_fu_658_p2; reg ap_sig_cseq_ST_st2_fsm_1; -reg ap_sig_139; +reg ap_sig_137; wire [3:0] kk_2_fu_678_p2; reg [3:0] kk_2_reg_1138; reg ap_sig_cseq_ST_st3_fsm_2; -reg ap_sig_148; +reg ap_sig_146; wire [14:0] tmp_3_fu_708_p2; reg [14:0] tmp_3_reg_1143; wire [0:0] exitcond1_fu_672_p2; wire [14:0] i_6_fu_719_p2; reg ap_sig_cseq_ST_st4_fsm_3; -reg ap_sig_163; +reg ap_sig_161; wire [14:0] i_7_fu_741_p2; reg ap_sig_cseq_ST_st6_fsm_5; -reg ap_sig_172; +reg ap_sig_170; wire [7:0] tmp_5_fu_759_p2; reg [7:0] tmp_5_reg_1170; reg ap_sig_cseq_ST_st7_fsm_6; -reg ap_sig_181; +reg ap_sig_179; wire [14:0] i_9_fu_770_p2; reg [14:0] i_9_reg_1178; reg ap_sig_cseq_ST_st8_fsm_7; -reg ap_sig_190; +reg ap_sig_188; wire [63:0] tmp_15_fu_776_p1; reg [63:0] tmp_15_reg_1186; wire [0:0] exitcond7_fu_765_p2; @@ -239,22 +236,22 @@ reg signed [31:0] tmp_19_reg_1231; reg [10:0] sum_overP1_addr_reg_1236; reg [10:0] sum_overP2_addr_reg_1241; reg ap_sig_cseq_ST_st10_fsm_9; -reg ap_sig_227; +reg ap_sig_225; wire [0:0] tmp_22_fu_822_p3; wire [3:0] kk_3_fu_950_p2; reg ap_sig_cseq_ST_st11_fsm_10; -reg ap_sig_245; +reg ap_sig_243; wire [31:0] tmp_24_fu_962_p2; reg [31:0] tmp_24_reg_1269; reg ap_sig_cseq_ST_st12_fsm_11; -reg ap_sig_254; +reg ap_sig_252; wire [0:0] tmp_25_fu_968_p2; wire [0:0] grp_fu_633_p2; reg [0:0] tmp_36_reg_1282; wire [14:0] i_8_fu_1021_p2; reg [14:0] i_8_reg_1296; -reg ap_sig_cseq_ST_st18_fsm_17; -reg ap_sig_270; +reg ap_sig_cseq_ST_st16_fsm_15; +reg ap_sig_268; wire [0:0] exitcond6_fu_1016_p2; reg [10:0] thresh1_addr_1_reg_1311; reg [10:0] thresh2_addr_1_reg_1316; @@ -263,14 +260,14 @@ reg ap_sig_ioackin_out_stream_TREADY; reg [24:0] tmp_11_reg_1326; wire [31:0] tmp_12_fu_1086_p2; reg [31:0] tmp_12_reg_1331; -reg ap_sig_cseq_ST_st20_fsm_19; -reg ap_sig_298; +reg ap_sig_cseq_ST_st18_fsm_17; +reg ap_sig_296; wire [31:0] tmp_13_fu_1091_p2; reg [31:0] tmp_13_reg_1337; wire [0:0] tmp_14_fu_1096_p2; reg [0:0] tmp_14_reg_1343; -reg ap_sig_cseq_ST_st21_fsm_20; -reg ap_sig_309; +reg ap_sig_cseq_ST_st19_fsm_18; +reg ap_sig_307; reg [10:0] sum_overP1_address0; reg sum_overP1_ce0; reg sum_overP1_we0; @@ -319,35 +316,31 @@ reg [14:0] i_1_reg_524; reg [14:0] i_2_reg_535; wire [0:0] exitcond8_fu_736_p2; reg ap_sig_cseq_ST_st5_fsm_4; -reg ap_sig_413; +reg ap_sig_411; wire [0:0] tmp_nbreadreq_fu_226_p9; reg [7:0] k_reg_546; reg [31:0] itrig_reg_557; reg [14:0] i_3_reg_569; wire [0:0] exitcond_fu_753_p2; -reg ap_sig_cseq_ST_st15_fsm_14; -reg ap_sig_439; +reg ap_sig_cseq_ST_st14_fsm_13; +reg ap_sig_437; reg ap_sig_cseq_ST_st13_fsm_12; -reg ap_sig_446; +reg ap_sig_444; wire [0:0] or_cond_fu_979_p2; -reg ap_sig_cseq_ST_st17_fsm_16; -reg ap_sig_457; +reg ap_sig_cseq_ST_st15_fsm_14; +reg ap_sig_455; reg [31:0] itrig_1_reg_587; reg [3:0] kk_1_reg_610; reg [14:0] i_4_reg_622; -reg ap_sig_cseq_ST_st22_fsm_21; -reg ap_sig_478; +reg ap_sig_cseq_ST_st20_fsm_19; +reg ap_sig_476; wire [63:0] tmp_4_fu_664_p1; wire [63:0] tmp_18_cast_fu_730_p1; wire [63:0] tmp_7_fu_747_p1; wire [63:0] tmp_45_cast_fu_866_p1; wire [63:0] tmp_49_cast_fu_926_p1; wire [63:0] tmp_9_fu_1027_p1; -reg ap_sig_cseq_ST_st14_fsm_13; -reg ap_sig_511; wire [31:0] tmp_40_cast_fu_998_p1; -reg ap_sig_cseq_ST_st16_fsm_15; -reg ap_sig_520; wire [31:0] tmp_38_cast_fu_1011_p1; reg ap_reg_ioackin_out_stream_TREADY; wire [31:0] tmp_18_fu_804_p2; @@ -388,13 +381,13 @@ wire [27:0] tmp_12_fu_1086_p0; wire [7:0] tmp_12_fu_1086_p1; wire [27:0] tmp_13_fu_1091_p0; wire [7:0] tmp_13_fu_1091_p1; -reg [21:0] ap_NS_fsm; +reg [19:0] ap_NS_fsm; wire [31:0] tmp_12_fu_1086_p00; wire [31:0] tmp_13_fu_1091_p00; // power-on initialization initial begin -#0 ap_CS_fsm = 22'b1; +#0 ap_CS_fsm = 20'b1; #0 ap_reg_ioackin_out_stream_TREADY = 1'b0; end @@ -556,9 +549,9 @@ always @ (posedge ap_clk) begin if (ap_rst_n_inv == 1'b1) begin ap_reg_ioackin_out_stream_TREADY <= 1'b0; end else begin - if (((1'b1 == ap_sig_cseq_ST_st19_fsm_18) & ~(1'b0 == ap_sig_ioackin_out_stream_TREADY))) begin + if (((1'b1 == ap_sig_cseq_ST_st17_fsm_16) & ~(1'b0 == ap_sig_ioackin_out_stream_TREADY))) begin ap_reg_ioackin_out_stream_TREADY <= 1'b0; - end else if (((1'b1 == ap_sig_cseq_ST_st19_fsm_18) & (1'b1 == out_stream_TREADY))) begin + end else if (((1'b1 == ap_sig_cseq_ST_st17_fsm_16) & (1'b1 == out_stream_TREADY))) begin ap_reg_ioackin_out_stream_TREADY <= 1'b1; end end @@ -581,7 +574,7 @@ always @ (posedge ap_clk) begin end always @ (posedge ap_clk) begin - if (((1'b1 == ap_sig_cseq_ST_st15_fsm_14) | ((1'b1 == ap_sig_cseq_ST_st13_fsm_12) & (1'b0 == or_cond_fu_979_p2)) | (1'b1 == ap_sig_cseq_ST_st17_fsm_16) | ((1'b1 == ap_sig_cseq_ST_st12_fsm_11) & (1'b0 == grp_fu_633_p2) & ~(1'b0 == tmp_25_fu_968_p2)))) begin + if (((1'b1 == ap_sig_cseq_ST_st14_fsm_13) | ((1'b1 == ap_sig_cseq_ST_st13_fsm_12) & (1'b0 == or_cond_fu_979_p2)) | (1'b1 == ap_sig_cseq_ST_st15_fsm_14) | ((1'b1 == ap_sig_cseq_ST_st12_fsm_11) & (1'b0 == grp_fu_633_p2) & ~(1'b0 == tmp_25_fu_968_p2)))) begin i_3_reg_569 <= i_9_reg_1178; end else if (((1'b1 == ap_sig_cseq_ST_st7_fsm_6) & (1'b0 == exitcond_fu_753_p2))) begin i_3_reg_569 <= ap_const_lv15_0; @@ -591,7 +584,7 @@ end always @ (posedge ap_clk) begin if (((1'b1 == ap_sig_cseq_ST_st7_fsm_6) & ~(1'b0 == exitcond_fu_753_p2))) begin i_4_reg_622 <= ap_const_lv15_0; - end else if ((1'b1 == ap_sig_cseq_ST_st22_fsm_21)) begin + end else if ((1'b1 == ap_sig_cseq_ST_st20_fsm_19)) begin i_4_reg_622 <= i_8_reg_1296; end end @@ -607,7 +600,7 @@ end always @ (posedge ap_clk) begin if ((((1'b1 == ap_sig_cseq_ST_st13_fsm_12) & (1'b0 == or_cond_fu_979_p2)) | ((1'b1 == ap_sig_cseq_ST_st12_fsm_11) & (1'b0 == grp_fu_633_p2) & ~(1'b0 == tmp_25_fu_968_p2)))) begin itrig_1_reg_587 <= itrig_1_reg_587; - end else if (((1'b1 == ap_sig_cseq_ST_st15_fsm_14) | (1'b1 == ap_sig_cseq_ST_st17_fsm_16))) begin + end else if (((1'b1 == ap_sig_cseq_ST_st14_fsm_13) | (1'b1 == ap_sig_cseq_ST_st15_fsm_14))) begin itrig_1_reg_587 <= ap_const_lv32_1; end else if (((1'b1 == ap_sig_cseq_ST_st7_fsm_6) & (1'b0 == exitcond_fu_753_p2))) begin itrig_1_reg_587 <= itrig_reg_557; @@ -668,7 +661,7 @@ always @ (posedge ap_clk) begin end always @ (posedge ap_clk) begin - if ((1'b1 == ap_sig_cseq_ST_st18_fsm_17)) begin + if ((1'b1 == ap_sig_cseq_ST_st16_fsm_15)) begin i_8_reg_1296 <= i_8_fu_1021_p2; end end @@ -694,28 +687,28 @@ always @ (posedge ap_clk) begin end always @ (posedge ap_clk) begin - if (((1'b1 == ap_sig_cseq_ST_st18_fsm_17) & (1'b0 == exitcond6_fu_1016_p2))) begin + if (((1'b1 == ap_sig_cseq_ST_st16_fsm_15) & (1'b0 == exitcond6_fu_1016_p2))) begin thresh1_addr_1_reg_1311 <= tmp_9_fu_1027_p1; thresh2_addr_1_reg_1316 <= tmp_9_fu_1027_p1; end end always @ (posedge ap_clk) begin - if (((1'b1 == ap_sig_cseq_ST_st19_fsm_18) & ~(1'b0 == ap_sig_ioackin_out_stream_TREADY))) begin + if (((1'b1 == ap_sig_cseq_ST_st17_fsm_16) & ~(1'b0 == ap_sig_ioackin_out_stream_TREADY))) begin tmp_10_reg_1321 <= {{sum_pix1_q0[ap_const_lv32_1F : ap_const_lv32_7]}}; tmp_11_reg_1326 <= {{sum_pix2_q0[ap_const_lv32_1F : ap_const_lv32_7]}}; end end always @ (posedge ap_clk) begin - if ((1'b1 == ap_sig_cseq_ST_st20_fsm_19)) begin + if ((1'b1 == ap_sig_cseq_ST_st18_fsm_17)) begin tmp_12_reg_1331 <= tmp_12_fu_1086_p2; tmp_13_reg_1337 <= tmp_13_fu_1091_p2; end end always @ (posedge ap_clk) begin - if ((1'b1 == ap_sig_cseq_ST_st21_fsm_20)) begin + if ((1'b1 == ap_sig_cseq_ST_st19_fsm_18)) begin tmp_14_reg_1343 <= tmp_14_fu_1096_p2; end end @@ -769,7 +762,7 @@ always @ (*) begin end always @ (*) begin - if (ap_sig_227) begin + if (ap_sig_225) begin ap_sig_cseq_ST_st10_fsm_9 = 1'b1; end else begin ap_sig_cseq_ST_st10_fsm_9 = 1'b0; @@ -777,7 +770,7 @@ always @ (*) begin end always @ (*) begin - if (ap_sig_245) begin + if (ap_sig_243) begin ap_sig_cseq_ST_st11_fsm_10 = 1'b1; end else begin ap_sig_cseq_ST_st11_fsm_10 = 1'b0; @@ -785,7 +778,7 @@ always @ (*) begin end always @ (*) begin - if (ap_sig_254) begin + if (ap_sig_252) begin ap_sig_cseq_ST_st12_fsm_11 = 1'b1; end else begin ap_sig_cseq_ST_st12_fsm_11 = 1'b0; @@ -793,7 +786,7 @@ always @ (*) begin end always @ (*) begin - if (ap_sig_446) begin + if (ap_sig_444) begin ap_sig_cseq_ST_st13_fsm_12 = 1'b1; end else begin ap_sig_cseq_ST_st13_fsm_12 = 1'b0; @@ -801,7 +794,7 @@ always @ (*) begin end always @ (*) begin - if (ap_sig_511) begin + if (ap_sig_437) begin ap_sig_cseq_ST_st14_fsm_13 = 1'b1; end else begin ap_sig_cseq_ST_st14_fsm_13 = 1'b0; @@ -809,7 +802,7 @@ always @ (*) begin end always @ (*) begin - if (ap_sig_439) begin + if (ap_sig_455) begin ap_sig_cseq_ST_st15_fsm_14 = 1'b1; end else begin ap_sig_cseq_ST_st15_fsm_14 = 1'b0; @@ -817,7 +810,7 @@ always @ (*) begin end always @ (*) begin - if (ap_sig_520) begin + if (ap_sig_268) begin ap_sig_cseq_ST_st16_fsm_15 = 1'b1; end else begin ap_sig_cseq_ST_st16_fsm_15 = 1'b0; @@ -825,7 +818,7 @@ always @ (*) begin end always @ (*) begin - if (ap_sig_457) begin + if (ap_sig_83) begin ap_sig_cseq_ST_st17_fsm_16 = 1'b1; end else begin ap_sig_cseq_ST_st17_fsm_16 = 1'b0; @@ -833,7 +826,7 @@ always @ (*) begin end always @ (*) begin - if (ap_sig_270) begin + if (ap_sig_296) begin ap_sig_cseq_ST_st18_fsm_17 = 1'b1; end else begin ap_sig_cseq_ST_st18_fsm_17 = 1'b0; @@ -841,7 +834,7 @@ always @ (*) begin end always @ (*) begin - if (ap_sig_85) begin + if (ap_sig_307) begin ap_sig_cseq_ST_st19_fsm_18 = 1'b1; end else begin ap_sig_cseq_ST_st19_fsm_18 = 1'b0; @@ -849,7 +842,7 @@ always @ (*) begin end always @ (*) begin - if (ap_sig_39) begin + if (ap_sig_37) begin ap_sig_cseq_ST_st1_fsm_0 = 1'b1; end else begin ap_sig_cseq_ST_st1_fsm_0 = 1'b0; @@ -857,7 +850,7 @@ always @ (*) begin end always @ (*) begin - if (ap_sig_298) begin + if (ap_sig_476) begin ap_sig_cseq_ST_st20_fsm_19 = 1'b1; end else begin ap_sig_cseq_ST_st20_fsm_19 = 1'b0; @@ -865,23 +858,7 @@ always @ (*) begin end always @ (*) begin - if (ap_sig_309) begin - ap_sig_cseq_ST_st21_fsm_20 = 1'b1; - end else begin - ap_sig_cseq_ST_st21_fsm_20 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_478) begin - ap_sig_cseq_ST_st22_fsm_21 = 1'b1; - end else begin - ap_sig_cseq_ST_st22_fsm_21 = 1'b0; - end -end - -always @ (*) begin - if (ap_sig_139) begin + if (ap_sig_137) begin ap_sig_cseq_ST_st2_fsm_1 = 1'b1; end else begin ap_sig_cseq_ST_st2_fsm_1 = 1'b0; @@ -889,7 +866,7 @@ always @ (*) begin end always @ (*) begin - if (ap_sig_148) begin + if (ap_sig_146) begin ap_sig_cseq_ST_st3_fsm_2 = 1'b1; end else begin ap_sig_cseq_ST_st3_fsm_2 = 1'b0; @@ -897,7 +874,7 @@ always @ (*) begin end always @ (*) begin - if (ap_sig_163) begin + if (ap_sig_161) begin ap_sig_cseq_ST_st4_fsm_3 = 1'b1; end else begin ap_sig_cseq_ST_st4_fsm_3 = 1'b0; @@ -905,7 +882,7 @@ always @ (*) begin end always @ (*) begin - if (ap_sig_413) begin + if (ap_sig_411) begin ap_sig_cseq_ST_st5_fsm_4 = 1'b1; end else begin ap_sig_cseq_ST_st5_fsm_4 = 1'b0; @@ -913,7 +890,7 @@ always @ (*) begin end always @ (*) begin - if (ap_sig_172) begin + if (ap_sig_170) begin ap_sig_cseq_ST_st6_fsm_5 = 1'b1; end else begin ap_sig_cseq_ST_st6_fsm_5 = 1'b0; @@ -921,7 +898,7 @@ always @ (*) begin end always @ (*) begin - if (ap_sig_181) begin + if (ap_sig_179) begin ap_sig_cseq_ST_st7_fsm_6 = 1'b1; end else begin ap_sig_cseq_ST_st7_fsm_6 = 1'b0; @@ -929,7 +906,7 @@ always @ (*) begin end always @ (*) begin - if (ap_sig_190) begin + if (ap_sig_188) begin ap_sig_cseq_ST_st8_fsm_7 = 1'b1; end else begin ap_sig_cseq_ST_st8_fsm_7 = 1'b0; @@ -937,7 +914,7 @@ always @ (*) begin end always @ (*) begin - if (ap_sig_77) begin + if (ap_sig_75) begin ap_sig_cseq_ST_st9_fsm_8 = 1'b1; end else begin ap_sig_cseq_ST_st9_fsm_8 = 1'b0; @@ -1053,7 +1030,7 @@ always @ (*) begin end always @ (*) begin - if ((1'b1 == ap_sig_cseq_ST_st19_fsm_18)) begin + if ((1'b1 == ap_sig_cseq_ST_st17_fsm_16)) begin out_stream_TDATA_blk_n = out_stream_TREADY; end else begin out_stream_TDATA_blk_n = 1'b1; @@ -1061,7 +1038,7 @@ always @ (*) begin end always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st19_fsm_18) & (1'b0 == ap_reg_ioackin_out_stream_TREADY))) begin + if (((1'b1 == ap_sig_cseq_ST_st17_fsm_16) & (1'b0 == ap_reg_ioackin_out_stream_TREADY))) begin out_stream_TVALID = 1'b1; end else begin out_stream_TVALID = 1'b0; @@ -1151,7 +1128,7 @@ always @ (*) begin sum_pix1_address0 = tmp_7_fu_747_p1; end else if ((1'b1 == ap_sig_cseq_ST_st2_fsm_1)) begin sum_pix1_address0 = tmp_4_fu_664_p1; - end else if ((1'b1 == ap_sig_cseq_ST_st18_fsm_17)) begin + end else if ((1'b1 == ap_sig_cseq_ST_st16_fsm_15)) begin sum_pix1_address0 = tmp_9_fu_1027_p1; end else if ((1'b1 == ap_sig_cseq_ST_st8_fsm_7)) begin sum_pix1_address0 = tmp_15_fu_776_p1; @@ -1161,7 +1138,7 @@ always @ (*) begin end always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) | (1'b1 == ap_sig_cseq_ST_st6_fsm_5) | (1'b1 == ap_sig_cseq_ST_st8_fsm_7) | ((1'b1 == ap_sig_cseq_ST_st9_fsm_8) & ~(in_stream_TVALID == 1'b0)) | (1'b1 == ap_sig_cseq_ST_st18_fsm_17))) begin + if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) | (1'b1 == ap_sig_cseq_ST_st6_fsm_5) | (1'b1 == ap_sig_cseq_ST_st8_fsm_7) | ((1'b1 == ap_sig_cseq_ST_st9_fsm_8) & ~(in_stream_TVALID == 1'b0)) | (1'b1 == ap_sig_cseq_ST_st16_fsm_15))) begin sum_pix1_ce0 = 1'b1; end else begin sum_pix1_ce0 = 1'b0; @@ -1193,7 +1170,7 @@ always @ (*) begin sum_pix2_address0 = tmp_7_fu_747_p1; end else if ((1'b1 == ap_sig_cseq_ST_st2_fsm_1)) begin sum_pix2_address0 = tmp_4_fu_664_p1; - end else if ((1'b1 == ap_sig_cseq_ST_st18_fsm_17)) begin + end else if ((1'b1 == ap_sig_cseq_ST_st16_fsm_15)) begin sum_pix2_address0 = tmp_9_fu_1027_p1; end else if ((1'b1 == ap_sig_cseq_ST_st8_fsm_7)) begin sum_pix2_address0 = tmp_15_fu_776_p1; @@ -1203,7 +1180,7 @@ always @ (*) begin end always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) | (1'b1 == ap_sig_cseq_ST_st6_fsm_5) | (1'b1 == ap_sig_cseq_ST_st8_fsm_7) | ((1'b1 == ap_sig_cseq_ST_st9_fsm_8) & ~(in_stream_TVALID == 1'b0)) | (1'b1 == ap_sig_cseq_ST_st18_fsm_17))) begin + if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) | (1'b1 == ap_sig_cseq_ST_st6_fsm_5) | (1'b1 == ap_sig_cseq_ST_st8_fsm_7) | ((1'b1 == ap_sig_cseq_ST_st9_fsm_8) & ~(in_stream_TVALID == 1'b0)) | (1'b1 == ap_sig_cseq_ST_st16_fsm_15))) begin sum_pix2_ce0 = 1'b1; end else begin sum_pix2_ce0 = 1'b0; @@ -1229,7 +1206,7 @@ always @ (*) begin end always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st21_fsm_20) | (1'b1 == ap_sig_cseq_ST_st22_fsm_21))) begin + if (((1'b1 == ap_sig_cseq_ST_st19_fsm_18) | (1'b1 == ap_sig_cseq_ST_st20_fsm_19))) begin thresh1_address0 = thresh1_addr_1_reg_1311; end else if ((1'b1 == ap_sig_cseq_ST_st2_fsm_1)) begin thresh1_address0 = tmp_4_fu_664_p1; @@ -1241,7 +1218,7 @@ always @ (*) begin end always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) | (1'b1 == ap_sig_cseq_ST_st10_fsm_9) | (1'b1 == ap_sig_cseq_ST_st21_fsm_20) | (1'b1 == ap_sig_cseq_ST_st22_fsm_21))) begin + if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) | (1'b1 == ap_sig_cseq_ST_st10_fsm_9) | (1'b1 == ap_sig_cseq_ST_st19_fsm_18) | (1'b1 == ap_sig_cseq_ST_st20_fsm_19))) begin thresh1_ce0 = 1'b1; end else begin thresh1_ce0 = 1'b0; @@ -1249,9 +1226,9 @@ always @ (*) begin end always @ (*) begin - if ((1'b1 == ap_sig_cseq_ST_st22_fsm_21)) begin + if ((1'b1 == ap_sig_cseq_ST_st20_fsm_19)) begin thresh1_d0 = LOW_THRESH_read_reg_1104; - end else if ((1'b1 == ap_sig_cseq_ST_st21_fsm_20)) begin + end else if ((1'b1 == ap_sig_cseq_ST_st19_fsm_18)) begin thresh1_d0 = tmp_12_reg_1331; end else if ((1'b1 == ap_sig_cseq_ST_st2_fsm_1)) begin thresh1_d0 = ap_const_lv32_639C; @@ -1261,7 +1238,7 @@ always @ (*) begin end always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st21_fsm_20) | ((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & (1'b0 == exitcond2_fu_653_p2)) | ((1'b1 == ap_sig_cseq_ST_st22_fsm_21) & ~(1'b0 == tmp_14_reg_1343)))) begin + if (((1'b1 == ap_sig_cseq_ST_st19_fsm_18) | ((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & (1'b0 == exitcond2_fu_653_p2)) | ((1'b1 == ap_sig_cseq_ST_st20_fsm_19) & ~(1'b0 == tmp_14_reg_1343)))) begin thresh1_we0 = 1'b1; end else begin thresh1_we0 = 1'b0; @@ -1269,7 +1246,7 @@ always @ (*) begin end always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st21_fsm_20) | (1'b1 == ap_sig_cseq_ST_st22_fsm_21))) begin + if (((1'b1 == ap_sig_cseq_ST_st19_fsm_18) | (1'b1 == ap_sig_cseq_ST_st20_fsm_19))) begin thresh2_address0 = thresh2_addr_1_reg_1316; end else if ((1'b1 == ap_sig_cseq_ST_st2_fsm_1)) begin thresh2_address0 = tmp_4_fu_664_p1; @@ -1281,7 +1258,7 @@ always @ (*) begin end always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) | (1'b1 == ap_sig_cseq_ST_st12_fsm_11) | (1'b1 == ap_sig_cseq_ST_st21_fsm_20) | (1'b1 == ap_sig_cseq_ST_st22_fsm_21))) begin + if (((1'b1 == ap_sig_cseq_ST_st2_fsm_1) | (1'b1 == ap_sig_cseq_ST_st12_fsm_11) | (1'b1 == ap_sig_cseq_ST_st19_fsm_18) | (1'b1 == ap_sig_cseq_ST_st20_fsm_19))) begin thresh2_ce0 = 1'b1; end else begin thresh2_ce0 = 1'b0; @@ -1289,9 +1266,9 @@ always @ (*) begin end always @ (*) begin - if ((1'b1 == ap_sig_cseq_ST_st22_fsm_21)) begin + if ((1'b1 == ap_sig_cseq_ST_st20_fsm_19)) begin thresh2_d0 = LOW_THRESH_read_reg_1104; - end else if ((1'b1 == ap_sig_cseq_ST_st21_fsm_20)) begin + end else if ((1'b1 == ap_sig_cseq_ST_st19_fsm_18)) begin thresh2_d0 = tmp_13_reg_1337; end else if ((1'b1 == ap_sig_cseq_ST_st2_fsm_1)) begin thresh2_d0 = ap_const_lv32_639C; @@ -1301,7 +1278,7 @@ always @ (*) begin end always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st21_fsm_20) | ((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & (1'b0 == exitcond2_fu_653_p2)) | ((1'b1 == ap_sig_cseq_ST_st22_fsm_21) & ~(1'b0 == tmp_21_fu_1100_p2)))) begin + if (((1'b1 == ap_sig_cseq_ST_st19_fsm_18) | ((1'b1 == ap_sig_cseq_ST_st2_fsm_1) & (1'b0 == exitcond2_fu_653_p2)) | ((1'b1 == ap_sig_cseq_ST_st20_fsm_19) & ~(1'b0 == tmp_21_fu_1100_p2)))) begin thresh2_we0 = 1'b1; end else begin thresh2_we0 = 1'b0; @@ -1309,13 +1286,9 @@ always @ (*) begin end always @ (*) begin - if ((1'b1 == ap_sig_cseq_ST_st17_fsm_16)) begin - trig_data = tmp_38_cast_fu_1011_p1; - end else if ((1'b1 == ap_sig_cseq_ST_st15_fsm_14)) begin - trig_data = tmp_40_cast_fu_998_p1; - end else if ((((1'b1 == ap_sig_cseq_ST_st12_fsm_11) & ~(1'b0 == tmp_25_fu_968_p2) & ~(1'b0 == grp_fu_633_p2)) | ((1'b1 == ap_sig_cseq_ST_st13_fsm_12) & ~(1'b0 == or_cond_fu_979_p2)))) begin + if ((((1'b1 == ap_sig_cseq_ST_st12_fsm_11) & ~(1'b0 == tmp_25_fu_968_p2) & ~(1'b0 == grp_fu_633_p2)) | ((1'b1 == ap_sig_cseq_ST_st13_fsm_12) & ~(1'b0 == or_cond_fu_979_p2)))) begin trig_data = ap_const_lv32_1; - end else if ((((1'b1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == 1'b0)) | (1'b1 == ap_sig_cseq_ST_st14_fsm_13) | (1'b1 == ap_sig_cseq_ST_st16_fsm_15))) begin + end else if ((((1'b1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == 1'b0)) | (1'b1 == ap_sig_cseq_ST_st14_fsm_13) | (1'b1 == ap_sig_cseq_ST_st15_fsm_14))) begin trig_data = ap_const_lv32_0; end else begin trig_data = 'bx; @@ -1323,7 +1296,7 @@ always @ (*) begin end always @ (*) begin - if ((((1'b1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == 1'b0)) | (1'b1 == ap_sig_cseq_ST_st15_fsm_14) | (1'b1 == ap_sig_cseq_ST_st17_fsm_16) | ((1'b1 == ap_sig_cseq_ST_st12_fsm_11) & ~(1'b0 == tmp_25_fu_968_p2) & ~(1'b0 == grp_fu_633_p2)) | ((1'b1 == ap_sig_cseq_ST_st13_fsm_12) & ~(1'b0 == or_cond_fu_979_p2)) | (1'b1 == ap_sig_cseq_ST_st14_fsm_13) | (1'b1 == ap_sig_cseq_ST_st16_fsm_15))) begin + if ((((1'b1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == 1'b0)) | (1'b1 == ap_sig_cseq_ST_st14_fsm_13) | (1'b1 == ap_sig_cseq_ST_st15_fsm_14) | ((1'b1 == ap_sig_cseq_ST_st12_fsm_11) & ~(1'b0 == tmp_25_fu_968_p2) & ~(1'b0 == grp_fu_633_p2)) | ((1'b1 == ap_sig_cseq_ST_st13_fsm_12) & ~(1'b0 == or_cond_fu_979_p2)))) begin trig_data_ap_vld = 1'b1; end else begin trig_data_ap_vld = 1'b0; @@ -1331,7 +1304,19 @@ always @ (*) begin end always @ (*) begin - if (((1'b1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == 1'b0))) begin + if ((1'b1 == ap_sig_cseq_ST_st15_fsm_14)) begin + trig_pixel = tmp_38_cast_fu_1011_p1; + end else if (((1'b1 == ap_sig_cseq_ST_st13_fsm_12) & ~(1'b0 == or_cond_fu_979_p2))) begin + trig_pixel = tmp_40_cast_fu_998_p1; + end else if (((1'b1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == 1'b0))) begin + trig_pixel = ap_const_lv32_0; + end else begin + trig_pixel = 'bx; + end +end + +always @ (*) begin + if ((((1'b1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == 1'b0)) | (1'b1 == ap_sig_cseq_ST_st15_fsm_14) | ((1'b1 == ap_sig_cseq_ST_st13_fsm_12) & ~(1'b0 == or_cond_fu_979_p2)))) begin trig_pixel_ap_vld = 1'b1; end else begin trig_pixel_ap_vld = 1'b0; @@ -1384,7 +1369,7 @@ always @ (*) begin end ap_ST_st7_fsm_6 : begin if (~(1'b0 == exitcond_fu_753_p2)) begin - ap_NS_fsm = ap_ST_st18_fsm_17; + ap_NS_fsm = ap_ST_st16_fsm_15; end else begin ap_NS_fsm = ap_ST_st8_fsm_7; end @@ -1415,7 +1400,7 @@ always @ (*) begin end ap_ST_st12_fsm_11 : begin if ((~(1'b0 == tmp_25_fu_968_p2) & ~(1'b0 == grp_fu_633_p2))) begin - ap_NS_fsm = ap_ST_st16_fsm_15; + ap_NS_fsm = ap_ST_st15_fsm_14; end else if (((1'b0 == grp_fu_633_p2) & ~(1'b0 == tmp_25_fu_968_p2))) begin ap_NS_fsm = ap_ST_st8_fsm_7; end else begin @@ -1430,39 +1415,33 @@ always @ (*) begin end end ap_ST_st14_fsm_13 : begin - ap_NS_fsm = ap_ST_st15_fsm_14; + ap_NS_fsm = ap_ST_st8_fsm_7; end ap_ST_st15_fsm_14 : begin ap_NS_fsm = ap_ST_st8_fsm_7; end ap_ST_st16_fsm_15 : begin - ap_NS_fsm = ap_ST_st17_fsm_16; - end - ap_ST_st17_fsm_16 : begin - ap_NS_fsm = ap_ST_st8_fsm_7; - end - ap_ST_st18_fsm_17 : begin if ((1'b0 == exitcond6_fu_1016_p2)) begin - ap_NS_fsm = ap_ST_st19_fsm_18; + ap_NS_fsm = ap_ST_st17_fsm_16; end else begin ap_NS_fsm = ap_ST_st5_fsm_4; end end - ap_ST_st19_fsm_18 : begin + ap_ST_st17_fsm_16 : begin if (~(1'b0 == ap_sig_ioackin_out_stream_TREADY)) begin - ap_NS_fsm = ap_ST_st20_fsm_19; + ap_NS_fsm = ap_ST_st18_fsm_17; end else begin - ap_NS_fsm = ap_ST_st19_fsm_18; + ap_NS_fsm = ap_ST_st17_fsm_16; end end - ap_ST_st20_fsm_19 : begin - ap_NS_fsm = ap_ST_st21_fsm_20; + ap_ST_st18_fsm_17 : begin + ap_NS_fsm = ap_ST_st19_fsm_18; end - ap_ST_st21_fsm_20 : begin - ap_NS_fsm = ap_ST_st22_fsm_21; + ap_ST_st19_fsm_18 : begin + ap_NS_fsm = ap_ST_st20_fsm_19; end - ap_ST_st22_fsm_21 : begin - ap_NS_fsm = ap_ST_st18_fsm_17; + ap_ST_st20_fsm_19 : begin + ap_NS_fsm = ap_ST_st16_fsm_15; end default : begin ap_NS_fsm = 'bx; @@ -1475,91 +1454,83 @@ always @ (*) begin end always @ (*) begin - ap_sig_139 = (1'b1 == ap_CS_fsm[ap_const_lv32_1]); -end - -always @ (*) begin - ap_sig_148 = (1'b1 == ap_CS_fsm[ap_const_lv32_2]); + ap_sig_137 = (1'b1 == ap_CS_fsm[ap_const_lv32_1]); end always @ (*) begin - ap_sig_163 = (1'b1 == ap_CS_fsm[ap_const_lv32_3]); + ap_sig_146 = (1'b1 == ap_CS_fsm[ap_const_lv32_2]); end always @ (*) begin - ap_sig_172 = (1'b1 == ap_CS_fsm[ap_const_lv32_5]); + ap_sig_161 = (1'b1 == ap_CS_fsm[ap_const_lv32_3]); end always @ (*) begin - ap_sig_181 = (1'b1 == ap_CS_fsm[ap_const_lv32_6]); + ap_sig_170 = (1'b1 == ap_CS_fsm[ap_const_lv32_5]); end always @ (*) begin - ap_sig_190 = (1'b1 == ap_CS_fsm[ap_const_lv32_7]); + ap_sig_179 = (1'b1 == ap_CS_fsm[ap_const_lv32_6]); end always @ (*) begin - ap_sig_227 = (1'b1 == ap_CS_fsm[ap_const_lv32_9]); + ap_sig_188 = (1'b1 == ap_CS_fsm[ap_const_lv32_7]); end always @ (*) begin - ap_sig_245 = (1'b1 == ap_CS_fsm[ap_const_lv32_A]); + ap_sig_225 = (1'b1 == ap_CS_fsm[ap_const_lv32_9]); end always @ (*) begin - ap_sig_254 = (1'b1 == ap_CS_fsm[ap_const_lv32_B]); + ap_sig_243 = (1'b1 == ap_CS_fsm[ap_const_lv32_A]); end always @ (*) begin - ap_sig_270 = (1'b1 == ap_CS_fsm[ap_const_lv32_11]); + ap_sig_252 = (1'b1 == ap_CS_fsm[ap_const_lv32_B]); end always @ (*) begin - ap_sig_298 = (1'b1 == ap_CS_fsm[ap_const_lv32_13]); + ap_sig_268 = (1'b1 == ap_CS_fsm[ap_const_lv32_F]); end always @ (*) begin - ap_sig_309 = (1'b1 == ap_CS_fsm[ap_const_lv32_14]); + ap_sig_296 = (1'b1 == ap_CS_fsm[ap_const_lv32_11]); end always @ (*) begin - ap_sig_39 = (ap_CS_fsm[ap_const_lv32_0] == 1'b1); + ap_sig_307 = (1'b1 == ap_CS_fsm[ap_const_lv32_12]); end always @ (*) begin - ap_sig_413 = (1'b1 == ap_CS_fsm[ap_const_lv32_4]); + ap_sig_37 = (ap_CS_fsm[ap_const_lv32_0] == 1'b1); end always @ (*) begin - ap_sig_439 = (1'b1 == ap_CS_fsm[ap_const_lv32_E]); + ap_sig_411 = (1'b1 == ap_CS_fsm[ap_const_lv32_4]); end always @ (*) begin - ap_sig_446 = (1'b1 == ap_CS_fsm[ap_const_lv32_C]); + ap_sig_437 = (1'b1 == ap_CS_fsm[ap_const_lv32_D]); end always @ (*) begin - ap_sig_457 = (1'b1 == ap_CS_fsm[ap_const_lv32_10]); + ap_sig_444 = (1'b1 == ap_CS_fsm[ap_const_lv32_C]); end always @ (*) begin - ap_sig_478 = (1'b1 == ap_CS_fsm[ap_const_lv32_15]); + ap_sig_455 = (1'b1 == ap_CS_fsm[ap_const_lv32_E]); end always @ (*) begin - ap_sig_511 = (1'b1 == ap_CS_fsm[ap_const_lv32_D]); + ap_sig_476 = (1'b1 == ap_CS_fsm[ap_const_lv32_13]); end always @ (*) begin - ap_sig_520 = (1'b1 == ap_CS_fsm[ap_const_lv32_F]); + ap_sig_75 = (1'b1 == ap_CS_fsm[ap_const_lv32_8]); end always @ (*) begin - ap_sig_77 = (1'b1 == ap_CS_fsm[ap_const_lv32_8]); -end - -always @ (*) begin - ap_sig_85 = (1'b1 == ap_CS_fsm[ap_const_lv32_12]); + ap_sig_83 = (1'b1 == ap_CS_fsm[ap_const_lv32_10]); end assign exitcond1_fu_672_p2 = ((kk_reg_513 == ap_const_lv4_8) ? 1'b1 : 1'b0); @@ -1734,8 +1705,6 @@ assign tmp_nbreadreq_fu_226_p9 = in_stream_TVALID; assign tmp_s_fu_696_p3 = {{kk_reg_513}, {ap_const_lv7_0}}; -assign trig_pixel = ap_const_lv32_0; - always @ (posedge ap_clk) begin tmp_1_reg_1112[31:8] <= 24'b000000000000000000000000; tmp_3_reg_1143[6:0] <= 7'b0000000; diff --git a/l2_trigger/solution1/syn/vhdl/l2_trigger.vhd b/l2_trigger/solution1/syn/vhdl/l2_trigger.vhd index 6ed5d2b..7bc5dff 100644 --- a/l2_trigger/solution1/syn/vhdl/l2_trigger.vhd +++ b/l2_trigger/solution1/syn/vhdl/l2_trigger.vhd @@ -62,35 +62,33 @@ end; architecture behav of l2_trigger is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is - "l2_trigger,hls_ip_2016_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z030ffg676-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.650000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=58,HLS_SYN_DSP=4,HLS_SYN_FF=746,HLS_SYN_LUT=1141}"; + "l2_trigger,hls_ip_2016_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z030ffg676-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=7.650000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=58,HLS_SYN_DSP=4,HLS_SYN_FF=744,HLS_SYN_LUT=1173}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; - constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (21 downto 0) := "0000000000000000000001"; - constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (21 downto 0) := "0000000000000000000010"; - constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (21 downto 0) := "0000000000000000000100"; - constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (21 downto 0) := "0000000000000000001000"; - constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (21 downto 0) := "0000000000000000010000"; - constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (21 downto 0) := "0000000000000000100000"; - constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (21 downto 0) := "0000000000000001000000"; - constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (21 downto 0) := "0000000000000010000000"; - constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (21 downto 0) := "0000000000000100000000"; - constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (21 downto 0) := "0000000000001000000000"; - constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (21 downto 0) := "0000000000010000000000"; - constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (21 downto 0) := "0000000000100000000000"; - constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (21 downto 0) := "0000000001000000000000"; - constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (21 downto 0) := "0000000010000000000000"; - constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (21 downto 0) := "0000000100000000000000"; - constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (21 downto 0) := "0000001000000000000000"; - constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (21 downto 0) := "0000010000000000000000"; - constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (21 downto 0) := "0000100000000000000000"; - constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (21 downto 0) := "0001000000000000000000"; - constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (21 downto 0) := "0010000000000000000000"; - constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (21 downto 0) := "0100000000000000000000"; - constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (21 downto 0) := "1000000000000000000000"; + constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (19 downto 0) := "00000000000000000001"; + constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (19 downto 0) := "00000000000000000010"; + constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (19 downto 0) := "00000000000000000100"; + constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (19 downto 0) := "00000000000000001000"; + constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (19 downto 0) := "00000000000000010000"; + constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (19 downto 0) := "00000000000000100000"; + constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (19 downto 0) := "00000000000001000000"; + constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (19 downto 0) := "00000000000010000000"; + constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (19 downto 0) := "00000000000100000000"; + constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (19 downto 0) := "00000000001000000000"; + constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (19 downto 0) := "00000000010000000000"; + constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (19 downto 0) := "00000000100000000000"; + constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (19 downto 0) := "00000001000000000000"; + constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (19 downto 0) := "00000010000000000000"; + constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (19 downto 0) := "00000100000000000000"; + constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (19 downto 0) := "00001000000000000000"; + constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (19 downto 0) := "00010000000000000000"; + constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (19 downto 0) := "00100000000000000000"; + constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (19 downto 0) := "01000000000000000000"; + constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (19 downto 0) := "10000000000000000000"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000"; - constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010"; + constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000"; constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010"; @@ -102,20 +100,18 @@ architecture behav of l2_trigger is constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001"; constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010"; constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011"; + constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111"; constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001"; - constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011"; - constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100"; + constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010"; constant ap_const_lv15_0 : STD_LOGIC_VECTOR (14 downto 0) := "000000000000000"; constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000"; constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100"; constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000"; - constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110"; + constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101"; constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100"; - constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000"; + constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110"; constant ap_const_lv4_6 : STD_LOGIC_VECTOR (3 downto 0) := "0110"; - constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101"; - constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101"; - constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111"; + constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011"; constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111"; constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00"; constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000"; @@ -138,49 +134,49 @@ architecture behav of l2_trigger is signal ap_start : STD_LOGIC; signal ap_done : STD_LOGIC; signal ap_idle : STD_LOGIC; - signal ap_CS_fsm : STD_LOGIC_VECTOR (21 downto 0) := "0000000000000000000001"; + signal ap_CS_fsm : STD_LOGIC_VECTOR (19 downto 0) := "00000000000000000001"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC; - signal ap_sig_39 : BOOLEAN; + signal ap_sig_37 : BOOLEAN; signal ap_ready : STD_LOGIC; signal n_pixels_in_bus : STD_LOGIC_VECTOR (15 downto 0); signal N_BG : STD_LOGIC_VECTOR (7 downto 0); signal LOW_THRESH : STD_LOGIC_VECTOR (31 downto 0); signal in_stream_TDATA_blk_n : STD_LOGIC; signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC; - signal ap_sig_77 : BOOLEAN; + signal ap_sig_75 : BOOLEAN; signal out_stream_TDATA_blk_n : STD_LOGIC; - signal ap_sig_cseq_ST_st19_fsm_18 : STD_LOGIC; - signal ap_sig_85 : BOOLEAN; + signal ap_sig_cseq_ST_st17_fsm_16 : STD_LOGIC; + signal ap_sig_83 : BOOLEAN; signal LOW_THRESH_read_reg_1104 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_fu_639_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_reg_1112 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_2_reg_1118 : STD_LOGIC_VECTOR (14 downto 0); signal i_5_fu_658_p2 : STD_LOGIC_VECTOR (14 downto 0); signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC; - signal ap_sig_139 : BOOLEAN; + signal ap_sig_137 : BOOLEAN; signal kk_2_fu_678_p2 : STD_LOGIC_VECTOR (3 downto 0); signal kk_2_reg_1138 : STD_LOGIC_VECTOR (3 downto 0); signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC; - signal ap_sig_148 : BOOLEAN; + signal ap_sig_146 : BOOLEAN; signal tmp_3_fu_708_p2 : STD_LOGIC_VECTOR (14 downto 0); signal tmp_3_reg_1143 : STD_LOGIC_VECTOR (14 downto 0); signal exitcond1_fu_672_p2 : STD_LOGIC_VECTOR (0 downto 0); signal i_6_fu_719_p2 : STD_LOGIC_VECTOR (14 downto 0); signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC; - signal ap_sig_163 : BOOLEAN; + signal ap_sig_161 : BOOLEAN; signal i_7_fu_741_p2 : STD_LOGIC_VECTOR (14 downto 0); signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC; - signal ap_sig_172 : BOOLEAN; + signal ap_sig_170 : BOOLEAN; signal tmp_5_fu_759_p2 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_5_reg_1170 : STD_LOGIC_VECTOR (7 downto 0); signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC; - signal ap_sig_181 : BOOLEAN; + signal ap_sig_179 : BOOLEAN; signal i_9_fu_770_p2 : STD_LOGIC_VECTOR (14 downto 0); signal i_9_reg_1178 : STD_LOGIC_VECTOR (14 downto 0); signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC; - signal ap_sig_190 : BOOLEAN; + signal ap_sig_188 : BOOLEAN; signal tmp_15_fu_776_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_15_reg_1186 : STD_LOGIC_VECTOR (63 downto 0); signal exitcond7_fu_765_p2 : STD_LOGIC_VECTOR (0 downto 0); @@ -199,22 +195,22 @@ architecture behav of l2_trigger is signal sum_overP1_addr_reg_1236 : STD_LOGIC_VECTOR (10 downto 0); signal sum_overP2_addr_reg_1241 : STD_LOGIC_VECTOR (10 downto 0); signal ap_sig_cseq_ST_st10_fsm_9 : STD_LOGIC; - signal ap_sig_227 : BOOLEAN; + signal ap_sig_225 : BOOLEAN; signal tmp_22_fu_822_p3 : STD_LOGIC_VECTOR (0 downto 0); signal kk_3_fu_950_p2 : STD_LOGIC_VECTOR (3 downto 0); signal ap_sig_cseq_ST_st11_fsm_10 : STD_LOGIC; - signal ap_sig_245 : BOOLEAN; + signal ap_sig_243 : BOOLEAN; signal tmp_24_fu_962_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_24_reg_1269 : STD_LOGIC_VECTOR (31 downto 0); signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC; - signal ap_sig_254 : BOOLEAN; + signal ap_sig_252 : BOOLEAN; signal tmp_25_fu_968_p2 : STD_LOGIC_VECTOR (0 downto 0); signal grp_fu_633_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_36_reg_1282 : STD_LOGIC_VECTOR (0 downto 0); signal i_8_fu_1021_p2 : STD_LOGIC_VECTOR (14 downto 0); signal i_8_reg_1296 : STD_LOGIC_VECTOR (14 downto 0); - signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC; - signal ap_sig_270 : BOOLEAN; + signal ap_sig_cseq_ST_st16_fsm_15 : STD_LOGIC; + signal ap_sig_268 : BOOLEAN; signal exitcond6_fu_1016_p2 : STD_LOGIC_VECTOR (0 downto 0); signal thresh1_addr_1_reg_1311 : STD_LOGIC_VECTOR (10 downto 0); signal thresh2_addr_1_reg_1316 : STD_LOGIC_VECTOR (10 downto 0); @@ -223,14 +219,14 @@ architecture behav of l2_trigger is signal tmp_11_reg_1326 : STD_LOGIC_VECTOR (24 downto 0); signal tmp_12_fu_1086_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_12_reg_1331 : STD_LOGIC_VECTOR (31 downto 0); - signal ap_sig_cseq_ST_st20_fsm_19 : STD_LOGIC; - signal ap_sig_298 : BOOLEAN; + signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC; + signal ap_sig_296 : BOOLEAN; signal tmp_13_fu_1091_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_13_reg_1337 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_14_fu_1096_p2 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_14_reg_1343 : STD_LOGIC_VECTOR (0 downto 0); - signal ap_sig_cseq_ST_st21_fsm_20 : STD_LOGIC; - signal ap_sig_309 : BOOLEAN; + signal ap_sig_cseq_ST_st19_fsm_18 : STD_LOGIC; + signal ap_sig_307 : BOOLEAN; signal sum_overP1_address0 : STD_LOGIC_VECTOR (10 downto 0); signal sum_overP1_ce0 : STD_LOGIC; signal sum_overP1_we0 : STD_LOGIC; @@ -279,35 +275,31 @@ architecture behav of l2_trigger is signal i_2_reg_535 : STD_LOGIC_VECTOR (14 downto 0); signal exitcond8_fu_736_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC; - signal ap_sig_413 : BOOLEAN; + signal ap_sig_411 : BOOLEAN; signal tmp_nbreadreq_fu_226_p9 : STD_LOGIC_VECTOR (0 downto 0); signal k_reg_546 : STD_LOGIC_VECTOR (7 downto 0); signal itrig_reg_557 : STD_LOGIC_VECTOR (31 downto 0); signal i_3_reg_569 : STD_LOGIC_VECTOR (14 downto 0); signal exitcond_fu_753_p2 : STD_LOGIC_VECTOR (0 downto 0); - signal ap_sig_cseq_ST_st15_fsm_14 : STD_LOGIC; - signal ap_sig_439 : BOOLEAN; + signal ap_sig_cseq_ST_st14_fsm_13 : STD_LOGIC; + signal ap_sig_437 : BOOLEAN; signal ap_sig_cseq_ST_st13_fsm_12 : STD_LOGIC; - signal ap_sig_446 : BOOLEAN; + signal ap_sig_444 : BOOLEAN; signal or_cond_fu_979_p2 : STD_LOGIC_VECTOR (0 downto 0); - signal ap_sig_cseq_ST_st17_fsm_16 : STD_LOGIC; - signal ap_sig_457 : BOOLEAN; + signal ap_sig_cseq_ST_st15_fsm_14 : STD_LOGIC; + signal ap_sig_455 : BOOLEAN; signal itrig_1_reg_587 : STD_LOGIC_VECTOR (31 downto 0); signal kk_1_reg_610 : STD_LOGIC_VECTOR (3 downto 0); signal i_4_reg_622 : STD_LOGIC_VECTOR (14 downto 0); - signal ap_sig_cseq_ST_st22_fsm_21 : STD_LOGIC; - signal ap_sig_478 : BOOLEAN; + signal ap_sig_cseq_ST_st20_fsm_19 : STD_LOGIC; + signal ap_sig_476 : BOOLEAN; signal tmp_4_fu_664_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_18_cast_fu_730_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_7_fu_747_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_45_cast_fu_866_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_49_cast_fu_926_p1 : STD_LOGIC_VECTOR (63 downto 0); signal tmp_9_fu_1027_p1 : STD_LOGIC_VECTOR (63 downto 0); - signal ap_sig_cseq_ST_st14_fsm_13 : STD_LOGIC; - signal ap_sig_511 : BOOLEAN; signal tmp_40_cast_fu_998_p1 : STD_LOGIC_VECTOR (31 downto 0); - signal ap_sig_cseq_ST_st16_fsm_15 : STD_LOGIC; - signal ap_sig_520 : BOOLEAN; signal tmp_38_cast_fu_1011_p1 : STD_LOGIC_VECTOR (31 downto 0); signal ap_reg_ioackin_out_stream_TREADY : STD_LOGIC := '0'; signal tmp_18_fu_804_p2 : STD_LOGIC_VECTOR (31 downto 0); @@ -348,7 +340,7 @@ architecture behav of l2_trigger is signal tmp_12_fu_1086_p1 : STD_LOGIC_VECTOR (7 downto 0); signal tmp_13_fu_1091_p0 : STD_LOGIC_VECTOR (27 downto 0); signal tmp_13_fu_1091_p1 : STD_LOGIC_VECTOR (7 downto 0); - signal ap_NS_fsm : STD_LOGIC_VECTOR (21 downto 0); + signal ap_NS_fsm : STD_LOGIC_VECTOR (19 downto 0); signal tmp_12_fu_1086_p00 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_13_fu_1091_p00 : STD_LOGIC_VECTOR (31 downto 0); @@ -590,9 +582,9 @@ begin if (ap_rst_n_inv = '1') then ap_reg_ioackin_out_stream_TREADY <= ap_const_logic_0; else - if ((((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) and not((ap_const_logic_0 = ap_sig_ioackin_out_stream_TREADY))))) then + if ((((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16) and not((ap_const_logic_0 = ap_sig_ioackin_out_stream_TREADY))))) then ap_reg_ioackin_out_stream_TREADY <= ap_const_logic_0; - elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) and (ap_const_logic_1 = out_stream_TREADY)))) then + elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16) and (ap_const_logic_1 = out_stream_TREADY)))) then ap_reg_ioackin_out_stream_TREADY <= ap_const_logic_1; end if; end if; @@ -625,7 +617,7 @@ begin i_3_reg_569_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then - if (((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14) or ((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) and (ap_const_lv1_0 = or_cond_fu_979_p2)) or (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16) or ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) and (ap_const_lv1_0 = grp_fu_633_p2) and not((ap_const_lv1_0 = tmp_25_fu_968_p2))))) then + if (((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) or ((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) and (ap_const_lv1_0 = or_cond_fu_979_p2)) or (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14) or ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) and (ap_const_lv1_0 = grp_fu_633_p2) and not((ap_const_lv1_0 = tmp_25_fu_968_p2))))) then i_3_reg_569 <= i_9_reg_1178; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and (ap_const_lv1_0 = exitcond_fu_753_p2))) then i_3_reg_569 <= ap_const_lv15_0; @@ -638,7 +630,7 @@ begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and not((ap_const_lv1_0 = exitcond_fu_753_p2)))) then i_4_reg_622 <= ap_const_lv15_0; - elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21)) then + elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19)) then i_4_reg_622 <= i_8_reg_1296; end if; end if; @@ -660,7 +652,7 @@ begin if (ap_clk'event and ap_clk = '1') then if ((((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) and (ap_const_lv1_0 = or_cond_fu_979_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) and (ap_const_lv1_0 = grp_fu_633_p2) and not((ap_const_lv1_0 = tmp_25_fu_968_p2))))) then itrig_1_reg_587 <= itrig_1_reg_587; - elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14) or (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16))) then + elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) or (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14))) then itrig_1_reg_587 <= ap_const_lv32_1; elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and (ap_const_lv1_0 = exitcond_fu_753_p2))) then itrig_1_reg_587 <= itrig_reg_557; @@ -739,7 +731,7 @@ begin process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then - if ((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)) then + if ((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) then i_8_reg_1296 <= i_8_fu_1021_p2; end if; end if; @@ -773,7 +765,7 @@ begin process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then - if (((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) and (ap_const_lv1_0 = exitcond6_fu_1016_p2))) then + if (((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15) and (ap_const_lv1_0 = exitcond6_fu_1016_p2))) then thresh1_addr_1_reg_1311 <= tmp_9_fu_1027_p1(11 - 1 downto 0); thresh2_addr_1_reg_1316 <= tmp_9_fu_1027_p1(11 - 1 downto 0); end if; @@ -782,7 +774,7 @@ begin process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then - if (((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) and not((ap_const_logic_0 = ap_sig_ioackin_out_stream_TREADY)))) then + if (((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16) and not((ap_const_logic_0 = ap_sig_ioackin_out_stream_TREADY)))) then tmp_10_reg_1321 <= sum_pix1_q0(31 downto 7); tmp_11_reg_1326 <= sum_pix2_q0(31 downto 7); end if; @@ -791,7 +783,7 @@ begin process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then - if ((ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19)) then + if ((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)) then tmp_12_reg_1331 <= tmp_12_fu_1086_p2; tmp_13_reg_1337 <= tmp_13_fu_1091_p2; end if; @@ -800,7 +792,7 @@ begin process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then - if ((ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20)) then + if ((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18)) then tmp_14_reg_1343 <= tmp_14_fu_1096_p2; end if; end if; @@ -882,7 +874,7 @@ begin end if; when ap_ST_st7_fsm_6 => if (not((ap_const_lv1_0 = exitcond_fu_753_p2))) then - ap_NS_fsm <= ap_ST_st18_fsm_17; + ap_NS_fsm <= ap_ST_st16_fsm_15; else ap_NS_fsm <= ap_ST_st8_fsm_7; end if; @@ -908,7 +900,7 @@ begin ap_NS_fsm <= ap_ST_st10_fsm_9; when ap_ST_st12_fsm_11 => if ((not((ap_const_lv1_0 = tmp_25_fu_968_p2)) and not((ap_const_lv1_0 = grp_fu_633_p2)))) then - ap_NS_fsm <= ap_ST_st16_fsm_15; + ap_NS_fsm <= ap_ST_st15_fsm_14; elsif (((ap_const_lv1_0 = grp_fu_633_p2) and not((ap_const_lv1_0 = tmp_25_fu_968_p2)))) then ap_NS_fsm <= ap_ST_st8_fsm_7; else @@ -921,33 +913,29 @@ begin ap_NS_fsm <= ap_ST_st8_fsm_7; end if; when ap_ST_st14_fsm_13 => - ap_NS_fsm <= ap_ST_st15_fsm_14; + ap_NS_fsm <= ap_ST_st8_fsm_7; when ap_ST_st15_fsm_14 => ap_NS_fsm <= ap_ST_st8_fsm_7; when ap_ST_st16_fsm_15 => - ap_NS_fsm <= ap_ST_st17_fsm_16; - when ap_ST_st17_fsm_16 => - ap_NS_fsm <= ap_ST_st8_fsm_7; - when ap_ST_st18_fsm_17 => if ((ap_const_lv1_0 = exitcond6_fu_1016_p2)) then - ap_NS_fsm <= ap_ST_st19_fsm_18; + ap_NS_fsm <= ap_ST_st17_fsm_16; else ap_NS_fsm <= ap_ST_st5_fsm_4; end if; - when ap_ST_st19_fsm_18 => + when ap_ST_st17_fsm_16 => if (not((ap_const_logic_0 = ap_sig_ioackin_out_stream_TREADY))) then - ap_NS_fsm <= ap_ST_st20_fsm_19; + ap_NS_fsm <= ap_ST_st18_fsm_17; else - ap_NS_fsm <= ap_ST_st19_fsm_18; + ap_NS_fsm <= ap_ST_st17_fsm_16; end if; + when ap_ST_st18_fsm_17 => + ap_NS_fsm <= ap_ST_st19_fsm_18; + when ap_ST_st19_fsm_18 => + ap_NS_fsm <= ap_ST_st20_fsm_19; when ap_ST_st20_fsm_19 => - ap_NS_fsm <= ap_ST_st21_fsm_20; - when ap_ST_st21_fsm_20 => - ap_NS_fsm <= ap_ST_st22_fsm_21; - when ap_ST_st22_fsm_21 => - ap_NS_fsm <= ap_ST_st18_fsm_17; + ap_NS_fsm <= ap_ST_st16_fsm_15; when others => - ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXX"; + ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXX"; end case; end process; @@ -987,141 +975,129 @@ begin end process; - ap_sig_139_assign_proc : process(ap_CS_fsm) + ap_sig_137_assign_proc : process(ap_CS_fsm) begin - ap_sig_139 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1)); + ap_sig_137 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1)); end process; - ap_sig_148_assign_proc : process(ap_CS_fsm) + ap_sig_146_assign_proc : process(ap_CS_fsm) begin - ap_sig_148 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2)); + ap_sig_146 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2)); end process; - ap_sig_163_assign_proc : process(ap_CS_fsm) + ap_sig_161_assign_proc : process(ap_CS_fsm) begin - ap_sig_163 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3)); + ap_sig_161 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3)); end process; - ap_sig_172_assign_proc : process(ap_CS_fsm) + ap_sig_170_assign_proc : process(ap_CS_fsm) begin - ap_sig_172 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5)); + ap_sig_170 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5)); end process; - ap_sig_181_assign_proc : process(ap_CS_fsm) + ap_sig_179_assign_proc : process(ap_CS_fsm) begin - ap_sig_181 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6)); + ap_sig_179 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6)); end process; - ap_sig_190_assign_proc : process(ap_CS_fsm) + ap_sig_188_assign_proc : process(ap_CS_fsm) begin - ap_sig_190 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7)); + ap_sig_188 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7)); end process; - ap_sig_227_assign_proc : process(ap_CS_fsm) + ap_sig_225_assign_proc : process(ap_CS_fsm) begin - ap_sig_227 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9)); + ap_sig_225 <= (ap_const_lv1_1 = ap_CS_fsm(9 downto 9)); end process; - ap_sig_245_assign_proc : process(ap_CS_fsm) + ap_sig_243_assign_proc : process(ap_CS_fsm) begin - ap_sig_245 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10)); + ap_sig_243 <= (ap_const_lv1_1 = ap_CS_fsm(10 downto 10)); end process; - ap_sig_254_assign_proc : process(ap_CS_fsm) + ap_sig_252_assign_proc : process(ap_CS_fsm) begin - ap_sig_254 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11)); + ap_sig_252 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11)); end process; - ap_sig_270_assign_proc : process(ap_CS_fsm) + ap_sig_268_assign_proc : process(ap_CS_fsm) begin - ap_sig_270 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17)); + ap_sig_268 <= (ap_const_lv1_1 = ap_CS_fsm(15 downto 15)); end process; - ap_sig_298_assign_proc : process(ap_CS_fsm) + ap_sig_296_assign_proc : process(ap_CS_fsm) begin - ap_sig_298 <= (ap_const_lv1_1 = ap_CS_fsm(19 downto 19)); + ap_sig_296 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17)); end process; - ap_sig_309_assign_proc : process(ap_CS_fsm) + ap_sig_307_assign_proc : process(ap_CS_fsm) begin - ap_sig_309 <= (ap_const_lv1_1 = ap_CS_fsm(20 downto 20)); + ap_sig_307 <= (ap_const_lv1_1 = ap_CS_fsm(18 downto 18)); end process; - ap_sig_39_assign_proc : process(ap_CS_fsm) + ap_sig_37_assign_proc : process(ap_CS_fsm) begin - ap_sig_39 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1); + ap_sig_37 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1); end process; - ap_sig_413_assign_proc : process(ap_CS_fsm) + ap_sig_411_assign_proc : process(ap_CS_fsm) begin - ap_sig_413 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4)); + ap_sig_411 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4)); end process; - ap_sig_439_assign_proc : process(ap_CS_fsm) + ap_sig_437_assign_proc : process(ap_CS_fsm) begin - ap_sig_439 <= (ap_const_lv1_1 = ap_CS_fsm(14 downto 14)); + ap_sig_437 <= (ap_const_lv1_1 = ap_CS_fsm(13 downto 13)); end process; - ap_sig_446_assign_proc : process(ap_CS_fsm) + ap_sig_444_assign_proc : process(ap_CS_fsm) begin - ap_sig_446 <= (ap_const_lv1_1 = ap_CS_fsm(12 downto 12)); + ap_sig_444 <= (ap_const_lv1_1 = ap_CS_fsm(12 downto 12)); end process; - ap_sig_457_assign_proc : process(ap_CS_fsm) + ap_sig_455_assign_proc : process(ap_CS_fsm) begin - ap_sig_457 <= (ap_const_lv1_1 = ap_CS_fsm(16 downto 16)); + ap_sig_455 <= (ap_const_lv1_1 = ap_CS_fsm(14 downto 14)); end process; - ap_sig_478_assign_proc : process(ap_CS_fsm) + ap_sig_476_assign_proc : process(ap_CS_fsm) begin - ap_sig_478 <= (ap_const_lv1_1 = ap_CS_fsm(21 downto 21)); + ap_sig_476 <= (ap_const_lv1_1 = ap_CS_fsm(19 downto 19)); end process; - ap_sig_511_assign_proc : process(ap_CS_fsm) + ap_sig_75_assign_proc : process(ap_CS_fsm) begin - ap_sig_511 <= (ap_const_lv1_1 = ap_CS_fsm(13 downto 13)); + ap_sig_75 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8)); end process; - ap_sig_520_assign_proc : process(ap_CS_fsm) + ap_sig_83_assign_proc : process(ap_CS_fsm) begin - ap_sig_520 <= (ap_const_lv1_1 = ap_CS_fsm(15 downto 15)); + ap_sig_83 <= (ap_const_lv1_1 = ap_CS_fsm(16 downto 16)); end process; - ap_sig_77_assign_proc : process(ap_CS_fsm) + ap_sig_cseq_ST_st10_fsm_9_assign_proc : process(ap_sig_225) begin - ap_sig_77 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8)); - end process; - - - ap_sig_85_assign_proc : process(ap_CS_fsm) - begin - ap_sig_85 <= (ap_const_lv1_1 = ap_CS_fsm(18 downto 18)); - end process; - - - ap_sig_cseq_ST_st10_fsm_9_assign_proc : process(ap_sig_227) - begin - if (ap_sig_227) then + if (ap_sig_225) then ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_1; else ap_sig_cseq_ST_st10_fsm_9 <= ap_const_logic_0; @@ -1129,9 +1105,9 @@ begin end process; - ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_245) + ap_sig_cseq_ST_st11_fsm_10_assign_proc : process(ap_sig_243) begin - if (ap_sig_245) then + if (ap_sig_243) then ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_1; else ap_sig_cseq_ST_st11_fsm_10 <= ap_const_logic_0; @@ -1139,9 +1115,9 @@ begin end process; - ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_254) + ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_252) begin - if (ap_sig_254) then + if (ap_sig_252) then ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1; else ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0; @@ -1149,9 +1125,9 @@ begin end process; - ap_sig_cseq_ST_st13_fsm_12_assign_proc : process(ap_sig_446) + ap_sig_cseq_ST_st13_fsm_12_assign_proc : process(ap_sig_444) begin - if (ap_sig_446) then + if (ap_sig_444) then ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_1; else ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_0; @@ -1159,9 +1135,9 @@ begin end process; - ap_sig_cseq_ST_st14_fsm_13_assign_proc : process(ap_sig_511) + ap_sig_cseq_ST_st14_fsm_13_assign_proc : process(ap_sig_437) begin - if (ap_sig_511) then + if (ap_sig_437) then ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_1; else ap_sig_cseq_ST_st14_fsm_13 <= ap_const_logic_0; @@ -1169,9 +1145,9 @@ begin end process; - ap_sig_cseq_ST_st15_fsm_14_assign_proc : process(ap_sig_439) + ap_sig_cseq_ST_st15_fsm_14_assign_proc : process(ap_sig_455) begin - if (ap_sig_439) then + if (ap_sig_455) then ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_1; else ap_sig_cseq_ST_st15_fsm_14 <= ap_const_logic_0; @@ -1179,9 +1155,9 @@ begin end process; - ap_sig_cseq_ST_st16_fsm_15_assign_proc : process(ap_sig_520) + ap_sig_cseq_ST_st16_fsm_15_assign_proc : process(ap_sig_268) begin - if (ap_sig_520) then + if (ap_sig_268) then ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_1; else ap_sig_cseq_ST_st16_fsm_15 <= ap_const_logic_0; @@ -1189,9 +1165,9 @@ begin end process; - ap_sig_cseq_ST_st17_fsm_16_assign_proc : process(ap_sig_457) + ap_sig_cseq_ST_st17_fsm_16_assign_proc : process(ap_sig_83) begin - if (ap_sig_457) then + if (ap_sig_83) then ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_1; else ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_0; @@ -1199,9 +1175,9 @@ begin end process; - ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_270) + ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_296) begin - if (ap_sig_270) then + if (ap_sig_296) then ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1; else ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0; @@ -1209,9 +1185,9 @@ begin end process; - ap_sig_cseq_ST_st19_fsm_18_assign_proc : process(ap_sig_85) + ap_sig_cseq_ST_st19_fsm_18_assign_proc : process(ap_sig_307) begin - if (ap_sig_85) then + if (ap_sig_307) then ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_1; else ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_0; @@ -1219,9 +1195,9 @@ begin end process; - ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_39) + ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_37) begin - if (ap_sig_39) then + if (ap_sig_37) then ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1; else ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0; @@ -1229,9 +1205,9 @@ begin end process; - ap_sig_cseq_ST_st20_fsm_19_assign_proc : process(ap_sig_298) + ap_sig_cseq_ST_st20_fsm_19_assign_proc : process(ap_sig_476) begin - if (ap_sig_298) then + if (ap_sig_476) then ap_sig_cseq_ST_st20_fsm_19 <= ap_const_logic_1; else ap_sig_cseq_ST_st20_fsm_19 <= ap_const_logic_0; @@ -1239,29 +1215,9 @@ begin end process; - ap_sig_cseq_ST_st21_fsm_20_assign_proc : process(ap_sig_309) - begin - if (ap_sig_309) then - ap_sig_cseq_ST_st21_fsm_20 <= ap_const_logic_1; - else - ap_sig_cseq_ST_st21_fsm_20 <= ap_const_logic_0; - end if; - end process; - - - ap_sig_cseq_ST_st22_fsm_21_assign_proc : process(ap_sig_478) - begin - if (ap_sig_478) then - ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_1; - else - ap_sig_cseq_ST_st22_fsm_21 <= ap_const_logic_0; - end if; - end process; - - - ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_139) + ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_137) begin - if (ap_sig_139) then + if (ap_sig_137) then ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1; else ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0; @@ -1269,9 +1225,9 @@ begin end process; - ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_148) + ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_146) begin - if (ap_sig_148) then + if (ap_sig_146) then ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1; else ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0; @@ -1279,9 +1235,9 @@ begin end process; - ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_163) + ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_161) begin - if (ap_sig_163) then + if (ap_sig_161) then ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1; else ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0; @@ -1289,9 +1245,9 @@ begin end process; - ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_413) + ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_411) begin - if (ap_sig_413) then + if (ap_sig_411) then ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1; else ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0; @@ -1299,9 +1255,9 @@ begin end process; - ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_172) + ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_170) begin - if (ap_sig_172) then + if (ap_sig_170) then ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1; else ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0; @@ -1309,9 +1265,9 @@ begin end process; - ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_181) + ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_179) begin - if (ap_sig_181) then + if (ap_sig_179) then ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1; else ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0; @@ -1319,9 +1275,9 @@ begin end process; - ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_190) + ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_188) begin - if (ap_sig_190) then + if (ap_sig_188) then ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1; else ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0; @@ -1329,9 +1285,9 @@ begin end process; - ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_77) + ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_75) begin - if (ap_sig_77) then + if (ap_sig_75) then ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1; else ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0; @@ -1490,9 +1446,9 @@ begin or_cond_fu_979_p2 <= (tmp_35_fu_974_p2 and tmp_36_reg_1282); out_stream_TDATA <= (sum_pix2_q0 & sum_pix1_q0); - out_stream_TDATA_blk_n_assign_proc : process(out_stream_TREADY, ap_sig_cseq_ST_st19_fsm_18) + out_stream_TDATA_blk_n_assign_proc : process(out_stream_TREADY, ap_sig_cseq_ST_st17_fsm_16) begin - if ((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18)) then + if ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) then out_stream_TDATA_blk_n <= out_stream_TREADY; else out_stream_TDATA_blk_n <= ap_const_logic_1; @@ -1506,9 +1462,9 @@ begin out_stream_TSTRB <= ap_const_lv8_FF; out_stream_TUSER <= ap_const_lv2_0; - out_stream_TVALID_assign_proc : process(ap_sig_cseq_ST_st19_fsm_18, ap_reg_ioackin_out_stream_TREADY) + out_stream_TVALID_assign_proc : process(ap_sig_cseq_ST_st17_fsm_16, ap_reg_ioackin_out_stream_TREADY) begin - if ((((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) and (ap_const_logic_0 = ap_reg_ioackin_out_stream_TREADY)))) then + if ((((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16) and (ap_const_logic_0 = ap_reg_ioackin_out_stream_TREADY)))) then out_stream_TVALID <= ap_const_logic_1; else out_stream_TVALID <= ap_const_logic_0; @@ -1617,7 +1573,7 @@ begin end process; - sum_pix1_address0_assign_proc : process(ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st8_fsm_7, tmp_15_fu_776_p1, sum_pix1_addr_3_reg_1196, ap_sig_cseq_ST_st18_fsm_17, tmp_4_fu_664_p1, tmp_7_fu_747_p1, tmp_9_fu_1027_p1) + sum_pix1_address0_assign_proc : process(ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st8_fsm_7, tmp_15_fu_776_p1, sum_pix1_addr_3_reg_1196, ap_sig_cseq_ST_st16_fsm_15, tmp_4_fu_664_p1, tmp_7_fu_747_p1, tmp_9_fu_1027_p1) begin if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then sum_pix1_address0 <= sum_pix1_addr_3_reg_1196; @@ -1625,7 +1581,7 @@ begin sum_pix1_address0 <= tmp_7_fu_747_p1(11 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then sum_pix1_address0 <= tmp_4_fu_664_p1(11 - 1 downto 0); - elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)) then + elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) then sum_pix1_address0 <= tmp_9_fu_1027_p1(11 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then sum_pix1_address0 <= tmp_15_fu_776_p1(11 - 1 downto 0); @@ -1635,9 +1591,9 @@ begin end process; - sum_pix1_ce0_assign_proc : process(in_stream_TVALID, ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st18_fsm_17) + sum_pix1_ce0_assign_proc : process(in_stream_TVALID, ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st16_fsm_15) begin - if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) and not((in_stream_TVALID = ap_const_logic_0))) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17))) then + if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) and not((in_stream_TVALID = ap_const_logic_0))) or (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15))) then sum_pix1_ce0 <= ap_const_logic_1; else sum_pix1_ce0 <= ap_const_logic_0; @@ -1667,7 +1623,7 @@ begin end process; - sum_pix2_address0_assign_proc : process(ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st8_fsm_7, tmp_15_fu_776_p1, sum_pix2_addr_3_reg_1201, ap_sig_cseq_ST_st18_fsm_17, tmp_4_fu_664_p1, tmp_7_fu_747_p1, tmp_9_fu_1027_p1) + sum_pix2_address0_assign_proc : process(ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st8_fsm_7, tmp_15_fu_776_p1, sum_pix2_addr_3_reg_1201, ap_sig_cseq_ST_st16_fsm_15, tmp_4_fu_664_p1, tmp_7_fu_747_p1, tmp_9_fu_1027_p1) begin if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then sum_pix2_address0 <= sum_pix2_addr_3_reg_1201; @@ -1675,7 +1631,7 @@ begin sum_pix2_address0 <= tmp_7_fu_747_p1(11 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then sum_pix2_address0 <= tmp_4_fu_664_p1(11 - 1 downto 0); - elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17)) then + elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15)) then sum_pix2_address0 <= tmp_9_fu_1027_p1(11 - 1 downto 0); elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then sum_pix2_address0 <= tmp_15_fu_776_p1(11 - 1 downto 0); @@ -1685,9 +1641,9 @@ begin end process; - sum_pix2_ce0_assign_proc : process(in_stream_TVALID, ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st18_fsm_17) + sum_pix2_ce0_assign_proc : process(in_stream_TVALID, ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st6_fsm_5, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st16_fsm_15) begin - if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) and not((in_stream_TVALID = ap_const_logic_0))) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17))) then + if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) and not((in_stream_TVALID = ap_const_logic_0))) or (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15))) then sum_pix2_ce0 <= ap_const_logic_1; else sum_pix2_ce0 <= ap_const_logic_0; @@ -1719,9 +1675,9 @@ begin sum_pixP1_fu_1064_p3 <= (tmp_10_reg_1321 & ap_const_lv3_0); sum_pixP2_fu_1075_p3 <= (tmp_11_reg_1326 & ap_const_lv3_0); - thresh1_address0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_15_reg_1186, ap_sig_cseq_ST_st10_fsm_9, thresh1_addr_1_reg_1311, ap_sig_cseq_ST_st21_fsm_20, ap_sig_cseq_ST_st22_fsm_21, tmp_4_fu_664_p1) + thresh1_address0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_15_reg_1186, ap_sig_cseq_ST_st10_fsm_9, thresh1_addr_1_reg_1311, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st20_fsm_19, tmp_4_fu_664_p1) begin - if (((ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20) or (ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21))) then + if (((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) or (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19))) then thresh1_address0 <= thresh1_addr_1_reg_1311; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then thresh1_address0 <= tmp_4_fu_664_p1(11 - 1 downto 0); @@ -1733,9 +1689,9 @@ begin end process; - thresh1_ce0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st21_fsm_20, ap_sig_cseq_ST_st22_fsm_21) + thresh1_ce0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st10_fsm_9, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st20_fsm_19) begin - if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9) or (ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20) or (ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21))) then + if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st10_fsm_9) or (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) or (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19))) then thresh1_ce0 <= ap_const_logic_1; else thresh1_ce0 <= ap_const_logic_0; @@ -1743,11 +1699,11 @@ begin end process; - thresh1_d0_assign_proc : process(LOW_THRESH_read_reg_1104, ap_sig_cseq_ST_st2_fsm_1, tmp_12_reg_1331, ap_sig_cseq_ST_st21_fsm_20, ap_sig_cseq_ST_st22_fsm_21) + thresh1_d0_assign_proc : process(LOW_THRESH_read_reg_1104, ap_sig_cseq_ST_st2_fsm_1, tmp_12_reg_1331, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st20_fsm_19) begin - if ((ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21)) then + if ((ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19)) then thresh1_d0 <= LOW_THRESH_read_reg_1104; - elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20)) then + elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18)) then thresh1_d0 <= tmp_12_reg_1331; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then thresh1_d0 <= ap_const_lv32_639C; @@ -1757,9 +1713,9 @@ begin end process; - thresh1_we0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_14_reg_1343, ap_sig_cseq_ST_st21_fsm_20, exitcond2_fu_653_p2, ap_sig_cseq_ST_st22_fsm_21) + thresh1_we0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_14_reg_1343, ap_sig_cseq_ST_st19_fsm_18, exitcond2_fu_653_p2, ap_sig_cseq_ST_st20_fsm_19) begin - if (((ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond2_fu_653_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21) and not((ap_const_lv1_0 = tmp_14_reg_1343))))) then + if (((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond2_fu_653_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19) and not((ap_const_lv1_0 = tmp_14_reg_1343))))) then thresh1_we0 <= ap_const_logic_1; else thresh1_we0 <= ap_const_logic_0; @@ -1767,9 +1723,9 @@ begin end process; - thresh2_address0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_15_reg_1186, ap_sig_cseq_ST_st12_fsm_11, thresh2_addr_1_reg_1316, ap_sig_cseq_ST_st21_fsm_20, ap_sig_cseq_ST_st22_fsm_21, tmp_4_fu_664_p1) + thresh2_address0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, tmp_15_reg_1186, ap_sig_cseq_ST_st12_fsm_11, thresh2_addr_1_reg_1316, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st20_fsm_19, tmp_4_fu_664_p1) begin - if (((ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20) or (ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21))) then + if (((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) or (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19))) then thresh2_address0 <= thresh2_addr_1_reg_1316; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then thresh2_address0 <= tmp_4_fu_664_p1(11 - 1 downto 0); @@ -1781,9 +1737,9 @@ begin end process; - thresh2_ce0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st21_fsm_20, ap_sig_cseq_ST_st22_fsm_21) + thresh2_ce0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st12_fsm_11, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st20_fsm_19) begin - if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20) or (ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21))) then + if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) or (ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19))) then thresh2_ce0 <= ap_const_logic_1; else thresh2_ce0 <= ap_const_logic_0; @@ -1791,11 +1747,11 @@ begin end process; - thresh2_d0_assign_proc : process(LOW_THRESH_read_reg_1104, ap_sig_cseq_ST_st2_fsm_1, tmp_13_reg_1337, ap_sig_cseq_ST_st21_fsm_20, ap_sig_cseq_ST_st22_fsm_21) + thresh2_d0_assign_proc : process(LOW_THRESH_read_reg_1104, ap_sig_cseq_ST_st2_fsm_1, tmp_13_reg_1337, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st20_fsm_19) begin - if ((ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21)) then + if ((ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19)) then thresh2_d0 <= LOW_THRESH_read_reg_1104; - elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20)) then + elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18)) then thresh2_d0 <= tmp_13_reg_1337; elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then thresh2_d0 <= ap_const_lv32_639C; @@ -1805,9 +1761,9 @@ begin end process; - thresh2_we0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st21_fsm_20, exitcond2_fu_653_p2, ap_sig_cseq_ST_st22_fsm_21, tmp_21_fu_1100_p2) + thresh2_we0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st19_fsm_18, exitcond2_fu_653_p2, ap_sig_cseq_ST_st20_fsm_19, tmp_21_fu_1100_p2) begin - if (((ap_const_logic_1 = ap_sig_cseq_ST_st21_fsm_20) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond2_fu_653_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st22_fsm_21) and not((ap_const_lv1_0 = tmp_21_fu_1100_p2))))) then + if (((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) or ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = exitcond2_fu_653_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st20_fsm_19) and not((ap_const_lv1_0 = tmp_21_fu_1100_p2))))) then thresh2_we0 <= ap_const_logic_1; else thresh2_we0 <= ap_const_logic_0; @@ -1871,15 +1827,11 @@ begin tmp_nbreadreq_fu_226_p9 <= (0=>(in_stream_TVALID), others=>'-'); tmp_s_fu_696_p3 <= (kk_reg_513 & ap_const_lv7_0); - trig_data_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st12_fsm_11, tmp_25_fu_968_p2, grp_fu_633_p2, ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st13_fsm_12, or_cond_fu_979_p2, ap_sig_cseq_ST_st17_fsm_16, ap_sig_cseq_ST_st14_fsm_13, tmp_40_cast_fu_998_p1, ap_sig_cseq_ST_st16_fsm_15, tmp_38_cast_fu_1011_p1) + trig_data_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st12_fsm_11, tmp_25_fu_968_p2, grp_fu_633_p2, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st13_fsm_12, or_cond_fu_979_p2, ap_sig_cseq_ST_st15_fsm_14) begin - if ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) then - trig_data <= tmp_38_cast_fu_1011_p1; - elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then - trig_data <= tmp_40_cast_fu_998_p1; - elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) and not((ap_const_lv1_0 = tmp_25_fu_968_p2)) and not((ap_const_lv1_0 = grp_fu_633_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) and not((ap_const_lv1_0 = or_cond_fu_979_p2))))) then + if ((((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) and not((ap_const_lv1_0 = tmp_25_fu_968_p2)) and not((ap_const_lv1_0 = grp_fu_633_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) and not((ap_const_lv1_0 = or_cond_fu_979_p2))))) then trig_data <= ap_const_lv32_1; - elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0))) or (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) or (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15))) then + elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0))) or (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) or (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14))) then trig_data <= ap_const_lv32_0; else trig_data <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; @@ -1887,20 +1839,33 @@ begin end process; - trig_data_ap_vld_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st12_fsm_11, tmp_25_fu_968_p2, grp_fu_633_p2, ap_sig_cseq_ST_st15_fsm_14, ap_sig_cseq_ST_st13_fsm_12, or_cond_fu_979_p2, ap_sig_cseq_ST_st17_fsm_16, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st16_fsm_15) + trig_data_ap_vld_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st12_fsm_11, tmp_25_fu_968_p2, grp_fu_633_p2, ap_sig_cseq_ST_st14_fsm_13, ap_sig_cseq_ST_st13_fsm_12, or_cond_fu_979_p2, ap_sig_cseq_ST_st15_fsm_14) begin - if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0))) or (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14) or (ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16) or ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) and not((ap_const_lv1_0 = tmp_25_fu_968_p2)) and not((ap_const_lv1_0 = grp_fu_633_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) and not((ap_const_lv1_0 = or_cond_fu_979_p2))) or (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) or (ap_const_logic_1 = ap_sig_cseq_ST_st16_fsm_15))) then + if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0))) or (ap_const_logic_1 = ap_sig_cseq_ST_st14_fsm_13) or (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14) or ((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) and not((ap_const_lv1_0 = tmp_25_fu_968_p2)) and not((ap_const_lv1_0 = grp_fu_633_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) and not((ap_const_lv1_0 = or_cond_fu_979_p2))))) then trig_data_ap_vld <= ap_const_logic_1; else trig_data_ap_vld <= ap_const_logic_0; end if; end process; - trig_pixel <= ap_const_lv32_0; - trig_pixel_ap_vld_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0) + trig_pixel_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st13_fsm_12, or_cond_fu_979_p2, ap_sig_cseq_ST_st15_fsm_14, tmp_40_cast_fu_998_p1, tmp_38_cast_fu_1011_p1) + begin + if ((ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14)) then + trig_pixel <= tmp_38_cast_fu_1011_p1; + elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) and not((ap_const_lv1_0 = or_cond_fu_979_p2)))) then + trig_pixel <= tmp_40_cast_fu_998_p1; + elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then + trig_pixel <= ap_const_lv32_0; + else + trig_pixel <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX"; + end if; + end process; + + + trig_pixel_ap_vld_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st13_fsm_12, or_cond_fu_979_p2, ap_sig_cseq_ST_st15_fsm_14) begin - if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then + if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0))) or (ap_const_logic_1 = ap_sig_cseq_ST_st15_fsm_14) or ((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) and not((ap_const_lv1_0 = or_cond_fu_979_p2))))) then trig_pixel_ap_vld <= ap_const_logic_1; else trig_pixel_ap_vld <= ap_const_logic_0;