diff --git a/README.md b/README.md index 0a6d97d24..850b06682 100644 --- a/README.md +++ b/README.md @@ -336,7 +336,7 @@ by [MNT Bench](https://www.cda.cit.tum.de/mntbench/). ## Reference -Since *fiction* is academic software, we would be thankful if you referred to it by citing the following publication: +Since *fiction* is academic software, we would be thankful if you referred to it by citing the following publications: ```bibtex @misc{fiction, @@ -350,6 +350,18 @@ Since *fiction* is academic software, we would be thankful if you referred to it } ``` +and + +```bibtex +@inproceedings{mnt, + author = {Walter, Marcel and Drewniok, Jan and Hofmann, Simon and Hien, Benjamin and Wille, Robert}, + title = {{The Munich Nanotech Toolkit (MNT)}}, + booktitle = {IEEE International Conference on Nanotechnology (IEEE NANO)}, + pages = {454--459}, + year = {2024} +} +``` + Additionally, many algorithms implemented in *fiction* have been published individually. For a full list of publications, please refer to the [documentation](https://fiction.readthedocs.io/en/latest/publications.html). diff --git a/bindings/pyfiction/include/pyfiction/pybind11_mkdoc_docstrings.hpp b/bindings/pyfiction/include/pyfiction/pybind11_mkdoc_docstrings.hpp index 7e58d5067..90f7ab620 100644 --- a/bindings/pyfiction/include/pyfiction/pybind11_mkdoc_docstrings.hpp +++ b/bindings/pyfiction/include/pyfiction/pybind11_mkdoc_docstrings.hpp @@ -8107,17 +8107,23 @@ Parameter ``n``: distributing k entities on n positions.)doc"; static const char *__doc_fiction_determine_clocking = -R"doc(Determines clock numbers for the given gate-level layout. This -algorithm parses the layout's gate and wire connections, disregarding -any existing clocking information, and constructs a SAT instance to -find a valid clock number assignment under which the information flow -is respected. It then assigns these clock numbers as an irregular -clock map to the given layout via the `assign_clock_number` function, -overriding any existing clocking scheme. +R"doc(Determines clock numbers for the given (unclocked) gate-level layout. +This algorithm parses the layout's gate and wire connections, +disregarding any existing clocking information, and constructs a SAT +instance to find a valid clock number assignment under which the +information flow is respected. It then assigns these clock numbers as +an irregular clock map to the given layout via the +`assign_clock_number` function, overriding any existing clocking +scheme. If no valid clock number assignment exists for `lyt`, this function returns `false` and does not modify `lyt`. +This algorithm was proposed in \"Ending the Tyranny of the Clock: SAT- +based Clock Number Assignment for Field-coupled Nanotechnologies\" by +M. Walter, J. Drewniok, and R. Wille in IEEE NANO 2024 +(https://ieeexplore.ieee.org/abstract/document/10628908). + Template parameter ``Lyt``: Gate-level layout type. @@ -10877,6 +10883,11 @@ the search space graph to find other complete layouts with lower cost. Exclusively generates 2DDWave-clocked layouts. +This algorithm was proposed in \"A* is Born: Efficient and Scalable +Physical Design for Field-coupled Nanocomputing\" by S. Hofmann, M. +Walter, and R. Wille in IEEE NANO 2024 +(https://ieeexplore.ieee.org/document/10628808). + Template parameter ``Lyt``: Cartesian gate-level layout type. @@ -13244,7 +13255,7 @@ circuit remains functional even in the presence of defects. This methodology is detailed in the paper "On-the-fly Defect-Aware Design of Circuits based on Silicon Dangling Bond Logic" by J. Drewniok, M. Walter, S. S. H. Ng, K. Walus, and R. Wille, IEEE NANO -2024. +2024 (https://ieeexplore.ieee.org/abstract/document/10628962). Template parameter ``Ntk``: The type of the input network. @@ -13255,7 +13266,7 @@ Template parameter ``CellLyt``: Template parameter ``GateLyt``: Gate-level layout type. -Parameter ``network``: +Parameter ``ntk``: The input network to be mapped onto the defective surface. Parameter ``lattice_tiling``: @@ -14072,7 +14083,8 @@ static const char *__doc_fiction_port_position_y = R"doc()doc"; static const char *__doc_fiction_post_layout_optimization = R"doc(A post-layout optimization algorithm as originally proposed in \"Post- Layout Optimization for Field-coupled Nanotechnologies\" by S. -Hofmann, M. Walter, and R. Wille in NANOARCH 2023. It can be used to +Hofmann, M. Walter, and R. Wille in NANOARCH 2023 +(https://dl.acm.org/doi/10.1145/3611315.3633247). It can be used to reduce the area of a given sub-optimal Cartesian gate-level layout created by heuristics or machine learning. This optimization utilizes the distinct characteristics of the 2DDWave clocking scheme, which diff --git a/docs/algorithms/determine_clocking.rst b/docs/algorithms/determine_clocking.rst index 430bd0908..d611a10c2 100644 --- a/docs/algorithms/determine_clocking.rst +++ b/docs/algorithms/determine_clocking.rst @@ -1,4 +1,4 @@ -.. _determine-clocking: +.. _determine_clocking: Determine Clocking ------------------ diff --git a/docs/publications.rst b/docs/publications.rst index 6f5e35bb5..c69caecb7 100644 --- a/docs/publications.rst +++ b/docs/publications.rst @@ -24,6 +24,21 @@ If you use *fiction* in your work, we would appreciate if you cited month = {May} } +and + + Marcel Walter, Jan Drewniok, Simon Hofmann, Benjamin Hien, and Robert Wille: "The Munich Nanotech Toolkit (MNT)", + IEEE International Conference on Nanotechnology (IEEE NANO), 2024. + +.. code-block:: tex + + @inproceedings{mnt, + author = {Walter, Marcel and Drewniok, Jan and Hofmann, Simon and Hien, Benjamin and Wille, Robert}, + title = {{The Munich Nanotech Toolkit (MNT)}}, + booktitle = {IEEE International Conference on Nanotechnology (IEEE NANO)}, + pages = {454--459}, + year = {2024} + } + Furthermore, if you use any of the design automation algorithms, please consider citing their respective papers as well. * :ref:`Exact physical design ` (``exact``): @@ -86,6 +101,8 @@ Furthermore, if you use any of the design automation algorithms, please consider year={2022} } + `Multi-path routing experiment script `_ + * :ref:`QuickSim ` (``quicksim``): .. code-block:: tex @@ -98,6 +115,8 @@ Furthermore, if you use any of the design automation algorithms, please consider year={2023} } + `QuickSim experiment script `_ + * :ref:`QuickExact ` (``quickexact``): .. code-block:: tex @@ -110,6 +129,8 @@ Furthermore, if you use any of the design automation algorithms, please consider year={2024} } + `QuickExact experiment script `_ + * :ref:`Critical temperature simulation ` (``critical_temperature``): .. code-block:: tex @@ -122,7 +143,7 @@ Furthermore, if you use any of the design automation algorithms, please consider year={2023} } -* :ref:`Operational Domain computation ` (``opdom``): +* :ref:`Operational domain computation ` (``opdom``): .. code-block:: tex @@ -133,7 +154,9 @@ Furthermore, if you use any of the design automation algorithms, please consider year={2023} } -* :ref:`SiDB Gate Design ` (``gate_design``): + `Operational domain experiment scripts `_ + +* :ref:`SiDB gate design ` (``gate_design``): .. code-block:: tex @@ -156,6 +179,7 @@ Furthermore, if you use any of the design automation algorithms, please consider year={2023} } + `Hexagonalization experiment script `_ * :ref:`Post-layout optimization ` (``post_layout_optimization``): @@ -168,6 +192,74 @@ Furthermore, if you use any of the design automation algorithms, please consider year={2023} } + `Post-layout optimization experiment script `_ + +* :ref:`Graph-oriented layout design ` (``gold``): + + .. code-block:: tex + + @inproceedings{hofmann2024gold, + title={{A* is Born: Efficient and Scalable Physical Design for Field-coupled Nanocomputing}}, + author={Hofmann, Simon and Walter, Marcel and Wille, Robert}, + booktitle={IEEE International Conference on Nanotechnology (IEEE NANO)}, + pages={80--85}, + year={2024} + } + + `Graph-oriented layout design experiment script `_ + +* :ref:`SAT-based clock number assignment `: + + .. code-block:: tex + + @inproceedings{walter2024clocknumber, + title={{Ending the Tyranny of the Clock: SAT-Based Clock Number Assignment for Field-coupled Nanotechnologies}}, + author={Walter, Marcel and Drewniok, Jan and Wille, Robert}, + booktitle={IEEE International Conference on Nanotechnology (IEEE NANO)}, + pages={68--73}, + year={2024} + } + + `Clock number assignment experiment script `_ + +* :ref:`On-the-fly Defect-Aware Design of Circuits `: + + .. code-block:: tex + + @inproceedings{drewniok2024ontheflydesign, + title={{On-the-fly Defect-Aware Design of Circuits based on Silicon Dangling Bond Logic}}, + author={Drewniok, Jan and Walter, Marcel and Hang Ng, Samuel Sze and Walus, Konrad and Wille, Robert}, + booktitle={IEEE International Conference on Nanotechnology (IEEE NANO)}, + pages={30--35}, + year={2024} + } + + `On-the-fly defect-aware design of circuits experiment script `_ + +* :ref:`Unifying Figures of Merit for Silicon Dangling Bond Logic`: + + .. code-block:: tex + + @inproceedings{drewniok2024figuresofmerit, + title={{Unifying Figures of Merit: A Versatile Cost Function for Silicon Dangling Bond Logic}}, + author={Drewniok, Jan and Walter, Marcel and Hang Ng, Samuel Sze and Walus, Konrad and Wille, Robert}, + booktitle={IEEE International Conference on Nanotechnology (IEEE NANO)}, + pages={91--96}, + year={2024} + } + +* :ref:`Alternative Silicon Orientations `: + + .. code-block:: tex + + @inproceedings{ng2024latorientations, + title={{Unlocking Flexible Silicon Dangling Bond Logic Designs on Alternative Silicon Orientations}}, + author={Ng, Samuel Sze Hang and Drewniok, Jan and Walter, Marcel and Retallick, Jacob and Wille, Robert and Walus, Konrad}, + booktitle={IEEE International Conference on Nanotechnology (IEEE NANO)}, + pages={57--92}, + year={2024} + } + * :ref:`SiDB Bestagon library `: .. code-block:: tex @@ -179,3 +271,5 @@ Furthermore, if you use any of the design automation algorithms, please consider pages = {739--744}, year={2022} } + + `Bestagon experiment script `_ diff --git a/docs/technology/hsi_lattices.rst b/docs/technology/hsi_lattices.rst index 55c20550b..8539d15cb 100644 --- a/docs/technology/hsi_lattices.rst +++ b/docs/technology/hsi_lattices.rst @@ -1,3 +1,5 @@ +.. _alternative_hsi_lattices: + H-Si Lattice Orientations ========================= diff --git a/experiments/physical_design_with_on_the_fly_gate_design/physical_design_with_on_the_fly_gate_design.cpp b/experiments/physical_design_with_on_the_fly_gate_design/physical_design_with_on_the_fly_gate_design.cpp index 0aa4ac8a6..baea44fb1 100644 --- a/experiments/physical_design_with_on_the_fly_gate_design/physical_design_with_on_the_fly_gate_design.cpp +++ b/experiments/physical_design_with_on_the_fly_gate_design/physical_design_with_on_the_fly_gate_design.cpp @@ -38,6 +38,10 @@ // This script conducts defect-aware placement and routing with defect-aware on-the-fly SiDB gate design. Thereby, SiDB // circuits can be designed in the presence of atomic defects. +// This algorithm was proposed in \"On-the-fly Defect-Aware Design of Circuits based on Silicon Dangling Bond Logic\" by +// J. Drewniok, M. Walter, S. S. H. Ng, K. Walus, and R. Wille in IEEE NANO 2024 +// (https://ieeexplore.ieee.org/abstract/document/10628962). + int main() // NOLINT { using gate_lyt = fiction::hex_even_row_gate_clk_lyt; diff --git a/include/fiction/algorithms/physical_design/determine_clocking.hpp b/include/fiction/algorithms/physical_design/determine_clocking.hpp index 11d09a1da..86c8d5ca5 100644 --- a/include/fiction/algorithms/physical_design/determine_clocking.hpp +++ b/include/fiction/algorithms/physical_design/determine_clocking.hpp @@ -396,13 +396,17 @@ class determine_clocking_impl } // namespace detail /** - * Determines clock numbers for the given gate-level layout. This algorithm parses the layout's gate and wire - * connections, disregarding any existing clocking information, and constructs a SAT instance to find a valid clock + * Determines clock numbers for the given (unclocked) gate-level layout. This algorithm parses the layout's gate and + * wire connections, disregarding any existing clocking information, and constructs a SAT instance to find a valid clock * number assignment under which the information flow is respected. It then assigns these clock numbers as an irregular * clock map to the given layout via the `assign_clock_number` function, overriding any existing clocking scheme. * * If no valid clock number assignment exists for `lyt`, this function returns `false` and does not modify `lyt`. * + * This algorithm was proposed in \"Ending the Tyranny of the Clock: SAT-based Clock Number Assignment for Field-coupled + * Nanotechnologies\" by M. Walter, J. Drewniok, and R. Wille in IEEE NANO 2024 + * (https://ieeexplore.ieee.org/abstract/document/10628908). + * * @tparam Lyt Gate-level layout type. * @param lyt The gate-level layout to assign clock numbers to. * @param params Parameters. diff --git a/include/fiction/algorithms/physical_design/graph_oriented_layout_design.hpp b/include/fiction/algorithms/physical_design/graph_oriented_layout_design.hpp index bdb9191e0..f1ae5e0c9 100644 --- a/include/fiction/algorithms/physical_design/graph_oriented_layout_design.hpp +++ b/include/fiction/algorithms/physical_design/graph_oriented_layout_design.hpp @@ -1625,6 +1625,9 @@ class graph_oriented_layout_design_impl * * Exclusively generates 2DDWave-clocked layouts. * + * This algorithm was proposed in \"A* is Born: Efficient and Scalable Physical Design for Field-coupled Nanocomputing\" + * by S. Hofmann, M. Walter, and R. Wille in IEEE NANO 2024 (https://ieeexplore.ieee.org/document/10628808). + * * @tparam Lyt Cartesian gate-level layout type. * @tparam Ntk Network type. * @param ntk The network to be placed and routed. diff --git a/include/fiction/algorithms/physical_design/on_the_fly_circuit_design_on_defective_surface.hpp b/include/fiction/algorithms/physical_design/on_the_fly_circuit_design_on_defective_surface.hpp index 93adb8715..a72a4edb9 100644 --- a/include/fiction/algorithms/physical_design/on_the_fly_circuit_design_on_defective_surface.hpp +++ b/include/fiction/algorithms/physical_design/on_the_fly_circuit_design_on_defective_surface.hpp @@ -164,12 +164,13 @@ class on_the_fly_circuit_design_impl * circuit remains functional even in the presence of defects. * * This methodology is detailed in the paper "On-the-fly Defect-Aware Design of Circuits based on Silicon Dangling Bond - * Logic" by J. Drewniok, M. Walter, S. S. H. Ng, K. Walus, and R. Wille, IEEE NANO 2024. + * Logic" by J. Drewniok, M. Walter, S. S. H. Ng, K. Walus, and R. Wille, IEEE NANO 2024 + * (https://ieeexplore.ieee.org/abstract/document/10628962). * * @tparam Ntk The type of the input network. * @tparam CellLyt Cell-level layout type. * @tparam GateLyt Gate-level layout type. - * @param network The input network to be mapped onto the defective surface. + * @param ntk The input network to be mapped onto the defective surface. * @param lattice_tiling The lattice tiling used for the circuit design. * @param params The parameters used for designing the circuit, encapsulated in an * `on_the_fly_circuit_design_params` object. diff --git a/include/fiction/algorithms/physical_design/post_layout_optimization.hpp b/include/fiction/algorithms/physical_design/post_layout_optimization.hpp index 1b612c69b..e201fc8ee 100644 --- a/include/fiction/algorithms/physical_design/post_layout_optimization.hpp +++ b/include/fiction/algorithms/physical_design/post_layout_optimization.hpp @@ -1040,10 +1040,11 @@ class post_layout_optimization_impl /** * A post-layout optimization algorithm as originally proposed in \"Post-Layout Optimization for Field-coupled - * Nanotechnologies\" by S. Hofmann, M. Walter, and R. Wille in NANOARCH 2023. It can be used to reduce the area of a - * given sub-optimal Cartesian gate-level layout created by heuristics or machine learning. This optimization utilizes - * the distinct characteristics of the 2DDWave clocking scheme, which only allows information flow from top to bottom - * and left to right, therefore only aforementioned clocking scheme is supported. + * Nanotechnologies\" by S. Hofmann, M. Walter, and R. Wille in NANOARCH 2023 + * (https://dl.acm.org/doi/10.1145/3611315.3633247). It can be used to reduce the area of a given sub-optimal Cartesian + * gate-level layout created by heuristics or machine learning. This optimization utilizes the distinct characteristics + * of the 2DDWave clocking scheme, which only allows information flow from top to bottom and left to right, therefore + * only aforementioned clocking scheme is supported. * * To reduce the layout area, first, gates are moved up and to the left as far as possible, including rerouting. This * creates more compact layouts by freeing up space to the right and bottom, as all gates were moved to the top left