Allow for more fine tuned CPU feature/mode settings

[Rot127]

Currently (almost) all features are enabled for each architecture. This leads to a little inaccurate disassembly. Especially when it comes to alias of instructions.

Example from ARM:

# Without ARM_FeatureRAS
0xaff31080	hint.w	#0x10
# WIth ARM_FeatureRAS
0xaff31080	esbge.w	#0x10

Since an architecture can have easily more than 100 features it needs another mechanism to toggle those.
Currently only a few CS_MODE_X flags can be passed.

[Rot127]

The whole way to store options should be overthought again. Currently there is no clear distinction between options for modules and whole CS. CS_MODE_ for example gets set by the module. But in general is saved in the handle.

[Rot127]

This would also allow to test instructions which are only used in certain modes independently. As well as instructions with changing asm text syntax.

It would also allow to add more MC test cases. Currently always the last generated file is written.

[wargio]

I think the most annoying part of the update is understanding which CPU feature is enabled or not.
LLVM uses Proc in the .td file to generate a list of CPUs which has features enabled/disabled.

Example:
From : https://github.com/llvm-mirror/llvm/blob/master/lib/Target/Mips/Mips.td#L230 and https://github.com/llvm-mirror/llvm/blob/master/lib/Target/Mips/Mips.td#L76
You can generate a table of features for each Proc, then you can convert into a reverse table to generate the correct configuration for https://github.com/capstone-engine/capstone/pull/2410/files#diff-b2b2f5b6be21623f5bfa0de90d0e496e176895a266ac013846baaa58784d27b2R57-R66