From da80c83842390f83ba5365adf2551e988ef3149c Mon Sep 17 00:00:00 2001 From: mssonicbld <79238446+mssonicbld@users.noreply.github.com> Date: Thu, 20 Oct 2022 10:26:58 +0800 Subject: [PATCH 01/35] [build] Fix dpkg front lock issue with apt-get (#12332) (#12349) Co-authored-by: Liu Shilong --- src/sonic-build-hooks/hooks/dpkg | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 src/sonic-build-hooks/hooks/dpkg diff --git a/src/sonic-build-hooks/hooks/dpkg b/src/sonic-build-hooks/hooks/dpkg new file mode 100644 index 000000000000..7fbc90f9fe5c --- /dev/null +++ b/src/sonic-build-hooks/hooks/dpkg @@ -0,0 +1,10 @@ +#!/bin/bash + +. /usr/local/share/buildinfo/scripts/buildinfo_base.sh +REAL_COMMAND=$(get_command dpkg) +COMMAND_INFO="Locked by command: $REAL_COMMAND $@" +lock_result=$(acquire_apt_installation_lock "$COMMAND_INFO" ) +$REAL_COMMAND "$@" +command_result=$? +[ "$lock_result" == y ] && release_apt_installation_lock +exit $command_result From 0772d36c6d4f636509b79e5cb663ea0bb675e645 Mon Sep 17 00:00:00 2001 From: Samuel Angebault Date: Thu, 20 Oct 2022 17:15:57 +0200 Subject: [PATCH 02/35] [202205][Arista] Update platform driver library (#12451) fix linecard provisioning issue (500 error) fix some value types for get_system_eeprom_info API refactor code to leverage pci topology (enabling dynamic Pcie plugin) refactor asic declaration logic to new style misc fixes --- platform/barefoot/sonic-platform-modules-arista | 2 +- platform/broadcom/sonic-platform-modules-arista | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/platform/barefoot/sonic-platform-modules-arista b/platform/barefoot/sonic-platform-modules-arista index 11180c37fa17..2eae0dd1ad35 160000 --- a/platform/barefoot/sonic-platform-modules-arista +++ b/platform/barefoot/sonic-platform-modules-arista @@ -1 +1 @@ -Subproject commit 11180c37fa17421afdeef346b3896552872a2721 +Subproject commit 2eae0dd1ad35b6fd5a78f3eebed466f2744d4fdc diff --git a/platform/broadcom/sonic-platform-modules-arista b/platform/broadcom/sonic-platform-modules-arista index 11180c37fa17..2eae0dd1ad35 160000 --- a/platform/broadcom/sonic-platform-modules-arista +++ b/platform/broadcom/sonic-platform-modules-arista @@ -1 +1 @@ -Subproject commit 11180c37fa17421afdeef346b3896552872a2721 +Subproject commit 2eae0dd1ad35b6fd5a78f3eebed466f2744d4fdc From 62c41101445c5ac8e5f21191920cf339c03f02c9 Mon Sep 17 00:00:00 2001 From: Sudharsan Dhamal Gopalarathnam Date: Sun, 23 Oct 2022 00:00:58 -0700 Subject: [PATCH 03/35] [202205][submodule] Advance sonic-utilities pointer (#12443) Update sonic-utilities submodule pointer to include the following: * ab21b58 [202205] check for vxlan mapping before removing vlan (#2388) ([#2446](https://github.com/Azure/sonic-utilities/pull/2446)) * e111ad4 [202205][Auto-Techsupport] Fix the coredump_gen_handler Exception when the History table is empty (#2265) ([#2433](https://github.com/Azure/sonic-utilities/pull/2433)) * 6925947 [watermarkstat][202205] Add new warning message for the 'q_shared_multi' counters ([#2406](https://github.com/Azure/sonic-utilities/pull/2406)) Signed-off-by: dgsudharsan --- src/sonic-utilities | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/sonic-utilities b/src/sonic-utilities index a255838d0b80..ab21b5888092 160000 --- a/src/sonic-utilities +++ b/src/sonic-utilities @@ -1 +1 @@ -Subproject commit a255838d0b804055371d116fba2e8e0a78a528be +Subproject commit ab21b58880927a289380798bc73bf844816a7d36 From db2128564b8d687e5df265fc4830970abc29c98e Mon Sep 17 00:00:00 2001 From: xumia <59720581+xumia@users.noreply.github.com> Date: Mon, 24 Oct 2022 13:13:14 +0800 Subject: [PATCH 04/35] [202205] Change submodule path from Azure to sonic-net (#12308) Why I did it Change the path of sonic submodules that point to "Azure" to point to "sonic-net" How I did it Replace "Azure" with "sonic-net" on all relevant paths of sonic submodules --- .gitmodules | 42 +++++++++++++------------- files/image_config/environment/motd | 2 +- platform/vs/sonic-gns3a.sh | 4 +-- src/sonic-host-services-data/README.md | 2 +- 4 files changed, 25 insertions(+), 25 deletions(-) diff --git a/.gitmodules b/.gitmodules index 6f1a611a1ea0..0812b366c61b 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,18 +1,18 @@ [submodule "sonic-swss-common"] path = src/sonic-swss-common - url = https://github.com/Azure/sonic-swss-common + url = https://github.com/sonic-net/sonic-swss-common branch = 202205 [submodule "sonic-linux-kernel"] path = src/sonic-linux-kernel - url = https://github.com/Azure/sonic-linux-kernel + url = https://github.com/sonic-net/sonic-linux-kernel branch = 202205 [submodule "sonic-sairedis"] path = src/sonic-sairedis - url = https://github.com/Azure/sonic-sairedis + url = https://github.com/sonic-net/sonic-sairedis branch = 202205 [submodule "sonic-swss"] path = src/sonic-swss - url = https://github.com/Azure/sonic-swss + url = https://github.com/sonic-net/sonic-swss branch = 202205 [submodule "src/p4c-bm/p4c-bm"] path = platform/p4/p4c-bm/p4c-bm @@ -22,37 +22,37 @@ url = https://github.com/p4lang/p4-hlir [submodule "sonic-dbsyncd"] path = src/sonic-dbsyncd - url = https://github.com/Azure/sonic-dbsyncd + url = https://github.com/sonic-net/sonic-dbsyncd [submodule "src/sonic-py-swsssdk"] path = src/sonic-py-swsssdk - url = https://github.com/Azure/sonic-py-swsssdk.git + url = https://github.com/sonic-net/sonic-py-swsssdk.git [submodule "src/sonic-snmpagent"] path = src/sonic-snmpagent - url = https://github.com/Azure/sonic-snmpagent + url = https://github.com/sonic-net/sonic-snmpagent [submodule "src/ptf"] path = src/ptf url = https://github.com/p4lang/ptf.git [submodule "src/sonic-utilities"] path = src/sonic-utilities - url = https://github.com/Azure/sonic-utilities + url = https://github.com/sonic-net/sonic-utilities branch = 202205 [submodule "platform/broadcom/sonic-platform-modules-arista"] path = platform/broadcom/sonic-platform-modules-arista url = https://github.com/aristanetworks/sonic [submodule "src/sonic-platform-common"] path = src/sonic-platform-common - url = https://github.com/Azure/sonic-platform-common + url = https://github.com/sonic-net/sonic-platform-common branch = 202205 [submodule "src/sonic-platform-daemons"] path = src/sonic-platform-daemons - url = https://github.com/Azure/sonic-platform-daemons + url = https://github.com/sonic-net/sonic-platform-daemons branch = 202205 [submodule "src/sonic-platform-pde"] path = src/sonic-platform-pde - url = https://github.com/Azure/sonic-platform-pdk-pde + url = https://github.com/sonic-net/sonic-platform-pdk-pde [submodule "src/sonic-frr/frr"] path = src/sonic-frr/frr - url = https://github.com/Azure/sonic-frr.git + url = https://github.com/sonic-net/sonic-frr.git branch = frr/8.2 [submodule "platform/p4/p4-hlir/p4-hlir-v1.1"] path = platform/p4/p4-hlir/p4-hlir-v1.1 @@ -77,40 +77,40 @@ url = https://github.com/Mellanox/SAI-Implementation [submodule "src/sonic-mgmt-framework"] path = src/sonic-mgmt-framework - url = https://github.com/Azure/sonic-mgmt-framework + url = https://github.com/sonic-net/sonic-mgmt-framework [submodule "src/sonic-telemetry"] path = src/sonic-telemetry - url = https://github.com/Azure/sonic-telemetry + url = https://github.com/sonic-net/sonic-telemetry [submodule "Switch-SDK-drivers"] path = platform/mellanox/sdk-src/sx-kernel/Switch-SDK-drivers url = https://github.com/Mellanox/Switch-SDK-drivers [submodule "src/sonic-ztp"] path = src/sonic-ztp - url = https://github.com/Azure/sonic-ztp + url = https://github.com/sonic-net/sonic-ztp [submodule "src/sonic-restapi"] path = src/sonic-restapi - url = https://github.com/Azure/sonic-restapi.git + url = https://github.com/sonic-net/sonic-restapi.git branch = master [submodule "src/sonic-mgmt-common"] path = src/sonic-mgmt-common - url = https://github.com/Azure/sonic-mgmt-common.git + url = https://github.com/sonic-net/sonic-mgmt-common.git [submodule "src/wpasupplicant/sonic-wpa-supplicant"] path = src/wpasupplicant/sonic-wpa-supplicant - url = https://github.com/Azure/sonic-wpa-supplicant.git + url = https://github.com/sonic-net/sonic-wpa-supplicant.git [submodule "platform/broadcom/saibcm-modules-dnx"] path = platform/broadcom/saibcm-modules-dnx - url = https://github.com/Azure/saibcm-modules.git + url = https://github.com/sonic-net/saibcm-modules.git branch = sdk-6.5.22-gpl-dnx [submodule "platform/broadcom/sonic-platform-modules-nokia"] path = platform/broadcom/sonic-platform-modules-nokia url = https://github.com/nokia/sonic-platform.git [submodule "src/linkmgrd"] path = src/linkmgrd - url = https://github.com/Azure/sonic-linkmgrd.git + url = https://github.com/sonic-net/sonic-linkmgrd.git branch = 202205 [submodule "src/sonic-p4rt/sonic-pins"] path = src/sonic-p4rt/sonic-pins - url = https://github.com/Azure/sonic-pins.git + url = https://github.com/sonic-net/sonic-pins.git [submodule "src/ptf-py3"] path = src/ptf-py3 url = https://github.com/p4lang/ptf.git diff --git a/files/image_config/environment/motd b/files/image_config/environment/motd index 8562e330fe2c..0d857e5c5f94 100644 --- a/files/image_config/environment/motd +++ b/files/image_config/environment/motd @@ -10,5 +10,5 @@ You are on Unauthorized access and/or use are prohibited. All access and/or use are subject to monitoring. -Help: http://azure.github.io/SONiC/ +Help: https://sonic-net.github.io/SONiC/ diff --git a/platform/vs/sonic-gns3a.sh b/platform/vs/sonic-gns3a.sh index 41e39cd8686a..2a772ce5a332 100644 --- a/platform/vs/sonic-gns3a.sh +++ b/platform/vs/sonic-gns3a.sh @@ -41,9 +41,9 @@ echo " \"category\": \"router\", \"description\": \"SONiC Virtual Switch/Router\", \"vendor_name\": \"SONiC\", - \"vendor_url\": \"https://azure.github.io/SONiC/\", + \"vendor_url\": \"https://sonic-net.github.io/SONiC/\", \"product_name\": \"SONiC\", - \"product_url\": \"https://azure.github.io/SONiC/\", + \"product_url\": \"https://sonic-net.github.io/SONiC/\", \"registry_version\": 3, \"status\": \"experimental\", \"maintainer\": \"SONiC\", diff --git a/src/sonic-host-services-data/README.md b/src/sonic-host-services-data/README.md index 93af66a83d6b..0b9e714932d2 100644 --- a/src/sonic-host-services-data/README.md +++ b/src/sonic-host-services-data/README.md @@ -16,4 +16,4 @@ dpkg-buildpackage -rfakeroot -Tclean --- -See the [SONiC Website](http://azure.github.io/SONiC/) for more information about the SONiC project. +See the [SONiC Website](https://sonic-net.github.io/SONiC/) for more information about the SONiC project. From ab8fc11a88da885c6da53b85792084ec0a402b71 Mon Sep 17 00:00:00 2001 From: Ye Jianquan Date: Tue, 25 Oct 2022 04:25:18 +0800 Subject: [PATCH 05/35] [TestbedV2]Migrate t0 and t1-lag to TestbedV2 (#12383) (#12474) co-authorized by: jianquanye@microsoft.com Migrate the t0 and t1-lag test jobs in buildimage repo to TestbedV2. Why I did it Migrate the t0 and t1-lag test jobs in buildimage repo to TestbedV2. How I did it Migrate the t0 and t1-lag test jobs in buildimage repo to TestbedV2. Remove ceos type setting Use 202205 branch as sonic-mgmt branch --- .../run-test-scheduler-template.yml | 118 ++++++++++++++++++ azure-pipelines.yml | 108 ++++++++++++++-- 2 files changed, 215 insertions(+), 11 deletions(-) create mode 100644 .azure-pipelines/run-test-scheduler-template.yml diff --git a/.azure-pipelines/run-test-scheduler-template.yml b/.azure-pipelines/run-test-scheduler-template.yml new file mode 100644 index 000000000000..9029c6aab622 --- /dev/null +++ b/.azure-pipelines/run-test-scheduler-template.yml @@ -0,0 +1,118 @@ +parameters: +- name: TOPOLOGY + type: string + +- name: POLL_INTERVAL + type: number + default: 10 + +- name: POLL_TIMEOUT + type: number + default: 36000 + +- name: MIN_WORKER + type: number + default: 1 + +- name: MAX_WORKER + type: number + default: 2 + +- name: TEST_SET + type: string + default: "" + +- name: DEPLOY_MG_EXTRA_PARAMS + type: string + default: "" + +- name: MGMT_BRANCH + type: string + default: master + +steps: + - script: | + set -ex + wget -O ./.azure-pipelines/test_plan.py https://raw.githubusercontent.com/sonic-net/sonic-mgmt/master/.azure-pipelines/test_plan.py + wget -O ./.azure-pipelines/pr_test_scripts.yaml https://raw.githubusercontent.com/sonic-net/sonic-mgmt/master/.azure-pipelines/pr_test_scripts.yaml + displayName: Download TestbedV2 scripts + + - script: | + set -ex + pip install PyYAML + rm -f new_test_plan_id.txt + python ./.azure-pipelines/test_plan.py create -t ${{ parameters.TOPOLOGY }} -o new_test_plan_id.txt --min-worker ${{ parameters.MIN_WORKER }} --max-worker ${{ parameters.MAX_WORKER }} --test-set ${{ parameters.TEST_SET }} --kvm-build-id $(KVM_BUILD_ID) --deploy-mg-extra-params "${{ parameters.DEPLOY_MG_EXTRA_PARAMS }}" --mgmt-branch ${{ parameters.MGMT_BRANCH }} + TEST_PLAN_ID=`cat new_test_plan_id.txt` + + echo "Created test plan $TEST_PLAN_ID" + echo "Check https://www.testbed-tools.org/scheduler/testplan/$TEST_PLAN_ID for test plan status" + echo "##vso[task.setvariable variable=TEST_PLAN_ID]$TEST_PLAN_ID" + env: + TESTBED_TOOLS_URL: $(TESTBED_TOOLS_URL) + TENANT_ID: $(TESTBED_TOOLS_MSAL_TENANT_ID) + CLIENT_ID: $(TESTBED_TOOLS_MSAL_CLIENT_ID) + CLIENT_SECRET: $(TESTBED_TOOLS_MSAL_CLIENT_SECRET) + displayName: Trigger test + + - script: | + set -ex + echo "Lock testbed" + echo "TestbedV2 is just online and might not be stable enough, for any issue, please send email to sonictestbedtools@microsoft.com" + echo "Runtime detailed progress at https://www.testbed-tools.org/scheduler/testplan/$TEST_PLAN_ID" + # When "LOCK_TESTBED" finish, it changes into "PREPARE_TESTBED" + python ./.azure-pipelines/test_plan.py poll -i "$(TEST_PLAN_ID)" --timeout 43200 --expected-states PREPARE_TESTBED EXECUTING KVMDUMP FINISHED CANCELLED FAILED + env: + TESTBED_TOOLS_URL: $(TESTBED_TOOLS_URL) + displayName: Lock testbed + timeoutInMinutes: 240 + + - script: | + set -ex + echo "Prepare testbed" + echo "Preparing the testbed(add-topo, deploy-mg) may take 15-30 minutes. Before the testbed is ready, the progress of the test plan keeps displayed as 0, please be patient(We will improve the indication in a short time)" + echo "If the progress keeps as 0 for more than 1 hour, please cancel and retry this pipeline" + echo "TestbedV2 is just online and might not be stable enough, for any issue, please send email to sonictestbedtools@microsoft.com" + echo "Runtime detailed progress at https://www.testbed-tools.org/scheduler/testplan/$TEST_PLAN_ID" + # When "PREPARE_TESTBED" finish, it changes into "EXECUTING" + python ./.azure-pipelines/test_plan.py poll -i "$(TEST_PLAN_ID)" --timeout 2400 --expected-states EXECUTING KVMDUMP FINISHED CANCELLED FAILED + env: + TESTBED_TOOLS_URL: $(TESTBED_TOOLS_URL) + displayName: Prepare testbed + timeoutInMinutes: 40 + + - script: | + set -ex + echo "Run test" + echo "TestbedV2 is just online and might not be stable enough, for any issue, please send email to sonictestbedtools@microsoft.com" + echo "Runtime detailed progress at https://www.testbed-tools.org/scheduler/testplan/$TEST_PLAN_ID" + # When "EXECUTING" finish, it changes into "KVMDUMP", "FAILED", "CANCELLED" or "FINISHED" + python ./.azure-pipelines/test_plan.py poll -i "$(TEST_PLAN_ID)" --timeout 18000 --expected-states KVMDUMP FINISHED CANCELLED FAILED + env: + TESTBED_TOOLS_URL: $(TESTBED_TOOLS_URL) + displayName: Run test + timeoutInMinutes: 300 + + - script: | + set -ex + echo "KVM dump" + echo "TestbedV2 is just online and might not be stable enough, for any issue, please send email to sonictestbedtools@microsoft.com" + echo "Runtime detailed progress at https://www.testbed-tools.org/scheduler/testplan/$TEST_PLAN_ID" + # When "KVMDUMP" finish, it changes into "FAILED", "CANCELLED" or "FINISHED" + python ./.azure-pipelines/test_plan.py poll -i "$(TEST_PLAN_ID)" --timeout 43200 --expected-states FINISHED CANCELLED FAILED + condition: succeededOrFailed() + env: + TESTBED_TOOLS_URL: $(TESTBED_TOOLS_URL) + displayName: KVM dump + timeoutInMinutes: 20 + + - script: | + set -ex + echo "Try to cancel test plan $TEST_PLAN_ID, cancelling finished test plan has no effect." + python ./.azure-pipelines/test_plan.py cancel -i "$(TEST_PLAN_ID)" + condition: always() + env: + TESTBED_TOOLS_URL: $(TESTBED_TOOLS_URL) + TENANT_ID: $(TESTBED_TOOLS_MSAL_TENANT_ID) + CLIENT_ID: $(TESTBED_TOOLS_MSAL_CLIENT_ID) + CLIENT_SECRET: $(TESTBED_TOOLS_MSAL_CLIENT_SECRET) + displayName: Finalize running test plan diff --git a/azure-pipelines.yml b/azure-pipelines.yml index fec16f2d64c9..be4478aaf4c4 100644 --- a/azure-pipelines.yml +++ b/azure-pipelines.yml @@ -79,6 +79,7 @@ stages: dependsOn: BuildVS condition: and(ne(stageDependencies.BuildVS.outputs['vs.SetVar.SKIP_VSTEST'], 'YES'), in(dependencies.BuildVS.result, 'Succeeded', 'SucceededWithIssues')) variables: + - group: Testbed-Tools - name: inventory value: veos_vtb - name: testbed_file @@ -138,7 +139,8 @@ stages: pool: sonictest displayName: "kvmtest-t0-part1" timeoutInMinutes: 360 - + condition: and(succeeded(), eq(variables.BUILD_IMG_RUN_CLASSICAL_TEST, 'YES')) + continueOnError: false steps: - template: .azure-pipelines/run-test-template.yml parameters: @@ -152,7 +154,8 @@ stages: pool: sonictest displayName: "kvmtest-t0-part2" timeoutInMinutes: 360 - + condition: and(succeeded(), eq(variables.BUILD_IMG_RUN_CLASSICAL_TEST, 'YES')) + continueOnError: false steps: - template: .azure-pipelines/run-test-template.yml parameters: @@ -162,33 +165,74 @@ stages: tbtype: t0 section: part-2 + - job: t0_testbedv2 + pool: + vmImage: 'ubuntu-20.04' + displayName: "kvmtest-t0 by TestbedV2" + timeoutInMinutes: 1080 + condition: and(succeeded(), eq(variables.BUILD_IMG_RUN_TESTBEDV2_TEST, 'YES')) + continueOnError: false + steps: + - template: .azure-pipelines/run-test-scheduler-template.yml + parameters: + TOPOLOGY: t0 + MIN_WORKER: 2 + MAX_WORKER: 3 + MGMT_BRANCH: 202205 + + - job: t0_2vlans_testbedv2 + pool: + vmImage: 'ubuntu-20.04' + displayName: "kvmtest-t0-2vlans by TestbedV2" + timeoutInMinutes: 1080 + condition: and(succeeded(), eq(variables.BUILD_IMG_RUN_TESTBEDV2_TEST, 'YES')) + continueOnError: false + steps: + - template: .azure-pipelines/run-test-scheduler-template.yml + parameters: + TOPOLOGY: t0 + TEST_SET: t0-2vlans + MAX_WORKER: 1 + DEPLOY_MG_EXTRA_PARAMS: "-e vlan_config=two_vlan_a" + MGMT_BRANCH: 202205 + - job: - pool: sonictest + pool: + vmImage: 'ubuntu-20.04' displayName: "kvmtest-t0" - timeoutInMinutes: 360 dependsOn: - t0_part1 - t0_part2 + - t0_testbedv2 + - t0_2vlans_testbedv2 condition: always() variables: resultOfPart1: $[ dependencies.t0_part1.result ] resultOfPart2: $[ dependencies.t0_part2.result ] + resultOfT0TestbedV2: $[ dependencies.t0_testbedv2.result ] + resultOfT02VlansTestbedV2: $[ dependencies.t0_2vlans_testbedv2.result ] steps: - script: | + if [ $(resultOfT0TestbedV2) == "Succeeded" ] && [ $(resultOfT02VlansTestbedV2) == "Succeeded" ]; then + echo "TestbedV2 t0 passed." + exit 0 + fi + if [ $(resultOfPart1) == "Succeeded" ] && [ $(resultOfPart2) == "Succeeded" ]; then - echo "Both job kvmtest-t0-part1 and kvmtest-t0-part2 are passed." + echo "Classic t0 jobs(both part1 and part2) passed." exit 0 - else - echo "Either job kvmtest-t0-part1 or job kvmtest-t0-part2 failed! Please check the detailed information." - exit 1 fi - - job: + echo "Both classic and TestbedV2 t0 jobs failed! Please check the detailed information. (Any of them passed, t0 will be considered as passed)" + exit 1 + + - job: t1_lag_classic pool: sonictest-t1-lag - displayName: "kvmtest-t1-lag" + displayName: "kvmtest-t1-lag classic" timeoutInMinutes: 360 - + condition: and(succeeded(), eq(variables.BUILD_IMG_RUN_CLASSICAL_TEST, 'YES')) + continueOnError: false steps: - template: .azure-pipelines/run-test-template.yml parameters: @@ -197,6 +241,48 @@ stages: ptf_name: ptf_vms6-2 tbtype: t1-lag + - job: t1_lag_testbedv2 + pool: + vmImage: 'ubuntu-20.04' + displayName: "kvmtest-t1-lag by TestbedV2" + timeoutInMinutes: 600 + condition: and(succeeded(), eq(variables.BUILD_IMG_RUN_TESTBEDV2_TEST, 'YES')) + continueOnError: false + steps: + - template: .azure-pipelines/run-test-scheduler-template.yml + parameters: + TOPOLOGY: t1-lag + MIN_WORKER: 2 + MAX_WORKER: 3 + MGMT_BRANCH: 202205 + + - job: + pool: + vmImage: 'ubuntu-20.04' + displayName: "kvmtest-t1-lag" + dependsOn: + - t1_lag_classic + - t1_lag_testbedv2 + condition: always() + continueOnError: false + variables: + resultOfClassic: $[ dependencies.t1_lag_classic.result ] + resultOfTestbedV2: $[ dependencies.t1_lag_testbedv2.result ] + steps: + - script: | + if [ $(resultOfTestbedV2) == "Succeeded" ]; then + echo "TestbedV2 t1-lag passed." + exit 0 + fi + + if [ $(resultOfClassic) == "Succeeded" ]; then + echo "Classic t1-lag passed." + exit 0 + fi + + echo "Both classic and TestbedV2 t1-lag jobs failed! Please check the detailed information. (Any of them passed, t1-lag will be considered as passed)" + exit 1 + - job: pool: sonictest-sonic-t0 displayName: "kvmtest-t0-sonic" From a4d6676f83b460aee669040c39a747e81b2f8d98 Mon Sep 17 00:00:00 2001 From: Sambath Kumar Balasubramanian <63021927+skbarista@users.noreply.github.com> Date: Mon, 17 Oct 2022 11:15:19 -0700 Subject: [PATCH 06/35] Add 36 port 100g sku for x86_64-arista_7800r3a_36d series of linecards. (#11813) Add 36 port 100g sku for x86_64-arista_7800r3a_36d series of linecards. --- .../Arista-7800R3A-36D-C36 | 1 + .../0/context_config.json | 25 + .../0/j2p-a7800r3a-36d-36x400G.config.bcm | 985 ++++++++++++++++++ .../Arista-7800R3A-36D2-C36/0/port_config.ini | 21 + .../Arista-7800R3A-36D2-C36/0/sai.profile | 2 + .../1/context_config.json | 1 + .../1/j2p-a7800r3a-36d-36x400G.config.bcm | 984 +++++++++++++++++ .../Arista-7800R3A-36D2-C36/1/port_config.ini | 21 + .../Arista-7800R3A-36D2-C36/1/sai.profile | 1 + .../Arista-7800R3A-36DM2-C36 | 1 + .../Arista-7800R3A-36P-C36 | 1 + .../Arista-7800R3AK-36D2-C36 | 1 + .../Arista-7800R3AK-36DM2-C36 | 1 + 13 files changed, 2045 insertions(+) create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D-C36 create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/0/context_config.json create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/0/j2p-a7800r3a-36d-36x400G.config.bcm create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/0/port_config.ini create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/0/sai.profile create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/1/context_config.json create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/1/j2p-a7800r3a-36d-36x400G.config.bcm create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/1/port_config.ini create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/1/sai.profile create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36DM2-C36 create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36P-C36 create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36D2-C36 create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36DM2-C36 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D-C36 b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D-C36 new file mode 120000 index 000000000000..41ebc98e1c4e --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D-C36 @@ -0,0 +1 @@ +Arista-7800R3A-36D2-C36 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/0/context_config.json b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/0/context_config.json new file mode 100644 index 000000000000..2c126e71899e --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/0/context_config.json @@ -0,0 +1,25 @@ +{ + "CONTEXTS": [ + { + "guid" : 0, + "name" : "syncd", + "dbAsic" : "ASIC_DB", + "dbCounters" : "COUNTERS_DB", + "dbFlex": "FLEX_COUNTER_DB", + "dbState" : "STATE_DB", + "zmq_enable": false, + "zmq_endpoint": "tcp://127.0.0.1:5555", + "zmq_ntf_endpoint": "tcp://127.0.0.1:5556", + "switches": [ + { + "index" : 0, + "hwinfo" : "06:00.0" + }, + { + "index" : 1, + "hwinfo" : "07:00.0" + } + ] + } + ] +} diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/0/j2p-a7800r3a-36d-36x400G.config.bcm b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/0/j2p-a7800r3a-36d-36x400G.config.bcm new file mode 100644 index 000000000000..9be5d8e836f3 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/0/j2p-a7800r3a-36d-36x400G.config.bcm @@ -0,0 +1,985 @@ +soc_family=BCM8885X +system_ref_core_clock_khz=1600000 + +dpp_db_path=/usr/share/bcm/db + +#################################################### +##Reference applications related properties - Start +#################################################### + +## PMF small EXEM connected stage: +# Options: IPMF2 - Ingress PMF 2 stage can perform small EXEM lookups. +# IPMF3 - Ingress PMF 3 stage can perform small EXEM lookups. +## PMF small EXEM connected stage: +# Options: IPMF2 - Ingress PMF 2 stage can perform small EXEM lookups. +# IPMF3 - Ingress PMF 3 stage can perform small EXEM lookups. +pmf_sexem3_stage=IPMF2 + +#################################################### +##Reference applications related properties - End +#################################################### + +# Jericho2-mode (description 0x1 used for Jericho 2 mode) +system_headers_mode=1 + +# HW mode to support 1024 16-member system wide LAGs +trunk_group_max_members=16 + +# Disable link-training +port_init_cl72=0 + +###Default interfaces for Jericho2Plus +#CPU interfaces +ucode_port_0=CPU.0:core_0.0 +ucode_port_200=CPU.8:core_1.200 +ucode_port_201=CPU.16:core_0.201 +ucode_port_202=CPU.24:core_1.202 +ucode_port_203=CPU.32:core_0.203 + +#NIF ETH interfaces on device +ucode_port_1=CGE18:core_1.1 +ucode_port_2=CGE20:core_1.2 +ucode_port_3=CGE22:core_1.3 +ucode_port_4=CGE24:core_1.4 +ucode_port_5=CGE26:core_1.5 +ucode_port_6=CGE28:core_1.6 +ucode_port_7=CGE30:core_1.7 +ucode_port_8=CGE32:core_1.8 +ucode_port_9=CGE34:core_1.9 + +ucode_port_10=CGE16:core_0.10 +ucode_port_11=CGE14:core_0.11 +ucode_port_12=CGE12:core_0.12 +ucode_port_13=CGE10:core_0.13 +ucode_port_14=CGE8:core_0.14 +ucode_port_15=CGE6:core_0.15 +ucode_port_16=CGE4:core_0.16 +ucode_port_17=CGE2:core_0.17 +ucode_port_18=CGE0:core_0.18 + +#NIF default speeds +port_init_speed_xe=10000 +port_init_speed_xl=40000 +port_init_speed_le=50000 +port_init_speed_ce=100000 +port_init_speed_cc=200000 +port_init_speed_cd=400000 +port_init_speed_il=10312 + +port_priorities=8 + +#special ports +ucode_port_240=OLP:core_0.240 + +# NIF lane mapping +lane_to_serdes_map_nif_lane0=rx3:tx4 +lane_to_serdes_map_nif_lane1=rx6:tx1 +lane_to_serdes_map_nif_lane2=rx7:tx5 +lane_to_serdes_map_nif_lane3=rx4:tx7 +lane_to_serdes_map_nif_lane4=rx1:tx2 +lane_to_serdes_map_nif_lane5=rx0:tx0 +lane_to_serdes_map_nif_lane6=rx5:tx3 +lane_to_serdes_map_nif_lane7=rx2:tx6 +lane_to_serdes_map_nif_lane8=rx10:tx11 +lane_to_serdes_map_nif_lane9=rx8:tx8 +lane_to_serdes_map_nif_lane10=rx14:tx12 +lane_to_serdes_map_nif_lane11=rx15:tx15 +lane_to_serdes_map_nif_lane12=rx13:tx10 +lane_to_serdes_map_nif_lane13=rx9:tx9 +lane_to_serdes_map_nif_lane14=rx11:tx13 +lane_to_serdes_map_nif_lane15=rx12:tx14 +lane_to_serdes_map_nif_lane16=rx16:tx17 +lane_to_serdes_map_nif_lane17=rx19:tx21 +lane_to_serdes_map_nif_lane18=rx21:tx18 +lane_to_serdes_map_nif_lane19=rx18:tx16 +lane_to_serdes_map_nif_lane20=rx17:tx23 +lane_to_serdes_map_nif_lane21=rx20:tx22 +lane_to_serdes_map_nif_lane22=rx22:tx20 +lane_to_serdes_map_nif_lane23=rx23:tx19 +lane_to_serdes_map_nif_lane24=rx26:tx28 +lane_to_serdes_map_nif_lane25=rx29:tx31 +lane_to_serdes_map_nif_lane26=rx31:tx29 +lane_to_serdes_map_nif_lane27=rx28:tx27 +lane_to_serdes_map_nif_lane28=rx25:tx25 +lane_to_serdes_map_nif_lane29=rx24:tx30 +lane_to_serdes_map_nif_lane30=rx30:tx24 +lane_to_serdes_map_nif_lane31=rx27:tx26 +lane_to_serdes_map_nif_lane32=rx32:tx39 +lane_to_serdes_map_nif_lane33=rx33:tx38 +lane_to_serdes_map_nif_lane34=rx38:tx32 +lane_to_serdes_map_nif_lane35=rx39:tx33 +lane_to_serdes_map_nif_lane36=rx35:tx37 +lane_to_serdes_map_nif_lane37=rx34:tx36 +lane_to_serdes_map_nif_lane38=rx36:tx34 +lane_to_serdes_map_nif_lane39=rx37:tx35 +lane_to_serdes_map_nif_lane40=rx40:tx41 +lane_to_serdes_map_nif_lane41=rx43:tx45 +lane_to_serdes_map_nif_lane42=rx45:tx42 +lane_to_serdes_map_nif_lane43=rx42:tx40 +lane_to_serdes_map_nif_lane44=rx41:tx47 +lane_to_serdes_map_nif_lane45=rx44:tx46 +lane_to_serdes_map_nif_lane46=rx46:tx44 +lane_to_serdes_map_nif_lane47=rx47:tx43 +lane_to_serdes_map_nif_lane48=rx50:tx52 +lane_to_serdes_map_nif_lane49=rx53:tx55 +lane_to_serdes_map_nif_lane50=rx55:tx53 +lane_to_serdes_map_nif_lane51=rx52:tx51 +lane_to_serdes_map_nif_lane52=rx49:tx49 +lane_to_serdes_map_nif_lane53=rx48:tx54 +lane_to_serdes_map_nif_lane54=rx54:tx48 +lane_to_serdes_map_nif_lane55=rx51:tx50 +lane_to_serdes_map_nif_lane56=rx56:tx63 +lane_to_serdes_map_nif_lane57=rx57:tx62 +lane_to_serdes_map_nif_lane58=rx62:tx56 +lane_to_serdes_map_nif_lane59=rx63:tx57 +lane_to_serdes_map_nif_lane60=rx59:tx61 +lane_to_serdes_map_nif_lane61=rx58:tx60 +lane_to_serdes_map_nif_lane62=rx60:tx58 +lane_to_serdes_map_nif_lane63=rx61:tx59 +lane_to_serdes_map_nif_lane64=rx64:tx65 +lane_to_serdes_map_nif_lane65=rx67:tx69 +lane_to_serdes_map_nif_lane66=rx69:tx66 +lane_to_serdes_map_nif_lane67=rx66:tx64 +lane_to_serdes_map_nif_lane68=rx65:tx71 +lane_to_serdes_map_nif_lane69=rx68:tx70 +lane_to_serdes_map_nif_lane70=rx70:tx68 +lane_to_serdes_map_nif_lane71=rx71:tx67 +lane_to_serdes_map_nif_lane72=rx79:tx74 +lane_to_serdes_map_nif_lane73=rx76:tx75 +lane_to_serdes_map_nif_lane74=rx72:tx76 +lane_to_serdes_map_nif_lane75=rx74:tx73 +lane_to_serdes_map_nif_lane76=rx77:tx79 +lane_to_serdes_map_nif_lane77=rx78:tx78 +lane_to_serdes_map_nif_lane78=rx73:tx77 +lane_to_serdes_map_nif_lane79=rx75:tx72 +lane_to_serdes_map_nif_lane80=rx86:tx86 +lane_to_serdes_map_nif_lane81=rx83:tx87 +lane_to_serdes_map_nif_lane82=rx82:tx81 +lane_to_serdes_map_nif_lane83=rx85:tx80 +lane_to_serdes_map_nif_lane84=rx87:tx85 +lane_to_serdes_map_nif_lane85=rx84:tx84 +lane_to_serdes_map_nif_lane86=rx80:tx82 +lane_to_serdes_map_nif_lane87=rx81:tx83 +lane_to_serdes_map_nif_lane88=rx95:tx90 +lane_to_serdes_map_nif_lane89=rx92:tx88 +lane_to_serdes_map_nif_lane90=rx88:tx92 +lane_to_serdes_map_nif_lane91=rx91:tx95 +lane_to_serdes_map_nif_lane92=rx94:tx89 +lane_to_serdes_map_nif_lane93=rx93:tx91 +lane_to_serdes_map_nif_lane94=rx89:tx93 +lane_to_serdes_map_nif_lane95=rx90:tx94 +lane_to_serdes_map_nif_lane96=rx103:tx97 +lane_to_serdes_map_nif_lane97=rx100:tx96 +lane_to_serdes_map_nif_lane98=rx96:tx100 +lane_to_serdes_map_nif_lane99=rx99:tx103 +lane_to_serdes_map_nif_lane100=rx102:tx99 +lane_to_serdes_map_nif_lane101=rx101:tx98 +lane_to_serdes_map_nif_lane102=rx97:tx101 +lane_to_serdes_map_nif_lane103=rx98:tx102 +lane_to_serdes_map_nif_lane104=rx110:tx107 +lane_to_serdes_map_nif_lane105=rx108:tx105 +lane_to_serdes_map_nif_lane106=rx104:tx108 +lane_to_serdes_map_nif_lane107=rx107:tx110 +lane_to_serdes_map_nif_lane108=rx111:tx106 +lane_to_serdes_map_nif_lane109=rx109:tx104 +lane_to_serdes_map_nif_lane110=rx105:tx109 +lane_to_serdes_map_nif_lane111=rx106:tx111 +lane_to_serdes_map_nif_lane112=rx119:tx114 +lane_to_serdes_map_nif_lane113=rx116:tx112 +lane_to_serdes_map_nif_lane114=rx112:tx116 +lane_to_serdes_map_nif_lane115=rx115:tx119 +lane_to_serdes_map_nif_lane116=rx118:tx113 +lane_to_serdes_map_nif_lane117=rx117:tx115 +lane_to_serdes_map_nif_lane118=rx113:tx117 +lane_to_serdes_map_nif_lane119=rx114:tx118 +lane_to_serdes_map_nif_lane120=rx127:tx121 +lane_to_serdes_map_nif_lane121=rx124:tx120 +lane_to_serdes_map_nif_lane122=rx120:tx124 +lane_to_serdes_map_nif_lane123=rx123:tx127 +lane_to_serdes_map_nif_lane124=rx126:tx123 +lane_to_serdes_map_nif_lane125=rx125:tx122 +lane_to_serdes_map_nif_lane126=rx121:tx125 +lane_to_serdes_map_nif_lane127=rx122:tx126 +lane_to_serdes_map_nif_lane128=rx134:tx131 +lane_to_serdes_map_nif_lane129=rx132:tx129 +lane_to_serdes_map_nif_lane130=rx128:tx132 +lane_to_serdes_map_nif_lane131=rx131:tx134 +lane_to_serdes_map_nif_lane132=rx135:tx130 +lane_to_serdes_map_nif_lane133=rx133:tx128 +lane_to_serdes_map_nif_lane134=rx129:tx133 +lane_to_serdes_map_nif_lane135=rx130:tx135 +lane_to_serdes_map_nif_lane136=rx143:tx138 +lane_to_serdes_map_nif_lane137=rx140:tx136 +lane_to_serdes_map_nif_lane138=rx136:tx140 +lane_to_serdes_map_nif_lane139=rx139:tx143 +lane_to_serdes_map_nif_lane140=rx142:tx137 +lane_to_serdes_map_nif_lane141=rx141:tx139 +lane_to_serdes_map_nif_lane142=rx137:tx141 +lane_to_serdes_map_nif_lane143=rx138:tx142 + +######################### +### High Availability ### +######################### + +sw_state_max_size=750000000 + +#location of warmboot NV memory +#Allowed options for dnx are - 3:external storage in filesystem 4:driver will save the state directly in shared memory +stable_location=4 + +# Note that each unit should have a unique filename and that adapter does not play well with tmp and dev/shm folders. +stable_filename=/dev/shm/warmboot_data_0 +stable_filename.1=/dev/shm/warmboot_data_1 +stable_filename.2=/dev/shm/warmboot_data_2 + +#Maximum size for NVM used for WB storage, must be larger than sw_state_max_size.BCM8885X +stable_size=800000000 + +######################### +######################### +######################### + +tm_port_header_type_in_0=INJECTED_2_PP +tm_port_header_type_out_0=CPU + +tm_port_header_type_in_200=INJECTED_2_PP +tm_port_header_type_out_200=ETH +tm_port_header_type_in_201=INJECTED_2_PP +tm_port_header_type_out_201=ETH +tm_port_header_type_in_202=INJECTED_2_PP +tm_port_header_type_out_202=ETH +tm_port_header_type_in_203=INJECTED_2_PP +tm_port_header_type_out_203=ETH + +### SAT +## Enable SAT Interface. 0 - Disable, 1 - Enable (Default) +sat_enable=1 +ucode_port_218=SAT:core_0.218 +tm_port_header_type_out_218=CPU +tm_port_header_type_in_218=INJECTED_2 +ucode_port_219=SAT:core_1.219 +tm_port_header_type_out_219=CPU +tm_port_header_type_in_219=INJECTED_2 +port_init_speed_sat=400000 + +### RCY +sai_recycle_port_lane_base=0 +ucode_port_221=RCY.21:core_0.221 +ucode_port_222=RCY.22:core_1.222 +tm_port_header_type_out_221=ETH +tm_port_header_type_in_221=ETH +tm_port_header_type_out_222=ETH +tm_port_header_type_in_222=ETH +port_init_speed_221=400000 +port_init_speed_222=400000 + +#OLP port +tm_port_header_type_in_240=INJECTED_2 +tm_port_header_type_out_240=RAW + +# Set statically the region mode per region id +dtm_flow_mapping_mode_region_257=3 +dtm_flow_mapping_mode_region_258=3 +dtm_flow_mapping_mode_region_259=3 +dtm_flow_mapping_mode_region_260=3 +dtm_flow_mapping_mode_region_261=3 +dtm_flow_mapping_mode_region_262=3 +dtm_flow_mapping_mode_region_263=3 +dtm_flow_mapping_mode_region_264=3 +dtm_flow_mapping_mode_region_265=3 +dtm_flow_mapping_mode_region_266=7 +dtm_flow_mapping_mode_region_267=3 +dtm_flow_mapping_mode_region_268=3 +dtm_flow_mapping_mode_region_269=3 +dtm_flow_mapping_mode_region_270=3 +dtm_flow_mapping_mode_region_271=3 +dtm_flow_mapping_mode_region_272=3 +dtm_flow_mapping_mode_region_273=3 +dtm_flow_mapping_mode_region_274=3 +dtm_flow_mapping_mode_region_275=3 +dtm_flow_mapping_mode_region_276=3 +dtm_flow_mapping_mode_region_277=3 +dtm_flow_mapping_mode_region_278=3 +dtm_flow_mapping_mode_region_279=3 +dtm_flow_mapping_mode_region_280=3 +dtm_flow_mapping_mode_region_281=3 +dtm_flow_mapping_mode_region_282=3 +dtm_flow_mapping_mode_region_283=3 +dtm_flow_mapping_mode_region_284=3 +dtm_flow_mapping_mode_region_285=3 +dtm_flow_mapping_mode_region_286=3 +dtm_flow_mapping_mode_region_287=3 + +## Configure number of symmetric cores each region supports ## +dtm_flow_nof_remote_cores_region_1=2 +dtm_flow_nof_remote_cores_region_2=2 +dtm_flow_nof_remote_cores_region_3=2 +dtm_flow_nof_remote_cores_region_4=2 +dtm_flow_nof_remote_cores_region_5=2 +dtm_flow_nof_remote_cores_region_6=2 +dtm_flow_nof_remote_cores_region_7=2 +dtm_flow_nof_remote_cores_region_8=2 +dtm_flow_nof_remote_cores_region_9=2 +dtm_flow_nof_remote_cores_region_10=2 +dtm_flow_nof_remote_cores_region_11=2 +dtm_flow_nof_remote_cores_region_12=2 +dtm_flow_nof_remote_cores_region_13=2 +dtm_flow_nof_remote_cores_region_14=2 +dtm_flow_nof_remote_cores_region_15=2 +dtm_flow_nof_remote_cores_region_16=2 +dtm_flow_nof_remote_cores_region_17=2 +dtm_flow_nof_remote_cores_region_18=2 +dtm_flow_nof_remote_cores_region_19=2 +dtm_flow_nof_remote_cores_region_20=2 +dtm_flow_nof_remote_cores_region_21=2 +dtm_flow_nof_remote_cores_region_22=2 +dtm_flow_nof_remote_cores_region_23=2 +dtm_flow_nof_remote_cores_region_24=2 +dtm_flow_nof_remote_cores_region_25=2 +dtm_flow_nof_remote_cores_region_26=2 +dtm_flow_nof_remote_cores_region_27=2 +dtm_flow_nof_remote_cores_region_28=2 +dtm_flow_nof_remote_cores_region_29=2 +dtm_flow_nof_remote_cores_region_30=2 +dtm_flow_nof_remote_cores_region_31=2 +dtm_flow_nof_remote_cores_region_32=2 +dtm_flow_nof_remote_cores_region_33=2 +dtm_flow_nof_remote_cores_region_34=2 +dtm_flow_nof_remote_cores_region_35=2 +dtm_flow_nof_remote_cores_region_36=2 +dtm_flow_nof_remote_cores_region_37=2 +dtm_flow_nof_remote_cores_region_38=2 +dtm_flow_nof_remote_cores_region_39=2 +dtm_flow_nof_remote_cores_region_40=2 +dtm_flow_nof_remote_cores_region_41=2 +dtm_flow_nof_remote_cores_region_42=2 +dtm_flow_nof_remote_cores_region_43=2 +dtm_flow_nof_remote_cores_region_44=2 +dtm_flow_nof_remote_cores_region_45=2 +dtm_flow_nof_remote_cores_region_46=2 +dtm_flow_nof_remote_cores_region_47=2 +dtm_flow_nof_remote_cores_region_48=2 +dtm_flow_nof_remote_cores_region_49=2 +dtm_flow_nof_remote_cores_region_50=2 +dtm_flow_nof_remote_cores_region_51=2 +dtm_flow_nof_remote_cores_region_52=2 +dtm_flow_nof_remote_cores_region_53=2 +dtm_flow_nof_remote_cores_region_54=2 +dtm_flow_nof_remote_cores_region_55=2 +dtm_flow_nof_remote_cores_region_56=2 +dtm_flow_nof_remote_cores_region_57=2 +dtm_flow_nof_remote_cores_region_58=2 +dtm_flow_nof_remote_cores_region_59=2 +dtm_flow_nof_remote_cores_region_60=2 + +### MDB configuration ### +mdb_profile=balanced-exem + +### Descriptor-DMA configuration ### +dma_desc_aggregator_chain_length_max=1000 +dma_desc_aggregator_buff_size_kb=100 +dma_desc_aggregator_timeout_usec=1000 +dma_desc_aggregator_enable_specific_MDB_LPM=1 +dma_desc_aggregator_enable_specific_MDB_FEC=1 + +### Outlif configuarion ### +outlif_logical_to_physical_phase_map_1=S1 +outlif_logical_to_physical_phase_map_2=L1 +outlif_logical_to_physical_phase_map_3=XL +outlif_logical_to_physical_phase_map_4=L2 +outlif_logical_to_physical_phase_map_5=M1 +outlif_logical_to_physical_phase_map_6=M2 +outlif_logical_to_physical_phase_map_7=M3 +outlif_logical_to_physical_phase_map_8=S2 + +### Outlif data granularity configuration ### +outlif_physical_phase_data_granularity_S1=60 +outlif_physical_phase_data_granularity_S2=60 +outlif_physical_phase_data_granularity_M1=60 +outlif_physical_phase_data_granularity_M2=60 +outlif_physical_phase_data_granularity_M3=60 +outlif_physical_phase_data_granularity_L1=60 +outlif_physical_phase_data_granularity_L2=60 +outlif_physical_phase_data_granularity_XL=60 + +### Fabric configuration ### +# Enable link-training +port_init_cl72_sfi=1 +serdes_lane_config_cl72_auto_polarity_en=0 +serdes_lane_config_cl72_auto_polarity_en_sfi=1 +serdes_lane_config_cl72_restart_timeout_en=0 + +#SFI speed rate +port_init_speed_fabric=53125 + +## Fabric transmission mode +# Set the Connect mode to the Fabric +# Options: FE - presence of a Fabric device (single stage) +# SINGLE_FAP - stand-alone device +# MESH - devices in Mesh +# Note: If 'diag_chassis' is on, value will be override in dnx.soc +# to be FE instead of SINGLE_FAP. +fabric_connect_mode=FE + +fabric_logical_port_base=512 + +# Fabric lane mapping +lane_to_serdes_map_fabric_lane0=rx0:tx0 +lane_to_serdes_map_fabric_lane1=rx1:tx1 +lane_to_serdes_map_fabric_lane2=rx2:tx2 +lane_to_serdes_map_fabric_lane3=rx3:tx3 +lane_to_serdes_map_fabric_lane4=rx4:tx4 +lane_to_serdes_map_fabric_lane5=rx5:tx5 +lane_to_serdes_map_fabric_lane6=rx6:tx6 +lane_to_serdes_map_fabric_lane7=rx7:tx7 +lane_to_serdes_map_fabric_lane8=rx8:tx10 +lane_to_serdes_map_fabric_lane9=rx9:tx11 +lane_to_serdes_map_fabric_lane10=rx10:tx9 +lane_to_serdes_map_fabric_lane11=rx11:tx8 +lane_to_serdes_map_fabric_lane12=rx12:tx12 +lane_to_serdes_map_fabric_lane13=rx13:tx15 +lane_to_serdes_map_fabric_lane14=rx14:tx14 +lane_to_serdes_map_fabric_lane15=rx15:tx13 +lane_to_serdes_map_fabric_lane16=rx16:tx17 +lane_to_serdes_map_fabric_lane17=rx17:tx18 +lane_to_serdes_map_fabric_lane18=rx18:tx16 +lane_to_serdes_map_fabric_lane19=rx19:tx19 +lane_to_serdes_map_fabric_lane20=rx20:tx21 +lane_to_serdes_map_fabric_lane21=rx21:tx23 +lane_to_serdes_map_fabric_lane22=rx22:tx20 +lane_to_serdes_map_fabric_lane23=rx23:tx22 +lane_to_serdes_map_fabric_lane24=rx24:tx26 +lane_to_serdes_map_fabric_lane25=rx25:tx24 +lane_to_serdes_map_fabric_lane26=rx26:tx25 +lane_to_serdes_map_fabric_lane27=rx27:tx27 +lane_to_serdes_map_fabric_lane28=rx28:tx31 +lane_to_serdes_map_fabric_lane29=rx29:tx30 +lane_to_serdes_map_fabric_lane30=rx30:tx29 +lane_to_serdes_map_fabric_lane31=rx31:tx28 +lane_to_serdes_map_fabric_lane32=rx32:tx32 +lane_to_serdes_map_fabric_lane33=rx33:tx33 +lane_to_serdes_map_fabric_lane34=rx34:tx34 +lane_to_serdes_map_fabric_lane35=rx35:tx35 +lane_to_serdes_map_fabric_lane36=rx36:tx36 +lane_to_serdes_map_fabric_lane37=rx37:tx37 +lane_to_serdes_map_fabric_lane38=rx38:tx38 +lane_to_serdes_map_fabric_lane39=rx39:tx39 +lane_to_serdes_map_fabric_lane40=rx40:tx43 +lane_to_serdes_map_fabric_lane41=rx41:tx42 +lane_to_serdes_map_fabric_lane42=rx42:tx41 +lane_to_serdes_map_fabric_lane43=rx43:tx40 +lane_to_serdes_map_fabric_lane44=rx44:tx47 +lane_to_serdes_map_fabric_lane45=rx45:tx46 +lane_to_serdes_map_fabric_lane46=rx46:tx45 +lane_to_serdes_map_fabric_lane47=rx47:tx44 +lane_to_serdes_map_fabric_lane48=rx48:tx48 +lane_to_serdes_map_fabric_lane49=rx49:tx49 +lane_to_serdes_map_fabric_lane50=rx50:tx50 +lane_to_serdes_map_fabric_lane51=rx51:tx51 +lane_to_serdes_map_fabric_lane52=rx52:tx52 +lane_to_serdes_map_fabric_lane53=rx53:tx53 +lane_to_serdes_map_fabric_lane54=rx54:tx54 +lane_to_serdes_map_fabric_lane55=rx55:tx55 +lane_to_serdes_map_fabric_lane56=rx56:tx59 +lane_to_serdes_map_fabric_lane57=rx57:tx58 +lane_to_serdes_map_fabric_lane58=rx58:tx57 +lane_to_serdes_map_fabric_lane59=rx59:tx56 +lane_to_serdes_map_fabric_lane60=rx60:tx63 +lane_to_serdes_map_fabric_lane61=rx61:tx62 +lane_to_serdes_map_fabric_lane62=rx62:tx61 +lane_to_serdes_map_fabric_lane63=rx63:tx60 +lane_to_serdes_map_fabric_lane64=rx64:tx64 +lane_to_serdes_map_fabric_lane65=rx65:tx65 +lane_to_serdes_map_fabric_lane66=rx66:tx66 +lane_to_serdes_map_fabric_lane67=rx67:tx67 +lane_to_serdes_map_fabric_lane68=rx68:tx68 +lane_to_serdes_map_fabric_lane69=rx69:tx69 +lane_to_serdes_map_fabric_lane70=rx70:tx70 +lane_to_serdes_map_fabric_lane71=rx71:tx71 +lane_to_serdes_map_fabric_lane72=rx72:tx75 +lane_to_serdes_map_fabric_lane73=rx73:tx74 +lane_to_serdes_map_fabric_lane74=rx74:tx73 +lane_to_serdes_map_fabric_lane75=rx75:tx72 +lane_to_serdes_map_fabric_lane76=rx76:tx79 +lane_to_serdes_map_fabric_lane77=rx77:tx78 +lane_to_serdes_map_fabric_lane78=rx78:tx77 +lane_to_serdes_map_fabric_lane79=rx79:tx76 +lane_to_serdes_map_fabric_lane80=rx80:tx80 +lane_to_serdes_map_fabric_lane81=rx81:tx81 +lane_to_serdes_map_fabric_lane82=rx82:tx83 +lane_to_serdes_map_fabric_lane83=rx83:tx82 +lane_to_serdes_map_fabric_lane84=rx84:tx85 +lane_to_serdes_map_fabric_lane85=rx85:tx86 +lane_to_serdes_map_fabric_lane86=rx86:tx84 +lane_to_serdes_map_fabric_lane87=rx87:tx87 +lane_to_serdes_map_fabric_lane88=rx88:tx90 +lane_to_serdes_map_fabric_lane89=rx89:tx88 +lane_to_serdes_map_fabric_lane90=rx90:tx91 +lane_to_serdes_map_fabric_lane91=rx91:tx89 +lane_to_serdes_map_fabric_lane92=rx92:tx93 +lane_to_serdes_map_fabric_lane93=rx93:tx92 +lane_to_serdes_map_fabric_lane94=rx94:tx94 +lane_to_serdes_map_fabric_lane95=rx95:tx95 +lane_to_serdes_map_fabric_lane96=rx96:tx96 +lane_to_serdes_map_fabric_lane97=rx97:tx97 +lane_to_serdes_map_fabric_lane98=rx98:tx98 +lane_to_serdes_map_fabric_lane99=rx99:tx99 +lane_to_serdes_map_fabric_lane100=rx100:tx100 +lane_to_serdes_map_fabric_lane101=rx101:tx101 +lane_to_serdes_map_fabric_lane102=rx102:tx102 +lane_to_serdes_map_fabric_lane103=rx103:tx103 +lane_to_serdes_map_fabric_lane104=rx104:tx105 +lane_to_serdes_map_fabric_lane105=rx105:tx106 +lane_to_serdes_map_fabric_lane106=rx106:tx107 +lane_to_serdes_map_fabric_lane107=rx107:tx104 +lane_to_serdes_map_fabric_lane108=rx108:tx111 +lane_to_serdes_map_fabric_lane109=rx109:tx109 +lane_to_serdes_map_fabric_lane110=rx110:tx110 +lane_to_serdes_map_fabric_lane111=rx111:tx108 +lane_to_serdes_map_fabric_lane112=rx112:tx114 +lane_to_serdes_map_fabric_lane113=rx113:tx113 +lane_to_serdes_map_fabric_lane114=rx114:tx112 +lane_to_serdes_map_fabric_lane115=rx115:tx115 +lane_to_serdes_map_fabric_lane116=rx116:tx117 +lane_to_serdes_map_fabric_lane117=rx117:tx116 +lane_to_serdes_map_fabric_lane118=rx118:tx119 +lane_to_serdes_map_fabric_lane119=rx119:tx118 +lane_to_serdes_map_fabric_lane120=rx120:tx123 +lane_to_serdes_map_fabric_lane121=rx121:tx120 +lane_to_serdes_map_fabric_lane122=rx122:tx122 +lane_to_serdes_map_fabric_lane123=rx123:tx121 +lane_to_serdes_map_fabric_lane124=rx124:tx127 +lane_to_serdes_map_fabric_lane125=rx125:tx125 +lane_to_serdes_map_fabric_lane126=rx126:tx124 +lane_to_serdes_map_fabric_lane127=rx127:tx126 +lane_to_serdes_map_fabric_lane128=rx128:tx128 +lane_to_serdes_map_fabric_lane129=rx129:tx129 +lane_to_serdes_map_fabric_lane130=rx130:tx130 +lane_to_serdes_map_fabric_lane131=rx131:tx131 +lane_to_serdes_map_fabric_lane132=rx132:tx132 +lane_to_serdes_map_fabric_lane133=rx133:tx133 +lane_to_serdes_map_fabric_lane134=rx134:tx134 +lane_to_serdes_map_fabric_lane135=rx135:tx135 +lane_to_serdes_map_fabric_lane136=rx136:tx139 +lane_to_serdes_map_fabric_lane137=rx137:tx138 +lane_to_serdes_map_fabric_lane138=rx138:tx137 +lane_to_serdes_map_fabric_lane139=rx139:tx136 +lane_to_serdes_map_fabric_lane140=rx140:tx140 +lane_to_serdes_map_fabric_lane141=rx141:tx142 +lane_to_serdes_map_fabric_lane142=rx142:tx141 +lane_to_serdes_map_fabric_lane143=rx143:tx143 +lane_to_serdes_map_fabric_lane144=rx144:tx144 +lane_to_serdes_map_fabric_lane145=rx145:tx145 +lane_to_serdes_map_fabric_lane146=rx146:tx146 +lane_to_serdes_map_fabric_lane147=rx147:tx147 +lane_to_serdes_map_fabric_lane148=rx148:tx148 +lane_to_serdes_map_fabric_lane149=rx149:tx149 +lane_to_serdes_map_fabric_lane150=rx150:tx150 +lane_to_serdes_map_fabric_lane151=rx151:tx151 +lane_to_serdes_map_fabric_lane152=rx152:tx155 +lane_to_serdes_map_fabric_lane153=rx153:tx154 +lane_to_serdes_map_fabric_lane154=rx154:tx153 +lane_to_serdes_map_fabric_lane155=rx155:tx152 +lane_to_serdes_map_fabric_lane156=rx156:tx159 +lane_to_serdes_map_fabric_lane157=rx157:tx158 +lane_to_serdes_map_fabric_lane158=rx158:tx157 +lane_to_serdes_map_fabric_lane159=rx159:tx156 +lane_to_serdes_map_fabric_lane160=rx160:tx160 +lane_to_serdes_map_fabric_lane161=rx161:tx161 +lane_to_serdes_map_fabric_lane162=rx162:tx162 +lane_to_serdes_map_fabric_lane163=rx163:tx163 +lane_to_serdes_map_fabric_lane164=rx164:tx164 +lane_to_serdes_map_fabric_lane165=rx165:tx165 +lane_to_serdes_map_fabric_lane166=rx166:tx166 +lane_to_serdes_map_fabric_lane167=rx167:tx167 +lane_to_serdes_map_fabric_lane168=rx168:tx171 +lane_to_serdes_map_fabric_lane169=rx169:tx170 +lane_to_serdes_map_fabric_lane170=rx170:tx169 +lane_to_serdes_map_fabric_lane171=rx171:tx168 +lane_to_serdes_map_fabric_lane172=rx172:tx175 +lane_to_serdes_map_fabric_lane173=rx173:tx174 +lane_to_serdes_map_fabric_lane174=rx174:tx173 +lane_to_serdes_map_fabric_lane175=rx175:tx172 +lane_to_serdes_map_fabric_lane176=rx176:tx176 +lane_to_serdes_map_fabric_lane177=rx177:tx177 +lane_to_serdes_map_fabric_lane178=rx178:tx179 +lane_to_serdes_map_fabric_lane179=rx179:tx178 +lane_to_serdes_map_fabric_lane180=rx180:tx181 +lane_to_serdes_map_fabric_lane181=rx181:tx182 +lane_to_serdes_map_fabric_lane182=rx182:tx180 +lane_to_serdes_map_fabric_lane183=rx183:tx183 +lane_to_serdes_map_fabric_lane184=rx184:tx186 +lane_to_serdes_map_fabric_lane185=rx185:tx184 +lane_to_serdes_map_fabric_lane186=rx186:tx185 +lane_to_serdes_map_fabric_lane187=rx187:tx187 +lane_to_serdes_map_fabric_lane188=rx188:tx188 +lane_to_serdes_map_fabric_lane189=rx189:tx189 +lane_to_serdes_map_fabric_lane190=rx190:tx190 +lane_to_serdes_map_fabric_lane191=rx191:tx191 + +# +##Protocol trap look-up mode: +# Options: IN_LIF - Look-ups in the profile table are done by IN-LIF +# IN_PORT - Look-ups in the profile table are done by IN-PORT +protocol_traps_mode=IN_LIF + +# access definitions +schan_intr_enable=0 +tdma_intr_enable=0 +tslam_intr_enable=0 +miim_intr_enable=0 +schan_timeout_usec=300000 +tdma_timeout_usec=1000000 +tslam_timeout_usec=1000000 + +### Interrupts +appl_enable_intr_init=1 +polled_irq_mode=1 +# reduce CPU load, configure delay 100ms +polled_irq_delay=1000 + +# reduce the CPU load over adapter (caused by counter thread) +bcm_stat_interval=1000 + +# shadow memory +mem_cache_enable_ecc=1 +mem_cache_enable_parity=1 + +# serdes_nif/fabric_clk_freq_in/out configuration +serdes_nif_clk_freq_in=2 +serdes_nif_clk_freq_out=1 +serdes_fabric_clk_freq_in=2 +serdes_fabric_clk_freq_out=1 + +dport_map_direct=1 + +rif_id_max=0x6000 + +phy_rx_polarity_flip_phy0=0 +phy_rx_polarity_flip_phy1=0 +phy_rx_polarity_flip_phy2=0 +phy_rx_polarity_flip_phy3=0 +phy_rx_polarity_flip_phy4=0 +phy_rx_polarity_flip_phy5=0 +phy_rx_polarity_flip_phy6=0 +phy_rx_polarity_flip_phy7=0 +phy_rx_polarity_flip_phy8=1 +phy_rx_polarity_flip_phy9=1 +phy_rx_polarity_flip_phy10=0 +phy_rx_polarity_flip_phy11=1 +phy_rx_polarity_flip_phy12=1 +phy_rx_polarity_flip_phy13=1 +phy_rx_polarity_flip_phy14=1 +phy_rx_polarity_flip_phy15=1 +phy_rx_polarity_flip_phy16=0 +phy_rx_polarity_flip_phy17=0 +phy_rx_polarity_flip_phy18=0 +phy_rx_polarity_flip_phy19=0 +phy_rx_polarity_flip_phy20=0 +phy_rx_polarity_flip_phy21=0 +phy_rx_polarity_flip_phy22=0 +phy_rx_polarity_flip_phy23=0 +phy_rx_polarity_flip_phy24=0 +phy_rx_polarity_flip_phy25=0 +phy_rx_polarity_flip_phy26=0 +phy_rx_polarity_flip_phy27=0 +phy_rx_polarity_flip_phy28=0 +phy_rx_polarity_flip_phy29=0 +phy_rx_polarity_flip_phy30=0 +phy_rx_polarity_flip_phy31=0 +phy_rx_polarity_flip_phy32=0 +phy_rx_polarity_flip_phy33=0 +phy_rx_polarity_flip_phy34=0 +phy_rx_polarity_flip_phy35=0 +phy_rx_polarity_flip_phy36=0 +phy_rx_polarity_flip_phy37=0 +phy_rx_polarity_flip_phy38=0 +phy_rx_polarity_flip_phy39=0 +phy_rx_polarity_flip_phy40=0 +phy_rx_polarity_flip_phy41=0 +phy_rx_polarity_flip_phy42=0 +phy_rx_polarity_flip_phy43=0 +phy_rx_polarity_flip_phy44=0 +phy_rx_polarity_flip_phy45=0 +phy_rx_polarity_flip_phy46=0 +phy_rx_polarity_flip_phy47=0 +phy_rx_polarity_flip_phy48=0 +phy_rx_polarity_flip_phy49=0 +phy_rx_polarity_flip_phy50=0 +phy_rx_polarity_flip_phy51=0 +phy_rx_polarity_flip_phy52=0 +phy_rx_polarity_flip_phy53=0 +phy_rx_polarity_flip_phy54=0 +phy_rx_polarity_flip_phy55=0 +phy_rx_polarity_flip_phy56=0 +phy_rx_polarity_flip_phy57=0 +phy_rx_polarity_flip_phy58=0 +phy_rx_polarity_flip_phy59=0 +phy_rx_polarity_flip_phy60=0 +phy_rx_polarity_flip_phy61=0 +phy_rx_polarity_flip_phy62=0 +phy_rx_polarity_flip_phy63=0 +phy_rx_polarity_flip_phy64=0 +phy_rx_polarity_flip_phy65=0 +phy_rx_polarity_flip_phy66=0 +phy_rx_polarity_flip_phy67=0 +phy_rx_polarity_flip_phy68=0 +phy_rx_polarity_flip_phy69=0 +phy_rx_polarity_flip_phy70=0 +phy_rx_polarity_flip_phy71=0 +phy_rx_polarity_flip_phy72=1 +phy_rx_polarity_flip_phy73=1 +phy_rx_polarity_flip_phy74=1 +phy_rx_polarity_flip_phy75=1 +phy_rx_polarity_flip_phy76=1 +phy_rx_polarity_flip_phy77=1 +phy_rx_polarity_flip_phy78=1 +phy_rx_polarity_flip_phy79=1 +phy_rx_polarity_flip_phy80=0 +phy_rx_polarity_flip_phy81=0 +phy_rx_polarity_flip_phy82=0 +phy_rx_polarity_flip_phy83=0 +phy_rx_polarity_flip_phy84=0 +phy_rx_polarity_flip_phy85=0 +phy_rx_polarity_flip_phy86=0 +phy_rx_polarity_flip_phy87=0 +phy_rx_polarity_flip_phy88=0 +phy_rx_polarity_flip_phy89=0 +phy_rx_polarity_flip_phy90=1 +phy_rx_polarity_flip_phy91=0 +phy_rx_polarity_flip_phy92=0 +phy_rx_polarity_flip_phy93=0 +phy_rx_polarity_flip_phy94=0 +phy_rx_polarity_flip_phy95=0 +phy_rx_polarity_flip_phy96=0 +phy_rx_polarity_flip_phy97=0 +phy_rx_polarity_flip_phy98=0 +phy_rx_polarity_flip_phy99=0 +phy_rx_polarity_flip_phy100=0 +phy_rx_polarity_flip_phy101=0 +phy_rx_polarity_flip_phy102=0 +phy_rx_polarity_flip_phy103=0 +phy_rx_polarity_flip_phy104=0 +phy_rx_polarity_flip_phy105=0 +phy_rx_polarity_flip_phy106=0 +phy_rx_polarity_flip_phy107=0 +phy_rx_polarity_flip_phy108=0 +phy_rx_polarity_flip_phy109=0 +phy_rx_polarity_flip_phy110=0 +phy_rx_polarity_flip_phy111=0 +phy_rx_polarity_flip_phy112=0 +phy_rx_polarity_flip_phy113=0 +phy_rx_polarity_flip_phy114=0 +phy_rx_polarity_flip_phy115=0 +phy_rx_polarity_flip_phy116=0 +phy_rx_polarity_flip_phy117=0 +phy_rx_polarity_flip_phy118=0 +phy_rx_polarity_flip_phy119=0 +phy_rx_polarity_flip_phy120=0 +phy_rx_polarity_flip_phy121=0 +phy_rx_polarity_flip_phy122=0 +phy_rx_polarity_flip_phy123=0 +phy_rx_polarity_flip_phy124=0 +phy_rx_polarity_flip_phy125=0 +phy_rx_polarity_flip_phy126=0 +phy_rx_polarity_flip_phy127=0 +phy_rx_polarity_flip_phy128=0 +phy_rx_polarity_flip_phy129=0 +phy_rx_polarity_flip_phy130=0 +phy_rx_polarity_flip_phy131=0 +phy_rx_polarity_flip_phy132=0 +phy_rx_polarity_flip_phy133=0 +phy_rx_polarity_flip_phy134=0 +phy_rx_polarity_flip_phy135=0 +phy_rx_polarity_flip_phy136=0 +phy_rx_polarity_flip_phy137=0 +phy_rx_polarity_flip_phy138=0 +phy_rx_polarity_flip_phy139=0 +phy_rx_polarity_flip_phy140=0 +phy_rx_polarity_flip_phy141=0 +phy_rx_polarity_flip_phy142=0 +phy_rx_polarity_flip_phy143=0 +phy_tx_polarity_flip_phy0=1 +phy_tx_polarity_flip_phy1=1 +phy_tx_polarity_flip_phy2=1 +phy_tx_polarity_flip_phy3=1 +phy_tx_polarity_flip_phy4=1 +phy_tx_polarity_flip_phy5=1 +phy_tx_polarity_flip_phy6=1 +phy_tx_polarity_flip_phy7=1 +phy_tx_polarity_flip_phy8=1 +phy_tx_polarity_flip_phy9=0 +phy_tx_polarity_flip_phy10=1 +phy_tx_polarity_flip_phy11=1 +phy_tx_polarity_flip_phy12=1 +phy_tx_polarity_flip_phy13=1 +phy_tx_polarity_flip_phy14=1 +phy_tx_polarity_flip_phy15=1 +phy_tx_polarity_flip_phy16=1 +phy_tx_polarity_flip_phy17=1 +phy_tx_polarity_flip_phy18=1 +phy_tx_polarity_flip_phy19=1 +phy_tx_polarity_flip_phy20=1 +phy_tx_polarity_flip_phy21=1 +phy_tx_polarity_flip_phy22=1 +phy_tx_polarity_flip_phy23=1 +phy_tx_polarity_flip_phy24=1 +phy_tx_polarity_flip_phy25=1 +phy_tx_polarity_flip_phy26=1 +phy_tx_polarity_flip_phy27=1 +phy_tx_polarity_flip_phy28=1 +phy_tx_polarity_flip_phy29=1 +phy_tx_polarity_flip_phy30=1 +phy_tx_polarity_flip_phy31=1 +phy_tx_polarity_flip_phy32=1 +phy_tx_polarity_flip_phy33=1 +phy_tx_polarity_flip_phy34=1 +phy_tx_polarity_flip_phy35=1 +phy_tx_polarity_flip_phy36=1 +phy_tx_polarity_flip_phy37=1 +phy_tx_polarity_flip_phy38=1 +phy_tx_polarity_flip_phy39=1 +phy_tx_polarity_flip_phy40=1 +phy_tx_polarity_flip_phy41=1 +phy_tx_polarity_flip_phy42=1 +phy_tx_polarity_flip_phy43=1 +phy_tx_polarity_flip_phy44=1 +phy_tx_polarity_flip_phy45=1 +phy_tx_polarity_flip_phy46=1 +phy_tx_polarity_flip_phy47=1 +phy_tx_polarity_flip_phy48=1 +phy_tx_polarity_flip_phy49=1 +phy_tx_polarity_flip_phy50=1 +phy_tx_polarity_flip_phy51=1 +phy_tx_polarity_flip_phy52=1 +phy_tx_polarity_flip_phy53=1 +phy_tx_polarity_flip_phy54=1 +phy_tx_polarity_flip_phy55=1 +phy_tx_polarity_flip_phy56=1 +phy_tx_polarity_flip_phy57=1 +phy_tx_polarity_flip_phy58=1 +phy_tx_polarity_flip_phy59=1 +phy_tx_polarity_flip_phy60=1 +phy_tx_polarity_flip_phy61=1 +phy_tx_polarity_flip_phy62=1 +phy_tx_polarity_flip_phy63=1 +phy_tx_polarity_flip_phy64=1 +phy_tx_polarity_flip_phy65=1 +phy_tx_polarity_flip_phy66=1 +phy_tx_polarity_flip_phy67=1 +phy_tx_polarity_flip_phy68=1 +phy_tx_polarity_flip_phy69=1 +phy_tx_polarity_flip_phy70=1 +phy_tx_polarity_flip_phy71=1 +phy_tx_polarity_flip_phy72=0 +phy_tx_polarity_flip_phy73=0 +phy_tx_polarity_flip_phy74=0 +phy_tx_polarity_flip_phy75=0 +phy_tx_polarity_flip_phy76=0 +phy_tx_polarity_flip_phy77=0 +phy_tx_polarity_flip_phy78=0 +phy_tx_polarity_flip_phy79=0 +phy_tx_polarity_flip_phy80=0 +phy_tx_polarity_flip_phy81=0 +phy_tx_polarity_flip_phy82=0 +phy_tx_polarity_flip_phy83=0 +phy_tx_polarity_flip_phy84=0 +phy_tx_polarity_flip_phy85=0 +phy_tx_polarity_flip_phy86=0 +phy_tx_polarity_flip_phy87=0 +phy_tx_polarity_flip_phy88=1 +phy_tx_polarity_flip_phy89=1 +phy_tx_polarity_flip_phy90=1 +phy_tx_polarity_flip_phy91=1 +phy_tx_polarity_flip_phy92=1 +phy_tx_polarity_flip_phy93=1 +phy_tx_polarity_flip_phy94=1 +phy_tx_polarity_flip_phy95=1 +phy_tx_polarity_flip_phy96=1 +phy_tx_polarity_flip_phy97=1 +phy_tx_polarity_flip_phy98=1 +phy_tx_polarity_flip_phy99=1 +phy_tx_polarity_flip_phy100=1 +phy_tx_polarity_flip_phy101=1 +phy_tx_polarity_flip_phy102=1 +phy_tx_polarity_flip_phy103=1 +phy_tx_polarity_flip_phy104=1 +phy_tx_polarity_flip_phy105=1 +phy_tx_polarity_flip_phy106=1 +phy_tx_polarity_flip_phy107=1 +phy_tx_polarity_flip_phy108=1 +phy_tx_polarity_flip_phy109=1 +phy_tx_polarity_flip_phy110=1 +phy_tx_polarity_flip_phy111=1 +phy_tx_polarity_flip_phy112=1 +phy_tx_polarity_flip_phy113=1 +phy_tx_polarity_flip_phy114=1 +phy_tx_polarity_flip_phy115=1 +phy_tx_polarity_flip_phy116=1 +phy_tx_polarity_flip_phy117=1 +phy_tx_polarity_flip_phy118=1 +phy_tx_polarity_flip_phy119=1 +phy_tx_polarity_flip_phy120=1 +phy_tx_polarity_flip_phy121=1 +phy_tx_polarity_flip_phy122=1 +phy_tx_polarity_flip_phy123=1 +phy_tx_polarity_flip_phy124=1 +phy_tx_polarity_flip_phy125=1 +phy_tx_polarity_flip_phy126=1 +phy_tx_polarity_flip_phy127=1 +phy_tx_polarity_flip_phy128=1 +phy_tx_polarity_flip_phy129=1 +phy_tx_polarity_flip_phy130=1 +phy_tx_polarity_flip_phy131=1 +phy_tx_polarity_flip_phy132=1 +phy_tx_polarity_flip_phy133=1 +phy_tx_polarity_flip_phy134=1 +phy_tx_polarity_flip_phy135=1 +phy_tx_polarity_flip_phy136=1 +phy_tx_polarity_flip_phy137=1 +phy_tx_polarity_flip_phy138=1 +phy_tx_polarity_flip_phy139=1 +phy_tx_polarity_flip_phy140=1 +phy_tx_polarity_flip_phy141=1 +phy_tx_polarity_flip_phy142=1 +phy_tx_polarity_flip_phy143=1 + +serdes_tx_taps_1=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_2=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_3=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_4=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_5=nrz:-5:80:-23:0:0:0 +serdes_tx_taps_6=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_7=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_8=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_9=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_10=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_11=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_12=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_13=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_14=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_15=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_16=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_17=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_18=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_19=nrz:-6:85:-21:0:0:0 +serdes_tx_taps_20=nrz:-5:83:-22:0:0:0 +serdes_tx_taps_21=nrz:-4:75:-21:0:0:0 +serdes_tx_taps_22=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_23=nrz:-6:85:-21:0:0:0 +serdes_tx_taps_24=nrz:-5:83:-22:0:0:0 +serdes_tx_taps_25=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_26=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_27=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_28=nrz:-5:80:-23:0:0:0 +serdes_tx_taps_29=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_30=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_31=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_32=nrz:-5:80:-23:0:0:0 +serdes_tx_taps_33=nrz:-5:83:-22:0:0:0 +serdes_tx_taps_34=nrz:-5:83:-22:0:0:0 +serdes_tx_taps_35=nrz:-4:75:-21:0:0:0 +serdes_tx_taps_36=nrz:-8:89:-29:0:0:0 + +xflow_macsec_secure_chan_to_num_secure_assoc_encrypt=2 +xflow_macsec_secure_chan_to_num_secure_assoc_decrypt=2 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/0/port_config.ini b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/0/port_config.ini new file mode 100644 index 000000000000..4756e475658e --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/0/port_config.ini @@ -0,0 +1,21 @@ +# name lanes alias index role speed asic_port_name coreId corePortId numVoq +Ethernet0 72,73,74,75 Ethernet1/1 1 Ext 100000 Eth0-ASIC0 1 1 8 +Ethernet8 80,81,82,83 Ethernet2/1 2 Ext 100000 Eth8-ASIC0 1 2 8 +Ethernet16 88,89,90,91 Ethernet3/1 3 Ext 100000 Eth16-ASIC0 1 3 8 +Ethernet24 96,97,98,99 Ethernet4/1 4 Ext 100000 Eth24-ASIC0 1 4 8 +Ethernet32 104,105,106,107 Ethernet5/1 5 Ext 100000 Eth32-ASIC0 1 5 8 +Ethernet40 112,113,114,115 Ethernet6/1 6 Ext 100000 Eth40-ASIC0 1 6 8 +Ethernet48 120,121,122,123 Ethernet7/1 7 Ext 100000 Eth48-ASIC0 1 7 8 +Ethernet56 128,129,130,131 Ethernet8/1 8 Ext 100000 Eth56-ASIC0 1 8 8 +Ethernet64 136,137,138,139 Ethernet9/1 9 Ext 100000 Eth64-ASIC0 1 9 8 +Ethernet72 64,65,66,67 Ethernet10/1 10 Ext 100000 Eth72-ASIC0 0 10 8 +Ethernet80 56,57,58,59 Ethernet11/1 11 Ext 100000 Eth80-ASIC0 0 11 8 +Ethernet88 48,49,50,51 Ethernet12/1 12 Ext 100000 Eth88-ASIC0 0 12 8 +Ethernet96 40,41,42,43 Ethernet13/1 13 Ext 100000 Eth96-ASIC0 0 13 8 +Ethernet104 32,33,34,35 Ethernet14/1 14 Ext 100000 Eth104-ASIC0 0 14 8 +Ethernet112 24,25,26,27 Ethernet15/1 15 Ext 100000 Eth112-ASIC0 0 15 8 +Ethernet120 16,17,18,19 Ethernet16/1 16 Ext 100000 Eth120-ASIC0 0 16 8 +Ethernet128 8,9,10,11 Ethernet17/1 17 Ext 100000 Eth128-ASIC0 0 17 8 +Ethernet136 0,1,2,3 Ethernet18/1 18 Ext 100000 Eth136-ASIC0 0 18 8 +Ethernet-Rec0 221 Recirc0/0 19 Rec 400000 Rcy0-ASIC0 0 221 8 +Ethernet-IB0 222 Recirc0/1 20 Inb 400000 Rcy1-ASIC0 1 222 8 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/0/sai.profile b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/0/sai.profile new file mode 100644 index 000000000000..894b300ad733 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/0/sai.profile @@ -0,0 +1,2 @@ +SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/j2p-a7800r3a-36d-36x400G.config.bcm + diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/1/context_config.json b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/1/context_config.json new file mode 120000 index 000000000000..3db0e8ed3d9b --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/1/context_config.json @@ -0,0 +1 @@ +../0/context_config.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/1/j2p-a7800r3a-36d-36x400G.config.bcm b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/1/j2p-a7800r3a-36d-36x400G.config.bcm new file mode 100644 index 000000000000..b30d9d238b29 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/1/j2p-a7800r3a-36d-36x400G.config.bcm @@ -0,0 +1,984 @@ +soc_family=BCM8885X + +dpp_db_path=/usr/share/bcm/db + +#################################################### +##Reference applications related properties - Start +#################################################### + +## PMF small EXEM connected stage: +# Options: IPMF2 - Ingress PMF 2 stage can perform small EXEM lookups. +# IPMF3 - Ingress PMF 3 stage can perform small EXEM lookups. +## PMF small EXEM connected stage: +# Options: IPMF2 - Ingress PMF 2 stage can perform small EXEM lookups. +# IPMF3 - Ingress PMF 3 stage can perform small EXEM lookups. +pmf_sexem3_stage=IPMF2 + +#################################################### +##Reference applications related properties - End +#################################################### + +# Jericho2-mode (description 0x1 used for Jericho 2 mode) +system_headers_mode=1 + +# HW mode to support 1024 16-member system wide LAGs +trunk_group_max_members=16 + +# Disable link-training +port_init_cl72=0 + +###Default interfaces for Jericho2Plus +#CPU interfaces +ucode_port_0=CPU.0:core_0.0 +ucode_port_200=CPU.8:core_1.200 +ucode_port_201=CPU.16:core_0.201 +ucode_port_202=CPU.24:core_1.202 +ucode_port_203=CPU.32:core_0.203 + +#NIF ETH interfaces on device +ucode_port_1=CGE18:core_1.1 +ucode_port_2=CGE20:core_1.2 +ucode_port_3=CGE22:core_1.3 +ucode_port_4=CGE24:core_1.4 +ucode_port_5=CGE26:core_1.5 +ucode_port_6=CGE28:core_1.6 +ucode_port_7=CGE30:core_1.7 +ucode_port_8=CGE32:core_1.8 +ucode_port_9=CGE34:core_1.9 + +ucode_port_10=CGE16:core_0.10 +ucode_port_11=CGE14:core_0.11 +ucode_port_12=CGE12:core_0.12 +ucode_port_13=CGE10:core_0.13 +ucode_port_14=CGE8:core_0.14 +ucode_port_15=CGE6:core_0.15 +ucode_port_16=CGE4:core_0.16 +ucode_port_17=CGE2:core_0.17 +ucode_port_18=CGE0:core_0.18 + +#NIF default speeds +port_init_speed_xe=10000 +port_init_speed_xl=40000 +port_init_speed_le=50000 +port_init_speed_ce=100000 +port_init_speed_cc=200000 +port_init_speed_cd=400000 +port_init_speed_il=10312 + +port_priorities=8 + +#special ports +ucode_port_240=OLP:core_0.240 + +# NIF lane mapping +lane_to_serdes_map_nif_lane0=rx3:tx4 +lane_to_serdes_map_nif_lane1=rx6:tx1 +lane_to_serdes_map_nif_lane2=rx7:tx5 +lane_to_serdes_map_nif_lane3=rx4:tx7 +lane_to_serdes_map_nif_lane4=rx1:tx2 +lane_to_serdes_map_nif_lane5=rx0:tx0 +lane_to_serdes_map_nif_lane6=rx5:tx3 +lane_to_serdes_map_nif_lane7=rx2:tx6 +lane_to_serdes_map_nif_lane8=rx10:tx11 +lane_to_serdes_map_nif_lane9=rx8:tx8 +lane_to_serdes_map_nif_lane10=rx14:tx12 +lane_to_serdes_map_nif_lane11=rx15:tx15 +lane_to_serdes_map_nif_lane12=rx13:tx10 +lane_to_serdes_map_nif_lane13=rx9:tx9 +lane_to_serdes_map_nif_lane14=rx11:tx13 +lane_to_serdes_map_nif_lane15=rx12:tx14 +lane_to_serdes_map_nif_lane16=rx16:tx17 +lane_to_serdes_map_nif_lane17=rx19:tx21 +lane_to_serdes_map_nif_lane18=rx21:tx18 +lane_to_serdes_map_nif_lane19=rx18:tx16 +lane_to_serdes_map_nif_lane20=rx17:tx23 +lane_to_serdes_map_nif_lane21=rx20:tx22 +lane_to_serdes_map_nif_lane22=rx22:tx20 +lane_to_serdes_map_nif_lane23=rx23:tx19 +lane_to_serdes_map_nif_lane24=rx26:tx28 +lane_to_serdes_map_nif_lane25=rx29:tx31 +lane_to_serdes_map_nif_lane26=rx31:tx29 +lane_to_serdes_map_nif_lane27=rx28:tx27 +lane_to_serdes_map_nif_lane28=rx25:tx25 +lane_to_serdes_map_nif_lane29=rx24:tx30 +lane_to_serdes_map_nif_lane30=rx30:tx24 +lane_to_serdes_map_nif_lane31=rx27:tx26 +lane_to_serdes_map_nif_lane32=rx32:tx39 +lane_to_serdes_map_nif_lane33=rx33:tx38 +lane_to_serdes_map_nif_lane34=rx38:tx32 +lane_to_serdes_map_nif_lane35=rx39:tx33 +lane_to_serdes_map_nif_lane36=rx35:tx37 +lane_to_serdes_map_nif_lane37=rx34:tx36 +lane_to_serdes_map_nif_lane38=rx36:tx34 +lane_to_serdes_map_nif_lane39=rx37:tx35 +lane_to_serdes_map_nif_lane40=rx40:tx41 +lane_to_serdes_map_nif_lane41=rx43:tx45 +lane_to_serdes_map_nif_lane42=rx45:tx42 +lane_to_serdes_map_nif_lane43=rx42:tx40 +lane_to_serdes_map_nif_lane44=rx41:tx47 +lane_to_serdes_map_nif_lane45=rx44:tx46 +lane_to_serdes_map_nif_lane46=rx46:tx44 +lane_to_serdes_map_nif_lane47=rx47:tx43 +lane_to_serdes_map_nif_lane48=rx50:tx52 +lane_to_serdes_map_nif_lane49=rx53:tx55 +lane_to_serdes_map_nif_lane50=rx55:tx53 +lane_to_serdes_map_nif_lane51=rx52:tx51 +lane_to_serdes_map_nif_lane52=rx49:tx49 +lane_to_serdes_map_nif_lane53=rx48:tx54 +lane_to_serdes_map_nif_lane54=rx54:tx48 +lane_to_serdes_map_nif_lane55=rx51:tx50 +lane_to_serdes_map_nif_lane56=rx56:tx63 +lane_to_serdes_map_nif_lane57=rx57:tx62 +lane_to_serdes_map_nif_lane58=rx62:tx56 +lane_to_serdes_map_nif_lane59=rx63:tx57 +lane_to_serdes_map_nif_lane60=rx59:tx61 +lane_to_serdes_map_nif_lane61=rx58:tx60 +lane_to_serdes_map_nif_lane62=rx60:tx58 +lane_to_serdes_map_nif_lane63=rx61:tx59 +lane_to_serdes_map_nif_lane64=rx64:tx65 +lane_to_serdes_map_nif_lane65=rx67:tx69 +lane_to_serdes_map_nif_lane66=rx69:tx66 +lane_to_serdes_map_nif_lane67=rx66:tx64 +lane_to_serdes_map_nif_lane68=rx65:tx71 +lane_to_serdes_map_nif_lane69=rx68:tx70 +lane_to_serdes_map_nif_lane70=rx70:tx68 +lane_to_serdes_map_nif_lane71=rx71:tx67 +lane_to_serdes_map_nif_lane72=rx79:tx74 +lane_to_serdes_map_nif_lane73=rx76:tx75 +lane_to_serdes_map_nif_lane74=rx72:tx76 +lane_to_serdes_map_nif_lane75=rx74:tx73 +lane_to_serdes_map_nif_lane76=rx77:tx79 +lane_to_serdes_map_nif_lane77=rx78:tx78 +lane_to_serdes_map_nif_lane78=rx73:tx77 +lane_to_serdes_map_nif_lane79=rx75:tx72 +lane_to_serdes_map_nif_lane80=rx86:tx86 +lane_to_serdes_map_nif_lane81=rx83:tx87 +lane_to_serdes_map_nif_lane82=rx82:tx81 +lane_to_serdes_map_nif_lane83=rx85:tx80 +lane_to_serdes_map_nif_lane84=rx87:tx85 +lane_to_serdes_map_nif_lane85=rx84:tx84 +lane_to_serdes_map_nif_lane86=rx80:tx82 +lane_to_serdes_map_nif_lane87=rx81:tx83 +lane_to_serdes_map_nif_lane88=rx95:tx90 +lane_to_serdes_map_nif_lane89=rx92:tx88 +lane_to_serdes_map_nif_lane90=rx88:tx92 +lane_to_serdes_map_nif_lane91=rx91:tx95 +lane_to_serdes_map_nif_lane92=rx94:tx89 +lane_to_serdes_map_nif_lane93=rx93:tx91 +lane_to_serdes_map_nif_lane94=rx89:tx93 +lane_to_serdes_map_nif_lane95=rx90:tx94 +lane_to_serdes_map_nif_lane96=rx103:tx97 +lane_to_serdes_map_nif_lane97=rx100:tx96 +lane_to_serdes_map_nif_lane98=rx96:tx100 +lane_to_serdes_map_nif_lane99=rx99:tx103 +lane_to_serdes_map_nif_lane100=rx102:tx99 +lane_to_serdes_map_nif_lane101=rx101:tx98 +lane_to_serdes_map_nif_lane102=rx97:tx101 +lane_to_serdes_map_nif_lane103=rx98:tx102 +lane_to_serdes_map_nif_lane104=rx110:tx107 +lane_to_serdes_map_nif_lane105=rx108:tx105 +lane_to_serdes_map_nif_lane106=rx104:tx108 +lane_to_serdes_map_nif_lane107=rx107:tx110 +lane_to_serdes_map_nif_lane108=rx111:tx106 +lane_to_serdes_map_nif_lane109=rx109:tx104 +lane_to_serdes_map_nif_lane110=rx105:tx109 +lane_to_serdes_map_nif_lane111=rx106:tx111 +lane_to_serdes_map_nif_lane112=rx119:tx114 +lane_to_serdes_map_nif_lane113=rx116:tx112 +lane_to_serdes_map_nif_lane114=rx112:tx116 +lane_to_serdes_map_nif_lane115=rx115:tx119 +lane_to_serdes_map_nif_lane116=rx118:tx113 +lane_to_serdes_map_nif_lane117=rx117:tx115 +lane_to_serdes_map_nif_lane118=rx113:tx117 +lane_to_serdes_map_nif_lane119=rx114:tx118 +lane_to_serdes_map_nif_lane120=rx127:tx121 +lane_to_serdes_map_nif_lane121=rx124:tx120 +lane_to_serdes_map_nif_lane122=rx120:tx124 +lane_to_serdes_map_nif_lane123=rx123:tx127 +lane_to_serdes_map_nif_lane124=rx126:tx123 +lane_to_serdes_map_nif_lane125=rx125:tx122 +lane_to_serdes_map_nif_lane126=rx121:tx125 +lane_to_serdes_map_nif_lane127=rx122:tx126 +lane_to_serdes_map_nif_lane128=rx134:tx131 +lane_to_serdes_map_nif_lane129=rx132:tx129 +lane_to_serdes_map_nif_lane130=rx128:tx132 +lane_to_serdes_map_nif_lane131=rx131:tx134 +lane_to_serdes_map_nif_lane132=rx135:tx130 +lane_to_serdes_map_nif_lane133=rx133:tx128 +lane_to_serdes_map_nif_lane134=rx129:tx133 +lane_to_serdes_map_nif_lane135=rx130:tx135 +lane_to_serdes_map_nif_lane136=rx143:tx138 +lane_to_serdes_map_nif_lane137=rx140:tx136 +lane_to_serdes_map_nif_lane138=rx136:tx140 +lane_to_serdes_map_nif_lane139=rx139:tx143 +lane_to_serdes_map_nif_lane140=rx142:tx137 +lane_to_serdes_map_nif_lane141=rx141:tx139 +lane_to_serdes_map_nif_lane142=rx137:tx141 +lane_to_serdes_map_nif_lane143=rx138:tx142 + +######################### +### High Availability ### +######################### + +sw_state_max_size=750000000 + +#location of warmboot NV memory +#Allowed options for dnx are - 3:external storage in filesystem 4:driver will save the state directly in shared memory +stable_location=4 + +# Note that each unit should have a unique filename and that adapter does not play well with tmp and dev/shm folders. +stable_filename=/dev/shm/warmboot_data_0 +stable_filename.1=/dev/shm/warmboot_data_1 +stable_filename.2=/dev/shm/warmboot_data_2 + +#Maximum size for NVM used for WB storage, must be larger than sw_state_max_size.BCM8885X +stable_size=800000000 + +######################### +######################### +######################### + +tm_port_header_type_in_0=INJECTED_2_PP +tm_port_header_type_out_0=CPU + +tm_port_header_type_in_200=INJECTED_2_PP +tm_port_header_type_out_200=ETH +tm_port_header_type_in_201=INJECTED_2_PP +tm_port_header_type_out_201=ETH +tm_port_header_type_in_202=INJECTED_2_PP +tm_port_header_type_out_202=ETH +tm_port_header_type_in_203=INJECTED_2_PP +tm_port_header_type_out_203=ETH + +### SAT +## Enable SAT Interface. 0 - Disable, 1 - Enable (Default) +sat_enable=1 +ucode_port_218=SAT:core_0.218 +tm_port_header_type_out_218=CPU +tm_port_header_type_in_218=INJECTED_2 +ucode_port_219=SAT:core_1.219 +tm_port_header_type_out_219=CPU +tm_port_header_type_in_219=INJECTED_2 +port_init_speed_sat=400000 + +### RCY +sai_recycle_port_lane_base=0 +ucode_port_221=RCY.21:core_0.221 +ucode_port_222=RCY.22:core_1.222 +tm_port_header_type_out_221=ETH +tm_port_header_type_in_221=ETH +tm_port_header_type_out_222=ETH +tm_port_header_type_in_222=ETH +port_init_speed_221=400000 +port_init_speed_222=400000 + +#OLP port +tm_port_header_type_in_240=INJECTED_2 +tm_port_header_type_out_240=RAW + +# Set statically the region mode per region id +dtm_flow_mapping_mode_region_257=3 +dtm_flow_mapping_mode_region_258=3 +dtm_flow_mapping_mode_region_259=3 +dtm_flow_mapping_mode_region_260=3 +dtm_flow_mapping_mode_region_261=3 +dtm_flow_mapping_mode_region_262=3 +dtm_flow_mapping_mode_region_263=3 +dtm_flow_mapping_mode_region_264=3 +dtm_flow_mapping_mode_region_265=3 +dtm_flow_mapping_mode_region_266=7 +dtm_flow_mapping_mode_region_267=3 +dtm_flow_mapping_mode_region_268=3 +dtm_flow_mapping_mode_region_269=3 +dtm_flow_mapping_mode_region_270=3 +dtm_flow_mapping_mode_region_271=3 +dtm_flow_mapping_mode_region_272=3 +dtm_flow_mapping_mode_region_273=3 +dtm_flow_mapping_mode_region_274=3 +dtm_flow_mapping_mode_region_275=3 +dtm_flow_mapping_mode_region_276=3 +dtm_flow_mapping_mode_region_277=3 +dtm_flow_mapping_mode_region_278=3 +dtm_flow_mapping_mode_region_279=3 +dtm_flow_mapping_mode_region_280=3 +dtm_flow_mapping_mode_region_281=3 +dtm_flow_mapping_mode_region_282=3 +dtm_flow_mapping_mode_region_283=3 +dtm_flow_mapping_mode_region_284=3 +dtm_flow_mapping_mode_region_285=3 +dtm_flow_mapping_mode_region_286=3 +dtm_flow_mapping_mode_region_287=3 + +## Configure number of symmetric cores each region supports ## +dtm_flow_nof_remote_cores_region_1=2 +dtm_flow_nof_remote_cores_region_2=2 +dtm_flow_nof_remote_cores_region_3=2 +dtm_flow_nof_remote_cores_region_4=2 +dtm_flow_nof_remote_cores_region_5=2 +dtm_flow_nof_remote_cores_region_6=2 +dtm_flow_nof_remote_cores_region_7=2 +dtm_flow_nof_remote_cores_region_8=2 +dtm_flow_nof_remote_cores_region_9=2 +dtm_flow_nof_remote_cores_region_10=2 +dtm_flow_nof_remote_cores_region_11=2 +dtm_flow_nof_remote_cores_region_12=2 +dtm_flow_nof_remote_cores_region_13=2 +dtm_flow_nof_remote_cores_region_14=2 +dtm_flow_nof_remote_cores_region_15=2 +dtm_flow_nof_remote_cores_region_16=2 +dtm_flow_nof_remote_cores_region_17=2 +dtm_flow_nof_remote_cores_region_18=2 +dtm_flow_nof_remote_cores_region_19=2 +dtm_flow_nof_remote_cores_region_20=2 +dtm_flow_nof_remote_cores_region_21=2 +dtm_flow_nof_remote_cores_region_22=2 +dtm_flow_nof_remote_cores_region_23=2 +dtm_flow_nof_remote_cores_region_24=2 +dtm_flow_nof_remote_cores_region_25=2 +dtm_flow_nof_remote_cores_region_26=2 +dtm_flow_nof_remote_cores_region_27=2 +dtm_flow_nof_remote_cores_region_28=2 +dtm_flow_nof_remote_cores_region_29=2 +dtm_flow_nof_remote_cores_region_30=2 +dtm_flow_nof_remote_cores_region_31=2 +dtm_flow_nof_remote_cores_region_32=2 +dtm_flow_nof_remote_cores_region_33=2 +dtm_flow_nof_remote_cores_region_34=2 +dtm_flow_nof_remote_cores_region_35=2 +dtm_flow_nof_remote_cores_region_36=2 +dtm_flow_nof_remote_cores_region_37=2 +dtm_flow_nof_remote_cores_region_38=2 +dtm_flow_nof_remote_cores_region_39=2 +dtm_flow_nof_remote_cores_region_40=2 +dtm_flow_nof_remote_cores_region_41=2 +dtm_flow_nof_remote_cores_region_42=2 +dtm_flow_nof_remote_cores_region_43=2 +dtm_flow_nof_remote_cores_region_44=2 +dtm_flow_nof_remote_cores_region_45=2 +dtm_flow_nof_remote_cores_region_46=2 +dtm_flow_nof_remote_cores_region_47=2 +dtm_flow_nof_remote_cores_region_48=2 +dtm_flow_nof_remote_cores_region_49=2 +dtm_flow_nof_remote_cores_region_50=2 +dtm_flow_nof_remote_cores_region_51=2 +dtm_flow_nof_remote_cores_region_52=2 +dtm_flow_nof_remote_cores_region_53=2 +dtm_flow_nof_remote_cores_region_54=2 +dtm_flow_nof_remote_cores_region_55=2 +dtm_flow_nof_remote_cores_region_56=2 +dtm_flow_nof_remote_cores_region_57=2 +dtm_flow_nof_remote_cores_region_58=2 +dtm_flow_nof_remote_cores_region_59=2 +dtm_flow_nof_remote_cores_region_60=2 + +### MDB configuration ### +mdb_profile=balanced-exem + +### Descriptor-DMA configuration ### +dma_desc_aggregator_chain_length_max=1000 +dma_desc_aggregator_buff_size_kb=100 +dma_desc_aggregator_timeout_usec=1000 +dma_desc_aggregator_enable_specific_MDB_LPM=1 +dma_desc_aggregator_enable_specific_MDB_FEC=1 + +### Outlif configuarion ### +outlif_logical_to_physical_phase_map_1=S1 +outlif_logical_to_physical_phase_map_2=L1 +outlif_logical_to_physical_phase_map_3=XL +outlif_logical_to_physical_phase_map_4=L2 +outlif_logical_to_physical_phase_map_5=M1 +outlif_logical_to_physical_phase_map_6=M2 +outlif_logical_to_physical_phase_map_7=M3 +outlif_logical_to_physical_phase_map_8=S2 + +### Outlif data granularity configuration ### +outlif_physical_phase_data_granularity_S1=60 +outlif_physical_phase_data_granularity_S2=60 +outlif_physical_phase_data_granularity_M1=60 +outlif_physical_phase_data_granularity_M2=60 +outlif_physical_phase_data_granularity_M3=60 +outlif_physical_phase_data_granularity_L1=60 +outlif_physical_phase_data_granularity_L2=60 +outlif_physical_phase_data_granularity_XL=60 + +### Fabric configuration ### +# Enable link-training +port_init_cl72_sfi=1 +serdes_lane_config_cl72_auto_polarity_en=0 +serdes_lane_config_cl72_auto_polarity_en_sfi=1 +serdes_lane_config_cl72_restart_timeout_en=0 + +#SFI speed rate +port_init_speed_fabric=53125 + +## Fabric transmission mode +# Set the Connect mode to the Fabric +# Options: FE - presence of a Fabric device (single stage) +# SINGLE_FAP - stand-alone device +# MESH - devices in Mesh +# Note: If 'diag_chassis' is on, value will be override in dnx.soc +# to be FE instead of SINGLE_FAP. +fabric_connect_mode=FE + +fabric_logical_port_base=512 + +# Fabric lane mapping +lane_to_serdes_map_fabric_lane0=rx0:tx0 +lane_to_serdes_map_fabric_lane1=rx1:tx1 +lane_to_serdes_map_fabric_lane2=rx2:tx2 +lane_to_serdes_map_fabric_lane3=rx3:tx3 +lane_to_serdes_map_fabric_lane4=rx4:tx4 +lane_to_serdes_map_fabric_lane5=rx5:tx5 +lane_to_serdes_map_fabric_lane6=rx6:tx6 +lane_to_serdes_map_fabric_lane7=rx7:tx7 +lane_to_serdes_map_fabric_lane8=rx8:tx10 +lane_to_serdes_map_fabric_lane9=rx9:tx11 +lane_to_serdes_map_fabric_lane10=rx10:tx9 +lane_to_serdes_map_fabric_lane11=rx11:tx8 +lane_to_serdes_map_fabric_lane12=rx12:tx12 +lane_to_serdes_map_fabric_lane13=rx13:tx15 +lane_to_serdes_map_fabric_lane14=rx14:tx14 +lane_to_serdes_map_fabric_lane15=rx15:tx13 +lane_to_serdes_map_fabric_lane16=rx16:tx17 +lane_to_serdes_map_fabric_lane17=rx17:tx18 +lane_to_serdes_map_fabric_lane18=rx18:tx16 +lane_to_serdes_map_fabric_lane19=rx19:tx19 +lane_to_serdes_map_fabric_lane20=rx20:tx21 +lane_to_serdes_map_fabric_lane21=rx21:tx23 +lane_to_serdes_map_fabric_lane22=rx22:tx20 +lane_to_serdes_map_fabric_lane23=rx23:tx22 +lane_to_serdes_map_fabric_lane24=rx24:tx26 +lane_to_serdes_map_fabric_lane25=rx25:tx24 +lane_to_serdes_map_fabric_lane26=rx26:tx25 +lane_to_serdes_map_fabric_lane27=rx27:tx27 +lane_to_serdes_map_fabric_lane28=rx28:tx31 +lane_to_serdes_map_fabric_lane29=rx29:tx30 +lane_to_serdes_map_fabric_lane30=rx30:tx29 +lane_to_serdes_map_fabric_lane31=rx31:tx28 +lane_to_serdes_map_fabric_lane32=rx32:tx32 +lane_to_serdes_map_fabric_lane33=rx33:tx33 +lane_to_serdes_map_fabric_lane34=rx34:tx34 +lane_to_serdes_map_fabric_lane35=rx35:tx35 +lane_to_serdes_map_fabric_lane36=rx36:tx36 +lane_to_serdes_map_fabric_lane37=rx37:tx37 +lane_to_serdes_map_fabric_lane38=rx38:tx38 +lane_to_serdes_map_fabric_lane39=rx39:tx39 +lane_to_serdes_map_fabric_lane40=rx40:tx43 +lane_to_serdes_map_fabric_lane41=rx41:tx42 +lane_to_serdes_map_fabric_lane42=rx42:tx41 +lane_to_serdes_map_fabric_lane43=rx43:tx40 +lane_to_serdes_map_fabric_lane44=rx44:tx47 +lane_to_serdes_map_fabric_lane45=rx45:tx46 +lane_to_serdes_map_fabric_lane46=rx46:tx45 +lane_to_serdes_map_fabric_lane47=rx47:tx44 +lane_to_serdes_map_fabric_lane48=rx48:tx48 +lane_to_serdes_map_fabric_lane49=rx49:tx49 +lane_to_serdes_map_fabric_lane50=rx50:tx50 +lane_to_serdes_map_fabric_lane51=rx51:tx51 +lane_to_serdes_map_fabric_lane52=rx52:tx52 +lane_to_serdes_map_fabric_lane53=rx53:tx53 +lane_to_serdes_map_fabric_lane54=rx54:tx54 +lane_to_serdes_map_fabric_lane55=rx55:tx55 +lane_to_serdes_map_fabric_lane56=rx56:tx59 +lane_to_serdes_map_fabric_lane57=rx57:tx58 +lane_to_serdes_map_fabric_lane58=rx58:tx57 +lane_to_serdes_map_fabric_lane59=rx59:tx56 +lane_to_serdes_map_fabric_lane60=rx60:tx63 +lane_to_serdes_map_fabric_lane61=rx61:tx62 +lane_to_serdes_map_fabric_lane62=rx62:tx61 +lane_to_serdes_map_fabric_lane63=rx63:tx60 +lane_to_serdes_map_fabric_lane64=rx64:tx64 +lane_to_serdes_map_fabric_lane65=rx65:tx65 +lane_to_serdes_map_fabric_lane66=rx66:tx66 +lane_to_serdes_map_fabric_lane67=rx67:tx67 +lane_to_serdes_map_fabric_lane68=rx68:tx68 +lane_to_serdes_map_fabric_lane69=rx69:tx69 +lane_to_serdes_map_fabric_lane70=rx70:tx70 +lane_to_serdes_map_fabric_lane71=rx71:tx71 +lane_to_serdes_map_fabric_lane72=rx72:tx75 +lane_to_serdes_map_fabric_lane73=rx73:tx74 +lane_to_serdes_map_fabric_lane74=rx74:tx73 +lane_to_serdes_map_fabric_lane75=rx75:tx72 +lane_to_serdes_map_fabric_lane76=rx76:tx79 +lane_to_serdes_map_fabric_lane77=rx77:tx78 +lane_to_serdes_map_fabric_lane78=rx78:tx77 +lane_to_serdes_map_fabric_lane79=rx79:tx76 +lane_to_serdes_map_fabric_lane80=rx80:tx80 +lane_to_serdes_map_fabric_lane81=rx81:tx81 +lane_to_serdes_map_fabric_lane82=rx82:tx83 +lane_to_serdes_map_fabric_lane83=rx83:tx82 +lane_to_serdes_map_fabric_lane84=rx84:tx85 +lane_to_serdes_map_fabric_lane85=rx85:tx86 +lane_to_serdes_map_fabric_lane86=rx86:tx84 +lane_to_serdes_map_fabric_lane87=rx87:tx87 +lane_to_serdes_map_fabric_lane88=rx88:tx90 +lane_to_serdes_map_fabric_lane89=rx89:tx88 +lane_to_serdes_map_fabric_lane90=rx90:tx91 +lane_to_serdes_map_fabric_lane91=rx91:tx89 +lane_to_serdes_map_fabric_lane92=rx92:tx93 +lane_to_serdes_map_fabric_lane93=rx93:tx92 +lane_to_serdes_map_fabric_lane94=rx94:tx94 +lane_to_serdes_map_fabric_lane95=rx95:tx95 +lane_to_serdes_map_fabric_lane96=rx96:tx96 +lane_to_serdes_map_fabric_lane97=rx97:tx97 +lane_to_serdes_map_fabric_lane98=rx98:tx98 +lane_to_serdes_map_fabric_lane99=rx99:tx99 +lane_to_serdes_map_fabric_lane100=rx100:tx100 +lane_to_serdes_map_fabric_lane101=rx101:tx101 +lane_to_serdes_map_fabric_lane102=rx102:tx102 +lane_to_serdes_map_fabric_lane103=rx103:tx103 +lane_to_serdes_map_fabric_lane104=rx104:tx105 +lane_to_serdes_map_fabric_lane105=rx105:tx106 +lane_to_serdes_map_fabric_lane106=rx106:tx107 +lane_to_serdes_map_fabric_lane107=rx107:tx104 +lane_to_serdes_map_fabric_lane108=rx108:tx111 +lane_to_serdes_map_fabric_lane109=rx109:tx109 +lane_to_serdes_map_fabric_lane110=rx110:tx110 +lane_to_serdes_map_fabric_lane111=rx111:tx108 +lane_to_serdes_map_fabric_lane112=rx112:tx114 +lane_to_serdes_map_fabric_lane113=rx113:tx113 +lane_to_serdes_map_fabric_lane114=rx114:tx112 +lane_to_serdes_map_fabric_lane115=rx115:tx115 +lane_to_serdes_map_fabric_lane116=rx116:tx117 +lane_to_serdes_map_fabric_lane117=rx117:tx116 +lane_to_serdes_map_fabric_lane118=rx118:tx119 +lane_to_serdes_map_fabric_lane119=rx119:tx118 +lane_to_serdes_map_fabric_lane120=rx120:tx123 +lane_to_serdes_map_fabric_lane121=rx121:tx120 +lane_to_serdes_map_fabric_lane122=rx122:tx122 +lane_to_serdes_map_fabric_lane123=rx123:tx121 +lane_to_serdes_map_fabric_lane124=rx124:tx127 +lane_to_serdes_map_fabric_lane125=rx125:tx125 +lane_to_serdes_map_fabric_lane126=rx126:tx124 +lane_to_serdes_map_fabric_lane127=rx127:tx126 +lane_to_serdes_map_fabric_lane128=rx128:tx128 +lane_to_serdes_map_fabric_lane129=rx129:tx129 +lane_to_serdes_map_fabric_lane130=rx130:tx130 +lane_to_serdes_map_fabric_lane131=rx131:tx131 +lane_to_serdes_map_fabric_lane132=rx132:tx132 +lane_to_serdes_map_fabric_lane133=rx133:tx133 +lane_to_serdes_map_fabric_lane134=rx134:tx134 +lane_to_serdes_map_fabric_lane135=rx135:tx135 +lane_to_serdes_map_fabric_lane136=rx136:tx139 +lane_to_serdes_map_fabric_lane137=rx137:tx138 +lane_to_serdes_map_fabric_lane138=rx138:tx137 +lane_to_serdes_map_fabric_lane139=rx139:tx136 +lane_to_serdes_map_fabric_lane140=rx140:tx140 +lane_to_serdes_map_fabric_lane141=rx141:tx142 +lane_to_serdes_map_fabric_lane142=rx142:tx141 +lane_to_serdes_map_fabric_lane143=rx143:tx143 +lane_to_serdes_map_fabric_lane144=rx144:tx144 +lane_to_serdes_map_fabric_lane145=rx145:tx145 +lane_to_serdes_map_fabric_lane146=rx146:tx146 +lane_to_serdes_map_fabric_lane147=rx147:tx147 +lane_to_serdes_map_fabric_lane148=rx148:tx148 +lane_to_serdes_map_fabric_lane149=rx149:tx149 +lane_to_serdes_map_fabric_lane150=rx150:tx150 +lane_to_serdes_map_fabric_lane151=rx151:tx151 +lane_to_serdes_map_fabric_lane152=rx152:tx155 +lane_to_serdes_map_fabric_lane153=rx153:tx154 +lane_to_serdes_map_fabric_lane154=rx154:tx153 +lane_to_serdes_map_fabric_lane155=rx155:tx152 +lane_to_serdes_map_fabric_lane156=rx156:tx159 +lane_to_serdes_map_fabric_lane157=rx157:tx158 +lane_to_serdes_map_fabric_lane158=rx158:tx157 +lane_to_serdes_map_fabric_lane159=rx159:tx156 +lane_to_serdes_map_fabric_lane160=rx160:tx160 +lane_to_serdes_map_fabric_lane161=rx161:tx161 +lane_to_serdes_map_fabric_lane162=rx162:tx162 +lane_to_serdes_map_fabric_lane163=rx163:tx163 +lane_to_serdes_map_fabric_lane164=rx164:tx164 +lane_to_serdes_map_fabric_lane165=rx165:tx165 +lane_to_serdes_map_fabric_lane166=rx166:tx166 +lane_to_serdes_map_fabric_lane167=rx167:tx167 +lane_to_serdes_map_fabric_lane168=rx168:tx171 +lane_to_serdes_map_fabric_lane169=rx169:tx170 +lane_to_serdes_map_fabric_lane170=rx170:tx169 +lane_to_serdes_map_fabric_lane171=rx171:tx168 +lane_to_serdes_map_fabric_lane172=rx172:tx175 +lane_to_serdes_map_fabric_lane173=rx173:tx174 +lane_to_serdes_map_fabric_lane174=rx174:tx173 +lane_to_serdes_map_fabric_lane175=rx175:tx172 +lane_to_serdes_map_fabric_lane176=rx176:tx176 +lane_to_serdes_map_fabric_lane177=rx177:tx177 +lane_to_serdes_map_fabric_lane178=rx178:tx179 +lane_to_serdes_map_fabric_lane179=rx179:tx178 +lane_to_serdes_map_fabric_lane180=rx180:tx181 +lane_to_serdes_map_fabric_lane181=rx181:tx182 +lane_to_serdes_map_fabric_lane182=rx182:tx180 +lane_to_serdes_map_fabric_lane183=rx183:tx183 +lane_to_serdes_map_fabric_lane184=rx184:tx186 +lane_to_serdes_map_fabric_lane185=rx185:tx184 +lane_to_serdes_map_fabric_lane186=rx186:tx185 +lane_to_serdes_map_fabric_lane187=rx187:tx187 +lane_to_serdes_map_fabric_lane188=rx188:tx188 +lane_to_serdes_map_fabric_lane189=rx189:tx189 +lane_to_serdes_map_fabric_lane190=rx190:tx190 +lane_to_serdes_map_fabric_lane191=rx191:tx191 + +# +##Protocol trap look-up mode: +# Options: IN_LIF - Look-ups in the profile table are done by IN-LIF +# IN_PORT - Look-ups in the profile table are done by IN-PORT +protocol_traps_mode=IN_LIF + +# access definitions +schan_intr_enable=0 +tdma_intr_enable=0 +tslam_intr_enable=0 +miim_intr_enable=0 +schan_timeout_usec=300000 +tdma_timeout_usec=1000000 +tslam_timeout_usec=1000000 + +### Interrupts +appl_enable_intr_init=1 +polled_irq_mode=1 +# reduce CPU load, configure delay 100ms +polled_irq_delay=1000 + +# reduce the CPU load over adapter (caused by counter thread) +bcm_stat_interval=1000 + +# shadow memory +mem_cache_enable_ecc=1 +mem_cache_enable_parity=1 + +# serdes_nif/fabric_clk_freq_in/out configuration +serdes_nif_clk_freq_in=2 +serdes_nif_clk_freq_out=1 +serdes_fabric_clk_freq_in=2 +serdes_fabric_clk_freq_out=1 + +dport_map_direct=1 + +rif_id_max=0x6000 + +phy_rx_polarity_flip_phy0=0 +phy_rx_polarity_flip_phy1=0 +phy_rx_polarity_flip_phy2=0 +phy_rx_polarity_flip_phy3=0 +phy_rx_polarity_flip_phy4=0 +phy_rx_polarity_flip_phy5=0 +phy_rx_polarity_flip_phy6=0 +phy_rx_polarity_flip_phy7=0 +phy_rx_polarity_flip_phy8=1 +phy_rx_polarity_flip_phy9=1 +phy_rx_polarity_flip_phy10=0 +phy_rx_polarity_flip_phy11=0 +phy_rx_polarity_flip_phy12=1 +phy_rx_polarity_flip_phy13=1 +phy_rx_polarity_flip_phy14=0 +phy_rx_polarity_flip_phy15=1 +phy_rx_polarity_flip_phy16=0 +phy_rx_polarity_flip_phy17=0 +phy_rx_polarity_flip_phy18=0 +phy_rx_polarity_flip_phy19=0 +phy_rx_polarity_flip_phy20=0 +phy_rx_polarity_flip_phy21=0 +phy_rx_polarity_flip_phy22=0 +phy_rx_polarity_flip_phy23=0 +phy_rx_polarity_flip_phy24=0 +phy_rx_polarity_flip_phy25=0 +phy_rx_polarity_flip_phy26=0 +phy_rx_polarity_flip_phy27=0 +phy_rx_polarity_flip_phy28=0 +phy_rx_polarity_flip_phy29=0 +phy_rx_polarity_flip_phy30=0 +phy_rx_polarity_flip_phy31=0 +phy_rx_polarity_flip_phy32=0 +phy_rx_polarity_flip_phy33=0 +phy_rx_polarity_flip_phy34=0 +phy_rx_polarity_flip_phy35=0 +phy_rx_polarity_flip_phy36=0 +phy_rx_polarity_flip_phy37=0 +phy_rx_polarity_flip_phy38=0 +phy_rx_polarity_flip_phy39=0 +phy_rx_polarity_flip_phy40=0 +phy_rx_polarity_flip_phy41=0 +phy_rx_polarity_flip_phy42=0 +phy_rx_polarity_flip_phy43=0 +phy_rx_polarity_flip_phy44=0 +phy_rx_polarity_flip_phy45=0 +phy_rx_polarity_flip_phy46=0 +phy_rx_polarity_flip_phy47=0 +phy_rx_polarity_flip_phy48=0 +phy_rx_polarity_flip_phy49=0 +phy_rx_polarity_flip_phy50=0 +phy_rx_polarity_flip_phy51=0 +phy_rx_polarity_flip_phy52=0 +phy_rx_polarity_flip_phy53=0 +phy_rx_polarity_flip_phy54=0 +phy_rx_polarity_flip_phy55=0 +phy_rx_polarity_flip_phy56=0 +phy_rx_polarity_flip_phy57=0 +phy_rx_polarity_flip_phy58=0 +phy_rx_polarity_flip_phy59=0 +phy_rx_polarity_flip_phy60=0 +phy_rx_polarity_flip_phy61=0 +phy_rx_polarity_flip_phy62=0 +phy_rx_polarity_flip_phy63=0 +phy_rx_polarity_flip_phy64=0 +phy_rx_polarity_flip_phy65=0 +phy_rx_polarity_flip_phy66=0 +phy_rx_polarity_flip_phy67=0 +phy_rx_polarity_flip_phy68=0 +phy_rx_polarity_flip_phy69=0 +phy_rx_polarity_flip_phy70=0 +phy_rx_polarity_flip_phy71=0 +phy_rx_polarity_flip_phy72=1 +phy_rx_polarity_flip_phy73=1 +phy_rx_polarity_flip_phy74=0 +phy_rx_polarity_flip_phy75=1 +phy_rx_polarity_flip_phy76=1 +phy_rx_polarity_flip_phy77=1 +phy_rx_polarity_flip_phy78=1 +phy_rx_polarity_flip_phy79=1 +phy_rx_polarity_flip_phy80=0 +phy_rx_polarity_flip_phy81=0 +phy_rx_polarity_flip_phy82=0 +phy_rx_polarity_flip_phy83=0 +phy_rx_polarity_flip_phy84=0 +phy_rx_polarity_flip_phy85=0 +phy_rx_polarity_flip_phy86=0 +phy_rx_polarity_flip_phy87=0 +phy_rx_polarity_flip_phy88=0 +phy_rx_polarity_flip_phy89=0 +phy_rx_polarity_flip_phy90=0 +phy_rx_polarity_flip_phy91=0 +phy_rx_polarity_flip_phy92=0 +phy_rx_polarity_flip_phy93=0 +phy_rx_polarity_flip_phy94=0 +phy_rx_polarity_flip_phy95=0 +phy_rx_polarity_flip_phy96=0 +phy_rx_polarity_flip_phy97=0 +phy_rx_polarity_flip_phy98=0 +phy_rx_polarity_flip_phy99=0 +phy_rx_polarity_flip_phy100=0 +phy_rx_polarity_flip_phy101=0 +phy_rx_polarity_flip_phy102=0 +phy_rx_polarity_flip_phy103=0 +phy_rx_polarity_flip_phy104=0 +phy_rx_polarity_flip_phy105=0 +phy_rx_polarity_flip_phy106=0 +phy_rx_polarity_flip_phy107=0 +phy_rx_polarity_flip_phy108=0 +phy_rx_polarity_flip_phy109=0 +phy_rx_polarity_flip_phy110=0 +phy_rx_polarity_flip_phy111=0 +phy_rx_polarity_flip_phy112=0 +phy_rx_polarity_flip_phy113=0 +phy_rx_polarity_flip_phy114=0 +phy_rx_polarity_flip_phy115=0 +phy_rx_polarity_flip_phy116=0 +phy_rx_polarity_flip_phy117=0 +phy_rx_polarity_flip_phy118=0 +phy_rx_polarity_flip_phy119=0 +phy_rx_polarity_flip_phy120=0 +phy_rx_polarity_flip_phy121=0 +phy_rx_polarity_flip_phy122=0 +phy_rx_polarity_flip_phy123=0 +phy_rx_polarity_flip_phy124=0 +phy_rx_polarity_flip_phy125=0 +phy_rx_polarity_flip_phy126=0 +phy_rx_polarity_flip_phy127=0 +phy_rx_polarity_flip_phy128=0 +phy_rx_polarity_flip_phy129=0 +phy_rx_polarity_flip_phy130=0 +phy_rx_polarity_flip_phy131=0 +phy_rx_polarity_flip_phy132=0 +phy_rx_polarity_flip_phy133=0 +phy_rx_polarity_flip_phy134=0 +phy_rx_polarity_flip_phy135=0 +phy_rx_polarity_flip_phy136=0 +phy_rx_polarity_flip_phy137=0 +phy_rx_polarity_flip_phy138=0 +phy_rx_polarity_flip_phy139=0 +phy_rx_polarity_flip_phy140=0 +phy_rx_polarity_flip_phy141=0 +phy_rx_polarity_flip_phy142=0 +phy_rx_polarity_flip_phy143=0 +phy_tx_polarity_flip_phy0=1 +phy_tx_polarity_flip_phy1=1 +phy_tx_polarity_flip_phy2=1 +phy_tx_polarity_flip_phy3=1 +phy_tx_polarity_flip_phy4=1 +phy_tx_polarity_flip_phy5=1 +phy_tx_polarity_flip_phy6=1 +phy_tx_polarity_flip_phy7=1 +phy_tx_polarity_flip_phy8=1 +phy_tx_polarity_flip_phy9=1 +phy_tx_polarity_flip_phy10=1 +phy_tx_polarity_flip_phy11=1 +phy_tx_polarity_flip_phy12=1 +phy_tx_polarity_flip_phy13=1 +phy_tx_polarity_flip_phy14=1 +phy_tx_polarity_flip_phy15=1 +phy_tx_polarity_flip_phy16=1 +phy_tx_polarity_flip_phy17=1 +phy_tx_polarity_flip_phy18=1 +phy_tx_polarity_flip_phy19=1 +phy_tx_polarity_flip_phy20=1 +phy_tx_polarity_flip_phy21=1 +phy_tx_polarity_flip_phy22=1 +phy_tx_polarity_flip_phy23=1 +phy_tx_polarity_flip_phy24=1 +phy_tx_polarity_flip_phy25=1 +phy_tx_polarity_flip_phy26=1 +phy_tx_polarity_flip_phy27=1 +phy_tx_polarity_flip_phy28=1 +phy_tx_polarity_flip_phy29=1 +phy_tx_polarity_flip_phy30=1 +phy_tx_polarity_flip_phy31=1 +phy_tx_polarity_flip_phy32=1 +phy_tx_polarity_flip_phy33=1 +phy_tx_polarity_flip_phy34=1 +phy_tx_polarity_flip_phy35=1 +phy_tx_polarity_flip_phy36=1 +phy_tx_polarity_flip_phy37=1 +phy_tx_polarity_flip_phy38=1 +phy_tx_polarity_flip_phy39=1 +phy_tx_polarity_flip_phy40=1 +phy_tx_polarity_flip_phy41=1 +phy_tx_polarity_flip_phy42=1 +phy_tx_polarity_flip_phy43=1 +phy_tx_polarity_flip_phy44=1 +phy_tx_polarity_flip_phy45=1 +phy_tx_polarity_flip_phy46=1 +phy_tx_polarity_flip_phy47=1 +phy_tx_polarity_flip_phy48=1 +phy_tx_polarity_flip_phy49=1 +phy_tx_polarity_flip_phy50=1 +phy_tx_polarity_flip_phy51=1 +phy_tx_polarity_flip_phy52=1 +phy_tx_polarity_flip_phy53=1 +phy_tx_polarity_flip_phy54=1 +phy_tx_polarity_flip_phy55=1 +phy_tx_polarity_flip_phy56=1 +phy_tx_polarity_flip_phy57=1 +phy_tx_polarity_flip_phy58=1 +phy_tx_polarity_flip_phy59=1 +phy_tx_polarity_flip_phy60=1 +phy_tx_polarity_flip_phy61=1 +phy_tx_polarity_flip_phy62=1 +phy_tx_polarity_flip_phy63=1 +phy_tx_polarity_flip_phy64=1 +phy_tx_polarity_flip_phy65=1 +phy_tx_polarity_flip_phy66=1 +phy_tx_polarity_flip_phy67=1 +phy_tx_polarity_flip_phy68=1 +phy_tx_polarity_flip_phy69=1 +phy_tx_polarity_flip_phy70=1 +phy_tx_polarity_flip_phy71=1 +phy_tx_polarity_flip_phy72=0 +phy_tx_polarity_flip_phy73=0 +phy_tx_polarity_flip_phy74=0 +phy_tx_polarity_flip_phy75=0 +phy_tx_polarity_flip_phy76=0 +phy_tx_polarity_flip_phy77=0 +phy_tx_polarity_flip_phy78=0 +phy_tx_polarity_flip_phy79=0 +phy_tx_polarity_flip_phy80=0 +phy_tx_polarity_flip_phy81=0 +phy_tx_polarity_flip_phy82=0 +phy_tx_polarity_flip_phy83=0 +phy_tx_polarity_flip_phy84=0 +phy_tx_polarity_flip_phy85=0 +phy_tx_polarity_flip_phy86=0 +phy_tx_polarity_flip_phy87=0 +phy_tx_polarity_flip_phy88=1 +phy_tx_polarity_flip_phy89=1 +phy_tx_polarity_flip_phy90=1 +phy_tx_polarity_flip_phy91=1 +phy_tx_polarity_flip_phy92=1 +phy_tx_polarity_flip_phy93=1 +phy_tx_polarity_flip_phy94=1 +phy_tx_polarity_flip_phy95=1 +phy_tx_polarity_flip_phy96=1 +phy_tx_polarity_flip_phy97=1 +phy_tx_polarity_flip_phy98=1 +phy_tx_polarity_flip_phy99=1 +phy_tx_polarity_flip_phy100=1 +phy_tx_polarity_flip_phy101=1 +phy_tx_polarity_flip_phy102=1 +phy_tx_polarity_flip_phy103=1 +phy_tx_polarity_flip_phy104=1 +phy_tx_polarity_flip_phy105=1 +phy_tx_polarity_flip_phy106=1 +phy_tx_polarity_flip_phy107=1 +phy_tx_polarity_flip_phy108=1 +phy_tx_polarity_flip_phy109=1 +phy_tx_polarity_flip_phy110=1 +phy_tx_polarity_flip_phy111=1 +phy_tx_polarity_flip_phy112=1 +phy_tx_polarity_flip_phy113=1 +phy_tx_polarity_flip_phy114=1 +phy_tx_polarity_flip_phy115=1 +phy_tx_polarity_flip_phy116=1 +phy_tx_polarity_flip_phy117=1 +phy_tx_polarity_flip_phy118=1 +phy_tx_polarity_flip_phy119=1 +phy_tx_polarity_flip_phy120=1 +phy_tx_polarity_flip_phy121=1 +phy_tx_polarity_flip_phy122=1 +phy_tx_polarity_flip_phy123=1 +phy_tx_polarity_flip_phy124=1 +phy_tx_polarity_flip_phy125=1 +phy_tx_polarity_flip_phy126=1 +phy_tx_polarity_flip_phy127=1 +phy_tx_polarity_flip_phy128=1 +phy_tx_polarity_flip_phy129=1 +phy_tx_polarity_flip_phy130=1 +phy_tx_polarity_flip_phy131=1 +phy_tx_polarity_flip_phy132=1 +phy_tx_polarity_flip_phy133=1 +phy_tx_polarity_flip_phy134=1 +phy_tx_polarity_flip_phy135=1 +phy_tx_polarity_flip_phy136=1 +phy_tx_polarity_flip_phy137=1 +phy_tx_polarity_flip_phy138=1 +phy_tx_polarity_flip_phy139=1 +phy_tx_polarity_flip_phy140=1 +phy_tx_polarity_flip_phy141=1 +phy_tx_polarity_flip_phy142=1 +phy_tx_polarity_flip_phy143=1 + +serdes_tx_taps_1=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_2=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_3=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_4=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_5=nrz:-5:80:-23:0:0:0 +serdes_tx_taps_6=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_7=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_8=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_9=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_10=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_11=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_12=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_13=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_14=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_15=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_16=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_17=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_18=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_19=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_20=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_21=nrz:-4:75:-21:0:0:0 +serdes_tx_taps_22=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_23=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_24=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_25=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_26=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_27=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_28=nrz:-5:80:-23:0:0:0 +serdes_tx_taps_29=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_30=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_31=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_32=nrz:-5:80:-23:0:0:0 +serdes_tx_taps_33=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_34=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_35=nrz:-5:80:-23:0:0:0 +serdes_tx_taps_36=nrz:-7:85:-25:0:0:0 + +xflow_macsec_secure_chan_to_num_secure_assoc_encrypt=2 +xflow_macsec_secure_chan_to_num_secure_assoc_decrypt=2 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/1/port_config.ini b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/1/port_config.ini new file mode 100644 index 000000000000..f77f5b35172c --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/1/port_config.ini @@ -0,0 +1,21 @@ +# name lanes alias index role speed asic_port_name coreId corePortId numVoq +Ethernet144 72,73,74,75 Ethernet19/1 21 Ext 100000 Eth0-ASIC1 1 1 8 +Ethernet152 80,81,82,83 Ethernet20/1 22 Ext 100000 Eth8-ASIC1 1 2 8 +Ethernet160 88,89,90,91 Ethernet21/1 23 Ext 100000 Eth16-ASIC1 1 3 8 +Ethernet168 96,97,98,99 Ethernet22/1 24 Ext 100000 Eth24-ASIC1 1 4 8 +Ethernet176 104,105,106,107 Ethernet23/1 25 Ext 100000 Eth32-ASIC1 1 5 8 +Ethernet184 112,113,114,115 Ethernet24/1 26 Ext 100000 Eth40-ASIC1 1 6 8 +Ethernet192 120,121,122,123 Ethernet25/1 27 Ext 100000 Eth48-ASIC1 1 7 8 +Ethernet200 128,129,130,131 Ethernet26/1 28 Ext 100000 Eth56-ASIC1 1 8 8 +Ethernet208 136,137,138,139 Ethernet27/1 29 Ext 100000 Eth64-ASIC1 1 9 8 +Ethernet216 64,65,66,67 Ethernet28/1 30 Ext 100000 Eth72-ASIC1 0 10 8 +Ethernet224 56,57,58,59 Ethernet29/1 31 Ext 100000 Eth80-ASIC1 0 11 8 +Ethernet232 48,49,50,51 Ethernet30/1 32 Ext 100000 Eth88-ASIC1 0 12 8 +Ethernet240 40,41,42,43 Ethernet31/1 33 Ext 100000 Eth96-ASIC1 0 13 8 +Ethernet248 32,33,34,35 Ethernet32/1 34 Ext 100000 Eth104-ASIC1 0 14 8 +Ethernet256 24,25,26,27 Ethernet33/1 35 Ext 100000 Eth112-ASIC1 0 15 8 +Ethernet264 16,17,18,19 Ethernet34/1 36 Ext 100000 Eth120-ASIC1 0 16 8 +Ethernet272 8,9,10,11 Ethernet35/1 37 Ext 100000 Eth128-ASIC1 0 17 8 +Ethernet280 0,1,2,3 Ethernet36/1 38 Ext 100000 Eth136-ASIC1 0 18 8 +Ethernet-Rec1 221 Recirc0/0 39 Rec 400000 Rcy0-ASIC1 0 221 8 +Ethernet-IB1 222 Recirc0/1 40 Inb 400000 Rcy1-ASIC1 1 222 8 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/1/sai.profile b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/1/sai.profile new file mode 120000 index 000000000000..1e172f3e0765 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/1/sai.profile @@ -0,0 +1 @@ +../0/sai.profile \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36DM2-C36 b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36DM2-C36 new file mode 120000 index 000000000000..41ebc98e1c4e --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36DM2-C36 @@ -0,0 +1 @@ +Arista-7800R3A-36D2-C36 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36P-C36 b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36P-C36 new file mode 120000 index 000000000000..41ebc98e1c4e --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36P-C36 @@ -0,0 +1 @@ +Arista-7800R3A-36D2-C36 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36D2-C36 b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36D2-C36 new file mode 120000 index 000000000000..41ebc98e1c4e --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36D2-C36 @@ -0,0 +1 @@ +Arista-7800R3A-36D2-C36 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36DM2-C36 b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36DM2-C36 new file mode 120000 index 000000000000..41ebc98e1c4e --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36DM2-C36 @@ -0,0 +1 @@ +Arista-7800R3A-36D2-C36 \ No newline at end of file From 08da4efe34e53991c21d346bba360cd9bb45d354 Mon Sep 17 00:00:00 2001 From: Bohan Yang <105526392+abohanyang@users.noreply.github.com> Date: Thu, 13 Oct 2022 20:36:44 -0700 Subject: [PATCH 07/35] Add 36 port 400g SKU for x86_64-arista_7800r3a_36d series of Linecards. (#11872) Add 36 port 400g SKU for x86_64-arista_7800r3a_36d series of Linecards. --- .../Arista-7800R3A-36D-D36 | 1 + .../Arista-7800R3A-36D2-D36/0/buffers.json.j2 | 2 + .../0/buffers_defaults_t2.j2 | 37 + .../0/context_config.json | 25 + .../0/j2p-a7800r3a-36d-36x400G.config.bcm | 1022 +++++++++++++++++ .../0/pg_profile_lookup.ini | 17 + .../Arista-7800R3A-36D2-D36/0/port_config.ini | 21 + .../Arista-7800R3A-36D2-D36/0/qos.json.j2 | 1 + .../Arista-7800R3A-36D2-D36/0/sai.profile | 2 + .../Arista-7800R3A-36D2-D36/1/buffers.json.j2 | 2 + .../1/buffers_defaults_t2.j2 | 37 + .../1/context_config.json | 1 + .../1/j2p-a7800r3a-36d-36x400G.config.bcm | 1022 +++++++++++++++++ .../1/pg_profile_lookup.ini | 17 + .../Arista-7800R3A-36D2-D36/1/port_config.ini | 21 + .../Arista-7800R3A-36D2-D36/1/qos.json.j2 | 1 + .../Arista-7800R3A-36D2-D36/1/sai.profile | 1 + .../Arista-7800R3A-36DM2-D36 | 1 + .../Arista-7800R3A-36P-P36 | 1 + .../Arista-7800R3AK-36D2-D36 | 1 + .../Arista-7800R3AK-36DM2-D36 | 1 + 21 files changed, 2234 insertions(+) create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D-D36 create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/buffers.json.j2 create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/buffers_defaults_t2.j2 create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/context_config.json create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/j2p-a7800r3a-36d-36x400G.config.bcm create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/pg_profile_lookup.ini create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/port_config.ini create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/qos.json.j2 create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/sai.profile create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/buffers.json.j2 create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/buffers_defaults_t2.j2 create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/context_config.json create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/j2p-a7800r3a-36d-36x400G.config.bcm create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/pg_profile_lookup.ini create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/port_config.ini create mode 100644 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/qos.json.j2 create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/sai.profile create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36DM2-D36 create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36P-P36 create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36D2-D36 create mode 120000 device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36DM2-D36 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D-D36 b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D-D36 new file mode 120000 index 000000000000..e029ef37b78a --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D-D36 @@ -0,0 +1 @@ +Arista-7800R3A-36D2-D36 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/buffers.json.j2 b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/buffers.json.j2 new file mode 100644 index 000000000000..f34a844f4a87 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/buffers.json.j2 @@ -0,0 +1,2 @@ +{%- set default_topo = 't2' %} +{%- include 'buffers_config.j2' %} diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/buffers_defaults_t2.j2 b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/buffers_defaults_t2.j2 new file mode 100644 index 000000000000..e7af0aff4934 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/buffers_defaults_t2.j2 @@ -0,0 +1,37 @@ +{%- set default_cable = '300m' %} + +{%- macro generate_port_lists(PORT_ALL) %} + {# Generate list of ports #} + {%- for port_idx in range(0,144,8) %} + {%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %} + {%- endfor %} +{%- endmacro %} + +{%- macro generate_buffer_pool_and_profiles() %} + "BUFFER_POOL": { + "ingress_lossless_pool": { + "size": "6441610000", + "type": "both", + "mode": "dynamic", + "xoff": "11354112" + } + }, + "BUFFER_PROFILE": { + "ingress_lossy_profile": { + "pool":"ingress_lossless_pool", + "size":"1280", + "xon_offset": "2560", + "dynamic_th":"0" + }, + "egress_lossless_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "static_th":"33030144" + }, + "egress_lossy_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "dynamic_th":"-1" + } + }, +{%- endmacro %} diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/context_config.json b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/context_config.json new file mode 100644 index 000000000000..2c126e71899e --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/context_config.json @@ -0,0 +1,25 @@ +{ + "CONTEXTS": [ + { + "guid" : 0, + "name" : "syncd", + "dbAsic" : "ASIC_DB", + "dbCounters" : "COUNTERS_DB", + "dbFlex": "FLEX_COUNTER_DB", + "dbState" : "STATE_DB", + "zmq_enable": false, + "zmq_endpoint": "tcp://127.0.0.1:5555", + "zmq_ntf_endpoint": "tcp://127.0.0.1:5556", + "switches": [ + { + "index" : 0, + "hwinfo" : "06:00.0" + }, + { + "index" : 1, + "hwinfo" : "07:00.0" + } + ] + } + ] +} diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/j2p-a7800r3a-36d-36x400G.config.bcm b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/j2p-a7800r3a-36d-36x400G.config.bcm new file mode 100644 index 000000000000..62fe61d49c9c --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/j2p-a7800r3a-36d-36x400G.config.bcm @@ -0,0 +1,1022 @@ +soc_family=BCM8885X +system_ref_core_clock_khz=1600000 + +dpp_db_path=/usr/share/bcm/db + +#################################################### +##Reference applications related properties - Start +#################################################### + +## PMF small EXEM connected stage: +# Options: IPMF2 - Ingress PMF 2 stage can perform small EXEM lookups. +# IPMF3 - Ingress PMF 3 stage can perform small EXEM lookups. +## PMF small EXEM connected stage: +# Options: IPMF2 - Ingress PMF 2 stage can perform small EXEM lookups. +# IPMF3 - Ingress PMF 3 stage can perform small EXEM lookups. +pmf_sexem3_stage=IPMF2 + +#################################################### +##Reference applications related properties - End +#################################################### + +# Jericho2-mode (description 0x1 used for Jericho 2 mode) +system_headers_mode=1 + +# HW mode to support 1024 16-member system wide LAGs +trunk_group_max_members=16 + +# Disable link-training +port_init_cl72=0 + +###Default interfaces for Jericho2Plus +#CPU interfaces +ucode_port_0=CPU.0:core_0.0 +ucode_port_200=CPU.8:core_1.200 +ucode_port_201=CPU.16:core_0.201 +ucode_port_202=CPU.24:core_1.202 +ucode_port_203=CPU.32:core_0.203 + +#NIF ETH interfaces on device +ucode_port_1=CDGE9:core_1.1 +ucode_port_2=CDGE10:core_1.2 +ucode_port_3=CDGE11:core_1.3 +ucode_port_4=CDGE12:core_1.4 +ucode_port_5=CDGE13:core_1.5 +ucode_port_6=CDGE14:core_1.6 +ucode_port_7=CDGE15:core_1.7 +ucode_port_8=CDGE16:core_1.8 +ucode_port_9=CDGE17:core_1.9 + +ucode_port_10=CDGE8:core_0.10 +ucode_port_11=CDGE7:core_0.11 +ucode_port_12=CDGE6:core_0.12 +ucode_port_13=CDGE5:core_0.13 +ucode_port_14=CDGE4:core_0.14 +ucode_port_15=CDGE3:core_0.15 +ucode_port_16=CDGE2:core_0.16 +ucode_port_17=CDGE1:core_0.17 +ucode_port_18=CDGE0:core_0.18 + +#NIF default speeds +port_init_speed_xe=10000 +port_init_speed_xl=40000 +port_init_speed_le=50000 +port_init_speed_ce=100000 +port_init_speed_cc=200000 +port_init_speed_cd=400000 +port_init_speed_il=10312 + +port_priorities=8 + +#special ports +ucode_port_240=OLP:core_0.240 + +# NIF lane mapping +lane_to_serdes_map_nif_lane0=rx3:tx4 +lane_to_serdes_map_nif_lane1=rx6:tx1 +lane_to_serdes_map_nif_lane2=rx7:tx5 +lane_to_serdes_map_nif_lane3=rx4:tx7 +lane_to_serdes_map_nif_lane4=rx1:tx2 +lane_to_serdes_map_nif_lane5=rx0:tx0 +lane_to_serdes_map_nif_lane6=rx5:tx3 +lane_to_serdes_map_nif_lane7=rx2:tx6 +lane_to_serdes_map_nif_lane8=rx10:tx11 +lane_to_serdes_map_nif_lane9=rx8:tx8 +lane_to_serdes_map_nif_lane10=rx14:tx12 +lane_to_serdes_map_nif_lane11=rx15:tx15 +lane_to_serdes_map_nif_lane12=rx13:tx10 +lane_to_serdes_map_nif_lane13=rx9:tx9 +lane_to_serdes_map_nif_lane14=rx11:tx13 +lane_to_serdes_map_nif_lane15=rx12:tx14 +lane_to_serdes_map_nif_lane16=rx16:tx17 +lane_to_serdes_map_nif_lane17=rx19:tx21 +lane_to_serdes_map_nif_lane18=rx21:tx18 +lane_to_serdes_map_nif_lane19=rx18:tx16 +lane_to_serdes_map_nif_lane20=rx17:tx23 +lane_to_serdes_map_nif_lane21=rx20:tx22 +lane_to_serdes_map_nif_lane22=rx22:tx20 +lane_to_serdes_map_nif_lane23=rx23:tx19 +lane_to_serdes_map_nif_lane24=rx26:tx28 +lane_to_serdes_map_nif_lane25=rx29:tx31 +lane_to_serdes_map_nif_lane26=rx31:tx29 +lane_to_serdes_map_nif_lane27=rx28:tx27 +lane_to_serdes_map_nif_lane28=rx25:tx25 +lane_to_serdes_map_nif_lane29=rx24:tx30 +lane_to_serdes_map_nif_lane30=rx30:tx24 +lane_to_serdes_map_nif_lane31=rx27:tx26 +lane_to_serdes_map_nif_lane32=rx32:tx39 +lane_to_serdes_map_nif_lane33=rx33:tx38 +lane_to_serdes_map_nif_lane34=rx38:tx32 +lane_to_serdes_map_nif_lane35=rx39:tx33 +lane_to_serdes_map_nif_lane36=rx35:tx37 +lane_to_serdes_map_nif_lane37=rx34:tx36 +lane_to_serdes_map_nif_lane38=rx36:tx34 +lane_to_serdes_map_nif_lane39=rx37:tx35 +lane_to_serdes_map_nif_lane40=rx40:tx41 +lane_to_serdes_map_nif_lane41=rx43:tx45 +lane_to_serdes_map_nif_lane42=rx45:tx42 +lane_to_serdes_map_nif_lane43=rx42:tx40 +lane_to_serdes_map_nif_lane44=rx41:tx47 +lane_to_serdes_map_nif_lane45=rx44:tx46 +lane_to_serdes_map_nif_lane46=rx46:tx44 +lane_to_serdes_map_nif_lane47=rx47:tx43 +lane_to_serdes_map_nif_lane48=rx50:tx52 +lane_to_serdes_map_nif_lane49=rx53:tx55 +lane_to_serdes_map_nif_lane50=rx55:tx53 +lane_to_serdes_map_nif_lane51=rx52:tx51 +lane_to_serdes_map_nif_lane52=rx49:tx49 +lane_to_serdes_map_nif_lane53=rx48:tx54 +lane_to_serdes_map_nif_lane54=rx54:tx48 +lane_to_serdes_map_nif_lane55=rx51:tx50 +lane_to_serdes_map_nif_lane56=rx56:tx63 +lane_to_serdes_map_nif_lane57=rx57:tx62 +lane_to_serdes_map_nif_lane58=rx62:tx56 +lane_to_serdes_map_nif_lane59=rx63:tx57 +lane_to_serdes_map_nif_lane60=rx59:tx61 +lane_to_serdes_map_nif_lane61=rx58:tx60 +lane_to_serdes_map_nif_lane62=rx60:tx58 +lane_to_serdes_map_nif_lane63=rx61:tx59 +lane_to_serdes_map_nif_lane64=rx64:tx65 +lane_to_serdes_map_nif_lane65=rx67:tx69 +lane_to_serdes_map_nif_lane66=rx69:tx66 +lane_to_serdes_map_nif_lane67=rx66:tx64 +lane_to_serdes_map_nif_lane68=rx65:tx71 +lane_to_serdes_map_nif_lane69=rx68:tx70 +lane_to_serdes_map_nif_lane70=rx70:tx68 +lane_to_serdes_map_nif_lane71=rx71:tx67 +lane_to_serdes_map_nif_lane72=rx79:tx74 +lane_to_serdes_map_nif_lane73=rx76:tx75 +lane_to_serdes_map_nif_lane74=rx72:tx76 +lane_to_serdes_map_nif_lane75=rx74:tx73 +lane_to_serdes_map_nif_lane76=rx77:tx79 +lane_to_serdes_map_nif_lane77=rx78:tx78 +lane_to_serdes_map_nif_lane78=rx73:tx77 +lane_to_serdes_map_nif_lane79=rx75:tx72 +lane_to_serdes_map_nif_lane80=rx86:tx86 +lane_to_serdes_map_nif_lane81=rx83:tx87 +lane_to_serdes_map_nif_lane82=rx82:tx81 +lane_to_serdes_map_nif_lane83=rx85:tx80 +lane_to_serdes_map_nif_lane84=rx87:tx85 +lane_to_serdes_map_nif_lane85=rx84:tx84 +lane_to_serdes_map_nif_lane86=rx80:tx82 +lane_to_serdes_map_nif_lane87=rx81:tx83 +lane_to_serdes_map_nif_lane88=rx95:tx90 +lane_to_serdes_map_nif_lane89=rx92:tx88 +lane_to_serdes_map_nif_lane90=rx88:tx92 +lane_to_serdes_map_nif_lane91=rx91:tx95 +lane_to_serdes_map_nif_lane92=rx94:tx89 +lane_to_serdes_map_nif_lane93=rx93:tx91 +lane_to_serdes_map_nif_lane94=rx89:tx93 +lane_to_serdes_map_nif_lane95=rx90:tx94 +lane_to_serdes_map_nif_lane96=rx103:tx97 +lane_to_serdes_map_nif_lane97=rx100:tx96 +lane_to_serdes_map_nif_lane98=rx96:tx100 +lane_to_serdes_map_nif_lane99=rx99:tx103 +lane_to_serdes_map_nif_lane100=rx102:tx99 +lane_to_serdes_map_nif_lane101=rx101:tx98 +lane_to_serdes_map_nif_lane102=rx97:tx101 +lane_to_serdes_map_nif_lane103=rx98:tx102 +lane_to_serdes_map_nif_lane104=rx110:tx107 +lane_to_serdes_map_nif_lane105=rx108:tx105 +lane_to_serdes_map_nif_lane106=rx104:tx108 +lane_to_serdes_map_nif_lane107=rx107:tx110 +lane_to_serdes_map_nif_lane108=rx111:tx106 +lane_to_serdes_map_nif_lane109=rx109:tx104 +lane_to_serdes_map_nif_lane110=rx105:tx109 +lane_to_serdes_map_nif_lane111=rx106:tx111 +lane_to_serdes_map_nif_lane112=rx119:tx114 +lane_to_serdes_map_nif_lane113=rx116:tx112 +lane_to_serdes_map_nif_lane114=rx112:tx116 +lane_to_serdes_map_nif_lane115=rx115:tx119 +lane_to_serdes_map_nif_lane116=rx118:tx113 +lane_to_serdes_map_nif_lane117=rx117:tx115 +lane_to_serdes_map_nif_lane118=rx113:tx117 +lane_to_serdes_map_nif_lane119=rx114:tx118 +lane_to_serdes_map_nif_lane120=rx127:tx121 +lane_to_serdes_map_nif_lane121=rx124:tx120 +lane_to_serdes_map_nif_lane122=rx120:tx124 +lane_to_serdes_map_nif_lane123=rx123:tx127 +lane_to_serdes_map_nif_lane124=rx126:tx123 +lane_to_serdes_map_nif_lane125=rx125:tx122 +lane_to_serdes_map_nif_lane126=rx121:tx125 +lane_to_serdes_map_nif_lane127=rx122:tx126 +lane_to_serdes_map_nif_lane128=rx134:tx131 +lane_to_serdes_map_nif_lane129=rx132:tx129 +lane_to_serdes_map_nif_lane130=rx128:tx132 +lane_to_serdes_map_nif_lane131=rx131:tx134 +lane_to_serdes_map_nif_lane132=rx135:tx130 +lane_to_serdes_map_nif_lane133=rx133:tx128 +lane_to_serdes_map_nif_lane134=rx129:tx133 +lane_to_serdes_map_nif_lane135=rx130:tx135 +lane_to_serdes_map_nif_lane136=rx143:tx138 +lane_to_serdes_map_nif_lane137=rx140:tx136 +lane_to_serdes_map_nif_lane138=rx136:tx140 +lane_to_serdes_map_nif_lane139=rx139:tx143 +lane_to_serdes_map_nif_lane140=rx142:tx137 +lane_to_serdes_map_nif_lane141=rx141:tx139 +lane_to_serdes_map_nif_lane142=rx137:tx141 +lane_to_serdes_map_nif_lane143=rx138:tx142 + +######################### +### High Availability ### +######################### + +sw_state_max_size=750000000 + +#location of warmboot NV memory +#Allowed options for dnx are - 3:external storage in filesystem 4:driver will save the state directly in shared memory +stable_location=4 + +# Note that each unit should have a unique filename and that adapter does not play well with tmp and dev/shm folders. +stable_filename=/dev/shm/warmboot_data_0 +stable_filename.1=/dev/shm/warmboot_data_1 +stable_filename.2=/dev/shm/warmboot_data_2 + +#Maximum size for NVM used for WB storage, must be larger than sw_state_max_size.BCM8885X +stable_size=800000000 + +######################### +######################### +######################### + +tm_port_header_type_in_0=INJECTED_2_PP +tm_port_header_type_out_0=CPU + +tm_port_header_type_in_200=INJECTED_2_PP +tm_port_header_type_out_200=ETH +tm_port_header_type_in_201=INJECTED_2_PP +tm_port_header_type_out_201=ETH +tm_port_header_type_in_202=INJECTED_2_PP +tm_port_header_type_out_202=ETH +tm_port_header_type_in_203=INJECTED_2_PP +tm_port_header_type_out_203=ETH + +### SAT +## Enable SAT Interface. 0 - Disable, 1 - Enable (Default) +sat_enable=1 +ucode_port_218=SAT:core_0.218 +tm_port_header_type_out_218=CPU +tm_port_header_type_in_218=INJECTED_2 +ucode_port_219=SAT:core_1.219 +tm_port_header_type_out_219=CPU +tm_port_header_type_in_219=INJECTED_2 +port_init_speed_sat=400000 + +### RCY +sai_recycle_port_lane_base=0 +ucode_port_221=RCY.21:core_0.221 +ucode_port_222=RCY.22:core_1.222 +tm_port_header_type_out_221=ETH +tm_port_header_type_in_221=ETH +tm_port_header_type_out_222=ETH +tm_port_header_type_in_222=ETH +port_init_speed_221=400000 +port_init_speed_222=400000 + +#OLP port +tm_port_header_type_in_240=INJECTED_2 +tm_port_header_type_out_240=RAW + +# Set statically the region mode per region id +dtm_flow_mapping_mode_region_257=3 +dtm_flow_mapping_mode_region_258=3 +dtm_flow_mapping_mode_region_259=3 +dtm_flow_mapping_mode_region_260=3 +dtm_flow_mapping_mode_region_261=3 +dtm_flow_mapping_mode_region_262=3 +dtm_flow_mapping_mode_region_263=3 +dtm_flow_mapping_mode_region_264=3 +dtm_flow_mapping_mode_region_265=3 +dtm_flow_mapping_mode_region_266=7 +dtm_flow_mapping_mode_region_267=3 +dtm_flow_mapping_mode_region_268=3 +dtm_flow_mapping_mode_region_269=3 +dtm_flow_mapping_mode_region_270=3 +dtm_flow_mapping_mode_region_271=3 +dtm_flow_mapping_mode_region_272=3 +dtm_flow_mapping_mode_region_273=3 +dtm_flow_mapping_mode_region_274=3 +dtm_flow_mapping_mode_region_275=3 +dtm_flow_mapping_mode_region_276=3 +dtm_flow_mapping_mode_region_277=3 +dtm_flow_mapping_mode_region_278=3 +dtm_flow_mapping_mode_region_279=3 +dtm_flow_mapping_mode_region_280=3 +dtm_flow_mapping_mode_region_281=3 +dtm_flow_mapping_mode_region_282=3 +dtm_flow_mapping_mode_region_283=3 +dtm_flow_mapping_mode_region_284=3 +dtm_flow_mapping_mode_region_285=3 +dtm_flow_mapping_mode_region_286=3 +dtm_flow_mapping_mode_region_287=3 + +## Configure number of symmetric cores each region supports ## +dtm_flow_nof_remote_cores_region_1=2 +dtm_flow_nof_remote_cores_region_2=2 +dtm_flow_nof_remote_cores_region_3=2 +dtm_flow_nof_remote_cores_region_4=2 +dtm_flow_nof_remote_cores_region_5=2 +dtm_flow_nof_remote_cores_region_6=2 +dtm_flow_nof_remote_cores_region_7=2 +dtm_flow_nof_remote_cores_region_8=2 +dtm_flow_nof_remote_cores_region_9=2 +dtm_flow_nof_remote_cores_region_10=2 +dtm_flow_nof_remote_cores_region_11=2 +dtm_flow_nof_remote_cores_region_12=2 +dtm_flow_nof_remote_cores_region_13=2 +dtm_flow_nof_remote_cores_region_14=2 +dtm_flow_nof_remote_cores_region_15=2 +dtm_flow_nof_remote_cores_region_16=2 +dtm_flow_nof_remote_cores_region_17=2 +dtm_flow_nof_remote_cores_region_18=2 +dtm_flow_nof_remote_cores_region_19=2 +dtm_flow_nof_remote_cores_region_20=2 +dtm_flow_nof_remote_cores_region_21=2 +dtm_flow_nof_remote_cores_region_22=2 +dtm_flow_nof_remote_cores_region_23=2 +dtm_flow_nof_remote_cores_region_24=2 +dtm_flow_nof_remote_cores_region_25=2 +dtm_flow_nof_remote_cores_region_26=2 +dtm_flow_nof_remote_cores_region_27=2 +dtm_flow_nof_remote_cores_region_28=2 +dtm_flow_nof_remote_cores_region_29=2 +dtm_flow_nof_remote_cores_region_30=2 +dtm_flow_nof_remote_cores_region_31=2 +dtm_flow_nof_remote_cores_region_32=2 +dtm_flow_nof_remote_cores_region_33=2 +dtm_flow_nof_remote_cores_region_34=2 +dtm_flow_nof_remote_cores_region_35=2 +dtm_flow_nof_remote_cores_region_36=2 +dtm_flow_nof_remote_cores_region_37=2 +dtm_flow_nof_remote_cores_region_38=2 +dtm_flow_nof_remote_cores_region_39=2 +dtm_flow_nof_remote_cores_region_40=2 +dtm_flow_nof_remote_cores_region_41=2 +dtm_flow_nof_remote_cores_region_42=2 +dtm_flow_nof_remote_cores_region_43=2 +dtm_flow_nof_remote_cores_region_44=2 +dtm_flow_nof_remote_cores_region_45=2 +dtm_flow_nof_remote_cores_region_46=2 +dtm_flow_nof_remote_cores_region_47=2 +dtm_flow_nof_remote_cores_region_48=2 +dtm_flow_nof_remote_cores_region_49=2 +dtm_flow_nof_remote_cores_region_50=2 +dtm_flow_nof_remote_cores_region_51=2 +dtm_flow_nof_remote_cores_region_52=2 +dtm_flow_nof_remote_cores_region_53=2 +dtm_flow_nof_remote_cores_region_54=2 +dtm_flow_nof_remote_cores_region_55=2 +dtm_flow_nof_remote_cores_region_56=2 +dtm_flow_nof_remote_cores_region_57=2 +dtm_flow_nof_remote_cores_region_58=2 +dtm_flow_nof_remote_cores_region_59=2 +dtm_flow_nof_remote_cores_region_60=2 + +### MDB configuration ### +mdb_profile=balanced-exem + +### Descriptor-DMA configuration ### +dma_desc_aggregator_chain_length_max=1000 +dma_desc_aggregator_buff_size_kb=100 +dma_desc_aggregator_timeout_usec=1000 +dma_desc_aggregator_enable_specific_MDB_LPM=1 +dma_desc_aggregator_enable_specific_MDB_FEC=1 + +### Outlif configuarion ### +outlif_logical_to_physical_phase_map_1=S1 +outlif_logical_to_physical_phase_map_2=L1 +outlif_logical_to_physical_phase_map_3=XL +outlif_logical_to_physical_phase_map_4=L2 +outlif_logical_to_physical_phase_map_5=M1 +outlif_logical_to_physical_phase_map_6=M2 +outlif_logical_to_physical_phase_map_7=M3 +outlif_logical_to_physical_phase_map_8=S2 + +### Outlif data granularity configuration ### +outlif_physical_phase_data_granularity_S1=60 +outlif_physical_phase_data_granularity_S2=60 +outlif_physical_phase_data_granularity_M1=60 +outlif_physical_phase_data_granularity_M2=60 +outlif_physical_phase_data_granularity_M3=60 +outlif_physical_phase_data_granularity_L1=60 +outlif_physical_phase_data_granularity_L2=60 +outlif_physical_phase_data_granularity_XL=60 + +### Fabric configuration ### +# Enable link-training +port_init_cl72_sfi=1 +serdes_lane_config_cl72_auto_polarity_en=0 +serdes_lane_config_cl72_auto_polarity_en_sfi=1 +serdes_lane_config_cl72_restart_timeout_en=0 + +#SFI speed rate +port_init_speed_fabric=53125 + +## Fabric transmission mode +# Set the Connect mode to the Fabric +# Options: FE - presence of a Fabric device (single stage) +# SINGLE_FAP - stand-alone device +# MESH - devices in Mesh +# Note: If 'diag_chassis' is on, value will be override in dnx.soc +# to be FE instead of SINGLE_FAP. +fabric_connect_mode=FE + +fabric_logical_port_base=512 + +# Fabric lane mapping +lane_to_serdes_map_fabric_lane0=rx0:tx0 +lane_to_serdes_map_fabric_lane1=rx1:tx1 +lane_to_serdes_map_fabric_lane2=rx2:tx2 +lane_to_serdes_map_fabric_lane3=rx3:tx3 +lane_to_serdes_map_fabric_lane4=rx4:tx4 +lane_to_serdes_map_fabric_lane5=rx5:tx5 +lane_to_serdes_map_fabric_lane6=rx6:tx6 +lane_to_serdes_map_fabric_lane7=rx7:tx7 +lane_to_serdes_map_fabric_lane8=rx8:tx10 +lane_to_serdes_map_fabric_lane9=rx9:tx11 +lane_to_serdes_map_fabric_lane10=rx10:tx9 +lane_to_serdes_map_fabric_lane11=rx11:tx8 +lane_to_serdes_map_fabric_lane12=rx12:tx12 +lane_to_serdes_map_fabric_lane13=rx13:tx15 +lane_to_serdes_map_fabric_lane14=rx14:tx14 +lane_to_serdes_map_fabric_lane15=rx15:tx13 +lane_to_serdes_map_fabric_lane16=rx16:tx17 +lane_to_serdes_map_fabric_lane17=rx17:tx18 +lane_to_serdes_map_fabric_lane18=rx18:tx16 +lane_to_serdes_map_fabric_lane19=rx19:tx19 +lane_to_serdes_map_fabric_lane20=rx20:tx21 +lane_to_serdes_map_fabric_lane21=rx21:tx23 +lane_to_serdes_map_fabric_lane22=rx22:tx20 +lane_to_serdes_map_fabric_lane23=rx23:tx22 +lane_to_serdes_map_fabric_lane24=rx24:tx26 +lane_to_serdes_map_fabric_lane25=rx25:tx24 +lane_to_serdes_map_fabric_lane26=rx26:tx25 +lane_to_serdes_map_fabric_lane27=rx27:tx27 +lane_to_serdes_map_fabric_lane28=rx28:tx31 +lane_to_serdes_map_fabric_lane29=rx29:tx30 +lane_to_serdes_map_fabric_lane30=rx30:tx29 +lane_to_serdes_map_fabric_lane31=rx31:tx28 +lane_to_serdes_map_fabric_lane32=rx32:tx32 +lane_to_serdes_map_fabric_lane33=rx33:tx33 +lane_to_serdes_map_fabric_lane34=rx34:tx34 +lane_to_serdes_map_fabric_lane35=rx35:tx35 +lane_to_serdes_map_fabric_lane36=rx36:tx36 +lane_to_serdes_map_fabric_lane37=rx37:tx37 +lane_to_serdes_map_fabric_lane38=rx38:tx38 +lane_to_serdes_map_fabric_lane39=rx39:tx39 +lane_to_serdes_map_fabric_lane40=rx40:tx43 +lane_to_serdes_map_fabric_lane41=rx41:tx42 +lane_to_serdes_map_fabric_lane42=rx42:tx41 +lane_to_serdes_map_fabric_lane43=rx43:tx40 +lane_to_serdes_map_fabric_lane44=rx44:tx47 +lane_to_serdes_map_fabric_lane45=rx45:tx46 +lane_to_serdes_map_fabric_lane46=rx46:tx45 +lane_to_serdes_map_fabric_lane47=rx47:tx44 +lane_to_serdes_map_fabric_lane48=rx48:tx48 +lane_to_serdes_map_fabric_lane49=rx49:tx49 +lane_to_serdes_map_fabric_lane50=rx50:tx50 +lane_to_serdes_map_fabric_lane51=rx51:tx51 +lane_to_serdes_map_fabric_lane52=rx52:tx52 +lane_to_serdes_map_fabric_lane53=rx53:tx53 +lane_to_serdes_map_fabric_lane54=rx54:tx54 +lane_to_serdes_map_fabric_lane55=rx55:tx55 +lane_to_serdes_map_fabric_lane56=rx56:tx59 +lane_to_serdes_map_fabric_lane57=rx57:tx58 +lane_to_serdes_map_fabric_lane58=rx58:tx57 +lane_to_serdes_map_fabric_lane59=rx59:tx56 +lane_to_serdes_map_fabric_lane60=rx60:tx63 +lane_to_serdes_map_fabric_lane61=rx61:tx62 +lane_to_serdes_map_fabric_lane62=rx62:tx61 +lane_to_serdes_map_fabric_lane63=rx63:tx60 +lane_to_serdes_map_fabric_lane64=rx64:tx64 +lane_to_serdes_map_fabric_lane65=rx65:tx65 +lane_to_serdes_map_fabric_lane66=rx66:tx66 +lane_to_serdes_map_fabric_lane67=rx67:tx67 +lane_to_serdes_map_fabric_lane68=rx68:tx68 +lane_to_serdes_map_fabric_lane69=rx69:tx69 +lane_to_serdes_map_fabric_lane70=rx70:tx70 +lane_to_serdes_map_fabric_lane71=rx71:tx71 +lane_to_serdes_map_fabric_lane72=rx72:tx75 +lane_to_serdes_map_fabric_lane73=rx73:tx74 +lane_to_serdes_map_fabric_lane74=rx74:tx73 +lane_to_serdes_map_fabric_lane75=rx75:tx72 +lane_to_serdes_map_fabric_lane76=rx76:tx79 +lane_to_serdes_map_fabric_lane77=rx77:tx78 +lane_to_serdes_map_fabric_lane78=rx78:tx77 +lane_to_serdes_map_fabric_lane79=rx79:tx76 +lane_to_serdes_map_fabric_lane80=rx80:tx80 +lane_to_serdes_map_fabric_lane81=rx81:tx81 +lane_to_serdes_map_fabric_lane82=rx82:tx83 +lane_to_serdes_map_fabric_lane83=rx83:tx82 +lane_to_serdes_map_fabric_lane84=rx84:tx85 +lane_to_serdes_map_fabric_lane85=rx85:tx86 +lane_to_serdes_map_fabric_lane86=rx86:tx84 +lane_to_serdes_map_fabric_lane87=rx87:tx87 +lane_to_serdes_map_fabric_lane88=rx88:tx90 +lane_to_serdes_map_fabric_lane89=rx89:tx88 +lane_to_serdes_map_fabric_lane90=rx90:tx91 +lane_to_serdes_map_fabric_lane91=rx91:tx89 +lane_to_serdes_map_fabric_lane92=rx92:tx93 +lane_to_serdes_map_fabric_lane93=rx93:tx92 +lane_to_serdes_map_fabric_lane94=rx94:tx94 +lane_to_serdes_map_fabric_lane95=rx95:tx95 +lane_to_serdes_map_fabric_lane96=rx96:tx96 +lane_to_serdes_map_fabric_lane97=rx97:tx97 +lane_to_serdes_map_fabric_lane98=rx98:tx98 +lane_to_serdes_map_fabric_lane99=rx99:tx99 +lane_to_serdes_map_fabric_lane100=rx100:tx100 +lane_to_serdes_map_fabric_lane101=rx101:tx101 +lane_to_serdes_map_fabric_lane102=rx102:tx102 +lane_to_serdes_map_fabric_lane103=rx103:tx103 +lane_to_serdes_map_fabric_lane104=rx104:tx105 +lane_to_serdes_map_fabric_lane105=rx105:tx106 +lane_to_serdes_map_fabric_lane106=rx106:tx107 +lane_to_serdes_map_fabric_lane107=rx107:tx104 +lane_to_serdes_map_fabric_lane108=rx108:tx111 +lane_to_serdes_map_fabric_lane109=rx109:tx109 +lane_to_serdes_map_fabric_lane110=rx110:tx110 +lane_to_serdes_map_fabric_lane111=rx111:tx108 +lane_to_serdes_map_fabric_lane112=rx112:tx114 +lane_to_serdes_map_fabric_lane113=rx113:tx113 +lane_to_serdes_map_fabric_lane114=rx114:tx112 +lane_to_serdes_map_fabric_lane115=rx115:tx115 +lane_to_serdes_map_fabric_lane116=rx116:tx117 +lane_to_serdes_map_fabric_lane117=rx117:tx116 +lane_to_serdes_map_fabric_lane118=rx118:tx119 +lane_to_serdes_map_fabric_lane119=rx119:tx118 +lane_to_serdes_map_fabric_lane120=rx120:tx123 +lane_to_serdes_map_fabric_lane121=rx121:tx120 +lane_to_serdes_map_fabric_lane122=rx122:tx122 +lane_to_serdes_map_fabric_lane123=rx123:tx121 +lane_to_serdes_map_fabric_lane124=rx124:tx127 +lane_to_serdes_map_fabric_lane125=rx125:tx125 +lane_to_serdes_map_fabric_lane126=rx126:tx124 +lane_to_serdes_map_fabric_lane127=rx127:tx126 +lane_to_serdes_map_fabric_lane128=rx128:tx128 +lane_to_serdes_map_fabric_lane129=rx129:tx129 +lane_to_serdes_map_fabric_lane130=rx130:tx130 +lane_to_serdes_map_fabric_lane131=rx131:tx131 +lane_to_serdes_map_fabric_lane132=rx132:tx132 +lane_to_serdes_map_fabric_lane133=rx133:tx133 +lane_to_serdes_map_fabric_lane134=rx134:tx134 +lane_to_serdes_map_fabric_lane135=rx135:tx135 +lane_to_serdes_map_fabric_lane136=rx136:tx139 +lane_to_serdes_map_fabric_lane137=rx137:tx138 +lane_to_serdes_map_fabric_lane138=rx138:tx137 +lane_to_serdes_map_fabric_lane139=rx139:tx136 +lane_to_serdes_map_fabric_lane140=rx140:tx140 +lane_to_serdes_map_fabric_lane141=rx141:tx142 +lane_to_serdes_map_fabric_lane142=rx142:tx141 +lane_to_serdes_map_fabric_lane143=rx143:tx143 +lane_to_serdes_map_fabric_lane144=rx144:tx144 +lane_to_serdes_map_fabric_lane145=rx145:tx145 +lane_to_serdes_map_fabric_lane146=rx146:tx146 +lane_to_serdes_map_fabric_lane147=rx147:tx147 +lane_to_serdes_map_fabric_lane148=rx148:tx148 +lane_to_serdes_map_fabric_lane149=rx149:tx149 +lane_to_serdes_map_fabric_lane150=rx150:tx150 +lane_to_serdes_map_fabric_lane151=rx151:tx151 +lane_to_serdes_map_fabric_lane152=rx152:tx155 +lane_to_serdes_map_fabric_lane153=rx153:tx154 +lane_to_serdes_map_fabric_lane154=rx154:tx153 +lane_to_serdes_map_fabric_lane155=rx155:tx152 +lane_to_serdes_map_fabric_lane156=rx156:tx159 +lane_to_serdes_map_fabric_lane157=rx157:tx158 +lane_to_serdes_map_fabric_lane158=rx158:tx157 +lane_to_serdes_map_fabric_lane159=rx159:tx156 +lane_to_serdes_map_fabric_lane160=rx160:tx160 +lane_to_serdes_map_fabric_lane161=rx161:tx161 +lane_to_serdes_map_fabric_lane162=rx162:tx162 +lane_to_serdes_map_fabric_lane163=rx163:tx163 +lane_to_serdes_map_fabric_lane164=rx164:tx164 +lane_to_serdes_map_fabric_lane165=rx165:tx165 +lane_to_serdes_map_fabric_lane166=rx166:tx166 +lane_to_serdes_map_fabric_lane167=rx167:tx167 +lane_to_serdes_map_fabric_lane168=rx168:tx171 +lane_to_serdes_map_fabric_lane169=rx169:tx170 +lane_to_serdes_map_fabric_lane170=rx170:tx169 +lane_to_serdes_map_fabric_lane171=rx171:tx168 +lane_to_serdes_map_fabric_lane172=rx172:tx175 +lane_to_serdes_map_fabric_lane173=rx173:tx174 +lane_to_serdes_map_fabric_lane174=rx174:tx173 +lane_to_serdes_map_fabric_lane175=rx175:tx172 +lane_to_serdes_map_fabric_lane176=rx176:tx176 +lane_to_serdes_map_fabric_lane177=rx177:tx177 +lane_to_serdes_map_fabric_lane178=rx178:tx179 +lane_to_serdes_map_fabric_lane179=rx179:tx178 +lane_to_serdes_map_fabric_lane180=rx180:tx181 +lane_to_serdes_map_fabric_lane181=rx181:tx182 +lane_to_serdes_map_fabric_lane182=rx182:tx180 +lane_to_serdes_map_fabric_lane183=rx183:tx183 +lane_to_serdes_map_fabric_lane184=rx184:tx186 +lane_to_serdes_map_fabric_lane185=rx185:tx184 +lane_to_serdes_map_fabric_lane186=rx186:tx185 +lane_to_serdes_map_fabric_lane187=rx187:tx187 +lane_to_serdes_map_fabric_lane188=rx188:tx188 +lane_to_serdes_map_fabric_lane189=rx189:tx189 +lane_to_serdes_map_fabric_lane190=rx190:tx190 +lane_to_serdes_map_fabric_lane191=rx191:tx191 + +# +##Protocol trap look-up mode: +# Options: IN_LIF - Look-ups in the profile table are done by IN-LIF +# IN_PORT - Look-ups in the profile table are done by IN-PORT +protocol_traps_mode=IN_LIF + +# access definitions +schan_intr_enable=0 +tdma_intr_enable=0 +tslam_intr_enable=0 +miim_intr_enable=0 +schan_timeout_usec=300000 +tdma_timeout_usec=1000000 +tslam_timeout_usec=1000000 + +### Interrupts +appl_enable_intr_init=1 +polled_irq_mode=1 +# reduce CPU load, configure delay 100ms +polled_irq_delay=1000 + +# reduce the CPU load over adapter (caused by counter thread) +bcm_stat_interval=1000 + +# shadow memory +mem_cache_enable_ecc=1 +mem_cache_enable_parity=1 + +# serdes_nif/fabric_clk_freq_in/out configuration +serdes_nif_clk_freq_in=2 +serdes_nif_clk_freq_out=1 +serdes_fabric_clk_freq_in=2 +serdes_fabric_clk_freq_out=1 + +dport_map_direct=1 + +rif_id_max=0x6000 + +phy_rx_polarity_flip_phy0=0 +phy_rx_polarity_flip_phy1=0 +phy_rx_polarity_flip_phy2=0 +phy_rx_polarity_flip_phy3=0 +phy_rx_polarity_flip_phy4=0 +phy_rx_polarity_flip_phy5=0 +phy_rx_polarity_flip_phy6=0 +phy_rx_polarity_flip_phy7=0 +phy_rx_polarity_flip_phy8=1 +phy_rx_polarity_flip_phy9=1 +phy_rx_polarity_flip_phy10=0 +phy_rx_polarity_flip_phy11=1 +phy_rx_polarity_flip_phy12=1 +phy_rx_polarity_flip_phy13=1 +phy_rx_polarity_flip_phy14=1 +phy_rx_polarity_flip_phy15=1 +phy_rx_polarity_flip_phy16=0 +phy_rx_polarity_flip_phy17=0 +phy_rx_polarity_flip_phy18=0 +phy_rx_polarity_flip_phy19=0 +phy_rx_polarity_flip_phy20=0 +phy_rx_polarity_flip_phy21=0 +phy_rx_polarity_flip_phy22=0 +phy_rx_polarity_flip_phy23=0 +phy_rx_polarity_flip_phy24=0 +phy_rx_polarity_flip_phy25=0 +phy_rx_polarity_flip_phy26=0 +phy_rx_polarity_flip_phy27=0 +phy_rx_polarity_flip_phy28=0 +phy_rx_polarity_flip_phy29=0 +phy_rx_polarity_flip_phy30=0 +phy_rx_polarity_flip_phy31=0 +phy_rx_polarity_flip_phy32=0 +phy_rx_polarity_flip_phy33=0 +phy_rx_polarity_flip_phy34=0 +phy_rx_polarity_flip_phy35=0 +phy_rx_polarity_flip_phy36=0 +phy_rx_polarity_flip_phy37=0 +phy_rx_polarity_flip_phy38=0 +phy_rx_polarity_flip_phy39=0 +phy_rx_polarity_flip_phy40=0 +phy_rx_polarity_flip_phy41=0 +phy_rx_polarity_flip_phy42=0 +phy_rx_polarity_flip_phy43=0 +phy_rx_polarity_flip_phy44=0 +phy_rx_polarity_flip_phy45=0 +phy_rx_polarity_flip_phy46=0 +phy_rx_polarity_flip_phy47=0 +phy_rx_polarity_flip_phy48=0 +phy_rx_polarity_flip_phy49=0 +phy_rx_polarity_flip_phy50=0 +phy_rx_polarity_flip_phy51=0 +phy_rx_polarity_flip_phy52=0 +phy_rx_polarity_flip_phy53=0 +phy_rx_polarity_flip_phy54=0 +phy_rx_polarity_flip_phy55=0 +phy_rx_polarity_flip_phy56=0 +phy_rx_polarity_flip_phy57=0 +phy_rx_polarity_flip_phy58=0 +phy_rx_polarity_flip_phy59=0 +phy_rx_polarity_flip_phy60=0 +phy_rx_polarity_flip_phy61=0 +phy_rx_polarity_flip_phy62=0 +phy_rx_polarity_flip_phy63=0 +phy_rx_polarity_flip_phy64=0 +phy_rx_polarity_flip_phy65=0 +phy_rx_polarity_flip_phy66=0 +phy_rx_polarity_flip_phy67=0 +phy_rx_polarity_flip_phy68=0 +phy_rx_polarity_flip_phy69=0 +phy_rx_polarity_flip_phy70=0 +phy_rx_polarity_flip_phy71=0 +phy_rx_polarity_flip_phy72=1 +phy_rx_polarity_flip_phy73=1 +phy_rx_polarity_flip_phy74=1 +phy_rx_polarity_flip_phy75=1 +phy_rx_polarity_flip_phy76=1 +phy_rx_polarity_flip_phy77=1 +phy_rx_polarity_flip_phy78=1 +phy_rx_polarity_flip_phy79=1 +phy_rx_polarity_flip_phy80=0 +phy_rx_polarity_flip_phy81=0 +phy_rx_polarity_flip_phy82=0 +phy_rx_polarity_flip_phy83=0 +phy_rx_polarity_flip_phy84=0 +phy_rx_polarity_flip_phy85=0 +phy_rx_polarity_flip_phy86=0 +phy_rx_polarity_flip_phy87=0 +phy_rx_polarity_flip_phy88=0 +phy_rx_polarity_flip_phy89=0 +phy_rx_polarity_flip_phy90=1 +phy_rx_polarity_flip_phy91=0 +phy_rx_polarity_flip_phy92=0 +phy_rx_polarity_flip_phy93=0 +phy_rx_polarity_flip_phy94=0 +phy_rx_polarity_flip_phy95=0 +phy_rx_polarity_flip_phy96=0 +phy_rx_polarity_flip_phy97=0 +phy_rx_polarity_flip_phy98=0 +phy_rx_polarity_flip_phy99=0 +phy_rx_polarity_flip_phy100=0 +phy_rx_polarity_flip_phy101=0 +phy_rx_polarity_flip_phy102=0 +phy_rx_polarity_flip_phy103=0 +phy_rx_polarity_flip_phy104=0 +phy_rx_polarity_flip_phy105=0 +phy_rx_polarity_flip_phy106=0 +phy_rx_polarity_flip_phy107=0 +phy_rx_polarity_flip_phy108=0 +phy_rx_polarity_flip_phy109=0 +phy_rx_polarity_flip_phy110=0 +phy_rx_polarity_flip_phy111=0 +phy_rx_polarity_flip_phy112=0 +phy_rx_polarity_flip_phy113=0 +phy_rx_polarity_flip_phy114=0 +phy_rx_polarity_flip_phy115=0 +phy_rx_polarity_flip_phy116=0 +phy_rx_polarity_flip_phy117=0 +phy_rx_polarity_flip_phy118=0 +phy_rx_polarity_flip_phy119=0 +phy_rx_polarity_flip_phy120=0 +phy_rx_polarity_flip_phy121=0 +phy_rx_polarity_flip_phy122=0 +phy_rx_polarity_flip_phy123=0 +phy_rx_polarity_flip_phy124=0 +phy_rx_polarity_flip_phy125=0 +phy_rx_polarity_flip_phy126=0 +phy_rx_polarity_flip_phy127=0 +phy_rx_polarity_flip_phy128=0 +phy_rx_polarity_flip_phy129=0 +phy_rx_polarity_flip_phy130=0 +phy_rx_polarity_flip_phy131=0 +phy_rx_polarity_flip_phy132=0 +phy_rx_polarity_flip_phy133=0 +phy_rx_polarity_flip_phy134=0 +phy_rx_polarity_flip_phy135=0 +phy_rx_polarity_flip_phy136=0 +phy_rx_polarity_flip_phy137=0 +phy_rx_polarity_flip_phy138=0 +phy_rx_polarity_flip_phy139=0 +phy_rx_polarity_flip_phy140=0 +phy_rx_polarity_flip_phy141=0 +phy_rx_polarity_flip_phy142=0 +phy_rx_polarity_flip_phy143=0 +phy_tx_polarity_flip_phy0=1 +phy_tx_polarity_flip_phy1=1 +phy_tx_polarity_flip_phy2=1 +phy_tx_polarity_flip_phy3=1 +phy_tx_polarity_flip_phy4=1 +phy_tx_polarity_flip_phy5=1 +phy_tx_polarity_flip_phy6=1 +phy_tx_polarity_flip_phy7=1 +phy_tx_polarity_flip_phy8=1 +phy_tx_polarity_flip_phy9=0 +phy_tx_polarity_flip_phy10=1 +phy_tx_polarity_flip_phy11=1 +phy_tx_polarity_flip_phy12=1 +phy_tx_polarity_flip_phy13=1 +phy_tx_polarity_flip_phy14=1 +phy_tx_polarity_flip_phy15=1 +phy_tx_polarity_flip_phy16=1 +phy_tx_polarity_flip_phy17=1 +phy_tx_polarity_flip_phy18=1 +phy_tx_polarity_flip_phy19=1 +phy_tx_polarity_flip_phy20=1 +phy_tx_polarity_flip_phy21=1 +phy_tx_polarity_flip_phy22=1 +phy_tx_polarity_flip_phy23=1 +phy_tx_polarity_flip_phy24=1 +phy_tx_polarity_flip_phy25=1 +phy_tx_polarity_flip_phy26=1 +phy_tx_polarity_flip_phy27=1 +phy_tx_polarity_flip_phy28=1 +phy_tx_polarity_flip_phy29=1 +phy_tx_polarity_flip_phy30=1 +phy_tx_polarity_flip_phy31=1 +phy_tx_polarity_flip_phy32=1 +phy_tx_polarity_flip_phy33=1 +phy_tx_polarity_flip_phy34=1 +phy_tx_polarity_flip_phy35=1 +phy_tx_polarity_flip_phy36=1 +phy_tx_polarity_flip_phy37=1 +phy_tx_polarity_flip_phy38=1 +phy_tx_polarity_flip_phy39=1 +phy_tx_polarity_flip_phy40=1 +phy_tx_polarity_flip_phy41=1 +phy_tx_polarity_flip_phy42=1 +phy_tx_polarity_flip_phy43=1 +phy_tx_polarity_flip_phy44=1 +phy_tx_polarity_flip_phy45=1 +phy_tx_polarity_flip_phy46=1 +phy_tx_polarity_flip_phy47=1 +phy_tx_polarity_flip_phy48=1 +phy_tx_polarity_flip_phy49=1 +phy_tx_polarity_flip_phy50=1 +phy_tx_polarity_flip_phy51=1 +phy_tx_polarity_flip_phy52=1 +phy_tx_polarity_flip_phy53=1 +phy_tx_polarity_flip_phy54=1 +phy_tx_polarity_flip_phy55=1 +phy_tx_polarity_flip_phy56=1 +phy_tx_polarity_flip_phy57=1 +phy_tx_polarity_flip_phy58=1 +phy_tx_polarity_flip_phy59=1 +phy_tx_polarity_flip_phy60=1 +phy_tx_polarity_flip_phy61=1 +phy_tx_polarity_flip_phy62=1 +phy_tx_polarity_flip_phy63=1 +phy_tx_polarity_flip_phy64=1 +phy_tx_polarity_flip_phy65=1 +phy_tx_polarity_flip_phy66=1 +phy_tx_polarity_flip_phy67=1 +phy_tx_polarity_flip_phy68=1 +phy_tx_polarity_flip_phy69=1 +phy_tx_polarity_flip_phy70=1 +phy_tx_polarity_flip_phy71=1 +phy_tx_polarity_flip_phy72=0 +phy_tx_polarity_flip_phy73=0 +phy_tx_polarity_flip_phy74=0 +phy_tx_polarity_flip_phy75=0 +phy_tx_polarity_flip_phy76=0 +phy_tx_polarity_flip_phy77=0 +phy_tx_polarity_flip_phy78=0 +phy_tx_polarity_flip_phy79=0 +phy_tx_polarity_flip_phy80=0 +phy_tx_polarity_flip_phy81=0 +phy_tx_polarity_flip_phy82=0 +phy_tx_polarity_flip_phy83=0 +phy_tx_polarity_flip_phy84=0 +phy_tx_polarity_flip_phy85=0 +phy_tx_polarity_flip_phy86=0 +phy_tx_polarity_flip_phy87=0 +phy_tx_polarity_flip_phy88=1 +phy_tx_polarity_flip_phy89=1 +phy_tx_polarity_flip_phy90=1 +phy_tx_polarity_flip_phy91=1 +phy_tx_polarity_flip_phy92=1 +phy_tx_polarity_flip_phy93=1 +phy_tx_polarity_flip_phy94=1 +phy_tx_polarity_flip_phy95=1 +phy_tx_polarity_flip_phy96=1 +phy_tx_polarity_flip_phy97=1 +phy_tx_polarity_flip_phy98=1 +phy_tx_polarity_flip_phy99=1 +phy_tx_polarity_flip_phy100=1 +phy_tx_polarity_flip_phy101=1 +phy_tx_polarity_flip_phy102=1 +phy_tx_polarity_flip_phy103=1 +phy_tx_polarity_flip_phy104=1 +phy_tx_polarity_flip_phy105=1 +phy_tx_polarity_flip_phy106=1 +phy_tx_polarity_flip_phy107=1 +phy_tx_polarity_flip_phy108=1 +phy_tx_polarity_flip_phy109=1 +phy_tx_polarity_flip_phy110=1 +phy_tx_polarity_flip_phy111=1 +phy_tx_polarity_flip_phy112=1 +phy_tx_polarity_flip_phy113=1 +phy_tx_polarity_flip_phy114=1 +phy_tx_polarity_flip_phy115=1 +phy_tx_polarity_flip_phy116=1 +phy_tx_polarity_flip_phy117=1 +phy_tx_polarity_flip_phy118=1 +phy_tx_polarity_flip_phy119=1 +phy_tx_polarity_flip_phy120=1 +phy_tx_polarity_flip_phy121=1 +phy_tx_polarity_flip_phy122=1 +phy_tx_polarity_flip_phy123=1 +phy_tx_polarity_flip_phy124=1 +phy_tx_polarity_flip_phy125=1 +phy_tx_polarity_flip_phy126=1 +phy_tx_polarity_flip_phy127=1 +phy_tx_polarity_flip_phy128=1 +phy_tx_polarity_flip_phy129=1 +phy_tx_polarity_flip_phy130=1 +phy_tx_polarity_flip_phy131=1 +phy_tx_polarity_flip_phy132=1 +phy_tx_polarity_flip_phy133=1 +phy_tx_polarity_flip_phy134=1 +phy_tx_polarity_flip_phy135=1 +phy_tx_polarity_flip_phy136=1 +phy_tx_polarity_flip_phy137=1 +phy_tx_polarity_flip_phy138=1 +phy_tx_polarity_flip_phy139=1 +phy_tx_polarity_flip_phy140=1 +phy_tx_polarity_flip_phy141=1 +phy_tx_polarity_flip_phy142=1 +phy_tx_polarity_flip_phy143=1 + +serdes_tx_taps_1=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_2=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_3=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_4=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_5=nrz:-5:80:-23:0:0:0 +serdes_tx_taps_6=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_7=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_8=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_9=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_10=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_11=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_12=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_13=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_14=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_15=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_16=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_17=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_18=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_19=nrz:-6:85:-21:0:0:0 +serdes_tx_taps_20=nrz:-5:83:-22:0:0:0 +serdes_tx_taps_21=nrz:-4:75:-21:0:0:0 +serdes_tx_taps_22=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_23=nrz:-6:85:-21:0:0:0 +serdes_tx_taps_24=nrz:-5:83:-22:0:0:0 +serdes_tx_taps_25=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_26=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_27=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_28=nrz:-5:80:-23:0:0:0 +serdes_tx_taps_29=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_30=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_31=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_32=nrz:-5:80:-23:0:0:0 +serdes_tx_taps_33=nrz:-5:83:-22:0:0:0 +serdes_tx_taps_34=nrz:-5:83:-22:0:0:0 +serdes_tx_taps_35=nrz:-4:75:-21:0:0:0 +serdes_tx_taps_36=nrz:-8:89:-29:0:0:0 + +serdes_tx_taps_1=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_2=pam4:-16:141:-5:3:-2:-3 +serdes_tx_taps_3=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_4=pam4:-16:141:-5:3:-2:-3 +serdes_tx_taps_5=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_6=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_7=pam4:-16:148:-3:2:0:-1 +serdes_tx_taps_8=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_9=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_10=pam4:-14:136:-14:2:0:-4 +serdes_tx_taps_11=pam4:-16:148:-3:2:0:-1 +serdes_tx_taps_12=pam4:-16:148:-3:2:0:-1 +serdes_tx_taps_13=pam4:-14:136:-14:2:0:-4 +serdes_tx_taps_14=pam4:-16:148:-3:2:0:-1 +serdes_tx_taps_15=pam4:-16:148:-3:2:0:-1 +serdes_tx_taps_16=pam4:-14:136:-14:2:0:-4 +serdes_tx_taps_17=pam4:-14:136:-14:2:0:-4 +serdes_tx_taps_18=pam4:-16:137:-12:2:0:-3 +serdes_tx_taps_19=pam4:-17:144:-1:2:-3:-3 +serdes_tx_taps_20=pam4:-16:141:-5:3:-2:-3 +serdes_tx_taps_21=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_22=pam4:-16:141:-5:3:-2:-3 +serdes_tx_taps_23=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_24=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_25=pam4:-16:148:-3:2:0:-1 +serdes_tx_taps_26=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_27=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_28=pam4:-14:136:-14:2:0:-4 +serdes_tx_taps_29=pam4:-16:148:-3:2:0:-1 +serdes_tx_taps_30=pam4:-16:148:-3:2:0:-1 +serdes_tx_taps_31=pam4:-14:136:-14:2:0:-4 +serdes_tx_taps_32=pam4:-16:148:-3:2:0:-1 +serdes_tx_taps_33=pam4:-16:148:-3:2:0:-1 +serdes_tx_taps_34=pam4:-14:136:-14:2:0:-4 +serdes_tx_taps_35=pam4:-16:141:-5:3:-2:-3 +serdes_tx_taps_36=pam4:-16:137:-12:2:0:-3 + +xflow_macsec_secure_chan_to_num_secure_assoc_encrypt=2 +xflow_macsec_secure_chan_to_num_secure_assoc_decrypt=4 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/pg_profile_lookup.ini b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/pg_profile_lookup.ini new file mode 100644 index 000000000000..e8289ab03112 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/pg_profile_lookup.ini @@ -0,0 +1,17 @@ +# PG lossless profiles. +# speed cable size xon xoff threshold xon_offset + 40000 300m 1280 2560 69632 0 1280 + 100000 300m 1280 2560 110592 0 1280 + 400000 300m 1280 2560 315392 0 1280 + 40000 1000m 1280 2560 114688 0 1280 + 100000 1000m 1280 2560 225280 0 1280 + 400000 1000m 1280 2560 778240 0 1280 + 40000 2000m 1280 2560 184320 0 1280 + 100000 2000m 1280 2560 393216 0 1280 + 400000 2000m 1280 2560 1445888 0 1280 + 40000 80000m 1280 2560 5369856 0 1280 + 100000 80000m 1280 2560 13357056 0 1280 + 400000 80000m 1280 2560 53305344 0 1280 + 40000 120000m 1280 2560 8028160 0 1280 + 100000 120000m 1280 2560 20004864 0 1280 + 400000 120000m 1280 2560 79900672 0 1280 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/port_config.ini b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/port_config.ini new file mode 100644 index 000000000000..4d20baee09fa --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/port_config.ini @@ -0,0 +1,21 @@ +# name lanes alias index role speed asic_port_name coreId corePortId numVoq +Ethernet0 72,73,74,75,76,77,78,79 Ethernet1/1 1 Ext 400000 Eth0-ASIC0 1 1 8 +Ethernet8 80,81,82,83,84,85,86,87 Ethernet2/1 2 Ext 400000 Eth8-ASIC0 1 2 8 +Ethernet16 88,89,90,91,92,93,94,95 Ethernet3/1 3 Ext 400000 Eth16-ASIC0 1 3 8 +Ethernet24 96,97,98,99,100,101,102,103 Ethernet4/1 4 Ext 400000 Eth24-ASIC0 1 4 8 +Ethernet32 104,105,106,107,108,109,110,111 Ethernet5/1 5 Ext 400000 Eth32-ASIC0 1 5 8 +Ethernet40 112,113,114,115,116,117,118,119 Ethernet6/1 6 Ext 400000 Eth40-ASIC0 1 6 8 +Ethernet48 120,121,122,123,124,125,126,127 Ethernet7/1 7 Ext 400000 Eth48-ASIC0 1 7 8 +Ethernet56 128,129,130,131,132,133,134,135 Ethernet8/1 8 Ext 400000 Eth56-ASIC0 1 8 8 +Ethernet64 136,137,138,139,140,141,142,143 Ethernet9/1 9 Ext 400000 Eth64-ASIC0 1 9 8 +Ethernet72 64,65,66,67,68,69,70,71 Ethernet10/1 10 Ext 400000 Eth72-ASIC0 0 10 8 +Ethernet80 56,57,58,59,60,61,62,63 Ethernet11/1 11 Ext 400000 Eth80-ASIC0 0 11 8 +Ethernet88 48,49,50,51,52,53,54,55 Ethernet12/1 12 Ext 400000 Eth88-ASIC0 0 12 8 +Ethernet96 40,41,42,43,44,45,46,47 Ethernet13/1 13 Ext 400000 Eth96-ASIC0 0 13 8 +Ethernet104 32,33,34,35,36,37,38,39 Ethernet14/1 14 Ext 400000 Eth104-ASIC0 0 14 8 +Ethernet112 24,25,26,27,28,29,30,31 Ethernet15/1 15 Ext 400000 Eth112-ASIC0 0 15 8 +Ethernet120 16,17,18,19,20,21,22,23 Ethernet16/1 16 Ext 400000 Eth120-ASIC0 0 16 8 +Ethernet128 8,9,10,11,12,13,14,15 Ethernet17/1 17 Ext 400000 Eth128-ASIC0 0 17 8 +Ethernet136 0,1,2,3,4,5,6,7 Ethernet18/1 18 Ext 400000 Eth136-ASIC0 0 18 8 +Ethernet-Rec0 221 Recirc0/0 19 Rec 400000 Rcy0-ASIC0 0 221 8 +Ethernet-IB0 222 Recirc0/1 20 Inb 400000 Rcy1-ASIC0 1 222 8 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/qos.json.j2 b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/qos.json.j2 new file mode 100644 index 000000000000..3e548325ea30 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/qos.json.j2 @@ -0,0 +1 @@ +{%- include 'qos_config.j2' %} diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/sai.profile b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/sai.profile new file mode 100644 index 000000000000..894b300ad733 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/0/sai.profile @@ -0,0 +1,2 @@ +SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/j2p-a7800r3a-36d-36x400G.config.bcm + diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/buffers.json.j2 b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/buffers.json.j2 new file mode 100644 index 000000000000..f34a844f4a87 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/buffers.json.j2 @@ -0,0 +1,2 @@ +{%- set default_topo = 't2' %} +{%- include 'buffers_config.j2' %} diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/buffers_defaults_t2.j2 b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/buffers_defaults_t2.j2 new file mode 100644 index 000000000000..3555175244d4 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/buffers_defaults_t2.j2 @@ -0,0 +1,37 @@ +{%- set default_cable = '300m' %} + +{%- macro generate_port_lists(PORT_ALL) %} + {# Generate list of ports #} + {%- for port_idx in range(144,288,8) %} + {%- if PORT_ALL.append("Ethernet%d" % (port_idx)) %}{%- endif %} + {%- endfor %} +{%- endmacro %} + +{%- macro generate_buffer_pool_and_profiles() %} + "BUFFER_POOL": { + "ingress_lossless_pool": { + "size": "6441610000", + "type": "both", + "mode": "dynamic", + "xoff": "11354112" + } + }, + "BUFFER_PROFILE": { + "ingress_lossy_profile": { + "pool":"ingress_lossless_pool", + "size":"1280", + "xon_offset": "2560", + "dynamic_th":"0" + }, + "egress_lossless_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "static_th":"33030144" + }, + "egress_lossy_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "dynamic_th":"-1" + } + }, +{%- endmacro %} diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/context_config.json b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/context_config.json new file mode 120000 index 000000000000..3db0e8ed3d9b --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/context_config.json @@ -0,0 +1 @@ +../0/context_config.json \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/j2p-a7800r3a-36d-36x400G.config.bcm b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/j2p-a7800r3a-36d-36x400G.config.bcm new file mode 100644 index 000000000000..56d425f9f9c2 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/j2p-a7800r3a-36d-36x400G.config.bcm @@ -0,0 +1,1022 @@ +soc_family=BCM8885X +system_ref_core_clock_khz=1600000 + +dpp_db_path=/usr/share/bcm/db + +#################################################### +##Reference applications related properties - Start +#################################################### + +## PMF small EXEM connected stage: +# Options: IPMF2 - Ingress PMF 2 stage can perform small EXEM lookups. +# IPMF3 - Ingress PMF 3 stage can perform small EXEM lookups. +## PMF small EXEM connected stage: +# Options: IPMF2 - Ingress PMF 2 stage can perform small EXEM lookups. +# IPMF3 - Ingress PMF 3 stage can perform small EXEM lookups. +pmf_sexem3_stage=IPMF2 + +#################################################### +##Reference applications related properties - End +#################################################### + +# Jericho2-mode (description 0x1 used for Jericho 2 mode) +system_headers_mode=1 + +# HW mode to support 1024 16-member system wide LAGs +trunk_group_max_members=16 + +# Disable link-training +port_init_cl72=0 + +###Default interfaces for Jericho2Plus +#CPU interfaces +ucode_port_0=CPU.0:core_0.0 +ucode_port_200=CPU.8:core_1.200 +ucode_port_201=CPU.16:core_0.201 +ucode_port_202=CPU.24:core_1.202 +ucode_port_203=CPU.32:core_0.203 + +#NIF ETH interfaces on device +ucode_port_1=CDGE9:core_1.1 +ucode_port_2=CDGE10:core_1.2 +ucode_port_3=CDGE11:core_1.3 +ucode_port_4=CDGE12:core_1.4 +ucode_port_5=CDGE13:core_1.5 +ucode_port_6=CDGE14:core_1.6 +ucode_port_7=CDGE15:core_1.7 +ucode_port_8=CDGE16:core_1.8 +ucode_port_9=CDGE17:core_1.9 + +ucode_port_10=CDGE8:core_0.10 +ucode_port_11=CDGE7:core_0.11 +ucode_port_12=CDGE6:core_0.12 +ucode_port_13=CDGE5:core_0.13 +ucode_port_14=CDGE4:core_0.14 +ucode_port_15=CDGE3:core_0.15 +ucode_port_16=CDGE2:core_0.16 +ucode_port_17=CDGE1:core_0.17 +ucode_port_18=CDGE0:core_0.18 + +#NIF default speeds +port_init_speed_xe=10000 +port_init_speed_xl=40000 +port_init_speed_le=50000 +port_init_speed_ce=100000 +port_init_speed_cc=200000 +port_init_speed_cd=400000 +port_init_speed_il=10312 + +port_priorities=8 + +#special ports +ucode_port_240=OLP:core_0.240 + +# NIF lane mapping +lane_to_serdes_map_nif_lane0=rx3:tx4 +lane_to_serdes_map_nif_lane1=rx6:tx1 +lane_to_serdes_map_nif_lane2=rx7:tx5 +lane_to_serdes_map_nif_lane3=rx4:tx7 +lane_to_serdes_map_nif_lane4=rx1:tx2 +lane_to_serdes_map_nif_lane5=rx0:tx0 +lane_to_serdes_map_nif_lane6=rx5:tx3 +lane_to_serdes_map_nif_lane7=rx2:tx6 +lane_to_serdes_map_nif_lane8=rx10:tx11 +lane_to_serdes_map_nif_lane9=rx8:tx8 +lane_to_serdes_map_nif_lane10=rx14:tx12 +lane_to_serdes_map_nif_lane11=rx15:tx15 +lane_to_serdes_map_nif_lane12=rx13:tx10 +lane_to_serdes_map_nif_lane13=rx9:tx9 +lane_to_serdes_map_nif_lane14=rx11:tx13 +lane_to_serdes_map_nif_lane15=rx12:tx14 +lane_to_serdes_map_nif_lane16=rx16:tx17 +lane_to_serdes_map_nif_lane17=rx19:tx21 +lane_to_serdes_map_nif_lane18=rx21:tx18 +lane_to_serdes_map_nif_lane19=rx18:tx16 +lane_to_serdes_map_nif_lane20=rx17:tx23 +lane_to_serdes_map_nif_lane21=rx20:tx22 +lane_to_serdes_map_nif_lane22=rx22:tx20 +lane_to_serdes_map_nif_lane23=rx23:tx19 +lane_to_serdes_map_nif_lane24=rx26:tx28 +lane_to_serdes_map_nif_lane25=rx29:tx31 +lane_to_serdes_map_nif_lane26=rx31:tx29 +lane_to_serdes_map_nif_lane27=rx28:tx27 +lane_to_serdes_map_nif_lane28=rx25:tx25 +lane_to_serdes_map_nif_lane29=rx24:tx30 +lane_to_serdes_map_nif_lane30=rx30:tx24 +lane_to_serdes_map_nif_lane31=rx27:tx26 +lane_to_serdes_map_nif_lane32=rx32:tx39 +lane_to_serdes_map_nif_lane33=rx33:tx38 +lane_to_serdes_map_nif_lane34=rx38:tx32 +lane_to_serdes_map_nif_lane35=rx39:tx33 +lane_to_serdes_map_nif_lane36=rx35:tx37 +lane_to_serdes_map_nif_lane37=rx34:tx36 +lane_to_serdes_map_nif_lane38=rx36:tx34 +lane_to_serdes_map_nif_lane39=rx37:tx35 +lane_to_serdes_map_nif_lane40=rx40:tx41 +lane_to_serdes_map_nif_lane41=rx43:tx45 +lane_to_serdes_map_nif_lane42=rx45:tx42 +lane_to_serdes_map_nif_lane43=rx42:tx40 +lane_to_serdes_map_nif_lane44=rx41:tx47 +lane_to_serdes_map_nif_lane45=rx44:tx46 +lane_to_serdes_map_nif_lane46=rx46:tx44 +lane_to_serdes_map_nif_lane47=rx47:tx43 +lane_to_serdes_map_nif_lane48=rx50:tx52 +lane_to_serdes_map_nif_lane49=rx53:tx55 +lane_to_serdes_map_nif_lane50=rx55:tx53 +lane_to_serdes_map_nif_lane51=rx52:tx51 +lane_to_serdes_map_nif_lane52=rx49:tx49 +lane_to_serdes_map_nif_lane53=rx48:tx54 +lane_to_serdes_map_nif_lane54=rx54:tx48 +lane_to_serdes_map_nif_lane55=rx51:tx50 +lane_to_serdes_map_nif_lane56=rx56:tx63 +lane_to_serdes_map_nif_lane57=rx57:tx62 +lane_to_serdes_map_nif_lane58=rx62:tx56 +lane_to_serdes_map_nif_lane59=rx63:tx57 +lane_to_serdes_map_nif_lane60=rx59:tx61 +lane_to_serdes_map_nif_lane61=rx58:tx60 +lane_to_serdes_map_nif_lane62=rx60:tx58 +lane_to_serdes_map_nif_lane63=rx61:tx59 +lane_to_serdes_map_nif_lane64=rx64:tx65 +lane_to_serdes_map_nif_lane65=rx67:tx69 +lane_to_serdes_map_nif_lane66=rx69:tx66 +lane_to_serdes_map_nif_lane67=rx66:tx64 +lane_to_serdes_map_nif_lane68=rx65:tx71 +lane_to_serdes_map_nif_lane69=rx68:tx70 +lane_to_serdes_map_nif_lane70=rx70:tx68 +lane_to_serdes_map_nif_lane71=rx71:tx67 +lane_to_serdes_map_nif_lane72=rx79:tx74 +lane_to_serdes_map_nif_lane73=rx76:tx75 +lane_to_serdes_map_nif_lane74=rx72:tx76 +lane_to_serdes_map_nif_lane75=rx74:tx73 +lane_to_serdes_map_nif_lane76=rx77:tx79 +lane_to_serdes_map_nif_lane77=rx78:tx78 +lane_to_serdes_map_nif_lane78=rx73:tx77 +lane_to_serdes_map_nif_lane79=rx75:tx72 +lane_to_serdes_map_nif_lane80=rx86:tx86 +lane_to_serdes_map_nif_lane81=rx83:tx87 +lane_to_serdes_map_nif_lane82=rx82:tx81 +lane_to_serdes_map_nif_lane83=rx85:tx80 +lane_to_serdes_map_nif_lane84=rx87:tx85 +lane_to_serdes_map_nif_lane85=rx84:tx84 +lane_to_serdes_map_nif_lane86=rx80:tx82 +lane_to_serdes_map_nif_lane87=rx81:tx83 +lane_to_serdes_map_nif_lane88=rx95:tx90 +lane_to_serdes_map_nif_lane89=rx92:tx88 +lane_to_serdes_map_nif_lane90=rx88:tx92 +lane_to_serdes_map_nif_lane91=rx91:tx95 +lane_to_serdes_map_nif_lane92=rx94:tx89 +lane_to_serdes_map_nif_lane93=rx93:tx91 +lane_to_serdes_map_nif_lane94=rx89:tx93 +lane_to_serdes_map_nif_lane95=rx90:tx94 +lane_to_serdes_map_nif_lane96=rx103:tx97 +lane_to_serdes_map_nif_lane97=rx100:tx96 +lane_to_serdes_map_nif_lane98=rx96:tx100 +lane_to_serdes_map_nif_lane99=rx99:tx103 +lane_to_serdes_map_nif_lane100=rx102:tx99 +lane_to_serdes_map_nif_lane101=rx101:tx98 +lane_to_serdes_map_nif_lane102=rx97:tx101 +lane_to_serdes_map_nif_lane103=rx98:tx102 +lane_to_serdes_map_nif_lane104=rx110:tx107 +lane_to_serdes_map_nif_lane105=rx108:tx105 +lane_to_serdes_map_nif_lane106=rx104:tx108 +lane_to_serdes_map_nif_lane107=rx107:tx110 +lane_to_serdes_map_nif_lane108=rx111:tx106 +lane_to_serdes_map_nif_lane109=rx109:tx104 +lane_to_serdes_map_nif_lane110=rx105:tx109 +lane_to_serdes_map_nif_lane111=rx106:tx111 +lane_to_serdes_map_nif_lane112=rx119:tx114 +lane_to_serdes_map_nif_lane113=rx116:tx112 +lane_to_serdes_map_nif_lane114=rx112:tx116 +lane_to_serdes_map_nif_lane115=rx115:tx119 +lane_to_serdes_map_nif_lane116=rx118:tx113 +lane_to_serdes_map_nif_lane117=rx117:tx115 +lane_to_serdes_map_nif_lane118=rx113:tx117 +lane_to_serdes_map_nif_lane119=rx114:tx118 +lane_to_serdes_map_nif_lane120=rx127:tx121 +lane_to_serdes_map_nif_lane121=rx124:tx120 +lane_to_serdes_map_nif_lane122=rx120:tx124 +lane_to_serdes_map_nif_lane123=rx123:tx127 +lane_to_serdes_map_nif_lane124=rx126:tx123 +lane_to_serdes_map_nif_lane125=rx125:tx122 +lane_to_serdes_map_nif_lane126=rx121:tx125 +lane_to_serdes_map_nif_lane127=rx122:tx126 +lane_to_serdes_map_nif_lane128=rx134:tx131 +lane_to_serdes_map_nif_lane129=rx132:tx129 +lane_to_serdes_map_nif_lane130=rx128:tx132 +lane_to_serdes_map_nif_lane131=rx131:tx134 +lane_to_serdes_map_nif_lane132=rx135:tx130 +lane_to_serdes_map_nif_lane133=rx133:tx128 +lane_to_serdes_map_nif_lane134=rx129:tx133 +lane_to_serdes_map_nif_lane135=rx130:tx135 +lane_to_serdes_map_nif_lane136=rx143:tx138 +lane_to_serdes_map_nif_lane137=rx140:tx136 +lane_to_serdes_map_nif_lane138=rx136:tx140 +lane_to_serdes_map_nif_lane139=rx139:tx143 +lane_to_serdes_map_nif_lane140=rx142:tx137 +lane_to_serdes_map_nif_lane141=rx141:tx139 +lane_to_serdes_map_nif_lane142=rx137:tx141 +lane_to_serdes_map_nif_lane143=rx138:tx142 + +######################### +### High Availability ### +######################### + +sw_state_max_size=750000000 + +#location of warmboot NV memory +#Allowed options for dnx are - 3:external storage in filesystem 4:driver will save the state directly in shared memory +stable_location=4 + +# Note that each unit should have a unique filename and that adapter does not play well with tmp and dev/shm folders. +stable_filename=/dev/shm/warmboot_data_0 +stable_filename.1=/dev/shm/warmboot_data_1 +stable_filename.2=/dev/shm/warmboot_data_2 + +#Maximum size for NVM used for WB storage, must be larger than sw_state_max_size.BCM8885X +stable_size=800000000 + +######################### +######################### +######################### + +tm_port_header_type_in_0=INJECTED_2_PP +tm_port_header_type_out_0=CPU + +tm_port_header_type_in_200=INJECTED_2_PP +tm_port_header_type_out_200=ETH +tm_port_header_type_in_201=INJECTED_2_PP +tm_port_header_type_out_201=ETH +tm_port_header_type_in_202=INJECTED_2_PP +tm_port_header_type_out_202=ETH +tm_port_header_type_in_203=INJECTED_2_PP +tm_port_header_type_out_203=ETH + +### SAT +## Enable SAT Interface. 0 - Disable, 1 - Enable (Default) +sat_enable=1 +ucode_port_218=SAT:core_0.218 +tm_port_header_type_out_218=CPU +tm_port_header_type_in_218=INJECTED_2 +ucode_port_219=SAT:core_1.219 +tm_port_header_type_out_219=CPU +tm_port_header_type_in_219=INJECTED_2 +port_init_speed_sat=400000 + +### RCY +sai_recycle_port_lane_base=0 +ucode_port_221=RCY.21:core_0.221 +ucode_port_222=RCY.22:core_1.222 +tm_port_header_type_out_221=ETH +tm_port_header_type_in_221=ETH +tm_port_header_type_out_222=ETH +tm_port_header_type_in_222=ETH +port_init_speed_221=400000 +port_init_speed_222=400000 + +#OLP port +tm_port_header_type_in_240=INJECTED_2 +tm_port_header_type_out_240=RAW + +# Set statically the region mode per region id +dtm_flow_mapping_mode_region_257=3 +dtm_flow_mapping_mode_region_258=3 +dtm_flow_mapping_mode_region_259=3 +dtm_flow_mapping_mode_region_260=3 +dtm_flow_mapping_mode_region_261=3 +dtm_flow_mapping_mode_region_262=3 +dtm_flow_mapping_mode_region_263=3 +dtm_flow_mapping_mode_region_264=3 +dtm_flow_mapping_mode_region_265=3 +dtm_flow_mapping_mode_region_266=7 +dtm_flow_mapping_mode_region_267=3 +dtm_flow_mapping_mode_region_268=3 +dtm_flow_mapping_mode_region_269=3 +dtm_flow_mapping_mode_region_270=3 +dtm_flow_mapping_mode_region_271=3 +dtm_flow_mapping_mode_region_272=3 +dtm_flow_mapping_mode_region_273=3 +dtm_flow_mapping_mode_region_274=3 +dtm_flow_mapping_mode_region_275=3 +dtm_flow_mapping_mode_region_276=3 +dtm_flow_mapping_mode_region_277=3 +dtm_flow_mapping_mode_region_278=3 +dtm_flow_mapping_mode_region_279=3 +dtm_flow_mapping_mode_region_280=3 +dtm_flow_mapping_mode_region_281=3 +dtm_flow_mapping_mode_region_282=3 +dtm_flow_mapping_mode_region_283=3 +dtm_flow_mapping_mode_region_284=3 +dtm_flow_mapping_mode_region_285=3 +dtm_flow_mapping_mode_region_286=3 +dtm_flow_mapping_mode_region_287=3 + +## Configure number of symmetric cores each region supports ## +dtm_flow_nof_remote_cores_region_1=2 +dtm_flow_nof_remote_cores_region_2=2 +dtm_flow_nof_remote_cores_region_3=2 +dtm_flow_nof_remote_cores_region_4=2 +dtm_flow_nof_remote_cores_region_5=2 +dtm_flow_nof_remote_cores_region_6=2 +dtm_flow_nof_remote_cores_region_7=2 +dtm_flow_nof_remote_cores_region_8=2 +dtm_flow_nof_remote_cores_region_9=2 +dtm_flow_nof_remote_cores_region_10=2 +dtm_flow_nof_remote_cores_region_11=2 +dtm_flow_nof_remote_cores_region_12=2 +dtm_flow_nof_remote_cores_region_13=2 +dtm_flow_nof_remote_cores_region_14=2 +dtm_flow_nof_remote_cores_region_15=2 +dtm_flow_nof_remote_cores_region_16=2 +dtm_flow_nof_remote_cores_region_17=2 +dtm_flow_nof_remote_cores_region_18=2 +dtm_flow_nof_remote_cores_region_19=2 +dtm_flow_nof_remote_cores_region_20=2 +dtm_flow_nof_remote_cores_region_21=2 +dtm_flow_nof_remote_cores_region_22=2 +dtm_flow_nof_remote_cores_region_23=2 +dtm_flow_nof_remote_cores_region_24=2 +dtm_flow_nof_remote_cores_region_25=2 +dtm_flow_nof_remote_cores_region_26=2 +dtm_flow_nof_remote_cores_region_27=2 +dtm_flow_nof_remote_cores_region_28=2 +dtm_flow_nof_remote_cores_region_29=2 +dtm_flow_nof_remote_cores_region_30=2 +dtm_flow_nof_remote_cores_region_31=2 +dtm_flow_nof_remote_cores_region_32=2 +dtm_flow_nof_remote_cores_region_33=2 +dtm_flow_nof_remote_cores_region_34=2 +dtm_flow_nof_remote_cores_region_35=2 +dtm_flow_nof_remote_cores_region_36=2 +dtm_flow_nof_remote_cores_region_37=2 +dtm_flow_nof_remote_cores_region_38=2 +dtm_flow_nof_remote_cores_region_39=2 +dtm_flow_nof_remote_cores_region_40=2 +dtm_flow_nof_remote_cores_region_41=2 +dtm_flow_nof_remote_cores_region_42=2 +dtm_flow_nof_remote_cores_region_43=2 +dtm_flow_nof_remote_cores_region_44=2 +dtm_flow_nof_remote_cores_region_45=2 +dtm_flow_nof_remote_cores_region_46=2 +dtm_flow_nof_remote_cores_region_47=2 +dtm_flow_nof_remote_cores_region_48=2 +dtm_flow_nof_remote_cores_region_49=2 +dtm_flow_nof_remote_cores_region_50=2 +dtm_flow_nof_remote_cores_region_51=2 +dtm_flow_nof_remote_cores_region_52=2 +dtm_flow_nof_remote_cores_region_53=2 +dtm_flow_nof_remote_cores_region_54=2 +dtm_flow_nof_remote_cores_region_55=2 +dtm_flow_nof_remote_cores_region_56=2 +dtm_flow_nof_remote_cores_region_57=2 +dtm_flow_nof_remote_cores_region_58=2 +dtm_flow_nof_remote_cores_region_59=2 +dtm_flow_nof_remote_cores_region_60=2 + +### MDB configuration ### +mdb_profile=balanced-exem + +### Descriptor-DMA configuration ### +dma_desc_aggregator_chain_length_max=1000 +dma_desc_aggregator_buff_size_kb=100 +dma_desc_aggregator_timeout_usec=1000 +dma_desc_aggregator_enable_specific_MDB_LPM=1 +dma_desc_aggregator_enable_specific_MDB_FEC=1 + +### Outlif configuarion ### +outlif_logical_to_physical_phase_map_1=S1 +outlif_logical_to_physical_phase_map_2=L1 +outlif_logical_to_physical_phase_map_3=XL +outlif_logical_to_physical_phase_map_4=L2 +outlif_logical_to_physical_phase_map_5=M1 +outlif_logical_to_physical_phase_map_6=M2 +outlif_logical_to_physical_phase_map_7=M3 +outlif_logical_to_physical_phase_map_8=S2 + +### Outlif data granularity configuration ### +outlif_physical_phase_data_granularity_S1=60 +outlif_physical_phase_data_granularity_S2=60 +outlif_physical_phase_data_granularity_M1=60 +outlif_physical_phase_data_granularity_M2=60 +outlif_physical_phase_data_granularity_M3=60 +outlif_physical_phase_data_granularity_L1=60 +outlif_physical_phase_data_granularity_L2=60 +outlif_physical_phase_data_granularity_XL=60 + +### Fabric configuration ### +# Enable link-training +port_init_cl72_sfi=1 +serdes_lane_config_cl72_auto_polarity_en=0 +serdes_lane_config_cl72_auto_polarity_en_sfi=1 +serdes_lane_config_cl72_restart_timeout_en=0 + +#SFI speed rate +port_init_speed_fabric=53125 + +## Fabric transmission mode +# Set the Connect mode to the Fabric +# Options: FE - presence of a Fabric device (single stage) +# SINGLE_FAP - stand-alone device +# MESH - devices in Mesh +# Note: If 'diag_chassis' is on, value will be override in dnx.soc +# to be FE instead of SINGLE_FAP. +fabric_connect_mode=FE + +fabric_logical_port_base=512 + +# Fabric lane mapping +lane_to_serdes_map_fabric_lane0=rx0:tx0 +lane_to_serdes_map_fabric_lane1=rx1:tx1 +lane_to_serdes_map_fabric_lane2=rx2:tx2 +lane_to_serdes_map_fabric_lane3=rx3:tx3 +lane_to_serdes_map_fabric_lane4=rx4:tx4 +lane_to_serdes_map_fabric_lane5=rx5:tx5 +lane_to_serdes_map_fabric_lane6=rx6:tx6 +lane_to_serdes_map_fabric_lane7=rx7:tx7 +lane_to_serdes_map_fabric_lane8=rx8:tx10 +lane_to_serdes_map_fabric_lane9=rx9:tx11 +lane_to_serdes_map_fabric_lane10=rx10:tx9 +lane_to_serdes_map_fabric_lane11=rx11:tx8 +lane_to_serdes_map_fabric_lane12=rx12:tx12 +lane_to_serdes_map_fabric_lane13=rx13:tx15 +lane_to_serdes_map_fabric_lane14=rx14:tx14 +lane_to_serdes_map_fabric_lane15=rx15:tx13 +lane_to_serdes_map_fabric_lane16=rx16:tx17 +lane_to_serdes_map_fabric_lane17=rx17:tx18 +lane_to_serdes_map_fabric_lane18=rx18:tx16 +lane_to_serdes_map_fabric_lane19=rx19:tx19 +lane_to_serdes_map_fabric_lane20=rx20:tx21 +lane_to_serdes_map_fabric_lane21=rx21:tx23 +lane_to_serdes_map_fabric_lane22=rx22:tx20 +lane_to_serdes_map_fabric_lane23=rx23:tx22 +lane_to_serdes_map_fabric_lane24=rx24:tx26 +lane_to_serdes_map_fabric_lane25=rx25:tx24 +lane_to_serdes_map_fabric_lane26=rx26:tx25 +lane_to_serdes_map_fabric_lane27=rx27:tx27 +lane_to_serdes_map_fabric_lane28=rx28:tx31 +lane_to_serdes_map_fabric_lane29=rx29:tx30 +lane_to_serdes_map_fabric_lane30=rx30:tx29 +lane_to_serdes_map_fabric_lane31=rx31:tx28 +lane_to_serdes_map_fabric_lane32=rx32:tx32 +lane_to_serdes_map_fabric_lane33=rx33:tx33 +lane_to_serdes_map_fabric_lane34=rx34:tx34 +lane_to_serdes_map_fabric_lane35=rx35:tx35 +lane_to_serdes_map_fabric_lane36=rx36:tx36 +lane_to_serdes_map_fabric_lane37=rx37:tx37 +lane_to_serdes_map_fabric_lane38=rx38:tx38 +lane_to_serdes_map_fabric_lane39=rx39:tx39 +lane_to_serdes_map_fabric_lane40=rx40:tx43 +lane_to_serdes_map_fabric_lane41=rx41:tx42 +lane_to_serdes_map_fabric_lane42=rx42:tx41 +lane_to_serdes_map_fabric_lane43=rx43:tx40 +lane_to_serdes_map_fabric_lane44=rx44:tx47 +lane_to_serdes_map_fabric_lane45=rx45:tx46 +lane_to_serdes_map_fabric_lane46=rx46:tx45 +lane_to_serdes_map_fabric_lane47=rx47:tx44 +lane_to_serdes_map_fabric_lane48=rx48:tx48 +lane_to_serdes_map_fabric_lane49=rx49:tx49 +lane_to_serdes_map_fabric_lane50=rx50:tx50 +lane_to_serdes_map_fabric_lane51=rx51:tx51 +lane_to_serdes_map_fabric_lane52=rx52:tx52 +lane_to_serdes_map_fabric_lane53=rx53:tx53 +lane_to_serdes_map_fabric_lane54=rx54:tx54 +lane_to_serdes_map_fabric_lane55=rx55:tx55 +lane_to_serdes_map_fabric_lane56=rx56:tx59 +lane_to_serdes_map_fabric_lane57=rx57:tx58 +lane_to_serdes_map_fabric_lane58=rx58:tx57 +lane_to_serdes_map_fabric_lane59=rx59:tx56 +lane_to_serdes_map_fabric_lane60=rx60:tx63 +lane_to_serdes_map_fabric_lane61=rx61:tx62 +lane_to_serdes_map_fabric_lane62=rx62:tx61 +lane_to_serdes_map_fabric_lane63=rx63:tx60 +lane_to_serdes_map_fabric_lane64=rx64:tx64 +lane_to_serdes_map_fabric_lane65=rx65:tx65 +lane_to_serdes_map_fabric_lane66=rx66:tx66 +lane_to_serdes_map_fabric_lane67=rx67:tx67 +lane_to_serdes_map_fabric_lane68=rx68:tx68 +lane_to_serdes_map_fabric_lane69=rx69:tx69 +lane_to_serdes_map_fabric_lane70=rx70:tx70 +lane_to_serdes_map_fabric_lane71=rx71:tx71 +lane_to_serdes_map_fabric_lane72=rx72:tx75 +lane_to_serdes_map_fabric_lane73=rx73:tx74 +lane_to_serdes_map_fabric_lane74=rx74:tx73 +lane_to_serdes_map_fabric_lane75=rx75:tx72 +lane_to_serdes_map_fabric_lane76=rx76:tx79 +lane_to_serdes_map_fabric_lane77=rx77:tx78 +lane_to_serdes_map_fabric_lane78=rx78:tx77 +lane_to_serdes_map_fabric_lane79=rx79:tx76 +lane_to_serdes_map_fabric_lane80=rx80:tx80 +lane_to_serdes_map_fabric_lane81=rx81:tx81 +lane_to_serdes_map_fabric_lane82=rx82:tx83 +lane_to_serdes_map_fabric_lane83=rx83:tx82 +lane_to_serdes_map_fabric_lane84=rx84:tx85 +lane_to_serdes_map_fabric_lane85=rx85:tx86 +lane_to_serdes_map_fabric_lane86=rx86:tx84 +lane_to_serdes_map_fabric_lane87=rx87:tx87 +lane_to_serdes_map_fabric_lane88=rx88:tx90 +lane_to_serdes_map_fabric_lane89=rx89:tx88 +lane_to_serdes_map_fabric_lane90=rx90:tx91 +lane_to_serdes_map_fabric_lane91=rx91:tx89 +lane_to_serdes_map_fabric_lane92=rx92:tx93 +lane_to_serdes_map_fabric_lane93=rx93:tx92 +lane_to_serdes_map_fabric_lane94=rx94:tx94 +lane_to_serdes_map_fabric_lane95=rx95:tx95 +lane_to_serdes_map_fabric_lane96=rx96:tx96 +lane_to_serdes_map_fabric_lane97=rx97:tx97 +lane_to_serdes_map_fabric_lane98=rx98:tx98 +lane_to_serdes_map_fabric_lane99=rx99:tx99 +lane_to_serdes_map_fabric_lane100=rx100:tx100 +lane_to_serdes_map_fabric_lane101=rx101:tx101 +lane_to_serdes_map_fabric_lane102=rx102:tx102 +lane_to_serdes_map_fabric_lane103=rx103:tx103 +lane_to_serdes_map_fabric_lane104=rx104:tx105 +lane_to_serdes_map_fabric_lane105=rx105:tx106 +lane_to_serdes_map_fabric_lane106=rx106:tx107 +lane_to_serdes_map_fabric_lane107=rx107:tx104 +lane_to_serdes_map_fabric_lane108=rx108:tx111 +lane_to_serdes_map_fabric_lane109=rx109:tx109 +lane_to_serdes_map_fabric_lane110=rx110:tx110 +lane_to_serdes_map_fabric_lane111=rx111:tx108 +lane_to_serdes_map_fabric_lane112=rx112:tx114 +lane_to_serdes_map_fabric_lane113=rx113:tx113 +lane_to_serdes_map_fabric_lane114=rx114:tx112 +lane_to_serdes_map_fabric_lane115=rx115:tx115 +lane_to_serdes_map_fabric_lane116=rx116:tx117 +lane_to_serdes_map_fabric_lane117=rx117:tx116 +lane_to_serdes_map_fabric_lane118=rx118:tx119 +lane_to_serdes_map_fabric_lane119=rx119:tx118 +lane_to_serdes_map_fabric_lane120=rx120:tx123 +lane_to_serdes_map_fabric_lane121=rx121:tx120 +lane_to_serdes_map_fabric_lane122=rx122:tx122 +lane_to_serdes_map_fabric_lane123=rx123:tx121 +lane_to_serdes_map_fabric_lane124=rx124:tx127 +lane_to_serdes_map_fabric_lane125=rx125:tx125 +lane_to_serdes_map_fabric_lane126=rx126:tx124 +lane_to_serdes_map_fabric_lane127=rx127:tx126 +lane_to_serdes_map_fabric_lane128=rx128:tx128 +lane_to_serdes_map_fabric_lane129=rx129:tx129 +lane_to_serdes_map_fabric_lane130=rx130:tx130 +lane_to_serdes_map_fabric_lane131=rx131:tx131 +lane_to_serdes_map_fabric_lane132=rx132:tx132 +lane_to_serdes_map_fabric_lane133=rx133:tx133 +lane_to_serdes_map_fabric_lane134=rx134:tx134 +lane_to_serdes_map_fabric_lane135=rx135:tx135 +lane_to_serdes_map_fabric_lane136=rx136:tx139 +lane_to_serdes_map_fabric_lane137=rx137:tx138 +lane_to_serdes_map_fabric_lane138=rx138:tx137 +lane_to_serdes_map_fabric_lane139=rx139:tx136 +lane_to_serdes_map_fabric_lane140=rx140:tx140 +lane_to_serdes_map_fabric_lane141=rx141:tx142 +lane_to_serdes_map_fabric_lane142=rx142:tx141 +lane_to_serdes_map_fabric_lane143=rx143:tx143 +lane_to_serdes_map_fabric_lane144=rx144:tx144 +lane_to_serdes_map_fabric_lane145=rx145:tx145 +lane_to_serdes_map_fabric_lane146=rx146:tx146 +lane_to_serdes_map_fabric_lane147=rx147:tx147 +lane_to_serdes_map_fabric_lane148=rx148:tx148 +lane_to_serdes_map_fabric_lane149=rx149:tx149 +lane_to_serdes_map_fabric_lane150=rx150:tx150 +lane_to_serdes_map_fabric_lane151=rx151:tx151 +lane_to_serdes_map_fabric_lane152=rx152:tx155 +lane_to_serdes_map_fabric_lane153=rx153:tx154 +lane_to_serdes_map_fabric_lane154=rx154:tx153 +lane_to_serdes_map_fabric_lane155=rx155:tx152 +lane_to_serdes_map_fabric_lane156=rx156:tx159 +lane_to_serdes_map_fabric_lane157=rx157:tx158 +lane_to_serdes_map_fabric_lane158=rx158:tx157 +lane_to_serdes_map_fabric_lane159=rx159:tx156 +lane_to_serdes_map_fabric_lane160=rx160:tx160 +lane_to_serdes_map_fabric_lane161=rx161:tx161 +lane_to_serdes_map_fabric_lane162=rx162:tx162 +lane_to_serdes_map_fabric_lane163=rx163:tx163 +lane_to_serdes_map_fabric_lane164=rx164:tx164 +lane_to_serdes_map_fabric_lane165=rx165:tx165 +lane_to_serdes_map_fabric_lane166=rx166:tx166 +lane_to_serdes_map_fabric_lane167=rx167:tx167 +lane_to_serdes_map_fabric_lane168=rx168:tx171 +lane_to_serdes_map_fabric_lane169=rx169:tx170 +lane_to_serdes_map_fabric_lane170=rx170:tx169 +lane_to_serdes_map_fabric_lane171=rx171:tx168 +lane_to_serdes_map_fabric_lane172=rx172:tx175 +lane_to_serdes_map_fabric_lane173=rx173:tx174 +lane_to_serdes_map_fabric_lane174=rx174:tx173 +lane_to_serdes_map_fabric_lane175=rx175:tx172 +lane_to_serdes_map_fabric_lane176=rx176:tx176 +lane_to_serdes_map_fabric_lane177=rx177:tx177 +lane_to_serdes_map_fabric_lane178=rx178:tx179 +lane_to_serdes_map_fabric_lane179=rx179:tx178 +lane_to_serdes_map_fabric_lane180=rx180:tx181 +lane_to_serdes_map_fabric_lane181=rx181:tx182 +lane_to_serdes_map_fabric_lane182=rx182:tx180 +lane_to_serdes_map_fabric_lane183=rx183:tx183 +lane_to_serdes_map_fabric_lane184=rx184:tx186 +lane_to_serdes_map_fabric_lane185=rx185:tx184 +lane_to_serdes_map_fabric_lane186=rx186:tx185 +lane_to_serdes_map_fabric_lane187=rx187:tx187 +lane_to_serdes_map_fabric_lane188=rx188:tx188 +lane_to_serdes_map_fabric_lane189=rx189:tx189 +lane_to_serdes_map_fabric_lane190=rx190:tx190 +lane_to_serdes_map_fabric_lane191=rx191:tx191 + +# +##Protocol trap look-up mode: +# Options: IN_LIF - Look-ups in the profile table are done by IN-LIF +# IN_PORT - Look-ups in the profile table are done by IN-PORT +protocol_traps_mode=IN_LIF + +# access definitions +schan_intr_enable=0 +tdma_intr_enable=0 +tslam_intr_enable=0 +miim_intr_enable=0 +schan_timeout_usec=300000 +tdma_timeout_usec=1000000 +tslam_timeout_usec=1000000 + +### Interrupts +appl_enable_intr_init=1 +polled_irq_mode=1 +# reduce CPU load, configure delay 100ms +polled_irq_delay=1000 + +# reduce the CPU load over adapter (caused by counter thread) +bcm_stat_interval=1000 + +# shadow memory +mem_cache_enable_ecc=1 +mem_cache_enable_parity=1 + +# serdes_nif/fabric_clk_freq_in/out configuration +serdes_nif_clk_freq_in=2 +serdes_nif_clk_freq_out=1 +serdes_fabric_clk_freq_in=2 +serdes_fabric_clk_freq_out=1 + +dport_map_direct=1 + +rif_id_max=0x6000 + +phy_rx_polarity_flip_phy0=0 +phy_rx_polarity_flip_phy1=0 +phy_rx_polarity_flip_phy2=0 +phy_rx_polarity_flip_phy3=0 +phy_rx_polarity_flip_phy4=0 +phy_rx_polarity_flip_phy5=0 +phy_rx_polarity_flip_phy6=0 +phy_rx_polarity_flip_phy7=0 +phy_rx_polarity_flip_phy8=1 +phy_rx_polarity_flip_phy9=1 +phy_rx_polarity_flip_phy10=0 +phy_rx_polarity_flip_phy11=0 +phy_rx_polarity_flip_phy12=1 +phy_rx_polarity_flip_phy13=1 +phy_rx_polarity_flip_phy14=0 +phy_rx_polarity_flip_phy15=1 +phy_rx_polarity_flip_phy16=0 +phy_rx_polarity_flip_phy17=0 +phy_rx_polarity_flip_phy18=0 +phy_rx_polarity_flip_phy19=0 +phy_rx_polarity_flip_phy20=0 +phy_rx_polarity_flip_phy21=0 +phy_rx_polarity_flip_phy22=0 +phy_rx_polarity_flip_phy23=0 +phy_rx_polarity_flip_phy24=0 +phy_rx_polarity_flip_phy25=0 +phy_rx_polarity_flip_phy26=0 +phy_rx_polarity_flip_phy27=0 +phy_rx_polarity_flip_phy28=0 +phy_rx_polarity_flip_phy29=0 +phy_rx_polarity_flip_phy30=0 +phy_rx_polarity_flip_phy31=0 +phy_rx_polarity_flip_phy32=0 +phy_rx_polarity_flip_phy33=0 +phy_rx_polarity_flip_phy34=0 +phy_rx_polarity_flip_phy35=0 +phy_rx_polarity_flip_phy36=0 +phy_rx_polarity_flip_phy37=0 +phy_rx_polarity_flip_phy38=0 +phy_rx_polarity_flip_phy39=0 +phy_rx_polarity_flip_phy40=0 +phy_rx_polarity_flip_phy41=0 +phy_rx_polarity_flip_phy42=0 +phy_rx_polarity_flip_phy43=0 +phy_rx_polarity_flip_phy44=0 +phy_rx_polarity_flip_phy45=0 +phy_rx_polarity_flip_phy46=0 +phy_rx_polarity_flip_phy47=0 +phy_rx_polarity_flip_phy48=0 +phy_rx_polarity_flip_phy49=0 +phy_rx_polarity_flip_phy50=0 +phy_rx_polarity_flip_phy51=0 +phy_rx_polarity_flip_phy52=0 +phy_rx_polarity_flip_phy53=0 +phy_rx_polarity_flip_phy54=0 +phy_rx_polarity_flip_phy55=0 +phy_rx_polarity_flip_phy56=0 +phy_rx_polarity_flip_phy57=0 +phy_rx_polarity_flip_phy58=0 +phy_rx_polarity_flip_phy59=0 +phy_rx_polarity_flip_phy60=0 +phy_rx_polarity_flip_phy61=0 +phy_rx_polarity_flip_phy62=0 +phy_rx_polarity_flip_phy63=0 +phy_rx_polarity_flip_phy64=0 +phy_rx_polarity_flip_phy65=0 +phy_rx_polarity_flip_phy66=0 +phy_rx_polarity_flip_phy67=0 +phy_rx_polarity_flip_phy68=0 +phy_rx_polarity_flip_phy69=0 +phy_rx_polarity_flip_phy70=0 +phy_rx_polarity_flip_phy71=0 +phy_rx_polarity_flip_phy72=1 +phy_rx_polarity_flip_phy73=1 +phy_rx_polarity_flip_phy74=0 +phy_rx_polarity_flip_phy75=1 +phy_rx_polarity_flip_phy76=1 +phy_rx_polarity_flip_phy77=1 +phy_rx_polarity_flip_phy78=1 +phy_rx_polarity_flip_phy79=1 +phy_rx_polarity_flip_phy80=0 +phy_rx_polarity_flip_phy81=0 +phy_rx_polarity_flip_phy82=0 +phy_rx_polarity_flip_phy83=0 +phy_rx_polarity_flip_phy84=0 +phy_rx_polarity_flip_phy85=0 +phy_rx_polarity_flip_phy86=0 +phy_rx_polarity_flip_phy87=0 +phy_rx_polarity_flip_phy88=0 +phy_rx_polarity_flip_phy89=0 +phy_rx_polarity_flip_phy90=0 +phy_rx_polarity_flip_phy91=0 +phy_rx_polarity_flip_phy92=0 +phy_rx_polarity_flip_phy93=0 +phy_rx_polarity_flip_phy94=0 +phy_rx_polarity_flip_phy95=0 +phy_rx_polarity_flip_phy96=0 +phy_rx_polarity_flip_phy97=0 +phy_rx_polarity_flip_phy98=0 +phy_rx_polarity_flip_phy99=0 +phy_rx_polarity_flip_phy100=0 +phy_rx_polarity_flip_phy101=0 +phy_rx_polarity_flip_phy102=0 +phy_rx_polarity_flip_phy103=0 +phy_rx_polarity_flip_phy104=0 +phy_rx_polarity_flip_phy105=0 +phy_rx_polarity_flip_phy106=0 +phy_rx_polarity_flip_phy107=0 +phy_rx_polarity_flip_phy108=0 +phy_rx_polarity_flip_phy109=0 +phy_rx_polarity_flip_phy110=0 +phy_rx_polarity_flip_phy111=0 +phy_rx_polarity_flip_phy112=0 +phy_rx_polarity_flip_phy113=0 +phy_rx_polarity_flip_phy114=0 +phy_rx_polarity_flip_phy115=0 +phy_rx_polarity_flip_phy116=0 +phy_rx_polarity_flip_phy117=0 +phy_rx_polarity_flip_phy118=0 +phy_rx_polarity_flip_phy119=0 +phy_rx_polarity_flip_phy120=0 +phy_rx_polarity_flip_phy121=0 +phy_rx_polarity_flip_phy122=0 +phy_rx_polarity_flip_phy123=0 +phy_rx_polarity_flip_phy124=0 +phy_rx_polarity_flip_phy125=0 +phy_rx_polarity_flip_phy126=0 +phy_rx_polarity_flip_phy127=0 +phy_rx_polarity_flip_phy128=0 +phy_rx_polarity_flip_phy129=0 +phy_rx_polarity_flip_phy130=0 +phy_rx_polarity_flip_phy131=0 +phy_rx_polarity_flip_phy132=0 +phy_rx_polarity_flip_phy133=0 +phy_rx_polarity_flip_phy134=0 +phy_rx_polarity_flip_phy135=0 +phy_rx_polarity_flip_phy136=0 +phy_rx_polarity_flip_phy137=0 +phy_rx_polarity_flip_phy138=0 +phy_rx_polarity_flip_phy139=0 +phy_rx_polarity_flip_phy140=0 +phy_rx_polarity_flip_phy141=0 +phy_rx_polarity_flip_phy142=0 +phy_rx_polarity_flip_phy143=0 +phy_tx_polarity_flip_phy0=1 +phy_tx_polarity_flip_phy1=1 +phy_tx_polarity_flip_phy2=1 +phy_tx_polarity_flip_phy3=1 +phy_tx_polarity_flip_phy4=1 +phy_tx_polarity_flip_phy5=1 +phy_tx_polarity_flip_phy6=1 +phy_tx_polarity_flip_phy7=1 +phy_tx_polarity_flip_phy8=1 +phy_tx_polarity_flip_phy9=1 +phy_tx_polarity_flip_phy10=1 +phy_tx_polarity_flip_phy11=1 +phy_tx_polarity_flip_phy12=1 +phy_tx_polarity_flip_phy13=1 +phy_tx_polarity_flip_phy14=1 +phy_tx_polarity_flip_phy15=1 +phy_tx_polarity_flip_phy16=1 +phy_tx_polarity_flip_phy17=1 +phy_tx_polarity_flip_phy18=1 +phy_tx_polarity_flip_phy19=1 +phy_tx_polarity_flip_phy20=1 +phy_tx_polarity_flip_phy21=1 +phy_tx_polarity_flip_phy22=1 +phy_tx_polarity_flip_phy23=1 +phy_tx_polarity_flip_phy24=1 +phy_tx_polarity_flip_phy25=1 +phy_tx_polarity_flip_phy26=1 +phy_tx_polarity_flip_phy27=1 +phy_tx_polarity_flip_phy28=1 +phy_tx_polarity_flip_phy29=1 +phy_tx_polarity_flip_phy30=1 +phy_tx_polarity_flip_phy31=1 +phy_tx_polarity_flip_phy32=1 +phy_tx_polarity_flip_phy33=1 +phy_tx_polarity_flip_phy34=1 +phy_tx_polarity_flip_phy35=1 +phy_tx_polarity_flip_phy36=1 +phy_tx_polarity_flip_phy37=1 +phy_tx_polarity_flip_phy38=1 +phy_tx_polarity_flip_phy39=1 +phy_tx_polarity_flip_phy40=1 +phy_tx_polarity_flip_phy41=1 +phy_tx_polarity_flip_phy42=1 +phy_tx_polarity_flip_phy43=1 +phy_tx_polarity_flip_phy44=1 +phy_tx_polarity_flip_phy45=1 +phy_tx_polarity_flip_phy46=1 +phy_tx_polarity_flip_phy47=1 +phy_tx_polarity_flip_phy48=1 +phy_tx_polarity_flip_phy49=1 +phy_tx_polarity_flip_phy50=1 +phy_tx_polarity_flip_phy51=1 +phy_tx_polarity_flip_phy52=1 +phy_tx_polarity_flip_phy53=1 +phy_tx_polarity_flip_phy54=1 +phy_tx_polarity_flip_phy55=1 +phy_tx_polarity_flip_phy56=1 +phy_tx_polarity_flip_phy57=1 +phy_tx_polarity_flip_phy58=1 +phy_tx_polarity_flip_phy59=1 +phy_tx_polarity_flip_phy60=1 +phy_tx_polarity_flip_phy61=1 +phy_tx_polarity_flip_phy62=1 +phy_tx_polarity_flip_phy63=1 +phy_tx_polarity_flip_phy64=1 +phy_tx_polarity_flip_phy65=1 +phy_tx_polarity_flip_phy66=1 +phy_tx_polarity_flip_phy67=1 +phy_tx_polarity_flip_phy68=1 +phy_tx_polarity_flip_phy69=1 +phy_tx_polarity_flip_phy70=1 +phy_tx_polarity_flip_phy71=1 +phy_tx_polarity_flip_phy72=0 +phy_tx_polarity_flip_phy73=0 +phy_tx_polarity_flip_phy74=0 +phy_tx_polarity_flip_phy75=0 +phy_tx_polarity_flip_phy76=0 +phy_tx_polarity_flip_phy77=0 +phy_tx_polarity_flip_phy78=0 +phy_tx_polarity_flip_phy79=0 +phy_tx_polarity_flip_phy80=0 +phy_tx_polarity_flip_phy81=0 +phy_tx_polarity_flip_phy82=0 +phy_tx_polarity_flip_phy83=0 +phy_tx_polarity_flip_phy84=0 +phy_tx_polarity_flip_phy85=0 +phy_tx_polarity_flip_phy86=0 +phy_tx_polarity_flip_phy87=0 +phy_tx_polarity_flip_phy88=1 +phy_tx_polarity_flip_phy89=1 +phy_tx_polarity_flip_phy90=1 +phy_tx_polarity_flip_phy91=1 +phy_tx_polarity_flip_phy92=1 +phy_tx_polarity_flip_phy93=1 +phy_tx_polarity_flip_phy94=1 +phy_tx_polarity_flip_phy95=1 +phy_tx_polarity_flip_phy96=1 +phy_tx_polarity_flip_phy97=1 +phy_tx_polarity_flip_phy98=1 +phy_tx_polarity_flip_phy99=1 +phy_tx_polarity_flip_phy100=1 +phy_tx_polarity_flip_phy101=1 +phy_tx_polarity_flip_phy102=1 +phy_tx_polarity_flip_phy103=1 +phy_tx_polarity_flip_phy104=1 +phy_tx_polarity_flip_phy105=1 +phy_tx_polarity_flip_phy106=1 +phy_tx_polarity_flip_phy107=1 +phy_tx_polarity_flip_phy108=1 +phy_tx_polarity_flip_phy109=1 +phy_tx_polarity_flip_phy110=1 +phy_tx_polarity_flip_phy111=1 +phy_tx_polarity_flip_phy112=1 +phy_tx_polarity_flip_phy113=1 +phy_tx_polarity_flip_phy114=1 +phy_tx_polarity_flip_phy115=1 +phy_tx_polarity_flip_phy116=1 +phy_tx_polarity_flip_phy117=1 +phy_tx_polarity_flip_phy118=1 +phy_tx_polarity_flip_phy119=1 +phy_tx_polarity_flip_phy120=1 +phy_tx_polarity_flip_phy121=1 +phy_tx_polarity_flip_phy122=1 +phy_tx_polarity_flip_phy123=1 +phy_tx_polarity_flip_phy124=1 +phy_tx_polarity_flip_phy125=1 +phy_tx_polarity_flip_phy126=1 +phy_tx_polarity_flip_phy127=1 +phy_tx_polarity_flip_phy128=1 +phy_tx_polarity_flip_phy129=1 +phy_tx_polarity_flip_phy130=1 +phy_tx_polarity_flip_phy131=1 +phy_tx_polarity_flip_phy132=1 +phy_tx_polarity_flip_phy133=1 +phy_tx_polarity_flip_phy134=1 +phy_tx_polarity_flip_phy135=1 +phy_tx_polarity_flip_phy136=1 +phy_tx_polarity_flip_phy137=1 +phy_tx_polarity_flip_phy138=1 +phy_tx_polarity_flip_phy139=1 +phy_tx_polarity_flip_phy140=1 +phy_tx_polarity_flip_phy141=1 +phy_tx_polarity_flip_phy142=1 +phy_tx_polarity_flip_phy143=1 + +serdes_tx_taps_1=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_2=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_3=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_4=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_5=nrz:-5:80:-23:0:0:0 +serdes_tx_taps_6=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_7=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_8=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_9=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_10=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_11=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_12=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_13=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_14=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_15=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_16=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_17=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_18=nrz:-8:89:-29:0:0:0 +serdes_tx_taps_19=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_20=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_21=nrz:-4:75:-21:0:0:0 +serdes_tx_taps_22=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_23=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_24=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_25=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_26=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_27=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_28=nrz:-5:80:-23:0:0:0 +serdes_tx_taps_29=nrz:-5:78:-22:0:0:0 +serdes_tx_taps_30=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_31=nrz:-7:85:-25:0:0:0 +serdes_tx_taps_32=nrz:-5:80:-23:0:0:0 +serdes_tx_taps_33=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_34=nrz:-5:75:-20:0:0:0 +serdes_tx_taps_35=nrz:-5:80:-23:0:0:0 +serdes_tx_taps_36=nrz:-7:85:-25:0:0:0 + +serdes_tx_taps_1=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_2=pam4:-16:141:-5:3:-2:-3 +serdes_tx_taps_3=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_4=pam4:-16:141:-5:3:-2:-3 +serdes_tx_taps_5=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_6=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_7=pam4:-16:148:-3:2:0:-1 +serdes_tx_taps_8=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_9=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_10=pam4:-14:136:-14:2:0:-4 +serdes_tx_taps_11=pam4:-16:148:-3:2:0:-1 +serdes_tx_taps_12=pam4:-16:148:-3:2:0:-1 +serdes_tx_taps_13=pam4:-14:136:-14:2:0:-4 +serdes_tx_taps_14=pam4:-16:148:-3:2:0:-1 +serdes_tx_taps_15=pam4:-16:148:-3:2:0:-1 +serdes_tx_taps_16=pam4:-14:136:-14:2:0:-4 +serdes_tx_taps_17=pam4:-14:136:-14:2:0:-4 +serdes_tx_taps_18=pam4:-16:137:-12:2:0:-3 +serdes_tx_taps_19=pam4:-17:144:-1:2:-3:-3 +serdes_tx_taps_20=pam4:-16:141:-5:3:-2:-3 +serdes_tx_taps_21=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_22=pam4:-16:141:-5:3:-2:-3 +serdes_tx_taps_23=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_24=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_25=pam4:-16:148:-3:2:0:-1 +serdes_tx_taps_26=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_27=pam4:-16:139:-7:3:-2:-3 +serdes_tx_taps_28=pam4:-14:136:-14:2:0:-4 +serdes_tx_taps_29=pam4:-16:148:-3:2:0:-1 +serdes_tx_taps_30=pam4:-16:148:-3:2:0:-1 +serdes_tx_taps_31=pam4:-14:136:-14:2:0:-4 +serdes_tx_taps_32=pam4:-16:148:-3:2:0:-1 +serdes_tx_taps_33=pam4:-16:148:-3:2:0:-1 +serdes_tx_taps_34=pam4:-14:136:-14:2:0:-4 +serdes_tx_taps_35=pam4:-16:141:-5:3:-2:-3 +serdes_tx_taps_36=pam4:-16:137:-12:2:0:-3 + +xflow_macsec_secure_chan_to_num_secure_assoc_encrypt=2 +xflow_macsec_secure_chan_to_num_secure_assoc_decrypt=4 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/pg_profile_lookup.ini b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/pg_profile_lookup.ini new file mode 100644 index 000000000000..e8289ab03112 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/pg_profile_lookup.ini @@ -0,0 +1,17 @@ +# PG lossless profiles. +# speed cable size xon xoff threshold xon_offset + 40000 300m 1280 2560 69632 0 1280 + 100000 300m 1280 2560 110592 0 1280 + 400000 300m 1280 2560 315392 0 1280 + 40000 1000m 1280 2560 114688 0 1280 + 100000 1000m 1280 2560 225280 0 1280 + 400000 1000m 1280 2560 778240 0 1280 + 40000 2000m 1280 2560 184320 0 1280 + 100000 2000m 1280 2560 393216 0 1280 + 400000 2000m 1280 2560 1445888 0 1280 + 40000 80000m 1280 2560 5369856 0 1280 + 100000 80000m 1280 2560 13357056 0 1280 + 400000 80000m 1280 2560 53305344 0 1280 + 40000 120000m 1280 2560 8028160 0 1280 + 100000 120000m 1280 2560 20004864 0 1280 + 400000 120000m 1280 2560 79900672 0 1280 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/port_config.ini b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/port_config.ini new file mode 100644 index 000000000000..bfdbc47fcf25 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/port_config.ini @@ -0,0 +1,21 @@ +# name lanes alias index role speed asic_port_name coreId corePortId numVoq +Ethernet144 72,73,74,75,76,77,78,79 Ethernet19/1 21 Ext 400000 Eth0-ASIC1 1 1 8 +Ethernet152 80,81,82,83,84,85,86,87 Ethernet20/1 22 Ext 400000 Eth8-ASIC1 1 2 8 +Ethernet160 88,89,90,91,92,93,94,95 Ethernet21/1 23 Ext 400000 Eth16-ASIC1 1 3 8 +Ethernet168 96,97,98,99,100,101,102,103 Ethernet22/1 24 Ext 400000 Eth24-ASIC1 1 4 8 +Ethernet176 104,105,106,107,108,109,110,111 Ethernet23/1 25 Ext 400000 Eth32-ASIC1 1 5 8 +Ethernet184 112,113,114,115,116,117,118,119 Ethernet24/1 26 Ext 400000 Eth40-ASIC1 1 6 8 +Ethernet192 120,121,122,123,124,125,126,127 Ethernet25/1 27 Ext 400000 Eth48-ASIC1 1 7 8 +Ethernet200 128,129,130,131,132,133,134,135 Ethernet26/1 28 Ext 400000 Eth56-ASIC1 1 8 8 +Ethernet208 136,137,138,139,140,141,142,143 Ethernet27/1 29 Ext 400000 Eth64-ASIC1 1 9 8 +Ethernet216 64,65,66,67,68,69,70,71 Ethernet28/1 30 Ext 400000 Eth72-ASIC1 0 10 8 +Ethernet224 56,57,58,59,60,61,62,63 Ethernet29/1 31 Ext 400000 Eth80-ASIC1 0 11 8 +Ethernet232 48,49,50,51,52,53,54,55 Ethernet30/1 32 Ext 400000 Eth88-ASIC1 0 12 8 +Ethernet240 40,41,42,43,44,45,46,47 Ethernet31/1 33 Ext 400000 Eth96-ASIC1 0 13 8 +Ethernet248 32,33,34,35,36,37,38,39 Ethernet32/1 34 Ext 400000 Eth104-ASIC1 0 14 8 +Ethernet256 24,25,26,27,28,29,30,31 Ethernet33/1 35 Ext 400000 Eth112-ASIC1 0 15 8 +Ethernet264 16,17,18,19,20,21,22,23 Ethernet34/1 36 Ext 400000 Eth120-ASIC1 0 16 8 +Ethernet272 8,9,10,11,12,13,14,15 Ethernet35/1 37 Ext 400000 Eth128-ASIC1 0 17 8 +Ethernet280 0,1,2,3,4,5,6,7 Ethernet36/1 38 Ext 400000 Eth136-ASIC1 0 18 8 +Ethernet-Rec1 221 Recirc0/0 39 Rec 400000 Rcy0-ASIC1 0 221 8 +Ethernet-IB1 222 Recirc0/1 40 Inb 400000 Rcy1-ASIC1 1 222 8 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/qos.json.j2 b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/qos.json.j2 new file mode 100644 index 000000000000..3e548325ea30 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/qos.json.j2 @@ -0,0 +1 @@ +{%- include 'qos_config.j2' %} diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/sai.profile b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/sai.profile new file mode 120000 index 000000000000..1e172f3e0765 --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-D36/1/sai.profile @@ -0,0 +1 @@ +../0/sai.profile \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36DM2-D36 b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36DM2-D36 new file mode 120000 index 000000000000..e029ef37b78a --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36DM2-D36 @@ -0,0 +1 @@ +Arista-7800R3A-36D2-D36 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36P-P36 b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36P-P36 new file mode 120000 index 000000000000..e029ef37b78a --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36P-P36 @@ -0,0 +1 @@ +Arista-7800R3A-36D2-D36 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36D2-D36 b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36D2-D36 new file mode 120000 index 000000000000..e029ef37b78a --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36D2-D36 @@ -0,0 +1 @@ +Arista-7800R3A-36D2-D36 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36DM2-D36 b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36DM2-D36 new file mode 120000 index 000000000000..e029ef37b78a --- /dev/null +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3AK-36DM2-D36 @@ -0,0 +1 @@ +Arista-7800R3A-36D2-D36 \ No newline at end of file From 43e1a9837e1acacf16af7d450135c82680f05642 Mon Sep 17 00:00:00 2001 From: Samuel Angebault Date: Fri, 23 Sep 2022 02:52:40 +0200 Subject: [PATCH 08/35] Add BUILD_DATE to SWI (#11915) Add the BUILD_DATE to the SWI version info, as this is a requirement of Secure Boot. --- build_image.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/build_image.sh b/build_image.sh index 69ea4ddf56ca..03303fbb41eb 100755 --- a/build_image.sh +++ b/build_image.sh @@ -191,6 +191,7 @@ elif [ "$IMAGE_TYPE" = "aboot" ]; then zip -g $ABOOT_BOOT_IMAGE .imagehash rm .imagehash echo "SWI_VERSION=42.0.0" > version + echo "BUILD_DATE=$(date -d "${build_date}" -u +%Y%m%dT%H%M%SZ)" >> version echo "SWI_MAX_HWEPOCH=2" >> version echo "SWI_VARIANT=US" >> version zip -g $OUTPUT_ABOOT_IMAGE version From 3d641129f5eee224fea309fdd1d48e39bfc1998e Mon Sep 17 00:00:00 2001 From: Neetha John Date: Fri, 7 Oct 2022 09:37:53 -0700 Subject: [PATCH 09/35] [minigraph] Remove SLB and bgp monitor peers for storage backend (#12251) Signed-off-by: Neetha John nejo@microsoft.com Why I did it slb and bgp mon peers are not needed for storage backend. These neighbor are present in the minigraph. How I did it After minigraph parsing, remove these neighbors if it is a storage backend device How to verify it Unit tests Verified on the device that once these tables are removed, these peers don't show up in "show runningconfig bgp" output --- src/sonic-config-engine/minigraph.py | 5 +++++ src/sonic-config-engine/tests/test_cfggen.py | 10 +++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/sonic-config-engine/minigraph.py b/src/sonic-config-engine/minigraph.py index b67595247db3..f47f8e7a1c5d 100644 --- a/src/sonic-config-engine/minigraph.py +++ b/src/sonic-config-engine/minigraph.py @@ -1768,6 +1768,11 @@ def parse_xml(filename, platform=None, port_config_file=None, asic_name=None, hw if is_storage_device: results['DEVICE_METADATA']['localhost']['storage_device'] = "true" + # remove bgp monitor and slb peers for storage backend + if is_storage_device and 'BackEnd' in current_device['type']: + results['BGP_MONITORS'] = {} + results['BGP_PEER_RANGE'] = {} + results['VLAN'] = vlans results['VLAN_MEMBER'] = vlan_members diff --git a/src/sonic-config-engine/tests/test_cfggen.py b/src/sonic-config-engine/tests/test_cfggen.py index 1190ef9680e5..ca5c83e88c79 100644 --- a/src/sonic-config-engine/tests/test_cfggen.py +++ b/src/sonic-config-engine/tests/test_cfggen.py @@ -804,6 +804,14 @@ def verify_sub_intf(self, **kwargs): output = self.run_script(argument) self.assertEqual(output.strip(), "") + # SLB and BGP Monitor table does not exist + argument = '-m "' + graph_file + '" -p "' + self.port_config + '" -v "BGP_PEER_RANGE"' + output = self.run_script(argument) + self.assertEqual(output.strip(), "{}") + argument = '-m "' + graph_file + '" -p "' + self.port_config + '" -v "BGP_MONITORS"' + output = self.run_script(argument) + self.assertEqual(output.strip(), "{}") + # ACL_TABLE should not contain EVERFLOW related entries argument = '-m "' + graph_file + '" -p "' + self.port_config + '" -v "ACL_TABLE"' output = self.run_script(argument) @@ -1021,4 +1029,4 @@ def test_minigraph_packet_chassis_400g_zr_port_config(self): output = self.run_script(argument) output_dict = utils.to_dict(output.strip()) self.assertEqual(output_dict['tx_power'], '7.5') - self.assertEqual(output_dict['laser_freq'], 131000) \ No newline at end of file + self.assertEqual(output_dict['laser_freq'], 131000) From 6578b9d790efc2708bd0612500ce03f06ebde929 Mon Sep 17 00:00:00 2001 From: Ying Xie Date: Thu, 6 Oct 2022 14:15:23 -0700 Subject: [PATCH 10/35] [RDMA] create split profiles for Arista-7050CX3-32S (#12228) Moving buffer configuration files to sub folders to enable multiple buffer profiles. Otherwise, non-functional change. Signed-off-by: Ying Xie ying.xie@microsoft.com --- .../BALANCED/buffers_defaults_t0.j2 | 52 +++++ .../BALANCED/buffers_defaults_t1.j2 | 46 ++++ .../BALANCED/pg_profile_lookup.ini | 8 + .../BALANCED/qos.json.j2 | 206 +++++++++++++++++ .../Arista-7050CX3-32S-C32/RDMA-CENTRIC | 1 + .../Arista-7050CX3-32S-C32/TCP-CENTRIC | 1 + .../buffers_defaults_t0.j2 | 53 +---- .../buffers_defaults_t1.j2 | 47 +--- .../pg_profile_lookup.ini | 9 +- .../Arista-7050CX3-32S-C32/qos.json.j2 | 2 +- .../BALANCED/buffers_defaults_t0.j2 | 53 +++++ .../BALANCED/pg_profile_lookup.ini | 8 + .../BALANCED/qos.json.j2 | 206 +++++++++++++++++ .../Arista-7050CX3-32S-D48C8/RDMA-CENTRIC | 1 + .../Arista-7050CX3-32S-D48C8/TCP-CENTRIC | 1 + .../buffers_defaults_t0.j2 | 54 +---- .../pg_profile_lookup.ini | 9 +- .../Arista-7050CX3-32S-D48C8/qos.json.j2 | 207 +----------------- 18 files changed, 590 insertions(+), 374 deletions(-) create mode 100644 device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/BALANCED/buffers_defaults_t0.j2 create mode 100644 device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/BALANCED/buffers_defaults_t1.j2 create mode 100644 device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/BALANCED/pg_profile_lookup.ini create mode 100644 device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/BALANCED/qos.json.j2 create mode 120000 device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/RDMA-CENTRIC create mode 120000 device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/TCP-CENTRIC mode change 100644 => 120000 device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/buffers_defaults_t0.j2 mode change 100644 => 120000 device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/buffers_defaults_t1.j2 mode change 100644 => 120000 device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/pg_profile_lookup.ini create mode 100644 device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/BALANCED/buffers_defaults_t0.j2 create mode 100644 device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/BALANCED/pg_profile_lookup.ini create mode 100644 device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/BALANCED/qos.json.j2 create mode 120000 device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/RDMA-CENTRIC create mode 120000 device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/TCP-CENTRIC mode change 100644 => 120000 device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/buffers_defaults_t0.j2 mode change 100644 => 120000 device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/pg_profile_lookup.ini mode change 100644 => 120000 device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/qos.json.j2 diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/BALANCED/buffers_defaults_t0.j2 b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/BALANCED/buffers_defaults_t0.j2 new file mode 100644 index 000000000000..d71cdcb265f6 --- /dev/null +++ b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/BALANCED/buffers_defaults_t0.j2 @@ -0,0 +1,52 @@ +{%- set default_cable = '300m' %} + +{%- macro generate_port_lists(PORT_ALL) %} + {# Generate list of ports #} + {%- for port_idx in range(0,32) %} + {%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %} + {%- endfor %} +{%- endmacro %} + +{%- macro generate_buffer_pool_and_profiles() %} + "BUFFER_POOL": { + "ingress_lossless_pool": { + "size": "32732160", + "type": "ingress", + "mode": "dynamic", + "xoff": "1622016" + }, + "egress_lossy_pool": { + "size": "24709632", + "type": "egress", + "mode": "dynamic" + }, + "egress_lossless_pool": { + "size": "32599040", + "type": "egress", + "mode": "static" + } + }, + "BUFFER_PROFILE": { + "ingress_lossy_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "static_th":"32732160" + }, + "egress_lossless_profile": { + "pool":"egress_lossless_pool", + "size":"0", + "static_th":"32599040" + }, + "egress_lossy_profile": { + "pool":"egress_lossy_pool", + "size":"1792", + "dynamic_th":"3" + } + }, +{%- endmacro %} + +{% import 'buffers_extra_queues.j2' as defs with context %} + +{%- macro generate_queue_buffers_with_extra_lossless_queues(port_names, port_names_require_extra_buffer) %} +{{ defs.generate_queue_buffers_with_extra_lossless_queues(port_names, port_names_require_extra_buffer) }} +{%- endmacro %} diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/BALANCED/buffers_defaults_t1.j2 b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/BALANCED/buffers_defaults_t1.j2 new file mode 100644 index 000000000000..eb1dc510e91b --- /dev/null +++ b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/BALANCED/buffers_defaults_t1.j2 @@ -0,0 +1,46 @@ +{%- set default_cable = '300m' %} + +{%- macro generate_port_lists(PORT_ALL) %} + {# Generate list of ports #} + {%- for port_idx in range(0,32) %} + {%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %} + {%- endfor %} +{%- endmacro %} + +{%- macro generate_buffer_pool_and_profiles() %} + "BUFFER_POOL": { + "ingress_lossless_pool": { + "size": "32712448", + "type": "ingress", + "mode": "dynamic", + "xoff": "1622016" + }, + "egress_lossy_pool": { + "size": "24709632", + "type": "egress", + "mode": "dynamic" + }, + "egress_lossless_pool": { + "size": "32599040", + "type": "egress", + "mode": "static" + } + }, + "BUFFER_PROFILE": { + "ingress_lossy_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "static_th":"32712448" + }, + "egress_lossless_profile": { + "pool":"egress_lossless_pool", + "size":"0", + "static_th":"32599040" + }, + "egress_lossy_profile": { + "pool":"egress_lossy_pool", + "size":"1792", + "dynamic_th":"3" + } + }, +{%- endmacro %} diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/BALANCED/pg_profile_lookup.ini b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/BALANCED/pg_profile_lookup.ini new file mode 100644 index 000000000000..5b4482bc74c7 --- /dev/null +++ b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/BALANCED/pg_profile_lookup.ini @@ -0,0 +1,8 @@ +# PG lossless profiles. +# speed cable size xon xoff threshold xon_offset + 50000 5m 4608 4608 160000 0 4608 + 100000 5m 4608 4608 160000 0 4608 + 50000 40m 4608 4608 160000 0 4608 + 100000 40m 4608 4608 160000 0 4608 + 50000 300m 4608 4608 160000 0 4608 + 100000 300m 4608 4608 160000 0 4608 diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/BALANCED/qos.json.j2 b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/BALANCED/qos.json.j2 new file mode 100644 index 000000000000..040da33dd79f --- /dev/null +++ b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/BALANCED/qos.json.j2 @@ -0,0 +1,206 @@ +{% if 'subtype' in DEVICE_METADATA['localhost'] and DEVICE_METADATA['localhost']['subtype'] == 'DualToR' %} +{%- macro generate_dscp_to_tc_map() %} + "DSCP_TO_TC_MAP": { + "AZURE": { + "0" : "1", + "1" : "1", + "2" : "1", + "3" : "3", + "4" : "4", + "5" : "1", + "6" : "1", + "7" : "1", + "8" : "0", + "9" : "1", + "10": "1", + "11": "1", + "12": "1", + "13": "1", + "14": "1", + "15": "1", + "16": "1", + "17": "1", + "18": "1", + "19": "1", + "20": "1", + "21": "1", + "22": "1", + "23": "1", + "24": "1", + "25": "1", + "26": "1", + "27": "1", + "28": "1", + "29": "1", + "30": "1", + "31": "1", + "32": "1", + "33": "8", + "34": "1", + "35": "1", + "36": "1", + "37": "1", + "38": "1", + "39": "1", + "40": "1", + "41": "1", + "42": "1", + "43": "1", + "44": "1", + "45": "1", + "46": "5", + "47": "1", + "48": "7", + "49": "1", + "50": "1", + "51": "1", + "52": "1", + "53": "1", + "54": "1", + "55": "1", + "56": "1", + "57": "1", + "58": "1", + "59": "1", + "60": "1", + "61": "1", + "62": "1", + "63": "1" + }, + "AZURE_TUNNEL": { + "0" : "1", + "1" : "1", + "2" : "1", + "3" : "3", + "4" : "4", + "5" : "1", + "6" : "1", + "7" : "1", + "8" : "0", + "9" : "1", + "10": "1", + "11": "1", + "12": "1", + "13": "1", + "14": "1", + "15": "1", + "16": "1", + "17": "1", + "18": "1", + "19": "1", + "20": "1", + "21": "1", + "22": "1", + "23": "1", + "24": "1", + "25": "1", + "26": "1", + "27": "1", + "28": "1", + "29": "1", + "30": "1", + "31": "1", + "32": "1", + "33": "8", + "34": "1", + "35": "1", + "36": "1", + "37": "1", + "38": "1", + "39": "1", + "40": "1", + "41": "1", + "42": "1", + "43": "1", + "44": "1", + "45": "1", + "46": "5", + "47": "1", + "48": "7", + "49": "1", + "50": "1", + "51": "1", + "52": "1", + "53": "1", + "54": "1", + "55": "1", + "56": "1", + "57": "1", + "58": "1", + "59": "1", + "60": "1", + "61": "1", + "62": "1", + "63": "1" + } + }, +{%- endmacro %} +{%- macro generate_tc_to_pg_map() %} + "TC_TO_PRIORITY_GROUP_MAP": { + "AZURE": { + "0": "0", + "1": "0", + "2": "2", + "3": "3", + "4": "4", + "5": "0", + "6": "6", + "7": "0", + "8": "0" + }, + "AZURE_TUNNEL": { + "0": "0", + "1": "0", + "2": "0", + "3": "2", + "4": "6", + "5": "0", + "6": "0", + "7": "0", + "8": "0" + } + }, +{%- endmacro %} +{%- macro generate_tc_to_queue_map() %} + "TC_TO_QUEUE_MAP": { + "AZURE": { + "0": "0", + "1": "1", + "2": "1", + "3": "3", + "4": "4", + "5": "5", + "6": "1", + "7": "7", + "8": "1" + }, + "AZURE_TUNNEL": { + "0": "0", + "1": "1", + "2": "1", + "3": "2", + "4": "6", + "5": "5", + "6": "1", + "7": "7", + "8": "1" + } + }, +{%- endmacro %} +{%- macro generate_tc_to_dscp_map() %} + "TC_TO_DSCP_MAP": { + "AZURE_TUNNEL": { + "0": "8", + "1": "0", + "2": "0", + "3": "2", + "4": "6", + "5": "46", + "6": "0", + "7": "48", + "8": "33" + } + }, +{%- endmacro %} +{% endif %} +{%- include 'qos_config.j2' %} diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/RDMA-CENTRIC b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/RDMA-CENTRIC new file mode 120000 index 000000000000..d6f7127aa748 --- /dev/null +++ b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/RDMA-CENTRIC @@ -0,0 +1 @@ +BALANCED \ No newline at end of file diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/TCP-CENTRIC b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/TCP-CENTRIC new file mode 120000 index 000000000000..d6f7127aa748 --- /dev/null +++ b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/TCP-CENTRIC @@ -0,0 +1 @@ +BALANCED \ No newline at end of file diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/buffers_defaults_t0.j2 b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/buffers_defaults_t0.j2 deleted file mode 100644 index d71cdcb265f6..000000000000 --- a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/buffers_defaults_t0.j2 +++ /dev/null @@ -1,52 +0,0 @@ -{%- set default_cable = '300m' %} - -{%- macro generate_port_lists(PORT_ALL) %} - {# Generate list of ports #} - {%- for port_idx in range(0,32) %} - {%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %} - {%- endfor %} -{%- endmacro %} - -{%- macro generate_buffer_pool_and_profiles() %} - "BUFFER_POOL": { - "ingress_lossless_pool": { - "size": "32732160", - "type": "ingress", - "mode": "dynamic", - "xoff": "1622016" - }, - "egress_lossy_pool": { - "size": "24709632", - "type": "egress", - "mode": "dynamic" - }, - "egress_lossless_pool": { - "size": "32599040", - "type": "egress", - "mode": "static" - } - }, - "BUFFER_PROFILE": { - "ingress_lossy_profile": { - "pool":"ingress_lossless_pool", - "size":"0", - "static_th":"32732160" - }, - "egress_lossless_profile": { - "pool":"egress_lossless_pool", - "size":"0", - "static_th":"32599040" - }, - "egress_lossy_profile": { - "pool":"egress_lossy_pool", - "size":"1792", - "dynamic_th":"3" - } - }, -{%- endmacro %} - -{% import 'buffers_extra_queues.j2' as defs with context %} - -{%- macro generate_queue_buffers_with_extra_lossless_queues(port_names, port_names_require_extra_buffer) %} -{{ defs.generate_queue_buffers_with_extra_lossless_queues(port_names, port_names_require_extra_buffer) }} -{%- endmacro %} diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/buffers_defaults_t0.j2 b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/buffers_defaults_t0.j2 new file mode 120000 index 000000000000..9524e6a476ac --- /dev/null +++ b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/buffers_defaults_t0.j2 @@ -0,0 +1 @@ +BALANCED/buffers_defaults_t0.j2 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/buffers_defaults_t1.j2 b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/buffers_defaults_t1.j2 deleted file mode 100644 index eb1dc510e91b..000000000000 --- a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/buffers_defaults_t1.j2 +++ /dev/null @@ -1,46 +0,0 @@ -{%- set default_cable = '300m' %} - -{%- macro generate_port_lists(PORT_ALL) %} - {# Generate list of ports #} - {%- for port_idx in range(0,32) %} - {%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %} - {%- endfor %} -{%- endmacro %} - -{%- macro generate_buffer_pool_and_profiles() %} - "BUFFER_POOL": { - "ingress_lossless_pool": { - "size": "32712448", - "type": "ingress", - "mode": "dynamic", - "xoff": "1622016" - }, - "egress_lossy_pool": { - "size": "24709632", - "type": "egress", - "mode": "dynamic" - }, - "egress_lossless_pool": { - "size": "32599040", - "type": "egress", - "mode": "static" - } - }, - "BUFFER_PROFILE": { - "ingress_lossy_profile": { - "pool":"ingress_lossless_pool", - "size":"0", - "static_th":"32712448" - }, - "egress_lossless_profile": { - "pool":"egress_lossless_pool", - "size":"0", - "static_th":"32599040" - }, - "egress_lossy_profile": { - "pool":"egress_lossy_pool", - "size":"1792", - "dynamic_th":"3" - } - }, -{%- endmacro %} diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/buffers_defaults_t1.j2 b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/buffers_defaults_t1.j2 new file mode 120000 index 000000000000..c25cc95d6d57 --- /dev/null +++ b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/buffers_defaults_t1.j2 @@ -0,0 +1 @@ +BALANCED/buffers_defaults_t1.j2 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/pg_profile_lookup.ini b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/pg_profile_lookup.ini deleted file mode 100644 index 5b4482bc74c7..000000000000 --- a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/pg_profile_lookup.ini +++ /dev/null @@ -1,8 +0,0 @@ -# PG lossless profiles. -# speed cable size xon xoff threshold xon_offset - 50000 5m 4608 4608 160000 0 4608 - 100000 5m 4608 4608 160000 0 4608 - 50000 40m 4608 4608 160000 0 4608 - 100000 40m 4608 4608 160000 0 4608 - 50000 300m 4608 4608 160000 0 4608 - 100000 300m 4608 4608 160000 0 4608 diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/pg_profile_lookup.ini b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/pg_profile_lookup.ini new file mode 120000 index 000000000000..297cddb2d223 --- /dev/null +++ b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/pg_profile_lookup.ini @@ -0,0 +1 @@ +BALANCED/pg_profile_lookup.ini \ No newline at end of file diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/qos.json.j2 b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/qos.json.j2 index 5ea713ce7f4c..aef6b6765cf2 120000 --- a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/qos.json.j2 +++ b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-C32/qos.json.j2 @@ -1 +1 @@ -../Arista-7050CX3-32S-D48C8/qos.json.j2 \ No newline at end of file +BALANCED/qos.json.j2 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/BALANCED/buffers_defaults_t0.j2 b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/BALANCED/buffers_defaults_t0.j2 new file mode 100644 index 000000000000..57a7fb131466 --- /dev/null +++ b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/BALANCED/buffers_defaults_t0.j2 @@ -0,0 +1,53 @@ + +{%- set default_cable = '300m' %} + +{%- macro generate_port_lists(PORT_ALL) %} + {# Generate list of ports #} + {%- for port_idx in range(0,32) %} + {%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %} + {%- endfor %} +{%- endmacro %} + +{%- macro generate_buffer_pool_and_profiles() %} + "BUFFER_POOL": { + "ingress_lossless_pool": { + "size": "32689152", + "type": "ingress", + "mode": "dynamic", + "xoff": "2058240" + }, + "egress_lossy_pool": { + "size": "24192256", + "type": "egress", + "mode": "dynamic" + }, + "egress_lossless_pool": { + "size": "32340992", + "type": "egress", + "mode": "static" + } + }, + "BUFFER_PROFILE": { + "ingress_lossy_profile": { + "pool":"ingress_lossless_pool", + "size":"0", + "static_th":"32689152" + }, + "egress_lossless_profile": { + "pool":"egress_lossless_pool", + "size":"0", + "static_th":"32340992" + }, + "egress_lossy_profile": { + "pool":"egress_lossy_pool", + "size":"1792", + "dynamic_th":"3" + } + }, +{%- endmacro %} + +{% import 'buffers_extra_queues.j2' as defs with context %} + +{%- macro generate_queue_buffers_with_extra_lossless_queues(port_names, port_names_require_extra_buffer) %} +{{ defs.generate_queue_buffers_with_extra_lossless_queues(port_names, port_names_require_extra_buffer) }} +{%- endmacro %} diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/BALANCED/pg_profile_lookup.ini b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/BALANCED/pg_profile_lookup.ini new file mode 100644 index 000000000000..5b4482bc74c7 --- /dev/null +++ b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/BALANCED/pg_profile_lookup.ini @@ -0,0 +1,8 @@ +# PG lossless profiles. +# speed cable size xon xoff threshold xon_offset + 50000 5m 4608 4608 160000 0 4608 + 100000 5m 4608 4608 160000 0 4608 + 50000 40m 4608 4608 160000 0 4608 + 100000 40m 4608 4608 160000 0 4608 + 50000 300m 4608 4608 160000 0 4608 + 100000 300m 4608 4608 160000 0 4608 diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/BALANCED/qos.json.j2 b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/BALANCED/qos.json.j2 new file mode 100644 index 000000000000..040da33dd79f --- /dev/null +++ b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/BALANCED/qos.json.j2 @@ -0,0 +1,206 @@ +{% if 'subtype' in DEVICE_METADATA['localhost'] and DEVICE_METADATA['localhost']['subtype'] == 'DualToR' %} +{%- macro generate_dscp_to_tc_map() %} + "DSCP_TO_TC_MAP": { + "AZURE": { + "0" : "1", + "1" : "1", + "2" : "1", + "3" : "3", + "4" : "4", + "5" : "1", + "6" : "1", + "7" : "1", + "8" : "0", + "9" : "1", + "10": "1", + "11": "1", + "12": "1", + "13": "1", + "14": "1", + "15": "1", + "16": "1", + "17": "1", + "18": "1", + "19": "1", + "20": "1", + "21": "1", + "22": "1", + "23": "1", + "24": "1", + "25": "1", + "26": "1", + "27": "1", + "28": "1", + "29": "1", + "30": "1", + "31": "1", + "32": "1", + "33": "8", + "34": "1", + "35": "1", + "36": "1", + "37": "1", + "38": "1", + "39": "1", + "40": "1", + "41": "1", + "42": "1", + "43": "1", + "44": "1", + "45": "1", + "46": "5", + "47": "1", + "48": "7", + "49": "1", + "50": "1", + "51": "1", + "52": "1", + "53": "1", + "54": "1", + "55": "1", + "56": "1", + "57": "1", + "58": "1", + "59": "1", + "60": "1", + "61": "1", + "62": "1", + "63": "1" + }, + "AZURE_TUNNEL": { + "0" : "1", + "1" : "1", + "2" : "1", + "3" : "3", + "4" : "4", + "5" : "1", + "6" : "1", + "7" : "1", + "8" : "0", + "9" : "1", + "10": "1", + "11": "1", + "12": "1", + "13": "1", + "14": "1", + "15": "1", + "16": "1", + "17": "1", + "18": "1", + "19": "1", + "20": "1", + "21": "1", + "22": "1", + "23": "1", + "24": "1", + "25": "1", + "26": "1", + "27": "1", + "28": "1", + "29": "1", + "30": "1", + "31": "1", + "32": "1", + "33": "8", + "34": "1", + "35": "1", + "36": "1", + "37": "1", + "38": "1", + "39": "1", + "40": "1", + "41": "1", + "42": "1", + "43": "1", + "44": "1", + "45": "1", + "46": "5", + "47": "1", + "48": "7", + "49": "1", + "50": "1", + "51": "1", + "52": "1", + "53": "1", + "54": "1", + "55": "1", + "56": "1", + "57": "1", + "58": "1", + "59": "1", + "60": "1", + "61": "1", + "62": "1", + "63": "1" + } + }, +{%- endmacro %} +{%- macro generate_tc_to_pg_map() %} + "TC_TO_PRIORITY_GROUP_MAP": { + "AZURE": { + "0": "0", + "1": "0", + "2": "2", + "3": "3", + "4": "4", + "5": "0", + "6": "6", + "7": "0", + "8": "0" + }, + "AZURE_TUNNEL": { + "0": "0", + "1": "0", + "2": "0", + "3": "2", + "4": "6", + "5": "0", + "6": "0", + "7": "0", + "8": "0" + } + }, +{%- endmacro %} +{%- macro generate_tc_to_queue_map() %} + "TC_TO_QUEUE_MAP": { + "AZURE": { + "0": "0", + "1": "1", + "2": "1", + "3": "3", + "4": "4", + "5": "5", + "6": "1", + "7": "7", + "8": "1" + }, + "AZURE_TUNNEL": { + "0": "0", + "1": "1", + "2": "1", + "3": "2", + "4": "6", + "5": "5", + "6": "1", + "7": "7", + "8": "1" + } + }, +{%- endmacro %} +{%- macro generate_tc_to_dscp_map() %} + "TC_TO_DSCP_MAP": { + "AZURE_TUNNEL": { + "0": "8", + "1": "0", + "2": "0", + "3": "2", + "4": "6", + "5": "46", + "6": "0", + "7": "48", + "8": "33" + } + }, +{%- endmacro %} +{% endif %} +{%- include 'qos_config.j2' %} diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/RDMA-CENTRIC b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/RDMA-CENTRIC new file mode 120000 index 000000000000..d6f7127aa748 --- /dev/null +++ b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/RDMA-CENTRIC @@ -0,0 +1 @@ +BALANCED \ No newline at end of file diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/TCP-CENTRIC b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/TCP-CENTRIC new file mode 120000 index 000000000000..d6f7127aa748 --- /dev/null +++ b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/TCP-CENTRIC @@ -0,0 +1 @@ +BALANCED \ No newline at end of file diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/buffers_defaults_t0.j2 b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/buffers_defaults_t0.j2 deleted file mode 100644 index 57a7fb131466..000000000000 --- a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/buffers_defaults_t0.j2 +++ /dev/null @@ -1,53 +0,0 @@ - -{%- set default_cable = '300m' %} - -{%- macro generate_port_lists(PORT_ALL) %} - {# Generate list of ports #} - {%- for port_idx in range(0,32) %} - {%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %} - {%- endfor %} -{%- endmacro %} - -{%- macro generate_buffer_pool_and_profiles() %} - "BUFFER_POOL": { - "ingress_lossless_pool": { - "size": "32689152", - "type": "ingress", - "mode": "dynamic", - "xoff": "2058240" - }, - "egress_lossy_pool": { - "size": "24192256", - "type": "egress", - "mode": "dynamic" - }, - "egress_lossless_pool": { - "size": "32340992", - "type": "egress", - "mode": "static" - } - }, - "BUFFER_PROFILE": { - "ingress_lossy_profile": { - "pool":"ingress_lossless_pool", - "size":"0", - "static_th":"32689152" - }, - "egress_lossless_profile": { - "pool":"egress_lossless_pool", - "size":"0", - "static_th":"32340992" - }, - "egress_lossy_profile": { - "pool":"egress_lossy_pool", - "size":"1792", - "dynamic_th":"3" - } - }, -{%- endmacro %} - -{% import 'buffers_extra_queues.j2' as defs with context %} - -{%- macro generate_queue_buffers_with_extra_lossless_queues(port_names, port_names_require_extra_buffer) %} -{{ defs.generate_queue_buffers_with_extra_lossless_queues(port_names, port_names_require_extra_buffer) }} -{%- endmacro %} diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/buffers_defaults_t0.j2 b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/buffers_defaults_t0.j2 new file mode 120000 index 000000000000..9524e6a476ac --- /dev/null +++ b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/buffers_defaults_t0.j2 @@ -0,0 +1 @@ +BALANCED/buffers_defaults_t0.j2 \ No newline at end of file diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/pg_profile_lookup.ini b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/pg_profile_lookup.ini deleted file mode 100644 index 5b4482bc74c7..000000000000 --- a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/pg_profile_lookup.ini +++ /dev/null @@ -1,8 +0,0 @@ -# PG lossless profiles. -# speed cable size xon xoff threshold xon_offset - 50000 5m 4608 4608 160000 0 4608 - 100000 5m 4608 4608 160000 0 4608 - 50000 40m 4608 4608 160000 0 4608 - 100000 40m 4608 4608 160000 0 4608 - 50000 300m 4608 4608 160000 0 4608 - 100000 300m 4608 4608 160000 0 4608 diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/pg_profile_lookup.ini b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/pg_profile_lookup.ini new file mode 120000 index 000000000000..297cddb2d223 --- /dev/null +++ b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/pg_profile_lookup.ini @@ -0,0 +1 @@ +BALANCED/pg_profile_lookup.ini \ No newline at end of file diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/qos.json.j2 b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/qos.json.j2 deleted file mode 100644 index 040da33dd79f..000000000000 --- a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/qos.json.j2 +++ /dev/null @@ -1,206 +0,0 @@ -{% if 'subtype' in DEVICE_METADATA['localhost'] and DEVICE_METADATA['localhost']['subtype'] == 'DualToR' %} -{%- macro generate_dscp_to_tc_map() %} - "DSCP_TO_TC_MAP": { - "AZURE": { - "0" : "1", - "1" : "1", - "2" : "1", - "3" : "3", - "4" : "4", - "5" : "1", - "6" : "1", - "7" : "1", - "8" : "0", - "9" : "1", - "10": "1", - "11": "1", - "12": "1", - "13": "1", - "14": "1", - "15": "1", - "16": "1", - "17": "1", - "18": "1", - "19": "1", - "20": "1", - "21": "1", - "22": "1", - "23": "1", - "24": "1", - "25": "1", - "26": "1", - "27": "1", - "28": "1", - "29": "1", - "30": "1", - "31": "1", - "32": "1", - "33": "8", - "34": "1", - "35": "1", - "36": "1", - "37": "1", - "38": "1", - "39": "1", - "40": "1", - "41": "1", - "42": "1", - "43": "1", - "44": "1", - "45": "1", - "46": "5", - "47": "1", - "48": "7", - "49": "1", - "50": "1", - "51": "1", - "52": "1", - "53": "1", - "54": "1", - "55": "1", - "56": "1", - "57": "1", - "58": "1", - "59": "1", - "60": "1", - "61": "1", - "62": "1", - "63": "1" - }, - "AZURE_TUNNEL": { - "0" : "1", - "1" : "1", - "2" : "1", - "3" : "3", - "4" : "4", - "5" : "1", - "6" : "1", - "7" : "1", - "8" : "0", - "9" : "1", - "10": "1", - "11": "1", - "12": "1", - "13": "1", - "14": "1", - "15": "1", - "16": "1", - "17": "1", - "18": "1", - "19": "1", - "20": "1", - "21": "1", - "22": "1", - "23": "1", - "24": "1", - "25": "1", - "26": "1", - "27": "1", - "28": "1", - "29": "1", - "30": "1", - "31": "1", - "32": "1", - "33": "8", - "34": "1", - "35": "1", - "36": "1", - "37": "1", - "38": "1", - "39": "1", - "40": "1", - "41": "1", - "42": "1", - "43": "1", - "44": "1", - "45": "1", - "46": "5", - "47": "1", - "48": "7", - "49": "1", - "50": "1", - "51": "1", - "52": "1", - "53": "1", - "54": "1", - "55": "1", - "56": "1", - "57": "1", - "58": "1", - "59": "1", - "60": "1", - "61": "1", - "62": "1", - "63": "1" - } - }, -{%- endmacro %} -{%- macro generate_tc_to_pg_map() %} - "TC_TO_PRIORITY_GROUP_MAP": { - "AZURE": { - "0": "0", - "1": "0", - "2": "2", - "3": "3", - "4": "4", - "5": "0", - "6": "6", - "7": "0", - "8": "0" - }, - "AZURE_TUNNEL": { - "0": "0", - "1": "0", - "2": "0", - "3": "2", - "4": "6", - "5": "0", - "6": "0", - "7": "0", - "8": "0" - } - }, -{%- endmacro %} -{%- macro generate_tc_to_queue_map() %} - "TC_TO_QUEUE_MAP": { - "AZURE": { - "0": "0", - "1": "1", - "2": "1", - "3": "3", - "4": "4", - "5": "5", - "6": "1", - "7": "7", - "8": "1" - }, - "AZURE_TUNNEL": { - "0": "0", - "1": "1", - "2": "1", - "3": "2", - "4": "6", - "5": "5", - "6": "1", - "7": "7", - "8": "1" - } - }, -{%- endmacro %} -{%- macro generate_tc_to_dscp_map() %} - "TC_TO_DSCP_MAP": { - "AZURE_TUNNEL": { - "0": "8", - "1": "0", - "2": "0", - "3": "2", - "4": "6", - "5": "46", - "6": "0", - "7": "48", - "8": "33" - } - }, -{%- endmacro %} -{% endif %} -{%- include 'qos_config.j2' %} diff --git a/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/qos.json.j2 b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/qos.json.j2 new file mode 120000 index 000000000000..aef6b6765cf2 --- /dev/null +++ b/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8/qos.json.j2 @@ -0,0 +1 @@ +BALANCED/qos.json.j2 \ No newline at end of file From c71c63b420c2be885f338f433ab95e3f5ecf42f6 Mon Sep 17 00:00:00 2001 From: Vivek Date: Wed, 12 Oct 2022 01:46:20 -0700 Subject: [PATCH 11/35] [DHCP_RELAY] Updated wait_for_intf.sh to wait for ipv6 global and link local addr (#12273) - Why I did it Fixes #11431 - How I did it dhcp6relay binds to ipv6 addresses configured on these vlan interfaces Thus check if they are ready before launching dhcp6relay - How to verify it Unit Tests Tested on a live device Signed-off-by: Vivek Reddy Karri --- dockers/docker-dhcp-relay/wait_for_intf.sh.j2 | 26 +++++++++++++++++++ .../tests/dhcp-relay-sample.json | 5 ++++ .../tests/sample_output/py2/wait_for_intf.sh | 22 ++++++++++++++++ .../tests/sample_output/py3/wait_for_intf.sh | 22 ++++++++++++++++ src/sonic-config-engine/tests/test_j2files.py | 3 ++- 5 files changed, 77 insertions(+), 1 deletion(-) create mode 100644 src/sonic-config-engine/tests/dhcp-relay-sample.json diff --git a/dockers/docker-dhcp-relay/wait_for_intf.sh.j2 b/dockers/docker-dhcp-relay/wait_for_intf.sh.j2 index b224a697b5ba..13499a6e6c54 100644 --- a/dockers/docker-dhcp-relay/wait_for_intf.sh.j2 +++ b/dockers/docker-dhcp-relay/wait_for_intf.sh.j2 @@ -21,8 +21,28 @@ function wait_until_iface_ready echo "Interface ${IFACE_NAME} is ready!" } +function check_for_ipv6_link_local +{ + IFACE_NAME=$1 + echo "Waiting until interface ${IFACE_NAME} has a link-local ipv6 address configured...." + + # Status of link local address is not populated in STATE_DB + while true; do + HAS_LL=$(ip -6 addr show ${IFACE_NAME} scope link 2> /dev/null) + RC=$? + if [[ ${RC} == "0" ]] && [[ ! -z ${HAS_LL} ]]; then + break + fi + + sleep 1 + done + + echo "Link-Local address is configured on ${IFACE_NAME}" +} # Wait for all interfaces with IPv4 addresses to be up and ready +# dhcp6relay binds to ipv6 addresses configured on these vlan ifaces +# Thus check if they are ready before launching dhcp6relay {% for (name, prefix) in INTERFACE|pfx_filter %} {% if prefix | ipv4 %} wait_until_iface_ready {{ name }} {{ prefix }} @@ -32,6 +52,12 @@ wait_until_iface_ready {{ name }} {{ prefix }} {% if prefix | ipv4 %} wait_until_iface_ready {{ name }} {{ prefix }} {% endif %} +{% if prefix | ipv6 %} +{% if DHCP_RELAY and name in DHCP_RELAY %} +wait_until_iface_ready {{ name }} {{ prefix }} +check_for_ipv6_link_local {{ name }} +{% endif %} +{% endif %} {% endfor %} {% for (name, prefix) in PORTCHANNEL_INTERFACE|pfx_filter %} {% if prefix | ipv4 %} diff --git a/src/sonic-config-engine/tests/dhcp-relay-sample.json b/src/sonic-config-engine/tests/dhcp-relay-sample.json new file mode 100644 index 000000000000..dfd29ed80f43 --- /dev/null +++ b/src/sonic-config-engine/tests/dhcp-relay-sample.json @@ -0,0 +1,5 @@ +{ + "VLAN_INTERFACE": { + "Vlan1000|fc02:2000::2/24": {} + } +} diff --git a/src/sonic-config-engine/tests/sample_output/py2/wait_for_intf.sh b/src/sonic-config-engine/tests/sample_output/py2/wait_for_intf.sh index 8ba15b1c8355..1d58bc956bd1 100644 --- a/src/sonic-config-engine/tests/sample_output/py2/wait_for_intf.sh +++ b/src/sonic-config-engine/tests/sample_output/py2/wait_for_intf.sh @@ -21,10 +21,32 @@ function wait_until_iface_ready echo "Interface ${IFACE_NAME} is ready!" } +function check_for_ipv6_link_local +{ + IFACE_NAME=$1 + echo "Waiting until interface ${IFACE_NAME} has a link-local ipv6 address configured...." + + # Status of link local address is not populated in STATE_DB + while true; do + HAS_LL=$(ip -6 addr show ${IFACE_NAME} scope link 2> /dev/null) + RC=$? + if [[ ${RC} == "0" ]] && [[ ! -z ${HAS_LL} ]]; then + break + fi + + sleep 1 + done + + echo "Link-Local address is configured on ${IFACE_NAME}" +} # Wait for all interfaces with IPv4 addresses to be up and ready +# dhcp6relay binds to ipv6 addresses configured on these vlan ifaces +# Thus check if they are ready before launching dhcp6relay wait_until_iface_ready Vlan2000 192.168.200.1/27 wait_until_iface_ready Vlan1000 192.168.0.1/27 +wait_until_iface_ready Vlan1000 fc02:2000::2/24 +check_for_ipv6_link_local Vlan1000 wait_until_iface_ready PortChannel02 10.0.0.58/31 wait_until_iface_ready PortChannel03 10.0.0.60/31 wait_until_iface_ready PortChannel04 10.0.0.62/31 diff --git a/src/sonic-config-engine/tests/sample_output/py3/wait_for_intf.sh b/src/sonic-config-engine/tests/sample_output/py3/wait_for_intf.sh index 6e5012d5939c..5f0f46a59147 100644 --- a/src/sonic-config-engine/tests/sample_output/py3/wait_for_intf.sh +++ b/src/sonic-config-engine/tests/sample_output/py3/wait_for_intf.sh @@ -21,8 +21,30 @@ function wait_until_iface_ready echo "Interface ${IFACE_NAME} is ready!" } +function check_for_ipv6_link_local +{ + IFACE_NAME=$1 + echo "Waiting until interface ${IFACE_NAME} has a link-local ipv6 address configured...." + + # Status of link local address is not populated in STATE_DB + while true; do + HAS_LL=$(ip -6 addr show ${IFACE_NAME} scope link 2> /dev/null) + RC=$? + if [[ ${RC} == "0" ]] && [[ ! -z ${HAS_LL} ]]; then + break + fi + + sleep 1 + done + + echo "Link-Local address is configured on ${IFACE_NAME}" +} # Wait for all interfaces with IPv4 addresses to be up and ready +# dhcp6relay binds to ipv6 addresses configured on these vlan ifaces +# Thus check if they are ready before launching dhcp6relay +wait_until_iface_ready Vlan1000 fc02:2000::2/24 +check_for_ipv6_link_local Vlan1000 wait_until_iface_ready Vlan1000 192.168.0.1/27 wait_until_iface_ready Vlan2000 192.168.200.1/27 wait_until_iface_ready PortChannel01 10.0.0.56/31 diff --git a/src/sonic-config-engine/tests/test_j2files.py b/src/sonic-config-engine/tests/test_j2files.py index 128a47980a08..92f9c810b35b 100644 --- a/src/sonic-config-engine/tests/test_j2files.py +++ b/src/sonic-config-engine/tests/test_j2files.py @@ -100,8 +100,9 @@ def test_ports_json(self): def test_dhcp_relay(self): # Test generation of wait_for_intf.sh + dhc_sample_data = os.path.join(self.test_dir, "dhcp-relay-sample.json") template_path = os.path.join(self.test_dir, '..', '..', '..', 'dockers', 'docker-dhcp-relay', 'wait_for_intf.sh.j2') - argument = '-m ' + self.t0_minigraph + ' -p ' + self.t0_port_config + ' -t ' + template_path + ' > ' + self.output_file + argument = '-m ' + self.t0_minigraph + ' -j ' + dhc_sample_data + ' -p ' + self.t0_port_config + ' -t ' + template_path + ' > ' + self.output_file self.run_script(argument) self.assertTrue(utils.cmp(os.path.join(self.test_dir, 'sample_output', utils.PYvX_DIR, 'wait_for_intf.sh'), self.output_file)) From 403da08a56350b84171ad3149363f61d81c4475e Mon Sep 17 00:00:00 2001 From: xumia <59720581+xumia@users.noreply.github.com> Date: Tue, 11 Oct 2022 07:59:14 +0800 Subject: [PATCH 12/35] [Build][Bug] Fix apt-get remove version not lock issue (#12193) Why I did it Fix apt-get remove/purge version not locked issue when the apt-get options not specified. How I did it Add a space character before and after the command line parameters. --- src/sonic-build-hooks/hooks/apt-get | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/sonic-build-hooks/hooks/apt-get b/src/sonic-build-hooks/hooks/apt-get index 068293a3e352..3f099375c074 100755 --- a/src/sonic-build-hooks/hooks/apt-get +++ b/src/sonic-build-hooks/hooks/apt-get @@ -20,7 +20,7 @@ if [ "$INSTALL" == y ]; then [ "$lock_result" == y ] && release_apt_installation_lock exit $command_result else - if [[ "$1" == "purge" || "$@" == *" purge "* || "$@" == *" remove "* ]]; then + if [[ " $@ " == *" purge "* || " $@ " == *" remove "* ]]; then # When running the purge command, collect the debian versions dpkg-query -W -f '${Package}==${Version}\n' >> $POST_VERSION_PATH/purge-versions-deb chmod a+wr $POST_VERSION_PATH/purge-versions-deb From 138c428dea45429a50ae46f114db0900d74a3608 Mon Sep 17 00:00:00 2001 From: henry huang <110922668+hehuang-nokia@users.noreply.github.com> Date: Tue, 11 Oct 2022 03:04:07 -0400 Subject: [PATCH 13/35] fixed nokia platform m0 asic mismatch (#12148) changed the platform device name under nokia directory; we now need to specify marvell armhf/arm64 to provide more accurate platform identity. otherwise onie discovery won't recognize the asic being installed. Why I did it when we load images using onie discovery, the process was failing because of marvell ASIC mismatch How I did it replace the platform asic with marvell-armhf under 7215 How to verify it load a new image using http server and verify that the image can be loaded successfully --- device/nokia/armhf-nokia_ixs7215_52x-r0/platform_asic | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/device/nokia/armhf-nokia_ixs7215_52x-r0/platform_asic b/device/nokia/armhf-nokia_ixs7215_52x-r0/platform_asic index a554752878b7..64b1d7dbb42b 100644 --- a/device/nokia/armhf-nokia_ixs7215_52x-r0/platform_asic +++ b/device/nokia/armhf-nokia_ixs7215_52x-r0/platform_asic @@ -1 +1 @@ -marvell +marvell-armhf From 81486021c1355020716f9e42b519d5fd1161c766 Mon Sep 17 00:00:00 2001 From: Sudharsan Dhamal Gopalarathnam Date: Fri, 14 Oct 2022 22:12:28 -0700 Subject: [PATCH 14/35] [Mellanox]Adding SKU Mellanox-SN2700-D44C10 (#12396) #### Why I did it To add new SKU Mellanox-SN2700-D44C10 with following requirements: | Port configuration | Value | | ------ |--------- | | Breakout mode for each port |**Defined in port mapping** | | Speed of the port | **Defined in Port mapping** | | Auto-negotiation enable/disable | **No setting required** | | FEC mode | **No setting required** | |Type of transceiver used | **Not needed**| Buffer configuration | Value ------ |--------- Shared headroom | **Enabled** Shared headroom pool factor | **2** Dynamic Buffer | **Disable** In static buffer scenario how many uplinks and downlinks? | **44 x50G and 2x100G Downlinks 8x100G uplinks** 2km cable support required? | **No** Switch configuration | Value ------ |--------- Warmboot enabled? | **yes** Should warmboot be added to SAI profile when enabled? | **yes** Is VxLAN source port range set? | **No** Should Vxlan source port range be added to SAI profile when set. | **No** Is Static Policy Based Hashing enabled? | **No** Port Mapping | Ports | Mode | | ------ |--------- | | 1,2 | 1x100G | | 3-6 | 2x50G | | 7-10 | 1x100G | | 11-22 | 2x50G | | 23-26 | 1x100G | | 27-32 | 2x50G | Number of Uplinks / Downlinks: TO topology: **44 x50G and 2x100G Downlinks 8x100G uplinks**. #### How I did it Defined the SKU as per requirements #### How to verify it Load the SKU and verify if all links come up and traffic passes. --- .../Mellanox-SN2700-D44C10/buffers.json.j2 | 15 + .../buffers_defaults_objects.j2 | 1 + .../buffers_defaults_t0.j2 | 36 +++ .../buffers_defaults_t1.j2 | 36 +++ .../buffers_dynamic.json.j2 | 16 ++ .../Mellanox-SN2700-D44C10/hwsku.json | 166 +++++++++++ .../pg_profile_lookup.ini | 1 + .../Mellanox-SN2700-D44C10/port_config.ini | 55 ++++ .../Mellanox-SN2700-D44C10/qos.json.j2 | 1 + .../Mellanox-SN2700-D44C10/sai.profile | 3 + .../sai_2700_44x50g_10x100g.xml | 269 ++++++++++++++++++ 11 files changed, 599 insertions(+) create mode 100644 device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/buffers.json.j2 create mode 120000 device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/buffers_defaults_objects.j2 create mode 100644 device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/buffers_defaults_t0.j2 create mode 100644 device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/buffers_defaults_t1.j2 create mode 100644 device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/buffers_dynamic.json.j2 create mode 100644 device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/hwsku.json create mode 120000 device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/pg_profile_lookup.ini create mode 100644 device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/port_config.ini create mode 120000 device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/qos.json.j2 create mode 100644 device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/sai.profile create mode 100644 device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/sai_2700_44x50g_10x100g.xml diff --git a/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/buffers.json.j2 b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/buffers.json.j2 new file mode 100644 index 000000000000..ad3266249133 --- /dev/null +++ b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/buffers.json.j2 @@ -0,0 +1,15 @@ +{# + Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. + Apache-2.0 + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + http://www.apache.org/licenses/LICENSE-2.0 + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +#} +{%- set default_topo = 't0' %} +{%- include 'buffers_config.j2' %} diff --git a/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/buffers_defaults_objects.j2 b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/buffers_defaults_objects.j2 new file mode 120000 index 000000000000..c01aebb7ae12 --- /dev/null +++ b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/buffers_defaults_objects.j2 @@ -0,0 +1 @@ +../../x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D48C8/buffers_defaults_objects.j2 \ No newline at end of file diff --git a/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/buffers_defaults_t0.j2 b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/buffers_defaults_t0.j2 new file mode 100644 index 000000000000..920730c15ecd --- /dev/null +++ b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/buffers_defaults_t0.j2 @@ -0,0 +1,36 @@ +{# + Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. + Apache-2.0 + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + http://www.apache.org/licenses/LICENSE-2.0 + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +#} +{% set default_cable = '5m' %} +{% set ingress_lossless_pool_size = '6822912' %} +{% set ingress_lossless_pool_xoff = '999424' %} +{% set egress_lossless_pool_size = '13945824' %} +{% set egress_lossy_pool_size = '6822912' %} + +{% import 'buffers_defaults_objects.j2' as defs with context %} + +{%- macro generate_buffer_pool_and_profiles_with_inactive_ports(port_names_inactive) %} +{{ defs.generate_buffer_pool_and_profiles_with_inactive_ports(port_names_inactive) }} +{%- endmacro %} + +{%- macro generate_profile_lists_with_inactive_ports(port_names_active, port_names_inactive) %} +{{ defs.generate_profile_lists(port_names_active, port_names_inactive) }} +{%- endmacro %} + +{%- macro generate_queue_buffers_with_inactive_ports(port_names_active, port_names_inactive) %} +{{ defs.generate_queue_buffers(port_names_active, port_names_inactive) }} +{%- endmacro %} + +{%- macro generate_pg_profiles_with_inactive_ports(port_names_active, port_names_inactive) %} +{{ defs.generate_pg_profiles(port_names_active, port_names_inactive) }} +{%- endmacro %} diff --git a/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/buffers_defaults_t1.j2 b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/buffers_defaults_t1.j2 new file mode 100644 index 000000000000..18a57073f823 --- /dev/null +++ b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/buffers_defaults_t1.j2 @@ -0,0 +1,36 @@ +{# + Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. + Apache-2.0 + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + http://www.apache.org/licenses/LICENSE-2.0 + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +#} +{% set default_cable = '300m' %} +{% set ingress_lossless_pool_size = '6282240' %} +{% set ingress_lossless_pool_xoff = '1540096' %} +{% set egress_lossless_pool_size = '13945824' %} +{% set egress_lossy_pool_size = '6282240' %} + +{% import 'buffers_defaults_objects.j2' as defs with context %} + +{%- macro generate_buffer_pool_and_profiles_with_inactive_ports(port_names_inactive) %} +{{ defs.generate_buffer_pool_and_profiles_with_inactive_ports(port_names_inactive) }} +{%- endmacro %} + +{%- macro generate_profile_lists_with_inactive_ports(port_names_active, port_names_inactive) %} +{{ defs.generate_profile_lists(port_names_active, port_names_inactive) }} +{%- endmacro %} + +{%- macro generate_queue_buffers_with_inactive_ports(port_names_active, port_names_inactive) %} +{{ defs.generate_queue_buffers(port_names_active, port_names_inactive) }} +{%- endmacro %} + +{%- macro generate_pg_profiles_with_inactive_ports(port_names_active, port_names_inactive) %} +{{ defs.generate_pg_profiles(port_names_active, port_names_inactive) }} +{%- endmacro %} diff --git a/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/buffers_dynamic.json.j2 b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/buffers_dynamic.json.j2 new file mode 100644 index 000000000000..cea77067d2a6 --- /dev/null +++ b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/buffers_dynamic.json.j2 @@ -0,0 +1,16 @@ +{# + Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. + Apache-2.0 + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + http://www.apache.org/licenses/LICENSE-2.0 + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +#} +{%- set default_topo = 't0' %} +{%- set dynamic_mode = 'true' %} +{%- include 'buffers_config.j2' %} diff --git a/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/hwsku.json b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/hwsku.json new file mode 100644 index 000000000000..b74b2d5ad570 --- /dev/null +++ b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/hwsku.json @@ -0,0 +1,166 @@ +{ + "interfaces": { + "Ethernet0": { + "default_brkout_mode": "1x100G[50G,40G,25G,10G]" + }, + "Ethernet4": { + "default_brkout_mode": "1x100G[50G,40G,25G,10G]" + }, + "Ethernet8": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet10": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet12": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet14": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet16": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet18": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet20": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet22": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet24": { + "default_brkout_mode": "1x100G[50G,40G,25G,10G]" + }, + "Ethernet28": { + "default_brkout_mode": "1x100G[50G,40G,25G,10G]" + }, + "Ethernet32": { + "default_brkout_mode": "1x100G[50G,40G,25G,10G]" + }, + "Ethernet36": { + "default_brkout_mode": "1x100G[50G,40G,25G,10G]" + }, + "Ethernet40": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet42": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet44": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet46": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet48": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet50": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet52": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet54": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet56": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet58": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet60": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet62": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet64": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet66": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet68": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet70": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet72": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet74": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet76": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet78": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet80": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet82": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet84": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet86": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet88": { + "default_brkout_mode": "1x100G[50G,40G,25G,10G]" + }, + "Ethernet92": { + "default_brkout_mode": "1x100G[50G,40G,25G,10G]" + }, + "Ethernet96": { + "default_brkout_mode": "1x100G[50G,40G,25G,10G]" + }, + "Ethernet100": { + "default_brkout_mode": "1x100G[50G,40G,25G,10G]" + }, + "Ethernet104": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet106": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet108": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet110": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet112": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet114": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet116": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet118": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet120": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet122": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet124": { + "default_brkout_mode": "2x50G[25G,10G]" + }, + "Ethernet126": { + "default_brkout_mode": "2x50G[25G,10G]" + } + } +} diff --git a/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/pg_profile_lookup.ini b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/pg_profile_lookup.ini new file mode 120000 index 000000000000..b1f8524ff2e5 --- /dev/null +++ b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/pg_profile_lookup.ini @@ -0,0 +1 @@ +../Mellanox-SN2700-D40C8S8/pg_profile_lookup.ini \ No newline at end of file diff --git a/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/port_config.ini b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/port_config.ini new file mode 100644 index 000000000000..1320b267d8c4 --- /dev/null +++ b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/port_config.ini @@ -0,0 +1,55 @@ +# name lanes alias index speed +Ethernet0 0,1,2,3 etp1 1 100000 +Ethernet4 4,5,6,7 etp2 2 100000 +Ethernet8 8,9 etp3a 3 50000 +Ethernet10 10,11 etp3b 3 50000 +Ethernet12 12,13 etp4a 4 50000 +Ethernet14 14,15 etp4b 4 50000 +Ethernet16 16,17 etp5a 5 50000 +Ethernet18 18,19 etp5b 5 50000 +Ethernet20 20,21 etp6a 6 50000 +Ethernet22 22,23 etp6b 6 50000 +Ethernet24 24,25,26,27 etp7 7 100000 +Ethernet28 28,29,30,31 etp8 8 100000 +Ethernet32 32,33,34,35 etp9 9 100000 +Ethernet36 36,37,38,39 etp10 10 100000 +Ethernet40 40,41 etp11a 11 50000 +Ethernet42 42,43 etp11b 11 50000 +Ethernet44 44,45 etp12a 12 50000 +Ethernet46 46,47 etp12b 12 50000 +Ethernet48 48,49 etp13a 13 50000 +Ethernet50 50,51 etp13b 13 50000 +Ethernet52 52,53 etp14a 14 50000 +Ethernet54 54,55 etp14b 14 50000 +Ethernet56 56,57 etp15a 15 50000 +Ethernet58 58,59 etp15b 15 50000 +Ethernet60 60,61 etp16a 16 50000 +Ethernet62 62,63 etp16b 16 50000 +Ethernet64 64,65 etp17a 17 50000 +Ethernet66 66,67 etp17b 17 50000 +Ethernet68 68,69 etp18a 18 50000 +Ethernet70 70,71 etp18b 18 50000 +Ethernet72 72,73 etp19a 19 50000 +Ethernet74 74,75 etp19b 19 50000 +Ethernet76 76,77 etp20a 20 50000 +Ethernet78 78,79 etp20b 20 50000 +Ethernet80 80,81 etp21a 21 50000 +Ethernet82 82,83 etp21b 21 50000 +Ethernet84 84,85 etp22a 22 50000 +Ethernet86 86,87 etp22b 22 50000 +Ethernet88 88,89,90,91 etp23 23 100000 +Ethernet92 92,93,94,95 etp24 24 100000 +Ethernet96 96,97,98,99 etp25 25 100000 +Ethernet100 100,101,102,103 etp26 26 100000 +Ethernet104 104,105 etp27a 27 50000 +Ethernet106 106,107 etp27b 27 50000 +Ethernet108 108,109 etp28a 28 50000 +Ethernet110 110,111 etp28b 28 50000 +Ethernet112 112,113 etp29a 29 50000 +Ethernet114 114,115 etp29b 29 50000 +Ethernet116 116,117 etp30a 30 50000 +Ethernet118 118,119 etp30b 30 50000 +Ethernet120 120,121 etp31a 31 50000 +Ethernet122 122,123 etp31b 31 50000 +Ethernet124 124,125 etp32a 32 50000 +Ethernet126 126,127 etp32b 32 50000 diff --git a/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/qos.json.j2 b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/qos.json.j2 new file mode 120000 index 000000000000..8bd2d26567b8 --- /dev/null +++ b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/qos.json.j2 @@ -0,0 +1 @@ +../ACS-MSN2700/qos.json.j2 \ No newline at end of file diff --git a/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/sai.profile b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/sai.profile new file mode 100644 index 000000000000..f25a70d39743 --- /dev/null +++ b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/sai.profile @@ -0,0 +1,3 @@ +SAI_INIT_CONFIG_FILE=/usr/share/sonic/hwsku/sai_2700_44x50g_10x100g.xml +SAI_DUMP_STORE_PATH=/var/log/mellanox/sdk-dumps +SAI_DUMP_STORE_AMOUNT=10 diff --git a/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/sai_2700_44x50g_10x100g.xml b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/sai_2700_44x50g_10x100g.xml new file mode 100644 index 000000000000..c505f0c449e6 --- /dev/null +++ b/device/mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D44C10/sai_2700_44x50g_10x100g.xml @@ -0,0 +1,269 @@ + + + + + + 00:02:03:04:05:00 + + + 1 + + + 32 + + + + + 1 + 2 + 4 + 16 + + + 3 + + + 3221487616 + + + 3 + 2 + 4 + 17 + 1 + 3221487616 + + + 5 + 2 + 4 + 18 + 3 + 3221487616 + + + 7 + 2 + 4 + 19 + 1 + 3221487616 + + + 9 + 2 + 4 + 20 + 3 + 3221487616 + + + 11 + 2 + 4 + 21 + 1 + 3221487616 + + + 13 + 4 + 22 + 3 + 11534336 + + + 15 + 4 + 23 + 1 + 11534336 + + + 17 + 4 + 24 + 3 + 11534336 + + + 19 + 4 + 25 + 1 + 11534336 + + + 21 + 2 + 4 + 26 + 3 + 3221487616 + + + 23 + 2 + 4 + 27 + 1 + 3221487616 + + + 25 + 2 + 4 + 28 + 3 + 3221487616 + + + 27 + 2 + 4 + 29 + 1 + 3221487616 + + + 29 + 2 + 4 + 30 + 3 + 3221487616 + + + 31 + 2 + 4 + 31 + 1 + 3221487616 + + + 33 + 2 + 4 + 14 + 3 + 3221487616 + + + 35 + 2 + 4 + 15 + 1 + 3221487616 + + + 37 + 2 + 4 + 12 + 3 + 3221487616 + + + 39 + 2 + 4 + 13 + 1 + 3221487616 + + + 41 + 2 + 4 + 10 + 3 + 3221487616 + + + 43 + 2 + 4 + 11 + 1 + 3221487616 + + + 45 + 4 + 8 + 3 + 11534336 + + + 47 + 4 + 9 + 1 + 11534336 + + + 49 + 2 + 4 + 6 + 3 + 3221487616 + + + 51 + 4 + 7 + 1 + 11534336 + + + 53 + 2 + 4 + 4 + 3 + 3221487616 + + + 55 + 2 + 4 + 5 + 1 + 3221487616 + + + 57 + 2 + 4 + 2 + 3 + 3221487616 + + + 59 + 2 + 4 + 3 + 1 + 3221487616 + + + 61 + 4 + 0 + 3 + 11534336 + + + 63 + 4 + 1 + 1 + 11534336 + + + + From 8930d70972a7a2439f85093869f3068c0aaa5646 Mon Sep 17 00:00:00 2001 From: cytsao1 <111393130+cytsao1@users.noreply.github.com> Date: Mon, 17 Oct 2022 13:26:31 -0700 Subject: [PATCH 15/35] [pmon] Add smartmontools to pmon docker (#11837) * Add smartmontools to pmon docker * Set smartmontools to install version 7.2-1 in pmon to match host; clean up smartmontools build files * Add comments on smartmontools version for both host and pmon --- dockers/docker-platform-monitor/Dockerfile.j2 | 4 +++- files/build_templates/sonic_debian_extension.j2 | 2 +- rules/smartmontools.dep | 10 ---------- rules/smartmontools.mk | 12 ------------ 4 files changed, 4 insertions(+), 24 deletions(-) delete mode 100644 rules/smartmontools.dep delete mode 100644 rules/smartmontools.mk diff --git a/dockers/docker-platform-monitor/Dockerfile.j2 b/dockers/docker-platform-monitor/Dockerfile.j2 index 5c34246ca8be..51d944d170dd 100755 --- a/dockers/docker-platform-monitor/Dockerfile.j2 +++ b/dockers/docker-platform-monitor/Dockerfile.j2 @@ -26,7 +26,9 @@ RUN apt-get update && \ psmisc \ python3-jsonschema \ libpci3 \ - iputils-ping + iputils-ping \ +# smartmontools version should match the installed smartmontools in sonic_debian_extension build template + smartmontools=7.2-1 # On Arista devices, the sonic_platform wheel is not installed in the container. # Instead, the installation directory is mounted from the host OS. However, this method diff --git a/files/build_templates/sonic_debian_extension.j2 b/files/build_templates/sonic_debian_extension.j2 index 736eaa52008e..e3219413209a 100644 --- a/files/build_templates/sonic_debian_extension.j2 +++ b/files/build_templates/sonic_debian_extension.j2 @@ -336,7 +336,7 @@ sudo chmod 755 $FILESYSTEM_ROOT/usr/bin/memory_checker sudo cp $IMAGE_CONFIGS/monit/restart_service $FILESYSTEM_ROOT/usr/bin/ sudo chmod 755 $FILESYSTEM_ROOT/usr/bin/restart_service -# Install custom-built smartmontools +# Installed smartmontools version should match installed smartmontools in docker-platform-monitor Dockerfile sudo LANG=C DEBIAN_FRONTEND=noninteractive chroot $FILESYSTEM_ROOT apt-get -y install smartmontools=7.2-1 # Install custom-built openssh sshd diff --git a/rules/smartmontools.dep b/rules/smartmontools.dep deleted file mode 100644 index 0ca63f5f1fac..000000000000 --- a/rules/smartmontools.dep +++ /dev/null @@ -1,10 +0,0 @@ - -SPATH := $($(SMARTMONTOOLS)_SRC_PATH) -DEP_FILES := $(SONIC_COMMON_FILES_LIST) rules/smartmontools.mk rules/smartmontools.dep -DEP_FILES += $(SONIC_COMMON_BASE_FILES_LIST) -DEP_FILES += $(shell git ls-files $(SPATH)) - -$(SMARTMONTOOLS)_CACHE_MODE := GIT_CONTENT_SHA -$(SMARTMONTOOLS)_DEP_FLAGS := $(SONIC_COMMON_FLAGS_LIST) -$(SMARTMONTOOLS)_DEP_FILES := $(DEP_FILES) - diff --git a/rules/smartmontools.mk b/rules/smartmontools.mk deleted file mode 100644 index 7cc61eee6feb..000000000000 --- a/rules/smartmontools.mk +++ /dev/null @@ -1,12 +0,0 @@ -# smartmontools package -# - -SMARTMONTOOLS_VERSION_MAJOR = 6.6 -SMARTMONTOOLS_VERSION_FULL = $(SMARTMONTOOLS_VERSION_MAJOR)-1 - -export SMARTMONTOOLS_VERSION_MAJOR SMARTMONTOOLS_VERSION_FULL - -SMARTMONTOOLS = smartmontools_$(SMARTMONTOOLS_VERSION_FULL)_$(CONFIGURED_ARCH).deb -$(SMARTMONTOOLS)_SRC_PATH = $(SRC_PATH)/smartmontools - -SONIC_MAKE_DEBS += $(SMARTMONTOOLS) From 834724fa874ee9177eb86057da06690e3fc55d88 Mon Sep 17 00:00:00 2001 From: kellyyeh <42761586+kellyyeh@users.noreply.github.com> Date: Wed, 19 Oct 2022 14:18:43 -0700 Subject: [PATCH 16/35] Advance dhcprelay submodule head (#12214) --- src/dhcprelay | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/dhcprelay b/src/dhcprelay index 6f94c2ededb3..9c3b73837f76 160000 --- a/src/dhcprelay +++ b/src/dhcprelay @@ -1 +1 @@ -Subproject commit 6f94c2ededb39ef4cdab788e295a041b2aec12b4 +Subproject commit 9c3b73837f768b3220d68ed01030d204c650d476 From 44d90f9d82874f891bc6593d95aa9f9ca8205a3e Mon Sep 17 00:00:00 2001 From: andywongarista <78833093+andywongarista@users.noreply.github.com> Date: Thu, 20 Oct 2022 23:25:24 -0700 Subject: [PATCH 17/35] Fix sensord service install (#12376) Why I did it #4021 describes an issue that is still being observed on master image whereby sensord does not start in pmon due to missing service. How I did it Updated the lm-sensors install patch with a case for systemd How to verify it Verified that sensord is up in pmon after boot Co-authored-by: Boyang Yu --- ...dh_installinit-to-include-sensord.in.patch | 24 ++++++------------- 1 file changed, 7 insertions(+), 17 deletions(-) diff --git a/src/lm-sensors/patch/0002-Patch-to-peform-dh_installinit-to-include-sensord.in.patch b/src/lm-sensors/patch/0002-Patch-to-peform-dh_installinit-to-include-sensord.in.patch index 7bfdee11e3be..bb88f423f4e4 100644 --- a/src/lm-sensors/patch/0002-Patch-to-peform-dh_installinit-to-include-sensord.in.patch +++ b/src/lm-sensors/patch/0002-Patch-to-peform-dh_installinit-to-include-sensord.in.patch @@ -1,23 +1,13 @@ -From b11fd3d516b62c01513d289bc901820aa150c63e Mon Sep 17 00:00:00 2001 -From: Charlie Chen -Date: Wed, 1 Apr 2020 06:59:06 +0000 -Subject: Patch to peform dh_installinit to include sensord.install in the - packed deb - -Signed-off-by: Charlie Chen ---- - debian/rules | 1 + - 1 file changed, 1 insertion(+) - diff --git a/debian/rules b/debian/rules -index 5ebda06..1d77e28 100755 +index 3cd5314..1dd0983 100755 --- a/debian/rules +++ b/debian/rules -@@ -56,3 +56,4 @@ override_dh_auto_install-arch: - +@@ -66,6 +66,8 @@ override_dh_auto_install-arch: + override_dh_installinit-arch: dh_installinit -plm-sensors --no-start + dh_installinit -psensord --no-start --- -2.17.1 - + + override_dh_installsystemd-arch: + dh_installsystemd -plm-sensors --no-start ++ dh_installsystemd -psensord --no-start From 89ac469d6223d004481faee0994ffc984fce4d79 Mon Sep 17 00:00:00 2001 From: vmittal-msft <46945843+vmittal-msft@users.noreply.github.com> Date: Tue, 18 Oct 2022 10:13:07 -0700 Subject: [PATCH 18/35] Updated config files to disable DLR_INIT capability (#12401) --- .../Arista-7800R3-48CQ2-C48/jr2-a7280cr3-32d4-40x100G.config.bcm | 1 + .../0/j2p-a7800r3a-36d-36x400G.config.bcm | 1 + .../1/j2p-a7800r3a-36d-36x400G.config.bcm | 1 + .../0/jr2cp-nokia-18x100g-4x25g-config.bcm | 1 + .../1/jr2cp-nokia-18x100g-4x25g-config.bcm | 1 + .../Nokia-IXR7250E-36x400G/0/jr2cp-nokia-18x400g-config.bcm | 1 + .../Nokia-IXR7250E-36x400G/1/jr2cp-nokia-18x400g-config.bcm | 1 + 7 files changed, 7 insertions(+) diff --git a/device/arista/x86_64-arista_7800r3_48cq2_lc/Arista-7800R3-48CQ2-C48/jr2-a7280cr3-32d4-40x100G.config.bcm b/device/arista/x86_64-arista_7800r3_48cq2_lc/Arista-7800R3-48CQ2-C48/jr2-a7280cr3-32d4-40x100G.config.bcm index f20ea81049fb..3db7f3a5147b 100644 --- a/device/arista/x86_64-arista_7800r3_48cq2_lc/Arista-7800R3-48CQ2-C48/jr2-a7280cr3-32d4-40x100G.config.bcm +++ b/device/arista/x86_64-arista_7800r3_48cq2_lc/Arista-7800R3-48CQ2-C48/jr2-a7280cr3-32d4-40x100G.config.bcm @@ -793,3 +793,4 @@ dma_desc_aggregator_buff_size_kb.BCM8869X=100 dma_desc_aggregator_timeout_usec.BCM8869X=1000 dma_desc_aggregator_enable_specific_MDB_LPM.BCM8869X=1 dma_desc_aggregator_enable_specific_MDB_FEC.BCM8869X=1 +sai_pfc_dlr_init_capability=0 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/0/j2p-a7800r3a-36d-36x400G.config.bcm b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/0/j2p-a7800r3a-36d-36x400G.config.bcm index e32603e1da0c..99dfb9e3e264 100644 --- a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/0/j2p-a7800r3a-36d-36x400G.config.bcm +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/0/j2p-a7800r3a-36d-36x400G.config.bcm @@ -1001,3 +1001,4 @@ serdes_tx_taps_36=nrz:-8:89:-29:0:0:0 xflow_macsec_secure_chan_to_num_secure_assoc_encrypt=2 xflow_macsec_secure_chan_to_num_secure_assoc_decrypt=4 +sai_pfc_dlr_init_capability=0 diff --git a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/1/j2p-a7800r3a-36d-36x400G.config.bcm b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/1/j2p-a7800r3a-36d-36x400G.config.bcm index c2a1d4229f24..bccc2d5be9f1 100644 --- a/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/1/j2p-a7800r3a-36d-36x400G.config.bcm +++ b/device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C72/1/j2p-a7800r3a-36d-36x400G.config.bcm @@ -1000,3 +1000,4 @@ serdes_tx_taps_36=nrz:-7:85:-25:0:0:0 xflow_macsec_secure_chan_to_num_secure_assoc_encrypt=2 xflow_macsec_secure_chan_to_num_secure_assoc_decrypt=4 +sai_pfc_dlr_init_capability=0 diff --git a/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x100G/0/jr2cp-nokia-18x100g-4x25g-config.bcm b/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x100G/0/jr2cp-nokia-18x100g-4x25g-config.bcm index 3eb3ba20a424..856d429a7e6e 100644 --- a/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x100G/0/jr2cp-nokia-18x100g-4x25g-config.bcm +++ b/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x100G/0/jr2cp-nokia-18x100g-4x25g-config.bcm @@ -2092,3 +2092,4 @@ modreg IPS_FORCE_LOCAL_OR_FABRIC FORCE_FABRIC=1 xflow_macsec_secure_chan_to_num_secure_assoc_encrypt=2 xflow_macsec_secure_chan_to_num_secure_assoc_decrypt=4 cmic_dma_abort_in_cold_boot=0 +sai_pfc_dlr_init_capability=0 diff --git a/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x100G/1/jr2cp-nokia-18x100g-4x25g-config.bcm b/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x100G/1/jr2cp-nokia-18x100g-4x25g-config.bcm index 57e966b35315..0d1b3972a5cf 100644 --- a/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x100G/1/jr2cp-nokia-18x100g-4x25g-config.bcm +++ b/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x100G/1/jr2cp-nokia-18x100g-4x25g-config.bcm @@ -2093,3 +2093,4 @@ modreg IPS_FORCE_LOCAL_OR_FABRIC FORCE_FABRIC=1 xflow_macsec_secure_chan_to_num_secure_assoc_encrypt=2 xflow_macsec_secure_chan_to_num_secure_assoc_decrypt=4 cmic_dma_abort_in_cold_boot=0 +sai_pfc_dlr_init_capability=0 diff --git a/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x400G/0/jr2cp-nokia-18x400g-config.bcm b/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x400G/0/jr2cp-nokia-18x400g-config.bcm index 1da65733155a..32fe9ef43709 100644 --- a/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x400G/0/jr2cp-nokia-18x400g-config.bcm +++ b/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x400G/0/jr2cp-nokia-18x400g-config.bcm @@ -2093,3 +2093,4 @@ modreg IPS_FORCE_LOCAL_OR_FABRIC FORCE_FABRIC=1 xflow_macsec_secure_chan_to_num_secure_assoc_encrypt=2 xflow_macsec_secure_chan_to_num_secure_assoc_decrypt=4 cmic_dma_abort_in_cold_boot=0 +sai_pfc_dlr_init_capability=0 diff --git a/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x400G/1/jr2cp-nokia-18x400g-config.bcm b/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x400G/1/jr2cp-nokia-18x400g-config.bcm index 4d6790d5398b..8dec8b48477e 100644 --- a/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x400G/1/jr2cp-nokia-18x400g-config.bcm +++ b/device/nokia/x86_64-nokia_ixr7250e_36x400g-r0/Nokia-IXR7250E-36x400G/1/jr2cp-nokia-18x400g-config.bcm @@ -2095,3 +2095,4 @@ modreg IPS_FORCE_LOCAL_OR_FABRIC FORCE_FABRIC=1 xflow_macsec_secure_chan_to_num_secure_assoc_encrypt=2 xflow_macsec_secure_chan_to_num_secure_assoc_decrypt=4 cmic_dma_abort_in_cold_boot=0 +sai_pfc_dlr_init_capability=0 From d40cd51d7216fd6dc94b903de4a0c938e37afbf6 Mon Sep 17 00:00:00 2001 From: Ying Xie Date: Sun, 16 Oct 2022 09:37:45 -0700 Subject: [PATCH 19/35] [FRR] import FRR patch: zebra: Note when the netlink DUMP command is interrupted (#12412) Why I did it There is an outstanding FRR issue #12380. This seems to be a known issue but without good fix so far. The root cause is around zebra and kernel netlink interaction. The failure was previously not noticed by zebra. How I did it Port the patch that would make the issue obvious. Signed-off-by: Ying Xie ying.xie@microsoft.com --- ...the-netlink-DUMP-command-is-interrup.patch | 45 +++++++++++++++++++ src/sonic-frr/patch/series | 1 + 2 files changed, 46 insertions(+) create mode 100644 src/sonic-frr/patch/0010-zebra-Note-when-the-netlink-DUMP-command-is-interrup.patch diff --git a/src/sonic-frr/patch/0010-zebra-Note-when-the-netlink-DUMP-command-is-interrup.patch b/src/sonic-frr/patch/0010-zebra-Note-when-the-netlink-DUMP-command-is-interrup.patch new file mode 100644 index 000000000000..3da1ab318d1c --- /dev/null +++ b/src/sonic-frr/patch/0010-zebra-Note-when-the-netlink-DUMP-command-is-interrup.patch @@ -0,0 +1,45 @@ +From 8f10590a85669f300d2706d5ef1e560cdbaaf0f8 Mon Sep 17 00:00:00 2001 +From: Donald Sharp +Date: Fri, 25 Mar 2022 19:08:14 -0400 +Subject: [PATCH 10/10] zebra: Note when the netlink DUMP command is + interrupted + +There exists code paths in the linux kernel where a dump command +will be interrupted( I am not sure I understand what this really +means ) and the data sent back from the kernel is wrong or incomplete. + +At this point in time I am not 100% certain what should be done, but +let's start noticing that this has happened so we can formulate a plan +or allow the end operator to know bad stuff is a foot at the circle K. + +Signed-off-by: Donald Sharp +--- + zebra/kernel_netlink.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/zebra/kernel_netlink.c b/zebra/kernel_netlink.c +index ccafc8f0c..9dc597fad 100644 +--- a/zebra/kernel_netlink.c ++++ b/zebra/kernel_netlink.c +@@ -972,6 +972,18 @@ int netlink_parse_info(int (*filter)(struct nlmsghdr *, ns_id_t, int), + return err; + } + ++ /* ++ * What is the right thing to do? The kernel ++ * is telling us that the dump request was interrupted ++ * and we more than likely are out of luck and have ++ * missed data from the kernel. At this point in time ++ * lets just note that this is happening. ++ */ ++ if (h->nlmsg_flags & NLM_F_DUMP_INTR) ++ flog_err( ++ EC_ZEBRA_NETLINK_BAD_SEQUENCE, ++ "netlink recvmsg: The Dump request was interrupted"); ++ + /* OK we got netlink message. */ + if (IS_ZEBRA_DEBUG_KERNEL) + zlog_debug( +-- +2.17.1 + diff --git a/src/sonic-frr/patch/series b/src/sonic-frr/patch/series index feaef719a0cd..3b762ee8f97c 100644 --- a/src/sonic-frr/patch/series +++ b/src/sonic-frr/patch/series @@ -8,3 +8,4 @@ 0008-Link-local-scope-was-not-set-while-binding-socket-for-bgp-ipv6-link-local-neighbors.patch Disable-ipv6-src-address-test-in-pceplib.patch 0009-ignore-route-from-default-table.patch +0010-zebra-Note-when-the-netlink-DUMP-command-is-interrup.patch From 93fbfbbf1fc716f32f79d9013cf5bce606fd5c81 Mon Sep 17 00:00:00 2001 From: vmittal-msft <46945843+vmittal-msft@users.noreply.github.com> Date: Mon, 17 Oct 2022 15:22:53 -0700 Subject: [PATCH 20/35] Updated BRCM SAI to version 7.1.10.4 (#12423) --- platform/broadcom/sai.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/platform/broadcom/sai.mk b/platform/broadcom/sai.mk index 6de969a662bc..ab8d47148b03 100644 --- a/platform/broadcom/sai.mk +++ b/platform/broadcom/sai.mk @@ -1,5 +1,5 @@ -LIBSAIBCM_XGS_VERSION = 7.1.7.2 -LIBSAIBCM_DNX_VERSION = 7.1.7.2 +LIBSAIBCM_XGS_VERSION = 7.1.10.4 +LIBSAIBCM_DNX_VERSION = 7.1.10.4 LIBSAIBCM_BRANCH_NAME = REL_7.0 LIBSAIBCM_XGS_URL_PREFIX = "https://sonicstorage.blob.core.windows.net/public/sai/bcmsai/$(LIBSAIBCM_BRANCH_NAME)/$(LIBSAIBCM_XGS_VERSION)" LIBSAIBCM_DNX_URL_PREFIX = "https://sonicstorage.blob.core.windows.net/public/sai/bcmsai/$(LIBSAIBCM_BRANCH_NAME)/$(LIBSAIBCM_DNX_VERSION)" From 94c8107f5e34424efe7de8e9c8eed49f545318f4 Mon Sep 17 00:00:00 2001 From: Samuel Angebault Date: Sat, 22 Oct 2022 03:27:32 +0200 Subject: [PATCH 21/35] Fix extraction of platform.tar.gz for firsttime (#11935) --- files/Aboot/boot0.j2 | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/files/Aboot/boot0.j2 b/files/Aboot/boot0.j2 index 48e29aaf33be..a2a1b82b32f7 100644 --- a/files/Aboot/boot0.j2 +++ b/files/Aboot/boot0.j2 @@ -401,9 +401,14 @@ extract_image() { extract_image_secureboot() { info "Extracting necessary swi content" # NOTE: boot/ is not used by the boot process but only extracted for kdump - unzip -oq "$swipath" 'boot/*' platform/firsttime .imagehash -d "$image_path" + unzip -oq "$swipath" 'boot/*' .imagehash -d "$image_path" - info "Installing image as $installer_image_path" + ## Extract platform.tar.gz + info "Extracting platform.tar.gz" + mkdir -p "$image_path/platform" + unzip -oqp "$swipath" "platform.tar.gz" | tar xzf - -C "$image_path/platform" $TAR_EXTRA_OPTION + + info "Installing swi under $installer_image_path" mv "$swipath" "$installer_image_path" chmod a+r "$installer_image_path" swipath="$installer_image_path" From 8a7200090943655f934b9f67df699b2fecb70964 Mon Sep 17 00:00:00 2001 From: Liu Shilong Date: Tue, 25 Oct 2022 16:34:07 +0800 Subject: [PATCH 22/35] [action] Use github code scan instead of LGTM. (#12402) * [action] Add code scan for python --- .github/codeql/codeql-config.yml | 4 +++ .github/workflows/codeql-analysis.yml | 43 +++++++++++++++++++++++++++ 2 files changed, 47 insertions(+) create mode 100644 .github/codeql/codeql-config.yml create mode 100644 .github/workflows/codeql-analysis.yml diff --git a/.github/codeql/codeql-config.yml b/.github/codeql/codeql-config.yml new file mode 100644 index 000000000000..2c8b0498f319 --- /dev/null +++ b/.github/codeql/codeql-config.yml @@ -0,0 +1,4 @@ +name: "CodeQL config" +queries: + - uses: security-and-quality + - uses: security-extended diff --git a/.github/workflows/codeql-analysis.yml b/.github/workflows/codeql-analysis.yml new file mode 100644 index 000000000000..0a8f2dc58682 --- /dev/null +++ b/.github/workflows/codeql-analysis.yml @@ -0,0 +1,43 @@ +# For more infomation, please visit: https://github.com/github/codeql-action + +name: "CodeQL" + +on: + push: + branches: + - 'master' + - '202[0-9][0-9][0-9]' + pull_request: + branches: + - 'master' + - '202[0-9][0-9][0-9]' + +jobs: + analyze: + name: Analyze + runs-on: ubuntu-latest + permissions: + actions: read + contents: read + security-events: write + + strategy: + fail-fast: false + matrix: + language: [ 'python' ] + + steps: + - name: Checkout repository + uses: actions/checkout@v3 + + # Initializes the CodeQL tools for scanning. + - name: Initialize CodeQL + uses: github/codeql-action/init@v2 + with: + config-file: ./.github/codeql/codeql-config.yml + languages: ${{ matrix.language }} + + - name: Perform CodeQL Analysis + uses: github/codeql-action/analyze@v2 + with: + category: "/language:${{matrix.language}}" From d9768be4757f2e77991e911bd78146c09652a01b Mon Sep 17 00:00:00 2001 From: Lawrence Lee Date: Thu, 20 Oct 2022 09:29:57 -0700 Subject: [PATCH 23/35] [tunnel_pkt_handler]: Skip nonexistent intfs (#12424) - Skip the interface status check if the interface does not exist. In the future, when the interface is created/comes up this check will be triggered again. Signed-off-by: Lawrence Lee --- dockers/docker-orchagent/tunnel_packet_handler.py | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/dockers/docker-orchagent/tunnel_packet_handler.py b/dockers/docker-orchagent/tunnel_packet_handler.py index 3d75fdd94a0c..44dbb19fda65 100755 --- a/dockers/docker-orchagent/tunnel_packet_handler.py +++ b/dockers/docker-orchagent/tunnel_packet_handler.py @@ -16,6 +16,7 @@ from sonic_py_common import logger as log from pyroute2 import IPRoute +from pyroute2.netlink.exceptions import NetlinkError from scapy.layers.inet import IP from scapy.layers.inet6 import IPv6 from scapy.sendrecv import AsyncSniffer @@ -115,7 +116,14 @@ def get_up_portchannels(self): portchannel_intf_names = [name for name, _ in self.portchannel_intfs] link_statuses = [] for intf in portchannel_intf_names: - status = self.netlink_api.link("get", ifname=intf) + try: + status = self.netlink_api.link("get", ifname=intf) + except NetlinkError: + # Continue if we find a non-existent interface since we don't + # need to listen on it while it's down/not created. Once it comes up, + # we will get another netlink message which will trigger this check again + logger.log_notice("Skipping non-existent interface {}".format(intf)) + continue link_statuses.append(status[0]) up_portchannels = [] From e91e38810a02a8f0614c5ec4c843dcc341a3bebf Mon Sep 17 00:00:00 2001 From: Ye Jianquan Date: Wed, 19 Oct 2022 12:26:50 +0800 Subject: [PATCH 24/35] Enable to cancel pipeline jobs during checkout code and tests (#12436) co-authorized by: jianquanye@microsoft.com Why I did it Now, checkout code step and KVM test job can't be cancelled even though the whole build is cancelled. That's because by using Azure Pipeline Conditions, we customized the running condition, and we need to react to the Cancel action explicitly by asserting 'succeeded' https://learn.microsoft.com/en-us/azure/devops/pipelines/process/expressions?view=azure-devops#succeeded https://learn.microsoft.com/en-us/azure/devops/pipelines/process/conditions?view=azure-devops&tabs=yaml#ive-got-a-conditional-step-that-runs-even-when-a-job-is-canceled-how-do-i-manage-to-cancel-all-jobs-at-once How I did it Assert 'succeeded' condition explicitly. How to verify it Verified by cancelling and rerunning the azure pipeline. --- .azure-pipelines/azure-pipelines-image-template.yml | 2 +- azure-pipelines.yml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.azure-pipelines/azure-pipelines-image-template.yml b/.azure-pipelines/azure-pipelines-image-template.yml index 6a9c2790572f..f055414e137d 100644 --- a/.azure-pipelines/azure-pipelines-image-template.yml +++ b/.azure-pipelines/azure-pipelines-image-template.yml @@ -36,7 +36,7 @@ jobs: displayName: "Set cache options" - checkout: self submodules: recursive - condition: eq(variables.SKIP_CHECKOUT, '') + condition: and(succeeded(), eq(variables.SKIP_CHECKOUT, '')) displayName: 'Checkout code' - script: | BRANCH_NAME=$(Build.SourceBranchName) diff --git a/azure-pipelines.yml b/azure-pipelines.yml index be4478aaf4c4..0f97ba3ec17c 100644 --- a/azure-pipelines.yml +++ b/azure-pipelines.yml @@ -77,7 +77,7 @@ stages: - stage: Test dependsOn: BuildVS - condition: and(ne(stageDependencies.BuildVS.outputs['vs.SetVar.SKIP_VSTEST'], 'YES'), in(dependencies.BuildVS.result, 'Succeeded', 'SucceededWithIssues')) + condition: and(succeeded(), and(ne(stageDependencies.BuildVS.outputs['vs.SetVar.SKIP_VSTEST'], 'YES'), in(dependencies.BuildVS.result, 'Succeeded', 'SucceededWithIssues'))) variables: - group: Testbed-Tools - name: inventory From 5dcfab999c65fe7a4df2d207326898ff61c69446 Mon Sep 17 00:00:00 2001 From: Sudharsan Dhamal Gopalarathnam Date: Wed, 19 Oct 2022 23:50:53 -0700 Subject: [PATCH 25/35] [FRR]Adding patch to fix enhanced capability turned on for interface (#12453) Fixing issue FRRouting/frr#11108 For interface based peers with peer-groups, "no neighbor capability extended-nexthop" gets added by default. This will result in IPv4 routes not having ipv6 next hops. - How I did it Porting the commit FRRouting/frr@8e89adc to FRR 8.2.2 which fixes the issue - How to verify it Load FRR and verify if the "no neighbor capability extended-nexthop" not gets added for interfaces associated with peer-groups --- ...pability-is-always-turned-on-for-int.patch | 36 +++++++++++++++++++ src/sonic-frr/patch/series | 1 + 2 files changed, 37 insertions(+) create mode 100644 src/sonic-frr/patch/0011-bgpd-enhanced-capability-is-always-turned-on-for-int.patch diff --git a/src/sonic-frr/patch/0011-bgpd-enhanced-capability-is-always-turned-on-for-int.patch b/src/sonic-frr/patch/0011-bgpd-enhanced-capability-is-always-turned-on-for-int.patch new file mode 100644 index 000000000000..cefa7c31449f --- /dev/null +++ b/src/sonic-frr/patch/0011-bgpd-enhanced-capability-is-always-turned-on-for-int.patch @@ -0,0 +1,36 @@ +From 4db4fc1bf0599f79067bfd62aa435be8e161d81e Mon Sep 17 00:00:00 2001 +From: Donald Sharp +Date: Tue, 3 May 2022 12:51:21 -0400 +Subject: [PATCH] bgpd: enhanced capability is always turned on for interface + based peers + +FRR is displaying that the peer enhanced capability command is not +turned on when the interface is part of a peer group. Saving the +config and then reloading actually turns it off. + +Fix the code so that FRR does not display the enhanced capability +for interface based peers. + +Fixes: #11108 +Signed-off-by: Donald Sharp +--- + bgpd/bgp_vty.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/bgpd/bgp_vty.c b/bgpd/bgp_vty.c +index 4df2abef8..6fcce239b 100644 +--- a/bgpd/bgp_vty.c ++++ b/bgpd/bgp_vty.c +@@ -16586,7 +16586,8 @@ static void bgp_config_write_peer_global(struct vty *vty, struct bgp *bgp, + + /* capability extended-nexthop */ + if (peergroup_flag_check(peer, PEER_FLAG_CAPABILITY_ENHE)) { +- if (CHECK_FLAG(peer->flags_invert, PEER_FLAG_CAPABILITY_ENHE)) ++ if (CHECK_FLAG(peer->flags_invert, PEER_FLAG_CAPABILITY_ENHE) && ++ !peer->conf_if) + vty_out(vty, + " no neighbor %s capability extended-nexthop\n", + addr); +-- +2.17.1 + diff --git a/src/sonic-frr/patch/series b/src/sonic-frr/patch/series index 3b762ee8f97c..5dd4e5a1fe71 100644 --- a/src/sonic-frr/patch/series +++ b/src/sonic-frr/patch/series @@ -9,3 +9,4 @@ Disable-ipv6-src-address-test-in-pceplib.patch 0009-ignore-route-from-default-table.patch 0010-zebra-Note-when-the-netlink-DUMP-command-is-interrup.patch +0011-bgpd-enhanced-capability-is-always-turned-on-for-int.patch From c001f2b916bf5f0b40498ed1db467bc806edc30a Mon Sep 17 00:00:00 2001 From: kellyyeh <42761586+kellyyeh@users.noreply.github.com> Date: Fri, 21 Oct 2022 10:33:10 -0700 Subject: [PATCH 26/35] Add dhcp6relay dualtor option (#12459) --- dockers/docker-dhcp-relay/dhcpv6-relay.agents.j2 | 3 +++ 1 file changed, 3 insertions(+) diff --git a/dockers/docker-dhcp-relay/dhcpv6-relay.agents.j2 b/dockers/docker-dhcp-relay/dhcpv6-relay.agents.j2 index cca0b1c4b21a..8f83e05efc7c 100644 --- a/dockers/docker-dhcp-relay/dhcpv6-relay.agents.j2 +++ b/dockers/docker-dhcp-relay/dhcpv6-relay.agents.j2 @@ -12,6 +12,9 @@ {% set _dummy = relay_for_ipv6.update({'flag': False}) %} [program:dhcp6relay] command=/usr/sbin/dhcp6relay +{#- Dual ToR Option #} +{% if 'subtype' in DEVICE_METADATA['localhost'] and DEVICE_METADATA['localhost']['subtype'] == 'DualToR' %} -d{% endif %} + priority=3 autostart=false autorestart=false From c84799418efa059f72bac969f8f126853d94506e Mon Sep 17 00:00:00 2001 From: xumia <59720581+xumia@users.noreply.github.com> Date: Tue, 25 Oct 2022 15:31:18 +0800 Subject: [PATCH 27/35] Add the original docker tag without username (#12472) Why I did it Add the original docker tag without username to support some of the docker file not changed build broken issue. The username suffix only required when the native build feature enabled, but if not enabled, the docker file not necessary to change, the build should be succeeded. It is to support cisco 202205 build. --- slave.mk | 3 +++ 1 file changed, 3 insertions(+) diff --git a/slave.mk b/slave.mk index 76274b21b39e..809045e14b1c 100644 --- a/slave.mk +++ b/slave.mk @@ -818,6 +818,7 @@ $(addprefix $(TARGET_PATH)/, $(SONIC_SIMPLE_DOCKER_IMAGES)) : $(TARGET_PATH)/%.g --label Tag=$(SONIC_IMAGE_VERSION) \ -f $(TARGET_DOCKERFILE)/Dockerfile.buildinfo \ -t $(DOCKER_IMAGE_REF) $($*.gz_PATH) $(LOG) + if [ x$(SONIC_CONFIG_USE_NATIVE_DOCKERD_FOR_BUILD) == x"y" ]; then docker tag $(DOCKER_IMAGE_REF) $*; fi scripts/collect_docker_version_files.sh $(DOCKER_IMAGE_REF) $(TARGET_PATH) $(call docker-image-save,$*,$@) # Clean up @@ -937,6 +938,7 @@ $(addprefix $(TARGET_PATH)/, $(DOCKER_IMAGES)) : $(TARGET_PATH)/%.gz : .platform --label Tag=$(SONIC_IMAGE_VERSION) \ $($(subst -,_,$(notdir $($*.gz_PATH)))_labels) \ -t $(DOCKER_IMAGE_REF) $($*.gz_PATH) $(LOG) + if [ x$(SONIC_CONFIG_USE_NATIVE_DOCKERD_FOR_BUILD) == x"y" ]; then docker tag $(DOCKER_IMAGE_REF) $*; fi scripts/collect_docker_version_files.sh $(DOCKER_IMAGE_REF) $(TARGET_PATH) $(call docker-image-save,$*,$@) # Clean up @@ -989,6 +991,7 @@ $(addprefix $(TARGET_PATH)/, $(DOCKER_DBG_IMAGES)) : $(TARGET_PATH)/%-$(DBG_IMAG --label Tag=$(SONIC_IMAGE_VERSION) \ --file $($*.gz_PATH)/Dockerfile-dbg \ -t $(DOCKER_DBG_IMAGE_REF) $($*.gz_PATH) $(LOG) + if [ x$(SONIC_CONFIG_USE_NATIVE_DOCKERD_FOR_BUILD) == x"y" ]; then docker tag $(DOCKER_IMAGE_REF) $*; fi scripts/collect_docker_version_files.sh $(DOCKER_DBG_IMAGE_REF) $(TARGET_PATH) $(call docker-image-save,$*-$(DBG_IMAGE_MARK),$@) # Clean up From 17c213a264d263b3a6fb84d017ea8e92926d7ad5 Mon Sep 17 00:00:00 2001 From: Devesh Pathak <54966909+devpatha@users.noreply.github.com> Date: Tue, 25 Oct 2022 14:51:02 -0700 Subject: [PATCH 28/35] Fix to improve hostname handling (#12064) * Fix to improve hostname handling If config_db.json is missing hostname entry, hostname-config.sh ends up deleting existing entry too and hostname changes to default 'localhost' * default hostname to 'sonic` if missing in config file --- files/image_config/hostname/hostname-config.sh | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/files/image_config/hostname/hostname-config.sh b/files/image_config/hostname/hostname-config.sh index e9f7fc122709..c2a4f1e546ce 100755 --- a/files/image_config/hostname/hostname-config.sh +++ b/files/image_config/hostname/hostname-config.sh @@ -3,6 +3,11 @@ CURRENT_HOSTNAME=`hostname` HOSTNAME=`sonic-cfggen -d -v DEVICE_METADATA[\'localhost\'][\'hostname\']` +if [ -z "$HOSTNAME" ] ; then + echo "Missing hostname in the config file, setting to default 'sonic'" + HOSTNAME='sonic' +fi + echo $HOSTNAME > /etc/hostname hostname -F /etc/hostname From 2cbe3bac10807bec3ff73147b04074f2c56c6e95 Mon Sep 17 00:00:00 2001 From: Ye Jianquan Date: Thu, 27 Oct 2022 08:14:26 +0800 Subject: [PATCH 29/35] [202205] use the pr_test_scripts.yaml from 202205 branch (#12505) Signed-off-by: jianquanye@microsoft.com Why I did it use the pr_test_scripts.yaml from sonic-mgmt's 202205 branch How I did it use the pr_test_scripts.yaml from sonic-mgmt's 202205 branch --- .azure-pipelines/run-test-scheduler-template.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.azure-pipelines/run-test-scheduler-template.yml b/.azure-pipelines/run-test-scheduler-template.yml index 9029c6aab622..963b9d5b59c5 100644 --- a/.azure-pipelines/run-test-scheduler-template.yml +++ b/.azure-pipelines/run-test-scheduler-template.yml @@ -33,8 +33,9 @@ parameters: steps: - script: | set -ex + # always use the test plan script from master branch. wget -O ./.azure-pipelines/test_plan.py https://raw.githubusercontent.com/sonic-net/sonic-mgmt/master/.azure-pipelines/test_plan.py - wget -O ./.azure-pipelines/pr_test_scripts.yaml https://raw.githubusercontent.com/sonic-net/sonic-mgmt/master/.azure-pipelines/pr_test_scripts.yaml + wget -O ./.azure-pipelines/pr_test_scripts.yaml https://raw.githubusercontent.com/sonic-net/sonic-mgmt/${{ parameters.MGMT_BRANCH }}/.azure-pipelines/pr_test_scripts.yaml displayName: Download TestbedV2 scripts - script: | From 3fa7f3b9e4b15b481961a237b6251bdc8bc2e278 Mon Sep 17 00:00:00 2001 From: Ying Xie Date: Wed, 26 Oct 2022 17:44:37 -0700 Subject: [PATCH 30/35] [202205][linkmgrd][utilities][swss][sairedis][platform-daemon][platform-common] advance submodule head (#12492) linkmgrd: * d7d6635 2022-10-21 | Fix link prober state event report twice issue (#149) (HEAD -> 202205) [Longxiang Lyu] * 0ef3296 2022-10-21 | [active-active] Add support to send/handle mux probe request (#147) [Longxiang Lyu] * a66fa34 2022-10-17 | [active-active] Fix config reload (#145) [Longxiang Lyu] * 7e1c820 2022-10-11 | [Active-Standby] avoid posting mux metrics event when receiving unsolicited mux state notification (#142) [Jing Zhang] * 237cfd2 2022-10-07 | [Active-Active] Update default route shutdown heartbeat logic (#141) [Jing Zhang] utilities: * 415d30e 2022-10-23 | [techsupport] Adding FRR EVPN dumps (#2442) (HEAD -> 202205) [Sudharsan Dhamal Gopalarathnam] * b3ffe45 2022-10-21 | [show][muxcable] add support for show mux firmware version all (#2441) [vdahiya12] * 7d68534 2022-10-19 | [app_ext] [auto-ts] Add available_mem_threshold option (#2423) [Vivek] * 52b9c16 2022-10-07 | [muxcable][config] add CLI support for mux mode detach (#2425) [Jing Zhang] * 14646ff 2022-10-10 | [show priority-group drop counters] Remove backup with cached PG drop counters after 'config reload' (#2386) [Andriy Yurkiv] * dffcc53 2022-10-11 | Add a subcommand to display a hexdump of transceiver EEPROM page (#2379) [mihirpat1] * 86175c2 2022-10-17 | [chassis]Add fabric counter cli commands (#1860) [Maxime Lorrillere] swss: * 6fe0afd 2022-10-25 | [portsorch] remove port OID from saiOidToAlias map on port deletion (#2483) (HEAD -> 202205, github/202205) [Stepan Blyshchak] * 7290d66 2022-10-07 | [vlanmgr] Disable `arp_evict_nocarrier` for vlan host intf (#2469) [Longxiang Lyu] * d074001 2022-10-05 | [chassis][voq]Collect counters for fabric links (#1944) [Maxime Lorrillere] * 3a0353a 2022-10-18 | [counters][202205] Improve performance by polling only configured ports buffer queue/pg counters (#2474) [Vadym Hlushko] * 2feb39d 2022-10-14 | [202205] [crm] Fix issue with continues EXCEEDED and CLEAR logs for ACL group/table counters (#2482) [Volodymyr Samotiy] sairedis: * 326b630 2022-10-21 | [gbsyncd] Add asic db prefix for channel NOTIFICATIONS (#1129) (HEAD -> 202205) [Junhua Zhai] platform-daemon: * 6dbda9b 2022-10-25 | [ycabled] fix no port/state returned by grpc server (#308) (HEAD -> 202205) [vdahiya12] * 3d1228a 2022-10-20 | Fix xcvrd to support 400G ZR optic (#293) [Bohan Yang] platform-common: * c04d710 2022-09-29 | Read CMIS data path state duration (#312) (HEAD -> 202205) [Bohan Yang] Signed-off-by: Ying Xie Signed-off-by: Ying Xie --- src/linkmgrd | 2 +- src/sonic-platform-common | 2 +- src/sonic-platform-daemons | 2 +- src/sonic-sairedis | 2 +- src/sonic-swss | 2 +- src/sonic-utilities | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/linkmgrd b/src/linkmgrd index a5ac7f6b310c..d7d6635b525e 160000 --- a/src/linkmgrd +++ b/src/linkmgrd @@ -1 +1 @@ -Subproject commit a5ac7f6b310cff7f4892349d10f98c3355dd66f4 +Subproject commit d7d6635b525eb4a9f4cb87075f0a2b60a9bdc20b diff --git a/src/sonic-platform-common b/src/sonic-platform-common index de1bd8e755e4..c04d71000129 160000 --- a/src/sonic-platform-common +++ b/src/sonic-platform-common @@ -1 +1 @@ -Subproject commit de1bd8e755e48fc9f99cb9460acdb5693ec87022 +Subproject commit c04d71000129abd611c87b6fc10876449501fc62 diff --git a/src/sonic-platform-daemons b/src/sonic-platform-daemons index 5b96170cb449..6dbda9b83a5a 160000 --- a/src/sonic-platform-daemons +++ b/src/sonic-platform-daemons @@ -1 +1 @@ -Subproject commit 5b96170cb4496d5b7335599ad96933c87f5ce16b +Subproject commit 6dbda9b83a5ae37194a241a09e88383f6592f906 diff --git a/src/sonic-sairedis b/src/sonic-sairedis index 80928dd7331e..326b630691a3 160000 --- a/src/sonic-sairedis +++ b/src/sonic-sairedis @@ -1 +1 @@ -Subproject commit 80928dd7331ee97cb287e5bc88606c329bf96636 +Subproject commit 326b630691a3cec01d26954783d8b8336b7d53d4 diff --git a/src/sonic-swss b/src/sonic-swss index 9d9f39522313..6fe0afdd3fa4 160000 --- a/src/sonic-swss +++ b/src/sonic-swss @@ -1 +1 @@ -Subproject commit 9d9f395223132906317e6e45e3dbace8291ecb1f +Subproject commit 6fe0afdd3fa41f5846be464a4382d7a779142d50 diff --git a/src/sonic-utilities b/src/sonic-utilities index ab21b5888092..415d30e06c80 160000 --- a/src/sonic-utilities +++ b/src/sonic-utilities @@ -1 +1 @@ -Subproject commit ab21b58880927a289380798bc73bf844816a7d36 +Subproject commit 415d30e06c80d8fdf9f55c06c4733922d645435c From 0b9a11da562d261f9bab7fab3c13d85d7d0b1631 Mon Sep 17 00:00:00 2001 From: Hua Liu <58683130+liuh-80@users.noreply.github.com> Date: Mon, 24 Oct 2022 13:03:52 +0800 Subject: [PATCH 31/35] [openssh] Update openssh make file, add missing dependency to libnl. (#12327) Update openssh make file, add missing dependency to libnl. #### Why I did it Openssh indirectly depends on libnl. Another PR #12447 need add new patch to openssh, after adding new patch to openssh, PR build failed with libnl missing error. #### How I did it Update openssh make file, add missing dependency to libnl. #### How to verify it Pass all test case #### Which release branch to backport (provide reason below if selected) - [ ] 201811 - [ ] 201911 - [ ] 202006 - [ ] 202012 - [ ] 202106 - [ ] 202111 - [ ] 202205 #### Description for the changelog Update openssh make file, add missing dependency to libnl. #### Ensure to add label/tag for the feature raised. example - PR#2174 under sonic-utilities repo. where, Generic Config and Update feature has been labelled as GCU. #### Link to config_db schema for YANG module changes #### A picture of a cute animal (not mandatory but encouraged) --- rules/openssh.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/rules/openssh.mk b/rules/openssh.mk index 53438b76ab73..a5e4b5c4b7b0 100644 --- a/rules/openssh.mk +++ b/rules/openssh.mk @@ -6,6 +6,7 @@ export OPENSSH_VERSION OPENSSH_SERVER = openssh-server_$(OPENSSH_VERSION)_$(CONFIGURED_ARCH).deb $(OPENSSH_SERVER)_SRC_PATH = $(SRC_PATH)/openssh +$(OPENSSH_SERVER)_DEPENDS += $(LIBNL3_DEV) $(LIBNL_ROUTE3_DEV) SONIC_MAKE_DEBS += $(OPENSSH_SERVER) # The .c, .cpp, .h & .hpp files under src/{$DBG_SRC_ARCHIVE list} From c12ee01c1b7182cbbebad253de22e133d6dd0519 Mon Sep 17 00:00:00 2001 From: DavidZagury <32644413+DavidZagury@users.noreply.github.com> Date: Thu, 27 Oct 2022 01:54:44 +0300 Subject: [PATCH 32/35] Fix CVE-2022-37032 on FRR submodule (#12435) * Fix CVE-2022-37032 on FRR submodule Patch was cherry picked from FRRouting/frr repo - d8d77d3733bc299ed5dd7b44c4d464ba2bfed288 * Fix CVE-2022-37032 on FRR submodule Patch was cherry picked from FRRouting/frr repo - d8d77d3733bc299ed5dd7b44c4d464ba2bfed288 * Update patch version number --- ...e-cannot-accidently-write-into-stack.patch | 108 ++++++++++++++++++ src/sonic-frr/patch/series | 1 + 2 files changed, 109 insertions(+) create mode 100644 src/sonic-frr/patch/0012-Ensure-ospf_apiclient_lsa_originate-cannot-accidently-write-into-stack.patch diff --git a/src/sonic-frr/patch/0012-Ensure-ospf_apiclient_lsa_originate-cannot-accidently-write-into-stack.patch b/src/sonic-frr/patch/0012-Ensure-ospf_apiclient_lsa_originate-cannot-accidently-write-into-stack.patch new file mode 100644 index 000000000000..d46f13a3caf1 --- /dev/null +++ b/src/sonic-frr/patch/0012-Ensure-ospf_apiclient_lsa_originate-cannot-accidently-write-into-stack.patch @@ -0,0 +1,108 @@ +From d8d77d3733bc299ed5dd7b44c4d464ba2bfed288 Mon Sep 17 00:00:00 2001 +From: Donald Sharp +Date: Wed, 20 Jul 2022 16:43:17 -0400 +Subject: [PATCH 1/3] ospfclient: Ensure ospf_apiclient_lsa_originate cannot + accidently write into stack + +Even though OSPF_MAX_LSA_SIZE is quite large and holds the upper bound +on what can be written into a lsa, let's add a small check to ensure +it is not possible to do a bad thing. + +This wins one of the long standing bug awards. 2003! + +Fixes: #11602 +Signed-off-by: Donald Sharp +--- + ospfclient/ospf_apiclient.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/ospfclient/ospf_apiclient.c b/ospfclient/ospf_apiclient.c +index 29f1c0807db..51c8a5b8c06 100644 +--- a/ospfclient/ospf_apiclient.c ++++ b/ospfclient/ospf_apiclient.c +@@ -447,6 +447,12 @@ int ospf_apiclient_lsa_originate(struct ospf_apiclient *oclient, + return OSPF_API_ILLEGALLSATYPE; + } + ++ if ((size_t)opaquelen > sizeof(buf) - sizeof(struct lsa_header)) { ++ fprintf(stderr, "opaquelen(%d) is larger than buf size %zu\n", ++ opaquelen, sizeof(buf)); ++ return OSPF_API_NOMEMORY; ++ } ++ + /* Make a new LSA from parameters */ + lsah = (struct lsa_header *)buf; + lsah->ls_age = 0; + +From 519929cdd47ac4d9f7f33e13922e1a063f69bb24 Mon Sep 17 00:00:00 2001 +From: Donald Sharp +Date: Wed, 20 Jul 2022 16:49:09 -0400 +Subject: [PATCH 2/3] isisd: Ensure rcap is freed in error case + +unpack_tlv_router_cap allocates memory that in the error +case is not being freed. + +Signed-off-by: Donald Sharp +--- + isisd/isis_tlvs.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/isisd/isis_tlvs.c b/isisd/isis_tlvs.c +index f1aae7caf10..dad271225b3 100644 +--- a/isisd/isis_tlvs.c ++++ b/isisd/isis_tlvs.c +@@ -2966,9 +2966,9 @@ static int pack_tlv_router_cap(const struct isis_router_cap *router_cap, + } + + static int unpack_tlv_router_cap(enum isis_tlv_context context, +- uint8_t tlv_type, uint8_t tlv_len, +- struct stream *s, struct sbuf *log, +- void *dest, int indent) ++ uint8_t tlv_type, uint8_t tlv_len, ++ struct stream *s, struct sbuf *log, void *dest, ++ int indent) + { + struct isis_tlvs *tlvs = dest; + struct isis_router_cap *rcap; +@@ -3013,7 +3013,7 @@ static int unpack_tlv_router_cap(enum isis_tlv_context context, + log, indent, + "WARNING: Router Capability subTLV length too large compared to expected size\n"); + stream_forward_getp(s, STREAM_READABLE(s)); +- ++ XFREE(MTYPE_ISIS_TLV, rcap); + return 0; + } + + +From 3c4821679f2362bcd38fcc7803f28a5210441ddb Mon Sep 17 00:00:00 2001 +From: Donald Sharp +Date: Thu, 21 Jul 2022 08:11:58 -0400 +Subject: [PATCH 3/3] bgpd: Make sure hdr length is at a minimum of what is + expected + +Ensure that if the capability length specified is enough data. + +Signed-off-by: Donald Sharp +--- + bgpd/bgp_packet.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/bgpd/bgp_packet.c b/bgpd/bgp_packet.c +index 7c92a8d9e83..bcd47e32d45 100644 +--- a/bgpd/bgp_packet.c ++++ b/bgpd/bgp_packet.c +@@ -2440,6 +2440,14 @@ static int bgp_capability_msg_parse(struct peer *peer, uint8_t *pnt, + "%s CAPABILITY has action: %d, code: %u, length %u", + peer->host, action, hdr->code, hdr->length); + ++ if (hdr->length < sizeof(struct capability_mp_data)) { ++ zlog_info( ++ "%s Capability structure is not properly filled out, expected at least %zu bytes but header length specified is %d", ++ peer->host, sizeof(struct capability_mp_data), ++ hdr->length); ++ return BGP_Stop; ++ } ++ + /* Capability length check. */ + if ((pnt + hdr->length + 3) > end) { + zlog_info("%s Capability length error", peer->host); diff --git a/src/sonic-frr/patch/series b/src/sonic-frr/patch/series index 5dd4e5a1fe71..5bee50310f5c 100644 --- a/src/sonic-frr/patch/series +++ b/src/sonic-frr/patch/series @@ -10,3 +10,4 @@ Disable-ipv6-src-address-test-in-pceplib.patch 0009-ignore-route-from-default-table.patch 0010-zebra-Note-when-the-netlink-DUMP-command-is-interrup.patch 0011-bgpd-enhanced-capability-is-always-turned-on-for-int.patch +0012-Ensure-ospf_apiclient_lsa_originate-cannot-accidently-write-into-stack.patch From b1c0d8d5e4b4311ffa59765353d591207ae84236 Mon Sep 17 00:00:00 2001 From: Samuel Angebault Date: Thu, 27 Oct 2022 16:09:03 +0200 Subject: [PATCH 33/35] Add emmc quirks to boot0 (#9989) (#12373) Why I did it Fix some unreliability seen on emmc device with some AMD CPUs How I did it Added a kernel parameter to add quirks to It depends on a sonic-linux-kernel change to work properly but will be a no-op without it. Description for the changelog Add emmc quirks for Upperlake --- files/Aboot/boot0.j2 | 1 + 1 file changed, 1 insertion(+) diff --git a/files/Aboot/boot0.j2 b/files/Aboot/boot0.j2 index a2a1b82b32f7..5aa0091a9d94 100644 --- a/files/Aboot/boot0.j2 +++ b/files/Aboot/boot0.j2 @@ -618,6 +618,7 @@ write_platform_specific_cmdline() { if in_array "$platform" "crow" "magpie"; then cmdline_add amd_iommu=off cmdline_add modprobe.blacklist=snd_hda_intel,hdaudio + cmdline_add sdhci.append_quirks2=0x40 read_system_eeprom fi if in_array "$platform" "woodpecker"; then From d28d39b53ccdf001244d2abed90328161c7ac0f6 Mon Sep 17 00:00:00 2001 From: Andriy Yurkiv Date: Thu, 27 Oct 2022 19:51:29 +0300 Subject: [PATCH 34/35] [Dual ToR][202205] update swss submodue, add new SAI attr Signed-off-by: Andriy Yurkiv --- .gitmodules | 2 +- src/sonic-swss | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index 0812b366c61b..aaae41a2c24d 100644 --- a/.gitmodules +++ b/.gitmodules @@ -12,7 +12,7 @@ branch = 202205 [submodule "sonic-swss"] path = src/sonic-swss - url = https://github.com/sonic-net/sonic-swss + url = https://github.com/ayurkiv-nvda/sonic-swss.git branch = 202205 [submodule "src/p4c-bm/p4c-bm"] path = platform/p4/p4c-bm/p4c-bm diff --git a/src/sonic-swss b/src/sonic-swss index 6fe0afdd3fa4..d0070b5d6e6c 160000 --- a/src/sonic-swss +++ b/src/sonic-swss @@ -1 +1 @@ -Subproject commit 6fe0afdd3fa41f5846be464a4382d7a779142d50 +Subproject commit d0070b5d6e6ccd38501e3d632598661663adb843 From 8576e309e6019aa0958bacbd04f170b40cb82138 Mon Sep 17 00:00:00 2001 From: Andriy Yurkiv Date: Thu, 27 Oct 2022 19:54:13 +0300 Subject: [PATCH 35/35] [Build] Add the missing debian source bullseye-updates/buster-updates Signed-off-by: Andriy Yurkiv --- dockers/docker-base-bullseye/sources.list | 1 + dockers/docker-base-buster/sources.list | 1 + dockers/docker-base-buster/sources.list.arm64 | 1 + dockers/docker-base-buster/sources.list.armhf | 1 + 4 files changed, 4 insertions(+) diff --git a/dockers/docker-base-bullseye/sources.list b/dockers/docker-base-bullseye/sources.list index 4a68761df7c8..c45ef0811f10 100644 --- a/dockers/docker-base-bullseye/sources.list +++ b/dockers/docker-base-bullseye/sources.list @@ -5,6 +5,7 @@ deb [arch=amd64] http://debian-archive.trafficmanager.net/debian/ bullseye main deb-src [arch=amd64] http://debian-archive.trafficmanager.net/debian/ bullseye main contrib non-free deb [arch=amd64] http://debian-archive.trafficmanager.net/debian-security/ bullseye-security main contrib non-free deb-src [arch=amd64] http://debian-archive.trafficmanager.net/debian-security/ bullseye-security main contrib non-free +deb [arch=amd64] http://debian-archive.trafficmanager.net/debian bullseye-updates main contrib non-free deb [arch=amd64] http://debian-archive.trafficmanager.net/debian/ bullseye-backports main contrib non-free # Debian mirror supports multiple versions for a package diff --git a/dockers/docker-base-buster/sources.list b/dockers/docker-base-buster/sources.list index 0eef72d9fa2d..473c9eb22e76 100644 --- a/dockers/docker-base-buster/sources.list +++ b/dockers/docker-base-buster/sources.list @@ -5,6 +5,7 @@ deb [arch=amd64] http://debian-archive.trafficmanager.net/debian/ buster main co deb-src [arch=amd64] http://debian-archive.trafficmanager.net/debian/ buster main contrib non-free deb [arch=amd64] http://debian-archive.trafficmanager.net/debian-security/ buster/updates main contrib non-free deb-src [arch=amd64] http://debian-archive.trafficmanager.net/debian-security/ buster/updates main contrib non-free +deb [arch=amd64] http://debian-archive.trafficmanager.net/debian buster-updates main contrib non-free deb [arch=amd64] http://debian-archive.trafficmanager.net/debian/ buster-backports main contrib non-free # Debian mirror supports multiple versions for a package diff --git a/dockers/docker-base-buster/sources.list.arm64 b/dockers/docker-base-buster/sources.list.arm64 index 6375734e99e6..249efc17b6fd 100644 --- a/dockers/docker-base-buster/sources.list.arm64 +++ b/dockers/docker-base-buster/sources.list.arm64 @@ -5,6 +5,7 @@ deb [arch=arm64] http://deb.debian.org/debian buster main contrib non-free deb-src [arch=arm64] http://deb.debian.org/debian buster main contrib non-free deb [arch=arm64] http://security.debian.org buster/updates main contrib non-free deb-src [arch=arm64] http://security.debian.org buster/updates main contrib non-free +deb [arch=arm64] http://deb.debian.org/debian buster-updates main contrib non-free deb [arch=arm64] http://deb.debian.org/debian/ buster-backports main contrib non-free deb [arch=arm64] http://packages.trafficmanager.net/debian/debian buster main contrib non-free deb [arch=arm64] http://packages.trafficmanager.net/debian/debian buster-updates main contrib non-free diff --git a/dockers/docker-base-buster/sources.list.armhf b/dockers/docker-base-buster/sources.list.armhf index a03af1a33ac0..ff6d5787b212 100644 --- a/dockers/docker-base-buster/sources.list.armhf +++ b/dockers/docker-base-buster/sources.list.armhf @@ -5,6 +5,7 @@ deb [arch=armhf] http://deb.debian.org/debian buster main contrib non-free deb-src [arch=armhf] http://deb.debian.org/debian buster main contrib non-free deb [arch=armhf] http://security.debian.org buster/updates main contrib non-free deb-src [arch=armhf] http://security.debian.org buster/updates main contrib non-free +deb [arch=armhf] http://deb.debian.org/debian buster-updates main contrib non-free deb [arch=armhf] http://deb.debian.org/debian/ buster-backports main contrib non-free deb [arch=armhf] http://packages.trafficmanager.net/debian/debian buster main contrib non-free deb [arch=armhf] http://packages.trafficmanager.net/debian/debian buster-updates main contrib non-free