diff --git a/config/boards/bananapim4berry.wip b/config/boards/bananapim4berry.wip new file mode 100644 index 000000000000..3d5700aef0d8 --- /dev/null +++ b/config/boards/bananapim4berry.wip @@ -0,0 +1,26 @@ +# Allwinner H618 quad core 2/4GB RAM 8GB eMMC SoC WiFi\Bt HDMI SPI USB-C +BOARD_NAME="BananaPi M4 Berry" +BOARDFAMILY="sun50iw9-bpi" +BOARD_MAINTAINER="The-going" +BOOTCONFIG="bananapi_m4_berry_defconfig" + +BOOTPATCHDIR="v2025.01/board_bananapim4berry" +BOOTBRANCH_BOARD="tag:v2025.01" + +OVERLAY_PREFIX="sun50i-h616" +BOOT_FDT_FILE="sun50i-h618-bananapi-m4-berry.dtb" +BOOT_LOGO="desktop" +KERNEL_TARGET="current,edge" +KERNEL_TEST_TARGET="current" + +PACKAGE_LIST_BOARD="rfkill bluetooth bluez bluez-tools gpiod libgpiod2 network-manager" + +function post_family_tweaks_bsp__bananapi_firmware() { + if [[ -d "$SRC/packages/bsp/bananapi/brcm" ]] && [[ -d "$SRC/packages/bsp/bananapi/rtl_bt" ]]; then + mkdir -p "${destination}"/lib/firmware/updates/brcm + mkdir -p "${destination}"/lib/firmware/updates/rtl_bt + display_alert "$BOARD" "Installing upstream firmware" "info" + cp -fr $SRC/packages/bsp/bananapi/brcm/* "${destination}"/lib/firmware/updates/brcm/ + cp -fr $SRC/packages/bsp/bananapi/rtl_bt/* "${destination}"/lib/firmware/updates/rtl_bt/ + fi +} diff --git a/config/sources/families/include/sunxi64_common.inc b/config/sources/families/include/sunxi64_common.inc index 3bde6f758c2c..ef5fddea301e 100644 --- a/config/sources/families/include/sunxi64_common.inc +++ b/config/sources/families/include/sunxi64_common.inc @@ -31,7 +31,7 @@ case $BRANCH in current) declare -g KERNEL_MAJOR_MINOR="6.6" # Major and minor versions of this kernel. - declare -g KERNELBRANCH="tag:v6.6.72" + declare -g KERNELBRANCH="tag:v6.6.75" ;; edge) diff --git a/config/sources/families/include/sunxi_common.inc b/config/sources/families/include/sunxi_common.inc index c6578f762275..2b85863bc9ea 100644 --- a/config/sources/families/include/sunxi_common.inc +++ b/config/sources/families/include/sunxi_common.inc @@ -32,7 +32,7 @@ case $BRANCH in current) declare -g KERNEL_MAJOR_MINOR="6.6" # Major and minor versions of this kernel. - declare -g KERNELBRANCH="tag:v6.6.72" + declare -g KERNELBRANCH="tag:v6.6.75" ;; edge) diff --git a/config/sources/families/sun50iw9-bpi.conf b/config/sources/families/sun50iw9-bpi.conf index 06725b8dfbbb..8096b10f1b3c 100644 --- a/config/sources/families/sun50iw9-bpi.conf +++ b/config/sources/families/sun50iw9-bpi.conf @@ -18,7 +18,7 @@ case $BRANCH in declare -g BOOTSOURCE='https://source.denx.de/u-boot/u-boot.git' declare -g BOOTBRANCH="${BOOTBRANCH_BOARD}" declare -g ATFSOURCE='https://github.com/ARM-software/arm-trusted-firmware' - declare -g ATFBRANCH='tag:lts-v2.10.7' + declare -g ATFBRANCH='tag:v2.12.0' declare -g ATF_PLAT="sun50i_h616" declare -g ATF_TARGET_MAP='PLAT=sun50i_h616 DEBUG=1 bl31;;build/sun50i_h616/debug/bl31.bin' declare -g BOOTSCRIPT='boot-sun50i-next.cmd:boot.cmd' diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-Add-BananaPi-M4-Berry-support.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-Add-BananaPi-M4-Berry-support.patch new file mode 100644 index 000000000000..d182ccd692c2 --- /dev/null +++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-Add-BananaPi-M4-Berry-support.patch @@ -0,0 +1,512 @@ +From 83dd3e784cf7a6f7e5271740e01dd0dd98b3d618 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Wed, 19 Feb 2025 11:20:08 +0300 +Subject: [PATCH] arm64: dts: Add BananaPi M4 Berry support + +--- + arch/arm64/boot/dts/allwinner/Makefile | 1 + + .../sun50i-h618-bananapi-m4-berry.dts | 480 ++++++++++++++++++ + 2 files changed, 481 insertions(+) + create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-berry.dts + +diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile +index 3f0bb0aae3ff..394cded5e038 100644 +--- a/arch/arm64/boot/dts/allwinner/Makefile ++++ b/arch/arm64/boot/dts/allwinner/Makefile +@@ -56,6 +56,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-cherryba-m1.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-sd.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-emmc.dtb ++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-bananapi-m4-berry.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-bananapi-m4-zero.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-longanpi-3h.dtb + dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-berry.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-berry.dts +new file mode 100644 +index 000000000000..0cd6c6d83a4b +--- /dev/null ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-berry.dts +@@ -0,0 +1,480 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++/* ++ * Copyright (C) 2020 Arm Ltd. ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-h616.dtsi" ++#include "sun50i-h616-cpu-opp.dtsi" ++/* #include "axp313a.dtsi" */ ++ ++#include ++#include ++#include ++#include ++ ++/ { ++ model = "BananaPi M4 Berry"; ++ compatible = "BiPai,bananapi-m4berry", "allwinner,sun50i-h616"; ++ ++ aliases { ++ ethernet0 = &emac0; ++ ethernet1 = &emac1; ++ serial0 = &uart0; ++ serial5 = &uart5; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ connector { ++ compatible = "hdmi-connector"; ++ type = "d"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ key-sw3 { ++ label = "sw3"; ++ linux,code = ; ++ gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */ ++ wakeup-source; ++ }; ++ }; ++ ++ leds: leds { ++ compatible = "gpio-leds"; ++ ++ led-0 { ++ color = ; ++ function = LED_FUNCTION_STATUS; ++ gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ wifi_usb { ++ compatible = "usb-wifi"; ++ status = "okay"; ++ power_on_pin = <&pio 2 2 GPIO_ACTIVE_HIGH>; /* PC2 */ ++ }; ++ ++ reg_vcc5v: vcc5v { ++ /* board wide 5V supply directly from the USB-C socket */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-5v"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ reg_gmac_3v3: gmac-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ vin-supply = <®_vcc5v>; ++ }; ++ ++ reg_vcc3v3: vcc3v3 { ++ /* SY8089 DC/DC converter */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <®_vcc5v>; ++ regulator-always-on; ++ }; ++ ++ reg_vcc_wifi_io: vcc-wifi-io { ++ /* Always on 1.8V/300mA regulator for WiFi and BT IO */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-wifi-io"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ vin-supply = <®_vcc3v3>; ++ }; ++ ++ ac200_pwm_clk: ac200_clk { ++ compatible = "pwm-clock"; ++ #clock-cells = <0>; ++ // pwm5 period_ns = 500 > 334 for select 24M clock. ++ pwms = <&pwm 5 500 0>; ++ clock-frequency = <2000000>; ++ status = "okay"; ++ }; ++ ++ soc { ++ pwm: pwm@300a000 { ++ compatible = "allwinner,sun50i-h616-pwm"; ++ reg = <0x0300a000 0x400>; ++ clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; ++ clock-names = "mod", "bus"; ++ resets = <&ccu RST_BUS_PWM>; ++ pwm-number = <6>; ++ pwm-base = <0x0>; ++ sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>, <&pwm5>; ++ #pwm-cells = <3>; ++ status = "okay"; ++ }; ++ ++ pwm0: pwm0@0300a000 { ++ compatible = "allwinner,sunxi-pwm0"; ++ reg = <0x0 0x0300a010 0x0 0x4>; ++ reg_base = <0x0300a000>; ++ }; ++ ++ pwm1: pwm1@0300a000 { ++ compatible = "allwinner,sunxi-pwm1"; ++ reg = <0x0 0x0300a010 0x0 0x4>; ++ reg_base = <0x0300a000>; ++ }; ++ ++ pwm2: pwm2@0300a000 { ++ compatible = "allwinner,sunxi-pwm2"; ++ reg = <0x0 0x0300a012 0x0 0x4>; ++ reg_base = <0x0300a000>; ++ }; ++ ++ pwm3: pwm3@0300a000 { ++ compatible = "allwinner,sunxi-pwm3"; ++ reg = <0x0 0x0300a013 0x0 0x4>; ++ reg_base = <0x0300a000>; ++ }; ++ ++ pwm4: pwm4@0300a000 { ++ compatible = "allwinner,sunxi-pwm4"; ++ reg = <0x0 0x0300a013 0x0 0x4>; ++ reg_base = <0x0300a000>; ++ }; ++ ++ pwm5: pwm5@0300a000 { ++ compatible = "allwinner,sunxi-pwm5"; ++ reg = <0x0 0x0300a015 0x0 0x4>; ++ reg_base = <0x0300a000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm5_pin>; ++ clk_bypass_output = <0x1>; ++ }; ++ }; ++}; ++ ++&de { ++ status = "okay"; ++}; ++ ++&hdmi { ++ hvcc-supply = <®_aldo1>; ++ status = "okay"; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&gpu { ++ mali-supply = <®_dcdc1>; ++ status = "disabled"; ++}; ++ ++&emac0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ext_rgmii_pins>; ++ phy-mode = "rgmii"; ++ phy-handle = <&ext_rgmii_phy>; ++ allwinner,rx-delay-ps = <3100>; ++ allwinner,tx-delay-ps = <700>; ++ status = "disabled"; ++}; ++ ++&mdio0 { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ }; ++}; ++ ++&emac1 { ++ phy-mode = "rmii"; ++ phy-handle = <&rmii_phy>; ++ phy-supply = <®_dldo1>; ++ allwinner,rx-delay-ps = <3100>; ++ allwinner,tx-delay-ps = <700>; ++ status = "disabled"; ++}; ++ ++&mdio1 { ++ rmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ }; ++}; ++ ++&mmc0 { ++ vmmc-supply = <®_dldo1>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ ++ bus-width = <4>; ++ max-frequency = <50000000>; ++ status = "okay"; ++}; ++ ++&mmc2 { ++ vmmc-supply = <®_dldo1>; ++ vqmmc-supply = <®_aldo1>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ mmc-hs200-1_8v; ++ status = "okay"; ++}; ++ ++&pio { ++ vcc-pc-supply = <®_aldo1>; ++ vcc-pf-supply = <®_dldo1>; ++ vcc-pg-supply = <®_dldo1>; ++ vcc-ph-supply = <®_dldo1>; ++ vcc-pi-supply = <®_dldo1>; ++}; ++ ++&r_i2c { ++ pinctrl-0 = <&r_i2c_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ axp313a: pmic@36 { ++ compatible = "x-powers,axp313a"; ++ reg = <0x36>; ++ wakeup-source; ++ ++ vin1-supply = <®_vcc5v>; ++ vin2-supply = <®_vcc5v>; ++ vin3-supply = <®_vcc5v>; ++ ++ regulators{ ++ reg_dcdc1: dcdc1 { ++ regulator-name = "dcdc1-gpu"; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-always-on; ++ }; ++ ++ reg_dcdc2: dcdc2 { ++ regulator-name = "dcdc2-cpu"; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-ramp-delay = <200>; ++ regulator-always-on; ++ }; ++ ++ reg_dcdc3: dcdc3 { ++ regulator-name = "dcdc3-dram"; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-always-on; ++ }; ++ ++ reg_aldo1: aldo1 { ++ regulator-name = "aldo1-1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-always-on; ++ }; ++ ++ reg_dldo1: dldo1 { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-always-on; ++ }; ++ }; ++ }; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_ph_pins>; ++ status = "okay"; ++}; ++ ++&usbotg { ++ /* ++ * PHY0 pins are connected to a USB-C socket, but a role switch ++ * is not implemented: both CC pins are pulled to GND. ++ * The VBUS pins power the device, so a fixed peripheral mode ++ * is the best choice. ++ * The board can be powered via GPIOs, in this case port0 *can* ++ * act as a host (with a cable/adapter ignoring CC), as VBUS is ++ * then provided by the GPIOs. Any user of this setup would ++ * need to adjust the DT accordingly: dr_mode set to "host", ++ * enabling OHCI0 and EHCI0. ++ */ ++ dr_mode = "peripheral"; ++ status = "okay"; ++}; ++ ++&usbphy { ++ usb1_vbus-supply = <®_vcc5v>; ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "disabled"; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&ehci2 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "disabled"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&ohci2 { ++ status = "okay"; ++}; ++ ++&ohci3 { ++ status = "okay"; ++}; ++ ++&ir { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ir_rx_pin>; ++ status = "okay"; ++}; ++ ++&i2c1 { ++ status = "disabled"; ++}; ++ ++&i2c2 { ++ status = "disabled"; ++}; ++ ++&i2c3 { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pa_pins>; ++ ++ ac200_x: mfd@10 { ++ compatible = "x-powers,ac200-sunxi"; ++ reg = <0x10>; ++ clocks = <&ac200_pwm_clk>; ++ // ephy id ++ nvmem-cells = <&ephy_calibration>; ++ nvmem-cell-names = "calibration"; ++ ++ ac200_ephy: phy { ++ compatible = "x-powers,ac200-ephy-sunxi"; ++ status = "okay"; ++ }; ++ }; ++}; ++ ++&i2c4 { ++ status = "disabled"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++ status = "disabled"; ++}; ++ ++&uart5 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart5_pins>; ++ status = "okay"; ++}; ++ ++&spi1 { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>, <&spi1_cs1_pin>; ++ ++ spidev@1 { ++ compatible = "rohm,dh2228fv"; ++ status = "okay"; ++ reg = <1>; ++ spi-max-frequency = <1000000>; ++ }; ++}; ++ ++&codec { ++ allwinner,audio-routing = ++ "Line Out", "LINEOUT"; ++ status = "okay"; ++}; ++ ++&ahub_dam_plat { ++ status = "okay"; ++}; ++/* ++&ahub_dam_mach { ++ status = "okay"; ++}; ++*/ ++&ahub1_plat { ++ status = "okay"; ++}; ++ ++&ahub1_mach { ++ status = "okay"; ++}; ++/* ++&ahub_i2s2 { ++ status = "okay"; ++}; ++*/ ++&cpu0 { ++ cpu-supply = <®_dcdc2>; ++ status = "okay"; ++}; ++ ++&sid { ++ ephy_calibration: ephy-calibration@2c { ++ reg = <0x2c 0x2>; ++ }; ++}; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-sun50i-h616-add-i2c3_pa-all-pwm-pins.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-sun50i-h616-add-i2c3_pa-all-pwm-pins.patch new file mode 100644 index 000000000000..4f91305cd0df --- /dev/null +++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/arm64-dts-sun50i-h616-add-i2c3_pa-all-pwm-pins.patch @@ -0,0 +1,76 @@ +From 4b1a9e607e47f2005a3b6cdc5c834bfc66c903ee Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Sat, 22 Feb 2025 10:16:51 +0300 +Subject: [PATCH] arm64: dts: sun50i-h616: add i2c3_pa, all pwm pins + +--- + .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 46 +++++++++++++++++++ + 1 file changed, 46 insertions(+) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +index 4c1b61b3c64f..fc1f15193d80 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +@@ -420,6 +420,11 @@ i2c2_ph_pins: i2c2-ph-pins { + function = "i2c2"; + }; + ++ i2c3_pa_pins: i2c3-pa-pins { ++ pins = "PA10", "PA11"; ++ function = "i2c3"; ++ }; ++ + i2c3_ph_pins: i2c3-ph-pins { + pins = "PH4", "PH5"; + function = "i2c3"; +@@ -468,6 +473,47 @@ rmii_pins: rmii-pins { + drive-strength = <40>; + }; + ++ /omit-if-no-ref/ ++ pwm0_pd_pin: pwm0-pd-pin { ++ pins = "PD28"; ++ function = "pwm0"; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1_pg_pin: pwm1-pg-pin { ++ pins = "PG19"; ++ function = "pwm1"; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1_ph_pin: pwm1-ph-pin { ++ pins = "PH3"; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2_ph_pin: pwm2-ph-pin { ++ pins = "PH2"; ++ function = "pwm2"; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm3_ph_pin: pwm3-ph-pin { ++ pins = "PH0"; ++ function = "pwm3"; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm4_ph_pin: pwm4-ph-pin { ++ pins = "PH1"; ++ function = "pwm4"; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm5_pin: pwm5-pin { ++ pins = "PA12"; ++ function = "pwm5"; ++ }; ++ + /omit-if-no-ref/ + spi0_pins: spi0-pins { + pins = "PC0", "PC2", "PC4"; +-- +2.35.3 + diff --git a/patch/kernel/archive/sunxi-6.6/series.armbian b/patch/kernel/archive/sunxi-6.6/series.armbian index 8cd7f64ccb79..6f7ad597d47d 100644 --- a/patch/kernel/archive/sunxi-6.6/series.armbian +++ b/patch/kernel/archive/sunxi-6.6/series.armbian @@ -203,3 +203,5 @@ patches.armbian/Add-BananaPi-BPI-M4-Zero-pinctrl.patch patches.armbian/Fix-ghost-touches-on-tsc2007-tft-screen.patch patches.armbian/bigtereetech-cb1-i2c-gpio-and-ws2812.patch + patches.armbian/arm64-dts-Add-BananaPi-M4-Berry-support.patch + patches.armbian/arm64-dts-sun50i-h616-add-i2c3_pa-all-pwm-pins.patch diff --git a/patch/kernel/archive/sunxi-6.6/series.conf b/patch/kernel/archive/sunxi-6.6/series.conf index 8d70becc4667..7dd3e383e47c 100644 --- a/patch/kernel/archive/sunxi-6.6/series.conf +++ b/patch/kernel/archive/sunxi-6.6/series.conf @@ -452,3 +452,5 @@ patches.armbian/Add-BananaPi-BPI-M4-Zero-pinctrl.patch patches.armbian/Fix-ghost-touches-on-tsc2007-tft-screen.patch patches.armbian/bigtereetech-cb1-i2c-gpio-and-ws2812.patch + patches.armbian/arm64-dts-Add-BananaPi-M4-Berry-support.patch + patches.armbian/arm64-dts-sun50i-h616-add-i2c3_pa-all-pwm-pins.patch diff --git a/patch/u-boot/v2025.01/board_bananapim4berry/0001-u-boot-configs-Add-sun50i-h618-bananapi-m4berry-defc.patch b/patch/u-boot/v2025.01/board_bananapim4berry/0001-u-boot-configs-Add-sun50i-h618-bananapi-m4berry-defc.patch new file mode 100644 index 000000000000..fd95e52b15bb --- /dev/null +++ b/patch/u-boot/v2025.01/board_bananapim4berry/0001-u-boot-configs-Add-sun50i-h618-bananapi-m4berry-defc.patch @@ -0,0 +1,50 @@ +From 1fbb4fc8a902b1ceb73e5848000b340715886d4d Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Tue, 21 Jan 2025 23:04:54 +0300 +Subject: [PATCH 1/6] u-boot: configs: Add sun50i-h618-bananapi-m4berry + defconfig + +--- + configs/bananapi_m4_berry_defconfig | 30 +++++++++++++++++++++++++++++ + 1 file changed, 30 insertions(+) + create mode 100644 configs/bananapi_m4_berry_defconfig + +diff --git a/configs/bananapi_m4_berry_defconfig b/configs/bananapi_m4_berry_defconfig +new file mode 100644 +index 00000000000..c5a97c739a0 +--- /dev/null ++++ b/configs/bananapi_m4_berry_defconfig +@@ -0,0 +1,30 @@ ++CONFIG_ARM=y ++CONFIG_ARCH_SUNXI=y ++CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h618-bananapi-m4-berry" ++CONFIG_OF_UPSTREAM=y ++CONFIG_SPL=y ++CONFIG_DRAM_SUN50I_H616_DX_ODT=0x07070707 ++CONFIG_DRAM_SUN50I_H616_DX_DRI=0x0e0e0e0e ++CONFIG_DRAM_SUN50I_H616_CA_DRI=0x0e0e ++CONFIG_DRAM_SUN50I_H616_ODT_EN=0xaaaaeeee ++CONFIG_DRAM_SUN50I_H616_TPR6=0x48808080 ++CONFIG_DRAM_SUN50I_H616_TPR10=0x402f6663 ++CONFIG_DRAM_SUN50I_H616_TPR11=0x26262524 ++CONFIG_DRAM_SUN50I_H616_TPR12=0x100f100f ++CONFIG_MACH_SUN50I_H616=y ++CONFIG_SUNXI_DRAM_H616_LPDDR4=y ++CONFIG_DRAM_CLK=792 ++CONFIG_MMC_SUNXI_SLOT_EXTRA=2 ++CONFIG_R_I2C_ENABLE=y ++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set ++CONFIG_SPL_I2C=y ++CONFIG_SPL_SYS_I2C_LEGACY=y ++CONFIG_SYS_I2C_MVTWSI=y ++CONFIG_SYS_I2C_SLAVE=0x7f ++CONFIG_SYS_I2C_SPEED=400000 ++CONFIG_SUN8I_EMAC=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_AXP313_POWER=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_MUSB_GADGET=y +-- +2.35.3 + diff --git a/patch/u-boot/v2025.01/board_bananapim4berry/0002-dts-upstream-sun50i-h616-add-emac1-node-pinctrl-pins.patch b/patch/u-boot/v2025.01/board_bananapim4berry/0002-dts-upstream-sun50i-h616-add-emac1-node-pinctrl-pins.patch new file mode 100644 index 000000000000..ce36b0b431cc --- /dev/null +++ b/patch/u-boot/v2025.01/board_bananapim4berry/0002-dts-upstream-sun50i-h616-add-emac1-node-pinctrl-pins.patch @@ -0,0 +1,129 @@ +From 573dcff4016af4570a577d7e72c54538d911ab30 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Sun, 16 Feb 2025 16:01:17 +0300 +Subject: [PATCH 2/6] dts: upstream: sun50i-h616: add emac1 node, pinctrl pins + +--- + .../src/arm64/allwinner/sun50i-h616.dtsi | 69 ++++++++++++++++++- + 1 file changed, 67 insertions(+), 2 deletions(-) + +diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi b/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi +index e88c1fbac6a..278ffdf2264 100644 +--- a/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi ++++ b/dts/upstream/src/arm64/allwinner/sun50i-h616.dtsi +@@ -100,12 +100,12 @@ + ranges; + + /* +- * 256 KiB reserved for Trusted Firmware-A (BL31). ++ * 512 KiB reserved for Trusted Firmware-A (BL31). + * This is added by BL31 itself, but some bootloaders fail + * to propagate this into the DTB handed to kernels. + */ + secmon@40000000 { +- reg = <0x0 0x40000000 0x0 0x40000>; ++ reg = <0x0 0x40000000 0x0 0x80000>; + no-map; + }; + }; +@@ -248,11 +248,23 @@ + drive-strength = <40>; + }; + ++ rmii_pins: rmii-pins { ++ pins = "PA0", "PA1", "PA2", "PA3", "PA4", ++ "PA5", "PA6", "PA7", "PA8", "PA9"; ++ function = "emac1"; ++ drive-strength = <40>; ++ }; ++ + i2c0_pins: i2c0-pins { + pins = "PI5", "PI6"; + function = "i2c0"; + }; + ++ i2c3_pa_pins: i2c3-pa-pins { ++ pins = "PA10", "PA11"; ++ function = "i2c3"; ++ }; ++ + i2c3_ph_pins: i2c3-ph-pins { + pins = "PH4", "PH5"; + function = "i2c3"; +@@ -313,6 +325,12 @@ + function = "spi1"; + }; + ++ /omit-if-no-ref/ ++ spi1_cs1_pin: spi1-cs1-pin { ++ pins = "PH9"; ++ function = "spi1"; ++ }; ++ + spdif_tx_pin: spdif-tx-pin { + pins = "PH4"; + function = "spdif"; +@@ -335,6 +353,24 @@ + function = "uart1"; + }; + ++ /omit-if-no-ref/ ++ uart2_pins: uart2-pins { ++ pins = "PH5", "PH6"; ++ function = "uart2"; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2_rts_cts_pins: uart2-rts-cts-pins { ++ pins = "PH7", "PH8"; ++ function = "uart2"; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5_pins: uart5-pins { ++ pins = "PH2", "PH3"; ++ function = "uart5"; ++ }; ++ + /omit-if-no-ref/ + x32clk_fanout_pin: x32clk-fanout-pin { + pins = "PG10"; +@@ -630,6 +666,35 @@ + }; + }; + ++ emac1: ethernet@5030000 { ++ compatible = "allwinner,sunxi-gmac"; ++ reg = <0x05030000 0x10000>, ++ <0x03000034 0x4>; ++ reg-names = "gmac1_reg","ephy_reg"; ++ interrupts = ; ++ interrupt-names = "gmacirq"; ++ resets = <&ccu RST_BUS_EMAC1>; ++ reset-names = "stmmaceth"; ++ clocks = <&ccu CLK_BUS_EMAC1>,<&ccu CLK_EMAC_25M>; ++ clock-names = "bus-emac1","emac-25m"; ++ pinctrl-0 = <&rmii_pins>; ++ pinctrl-names = "default"; ++ phy-mode = "rmii"; ++ tx-delay = <7>; ++ rx-delay = <31>; ++ phy-rst; ++ gmac-power0; ++ gmac-power1; ++ gmac-power2; ++ status = "disabled"; ++ ++ mdio1: mdio { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; ++ + spdif: spdif@5093000 { + compatible = "allwinner,sun50i-h616-spdif"; + reg = <0x05093000 0x400>; +-- +2.35.3 + diff --git a/patch/u-boot/v2025.01/board_bananapim4berry/0003-dts-upstream-arm64-Add-sun50i-h618-bananapi-m4-berry.patch b/patch/u-boot/v2025.01/board_bananapim4berry/0003-dts-upstream-arm64-Add-sun50i-h618-bananapi-m4-berry.patch new file mode 100644 index 000000000000..ab439f5f3c48 --- /dev/null +++ b/patch/u-boot/v2025.01/board_bananapim4berry/0003-dts-upstream-arm64-Add-sun50i-h618-bananapi-m4-berry.patch @@ -0,0 +1,458 @@ +From 505d989ac115c9efe43742fe3fba557c271e944b Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Sat, 25 Jan 2025 19:30:16 +0300 +Subject: [PATCH 3/6] dts: upstream: arm64: Add + sun50i-h618-bananapi-m4-berry.dts + +--- + .../sun50i-h618-bananapi-m4-berry.dts | 438 ++++++++++++++++++ + 1 file changed, 438 insertions(+) + create mode 100644 dts/upstream/src/arm64/allwinner/sun50i-h618-bananapi-m4-berry.dts + +diff --git a/dts/upstream/src/arm64/allwinner/sun50i-h618-bananapi-m4-berry.dts b/dts/upstream/src/arm64/allwinner/sun50i-h618-bananapi-m4-berry.dts +new file mode 100644 +index 00000000000..95280c81056 +--- /dev/null ++++ b/dts/upstream/src/arm64/allwinner/sun50i-h618-bananapi-m4-berry.dts +@@ -0,0 +1,438 @@ ++// SPDX-License-Identifier: (GPL-2.0+ or MIT) ++/* ++ * Copyright (C) 2020 Arm Ltd. ++ */ ++ ++/dts-v1/; ++ ++#include "sun50i-h616.dtsi" ++#include "sun50i-h616-cpu-opp.dtsi" ++ ++#include ++#include ++#include ++ ++/ { ++ model = "BananaPi M4 Berry"; ++ compatible = "BiPai,bananapi-m4berry", "allwinner,sun50i-h616"; ++ ++ aliases { ++ ethernet0 = &emac0; ++ ethernet1 = &emac1; ++ serial0 = &uart0; ++ serial5 = &uart5; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ leds: leds { ++ compatible = "gpio-leds"; ++ ++ led-greed { ++ label = "red_led"; ++ gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */ ++ linux,default-trigger = "heartbeat"; ++ }; ++ }; ++ ++ wifi_usb { ++ compatible = "usb-wifi"; ++ status = "okay"; ++ power_on_pin = <&pio 2 2 GPIO_ACTIVE_HIGH>; /* PC2 */ ++ }; ++ ++ reg_vcc5v: reg-vcc5v { ++ /* board wide 5V supply directly from the USB-C socket */ ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-5v"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ reg_usb1_vbus: reg-usb1-vbus { ++ /* separate discrete regulator for the USB ports */ ++ compatible = "regulator-fixed"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <®_vcc5v>; ++ }; ++ ++ reg_gmac_3v3: reg-gmac-3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "gmac-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ vin-supply = <®_vcc5v>; ++ }; ++ ++ ac200_pwm_clk: ac200_clk { ++ compatible = "pwm-clock"; ++ #clock-cells = <0>; ++ // pwm5 period_ns = 500 > 334 for select 24M clock. ++ pwms = <&pwm 5 500 0>; ++ clock-frequency = <2000000>; ++ status = "okay"; ++ }; ++ ++ soc { ++ pwm: pwm@300a000 { ++ compatible = "allwinner,sun50i-h616-pwm"; ++ reg = <0x0300a000 0x400>; ++ clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; ++ clock-names = "mod", "bus"; ++ resets = <&ccu RST_BUS_PWM>; ++ pwm-number = <6>; ++ pwm-base = <0x0>; ++ sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>, <&pwm3>, <&pwm4>, <&pwm5>; ++ #pwm-cells = <3>; ++ status = "okay"; ++ }; ++ ++ pwm0: pwm0@0300a000 { ++ compatible = "allwinner,sunxi-pwm0"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm0_pd_pin>; ++ }; ++ ++ pwm1: pwm1@0300a000 { ++ compatible = "allwinner,sunxi-pwm1"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm1_ph_pin>; ++ }; ++ ++ pwm2: pwm2@0300a000 { ++ compatible = "allwinner,sunxi-pwm2"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm2_ph_pin>; ++ }; ++ ++ pwm3: pwm3@0300a000 { ++ compatible = "allwinner,sunxi-pwm3"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm3_ph_pin>; ++ }; ++ ++ pwm4: pwm4@0300a000 { ++ compatible = "allwinner,sunxi-pwm4"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm4_ph_pin>; ++ }; ++ ++ pwm5: pwm5@0300a000 { ++ compatible = "allwinner,sunxi-pwm5"; ++ reg = <0x0 0x0300a015 0x0 0x4>; ++ reg_base = <0x0300a000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm5_pin>; ++ clk_bypass_output = <0x1>; ++ status = "okay"; ++ }; ++ }; ++}; ++ ++&pio { ++ vcc-pc-supply = <®_aldo1>; ++ vcc-pf-supply = <®_dldo1>; ++ vcc-pg-supply = <®_dldo1>; ++ vcc-ph-supply = <®_dldo1>; ++ vcc-pi-supply = <®_dldo1>; ++ ++ /omit-if-no-ref/ ++ pwm0_pd_pin: pwm0-pd-pin { ++ pins = "PD28"; ++ function = "pwm0"; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1_pg_pin: pwm1-pg-pin { ++ pins = "PG19"; ++ function = "pwm1"; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm1_ph_pin: pwm1-ph-pin { ++ pins = "PH3"; ++ function = "pwm1"; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm2_ph_pin: pwm2-ph-pin { ++ pins = "PH2"; ++ function = "pwm2"; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm3_ph_pin: pwm3-ph-pin { ++ pins = "PH0"; ++ function = "pwm3"; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm4_ph_pin: pwm4-ph-pin { ++ pins = "PH1"; ++ function = "pwm4"; ++ }; ++ ++ /omit-if-no-ref/ ++ pwm5_pin: pwm5-pin { ++ pins = "PA12"; ++ function = "pwm5"; ++ }; ++}; ++ ++&r_i2c { ++ pinctrl-0 = <&r_i2c_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ axp313a: pmic@36 { ++ compatible = "x-powers,axp313a"; ++ reg = <0x36>; ++ ++ vin1-supply = <®_vcc5v>; ++ vin2-supply = <®_vcc5v>; ++ vin3-supply = <®_vcc5v>; ++ ++ regulators{ ++ reg_dcdc1: dcdc1 { ++ regulator-name = "dcdc1-gpu"; ++ regulator-min-microvolt = <810000>; ++ regulator-max-microvolt = <990000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-always-on; ++ }; ++ ++ reg_dcdc2: dcdc2 { ++ regulator-name = "dcdc2-cpu"; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1200000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-ramp-delay = <200>; ++ regulator-always-on; ++ }; ++ ++ reg_dcdc3: dcdc3 { ++ regulator-name = "dcdc3-dram"; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-always-on; ++ }; ++ ++ reg_aldo1: aldo1 { ++ regulator-name = "aldo1-1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-always-on; ++ }; ++ ++ reg_dldo1: dldo1 { ++ regulator-name = "dldo1-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-step-delay-us = <25>; ++ regulator-final-delay-us = <50>; ++ regulator-always-on; ++ }; ++ }; ++ }; ++}; ++ ++&emac0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ext_rgmii_pins>; ++ phy-mode = "rgmii"; ++ phy-handle = <&ext_rgmii_phy>; ++ allwinner,rx-delay-ps = <3100>; ++ allwinner,tx-delay-ps = <700>; ++ status = "disabled"; ++}; ++ ++&mdio0 { ++ ext_rgmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ }; ++}; ++ ++&emac1 { ++ phy-mode = "rmii"; ++ phy-handle = <&rmii_phy>; ++ phy-supply = <®_dldo1>; ++ allwinner,rx-delay-ps = <3100>; ++ allwinner,tx-delay-ps = <700>; ++ status = "disabled"; ++}; ++ ++&mdio1 { ++ rmii_phy: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <1>; ++ }; ++}; ++ ++&mmc0 { ++ vmmc-supply = <®_dldo1>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ ++ bus-width = <4>; ++ max-frequency = <50000000>; ++ status = "okay"; ++}; ++ ++&mmc2 { ++ pinctrl-names = "default"; ++ ++ vmmc-supply = <®_dldo1>; ++ bus-width = <8>; ++ non-removable; ++ cap-mmc-hw-reset; ++ status = "okay"; ++}; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_ph_pins>; ++ status = "okay"; ++}; ++ ++&usbotg { ++ /* ++ * PHY0 pins are connected to a USB-C socket, but a role switch ++ * is not implemented: both CC pins are pulled to GND. ++ * The VBUS pins power the device, so a fixed peripheral mode ++ * is the best choice. ++ * The board can be powered via GPIOs, in this case port0 *can* ++ * act as a host (with a cable/adapter ignoring CC), as VBUS is ++ * then provided by the GPIOs. Any user of this setup would ++ * need to adjust the DT accordingly: dr_mode set to "host", ++ * enabling OHCI0 and EHCI0. ++ */ ++ dr_mode = "peripheral"; ++ status = "okay"; ++}; ++ ++&usbphy { ++ usb1_vbus-supply = <®_vcc5v>; ++ status = "okay"; ++}; ++ ++&ehci0 { ++ status = "disabled"; ++}; ++ ++&ehci1 { ++ status = "okay"; ++}; ++ ++&ehci2 { ++ status = "okay"; ++}; ++ ++&ehci3 { ++ status = "okay"; ++}; ++ ++&ohci0 { ++ status = "disabled"; ++}; ++ ++&ohci1 { ++ status = "okay"; ++}; ++ ++&ohci2 { ++ status = "okay"; ++}; ++ ++&ohci3 { ++ status = "okay"; ++}; ++ ++&ir { ++ status = "disabled"; ++}; ++ ++&i2c1 { ++ status = "disabled"; ++}; ++ ++&i2c2 { ++ status = "disabled"; ++}; ++ ++&i2c3 { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pa_pins>; ++ ++ ac200_x: mfd@10 { ++ compatible = "x-powers,ac200-sunxi"; ++ reg = <0x10>; ++ clocks = <&ac200_pwm_clk>; ++ // ephy id ++ nvmem-cells = <&ephy_calibration>; ++ nvmem-cell-names = "calibration"; ++ ++ ac200_ephy: phy { ++ compatible = "x-powers,ac200-ephy-sunxi"; ++ status = "okay"; ++ }; ++ }; ++}; ++ ++&i2c4 { ++ status = "disabled"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; ++ status = "disabled"; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart2_pins>; ++ status = "disabled"; ++}; ++ ++&uart5 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart5_pins>; ++ status = "okay"; ++}; ++ ++&spi1 { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins>, <&spi1_cs1_pin>; ++ ++ spidev@1 { ++ compatible = "rohm,dh2228fv"; ++ status = "okay"; ++ reg = <1>; ++ spi-max-frequency = <1000000>; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <®_dcdc2>; ++ status = "okay"; ++}; ++ ++&sid { ++ ephy_calibration: ephy-calibration@2c { ++ reg = <0x2c 0x2>; ++ }; ++}; +-- +2.35.3 + diff --git a/patch/u-boot/v2025.01/board_bananapim4berry/0004-u-boot-v2025-DEBUG-sunxi-mmc-fix-logik.patch b/patch/u-boot/v2025.01/board_bananapim4berry/0004-u-boot-v2025-DEBUG-sunxi-mmc-fix-logik.patch new file mode 100644 index 000000000000..5fcdad4a4b50 --- /dev/null +++ b/patch/u-boot/v2025.01/board_bananapim4berry/0004-u-boot-v2025-DEBUG-sunxi-mmc-fix-logik.patch @@ -0,0 +1,72 @@ +From 783a11dad0e9c049e12efebbbd876703002ff992 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Fri, 21 Feb 2025 14:21:13 +0300 +Subject: [PATCH 4/6] u-boot: v2025: DEBUG sunxi mmc fix logik + +--- + drivers/mmc/sunxi_mmc.c | 18 +++++++++++++----- + 1 file changed, 13 insertions(+), 5 deletions(-) + +diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c +index 0b56d1405be..78814ecd50b 100644 +--- a/drivers/mmc/sunxi_mmc.c ++++ b/drivers/mmc/sunxi_mmc.c +@@ -36,6 +36,8 @@ + #define CCM_MMC_CTRL_MODE_SEL_NEW 0 + #endif + ++#define DEBUG 1 ++ + struct sunxi_mmc_plat { + struct mmc_config cfg; + struct mmc mmc; +@@ -61,6 +63,7 @@ static bool sunxi_mmc_can_calibrate(void) + IS_ENABLED(CONFIG_MACH_SUN50I_H5) || + IS_ENABLED(CONFIG_SUN50I_GEN_H6) || + IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) || ++ IS_ENABLED(CONFIG_MACH_SUN8I_A83T) || + IS_ENABLED(CONFIG_MACH_SUN8I_R40); + } + +@@ -639,20 +642,25 @@ static int sunxi_mmc_probe(struct udevice *dev) + struct mmc_config *cfg = &plat->cfg; + struct ofnode_phandle_args args; + u32 *ccu_reg; +- int ret; ++ int ret, bus_width; + + cfg->name = dev->name; ++ bus_width = dev_read_u32_default(dev, "bus-width", 1); + + cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; ++ cfg->host_caps = 0; ++ if (bus_width == 8) ++ cfg->host_caps |= MMC_MODE_8BIT; ++ if (bus_width >= 4) ++ cfg->host_caps |= MMC_MODE_4BIT; + cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS; + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + + cfg->f_min = 400000; + cfg->f_max = 52000000; + +- ret = mmc_of_parse(dev, cfg); +- if (ret) +- return ret; ++ if (bus_width == 8) ++ cfg->f_max = 52000000; + + priv->reg = dev_read_addr_ptr(dev); + +@@ -686,7 +694,7 @@ static int sunxi_mmc_probe(struct udevice *dev) + + /* Reset controller */ + writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl); +- udelay(1000); ++ udelay(2000); + + return 0; + } +-- +2.35.3 + diff --git a/patch/u-boot/v2025.01/board_bananapim4berry/0005-h616-THS-workaround.patch b/patch/u-boot/v2025.01/board_bananapim4berry/0005-h616-THS-workaround.patch new file mode 100644 index 000000000000..26326e908f85 --- /dev/null +++ b/patch/u-boot/v2025.01/board_bananapim4berry/0005-h616-THS-workaround.patch @@ -0,0 +1,32 @@ +From f6e223575f0f74e008e4688a58600eda615460e2 Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Thu, 6 Feb 2025 14:00:06 +0300 +Subject: [PATCH 5/6] h616: THS workaround + +--- + board/sunxi/board.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/board/sunxi/board.c b/board/sunxi/board.c +index 824c322a0dc..981f406aeea 100644 +--- a/board/sunxi/board.c ++++ b/board/sunxi/board.c +@@ -227,6 +227,15 @@ int board_init(void) + + eth_init_board(); + ++#if CONFIG_MACH_SUN50I_H616 ++ /* ++ * The bit[16] of register reg[0x03000000] must be zero for the THS ++ * driver to work properly in the kernel. The BSP u-boot is putting ++ * the whole register to zero so we are doing the same. ++ */ ++ writel(0x0, SUNXI_SRAMC_BASE); ++#endif ++ + return 0; + } + +-- +2.35.3 + diff --git a/patch/u-boot/v2025.01/board_bananapim4berry/0006-h616-GPU-enable.-Magic-register.patch b/patch/u-boot/v2025.01/board_bananapim4berry/0006-h616-GPU-enable.-Magic-register.patch new file mode 100644 index 000000000000..a4bb594e836b --- /dev/null +++ b/patch/u-boot/v2025.01/board_bananapim4berry/0006-h616-GPU-enable.-Magic-register.patch @@ -0,0 +1,25 @@ +From d2a852603b364b90903dc0a9040d4b11f79b8fea Mon Sep 17 00:00:00 2001 +From: The-going <48602507+The-going@users.noreply.github.com> +Date: Thu, 6 Feb 2025 15:11:40 +0300 +Subject: [PATCH 6/6] h616: GPU enable. Magic register. + +--- + arch/arm/mach-sunxi/clock_sun50i_h6.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c +index b424a7893ea..9ed5852d547 100644 +--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c ++++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c +@@ -15,6 +15,8 @@ void clock_init_safe(void) + /* this seems to enable PLLs on H616 */ + setbits_le32(&prcm->sys_pwroff_gating, 0x10); + setbits_le32(&prcm->res_cal_ctrl, 2); ++ /* enable GPU */ ++ writel(0, 0x7010254); + } + + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) || +-- +2.35.3 +