From d510f741e4230ad00832e0eea6bbdda4fbb8a002 Mon Sep 17 00:00:00 2001 From: hzy Date: Tue, 31 Jan 2023 02:00:18 +0800 Subject: [PATCH] meson: remove legacy branch --- config/boards/odroidc1.eos | 2 +- config/boards/onecloud.csc | 2 +- config/kernel/linux-meson-legacy.config | 7153 ----------------- .../sources/families/include/meson_common.inc | 7 - ...-clock-speed-before-sending-HS-CMD13.patch | 73 - .../board_odroidc1/dts-Enable-HDMI.patch | 57 - .../board_onecloud/0001-add-dts.patch | 431 - .../0002-dts-Support-HDMI.patch | 92 - .../usb-disable-ACA-check.patch | 32 - .../generate-uImage-instand-of-zImage.patch | 27 - .../meson-5.10/m8-m8b-m8m2-Support-HDMI.patch | 5177 ------------ patch/kernel/meson-legacy | 1 - 12 files changed, 2 insertions(+), 13052 deletions(-) delete mode 100644 config/kernel/linux-meson-legacy.config delete mode 100644 patch/kernel/archive/meson-5.10/Revert-mmc-core-Set-HS-clock-speed-before-sending-HS-CMD13.patch delete mode 100644 patch/kernel/archive/meson-5.10/board_odroidc1/dts-Enable-HDMI.patch delete mode 100644 patch/kernel/archive/meson-5.10/board_onecloud/0001-add-dts.patch delete mode 100644 patch/kernel/archive/meson-5.10/board_onecloud/0002-dts-Support-HDMI.patch delete mode 100644 patch/kernel/archive/meson-5.10/board_onecloud/usb-disable-ACA-check.patch delete mode 100644 patch/kernel/archive/meson-5.10/generate-uImage-instand-of-zImage.patch delete mode 100644 patch/kernel/archive/meson-5.10/m8-m8b-m8m2-Support-HDMI.patch delete mode 120000 patch/kernel/meson-legacy diff --git a/config/boards/odroidc1.eos b/config/boards/odroidc1.eos index 8aee9a8f929f..1c438c4ca4b4 100644 --- a/config/boards/odroidc1.eos +++ b/config/boards/odroidc1.eos @@ -1,7 +1,7 @@ # Amlogic S805 C1 quad core 1GB RAM SoC GBE BOARD_NAME="Odroid C1" BOARDFAMILY="meson8b" -KERNEL_TARGET="legacy,current,edge" +KERNEL_TARGET="current,edge" BOOTCONFIG="odroidc_config" BOOTSCRIPT="boot-odroid-c1.ini:boot.ini" diff --git a/config/boards/onecloud.csc b/config/boards/onecloud.csc index 9f857054af47..eb6f0f5c72c7 100644 --- a/config/boards/onecloud.csc +++ b/config/boards/onecloud.csc @@ -1,7 +1,7 @@ # Amlogic S805 quad core 1GB RAM SoC GBE BOARD_NAME="OneCloud" BOARDFAMILY="meson8b" -KERNEL_TARGET="legacy,current,edge" +KERNEL_TARGET="current,edge" BOOTCONFIG="none" BOOTSCRIPT="boot-onecloud.cmd:boot.cmd" diff --git a/config/kernel/linux-meson-legacy.config b/config/kernel/linux-meson-legacy.config deleted file mode 100644 index a8b07f223800..000000000000 --- a/config/kernel/linux-meson-legacy.config +++ /dev/null @@ -1,7153 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Linux/arm 5.10.155 Kernel Configuration -# -CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0" -CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=80300 -CONFIG_LD_VERSION=232000000 -CONFIG_CLANG_VERSION=0 -CONFIG_LLD_VERSION=0 -CONFIG_CC_CAN_LINK=y -CONFIG_CC_CAN_LINK_STATIC=y -CONFIG_CC_HAS_ASM_GOTO=y -CONFIG_CC_HAS_ASM_INLINE=y -CONFIG_IRQ_WORK=y -CONFIG_BUILDTIME_TABLE_SORT=y - -# -# General setup -# -CONFIG_INIT_ENV_ARG_LIMIT=32 -# CONFIG_COMPILE_TEST is not set -CONFIG_LOCALVERSION="" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_BUILD_SALT="" -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_LZMA=y -CONFIG_HAVE_KERNEL_XZ=y -CONFIG_HAVE_KERNEL_LZO=y -CONFIG_HAVE_KERNEL_LZ4=y -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_LZMA is not set -# CONFIG_KERNEL_XZ is not set -# CONFIG_KERNEL_LZO is not set -# CONFIG_KERNEL_LZ4 is not set -CONFIG_DEFAULT_INIT="" -CONFIG_DEFAULT_HOSTNAME="(none)" -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -CONFIG_POSIX_MQUEUE=y -CONFIG_POSIX_MQUEUE_SYSCTL=y -CONFIG_WATCH_QUEUE=y -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_USELIB=y -CONFIG_AUDIT=y -CONFIG_HAVE_ARCH_AUDITSYSCALL=y -CONFIG_AUDITSYSCALL=y - -# -# IRQ subsystem -# -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_GENERIC_IRQ_CHIP=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_GENERIC_IRQ_IPI=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_HANDLE_DOMAIN_IRQ=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_SPARSE_IRQ=y -# CONFIG_GENERIC_IRQ_DEBUGFS is not set -# end of IRQ subsystem - -CONFIG_GENERIC_IRQ_MULTI_HANDLER=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_ARCH_HAS_TICK_BROADCAST=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y - -# -# Timers subsystem -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ_COMMON=y -# CONFIG_HZ_PERIODIC is not set -CONFIG_NO_HZ_IDLE=y -# CONFIG_NO_HZ_FULL is not set -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -# end of Timers subsystem - -CONFIG_PREEMPT_NONE=y -# CONFIG_PREEMPT_VOLUNTARY is not set -# CONFIG_PREEMPT is not set - -# -# CPU/Task time and stats accounting -# -CONFIG_TICK_CPU_ACCOUNTING=y -# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set -CONFIG_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_SCHED_AVG_IRQ=y -CONFIG_SCHED_THERMAL_PRESSURE=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_TASKSTATS=y -CONFIG_TASK_DELAY_ACCT=y -CONFIG_TASK_XACCT=y -CONFIG_TASK_IO_ACCOUNTING=y -# CONFIG_PSI is not set -# end of CPU/Task time and stats accounting - -CONFIG_CPU_ISOLATION=y - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_RCU_EXPERT is not set -CONFIG_SRCU=y -CONFIG_TREE_SRCU=y -CONFIG_TASKS_RCU_GENERIC=y -CONFIG_TASKS_TRACE_RCU=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_RCU_NEED_SEGCBLIST=y -# end of RCU Subsystem - -CONFIG_IKCONFIG=m -CONFIG_IKCONFIG_PROC=y -# CONFIG_IKHEADERS is not set -CONFIG_LOG_BUF_SHIFT=17 -CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 -CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 -CONFIG_GENERIC_SCHED_CLOCK=y - -# -# Scheduler features -# -# CONFIG_UCLAMP_TASK is not set -# end of Scheduler features - -CONFIG_CGROUPS=y -CONFIG_PAGE_COUNTER=y -CONFIG_MEMCG=y -CONFIG_MEMCG_SWAP=y -CONFIG_MEMCG_KMEM=y -CONFIG_BLK_CGROUP=y -CONFIG_CGROUP_WRITEBACK=y -CONFIG_CGROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -CONFIG_CFS_BANDWIDTH=y -CONFIG_RT_GROUP_SCHED=y -CONFIG_CGROUP_PIDS=y -CONFIG_CGROUP_RDMA=y -CONFIG_CGROUP_FREEZER=y -CONFIG_CPUSETS=y -CONFIG_PROC_PID_CPUSET=y -CONFIG_CGROUP_DEVICE=y -CONFIG_CGROUP_CPUACCT=y -CONFIG_CGROUP_PERF=y -CONFIG_CGROUP_BPF=y -CONFIG_CGROUP_DEBUG=y -CONFIG_SOCK_CGROUP_DATA=y -CONFIG_NAMESPACES=y -CONFIG_UTS_NS=y -CONFIG_IPC_NS=y -CONFIG_USER_NS=y -CONFIG_PID_NS=y -CONFIG_NET_NS=y -# CONFIG_CHECKPOINT_RESTORE is not set -# CONFIG_SCHED_AUTOGROUP is not set -# CONFIG_SYSFS_DEPRECATED is not set -CONFIG_RELAY=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -CONFIG_RD_BZIP2=y -CONFIG_RD_LZMA=y -CONFIG_RD_XZ=y -CONFIG_RD_LZO=y -CONFIG_RD_LZ4=y -CONFIG_RD_ZSTD=y -# CONFIG_BOOT_CONFIG is not set -CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_LD_ORPHAN_WARN=y -CONFIG_SYSCTL=y -CONFIG_HAVE_UID16=y -CONFIG_BPF=y -CONFIG_EXPERT=y -CONFIG_UID16=y -CONFIG_MULTIUSER=y -# CONFIG_SGETMASK_SYSCALL is not set -CONFIG_SYSFS_SYSCALL=y -CONFIG_FHANDLE=y -CONFIG_POSIX_TIMERS=y -CONFIG_PRINTK=y -CONFIG_PRINTK_NMI=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_FUTEX_PI=y -CONFIG_HAVE_FUTEX_CMPXCHG=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y -CONFIG_IO_URING=y -CONFIG_ADVISE_SYSCALLS=y -CONFIG_MEMBARRIER=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_ALL is not set -CONFIG_KALLSYMS_BASE_RELATIVE=y -CONFIG_BPF_SYSCALL=y -# CONFIG_BPF_JIT_ALWAYS_ON is not set -CONFIG_BPF_UNPRIV_DEFAULT_OFF=y -CONFIG_USERMODE_DRIVER=y -# CONFIG_BPF_PRELOAD is not set -# CONFIG_USERFAULTFD is not set -CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y -CONFIG_KCMP=y -CONFIG_RSEQ=y -# CONFIG_DEBUG_RSEQ is not set -CONFIG_EMBEDDED=y -CONFIG_HAVE_PERF_EVENTS=y -CONFIG_PERF_USE_VMALLOC=y -# CONFIG_PC104 is not set - -# -# Kernel Performance Events And Counters -# -CONFIG_PERF_EVENTS=y -# CONFIG_DEBUG_PERF_USE_VMALLOC is not set -# end of Kernel Performance Events And Counters - -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLUB_DEBUG=y -# CONFIG_SLUB_MEMCG_SYSFS_ON is not set -CONFIG_COMPAT_BRK=y -# CONFIG_SLAB is not set -CONFIG_SLUB=y -# CONFIG_SLOB is not set -CONFIG_SLAB_MERGE_DEFAULT=y -# CONFIG_SLAB_FREELIST_RANDOM is not set -# CONFIG_SLAB_FREELIST_HARDENED is not set -# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set -CONFIG_SLUB_CPU_PARTIAL=y -CONFIG_SYSTEM_DATA_VERIFICATION=y -# CONFIG_PROFILING is not set -CONFIG_TRACEPOINTS=y -# end of General setup - -CONFIG_ARM=y -CONFIG_ARM_HAS_SG_CHAIN=y -CONFIG_SYS_SUPPORTS_APM_EMULATION=y -CONFIG_HAVE_PROC_CPU=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_ARM_PATCH_PHYS_VIRT=y -CONFIG_GENERIC_BUG=y -CONFIG_PGTABLE_LEVELS=2 - -# -# System Type -# -CONFIG_MMU=y -CONFIG_ARCH_MMAP_RND_BITS_MIN=8 -CONFIG_ARCH_MMAP_RND_BITS_MAX=16 -CONFIG_ARCH_MULTIPLATFORM=y -# CONFIG_ARCH_EBSA110 is not set -# CONFIG_ARCH_EP93XX is not set -# CONFIG_ARCH_FOOTBRIDGE is not set -# CONFIG_ARCH_IOP32X is not set -# CONFIG_ARCH_IXP4XX is not set -# CONFIG_ARCH_DOVE is not set -# CONFIG_ARCH_PXA is not set -# CONFIG_ARCH_RPC is not set -# CONFIG_ARCH_SA1100 is not set -# CONFIG_ARCH_S3C24XX is not set -# CONFIG_ARCH_OMAP1 is not set - -# -# Multiple platform selection -# - -# -# CPU Core family selection -# -# CONFIG_ARCH_MULTI_V6 is not set -CONFIG_ARCH_MULTI_V7=y -CONFIG_ARCH_MULTI_V6_V7=y -# end of Multiple platform selection - -# CONFIG_ARCH_VIRT is not set -# CONFIG_ARCH_ACTIONS is not set -# CONFIG_ARCH_ALPINE is not set -# CONFIG_ARCH_ARTPEC is not set -# CONFIG_ARCH_ASPEED is not set -# CONFIG_ARCH_AT91 is not set -# CONFIG_ARCH_BCM is not set -# CONFIG_ARCH_BERLIN is not set -# CONFIG_ARCH_DIGICOLOR is not set -# CONFIG_ARCH_EXYNOS is not set -# CONFIG_ARCH_HIGHBANK is not set -# CONFIG_ARCH_HISI is not set -# CONFIG_ARCH_MXC is not set -# CONFIG_ARCH_KEYSTONE is not set -# CONFIG_ARCH_MEDIATEK is not set -CONFIG_ARCH_MESON=y -CONFIG_MACH_MESON6=y -CONFIG_MACH_MESON8=y -# CONFIG_ARCH_MILBEAUT is not set -# CONFIG_ARCH_MMP is not set -# CONFIG_ARCH_MSTARV7 is not set -# CONFIG_ARCH_MVEBU is not set -# CONFIG_ARCH_NPCM is not set - -# -# TI OMAP/AM/DM/DRA Family -# -# CONFIG_ARCH_OMAP3 is not set -# CONFIG_ARCH_OMAP4 is not set -# CONFIG_SOC_OMAP5 is not set -# CONFIG_SOC_AM33XX is not set -# CONFIG_SOC_AM43XX is not set -# CONFIG_SOC_DRA7XX is not set -# end of TI OMAP/AM/DM/DRA Family - -# CONFIG_ARCH_SIRF is not set -# CONFIG_ARCH_QCOM is not set -# CONFIG_ARCH_RDA is not set -# CONFIG_ARCH_REALTEK is not set -# CONFIG_ARCH_REALVIEW is not set -# CONFIG_ARCH_ROCKCHIP is not set -# CONFIG_ARCH_S5PV210 is not set -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_SOCFPGA is not set -# CONFIG_PLAT_SPEAR is not set -# CONFIG_ARCH_STI is not set -# CONFIG_ARCH_STM32 is not set -# CONFIG_ARCH_SUNXI is not set -# CONFIG_ARCH_TANGO is not set -# CONFIG_ARCH_TEGRA is not set -# CONFIG_ARCH_UNIPHIER is not set -# CONFIG_ARCH_U8500 is not set -# CONFIG_ARCH_VEXPRESS is not set -# CONFIG_ARCH_WM8850 is not set -# CONFIG_ARCH_ZX is not set -# CONFIG_ARCH_ZYNQ is not set - -# -# Processor Type -# -CONFIG_CPU_V7=y -CONFIG_CPU_THUMB_CAPABLE=y -CONFIG_CPU_32v6K=y -CONFIG_CPU_32v7=y -CONFIG_CPU_ABRT_EV7=y -CONFIG_CPU_PABRT_V7=y -CONFIG_CPU_CACHE_V7=y -CONFIG_CPU_CACHE_VIPT=y -CONFIG_CPU_COPY_V6=y -CONFIG_CPU_TLB_V7=y -CONFIG_CPU_HAS_ASID=y -CONFIG_CPU_CP15=y -CONFIG_CPU_CP15_MMU=y - -# -# Processor Features -# -# CONFIG_ARM_LPAE is not set -CONFIG_ARM_THUMB=y -CONFIG_ARM_THUMBEE=y -CONFIG_ARM_VIRT_EXT=y -CONFIG_SWP_EMULATE=y -# CONFIG_CPU_ICACHE_DISABLE is not set -# CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set -# CONFIG_CPU_BPREDICT_DISABLE is not set -CONFIG_CPU_SPECTRE=y -CONFIG_HARDEN_BRANCH_PREDICTOR=y -CONFIG_HARDEN_BRANCH_HISTORY=y -CONFIG_KUSER_HELPERS=y -CONFIG_VDSO=y -CONFIG_OUTER_CACHE=y -CONFIG_OUTER_CACHE_SYNC=y -CONFIG_MIGHT_HAVE_CACHE_L2X0=y -CONFIG_CACHE_L2X0=y -# CONFIG_CACHE_L2X0_PMU is not set -CONFIG_PL310_ERRATA_588369=y -CONFIG_PL310_ERRATA_727915=y -CONFIG_PL310_ERRATA_753970=y -CONFIG_PL310_ERRATA_769419=y -CONFIG_ARM_L1_CACHE_SHIFT_6=y -CONFIG_ARM_L1_CACHE_SHIFT=6 -CONFIG_ARM_DMA_MEM_BUFFERABLE=y -CONFIG_ARM_HEAVY_MB=y -CONFIG_DEBUG_ALIGN_RODATA=y -# CONFIG_ARM_ERRATA_430973 is not set -# CONFIG_ARM_ERRATA_643719 is not set -# CONFIG_ARM_ERRATA_720789 is not set -# CONFIG_ARM_ERRATA_754322 is not set -# CONFIG_ARM_ERRATA_754327 is not set -# CONFIG_ARM_ERRATA_764369 is not set -# CONFIG_ARM_ERRATA_775420 is not set -# CONFIG_ARM_ERRATA_798181 is not set -# CONFIG_ARM_ERRATA_773022 is not set -# CONFIG_ARM_ERRATA_818325_852422 is not set -# CONFIG_ARM_ERRATA_821420 is not set -# CONFIG_ARM_ERRATA_825619 is not set -# CONFIG_ARM_ERRATA_857271 is not set -# CONFIG_ARM_ERRATA_852421 is not set -# CONFIG_ARM_ERRATA_852423 is not set -# CONFIG_ARM_ERRATA_857272 is not set -# end of System Type - -# -# Bus support -# -CONFIG_ARM_ERRATA_814220=y -# end of Bus support - -# -# Kernel Features -# -CONFIG_HAVE_SMP=y -CONFIG_SMP=y -CONFIG_SMP_ON_UP=y -CONFIG_ARM_CPU_TOPOLOGY=y -# CONFIG_SCHED_MC is not set -# CONFIG_SCHED_SMT is not set -CONFIG_HAVE_ARM_SCU=y -CONFIG_HAVE_ARM_ARCH_TIMER=y -CONFIG_HAVE_ARM_TWD=y -CONFIG_MCPM=y -# CONFIG_BIG_LITTLE is not set -CONFIG_VMSPLIT_3G=y -# CONFIG_VMSPLIT_3G_OPT is not set -# CONFIG_VMSPLIT_2G is not set -# CONFIG_VMSPLIT_1G is not set -CONFIG_PAGE_OFFSET=0xC0000000 -CONFIG_NR_CPUS=16 -CONFIG_HOTPLUG_CPU=y -CONFIG_ARM_PSCI=y -CONFIG_ARCH_NR_GPIO=0 -CONFIG_HZ_FIXED=0 -CONFIG_HZ_100=y -# CONFIG_HZ_200 is not set -# CONFIG_HZ_250 is not set -# CONFIG_HZ_300 is not set -# CONFIG_HZ_500 is not set -# CONFIG_HZ_1000 is not set -CONFIG_HZ=100 -CONFIG_SCHED_HRTICK=y -# CONFIG_THUMB2_KERNEL is not set -CONFIG_ARM_PATCH_IDIV=y -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_HAVE_ARCH_PFN_VALID=y -CONFIG_HIGHMEM=y -CONFIG_HIGHPTE=y -CONFIG_CPU_SW_DOMAIN_PAN=y -CONFIG_HW_PERF_EVENTS=y -CONFIG_ARCH_WANT_GENERAL_HUGETLB=y -CONFIG_ARM_MODULE_PLTS=y -CONFIG_FORCE_MAX_ZONEORDER=12 -CONFIG_ALIGNMENT_TRAP=y -# CONFIG_UACCESS_WITH_MEMCPY is not set -# CONFIG_PARAVIRT is not set -# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set -# CONFIG_XEN is not set -CONFIG_STACKPROTECTOR_PER_TASK=y -# end of Kernel Features - -# -# Boot options -# -CONFIG_USE_OF=y -CONFIG_ATAGS=y -# CONFIG_DEPRECATED_PARAM_STRUCT is not set -CONFIG_ZBOOT_ROM_TEXT=0x0 -CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ATAG_DTB_COMPAT=y -CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y -# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set -CONFIG_CMDLINE="" -CONFIG_KEXEC=y -CONFIG_ATAGS_PROC=y -# CONFIG_CRASH_DUMP is not set -CONFIG_AUTO_ZRELADDR=y -CONFIG_EFI_STUB=y -CONFIG_EFI=y -CONFIG_DMI=y -# end of Boot options - -# -# CPU Power Management -# - -# -# CPU Frequency scaling -# -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y -CONFIG_CPU_FREQ_STAT=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=m -CONFIG_CPU_FREQ_GOV_USERSPACE=m -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y - -# -# CPU frequency scaling drivers -# -CONFIG_CPUFREQ_DT=y -CONFIG_CPUFREQ_DT_PLATDEV=y -# CONFIG_ARM_SCMI_CPUFREQ is not set -# end of CPU Frequency scaling - -# -# CPU Idle -# -CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -# CONFIG_CPU_IDLE_GOV_LADDER is not set -CONFIG_CPU_IDLE_GOV_MENU=y -CONFIG_CPU_IDLE_GOV_TEO=y -CONFIG_DT_IDLE_STATES=y - -# -# ARM CPU Idle Drivers -# -CONFIG_ARM_CPUIDLE=y -# CONFIG_ARM_PSCI_CPUIDLE is not set -# CONFIG_ARM_HIGHBANK_CPUIDLE is not set -# end of ARM CPU Idle Drivers -# end of CPU Idle -# end of CPU Power Management - -# -# Floating point emulation -# - -# -# At least one emulation must be selected -# -CONFIG_VFP=y -CONFIG_VFPv3=y -CONFIG_NEON=y -CONFIG_KERNEL_MODE_NEON=y -# end of Floating point emulation - -# -# Power management options -# -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -# CONFIG_SUSPEND_SKIP_SYNC is not set -# CONFIG_HIBERNATION is not set -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -# CONFIG_PM_AUTOSLEEP is not set -# CONFIG_PM_WAKELOCKS is not set -CONFIG_PM=y -# CONFIG_PM_DEBUG is not set -# CONFIG_APM_EMULATION is not set -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set -CONFIG_PM_GENERIC_DOMAINS_SLEEP=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_CPU_PM=y -# CONFIG_ENERGY_MODEL is not set -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARM_CPU_SUSPEND=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -# end of Power management options - -# -# Firmware Drivers -# -CONFIG_ARM_SCMI_PROTOCOL=m -CONFIG_ARM_SCMI_POWER_DOMAIN=m -# CONFIG_ARM_SCPI_PROTOCOL is not set -# CONFIG_FIRMWARE_MEMMAP is not set -CONFIG_DMIID=y -# CONFIG_DMI_SYSFS is not set -# CONFIG_FW_CFG_SYSFS is not set -# CONFIG_TRUSTED_FOUNDATIONS is not set -# CONFIG_GOOGLE_FIRMWARE is not set - -# -# EFI (Extensible Firmware Interface) Support -# -CONFIG_EFI_ESRT=y -CONFIG_EFI_VARS_PSTORE=m -# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set -CONFIG_EFI_PARAMS_FROM_FDT=y -CONFIG_EFI_RUNTIME_WRAPPERS=y -CONFIG_EFI_GENERIC_STUB=y -CONFIG_EFI_ARMSTUB_DTB_LOADER=y -CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y -CONFIG_EFI_BOOTLOADER_CONTROL=m -CONFIG_EFI_CAPSULE_LOADER=m -# CONFIG_EFI_TEST is not set -# CONFIG_RESET_ATTACK_MITIGATION is not set -# CONFIG_EFI_DISABLE_PCI_DMA is not set -# end of EFI (Extensible Firmware Interface) Support - -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_PSCI_CHECKER is not set -CONFIG_HAVE_ARM_SMCCC=y -CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y -CONFIG_ARM_SMCCC_SOC_ID=y - -# -# Tegra firmware driver -# -# end of Tegra firmware driver -# end of Firmware Drivers - -CONFIG_ARM_CRYPTO=y -CONFIG_CRYPTO_SHA1_ARM=m -CONFIG_CRYPTO_SHA1_ARM_NEON=m -CONFIG_CRYPTO_SHA1_ARM_CE=m -CONFIG_CRYPTO_SHA2_ARM_CE=m -CONFIG_CRYPTO_SHA256_ARM=m -CONFIG_CRYPTO_SHA512_ARM=m -CONFIG_CRYPTO_AES_ARM=m -CONFIG_CRYPTO_AES_ARM_BS=m -CONFIG_CRYPTO_AES_ARM_CE=m -CONFIG_CRYPTO_GHASH_ARM_CE=m -# CONFIG_CRYPTO_CRCT10DIF_ARM_CE is not set -CONFIG_CRYPTO_CRC32_ARM_CE=m -CONFIG_CRYPTO_CHACHA20_NEON=m -CONFIG_CRYPTO_POLY1305_ARM=m -CONFIG_CRYPTO_NHPOLY1305_NEON=m -CONFIG_CRYPTO_CURVE25519_NEON=m -CONFIG_AS_VFP_VMRS_FPINST=y - -# -# General architecture-dependent options -# -CONFIG_CRASH_CORE=y -CONFIG_KEXEC_CORE=y -CONFIG_SET_FS=y -CONFIG_HAVE_OPROFILE=y -CONFIG_KPROBES=y -# CONFIG_JUMP_LABEL is not set -CONFIG_OPTPROBES=y -CONFIG_UPROBES=y -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_KRETPROBES=y -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_OPTPROBES=y -CONFIG_HAVE_NMI=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_ARCH_HAS_FORTIFY_SOURCE=y -CONFIG_ARCH_HAS_KEEPINITRD=y -CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y -CONFIG_ARCH_32BIT_OFF_T=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_RSEQ=y -CONFIG_HAVE_HW_BREAKPOINT=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y -CONFIG_HAVE_ARCH_SECCOMP=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_SECCOMP=y -CONFIG_SECCOMP_FILTER=y -CONFIG_HAVE_STACKPROTECTOR=y -CONFIG_STACKPROTECTOR=y -CONFIG_STACKPROTECTOR_STRONG=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_MODULES_USE_ELF_REL=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_HAVE_ARCH_MMAP_RND_BITS=y -CONFIG_HAVE_EXIT_THREAD=y -CONFIG_ARCH_MMAP_RND_BITS=8 -CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y -CONFIG_CLONE_BACKWARDS=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_OLD_SIGACTION=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y -CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y -CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -CONFIG_STRICT_KERNEL_RWX=y -CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -CONFIG_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAS_PHYS_TO_DMA=y -# CONFIG_LOCK_EVENT_COUNTS is not set -CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -# end of GCOV-based kernel profiling - -CONFIG_HAVE_GCC_PLUGINS=y -CONFIG_GCC_PLUGINS=y -# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set -# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set -# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set -CONFIG_GCC_PLUGIN_ARM_SSP_PER_TASK=y -# end of General architecture-dependent options - -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULE_SIG_FORMAT=y -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_MODULE_SIG=y -# CONFIG_MODULE_SIG_FORCE is not set -CONFIG_MODULE_SIG_ALL=y -CONFIG_MODULE_SIG_SHA1=y -# CONFIG_MODULE_SIG_SHA224 is not set -# CONFIG_MODULE_SIG_SHA256 is not set -# CONFIG_MODULE_SIG_SHA384 is not set -# CONFIG_MODULE_SIG_SHA512 is not set -CONFIG_MODULE_SIG_HASH="sha1" -# CONFIG_MODULE_COMPRESS is not set -# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_TRIM_UNUSED_KSYMS is not set -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_BLOCK=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BLK_CGROUP_RWSTAT=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_BSGLIB=y -CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_BLK_DEV_INTEGRITY_T10=y -# CONFIG_BLK_DEV_ZONED is not set -# CONFIG_BLK_DEV_THROTTLING is not set -CONFIG_BLK_CMDLINE_PARSER=y -# CONFIG_BLK_WBT is not set -# CONFIG_BLK_CGROUP_IOLATENCY is not set -# CONFIG_BLK_CGROUP_IOCOST is not set -CONFIG_BLK_DEBUG_FS=y -# CONFIG_BLK_SED_OPAL is not set -# CONFIG_BLK_INLINE_ENCRYPTION is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_AIX_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -CONFIG_EFI_PARTITION=y -# CONFIG_SYSV68_PARTITION is not set -CONFIG_CMDLINE_PARTITION=y -# end of Partition Types - -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_MQ_VIRTIO=y -CONFIG_BLK_PM=y - -# -# IO Schedulers -# -CONFIG_MQ_IOSCHED_DEADLINE=y -CONFIG_MQ_IOSCHED_KYBER=y -CONFIG_IOSCHED_BFQ=y -CONFIG_BFQ_GROUP_IOSCHED=y -# CONFIG_BFQ_CGROUP_DEBUG is not set -# end of IO Schedulers - -CONFIG_PADATA=y -CONFIG_ASN1=y -CONFIG_INLINE_SPIN_UNLOCK_IRQ=y -CONFIG_INLINE_READ_UNLOCK=y -CONFIG_INLINE_READ_UNLOCK_IRQ=y -CONFIG_INLINE_WRITE_UNLOCK=y -CONFIG_INLINE_WRITE_UNLOCK_IRQ=y -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y -CONFIG_FREEZER=y - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_ELF_FDPIC is not set -CONFIG_ELFCORE=y -CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -CONFIG_BINFMT_SCRIPT=y -CONFIG_ARCH_HAS_BINFMT_FLAT=y -# CONFIG_BINFMT_FLAT is not set -CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y -CONFIG_BINFMT_MISC=m -CONFIG_COREDUMP=y -# end of Executable file formats - -# -# Memory Management options -# -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_ARCH_KEEP_MEMBLOCK=y -CONFIG_MEMORY_ISOLATION=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_COMPACTION=y -# CONFIG_PAGE_REPORTING is not set -CONFIG_MIGRATION=y -CONFIG_CONTIG_ALLOC=y -CONFIG_BOUNCE=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -# CONFIG_CLEANCACHE is not set -# CONFIG_FRONTSWAP is not set -CONFIG_CMA=y -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_AREAS=7 -CONFIG_ZPOOL=m -CONFIG_ZBUD=m -CONFIG_Z3FOLD=m -CONFIG_ZSMALLOC=m -# CONFIG_ZSMALLOC_STAT is not set -CONFIG_GENERIC_EARLY_IOREMAP=y -# CONFIG_IDLE_PAGE_TRACKING is not set -CONFIG_FRAME_VECTOR=y -# CONFIG_PERCPU_STATS is not set -# CONFIG_GUP_BENCHMARK is not set -# end of Memory Management options - -CONFIG_NET=y -CONFIG_NET_INGRESS=y -CONFIG_NET_EGRESS=y -CONFIG_NET_REDIRECT=y -CONFIG_SKB_EXTENSIONS=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_DIAG=m -CONFIG_UNIX=y -CONFIG_UNIX_SCM=y -CONFIG_UNIX_DIAG=m -CONFIG_TLS=m -CONFIG_TLS_DEVICE=y -CONFIG_TLS_TOE=y -CONFIG_XFRM=y -CONFIG_XFRM_OFFLOAD=y -CONFIG_XFRM_ALGO=m -CONFIG_XFRM_USER=m -CONFIG_XFRM_INTERFACE=m -CONFIG_XFRM_SUB_POLICY=y -CONFIG_XFRM_MIGRATE=y -CONFIG_XFRM_STATISTICS=y -CONFIG_XFRM_AH=m -CONFIG_XFRM_ESP=m -CONFIG_XFRM_IPCOMP=m -CONFIG_NET_KEY=m -CONFIG_NET_KEY_MIGRATE=y -CONFIG_XFRM_ESPINTCP=y -CONFIG_XDP_SOCKETS=y -CONFIG_XDP_SOCKETS_DIAG=m -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_FIB_TRIE_STATS=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_ROUTE_CLASSID=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE_DEMUX=m -CONFIG_NET_IP_TUNNEL=m -CONFIG_NET_IPGRE=m -CONFIG_NET_IPGRE_BROADCAST=y -CONFIG_IP_MROUTE_COMMON=y -CONFIG_IP_MROUTE=y -CONFIG_IP_MROUTE_MULTIPLE_TABLES=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -CONFIG_SYN_COOKIES=y -CONFIG_NET_IPVTI=m -CONFIG_NET_UDP_TUNNEL=m -CONFIG_NET_FOU=m -CONFIG_NET_FOU_IP_TUNNELS=y -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_ESP_OFFLOAD=m -CONFIG_INET_ESPINTCP=y -CONFIG_INET_IPCOMP=m -CONFIG_INET_XFRM_TUNNEL=m -CONFIG_INET_TUNNEL=m -CONFIG_INET_DIAG=m -CONFIG_INET_TCP_DIAG=m -CONFIG_INET_UDP_DIAG=m -CONFIG_INET_RAW_DIAG=m -CONFIG_INET_DIAG_DESTROY=y -CONFIG_TCP_CONG_ADVANCED=y -CONFIG_TCP_CONG_BIC=m -CONFIG_TCP_CONG_CUBIC=y -CONFIG_TCP_CONG_WESTWOOD=m -CONFIG_TCP_CONG_HTCP=m -CONFIG_TCP_CONG_HSTCP=m -CONFIG_TCP_CONG_HYBLA=m -CONFIG_TCP_CONG_VEGAS=m -CONFIG_TCP_CONG_NV=m -CONFIG_TCP_CONG_SCALABLE=m -CONFIG_TCP_CONG_LP=m -CONFIG_TCP_CONG_VENO=m -CONFIG_TCP_CONG_YEAH=m -CONFIG_TCP_CONG_ILLINOIS=m -CONFIG_TCP_CONG_DCTCP=m -CONFIG_TCP_CONG_CDG=m -CONFIG_TCP_CONG_BBR=m -CONFIG_DEFAULT_CUBIC=y -# CONFIG_DEFAULT_RENO is not set -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -CONFIG_IPV6=y -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_IPV6_ROUTE_INFO=y -CONFIG_IPV6_OPTIMISTIC_DAD=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_ESP_OFFLOAD=m -CONFIG_INET6_ESPINTCP=y -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_MIP6=m -# CONFIG_IPV6_ILA is not set -CONFIG_INET6_XFRM_TUNNEL=m -CONFIG_INET6_TUNNEL=m -CONFIG_IPV6_VTI=m -CONFIG_IPV6_SIT=m -CONFIG_IPV6_SIT_6RD=y -CONFIG_IPV6_NDISC_NODETYPE=y -CONFIG_IPV6_TUNNEL=m -CONFIG_IPV6_GRE=m -CONFIG_IPV6_FOU=m -CONFIG_IPV6_FOU_TUNNEL=m -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_IPV6_MROUTE=y -CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y -CONFIG_IPV6_PIMSM_V2=y -CONFIG_IPV6_SEG6_LWTUNNEL=y -CONFIG_IPV6_SEG6_HMAC=y -CONFIG_IPV6_SEG6_BPF=y -CONFIG_IPV6_RPL_LWTUNNEL=y -CONFIG_MPTCP=y -CONFIG_INET_MPTCP_DIAG=m -CONFIG_MPTCP_IPV6=y -CONFIG_NETWORK_SECMARK=y -# CONFIG_NETWORK_PHY_TIMESTAMPING is not set -CONFIG_NETFILTER=y -CONFIG_NETFILTER_ADVANCED=y -CONFIG_BRIDGE_NETFILTER=m - -# -# Core Netfilter Configuration -# -CONFIG_NETFILTER_INGRESS=y -CONFIG_NETFILTER_NETLINK=m -CONFIG_NETFILTER_FAMILY_BRIDGE=y -CONFIG_NETFILTER_FAMILY_ARP=y -CONFIG_NETFILTER_NETLINK_ACCT=m -CONFIG_NETFILTER_NETLINK_QUEUE=m -CONFIG_NETFILTER_NETLINK_LOG=m -CONFIG_NETFILTER_NETLINK_OSF=m -CONFIG_NF_CONNTRACK=m -CONFIG_NF_LOG_COMMON=m -# CONFIG_NF_LOG_NETDEV is not set -CONFIG_NETFILTER_CONNCOUNT=m -CONFIG_NF_CONNTRACK_MARK=y -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_ZONES=y -CONFIG_NF_CONNTRACK_PROCFS=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CONNTRACK_TIMEOUT=y -CONFIG_NF_CONNTRACK_TIMESTAMP=y -CONFIG_NF_CONNTRACK_LABELS=y -CONFIG_NF_CT_PROTO_DCCP=y -CONFIG_NF_CT_PROTO_GRE=y -CONFIG_NF_CT_PROTO_SCTP=y -CONFIG_NF_CT_PROTO_UDPLITE=y -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_BROADCAST=m -CONFIG_NF_CONNTRACK_NETBIOS_NS=m -CONFIG_NF_CONNTRACK_SNMP=m -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -CONFIG_NF_CT_NETLINK_TIMEOUT=m -CONFIG_NF_CT_NETLINK_HELPER=m -CONFIG_NETFILTER_NETLINK_GLUE_CT=y -CONFIG_NF_NAT=m -CONFIG_NF_NAT_AMANDA=m -CONFIG_NF_NAT_FTP=m -CONFIG_NF_NAT_IRC=m -CONFIG_NF_NAT_SIP=m -CONFIG_NF_NAT_TFTP=m -CONFIG_NF_NAT_REDIRECT=y -CONFIG_NF_NAT_MASQUERADE=y -CONFIG_NETFILTER_SYNPROXY=m -CONFIG_NF_TABLES=m -CONFIG_NF_TABLES_INET=y -CONFIG_NF_TABLES_NETDEV=y -CONFIG_NFT_NUMGEN=m -CONFIG_NFT_CT=m -CONFIG_NFT_FLOW_OFFLOAD=m -# CONFIG_NFT_COUNTER is not set -CONFIG_NFT_CONNLIMIT=m -CONFIG_NFT_LOG=m -CONFIG_NFT_LIMIT=m -CONFIG_NFT_MASQ=m -CONFIG_NFT_REDIR=m -CONFIG_NFT_NAT=m -CONFIG_NFT_TUNNEL=m -CONFIG_NFT_OBJREF=m -CONFIG_NFT_QUEUE=m -CONFIG_NFT_QUOTA=m -CONFIG_NFT_REJECT=m -CONFIG_NFT_REJECT_INET=m -CONFIG_NFT_COMPAT=m -CONFIG_NFT_HASH=m -CONFIG_NFT_FIB=m -CONFIG_NFT_FIB_INET=m -CONFIG_NFT_XFRM=m -CONFIG_NFT_SOCKET=m -CONFIG_NFT_OSF=m -CONFIG_NFT_TPROXY=m -CONFIG_NFT_SYNPROXY=m -CONFIG_NF_DUP_NETDEV=m -CONFIG_NFT_DUP_NETDEV=m -CONFIG_NFT_FWD_NETDEV=m -CONFIG_NFT_FIB_NETDEV=m -CONFIG_NF_FLOW_TABLE_INET=m -CONFIG_NF_FLOW_TABLE=m -CONFIG_NETFILTER_XTABLES=m - -# -# Xtables combined modules -# -CONFIG_NETFILTER_XT_MARK=m -CONFIG_NETFILTER_XT_CONNMARK=m -CONFIG_NETFILTER_XT_SET=m - -# -# Xtables targets -# -CONFIG_NETFILTER_XT_TARGET_AUDIT=m -CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m -CONFIG_NETFILTER_XT_TARGET_CT=m -CONFIG_NETFILTER_XT_TARGET_DSCP=m -CONFIG_NETFILTER_XT_TARGET_HL=m -CONFIG_NETFILTER_XT_TARGET_HMARK=m -CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m -CONFIG_NETFILTER_XT_TARGET_LED=m -CONFIG_NETFILTER_XT_TARGET_LOG=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_NAT=m -CONFIG_NETFILTER_XT_TARGET_NETMAP=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_NOTRACK=m -CONFIG_NETFILTER_XT_TARGET_RATEEST=m -CONFIG_NETFILTER_XT_TARGET_REDIRECT=m -CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m -CONFIG_NETFILTER_XT_TARGET_TEE=m -CONFIG_NETFILTER_XT_TARGET_TPROXY=m -CONFIG_NETFILTER_XT_TARGET_TRACE=m -CONFIG_NETFILTER_XT_TARGET_SECMARK=m -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m - -# -# Xtables matches -# -CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -CONFIG_NETFILTER_XT_MATCH_BPF=m -CONFIG_NETFILTER_XT_MATCH_CGROUP=m -CONFIG_NETFILTER_XT_MATCH_CLUSTER=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_CPU=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ECN=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_HL=m -CONFIG_NETFILTER_XT_MATCH_IPCOMP=m -CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -CONFIG_NETFILTER_XT_MATCH_IPVS=m -CONFIG_NETFILTER_XT_MATCH_L2TP=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_NFACCT=m -CONFIG_NETFILTER_XT_MATCH_OSF=m -CONFIG_NETFILTER_XT_MATCH_OWNER=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_RATEEST=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_RECENT=m -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_SOCKET=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_TIME=m -CONFIG_NETFILTER_XT_MATCH_U32=m -# end of Core Netfilter Configuration - -CONFIG_IP_SET=m -CONFIG_IP_SET_MAX=256 -CONFIG_IP_SET_BITMAP_IP=m -CONFIG_IP_SET_BITMAP_IPMAC=m -CONFIG_IP_SET_BITMAP_PORT=m -CONFIG_IP_SET_HASH_IP=m -CONFIG_IP_SET_HASH_IPMARK=m -CONFIG_IP_SET_HASH_IPPORT=m -CONFIG_IP_SET_HASH_IPPORTIP=m -CONFIG_IP_SET_HASH_IPPORTNET=m -CONFIG_IP_SET_HASH_IPMAC=m -CONFIG_IP_SET_HASH_MAC=m -CONFIG_IP_SET_HASH_NETPORTNET=m -CONFIG_IP_SET_HASH_NET=m -CONFIG_IP_SET_HASH_NETNET=m -CONFIG_IP_SET_HASH_NETPORT=m -CONFIG_IP_SET_HASH_NETIFACE=m -CONFIG_IP_SET_LIST_SET=m -CONFIG_IP_VS=m -CONFIG_IP_VS_IPV6=y -CONFIG_IP_VS_DEBUG=y -CONFIG_IP_VS_TAB_BITS=12 - -# -# IPVS transport protocol load balancing support -# -CONFIG_IP_VS_PROTO_TCP=y -CONFIG_IP_VS_PROTO_UDP=y -CONFIG_IP_VS_PROTO_AH_ESP=y -CONFIG_IP_VS_PROTO_ESP=y -CONFIG_IP_VS_PROTO_AH=y -CONFIG_IP_VS_PROTO_SCTP=y - -# -# IPVS scheduler -# -CONFIG_IP_VS_RR=m -CONFIG_IP_VS_WRR=m -CONFIG_IP_VS_LC=m -CONFIG_IP_VS_WLC=m -CONFIG_IP_VS_FO=m -CONFIG_IP_VS_OVF=m -CONFIG_IP_VS_LBLC=m -CONFIG_IP_VS_LBLCR=m -CONFIG_IP_VS_DH=m -CONFIG_IP_VS_SH=m -CONFIG_IP_VS_MH=m -CONFIG_IP_VS_SED=m -CONFIG_IP_VS_NQ=m - -# -# IPVS SH scheduler -# -CONFIG_IP_VS_SH_TAB_BITS=8 - -# -# IPVS MH scheduler -# -CONFIG_IP_VS_MH_TAB_INDEX=12 - -# -# IPVS application helper -# -CONFIG_IP_VS_FTP=m -CONFIG_IP_VS_NFCT=y -CONFIG_IP_VS_PE_SIP=m - -# -# IP: Netfilter Configuration -# -CONFIG_NF_DEFRAG_IPV4=m -CONFIG_NF_SOCKET_IPV4=m -CONFIG_NF_TPROXY_IPV4=m -CONFIG_NF_TABLES_IPV4=y -CONFIG_NFT_REJECT_IPV4=m -CONFIG_NFT_DUP_IPV4=m -CONFIG_NFT_FIB_IPV4=m -CONFIG_NF_TABLES_ARP=y -# CONFIG_NF_FLOW_TABLE_IPV4 is not set -CONFIG_NF_DUP_IPV4=m -CONFIG_NF_LOG_ARP=m -CONFIG_NF_LOG_IPV4=m -CONFIG_NF_REJECT_IPV4=m -CONFIG_NF_NAT_SNMP_BASIC=m -CONFIG_NF_NAT_PPTP=m -CONFIG_NF_NAT_H323=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_RPFILTER=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_SYNPROXY=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m -# end of IP: Netfilter Configuration - -# -# IPv6: Netfilter Configuration -# -CONFIG_NF_SOCKET_IPV6=m -CONFIG_NF_TPROXY_IPV6=m -CONFIG_NF_TABLES_IPV6=y -CONFIG_NFT_REJECT_IPV6=m -CONFIG_NFT_DUP_IPV6=m -CONFIG_NFT_FIB_IPV6=m -# CONFIG_NF_FLOW_TABLE_IPV6 is not set -CONFIG_NF_DUP_IPV6=m -CONFIG_NF_REJECT_IPV6=m -CONFIG_NF_LOG_IPV6=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_RPFILTER=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_MATCH_SRH=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_TARGET_SYNPROXY=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_RAW=m -CONFIG_IP6_NF_NAT=m -CONFIG_IP6_NF_TARGET_MASQUERADE=m -CONFIG_IP6_NF_TARGET_NPT=m -# end of IPv6: Netfilter Configuration - -CONFIG_NF_DEFRAG_IPV6=m - -# -# DECnet: Netfilter Configuration -# -CONFIG_DECNET_NF_GRABULATOR=m -# end of DECnet: Netfilter Configuration - -CONFIG_NF_TABLES_BRIDGE=m -CONFIG_NFT_BRIDGE_META=m -CONFIG_NFT_BRIDGE_REJECT=m -# CONFIG_NF_LOG_BRIDGE is not set -CONFIG_NF_CONNTRACK_BRIDGE=m -CONFIG_BRIDGE_NF_EBTABLES=m -CONFIG_BRIDGE_EBT_BROUTE=m -CONFIG_BRIDGE_EBT_T_FILTER=m -CONFIG_BRIDGE_EBT_T_NAT=m -CONFIG_BRIDGE_EBT_802_3=m -CONFIG_BRIDGE_EBT_AMONG=m -CONFIG_BRIDGE_EBT_ARP=m -CONFIG_BRIDGE_EBT_IP=m -CONFIG_BRIDGE_EBT_IP6=m -CONFIG_BRIDGE_EBT_LIMIT=m -CONFIG_BRIDGE_EBT_MARK=m -CONFIG_BRIDGE_EBT_PKTTYPE=m -CONFIG_BRIDGE_EBT_STP=m -CONFIG_BRIDGE_EBT_VLAN=m -CONFIG_BRIDGE_EBT_ARPREPLY=m -CONFIG_BRIDGE_EBT_DNAT=m -CONFIG_BRIDGE_EBT_MARK_T=m -CONFIG_BRIDGE_EBT_REDIRECT=m -CONFIG_BRIDGE_EBT_SNAT=m -CONFIG_BRIDGE_EBT_LOG=m -CONFIG_BRIDGE_EBT_NFLOG=m -CONFIG_BPFILTER=y -CONFIG_BPFILTER_UMH=m -CONFIG_IP_DCCP=m -CONFIG_INET_DCCP_DIAG=m - -# -# DCCP CCIDs Configuration -# -# CONFIG_IP_DCCP_CCID2_DEBUG is not set -CONFIG_IP_DCCP_CCID3=y -# CONFIG_IP_DCCP_CCID3_DEBUG is not set -CONFIG_IP_DCCP_TFRC_LIB=y -# end of DCCP CCIDs Configuration - -# -# DCCP Kernel Hacking -# -# CONFIG_IP_DCCP_DEBUG is not set -# end of DCCP Kernel Hacking - -CONFIG_IP_SCTP=y -# CONFIG_SCTP_DBG_OBJCNT is not set -CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y -# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set -# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set -CONFIG_SCTP_COOKIE_HMAC_MD5=y -# CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set -CONFIG_INET_SCTP_DIAG=m -CONFIG_RDS=m -CONFIG_RDS_TCP=m -# CONFIG_RDS_DEBUG is not set -CONFIG_TIPC=m -CONFIG_TIPC_MEDIA_UDP=y -CONFIG_TIPC_CRYPTO=y -CONFIG_TIPC_DIAG=m -CONFIG_ATM=m -CONFIG_ATM_CLIP=m -# CONFIG_ATM_CLIP_NO_ICMP is not set -CONFIG_ATM_LANE=m -CONFIG_ATM_MPOA=m -CONFIG_ATM_BR2684=m -CONFIG_ATM_BR2684_IPFILTER=y -CONFIG_L2TP=m -CONFIG_L2TP_DEBUGFS=m -CONFIG_L2TP_V3=y -CONFIG_L2TP_IP=m -CONFIG_L2TP_ETH=m -CONFIG_STP=m -CONFIG_GARP=m -CONFIG_MRP=m -CONFIG_BRIDGE=m -CONFIG_BRIDGE_IGMP_SNOOPING=y -CONFIG_BRIDGE_VLAN_FILTERING=y -CONFIG_BRIDGE_MRP=y -CONFIG_HAVE_NET_DSA=y -# CONFIG_NET_DSA is not set -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -CONFIG_VLAN_8021Q_MVRP=y -CONFIG_DECNET=m -CONFIG_DECNET_ROUTER=y -CONFIG_LLC=m -CONFIG_LLC2=m -CONFIG_ATALK=m -CONFIG_DEV_APPLETALK=m -CONFIG_IPDDP=m -CONFIG_IPDDP_ENCAP=y -CONFIG_X25=m -CONFIG_LAPB=m -CONFIG_PHONET=m -CONFIG_6LOWPAN=m -CONFIG_6LOWPAN_DEBUGFS=y -CONFIG_6LOWPAN_NHC=m -CONFIG_6LOWPAN_NHC_DEST=m -CONFIG_6LOWPAN_NHC_FRAGMENT=m -CONFIG_6LOWPAN_NHC_HOP=m -CONFIG_6LOWPAN_NHC_IPV6=m -CONFIG_6LOWPAN_NHC_MOBILITY=m -CONFIG_6LOWPAN_NHC_ROUTING=m -CONFIG_6LOWPAN_NHC_UDP=m -CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m -CONFIG_6LOWPAN_GHC_UDP=m -CONFIG_6LOWPAN_GHC_ICMPV6=m -CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m -CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m -CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m -CONFIG_IEEE802154=m -CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y -CONFIG_IEEE802154_SOCKET=m -CONFIG_IEEE802154_6LOWPAN=m -CONFIG_MAC802154=m -CONFIG_NET_SCHED=y - -# -# Queueing/Scheduling -# -CONFIG_NET_SCH_CBQ=m -CONFIG_NET_SCH_HTB=m -CONFIG_NET_SCH_HFSC=m -CONFIG_NET_SCH_ATM=m -CONFIG_NET_SCH_PRIO=m -CONFIG_NET_SCH_MULTIQ=m -CONFIG_NET_SCH_RED=m -CONFIG_NET_SCH_SFB=m -CONFIG_NET_SCH_SFQ=m -CONFIG_NET_SCH_TEQL=m -CONFIG_NET_SCH_TBF=m -CONFIG_NET_SCH_CBS=m -CONFIG_NET_SCH_ETF=m -CONFIG_NET_SCH_TAPRIO=m -CONFIG_NET_SCH_GRED=m -CONFIG_NET_SCH_DSMARK=m -CONFIG_NET_SCH_NETEM=m -CONFIG_NET_SCH_DRR=m -CONFIG_NET_SCH_MQPRIO=m -CONFIG_NET_SCH_SKBPRIO=m -CONFIG_NET_SCH_CHOKE=m -CONFIG_NET_SCH_QFQ=m -CONFIG_NET_SCH_CODEL=m -CONFIG_NET_SCH_FQ_CODEL=m -CONFIG_NET_SCH_CAKE=m -CONFIG_NET_SCH_FQ=m -CONFIG_NET_SCH_HHF=m -CONFIG_NET_SCH_PIE=m -CONFIG_NET_SCH_FQ_PIE=m -CONFIG_NET_SCH_INGRESS=m -CONFIG_NET_SCH_PLUG=m -CONFIG_NET_SCH_ETS=m -CONFIG_NET_SCH_DEFAULT=y -# CONFIG_DEFAULT_FQ is not set -# CONFIG_DEFAULT_CODEL is not set -# CONFIG_DEFAULT_FQ_CODEL is not set -# CONFIG_DEFAULT_FQ_PIE is not set -# CONFIG_DEFAULT_SFQ is not set -CONFIG_DEFAULT_PFIFO_FAST=y -CONFIG_DEFAULT_NET_SCH="pfifo_fast" - -# -# Classification -# -CONFIG_NET_CLS=y -CONFIG_NET_CLS_BASIC=m -CONFIG_NET_CLS_TCINDEX=m -CONFIG_NET_CLS_ROUTE4=m -CONFIG_NET_CLS_FW=m -CONFIG_NET_CLS_U32=m -CONFIG_CLS_U32_PERF=y -CONFIG_CLS_U32_MARK=y -CONFIG_NET_CLS_RSVP=m -CONFIG_NET_CLS_RSVP6=m -CONFIG_NET_CLS_FLOW=m -CONFIG_NET_CLS_CGROUP=m -CONFIG_NET_CLS_BPF=m -CONFIG_NET_CLS_FLOWER=m -CONFIG_NET_CLS_MATCHALL=m -CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_STACK=32 -CONFIG_NET_EMATCH_CMP=m -CONFIG_NET_EMATCH_NBYTE=m -CONFIG_NET_EMATCH_U32=m -CONFIG_NET_EMATCH_META=m -CONFIG_NET_EMATCH_TEXT=m -CONFIG_NET_EMATCH_IPSET=m -CONFIG_NET_EMATCH_IPT=m -CONFIG_NET_CLS_ACT=y -CONFIG_NET_ACT_POLICE=m -CONFIG_NET_ACT_GACT=m -CONFIG_GACT_PROB=y -CONFIG_NET_ACT_MIRRED=m -CONFIG_NET_ACT_SAMPLE=m -CONFIG_NET_ACT_IPT=m -CONFIG_NET_ACT_NAT=m -CONFIG_NET_ACT_PEDIT=m -CONFIG_NET_ACT_SIMP=m -CONFIG_NET_ACT_SKBEDIT=m -CONFIG_NET_ACT_CSUM=m -CONFIG_NET_ACT_MPLS=m -CONFIG_NET_ACT_VLAN=m -CONFIG_NET_ACT_BPF=m -CONFIG_NET_ACT_CONNMARK=m -CONFIG_NET_ACT_CTINFO=m -CONFIG_NET_ACT_SKBMOD=m -CONFIG_NET_ACT_IFE=m -CONFIG_NET_ACT_TUNNEL_KEY=m -CONFIG_NET_ACT_CT=m -CONFIG_NET_ACT_GATE=m -CONFIG_NET_IFE_SKBMARK=m -CONFIG_NET_IFE_SKBPRIO=m -CONFIG_NET_IFE_SKBTCINDEX=m -CONFIG_NET_TC_SKB_EXT=y -CONFIG_NET_SCH_FIFO=y -CONFIG_DCB=y -CONFIG_DNS_RESOLVER=y -CONFIG_BATMAN_ADV=m -CONFIG_BATMAN_ADV_BATMAN_V=y -CONFIG_BATMAN_ADV_BLA=y -CONFIG_BATMAN_ADV_DAT=y -CONFIG_BATMAN_ADV_NC=y -CONFIG_BATMAN_ADV_MCAST=y -# CONFIG_BATMAN_ADV_DEBUGFS is not set -# CONFIG_BATMAN_ADV_DEBUG is not set -# CONFIG_BATMAN_ADV_SYSFS is not set -# CONFIG_BATMAN_ADV_TRACING is not set -CONFIG_OPENVSWITCH=m -CONFIG_OPENVSWITCH_GRE=m -CONFIG_OPENVSWITCH_VXLAN=m -CONFIG_OPENVSWITCH_GENEVE=m -CONFIG_VSOCKETS=m -CONFIG_VSOCKETS_DIAG=m -CONFIG_VSOCKETS_LOOPBACK=m -CONFIG_VIRTIO_VSOCKETS=m -CONFIG_VIRTIO_VSOCKETS_COMMON=m -CONFIG_NETLINK_DIAG=m -CONFIG_MPLS=y -CONFIG_NET_MPLS_GSO=m -CONFIG_MPLS_ROUTING=m -CONFIG_MPLS_IPTUNNEL=m -CONFIG_NET_NSH=m -CONFIG_HSR=m -CONFIG_NET_SWITCHDEV=y -CONFIG_NET_L3_MASTER_DEV=y -CONFIG_QRTR=m -CONFIG_QRTR_SMD=m -CONFIG_QRTR_TUN=m -CONFIG_NET_NCSI=y -CONFIG_NCSI_OEM_CMD_GET_MAC=y -CONFIG_RPS=y -CONFIG_RFS_ACCEL=y -CONFIG_XPS=y -CONFIG_CGROUP_NET_PRIO=y -CONFIG_CGROUP_NET_CLASSID=y -CONFIG_NET_RX_BUSY_POLL=y -CONFIG_BQL=y -CONFIG_BPF_JIT=y -CONFIG_BPF_STREAM_PARSER=y -CONFIG_NET_FLOW_LIMIT=y - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_DROP_MONITOR is not set -# end of Network testing -# end of Networking options - -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -CONFIG_BT=m -CONFIG_BT_BREDR=y -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m -CONFIG_BT_HS=y -CONFIG_BT_LE=y -CONFIG_BT_6LOWPAN=m -CONFIG_BT_LEDS=y -CONFIG_BT_MSFTEXT=y -CONFIG_BT_DEBUGFS=y -# CONFIG_BT_SELFTEST is not set -CONFIG_BT_FEATURE_DEBUG=y - -# -# Bluetooth device drivers -# -CONFIG_BT_INTEL=m -CONFIG_BT_BCM=m -CONFIG_BT_RTL=m -CONFIG_BT_QCA=m -CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y -CONFIG_BT_HCIBTUSB_BCM=y -CONFIG_BT_HCIBTUSB_MTK=y -CONFIG_BT_HCIBTUSB_RTL=y -CONFIG_BT_HCIBTSDIO=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_SERDEV=y -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_NOKIA=m -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_ATH3K=y -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIUART_3WIRE=y -CONFIG_BT_HCIUART_INTEL=y -CONFIG_BT_HCIUART_BCM=y -CONFIG_BT_HCIUART_RTL=y -CONFIG_BT_HCIUART_QCA=y -CONFIG_BT_HCIUART_AG6XX=y -CONFIG_BT_HCIUART_MRVL=y -CONFIG_BT_HCIBCM203X=m -CONFIG_BT_HCIBPA10X=m -CONFIG_BT_HCIBFUSB=m -CONFIG_BT_HCIVHCI=m -CONFIG_BT_MRVL=m -CONFIG_BT_MRVL_SDIO=m -CONFIG_BT_ATH3K=m -CONFIG_BT_MTKSDIO=m -CONFIG_BT_MTKUART=m -# end of Bluetooth device drivers - -CONFIG_AF_RXRPC=m -CONFIG_AF_RXRPC_IPV6=y -CONFIG_AF_RXRPC_INJECT_LOSS=y -CONFIG_AF_RXRPC_DEBUG=y -CONFIG_RXKAD=y -# CONFIG_AF_KCM is not set -CONFIG_STREAM_PARSER=y -CONFIG_FIB_RULES=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_EXT=y -CONFIG_WEXT_CORE=y -CONFIG_WEXT_PROC=y -CONFIG_WEXT_PRIV=y -CONFIG_CFG80211=m -# CONFIG_NL80211_TESTMODE is not set -# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set -# CONFIG_CFG80211_CERTIFICATION_ONUS is not set -CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y -CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y -CONFIG_CFG80211_DEFAULT_PS=y -CONFIG_CFG80211_DEBUGFS=y -CONFIG_CFG80211_CRDA_SUPPORT=y -CONFIG_CFG80211_WEXT=y -CONFIG_MAC80211=m -CONFIG_MAC80211_HAS_RC=y -CONFIG_MAC80211_RC_MINSTREL=y -CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y -CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" -CONFIG_MAC80211_MESH=y -CONFIG_MAC80211_LEDS=y -CONFIG_MAC80211_DEBUGFS=y -# CONFIG_MAC80211_MESSAGE_TRACING is not set -# CONFIG_MAC80211_DEBUG_MENU is not set -CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 -# CONFIG_WIMAX is not set -CONFIG_RFKILL=m -CONFIG_RFKILL_LEDS=y -CONFIG_RFKILL_INPUT=y -CONFIG_RFKILL_GPIO=m -# CONFIG_NET_9P is not set -# CONFIG_CAIF is not set -CONFIG_CEPH_LIB=m -# CONFIG_CEPH_LIB_PRETTYDEBUG is not set -# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set -# CONFIG_NFC is not set -CONFIG_PSAMPLE=m -CONFIG_NET_IFE=m -CONFIG_LWTUNNEL=y -CONFIG_LWTUNNEL_BPF=y -CONFIG_DST_CACHE=y -CONFIG_GRO_CELLS=y -CONFIG_SOCK_VALIDATE_XMIT=y -CONFIG_NET_SOCK_MSG=y -CONFIG_NET_DEVLINK=y -CONFIG_PAGE_POOL=y -CONFIG_FAILOVER=y -CONFIG_ETHTOOL_NETLINK=y -CONFIG_HAVE_EBPF_JIT=y - -# -# Device Drivers -# -CONFIG_HAVE_PCI=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_SYSCALL=y -# CONFIG_PCIEPORTBUS is not set -# CONFIG_PCIEASPM is not set -# CONFIG_PCIE_PTM is not set -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCI_QUIRKS=y -# CONFIG_PCI_DEBUG is not set -# CONFIG_PCI_STUB is not set -CONFIG_PCI_ECAM=y -# CONFIG_PCI_IOV is not set -# CONFIG_PCI_PRI is not set -# CONFIG_PCI_PASID is not set -CONFIG_PCI_LABEL=y -# CONFIG_PCIE_BUS_TUNE_OFF is not set -CONFIG_PCIE_BUS_DEFAULT=y -# CONFIG_PCIE_BUS_SAFE is not set -# CONFIG_PCIE_BUS_PERFORMANCE is not set -# CONFIG_PCIE_BUS_PEER2PEER is not set -# CONFIG_HOTPLUG_PCI is not set - -# -# PCI controller drivers -# -# CONFIG_PCI_FTPCI100 is not set -CONFIG_PCI_HOST_COMMON=y -CONFIG_PCI_HOST_GENERIC=y -# CONFIG_PCIE_XILINX is not set -# CONFIG_PCI_V3_SEMI is not set -# CONFIG_PCIE_ALTERA is not set - -# -# DesignWare PCI Core Support -# -# CONFIG_PCIE_DW_PLAT_HOST is not set -# CONFIG_PCI_LAYERSCAPE is not set -# CONFIG_PCI_MESON is not set -# end of DesignWare PCI Core Support - -# -# Mobiveil PCIe Core Support -# -# end of Mobiveil PCIe Core Support - -# -# Cadence PCIe controllers support -# -# CONFIG_PCIE_CADENCE_PLAT_HOST is not set -# CONFIG_PCI_J721E_HOST is not set -# end of Cadence PCIe controllers support -# end of PCI controller drivers - -# -# PCI Endpoint -# -# CONFIG_PCI_ENDPOINT is not set -# end of PCI Endpoint - -# -# PCI switch controller drivers -# -# CONFIG_PCI_SW_SWITCHTEC is not set -# end of PCI switch controller drivers - -# CONFIG_PCCARD is not set -# CONFIG_RAPIDIO is not set - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER=y -CONFIG_UEVENT_HELPER_PATH="" -CONFIG_DEVTMPFS=y -CONFIG_DEVTMPFS_MOUNT=y -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y - -# -# Firmware loader -# -CONFIG_FW_LOADER=y -CONFIG_FW_LOADER_PAGED_BUF=y -CONFIG_EXTRA_FIRMWARE="" -CONFIG_FW_LOADER_USER_HELPER=y -# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set -CONFIG_FW_LOADER_COMPRESS=y -CONFIG_FW_CACHE=y -# end of Firmware loader - -CONFIG_WANT_DEV_COREDUMP=y -CONFIG_ALLOW_DEV_COREDUMP=y -CONFIG_DEV_COREDUMP=y -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set -# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_SOC_BUS=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_SPI=m -CONFIG_REGMAP_MMIO=y -CONFIG_DMA_SHARED_BUFFER=y -# CONFIG_DMA_FENCE_TRACE is not set -CONFIG_GENERIC_ARCH_TOPOLOGY=y -# end of Generic Driver Options - -# -# Bus devices -# -# CONFIG_BRCMSTB_GISB_ARB is not set -# CONFIG_MOXTET is not set -# CONFIG_SIMPLE_PM_BUS is not set -CONFIG_VEXPRESS_CONFIG=y -# CONFIG_MHI_BUS is not set -# end of Bus devices - -CONFIG_CONNECTOR=m -# CONFIG_GNSS is not set -# CONFIG_MTD is not set -CONFIG_DTC=y -CONFIG_OF=y -# CONFIG_OF_UNITTEST is not set -CONFIG_OF_FLATTREE=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_KOBJ=y -CONFIG_OF_DYNAMIC=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_IRQ=y -CONFIG_OF_NET=y -CONFIG_OF_RESERVED_MEM=y -CONFIG_OF_RESOLVE=y -CONFIG_OF_OVERLAY=y -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_NULL_BLK is not set -CONFIG_CDROM=y -# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set -CONFIG_ZRAM=m -CONFIG_ZRAM_WRITEBACK=y -CONFIG_ZRAM_MEMORY_TRACKING=y -# CONFIG_BLK_DEV_UMEM is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -CONFIG_BLK_DEV_DRBD=m -CONFIG_DRBD_FAULT_INJECTION=y -CONFIG_BLK_DEV_NBD=m -# CONFIG_BLK_DEV_SX8 is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=65536 -# CONFIG_CDROM_PKTCDVD is not set -CONFIG_ATA_OVER_ETH=m -# CONFIG_VIRTIO_BLK is not set -CONFIG_BLK_DEV_RBD=m -# CONFIG_BLK_DEV_RSXX is not set - -# -# NVME Support -# -# CONFIG_BLK_DEV_NVME is not set -# CONFIG_NVME_FC is not set -# CONFIG_NVME_TCP is not set -# CONFIG_NVME_TARGET is not set -# end of NVME Support - -# -# Misc devices -# -CONFIG_AD525X_DPOT=m -CONFIG_AD525X_DPOT_I2C=m -CONFIG_AD525X_DPOT_SPI=m -CONFIG_DUMMY_IRQ=m -# CONFIG_PHANTOM is not set -# CONFIG_TIFM_CORE is not set -# CONFIG_ICS932S401 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_HP_ILO is not set -# CONFIG_APDS9802ALS is not set -# CONFIG_ISL29003 is not set -# CONFIG_ISL29020 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_SENSORS_BH1770 is not set -# CONFIG_SENSORS_APDS990X is not set -# CONFIG_HMC6352 is not set -# CONFIG_DS1682 is not set -# CONFIG_LATTICE_ECP3_CONFIG is not set -CONFIG_SRAM=y -CONFIG_SRAM_EXEC=y -# CONFIG_PCI_ENDPOINT_TEST is not set -# CONFIG_XILINX_SDFEC is not set -CONFIG_MISC_RTSX=m -# CONFIG_PVPANIC is not set -# CONFIG_HISI_HIKEY_USB is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -CONFIG_EEPROM_93CX6=m -# CONFIG_EEPROM_93XX46 is not set -# CONFIG_EEPROM_IDT_89HPESX is not set -# CONFIG_EEPROM_EE1004 is not set -# end of EEPROM support - -# CONFIG_CB710_CORE is not set - -# -# Texas Instruments shared transport line discipline -# -# CONFIG_TI_ST is not set -# end of Texas Instruments shared transport line discipline - -# CONFIG_SENSORS_LIS3_SPI is not set -# CONFIG_SENSORS_LIS3_I2C is not set -# CONFIG_ALTERA_STAPL is not set -# CONFIG_ECHO is not set -# CONFIG_MISC_ALCOR_PCI is not set -# CONFIG_MISC_RTSX_PCI is not set -CONFIG_MISC_RTSX_USB=m -# CONFIG_HABANA_AI is not set -# end of Misc devices - -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_SCSI_MOD=y -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -CONFIG_SCSI_NETLINK=y -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -CONFIG_BLK_DEV_SR=y -# CONFIG_CHR_DEV_SG is not set -# CONFIG_CHR_DEV_SCH is not set -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set - -# -# SCSI Transports -# -CONFIG_SCSI_SPI_ATTRS=m -CONFIG_SCSI_FC_ATTRS=m -CONFIG_SCSI_ISCSI_ATTRS=m -CONFIG_SCSI_SAS_ATTRS=m -CONFIG_SCSI_SAS_LIBSAS=m -CONFIG_SCSI_SAS_ATA=y -CONFIG_SCSI_SAS_HOST_SMP=y -CONFIG_SCSI_SRP_ATTRS=m -# end of SCSI Transports - -CONFIG_SCSI_LOWLEVEL=y -CONFIG_ISCSI_TCP=m -CONFIG_ISCSI_BOOT_SYSFS=m -# CONFIG_SCSI_CXGB3_ISCSI is not set -# CONFIG_SCSI_CXGB4_ISCSI is not set -# CONFIG_SCSI_BNX2_ISCSI is not set -# CONFIG_BE2ISCSI is not set -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_HPSA is not set -# CONFIG_SCSI_3W_9XXX is not set -# CONFIG_SCSI_3W_SAS is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AACRAID is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_AIC94XX is not set -# CONFIG_SCSI_MVSAS is not set -# CONFIG_SCSI_MVUMI is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_ARCMSR is not set -# CONFIG_SCSI_ESAS2R is not set -# CONFIG_MEGARAID_NEWGEN is not set -# CONFIG_MEGARAID_LEGACY is not set -# CONFIG_MEGARAID_SAS is not set -# CONFIG_SCSI_MPT3SAS is not set -# CONFIG_SCSI_MPT2SAS is not set -# CONFIG_SCSI_SMARTPQI is not set -# CONFIG_SCSI_UFSHCD is not set -# CONFIG_SCSI_HPTIOP is not set -# CONFIG_SCSI_MYRB is not set -# CONFIG_SCSI_MYRS is not set -# CONFIG_LIBFC is not set -# CONFIG_SCSI_SNIC is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_FDOMAIN_PCI is not set -# CONFIG_SCSI_GDTH is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_STEX is not set -# CONFIG_SCSI_SYM53C8XX_2 is not set -# CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLA_FC is not set -# CONFIG_SCSI_QLA_ISCSI is not set -# CONFIG_SCSI_LPFC is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_NSP32 is not set -# CONFIG_SCSI_WD719X is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_PMCRAID is not set -# CONFIG_SCSI_PM8001 is not set -# CONFIG_SCSI_BFA_FC is not set -# CONFIG_SCSI_VIRTIO is not set -# CONFIG_SCSI_CHELSIO_FCOE is not set -# CONFIG_SCSI_DH is not set -# end of SCSI device support - -CONFIG_ATA=y -CONFIG_SATA_HOST=y -CONFIG_ATA_VERBOSE_ERROR=y -CONFIG_ATA_FORCE=y -CONFIG_SATA_PMP=y - -# -# Controllers with non-SFF native interface -# -CONFIG_SATA_AHCI=y -CONFIG_SATA_MOBILE_LPM_POLICY=0 -CONFIG_SATA_AHCI_PLATFORM=y -# CONFIG_AHCI_CEVA is not set -# CONFIG_AHCI_QORIQ is not set -# CONFIG_SATA_INIC162X is not set -# CONFIG_SATA_ACARD_AHCI is not set -# CONFIG_SATA_SIL24 is not set -CONFIG_ATA_SFF=y - -# -# SFF controllers with custom DMA interface -# -# CONFIG_PDC_ADMA is not set -# CONFIG_SATA_QSTOR is not set -# CONFIG_SATA_SX4 is not set -CONFIG_ATA_BMDMA=y - -# -# SATA SFF controllers with BMDMA -# -# CONFIG_ATA_PIIX is not set -# CONFIG_SATA_DWC is not set -CONFIG_SATA_MV=y -# CONFIG_SATA_NV is not set -# CONFIG_SATA_PROMISE is not set -# CONFIG_SATA_SIL is not set -# CONFIG_SATA_SIS is not set -# CONFIG_SATA_SVW is not set -# CONFIG_SATA_ULI is not set -# CONFIG_SATA_VIA is not set -# CONFIG_SATA_VITESSE is not set - -# -# PATA SFF controllers with BMDMA -# -# CONFIG_PATA_ALI is not set -# CONFIG_PATA_AMD is not set -# CONFIG_PATA_ARTOP is not set -# CONFIG_PATA_ATIIXP is not set -# CONFIG_PATA_ATP867X is not set -# CONFIG_PATA_CMD64X is not set -# CONFIG_PATA_CYPRESS is not set -# CONFIG_PATA_EFAR is not set -# CONFIG_PATA_HPT366 is not set -# CONFIG_PATA_HPT37X is not set -# CONFIG_PATA_HPT3X2N is not set -# CONFIG_PATA_HPT3X3 is not set -# CONFIG_PATA_IT8213 is not set -# CONFIG_PATA_IT821X is not set -# CONFIG_PATA_JMICRON is not set -# CONFIG_PATA_MARVELL is not set -# CONFIG_PATA_NETCELL is not set -# CONFIG_PATA_NINJA32 is not set -# CONFIG_PATA_NS87415 is not set -# CONFIG_PATA_OLDPIIX is not set -# CONFIG_PATA_OPTIDMA is not set -# CONFIG_PATA_PDC2027X is not set -# CONFIG_PATA_PDC_OLD is not set -# CONFIG_PATA_RADISYS is not set -# CONFIG_PATA_RDC is not set -# CONFIG_PATA_SCH is not set -# CONFIG_PATA_SERVERWORKS is not set -# CONFIG_PATA_SIL680 is not set -# CONFIG_PATA_SIS is not set -# CONFIG_PATA_TOSHIBA is not set -# CONFIG_PATA_TRIFLEX is not set -# CONFIG_PATA_VIA is not set -# CONFIG_PATA_WINBOND is not set - -# -# PIO-only SFF controllers -# -# CONFIG_PATA_CMD640_PCI is not set -# CONFIG_PATA_MPIIX is not set -# CONFIG_PATA_NS87410 is not set -# CONFIG_PATA_OPTI is not set -# CONFIG_PATA_PLATFORM is not set -# CONFIG_PATA_RZ1000 is not set - -# -# Generic fallback / legacy drivers -# -# CONFIG_ATA_GENERIC is not set -# CONFIG_PATA_LEGACY is not set -CONFIG_MD=y -CONFIG_BLK_DEV_MD=m -CONFIG_MD_LINEAR=m -CONFIG_MD_RAID0=m -CONFIG_MD_RAID1=m -CONFIG_MD_RAID10=m -CONFIG_MD_RAID456=m -CONFIG_MD_MULTIPATH=m -CONFIG_MD_FAULTY=m -# CONFIG_MD_CLUSTER is not set -CONFIG_BCACHE=m -# CONFIG_BCACHE_DEBUG is not set -# CONFIG_BCACHE_CLOSURES_DEBUG is not set -CONFIG_BCACHE_ASYNC_REGISTRATION=y -CONFIG_BLK_DEV_DM_BUILTIN=y -CONFIG_BLK_DEV_DM=m -CONFIG_DM_DEBUG=y -CONFIG_DM_BUFIO=m -CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING=y -# CONFIG_DM_DEBUG_BLOCK_STACK_TRACING is not set -CONFIG_DM_BIO_PRISON=m -CONFIG_DM_PERSISTENT_DATA=m -CONFIG_DM_UNSTRIPED=m -CONFIG_DM_CRYPT=m -CONFIG_DM_SNAPSHOT=m -CONFIG_DM_THIN_PROVISIONING=m -CONFIG_DM_CACHE=m -CONFIG_DM_CACHE_SMQ=m -CONFIG_DM_WRITECACHE=m -# CONFIG_DM_EBS is not set -CONFIG_DM_ERA=m -CONFIG_DM_CLONE=m -CONFIG_DM_MIRROR=m -CONFIG_DM_LOG_USERSPACE=m -CONFIG_DM_RAID=m -CONFIG_DM_ZERO=m -CONFIG_DM_MULTIPATH=m -CONFIG_DM_MULTIPATH_QL=m -CONFIG_DM_MULTIPATH_ST=m -CONFIG_DM_MULTIPATH_HST=m -CONFIG_DM_DELAY=m -CONFIG_DM_DUST=m -CONFIG_DM_UEVENT=y -CONFIG_DM_FLAKEY=m -CONFIG_DM_VERITY=m -CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y -CONFIG_DM_VERITY_FEC=y -CONFIG_DM_SWITCH=m -CONFIG_DM_LOG_WRITES=m -CONFIG_DM_INTEGRITY=m -# CONFIG_TARGET_CORE is not set -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_FIREWIRE is not set -# CONFIG_FIREWIRE_NOSY is not set -# end of IEEE 1394 (FireWire) support - -CONFIG_NETDEVICES=y -CONFIG_MII=y -CONFIG_NET_CORE=y -CONFIG_BONDING=m -CONFIG_DUMMY=m -CONFIG_WIREGUARD=m -# CONFIG_WIREGUARD_DEBUG is not set -CONFIG_EQUALIZER=m -# CONFIG_NET_FC is not set -CONFIG_IFB=m -CONFIG_NET_TEAM=m -CONFIG_NET_TEAM_MODE_BROADCAST=m -CONFIG_NET_TEAM_MODE_ROUNDROBIN=m -CONFIG_NET_TEAM_MODE_RANDOM=m -CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m -CONFIG_NET_TEAM_MODE_LOADBALANCE=m -CONFIG_MACVLAN=m -CONFIG_MACVTAP=m -CONFIG_IPVLAN_L3S=y -CONFIG_IPVLAN=m -CONFIG_IPVTAP=m -CONFIG_VXLAN=m -CONFIG_GENEVE=m -CONFIG_BAREUDP=m -CONFIG_GTP=m -CONFIG_MACSEC=m -CONFIG_NETCONSOLE=m -CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_NETPOLL=y -CONFIG_NET_POLL_CONTROLLER=y -CONFIG_TUN=m -CONFIG_TAP=m -CONFIG_TUN_VNET_CROSS_LE=y -CONFIG_VETH=m -CONFIG_VIRTIO_NET=m -CONFIG_NLMON=m -CONFIG_NET_VRF=m -# CONFIG_VSOCKMON is not set -# CONFIG_ARCNET is not set -# CONFIG_ATM_DRIVERS is not set - -# -# Distributed Switch Architecture drivers -# -# end of Distributed Switch Architecture drivers - -CONFIG_ETHERNET=y -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_NET_VENDOR_ADAPTEC is not set -# CONFIG_NET_VENDOR_AGERE is not set -# CONFIG_NET_VENDOR_ALACRITECH is not set -# CONFIG_NET_VENDOR_ALTEON is not set -# CONFIG_ALTERA_TSE is not set -# CONFIG_NET_VENDOR_AMAZON is not set -# CONFIG_NET_VENDOR_AMD is not set -# CONFIG_NET_VENDOR_AQUANTIA is not set -# CONFIG_NET_VENDOR_ARC is not set -# CONFIG_NET_VENDOR_ATHEROS is not set -CONFIG_NET_VENDOR_AURORA=y -# CONFIG_AURORA_NB8800 is not set -# CONFIG_NET_VENDOR_BROADCOM is not set -# CONFIG_NET_VENDOR_BROCADE is not set -# CONFIG_NET_VENDOR_CADENCE is not set -# CONFIG_NET_VENDOR_CAVIUM is not set -# CONFIG_NET_VENDOR_CHELSIO is not set -# CONFIG_NET_VENDOR_CIRRUS is not set -# CONFIG_NET_VENDOR_CISCO is not set -# CONFIG_NET_VENDOR_CORTINA is not set -# CONFIG_DM9000 is not set -# CONFIG_DNET is not set -# CONFIG_NET_VENDOR_DEC is not set -# CONFIG_NET_VENDOR_DLINK is not set -# CONFIG_NET_VENDOR_EMULEX is not set -# CONFIG_NET_VENDOR_EZCHIP is not set -# CONFIG_NET_VENDOR_FARADAY is not set -# CONFIG_NET_VENDOR_GOOGLE is not set -# CONFIG_NET_VENDOR_HISILICON is not set -# CONFIG_NET_VENDOR_HUAWEI is not set -# CONFIG_NET_VENDOR_INTEL is not set -# CONFIG_JME is not set -# CONFIG_NET_VENDOR_MARVELL is not set -# CONFIG_NET_VENDOR_MELLANOX is not set -# CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set -# CONFIG_NET_VENDOR_MICROSEMI is not set -# CONFIG_NET_VENDOR_MYRI is not set -# CONFIG_FEALNX is not set -# CONFIG_NET_VENDOR_NATSEMI is not set -# CONFIG_NET_VENDOR_NETERION is not set -# CONFIG_NET_VENDOR_NETRONOME is not set -# CONFIG_NET_VENDOR_NI is not set -# CONFIG_NET_VENDOR_NVIDIA is not set -# CONFIG_NET_VENDOR_OKI is not set -# CONFIG_ETHOC is not set -# CONFIG_NET_VENDOR_PACKET_ENGINES is not set -# CONFIG_NET_VENDOR_PENSANDO is not set -# CONFIG_NET_VENDOR_QLOGIC is not set -# CONFIG_NET_VENDOR_QUALCOMM is not set -# CONFIG_NET_VENDOR_RDC is not set -# CONFIG_NET_VENDOR_REALTEK is not set -# CONFIG_NET_VENDOR_RENESAS is not set -# CONFIG_NET_VENDOR_ROCKER is not set -# CONFIG_NET_VENDOR_SAMSUNG is not set -# CONFIG_NET_VENDOR_SEEQ is not set -# CONFIG_NET_VENDOR_SOLARFLARE is not set -# CONFIG_NET_VENDOR_SILAN is not set -# CONFIG_NET_VENDOR_SIS is not set -# CONFIG_NET_VENDOR_SMSC is not set -# CONFIG_NET_VENDOR_SOCIONEXT is not set -CONFIG_NET_VENDOR_STMICRO=y -CONFIG_STMMAC_ETH=y -# CONFIG_STMMAC_SELFTESTS is not set -CONFIG_STMMAC_PLATFORM=y -CONFIG_DWMAC_DWC_QOS_ETH=y -CONFIG_DWMAC_GENERIC=y -CONFIG_DWMAC_MESON=y -# CONFIG_DWMAC_INTEL_PLAT is not set -# CONFIG_STMMAC_PCI is not set -# CONFIG_NET_VENDOR_SUN is not set -# CONFIG_NET_VENDOR_SYNOPSYS is not set -# CONFIG_NET_VENDOR_TEHUTI is not set -# CONFIG_NET_VENDOR_TI is not set -# CONFIG_NET_VENDOR_VIA is not set -# CONFIG_NET_VENDOR_WIZNET is not set -# CONFIG_NET_VENDOR_XILINX is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -CONFIG_PHYLINK=y -CONFIG_PHYLIB=y -CONFIG_SWPHY=y -# CONFIG_LED_TRIGGER_PHY is not set -CONFIG_FIXED_PHY=y -# CONFIG_SFP is not set - -# -# MII PHY device drivers -# -# CONFIG_AMD_PHY is not set -# CONFIG_MESON_GXL_PHY is not set -# CONFIG_ADIN_PHY is not set -# CONFIG_AQUANTIA_PHY is not set -CONFIG_AX88796B_PHY=m -# CONFIG_BROADCOM_PHY is not set -# CONFIG_BCM54140_PHY is not set -# CONFIG_BCM7XXX_PHY is not set -# CONFIG_BCM84881_PHY is not set -# CONFIG_BCM87XX_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_CORTINA_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_INTEL_XWAY_PHY is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_MARVELL_PHY is not set -# CONFIG_MARVELL_10G_PHY is not set -# CONFIG_MICREL_PHY is not set -CONFIG_MICROCHIP_PHY=m -# CONFIG_MICROCHIP_T1_PHY is not set -# CONFIG_MICROSEMI_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_NXP_TJA11XX_PHY is not set -# CONFIG_AT803X_PHY is not set -# CONFIG_QSEMI_PHY is not set -CONFIG_REALTEK_PHY=y -# CONFIG_RENESAS_PHY is not set -# CONFIG_ROCKCHIP_PHY is not set -CONFIG_SMSC_PHY=m -# CONFIG_STE10XP is not set -# CONFIG_TERANETICS_PHY is not set -# CONFIG_DP83822_PHY is not set -# CONFIG_DP83TC811_PHY is not set -# CONFIG_DP83848_PHY is not set -# CONFIG_DP83867_PHY is not set -# CONFIG_DP83869_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_XILINX_GMII2RGMII is not set -# CONFIG_MICREL_KS8995MA is not set -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_BUS=y -CONFIG_OF_MDIO=y -CONFIG_MDIO_DEVRES=y -# CONFIG_MDIO_BITBANG is not set -# CONFIG_MDIO_BCM_UNIMAC is not set -# CONFIG_MDIO_HISI_FEMAC is not set -# CONFIG_MDIO_MVUSB is not set -# CONFIG_MDIO_MSCC_MIIM is not set -# CONFIG_MDIO_IPQ4019 is not set -# CONFIG_MDIO_IPQ8064 is not set - -# -# MDIO Multiplexers -# -# CONFIG_MDIO_BUS_MUX_MESON_G12A is not set -# CONFIG_MDIO_BUS_MUX_GPIO is not set -# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set -# CONFIG_MDIO_BUS_MUX_MMIOREG is not set - -# -# PCS device drivers -# -CONFIG_PCS_XPCS=y -# end of PCS device drivers - -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -CONFIG_USB_NET_DRIVERS=m -CONFIG_USB_CATC=m -CONFIG_USB_KAWETH=m -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_RTL8152=m -CONFIG_USB_LAN78XX=m -CONFIG_USB_USBNET=m -CONFIG_USB_NET_AX8817X=m -CONFIG_USB_NET_AX88179_178A=m -CONFIG_USB_NET_CDCETHER=m -CONFIG_USB_NET_CDC_EEM=m -CONFIG_USB_NET_CDC_NCM=m -CONFIG_USB_NET_HUAWEI_CDC_NCM=m -CONFIG_USB_NET_CDC_MBIM=m -CONFIG_USB_NET_DM9601=m -CONFIG_USB_NET_SR9700=m -CONFIG_USB_NET_SR9800=m -CONFIG_USB_NET_SMSC75XX=m -CONFIG_USB_NET_SMSC95XX=m -CONFIG_USB_NET_GL620A=m -CONFIG_USB_NET_NET1080=m -CONFIG_USB_NET_PLUSB=m -CONFIG_USB_NET_MCS7830=m -CONFIG_USB_NET_RNDIS_HOST=m -CONFIG_USB_NET_CDC_SUBSET_ENABLE=m -CONFIG_USB_NET_CDC_SUBSET=m -CONFIG_USB_ALI_M5632=y -CONFIG_USB_AN2720=y -CONFIG_USB_BELKIN=y -CONFIG_USB_ARMLINUX=y -CONFIG_USB_EPSON2888=y -CONFIG_USB_KC2190=y -CONFIG_USB_NET_ZAURUS=m -CONFIG_USB_NET_CX82310_ETH=m -CONFIG_USB_NET_KALMIA=m -CONFIG_USB_NET_QMI_WWAN=m -CONFIG_USB_HSO=m -CONFIG_USB_NET_INT51X1=m -CONFIG_USB_CDC_PHONET=m -CONFIG_USB_IPHETH=m -CONFIG_USB_SIERRA_NET=m -CONFIG_USB_VL600=m -CONFIG_USB_NET_CH9200=m -CONFIG_USB_NET_AQC111=m -CONFIG_WLAN=y -# CONFIG_WIRELESS_WDS is not set -# CONFIG_WLAN_VENDOR_ADMTEK is not set -CONFIG_WLAN_VENDOR_ATH=y -# CONFIG_ATH_DEBUG is not set -# CONFIG_ATH5K is not set -# CONFIG_ATH5K_PCI is not set -# CONFIG_ATH9K is not set -# CONFIG_ATH9K_HTC is not set -# CONFIG_CARL9170 is not set -CONFIG_ATH6KL=m -CONFIG_ATH6KL_SDIO=m -CONFIG_ATH6KL_USB=m -# CONFIG_ATH6KL_DEBUG is not set -# CONFIG_ATH6KL_TRACING is not set -# CONFIG_AR5523 is not set -# CONFIG_WIL6210 is not set -# CONFIG_ATH10K is not set -# CONFIG_WCN36XX is not set -# CONFIG_ATH11K is not set -CONFIG_WLAN_VENDOR_ATMEL=y -# CONFIG_ATMEL is not set -CONFIG_AT76C50X_USB=m -CONFIG_WLAN_VENDOR_BROADCOM=y -# CONFIG_B43 is not set -# CONFIG_B43LEGACY is not set -CONFIG_BRCMUTIL=m -# CONFIG_BRCMSMAC is not set -CONFIG_BRCMFMAC=m -CONFIG_BRCMFMAC_PROTO_BCDC=y -CONFIG_BRCMFMAC_SDIO=y -CONFIG_BRCMFMAC_USB=y -# CONFIG_BRCMFMAC_PCIE is not set -# CONFIG_BRCM_TRACING is not set -# CONFIG_BRCMDBG is not set -# CONFIG_WLAN_VENDOR_CISCO is not set -# CONFIG_WLAN_VENDOR_INTEL is not set -# CONFIG_WLAN_VENDOR_INTERSIL is not set -# CONFIG_WLAN_VENDOR_MARVELL is not set -CONFIG_WLAN_VENDOR_MEDIATEK=y -CONFIG_MT7601U=m -CONFIG_MT76_CORE=m -CONFIG_MT76_LEDS=y -CONFIG_MT76_USB=m -CONFIG_MT76_SDIO=m -CONFIG_MT76x02_LIB=m -CONFIG_MT76x02_USB=m -CONFIG_MT76x0_COMMON=m -CONFIG_MT76x0U=m -# CONFIG_MT76x0E is not set -CONFIG_MT76x2_COMMON=m -# CONFIG_MT76x2E is not set -CONFIG_MT76x2U=m -# CONFIG_MT7603E is not set -CONFIG_MT7615_COMMON=m -# CONFIG_MT7615E is not set -CONFIG_MT7663_USB_SDIO_COMMON=m -CONFIG_MT7663U=m -CONFIG_MT7663S=m -# CONFIG_MT7915E is not set -CONFIG_WLAN_VENDOR_MICROCHIP=y -CONFIG_WILC1000=m -CONFIG_WILC1000_SDIO=m -# CONFIG_WILC1000_SPI is not set -# CONFIG_WILC1000_HW_OOB_INTR is not set -CONFIG_WLAN_VENDOR_RALINK=y -CONFIG_RT2X00=m -# CONFIG_RT2400PCI is not set -# CONFIG_RT2500PCI is not set -# CONFIG_RT61PCI is not set -# CONFIG_RT2800PCI is not set -CONFIG_RT2500USB=m -CONFIG_RT73USB=m -CONFIG_RT2800USB=m -CONFIG_RT2800USB_RT33XX=y -CONFIG_RT2800USB_RT35XX=y -CONFIG_RT2800USB_RT3573=y -CONFIG_RT2800USB_RT53XX=y -CONFIG_RT2800USB_RT55XX=y -CONFIG_RT2800USB_UNKNOWN=y -CONFIG_RT2800_LIB=m -CONFIG_RT2X00_LIB_USB=m -CONFIG_RT2X00_LIB=m -CONFIG_RT2X00_LIB_FIRMWARE=y -CONFIG_RT2X00_LIB_CRYPTO=y -CONFIG_RT2X00_LIB_LEDS=y -# CONFIG_RT2X00_LIB_DEBUGFS is not set -# CONFIG_RT2X00_DEBUG is not set -CONFIG_WLAN_VENDOR_REALTEK=y -# CONFIG_RTL8180 is not set -CONFIG_RTL8187=m -CONFIG_RTL8187_LEDS=y -CONFIG_RTL_CARDS=m -# CONFIG_RTL8192CE is not set -# CONFIG_RTL8192SE is not set -# CONFIG_RTL8192DE is not set -# CONFIG_RTL8723AE is not set -# CONFIG_RTL8723BE is not set -# CONFIG_RTL8188EE is not set -# CONFIG_RTL8192EE is not set -# CONFIG_RTL8821AE is not set -CONFIG_RTL8192CU=m -CONFIG_RTLWIFI=m -CONFIG_RTLWIFI_USB=m -CONFIG_RTLWIFI_DEBUG=y -CONFIG_RTL8192C_COMMON=m -CONFIG_RTL8XXXU=m -CONFIG_RTL8XXXU_UNTESTED=y -# CONFIG_RTW88 is not set -# CONFIG_WLAN_VENDOR_RSI is not set -# CONFIG_WLAN_VENDOR_ST is not set -# CONFIG_WLAN_VENDOR_TI is not set -CONFIG_WLAN_VENDOR_ZYDAS=y -CONFIG_USB_ZD1201=m -CONFIG_ZD1211RW=m -# CONFIG_ZD1211RW_DEBUG is not set -# CONFIG_WLAN_VENDOR_QUANTENNA is not set -# CONFIG_MAC80211_HWSIM is not set -CONFIG_USB_NET_RNDIS_WLAN=m -CONFIG_VIRT_WIFI=m - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# -# CONFIG_WAN is not set -CONFIG_IEEE802154_DRIVERS=m -# CONFIG_IEEE802154_FAKELB is not set -# CONFIG_IEEE802154_AT86RF230 is not set -# CONFIG_IEEE802154_MRF24J40 is not set -# CONFIG_IEEE802154_CC2520 is not set -# CONFIG_IEEE802154_ATUSB is not set -# CONFIG_IEEE802154_ADF7242 is not set -# CONFIG_IEEE802154_CA8210 is not set -# CONFIG_IEEE802154_MCR20A is not set -# CONFIG_IEEE802154_HWSIM is not set -# CONFIG_VMXNET3 is not set -CONFIG_NETDEVSIM=m -CONFIG_NET_FAILOVER=y -# CONFIG_ISDN is not set - -# -# Input device support -# -CONFIG_INPUT=y -CONFIG_INPUT_LEDS=y -CONFIG_INPUT_FF_MEMLESS=m -# CONFIG_INPUT_POLLDEV is not set -# CONFIG_INPUT_SPARSEKMAP is not set -# CONFIG_INPUT_MATRIXKMAP is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=m -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -CONFIG_INPUT_JOYDEV=m -CONFIG_INPUT_EVDEV=m -CONFIG_INPUT_EVBUG=m - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADC is not set -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ADP5589 is not set -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_QT1050 is not set -# CONFIG_KEYBOARD_QT1070 is not set -# CONFIG_KEYBOARD_QT2160 is not set -# CONFIG_KEYBOARD_DLINK_DIR685 is not set -# CONFIG_KEYBOARD_LKKBD is not set -CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_GPIO_POLLED=y -# CONFIG_KEYBOARD_TCA6416 is not set -# CONFIG_KEYBOARD_TCA8418 is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_LM8323 is not set -# CONFIG_KEYBOARD_LM8333 is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_MCS is not set -# CONFIG_KEYBOARD_MPR121 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_SAMSUNG is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_OMAP4 is not set -# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_KEYBOARD_CAP11XX is not set -# CONFIG_KEYBOARD_BCM is not set -CONFIG_INPUT_MOUSE=y -# CONFIG_MOUSE_PS2 is not set -# CONFIG_MOUSE_SERIAL is not set -CONFIG_MOUSE_APPLETOUCH=m -CONFIG_MOUSE_BCM5974=m -# CONFIG_MOUSE_CYAPA is not set -# CONFIG_MOUSE_ELAN_I2C is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_MOUSE_GPIO is not set -# CONFIG_MOUSE_SYNAPTICS_I2C is not set -CONFIG_MOUSE_SYNAPTICS_USB=m -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set -# CONFIG_RMI4_CORE is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_SERIO_ALTERA_PS2 is not set -# CONFIG_SERIO_PS2MULT is not set -# CONFIG_SERIO_ARC_PS2 is not set -# CONFIG_SERIO_APBPS2 is not set -# CONFIG_SERIO_GPIO_PS2 is not set -# CONFIG_USERIO is not set -# CONFIG_GAMEPORT is not set -# end of Hardware I/O ports -# end of Input device support - -# -# Character devices -# -CONFIG_TTY=y -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -CONFIG_LDISC_AUTOLOAD=y - -# -# Serial drivers -# -CONFIG_SERIAL_EARLYCON=y -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set -CONFIG_SERIAL_MESON=y -CONFIG_SERIAL_MESON_CONSOLE=y -# CONFIG_SERIAL_MAX3100 is not set -# CONFIG_SERIAL_MAX310X is not set -# CONFIG_SERIAL_UARTLITE is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -# CONFIG_SERIAL_SIFIVE is not set -# CONFIG_SERIAL_SCCNXP is not set -# CONFIG_SERIAL_SC16IS7XX is not set -# CONFIG_SERIAL_BCM63XX is not set -# CONFIG_SERIAL_ALTERA_JTAGUART is not set -# CONFIG_SERIAL_ALTERA_UART is not set -# CONFIG_SERIAL_IFX6X60 is not set -# CONFIG_SERIAL_XILINX_PS_UART is not set -# CONFIG_SERIAL_ARC is not set -# CONFIG_SERIAL_RP2 is not set -# CONFIG_SERIAL_FSL_LPUART is not set -# CONFIG_SERIAL_FSL_LINFLEXUART is not set -# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set -# CONFIG_SERIAL_ST_ASC is not set -# CONFIG_SERIAL_SPRD is not set -# end of Serial drivers - -# CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_N_GSM is not set -# CONFIG_NOZOMI is not set -# CONFIG_NULL_TTY is not set -# CONFIG_TRACE_SINK is not set -CONFIG_HVC_DRIVER=y -# CONFIG_HVC_DCC is not set -CONFIG_SERIAL_DEV_BUS=y -CONFIG_SERIAL_DEV_CTRL_TTYPORT=y -CONFIG_TTY_PRINTK=y -CONFIG_TTY_PRINTK_LEVEL=6 -CONFIG_VIRTIO_CONSOLE=y -# CONFIG_IPMI_HANDLER is not set -# CONFIG_IPMB_DEVICE_INTERFACE is not set -CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_TIMERIOMEM is not set -# CONFIG_HW_RANDOM_BA431 is not set -# CONFIG_HW_RANDOM_VIRTIO is not set -CONFIG_HW_RANDOM_MESON=y -# CONFIG_HW_RANDOM_CCTRNG is not set -# CONFIG_HW_RANDOM_XIPHERA is not set -# CONFIG_APPLICOM is not set -CONFIG_DEVMEM=y -# CONFIG_DEVKMEM is not set -# CONFIG_RAW_DRIVER is not set -CONFIG_DEVPORT=y -# CONFIG_TCG_TPM is not set -# CONFIG_XILLYBUS is not set -CONFIG_RANDOM_TRUST_BOOTLOADER=y -# end of Character devices - -# -# I2C support -# -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MUX=y - -# -# Multiplexer I2C Chip support -# -CONFIG_I2C_ARB_GPIO_CHALLENGE=m -CONFIG_I2C_MUX_GPIO=m -# CONFIG_I2C_MUX_GPMUX is not set -# CONFIG_I2C_MUX_LTC4306 is not set -# CONFIG_I2C_MUX_PCA9541 is not set -# CONFIG_I2C_MUX_PCA954x is not set -CONFIG_I2C_MUX_PINCTRL=m -CONFIG_I2C_MUX_REG=m -CONFIG_I2C_DEMUX_PINCTRL=m -# CONFIG_I2C_MUX_MLXCPLD is not set -# end of Multiplexer I2C Chip support - -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_ALGOBIT=y - -# -# I2C Hardware Bus support -# - -# -# PC SMBus host controller drivers -# -# CONFIG_I2C_ALI1535 is not set -# CONFIG_I2C_ALI1563 is not set -# CONFIG_I2C_ALI15X3 is not set -# CONFIG_I2C_AMD756 is not set -# CONFIG_I2C_AMD8111 is not set -# CONFIG_I2C_I801 is not set -# CONFIG_I2C_ISCH is not set -# CONFIG_I2C_PIIX4 is not set -# CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_NVIDIA_GPU is not set -# CONFIG_I2C_SIS5595 is not set -# CONFIG_I2C_SIS630 is not set -# CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_VIA is not set -# CONFIG_I2C_VIAPRO is not set - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_CBUS_GPIO is not set -# CONFIG_I2C_DESIGNWARE_PLATFORM is not set -# CONFIG_I2C_DESIGNWARE_PCI is not set -# CONFIG_I2C_EMEV2 is not set -CONFIG_I2C_GPIO=m -# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set -CONFIG_I2C_MESON=y -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_RK3X is not set -# CONFIG_I2C_SIMTEC is not set -# CONFIG_I2C_XILINX is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_DIOLAN_U2C is not set -# CONFIG_I2C_ROBOTFUZZ_OSIF is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -# end of I2C Hardware Bus support - -# CONFIG_I2C_STUB is not set -CONFIG_I2C_SLAVE=y -CONFIG_I2C_SLAVE_EEPROM=y -# CONFIG_I2C_SLAVE_TESTUNIT is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# end of I2C support - -# CONFIG_I3C is not set -CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y -CONFIG_SPI_MEM=y - -# -# SPI Master Controller Drivers -# -# CONFIG_SPI_ALTERA is not set -# CONFIG_SPI_AXI_SPI_ENGINE is not set -CONFIG_SPI_BITBANG=m -# CONFIG_SPI_CADENCE is not set -# CONFIG_SPI_CADENCE_QUADSPI is not set -# CONFIG_SPI_DESIGNWARE is not set -# CONFIG_SPI_NXP_FLEXSPI is not set -CONFIG_SPI_GPIO=m -# CONFIG_SPI_FSL_SPI is not set -CONFIG_SPI_MESON_SPICC=y -CONFIG_SPI_MESON_SPIFC=y -# CONFIG_SPI_OC_TINY is not set -# CONFIG_SPI_PXA2XX is not set -# CONFIG_SPI_ROCKCHIP is not set -# CONFIG_SPI_SC18IS602 is not set -# CONFIG_SPI_SIFIVE is not set -# CONFIG_SPI_MXIC is not set -# CONFIG_SPI_XCOMM is not set -# CONFIG_SPI_XILINX is not set -# CONFIG_SPI_ZYNQMP_GQSPI is not set -# CONFIG_SPI_AMD is not set - -# -# SPI Multiplexer support -# -# CONFIG_SPI_MUX is not set - -# -# SPI Protocol Masters -# -CONFIG_SPI_SPIDEV=y -# CONFIG_SPI_LOOPBACK_TEST is not set -# CONFIG_SPI_TLE62X0 is not set -# CONFIG_SPI_SLAVE is not set -CONFIG_SPI_DYNAMIC=y -# CONFIG_SPMI is not set -# CONFIG_HSI is not set -CONFIG_PPS=y -# CONFIG_PPS_DEBUG is not set - -# -# PPS clients support -# -# CONFIG_PPS_CLIENT_KTIMER is not set -# CONFIG_PPS_CLIENT_LDISC is not set -# CONFIG_PPS_CLIENT_GPIO is not set - -# -# PPS generators support -# - -# -# PTP clock support -# -# CONFIG_PTP_1588_CLOCK is not set - -# -# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. -# -# end of PTP clock support - -CONFIG_PINCTRL=y -CONFIG_GENERIC_PINCTRL_GROUPS=y -CONFIG_PINMUX=y -CONFIG_GENERIC_PINMUX_FUNCTIONS=y -CONFIG_PINCONF=y -CONFIG_GENERIC_PINCONF=y -# CONFIG_DEBUG_PINCTRL is not set -# CONFIG_PINCTRL_MCP23S08 is not set -CONFIG_PINCTRL_SINGLE=y -# CONFIG_PINCTRL_SX150X is not set -# CONFIG_PINCTRL_STMFX is not set -# CONFIG_PINCTRL_OCELOT is not set - -# -# Renesas pinctrl drivers -# -# end of Renesas pinctrl drivers - -CONFIG_PINCTRL_MESON=y -CONFIG_PINCTRL_MESON8=y -CONFIG_PINCTRL_MESON8B=y -CONFIG_PINCTRL_MESON8_PMX=y -CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y -CONFIG_GPIOLIB=y -CONFIG_GPIOLIB_FASTPATH_LIMIT=512 -CONFIG_OF_GPIO=y -# CONFIG_DEBUG_GPIO is not set -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_CDEV=y -CONFIG_GPIO_CDEV_V1=y -CONFIG_GPIO_GENERIC=y - -# -# Memory mapped GPIO drivers -# -# CONFIG_GPIO_74XX_MMIO is not set -# CONFIG_GPIO_ALTERA is not set -# CONFIG_GPIO_CADENCE is not set -# CONFIG_GPIO_DWAPB is not set -# CONFIG_GPIO_FTGPIO010 is not set -CONFIG_GPIO_GENERIC_PLATFORM=y -# CONFIG_GPIO_GRGPIO is not set -# CONFIG_GPIO_HLWD is not set -# CONFIG_GPIO_LOGICVC is not set -# CONFIG_GPIO_MB86S7X is not set -# CONFIG_GPIO_MPC8XXX is not set -# CONFIG_GPIO_SAMA5D2_PIOBU is not set -# CONFIG_GPIO_SIFIVE is not set -CONFIG_GPIO_SYSCON=y -# CONFIG_GPIO_XILINX is not set -# CONFIG_GPIO_ZEVIO is not set -# CONFIG_GPIO_AMD_FCH is not set -# end of Memory mapped GPIO drivers - -# -# I2C GPIO expanders -# -# CONFIG_GPIO_ADP5588 is not set -# CONFIG_GPIO_ADNP is not set -# CONFIG_GPIO_GW_PLD is not set -# CONFIG_GPIO_MAX7300 is not set -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCA9570 is not set -# CONFIG_GPIO_PCF857X is not set -# CONFIG_GPIO_TPIC2810 is not set -# end of I2C GPIO expanders - -# -# MFD GPIO expanders -# -# CONFIG_HTC_EGPIO is not set -# end of MFD GPIO expanders - -# -# PCI GPIO expanders -# -# CONFIG_GPIO_BT8XX is not set -# CONFIG_GPIO_PCI_IDIO_16 is not set -# CONFIG_GPIO_PCIE_IDIO_24 is not set -# CONFIG_GPIO_RDC321X is not set -# end of PCI GPIO expanders - -# -# SPI GPIO expanders -# -# CONFIG_GPIO_74X164 is not set -# CONFIG_GPIO_MAX3191X is not set -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MC33880 is not set -# CONFIG_GPIO_PISOSR is not set -# CONFIG_GPIO_XRA1403 is not set -# end of SPI GPIO expanders - -# -# USB GPIO expanders -# -# end of USB GPIO expanders - -# CONFIG_GPIO_AGGREGATOR is not set -# CONFIG_GPIO_MOCKUP is not set -# CONFIG_W1 is not set -CONFIG_POWER_RESET=y -# CONFIG_POWER_RESET_BRCMKONA is not set -# CONFIG_POWER_RESET_BRCMSTB is not set -CONFIG_POWER_RESET_GPIO=y -CONFIG_POWER_RESET_GPIO_RESTART=y -# CONFIG_POWER_RESET_LTC2952 is not set -CONFIG_POWER_RESET_RESTART=y -CONFIG_POWER_RESET_VERSATILE=y -CONFIG_POWER_RESET_VEXPRESS=y -CONFIG_POWER_RESET_SYSCON=y -CONFIG_POWER_RESET_SYSCON_POWEROFF=y -CONFIG_REBOOT_MODE=y -CONFIG_SYSCON_REBOOT_MODE=y -# CONFIG_NVMEM_REBOOT_MODE is not set -CONFIG_POWER_SUPPLY=y -# CONFIG_POWER_SUPPLY_DEBUG is not set -# CONFIG_POWER_SUPPLY_HWMON is not set -# CONFIG_PDA_POWER is not set -# CONFIG_GENERIC_ADC_BATTERY is not set -# CONFIG_TEST_POWER is not set -# CONFIG_CHARGER_ADP5061 is not set -# CONFIG_BATTERY_CW2015 is not set -# CONFIG_BATTERY_DS2780 is not set -# CONFIG_BATTERY_DS2781 is not set -# CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_SBS is not set -# CONFIG_CHARGER_SBS is not set -# CONFIG_MANAGER_SBS is not set -# CONFIG_BATTERY_BQ27XXX is not set -# CONFIG_BATTERY_MAX17040 is not set -# CONFIG_BATTERY_MAX17042 is not set -# CONFIG_CHARGER_ISP1704 is not set -# CONFIG_CHARGER_MAX8903 is not set -# CONFIG_CHARGER_LP8727 is not set -# CONFIG_CHARGER_GPIO is not set -# CONFIG_CHARGER_MANAGER is not set -# CONFIG_CHARGER_LT3651 is not set -# CONFIG_CHARGER_DETECTOR_MAX14656 is not set -# CONFIG_CHARGER_BQ2415X is not set -# CONFIG_CHARGER_BQ24190 is not set -# CONFIG_CHARGER_BQ24257 is not set -# CONFIG_CHARGER_BQ24735 is not set -# CONFIG_CHARGER_BQ2515X is not set -# CONFIG_CHARGER_BQ25890 is not set -# CONFIG_CHARGER_BQ25980 is not set -# CONFIG_CHARGER_SMB347 is not set -# CONFIG_BATTERY_GAUGE_LTC2941 is not set -# CONFIG_BATTERY_RT5033 is not set -# CONFIG_CHARGER_RT9455 is not set -# CONFIG_CHARGER_UCS1002 is not set -# CONFIG_CHARGER_BD99954 is not set -CONFIG_HWMON=y -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Native drivers -# -# CONFIG_SENSORS_AD7314 is not set -# CONFIG_SENSORS_AD7414 is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM1177 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADT7310 is not set -# CONFIG_SENSORS_ADT7410 is not set -# CONFIG_SENSORS_ADT7411 is not set -# CONFIG_SENSORS_ADT7462 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7475 is not set -# CONFIG_SENSORS_AS370 is not set -# CONFIG_SENSORS_ASC7621 is not set -# CONFIG_SENSORS_AXI_FAN_CONTROL is not set -CONFIG_SENSORS_ARM_SCMI=m -# CONFIG_SENSORS_ASPEED is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_CORSAIR_CPRO is not set -# CONFIG_SENSORS_DRIVETEMP is not set -# CONFIG_SENSORS_DS620 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_I5K_AMB is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_FTSTEUTATES is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_G760A is not set -# CONFIG_SENSORS_G762 is not set -# CONFIG_SENSORS_GPIO_FAN is not set -# CONFIG_SENSORS_HIH6130 is not set -CONFIG_SENSORS_IIO_HWMON=y -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_JC42 is not set -# CONFIG_SENSORS_POWR1220 is not set -# CONFIG_SENSORS_LINEAGE is not set -# CONFIG_SENSORS_LTC2945 is not set -# CONFIG_SENSORS_LTC2947_I2C is not set -# CONFIG_SENSORS_LTC2947_SPI is not set -# CONFIG_SENSORS_LTC2990 is not set -# CONFIG_SENSORS_LTC4151 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4222 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LTC4260 is not set -# CONFIG_SENSORS_LTC4261 is not set -# CONFIG_SENSORS_MAX1111 is not set -# CONFIG_SENSORS_MAX16065 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX1668 is not set -# CONFIG_SENSORS_MAX197 is not set -# CONFIG_SENSORS_MAX31722 is not set -# CONFIG_SENSORS_MAX31730 is not set -# CONFIG_SENSORS_MAX6621 is not set -# CONFIG_SENSORS_MAX6639 is not set -# CONFIG_SENSORS_MAX6642 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_MAX6697 is not set -# CONFIG_SENSORS_MAX31790 is not set -# CONFIG_SENSORS_MCP3021 is not set -# CONFIG_SENSORS_TC654 is not set -# CONFIG_SENSORS_MR75203 is not set -# CONFIG_SENSORS_ADCXX is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM70 is not set -# CONFIG_SENSORS_LM73 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_LM95234 is not set -# CONFIG_SENSORS_LM95241 is not set -# CONFIG_SENSORS_LM95245 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_NTC_THERMISTOR is not set -# CONFIG_SENSORS_NCT6683 is not set -# CONFIG_SENSORS_NCT6775 is not set -# CONFIG_SENSORS_NCT7802 is not set -# CONFIG_SENSORS_NCT7904 is not set -# CONFIG_SENSORS_NPCM7XX is not set -# CONFIG_SENSORS_OCC_P8_I2C is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_PMBUS is not set -CONFIG_SENSORS_PWM_FAN=m -# CONFIG_SENSORS_SHT15 is not set -# CONFIG_SENSORS_SHT21 is not set -# CONFIG_SENSORS_SHT3x is not set -# CONFIG_SENSORS_SHTC1 is not set -# CONFIG_SENSORS_SIS5595 is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_EMC1403 is not set -# CONFIG_SENSORS_EMC2103 is not set -# CONFIG_SENSORS_EMC6W201 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_SCH5627 is not set -# CONFIG_SENSORS_SCH5636 is not set -# CONFIG_SENSORS_STTS751 is not set -# CONFIG_SENSORS_SMM665 is not set -# CONFIG_SENSORS_ADC128D818 is not set -# CONFIG_SENSORS_ADS7828 is not set -# CONFIG_SENSORS_ADS7871 is not set -# CONFIG_SENSORS_AMC6821 is not set -# CONFIG_SENSORS_INA209 is not set -# CONFIG_SENSORS_INA2XX is not set -# CONFIG_SENSORS_INA3221 is not set -# CONFIG_SENSORS_TC74 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_TMP102 is not set -# CONFIG_SENSORS_TMP103 is not set -# CONFIG_SENSORS_TMP108 is not set -# CONFIG_SENSORS_TMP401 is not set -# CONFIG_SENSORS_TMP421 is not set -# CONFIG_SENSORS_TMP513 is not set -# CONFIG_SENSORS_VEXPRESS is not set -# CONFIG_SENSORS_VIA686A is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_VT8231 is not set -# CONFIG_SENSORS_W83773G is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83795 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83L786NG is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -CONFIG_THERMAL=y -# CONFIG_THERMAL_NETLINK is not set -# CONFIG_THERMAL_STATISTICS is not set -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y -# CONFIG_THERMAL_WRITABLE_TRIPS is not set -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set -# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set -# CONFIG_THERMAL_GOV_FAIR_SHARE is not set -CONFIG_THERMAL_GOV_STEP_WISE=y -# CONFIG_THERMAL_GOV_BANG_BANG is not set -# CONFIG_THERMAL_GOV_USER_SPACE is not set -CONFIG_CPU_THERMAL=y -CONFIG_CPU_FREQ_THERMAL=y -CONFIG_DEVFREQ_THERMAL=y -# CONFIG_THERMAL_EMULATION is not set -# CONFIG_THERMAL_MMIO is not set -CONFIG_AMLOGIC_THERMAL=y -CONFIG_GENERIC_ADC_THERMAL=m -CONFIG_WATCHDOG=y -CONFIG_WATCHDOG_CORE=y -# CONFIG_WATCHDOG_NOWAYOUT is not set -CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y -CONFIG_WATCHDOG_OPEN_TIMEOUT=0 -CONFIG_WATCHDOG_SYSFS=y - -# -# Watchdog Pretimeout Governors -# -# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -# CONFIG_GPIO_WATCHDOG is not set -# CONFIG_XILINX_WATCHDOG is not set -# CONFIG_ZIIRAVE_WATCHDOG is not set -# CONFIG_CADENCE_WATCHDOG is not set -# CONFIG_FTWDT010_WATCHDOG is not set -# CONFIG_DW_WATCHDOG is not set -# CONFIG_MAX63XX_WATCHDOG is not set -# CONFIG_MESON_GXBB_WATCHDOG is not set -CONFIG_MESON_WATCHDOG=y -# CONFIG_ARM_SMC_WATCHDOG is not set -# CONFIG_ALIM7101_WDT is not set -# CONFIG_I6300ESB_WDT is not set -# CONFIG_MEN_A21_WDT is not set - -# -# PCI-based Watchdog Cards -# -# CONFIG_PCIPCWATCHDOG is not set -# CONFIG_WDTPCI is not set - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y -# CONFIG_SSB is not set -CONFIG_BCMA_POSSIBLE=y -# CONFIG_BCMA is not set - -# -# Multifunction device drivers -# -CONFIG_MFD_CORE=m -# CONFIG_MFD_ACT8945A is not set -# CONFIG_MFD_AS3711 is not set -# CONFIG_MFD_AS3722 is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_AAT2870_CORE is not set -# CONFIG_MFD_ATMEL_FLEXCOM is not set -# CONFIG_MFD_ATMEL_HLCDC is not set -# CONFIG_MFD_BCM590XX is not set -# CONFIG_MFD_BD9571MWV is not set -# CONFIG_MFD_AXP20X_I2C is not set -# CONFIG_MFD_MADERA is not set -# CONFIG_MFD_ASIC3 is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_MFD_DA9052_SPI is not set -# CONFIG_MFD_DA9052_I2C is not set -# CONFIG_MFD_DA9055 is not set -# CONFIG_MFD_DA9062 is not set -# CONFIG_MFD_DA9063 is not set -# CONFIG_MFD_DA9150 is not set -# CONFIG_MFD_DLN2 is not set -# CONFIG_MFD_GATEWORKS_GSC is not set -# CONFIG_MFD_MC13XXX_SPI is not set -# CONFIG_MFD_MC13XXX_I2C is not set -# CONFIG_MFD_MP2629 is not set -# CONFIG_MFD_HI6421_PMIC is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_HTC_I2CPLD is not set -# CONFIG_LPC_ICH is not set -# CONFIG_LPC_SCH is not set -# CONFIG_MFD_IQS62X is not set -# CONFIG_MFD_JANZ_CMODIO is not set -# CONFIG_MFD_KEMPLD is not set -# CONFIG_MFD_88PM800 is not set -# CONFIG_MFD_88PM805 is not set -# CONFIG_MFD_88PM860X is not set -# CONFIG_MFD_MAX14577 is not set -# CONFIG_MFD_MAX77620 is not set -# CONFIG_MFD_MAX77650 is not set -# CONFIG_MFD_MAX77686 is not set -# CONFIG_MFD_MAX77693 is not set -# CONFIG_MFD_MAX77843 is not set -# CONFIG_MFD_MAX8907 is not set -# CONFIG_MFD_MAX8925 is not set -# CONFIG_MFD_MAX8997 is not set -# CONFIG_MFD_MAX8998 is not set -# CONFIG_MFD_MT6360 is not set -# CONFIG_MFD_MT6397 is not set -# CONFIG_MFD_MENF21BMC is not set -# CONFIG_EZX_PCAP is not set -# CONFIG_MFD_CPCAP is not set -# CONFIG_MFD_VIPERBOARD is not set -# CONFIG_MFD_RETU is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_PM8XXX is not set -# CONFIG_MFD_RDC321X is not set -# CONFIG_MFD_RT5033 is not set -# CONFIG_MFD_RC5T583 is not set -# CONFIG_MFD_RK808 is not set -# CONFIG_MFD_RN5T618 is not set -# CONFIG_MFD_SEC_CORE is not set -# CONFIG_MFD_SI476X_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_SKY81452 is not set -# CONFIG_ABX500_CORE is not set -# CONFIG_MFD_STMPE is not set -CONFIG_MFD_SYSCON=y -# CONFIG_MFD_TI_AM335X_TSCADC is not set -# CONFIG_MFD_LP3943 is not set -# CONFIG_MFD_LP8788 is not set -# CONFIG_MFD_TI_LMU is not set -# CONFIG_MFD_PALMAS is not set -# CONFIG_TPS6105X is not set -# CONFIG_TPS65010 is not set -# CONFIG_TPS6507X is not set -# CONFIG_MFD_TPS65086 is not set -# CONFIG_MFD_TPS65090 is not set -# CONFIG_MFD_TPS65217 is not set -# CONFIG_MFD_TI_LP873X is not set -# CONFIG_MFD_TI_LP87565 is not set -# CONFIG_MFD_TPS65218 is not set -# CONFIG_MFD_TPS6586X is not set -# CONFIG_MFD_TPS65910 is not set -# CONFIG_MFD_TPS65912_I2C is not set -# CONFIG_MFD_TPS65912_SPI is not set -# CONFIG_MFD_TPS80031 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_TWL6040_CORE is not set -# CONFIG_MFD_WL1273_CORE is not set -# CONFIG_MFD_LM3533 is not set -# CONFIG_MFD_TC3589X is not set -# CONFIG_MFD_T7L66XB is not set -# CONFIG_MFD_TC6387XB is not set -# CONFIG_MFD_TC6393XB is not set -# CONFIG_MFD_TQMX86 is not set -# CONFIG_MFD_VX855 is not set -# CONFIG_MFD_LOCHNAGAR is not set -# CONFIG_MFD_ARIZONA_I2C is not set -# CONFIG_MFD_ARIZONA_SPI is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X_I2C is not set -# CONFIG_MFD_WM831X_SPI is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_WM8994 is not set -# CONFIG_MFD_ROHM_BD718XX is not set -# CONFIG_MFD_ROHM_BD70528 is not set -# CONFIG_MFD_ROHM_BD71828 is not set -# CONFIG_MFD_STPMIC1 is not set -# CONFIG_MFD_STMFX is not set -# CONFIG_MFD_KHADAS_MCU is not set -# CONFIG_MFD_VEXPRESS_SYSREG is not set -# CONFIG_RAVE_SP_CORE is not set -# CONFIG_MFD_INTEL_M10_BMC is not set -# end of Multifunction device drivers - -CONFIG_REGULATOR=y -# CONFIG_REGULATOR_DEBUG is not set -CONFIG_REGULATOR_FIXED_VOLTAGE=y -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set -# CONFIG_REGULATOR_88PG86X is not set -# CONFIG_REGULATOR_ACT8865 is not set -# CONFIG_REGULATOR_AD5398 is not set -# CONFIG_REGULATOR_DA9210 is not set -# CONFIG_REGULATOR_DA9211 is not set -# CONFIG_REGULATOR_FAN53555 is not set -# CONFIG_REGULATOR_FAN53880 is not set -CONFIG_REGULATOR_GPIO=y -# CONFIG_REGULATOR_ISL9305 is not set -# CONFIG_REGULATOR_ISL6271A is not set -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_LP3972 is not set -# CONFIG_REGULATOR_LP872X is not set -# CONFIG_REGULATOR_LP8755 is not set -# CONFIG_REGULATOR_LTC3589 is not set -# CONFIG_REGULATOR_LTC3676 is not set -# CONFIG_REGULATOR_MAX1586 is not set -# CONFIG_REGULATOR_MAX8649 is not set -# CONFIG_REGULATOR_MAX8660 is not set -# CONFIG_REGULATOR_MAX8952 is not set -# CONFIG_REGULATOR_MAX8973 is not set -# CONFIG_REGULATOR_MAX77826 is not set -# CONFIG_REGULATOR_MCP16502 is not set -# CONFIG_REGULATOR_MP5416 is not set -# CONFIG_REGULATOR_MP8859 is not set -# CONFIG_REGULATOR_MP886X is not set -# CONFIG_REGULATOR_MPQ7920 is not set -# CONFIG_REGULATOR_MT6311 is not set -# CONFIG_REGULATOR_PCA9450 is not set -# CONFIG_REGULATOR_PFUZE100 is not set -# CONFIG_REGULATOR_PV88060 is not set -# CONFIG_REGULATOR_PV88080 is not set -# CONFIG_REGULATOR_PV88090 is not set -CONFIG_REGULATOR_PWM=y -# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set -# CONFIG_REGULATOR_RT4801 is not set -# CONFIG_REGULATOR_RTMV20 is not set -# CONFIG_REGULATOR_SLG51000 is not set -# CONFIG_REGULATOR_SY8106A is not set -# CONFIG_REGULATOR_SY8824X is not set -# CONFIG_REGULATOR_SY8827N is not set -# CONFIG_REGULATOR_TPS51632 is not set -# CONFIG_REGULATOR_TPS62360 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -# CONFIG_REGULATOR_TPS65132 is not set -# CONFIG_REGULATOR_TPS6524X is not set -# CONFIG_REGULATOR_VCTRL is not set -# CONFIG_REGULATOR_VEXPRESS is not set -CONFIG_RC_CORE=m -CONFIG_RC_MAP=m -CONFIG_LIRC=y -CONFIG_RC_DECODERS=y -CONFIG_IR_NEC_DECODER=m -CONFIG_IR_RC5_DECODER=m -CONFIG_IR_RC6_DECODER=m -CONFIG_IR_JVC_DECODER=m -CONFIG_IR_SONY_DECODER=m -CONFIG_IR_SANYO_DECODER=m -CONFIG_IR_SHARP_DECODER=m -CONFIG_IR_MCE_KBD_DECODER=m -CONFIG_IR_XMP_DECODER=m -CONFIG_IR_IMON_DECODER=m -CONFIG_IR_RCMM_DECODER=m -CONFIG_RC_DEVICES=y -CONFIG_RC_ATI_REMOTE=m -# CONFIG_IR_HIX5HD2 is not set -# CONFIG_IR_IMON is not set -# CONFIG_IR_IMON_RAW is not set -CONFIG_IR_MCEUSB=m -CONFIG_IR_MESON=m -# CONFIG_IR_REDRAT3 is not set -# CONFIG_IR_SPI is not set -# CONFIG_IR_STREAMZAP is not set -CONFIG_IR_IGORPLUGUSB=m -CONFIG_IR_IGUANA=m -CONFIG_IR_TTUSBIR=m -# CONFIG_RC_LOOPBACK is not set -CONFIG_IR_GPIO_CIR=m -CONFIG_IR_GPIO_TX=m -# CONFIG_IR_PWM_TX is not set -# CONFIG_IR_SERIAL is not set -# CONFIG_IR_SIR is not set -# CONFIG_RC_XBOX_DVD is not set -# CONFIG_IR_TOY is not set -CONFIG_CEC_CORE=y -CONFIG_CEC_NOTIFIER=y -CONFIG_MEDIA_CEC_SUPPORT=y -# CONFIG_CEC_CH7322 is not set -CONFIG_CEC_MESON_AO=y -# CONFIG_CEC_MESON_G12A_AO is not set -# CONFIG_USB_PULSE8_CEC is not set -# CONFIG_USB_RAINSHADOW_CEC is not set -CONFIG_MEDIA_SUPPORT=m -# CONFIG_MEDIA_SUPPORT_FILTER is not set -CONFIG_MEDIA_SUBDRV_AUTOSELECT=y - -# -# Media device types -# -CONFIG_MEDIA_CAMERA_SUPPORT=y -CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -CONFIG_MEDIA_RADIO_SUPPORT=y -CONFIG_MEDIA_SDR_SUPPORT=y -CONFIG_MEDIA_PLATFORM_SUPPORT=y -CONFIG_MEDIA_TEST_SUPPORT=y -# end of Media device types - -# -# Media core support -# -CONFIG_VIDEO_DEV=m -CONFIG_MEDIA_CONTROLLER=y -CONFIG_DVB_CORE=m -# end of Media core support - -# -# Video4Linux options -# -CONFIG_VIDEO_V4L2=m -CONFIG_VIDEO_V4L2_I2C=y -CONFIG_VIDEO_V4L2_SUBDEV_API=y -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -CONFIG_VIDEO_TUNER=m -CONFIG_V4L2_MEM2MEM_DEV=m -CONFIG_V4L2_FWNODE=m -CONFIG_VIDEOBUF_GEN=m -CONFIG_VIDEOBUF_VMALLOC=m -# end of Video4Linux options - -# -# Media controller options -# -CONFIG_MEDIA_CONTROLLER_DVB=y -CONFIG_MEDIA_CONTROLLER_REQUEST_API=y - -# -# Please notice that the enabled Media controller Request API is EXPERIMENTAL -# -# end of Media controller options - -# -# Digital TV options -# -# CONFIG_DVB_MMAP is not set -CONFIG_DVB_NET=y -CONFIG_DVB_MAX_ADAPTERS=16 -CONFIG_DVB_DYNAMIC_MINORS=y -# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set -# CONFIG_DVB_ULE_DEBUG is not set -# end of Digital TV options - -# -# Media drivers -# -CONFIG_TTPCI_EEPROM=m -CONFIG_MEDIA_USB_SUPPORT=y - -# -# Webcam devices -# -CONFIG_USB_VIDEO_CLASS=m -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -CONFIG_USB_GSPCA=m -CONFIG_USB_M5602=m -CONFIG_USB_STV06XX=m -CONFIG_USB_GL860=m -CONFIG_USB_GSPCA_BENQ=m -CONFIG_USB_GSPCA_CONEX=m -CONFIG_USB_GSPCA_CPIA1=m -CONFIG_USB_GSPCA_DTCS033=m -CONFIG_USB_GSPCA_ETOMS=m -CONFIG_USB_GSPCA_FINEPIX=m -CONFIG_USB_GSPCA_JEILINJ=m -CONFIG_USB_GSPCA_JL2005BCD=m -CONFIG_USB_GSPCA_KINECT=m -CONFIG_USB_GSPCA_KONICA=m -CONFIG_USB_GSPCA_MARS=m -CONFIG_USB_GSPCA_MR97310A=m -CONFIG_USB_GSPCA_NW80X=m -CONFIG_USB_GSPCA_OV519=m -CONFIG_USB_GSPCA_OV534=m -CONFIG_USB_GSPCA_OV534_9=m -CONFIG_USB_GSPCA_PAC207=m -CONFIG_USB_GSPCA_PAC7302=m -CONFIG_USB_GSPCA_PAC7311=m -CONFIG_USB_GSPCA_SE401=m -CONFIG_USB_GSPCA_SN9C2028=m -CONFIG_USB_GSPCA_SN9C20X=m -CONFIG_USB_GSPCA_SONIXB=m -CONFIG_USB_GSPCA_SONIXJ=m -CONFIG_USB_GSPCA_SPCA500=m -CONFIG_USB_GSPCA_SPCA501=m -CONFIG_USB_GSPCA_SPCA505=m -CONFIG_USB_GSPCA_SPCA506=m -CONFIG_USB_GSPCA_SPCA508=m -CONFIG_USB_GSPCA_SPCA561=m -CONFIG_USB_GSPCA_SPCA1528=m -CONFIG_USB_GSPCA_SQ905=m -CONFIG_USB_GSPCA_SQ905C=m -CONFIG_USB_GSPCA_SQ930X=m -CONFIG_USB_GSPCA_STK014=m -CONFIG_USB_GSPCA_STK1135=m -CONFIG_USB_GSPCA_STV0680=m -CONFIG_USB_GSPCA_SUNPLUS=m -CONFIG_USB_GSPCA_T613=m -CONFIG_USB_GSPCA_TOPRO=m -CONFIG_USB_GSPCA_TOUPTEK=m -CONFIG_USB_GSPCA_TV8532=m -CONFIG_USB_GSPCA_VC032X=m -CONFIG_USB_GSPCA_VICAM=m -CONFIG_USB_GSPCA_XIRLINK_CIT=m -CONFIG_USB_GSPCA_ZC3XX=m -CONFIG_USB_PWC=m -# CONFIG_USB_PWC_DEBUG is not set -CONFIG_USB_PWC_INPUT_EVDEV=y -CONFIG_VIDEO_CPIA2=m -CONFIG_USB_ZR364XX=m -CONFIG_USB_STKWEBCAM=m -CONFIG_USB_S2255=m -CONFIG_VIDEO_USBTV=m - -# -# Analog TV USB devices -# -CONFIG_VIDEO_PVRUSB2=m -CONFIG_VIDEO_PVRUSB2_SYSFS=y -CONFIG_VIDEO_PVRUSB2_DVB=y -# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set -CONFIG_VIDEO_HDPVR=m -CONFIG_VIDEO_STK1160_COMMON=m -CONFIG_VIDEO_STK1160=m -CONFIG_VIDEO_GO7007=m -CONFIG_VIDEO_GO7007_USB=m -CONFIG_VIDEO_GO7007_LOADER=m -CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m - -# -# Analog/digital TV USB devices -# -CONFIG_VIDEO_AU0828=m -CONFIG_VIDEO_AU0828_V4L2=y -CONFIG_VIDEO_AU0828_RC=y -CONFIG_VIDEO_CX231XX=m -CONFIG_VIDEO_CX231XX_RC=y -CONFIG_VIDEO_CX231XX_ALSA=m -CONFIG_VIDEO_CX231XX_DVB=m -CONFIG_VIDEO_TM6000=m -CONFIG_VIDEO_TM6000_ALSA=m -CONFIG_VIDEO_TM6000_DVB=m - -# -# Digital TV USB devices -# -CONFIG_DVB_USB=m -# CONFIG_DVB_USB_DEBUG is not set -CONFIG_DVB_USB_DIB3000MC=m -CONFIG_DVB_USB_A800=m -CONFIG_DVB_USB_DIBUSB_MB=m -CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y -CONFIG_DVB_USB_DIBUSB_MC=m -CONFIG_DVB_USB_DIB0700=m -CONFIG_DVB_USB_UMT_010=m -CONFIG_DVB_USB_CXUSB=m -CONFIG_DVB_USB_CXUSB_ANALOG=y -CONFIG_DVB_USB_M920X=m -CONFIG_DVB_USB_DIGITV=m -CONFIG_DVB_USB_VP7045=m -CONFIG_DVB_USB_VP702X=m -CONFIG_DVB_USB_GP8PSK=m -CONFIG_DVB_USB_NOVA_T_USB2=m -CONFIG_DVB_USB_TTUSB2=m -CONFIG_DVB_USB_DTT200U=m -CONFIG_DVB_USB_OPERA1=m -CONFIG_DVB_USB_AF9005=m -CONFIG_DVB_USB_AF9005_REMOTE=m -CONFIG_DVB_USB_PCTV452E=m -CONFIG_DVB_USB_DW2102=m -CONFIG_DVB_USB_CINERGY_T2=m -CONFIG_DVB_USB_DTV5100=m -CONFIG_DVB_USB_AZ6027=m -CONFIG_DVB_USB_TECHNISAT_USB2=m -CONFIG_DVB_USB_V2=m -CONFIG_DVB_USB_AF9015=m -CONFIG_DVB_USB_AF9035=m -CONFIG_DVB_USB_ANYSEE=m -CONFIG_DVB_USB_AU6610=m -CONFIG_DVB_USB_AZ6007=m -CONFIG_DVB_USB_CE6230=m -CONFIG_DVB_USB_EC168=m -CONFIG_DVB_USB_GL861=m -CONFIG_DVB_USB_LME2510=m -CONFIG_DVB_USB_MXL111SF=m -CONFIG_DVB_USB_RTL28XXU=m -CONFIG_DVB_USB_DVBSKY=m -CONFIG_DVB_USB_ZD1301=m -CONFIG_DVB_TTUSB_BUDGET=m -CONFIG_DVB_TTUSB_DEC=m -CONFIG_SMS_USB_DRV=m -CONFIG_DVB_B2C2_FLEXCOP_USB=m -# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set -CONFIG_DVB_AS102=m - -# -# Webcam, TV (analog/digital) USB devices -# -CONFIG_VIDEO_EM28XX=m -CONFIG_VIDEO_EM28XX_V4L2=m -CONFIG_VIDEO_EM28XX_ALSA=m -CONFIG_VIDEO_EM28XX_DVB=m -CONFIG_VIDEO_EM28XX_RC=m - -# -# Software defined radio USB devices -# -CONFIG_USB_AIRSPY=m -CONFIG_USB_HACKRF=m -CONFIG_USB_MSI2500=m -# CONFIG_MEDIA_PCI_SUPPORT is not set -CONFIG_RADIO_ADAPTERS=y -CONFIG_RADIO_TEA575X=m -CONFIG_RADIO_SI470X=m -CONFIG_USB_SI470X=m -# CONFIG_I2C_SI470X is not set -CONFIG_RADIO_SI4713=m -CONFIG_USB_SI4713=m -# CONFIG_PLATFORM_SI4713 is not set -CONFIG_I2C_SI4713=m -CONFIG_USB_MR800=m -CONFIG_USB_DSBR=m -# CONFIG_RADIO_MAXIRADIO is not set -CONFIG_RADIO_SHARK=m -CONFIG_RADIO_SHARK2=m -CONFIG_USB_KEENE=m -CONFIG_USB_RAREMONO=m -CONFIG_USB_MA901=m -# CONFIG_RADIO_TEA5764 is not set -# CONFIG_RADIO_SAA7706H is not set -# CONFIG_RADIO_TEF6862 is not set -# CONFIG_RADIO_WL1273 is not set -CONFIG_MEDIA_COMMON_OPTIONS=y - -# -# common driver options -# -CONFIG_VIDEO_CX2341X=m -CONFIG_VIDEO_TVEEPROM=m -CONFIG_CYPRESS_FIRMWARE=m -CONFIG_VIDEOBUF2_CORE=m -CONFIG_VIDEOBUF2_V4L2=m -CONFIG_VIDEOBUF2_MEMOPS=m -CONFIG_VIDEOBUF2_DMA_CONTIG=m -CONFIG_VIDEOBUF2_VMALLOC=m -CONFIG_DVB_B2C2_FLEXCOP=m -CONFIG_SMS_SIANO_MDTV=m -CONFIG_SMS_SIANO_RC=y -CONFIG_VIDEO_V4L2_TPG=m -CONFIG_V4L_PLATFORM_DRIVERS=y -# CONFIG_VIDEO_CAFE_CCIC is not set -# CONFIG_VIDEO_CADENCE is not set -# CONFIG_VIDEO_ASPEED is not set -CONFIG_VIDEO_MUX=m -# CONFIG_VIDEO_XILINX is not set -CONFIG_V4L_MEM2MEM_DRIVERS=y -CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m -CONFIG_DVB_PLATFORM_DRIVERS=y -# CONFIG_DVB_C8SECTPFE is not set -CONFIG_SDR_PLATFORM_DRIVERS=y - -# -# MMC/SDIO DVB adapters -# -# CONFIG_SMS_SDIO_DRV is not set -CONFIG_V4L_TEST_DRIVERS=y -CONFIG_VIDEO_VIMC=m -CONFIG_VIDEO_VIVID=m -CONFIG_VIDEO_VIVID_CEC=y -CONFIG_VIDEO_VIVID_MAX_DEVS=64 -CONFIG_VIDEO_VIM2M=m -CONFIG_VIDEO_VICODEC=m -# CONFIG_DVB_TEST_DRIVERS is not set -# end of Media drivers - -# -# Media ancillary drivers -# -CONFIG_MEDIA_ATTACH=y - -# -# IR I2C driver auto-selected by 'Autoselect ancillary drivers' -# -CONFIG_VIDEO_IR_I2C=m - -# -# Audio decoders, processors and mixers -# -# CONFIG_VIDEO_TVAUDIO is not set -# CONFIG_VIDEO_TDA7432 is not set -# CONFIG_VIDEO_TDA9840 is not set -# CONFIG_VIDEO_TDA1997X is not set -# CONFIG_VIDEO_TEA6415C is not set -# CONFIG_VIDEO_TEA6420 is not set -CONFIG_VIDEO_MSP3400=m -# CONFIG_VIDEO_CS3308 is not set -# CONFIG_VIDEO_CS5345 is not set -CONFIG_VIDEO_CS53L32A=m -# CONFIG_VIDEO_TLV320AIC23B is not set -CONFIG_VIDEO_UDA1342=m -CONFIG_VIDEO_WM8775=m -# CONFIG_VIDEO_WM8739 is not set -# CONFIG_VIDEO_VP27SMPX is not set -CONFIG_VIDEO_SONY_BTF_MPX=m -# end of Audio decoders, processors and mixers - -# -# RDS decoders -# -# CONFIG_VIDEO_SAA6588 is not set -# end of RDS decoders - -# -# Video decoders -# -# CONFIG_VIDEO_ADV7180 is not set -# CONFIG_VIDEO_ADV7183 is not set -# CONFIG_VIDEO_ADV748X is not set -# CONFIG_VIDEO_ADV7604 is not set -# CONFIG_VIDEO_ADV7842 is not set -# CONFIG_VIDEO_BT819 is not set -# CONFIG_VIDEO_BT856 is not set -# CONFIG_VIDEO_BT866 is not set -# CONFIG_VIDEO_KS0127 is not set -# CONFIG_VIDEO_ML86V7667 is not set -# CONFIG_VIDEO_SAA7110 is not set -CONFIG_VIDEO_SAA711X=m -# CONFIG_VIDEO_TC358743 is not set -# CONFIG_VIDEO_TVP514X is not set -CONFIG_VIDEO_TVP5150=m -# CONFIG_VIDEO_TVP7002 is not set -CONFIG_VIDEO_TW2804=m -CONFIG_VIDEO_TW9903=m -CONFIG_VIDEO_TW9906=m -# CONFIG_VIDEO_TW9910 is not set -# CONFIG_VIDEO_VPX3220 is not set -# CONFIG_VIDEO_MAX9286 is not set - -# -# Video and audio decoders -# -# CONFIG_VIDEO_SAA717X is not set -CONFIG_VIDEO_CX25840=m -# end of Video decoders - -# -# Video encoders -# -# CONFIG_VIDEO_SAA7127 is not set -# CONFIG_VIDEO_SAA7185 is not set -# CONFIG_VIDEO_ADV7170 is not set -# CONFIG_VIDEO_ADV7175 is not set -# CONFIG_VIDEO_ADV7343 is not set -# CONFIG_VIDEO_ADV7393 is not set -# CONFIG_VIDEO_ADV7511 is not set -# CONFIG_VIDEO_AD9389B is not set -# CONFIG_VIDEO_AK881X is not set -# CONFIG_VIDEO_THS8200 is not set -# end of Video encoders - -# -# Video improvement chips -# -# CONFIG_VIDEO_UPD64031A is not set -# CONFIG_VIDEO_UPD64083 is not set -# end of Video improvement chips - -# -# Audio/Video compression chips -# -# CONFIG_VIDEO_SAA6752HS is not set -# end of Audio/Video compression chips - -# -# SDR tuner chips -# -# CONFIG_SDR_MAX2175 is not set -# end of SDR tuner chips - -# -# Miscellaneous helper chips -# -# CONFIG_VIDEO_THS7303 is not set -# CONFIG_VIDEO_M52790 is not set -# CONFIG_VIDEO_I2C is not set -# CONFIG_VIDEO_ST_MIPID02 is not set -# end of Miscellaneous helper chips - -# -# Camera sensor devices -# -# CONFIG_VIDEO_HI556 is not set -# CONFIG_VIDEO_IMX214 is not set -# CONFIG_VIDEO_IMX219 is not set -# CONFIG_VIDEO_IMX258 is not set -# CONFIG_VIDEO_IMX274 is not set -# CONFIG_VIDEO_IMX290 is not set -# CONFIG_VIDEO_IMX319 is not set -# CONFIG_VIDEO_IMX355 is not set -CONFIG_VIDEO_OV2640=m -# CONFIG_VIDEO_OV2659 is not set -# CONFIG_VIDEO_OV2680 is not set -# CONFIG_VIDEO_OV2685 is not set -# CONFIG_VIDEO_OV5640 is not set -# CONFIG_VIDEO_OV5645 is not set -# CONFIG_VIDEO_OV5647 is not set -# CONFIG_VIDEO_OV6650 is not set -# CONFIG_VIDEO_OV5670 is not set -# CONFIG_VIDEO_OV5675 is not set -# CONFIG_VIDEO_OV5695 is not set -# CONFIG_VIDEO_OV7251 is not set -# CONFIG_VIDEO_OV772X is not set -CONFIG_VIDEO_OV7640=m -# CONFIG_VIDEO_OV7670 is not set -# CONFIG_VIDEO_OV7740 is not set -# CONFIG_VIDEO_OV8856 is not set -# CONFIG_VIDEO_OV9640 is not set -# CONFIG_VIDEO_OV9650 is not set -# CONFIG_VIDEO_OV13858 is not set -# CONFIG_VIDEO_VS6624 is not set -# CONFIG_VIDEO_MT9M001 is not set -# CONFIG_VIDEO_MT9M032 is not set -# CONFIG_VIDEO_MT9M111 is not set -# CONFIG_VIDEO_MT9P031 is not set -# CONFIG_VIDEO_MT9T001 is not set -# CONFIG_VIDEO_MT9T112 is not set -CONFIG_VIDEO_MT9V011=m -# CONFIG_VIDEO_MT9V032 is not set -# CONFIG_VIDEO_MT9V111 is not set -# CONFIG_VIDEO_SR030PC30 is not set -# CONFIG_VIDEO_NOON010PC30 is not set -# CONFIG_VIDEO_M5MOLS is not set -# CONFIG_VIDEO_RDACM20 is not set -# CONFIG_VIDEO_RJ54N1 is not set -# CONFIG_VIDEO_S5K6AA is not set -# CONFIG_VIDEO_S5K6A3 is not set -# CONFIG_VIDEO_S5K4ECGX is not set -# CONFIG_VIDEO_S5K5BAF is not set -# CONFIG_VIDEO_SMIAPP is not set -# CONFIG_VIDEO_ET8EK8 is not set -# CONFIG_VIDEO_S5C73M3 is not set -# end of Camera sensor devices - -# -# Lens drivers -# -# CONFIG_VIDEO_AD5820 is not set -# CONFIG_VIDEO_AK7375 is not set -# CONFIG_VIDEO_DW9714 is not set -# CONFIG_VIDEO_DW9768 is not set -# CONFIG_VIDEO_DW9807_VCM is not set -# end of Lens drivers - -# -# Flash devices -# -# CONFIG_VIDEO_ADP1653 is not set -# CONFIG_VIDEO_LM3560 is not set -# CONFIG_VIDEO_LM3646 is not set -# end of Flash devices - -# -# SPI helper chips -# -# CONFIG_VIDEO_GS1662 is not set -# end of SPI helper chips - -# -# Media SPI Adapters -# -# CONFIG_CXD2880_SPI_DRV is not set -# end of Media SPI Adapters - -CONFIG_MEDIA_TUNER=m - -# -# Customize TV tuners -# -CONFIG_MEDIA_TUNER_SIMPLE=m -CONFIG_MEDIA_TUNER_TDA18250=m -CONFIG_MEDIA_TUNER_TDA8290=m -CONFIG_MEDIA_TUNER_TDA827X=m -CONFIG_MEDIA_TUNER_TDA18271=m -CONFIG_MEDIA_TUNER_TDA9887=m -CONFIG_MEDIA_TUNER_TEA5761=m -CONFIG_MEDIA_TUNER_TEA5767=m -CONFIG_MEDIA_TUNER_MSI001=m -CONFIG_MEDIA_TUNER_MT20XX=m -CONFIG_MEDIA_TUNER_MT2060=m -CONFIG_MEDIA_TUNER_MT2063=m -CONFIG_MEDIA_TUNER_MT2266=m -# CONFIG_MEDIA_TUNER_MT2131 is not set -CONFIG_MEDIA_TUNER_QT1010=m -CONFIG_MEDIA_TUNER_XC2028=m -CONFIG_MEDIA_TUNER_XC5000=m -CONFIG_MEDIA_TUNER_XC4000=m -CONFIG_MEDIA_TUNER_MXL5005S=m -CONFIG_MEDIA_TUNER_MXL5007T=m -CONFIG_MEDIA_TUNER_MC44S803=m -CONFIG_MEDIA_TUNER_MAX2165=m -CONFIG_MEDIA_TUNER_TDA18218=m -CONFIG_MEDIA_TUNER_FC0011=m -CONFIG_MEDIA_TUNER_FC0012=m -CONFIG_MEDIA_TUNER_FC0013=m -CONFIG_MEDIA_TUNER_TDA18212=m -CONFIG_MEDIA_TUNER_E4000=m -CONFIG_MEDIA_TUNER_FC2580=m -# CONFIG_MEDIA_TUNER_M88RS6000T is not set -CONFIG_MEDIA_TUNER_TUA9001=m -CONFIG_MEDIA_TUNER_SI2157=m -CONFIG_MEDIA_TUNER_IT913X=m -CONFIG_MEDIA_TUNER_R820T=m -# CONFIG_MEDIA_TUNER_MXL301RF is not set -CONFIG_MEDIA_TUNER_QM1D1C0042=m -# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set -# end of Customize TV tuners - -# -# Customise DVB Frontends -# - -# -# Multistandard (satellite) frontends -# -CONFIG_DVB_STB0899=m -CONFIG_DVB_STB6100=m -CONFIG_DVB_STV090x=m -# CONFIG_DVB_STV0910 is not set -CONFIG_DVB_STV6110x=m -# CONFIG_DVB_STV6111 is not set -# CONFIG_DVB_MXL5XX is not set -CONFIG_DVB_M88DS3103=m - -# -# Multistandard (cable + terrestrial) frontends -# -CONFIG_DVB_DRXK=m -CONFIG_DVB_TDA18271C2DD=m -CONFIG_DVB_SI2165=m -CONFIG_DVB_MN88472=m -CONFIG_DVB_MN88473=m - -# -# DVB-S (satellite) frontends -# -# CONFIG_DVB_CX24110 is not set -CONFIG_DVB_CX24123=m -CONFIG_DVB_MT312=m -# CONFIG_DVB_ZL10036 is not set -CONFIG_DVB_ZL10039=m -CONFIG_DVB_S5H1420=m -CONFIG_DVB_STV0288=m -CONFIG_DVB_STB6000=m -CONFIG_DVB_STV0299=m -CONFIG_DVB_STV6110=m -CONFIG_DVB_STV0900=m -CONFIG_DVB_TDA8083=m -CONFIG_DVB_TDA10086=m -# CONFIG_DVB_TDA8261 is not set -# CONFIG_DVB_VES1X93 is not set -CONFIG_DVB_TUNER_ITD1000=m -CONFIG_DVB_TUNER_CX24113=m -CONFIG_DVB_TDA826X=m -# CONFIG_DVB_TUA6100 is not set -CONFIG_DVB_CX24116=m -# CONFIG_DVB_CX24117 is not set -CONFIG_DVB_CX24120=m -CONFIG_DVB_SI21XX=m -CONFIG_DVB_TS2020=m -CONFIG_DVB_DS3000=m -CONFIG_DVB_MB86A16=m -CONFIG_DVB_TDA10071=m - -# -# DVB-T (terrestrial) frontends -# -# CONFIG_DVB_SP8870 is not set -# CONFIG_DVB_SP887X is not set -CONFIG_DVB_CX22700=m -CONFIG_DVB_CX22702=m -# CONFIG_DVB_S5H1432 is not set -CONFIG_DVB_DRXD=m -# CONFIG_DVB_L64781 is not set -CONFIG_DVB_TDA1004X=m -CONFIG_DVB_NXT6000=m -CONFIG_DVB_MT352=m -CONFIG_DVB_ZL10353=m -CONFIG_DVB_DIB3000MB=m -CONFIG_DVB_DIB3000MC=m -CONFIG_DVB_DIB7000M=m -CONFIG_DVB_DIB7000P=m -# CONFIG_DVB_DIB9000 is not set -CONFIG_DVB_TDA10048=m -CONFIG_DVB_AF9013=m -CONFIG_DVB_EC100=m -# CONFIG_DVB_STV0367 is not set -CONFIG_DVB_CXD2820R=m -CONFIG_DVB_CXD2841ER=m -CONFIG_DVB_RTL2830=m -CONFIG_DVB_RTL2832=m -CONFIG_DVB_RTL2832_SDR=m -CONFIG_DVB_SI2168=m -CONFIG_DVB_AS102_FE=m -CONFIG_DVB_ZD1301_DEMOD=m -CONFIG_DVB_GP8PSK_FE=m -# CONFIG_DVB_CXD2880 is not set - -# -# DVB-C (cable) frontends -# -CONFIG_DVB_VES1820=m -# CONFIG_DVB_TDA10021 is not set -CONFIG_DVB_TDA10023=m -CONFIG_DVB_STV0297=m - -# -# ATSC (North American/Korean Terrestrial/Cable DTV) frontends -# -CONFIG_DVB_NXT200X=m -# CONFIG_DVB_OR51211 is not set -# CONFIG_DVB_OR51132 is not set -CONFIG_DVB_BCM3510=m -CONFIG_DVB_LGDT330X=m -CONFIG_DVB_LGDT3305=m -CONFIG_DVB_LGDT3306A=m -CONFIG_DVB_LG2160=m -CONFIG_DVB_S5H1409=m -CONFIG_DVB_AU8522=m -CONFIG_DVB_AU8522_DTV=m -CONFIG_DVB_AU8522_V4L=m -CONFIG_DVB_S5H1411=m - -# -# ISDB-T (terrestrial) frontends -# -CONFIG_DVB_S921=m -CONFIG_DVB_DIB8000=m -CONFIG_DVB_MB86A20S=m - -# -# ISDB-S (satellite) & ISDB-T (terrestrial) frontends -# -CONFIG_DVB_TC90522=m -# CONFIG_DVB_MN88443X is not set - -# -# Digital terrestrial only tuners/PLL -# -CONFIG_DVB_PLL=m -CONFIG_DVB_TUNER_DIB0070=m -CONFIG_DVB_TUNER_DIB0090=m - -# -# SEC control devices for DVB-S -# -CONFIG_DVB_DRX39XYJ=m -# CONFIG_DVB_LNBH25 is not set -# CONFIG_DVB_LNBH29 is not set -CONFIG_DVB_LNBP21=m -CONFIG_DVB_LNBP22=m -# CONFIG_DVB_ISL6405 is not set -CONFIG_DVB_ISL6421=m -CONFIG_DVB_ISL6423=m -CONFIG_DVB_A8293=m -# CONFIG_DVB_LGS8GL5 is not set -CONFIG_DVB_LGS8GXX=m -CONFIG_DVB_ATBM8830=m -# CONFIG_DVB_TDA665x is not set -CONFIG_DVB_IX2505V=m -CONFIG_DVB_M88RS2000=m -CONFIG_DVB_AF9033=m -# CONFIG_DVB_HORUS3A is not set -# CONFIG_DVB_ASCOT2E is not set -# CONFIG_DVB_HELENE is not set - -# -# Common Interface (EN50221) controller drivers -# -# CONFIG_DVB_CXD2099 is not set -CONFIG_DVB_SP2=m -# end of Customise DVB Frontends - -# -# Tools to develop new frontends -# -# CONFIG_DVB_DUMMY_FE is not set -# end of Media ancillary drivers - -# -# Graphics support -# -# CONFIG_VGA_ARB is not set -# CONFIG_IMX_IPUV3_CORE is not set -CONFIG_DRM=y -# CONFIG_DRM_DP_AUX_CHARDEV is not set -# CONFIG_DRM_DEBUG_MM is not set -# CONFIG_DRM_DEBUG_SELFTEST is not set -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_KMS_FB_HELPER=y -# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set -# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set -# CONFIG_DRM_DP_CEC is not set -CONFIG_DRM_GEM_CMA_HELPER=y -CONFIG_DRM_KMS_CMA_HELPER=y -CONFIG_DRM_GEM_SHMEM_HELPER=y -CONFIG_DRM_SCHED=y - -# -# I2C encoder or helper chips -# -# CONFIG_DRM_I2C_CH7006 is not set -# CONFIG_DRM_I2C_SIL164 is not set -# CONFIG_DRM_I2C_NXP_TDA998X is not set -# CONFIG_DRM_I2C_NXP_TDA9950 is not set -# end of I2C encoder or helper chips - -# -# ARM devices -# -# CONFIG_DRM_HDLCD is not set -CONFIG_DRM_MALI_DISPLAY=y -# CONFIG_DRM_KOMEDA is not set -# end of ARM devices - -# CONFIG_DRM_RADEON is not set -# CONFIG_DRM_AMDGPU is not set -# CONFIG_DRM_NOUVEAU is not set -# CONFIG_DRM_VGEM is not set -# CONFIG_DRM_VKMS is not set -# CONFIG_DRM_EXYNOS is not set -# CONFIG_DRM_UDL is not set -# CONFIG_DRM_AST is not set -# CONFIG_DRM_MGAG200 is not set -# CONFIG_DRM_ARMADA is not set -# CONFIG_DRM_RCAR_DW_HDMI is not set -# CONFIG_DRM_RCAR_LVDS is not set -# CONFIG_DRM_OMAP is not set -# CONFIG_DRM_TILCDC is not set -# CONFIG_DRM_QXL is not set -# CONFIG_DRM_BOCHS is not set -# CONFIG_DRM_FSL_DCU is not set -# CONFIG_DRM_STM is not set -CONFIG_DRM_PANEL=y - -# -# Display Panels -# -# CONFIG_DRM_PANEL_ARM_VERSATILE is not set -# CONFIG_DRM_PANEL_LVDS is not set -# CONFIG_DRM_PANEL_SIMPLE is not set -# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set -# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set -# CONFIG_DRM_PANEL_LG_LB035Q02 is not set -# CONFIG_DRM_PANEL_LG_LG4573 is not set -# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set -# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set -# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set -# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set -# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set -# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set -# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set -# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set -# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set -# CONFIG_DRM_PANEL_TPO_TPG110 is not set -# end of Display Panels - -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_PANEL_BRIDGE=y - -# -# Display Interface Bridges -# -# CONFIG_DRM_CDNS_DSI is not set -# CONFIG_DRM_CHRONTEL_CH7033 is not set -CONFIG_DRM_DISPLAY_CONNECTOR=y -# CONFIG_DRM_LONTIUM_LT9611 is not set -# CONFIG_DRM_LVDS_CODEC is not set -# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set -# CONFIG_DRM_NWL_MIPI_DSI is not set -# CONFIG_DRM_NXP_PTN3460 is not set -# CONFIG_DRM_PARADE_PS8622 is not set -# CONFIG_DRM_PARADE_PS8640 is not set -# CONFIG_DRM_SIL_SII8620 is not set -# CONFIG_DRM_SII902X is not set -# CONFIG_DRM_SII9234 is not set -# CONFIG_DRM_SIMPLE_BRIDGE is not set -# CONFIG_DRM_THINE_THC63LVD1024 is not set -# CONFIG_DRM_TOSHIBA_TC358762 is not set -# CONFIG_DRM_TOSHIBA_TC358764 is not set -# CONFIG_DRM_TOSHIBA_TC358767 is not set -# CONFIG_DRM_TOSHIBA_TC358768 is not set -# CONFIG_DRM_TOSHIBA_TC358775 is not set -# CONFIG_DRM_TI_TFP410 is not set -# CONFIG_DRM_TI_SN65DSI86 is not set -# CONFIG_DRM_TI_TPD12S015 is not set -# CONFIG_DRM_ANALOGIX_ANX6345 is not set -# CONFIG_DRM_ANALOGIX_ANX78XX is not set -# CONFIG_DRM_I2C_ADV7511 is not set -# CONFIG_DRM_CDNS_MHDP8546 is not set -CONFIG_DRM_DW_HDMI=y -# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set -# CONFIG_DRM_DW_HDMI_I2S_AUDIO is not set -# CONFIG_DRM_DW_HDMI_CEC is not set -CONFIG_DRM_TRANSWITCH_TXC_48352=y -# end of Display Interface Bridges - -# CONFIG_DRM_STI is not set -# CONFIG_DRM_ETNAVIV is not set -# CONFIG_DRM_ARCPGU is not set -# CONFIG_DRM_MXSFB is not set -CONFIG_DRM_MESON=y -CONFIG_DRM_MESON_DW_HDMI=y -CONFIG_DRM_MESON_MX_HDMI=y -# CONFIG_DRM_CIRRUS_QEMU is not set -# CONFIG_DRM_GM12U320 is not set -# CONFIG_TINYDRM_HX8357D is not set -# CONFIG_TINYDRM_ILI9225 is not set -# CONFIG_TINYDRM_ILI9341 is not set -# CONFIG_TINYDRM_ILI9486 is not set -# CONFIG_TINYDRM_MI0283QT is not set -# CONFIG_TINYDRM_REPAPER is not set -# CONFIG_TINYDRM_ST7586 is not set -# CONFIG_TINYDRM_ST7735R is not set -# CONFIG_DRM_PL111 is not set -# CONFIG_DRM_TVE200 is not set -CONFIG_DRM_LIMA=y -# CONFIG_DRM_PANFROST is not set -# CONFIG_DRM_MCDE is not set -# CONFIG_DRM_TIDSS is not set -# CONFIG_DRM_LEGACY is not set -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y - -# -# Frame buffer Devices -# -CONFIG_FB_CMDLINE=y -CONFIG_FB_NOTIFY=y -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_IMAGEBLIT=y -# CONFIG_FB_FOREIGN_ENDIAN is not set -CONFIG_FB_SYS_FOPS=y -CONFIG_FB_DEFERRED_IO=y -CONFIG_FB_MODE_HELPERS=y -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_CIRRUS is not set -# CONFIG_FB_PM2 is not set -# CONFIG_FB_CYBER2000 is not set -# CONFIG_FB_ASILIANT is not set -# CONFIG_FB_IMSTT is not set -# CONFIG_FB_UVESA is not set -# CONFIG_FB_EFI is not set -# CONFIG_FB_OPENCORES is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_NVIDIA is not set -# CONFIG_FB_RIVA is not set -# CONFIG_FB_I740 is not set -# CONFIG_FB_MATROX is not set -# CONFIG_FB_RADEON is not set -# CONFIG_FB_ATY128 is not set -# CONFIG_FB_ATY is not set -# CONFIG_FB_S3 is not set -# CONFIG_FB_SAVAGE is not set -# CONFIG_FB_SIS is not set -# CONFIG_FB_NEOMAGIC is not set -# CONFIG_FB_KYRO is not set -# CONFIG_FB_3DFX is not set -# CONFIG_FB_VOODOO1 is not set -# CONFIG_FB_VT8623 is not set -# CONFIG_FB_TRIDENT is not set -# CONFIG_FB_ARK is not set -# CONFIG_FB_PM3 is not set -# CONFIG_FB_CARMINE is not set -# CONFIG_FB_SMSCUFX is not set -# CONFIG_FB_UDL is not set -# CONFIG_FB_IBM_GXT4500 is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -CONFIG_FB_SIMPLE=y -# CONFIG_FB_SSD1307 is not set -# CONFIG_FB_SM712 is not set -# end of Frame buffer Devices - -# -# Backlight & LCD device support -# -# CONFIG_LCD_CLASS_DEVICE is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=m -# CONFIG_BACKLIGHT_KTD253 is not set -# CONFIG_BACKLIGHT_PWM is not set -# CONFIG_BACKLIGHT_QCOM_WLED is not set -# CONFIG_BACKLIGHT_ADP8860 is not set -# CONFIG_BACKLIGHT_ADP8870 is not set -# CONFIG_BACKLIGHT_LM3630A is not set -# CONFIG_BACKLIGHT_LM3639 is not set -# CONFIG_BACKLIGHT_LP855X is not set -# CONFIG_BACKLIGHT_GPIO is not set -# CONFIG_BACKLIGHT_LV5207LP is not set -# CONFIG_BACKLIGHT_BD6107 is not set -# CONFIG_BACKLIGHT_ARCXCNN is not set -# CONFIG_BACKLIGHT_LED is not set -# end of Backlight & LCD device support - -CONFIG_VIDEOMODE_HELPERS=y -CONFIG_HDMI=y - -# -# Console display driver support -# -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set -# end of Console display driver support - -# CONFIG_LOGO is not set -# end of Graphics support - -CONFIG_SOUND=m -CONFIG_SND=m -CONFIG_SND_TIMER=m -CONFIG_SND_PCM=m -CONFIG_SND_PCM_ELD=y -CONFIG_SND_PCM_IEC958=y -CONFIG_SND_HWDEP=m -CONFIG_SND_RAWMIDI=m -CONFIG_SND_JACK=y -CONFIG_SND_JACK_INPUT_DEV=y -# CONFIG_SND_OSSEMUL is not set -CONFIG_SND_PCM_TIMER=y -# CONFIG_SND_HRTIMER is not set -CONFIG_SND_DYNAMIC_MINORS=y -CONFIG_SND_MAX_CARDS=32 -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_PROC_FS=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -CONFIG_SND_VMASTER=y -# CONFIG_SND_SEQUENCER is not set -CONFIG_SND_DRIVERS=y -# CONFIG_SND_DUMMY is not set -# CONFIG_SND_ALOOP is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_MPU401 is not set -# CONFIG_SND_PCI is not set - -# -# HD-Audio -# -# end of HD-Audio - -CONFIG_SND_HDA_PREALLOC_SIZE=64 -CONFIG_SND_ARM=y -# CONFIG_SND_SPI is not set -CONFIG_SND_USB=y -CONFIG_SND_USB_AUDIO=m -CONFIG_SND_USB_AUDIO_USE_MEDIA_CONTROLLER=y -CONFIG_SND_USB_UA101=m -CONFIG_SND_USB_CAIAQ=m -CONFIG_SND_USB_CAIAQ_INPUT=y -CONFIG_SND_USB_6FIRE=m -CONFIG_SND_USB_HIFACE=m -CONFIG_SND_BCD2000=m -CONFIG_SND_USB_LINE6=m -CONFIG_SND_USB_POD=m -CONFIG_SND_USB_PODHD=m -CONFIG_SND_USB_TONEPORT=m -CONFIG_SND_USB_VARIAX=m -CONFIG_SND_SOC=m -# CONFIG_SND_SOC_AMD_ACP is not set -# CONFIG_SND_ATMEL_SOC is not set -# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set -# CONFIG_SND_DESIGNWARE_I2S is not set - -# -# SoC Audio for Freescale CPUs -# - -# -# Common SoC Audio options for Freescale CPUs: -# -# CONFIG_SND_SOC_FSL_ASRC is not set -# CONFIG_SND_SOC_FSL_SAI is not set -# CONFIG_SND_SOC_FSL_AUDMIX is not set -# CONFIG_SND_SOC_FSL_SSI is not set -# CONFIG_SND_SOC_FSL_SPDIF is not set -# CONFIG_SND_SOC_FSL_ESAI is not set -# CONFIG_SND_SOC_FSL_MICFIL is not set -# CONFIG_SND_SOC_IMX_AUDMUX is not set -# end of SoC Audio for Freescale CPUs - -# CONFIG_SND_I2S_HI6210_I2S is not set -# CONFIG_SND_SOC_IMG is not set -# CONFIG_SND_SOC_MTK_BTCVSD is not set - -# -# ASoC support for Amlogic platforms -# -CONFIG_SND_MESON_AIU=m -# CONFIG_SND_MESON_AXG_FRDDR is not set -# CONFIG_SND_MESON_AXG_TODDR is not set -# CONFIG_SND_MESON_AXG_TDMIN is not set -# CONFIG_SND_MESON_AXG_TDMOUT is not set -# CONFIG_SND_MESON_AXG_SOUND_CARD is not set -# CONFIG_SND_MESON_AXG_SPDIFOUT is not set -# CONFIG_SND_MESON_AXG_SPDIFIN is not set -# CONFIG_SND_MESON_AXG_PDM is not set -CONFIG_SND_MESON_CODEC_GLUE=m -# CONFIG_SND_MESON_GX_SOUND_CARD is not set -# CONFIG_SND_MESON_G12A_TOACODEC is not set -# CONFIG_SND_MESON_G12A_TOHDMITX is not set -# CONFIG_SND_SOC_MESON_T9015 is not set -# end of ASoC support for Amlogic platforms - -# CONFIG_SND_SOC_SOF_TOPLEVEL is not set - -# -# STMicroelectronics STM32 SOC audio support -# -# end of STMicroelectronics STM32 SOC audio support - -# CONFIG_SND_SOC_XILINX_I2S is not set -# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set -# CONFIG_SND_SOC_XILINX_SPDIF is not set -# CONFIG_SND_SOC_XTFPGA_I2S is not set -# CONFIG_ZX_TDM is not set -CONFIG_SND_SOC_I2C_AND_SPI=m - -# -# CODEC drivers -# -# CONFIG_SND_SOC_AC97_CODEC is not set -# CONFIG_SND_SOC_ADAU1701 is not set -# CONFIG_SND_SOC_ADAU1761_I2C is not set -# CONFIG_SND_SOC_ADAU1761_SPI is not set -# CONFIG_SND_SOC_ADAU7002 is not set -# CONFIG_SND_SOC_ADAU7118_HW is not set -# CONFIG_SND_SOC_ADAU7118_I2C is not set -# CONFIG_SND_SOC_AK4104 is not set -# CONFIG_SND_SOC_AK4118 is not set -# CONFIG_SND_SOC_AK4458 is not set -# CONFIG_SND_SOC_AK4554 is not set -# CONFIG_SND_SOC_AK4613 is not set -# CONFIG_SND_SOC_AK4642 is not set -# CONFIG_SND_SOC_AK5386 is not set -# CONFIG_SND_SOC_AK5558 is not set -# CONFIG_SND_SOC_ALC5623 is not set -# CONFIG_SND_SOC_BD28623 is not set -# CONFIG_SND_SOC_BT_SCO is not set -# CONFIG_SND_SOC_CS35L32 is not set -# CONFIG_SND_SOC_CS35L33 is not set -# CONFIG_SND_SOC_CS35L34 is not set -# CONFIG_SND_SOC_CS35L35 is not set -# CONFIG_SND_SOC_CS35L36 is not set -# CONFIG_SND_SOC_CS42L42 is not set -# CONFIG_SND_SOC_CS42L51_I2C is not set -# CONFIG_SND_SOC_CS42L52 is not set -# CONFIG_SND_SOC_CS42L56 is not set -# CONFIG_SND_SOC_CS42L73 is not set -# CONFIG_SND_SOC_CS4234 is not set -# CONFIG_SND_SOC_CS4265 is not set -# CONFIG_SND_SOC_CS4270 is not set -# CONFIG_SND_SOC_CS4271_I2C is not set -# CONFIG_SND_SOC_CS4271_SPI is not set -# CONFIG_SND_SOC_CS42XX8_I2C is not set -# CONFIG_SND_SOC_CS43130 is not set -# CONFIG_SND_SOC_CS4341 is not set -# CONFIG_SND_SOC_CS4349 is not set -# CONFIG_SND_SOC_CS53L30 is not set -# CONFIG_SND_SOC_CX2072X is not set -# CONFIG_SND_SOC_DA7213 is not set -# CONFIG_SND_SOC_DMIC is not set -CONFIG_SND_SOC_HDMI_CODEC=m -# CONFIG_SND_SOC_ES7134 is not set -# CONFIG_SND_SOC_ES7241 is not set -# CONFIG_SND_SOC_ES8316 is not set -# CONFIG_SND_SOC_ES8328_I2C is not set -# CONFIG_SND_SOC_ES8328_SPI is not set -# CONFIG_SND_SOC_GTM601 is not set -# CONFIG_SND_SOC_INNO_RK3036 is not set -# CONFIG_SND_SOC_MAX98088 is not set -# CONFIG_SND_SOC_MAX98357A is not set -# CONFIG_SND_SOC_MAX98504 is not set -# CONFIG_SND_SOC_MAX9867 is not set -# CONFIG_SND_SOC_MAX98927 is not set -# CONFIG_SND_SOC_MAX98373_I2C is not set -# CONFIG_SND_SOC_MAX98390 is not set -# CONFIG_SND_SOC_MAX9860 is not set -# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set -# CONFIG_SND_SOC_PCM1681 is not set -# CONFIG_SND_SOC_PCM1789_I2C is not set -# CONFIG_SND_SOC_PCM179X_I2C is not set -# CONFIG_SND_SOC_PCM179X_SPI is not set -# CONFIG_SND_SOC_PCM186X_I2C is not set -# CONFIG_SND_SOC_PCM186X_SPI is not set -# CONFIG_SND_SOC_PCM3060_I2C is not set -# CONFIG_SND_SOC_PCM3060_SPI is not set -# CONFIG_SND_SOC_PCM3168A_I2C is not set -# CONFIG_SND_SOC_PCM3168A_SPI is not set -# CONFIG_SND_SOC_PCM512x_I2C is not set -# CONFIG_SND_SOC_PCM512x_SPI is not set -# CONFIG_SND_SOC_RK3328 is not set -# CONFIG_SND_SOC_RT5616 is not set -# CONFIG_SND_SOC_RT5631 is not set -# CONFIG_SND_SOC_SGTL5000 is not set -# CONFIG_SND_SOC_SIMPLE_AMPLIFIER is not set -# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set -# CONFIG_SND_SOC_SPDIF is not set -# CONFIG_SND_SOC_SSM2305 is not set -# CONFIG_SND_SOC_SSM2602_SPI is not set -# CONFIG_SND_SOC_SSM2602_I2C is not set -# CONFIG_SND_SOC_SSM4567 is not set -# CONFIG_SND_SOC_STA32X is not set -# CONFIG_SND_SOC_STA350 is not set -# CONFIG_SND_SOC_STI_SAS is not set -# CONFIG_SND_SOC_TAS2552 is not set -# CONFIG_SND_SOC_TAS2562 is not set -# CONFIG_SND_SOC_TAS2764 is not set -# CONFIG_SND_SOC_TAS2770 is not set -# CONFIG_SND_SOC_TAS5086 is not set -# CONFIG_SND_SOC_TAS571X is not set -# CONFIG_SND_SOC_TAS5720 is not set -# CONFIG_SND_SOC_TAS6424 is not set -# CONFIG_SND_SOC_TDA7419 is not set -# CONFIG_SND_SOC_TFA9879 is not set -# CONFIG_SND_SOC_TLV320AIC23_I2C is not set -# CONFIG_SND_SOC_TLV320AIC23_SPI is not set -# CONFIG_SND_SOC_TLV320AIC31XX is not set -# CONFIG_SND_SOC_TLV320AIC32X4_I2C is not set -# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set -# CONFIG_SND_SOC_TLV320AIC3X is not set -# CONFIG_SND_SOC_TLV320ADCX140 is not set -# CONFIG_SND_SOC_TS3A227E is not set -# CONFIG_SND_SOC_TSCS42XX is not set -# CONFIG_SND_SOC_TSCS454 is not set -# CONFIG_SND_SOC_UDA1334 is not set -# CONFIG_SND_SOC_WM8510 is not set -# CONFIG_SND_SOC_WM8523 is not set -# CONFIG_SND_SOC_WM8524 is not set -# CONFIG_SND_SOC_WM8580 is not set -# CONFIG_SND_SOC_WM8711 is not set -# CONFIG_SND_SOC_WM8728 is not set -# CONFIG_SND_SOC_WM8731 is not set -# CONFIG_SND_SOC_WM8737 is not set -# CONFIG_SND_SOC_WM8741 is not set -# CONFIG_SND_SOC_WM8750 is not set -# CONFIG_SND_SOC_WM8753 is not set -# CONFIG_SND_SOC_WM8770 is not set -# CONFIG_SND_SOC_WM8776 is not set -# CONFIG_SND_SOC_WM8782 is not set -# CONFIG_SND_SOC_WM8804_I2C is not set -# CONFIG_SND_SOC_WM8804_SPI is not set -# CONFIG_SND_SOC_WM8903 is not set -# CONFIG_SND_SOC_WM8904 is not set -# CONFIG_SND_SOC_WM8960 is not set -# CONFIG_SND_SOC_WM8962 is not set -# CONFIG_SND_SOC_WM8974 is not set -# CONFIG_SND_SOC_WM8978 is not set -# CONFIG_SND_SOC_WM8985 is not set -# CONFIG_SND_SOC_ZL38060 is not set -# CONFIG_SND_SOC_ZX_AUD96P22 is not set -# CONFIG_SND_SOC_MAX9759 is not set -# CONFIG_SND_SOC_MT6351 is not set -# CONFIG_SND_SOC_MT6358 is not set -# CONFIG_SND_SOC_MT6660 is not set -# CONFIG_SND_SOC_NAU8540 is not set -# CONFIG_SND_SOC_NAU8810 is not set -# CONFIG_SND_SOC_NAU8822 is not set -# CONFIG_SND_SOC_NAU8824 is not set -# CONFIG_SND_SOC_TPA6130A2 is not set -# end of CODEC drivers - -CONFIG_SND_SIMPLE_CARD_UTILS=m -CONFIG_SND_SIMPLE_CARD=m -CONFIG_SND_AUDIO_GRAPH_CARD=m - -# -# HID support -# -CONFIG_HID=y -# CONFIG_HID_BATTERY_STRENGTH is not set -# CONFIG_HIDRAW is not set -# CONFIG_UHID is not set -CONFIG_HID_GENERIC=y - -# -# Special HID drivers -# -# CONFIG_HID_A4TECH is not set -# CONFIG_HID_ACCUTOUCH is not set -# CONFIG_HID_ACRUX is not set -# CONFIG_HID_APPLE is not set -# CONFIG_HID_APPLEIR is not set -# CONFIG_HID_ASUS is not set -# CONFIG_HID_AUREAL is not set -# CONFIG_HID_BELKIN is not set -# CONFIG_HID_BETOP_FF is not set -# CONFIG_HID_BIGBEN_FF is not set -# CONFIG_HID_CHERRY is not set -# CONFIG_HID_CHICONY is not set -# CONFIG_HID_CORSAIR is not set -# CONFIG_HID_COUGAR is not set -# CONFIG_HID_MACALLY is not set -# CONFIG_HID_PRODIKEYS is not set -# CONFIG_HID_CMEDIA is not set -# CONFIG_HID_CREATIVE_SB0540 is not set -# CONFIG_HID_CYPRESS is not set -# CONFIG_HID_DRAGONRISE is not set -# CONFIG_HID_EMS_FF is not set -# CONFIG_HID_ELAN is not set -# CONFIG_HID_ELECOM is not set -# CONFIG_HID_ELO is not set -# CONFIG_HID_EZKEY is not set -# CONFIG_HID_GEMBIRD is not set -# CONFIG_HID_GFRM is not set -# CONFIG_HID_GLORIOUS is not set -# CONFIG_HID_HOLTEK is not set -# CONFIG_HID_VIVALDI is not set -# CONFIG_HID_GT683R is not set -# CONFIG_HID_KEYTOUCH is not set -# CONFIG_HID_KYE is not set -# CONFIG_HID_UCLOGIC is not set -# CONFIG_HID_WALTOP is not set -# CONFIG_HID_VIEWSONIC is not set -# CONFIG_HID_GYRATION is not set -# CONFIG_HID_ICADE is not set -# CONFIG_HID_ITE is not set -# CONFIG_HID_JABRA is not set -# CONFIG_HID_TWINHAN is not set -# CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_LCPOWER is not set -# CONFIG_HID_LED is not set -# CONFIG_HID_LENOVO is not set -# CONFIG_HID_LOGITECH is not set -# CONFIG_HID_MAGICMOUSE is not set -# CONFIG_HID_MALTRON is not set -# CONFIG_HID_MAYFLASH is not set -# CONFIG_HID_REDRAGON is not set -# CONFIG_HID_MICROSOFT is not set -# CONFIG_HID_MONTEREY is not set -# CONFIG_HID_MULTITOUCH is not set -# CONFIG_HID_NTI is not set -# CONFIG_HID_NTRIG is not set -# CONFIG_HID_ORTEK is not set -# CONFIG_HID_PANTHERLORD is not set -# CONFIG_HID_PENMOUNT is not set -# CONFIG_HID_PETALYNX is not set -# CONFIG_HID_PICOLCD is not set -# CONFIG_HID_PLANTRONICS is not set -# CONFIG_HID_PRIMAX is not set -# CONFIG_HID_RETRODE is not set -# CONFIG_HID_ROCCAT is not set -# CONFIG_HID_SAITEK is not set -# CONFIG_HID_SAMSUNG is not set -# CONFIG_HID_SONY is not set -# CONFIG_HID_SPEEDLINK is not set -# CONFIG_HID_STEAM is not set -# CONFIG_HID_STEELSERIES is not set -# CONFIG_HID_SUNPLUS is not set -# CONFIG_HID_RMI is not set -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -# CONFIG_HID_TIVO is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_HID_THINGM is not set -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_UDRAW_PS3 is not set -# CONFIG_HID_U2FZERO is not set -# CONFIG_HID_WACOM is not set -# CONFIG_HID_WIIMOTE is not set -# CONFIG_HID_XINMO is not set -# CONFIG_HID_ZEROPLUS is not set -# CONFIG_HID_ZYDACRON is not set -# CONFIG_HID_SENSOR_HUB is not set -# CONFIG_HID_ALPS is not set -# CONFIG_HID_MCP2221 is not set -# end of Special HID drivers - -# -# USB HID support -# -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -# CONFIG_USB_HIDDEV is not set -# end of USB HID support - -# -# I2C HID support -# -# CONFIG_I2C_HID is not set -# end of I2C HID support -# end of HID support - -CONFIG_USB_OHCI_LITTLE_ENDIAN=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_COMMON=y -CONFIG_USB_LED_TRIG=y -CONFIG_USB_ULPI_BUS=y -CONFIG_USB_CONN_GPIO=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB=y -# CONFIG_USB_PCI is not set -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set - -# -# Miscellaneous USB options -# -CONFIG_USB_DEFAULT_PERSIST=y -# CONFIG_USB_FEW_INIT_RETRIES is not set -# CONFIG_USB_DYNAMIC_MINORS is not set -CONFIG_USB_OTG=y -# CONFIG_USB_OTG_PRODUCTLIST is not set -# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set -# CONFIG_USB_OTG_FSM is not set -CONFIG_USB_LEDS_TRIGGER_USBPORT=y -CONFIG_USB_AUTOSUSPEND_DELAY=2 -# CONFIG_USB_MON is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -# CONFIG_USB_XHCI_HCD is not set -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y -# CONFIG_USB_EHCI_FSL is not set -CONFIG_USB_EHCI_HCD_PLATFORM=y -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_FOTG210_HCD is not set -# CONFIG_USB_MAX3421_HCD is not set -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -# CONFIG_USB_U132_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HCD_TEST_MODE is not set - -# -# USB Device Class drivers -# -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m -CONFIG_USB_WDM=m -CONFIG_USB_TMC=m - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -CONFIG_USB_STORAGE_REALTEK=m -CONFIG_REALTEK_AUTOPM=y -CONFIG_USB_STORAGE_DATAFAB=m -CONFIG_USB_STORAGE_FREECOM=m -CONFIG_USB_STORAGE_ISD200=m -CONFIG_USB_STORAGE_USBAT=m -CONFIG_USB_STORAGE_SDDR09=m -CONFIG_USB_STORAGE_SDDR55=m -CONFIG_USB_STORAGE_JUMPSHOT=m -CONFIG_USB_STORAGE_ALAUDA=m -CONFIG_USB_STORAGE_ONETOUCH=m -CONFIG_USB_STORAGE_KARMA=m -CONFIG_USB_STORAGE_CYPRESS_ATACB=m -CONFIG_USB_STORAGE_ENE_UB6250=m -CONFIG_USB_UAS=m - -# -# USB Imaging devices -# -CONFIG_USB_MDC800=m -CONFIG_USB_MICROTEK=m -CONFIG_USBIP_CORE=m -CONFIG_USBIP_VHCI_HCD=m -CONFIG_USBIP_VHCI_HC_PORTS=8 -CONFIG_USBIP_VHCI_NR_HCS=1 -CONFIG_USBIP_HOST=m -CONFIG_USBIP_VUDC=m -# CONFIG_USBIP_DEBUG is not set -# CONFIG_USB_CDNS3 is not set -# CONFIG_USB_MUSB_HDRC is not set -# CONFIG_USB_DWC3 is not set -CONFIG_USB_DWC2=y -# CONFIG_USB_DWC2_HOST is not set - -# -# Gadget/Dual-role mode requires USB Gadget support to be enabled -# -# CONFIG_USB_DWC2_PERIPHERAL is not set -CONFIG_USB_DWC2_DUAL_ROLE=y -# CONFIG_USB_DWC2_DEBUG is not set -# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set -# CONFIG_USB_CHIPIDEA is not set -# CONFIG_USB_ISP1760 is not set - -# -# USB port drivers -# -CONFIG_USB_SERIAL=m -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_SIMPLE=m -CONFIG_USB_SERIAL_AIRCABLE=m -CONFIG_USB_SERIAL_ARK3116=m -CONFIG_USB_SERIAL_BELKIN=m -CONFIG_USB_SERIAL_CH341=m -CONFIG_USB_SERIAL_WHITEHEAT=m -CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -CONFIG_USB_SERIAL_CP210X=m -CONFIG_USB_SERIAL_CYPRESS_M8=m -CONFIG_USB_SERIAL_EMPEG=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_VISOR=m -CONFIG_USB_SERIAL_IPAQ=m -CONFIG_USB_SERIAL_IR=m -CONFIG_USB_SERIAL_EDGEPORT=m -CONFIG_USB_SERIAL_EDGEPORT_TI=m -CONFIG_USB_SERIAL_F81232=m -CONFIG_USB_SERIAL_F8153X=m -CONFIG_USB_SERIAL_GARMIN=m -CONFIG_USB_SERIAL_IPW=m -CONFIG_USB_SERIAL_IUU=m -CONFIG_USB_SERIAL_KEYSPAN_PDA=m -CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_KLSI=m -CONFIG_USB_SERIAL_KOBIL_SCT=m -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_SERIAL_METRO=m -CONFIG_USB_SERIAL_MOS7720=m -CONFIG_USB_SERIAL_MOS7840=m -CONFIG_USB_SERIAL_MXUPORT=m -CONFIG_USB_SERIAL_NAVMAN=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_SERIAL_OTI6858=m -CONFIG_USB_SERIAL_QCAUX=m -CONFIG_USB_SERIAL_QUALCOMM=m -CONFIG_USB_SERIAL_SPCP8X5=m -CONFIG_USB_SERIAL_SAFE=m -CONFIG_USB_SERIAL_SAFE_PADDED=y -CONFIG_USB_SERIAL_SIERRAWIRELESS=m -CONFIG_USB_SERIAL_SYMBOL=m -CONFIG_USB_SERIAL_TI=m -CONFIG_USB_SERIAL_CYBERJACK=m -# CONFIG_USB_SERIAL_XIRCOM is not set -CONFIG_USB_SERIAL_WWAN=m -CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_SERIAL_OMNINET=m -CONFIG_USB_SERIAL_OPTICON=m -CONFIG_USB_SERIAL_XSENS_MT=m -CONFIG_USB_SERIAL_WISHBONE=m -CONFIG_USB_SERIAL_SSU100=m -CONFIG_USB_SERIAL_QT2=m -CONFIG_USB_SERIAL_UPD78F0730=m -CONFIG_USB_SERIAL_DEBUG=m - -# -# USB Miscellaneous drivers -# -CONFIG_USB_EMI62=m -CONFIG_USB_EMI26=m -CONFIG_USB_ADUTUX=m -CONFIG_USB_SEVSEG=m -CONFIG_USB_LEGOTOWER=m -CONFIG_USB_LCD=m -CONFIG_USB_CYPRESS_CY7C63=m -CONFIG_USB_CYTHERM=m -CONFIG_USB_IDMOUSE=m -CONFIG_USB_FTDI_ELAN=m -CONFIG_USB_APPLEDISPLAY=m -CONFIG_APPLE_MFI_FASTCHARGE=m -CONFIG_USB_SISUSBVGA=m -CONFIG_USB_LD=m -CONFIG_USB_TRANCEVIBRATOR=m -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set -# CONFIG_USB_EHSET_TEST_FIXTURE is not set -CONFIG_USB_ISIGHTFW=m -CONFIG_USB_YUREX=m -CONFIG_USB_EZUSB_FX2=m -# CONFIG_USB_HUB_USB251XB is not set -# CONFIG_USB_HSIC_USB3503 is not set -# CONFIG_USB_HSIC_USB4604 is not set -# CONFIG_USB_LINK_LAYER_TEST is not set -# CONFIG_USB_CHAOSKEY is not set -# CONFIG_USB_ATM is not set - -# -# USB Physical Layer drivers -# -CONFIG_USB_PHY=y -# CONFIG_NOP_USB_XCEIV is not set -CONFIG_USB_GPIO_VBUS=y -# CONFIG_USB_ISP1301 is not set -CONFIG_USB_ULPI=y -CONFIG_USB_ULPI_VIEWPORT=y -# end of USB Physical Layer drivers - -CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_DEBUG_FS is not set -CONFIG_USB_GADGET_VBUS_DRAW=2 -CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 -CONFIG_U_SERIAL_CONSOLE=y - -# -# USB Peripheral Controller -# -# CONFIG_USB_FUSB300 is not set -# CONFIG_USB_FOTG210_UDC is not set -# CONFIG_USB_GR_UDC is not set -# CONFIG_USB_R8A66597 is not set -# CONFIG_USB_PXA27X is not set -# CONFIG_USB_MV_UDC is not set -# CONFIG_USB_MV_U3D is not set -# CONFIG_USB_SNP_UDC_PLAT is not set -# CONFIG_USB_M66592 is not set -# CONFIG_USB_BDC_UDC is not set -# CONFIG_USB_NET2272 is not set -# CONFIG_USB_GADGET_XILINX is not set -# CONFIG_USB_MAX3420_UDC is not set -# CONFIG_USB_DUMMY_HCD is not set -# end of USB Peripheral Controller - -CONFIG_USB_LIBCOMPOSITE=m -CONFIG_USB_F_ACM=m -CONFIG_USB_F_SS_LB=m -CONFIG_USB_U_SERIAL=m -CONFIG_USB_U_ETHER=m -CONFIG_USB_U_AUDIO=m -CONFIG_USB_F_SERIAL=m -CONFIG_USB_F_OBEX=m -CONFIG_USB_F_NCM=m -CONFIG_USB_F_ECM=m -CONFIG_USB_F_EEM=m -CONFIG_USB_F_SUBSET=m -CONFIG_USB_F_RNDIS=m -CONFIG_USB_F_MASS_STORAGE=m -CONFIG_USB_F_FS=m -CONFIG_USB_F_UAC1=m -CONFIG_USB_F_UAC1_LEGACY=m -CONFIG_USB_F_UAC2=m -CONFIG_USB_F_UVC=m -CONFIG_USB_F_MIDI=m -CONFIG_USB_F_HID=m -CONFIG_USB_F_PRINTER=m -CONFIG_USB_CONFIGFS=m -CONFIG_USB_CONFIGFS_SERIAL=y -CONFIG_USB_CONFIGFS_ACM=y -CONFIG_USB_CONFIGFS_OBEX=y -CONFIG_USB_CONFIGFS_NCM=y -CONFIG_USB_CONFIGFS_ECM=y -CONFIG_USB_CONFIGFS_ECM_SUBSET=y -CONFIG_USB_CONFIGFS_RNDIS=y -CONFIG_USB_CONFIGFS_EEM=y -# CONFIG_USB_CONFIGFS_PHONET is not set -CONFIG_USB_CONFIGFS_MASS_STORAGE=y -CONFIG_USB_CONFIGFS_F_LB_SS=y -CONFIG_USB_CONFIGFS_F_FS=y -CONFIG_USB_CONFIGFS_F_UAC1=y -CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y -CONFIG_USB_CONFIGFS_F_UAC2=y -CONFIG_USB_CONFIGFS_F_MIDI=y -CONFIG_USB_CONFIGFS_F_HID=y -CONFIG_USB_CONFIGFS_F_UVC=y -CONFIG_USB_CONFIGFS_F_PRINTER=y - -# -# USB Gadget precomposed configurations -# -CONFIG_USB_ZERO=m -# CONFIG_USB_ZERO_HNPTEST is not set -CONFIG_USB_AUDIO=m -# CONFIG_GADGET_UAC1 is not set -CONFIG_USB_ETH=m -CONFIG_USB_ETH_RNDIS=y -CONFIG_USB_ETH_EEM=y -CONFIG_USB_G_NCM=m -CONFIG_USB_GADGETFS=m -CONFIG_USB_FUNCTIONFS=m -CONFIG_USB_FUNCTIONFS_ETH=y -CONFIG_USB_FUNCTIONFS_RNDIS=y -CONFIG_USB_FUNCTIONFS_GENERIC=y -CONFIG_USB_MASS_STORAGE=m -CONFIG_USB_G_SERIAL=m -CONFIG_USB_MIDI_GADGET=m -CONFIG_USB_G_PRINTER=m -CONFIG_USB_CDC_COMPOSITE=m -# CONFIG_USB_G_NOKIA is not set -CONFIG_USB_G_ACM_MS=m -CONFIG_USB_G_MULTI=m -CONFIG_USB_G_MULTI_RNDIS=y -CONFIG_USB_G_MULTI_CDC=y -CONFIG_USB_G_HID=m -# CONFIG_USB_G_DBGP is not set -CONFIG_USB_G_WEBCAM=m -CONFIG_USB_RAW_GADGET=m -# end of USB Gadget precomposed configurations - -# CONFIG_TYPEC is not set -CONFIG_USB_ROLE_SWITCH=y -CONFIG_MMC=y -CONFIG_PWRSEQ_EMMC=y -# CONFIG_PWRSEQ_SD8787 is not set -CONFIG_PWRSEQ_SIMPLE=y -CONFIG_MMC_BLOCK=y -CONFIG_MMC_BLOCK_MINORS=16 -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_DEBUG is not set -# CONFIG_MMC_SDHCI is not set -# CONFIG_MMC_MESON_GX is not set -CONFIG_MMC_MESON_MX_SDHC=y -CONFIG_MMC_MESON_MX_SDIO=y -# CONFIG_MMC_TIFM_SD is not set -# CONFIG_MMC_SPI is not set -# CONFIG_MMC_CB710 is not set -# CONFIG_MMC_VIA_SDMMC is not set -# CONFIG_MMC_DW is not set -CONFIG_MMC_VUB300=m -CONFIG_MMC_USHC=m -# CONFIG_MMC_USDHI6ROL0 is not set -CONFIG_MMC_REALTEK_USB=m -CONFIG_MMC_CQHCI=y -CONFIG_MMC_HSQ=m -# CONFIG_MMC_TOSHIBA_PCI is not set -# CONFIG_MMC_MTK is not set -# CONFIG_MEMSTICK is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -# CONFIG_LEDS_CLASS_FLASH is not set -# CONFIG_LEDS_CLASS_MULTICOLOR is not set -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set - -# -# LED drivers -# -# CONFIG_LEDS_AN30259A is not set -# CONFIG_LEDS_AW2013 is not set -# CONFIG_LEDS_BCM6328 is not set -# CONFIG_LEDS_BCM6358 is not set -# CONFIG_LEDS_CR0014114 is not set -# CONFIG_LEDS_EL15203000 is not set -# CONFIG_LEDS_LM3530 is not set -# CONFIG_LEDS_LM3532 is not set -# CONFIG_LEDS_LM3642 is not set -# CONFIG_LEDS_LM3692X is not set -# CONFIG_LEDS_PCA9532 is not set -CONFIG_LEDS_GPIO=y -# CONFIG_LEDS_LP3944 is not set -# CONFIG_LEDS_LP3952 is not set -# CONFIG_LEDS_LP50XX is not set -# CONFIG_LEDS_LP55XX_COMMON is not set -# CONFIG_LEDS_LP8860 is not set -# CONFIG_LEDS_PCA955X is not set -# CONFIG_LEDS_PCA963X is not set -# CONFIG_LEDS_DAC124S085 is not set -CONFIG_LEDS_PWM=y -# CONFIG_LEDS_REGULATOR is not set -# CONFIG_LEDS_BD2802 is not set -# CONFIG_LEDS_LT3593 is not set -# CONFIG_LEDS_TCA6507 is not set -# CONFIG_LEDS_TLC591XX is not set -# CONFIG_LEDS_LM355x is not set -# CONFIG_LEDS_IS31FL319X is not set -# CONFIG_LEDS_IS31FL32XX is not set - -# -# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) -# -# CONFIG_LEDS_BLINKM is not set -# CONFIG_LEDS_SYSCON is not set -# CONFIG_LEDS_MLXREG is not set -# CONFIG_LEDS_USER is not set -# CONFIG_LEDS_SPI_BYTE is not set -# CONFIG_LEDS_TI_LMU_COMMON is not set - -# -# LED Triggers -# -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_ONESHOT=y -CONFIG_LEDS_TRIGGER_DISK=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_BACKLIGHT=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_LEDS_TRIGGER_ACTIVITY=y -CONFIG_LEDS_TRIGGER_GPIO=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y - -# -# iptables trigger is under Netfilter config (LED target) -# -CONFIG_LEDS_TRIGGER_TRANSIENT=y -CONFIG_LEDS_TRIGGER_CAMERA=y -CONFIG_LEDS_TRIGGER_PANIC=y -CONFIG_LEDS_TRIGGER_NETDEV=y -CONFIG_LEDS_TRIGGER_PATTERN=y -CONFIG_LEDS_TRIGGER_AUDIO=y -# CONFIG_ACCESSIBILITY is not set -# CONFIG_INFINIBAND is not set -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -CONFIG_EDAC=y -CONFIG_EDAC_LEGACY_SYSFS=y -# CONFIG_EDAC_DEBUG is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -CONFIG_RTC_SYSTOHC=y -CONFIG_RTC_SYSTOHC_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set -CONFIG_RTC_NVMEM=y - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -# CONFIG_RTC_DRV_ABB5ZES3 is not set -# CONFIG_RTC_DRV_ABEOZ9 is not set -# CONFIG_RTC_DRV_ABX80X is not set -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_HYM8563 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_ISL12022 is not set -# CONFIG_RTC_DRV_ISL12026 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8523 is not set -# CONFIG_RTC_DRV_PCF85063 is not set -# CONFIG_RTC_DRV_PCF85363 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_BQ32K is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8010 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set -# CONFIG_RTC_DRV_EM3027 is not set -# CONFIG_RTC_DRV_RV3028 is not set -# CONFIG_RTC_DRV_RV3032 is not set -# CONFIG_RTC_DRV_RV8803 is not set -# CONFIG_RTC_DRV_SD3078 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T93 is not set -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1302 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1343 is not set -# CONFIG_RTC_DRV_DS1347 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6916 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RX4581 is not set -# CONFIG_RTC_DRV_RX6110 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_PCF2123 is not set -# CONFIG_RTC_DRV_MCP795 is not set -CONFIG_RTC_I2C_AND_SPI=y - -# -# SPI and I2C RTC drivers -# -# CONFIG_RTC_DRV_DS3232 is not set -# CONFIG_RTC_DRV_PCF2127 is not set -# CONFIG_RTC_DRV_RV3029C2 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_CMOS is not set -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1685_FAMILY is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_DS2404 is not set -CONFIG_RTC_DRV_EFI=m -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_RP5C01 is not set -# CONFIG_RTC_DRV_V3020 is not set -# CONFIG_RTC_DRV_ZYNQMP is not set - -# -# on-CPU RTC drivers -# -CONFIG_RTC_DRV_MESON=y -CONFIG_RTC_DRV_MESON_VRTC=y -# CONFIG_RTC_DRV_CADENCE is not set -# CONFIG_RTC_DRV_FTRTC010 is not set -# CONFIG_RTC_DRV_R7301 is not set - -# -# HID Sensor RTC drivers -# -CONFIG_DMADEVICES=y -# CONFIG_DMADEVICES_DEBUG is not set - -# -# DMA Devices -# -CONFIG_DMA_ENGINE=y -CONFIG_DMA_OF=y -# CONFIG_ALTERA_MSGDMA is not set -# CONFIG_DW_AXI_DMAC is not set -# CONFIG_FSL_EDMA is not set -# CONFIG_FSL_QDMA is not set -# CONFIG_INTEL_IDMA64 is not set -# CONFIG_NBPFAXI_DMA is not set -# CONFIG_PLX_DMA is not set -# CONFIG_XILINX_ZYNQMP_DPDMA is not set -# CONFIG_QCOM_HIDMA_MGMT is not set -# CONFIG_QCOM_HIDMA is not set -# CONFIG_DW_DMAC is not set -# CONFIG_DW_DMAC_PCI is not set -# CONFIG_DW_EDMA is not set -# CONFIG_DW_EDMA_PCIE is not set -# CONFIG_SF_PDMA is not set - -# -# DMA Clients -# -# CONFIG_ASYNC_TX_DMA is not set -# CONFIG_DMATEST is not set - -# -# DMABUF options -# -CONFIG_SYNC_FILE=y -# CONFIG_SW_SYNC is not set -# CONFIG_UDMABUF is not set -# CONFIG_DMABUF_MOVE_NOTIFY is not set -# CONFIG_DMABUF_SELFTESTS is not set -# CONFIG_DMABUF_HEAPS is not set -# end of DMABUF options - -# CONFIG_AUXDISPLAY is not set -# CONFIG_UIO is not set -# CONFIG_VFIO is not set -# CONFIG_VIRT_DRIVERS is not set -CONFIG_VIRTIO=y -# CONFIG_VIRTIO_MENU is not set -# CONFIG_VDPA is not set -CONFIG_VHOST_IOTLB=m -CONFIG_VHOST=m -CONFIG_VHOST_MENU=y -CONFIG_VHOST_NET=m -CONFIG_VHOST_VSOCK=m -# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set - -# -# Microsoft Hyper-V guest support -# -# end of Microsoft Hyper-V guest support - -# CONFIG_GREYBUS is not set -# CONFIG_STAGING is not set -# CONFIG_GOLDFISH is not set -# CONFIG_CHROME_PLATFORMS is not set -# CONFIG_MELLANOX_PLATFORM is not set -CONFIG_HAVE_CLK=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_COMMON_CLK=y -# CONFIG_COMMON_CLK_MAX9485 is not set -# CONFIG_COMMON_CLK_SCMI is not set -# CONFIG_COMMON_CLK_SI5341 is not set -# CONFIG_COMMON_CLK_SI5351 is not set -# CONFIG_COMMON_CLK_SI514 is not set -# CONFIG_COMMON_CLK_SI544 is not set -# CONFIG_COMMON_CLK_SI570 is not set -# CONFIG_COMMON_CLK_CDCE706 is not set -# CONFIG_COMMON_CLK_CDCE925 is not set -# CONFIG_COMMON_CLK_CS2000_CP is not set -# CONFIG_CLK_QORIQ is not set -# CONFIG_COMMON_CLK_PWM is not set -# CONFIG_COMMON_CLK_VC5 is not set -# CONFIG_COMMON_CLK_FIXED_MMIO is not set - -# -# Clock support for Amlogic platforms -# -CONFIG_COMMON_CLK_MESON_REGMAP=y -CONFIG_COMMON_CLK_MESON_MPLL=y -CONFIG_COMMON_CLK_MESON_PLL=y -CONFIG_COMMON_CLK_MESON8B=y -# end of Clock support for Amlogic platforms - -CONFIG_HWSPINLOCK=y - -# -# Clock Source drivers -# -CONFIG_TIMER_OF=y -CONFIG_TIMER_PROBE=y -CONFIG_CLKSRC_MMIO=y -CONFIG_MESON6_TIMER=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -CONFIG_ARM_GLOBAL_TIMER=y -CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y -# CONFIG_MICROCHIP_PIT64B is not set -# end of Clock Source drivers - -CONFIG_MAILBOX=y -# CONFIG_PLATFORM_MHU is not set -# CONFIG_ALTERA_MBOX is not set -# CONFIG_MAILBOX_TEST is not set -CONFIG_IOMMU_SUPPORT=y - -# -# Generic IOMMU Pagetable Support -# -CONFIG_IOMMU_IO_PGTABLE=y -CONFIG_IOMMU_IO_PGTABLE_LPAE=y -# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set -# end of Generic IOMMU Pagetable Support - -CONFIG_IOMMU_DEBUGFS=y -# CONFIG_ARM_SMMU is not set - -# -# Remoteproc drivers -# -CONFIG_REMOTEPROC=y -CONFIG_REMOTEPROC_CDEV=y -# end of Remoteproc drivers - -# -# Rpmsg drivers -# -CONFIG_RPMSG=m -# CONFIG_RPMSG_CHAR is not set -# CONFIG_RPMSG_QCOM_GLINK_RPM is not set -CONFIG_RPMSG_VIRTIO=m -# end of Rpmsg drivers - -# CONFIG_SOUNDWIRE is not set - -# -# SOC (System On Chip) specific Drivers -# - -# -# Amlogic SoC drivers -# -CONFIG_MESON_CANVAS=y -CONFIG_MESON_CLK_MEASURE=y -CONFIG_MESON_GX_SOCINFO=y -# CONFIG_MESON_GX_PM_DOMAINS is not set -CONFIG_MESON_EE_PM_DOMAINS=y -CONFIG_MESON_MX_SOCINFO=y -# end of Amlogic SoC drivers - -# -# Aspeed SoC drivers -# -# end of Aspeed SoC drivers - -# -# Broadcom SoC drivers -# -# CONFIG_SOC_BRCMSTB is not set -# end of Broadcom SoC drivers - -# -# NXP/Freescale QorIQ SoC drivers -# -# CONFIG_QUICC_ENGINE is not set -# CONFIG_FSL_RCPM is not set -# end of NXP/Freescale QorIQ SoC drivers - -# -# i.MX SoC drivers -# -# end of i.MX SoC drivers - -# -# Qualcomm SoC drivers -# -# end of Qualcomm SoC drivers - -# CONFIG_SOC_TI is not set - -# -# Xilinx SoC drivers -# -# CONFIG_XILINX_VCU is not set -# end of Xilinx SoC drivers -# end of SOC (System On Chip) specific Drivers - -CONFIG_PM_DEVFREQ=y - -# -# DEVFREQ Governors -# -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -CONFIG_DEVFREQ_GOV_PERFORMANCE=m -CONFIG_DEVFREQ_GOV_POWERSAVE=m -CONFIG_DEVFREQ_GOV_USERSPACE=m -CONFIG_DEVFREQ_GOV_PASSIVE=m - -# -# DEVFREQ Drivers -# -CONFIG_PM_DEVFREQ_EVENT=y -CONFIG_EXTCON=y - -# -# Extcon Device Drivers -# -# CONFIG_EXTCON_ADC_JACK is not set -# CONFIG_EXTCON_FSA9480 is not set -# CONFIG_EXTCON_GPIO is not set -# CONFIG_EXTCON_MAX3355 is not set -# CONFIG_EXTCON_PTN5150 is not set -# CONFIG_EXTCON_RT8973A is not set -# CONFIG_EXTCON_SM5502 is not set -CONFIG_EXTCON_USB_GPIO=y -CONFIG_MEMORY=y -CONFIG_IIO=y -CONFIG_IIO_BUFFER=y -CONFIG_IIO_BUFFER_CB=m -CONFIG_IIO_BUFFER_DMA=m -CONFIG_IIO_BUFFER_DMAENGINE=m -CONFIG_IIO_BUFFER_HW_CONSUMER=m -CONFIG_IIO_KFIFO_BUF=y -CONFIG_IIO_TRIGGERED_BUFFER=y -CONFIG_IIO_CONFIGFS=y -CONFIG_IIO_TRIGGER=y -CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 -# CONFIG_IIO_SW_DEVICE is not set -CONFIG_IIO_SW_TRIGGER=y -CONFIG_IIO_TRIGGERED_EVENT=m - -# -# Accelerometers -# -# CONFIG_ADIS16201 is not set -# CONFIG_ADIS16209 is not set -# CONFIG_ADXL345_I2C is not set -# CONFIG_ADXL345_SPI is not set -# CONFIG_ADXL372_SPI is not set -# CONFIG_ADXL372_I2C is not set -# CONFIG_BMA180 is not set -# CONFIG_BMA220 is not set -# CONFIG_BMA400 is not set -# CONFIG_BMC150_ACCEL is not set -# CONFIG_DA280 is not set -# CONFIG_DA311 is not set -# CONFIG_DMARD06 is not set -# CONFIG_DMARD09 is not set -# CONFIG_DMARD10 is not set -# CONFIG_IIO_ST_ACCEL_3AXIS is not set -# CONFIG_KXSD9 is not set -# CONFIG_KXCJK1013 is not set -# CONFIG_MC3230 is not set -# CONFIG_MMA7455_I2C is not set -# CONFIG_MMA7455_SPI is not set -# CONFIG_MMA7660 is not set -# CONFIG_MMA8452 is not set -# CONFIG_MMA9551 is not set -# CONFIG_MMA9553 is not set -# CONFIG_MXC4005 is not set -# CONFIG_MXC6255 is not set -# CONFIG_SCA3000 is not set -# CONFIG_STK8312 is not set -# CONFIG_STK8BA50 is not set -# end of Accelerometers - -# -# Analog to digital converters -# -# CONFIG_AD7091R5 is not set -# CONFIG_AD7124 is not set -# CONFIG_AD7192 is not set -# CONFIG_AD7266 is not set -# CONFIG_AD7291 is not set -# CONFIG_AD7292 is not set -# CONFIG_AD7298 is not set -# CONFIG_AD7476 is not set -# CONFIG_AD7606_IFACE_PARALLEL is not set -# CONFIG_AD7606_IFACE_SPI is not set -# CONFIG_AD7766 is not set -# CONFIG_AD7768_1 is not set -# CONFIG_AD7780 is not set -# CONFIG_AD7791 is not set -# CONFIG_AD7793 is not set -# CONFIG_AD7887 is not set -# CONFIG_AD7923 is not set -# CONFIG_AD7949 is not set -# CONFIG_AD799X is not set -# CONFIG_ADI_AXI_ADC is not set -# CONFIG_CC10001_ADC is not set -# CONFIG_ENVELOPE_DETECTOR is not set -# CONFIG_HI8435 is not set -# CONFIG_HX711 is not set -# CONFIG_INA2XX_ADC is not set -# CONFIG_LTC2471 is not set -# CONFIG_LTC2485 is not set -# CONFIG_LTC2496 is not set -# CONFIG_LTC2497 is not set -# CONFIG_MAX1027 is not set -# CONFIG_MAX11100 is not set -# CONFIG_MAX1118 is not set -# CONFIG_MAX1241 is not set -# CONFIG_MAX1363 is not set -# CONFIG_MAX9611 is not set -# CONFIG_MCP320X is not set -# CONFIG_MCP3422 is not set -# CONFIG_MCP3911 is not set -CONFIG_MESON_SARADC=m -# CONFIG_NAU7802 is not set -# CONFIG_SD_ADC_MODULATOR is not set -# CONFIG_TI_ADC081C is not set -# CONFIG_TI_ADC0832 is not set -# CONFIG_TI_ADC084S021 is not set -# CONFIG_TI_ADC12138 is not set -# CONFIG_TI_ADC108S102 is not set -# CONFIG_TI_ADC128S052 is not set -# CONFIG_TI_ADC161S626 is not set -# CONFIG_TI_ADS1015 is not set -# CONFIG_TI_ADS7950 is not set -# CONFIG_TI_ADS8344 is not set -# CONFIG_TI_ADS8688 is not set -# CONFIG_TI_ADS124S08 is not set -# CONFIG_TI_TLC4541 is not set -# CONFIG_VF610_ADC is not set -# CONFIG_XILINX_XADC is not set -# end of Analog to digital converters - -# -# Analog Front Ends -# -# CONFIG_IIO_RESCALE is not set -# end of Analog Front Ends - -# -# Amplifiers -# -# CONFIG_AD8366 is not set -# CONFIG_HMC425 is not set -# end of Amplifiers - -# -# Chemical Sensors -# -# CONFIG_ATLAS_PH_SENSOR is not set -# CONFIG_ATLAS_EZO_SENSOR is not set -# CONFIG_BME680 is not set -# CONFIG_CCS811 is not set -# CONFIG_IAQCORE is not set -# CONFIG_PMS7003 is not set -# CONFIG_SCD30_CORE is not set -# CONFIG_SENSIRION_SGP30 is not set -# CONFIG_SPS30 is not set -# CONFIG_VZ89X is not set -# end of Chemical Sensors - -# -# Hid Sensor IIO Common -# -# end of Hid Sensor IIO Common - -# -# SSP Sensor Common -# -# CONFIG_IIO_SSP_SENSORHUB is not set -# end of SSP Sensor Common - -# -# Digital to analog converters -# -# CONFIG_AD5064 is not set -# CONFIG_AD5360 is not set -# CONFIG_AD5380 is not set -# CONFIG_AD5421 is not set -# CONFIG_AD5446 is not set -# CONFIG_AD5449 is not set -# CONFIG_AD5592R is not set -# CONFIG_AD5593R is not set -# CONFIG_AD5504 is not set -# CONFIG_AD5624R_SPI is not set -# CONFIG_AD5686_SPI is not set -# CONFIG_AD5696_I2C is not set -# CONFIG_AD5755 is not set -# CONFIG_AD5758 is not set -# CONFIG_AD5761 is not set -# CONFIG_AD5764 is not set -# CONFIG_AD5770R is not set -# CONFIG_AD5791 is not set -# CONFIG_AD7303 is not set -# CONFIG_AD8801 is not set -# CONFIG_DPOT_DAC is not set -# CONFIG_DS4424 is not set -# CONFIG_LTC1660 is not set -# CONFIG_LTC2632 is not set -# CONFIG_M62332 is not set -# CONFIG_MAX517 is not set -# CONFIG_MAX5821 is not set -# CONFIG_MCP4725 is not set -# CONFIG_MCP4922 is not set -# CONFIG_TI_DAC082S085 is not set -# CONFIG_TI_DAC5571 is not set -# CONFIG_TI_DAC7311 is not set -# CONFIG_TI_DAC7612 is not set -# CONFIG_VF610_DAC is not set -# end of Digital to analog converters - -# -# IIO dummy driver -# -# end of IIO dummy driver - -# -# Frequency Synthesizers DDS/PLL -# - -# -# Clock Generator/Distribution -# -# CONFIG_AD9523 is not set -# end of Clock Generator/Distribution - -# -# Phase-Locked Loop (PLL) frequency synthesizers -# -# CONFIG_ADF4350 is not set -# CONFIG_ADF4371 is not set -# end of Phase-Locked Loop (PLL) frequency synthesizers -# end of Frequency Synthesizers DDS/PLL - -# -# Digital gyroscope sensors -# -# CONFIG_ADIS16080 is not set -# CONFIG_ADIS16130 is not set -# CONFIG_ADIS16136 is not set -# CONFIG_ADIS16260 is not set -# CONFIG_ADXRS290 is not set -# CONFIG_ADXRS450 is not set -# CONFIG_BMG160 is not set -# CONFIG_FXAS21002C is not set -CONFIG_MPU3050=y -CONFIG_MPU3050_I2C=y -# CONFIG_IIO_ST_GYRO_3AXIS is not set -# CONFIG_ITG3200 is not set -# end of Digital gyroscope sensors - -# -# Health Sensors -# - -# -# Heart Rate Monitors -# -# CONFIG_AFE4403 is not set -# CONFIG_AFE4404 is not set -# CONFIG_MAX30100 is not set -# CONFIG_MAX30102 is not set -# end of Heart Rate Monitors -# end of Health Sensors - -# -# Humidity sensors -# -# CONFIG_AM2315 is not set -# CONFIG_DHT11 is not set -# CONFIG_HDC100X is not set -# CONFIG_HDC2010 is not set -# CONFIG_HTS221 is not set -# CONFIG_HTU21 is not set -# CONFIG_SI7005 is not set -# CONFIG_SI7020 is not set -# end of Humidity sensors - -# -# Inertial measurement units -# -# CONFIG_ADIS16400 is not set -# CONFIG_ADIS16460 is not set -# CONFIG_ADIS16475 is not set -# CONFIG_ADIS16480 is not set -# CONFIG_BMI160_I2C is not set -# CONFIG_BMI160_SPI is not set -# CONFIG_FXOS8700_I2C is not set -# CONFIG_FXOS8700_SPI is not set -# CONFIG_KMX61 is not set -# CONFIG_INV_ICM42600_I2C is not set -# CONFIG_INV_ICM42600_SPI is not set -# CONFIG_INV_MPU6050_I2C is not set -# CONFIG_INV_MPU6050_SPI is not set -# CONFIG_IIO_ST_LSM6DSX is not set -# end of Inertial measurement units - -# -# Light sensors -# -# CONFIG_ADJD_S311 is not set -# CONFIG_ADUX1020 is not set -# CONFIG_AL3010 is not set -# CONFIG_AL3320A is not set -# CONFIG_APDS9300 is not set -# CONFIG_APDS9960 is not set -# CONFIG_AS73211 is not set -# CONFIG_BH1750 is not set -# CONFIG_BH1780 is not set -# CONFIG_CM32181 is not set -# CONFIG_CM3232 is not set -# CONFIG_CM3323 is not set -# CONFIG_CM3605 is not set -# CONFIG_CM36651 is not set -# CONFIG_GP2AP002 is not set -# CONFIG_GP2AP020A00F is not set -# CONFIG_SENSORS_ISL29018 is not set -# CONFIG_SENSORS_ISL29028 is not set -# CONFIG_ISL29125 is not set -# CONFIG_JSA1212 is not set -# CONFIG_RPR0521 is not set -# CONFIG_LTR501 is not set -# CONFIG_LV0104CS is not set -# CONFIG_MAX44000 is not set -# CONFIG_MAX44009 is not set -# CONFIG_NOA1305 is not set -# CONFIG_OPT3001 is not set -# CONFIG_PA12203001 is not set -# CONFIG_SI1133 is not set -# CONFIG_SI1145 is not set -# CONFIG_STK3310 is not set -# CONFIG_ST_UVIS25 is not set -# CONFIG_TCS3414 is not set -# CONFIG_TCS3472 is not set -# CONFIG_SENSORS_TSL2563 is not set -# CONFIG_TSL2583 is not set -# CONFIG_TSL2772 is not set -# CONFIG_TSL4531 is not set -# CONFIG_US5182D is not set -# CONFIG_VCNL4000 is not set -# CONFIG_VCNL4035 is not set -# CONFIG_VEML6030 is not set -# CONFIG_VEML6070 is not set -# CONFIG_VL6180 is not set -# CONFIG_ZOPT2201 is not set -# end of Light sensors - -# -# Magnetometer sensors -# -# CONFIG_AK8974 is not set -# CONFIG_AK8975 is not set -# CONFIG_AK09911 is not set -# CONFIG_BMC150_MAGN_I2C is not set -# CONFIG_BMC150_MAGN_SPI is not set -# CONFIG_MAG3110 is not set -# CONFIG_MMC35240 is not set -# CONFIG_IIO_ST_MAGN_3AXIS is not set -# CONFIG_SENSORS_HMC5843_I2C is not set -# CONFIG_SENSORS_HMC5843_SPI is not set -# CONFIG_SENSORS_RM3100_I2C is not set -# CONFIG_SENSORS_RM3100_SPI is not set -# end of Magnetometer sensors - -# -# Multiplexers -# -# CONFIG_IIO_MUX is not set -# end of Multiplexers - -# -# Inclinometer sensors -# -# end of Inclinometer sensors - -# -# Triggers - standalone -# -CONFIG_IIO_HRTIMER_TRIGGER=y -# CONFIG_IIO_INTERRUPT_TRIGGER is not set -# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set -# CONFIG_IIO_SYSFS_TRIGGER is not set -# end of Triggers - standalone - -# -# Linear and angular position sensors -# -# end of Linear and angular position sensors - -# -# Digital potentiometers -# -# CONFIG_AD5272 is not set -# CONFIG_DS1803 is not set -# CONFIG_MAX5432 is not set -# CONFIG_MAX5481 is not set -# CONFIG_MAX5487 is not set -# CONFIG_MCP4018 is not set -# CONFIG_MCP4131 is not set -# CONFIG_MCP4531 is not set -# CONFIG_MCP41010 is not set -# CONFIG_TPL0102 is not set -# end of Digital potentiometers - -# -# Digital potentiostats -# -# CONFIG_LMP91000 is not set -# end of Digital potentiostats - -# -# Pressure sensors -# -# CONFIG_ABP060MG is not set -# CONFIG_BMP280 is not set -# CONFIG_DLHL60D is not set -# CONFIG_DPS310 is not set -# CONFIG_HP03 is not set -# CONFIG_ICP10100 is not set -# CONFIG_MPL115_I2C is not set -# CONFIG_MPL115_SPI is not set -# CONFIG_MPL3115 is not set -# CONFIG_MS5611 is not set -# CONFIG_MS5637 is not set -# CONFIG_IIO_ST_PRESS is not set -# CONFIG_T5403 is not set -# CONFIG_HP206C is not set -# CONFIG_ZPA2326 is not set -# end of Pressure sensors - -# -# Lightning sensors -# -# CONFIG_AS3935 is not set -# end of Lightning sensors - -# -# Proximity and distance sensors -# -# CONFIG_ISL29501 is not set -# CONFIG_LIDAR_LITE_V2 is not set -# CONFIG_MB1232 is not set -# CONFIG_PING is not set -# CONFIG_RFD77402 is not set -# CONFIG_SRF04 is not set -# CONFIG_SX9310 is not set -# CONFIG_SX9500 is not set -# CONFIG_SRF08 is not set -# CONFIG_VCNL3020 is not set -# CONFIG_VL53L0X_I2C is not set -# end of Proximity and distance sensors - -# -# Resolver to digital converters -# -# CONFIG_AD2S90 is not set -# CONFIG_AD2S1200 is not set -# end of Resolver to digital converters - -# -# Temperature sensors -# -# CONFIG_LTC2983 is not set -# CONFIG_MAXIM_THERMOCOUPLE is not set -# CONFIG_MLX90614 is not set -# CONFIG_MLX90632 is not set -# CONFIG_TMP006 is not set -# CONFIG_TMP007 is not set -# CONFIG_TSYS01 is not set -# CONFIG_TSYS02D is not set -# CONFIG_MAX31856 is not set -# end of Temperature sensors - -# CONFIG_NTB is not set -# CONFIG_VME_BUS is not set -CONFIG_PWM=y -CONFIG_PWM_SYSFS=y -# CONFIG_PWM_DEBUG is not set -# CONFIG_PWM_FSL_FTM is not set -CONFIG_PWM_MESON=y -# CONFIG_PWM_PCA9685 is not set - -# -# IRQ chip support -# -CONFIG_IRQCHIP=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_MAX_NR=1 -# CONFIG_AL_FIC is not set -CONFIG_MESON_IRQ_GPIO=y -# end of IRQ chip support - -# CONFIG_IPACK_BUS is not set -CONFIG_RESET_CONTROLLER=y -CONFIG_RESET_MESON=y -CONFIG_RESET_MESON_AUDIO_ARB=m -CONFIG_RESET_SCMI=m -# CONFIG_RESET_TI_SYSCON is not set - -# -# PHY Subsystem -# -CONFIG_GENERIC_PHY=y -CONFIG_PHY_MESON8_HDMI_TX=y -CONFIG_PHY_MESON8B_USB2=y -# CONFIG_PHY_MESON_GXL_USB2 is not set -# CONFIG_PHY_MESON_G12A_USB2 is not set -# CONFIG_PHY_MESON_G12A_USB3_PCIE is not set -# CONFIG_PHY_MESON_AXG_PCIE is not set -# CONFIG_PHY_MESON_AXG_MIPI_PCIE_ANALOG is not set -# CONFIG_BCM_KONA_USB2_PHY is not set -# CONFIG_PHY_CADENCE_TORRENT is not set -# CONFIG_PHY_CADENCE_DPHY is not set -# CONFIG_PHY_CADENCE_SIERRA is not set -# CONFIG_PHY_CADENCE_SALVO is not set -# CONFIG_PHY_FSL_IMX8MQ_USB is not set -# CONFIG_PHY_MIXEL_MIPI_DPHY is not set -# CONFIG_PHY_PXA_28NM_HSIC is not set -# CONFIG_PHY_PXA_28NM_USB2 is not set -# CONFIG_PHY_CPCAP_USB is not set -# CONFIG_PHY_MAPPHONE_MDM6600 is not set -# CONFIG_PHY_OCELOT_SERDES is not set -# CONFIG_PHY_QCOM_USB_HS is not set -# CONFIG_PHY_QCOM_USB_HSIC is not set -# CONFIG_PHY_SAMSUNG_USB2 is not set -# CONFIG_PHY_TUSB1210 is not set -# end of PHY Subsystem - -# CONFIG_POWERCAP is not set -# CONFIG_MCB is not set - -# -# Performance monitor support -# -# CONFIG_ARM_CCI_PMU is not set -# CONFIG_ARM_CCN is not set -CONFIG_ARM_PMU=y -# end of Performance monitor support - -CONFIG_RAS=y -# CONFIG_USB4 is not set - -# -# Android -# -# CONFIG_ANDROID is not set -# end of Android - -CONFIG_DAX=m -CONFIG_NVMEM=y -CONFIG_NVMEM_SYSFS=y -CONFIG_MESON_MX_EFUSE=y - -# -# HW tracing support -# -# CONFIG_STM is not set -# CONFIG_INTEL_TH is not set -# end of HW tracing support - -# CONFIG_FPGA is not set -# CONFIG_FSI is not set -# CONFIG_TEE is not set -CONFIG_MULTIPLEXER=m - -# -# Multiplexer drivers -# -# CONFIG_MUX_ADG792A is not set -# CONFIG_MUX_ADGS1408 is not set -# CONFIG_MUX_GPIO is not set -# CONFIG_MUX_MMIO is not set -# end of Multiplexer drivers - -CONFIG_PM_OPP=y -# CONFIG_SIOX is not set -# CONFIG_SLIMBUS is not set -# CONFIG_INTERCONNECT is not set -CONFIG_COUNTER=m -# CONFIG_FTM_QUADDEC is not set -# CONFIG_MICROCHIP_TCB_CAPTURE is not set -# CONFIG_MOST is not set -# end of Device Drivers - -# -# File systems -# -CONFIG_DCACHE_WORD_ACCESS=y -CONFIG_VALIDATE_FS_PARSER=y -CONFIG_FS_IOMAP=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXT4_FS_SECURITY=y -# CONFIG_EXT4_DEBUG is not set -CONFIG_JBD2=y -# CONFIG_JBD2_DEBUG is not set -CONFIG_FS_MBCACHE=y -CONFIG_REISERFS_FS=y -# CONFIG_REISERFS_CHECK is not set -CONFIG_REISERFS_PROC_INFO=y -CONFIG_REISERFS_FS_XATTR=y -CONFIG_REISERFS_FS_POSIX_ACL=y -CONFIG_REISERFS_FS_SECURITY=y -CONFIG_JFS_FS=y -CONFIG_JFS_POSIX_ACL=y -CONFIG_JFS_SECURITY=y -# CONFIG_JFS_DEBUG is not set -CONFIG_JFS_STATISTICS=y -CONFIG_XFS_FS=y -CONFIG_XFS_SUPPORT_V4=y -CONFIG_XFS_QUOTA=y -CONFIG_XFS_POSIX_ACL=y -CONFIG_XFS_RT=y -CONFIG_XFS_ONLINE_SCRUB=y -CONFIG_XFS_ONLINE_REPAIR=y -# CONFIG_XFS_WARN is not set -# CONFIG_XFS_DEBUG is not set -CONFIG_GFS2_FS=y -# CONFIG_GFS2_FS_LOCKING_DLM is not set -CONFIG_OCFS2_FS=y -CONFIG_OCFS2_FS_O2CB=y -CONFIG_OCFS2_FS_USERSPACE_CLUSTER=y -CONFIG_OCFS2_FS_STATS=y -CONFIG_OCFS2_DEBUG_MASKLOG=y -CONFIG_OCFS2_DEBUG_FS=y -CONFIG_BTRFS_FS=y -CONFIG_BTRFS_FS_POSIX_ACL=y -# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set -# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set -# CONFIG_BTRFS_DEBUG is not set -CONFIG_BTRFS_ASSERT=y -# CONFIG_BTRFS_FS_REF_VERIFY is not set -CONFIG_NILFS2_FS=y -CONFIG_F2FS_FS=y -CONFIG_F2FS_STAT_FS=y -CONFIG_F2FS_FS_XATTR=y -CONFIG_F2FS_FS_POSIX_ACL=y -CONFIG_F2FS_FS_SECURITY=y -CONFIG_F2FS_CHECK_FS=y -CONFIG_F2FS_FAULT_INJECTION=y -CONFIG_F2FS_FS_COMPRESSION=y -CONFIG_F2FS_FS_LZO=y -CONFIG_F2FS_FS_LZ4=y -CONFIG_F2FS_FS_ZSTD=y -CONFIG_F2FS_FS_LZORLE=y -CONFIG_FS_POSIX_ACL=y -CONFIG_EXPORTFS=y -CONFIG_EXPORTFS_BLOCK_OPS=y -CONFIG_FILE_LOCKING=y -CONFIG_MANDATORY_FILE_LOCKING=y -CONFIG_FS_ENCRYPTION=y -CONFIG_FS_ENCRYPTION_ALGS=y -CONFIG_FS_VERITY=y -# CONFIG_FS_VERITY_DEBUG is not set -# CONFIG_FS_VERITY_BUILTIN_SIGNATURES is not set -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY_USER=y -CONFIG_FANOTIFY=y -CONFIG_QUOTA=y -CONFIG_QUOTA_NETLINK_INTERFACE=y -CONFIG_PRINT_QUOTA_WARNING=y -# CONFIG_QUOTA_DEBUG is not set -CONFIG_QUOTA_TREE=y -CONFIG_QFMT_V1=y -CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y -CONFIG_AUTOFS4_FS=y -CONFIG_AUTOFS_FS=y -CONFIG_FUSE_FS=y -CONFIG_CUSE=y -CONFIG_VIRTIO_FS=y -CONFIG_OVERLAY_FS=y -# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set -CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y -# CONFIG_OVERLAY_FS_INDEX is not set -# CONFIG_OVERLAY_FS_METACOPY is not set - -# -# Caches -# -CONFIG_FSCACHE=y -CONFIG_FSCACHE_STATS=y -# CONFIG_FSCACHE_HISTOGRAM is not set -# CONFIG_FSCACHE_DEBUG is not set -# CONFIG_FSCACHE_OBJECT_LIST is not set -CONFIG_CACHEFILES=y -# CONFIG_CACHEFILES_DEBUG is not set -# CONFIG_CACHEFILES_HISTOGRAM is not set -# end of Caches - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=y -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=y -# end of CD-ROM/DVD Filesystems - -# -# DOS/FAT/EXFAT/NT Filesystems -# -CONFIG_FAT_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -CONFIG_FAT_DEFAULT_UTF8=y -CONFIG_EXFAT_FS=y -CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" -CONFIG_NTFS_FS=y -# CONFIG_NTFS_DEBUG is not set -CONFIG_NTFS_RW=y -# end of DOS/FAT/EXFAT/NT Filesystems - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PROC_CHILDREN=y -CONFIG_KERNFS=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_TMPFS_XATTR=y -CONFIG_MEMFD_CREATE=y -CONFIG_CONFIGFS_FS=y -CONFIG_EFIVAR_FS=m -# end of Pseudo filesystems - -CONFIG_MISC_FILESYSTEMS=y -CONFIG_ORANGEFS_FS=m -CONFIG_ADFS_FS=m -# CONFIG_ADFS_FS_RW is not set -CONFIG_AFFS_FS=m -CONFIG_ECRYPT_FS=m -CONFIG_ECRYPT_FS_MESSAGING=y -CONFIG_HFS_FS=m -CONFIG_HFSPLUS_FS=m -CONFIG_BEFS_FS=m -# CONFIG_BEFS_DEBUG is not set -CONFIG_BFS_FS=m -CONFIG_EFS_FS=m -CONFIG_CRAMFS=m -CONFIG_CRAMFS_BLOCKDEV=y -CONFIG_SQUASHFS=m -CONFIG_SQUASHFS_FILE_CACHE=y -# CONFIG_SQUASHFS_FILE_DIRECT is not set -CONFIG_SQUASHFS_DECOMP_SINGLE=y -# CONFIG_SQUASHFS_DECOMP_MULTI is not set -# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set -CONFIG_SQUASHFS_XATTR=y -CONFIG_SQUASHFS_ZLIB=y -CONFIG_SQUASHFS_LZ4=y -CONFIG_SQUASHFS_LZO=y -CONFIG_SQUASHFS_XZ=y -CONFIG_SQUASHFS_ZSTD=y -CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y -CONFIG_SQUASHFS_EMBEDDED=y -CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 -CONFIG_VXFS_FS=m -CONFIG_MINIX_FS=m -CONFIG_OMFS_FS=m -CONFIG_HPFS_FS=m -CONFIG_QNX4FS_FS=m -CONFIG_QNX6FS_FS=m -# CONFIG_QNX6FS_DEBUG is not set -CONFIG_ROMFS_FS=m -CONFIG_ROMFS_BACKED_BY_BLOCK=y -CONFIG_ROMFS_ON_BLOCK=y -CONFIG_PSTORE=m -CONFIG_PSTORE_DEFLATE_COMPRESS=m -CONFIG_PSTORE_LZO_COMPRESS=m -CONFIG_PSTORE_LZ4_COMPRESS=m -CONFIG_PSTORE_LZ4HC_COMPRESS=m -CONFIG_PSTORE_842_COMPRESS=y -CONFIG_PSTORE_ZSTD_COMPRESS=y -CONFIG_PSTORE_COMPRESS=y -CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y -# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set -# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set -# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set -# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set -# CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT is not set -CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" -CONFIG_PSTORE_CONSOLE=y -CONFIG_PSTORE_PMSG=y -CONFIG_PSTORE_RAM=m -CONFIG_SYSV_FS=m -CONFIG_UFS_FS=m -# CONFIG_UFS_FS_WRITE is not set -# CONFIG_UFS_DEBUG is not set -CONFIG_EROFS_FS=m -# CONFIG_EROFS_FS_DEBUG is not set -CONFIG_EROFS_FS_XATTR=y -CONFIG_EROFS_FS_POSIX_ACL=y -CONFIG_EROFS_FS_SECURITY=y -CONFIG_EROFS_FS_ZIP=y -CONFIG_EROFS_FS_CLUSTER_PAGE_LIMIT=1 -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V2=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NFS_SWAP=y -CONFIG_NFS_V4_1=y -CONFIG_NFS_V4_2=y -CONFIG_PNFS_FILE_LAYOUT=y -CONFIG_PNFS_BLOCK=m -CONFIG_PNFS_FLEXFILE_LAYOUT=y -CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" -CONFIG_NFS_V4_1_MIGRATION=y -CONFIG_ROOT_NFS=y -CONFIG_NFS_FSCACHE=y -# CONFIG_NFS_USE_LEGACY_DNS is not set -CONFIG_NFS_USE_KERNEL_DNS=y -CONFIG_NFS_DEBUG=y -CONFIG_NFS_DISABLE_UDP_SUPPORT=y -CONFIG_NFS_V4_2_READ_PLUS=y -CONFIG_NFSD=m -CONFIG_NFSD_V2_ACL=y -CONFIG_NFSD_V3=y -CONFIG_NFSD_V3_ACL=y -CONFIG_NFSD_V4=y -CONFIG_NFSD_PNFS=y -CONFIG_NFSD_BLOCKLAYOUT=y -CONFIG_NFSD_SCSILAYOUT=y -CONFIG_NFSD_FLEXFILELAYOUT=y -CONFIG_NFSD_V4_2_INTER_SSC=y -CONFIG_GRACE_PERIOD=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -CONFIG_SUNRPC_BACKCHANNEL=y -CONFIG_SUNRPC_SWAP=y -CONFIG_RPCSEC_GSS_KRB5=m -# CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES is not set -CONFIG_SUNRPC_DEBUG=y -CONFIG_CEPH_FS=m -CONFIG_CEPH_FSCACHE=y -CONFIG_CEPH_FS_POSIX_ACL=y -CONFIG_CIFS=m -CONFIG_CIFS_STATS2=y -CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y -# CONFIG_CIFS_WEAK_PW_HASH is not set -CONFIG_CIFS_UPCALL=y -CONFIG_CIFS_XATTR=y -CONFIG_CIFS_POSIX=y -CONFIG_CIFS_DEBUG=y -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set -CONFIG_CIFS_DFS_UPCALL=y -CONFIG_CIFS_FSCACHE=y -CONFIG_CODA_FS=m -CONFIG_AFS_FS=m -# CONFIG_AFS_DEBUG is not set -CONFIG_AFS_FSCACHE=y -# CONFIG_AFS_DEBUG_CURSOR is not set -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="utf-8" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_MAC_ROMAN=m -CONFIG_NLS_MAC_CELTIC=m -CONFIG_NLS_MAC_CENTEURO=m -CONFIG_NLS_MAC_CROATIAN=m -CONFIG_NLS_MAC_CYRILLIC=m -CONFIG_NLS_MAC_GAELIC=m -CONFIG_NLS_MAC_GREEK=m -CONFIG_NLS_MAC_ICELAND=m -CONFIG_NLS_MAC_INUIT=m -CONFIG_NLS_MAC_ROMANIAN=m -CONFIG_NLS_MAC_TURKISH=m -CONFIG_NLS_UTF8=y -CONFIG_DLM=y -# CONFIG_DLM_DEBUG is not set -CONFIG_UNICODE=y -# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set -CONFIG_IO_WQ=y -# end of File systems - -# -# Security options -# -CONFIG_KEYS=y -# CONFIG_KEYS_REQUEST_CACHE is not set -# CONFIG_PERSISTENT_KEYRINGS is not set -# CONFIG_ENCRYPTED_KEYS is not set -# CONFIG_KEY_DH_OPERATIONS is not set -# CONFIG_KEY_NOTIFICATIONS is not set -# CONFIG_SECURITY_DMESG_RESTRICT is not set -# CONFIG_SECURITY is not set -CONFIG_SECURITYFS=y -CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y -# CONFIG_HARDENED_USERCOPY is not set -# CONFIG_FORTIFY_SOURCE is not set -# CONFIG_STATIC_USERMODEHELPER is not set -CONFIG_DEFAULT_SECURITY_DAC=y -CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,integrity,bpf" - -# -# Kernel hardening options -# - -# -# Memory initialization -# -CONFIG_INIT_STACK_NONE=y -# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set -# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set -# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set -# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set -# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set -# end of Memory initialization -# end of Kernel hardening options -# end of Security options - -CONFIG_XOR_BLOCKS=y -CONFIG_ASYNC_CORE=m -CONFIG_ASYNC_MEMCPY=m -CONFIG_ASYNC_XOR=m -CONFIG_ASYNC_PQ=m -CONFIG_ASYNC_RAID6_RECOV=m -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD=m -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_SKCIPHER=y -CONFIG_CRYPTO_SKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG=m -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=m -CONFIG_CRYPTO_AKCIPHER2=y -CONFIG_CRYPTO_AKCIPHER=y -CONFIG_CRYPTO_KPP2=y -CONFIG_CRYPTO_KPP=m -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -CONFIG_CRYPTO_USER=m -CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_NULL2=y -CONFIG_CRYPTO_PCRYPT=m -CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_AUTHENC=m -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_SIMD=m - -# -# Public-key cryptography -# -CONFIG_CRYPTO_RSA=y -CONFIG_CRYPTO_DH=m -CONFIG_CRYPTO_ECC=m -CONFIG_CRYPTO_ECDH=m -CONFIG_CRYPTO_ECRDSA=m -CONFIG_CRYPTO_SM2=m -CONFIG_CRYPTO_CURVE25519=m - -# -# Authenticated Encryption with Associated Data -# -CONFIG_CRYPTO_CCM=m -CONFIG_CRYPTO_GCM=m -CONFIG_CRYPTO_CHACHA20POLY1305=m -CONFIG_CRYPTO_AEGIS128=m -CONFIG_CRYPTO_AEGIS128_SIMD=y -CONFIG_CRYPTO_SEQIV=m -CONFIG_CRYPTO_ECHAINIV=m - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CFB=m -CONFIG_CRYPTO_CTR=m -CONFIG_CRYPTO_CTS=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_OFB=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XTS=y -CONFIG_CRYPTO_KEYWRAP=m -CONFIG_CRYPTO_NHPOLY1305=m -CONFIG_CRYPTO_ADIANTUM=m -CONFIG_CRYPTO_ESSIV=m - -# -# Hash modes -# -CONFIG_CRYPTO_CMAC=m -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_VMAC=m - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRC32=y -CONFIG_CRYPTO_XXHASH=y -CONFIG_CRYPTO_BLAKE2B=y -# CONFIG_CRYPTO_BLAKE2S is not set -CONFIG_CRYPTO_CRCT10DIF=y -CONFIG_CRYPTO_GHASH=m -CONFIG_CRYPTO_POLY1305=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_MICHAEL_MIC=m -# CONFIG_CRYPTO_RMD128 is not set -CONFIG_CRYPTO_RMD160=m -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_SHA3=m -CONFIG_CRYPTO_SM3=m -CONFIG_CRYPTO_STREEBOG=m -# CONFIG_CRYPTO_TGR192 is not set -CONFIG_CRYPTO_WP512=m - -# -# Ciphers -# -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_AES_TI=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_BLOWFISH_COMMON=m -CONFIG_CRYPTO_CAMELLIA=m -CONFIG_CRYPTO_CAST_COMMON=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -# CONFIG_CRYPTO_SALSA20 is not set -CONFIG_CRYPTO_CHACHA20=m -CONFIG_CRYPTO_SEED=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_SM4=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m - -# -# Compression -# -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -CONFIG_CRYPTO_842=m -CONFIG_CRYPTO_LZ4=m -CONFIG_CRYPTO_LZ4HC=m -CONFIG_CRYPTO_ZSTD=y - -# -# Random Number Generation -# -CONFIG_CRYPTO_ANSI_CPRNG=m -CONFIG_CRYPTO_DRBG_MENU=m -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_HASH=y -CONFIG_CRYPTO_DRBG_CTR=y -CONFIG_CRYPTO_DRBG=m -CONFIG_CRYPTO_JITTERENTROPY=m -CONFIG_CRYPTO_USER_API=m -CONFIG_CRYPTO_USER_API_HASH=m -CONFIG_CRYPTO_USER_API_SKCIPHER=m -CONFIG_CRYPTO_USER_API_RNG=m -# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set -CONFIG_CRYPTO_USER_API_AEAD=m -CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE=y -CONFIG_CRYPTO_STATS=y -CONFIG_CRYPTO_HASH_INFO=y -# CONFIG_CRYPTO_HW is not set -CONFIG_ASYMMETRIC_KEY_TYPE=y -CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y -CONFIG_X509_CERTIFICATE_PARSER=y -CONFIG_PKCS8_PRIVATE_KEY_PARSER=m -CONFIG_PKCS7_MESSAGE_PARSER=y -# CONFIG_PKCS7_TEST_KEY is not set -CONFIG_SIGNED_PE_FILE_VERIFICATION=y - -# -# Certificates for signature checking -# -CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" -CONFIG_SYSTEM_TRUSTED_KEYRING=y -CONFIG_SYSTEM_TRUSTED_KEYS="" -CONFIG_SYSTEM_EXTRA_CERTIFICATE=y -CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096 -CONFIG_SECONDARY_TRUSTED_KEYRING=y -CONFIG_SYSTEM_BLACKLIST_KEYRING=y -CONFIG_SYSTEM_BLACKLIST_HASH_LIST="" -# CONFIG_SYSTEM_REVOCATION_LIST is not set -# end of Certificates for signature checking - -CONFIG_BINARY_PRINTF=y - -# -# Library routines -# -CONFIG_RAID6_PQ=y -CONFIG_RAID6_PQ_BENCHMARK=y -CONFIG_LINEAR_RANGES=y -CONFIG_PACKING=y -CONFIG_BITREVERSE=y -CONFIG_HAVE_ARCH_BITREVERSE=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_NET_UTILS=y -CONFIG_CORDIC=m -CONFIG_PRIME_NUMBERS=m -CONFIG_RATIONAL=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y - -# -# Crypto library routines -# -CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=m -CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y -CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=m -CONFIG_CRYPTO_LIB_CHACHA_GENERIC=m -CONFIG_CRYPTO_LIB_CHACHA=m -CONFIG_CRYPTO_ARCH_HAVE_LIB_CURVE25519=m -CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=m -CONFIG_CRYPTO_LIB_CURVE25519=m -CONFIG_CRYPTO_LIB_DES=m -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=9 -CONFIG_CRYPTO_ARCH_HAVE_LIB_POLY1305=m -CONFIG_CRYPTO_LIB_POLY1305_GENERIC=m -CONFIG_CRYPTO_LIB_POLY1305=m -CONFIG_CRYPTO_LIB_CHACHA20POLY1305=m -CONFIG_CRYPTO_LIB_SHA256=y -# end of Crypto library routines - -CONFIG_LIB_MEMNEQ=y -CONFIG_CRC_CCITT=m -CONFIG_CRC16=y -CONFIG_CRC_T10DIF=y -CONFIG_CRC_ITU_T=y -CONFIG_CRC32=y -# CONFIG_CRC32_SELFTEST is not set -CONFIG_CRC32_SLICEBY8=y -# CONFIG_CRC32_SLICEBY4 is not set -# CONFIG_CRC32_SARWATE is not set -# CONFIG_CRC32_BIT is not set -CONFIG_CRC64=y -CONFIG_CRC4=m -CONFIG_CRC7=m -CONFIG_LIBCRC32C=y -CONFIG_CRC8=m -CONFIG_XXHASH=y -CONFIG_AUDIT_GENERIC=y -# CONFIG_RANDOM32_SELFTEST is not set -CONFIG_842_COMPRESS=m -CONFIG_842_DECOMPRESS=m -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_LZ4_COMPRESS=y -CONFIG_LZ4HC_COMPRESS=m -CONFIG_LZ4_DECOMPRESS=y -CONFIG_ZSTD_COMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y -CONFIG_XZ_DEC=y -CONFIG_XZ_DEC_X86=y -CONFIG_XZ_DEC_POWERPC=y -CONFIG_XZ_DEC_IA64=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_SPARC=y -CONFIG_XZ_DEC_BCJ=y -# CONFIG_XZ_DEC_TEST is not set -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DECOMPRESS_BZIP2=y -CONFIG_DECOMPRESS_LZMA=y -CONFIG_DECOMPRESS_XZ=y -CONFIG_DECOMPRESS_LZO=y -CONFIG_DECOMPRESS_LZ4=y -CONFIG_DECOMPRESS_ZSTD=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_REED_SOLOMON=m -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_ASSOCIATIVE_ARRAY=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAS_DMA=y -CONFIG_DMA_OPS=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_DMA_DECLARE_COHERENT=y -CONFIG_ARCH_HAS_SETUP_DMA_OPS=y -CONFIG_ARCH_HAS_TEARDOWN_DMA_OPS=y -CONFIG_DMA_NONCOHERENT_MMAP=y -CONFIG_DMA_REMAP=y -CONFIG_DMA_CMA=y -# CONFIG_DMA_PERNUMA_CMA is not set - -# -# Default contiguous memory area size: -# -CONFIG_CMA_SIZE_MBYTES=64 -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_ALIGNMENT=8 -# CONFIG_DMA_API_DEBUG is not set -CONFIG_SGL_ALLOC=y -CONFIG_CPU_RMAP=y -CONFIG_DQL=y -CONFIG_GLOB=y -# CONFIG_GLOB_SELFTEST is not set -CONFIG_NLATTR=y -CONFIG_LRU_CACHE=m -CONFIG_CLZ_TAB=y -# CONFIG_IRQ_POLL is not set -CONFIG_MPILIB=y -CONFIG_LIBFDT=y -CONFIG_OID_REGISTRY=y -CONFIG_UCS2_STRING=y -CONFIG_HAVE_GENERIC_VDSO=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_VDSO_32=y -CONFIG_FONT_SUPPORT=y -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -CONFIG_SG_POOL=y -CONFIG_SBITMAP=y -# CONFIG_STRING_SELFTEST is not set -# end of Library routines - -# -# Kernel hacking -# - -# -# printk and dmesg options -# -CONFIG_PRINTK_TIME=y -# CONFIG_PRINTK_CALLER is not set -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 -CONFIG_CONSOLE_LOGLEVEL_QUIET=4 -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 -# CONFIG_BOOT_PRINTK_DELAY is not set -# CONFIG_DYNAMIC_DEBUG is not set -# CONFIG_DYNAMIC_DEBUG_CORE is not set -CONFIG_SYMBOLIC_ERRNAME=y -CONFIG_DEBUG_BUGVERBOSE=y -# end of printk and dmesg options - -# -# Compile-time checks and compiler options -# -# CONFIG_DEBUG_INFO is not set -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=1024 -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_READABLE_ASM is not set -# CONFIG_HEADERS_INSTALL is not set -# CONFIG_DEBUG_SECTION_MISMATCH is not set -CONFIG_SECTION_MISMATCH_WARN_ONLY=y -# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# end of Compile-time checks and compiler options - -# -# Generic Kernel Debugging Instruments -# -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 -CONFIG_MAGIC_SYSRQ_SERIAL=y -CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_FS_ALLOW_ALL=y -# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set -# CONFIG_DEBUG_FS_ALLOW_NONE is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -# CONFIG_UBSAN is not set -# end of Generic Kernel Debugging Instruments - -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MISC=y - -# -# Memory Debugging -# -# CONFIG_PAGE_EXTENSION is not set -# CONFIG_DEBUG_PAGEALLOC is not set -# CONFIG_PAGE_OWNER is not set -# CONFIG_PAGE_POISONING is not set -# CONFIG_DEBUG_PAGE_REF is not set -# CONFIG_DEBUG_RODATA_TEST is not set -# CONFIG_DEBUG_WX is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_SLUB_DEBUG_ON is not set -# CONFIG_SLUB_STATS is not set -CONFIG_HAVE_DEBUG_KMEMLEAK=y -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_SCHED_STACK_END_CHECK is not set -# CONFIG_DEBUG_VM is not set -CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -# CONFIG_DEBUG_VIRTUAL is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_PER_CPU_MAPS is not set -# CONFIG_DEBUG_HIGHMEM is not set -CONFIG_CC_HAS_KASAN_GENERIC=y -CONFIG_CC_HAS_WORKING_NOSANITIZE_ADDRESS=y -# end of Memory Debugging - -# CONFIG_DEBUG_SHIRQ is not set - -# -# Debug Oops, Lockups and Hangs -# -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 -# CONFIG_SOFTLOCKUP_DETECTOR is not set -# CONFIG_DETECT_HUNG_TASK is not set -# CONFIG_WQ_WATCHDOG is not set -# CONFIG_TEST_LOCKUP is not set -# end of Debug Oops, Lockups and Hangs - -# -# Scheduler Debugging -# -CONFIG_SCHED_DEBUG=y -CONFIG_SCHED_INFO=y -# CONFIG_SCHEDSTATS is not set -# end of Scheduler Debugging - -# CONFIG_DEBUG_TIMEKEEPING is not set - -# -# Lock Debugging (spinlocks, mutexes, etc...) -# -CONFIG_LOCK_DEBUGGING_SUPPORT=y -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set -# CONFIG_DEBUG_RWSEMS is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_DEBUG_ATOMIC_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_LOCK_TORTURE_TEST is not set -# CONFIG_WW_MUTEX_SELFTEST is not set -# CONFIG_SCF_TORTURE_TEST is not set -# end of Lock Debugging (spinlocks, mutexes, etc...) - -CONFIG_STACKTRACE=y -# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set -# CONFIG_DEBUG_KOBJECT is not set - -# -# Debug kernel data structures -# -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_PLIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_BUG_ON_DATA_CORRUPTION is not set -# end of Debug kernel data structures - -# CONFIG_DEBUG_CREDENTIALS is not set - -# -# RCU Debugging -# -# CONFIG_RCU_SCALE_TEST is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_REF_SCALE_TEST is not set -CONFIG_RCU_CPU_STALL_TIMEOUT=21 -CONFIG_RCU_TRACE=y -# CONFIG_RCU_EQS_DEBUG is not set -# end of RCU Debugging - -# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -# CONFIG_LATENCYTOP is not set -CONFIG_NOP_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_TRACE_CLOCK=y -CONFIG_RING_BUFFER=y -CONFIG_EVENT_TRACING=y -CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_TRACING=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_BOOTTIME_TRACING is not set -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_HWLAT_TRACER is not set -# CONFIG_ENABLE_DEFAULT_TRACERS is not set -# CONFIG_FTRACE_SYSCALLS is not set -# CONFIG_TRACER_SNAPSHOT is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -CONFIG_KPROBE_EVENTS=y -CONFIG_UPROBE_EVENTS=y -CONFIG_BPF_EVENTS=y -CONFIG_DYNAMIC_EVENTS=y -CONFIG_PROBE_EVENTS=y -# CONFIG_SYNTH_EVENTS is not set -# CONFIG_TRACE_EVENT_INJECT is not set -# CONFIG_TRACEPOINT_BENCHMARK is not set -# CONFIG_RING_BUFFER_BENCHMARK is not set -# CONFIG_TRACE_EVAL_MAP_FILE is not set -# CONFIG_RING_BUFFER_STARTUP_TEST is not set -# CONFIG_PREEMPTIRQ_DELAY_TEST is not set -# CONFIG_KPROBE_EVENT_GEN_TEST is not set -# CONFIG_SAMPLES is not set -CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y -# CONFIG_STRICT_DEVMEM is not set - -# -# arm Debugging -# -# CONFIG_ARM_PTDUMP_DEBUGFS is not set -# CONFIG_UNWINDER_FRAME_POINTER is not set -CONFIG_UNWINDER_ARM=y -CONFIG_ARM_UNWIND=y -# CONFIG_DEBUG_USER is not set -# CONFIG_DEBUG_LL is not set -CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" -CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" -# CONFIG_ARM_KPROBES_TEST is not set -# CONFIG_PID_IN_CONTEXTIDR is not set -# CONFIG_CORESIGHT is not set -# end of arm Debugging - -# -# Kernel Testing and Coverage -# -# CONFIG_KUNIT is not set -# CONFIG_NOTIFIER_ERROR_INJECTION is not set -# CONFIG_FAULT_INJECTION is not set -CONFIG_ARCH_HAS_KCOV=y -CONFIG_CC_HAS_SANCOV_TRACE_PC=y -# CONFIG_KCOV is not set -CONFIG_RUNTIME_TESTING_MENU=y -# CONFIG_LKDTM is not set -# CONFIG_TEST_LIST_SORT is not set -# CONFIG_TEST_MIN_HEAP is not set -# CONFIG_TEST_SORT is not set -# CONFIG_KPROBES_SANITY_TEST is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_RBTREE_TEST is not set -# CONFIG_REED_SOLOMON_TEST is not set -# CONFIG_INTERVAL_TREE_TEST is not set -# CONFIG_PERCPU_TEST is not set -# CONFIG_ATOMIC64_SELFTEST is not set -# CONFIG_ASYNC_RAID6_TEST is not set -# CONFIG_TEST_HEXDUMP is not set -# CONFIG_TEST_STRING_HELPERS is not set -# CONFIG_TEST_STRSCPY is not set -# CONFIG_TEST_KSTRTOX is not set -# CONFIG_TEST_PRINTF is not set -# CONFIG_TEST_BITMAP is not set -# CONFIG_TEST_UUID is not set -# CONFIG_TEST_XARRAY is not set -# CONFIG_TEST_OVERFLOW is not set -# CONFIG_TEST_RHASHTABLE is not set -# CONFIG_TEST_HASH is not set -# CONFIG_TEST_IDA is not set -# CONFIG_TEST_LKM is not set -# CONFIG_TEST_BITOPS is not set -# CONFIG_TEST_VMALLOC is not set -# CONFIG_TEST_USER_COPY is not set -# CONFIG_TEST_BPF is not set -# CONFIG_TEST_BLACKHOLE_DEV is not set -# CONFIG_FIND_BIT_BENCHMARK is not set -# CONFIG_TEST_FIRMWARE is not set -# CONFIG_TEST_SYSCTL is not set -# CONFIG_TEST_UDELAY is not set -# CONFIG_TEST_STATIC_KEYS is not set -# CONFIG_TEST_KMOD is not set -# CONFIG_TEST_MEMCAT_P is not set -# CONFIG_TEST_STACKINIT is not set -# CONFIG_TEST_MEMINIT is not set -# CONFIG_TEST_FREE_PAGES is not set -# CONFIG_MEMTEST is not set -# end of Kernel Testing and Coverage -# end of Kernel hacking diff --git a/config/sources/families/include/meson_common.inc b/config/sources/families/include/meson_common.inc index 21ac68402801..8c3f9cac3579 100644 --- a/config/sources/families/include/meson_common.inc +++ b/config/sources/families/include/meson_common.inc @@ -34,13 +34,6 @@ case $BOARD in esac case $BRANCH in - legacy) - - KERNELBRANCH="branch:linux-5.10.y" - KERNELPATCHDIR='meson-'$BRANCH - - ;; - current) KERNELBRANCH="branch:linux-5.15.y" diff --git a/patch/kernel/archive/meson-5.10/Revert-mmc-core-Set-HS-clock-speed-before-sending-HS-CMD13.patch b/patch/kernel/archive/meson-5.10/Revert-mmc-core-Set-HS-clock-speed-before-sending-HS-CMD13.patch deleted file mode 100644 index 2cde1c334531..000000000000 --- a/patch/kernel/archive/meson-5.10/Revert-mmc-core-Set-HS-clock-speed-before-sending-HS-CMD13.patch +++ /dev/null @@ -1,73 +0,0 @@ -Revert "mmc: core: Set HS clock speed before sending HS CMD13" - -This reverts commit 4bc31edebde51fcf8ad0794763b8679a7ecb5ec0. ---- - drivers/mmc/core/mmc.c | 23 ++++------------------- - 1 file changed, 4 insertions(+), 19 deletions(-) - -diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c -index efa95dc4fc4..e7ea45386c2 100644 ---- a/drivers/mmc/core/mmc.c -+++ b/drivers/mmc/core/mmc.c -@@ -1384,17 +1384,13 @@ static int mmc_select_hs400es(struct mmc_card *card) - goto out_err; - } - -- /* -- * Bump to HS timing and frequency. Some cards don't handle -- * SEND_STATUS reliably at the initial frequency. -- */ - mmc_set_timing(host, MMC_TIMING_MMC_HS); -- mmc_set_bus_speed(card); -- - err = mmc_switch_status(card, true); - if (err) - goto out_err; - -+ mmc_set_clock(host, card->ext_csd.hs_max_dtr); -+ - /* Switch card to DDR with strobe bit */ - val = EXT_CSD_DDR_BUS_WIDTH_8 | EXT_CSD_BUS_WIDTH_STROBE; - err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, -@@ -1452,7 +1448,7 @@ static int mmc_select_hs400es(struct mmc_card *card) - static int mmc_select_hs200(struct mmc_card *card) - { - struct mmc_host *host = card->host; -- unsigned int old_timing, old_signal_voltage, old_clock; -+ unsigned int old_timing, old_signal_voltage; - int err = -EINVAL; - u8 val; - -@@ -1483,17 +1479,8 @@ static int mmc_select_hs200(struct mmc_card *card) - false, true, MMC_CMD_RETRIES); - if (err) - goto err; -- -- /* -- * Bump to HS timing and frequency. Some cards don't handle -- * SEND_STATUS reliably at the initial frequency. -- * NB: We can't move to full (HS200) speeds until after we've -- * successfully switched over. -- */ - old_timing = host->ios.timing; -- old_clock = host->ios.clock; - mmc_set_timing(host, MMC_TIMING_MMC_HS200); -- mmc_set_clock(card->host, card->ext_csd.hs_max_dtr); - - /* - * For HS200, CRC errors are not a reliable way to know the -@@ -1506,10 +1493,8 @@ static int mmc_select_hs200(struct mmc_card *card) - * mmc_select_timing() assumes timing has not changed if - * it is a switch error. - */ -- if (err == -EBADMSG) { -- mmc_set_clock(host, old_clock); -+ if (err == -EBADMSG) - mmc_set_timing(host, old_timing); -- } - } - err: - if (err) { --- -2.25.1 - diff --git a/patch/kernel/archive/meson-5.10/board_odroidc1/dts-Enable-HDMI.patch b/patch/kernel/archive/meson-5.10/board_odroidc1/dts-Enable-HDMI.patch deleted file mode 100644 index 136765cd441c..000000000000 --- a/patch/kernel/archive/meson-5.10/board_odroidc1/dts-Enable-HDMI.patch +++ /dev/null @@ -1,57 +0,0 @@ -From e59c976f9dea2d6e010dd1a615565117a31f047a Mon Sep 17 00:00:00 2001 -From: Martin Blumenstingl -Date: Fri, 20 Mar 2020 15:17:51 +0100 -Subject: [PATCH 1/1] ARM: dts: meson8b: odroid-c1: enable HDMI for the - Odroid-C1 - WiP - -WiP - -Signed-off-by: Martin Blumenstingl ---- - arch/arm/boot/dts/meson8b-odroidc1.dts | 23 +++++++++++++++++++++++ - 1 file changed, 23 insertions(+) - -diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts -index 386dd44daba..af49a50a69a 100644 ---- a/arch/arm/boot/dts/meson8b-odroidc1.dts -+++ b/arch/arm/boot/dts/meson8b-odroidc1.dts -@@ -32,6 +32,17 @@ emmc_pwrseq: emmc-pwrseq { - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - -+ hdmi-connector { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_connector_in: endpoint { -+ remote-endpoint = <&hdmi_tx_tmds_out>; -+ }; -+ }; -+ }; -+ - leds { - compatible = "gpio-leds"; - blue { -@@ -298,6 +309,18 @@ usb-hub { - }; - }; - -+&hdmi_tx { -+ status = "okay"; -+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; -+ pinctrl-names = "default"; -+}; -+ -+&hdmi_tx_tmds_port { -+ hdmi_tx_tmds_out: endpoint { -+ remote-endpoint = <&hdmi_connector_in>; -+ }; -+}; -+ - &ir_receiver { - status = "okay"; - pinctrl-0 = <&ir_recv_pins>; --- -2.25.1 - diff --git a/patch/kernel/archive/meson-5.10/board_onecloud/0001-add-dts.patch b/patch/kernel/archive/meson-5.10/board_onecloud/0001-add-dts.patch deleted file mode 100644 index f3358e4bc9e2..000000000000 --- a/patch/kernel/archive/meson-5.10/board_onecloud/0001-add-dts.patch +++ /dev/null @@ -1,431 +0,0 @@ -Add dts - ---- - arch/arm/boot/dts/Makefile | 1 + - arch/arm/boot/dts/meson8b-onecloud.dts | 402 +++++++++++++++++++++++++ - 2 files changed, 403 insertions(+) - create mode 100644 arch/arm/boot/dts/meson8b-onecloud.dts - -diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile -index 7e8151681597..e8d5ca39d0c6 100644 ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -347,6 +347,7 @@ dtb-$(CONFIG_MACH_MESON8) += \ - meson8b-ec100.dtb \ - meson8b-mxq.dtb \ - meson8b-odroidc1.dtb \ -+ meson8b-onecloud.dtb \ - meson8m2-mxiii-plus.dtb - dtb-$(CONFIG_ARCH_MMP) += \ - pxa168-aspenite.dtb \ -diff --git a/arch/arm/boot/dts/meson8b-onecloud.dts b/arch/arm/boot/dts/meson8b-onecloud.dts -new file mode 100644 -index 000000000000..d517e45e22ba ---- /dev/null -+++ b/arch/arm/boot/dts/meson8b-onecloud.dts -@@ -0,0 +1,402 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+/* -+ * Author: hzyitc -+ */ -+ -+/dts-v1/; -+#include "meson8b.dtsi" -+#include -+#include -+ -+/ { -+ model = "Xunlei OneCloud"; -+ compatible = "xunlei,onecloud", "amlogic,meson8b"; -+ -+ aliases { -+ serial0 = &uart_AO; -+ mmc0 = &sd_card_slot; -+ mmc1 = &sdhc; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ memory { -+ device_type = "memory"; -+ reg = <0x40000000 0x40000000>; -+ }; -+ -+ emmc_pwrseq: emmc-pwrseq { -+ compatible = "mmc-pwrseq-emmc"; -+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; -+ }; -+ -+ button { -+ // compatible = "gpio-keys-polled"; -+ // poll-interval = <100>; -+ -+ compatible = "gpio-keys"; -+ -+ autorepeat; -+ -+ reset-button { -+ label = "reset"; -+ linux,code = ; -+ -+ // gpios = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_LOW>; -+ -+ interrupt-parent = <&gpio_intc>; -+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>; // GPIOAO 5 -+ }; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ red { -+ label = "onecloud:red:alive"; -+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>; -+ -+ default-state = "on"; -+ linux,default-trigger = "default-on"; -+ }; -+ -+ green { -+ label = "onecloud:green:alive"; -+ gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; -+ -+ default-state = "off"; -+ linux,default-trigger = "mmc1"; -+ }; -+ -+ blue { -+ label = "onecloud:blue:alive"; -+ gpios = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_HIGH>; -+ -+ default-state = "off"; -+ linux,default-trigger = "usb-host"; -+ }; -+ }; -+ -+ p12v: regulator-p12v { -+ compatible = "regulator-fixed"; -+ -+ regulator-name = "P12V"; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ }; -+ -+ vcc_5v: regulator-vcc-5v { -+ compatible = "regulator-fixed"; -+ -+ regulator-name = "VCC5V"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ -+ vin-supply = <&p12v>; -+ -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ vcc_3v3: regulator-vcc-3v3 { -+ compatible = "regulator-fixed"; -+ -+ regulator-name = "VCC3V3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ -+ vin-supply = <&p12v>; -+ -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ vcc_1v8: regulator-vcc-1v8 { -+ compatible = "regulator-fixed"; -+ -+ regulator-name = "VCC1V8"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ -+ vin-supply = <&p12v>; -+ -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ vcc_ddr: regulator-vcc-ddr { -+ compatible = "regulator-fixed"; -+ -+ regulator-name = "VCC_DDR"; -+ regulator-min-microvolt = <1500000>; -+ regulator-max-microvolt = <1500000>; -+ -+ vin-supply = <&vcc_3v3>; -+ -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ vcc_core: regulator-vcc-core { -+ compatible = "pwm-regulator"; -+ -+ regulator-name = "VCC_CORE"; -+ -+ // +---------------------------------------------------+ -+ // | The actual mapping in phyical | -+ // +------+--------+--------+--------+--------+--------+ -+ // | | 100% | 60% | 30% | 10% | 0% | -+ // +------+--------+--------+--------+--------+--------+ -+ // | V1.0 | 677mV | 857mV | 992mV | 1082mV | 1127mV | -+ // | V1.3 | 1116mV | 1121mV | 1125mV | 1128mV | 1129mV | -+ // +------+--------+--------+--------+--------+--------+ -+ // -+ // According to meson8b.dtsi, the CPU should be able to -+ // run at 504MHz with 870mV. But this regulator supplies -+ // not only CPU but also GPU. And according to the users' -+ // tests on V1.0, we need such higher voltages. -+ -+ pwms = <&pwm_cd 1 12001 0>; // PWM_D -+ pwm-dutycycle-range = <10 0>; -+ regulator-min-microvolt = <860000>; -+ regulator-max-microvolt = <1140000>; -+ -+ pwm-supply = <&p12v>; -+ -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+}; -+ -+&pwm_cd { -+ status = "okay"; -+ pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; -+ pinctrl-names = "default"; -+ clocks = <&xtal>, <&xtal>; -+ clock-names = "clkin0", "clkin1"; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vcc_core>; -+}; -+ -+&mali { -+ // commented to allow cpufreq tweaking -+ // mali-supply = <&vcc_core>; -+}; -+ -+&gpio { -+ gpio-line-names = -+ // 0-3 Bank GPIOX 0-3 -+ "7U1_PIN_18", "7U1_PIN_19", -+ "7U1_PIN_14", "7U1_PIN_15", -+ // 4-7 Bank GPIOX 4-7 -+ "7U1_PIN_27", "7U1_PIN_25", -+ "7U1_PIN_28", "7U1_PIN_26", -+ // 8 Bank GPIOX 8 -+ "R_RightOf_LED", -+ // 9 Bank GPIOX 9 -+ "7U1_PIN_16", -+ // 10 Bank GPIOX 10 -+ "", -+ // 11 Bank GPIOX 11 -+ "7U1_PIN_12", -+ // 12-16 Bank GPIOX 16-20 -+ "7U1_PIN_43", "7U1_PIN_42", -+ "7U1_PIN_41(Resistor)", "7U1_PIN_44", -+ "7U1_PIN_34", -+ // 17 Bank GPIOX 21 -+ "7U1_PIN_13", -+ -+ // 18 Bank GPIOY 0 -+ "Resistor_TopOf_LED", -+ // 19-20 Bank GPIOY 1-3 -+ "", "", -+ // 21-26 Bank GPIOY 6-11 -+ "", "", -+ "", "", -+ "", "", -+ // 27 Bank GPIOY 12 -+ "", -+ // 28-29 Bank GPIOY 13-14 -+ "Left_BottomOf_CPU", "Right_BottomOf_CPU", -+ -+ // 30 Bank GPIODV 9 -+ "VCCK_PWM (PWM_C)", -+ // 31-35 Bank GPIODV 24-28 -+ "I2CA_SDA", "I2CA_SCL", -+ "I2CB_SDA", "I2CB_SCL", -+ "VDDEE_PWM (PWM_D)", -+ // 36 Bank GPIODV 29 -+ "", -+ -+ // 37-39 Bank GPIOH 0-2 -+ "HDMI_HPD", "HDMI_I2C_SDA", "HDMI_I2C_SCL", -+ // 40-46 Bank GPIOH 3-9 -+ "ETH_PHY_INTR", "ETH_PHY_NRST", -+ "ETH_TXD1", "ETH_TXD0", -+ "ETH_TXD3", "ETH_TXD2", -+ "ETH_RGMII_TX_CLK", -+ -+ // 47-53 Bank CARD 0-6 -+ "SD_D1", "SD_D0", -+ "SD_CLK", "SD_CMD", -+ "SD_D3", "SD_D2", -+ "SD_CD", -+ -+ // 54-65 Bank BOOT 0-11 -+ "EMMC_D0", "EMMC_D1", -+ "EMMC_D2", "EMMC_D3", -+ "EMMC_D4", "EMMC_D5", -+ "EMMC_D6", "EMMC_D7", -+ "EMMC_CLK", "EMMC_RSTn", -+ "EMMC_CMD", "BOOT_SEL", -+ // 66-72 Bank BOOT 12-18 -+ "", "", -+ "", "", -+ "", "", -+ "", -+ -+ // 73-74 Bank DIF 0P 0N -+ "ETH_RXD1", "ETH_RXD0", -+ // 75-76 Bank DIF 1P 1N -+ "ETH_RX_DV", "RGMII_RX_CLK", -+ // 77-78 Bank DIF 2P 2N -+ "ETH_RXD3", "ETH_RXD2", -+ // 79-80 Bank DIF 3P 3N -+ "ETH_TXEN", "ETH_PHY_REF_CLK_25MOUT", -+ // 81-82 Bank DIF 4P 4N -+ "ETH_MDC", "ETH_MDIO"; -+}; -+ -+&gpio_ao { -+ gpio-line-names = -+ // 0-1 Band GPIOAO 0-1 -+ "UART TX", "UART RX", -+ // 2-4 Band GPIOAO 2-4 -+ "RED_LED", "GREEN_LED", "BLUE_LED", -+ // 5 Band GPIOAO 5 -+ "BUTTON", -+ // 6 Band GPIOAO 6 -+ "", -+ // 7 Band GPIOAO 7 -+ "IR_IN", -+ // 8 Band GPIOAO 8-13 -+ "", "", -+ "", "", -+ "", "", -+ -+ // 14 Band GPIO_BSD_EN -+ "", -+ // 15 GPIO_TEST_N -+ ""; -+}; -+ -+ðmac { -+ status = "okay"; -+ -+ pinctrl-0 = <ð_rgmii_pins>; -+ pinctrl-names = "default"; -+ -+ phy-handle = <ð_phy>; -+ phy-mode = "rgmii-id"; -+ -+ mdio { -+ compatible = "snps,dwmac-mdio"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ // Realtek RTL8211F (0x001cc916) -+ eth_phy: ethernet-phy@0 { -+ reg = <0>; -+ -+ reset-assert-us = <10000>; -+ reset-deassert-us = <80000>; -+ reset-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_LOW>; -+ -+ interrupt-parent = <&gpio_intc>; -+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>; // GPIOH 3 -+ }; -+ }; -+}; -+ -+&saradc { -+ status = "okay"; -+ vref-supply = <&vcc_1v8>; -+}; -+ -+// eMMC -+&sdhc { -+ status = "okay"; -+ -+ pinctrl-0 = <&sdxc_c_pins>; -+ pinctrl-names = "default"; -+ -+ bus-width = <8>; -+ max-frequency = <100000000>; -+ -+ disable-wp; -+ cap-mmc-highspeed; -+ mmc-hs200-1_8v; -+ no-sdio; -+ -+ mmc-pwrseq = <&emmc_pwrseq>; -+ -+ vmmc-supply = <&vcc_3v3>; -+ // vqmmc-supply = <&vcc_3v3>; -+}; -+ -+&sdio { -+ status = "okay"; -+ -+ pinctrl-0 = <&sd_b_pins>; -+ pinctrl-names = "default"; -+ -+ // SD card -+ sd_card_slot: slot@1 { -+ compatible = "mmc-slot"; -+ reg = <1>; -+ status = "okay"; -+ -+ bus-width = <4>; -+ no-sdio; -+ cap-mmc-highspeed; -+ cap-sd-highspeed; -+ disable-wp; -+ -+ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_LOW>; -+ -+ vmmc-supply = <&vcc_3v3>; -+ // vqmmc-supply = <&vcc_3v3>; -+ }; -+}; -+ -+&uart_AO { -+ status = "okay"; -+ pinctrl-0 = <&uart_ao_a_pins>; -+ pinctrl-names = "default"; -+}; -+ -+&usb0_phy { -+ status = "okay"; -+}; -+ -+&usb0 { -+ status = "okay"; -+}; -+ -+&usb1_phy { -+ status = "okay"; -+}; -+ -+&usb1 { -+ status = "okay"; -+}; -+ -+&ir_receiver { -+ status = "okay"; -+ pinctrl-0 = <&ir_recv_pins>; -+ pinctrl-names = "default"; -+}; --- -2.25.1 - diff --git a/patch/kernel/archive/meson-5.10/board_onecloud/0002-dts-Support-HDMI.patch b/patch/kernel/archive/meson-5.10/board_onecloud/0002-dts-Support-HDMI.patch deleted file mode 100644 index b901f6dd5a28..000000000000 --- a/patch/kernel/archive/meson-5.10/board_onecloud/0002-dts-Support-HDMI.patch +++ /dev/null @@ -1,92 +0,0 @@ -dts: Support HDMI - ---- - arch/arm/boot/dts/meson8b-onecloud.dts | 58 ++++++++++++++++++++++++++ - 1 file changed, 58 insertions(+) - -diff --git a/arch/arm/boot/dts/meson8b-onecloud.dts b/arch/arm/boot/dts/meson8b-onecloud.dts -index 050b2e65348..69fff33c496 100644 ---- a/arch/arm/boot/dts/meson8b-onecloud.dts -+++ b/arch/arm/boot/dts/meson8b-onecloud.dts -@@ -32,6 +32,48 @@ emmc_pwrseq: emmc-pwrseq { - reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; - }; - -+ hdmi-connector { -+ compatible = "hdmi-connector"; -+ type = "a"; -+ -+ port { -+ hdmi_connector_in: endpoint { -+ remote-endpoint = <&hdmi_tx_tmds_out>; -+ }; -+ }; -+ }; -+ -+ sound { -+ compatible = "amlogic,gx-sound-card"; -+ -+ assigned-clocks = <&clkc CLKID_MPLL0>, -+ <&clkc CLKID_MPLL1>; -+ assigned-clock-rates = <294912000>, -+ <270950400>; -+ -+ dai-link-0 { -+ sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; -+ }; -+ -+ dai-link-1 { -+ sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; -+ dai-format = "i2s"; -+ mclk-fs = <256>; -+ -+ codec-0 { -+ sound-dai = <&aiu AIU_HDMI CTRL_I2S>; -+ }; -+ }; -+ -+ dai-link-2 { -+ sound-dai = <&aiu AIU_HDMI CTRL_OUT>; -+ -+ codec-0 { -+ sound-dai = <&hdmi_tx 0>; -+ }; -+ }; -+ }; -+ - button { - // compatible = "gpio-keys-polled"; - // poll-interval = <100>; -@@ -142,6 +184,10 @@ vcc_core: regulator-vcc-core { - }; - }; - -+&aiu { -+ status = "okay"; -+}; -+ - &cpu0 { - cpu-supply = <&vcc_core>; - }; -@@ -150,6 +196,18 @@ &mali { - mali-supply = <&vcc_core>; - }; - -+&hdmi_tx { -+ status = "okay"; -+ pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; -+ pinctrl-names = "default"; -+}; -+ -+&hdmi_tx_tmds_port { -+ hdmi_tx_tmds_out: endpoint { -+ remote-endpoint = <&hdmi_connector_in>; -+ }; -+}; -+ - &gpio { - gpio-line-names = - // 0-3 Bank GPIOX 0-3 --- -2.25.1 - diff --git a/patch/kernel/archive/meson-5.10/board_onecloud/usb-disable-ACA-check.patch b/patch/kernel/archive/meson-5.10/board_onecloud/usb-disable-ACA-check.patch deleted file mode 100644 index df0dcf656ce4..000000000000 --- a/patch/kernel/archive/meson-5.10/board_onecloud/usb-disable-ACA-check.patch +++ /dev/null @@ -1,32 +0,0 @@ -USB: Disable ACA check - -In V1.3, USB0 fails in this check. -But it can work normally. -So just disable this check. - ---- - drivers/phy/amlogic/phy-meson8b-usb2.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/phy/amlogic/phy-meson8b-usb2.c b/drivers/phy/amlogic/phy-meson8b-usb2.c -index 8f40b9342a97..24b685bded97 100644 ---- a/drivers/phy/amlogic/phy-meson8b-usb2.c -+++ b/drivers/phy/amlogic/phy-meson8b-usb2.c -@@ -195,12 +195,12 @@ static int phy_meson8b_usb2_power_on(struct phy *phy) - udelay(ACA_ENABLE_COMPLETE_TIME); - - regmap_read(priv->regmap, REG_ADP_BC, ®); -- if (reg & REG_ADP_BC_ACA_PIN_FLOAT) { -+ /*if (reg & REG_ADP_BC_ACA_PIN_FLOAT) { - dev_warn(&phy->dev, "USB ID detect failed!\n"); - clk_disable_unprepare(priv->clk_usb); - clk_disable_unprepare(priv->clk_usb_general); - return -EINVAL; -- } -+ }*/ - } - } - --- -2.25.1 - diff --git a/patch/kernel/archive/meson-5.10/generate-uImage-instand-of-zImage.patch b/patch/kernel/archive/meson-5.10/generate-uImage-instand-of-zImage.patch deleted file mode 100644 index 085dd2ff6726..000000000000 --- a/patch/kernel/archive/meson-5.10/generate-uImage-instand-of-zImage.patch +++ /dev/null @@ -1,27 +0,0 @@ -Generate uImage instand of zImage - ---- - scripts/package/builddeb | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/scripts/package/builddeb b/scripts/package/builddeb -index 91a502bb9..196889f1d 100755 ---- a/scripts/package/builddeb -+++ b/scripts/package/builddeb -@@ -218,6 +218,13 @@ if [ "$ARCH" != "um" ]; then - create_package linux-libc-dev debian/linux-libc-dev - fi - -+sed -e "s/exit 0//g" -i $tmpdir/DEBIAN/postinst -+cat >> $tmpdir/DEBIAN/postinst < /dev/null 2>&1 -+rm -f /boot/zImage -+exit 0 -+EOT -+ - create_package "$packagename" "$tmpdir" - - if [ -n "$BUILD_DEBUG" ] ; then --- -2.25.1 - diff --git a/patch/kernel/archive/meson-5.10/m8-m8b-m8m2-Support-HDMI.patch b/patch/kernel/archive/meson-5.10/m8-m8b-m8m2-Support-HDMI.patch deleted file mode 100644 index 4220bc103249..000000000000 --- a/patch/kernel/archive/meson-5.10/m8-m8b-m8m2-Support-HDMI.patch +++ /dev/null @@ -1,5177 +0,0 @@ -meson8/meson8b/meson8m2: Support HDMI - -The following codes are come from https://github.com/xdarklight/linux/commits/meson-mx-integration-5.11-20210124. - -Special thank. - ---- - arch/arm/boot/dts/meson.dtsi | 11 + - arch/arm/boot/dts/meson8.dtsi | 166 +- - arch/arm/boot/dts/meson8b.dtsi | 163 ++ - arch/arm/boot/dts/meson8m2.dtsi | 4 + - drivers/clk/meson/meson8b.c | 177 +- - drivers/clk/meson/meson8b.h | 22 +- - drivers/gpu/drm/bridge/Kconfig | 2 + - drivers/gpu/drm/bridge/Makefile | 1 + - drivers/gpu/drm/bridge/transwitch/Kconfig | 8 + - drivers/gpu/drm/bridge/transwitch/Makefile | 2 + - .../drm/bridge/transwitch/txccq-txc-48352.c | 1598 +++++++++++++++++ - .../drm/bridge/transwitch/txccq-txc-48352.h | 537 ++++++ - drivers/gpu/drm/meson/Kconfig | 7 + - drivers/gpu/drm/meson/Makefile | 1 + - drivers/gpu/drm/meson/meson_drv.c | 316 +++- - drivers/gpu/drm/meson/meson_drv.h | 41 +- - drivers/gpu/drm/meson/meson_dw_hdmi.c | 79 +- - drivers/gpu/drm/meson/meson_mx_hdmi.c | 432 +++++ - drivers/gpu/drm/meson/meson_osd_afbcd.c | 41 +- - drivers/gpu/drm/meson/meson_osd_afbcd.h | 1 - - drivers/gpu/drm/meson/meson_plane.c | 33 +- - drivers/gpu/drm/meson/meson_registers.h | 5 - - drivers/gpu/drm/meson/meson_vclk.c | 100 +- - drivers/gpu/drm/meson/meson_venc.c | 64 +- - drivers/gpu/drm/meson/meson_venc.h | 4 + - drivers/gpu/drm/meson/meson_venc_cvbs.c | 17 +- - drivers/gpu/drm/meson/meson_viu.c | 45 +- - drivers/phy/amlogic/Kconfig | 11 + - drivers/phy/amlogic/Makefile | 1 + - drivers/phy/amlogic/phy-meson8-hdmi-tx.c | 150 ++ - include/drm/bridge/txccq_txc_48352.h | 16 + - include/dt-bindings/clock/meson8b-clkc.h | 7 + - 32 files changed, 3803 insertions(+), 259 deletions(-) - create mode 100644 drivers/gpu/drm/bridge/transwitch/Kconfig - create mode 100644 drivers/gpu/drm/bridge/transwitch/Makefile - create mode 100644 drivers/gpu/drm/bridge/transwitch/txccq-txc-48352.c - create mode 100644 drivers/gpu/drm/bridge/transwitch/txccq-txc-48352.h - create mode 100644 drivers/gpu/drm/meson/meson_mx_hdmi.c - create mode 100644 drivers/phy/amlogic/phy-meson8-hdmi-tx.c - create mode 100644 include/drm/bridge/txccq_txc_48352.h - -diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi -index c928ae312..6fa8c89e1 100644 ---- a/arch/arm/boot/dts/meson.dtsi -+++ b/arch/arm/boot/dts/meson.dtsi -@@ -5,6 +5,7 @@ - - #include - #include -+#include - - / { - #address-cells = <1>; -@@ -31,6 +32,16 @@ hhi: system-controller@4000 { - reg = <0x4000 0x400>; - }; - -+ aiu: audio-controller@5400 { -+ compatible = "amlogic,aiu"; -+ #sound-dai-cells = <2>; -+ reg = <0x5400 0x2ac>; -+ interrupts = , -+ ; -+ interrupt-names = "i2s", "spdif"; -+ status = "disabled"; -+ }; -+ - assist: assist@7c00 { - compatible = "amlogic,meson-mx-assist", "syscon"; - reg = <0x7c00 0x200>; -diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi -index 08533116a..b1f6a3406 100644 ---- a/arch/arm/boot/dts/meson8.dtsi -+++ b/arch/arm/boot/dts/meson8.dtsi -@@ -255,14 +255,131 @@ mali: gpu@c0000 { - clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; - clock-names = "bus", "core"; - -- assigned-clocks = <&clkc CLKID_MALI>; -- assigned-clock-rates = <318750000>; -- - operating-points-v2 = <&gpu_opp_table>; - }; -+ -+ hdmi_tx: hdmi-tx@42000 { -+ compatible = "amlogic,meson8-hdmi-tx"; -+ reg = <0x42000 0xc>; -+ interrupts = ; -+ phys = <&hdmi_tx_phy>; -+ phy-names = "hdmi"; -+ clocks = <&clkc CLKID_HDMI_PCLK>, -+ <&clkc CLKID_HDMI_SYS>; -+ clock-names = "pclk", "sys"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ #sound-dai-cells = <0>; -+ sound-name-prefix = "HDMITX"; -+ -+ status = "disabled"; -+ -+ /* VPU VENC Input */ -+ hdmi_tx_venc_port: port@0 { -+ reg = <0>; -+ -+ hdmi_tx_in: endpoint { -+ remote-endpoint = <&hdmi_tx_out>; -+ }; -+ }; -+ -+ /* TMDS Output */ -+ hdmi_tx_tmds_port: port@1 { -+ reg = <1>; -+ }; -+ }; -+ -+ vpu: vpu@100000 { -+ compatible = "amlogic,meson8-vpu"; -+ -+ reg = <0x100000 0x10000>; -+ reg-names = "vpu"; -+ -+ interrupts = ; -+ -+ amlogic,canvas = <&canvas>; -+ amlogic,hhi-sysctrl = <&hhi>; -+ -+ clocks = <&clkc CLKID_VPU_INTR>, -+ <&clkc CLKID_HDMI_INTR_SYNC>, -+ <&clkc CLKID_GCLK_VENCI_INT>, -+ <&clkc CLKID_HDMI_PLL_HDMI_OUT>, -+ <&clkc CLKID_HDMI_TX_PIXEL>, -+ <&clkc CLKID_CTS_ENCP>, -+ <&clkc CLKID_CTS_ENCI>, -+ <&clkc CLKID_CTS_ENCT>, -+ <&clkc CLKID_CTS_ENCL>, -+ <&clkc CLKID_CTS_VDAC0>; -+ clock-names = "vpu_intr", -+ "hdmi_intr_sync", -+ "venci_int", -+ "tmds", -+ "hdmi_tx_pixel", -+ "cts_encp", -+ "cts_enci", -+ "cts_enct", -+ "cts_encl", -+ "cts_vdac0"; -+ -+ resets = <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE>, -+ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST>, -+ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE>, -+ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST>; -+ reset-names = "vid_pll_pre", -+ "vid_pll_post", -+ "vid_pll_soft_pre", -+ "vid_pll_soft_post"; -+ -+ power-domains = <&pwrc PWRC_MESON8_VPU_ID>; -+ -+ nvmem-cells = <&cvbs_trimming>; -+ nvmem-cell-names = "cvbs_trimming"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* CVBS VDAC output port */ -+ cvbs_vdac_port: port@0 { -+ reg = <0>; -+ }; -+ -+ /* HDMI-TX output port */ -+ hdmi_tx_port: port@1 { -+ reg = <1>; -+ -+ hdmi_tx_out: endpoint { -+ remote-endpoint = <&hdmi_tx_in>; -+ }; -+ }; -+ }; - }; - }; /* end of / */ - -+&aiu { -+ compatible = "amlogic,aiu-meson8", "amlogic,aiu"; -+ clocks = <&clkc CLKID_AIU_GLUE>, -+ <&clkc CLKID_I2S_OUT>, -+ <&clkc CLKID_AOCLK_GATE>, -+ <&clkc CLKID_CTS_AMCLK>, -+ <&clkc CLKID_MIXER_IFACE>, -+ <&clkc CLKID_IEC958>, -+ <&clkc CLKID_IEC958_GATE>, -+ <&clkc CLKID_CTS_MCLK_I958>, -+ <&clkc CLKID_CTS_I958>; -+ clock-names = "pclk", -+ "i2s_pclk", -+ "i2s_aoclk", -+ "i2s_mclk", -+ "i2s_mixer", -+ "spdif_pclk", -+ "spdif_aoclk", -+ "spdif_mclk", -+ "spdif_mclk_sel"; -+ resets = <&reset RESET_AIU>; -+}; -+ - &aobus { - pmu: pmu@e0 { - compatible = "amlogic,meson8-pmu", "syscon"; -@@ -286,6 +403,14 @@ gpio_ao: ao-bank@14 { - gpio-ranges = <&pinctrl_aobus 0 0 16>; - }; - -+ hdmi_cec_ao_pins: hdmi-cec-ao { -+ mux { -+ groups = "hdmi_cec_ao"; -+ function = "hdmi_cec_ao"; -+ bias-pull-up; -+ }; -+ }; -+ - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a"; -@@ -318,6 +443,15 @@ mux { - }; - }; - }; -+ -+ cec_AO: cec@100 { -+ compatible = "amlogic,meson-gx-ao-cec"; // FIXME -+ reg = <0x100 0x14>; -+ interrupts = ; -+ // TODO: 32768HZ clock -+ hdmi-phandle = <&hdmi_tx>; -+ status = "disabled"; -+ }; - }; - - &cbus { -@@ -362,6 +496,22 @@ gpio: banks@80b0 { - gpio-ranges = <&pinctrl_cbus 0 0 120>; - }; - -+ hdmi_hpd_pins: hdmi-hpd { -+ mux { -+ groups = "hdmi_hpd"; -+ function = "hdmi"; -+ bias-disable; -+ }; -+ }; -+ -+ hdmi_i2c_pins: hdmi-i2c { -+ mux { -+ groups = "hdmi_sda", "hdmi_scl"; -+ function = "hdmi"; -+ bias-disable; -+ }; -+ }; -+ - sd_a_pins: sd-a { - mux { - groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", -@@ -462,6 +612,10 @@ temperature_calib: calib@1f4 { - /* only the upper two bytes are relevant */ - reg = <0x1f4 0x4>; - }; -+ -+ cvbs_trimming: calib@1f8 { -+ reg = <0x1f8 0x2>; -+ }; - }; - - ðmac { -@@ -485,6 +639,12 @@ clkc: clock-controller { - #reset-cells = <1>; - }; - -+ hdmi_tx_phy: phy { -+ compatible = "amlogic,meson8-hdmi-tx-phy"; -+ clocks = <&clkc CLKID_HDMI_PLL_HDMI_OUT>; -+ #phy-cells = <0>; -+ }; -+ - pwrc: power-controller { - compatible = "amlogic,meson8-pwrc"; - #power-domain-cells = <1>; -diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi -index f6eb7c803..9fc8823b2 100644 ---- a/arch/arm/boot/dts/meson8b.dtsi -+++ b/arch/arm/boot/dts/meson8b.dtsi -@@ -222,9 +222,129 @@ mali: gpu@c0000 { - clock-names = "bus", "core"; - operating-points-v2 = <&gpu_opp_table>; - }; -+ -+ hdmi_tx: hdmi-tx@42000 { -+ compatible = "amlogic,meson8b-hdmi-tx"; -+ reg = <0x42000 0xc>; -+ interrupts = ; -+ phys = <&hdmi_tx_phy>; -+ phy-names = "hdmi"; -+ clocks = <&clkc CLKID_HDMI_PCLK>, -+ <&clkc CLKID_HDMI_SYS>; -+ clock-names = "pclk", "sys"; -+ sound-name-prefix = "HDMITX"; -+ #sound-dai-cells = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ /* VPU VENC Input */ -+ hdmi_tx_venc_port: port@0 { -+ reg = <0>; -+ -+ hdmi_tx_in: endpoint { -+ remote-endpoint = <&hdmi_tx_out>; -+ }; -+ }; -+ -+ /* TMDS Output */ -+ hdmi_tx_tmds_port: port@1 { -+ reg = <1>; -+ }; -+ }; -+ -+ vpu: vpu@100000 { -+ compatible = "amlogic,meson8b-vpu"; -+ -+ reg = <0x100000 0x10000>; -+ reg-names = "vpu"; -+ -+ interrupts = ; -+ -+ amlogic,canvas = <&canvas>; -+ amlogic,hhi-sysctrl = <&hhi>; -+ -+ clocks = <&clkc CLKID_VPU_INTR>, -+ <&clkc CLKID_HDMI_INTR_SYNC>, -+ <&clkc CLKID_GCLK_VENCI_INT>, -+ <&clkc CLKID_HDMI_PLL_HDMI_OUT>, -+ <&clkc CLKID_HDMI_TX_PIXEL>, -+ <&clkc CLKID_CTS_ENCP>, -+ <&clkc CLKID_CTS_ENCI>, -+ <&clkc CLKID_CTS_ENCT>, -+ <&clkc CLKID_CTS_ENCL>, -+ <&clkc CLKID_CTS_VDAC0>; -+ clock-names = "vpu_intr", -+ "hdmi_intr_sync", -+ "venci_int", -+ "tmds", -+ "hdmi_tx_pixel", -+ "cts_encp", -+ "cts_enci", -+ "cts_enct", -+ "cts_encl", -+ "cts_vdac0"; -+ -+ resets = <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE>, -+ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST>, -+ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE>, -+ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST>; -+ reset-names = "vid_pll_pre", -+ "vid_pll_post", -+ "vid_pll_soft_pre", -+ "vid_pll_soft_post"; -+ -+ power-domains = <&pwrc PWRC_MESON8_VPU_ID>; -+ -+ nvmem-cells = <&cvbs_trimming>; -+ nvmem-cell-names = "cvbs_trimming"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ #sound-dai-cells = <0>; -+ sound-name-prefix = "HDMITX"; -+ -+ /* CVBS VDAC output port */ -+ cvbs_vdac_port: port@0 { -+ reg = <0>; -+ }; -+ -+ /* HDMI-TX output port */ -+ hdmi_tx_port: port@1 { -+ reg = <1>; -+ -+ hdmi_tx_out: endpoint { -+ remote-endpoint = <&hdmi_tx_in>; -+ }; -+ }; -+ }; - }; - }; /* end of / */ - -+&aiu { -+ compatible = "amlogic,aiu-meson8b", "amlogic,aiu"; -+ clocks = <&clkc CLKID_AIU_GLUE>, -+ <&clkc CLKID_I2S_OUT>, -+ <&clkc CLKID_AOCLK_GATE>, -+ <&clkc CLKID_CTS_AMCLK>, -+ <&clkc CLKID_MIXER_IFACE>, -+ <&clkc CLKID_IEC958>, -+ <&clkc CLKID_IEC958_GATE>, -+ <&clkc CLKID_CTS_MCLK_I958>, -+ <&clkc CLKID_CTS_I958>; -+ clock-names = "pclk", -+ "i2s_pclk", -+ "i2s_aoclk", -+ "i2s_mclk", -+ "i2s_mixer", -+ "spdif_pclk", -+ "spdif_aoclk", -+ "spdif_mclk", -+ "spdif_mclk_sel"; -+ resets = <&reset RESET_AIU>; -+}; -+ - &aobus { - pmu: pmu@e0 { - compatible = "amlogic,meson8b-pmu", "syscon"; -@@ -248,6 +368,14 @@ gpio_ao: ao-bank@14 { - gpio-ranges = <&pinctrl_aobus 0 0 16>; - }; - -+ hdmi_cec_ao_pins: hdmi-cec-ao { -+ mux { -+ groups = "hdmi_cec_1"; -+ function = "hdmi_cec"; -+ bias-pull-up; -+ }; -+ }; -+ - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a"; -@@ -264,6 +392,15 @@ mux { - }; - }; - }; -+ -+ cec_AO: cec@100 { -+ compatible = "amlogic,meson-gx-ao-cec"; // FIXME -+ reg = <0x100 0x14>; -+ interrupts = ; -+ // TODO: 32768HZ clock -+ hdmi-phandle = <&hdmi_tx>; -+ status = "disabled"; -+ }; - }; - - &cbus { -@@ -346,6 +483,22 @@ mux { - }; - }; - -+ hdmi_hpd_pins: hdmi-hpd { -+ mux { -+ groups = "hdmi_hpd"; -+ function = "hdmi"; -+ bias-disable; -+ }; -+ }; -+ -+ hdmi_i2c_pins: hdmi-i2c { -+ mux { -+ groups = "hdmi_sda", "hdmi_scl"; -+ function = "hdmi"; -+ bias-disable; -+ }; -+ }; -+ - i2c_a_pins: i2c-a { - mux { - groups = "i2c_sda_a", "i2c_sck_a"; -@@ -426,6 +579,10 @@ temperature_calib: calib@1f4 { - /* only the upper two bytes are relevant */ - reg = <0x1f4 0x4>; - }; -+ -+ cvbs_trimming: calib@1f8 { -+ reg = <0x1f8 0x2>; -+ }; - }; - - ðmac { -@@ -463,6 +620,12 @@ clkc: clock-controller { - #reset-cells = <1>; - }; - -+ hdmi_tx_phy: phy { -+ compatible = "amlogic,meson8b-hdmi-tx-phy"; -+ clocks = <&clkc CLKID_HDMI_PLL_HDMI_OUT>; -+ #phy-cells = <0>; -+ }; -+ - pwrc: power-controller { - compatible = "amlogic,meson8b-pwrc"; - #power-domain-cells = <1>; -diff --git a/arch/arm/boot/dts/meson8m2.dtsi b/arch/arm/boot/dts/meson8m2.dtsi -index 6725dd9fd..fcb2ad976 100644 ---- a/arch/arm/boot/dts/meson8m2.dtsi -+++ b/arch/arm/boot/dts/meson8m2.dtsi -@@ -96,6 +96,10 @@ &usb1_phy { - compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; - }; - -+&vpu { -+ compatible = "amlogic,meson8m2-vpu"; -+}; -+ - &wdt { - compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt"; - }; -diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c -index 862f0756b..98aaf028f 100644 ---- a/drivers/clk/meson/meson8b.c -+++ b/drivers/clk/meson/meson8b.c -@@ -127,6 +127,36 @@ static struct clk_regmap meson8b_fixed_pll = { - }, - }; - -+static const struct reg_sequence meson8b_hdmi_pll_init_regs[] = { -+ { .reg = HHI_VID_PLL_CNTL2, .def = 0x59c88000 }, -+ { .reg = HHI_VID_PLL_CNTL3, .def = 0xca49b022 }, -+ { .reg = HHI_VID_PLL_CNTL4, .def = 0x0023b100 }, -+ { .reg = HHI_VID_PLL_CNTL5, .def = 0x00016385 }, -+ { .reg = HHI_VID2_PLL_CNTL2, .def = 0x0430a800 }, -+}; -+ -+static const struct pll_params_table hdmi_pll_params_table[] = { -+ PLL_PARAMS(34, 1), -+ PLL_PARAMS(40, 1), -+ PLL_PARAMS(42, 1), -+ PLL_PARAMS(44, 1), -+ PLL_PARAMS(45, 1), -+ PLL_PARAMS(49, 1), -+ PLL_PARAMS(52, 1), -+ PLL_PARAMS(54, 1), -+ PLL_PARAMS(56, 1), -+ PLL_PARAMS(59, 1), -+ PLL_PARAMS(60, 1), -+ PLL_PARAMS(61, 1), -+ PLL_PARAMS(62, 1), -+ PLL_PARAMS(64, 1), -+ PLL_PARAMS(66, 1), -+ PLL_PARAMS(68, 1), -+ PLL_PARAMS(71, 1), -+ PLL_PARAMS(82, 1), -+ { /* sentinel */ } -+}; -+ - static struct clk_regmap meson8b_hdmi_pll_dco = { - .data = &(struct meson_clk_pll_data){ - .en = { -@@ -159,11 +189,14 @@ static struct clk_regmap meson8b_hdmi_pll_dco = { - .shift = 29, - .width = 1, - }, -+ .table = hdmi_pll_params_table, -+ .init_regs = meson8b_hdmi_pll_init_regs, -+ .init_count = ARRAY_SIZE(meson8b_hdmi_pll_init_regs), - }, - .hw.init = &(struct clk_init_data){ - /* sometimes also called "HPLL" or "HPLL PLL" */ - .name = "hdmi_pll_dco", -- .ops = &meson_clk_pll_ro_ops, -+ .ops = &meson_clk_pll_ops, - .parent_data = &(const struct clk_parent_data) { - .fw_name = "xtal", - .name = "xtal", -@@ -182,7 +215,7 @@ static struct clk_regmap meson8b_hdmi_pll_lvds_out = { - }, - .hw.init = &(struct clk_init_data){ - .name = "hdmi_pll_lvds_out", -- .ops = &clk_regmap_divider_ro_ops, -+ .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_hdmi_pll_dco.hw - }, -@@ -200,7 +233,7 @@ static struct clk_regmap meson8b_hdmi_pll_hdmi_out = { - }, - .hw.init = &(struct clk_init_data){ - .name = "hdmi_pll_hdmi_out", -- .ops = &clk_regmap_divider_ro_ops, -+ .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_hdmi_pll_dco.hw - }, -@@ -1054,6 +1087,23 @@ static struct clk_regmap meson8b_l2_dram_clk_gate = { - }, - }; - -+/* also called LVDS_CLK_EN */ -+static struct clk_regmap meson8b_vid_pll_lvds_en = { -+ .data = &(struct clk_regmap_gate_data){ -+ .offset = HHI_VID_DIVIDER_CNTL, -+ .bit_idx = 11, -+ }, -+ .hw.init = &(struct clk_init_data){ -+ .name = "vid_pll_lvds_en", -+ .ops = &clk_regmap_gate_ops, -+ .parent_hws = (const struct clk_hw *[]) { -+ &meson8b_hdmi_pll_lvds_out.hw -+ }, -+ .num_parents = 1, -+ .flags = CLK_SET_RATE_PARENT, -+ }, -+}; -+ - static struct clk_regmap meson8b_vid_pll_in_sel = { - .data = &(struct clk_regmap_mux_data){ - .offset = HHI_VID_DIVIDER_CNTL, -@@ -1062,7 +1112,7 @@ static struct clk_regmap meson8b_vid_pll_in_sel = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vid_pll_in_sel", -- .ops = &clk_regmap_mux_ro_ops, -+ .ops = &clk_regmap_mux_ops, - /* - * TODO: depending on the SoC there is also a second parent: - * Meson8: unknown -@@ -1070,7 +1120,7 @@ static struct clk_regmap meson8b_vid_pll_in_sel = { - * Meson8m2: vid2_pll - */ - .parent_hws = (const struct clk_hw *[]) { -- &meson8b_hdmi_pll_lvds_out.hw -+ &meson8b_vid_pll_lvds_en.hw - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, -@@ -1084,7 +1134,7 @@ static struct clk_regmap meson8b_vid_pll_in_en = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vid_pll_in_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vid_pll_in_sel.hw - }, -@@ -1093,15 +1143,23 @@ static struct clk_regmap meson8b_vid_pll_in_en = { - }, - }; - -+static const struct clk_div_table vid_pll_pre_div_table[] = { -+ { .val = 0, .div = 1 }, -+ { .val = 4, .div = 5 }, -+ { .val = 5, .div = 6 }, -+ { /* sentinel */ } -+}; -+ - static struct clk_regmap meson8b_vid_pll_pre_div = { - .data = &(struct clk_regmap_div_data){ - .offset = HHI_VID_DIVIDER_CNTL, - .shift = 4, - .width = 3, -+ .table = vid_pll_pre_div_table, - }, - .hw.init = &(struct clk_init_data){ - .name = "vid_pll_pre_div", -- .ops = &clk_regmap_divider_ro_ops, -+ .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vid_pll_in_en.hw - }, -@@ -1110,15 +1168,22 @@ static struct clk_regmap meson8b_vid_pll_pre_div = { - }, - }; - -+static const struct clk_div_table vid_pll_post_div_table[] = { -+ { .val = 0, .div = 1 }, -+ { .val = 1, .div = 2 }, -+ { /* sentinel */ } -+}; -+ - static struct clk_regmap meson8b_vid_pll_post_div = { - .data = &(struct clk_regmap_div_data){ - .offset = HHI_VID_DIVIDER_CNTL, - .shift = 12, - .width = 3, -+ .table = vid_pll_post_div_table, - }, - .hw.init = &(struct clk_init_data){ - .name = "vid_pll_post_div", -- .ops = &clk_regmap_divider_ro_ops, -+ .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vid_pll_pre_div.hw - }, -@@ -1135,7 +1200,7 @@ static struct clk_regmap meson8b_vid_pll = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vid_pll", -- .ops = &clk_regmap_mux_ro_ops, -+ .ops = &clk_regmap_mux_ops, - /* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */ - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vid_pll_pre_div.hw, -@@ -1146,15 +1211,23 @@ static struct clk_regmap meson8b_vid_pll = { - }, - }; - -+static const struct clk_div_table meson8b_vid_pll_final_div_table[] = { -+ { .val = 0, .div = 1 }, -+ { .val = 1, .div = 2 }, -+ { .val = 3, .div = 4 }, -+ { /* sentinel */ } -+}; -+ - static struct clk_regmap meson8b_vid_pll_final_div = { - .data = &(struct clk_regmap_div_data){ - .offset = HHI_VID_CLK_DIV, - .shift = 0, - .width = 8, -+ .table = meson8b_vid_pll_final_div_table, - }, - .hw.init = &(struct clk_init_data){ - .name = "vid_pll_final_div", -- .ops = &clk_regmap_divider_ro_ops, -+ .ops = &clk_regmap_divider_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vid_pll.hw - }, -@@ -1163,6 +1236,10 @@ static struct clk_regmap meson8b_vid_pll_final_div = { - }, - }; - -+/* -+ * parent 0x6 is meson8b_mpll1 but we don't use it here because it's reserved -+ * for the audio outputs. -+ */ - static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = { - &meson8b_vid_pll_final_div.hw, - &meson8b_fclk_div4.hw, -@@ -1170,7 +1247,6 @@ static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = { - &meson8b_fclk_div5.hw, - &meson8b_vid_pll_final_div.hw, - &meson8b_fclk_div7.hw, -- &meson8b_mpll1.hw, - }; - - static struct clk_regmap meson8b_vclk_in_sel = { -@@ -1181,7 +1257,7 @@ static struct clk_regmap meson8b_vclk_in_sel = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk_in_sel", -- .ops = &clk_regmap_mux_ro_ops, -+ .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vclk_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws), - .flags = CLK_SET_RATE_PARENT, -@@ -1195,7 +1271,7 @@ static struct clk_regmap meson8b_vclk_in_en = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk_in_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk_in_sel.hw - }, -@@ -1211,7 +1287,7 @@ static struct clk_regmap meson8b_vclk_en = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk_in_en.hw - }, -@@ -1227,7 +1303,7 @@ static struct clk_regmap meson8b_vclk_div1_gate = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk_div1_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk_en.hw - }, -@@ -1257,7 +1333,7 @@ static struct clk_regmap meson8b_vclk_div2_div_gate = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk_div2_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk_div2_div.hw - }, -@@ -1287,7 +1363,7 @@ static struct clk_regmap meson8b_vclk_div4_div_gate = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk_div4_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk_div4_div.hw - }, -@@ -1317,7 +1393,7 @@ static struct clk_regmap meson8b_vclk_div6_div_gate = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk_div6_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk_div6_div.hw - }, -@@ -1347,7 +1423,7 @@ static struct clk_regmap meson8b_vclk_div12_div_gate = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk_div12_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk_div12_div.hw - }, -@@ -1364,7 +1440,7 @@ static struct clk_regmap meson8b_vclk2_in_sel = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk2_in_sel", -- .ops = &clk_regmap_mux_ro_ops, -+ .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vclk_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws), - .flags = CLK_SET_RATE_PARENT, -@@ -1378,7 +1454,7 @@ static struct clk_regmap meson8b_vclk2_clk_in_en = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk2_in_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk2_in_sel.hw - }, -@@ -1394,7 +1470,7 @@ static struct clk_regmap meson8b_vclk2_clk_en = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk2_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk2_clk_in_en.hw - }, -@@ -1410,7 +1486,7 @@ static struct clk_regmap meson8b_vclk2_div1_gate = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk2_div1_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk2_clk_en.hw - }, -@@ -1440,7 +1516,7 @@ static struct clk_regmap meson8b_vclk2_div2_div_gate = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk2_div2_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk2_div2_div.hw - }, -@@ -1470,7 +1546,7 @@ static struct clk_regmap meson8b_vclk2_div4_div_gate = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk2_div4_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk2_div4_div.hw - }, -@@ -1500,7 +1576,7 @@ static struct clk_regmap meson8b_vclk2_div6_div_gate = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk2_div6_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk2_div6_div.hw - }, -@@ -1530,7 +1606,7 @@ static struct clk_regmap meson8b_vclk2_div12_div_gate = { - }, - .hw.init = &(struct clk_init_data){ - .name = "vclk2_div12_en", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_vclk2_div12_div.hw - }, -@@ -1555,7 +1631,7 @@ static struct clk_regmap meson8b_cts_enct_sel = { - }, - .hw.init = &(struct clk_init_data){ - .name = "cts_enct_sel", -- .ops = &clk_regmap_mux_ro_ops, -+ .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vclk_enc_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws), - .flags = CLK_SET_RATE_PARENT, -@@ -1569,7 +1645,7 @@ static struct clk_regmap meson8b_cts_enct = { - }, - .hw.init = &(struct clk_init_data){ - .name = "cts_enct", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_cts_enct_sel.hw - }, -@@ -1586,7 +1662,7 @@ static struct clk_regmap meson8b_cts_encp_sel = { - }, - .hw.init = &(struct clk_init_data){ - .name = "cts_encp_sel", -- .ops = &clk_regmap_mux_ro_ops, -+ .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vclk_enc_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws), - .flags = CLK_SET_RATE_PARENT, -@@ -1600,7 +1676,7 @@ static struct clk_regmap meson8b_cts_encp = { - }, - .hw.init = &(struct clk_init_data){ - .name = "cts_encp", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_cts_encp_sel.hw - }, -@@ -1617,7 +1693,7 @@ static struct clk_regmap meson8b_cts_enci_sel = { - }, - .hw.init = &(struct clk_init_data){ - .name = "cts_enci_sel", -- .ops = &clk_regmap_mux_ro_ops, -+ .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vclk_enc_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws), - .flags = CLK_SET_RATE_PARENT, -@@ -1631,7 +1707,7 @@ static struct clk_regmap meson8b_cts_enci = { - }, - .hw.init = &(struct clk_init_data){ - .name = "cts_enci", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_cts_enci_sel.hw - }, -@@ -1648,7 +1724,7 @@ static struct clk_regmap meson8b_hdmi_tx_pixel_sel = { - }, - .hw.init = &(struct clk_init_data){ - .name = "hdmi_tx_pixel_sel", -- .ops = &clk_regmap_mux_ro_ops, -+ .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vclk_enc_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws), - .flags = CLK_SET_RATE_PARENT, -@@ -1662,7 +1738,7 @@ static struct clk_regmap meson8b_hdmi_tx_pixel = { - }, - .hw.init = &(struct clk_init_data){ - .name = "hdmi_tx_pixel", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_hdmi_tx_pixel_sel.hw - }, -@@ -1687,7 +1763,7 @@ static struct clk_regmap meson8b_cts_encl_sel = { - }, - .hw.init = &(struct clk_init_data){ - .name = "cts_encl_sel", -- .ops = &clk_regmap_mux_ro_ops, -+ .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vclk2_enc_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws), - .flags = CLK_SET_RATE_PARENT, -@@ -1701,7 +1777,7 @@ static struct clk_regmap meson8b_cts_encl = { - }, - .hw.init = &(struct clk_init_data){ - .name = "cts_encl", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_cts_encl_sel.hw - }, -@@ -1718,7 +1794,7 @@ static struct clk_regmap meson8b_cts_vdac0_sel = { - }, - .hw.init = &(struct clk_init_data){ - .name = "cts_vdac0_sel", -- .ops = &clk_regmap_mux_ro_ops, -+ .ops = &clk_regmap_mux_ops, - .parent_hws = meson8b_vclk2_enc_mux_parent_hws, - .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws), - .flags = CLK_SET_RATE_PARENT, -@@ -1732,7 +1808,7 @@ static struct clk_regmap meson8b_cts_vdac0 = { - }, - .hw.init = &(struct clk_init_data){ - .name = "cts_vdac0", -- .ops = &clk_regmap_gate_ro_ops, -+ .ops = &clk_regmap_gate_ops, - .parent_hws = (const struct clk_hw *[]) { - &meson8b_cts_vdac0_sel.hw - }, -@@ -2915,6 +2991,7 @@ static struct clk_hw_onecell_data meson8_hw_onecell_data = { - [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw, - [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, - [CLKID_CTS_I958] = &meson8b_cts_i958.hw, -+ [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, - [CLK_NR_CLKS] = NULL, - }, - .num = CLK_NR_CLKS, -@@ -3133,6 +3210,7 @@ static struct clk_hw_onecell_data meson8b_hw_onecell_data = { - [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw, - [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, - [CLKID_CTS_I958] = &meson8b_cts_i958.hw, -+ [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, - [CLK_NR_CLKS] = NULL, - }, - .num = CLK_NR_CLKS, -@@ -3353,6 +3431,7 @@ static struct clk_hw_onecell_data meson8m2_hw_onecell_data = { - [CLKID_CTS_MCLK_I958_DIV] = &meson8b_cts_mclk_i958_div.hw, - [CLKID_CTS_MCLK_I958] = &meson8b_cts_mclk_i958.hw, - [CLKID_CTS_I958] = &meson8b_cts_i958.hw, -+ [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, - [CLK_NR_CLKS] = NULL, - }, - .num = CLK_NR_CLKS, -@@ -3551,6 +3630,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { - &meson8b_cts_mclk_i958_div, - &meson8b_cts_mclk_i958, - &meson8b_cts_i958, -+ &meson8b_vid_pll_lvds_en, - }; - - static const struct meson8b_clk_reset_line { -@@ -3743,18 +3823,8 @@ static void __init meson8b_clkc_init_common(struct device_node *np, - - map = syscon_node_to_regmap(of_get_parent(np)); - if (IS_ERR(map)) { -- pr_info("failed to get HHI regmap - Trying obsolete regs\n"); -- -- /* Generic clocks, PLLs and some of the reset-bits */ -- clk_base = of_iomap(np, 1); -- if (!clk_base) { -- pr_err("%s: Unable to map clk base\n", __func__); -- return; -- } -- -- map = regmap_init_mmio(NULL, clk_base, &clkc_regmap_config); -- if (IS_ERR(map)) -- return; -+ pr_err("failed to get HHI regmap - Trying obsolete regs\n"); -+ return; - } - - rstc = kzalloc(sizeof(*rstc), GFP_KERNEL); -@@ -3813,6 +3883,11 @@ static void __init meson8b_clkc_init_common(struct device_node *np, - return; - } - -+ /* The HDMI PLL VCO is limited to 1.2G~3.0GHz */ -+ clk_hw_set_rate_range(clk_hw_onecell_data->hws[CLKID_HDMI_PLL_DCO], -+ 1200 * 1000UL * 1000UL, -+ 3000 * 1000UL * 1000UL); -+ - ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, - clk_hw_onecell_data); - if (ret) -diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h -index b1a5074cf..8d1e9cb15 100644 ---- a/drivers/clk/meson/meson8b.h -+++ b/drivers/clk/meson/meson8b.h -@@ -51,6 +51,16 @@ - #define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */ - #define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ - #define HHI_VID_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ -+#define HHI_VID_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ -+#define HHI_VID_PLL_CNTL4 0x32c /* 0xcb offset in data sheet */ -+#define HHI_VID_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ -+#define HHI_VID_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */ -+#define HHI_VID2_PLL_CNTL 0x380 /* 0xe0 offset in data sheet */ -+#define HHI_VID2_PLL_CNTL2 0x384 /* 0xe1 offset in data sheet */ -+#define HHI_VID2_PLL_CNTL3 0x388 /* 0xe2 offset in data sheet */ -+#define HHI_VID2_PLL_CNTL4 0x38c /* 0xe3 offset in data sheet */ -+#define HHI_VID2_PLL_CNTL5 0x390 /* 0xe4 offset in data sheet */ -+#define HHI_VID2_PLL_CNTL6 0x394 /* 0xe5 offset in data sheet */ - - /* - * MPLL register offeset taken from the S905 datasheet. Vendor kernel source -@@ -107,8 +117,7 @@ - #define CLKID_PERIPH_SEL 125 - #define CLKID_AXI_SEL 127 - #define CLKID_L2_DRAM_SEL 129 --#define CLKID_HDMI_PLL_LVDS_OUT 131 --#define CLKID_HDMI_PLL_HDMI_OUT 132 -+#define CLKID_HDMI_PLL_LVDS_OUT 131 - #define CLKID_VID_PLL_IN_SEL 133 - #define CLKID_VID_PLL_IN_EN 134 - #define CLKID_VID_PLL_PRE_DIV 135 -@@ -137,17 +146,11 @@ - #define CLKID_VCLK2_DIV12_DIV 158 - #define CLKID_VCLK2_DIV12 159 - #define CLKID_CTS_ENCT_SEL 160 --#define CLKID_CTS_ENCT 161 - #define CLKID_CTS_ENCP_SEL 162 --#define CLKID_CTS_ENCP 163 - #define CLKID_CTS_ENCI_SEL 164 --#define CLKID_CTS_ENCI 165 - #define CLKID_HDMI_TX_PIXEL_SEL 166 --#define CLKID_HDMI_TX_PIXEL 167 - #define CLKID_CTS_ENCL_SEL 168 --#define CLKID_CTS_ENCL 169 - #define CLKID_CTS_VDAC0_SEL 170 --#define CLKID_CTS_VDAC0 171 - #define CLKID_HDMI_SYS_SEL 172 - #define CLKID_HDMI_SYS_DIV 173 - #define CLKID_MALI_0_SEL 175 -@@ -182,8 +185,9 @@ - #define CLKID_CTS_MCLK_I958_DIV 211 - #define CLKID_VCLK_EN 214 - #define CLKID_VCLK2_EN 215 -+#define CLKID_VID_PLL_LVDS_EN 216 - --#define CLK_NR_CLKS 216 -+#define CLK_NR_CLKS 222 - - /* - * include the CLKID and RESETID that have -diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig -index 4e82647a6..708d82d61 100644 ---- a/drivers/gpu/drm/bridge/Kconfig -+++ b/drivers/gpu/drm/bridge/Kconfig -@@ -248,4 +248,6 @@ source "drivers/gpu/drm/bridge/cadence/Kconfig" - - source "drivers/gpu/drm/bridge/synopsys/Kconfig" - -+source "drivers/gpu/drm/bridge/transwitch/Kconfig" -+ - endmenu -diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile -index 2b3aff104..6f3bb787c 100644 ---- a/drivers/gpu/drm/bridge/Makefile -+++ b/drivers/gpu/drm/bridge/Makefile -@@ -27,3 +27,4 @@ obj-$(CONFIG_DRM_NWL_MIPI_DSI) += nwl-dsi.o - obj-y += analogix/ - obj-y += cadence/ - obj-y += synopsys/ -+obj-y += transwitch/ -diff --git a/drivers/gpu/drm/bridge/transwitch/Kconfig b/drivers/gpu/drm/bridge/transwitch/Kconfig -new file mode 100644 -index 000000000..272084b0b ---- /dev/null -+++ b/drivers/gpu/drm/bridge/transwitch/Kconfig -@@ -0,0 +1,8 @@ -+# SPDX-License-Identifier: GPL-2.0-or-later -+config DRM_TRANSWITCH_TXC_48352 -+ tristate -+ depends on DRM -+ depends on REGMAP -+ depends on OF -+ select CEC_CORE if CEC_NOTIFIER -+ select SND_SOC_HDMI_CODEC if SND_SOC -diff --git a/drivers/gpu/drm/bridge/transwitch/Makefile b/drivers/gpu/drm/bridge/transwitch/Makefile -new file mode 100644 -index 000000000..ef98e79a5 ---- /dev/null -+++ b/drivers/gpu/drm/bridge/transwitch/Makefile -@@ -0,0 +1,2 @@ -+# SPDX-License-Identifier: GPL-2.0-or-later -+obj-$(CONFIG_DRM_TRANSWITCH_TXC_48352) += txccq-txc-48352.o -diff --git a/drivers/gpu/drm/bridge/transwitch/txccq-txc-48352.c b/drivers/gpu/drm/bridge/transwitch/txccq-txc-48352.c -new file mode 100644 -index 000000000..b2593a014 ---- /dev/null -+++ b/drivers/gpu/drm/bridge/transwitch/txccq-txc-48352.c -@@ -0,0 +1,1598 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2020 Martin Blumenstingl -+ * -+ * All registers and magic values are taken from Amlogic's GPL kernel sources: -+ * Copyright (C) 2010 Amlogic, Inc. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include -+ -+#include -+#include -+ -+#include "txccq-txc-48352.h" -+ -+struct txc_48352 { -+ struct device *dev; -+ int irq; -+ struct regmap *tx_regmap; -+ struct regmap *other_regmap; -+ struct clk *sys_clk; -+ struct phy *phy; -+ bool phy_is_on; -+ -+ struct mutex cec_notifier_mutex; -+ struct cec_notifier *cec_notifier; -+ -+ struct mutex codec_mutex; -+ hdmi_codec_plugged_cb codec_plugged_cb; -+ struct device *codec_dev; -+ -+ struct platform_device *hdmi_codec_pdev; -+ -+ struct drm_connector connector; -+ struct drm_bridge bridge; -+ -+ unsigned int intr_stat; -+ -+ int cea_mode; -+ enum hdmi_colorimetry colorimetry; -+ unsigned int input_bus_format; -+ unsigned int output_bus_format; -+ bool limited_rgb_quant_range; -+ bool sink_is_hdmi; -+ bool sink_has_audio; -+}; -+ -+#define to_txc_48352(x) container_of(x, struct txc_48352, x) -+ -+static void txc_48352_write_infoframe(struct regmap *regmap, -+ unsigned int tx_pkt_reg, u8 *buf, -+ unsigned int len, bool enable) -+{ -+ unsigned int i; -+ -+ /* write the payload starting register offset 1 and skip the header */ -+ for (i = HDMI_INFOFRAME_HEADER_SIZE; i < len; i++) -+ regmap_write(regmap, -+ tx_pkt_reg + i - HDMI_INFOFRAME_HEADER_SIZE + 1, -+ buf[i]); -+ -+ /* zero the remaining payload bytes */ -+ for (; i < 0x1c; i++) -+ regmap_write(regmap, tx_pkt_reg + i, 0x00); -+ -+ /* write the header */ -+ regmap_write(regmap, tx_pkt_reg + 0x00, buf[3]); -+ regmap_write(regmap, tx_pkt_reg + 0x1c, buf[0]); -+ regmap_write(regmap, tx_pkt_reg + 0x1d, buf[1]); -+ regmap_write(regmap, tx_pkt_reg + 0x1e, buf[2]); -+ -+ regmap_write(regmap, tx_pkt_reg + 0x1f, enable ? 0xff : 0x00); -+} -+ -+static void txc_48352_disable_infoframe(struct txc_48352 *priv, -+ unsigned int tx_pkt_reg) -+{ -+ u8 buf[HDMI_INFOFRAME_HEADER_SIZE] = { 0 }; -+ -+ txc_48352_write_infoframe(priv->tx_regmap, tx_pkt_reg, buf, -+ HDMI_INFOFRAME_HEADER_SIZE, false); -+} -+ -+static void txc_48352_sys5_reset_assert(struct txc_48352 *priv) -+{ -+ /* A comment in the vendor driver says: bit5,6 is converted */ -+ regmap_write(priv->tx_regmap, TX_SYS5_TX_SOFT_RESET_2, -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH3_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH0_RST_IN); -+ usleep_range(10, 20); -+ -+ regmap_write(priv->tx_regmap, TX_SYS5_TX_SOFT_RESET_2, -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN); -+ usleep_range(10, 20); -+ -+ regmap_write(priv->tx_regmap, TX_SYS5_TX_SOFT_RESET_1, -+ TX_SYS5_TX_SOFT_RESET_1_TX_PIXEL_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_TMDS_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_MASTER_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_RESAMPLE_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_I2S_RESET_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH2 | -+ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH1 | -+ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH0); -+ usleep_range(10, 20); -+} -+ -+static void txc_48352_sys5_reset_deassert(struct txc_48352 *priv) -+{ -+ /* Release the resets except tmds_clk */ -+ regmap_write(priv->tx_regmap, TX_SYS5_TX_SOFT_RESET_1, -+ TX_SYS5_TX_SOFT_RESET_1_TX_TMDS_RSTN); -+ usleep_range(10, 20); -+ -+ /* Release the tmds_clk reset as well */ -+ regmap_write(priv->tx_regmap, TX_SYS5_TX_SOFT_RESET_1, 0x0); -+ usleep_range(10, 20); -+ -+ regmap_write(priv->tx_regmap, TX_SYS5_TX_SOFT_RESET_2, -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_SR_RST); -+ usleep_range(10, 20); -+ -+ regmap_write(priv->tx_regmap, TX_SYS5_TX_SOFT_RESET_2, -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN); -+ usleep_range(10, 20); -+} -+ -+static void txc_48352_config_hdcp_registers(struct txc_48352 *priv) -+{ -+ regmap_write(priv->tx_regmap, TX_HDCP_CONFIG0, -+ FIELD_PREP(TX_HDCP_CONFIG0_ROM_ENCRYPT_OFF, 0x3)); -+ regmap_write(priv->tx_regmap, TX_HDCP_MEM_CONFIG, 0x0); -+ regmap_write(priv->tx_regmap, TX_HDCP_ENCRYPT_BYTE, 0x0); -+ -+ regmap_write(priv->tx_regmap, TX_HDCP_MODE, TX_HDCP_MODE_CLEAR_AVMUTE); -+ -+ regmap_write(priv->tx_regmap, TX_HDCP_MODE, TX_HDCP_MODE_ESS_CONFIG); -+} -+ -+static u8 txc_48352_bus_fmt_to_color_depth(unsigned int bus_format) -+{ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_RGB888_1X24: -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ case MEDIA_BUS_FMT_UYVY8_1X16: -+ /* 8 bit */ -+ return 0x0; -+ -+ case MEDIA_BUS_FMT_RGB101010_1X30: -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ case MEDIA_BUS_FMT_UYVY10_1X20: -+ /* 10 bit */ -+ return 0x1; -+ -+ case MEDIA_BUS_FMT_RGB121212_1X36: -+ case MEDIA_BUS_FMT_YUV12_1X36: -+ case MEDIA_BUS_FMT_UYVY12_1X24: -+ /* 12 bit */ -+ return 0x2; -+ -+ case MEDIA_BUS_FMT_RGB161616_1X48: -+ case MEDIA_BUS_FMT_YUV16_1X48: -+ /* 16 bit */ -+ return 0x3; -+ -+ default: -+ /* unknown, default to 8 bit */ -+ return 0x0; -+ } -+} -+ -+static enum hdmi_colorspace -+txc_48352_bus_fmt_hdmi_colorspace(unsigned int bus_format) -+{ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ case MEDIA_BUS_FMT_YUV12_1X36: -+ case MEDIA_BUS_FMT_YUV16_1X48: -+ return HDMI_COLORSPACE_YUV444; -+ -+ case MEDIA_BUS_FMT_UYVY8_1X16: -+ case MEDIA_BUS_FMT_UYVY10_1X20: -+ case MEDIA_BUS_FMT_UYVY12_1X24: -+ return HDMI_COLORSPACE_YUV422; -+ -+ case MEDIA_BUS_FMT_RGB888_1X24: -+ case MEDIA_BUS_FMT_RGB101010_1X30: -+ case MEDIA_BUS_FMT_RGB121212_1X36: -+ case MEDIA_BUS_FMT_RGB161616_1X48: -+ default: -+ return HDMI_COLORSPACE_RGB; -+ -+ } -+} -+ -+static u8 txc_48352_bus_fmt_to_color_format(unsigned int bus_format) -+{ -+ switch (txc_48352_bus_fmt_hdmi_colorspace(bus_format)) { -+ case HDMI_COLORSPACE_YUV422: -+ /* Documented as YCbCr422 */ -+ return 0x3; -+ -+ case HDMI_COLORSPACE_YUV444: -+ /* Documented as YCbCr444 */ -+ return 0x1; -+ -+ case HDMI_COLORSPACE_RGB: -+ default: -+ /* Documented as RGB444 */ -+ return 0x0; -+ } -+} -+ -+static void txc_48352_config_color_space(struct txc_48352 *priv) -+{ -+ unsigned int regval; -+ -+ regmap_write(priv->tx_regmap, TX_VIDEO_DTV_MODE, -+ FIELD_PREP(TX_VIDEO_DTV_MODE_COLOR_DEPTH, -+ txc_48352_bus_fmt_to_color_depth(priv->output_bus_format))); -+ -+ regmap_write(priv->tx_regmap, TX_VIDEO_DTV_OPTION_L, -+ FIELD_PREP(TX_VIDEO_DTV_OPTION_L_OUTPUT_COLOR_FORMAT, -+ txc_48352_bus_fmt_to_color_format(priv->output_bus_format)) | -+ FIELD_PREP(TX_VIDEO_DTV_OPTION_L_INPUT_COLOR_FORMAT, -+ txc_48352_bus_fmt_to_color_format(priv->input_bus_format)) | -+ FIELD_PREP(TX_VIDEO_DTV_OPTION_L_OUTPUT_COLOR_DEPTH, -+ txc_48352_bus_fmt_to_color_depth(priv->output_bus_format)) | -+ FIELD_PREP(TX_VIDEO_DTV_OPTION_L_INPUT_COLOR_DEPTH, -+ txc_48352_bus_fmt_to_color_depth(priv->input_bus_format))); -+ -+ if (priv->limited_rgb_quant_range) -+ regval = FIELD_PREP(TX_VIDEO_DTV_OPTION_H_OUTPUT_COLOR_RANGE, -+ TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_16_235) | -+ FIELD_PREP(TX_VIDEO_DTV_OPTION_H_INPUT_COLOR_RANGE, -+ TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_16_235); -+ else -+ regval = FIELD_PREP(TX_VIDEO_DTV_OPTION_H_OUTPUT_COLOR_RANGE, -+ TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_0_255) | -+ FIELD_PREP(TX_VIDEO_DTV_OPTION_H_INPUT_COLOR_RANGE, -+ TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_0_255); -+ -+ regmap_write(priv->tx_regmap, TX_VIDEO_DTV_OPTION_H, regval); -+ -+ if (priv->colorimetry == HDMI_COLORIMETRY_ITU_601) { -+ regmap_write(priv->tx_regmap, TX_VIDEO_CSC_COEFF_B0, 0x2f); -+ regmap_write(priv->tx_regmap, TX_VIDEO_CSC_COEFF_B1, 0x1d); -+ regmap_write(priv->tx_regmap, TX_VIDEO_CSC_COEFF_R0, 0x8b); -+ regmap_write(priv->tx_regmap, TX_VIDEO_CSC_COEFF_R1, 0x4c); -+ -+ regmap_write(priv->tx_regmap, TX_VIDEO_CSC_COEFF_CB0, 0x18); -+ regmap_write(priv->tx_regmap, TX_VIDEO_CSC_COEFF_CB1, 0x58); -+ regmap_write(priv->tx_regmap, TX_VIDEO_CSC_COEFF_CR0, 0xd0); -+ regmap_write(priv->tx_regmap, TX_VIDEO_CSC_COEFF_CR1, 0xb6); -+ } else { -+ regmap_write(priv->tx_regmap, TX_VIDEO_CSC_COEFF_B0, 0x7b); -+ regmap_write(priv->tx_regmap, TX_VIDEO_CSC_COEFF_B1, 0x12); -+ regmap_write(priv->tx_regmap, TX_VIDEO_CSC_COEFF_R0, 0x6c); -+ regmap_write(priv->tx_regmap, TX_VIDEO_CSC_COEFF_R1, 0x36); -+ -+ regmap_write(priv->tx_regmap, TX_VIDEO_CSC_COEFF_CB0, 0xf2); -+ regmap_write(priv->tx_regmap, TX_VIDEO_CSC_COEFF_CB1, 0x2f); -+ regmap_write(priv->tx_regmap, TX_VIDEO_CSC_COEFF_CR0, 0xd4); -+ regmap_write(priv->tx_regmap, TX_VIDEO_CSC_COEFF_CR1, 0x77); -+ } -+} -+ -+/* -+ * FIXME - questions for CDNS team: -+ * - what is the name of the 0x0018 register? -+ * - what do BIT(1), BIT(2), BIT(4) and BIT(5) mean? -+ * - if it's not clear from the names of these bits: when to set each of them? -+ * (below code depends on the HDMI_COLORIMETRY and one special case also on -+ * the color depth and a special HDMI VIC) -+ */ -+static void txc_48352_config_serializer_clock(struct txc_48352 *priv) -+{ -+ /* Serializer Internal clock setting */ -+ if (priv->colorimetry == HDMI_COLORIMETRY_ITU_601) -+ regmap_write(priv->tx_regmap, 0x0018, 0x24); -+ else -+ regmap_write(priv->tx_regmap, 0x0018, 0x22); -+ -+#if 0 -+ // TODO: not ported yet -+ if ((param->VIC==HDMI_1080p60)&&(param->color_depth==COLOR_30BIT)&&(hdmi_rd_reg(0x018)==0x22)) { -+ regmap_write(priv->tx_regmap, 0x0018,0x12); -+ } -+#endif -+} -+ -+static void txc_48352_reconfig_packet_setting(struct txc_48352 *priv) -+{ -+ u8 alloc_active2, alloc_eof1, alloc_sof1, alloc_sof2; -+ -+ regmap_write(priv->tx_regmap, TX_PACKET_CONTROL_1, -+ FIELD_PREP(TX_PACKET_CONTROL_1_PACKET_START_LATENCY, 58)); -+ regmap_write(priv->tx_regmap, TX_PACKET_CONTROL_2, -+ TX_PACKET_CONTROL_2_HORIZONTAL_GC_PACKET_TRANSPORT_EN); -+ -+ switch (priv->cea_mode) { -+ case 31: -+ /* 1920x1080p50 */ -+ alloc_active2 = 0x12; -+ alloc_eof1 = 0x10; -+ alloc_sof1 = 0xb6; -+ alloc_sof2 = 0x11; -+ break; -+ case 93: -+ /* 3840x2160p24 */ -+ alloc_active2 = 0x12; -+ alloc_eof1 = 0x47; -+ alloc_sof1 = 0xf8; -+ alloc_sof2 = 0x52; -+ break; -+ case 94: -+ /* 3840x2160p25 */ -+ alloc_active2 = 0x12; -+ alloc_eof1 = 0x44; -+ alloc_sof1 = 0xda; -+ alloc_sof2 = 0x52; -+ break; -+ case 95: -+ /* 3840x2160p30 */ -+ alloc_active2 = 0x0f; -+ alloc_eof1 = 0x3a; -+ alloc_sof1 = 0x60; -+ alloc_sof2 = 0x52; -+ break; -+ case 98: -+ /* 4096x2160p24 */ -+ alloc_active2 = 0x12; -+ alloc_eof1 = 0x47; -+ alloc_sof1 = 0xf8; -+ alloc_sof2 = 0x52; -+ break; -+ default: -+ /* Disable the special packet settings only */ -+ regmap_write(priv->tx_regmap, TX_PACKET_ALLOC_ACTIVE_1, 0x00); -+ return; -+ } -+ -+ /* -+ * The vendor driver says: manually configure these register to get -+ * stable video timings. -+ */ -+ regmap_write(priv->tx_regmap, TX_PACKET_ALLOC_ACTIVE_1, 0x01); -+ regmap_write(priv->tx_regmap, TX_PACKET_ALLOC_ACTIVE_2, alloc_active2); -+ regmap_write(priv->tx_regmap, TX_PACKET_ALLOC_EOF_1, alloc_eof1); -+ regmap_write(priv->tx_regmap, TX_PACKET_ALLOC_EOF_2, 0x12); -+ regmap_write(priv->tx_regmap, TX_CORE_ALLOC_VSYNC_0, 0x01); -+ regmap_write(priv->tx_regmap, TX_CORE_ALLOC_VSYNC_1, 0x00); -+ regmap_write(priv->tx_regmap, TX_CORE_ALLOC_VSYNC_2, 0x0a); -+ regmap_write(priv->tx_regmap, TX_PACKET_ALLOC_SOF_1, alloc_sof1); -+ regmap_write(priv->tx_regmap, TX_PACKET_ALLOC_SOF_2, alloc_sof2); -+ regmap_update_bits(priv->tx_regmap, TX_PACKET_CONTROL_1, -+ TX_PACKET_CONTROL_1_FORCE_PACKET_TIMING, -+ TX_PACKET_CONTROL_1_FORCE_PACKET_TIMING); -+} -+ -+static void txc_48352_set_avi_infoframe(struct txc_48352 *priv, -+ const struct drm_display_mode *mode) -+{ -+ u8 buf[HDMI_INFOFRAME_SIZE(AVI)], *video_code; -+ struct hdmi_avi_infoframe frame; -+ int ret; -+ -+ ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, -+ &priv->connector, mode); -+ if (ret < 0) { -+ drm_err(priv->bridge.dev, -+ "Failed to setup AVI infoframe: %d\n", ret); -+ return; -+ } -+ -+ /* fixed infoframe configuration not linked to the mode */ -+ frame.colorspace = -+ txc_48352_bus_fmt_hdmi_colorspace(priv->output_bus_format); -+ frame.colorimetry = priv->colorimetry; -+ -+ drm_hdmi_avi_infoframe_quant_range(&frame, -+ &priv->connector, mode, -+ priv->limited_rgb_quant_range ? -+ HDMI_QUANTIZATION_RANGE_LIMITED : -+ HDMI_QUANTIZATION_RANGE_FULL); -+ -+ ret = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf)); -+ if (ret < 0) { -+ drm_err(priv->bridge.dev, -+ "Failed to pack AVI infoframe: %d\n", ret); -+ return; -+ } -+ -+ video_code = &buf[HDMI_INFOFRAME_HEADER_SIZE + 3]; -+ if (*video_code > 109) { -+ regmap_write(priv->tx_regmap, TX_PKT_REG_EXCEPT0_BASE_ADDR, -+ *video_code); -+ *video_code = 0x00; -+ } else { -+ regmap_write(priv->tx_regmap, TX_PKT_REG_EXCEPT0_BASE_ADDR, 0x00); -+ } -+ -+ txc_48352_write_infoframe(priv->tx_regmap, -+ TX_PKT_REG_AVI_INFO_BASE_ADDR, buf, -+ sizeof(buf), true); -+} -+ -+static void txc_48352_set_vendor_infoframe(struct txc_48352 *priv, -+ const struct drm_display_mode *mode) -+{ -+ u8 buf[HDMI_INFOFRAME_HEADER_SIZE + 6]; -+ struct hdmi_vendor_infoframe frame; -+ int ret; -+ -+ ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame, -+ &priv->connector, -+ mode); -+ if (ret) { -+ drm_dbg(priv->bridge.dev, -+ "Failed to setup vendor infoframe: %d\n", ret); -+ return; -+ } -+ -+ ret = hdmi_vendor_infoframe_pack(&frame, buf, sizeof(buf)); -+ if (ret < 0) { -+ drm_err(priv->bridge.dev, -+ "Failed to pack vendor infoframe: %d\n", ret); -+ return; -+ } -+ -+ txc_48352_write_infoframe(priv->tx_regmap, -+ TX_PKT_REG_VEND_INFO_BASE_ADDR, buf, -+ sizeof(buf), true); -+} -+ -+static void txc_48352_set_spd_infoframe(struct txc_48352 *priv) -+{ -+ u8 buf[HDMI_INFOFRAME_SIZE(SPD)]; -+ struct hdmi_spd_infoframe frame; -+ int ret; -+ -+ ret = hdmi_spd_infoframe_init(&frame, "TXCCQ", "TXC-48352"); -+ if (ret < 0) { -+ drm_err(priv->bridge.dev, -+ "Failed to setup SPD infoframe: %d\n", ret); -+ return; -+ } -+ -+ ret = hdmi_spd_infoframe_pack(&frame, buf, sizeof(buf)); -+ if (ret < 0) { -+ drm_err(priv->bridge.dev, -+ "Failed to pack SDP infoframe: %d\n", ret); -+ return; -+ } -+ -+ txc_48352_write_infoframe(priv->tx_regmap, -+ TX_PKT_REG_SPD_INFO_BASE_ADDR, buf, -+ sizeof(buf), true); -+} -+ -+static void txc_48352_update_codec_status(struct txc_48352 *priv, -+ enum drm_connector_status status) -+{ -+ mutex_lock(&priv->codec_mutex); -+ if (priv->codec_dev && priv->codec_plugged_cb) -+ priv->codec_plugged_cb(priv->codec_dev, -+ status == connector_status_connected); -+ mutex_unlock(&priv->codec_mutex); -+} -+ -+static enum drm_connector_status txc_48352_detect(struct txc_48352 *priv) -+{ -+ enum drm_connector_status status; -+ unsigned int val; -+ -+ regmap_read(priv->tx_regmap, TX_HDCP_ST_EDID_STATUS, &val); -+ if (val & TX_HDCP_ST_EDID_STATUS_HPD_STATUS) -+ status = connector_status_connected; -+ else -+ status = connector_status_disconnected; -+ -+ if (status == connector_status_disconnected) { -+ mutex_lock(&priv->cec_notifier_mutex); -+ cec_notifier_phys_addr_invalidate(priv->cec_notifier); -+ mutex_unlock(&priv->cec_notifier_mutex); -+ } -+ -+ txc_48352_update_codec_status(priv, status); -+ -+ return status; -+} -+ -+static int txc_48352_get_edid_block(void *data, u8 *buf, unsigned int block, -+ size_t len) -+{ -+ unsigned int i, regval, start = block * EDID_LENGTH; -+ struct txc_48352 *priv = data; -+ int ret; -+ -+ /* Start the DDC transaction */ -+ regmap_update_bits(priv->tx_regmap, TX_HDCP_EDID_CONFIG, -+ TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG, 0); -+ regmap_update_bits(priv->tx_regmap, TX_HDCP_EDID_CONFIG, -+ TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG, -+ TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG); -+ -+ ret = regmap_read_poll_timeout(priv->tx_regmap, -+ TX_HDCP_ST_EDID_STATUS, -+ regval, -+ (regval & TX_HDCP_ST_EDID_STATUS_EDID_DATA_READY), -+ 1000, 200000); -+ -+ regmap_update_bits(priv->tx_regmap, TX_HDCP_EDID_CONFIG, -+ TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG, 0); -+ -+ if (ret) -+ return ret; -+ -+ for (i = 0; i < len; i++) { -+ regmap_read(priv->tx_regmap, TX_RX_EDID_OFFSET + start + i, -+ ®val); -+ buf[i] = regval; -+ } -+ -+ return 0; -+} -+ -+static struct edid *txc_48352_get_edid(struct txc_48352 *priv, -+ struct drm_connector *connector) -+{ -+ struct edid *edid; -+ -+ edid = drm_do_get_edid(connector, txc_48352_get_edid_block, priv); -+ if (!edid) { -+ drm_dbg(priv->bridge.dev, "Failed to get EDID\n"); -+ return NULL; -+ } -+ -+ priv->sink_is_hdmi = drm_detect_hdmi_monitor(edid); -+ priv->sink_has_audio = drm_detect_monitor_audio(edid); -+ -+ return edid; -+} -+ -+static int txc_48352_connector_get_modes(struct drm_connector *connector) -+{ -+ struct txc_48352 *priv = to_txc_48352(connector); -+ struct edid *edid; -+ int ret; -+ -+ edid = txc_48352_get_edid(priv, connector); -+ if (!edid) -+ return 0; -+ -+ drm_connector_update_edid_property(connector, edid); -+ -+ mutex_lock(&priv->cec_notifier_mutex); -+ cec_notifier_set_phys_addr_from_edid(priv->cec_notifier, edid); -+ mutex_unlock(&priv->cec_notifier_mutex); -+ -+ ret = drm_add_edid_modes(connector, edid); -+ -+ kfree(edid); -+ -+ return ret; -+} -+ -+static struct drm_connector_helper_funcs txc_48352_connector_helper_funcs = { -+ .get_modes = txc_48352_connector_get_modes, -+}; -+ -+static enum drm_connector_status -+txc_48352_connector_detect(struct drm_connector *connector, bool force) -+{ -+ struct txc_48352 *priv = to_txc_48352(connector); -+ -+ return txc_48352_detect(priv); -+} -+ -+static const struct drm_connector_funcs txc_48352_connector_funcs = { -+ .fill_modes = drm_helper_probe_single_connector_modes, -+ .detect = txc_48352_connector_detect, -+ .destroy = drm_connector_cleanup, -+ .reset = drm_atomic_helper_connector_reset, -+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, -+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, -+}; -+ -+static int txc_48352_bridge_attach(struct drm_bridge *bridge, -+ enum drm_bridge_attach_flags flags) -+{ -+ struct txc_48352 *priv = bridge->driver_private; -+ struct drm_connector *connector = &priv->connector; -+ struct drm_encoder *encoder = bridge->encoder; -+ struct cec_connector_info conn_info; -+ struct cec_notifier *notifier; -+ int ret; -+ -+ if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) { -+ drm_err(priv->bridge.dev, "Skipping connector creation"); -+ return 0; -+ } -+ -+ connector->interlace_allowed = 1; -+ connector->polled = DRM_CONNECTOR_POLL_HPD; -+ -+ drm_connector_helper_add(connector, -+ &txc_48352_connector_helper_funcs); -+ -+ ret = drm_connector_init(bridge->dev, &priv->connector, -+ &txc_48352_connector_funcs, -+ DRM_MODE_CONNECTOR_HDMIA); -+ if (ret) -+ return ret; -+ -+ /* -+ * drm_connector_attach_max_bpc_property() requires the -+ * connector to have a state. -+ */ -+ drm_atomic_helper_connector_reset(connector); -+ -+ drm_connector_attach_max_bpc_property(connector, 8, 16); -+ -+ ret = drm_connector_attach_encoder(connector, encoder); -+ if (ret) -+ return ret; -+ -+ cec_fill_conn_info_from_drm(&conn_info, connector); -+ notifier = cec_notifier_conn_register(priv->dev, NULL, &conn_info); -+ if (!notifier) -+ return -ENOMEM; -+ -+ mutex_lock(&priv->cec_notifier_mutex); -+ priv->cec_notifier = notifier; -+ mutex_unlock(&priv->cec_notifier_mutex); -+ -+ return 0; -+} -+ -+static void txc_48352_bridge_detach(struct drm_bridge *bridge) -+{ -+ struct txc_48352 *priv = bridge->driver_private; -+ -+ mutex_lock(&priv->cec_notifier_mutex); -+ cec_notifier_conn_unregister(priv->cec_notifier); -+ priv->cec_notifier = NULL; -+ mutex_unlock(&priv->cec_notifier_mutex); -+} -+ -+static int txc_48352_bridge_atomic_check(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state) -+{ -+ struct txc_48352 *priv = bridge->driver_private; -+ -+ priv->output_bus_format = bridge_state->output_bus_cfg.format; -+ priv->input_bus_format = bridge_state->input_bus_cfg.format; -+ -+ drm_dbg(bridge->dev, "input format 0x%04x, output format 0x%04x\n", -+ priv->input_bus_format, priv->output_bus_format); -+ -+ return 0; -+} -+ -+/* Can return a maximum of 11 possible output formats for a mode/connector */ -+#define MAX_OUTPUT_SEL_FORMATS 11 -+ -+static u32 * -+txc_48352_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state, -+ unsigned int *num_output_fmts) -+{ -+ struct drm_connector *conn = conn_state->connector; -+ struct drm_display_info *info = &conn->display_info; -+ u8 max_bpc = conn_state->max_requested_bpc; -+ unsigned int i = 0; -+ u32 *output_fmts; -+ -+ *num_output_fmts = 0; -+ -+ output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts), -+ GFP_KERNEL); -+ if (!output_fmts) -+ return NULL; -+ -+ /* If we are the only bridge, avoid negotiating with ourselves */ -+ if (list_is_singular(&bridge->encoder->bridge_chain)) { -+ *num_output_fmts = 1; -+ output_fmts[0] = MEDIA_BUS_FMT_FIXED; -+ -+ return output_fmts; -+ } -+ -+ /* -+ * Order bus formats from 16bit to 8bit and from YUV422 to RGB -+ * if supported. In any case the default RGB888 format is added -+ */ -+ -+ if (max_bpc >= 16 && info->bpc == 16) { -+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) -+ output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; -+ -+ output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; -+ } -+ -+ if (max_bpc >= 12 && info->bpc >= 12) { -+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) -+ output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; -+ -+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) -+ output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; -+ -+ output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; -+ } -+ -+ if (max_bpc >= 10 && info->bpc >= 10) { -+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) -+ output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; -+ -+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) -+ output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; -+ -+ output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; -+ } -+ -+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB422) -+ output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; -+ -+ if (info->color_formats & DRM_COLOR_FORMAT_YCRCB444) -+ output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; -+ -+ /* Default 8bit RGB fallback */ -+ output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; -+ -+ *num_output_fmts = i; -+ -+ return output_fmts; -+} -+ -+/* Can return a maximum of 3 possible input formats for an output format */ -+#define MAX_INPUT_SEL_FORMATS 3 -+ -+static u32 * -+txc_48352_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state, -+ u32 output_fmt, -+ unsigned int *num_input_fmts) -+{ -+ u32 *input_fmts; -+ unsigned int i = 0; -+ -+ *num_input_fmts = 0; -+ -+ input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), -+ GFP_KERNEL); -+ if (!input_fmts) -+ return NULL; -+ -+ switch (output_fmt) { -+ /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */ -+ case MEDIA_BUS_FMT_FIXED: -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; -+ break; -+ -+ /* 8bit */ -+ case MEDIA_BUS_FMT_RGB888_1X24: -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; -+ break; -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; -+ break; -+ case MEDIA_BUS_FMT_UYVY8_1X16: -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; -+ break; -+ -+ /* 10bit */ -+ case MEDIA_BUS_FMT_RGB101010_1X30: -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; -+ break; -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; -+ break; -+ case MEDIA_BUS_FMT_UYVY10_1X20: -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; -+ break; -+ -+ /* 12bit */ -+ case MEDIA_BUS_FMT_RGB121212_1X36: -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; -+ break; -+ case MEDIA_BUS_FMT_YUV12_1X36: -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; -+ break; -+ case MEDIA_BUS_FMT_UYVY12_1X24: -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; -+ break; -+ -+ /* 16bit */ -+ case MEDIA_BUS_FMT_RGB161616_1X48: -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; -+ break; -+ case MEDIA_BUS_FMT_YUV16_1X48: -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; -+ break; -+ } -+ -+ *num_input_fmts = i; -+ -+ if (*num_input_fmts == 0) { -+ kfree(input_fmts); -+ input_fmts = NULL; -+ } -+ -+ return input_fmts; -+} -+static void txc_48352_bridge_enable(struct drm_bridge *bridge) -+{ -+ struct txc_48352 *priv = to_txc_48352(bridge); -+ unsigned int i; -+ -+ txc_48352_sys5_reset_assert(priv); -+ -+ txc_48352_config_hdcp_registers(priv); -+ -+ regmap_write(priv->tx_regmap, TX_AUDIO_CONTROL_MORE, 0x1); -+ -+ if (priv->cea_mode == 39) -+ regmap_write(priv->tx_regmap, TX_VIDEO_DTV_TIMING, 0x0); -+ else -+ regmap_write(priv->tx_regmap, TX_VIDEO_DTV_TIMING, -+ TX_VIDEO_DTV_TIMING_DISABLE_VIC39_CORRECTION); -+ -+ regmap_write(priv->tx_regmap, TX_CORE_DATA_CAPTURE_2, -+ TX_CORE_DATA_CAPTURE_2_INTERNAL_PACKET_ENABLE); -+ regmap_write(priv->tx_regmap, TX_CORE_DATA_MONITOR_1, -+ TX_CORE_DATA_MONITOR_1_LANE0 | -+ FIELD_PREP(TX_CORE_DATA_MONITOR_1_SELECT_LANE0, 0x7)); -+ regmap_write(priv->tx_regmap, TX_CORE_DATA_MONITOR_2, -+ FIELD_PREP(TX_CORE_DATA_MONITOR_2_MONITOR_SELECT, -+ 0x2)); -+ -+ if (priv->sink_is_hdmi) -+ regmap_write(priv->tx_regmap, TX_TMDS_MODE, -+ TX_TMDS_MODE_FORCED_HDMI | -+ TX_TMDS_MODE_HDMI_CONFIG); -+ else -+ regmap_write(priv->tx_regmap, TX_TMDS_MODE, -+ TX_TMDS_MODE_FORCED_HDMI); -+ -+ regmap_write(priv->tx_regmap, TX_SYS4_CONNECT_SEL_1, 0x0); -+ -+ /* -+ * Set tmds_clk pattern to be "0000011111" before being sent to AFE -+ * clock channel -+ */ -+ regmap_write(priv->tx_regmap, TX_SYS4_CK_INV_VIDEO, -+ TX_SYS4_CK_INV_VIDEO_TMDS_CLK_PATTERN); -+ -+ regmap_write(priv->tx_regmap, TX_SYS5_FIFO_CONFIG, -+ TX_SYS5_FIFO_CONFIG_CLK_CHANNEL3_OUTPUT_ENABLE | -+ TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL2_ENABLE | -+ TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL1_ENABLE | -+ TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL0_ENABLE); -+ -+ txc_48352_config_color_space(priv); -+ -+ txc_48352_sys5_reset_deassert(priv); -+ -+ txc_48352_config_serializer_clock(priv); -+ txc_48352_reconfig_packet_setting(priv); -+ -+ /* all resets need to be applied twice */ -+ for (i = 0; i < 2; i++) { -+ regmap_write(priv->tx_regmap, TX_SYS5_TX_SOFT_RESET_1, -+ TX_SYS5_TX_SOFT_RESET_1_TX_PIXEL_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_TMDS_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_MASTER_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_RESAMPLE_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_I2S_RESET_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH2 | -+ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH1 | -+ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH0); -+ regmap_write(priv->tx_regmap, TX_SYS5_TX_SOFT_RESET_2, -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH3_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH0_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_SR_RST | -+ TX_SYS5_TX_SOFT_RESET_2_TX_DDC_HDCP_RSTN | -+ TX_SYS5_TX_SOFT_RESET_2_TX_DDC_EDID_RSTN | -+ TX_SYS5_TX_SOFT_RESET_2_TX_DIG_RESET_N_CH3); -+ usleep_range(5000, 10000); -+ regmap_write(priv->tx_regmap, TX_SYS5_TX_SOFT_RESET_1, 0x00); -+ regmap_write(priv->tx_regmap, TX_SYS5_TX_SOFT_RESET_2, 0x00); -+ usleep_range(5000, 10000); -+ } -+ -+ if (!priv->phy_is_on) { -+ int ret = phy_power_on(priv->phy); -+ if (ret) -+ drm_err(bridge->dev, "Failed to turn on PHY\n"); -+ else -+ priv->phy_is_on = true; -+ } -+} -+ -+static void txc_48352_bridge_disable(struct drm_bridge *bridge) -+{ -+ struct txc_48352 *priv = to_txc_48352(bridge); -+ -+ if (priv->phy_is_on) { -+ int ret = phy_power_off(priv->phy); -+ if (ret) -+ drm_err(bridge->dev, "Failed to turn off PHY\n"); -+ else -+ priv->phy_is_on = false; -+ } -+ -+ txc_48352_disable_infoframe(priv, TX_PKT_REG_AUDIO_INFO_BASE_ADDR); -+ txc_48352_disable_infoframe(priv, TX_PKT_REG_AVI_INFO_BASE_ADDR); -+ txc_48352_disable_infoframe(priv, TX_PKT_REG_EXCEPT0_BASE_ADDR); -+ txc_48352_disable_infoframe(priv, TX_PKT_REG_VEND_INFO_BASE_ADDR); -+} -+ -+static void txc_48352_bridge_mode_set(struct drm_bridge *bridge, -+ const struct drm_display_mode *mode, -+ const struct drm_display_mode *adj) -+{ -+ struct txc_48352 *priv = to_txc_48352(bridge); -+ -+ if (priv->input_bus_format == MEDIA_BUS_FMT_FIXED) -+ priv->input_bus_format = MEDIA_BUS_FMT_RGB888_1X24; -+ -+ priv->cea_mode = drm_match_cea_mode(mode); -+ -+ if (priv->sink_is_hdmi) { -+ enum hdmi_quantization_range quant_range; -+ -+ quant_range = drm_default_rgb_quant_range(mode); -+ priv->limited_rgb_quant_range = -+ quant_range == HDMI_QUANTIZATION_RANGE_LIMITED; -+ -+ switch (priv->cea_mode) { -+ case 2 ... 3: -+ case 6 ... 7: -+ case 17 ... 18: -+ case 21 ... 22: -+ priv->colorimetry = HDMI_COLORIMETRY_ITU_601; -+ break; -+ -+ default: -+ priv->colorimetry = HDMI_COLORIMETRY_ITU_709; -+ break; -+ } -+ -+ txc_48352_set_avi_infoframe(priv, mode); -+ txc_48352_set_vendor_infoframe(priv, mode); -+ txc_48352_set_spd_infoframe(priv); -+ } else { -+ priv->limited_rgb_quant_range = false; -+ priv->colorimetry = HDMI_COLORIMETRY_NONE; -+ } -+} -+ -+static enum drm_mode_status -+txc_48352_bridge_mode_valid(struct drm_bridge *bridge, -+ const struct drm_display_info *info, -+ const struct drm_display_mode *mode) -+{ -+ return MODE_OK; -+} -+ -+static enum drm_connector_status txc_48352_bridge_detect(struct drm_bridge *bridge) -+{ -+ struct txc_48352 *priv = to_txc_48352(bridge); -+ -+ return txc_48352_detect(priv); -+} -+ -+static struct edid *txc_48352_bridge_get_edid(struct drm_bridge *bridge, -+ struct drm_connector *connector) -+{ -+ struct txc_48352 *priv = to_txc_48352(bridge); -+ -+ return txc_48352_get_edid(priv, connector); -+} -+ -+static const struct drm_bridge_funcs txc_48352_bridge_funcs = { -+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, -+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, -+ .atomic_reset = drm_atomic_helper_bridge_reset, -+ .attach = txc_48352_bridge_attach, -+ .detach = txc_48352_bridge_detach, -+ .atomic_check = txc_48352_bridge_atomic_check, -+ .atomic_get_output_bus_fmts = txc_48352_bridge_atomic_get_output_bus_fmts, -+ .atomic_get_input_bus_fmts = txc_48352_bridge_atomic_get_input_bus_fmts, -+ .enable = txc_48352_bridge_enable, -+ .disable = txc_48352_bridge_disable, -+ .mode_set = txc_48352_bridge_mode_set, -+ .mode_valid = txc_48352_bridge_mode_valid, -+ .detect = txc_48352_bridge_detect, -+ .get_edid = txc_48352_bridge_get_edid, -+}; -+ -+static irqreturn_t txc_48352_irq_thread(int irq, void *dev_id) -+{ -+ enum drm_connector_status status; -+ struct txc_48352 *priv = dev_id; -+ -+ if (priv->intr_stat & (HDMI_OTHER_INTR_STAT_HPD_RISING | -+ HDMI_OTHER_INTR_STAT_HPD_FALLING)) { -+ drm_helper_hpd_irq_event(priv->bridge.dev); -+ -+ if (priv->intr_stat & HDMI_OTHER_INTR_STAT_HPD_RISING) -+ status = connector_status_connected; -+ else -+ status = connector_status_disconnected; -+ -+ drm_bridge_hpd_notify(&priv->bridge, status); -+ } -+ -+ return IRQ_HANDLED; -+} -+ -+static irqreturn_t txc_48352_irq_handler(int irq, void *dev_id) -+{ -+ struct txc_48352 *priv = dev_id; -+ irqreturn_t ret; -+ -+ regmap_read(priv->other_regmap, HDMI_OTHER_INTR_STAT, &priv->intr_stat); -+ if (!priv->intr_stat) -+ return IRQ_NONE; -+ -+ if (priv->intr_stat & (HDMI_OTHER_INTR_STAT_EDID_RISING | -+ HDMI_OTHER_INTR_STAT_HPD_FALLING | -+ HDMI_OTHER_INTR_STAT_HPD_RISING)) { -+ ret = IRQ_WAKE_THREAD; -+ } else { -+ dev_warn(priv->dev, "IRQ status has unknown bit set: 0x%04x\n", -+ priv->intr_stat); -+ ret = IRQ_HANDLED; -+ } -+ -+ regmap_write(priv->other_regmap, HDMI_OTHER_INTR_STAT_CLR, priv->intr_stat); -+ -+ return ret; -+} -+ -+static int txc_48352_init(struct txc_48352 *priv) -+{ -+ unsigned long ddc_i2c_bus_clk_hz = 500 * 1000; -+ unsigned long sys_clk_hz = 24 * 1000 * 1000; -+ int ret; -+ -+ ret = phy_init(priv->phy); -+ if (ret) { -+ dev_err(priv->dev, "Failed to initialize the PHY: %d\n", ret); -+ return ret; -+ } -+ -+ ret = clk_set_rate(priv->sys_clk, sys_clk_hz); -+ if (ret) { -+ dev_err(priv->dev, "Failed to set HDMI system clock to 24MHz\n"); -+ goto err_phy_exit; -+ } -+ -+ ret = clk_prepare_enable(priv->sys_clk); -+ if (ret) { -+ dev_err(priv->dev, "Failed to enable the sys clk\n"); -+ goto err_phy_exit; -+ } -+ -+ regmap_update_bits(priv->other_regmap, HDMI_OTHER_CTRL1, -+ HDMI_OTHER_CTRL1_POWER_ON, -+ HDMI_OTHER_CTRL1_POWER_ON); -+ -+ /* -+ * FIXME - questions for CDNS team: -+ * - what is the name of the 0x0010 register? -+ * - what do bit [7:0] stand for? -+ */ -+ regmap_write(priv->tx_regmap, 0x0010, 0xff); -+ -+ regmap_write(priv->tx_regmap, TX_HDCP_MODE, 0x40); -+ -+ /* -+ * FIXME - questions for CDNS team: -+ * - what is the name of the 0x0017 register? -+ * - is there a description for BIT(0), BIT(2), BIT(3) and BIT(4) or -+ * are 0x1d and 0x0 the only allowed values? -+ */ -+ /* Band-gap and main-bias. 0x1d = power-up, 0x00 = power-down */ -+ regmap_write(priv->tx_regmap, 0x0017, 0x1d); -+ -+ txc_48352_config_serializer_clock(priv); -+ -+ /* -+ * FIXME - questions for CDNS team: -+ * - what is the name of the 0x001a register? -+ * - is there a description for BIT(3), BIT(4), BIT(5), BIT(6) and -+ * BIT(7)? -+ */ -+ /* -+ * bit[2:0]=011: CK channel output TMDS CLOCK -+ * bit[2:0]=101, ck channel output PHYCLCK -+ */ -+ regmap_write(priv->tx_regmap, 0x001a, 0xfb); -+ -+ /* Termination resistor calib value */ -+ regmap_write(priv->tx_regmap, TX_CORE_CALIB_VALUE, 0x0f); -+ -+ /* HPD glitch filter */ -+ regmap_write(priv->tx_regmap, TX_HDCP_HPD_FILTER_L, 0xa0); -+ regmap_write(priv->tx_regmap, TX_HDCP_HPD_FILTER_H, 0xa0); -+ -+ /* Disable MEM power-down */ -+ regmap_write(priv->tx_regmap, TX_MEM_PD_REG0, 0); -+ -+ regmap_write(priv->tx_regmap, TX_HDCP_CONFIG3, -+ FIELD_PREP(TX_HDCP_CONFIG3_DDC_I2C_BUS_CLOCK_TIME_DIVIDER, -+ (sys_clk_hz / ddc_i2c_bus_clk_hz) - 1)); -+ -+ /* Enable software controlled DDC transaction */ -+ regmap_write(priv->tx_regmap, TX_HDCP_EDID_CONFIG, -+ TX_HDCP_EDID_CONFIG_FORCED_MEM_COPY_DONE | -+ TX_HDCP_EDID_CONFIG_MEM_COPY_DONE_CONFIG); -+ regmap_write(priv->tx_regmap, TX_CORE_EDID_CONFIG_MORE, -+ TX_CORE_EDID_CONFIG_MORE_SYS_TRIGGER_CONFIG_SEMI_MANU); -+ -+ /* clear any pending interrupt */ -+ regmap_write(priv->other_regmap, HDMI_OTHER_INTR_STAT_CLR, -+ HDMI_OTHER_INTR_STAT_CLR_EDID_RISING | -+ HDMI_OTHER_INTR_STAT_CLR_HPD_FALLING | -+ HDMI_OTHER_INTR_STAT_CLR_HPD_RISING); -+ -+ /* unmask (= enable) all interrupts */ -+ regmap_write(priv->other_regmap, HDMI_OTHER_INTR_MASKN, -+ HDMI_OTHER_INTR_MASKN_TX_EDID_INT_RISE | -+ HDMI_OTHER_INTR_MASKN_TX_HPD_INT_FALL | -+ HDMI_OTHER_INTR_MASKN_TX_HPD_INT_RISE); -+ -+ ret = devm_request_threaded_irq(priv->dev, priv->irq, -+ txc_48352_irq_handler, -+ txc_48352_irq_thread, 0, NULL, priv); -+ if (ret) { -+ dev_err(priv->dev, "Failed to request threaded irq: %d\n", ret); -+ goto err_clk_disable; -+ } -+ -+ return 0; -+ -+err_clk_disable: -+ clk_disable_unprepare(priv->sys_clk); -+err_phy_exit: -+ phy_exit(priv->phy); -+ return 0; -+} -+ -+static u32 txc_48352_hdmi_codec_calc_audio_n(struct hdmi_codec_params *hparms) -+{ -+ u32 audio_n; -+ -+ if ((hparms->sample_rate % 44100) == 0) -+ audio_n = (128 * hparms->sample_rate) / 900; -+ else -+ audio_n = (128 * hparms->sample_rate) / 1000; -+ -+ if (hparms->cea.coding_type == HDMI_AUDIO_CODING_TYPE_EAC3 || -+ hparms->cea.coding_type == HDMI_AUDIO_CODING_TYPE_DTS_HD) -+ audio_n *= 4; -+ -+ return audio_n; -+} -+ -+static u8 txc_48352_hdmi_codec_coding_type(struct hdmi_codec_params *hparms) -+{ -+ switch (hparms->cea.coding_type) { -+ case HDMI_AUDIO_CODING_TYPE_MLP: -+ return TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_HBR_AUDIO_PACKET; -+ case HDMI_AUDIO_CODING_TYPE_DSD: -+ return TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_ONE_BIT_AUDIO; -+ case HDMI_AUDIO_CODING_TYPE_DST: -+ return TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_DST_AUDIO_PACKET; -+ default: -+ return TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_AUDIO_SAMPLE_PACKET; -+ } -+} -+ -+static int txc_48352_hdmi_codec_hw_params(struct device *dev, void *data, -+ struct hdmi_codec_daifmt *fmt, -+ struct hdmi_codec_params *hparms) -+{ -+ u8 buf[HDMI_INFOFRAME_SIZE(AUDIO)]; -+ struct txc_48352 *priv = data; -+ u8 audio_format_sample_width; -+ u32 audio_n; -+ int len, i; -+ -+ if (hparms->cea.coding_type == HDMI_AUDIO_CODING_TYPE_MLP) { -+ /* -+ * TODO: fixed CTS is not supported yet, it needs special -+ * TX_SYS1_ACR_N_* settings -+ */ -+ return -EINVAL; -+ } -+ -+ switch (hparms->sample_width) { -+ case 16: -+ audio_format_sample_width = TX_AUDIO_FORMAT_BIT_WIDTH_16; -+ break; -+ -+ case 20: -+ audio_format_sample_width = TX_AUDIO_FORMAT_BIT_WIDTH_20; -+ break; -+ -+ case 24: -+ audio_format_sample_width = TX_AUDIO_FORMAT_BIT_WIDTH_24; -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ switch (fmt->fmt) { -+ case HDMI_I2S: -+ regmap_update_bits(priv->other_regmap, HDMI_OTHER_CTRL1, -+ HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON, -+ HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON); -+ -+ regmap_write(priv->tx_regmap, TX_AUDIO_FORMAT, -+ TX_AUDIO_FORMAT_SPDIF_OR_I2S | -+ FIELD_PREP(TX_AUDIO_FORMAT_I2S_FORMAT, 0x2) | -+ FIELD_PREP(TX_AUDIO_FORMAT_BIT_WIDTH_MASK, -+ audio_format_sample_width) | -+ TX_AUDIO_FORMAT_I2S_ONE_BIT_OR_I2S); -+ -+ if (hparms->channels > 2) -+ regmap_update_bits(priv->tx_regmap, TX_AUDIO_FORMAT, -+ TX_AUDIO_FORMAT_I2S_2_OR_8_CH, -+ TX_AUDIO_FORMAT_I2S_2_OR_8_CH); -+ -+ regmap_write(priv->tx_regmap, TX_AUDIO_I2S, TX_AUDIO_I2S_ENABLE); -+ regmap_write(priv->tx_regmap, TX_AUDIO_SPDIF, 0x0); -+ break; -+ -+ case HDMI_SPDIF: -+ regmap_update_bits(priv->other_regmap, HDMI_OTHER_CTRL1, -+ HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON, 0x0); -+ -+ if (hparms->cea.coding_type == HDMI_AUDIO_CODING_TYPE_PCM) -+ regmap_write(priv->tx_regmap, TX_AUDIO_FORMAT, -+ TX_AUDIO_FORMAT_SPDIF_CHANNEL_STATUS_FROM_DATA_OR_REG); -+ else -+ regmap_write(priv->tx_regmap, TX_AUDIO_FORMAT, 0x0); -+ -+ regmap_write(priv->tx_regmap, TX_AUDIO_I2S, 0x0); -+ regmap_write(priv->tx_regmap, TX_AUDIO_SPDIF, TX_AUDIO_SPDIF_ENABLE); -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ if (hparms->channels > 2) -+ regmap_write(priv->tx_regmap, TX_AUDIO_HEADER, -+ TX_AUDIO_HEADER_AUDIO_SAMPLE_PACKET_HEADER_LAYOUT); -+ else -+ regmap_write(priv->tx_regmap, TX_AUDIO_HEADER, 0x0); -+ -+ regmap_write(priv->tx_regmap, TX_AUDIO_SAMPLE, -+ FIELD_PREP(TX_AUDIO_SAMPLE_CHANNEL_VALID, -+ BIT(hparms->channels) - 1)); -+ -+ audio_n = txc_48352_hdmi_codec_calc_audio_n(hparms); -+ -+ regmap_write(priv->tx_regmap, TX_SYS1_ACR_N_0, -+ FIELD_PREP(TX_SYS1_ACR_N_0_N_BYTE0, -+ (audio_n >> 0) & 0xff)); -+ regmap_write(priv->tx_regmap, TX_SYS1_ACR_N_1, -+ FIELD_PREP(TX_SYS1_ACR_N_1_N_BYTE1, -+ (audio_n >> 8) & 0xff)); -+ regmap_update_bits(priv->tx_regmap, TX_SYS1_ACR_N_2, -+ TX_SYS1_ACR_N_2_N_UPPER_NIBBLE, -+ FIELD_PREP(TX_SYS1_ACR_N_2_N_UPPER_NIBBLE, -+ (audio_n >> 16) & 0xf)); -+ -+ regmap_write(priv->tx_regmap, TX_SYS0_ACR_CTS_0, 0x0); -+ regmap_write(priv->tx_regmap, TX_SYS0_ACR_CTS_1, 0x0); -+ regmap_write(priv->tx_regmap, TX_SYS0_ACR_CTS_2, -+ TX_SYS0_ACR_CTS_2_FORCE_ARC_STABLE); -+ -+ regmap_write(priv->tx_regmap, TX_AUDIO_CONTROL, -+ TX_AUDIO_CONTROL_AUTO_AUDIO_FIFO_CLEAR | -+ FIELD_PREP(TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_MASK, -+ txc_48352_hdmi_codec_coding_type(hparms)) | -+ TX_AUDIO_CONTROL_AUDIO_SAMPLE_PACKET_FLAT); -+ -+ len = hdmi_audio_infoframe_pack(&hparms->cea, buf, sizeof(buf)); -+ if (len < 0) -+ return len; -+ -+ txc_48352_write_infoframe(priv->tx_regmap, -+ TX_PKT_REG_AUDIO_INFO_BASE_ADDR, -+ buf, len, true); -+ -+ for (i = 0; i < ARRAY_SIZE(hparms->iec.status); i++) { -+ if (i == 2) { -+ regmap_write(priv->tx_regmap, -+ TX_IEC60958_SUB1_OFFSET + i, -+ FIELD_PREP(IEC958_AES2_CON_SOURCE, -+ hparms->channels) | -+ FIELD_PREP(IEC958_AES2_CON_CHANNEL, 1)); -+ regmap_write(priv->tx_regmap, -+ TX_IEC60958_SUB2_OFFSET + i, -+ FIELD_PREP(IEC958_AES2_CON_SOURCE, -+ hparms->channels) | -+ FIELD_PREP(IEC958_AES2_CON_CHANNEL, 2)); -+ } else { -+ regmap_write(priv->tx_regmap, -+ TX_IEC60958_SUB1_OFFSET + i, -+ hparms->iec.status[i]); -+ regmap_write(priv->tx_regmap, -+ TX_IEC60958_SUB2_OFFSET + i, -+ hparms->iec.status[i]); -+ } -+ } -+ -+ return 0; -+} -+ -+static int txc_48352_hdmi_codec_audio_startup(struct device *dev, void *data) -+{ -+ struct txc_48352 *priv = data; -+ -+ regmap_update_bits(priv->tx_regmap, TX_PACKET_CONTROL_2, -+ TX_PACKET_CONTROL_2_AUDIO_REQUEST_DISABLE, 0x0); -+ -+ /* reset audio master and sample */ -+ regmap_write(priv->tx_regmap, TX_SYS5_TX_SOFT_RESET_1, -+ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_RESAMPLE_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_MASTER_RSTN); -+ regmap_write(priv->tx_regmap, TX_SYS5_TX_SOFT_RESET_1, 0x0); -+ -+ regmap_write(priv->tx_regmap, TX_AUDIO_CONTROL_MORE, -+ TX_AUDIO_CONTROL_MORE_ENABLE); -+ -+ regmap_write(priv->tx_regmap, TX_AUDIO_FIFO, -+ FIELD_PREP(TX_AUDIO_FIFO_FIFO_DEPTH_MASK, -+ TX_AUDIO_FIFO_FIFO_DEPTH_512) | -+ FIELD_PREP(TX_AUDIO_FIFO_CRITICAL_THRESHOLD_MASK, -+ TX_AUDIO_FIFO_CRITICAL_THRESHOLD_DEPTH_DIV16) | -+ FIELD_PREP(TX_AUDIO_FIFO_NORMAL_THRESHOLD_MASK, -+ TX_AUDIO_FIFO_NORMAL_THRESHOLD_DEPTH_DIV8)); -+ -+ regmap_write(priv->tx_regmap, TX_AUDIO_LIPSYNC, 0x0); -+ -+ regmap_write(priv->tx_regmap, TX_SYS1_ACR_N_2, -+ FIELD_PREP(TX_SYS1_ACR_N_2_N_MEAS_TOLERANCE, 0x3)); -+ -+ return 0; -+} -+ -+static void txc_48352_hdmi_codec_audio_shutdown(struct device *dev, void *data) -+{ -+ struct txc_48352 *priv = data; -+ -+ regmap_write(priv->tx_regmap, TX_AUDIO_CONTROL_MORE, 0x0); -+ regmap_update_bits(priv->other_regmap, HDMI_OTHER_CTRL1, -+ HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON, 0x0); -+ -+ regmap_update_bits(priv->tx_regmap, TX_PACKET_CONTROL_2, -+ TX_PACKET_CONTROL_2_AUDIO_REQUEST_DISABLE, -+ TX_PACKET_CONTROL_2_AUDIO_REQUEST_DISABLE); -+} -+ -+static int txc_48352_hdmi_codec_mute_stream(struct device *dev, void *data, -+ bool enable, int direction) -+{ -+ struct txc_48352 *priv = data; -+ -+ regmap_write(priv->tx_regmap, TX_AUDIO_PACK, -+ enable ? 0 : TX_AUDIO_PACK_AUDIO_SAMPLE_PACKETS_ENABLE); -+ -+ return 0; -+} -+ -+static int txc_48352_hdmi_codec_get_eld(struct device *dev, void *data, -+ uint8_t *buf, size_t len) -+{ -+ struct txc_48352 *priv = data; -+ -+ memcpy(buf, priv->connector.eld, min_t(size_t, MAX_ELD_BYTES, len)); -+ -+ return 0; -+} -+ -+static int txc_48352_hdmi_codec_get_dai_id(struct snd_soc_component *component, -+ struct device_node *endpoint) -+{ -+ struct of_endpoint of_ep; -+ int ret; -+ -+ ret = of_graph_parse_endpoint(endpoint, &of_ep); -+ if (ret < 0) -+ return ret; -+ -+ /* -+ * HDMI sound should be located as reg = <2> -+ * Then, it is sound port 0 -+ */ -+ if (of_ep.port == 2) -+ return 0; -+ -+ return -EINVAL; -+} -+ -+static int txc_48352_hdmi_codec_hook_plugged_cb(struct device *dev, void *data, -+ hdmi_codec_plugged_cb fn, -+ struct device *codec_dev) -+{ -+ struct txc_48352 *priv = data; -+ -+ mutex_lock(&priv->codec_mutex); -+ priv->codec_plugged_cb = fn; -+ priv->codec_dev = codec_dev; -+ txc_48352_update_codec_status(priv, priv->connector.status); -+ mutex_unlock(&priv->codec_mutex); -+ -+ return 0; -+} -+ -+static struct hdmi_codec_ops txc_48352_hdmi_codec_ops = { -+ .hw_params = txc_48352_hdmi_codec_hw_params, -+ .audio_startup = txc_48352_hdmi_codec_audio_startup, -+ .audio_shutdown = txc_48352_hdmi_codec_audio_shutdown, -+ .mute_stream = txc_48352_hdmi_codec_mute_stream, -+ .get_eld = txc_48352_hdmi_codec_get_eld, -+ .get_dai_id = txc_48352_hdmi_codec_get_dai_id, -+ .hook_plugged_cb = txc_48352_hdmi_codec_hook_plugged_cb, -+}; -+ -+static int txc_48352_hdmi_codec_init(struct txc_48352 *priv) -+{ -+ struct hdmi_codec_pdata pdata = { -+ .ops = &txc_48352_hdmi_codec_ops, -+ .i2s = 1, -+ .spdif = 1, -+ .max_i2s_channels = 8, -+ .data = priv, -+ }; -+ -+ priv->hdmi_codec_pdev = platform_device_register_data(priv->dev, -+ HDMI_CODEC_DRV_NAME, -+ PLATFORM_DEVID_AUTO, -+ &pdata, sizeof(pdata)); -+ return PTR_ERR_OR_ZERO(priv->hdmi_codec_pdev); -+} -+ -+static void txc_48352_exit(struct txc_48352 *priv) -+{ -+ /* mask (= disable) all interrupts */ -+ regmap_write(priv->other_regmap, HDMI_OTHER_INTR_MASKN, 0); -+ -+ devm_free_irq(priv->dev, priv->irq, priv); -+ -+ regmap_update_bits(priv->other_regmap, HDMI_OTHER_CTRL1, -+ HDMI_OTHER_CTRL1_POWER_ON, 0); -+ -+ clk_disable_unprepare(priv->sys_clk); -+} -+ -+struct txc_48352 *txc_48352_bind(struct drm_encoder *encoder, -+ struct device *dev) -+{ -+ struct txc_48352 *priv; -+ int ret; -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return ERR_PTR(-ENOMEM); -+ -+ priv->dev = dev; -+ -+ priv->input_bus_format = MEDIA_BUS_FMT_FIXED; -+ priv->output_bus_format = MEDIA_BUS_FMT_FIXED; -+ -+ mutex_init(&priv->cec_notifier_mutex); -+ mutex_init(&priv->codec_mutex); -+ -+ priv->irq = of_irq_get(dev->of_node, 0); -+ if (priv->irq < 0) -+ return ERR_PTR(priv->irq); -+ -+ priv->tx_regmap = dev_get_regmap(dev, "bridge"); -+ if (IS_ERR(priv->tx_regmap)) -+ return ERR_CAST(priv->tx_regmap); -+ -+ priv->other_regmap = dev_get_regmap(dev, "other"); -+ if (IS_ERR(priv->other_regmap)) -+ return ERR_CAST(priv->other_regmap); -+ -+ priv->sys_clk = devm_clk_get(dev, "sys"); -+ if (IS_ERR(priv->sys_clk)) { -+ dev_err(dev, "Failed to get the sys clock\n"); -+ return ERR_CAST(priv->sys_clk); -+ } -+ -+ priv->phy = devm_phy_get(priv->dev, "hdmi"); -+ if (IS_ERR(priv->phy)) { -+ ret = PTR_ERR(priv->phy); -+ dev_err(dev, "Failed to get the HDMI PHY: %d\n", ret); -+ return ERR_PTR(ret); -+ } -+ -+ ret = txc_48352_init(priv); -+ if (ret) -+ return ERR_PTR(ret); -+ -+ ret = txc_48352_hdmi_codec_init(priv); -+ if (ret) -+ return ERR_PTR(ret); -+ -+ priv->bridge.driver_private = priv; -+ priv->bridge.funcs = &txc_48352_bridge_funcs; -+ priv->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD; -+ priv->bridge.of_node = dev->of_node; -+ -+ drm_bridge_add(&priv->bridge); -+ -+ return priv; -+} -+EXPORT_SYMBOL_GPL(txc_48352_bind); -+ -+void txc_48352_unbind(struct txc_48352 *priv) -+{ -+ platform_device_unregister(priv->hdmi_codec_pdev); -+ -+ drm_bridge_remove(&priv->bridge); -+ -+ txc_48352_exit(priv); -+} -+EXPORT_SYMBOL_GPL(txc_48352_unbind); -+ -+MODULE_AUTHOR("Martin Blumenstingl "); -+MODULE_DESCRIPTION("TranSwitch TXC-48352 HDMI 1.4 Transmitter IP core driver"); -+MODULE_LICENSE("GPL v2"); -diff --git a/drivers/gpu/drm/bridge/transwitch/txccq-txc-48352.h b/drivers/gpu/drm/bridge/transwitch/txccq-txc-48352.h -new file mode 100644 -index 000000000..8dcdb67fe ---- /dev/null -+++ b/drivers/gpu/drm/bridge/transwitch/txccq-txc-48352.h -@@ -0,0 +1,537 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2020 Martin Blumenstingl -+ * -+ * All registers and magic values are taken from Amlogic's GPL kernel sources: -+ * Copyright (C) 2010 Amlogic, Inc. -+ */ -+ -+#include -+#include -+ -+#ifndef __TXCCQ_TXC_84352_H__ -+#define __TXCCQ_TXC_84352_H__ -+ -+/* HDMI TX register */ -+ -+// System config 0 -+#define TX_SYS0_AFE_SIGNAL 0x0000 -+#define TX_SYS0_AFE_LOOP 0x0001 -+#define TX_SYS0_ACR_CTS_0 0x0002 -+ #define TX_SYS0_ACR_CTS_0_AUDIO_CTS_BYTE0 GENMASK(7, 0) -+#define TX_SYS0_ACR_CTS_1 0x0003 -+ #define TX_SYS0_ACR_CTS_1_AUDIO_CTS_BYTE1 GENMASK(7, 0) -+#define TX_SYS0_ACR_CTS_2 0x0004 -+ #define TX_SYS0_ACR_CTS_2_FORCE_ARC_STABLE BIT(5) -+#define TX_SYS0_BIST_CONTROL 0x0005 -+ #define TX_SYS0_BIST_CONTROL_AFE_BIST_ENABLE BIT(7) -+ #define TX_SYS0_BIST_CONTROL_TMDS_SHIFT_PATTERN_SELECT BIT(6) -+ #define TX_SYS0_BIST_CONTROL_TMDS_PRBS_PATTERN_SELECT GENMASK(5, 4) -+ #define TX_SYS0_BIST_CONTROL_TMDS_REPEAT_BIST_PATTERN GENMASK(2, 0) -+ -+#define TX_SYS0_BIST_DATA_0 0x0006 -+#define TX_SYS0_BIST_DATA_1 0x0007 -+#define TX_SYS0_BIST_DATA_2 0x0008 -+#define TX_SYS0_BIST_DATA_3 0x0009 -+#define TX_SYS0_BIST_DATA_4 0x000A -+#define TX_SYS0_BIST_DATA_5 0x000B -+#define TX_SYS0_BIST_DATA_6 0x000C -+#define TX_SYS0_BIST_DATA_7 0x000D -+#define TX_SYS0_BIST_DATA_8 0x000E -+#define TX_SYS0_BIST_DATA_9 0x000F -+ -+// system config 1 -+#define TX_HDMI_PHY_CONFIG0 0x0010 -+ #define TX_HDMI_PHY_CONFIG0_HDMI_COMMON_B7_B0 GENMASK(7, 0) -+#define TX_HDMI_PHY_CONFIG1 0x0010 -+ #define TX_HDMI_PHY_CONFIG1_HDMI_COMMON_B11_B8 GENMASK(3, 0) -+ #define TX_HDMI_PHY_CONFIG1_HDMI_CTL_REG_B3_B0 GENMASK(7, 4) -+#define TX_HDMI_PHY_CONFIG2 0x0012 -+ #define TX_HDMI_PHY_CONFIG_HDMI_CTL_REG_B11_B4 GENMASK(7, 0) -+#define TX_HDMI_PHY_CONFIG3 0x0013 -+ #define TX_HDMI_PHY_CONFIG3_HDMI_L2H_CTL GENMASK(3, 0) -+ #define TX_HDMI_PHY_CONFIG3_HDMI_MDR_PU GENMASK(7, 4) -+#define TX_HDMI_PHY_CONFIG4 0x0014 -+ #define TX_HDMI_PHY_CONFIG4_HDMI_LF_PD BIT(0) -+ #define TX_HDMI_PHY_CONFIG4_HDMI_PHY_CLK_EN BIT(1) -+ #define TX_HDMI_PHY_CONFIG4_HDMI_MODE GENMASK(3, 2) -+ #define TX_HDMI_PHY_CONFIG4_HDMI_MODE_NORMAL 0x0 -+ #define TX_HDMI_PHY_CONFIG4_HDMI_MODE_CLK_CH3_EQUAL_CH0 0x1 -+ #define TX_HDMI_PHY_CONFIG4_HDMI_MODE_ALTERNATE_HIGH_LOW 0x2 -+ #define TX_HDMI_PHY_CONFIG4_HDMI_MODE_ALTERNATE_LOW_HIGH 0x3 -+ #define TX_HDMI_PHY_CONFIG4_HDMI_PREM_CTL GENMASK(7, 4) -+#define TX_HDMI_PHY_CONFIG5 0x0015 -+ #define TX_HDMI_PHY_CONFIG5_HDMI_VCM_CTL GENMASK(7, 5) -+ #define TX_HDMI_PHY_CONFIG5_HDMI_PREFCTL GENMASK(2, 0) -+#define TX_HDMI_PHY_CONFIG6 0x0016 -+ #define TX_HDMI_PHY_CONFIG6_HDMI_RTERM_CTL GENMASK(3, 0) -+ #define TX_HDMI_PHY_CONFIG6_HDMI_SWING_CTL GENMASK(7, 4) -+#define TX_SYS1_AFE_TEST 0x0017 -+#define TX_SYS1_PLL 0x0018 -+#define TX_SYS1_TUNE 0x0019 -+#define TX_SYS1_AFE_CONNECT 0x001A -+ -+#define TX_SYS1_ACR_N_0 0x001C -+ #define TX_SYS1_ACR_N_0_N_BYTE0 GENMASK(7, 0) -+#define TX_SYS1_ACR_N_1 0x001D -+ #define TX_SYS1_ACR_N_1_N_BYTE1 GENMASK(7, 0) -+#define TX_SYS1_ACR_N_2 0x001E -+ #define TX_SYS1_ACR_N_2_N_MEAS_TOLERANCE GENMASK(7, 4) -+ #define TX_SYS1_ACR_N_2_N_UPPER_NIBBLE GENMASK(3, 0) -+#define TX_SYS1_PRBS_DATA 0x001F -+ #define TX_SYS1_PRBS_DATA_PRBS_MODE GENMASK(1, 0) -+ #define TX_SYS1_PRBS_DATA_PRBS_MODE_11 0x0 -+ #define TX_SYS1_PRBS_DATA_PRBS_MODE_15 0x1 -+ #define TX_SYS1_PRBS_DATA_PRBS_MODE_7 0x2 -+ #define TX_SYS1_PRBS_DATA_PRBS_MODE_31 0x3 -+ -+// HDCP CONFIG -+#define TX_HDCP_ECC_CONFIG 0x0024 -+#define TX_HDCP_CRC_CONFIG 0x0025 -+#define TX_HDCP_EDID_CONFIG 0x0026 -+ #define TX_HDCP_EDID_CONFIG_FORCED_SYS_TRIGGER BIT(7) -+ #define TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG BIT(6) -+ #define TX_HDCP_EDID_CONFIG_MEM_ACC_SEQ_MODE BIT(5) -+ #define TX_HDCP_EDID_CONFIG_MEM_ACC_SEQ_START BIT(4) -+ #define TX_HDCP_EDID_CONFIG_FORCED_MEM_COPY_DONE BIT(3) -+ #define TX_HDCP_EDID_CONFIG_MEM_COPY_DONE_CONFIG BIT(2) -+ #define TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG_SEMI_MANU BIT(1) -+ -+#define TX_HDCP_MEM_CONFIG 0x0027 -+ #define TX_HDCP_MEM_CONFIG_READ_DECRYPT BIT(3) -+ -+#define TX_HDCP_HPD_FILTER_L 0x0028 -+#define TX_HDCP_HPD_FILTER_H 0x0029 -+#define TX_HDCP_ENCRYPT_BYTE 0x002A -+#define TX_HDCP_CONFIG0 0x002B -+ #define TX_HDCP_CONFIG0_ROM_ENCRYPT_OFF GENMASK(4, 3) -+ -+#define TX_HDCP_CONFIG1 0x002C -+#define TX_HDCP_CONFIG2 0x002D -+#define TX_HDCP_CONFIG3 0x002E -+ #define TX_HDCP_CONFIG3_DDC_I2C_BUS_CLOCK_TIME_DIVIDER GENMASK(7, 0) -+ -+#define TX_HDCP_MODE 0x002F -+ #define TX_HDCP_MODE_CP_DESIRED BIT(7) -+ #define TX_HDCP_MODE_ESS_CONFIG BIT(6) -+ #define TX_HDCP_MODE_SET_AVMUTE BIT(5) -+ #define TX_HDCP_MODE_CLEAR_AVMUTE BIT(4) -+ #define TX_HDCP_MODE_HDCP_1_1 BIT(3) -+ #define TX_HDCP_MODE_VSYNC_HSYNC_FORCED_POLARITY_SELECT BIT(2) -+ #define TX_HDCP_MODE_FORCED_VSYNC_POLARITY BIT(1) -+ #define TX_HDCP_MODE_FORCED_HSYNC_POLARITY BIT(0) -+ -+// Video config, part 1 -+#define TX_VIDEO_ACTIVE_PIXELS_0 0x0030 -+#define TX_VIDEO_ACTIVE_PIXELS_1 0x0031 -+#define TX_VIDEO_FRONT_PIXELS 0x0032 -+#define TX_VIDEO_HSYNC_PIXELS 0x0033 -+#define TX_VIDEO_BACK_PIXELS 0x0034 -+#define TX_VIDEO_ACTIVE_LINES_0 0x0035 -+#define TX_VIDEO_ACTIVE_LINES_1 0x0036 -+#define TX_VIDEO_EOF_LINES 0x0037 -+#define TX_VIDEO_VSYNC_LINES 0x0038 -+#define TX_VIDEO_SOF_LINES 0x0039 -+#define TX_VIDEO_DTV_TIMING 0x003A -+ #define TX_VIDEO_DTV_TIMING_FORCE_DTV_TIMING_AUTO BIT(7) -+ #define TX_VIDEO_DTV_TIMING_FORCE_VIDEO_SCAN BIT(6) -+ #define TX_VIDEO_DTV_TIMING_FORCE_VIDEO_FIELD BIT(5) -+ #define TX_VIDEO_DTV_TIMING_DISABLE_VIC39_CORRECTION BIT(4) -+ -+#define TX_VIDEO_DTV_MODE 0x003B -+ #define TX_VIDEO_DTV_MODE_FORCED_DEFAULT_PHASE BIT(7) -+ #define TX_VIDEO_DTV_MODE_COLOR_DEPTH GENMASK(1, 0) -+ -+#define TX_VIDEO_DTV_FORMAT0 0x003C -+#define TX_VIDEO_DTV_FORMAT1 0x003D -+#define TX_VIDEO_PIXEL_PACK 0x003F -+// video config, part 2 -+#define TX_VIDEO_CSC_COEFF_B0 0x0040 -+#define TX_VIDEO_CSC_COEFF_B1 0x0041 -+#define TX_VIDEO_CSC_COEFF_R0 0x0042 -+#define TX_VIDEO_CSC_COEFF_R1 0x0043 -+#define TX_VIDEO_CSC_COEFF_CB0 0x0044 -+#define TX_VIDEO_CSC_COEFF_CB1 0x0045 -+#define TX_VIDEO_CSC_COEFF_CR0 0x0046 -+#define TX_VIDEO_CSC_COEFF_CR1 0x0047 -+#define TX_VIDEO_DTV_OPTION_L 0x0048 -+ #define TX_VIDEO_DTV_OPTION_L_OUTPUT_COLOR_FORMAT GENMASK(7, 6) -+ #define TX_VIDEO_DTV_OPTION_L_INPUT_COLOR_FORMAT GENMASK(5, 4) -+ #define TX_VIDEO_DTV_OPTION_L_OUTPUT_COLOR_DEPTH GENMASK(3, 2) -+ #define TX_VIDEO_DTV_OPTION_L_INPUT_COLOR_DEPTH GENMASK(1, 0) -+ -+#define TX_VIDEO_DTV_OPTION_H 0x0049 -+ #define TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_16_235 0x0 -+ #define TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_16_240 0x1 -+ #define TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_1_254 0x2 -+ #define TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_0_255 0x3 -+ #define TX_VIDEO_DTV_OPTION_H_OUTPUT_COLOR_RANGE GENMASK(3, 2) -+ #define TX_VIDEO_DTV_OPTION_H_INPUT_COLOR_RANGE GENMASK(1, 0) -+ -+#define TX_VIDEO_DTV_FILTER 0x004A -+#define TX_VIDEO_DTV_DITHER 0x004B -+#define TX_VIDEO_DTV_DEDITHER 0x004C -+#define TX_VIDEO_PROC_CONFIG0 0x004E -+#define TX_VIDEO_PROC_CONFIG1 0x004F -+ -+// Audio config -+#define TX_AUDIO_FORMAT 0x0058 -+ #define TX_AUDIO_FORMAT_SPDIF_OR_I2S BIT(7) -+ #define TX_AUDIO_FORMAT_I2S_2_OR_8_CH BIT(6) -+ #define TX_AUDIO_FORMAT_I2S_FORMAT GENMASK(5, 4) -+ #define TX_AUDIO_FORMAT_BIT_WIDTH_MASK GENMASK(3, 2) -+ #define TX_AUDIO_FORMAT_BIT_WIDTH_16 0x1 -+ #define TX_AUDIO_FORMAT_BIT_WIDTH_20 0x2 -+ #define TX_AUDIO_FORMAT_BIT_WIDTH_24 0x3 -+ #define TX_AUDIO_FORMAT_WS_POLARITY BIT(1) -+ #define TX_AUDIO_FORMAT_I2S_ONE_BIT_OR_I2S BIT(0) -+ #define TX_AUDIO_FORMAT_SPDIF_CHANNEL_STATUS_FROM_DATA_OR_REG BIT(0) -+ -+#define TX_AUDIO_SPDIF 0x0059 -+ #define TX_AUDIO_SPDIF_ENABLE BIT(0) -+#define TX_AUDIO_I2S 0x005A -+ #define TX_AUDIO_I2S_ENABLE BIT(0) -+#define TX_AUDIO_FIFO 0x005B -+ #define TX_AUDIO_FIFO_FIFO_DEPTH_MASK GENMASK(7, 4) -+ #define TX_AUDIO_FIFO_FIFO_DEPTH_512 0x4 -+ #define TX_AUDIO_FIFO_CRITICAL_THRESHOLD_MASK GENMASK(3, 2) -+ #define TX_AUDIO_FIFO_CRITICAL_THRESHOLD_DEPTH_DIV16 0x2 -+ #define TX_AUDIO_FIFO_NORMAL_THRESHOLD_MASK GENMASK(1, 0) -+ #define TX_AUDIO_FIFO_NORMAL_THRESHOLD_DEPTH_DIV8 0x1 -+#define TX_AUDIO_LIPSYNC 0x005C -+ #define TX_AUDIO_LIPSYNC_NORMALIZED_LIPSYNC_PARAM GENMASK(7, 0) -+#define TX_AUDIO_CONTROL 0x005D -+ #define TX_AUDIO_CONTROL_FORCED_AUDIO_FIFO_CLEAR BIT(7) -+ #define TX_AUDIO_CONTROL_AUTO_AUDIO_FIFO_CLEAR BIT(6) -+ #define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_MASK GENMASK(5, 4) -+ #define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_AUDIO_SAMPLE_PACKET 0x0 -+ #define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_ONE_BIT_AUDIO 0x1 -+ #define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_HBR_AUDIO_PACKET 0x2 -+ #define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_DST_AUDIO_PACKET 0x3 -+ #define TX_AUDIO_CONTROL_AUDIO_SAMPLE_PACKET_VALID BIT(2) -+ #define TX_AUDIO_CONTROL_AUDIO_SAMPLE_PACKET_USER BIT(1) -+ #define TX_AUDIO_CONTROL_AUDIO_SAMPLE_PACKET_FLAT BIT(0) -+#define TX_AUDIO_HEADER 0x005E -+ #define TX_AUDIO_HEADER_AUDIO_SAMPLE_PACKET_HEADER_LAYOUT BIT(7) -+ #define TX_AUDIO_HEADER_SET_NORMAL_DOUBLE_IN_DST_PACKET_HEADER BIT(6) -+#define TX_AUDIO_SAMPLE 0x005F -+ #define TX_AUDIO_SAMPLE_CHANNEL_VALID GENMASK(7, 0) -+#define TX_AUDIO_VALID 0x0060 -+#define TX_AUDIO_USER 0x0061 -+#define TX_AUDIO_PACK 0x0062 -+ #define TX_AUDIO_PACK_AUDIO_SAMPLE_PACKETS_ENABLE BIT(0) -+#define TX_AUDIO_CONTROL_MORE 0x0064 -+ #define TX_AUDIO_CONTROL_MORE_ENABLE BIT(0) -+ -+// tmds config -+#define TX_TMDS_MODE 0x0068 -+ #define TX_TMDS_MODE_FORCED_HDMI BIT(7) -+ #define TX_TMDS_MODE_HDMI_CONFIG BIT(6) -+ #define TX_TMDS_MODE_BIT_SWAP BIT(3) -+ #define TX_TMDS_MODE_CHANNEL_SWAP GENMASK(2, 0) -+ -+#define TX_TMDS_CONFIG0 0x006C -+#define TX_TMDS_CONFIG1 0x006D -+ -+// packet config -+#define TX_PACKET_ALLOC_ACTIVE_1 0x0078 -+#define TX_PACKET_ALLOC_ACTIVE_2 0x0079 -+#define TX_PACKET_ALLOC_EOF_1 0x007A -+#define TX_PACKET_ALLOC_EOF_2 0x007B -+#define TX_PACKET_ALLOC_SOF_1 0x007C -+#define TX_PACKET_ALLOC_SOF_2 0x007D -+#define TX_PACKET_CONTROL_1 0x007E -+ #define TX_PACKET_CONTROL_1_FORCE_PACKET_TIMING BIT(7) -+ #define TX_PACKET_CONTROL_1_PACKET_ALLOC_MODE BIT(6) -+ #define TX_PACKET_CONTROL_1_PACKET_START_LATENCY GENMASK(5, 0) -+ -+#define TX_PACKET_CONTROL_2 0x007F -+ #define TX_PACKET_CONTROL_2_AUDIO_REQUEST_DISABLE BIT(3) -+ #define TX_PACKET_CONTROL_2_HORIZONTAL_GC_PACKET_TRANSPORT_EN BIT(1) -+ -+#define TX_CORE_EDID_CONFIG_MORE 0x0080 -+ #define TX_CORE_EDID_CONFIG_MORE_KEEP_EDID_ERROR BIT(1) -+ #define TX_CORE_EDID_CONFIG_MORE_SYS_TRIGGER_CONFIG_SEMI_MANU BIT(0) -+ -+#define TX_CORE_ALLOC_VSYNC_0 0x0081 -+#define TX_CORE_ALLOC_VSYNC_1 0x0082 -+#define TX_CORE_ALLOC_VSYNC_2 0x0083 -+#define TX_MEM_PD_REG0 0x0084 -+ -+// core config -+#define TX_CORE_DATA_CAPTURE_1 0x00F0 -+#define TX_CORE_DATA_CAPTURE_2 0x00F1 -+ #define TX_CORE_DATA_CAPTURE_2_AUDIO_SOURCE_SELECT GENMASK(7, 6) -+ #define TX_CORE_DATA_CAPTURE_2_EXTERNAL_PACKET_ENABLE BIT(5) -+ #define TX_CORE_DATA_CAPTURE_2_INTERNAL_PACKET_ENABLE BIT(4) -+ #define TX_CORE_DATA_CAPTURE_2_AFE_FIFO_SRC_LANE1 GENMASK(3, 2) -+ #define TX_CORE_DATA_CAPTURE_2_AFE_FIFO_SRC_LANE0 GENMASK(1, 0) -+ -+#define TX_CORE_DATA_MONITOR_1 0x00F2 -+ #define TX_CORE_DATA_MONITOR_1_LANE1 BIT(7) -+ #define TX_CORE_DATA_MONITOR_1_SELECT_LANE1 GENMASK(6, 4) -+ #define TX_CORE_DATA_MONITOR_1_LANE0 BIT(3) -+ #define TX_CORE_DATA_MONITOR_1_SELECT_LANE0 GENMASK(2, 0) -+ -+#define TX_CORE_DATA_MONITOR_2 0x00F3 -+ #define TX_CORE_DATA_MONITOR_2_MONITOR_SELECT GENMASK(2, 0) -+ -+#define TX_CORE_CALIB_MODE 0x00F4 -+#define TX_CORE_CALIB_SAMPLE_DELAY 0x00F5 -+#define TX_CORE_CALIB_VALUE_AUTO 0x00F6 -+#define TX_CORE_CALIB_VALUE 0x00F7 -+ -+// system config 4 -+#define TX_SYS4_TX_CKI_DDR 0x00A0 -+#define TX_SYS4_TX_CKO_DDR 0x00A1 -+#define TX_SYS4_RX_CKI_DDR 0x00A2 -+#define TX_SYS4_RX_CKO_DDR 0x00A3 -+#define TX_SYS4_CONNECT_SEL_0 0x00A4 -+#define TX_SYS4_CONNECT_SEL_1 0x00A5 -+ #define TX_SYS4_CONNECT_SEL_1_TX_CONNECT_SEL_UPPER_CHANNEL_DATA BIT(6) -+ -+#define TX_SYS4_CONNECT_SEL_2 0x00A6 -+#define TX_SYS4_CONNECT_SEL_3 0x00A7 -+#define TX_SYS4_CK_INV_VIDEO 0x00A8 -+ #define TX_SYS4_CK_INV_VIDEO_TMDS_CLK_PATTERN BIT(4) -+#define TX_SYS4_CK_INV_AUDIO 0x00A9 -+#define TX_SYS4_CK_INV_AFE 0x00AA -+#define TX_SYS4_CK_INV_CH01 0x00AB -+#define TX_SYS4_CK_INV_CH2 0x00AC -+#define TX_SYS4_CK_CEC 0x00AD -+#define TX_SYS4_CK_SOURCE_1 0x00AE -+#define TX_SYS4_CK_SOURCE_2 0x00AF -+ -+#define TX_IEC60958_SUB1_OFFSET 0x00B0 -+#define TX_IEC60958_SUB2_OFFSET 0x00C8 -+ -+// system config 5 -+#define TX_SYS5_TX_SOFT_RESET_1 0x00E0 -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_PIXEL_RSTN BIT(7) -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_TMDS_RSTN BIT(6) -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_MASTER_RSTN BIT(5) -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_RESAMPLE_RSTN BIT(4) -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_I2S_RESET_RSTN BIT(3) -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH2 BIT(2) -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH1 BIT(1) -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH0 BIT(0) -+ -+#define TX_SYS5_TX_SOFT_RESET_2 0x00E1 -+ #define TX_SYS5_TX_SOFT_RESET_2_HDMI_CH3_RST_IN BIT(7) -+ #define TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN BIT(6) -+ #define TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN BIT(5) -+ #define TX_SYS5_TX_SOFT_RESET_2_HDMI_CH0_RST_IN BIT(4) -+ #define TX_SYS5_TX_SOFT_RESET_2_HDMI_SR_RST BIT(3) -+ #define TX_SYS5_TX_SOFT_RESET_2_TX_DDC_HDCP_RSTN BIT(2) -+ #define TX_SYS5_TX_SOFT_RESET_2_TX_DDC_EDID_RSTN BIT(1) -+ #define TX_SYS5_TX_SOFT_RESET_2_TX_DIG_RESET_N_CH3 BIT(0) -+ -+#define TX_SYS5_RX_SOFT_RESET_1 0x00E2 -+#define TX_SYS5_RX_SOFT_RESET_2 0x00E3 -+#define TX_SYS5_RX_SOFT_RESET_3 0x00E4 -+#define TX_SYS5_SSTL_BIDIR_IN 0x00E5 -+#define TX_SYS5_SSTL_IN 0x00E6 -+#define TX_SYS5_SSTL_DIFF_IN 0x00E7 -+#define TX_SYS5_FIFO_CONFIG 0x00E8 -+ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL2_BYPASS BIT(6) -+ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL1_BYPASS BIT(5) -+ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL0_BYPASS BIT(4) -+ #define TX_SYS5_FIFO_CONFIG_CLK_CHANNEL3_OUTPUT_ENABLE BIT(3) -+ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL2_ENABLE BIT(2) -+ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL1_ENABLE BIT(1) -+ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL0_ENABLE BIT(0) -+ -+#define TX_SYS5_FIFO_SAMP01_CFG 0x00E9 -+#define TX_SYS5_FIFO_SAMP23_CFG 0x00EA -+#define TX_SYS5_CONNECT_FIFO_CFG 0x00EB -+#define TX_SYS5_IO_CALIB_CONTROL 0x00EC -+#define TX_SYS5_SSTL_BIDIR_OUT 0x00ED -+#define TX_SYS5_SSTL_OUT 0x00EE -+#define TX_SYS5_SSTL_DIFF_OUT 0x00EF -+ -+// HDCP shadow register -+#define TX_HDCP_SHW_BKSV_0 0x0100 -+#define TX_HDCP_SHW_BKSV_1 0x0101 -+#define TX_HDCP_SHW_BKSV_2 0x0102 -+#define TX_HDCP_SHW_BKSV_3 0x0103 -+#define TX_HDCP_SHW_BKSV_4 0x0104 -+#define TX_HDCP_SHW_RI1_0 0x0108 -+#define TX_HDCP_SHW_RI1_1 0x0109 -+#define TX_HDCP_SHW_PJ1 0x010A -+#define TX_HDCP_SHW_AKSV_0 0x0110 -+#define TX_HDCP_SHW_AKSV_1 0x0111 -+#define TX_HDCP_SHW_AKSV_2 0x0112 -+#define TX_HDCP_SHW_AKSV_3 0x0113 -+#define TX_HDCP_SHW_AKSV_4 0x0114 -+#define TX_HDCP_SHW_AINFO 0x0115 -+#define TX_HDCP_SHW_AN_0 0x0118 -+#define TX_HDCP_SHW_AN_1 0x0119 -+#define TX_HDCP_SHW_AN_2 0x011A -+#define TX_HDCP_SHW_AN_3 0x011B -+#define TX_HDCP_SHW_AN_4 0x011C -+#define TX_HDCP_SHW_AN_5 0x011D -+#define TX_HDCP_SHW_AN_6 0x011E -+#define TX_HDCP_SHW_AN_7 0x011F -+#define TX_HDCP_SHW_V1_H0_0 0x0120 -+#define TX_HDCP_SHW_V1_H0_1 0x0121 -+#define TX_HDCP_SHW_V1_H0_2 0x0122 -+#define TX_HDCP_SHW_V1_H0_3 0x0123 -+#define TX_HDCP_SHW_V1_H1_0 0x0124 -+#define TX_HDCP_SHW_V1_H1_1 0x0125 -+#define TX_HDCP_SHW_V1_H1_2 0x0126 -+#define TX_HDCP_SHW_V1_H1_3 0x0127 -+#define TX_HDCP_SHW_V1_H2_0 0x0128 -+#define TX_HDCP_SHW_V1_H2_1 0x0129 -+#define TX_HDCP_SHW_V1_H2_2 0x012A -+#define TX_HDCP_SHW_V1_H2_3 0x012B -+#define TX_HDCP_SHW_V1_H3_0 0x012C -+#define TX_HDCP_SHW_V1_H3_1 0x012D -+#define TX_HDCP_SHW_V1_H3_2 0x012E -+#define TX_HDCP_SHW_V1_H3_3 0x012F -+#define TX_HDCP_SHW_V1_H4_0 0x0130 -+#define TX_HDCP_SHW_V1_H4_1 0x0131 -+#define TX_HDCP_SHW_V1_H4_2 0x0132 -+#define TX_HDCP_SHW_V1_H4_3 0x0133 -+#define TX_HDCP_SHW_BCAPS 0x0140 -+#define TX_HDCP_SHW_BSTATUS_0 0x0141 -+#define TX_HDCP_SHW_BSTATUS_1 0x0142 -+#define TX_HDCP_SHW_KSV_FIFO 0x0143 -+ -+// system status 0 -+#define TX_SYSST0_CONNECT_FIFO 0x0180 -+#define TX_SYSST0_PLL_MONITOR 0x0181 -+#define TX_SYSST0_AFE_FIFO 0x0182 -+#define TX_SYSST0_ROM_STATUS 0x018F -+ -+// hdcp status -+#define TX_HDCP_ST_AUTHENTICATION 0x0190 -+#define TX_HDCP_ST_FRAME_COUNT 0x0191 -+#define TX_HDCP_ST_STATUS_0 0x0192 -+#define TX_HDCP_ST_STATUS_1 0x0193 -+#define TX_HDCP_ST_STATUS_2 0x0194 -+#define TX_HDCP_ST_STATUS_3 0x0195 -+#define TX_HDCP_ST_EDID_STATUS 0x0196 -+ #define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS GENMASK(7, 6) -+ #define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS_NO_SINK_ATTACHED 0x0 -+ #define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS_READING_EDID 0x1 -+ #define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS_DVI_MODE 0x2 -+ #define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS_HDMI_MODE 0x3 -+ #define TX_HDCP_ST_EDID_STATUS_EDID_DATA_READY BIT(4) -+ #define TX_HDCP_ST_EDID_STATUS_HPD_STATUS BIT(1) -+ -+#define TX_HDCP_ST_MEM_STATUS 0x0197 -+#define TX_HDCP_ST_ST_MODE 0x019F -+ -+// video status -+#define TX_VIDEO_ST_ACTIVE_PIXELS_1 0x01A0 -+#define TX_VIDEO_ST_ACTIVE_PIXELS_2 0x01A1 -+#define TX_VIDEO_ST_FRONT_PIXELS 0x01A2 -+#define TX_VIDEO_ST_HSYNC_PIXELS 0x01A3 -+#define TX_VIDEO_ST_BACK_PIXELS 0x01A4 -+#define TX_VIDEO_ST_ACTIVE_LINES_1 0x01A5 -+#define TX_VIDEO_ST_ACTIVE_LINES_2 0x01A6 -+#define TX_VIDEO_ST_EOF_LINES 0x01A7 -+#define TX_VIDEO_ST_VSYNC_LINES 0x01A8 -+#define TX_VIDEO_ST_SOF_LINES 0x01A9 -+#define TX_VIDEO_ST_DTV_TIMING 0x01AA -+#define TX_VIDEO_ST_DTV_MODE 0x01AB -+// audio status -+#define TX_VIDEO_ST_AUDIO_STATUS 0x01AC -+#define TX_AFE_STATUS_0 0x01AE -+#define TX_AFE_STATUS_1 0x01AF -+ -+#define TX_IEC60958_ST_SUB1_OFFSET 0x01B0 -+#define TX_IEC60958_ST_SUB2_OFFSET 0x01C8 -+ -+// system status 1 -+#define TX_SYSST1_CALIB_BIT_RESULT_0 0x01E0 -+#define TX_SYSST1_CALIB_BIT_RESULT_1 0x01E1 -+//HDMI_STATUS_OUT[7:0] -+#define TX_HDMI_PHY_READBACK_0 0x01E2 -+//HDMI_COMP_OUT[4] -+//HDMI_STATUS_OUT[11:8] -+#define TX_HDMI_PHY_READBACK_1 0x01E3 -+#define TX_SYSST1_CALIB_BIT_RESULT_4 0x01E4 -+#define TX_SYSST1_CALIB_BIT_RESULT_5 0x01E5 -+#define TX_SYSST1_CALIB_BIT_RESULT_6 0x01E6 -+#define TX_SYSST1_CALIB_BIT_RESULT_7 0x01E7 -+#define TX_SYSST1_CALIB_BUS_RESULT_0 0x01E8 -+#define TX_SYSST1_CALIB_BUS_RESULT_1 0x01E9 -+#define TX_SYSST1_CALIB_BUS_RESULT_2 0x01EA -+#define TX_SYSST1_CALIB_BUS_RESULT_3 0x01EB -+#define TX_SYSST1_CALIB_BUS_RESULT_4 0x01EC -+#define TX_SYSST1_CALIB_BUS_RESULT_5 0x01ED -+#define TX_SYSST1_CALIB_BUS_RESULT_6 0x01EE -+#define TX_SYSST1_CALIB_BUS_RESULT_7 0x01EF -+ -+// Packet status -+#define TX_PACKET_ST_REQUEST_STATUS_1 0x01F0 -+#define TX_PACKET_ST_REQUEST_STATUS_2 0x01F1 -+#define TX_PACKET_ST_REQUEST_MISSED_1 0x01F2 -+#define TX_PACKET_ST_REQUEST_MISSED_2 0x01F3 -+#define TX_PACKET_ST_ENCODE_STATUS_0 0x01F4 -+#define TX_PACKET_ST_ENCODE_STATUS_1 0x01F5 -+#define TX_PACKET_ST_ENCODE_STATUS_2 0x01F6 -+#define TX_PACKET_ST_TIMER_STATUS 0x01F7 -+ -+// tmds status -+#define TX_TMDS_ST_CLOCK_METER_1 0x01F8 -+#define TX_TMDS_ST_CLOCK_METER_2 0x01F9 -+#define TX_TMDS_ST_CLOCK_METER_3 0x01FA -+#define TX_TMDS_ST_TMDS_STATUS_1 0x01FC -+#define TX_TMDS_ST_TMDS_STATUS_2 0x01FD -+#define TX_TMDS_ST_TMDS_STATUS_3 0x01FE -+#define TX_TMDS_ST_TMDS_STATUS_4 0x01FF -+ -+ -+// Packet register -+#define TX_PKT_REG_SPD_INFO_BASE_ADDR 0x0200 -+#define TX_PKT_REG_VEND_INFO_BASE_ADDR 0x0220 -+#define TX_PKT_REG_MPEG_INFO_BASE_ADDR 0x0240 -+#define TX_PKT_REG_AVI_INFO_BASE_ADDR 0x0260 -+#define TX_PKT_REG_AUDIO_INFO_BASE_ADDR 0x0280 -+#define TX_PKT_REG_ACP_INFO_BASE_ADDR 0x02A0 -+#define TX_PKT_REG_ISRC1_BASE_ADDR 0x02C0 -+#define TX_PKT_REG_ISRC2_BASE_ADDR 0x02E0 -+#define TX_PKT_REG_EXCEPT0_BASE_ADDR 0x0300 -+#define TX_PKT_REG_EXCEPT1_BASE_ADDR 0x0320 -+#define TX_PKT_REG_EXCEPT2_BASE_ADDR 0x0340 -+#define TX_PKT_REG_EXCEPT3_BASE_ADDR 0x0360 -+#define TX_PKT_REG_EXCEPT4_BASE_ADDR 0x0380 -+#define TX_PKT_REG_GAMUT_P0_BASE_ADDR 0x03A0 -+#define TX_PKT_REG_GAMUT_P1_1_BASE_ADDR 0x03C0 -+#define TX_PKT_REG_GAMUT_P1_2_BASE_ADDR 0x03E0 -+ -+#define TX_RX_EDID_OFFSET 0x0600 -+ -+/* HDMI OTHER registers */ -+ -+#define HDMI_OTHER_CTRL0 0x8000 -+#define HDMI_OTHER_CTRL1 0x8001 -+ #define HDMI_OTHER_CTRL1_POWER_ON BIT(15) -+ #define HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON BIT(13) -+ -+#define HDMI_OTHER_STATUS0 0x8002 -+#define HDMI_OTHER_CTRL2 0x8003 -+#define HDMI_OTHER_INTR_MASKN 0x8004 -+ #define HDMI_OTHER_INTR_MASKN_TX_EDID_INT_RISE BIT(2) -+ #define HDMI_OTHER_INTR_MASKN_TX_HPD_INT_FALL BIT(1) -+ #define HDMI_OTHER_INTR_MASKN_TX_HPD_INT_RISE BIT(0) -+ -+#define HDMI_OTHER_INTR_STAT 0x8005 -+ #define HDMI_OTHER_INTR_STAT_EDID_RISING BIT(2) -+ #define HDMI_OTHER_INTR_STAT_HPD_FALLING BIT(1) -+ #define HDMI_OTHER_INTR_STAT_HPD_RISING BIT(0) -+ -+#define HDMI_OTHER_INTR_STAT_CLR 0x8006 -+ #define HDMI_OTHER_INTR_STAT_CLR_EDID_RISING BIT(2) -+ #define HDMI_OTHER_INTR_STAT_CLR_HPD_FALLING BIT(1) -+ #define HDMI_OTHER_INTR_STAT_CLR_HPD_RISING BIT(0) -+ -+#define HDMI_OTHER_AVI_INTR_MASKN0 0x8008 -+#define HDMI_OTHER_AVI_INTR_MASKN1 0x8009 -+#define HDMI_OTHER_RX_AINFO_INTR_MASKN0 0x800a -+#define HDMI_OTHER_RX_AINFO_INTR_MASKN1 0x800b -+#define HDMI_OTHER_RX_PACKET_INTR_CLR 0x800c -+ -+#endif /* __TXCCQ_TXC_84352_H__ */ -diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig -index 9f9281dd4..d4d4bb20e 100644 ---- a/drivers/gpu/drm/meson/Kconfig -+++ b/drivers/gpu/drm/meson/Kconfig -@@ -16,3 +16,10 @@ config DRM_MESON_DW_HDMI - default y if DRM_MESON - select DRM_DW_HDMI - imply DRM_DW_HDMI_I2S_AUDIO -+ -+config DRM_MESON_MX_HDMI -+ tristate "Amlogic Meson8/Meson8b HDMI Controller support" -+ depends on ARM || COMPILE_TEST -+ depends on DRM_MESON -+ default y if DRM_MESON -+ select DRM_TRANSWITCH_TXC_48352 -diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile -index 28a519cdf..1ef803c0a 100644 ---- a/drivers/gpu/drm/meson/Makefile -+++ b/drivers/gpu/drm/meson/Makefile -@@ -5,3 +5,4 @@ meson-drm-y += meson_rdma.o meson_osd_afbcd.o - - obj-$(CONFIG_DRM_MESON) += meson-drm.o - obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o -+obj-$(CONFIG_DRM_MESON_MX_HDMI) += meson_mx_hdmi.o -diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c -index 728fea509..c86517868 100644 ---- a/drivers/gpu/drm/meson/meson_drv.c -+++ b/drivers/gpu/drm/meson/meson_drv.c -@@ -9,7 +9,9 @@ - */ - - #include -+#include - #include -+#include - #include - #include - #include -@@ -90,7 +92,7 @@ static int meson_dumb_create(struct drm_file *file, struct drm_device *dev, - - DEFINE_DRM_GEM_CMA_FOPS(fops); - --static struct drm_driver meson_driver = { -+static const struct drm_driver meson_driver = { - .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, - - /* IRQ */ -@@ -132,28 +134,132 @@ static struct regmap_config meson_regmap_config = { - - static void meson_vpu_init(struct meson_drm *priv) - { -- u32 value; -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { -+ writel(0x0, priv->io_base + _REG(VPU_MEM_PD_REG0)); -+ writel(0x0, priv->io_base + _REG(VPU_MEM_PD_REG1)); -+ } else { -+ u32 value; -+ -+ /* -+ * Slave dc0 and dc5 connected to master port 1. -+ * By default other slaves are connected to master port 0. -+ */ -+ value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) | -+ VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1); -+ writel_relaxed(value, -+ priv->io_base + _REG(VPU_RDARB_MODE_L1C1)); -+ -+ /* Slave dc0 connected to master port 1 */ -+ value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1); -+ writel_relaxed(value, -+ priv->io_base + _REG(VPU_RDARB_MODE_L1C2)); -+ -+ /* Slave dc4 and dc7 connected to master port 1 */ -+ value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) | -+ VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1); -+ writel_relaxed(value, -+ priv->io_base + _REG(VPU_RDARB_MODE_L2C1)); -+ -+ /* Slave dc1 connected to master port 1 */ -+ value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1); -+ writel_relaxed(value, -+ priv->io_base + _REG(VPU_WRARB_MODE_L2C1)); -+ } -+} - -- /* -- * Slave dc0 and dc5 connected to master port 1. -- * By default other slaves are connected to master port 0. -- */ -- value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) | -- VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1); -- writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1)); -- -- /* Slave dc0 connected to master port 1 */ -- value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1); -- writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2)); -- -- /* Slave dc4 and dc7 connected to master port 1 */ -- value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) | -- VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1); -- writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1)); -- -- /* Slave dc1 connected to master port 1 */ -- value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1); -- writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1)); -+static int meson_video_clock_init(struct meson_drm *priv) -+{ -+ int i, ret; -+ -+ if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) -+ return 0; -+ -+ for (i = 0; i < ARRAY_SIZE(priv->vid_pll_resets); i++) { -+ ret = reset_control_deassert(priv->vid_pll_resets[i]); -+ if (ret) -+ goto assert_resets; -+ } -+ -+ ret = clk_bulk_prepare_enable(VPU_VID_CLK_NUM, priv->vid_clks); -+ if (ret) -+ goto assert_resets; -+ -+ ret = clk_rate_exclusive_get(priv->vid_clks[VPU_VID_CLK_TMDS].clk); -+ if (ret) -+ goto disable_clks; -+ -+ ret = clk_bulk_prepare_enable(VPU_INTR_CLK_NUM, priv->intr_clks); -+ if (ret) -+ goto put_exclusive_clk; -+ -+ return 0; -+ -+put_exclusive_clk: -+ clk_rate_exclusive_put(priv->vid_clks[VPU_VID_CLK_TMDS].clk); -+assert_resets: -+ for (; i > 0; i++) -+ reset_control_assert(priv->vid_pll_resets[i - 1]); -+disable_clks: -+ clk_bulk_disable_unprepare(VPU_VID_CLK_NUM, priv->vid_clks); -+ -+ return ret; -+} -+ -+static void meson_video_clock_exit(struct meson_drm *priv) -+{ -+ unsigned int i; -+ -+ if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) -+ return; -+ -+ clk_bulk_disable_unprepare(VPU_INTR_CLK_NUM, priv->intr_clks); -+ -+ clk_rate_exclusive_put(priv->clk_venc); -+ clk_rate_exclusive_put(priv->vid_clks[VPU_VID_CLK_TMDS].clk); -+ -+ clk_bulk_disable_unprepare(VPU_VID_CLK_NUM, priv->vid_clks); -+ -+ for (i = 0; i < ARRAY_SIZE(priv->vid_pll_resets); i++) -+ reset_control_assert(priv->vid_pll_resets[i]); -+} -+ -+static int meson_cvbs_trimming_init(struct meson_drm *priv) -+{ -+ struct nvmem_cell *cell; -+ u8 *trimming; -+ size_t len; -+ -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { -+ cell = devm_nvmem_cell_get(priv->dev, "cvbs_trimming"); -+ if (IS_ERR(cell)) -+ return PTR_ERR(cell); -+ -+ trimming = nvmem_cell_read(cell, &len); -+ if (IS_ERR(trimming)) -+ return PTR_ERR(trimming); -+ -+ if (len != 2) -+ return -EINVAL; -+ -+ if ((trimming[1] & 0xf0) == 0xa0 || -+ (trimming[1] & 0xf0) == 0x40 || -+ (trimming[1] & 0xc0) == 0x80) -+ priv->cvbs.cntl1 = trimming[0] & 0x7; -+ else -+ priv->cvbs.cntl1 = 0x0; -+ } else { -+ priv->cvbs.cntl1 = 0x0; -+ } -+ -+ return 0; - } - - static void meson_remove_framebuffers(void) -@@ -173,12 +279,44 @@ static void meson_remove_framebuffers(void) - kfree(ap); - } - -+static void meson_fbdev_setup(struct meson_drm *priv) -+{ -+ unsigned int preferred_bpp; -+ -+ /* -+ * All SoC generations before GXBB don't have a way to configure the -+ * alpha value for DRM_FORMAT_XRGB8888 and DRM_FORMAT_XBGR8888 with -+ * 32-bit but missing alpha ??? TODO: better explanation here. -+ * Use 24-bit to get a working framebuffer console. Applications that -+ * can do better (for example: kmscube) will switch to a better format -+ * like DRM_FORMAT_XRGB8888 while passing a sane alpha value. -+ */ -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) -+ preferred_bpp = 24; -+ else -+ preferred_bpp = 32; -+ -+ drm_fbdev_generic_setup(priv->drm, preferred_bpp); -+} -+ - struct meson_drm_soc_attr { - struct meson_drm_soc_limits limits; - const struct soc_device_attribute *attrs; - }; - - static const struct meson_drm_soc_attr meson_drm_soc_attrs[] = { -+ /* The maximum frequency of HDMI PLL on Meson8/8b/8m2 is ~3GHz */ -+ { -+ .limits = { -+ .max_hdmi_phy_freq = 2976000, -+ }, -+ .attrs = (const struct soc_device_attribute []) { -+ { .soc_id = "Meson8*", }, -+ { /* sentinel */ }, -+ } -+ }, - /* S805X/S805Y HDMI PLL won't lock for HDMI PHY freq > 1,65GHz */ - { - .limits = { -@@ -226,6 +364,51 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) - priv->compat = match->compat; - priv->afbcd.ops = match->afbcd_ops; - -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { -+ priv->vid_pll_resets[0] = devm_reset_control_get_exclusive(dev, "vid_pll_pre"); -+ if (IS_ERR(priv->vid_pll_resets[0])) -+ return PTR_ERR(priv->vid_pll_resets[0]); -+ -+ priv->vid_pll_resets[1] = devm_reset_control_get_exclusive(dev, "vid_pll_post"); -+ if (IS_ERR(priv->vid_pll_resets[1])) -+ return PTR_ERR(priv->vid_pll_resets[1]); -+ -+ priv->vid_pll_resets[2] = devm_reset_control_get_exclusive(dev, "vid_pll_soft_pre"); -+ if (IS_ERR(priv->vid_pll_resets[2])) -+ return PTR_ERR(priv->vid_pll_resets[2]); -+ -+ priv->vid_pll_resets[3] = devm_reset_control_get_exclusive(dev, "vid_pll_soft_post"); -+ if (IS_ERR(priv->vid_pll_resets[3])) -+ return PTR_ERR(priv->vid_pll_resets[3]); -+ -+ priv->intr_clks[VPU_INTR_CLK_VPU].id = "vpu_intr"; -+ priv->intr_clks[VPU_INTR_CLK_HDMI_INTR_SYNC].id = "hdmi_intr_sync"; -+ priv->intr_clks[VPU_INTR_CLK_VENCI].id = "venci_int"; -+ -+ ret = devm_clk_bulk_get(dev, VPU_INTR_CLK_NUM, priv->intr_clks); -+ if (ret) -+ return ret; -+ -+ priv->vid_clks[VPU_VID_CLK_TMDS].id = "tmds"; -+ priv->vid_clks[VPU_VID_CLK_HDMI_TX_PIXEL].id = "hdmi_tx_pixel"; -+ priv->vid_clks[VPU_VID_CLK_CTS_ENCP].id = "cts_encp"; -+ priv->vid_clks[VPU_VID_CLK_CTS_ENCI].id = "cts_enci"; -+ priv->vid_clks[VPU_VID_CLK_CTS_ENCT].id = "cts_enct"; -+ priv->vid_clks[VPU_VID_CLK_CTS_ENCL].id = "cts_encl"; -+ priv->vid_clks[VPU_VID_CLK_CTS_VDAC0].id = "cts_vdac0"; -+ -+ ret = devm_clk_bulk_get(dev, VPU_VID_CLK_NUM, priv->vid_clks); -+ if (ret) -+ return ret; -+ -+ ret = meson_video_clock_init(priv); -+ if (ret) -+ goto free_drm; -+ // TODO: error handling below -+ } -+ - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vpu"); - regs = devm_ioremap_resource(dev, res); - if (IS_ERR(regs)) { -@@ -235,24 +418,32 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) - - priv->io_base = regs; - -- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi"); -- if (!res) { -- ret = -EINVAL; -- goto free_drm; -- } -- /* Simply ioremap since it may be a shared register zone */ -- regs = devm_ioremap(dev, res->start, resource_size(res)); -- if (!regs) { -- ret = -EADDRNOTAVAIL; -- goto free_drm; -- } -- -- priv->hhi = devm_regmap_init_mmio(dev, regs, -- &meson_regmap_config); -+ priv->hhi = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, -+ "amlogic,hhi-sysctrl"); - if (IS_ERR(priv->hhi)) { -- dev_err(&pdev->dev, "Couldn't create the HHI regmap\n"); -- ret = PTR_ERR(priv->hhi); -- goto free_drm; -+ dev_dbg(dev, "Falling back to parsing the 'hhi' registers\n"); -+ -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi"); -+ if (!res) { -+ ret = -EINVAL; -+ goto free_drm; -+ } -+ -+ /* Simply ioremap since it may be a shared register zone */ -+ regs = devm_ioremap(dev, res->start, resource_size(res)); -+ if (!regs) { -+ ret = -EADDRNOTAVAIL; -+ goto free_drm; -+ } -+ -+ priv->hhi = devm_regmap_init_mmio(dev, regs, -+ &meson_regmap_config); -+ if (IS_ERR(priv->hhi)) { -+ dev_err(&pdev->dev, -+ "Couldn't create the HHI regmap\n"); -+ ret = PTR_ERR(priv->hhi); -+ goto free_drm; -+ } - } - - priv->canvas = meson_canvas_get(dev); -@@ -283,6 +474,10 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) - goto free_drm; - } - -+ ret = meson_cvbs_trimming_init(priv); -+ if (ret) -+ goto free_drm; -+ - priv->vsync_irq = platform_get_irq(pdev, 0); - - ret = drm_vblank_init(drm, 1); -@@ -360,7 +555,7 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) - if (ret) - goto uninstall_irq; - -- drm_fbdev_generic_setup(drm, 32); -+ meson_fbdev_setup(priv); - - return 0; - -@@ -396,8 +591,12 @@ static void meson_drv_unbind(struct device *dev) - drm_irq_uninstall(drm); - drm_dev_put(drm); - -- if (priv->afbcd.ops) -- priv->afbcd.ops->exit(priv); -+ if (priv->afbcd.ops) { -+ priv->afbcd.ops->reset(priv); -+ meson_rdma_free(priv); -+ } -+ -+ meson_video_clock_exit(priv); - } - - static const struct component_master_ops meson_drv_master_ops = { -@@ -412,6 +611,8 @@ static int __maybe_unused meson_drv_pm_suspend(struct device *dev) - if (!priv) - return 0; - -+ // TODO: video clock suspend -+ - return drm_mode_config_helper_suspend(priv->drm); - } - -@@ -422,6 +623,7 @@ static int __maybe_unused meson_drv_pm_resume(struct device *dev) - if (!priv) - return 0; - -+ meson_video_clock_init(priv); - meson_vpu_init(priv); - meson_venc_init(priv); - meson_vpp_init(priv); -@@ -480,17 +682,6 @@ static int meson_probe_remote(struct platform_device *pdev, - return count; - } - --static void meson_drv_shutdown(struct platform_device *pdev) --{ -- struct meson_drm *priv = dev_get_drvdata(&pdev->dev); -- -- if (!priv) -- return; -- -- drm_kms_helper_poll_fini(priv->drm); -- drm_atomic_helper_shutdown(priv->drm); --} -- - static int meson_drv_probe(struct platform_device *pdev) - { - struct component_match *match = NULL; -@@ -525,6 +716,18 @@ static int meson_drv_probe(struct platform_device *pdev) - return 0; - }; - -+static struct meson_drm_match_data meson_drm_m8_data = { -+ .compat = VPU_COMPATIBLE_M8, -+}; -+ -+static struct meson_drm_match_data meson_drm_m8b_data = { -+ .compat = VPU_COMPATIBLE_M8B, -+}; -+ -+static struct meson_drm_match_data meson_drm_m8m2_data = { -+ .compat = VPU_COMPATIBLE_M8M2, -+}; -+ - static struct meson_drm_match_data meson_drm_gxbb_data = { - .compat = VPU_COMPATIBLE_GXBB, - }; -@@ -544,6 +747,12 @@ static struct meson_drm_match_data meson_drm_g12a_data = { - }; - - static const struct of_device_id dt_match[] = { -+ { .compatible = "amlogic,meson8-vpu", -+ .data = (void *)&meson_drm_m8_data }, -+ { .compatible = "amlogic,meson8b-vpu", -+ .data = (void *)&meson_drm_m8b_data }, -+ { .compatible = "amlogic,meson8m2-vpu", -+ .data = (void *)&meson_drm_m8m2_data }, - { .compatible = "amlogic,meson-gxbb-vpu", - .data = (void *)&meson_drm_gxbb_data }, - { .compatible = "amlogic,meson-gxl-vpu", -@@ -562,7 +771,6 @@ static const struct dev_pm_ops meson_drv_pm_ops = { - static struct platform_driver meson_drm_platform_driver = { - .probe = meson_drv_probe, - .remove = meson_drv_remove, -- .shutdown = meson_drv_shutdown, - .driver = { - .name = "meson-drm", - .of_match_table = dt_match, -diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h -index 177dac3ca..399516842 100644 ---- a/drivers/gpu/drm/meson/meson_drv.h -+++ b/drivers/gpu/drm/meson/meson_drv.h -@@ -7,10 +7,12 @@ - #ifndef __MESON_DRV_H - #define __MESON_DRV_H - -+#include - #include - #include - #include - #include -+#include - - struct drm_crtc; - struct drm_device; -@@ -19,10 +21,13 @@ struct meson_drm; - struct meson_afbcd_ops; - - enum vpu_compatible { -- VPU_COMPATIBLE_GXBB = 0, -- VPU_COMPATIBLE_GXL = 1, -- VPU_COMPATIBLE_GXM = 2, -- VPU_COMPATIBLE_G12A = 3, -+ VPU_COMPATIBLE_M8 = 0, -+ VPU_COMPATIBLE_M8B = 1, -+ VPU_COMPATIBLE_M8M2 = 2, -+ VPU_COMPATIBLE_GXBB = 3, -+ VPU_COMPATIBLE_GXL = 4, -+ VPU_COMPATIBLE_GXM = 5, -+ VPU_COMPATIBLE_G12A = 6, - }; - - struct meson_drm_match_data { -@@ -34,6 +39,24 @@ struct meson_drm_soc_limits { - unsigned int max_hdmi_phy_freq; - }; - -+enum vpu_bulk_intr_clk_id { -+ VPU_INTR_CLK_VPU = 0, -+ VPU_INTR_CLK_HDMI_INTR_SYNC, -+ VPU_INTR_CLK_VENCI, -+ VPU_INTR_CLK_NUM -+}; -+ -+enum vpu_bulk_clk_id { -+ VPU_VID_CLK_TMDS = 0, -+ VPU_VID_CLK_HDMI_TX_PIXEL, -+ VPU_VID_CLK_CTS_ENCP, -+ VPU_VID_CLK_CTS_ENCI, -+ VPU_VID_CLK_CTS_ENCT, -+ VPU_VID_CLK_CTS_ENCL, -+ VPU_VID_CLK_CTS_VDAC0, -+ VPU_VID_CLK_NUM -+}; -+ - struct meson_drm { - struct device *dev; - enum vpu_compatible compat; -@@ -54,6 +77,12 @@ struct meson_drm { - - const struct meson_drm_soc_limits *limits; - -+ struct clk_bulk_data intr_clks[VPU_INTR_CLK_NUM]; -+ struct clk_bulk_data vid_clks[VPU_VID_CLK_NUM]; -+ struct clk *clk_venc; -+ struct clk *clk_dac; -+ struct reset_control *vid_pll_resets[4]; -+ - /* Components Data */ - struct { - bool osd1_enabled; -@@ -167,6 +196,10 @@ struct meson_drm { - u64 modifier; - u32 format; - } afbcd; -+ -+ struct { -+ uint32_t cntl1; -+ } cvbs; - }; - - static inline int meson_vpu_is_compatible(struct meson_drm *priv, -diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/meson_dw_hdmi.c -index aad75a22d..c01aac9e4 100644 ---- a/drivers/gpu/drm/meson/meson_dw_hdmi.c -+++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c -@@ -115,12 +115,6 @@ - - static DEFINE_SPINLOCK(reg_lock); - --enum meson_venc_source { -- MESON_VENC_SOURCE_NONE = 0, -- MESON_VENC_SOURCE_ENCI = 1, -- MESON_VENC_SOURCE_ENCP = 2, --}; -- - struct meson_dw_hdmi; - - struct meson_dw_hdmi_data { -@@ -430,8 +424,6 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, - { - struct meson_dw_hdmi *dw_hdmi = (struct meson_dw_hdmi *)data; - struct meson_drm *priv = dw_hdmi->priv; -- unsigned int wr_clk = -- readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING)); - - DRM_DEBUG_DRIVER("\"%s\" div%d\n", mode->name, - mode->clock > 340000 ? 40 : 10); -@@ -504,35 +496,7 @@ static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, - meson_dw_hdmi_phy_reset(dw_hdmi); - meson_dw_hdmi_phy_reset(dw_hdmi); - -- /* Temporary Disable VENC video stream */ -- if (priv->venc.hdmi_use_enci) -- writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); -- else -- writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); -- -- /* Temporary Disable HDMI video stream to HDMI-TX */ -- writel_bits_relaxed(0x3, 0, -- priv->io_base + _REG(VPU_HDMI_SETTING)); -- writel_bits_relaxed(0xf << 8, 0, -- priv->io_base + _REG(VPU_HDMI_SETTING)); -- -- /* Re-Enable VENC video stream */ -- if (priv->venc.hdmi_use_enci) -- writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); -- else -- writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); -- -- /* Push back HDMI clock settings */ -- writel_bits_relaxed(0xf << 8, wr_clk & (0xf << 8), -- priv->io_base + _REG(VPU_HDMI_SETTING)); -- -- /* Enable and Select HDMI video source for HDMI-TX */ -- if (priv->venc.hdmi_use_enci) -- writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCI, -- priv->io_base + _REG(VPU_HDMI_SETTING)); -- else -- writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCP, -- priv->io_base + _REG(VPU_HDMI_SETTING)); -+ meson_venc_hdmi_bridge_reset(priv); - - return 0; - } -@@ -716,12 +680,12 @@ static const struct drm_encoder_funcs meson_venc_hdmi_encoder_funcs = { - }; - - static u32 * --meson_venc_hdmi_encoder_get_inp_bus_fmts(struct drm_bridge *bridge, -- struct drm_bridge_state *bridge_state, -- struct drm_crtc_state *crtc_state, -- struct drm_connector_state *conn_state, -- u32 output_fmt, -- unsigned int *num_input_fmts) -+meson_dw_hdmi_encoder_get_inp_bus_fmts(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state, -+ u32 output_fmt, -+ unsigned int *num_input_fmts) - { - u32 *input_fmts = NULL; - int i; -@@ -746,7 +710,7 @@ meson_venc_hdmi_encoder_get_inp_bus_fmts(struct drm_bridge *bridge, - return input_fmts; - } - --static int meson_venc_hdmi_encoder_atomic_check(struct drm_bridge *bridge, -+static int meson_dw_hdmi_encoder_atomic_check(struct drm_bridge *bridge, - struct drm_bridge_state *bridge_state, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -@@ -760,34 +724,27 @@ static int meson_venc_hdmi_encoder_atomic_check(struct drm_bridge *bridge, - return 0; - } - --static void meson_venc_hdmi_encoder_disable(struct drm_bridge *bridge) -+static void meson_dw_hdmi_encoder_disable(struct drm_bridge *bridge) - { - struct meson_dw_hdmi *dw_hdmi = bridge_to_meson_dw_hdmi(bridge); - struct meson_drm *priv = dw_hdmi->priv; - - DRM_DEBUG_DRIVER("\n"); - -- writel_bits_relaxed(0x3, 0, -- priv->io_base + _REG(VPU_HDMI_SETTING)); -- -- writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); -- writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); -+ meson_venc_hdmi_encoder_disable(priv); - } - --static void meson_venc_hdmi_encoder_enable(struct drm_bridge *bridge) -+static void meson_dw_hdmi_encoder_enable(struct drm_bridge *bridge) - { - struct meson_dw_hdmi *dw_hdmi = bridge_to_meson_dw_hdmi(bridge); - struct meson_drm *priv = dw_hdmi->priv; - - DRM_DEBUG_DRIVER("%s\n", priv->venc.hdmi_use_enci ? "VENCI" : "VENCP"); - -- if (priv->venc.hdmi_use_enci) -- writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); -- else -- writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); -+ meson_venc_hdmi_encoder_enable(priv); - } - --static void meson_venc_hdmi_encoder_mode_set(struct drm_bridge *bridge, -+static void meson_dw_hdmi_encoder_mode_set(struct drm_bridge *bridge, - const struct drm_display_mode *mode, - const struct drm_display_mode *adjusted_mode) - { -@@ -822,12 +779,12 @@ static void meson_venc_hdmi_encoder_mode_set(struct drm_bridge *bridge, - static const struct drm_bridge_funcs meson_venc_hdmi_encoder_bridge_funcs = { - .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, -- .atomic_get_input_bus_fmts = meson_venc_hdmi_encoder_get_inp_bus_fmts, -+ .atomic_get_input_bus_fmts = meson_dw_hdmi_encoder_get_inp_bus_fmts, - .atomic_reset = drm_atomic_helper_bridge_reset, -- .atomic_check = meson_venc_hdmi_encoder_atomic_check, -- .enable = meson_venc_hdmi_encoder_enable, -- .disable = meson_venc_hdmi_encoder_disable, -- .mode_set = meson_venc_hdmi_encoder_mode_set, -+ .atomic_check = meson_dw_hdmi_encoder_atomic_check, -+ .enable = meson_dw_hdmi_encoder_enable, -+ .disable = meson_dw_hdmi_encoder_disable, -+ .mode_set = meson_dw_hdmi_encoder_mode_set, - }; - - /* DW HDMI Regmap */ -diff --git a/drivers/gpu/drm/meson/meson_mx_hdmi.c b/drivers/gpu/drm/meson/meson_mx_hdmi.c -new file mode 100644 -index 000000000..c2e7efa04 ---- /dev/null -+++ b/drivers/gpu/drm/meson/meson_mx_hdmi.c -@@ -0,0 +1,432 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2020 Martin Blumenstingl -+ * -+ * All registers and magic values are taken from Amlogic's GPL kernel sources: -+ * Copyright (C) 2010 Amlogic, Inc. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "meson_drv.h" -+#include "meson_registers.h" -+#include "meson_vclk.h" -+#include "meson_venc.h" -+ -+#define HDMI_ADDR_PORT 0x0 -+#define HDMI_DATA_PORT 0x4 -+#define HDMI_CTRL_PORT 0x8 -+ #define HDMI_CTRL_PORT_APB3_ERR_EN BIT(15) -+ -+struct meson_mx_hdmi { -+ struct device *dev; -+ struct drm_device *drm; -+ struct txc_48352 *txc_48352; -+ -+ struct clk *pclk; -+ -+ struct drm_encoder encoder; -+ struct drm_bridge bridge; -+ -+ unsigned int output_bus_format; -+}; -+ -+#define to_meson_mx_hdmi(x) container_of(x, struct meson_mx_hdmi, x) -+ -+static int meson_mx_hdmi_reg_read(void *context, unsigned int addr, -+ unsigned int *data) -+{ -+ void __iomem *base = context; -+ -+ writel(addr, base + HDMI_ADDR_PORT); -+ writel(addr, base + HDMI_ADDR_PORT); -+ -+ *data = readl(base + HDMI_DATA_PORT); -+ -+ return 0; -+} -+ -+static int meson_mx_hdmi_reg_write(void *context, unsigned int addr, -+ unsigned int data) -+{ -+ void __iomem *base = context; -+ -+ writel(addr, base + HDMI_ADDR_PORT); -+ writel(addr, base + HDMI_ADDR_PORT); -+ -+ writel(data, base + HDMI_DATA_PORT); -+ -+ return 0; -+} -+ -+static const struct regmap_config meson_mx_hdmi_bus_regmap_config = { -+ .name = "bus", -+ .reg_bits = 16, -+ .val_bits = 16, -+ .reg_stride = 1, -+ .reg_read = meson_mx_hdmi_reg_read, -+ .reg_write = meson_mx_hdmi_reg_write, -+ .fast_io = true, -+}; -+ -+static int meson_mx_hdmi_child_regmap_read(void *context, unsigned int addr, -+ unsigned int *data) -+{ -+ struct regmap *bus_regmap = context; -+ -+ return regmap_read(bus_regmap, addr, data); -+} -+ -+static int meson_mx_hdmi_child_regmap_write(void *context, unsigned int addr, -+ unsigned int data) -+{ -+ struct regmap *bus_regmap = context; -+ -+ return regmap_write(bus_regmap, addr, data); -+} -+ -+static const struct regmap_config meson_mx_hdmi_bridge_regmap_config = { -+ .name = "bridge", -+ .reg_bits = 16, -+ .val_bits = 8, -+ .reg_stride = 1, -+ .reg_read = meson_mx_hdmi_child_regmap_read, -+ .reg_write = meson_mx_hdmi_child_regmap_write, -+ .max_register = 0x7ff, -+ .fast_io = true, -+}; -+ -+static const struct regmap_range meson_mx_hdmi_other_regmap_ranges[] = { -+ regmap_reg_range(0x8000, 0x800c), -+}; -+ -+static const struct regmap_access_table meson_mx_hdmi_other_regmap_access = { -+ .yes_ranges = meson_mx_hdmi_other_regmap_ranges, -+ .n_yes_ranges = ARRAY_SIZE(meson_mx_hdmi_other_regmap_ranges), -+}; -+ -+static const struct regmap_config meson_mx_hdmi_other_regmap_config = { -+ .name = "other", -+ .reg_bits = 16, -+ .val_bits = 16, -+ .reg_stride = 1, -+ .reg_read = meson_mx_hdmi_child_regmap_read, -+ .reg_write = meson_mx_hdmi_child_regmap_write, -+ .rd_table = &meson_mx_hdmi_other_regmap_access, -+ .wr_table = &meson_mx_hdmi_other_regmap_access, -+ .max_register = 0xffff, -+ .fast_io = true, -+}; -+ -+static const u32 meson_mx_hdmi_bridge_input_bus_fmts[] = { -+ /* -+ * TODO: meson_plane.c unconditionally enables the RGB2YUV converter -+ * (OSD_OUTPUT_COLOR_RGB). Thus the output format (from the VPU) is -+ * always YUV444, whereas the hardware can toggle at least between -+ * RGB888 and YUV444). -+ * Thus MEDIA_BUS_FMT_RGB888_1X24 is omitted here for now. -+ */ -+ MEDIA_BUS_FMT_YUV8_1X24, -+}; -+ -+static u32 * -+meson_mx_hdmi_bridge_get_input_bus_fmts(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state, -+ u32 output_fmt, -+ unsigned int *num_input_fmts) -+{ -+ u32 *input_fmts; -+ int i; -+ -+ *num_input_fmts = 0; -+ -+ for (i = 0; i < ARRAY_SIZE(meson_mx_hdmi_bridge_input_bus_fmts) ; i++) { -+ if (output_fmt != meson_mx_hdmi_bridge_input_bus_fmts[i]) -+ continue; -+ -+ *num_input_fmts = 1; -+ input_fmts = kcalloc(*num_input_fmts, sizeof(*input_fmts), -+ GFP_KERNEL); -+ if (!input_fmts) -+ return NULL; -+ -+ input_fmts[0] = output_fmt; -+ -+ return input_fmts; -+ } -+ -+ return NULL; -+} -+ -+static int meson_mx_hdmi_bridge_atomic_check(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state) -+{ -+ struct meson_mx_hdmi *hdmi = to_meson_mx_hdmi(bridge); -+ -+ hdmi->output_bus_format = bridge_state->output_bus_cfg.format; -+ -+ return 0; -+} -+ -+static void meson_mx_hdmi_bridge_enable(struct drm_bridge *bridge) -+{ -+ struct meson_mx_hdmi *hdmi = to_meson_mx_hdmi(bridge); -+ struct meson_drm *priv = hdmi->drm->dev_private; -+ -+ meson_venc_hdmi_bridge_reset(priv); -+ -+ meson_venc_hdmi_encoder_enable(priv); -+} -+ -+static void meson_mx_hdmi_bridge_disable(struct drm_bridge *bridge) -+{ -+ struct meson_mx_hdmi *hdmi = to_meson_mx_hdmi(bridge); -+ struct meson_drm *priv = hdmi->drm->dev_private; -+ -+ meson_venc_hdmi_encoder_disable(priv); -+} -+ -+static void meson_mx_hdmi_bridge_mode_set(struct drm_bridge *bridge, -+ const struct drm_display_mode *mode, -+ const struct drm_display_mode *adj_mode) -+{ -+ unsigned int vclk_freq, venc_freq, hdmi_freq, phy_freq, ycrcb_map; -+ struct meson_mx_hdmi *hdmi = to_meson_mx_hdmi(bridge); -+ struct meson_drm *priv = hdmi->drm->dev_private; -+ int cea_mode = drm_match_cea_mode(mode); -+ -+ if (hdmi->output_bus_format == MEDIA_BUS_FMT_RGB888_1X24) -+ ycrcb_map = VPU_HDMI_OUTPUT_YCBCR; -+ else -+ ycrcb_map = VPU_HDMI_OUTPUT_CRYCB; -+ -+ /* VENC + VENC-DVI Mode setup */ -+ meson_venc_hdmi_mode_set(priv, cea_mode, ycrcb_map, false, mode); -+ -+ vclk_freq = mode->clock; -+ phy_freq = vclk_freq * 10; -+ -+ if (!cea_mode) { -+ meson_vclk_setup(priv, MESON_VCLK_TARGET_DMT, phy_freq, -+ vclk_freq, vclk_freq, vclk_freq, false); -+ } else { -+ if (mode->flags & DRM_MODE_FLAG_DBLCLK) -+ vclk_freq *= 2; -+ -+ venc_freq = vclk_freq; -+ hdmi_freq = vclk_freq; -+ -+ if (meson_venc_hdmi_venc_repeat(cea_mode)) -+ venc_freq *= 2; -+ -+ vclk_freq = max(venc_freq, hdmi_freq); -+ -+ if (mode->flags & DRM_MODE_FLAG_DBLCLK) -+ venc_freq /= 2; -+ -+ drm_dbg(hdmi->drm, "vclk:%d venc=%d hdmi=%d enci=%d\n", -+ vclk_freq, venc_freq, hdmi_freq, -+ priv->venc.hdmi_use_enci); -+ -+ meson_vclk_setup(priv, MESON_VCLK_TARGET_HDMI, phy_freq, -+ vclk_freq, venc_freq, hdmi_freq, -+ priv->venc.hdmi_use_enci); -+ } -+} -+ -+static const struct drm_bridge_funcs meson_mx_hdmi_bridge_funcs = { -+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, -+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, -+ .atomic_get_input_bus_fmts = meson_mx_hdmi_bridge_get_input_bus_fmts, -+ .atomic_reset = drm_atomic_helper_bridge_reset, -+ .atomic_check = meson_mx_hdmi_bridge_atomic_check, -+ .enable = meson_mx_hdmi_bridge_enable, -+ .disable = meson_mx_hdmi_bridge_disable, -+ .mode_set = meson_mx_hdmi_bridge_mode_set, -+}; -+ -+static const struct drm_encoder_funcs meson_mx_hdmi_encoder_funcs = { -+ .destroy = drm_encoder_cleanup, -+}; -+ -+static void meson_mx_hdmi_exit(struct meson_mx_hdmi *hdmi) -+{ -+ if (hdmi->txc_48352) -+ txc_48352_unbind(hdmi->txc_48352); -+ -+ drm_encoder_cleanup(&hdmi->encoder); -+ -+ clk_disable_unprepare(hdmi->pclk); -+} -+ -+static int meson_mx_hdmi_init(struct meson_mx_hdmi *hdmi, void __iomem *base) -+{ -+ struct drm_bridge *next_bridge; -+ u32 regval; -+ int ret; -+ -+ ret = clk_prepare_enable(hdmi->pclk); -+ if (ret) { -+ drm_err(hdmi->drm, "Failed to enable the pclk: %d\n", ret); -+ return ret; -+ } -+ -+ regval = readl(base + HDMI_CTRL_PORT); -+ regval |= HDMI_CTRL_PORT_APB3_ERR_EN; -+ writel(regval, base + HDMI_CTRL_PORT); -+ -+ hdmi->encoder.possible_crtcs = BIT(0); -+ ret = drm_encoder_init(hdmi->drm, &hdmi->encoder, -+ &meson_mx_hdmi_encoder_funcs, -+ DRM_MODE_ENCODER_TMDS, NULL); -+ if (ret) { -+ return ret; -+ goto err_disable_clk; -+ } -+ -+ hdmi->bridge.funcs = &meson_mx_hdmi_bridge_funcs; -+ ret = drm_bridge_attach(&hdmi->encoder, &hdmi->bridge, NULL, 0); -+ if (ret) { -+ return ret; -+ goto err_cleanup_encoder; -+ } -+ -+ hdmi->txc_48352 = txc_48352_bind(&hdmi->encoder, hdmi->dev); -+ if (IS_ERR(hdmi->txc_48352)) { -+ ret = PTR_ERR(hdmi->txc_48352); -+ goto err_cleanup_encoder; -+ } -+ -+ next_bridge = of_drm_find_bridge(hdmi->dev->of_node); -+ if (next_bridge) -+ drm_bridge_attach(&hdmi->encoder, next_bridge, -+ &hdmi->bridge, 0); -+ -+ return 0; -+ -+err_disable_clk: -+ clk_disable_unprepare(hdmi->pclk); -+err_cleanup_encoder: -+ drm_encoder_cleanup(&hdmi->encoder); -+ return ret; -+} -+ -+static int meson_mx_hdmi_bind(struct device *dev, struct device *master, -+ void *data) -+{ -+ struct platform_device *pdev = to_platform_device(dev); -+ struct regmap *bus_regmap, *child_regmap; -+ struct drm_device *drm = data; -+ struct meson_mx_hdmi *hdmi; -+ struct resource *res; -+ void __iomem *base; -+ int ret; -+ -+ hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); -+ if (!hdmi) -+ return -ENOMEM; -+ -+ hdmi->dev = dev; -+ hdmi->drm = drm; -+ -+ dev_set_drvdata(dev, hdmi); -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ base = devm_ioremap_resource(dev, res); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ bus_regmap = devm_regmap_init(dev, NULL, base, -+ &meson_mx_hdmi_bus_regmap_config); -+ if (IS_ERR(bus_regmap)) -+ return PTR_ERR(bus_regmap); -+ -+ child_regmap = devm_regmap_init(dev, NULL, bus_regmap, -+ &meson_mx_hdmi_bridge_regmap_config); -+ if (IS_ERR(child_regmap)) -+ return PTR_ERR(child_regmap); -+ -+ child_regmap = devm_regmap_init(dev, NULL, bus_regmap, -+ &meson_mx_hdmi_other_regmap_config); -+ if (IS_ERR(child_regmap)) -+ return PTR_ERR(child_regmap); -+ -+ hdmi->pclk = devm_clk_get(hdmi->dev, "pclk"); -+ if (IS_ERR(hdmi->pclk)) { -+ ret = PTR_ERR(hdmi->pclk); -+ drm_err(drm, "Failed to get the pclk: %d\n", ret); -+ return ret; -+ } -+ -+ ret = meson_mx_hdmi_init(hdmi, base); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+ -+static void meson_mx_hdmi_unbind(struct device *dev, struct device *master, -+ void *data) -+{ -+ struct meson_mx_hdmi *hdmi = dev_get_drvdata(dev); -+ -+ hdmi->encoder.funcs->destroy(&hdmi->encoder); -+ -+ meson_mx_hdmi_exit(hdmi); -+} -+ -+static const struct component_ops meson_mx_hdmi_component_ops = { -+ .bind = meson_mx_hdmi_bind, -+ .unbind = meson_mx_hdmi_unbind, -+}; -+ -+static int meson_mx_hdmi_probe(struct platform_device *pdev) -+{ -+ return component_add(&pdev->dev, &meson_mx_hdmi_component_ops); -+} -+ -+static int meson_mx_hdmi_remove(struct platform_device *pdev) -+{ -+ component_del(&pdev->dev, &meson_mx_hdmi_component_ops); -+ -+ return 0; -+} -+ -+static const struct of_device_id meson_mx_hdmi_of_table[] = { -+ { .compatible = "amlogic,meson8-hdmi-tx" }, -+ { .compatible = "amlogic,meson8b-hdmi-tx" }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, meson_mx_hdmi_of_table); -+ -+static struct platform_driver meson_mx_hdmi_platform_driver = { -+ .probe = meson_mx_hdmi_probe, -+ .remove = meson_mx_hdmi_remove, -+ .driver = { -+ .name = "meson-mx-hdmi", -+ .of_match_table = meson_mx_hdmi_of_table, -+ }, -+}; -+module_platform_driver(meson_mx_hdmi_platform_driver); -+ -+MODULE_AUTHOR("Martin Blumenstingl "); -+MODULE_DESCRIPTION("Amlogic Meson8 and Meson8b HDMI TX DRM driver"); -+MODULE_LICENSE("GPL v2"); -diff --git a/drivers/gpu/drm/meson/meson_osd_afbcd.c b/drivers/gpu/drm/meson/meson_osd_afbcd.c -index 0cdbe8994..ffc6b584d 100644 ---- a/drivers/gpu/drm/meson/meson_osd_afbcd.c -+++ b/drivers/gpu/drm/meson/meson_osd_afbcd.c -@@ -79,6 +79,11 @@ static bool meson_gxm_afbcd_supported_fmt(u64 modifier, uint32_t format) - return meson_gxm_afbcd_pixel_fmt(modifier, format) >= 0; - } - -+static int meson_gxm_afbcd_init(struct meson_drm *priv) -+{ -+ return 0; -+} -+ - static int meson_gxm_afbcd_reset(struct meson_drm *priv) - { - writel_relaxed(VIU_SW_RESET_OSD1_AFBCD, -@@ -88,16 +93,6 @@ static int meson_gxm_afbcd_reset(struct meson_drm *priv) - return 0; - } - --static int meson_gxm_afbcd_init(struct meson_drm *priv) --{ -- return 0; --} -- --static void meson_gxm_afbcd_exit(struct meson_drm *priv) --{ -- meson_gxm_afbcd_reset(priv); --} -- - static int meson_gxm_afbcd_enable(struct meson_drm *priv) - { - writel_relaxed(FIELD_PREP(OSD1_AFBCD_ID_FIFO_THRD, 0x40) | -@@ -177,7 +172,6 @@ static int meson_gxm_afbcd_setup(struct meson_drm *priv) - - struct meson_afbcd_ops meson_afbcd_gxm_ops = { - .init = meson_gxm_afbcd_init, -- .exit = meson_gxm_afbcd_exit, - .reset = meson_gxm_afbcd_reset, - .enable = meson_gxm_afbcd_enable, - .disable = meson_gxm_afbcd_disable, -@@ -275,18 +269,6 @@ static bool meson_g12a_afbcd_supported_fmt(u64 modifier, uint32_t format) - return meson_g12a_afbcd_pixel_fmt(modifier, format) >= 0; - } - --static int meson_g12a_afbcd_reset(struct meson_drm *priv) --{ -- meson_rdma_reset(priv); -- -- meson_rdma_writel_sync(priv, VIU_SW_RESET_G12A_AFBC_ARB | -- VIU_SW_RESET_G12A_OSD1_AFBCD, -- VIU_SW_RESET); -- meson_rdma_writel_sync(priv, 0, VIU_SW_RESET); -- -- return 0; --} -- - static int meson_g12a_afbcd_init(struct meson_drm *priv) - { - int ret; -@@ -304,10 +286,16 @@ static int meson_g12a_afbcd_init(struct meson_drm *priv) - return 0; - } - --static void meson_g12a_afbcd_exit(struct meson_drm *priv) -+static int meson_g12a_afbcd_reset(struct meson_drm *priv) - { -- meson_g12a_afbcd_reset(priv); -- meson_rdma_free(priv); -+ meson_rdma_reset(priv); -+ -+ meson_rdma_writel_sync(priv, VIU_SW_RESET_G12A_AFBC_ARB | -+ VIU_SW_RESET_G12A_OSD1_AFBCD, -+ VIU_SW_RESET); -+ meson_rdma_writel_sync(priv, 0, VIU_SW_RESET); -+ -+ return 0; - } - - static int meson_g12a_afbcd_enable(struct meson_drm *priv) -@@ -392,7 +380,6 @@ static int meson_g12a_afbcd_setup(struct meson_drm *priv) - - struct meson_afbcd_ops meson_afbcd_g12a_ops = { - .init = meson_g12a_afbcd_init, -- .exit = meson_g12a_afbcd_exit, - .reset = meson_g12a_afbcd_reset, - .enable = meson_g12a_afbcd_enable, - .disable = meson_g12a_afbcd_disable, -diff --git a/drivers/gpu/drm/meson/meson_osd_afbcd.h b/drivers/gpu/drm/meson/meson_osd_afbcd.h -index e77ddeb64..5e5523304 100644 ---- a/drivers/gpu/drm/meson/meson_osd_afbcd.h -+++ b/drivers/gpu/drm/meson/meson_osd_afbcd.h -@@ -14,7 +14,6 @@ - - struct meson_afbcd_ops { - int (*init)(struct meson_drm *priv); -- void (*exit)(struct meson_drm *priv); - int (*reset)(struct meson_drm *priv); - int (*enable)(struct meson_drm *priv); - int (*disable)(struct meson_drm *priv); -diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c -index 35338ed18..2c403624e 100644 ---- a/drivers/gpu/drm/meson/meson_plane.c -+++ b/drivers/gpu/drm/meson/meson_plane.c -@@ -194,8 +194,11 @@ static void meson_plane_atomic_update(struct drm_plane *plane, - priv->viu.osd1_ctrl_stat2 &= ~OSD_DPATH_MALI_AFBCD; - } - -- /* On GXBB, Use the old non-HDR RGB2YUV converter */ -- if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) -+ /* On GXBB and earlier, Use the old non-HDR RGB2YUV converter */ -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) - priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB; - - if (priv->viu.osd1_afbcd && -@@ -226,17 +229,21 @@ static void meson_plane_atomic_update(struct drm_plane *plane, - } - } - -- switch (fb->format->format) { -- case DRM_FORMAT_XRGB8888: -- case DRM_FORMAT_XBGR8888: -- /* For XRGB, replace the pixel's alpha by 0xFF */ -- priv->viu.osd1_ctrl_stat2 |= OSD_REPLACE_EN; -- break; -- case DRM_FORMAT_ARGB8888: -- case DRM_FORMAT_ABGR8888: -- /* For ARGB, use the pixel's alpha */ -- priv->viu.osd1_ctrl_stat2 &= ~OSD_REPLACE_EN; -- break; -+ if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { -+ switch (fb->format->format) { -+ case DRM_FORMAT_XRGB8888: -+ case DRM_FORMAT_XBGR8888: -+ /* For XRGB, replace the pixel's alpha by 0xFF */ -+ priv->viu.osd1_ctrl_stat2 |= OSD_REPLACE_EN; -+ break; -+ case DRM_FORMAT_ARGB8888: -+ case DRM_FORMAT_ABGR8888: -+ /* For ARGB, use the pixel's alpha */ -+ priv->viu.osd1_ctrl_stat2 &= ~OSD_REPLACE_EN; -+ break; -+ } - } - - /* Default scaler parameters */ -diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h -index 0f3cafab8..446e7961d 100644 ---- a/drivers/gpu/drm/meson/meson_registers.h -+++ b/drivers/gpu/drm/meson/meson_registers.h -@@ -634,11 +634,6 @@ - #define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2 0x3dbc - #define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd - --/* osd1 HDR */ --#define OSD1_HDR2_CTRL 0x38a0 --#define OSD1_HDR2_CTRL_VDIN0_HDR2_TOP_EN BIT(13) --#define OSD1_HDR2_CTRL_REG_ONLY_MAT BIT(16) -- - /* osd2 scaler */ - #define OSD2_VSC_PHASE_STEP 0x3d00 - #define OSD2_VSC_INI_PHASE 0x3d01 -diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c -index 0eb86943a..e14f5b84a 100644 ---- a/drivers/gpu/drm/meson/meson_vclk.c -+++ b/drivers/gpu/drm/meson/meson_vclk.c -@@ -131,7 +131,7 @@ enum { - VID_PLL_DIV_15, - }; - --void meson_vid_pll_set(struct meson_drm *priv, unsigned int div) -+static void meson_vid_pll_set(struct meson_drm *priv, unsigned int div) - { - unsigned int shift_val = 0; - unsigned int shift_sel = 0; -@@ -487,9 +487,9 @@ static inline unsigned int pll_od_to_reg(unsigned int od) - return 0; - } - --void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m, -- unsigned int frac, unsigned int od1, -- unsigned int od2, unsigned int od3) -+static void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m, -+ unsigned int frac, unsigned int od1, -+ unsigned int od2, unsigned int od3) - { - unsigned int val; - -@@ -1024,6 +1024,89 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq, - regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN); - } - -+static void meson_vclk_setup_ccf(struct meson_drm *priv, unsigned int target, -+ bool hdmi_use_enci, unsigned int phy_freq, -+ unsigned int dac_freq, unsigned int venc_freq) -+{ -+ unsigned int i; -+ int ret; -+ -+ dev_err(priv->dev, "%s(target: %u, phy: %u, dac: %u, venc: %u, hdmi_use_enci: %u)\n", __func__, target, phy_freq, dac_freq, venc_freq, hdmi_use_enci); -+ -+ clk_rate_exclusive_put(priv->clk_venc); -+ clk_rate_exclusive_put(priv->vid_clks[VPU_VID_CLK_TMDS].clk); -+ clk_disable(priv->clk_dac); -+ clk_disable(priv->clk_venc); -+ -+ /* -+ * The TMDS clock also updates the PLL. Protect the PLL rate so all -+ * following clocks are derived from the PLL setting which matches the -+ * TMDS clock. -+ */ -+ ret = clk_set_rate_exclusive(priv->vid_clks[VPU_VID_CLK_TMDS].clk, -+ phy_freq * 1000UL); -+ if (ret) { -+ dev_err(priv->dev, "Failed to set TMDS clock to %ukHz\n", -+ phy_freq); -+ clk_rate_exclusive_get(priv->clk_venc); -+ clk_rate_exclusive_get(priv->vid_clks[VPU_VID_CLK_TMDS].clk); -+ goto out_enable_clocks; -+ } -+ -+ if (target == MESON_VCLK_TARGET_CVBS || hdmi_use_enci) -+ priv->clk_venc = priv->vid_clks[VPU_VID_CLK_CTS_ENCI].clk; -+ else -+ priv->clk_venc = priv->vid_clks[VPU_VID_CLK_CTS_ENCP].clk; -+ -+ if (target == MESON_VCLK_TARGET_CVBS) -+ priv->clk_dac = priv->vid_clks[VPU_VID_CLK_CTS_VDAC0].clk; -+ else -+ priv->clk_dac = priv->vid_clks[VPU_VID_CLK_HDMI_TX_PIXEL].clk; -+ -+ /* -+ * The DAC clock may be derived from a parent of the VENC clock so we -+ * must protect the VENC clock from changing it's rate. This works -+ * because the DAC freq can be divided by the VENC clock. -+ */ -+ ret = clk_set_rate_exclusive(priv->clk_venc, venc_freq * 1000UL); -+ if (ret) { -+ dev_warn(priv->dev, -+ "Failed to set VENC clock to %ukHz while TMDS clock is %ukHz\n", -+ venc_freq, phy_freq); -+ clk_rate_exclusive_get(priv->clk_venc); -+ goto out_enable_clocks; -+ } -+ -+ /* -+ * after changing any of the VID_PLL_* clocks (which can happen when -+ * update the VENC clock rate) we need to assert and then deassert the -+ * VID_DIVIDER_CNTL_* reset lines. -+ */ -+ for (i = 0; i < ARRAY_SIZE(priv->vid_pll_resets); i++) -+ reset_control_assert(priv->vid_pll_resets[i]); -+ for (i = 0; i < ARRAY_SIZE(priv->vid_pll_resets); i++) -+ reset_control_deassert(priv->vid_pll_resets[i]); -+ -+ ret = clk_set_rate(priv->clk_dac, dac_freq * 1000UL); -+ if (ret) { -+ dev_warn(priv->dev, -+ "Failed to set pixel clock to %ukHz while TMDS clock is %ukHz\n", -+ dac_freq, phy_freq); -+ goto out_enable_clocks; -+ } -+ -+out_enable_clocks: -+ ret = clk_enable(priv->clk_venc); -+ if (ret) -+ dev_err(priv->dev, -+ "Failed to re-enable the VENC clock at %ukHz\n", venc_freq); -+ ret = clk_enable(priv->clk_dac); -+ if (ret) -+ dev_err(priv->dev, -+ "Failed to re-enable the pixel clock at %ukHz\n", -+ dac_freq); -+} -+ - void meson_vclk_setup(struct meson_drm *priv, unsigned int target, - unsigned int phy_freq, unsigned int vclk_freq, - unsigned int venc_freq, unsigned int dac_freq, -@@ -1034,6 +1117,15 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target, - unsigned int hdmi_tx_div; - unsigned int venc_div; - -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { -+ meson_vclk_setup_ccf(priv, -+ target, hdmi_use_enci, -+ phy_freq, dac_freq, venc_freq); -+ return; -+ } -+ - if (target == MESON_VCLK_TARGET_CVBS) { - meson_venci_cvbs_clock_config(priv); - return; -diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c -index f93c725b6..145e1d64b 100644 ---- a/drivers/gpu/drm/meson/meson_venc.c -+++ b/drivers/gpu/drm/meson/meson_venc.c -@@ -890,8 +890,8 @@ bool meson_venc_hdmi_supported_vic(int vic) - } - EXPORT_SYMBOL_GPL(meson_venc_hdmi_supported_vic); - --void meson_venc_hdmi_get_dmt_vmode(const struct drm_display_mode *mode, -- union meson_hdmi_venc_mode *dmt_mode) -+static void meson_venc_hdmi_get_dmt_vmode(const struct drm_display_mode *mode, -+ union meson_hdmi_venc_mode *dmt_mode) - { - memset(dmt_mode, 0, sizeof(*dmt_mode)); - -@@ -945,6 +945,66 @@ bool meson_venc_hdmi_venc_repeat(int vic) - } - EXPORT_SYMBOL_GPL(meson_venc_hdmi_venc_repeat); - -+void meson_venc_hdmi_bridge_reset(struct meson_drm *priv) -+{ -+ u32 wr_clk = readl_relaxed(priv->io_base + _REG(VPU_HDMI_SETTING)); -+ enum meson_venc_source { -+ MESON_VENC_SOURCE_NONE = 0, -+ MESON_VENC_SOURCE_ENCI = 1, -+ MESON_VENC_SOURCE_ENCP = 2, -+ }; -+ -+ /* Temporary Disable VENC video stream */ -+ if (priv->venc.hdmi_use_enci) -+ writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); -+ else -+ writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); -+ -+ /* Temporary Disable HDMI video stream to HDMI-TX */ -+ writel_bits_relaxed(0x3, 0, -+ priv->io_base + _REG(VPU_HDMI_SETTING)); -+ writel_bits_relaxed(0xf << 8, 0, -+ priv->io_base + _REG(VPU_HDMI_SETTING)); -+ -+ /* Re-Enable VENC video stream */ -+ if (priv->venc.hdmi_use_enci) -+ writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); -+ else -+ writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); -+ -+ /* Push back HDMI clock settings */ -+ writel_bits_relaxed(0xf << 8, wr_clk & (0xf << 8), -+ priv->io_base + _REG(VPU_HDMI_SETTING)); -+ -+ /* Enable and Select HDMI video source for HDMI-TX */ -+ if (priv->venc.hdmi_use_enci) -+ writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCI, -+ priv->io_base + _REG(VPU_HDMI_SETTING)); -+ else -+ writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCP, -+ priv->io_base + _REG(VPU_HDMI_SETTING)); -+} -+EXPORT_SYMBOL_GPL(meson_venc_hdmi_bridge_reset); -+ -+void meson_venc_hdmi_encoder_enable(struct meson_drm *priv) -+{ -+ if (priv->venc.hdmi_use_enci) -+ writel_relaxed(1, priv->io_base + _REG(ENCI_VIDEO_EN)); -+ else -+ writel_relaxed(1, priv->io_base + _REG(ENCP_VIDEO_EN)); -+} -+EXPORT_SYMBOL_GPL(meson_venc_hdmi_encoder_enable); -+ -+void meson_venc_hdmi_encoder_disable(struct meson_drm *priv) -+{ -+ writel_bits_relaxed(0x3, 0, -+ priv->io_base + _REG(VPU_HDMI_SETTING)); -+ -+ writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); -+ writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); -+} -+EXPORT_SYMBOL_GPL(meson_venc_hdmi_encoder_disable); -+ - void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, - unsigned int ycrcb_map, - bool yuv420_mode, -diff --git a/drivers/gpu/drm/meson/meson_venc.h b/drivers/gpu/drm/meson/meson_venc.h -index 9138255ff..0c4df5d5c 100644 ---- a/drivers/gpu/drm/meson/meson_venc.h -+++ b/drivers/gpu/drm/meson/meson_venc.h -@@ -15,6 +15,7 @@ - #define __MESON_VENC_H - - struct drm_display_mode; -+struct meson_drm; - - enum { - MESON_VENC_MODE_NONE = 0, -@@ -59,6 +60,9 @@ extern struct meson_cvbs_enci_mode meson_cvbs_enci_ntsc; - - void meson_venci_cvbs_mode_set(struct meson_drm *priv, - struct meson_cvbs_enci_mode *mode); -+void meson_venc_hdmi_bridge_reset(struct meson_drm *priv); -+void meson_venc_hdmi_encoder_enable(struct meson_drm *priv); -+void meson_venc_hdmi_encoder_disable(struct meson_drm *priv); - void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic, - unsigned int ycrcb_map, - bool yuv420_mode, -diff --git a/drivers/gpu/drm/meson/meson_venc_cvbs.c b/drivers/gpu/drm/meson/meson_venc_cvbs.c -index f1747fde1..fe99d175f 100644 ---- a/drivers/gpu/drm/meson/meson_venc_cvbs.c -+++ b/drivers/gpu/drm/meson/meson_venc_cvbs.c -@@ -185,17 +185,18 @@ static void meson_venc_cvbs_encoder_enable(struct drm_encoder *encoder) - writel_bits_relaxed(VENC_VDAC_SEL_ATV_DMD, 0, - priv->io_base + _REG(VENC_VDAC_DACSEL0)); - -- if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) { -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) - regmap_write(priv->hhi, HHI_VDAC_CNTL0, 1); -- regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0); -- } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || -- meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) { -+ else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) - regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0xf0001); -- regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0); -- } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { -+ else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) - regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0x906001); -- regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0); -- } -+ -+ regmap_write(priv->hhi, HHI_VDAC_CNTL1, priv->cvbs.cntl1); - } - - static void meson_venc_cvbs_encoder_mode_set(struct drm_encoder *encoder, -diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c -index 259f3e6be..69757e784 100644 ---- a/drivers/gpu/drm/meson/meson_viu.c -+++ b/drivers/gpu/drm/meson/meson_viu.c -@@ -425,21 +425,28 @@ void meson_viu_init(struct meson_drm *priv) - if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || - meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) - meson_viu_load_matrix(priv); -- else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { -+ else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) - meson_viu_set_g12a_osd1_matrix(priv, RGB709_to_YUV709l_coeff, - true); -- /* fix green/pink color distortion from vendor u-boot */ -- writel_bits_relaxed(OSD1_HDR2_CTRL_REG_ONLY_MAT | -- OSD1_HDR2_CTRL_VDIN0_HDR2_TOP_EN, 0, -- priv->io_base + _REG(OSD1_HDR2_CTRL)); -- } - - /* Initialize OSD1 fifo control register */ - reg = VIU_OSD_DDR_PRIORITY_URGENT | -- VIU_OSD_HOLD_FIFO_LINES(31) | -- VIU_OSD_FIFO_DEPTH_VAL(32) | /* fifo_depth_val: 32*8=256 */ -- VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */ -- VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */ -+ VIU_OSD_FIFO_DEPTH_VAL(32) | /* fifo_depth_val: 32*8=256 */ -+ VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */ -+ VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */ -+ -+ /* -+ * When using AFBC on newer SoCs the AFBC encoder has to be reset. To -+ * leave time for that we need hold more lines to avoid glitches. -+ * On the 32-bit SoCs however we need to hold fewer lines because -+ * otherwise screen tearing can occur (for example in kmscube). -+ */ -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) -+ reg |= VIU_OSD_HOLD_FIFO_LINES(12); -+ else -+ reg |= VIU_OSD_HOLD_FIFO_LINES(31); - - if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) - reg |= VIU_OSD_BURST_LENGTH_32; -@@ -449,13 +456,17 @@ void meson_viu_init(struct meson_drm *priv) - writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT)); - writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT)); - -- /* Set OSD alpha replace value */ -- writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, -- 0xff << OSD_REPLACE_SHIFT, -- priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); -- writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, -- 0xff << OSD_REPLACE_SHIFT, -- priv->io_base + _REG(VIU_OSD2_CTRL_STAT2)); -+ if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { -+ /* Set OSD alpha replace value */ -+ writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, -+ 0xff << OSD_REPLACE_SHIFT, -+ priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); -+ writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, -+ 0xff << OSD_REPLACE_SHIFT, -+ priv->io_base + _REG(VIU_OSD2_CTRL_STAT2)); -+ } - - /* Disable VD1 AFBC */ - /* di_mif0_en=0 mif0_to_vpp_en=0 di_mad_en=0 and afbc vd1 set=0*/ -diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig -index 617cf073e..3f5e32a0f 100644 ---- a/drivers/phy/amlogic/Kconfig -+++ b/drivers/phy/amlogic/Kconfig -@@ -2,6 +2,17 @@ - # - # Phy drivers for Amlogic platforms - # -+config PHY_MESON8_HDMI_TX -+ tristate "Meson8, Meson8b and Meson8m2 HDMI TX PHY driver" -+ default ARCH_MESON -+ depends on (ARCH_MESON && ARM) || COMPILE_TEST -+ depends on OF -+ select MFD_SYSCON -+ help -+ Enable this to support the HDMI TX PHYs found in Meson8, -+ Meson8b and Meson8m SoCs. -+ If unsure, say N. -+ - config PHY_MESON8B_USB2 - tristate "Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY driver" - default ARCH_MESON -diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile -index 99702a45e..bdf139f57 100644 ---- a/drivers/phy/amlogic/Makefile -+++ b/drivers/phy/amlogic/Makefile -@@ -1,4 +1,5 @@ - # SPDX-License-Identifier: GPL-2.0-only -+obj-$(CONFIG_PHY_MESON8_HDMI_TX) += phy-meson8-hdmi-tx.o - obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o - obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o - obj-$(CONFIG_PHY_MESON_G12A_USB2) += phy-meson-g12a-usb2.o -diff --git a/drivers/phy/amlogic/phy-meson8-hdmi-tx.c b/drivers/phy/amlogic/phy-meson8-hdmi-tx.c -new file mode 100644 -index 000000000..8f13960a4 ---- /dev/null -+++ b/drivers/phy/amlogic/phy-meson8-hdmi-tx.c -@@ -0,0 +1,150 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Meson8, Meson8b and Meson8m2 HDMI TX PHY. -+ * -+ * Copyright (C) 2020 Martin Blumenstingl -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define HHI_HDMI_PHY_CNTL0 0x3a0 -+ #define HHI_HDMI_PHY_CNTL0_HDMI_CTL1 GENMASK(31, 16) -+ #define HHI_HDMI_PHY_CNTL0_HDMI_CTL0 GENMASK(15, 0) -+ -+#define HHI_HDMI_PHY_CNTL1 0x3a4 -+ #define HHI_HDMI_PHY_CNTL1_CLOCK_ENABLE BIT(1) -+ #define HHI_HDMI_PHY_CNTL1_SOFT_RESET BIT(0) -+ -+#define HHI_HDMI_PHY_CNTL2 0x3a8 -+ -+struct phy_meson8_hdmi_tx_priv { -+ struct regmap *hhi; -+ struct clk *tmds_clk; -+}; -+ -+static int phy_meson8_hdmi_tx_init(struct phy *phy) -+{ -+ struct phy_meson8_hdmi_tx_priv *priv = phy_get_drvdata(phy); -+ -+ return clk_prepare_enable(priv->tmds_clk); -+} -+ -+static int phy_meson8_hdmi_tx_exit(struct phy *phy) -+{ -+ struct phy_meson8_hdmi_tx_priv *priv = phy_get_drvdata(phy); -+ -+ clk_disable_unprepare(priv->tmds_clk); -+ -+ return 0; -+} -+ -+static int phy_meson8_hdmi_tx_power_on(struct phy *phy) -+{ -+ struct phy_meson8_hdmi_tx_priv *priv = phy_get_drvdata(phy); -+ unsigned int i; -+ u16 hdmi_ctl0; -+ -+ if (clk_get_rate(priv->tmds_clk) >= 2970UL * 1000 * 1000) -+ hdmi_ctl0 = 0x1e8b; -+ else -+ hdmi_ctl0 = 0x4d0b; -+ -+ regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, -+ FIELD_PREP(HHI_HDMI_PHY_CNTL0_HDMI_CTL1, 0x08c3) | -+ FIELD_PREP(HHI_HDMI_PHY_CNTL0_HDMI_CTL0, hdmi_ctl0)); -+ -+ regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, 0x00000000); -+ -+ /* Reset three times, just like the vendor driver does */ -+ for (i = 0; i < 3; i++) { -+ regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, -+ HHI_HDMI_PHY_CNTL1_CLOCK_ENABLE | -+ HHI_HDMI_PHY_CNTL1_SOFT_RESET); -+ usleep_range(1000, 2000); -+ -+ regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL1, -+ HHI_HDMI_PHY_CNTL1_CLOCK_ENABLE); -+ usleep_range(1000, 2000); -+ } -+ -+ return 0; -+} -+ -+static int phy_meson8_hdmi_tx_power_off(struct phy *phy) -+{ -+ struct phy_meson8_hdmi_tx_priv *priv = phy_get_drvdata(phy); -+ -+ regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, -+ FIELD_PREP(HHI_HDMI_PHY_CNTL0_HDMI_CTL1, 0x0841) | -+ FIELD_PREP(HHI_HDMI_PHY_CNTL0_HDMI_CTL0, 0x8d00)); -+ -+ return 0; -+} -+ -+static const struct phy_ops phy_meson8_hdmi_tx_ops = { -+ .init = phy_meson8_hdmi_tx_init, -+ .exit = phy_meson8_hdmi_tx_exit, -+ .power_on = phy_meson8_hdmi_tx_power_on, -+ .power_off = phy_meson8_hdmi_tx_power_off, -+ .owner = THIS_MODULE, -+}; -+ -+static int phy_meson8_hdmi_tx_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ struct phy_meson8_hdmi_tx_priv *priv; -+ struct phy_provider *phy_provider; -+ struct phy *phy; -+ -+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ priv->hhi = syscon_node_to_regmap(np->parent); -+ if (IS_ERR(priv->hhi)) -+ return PTR_ERR(priv->hhi); -+ -+ priv->tmds_clk = devm_clk_get(&pdev->dev, NULL); -+ if (IS_ERR(priv->tmds_clk)) -+ return PTR_ERR(priv->tmds_clk); -+ -+ phy = devm_phy_create(&pdev->dev, np, &phy_meson8_hdmi_tx_ops); -+ if (IS_ERR(phy)) -+ return PTR_ERR(phy); -+ -+ phy_set_drvdata(phy, priv); -+ -+ phy_provider = devm_of_phy_provider_register(&pdev->dev, -+ of_phy_simple_xlate); -+ -+ return PTR_ERR_OR_ZERO(phy_provider); -+} -+ -+static const struct of_device_id phy_meson8_hdmi_tx_of_match[] = { -+ { .compatible = "amlogic,meson8-hdmi-tx-phy" }, -+ { .compatible = "amlogic,meson8b-hdmi-tx-phy" }, -+ { .compatible = "amlogic,meson8m2-hdmi-tx-phy" }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, phy_meson8_hdmi_tx_of_match); -+ -+static struct platform_driver phy_meson8_hdmi_tx_driver = { -+ .probe = phy_meson8_hdmi_tx_probe, -+ .driver = { -+ .name = "phy-meson8-hdmi-tx", -+ .of_match_table = phy_meson8_hdmi_tx_of_match, -+ }, -+}; -+module_platform_driver(phy_meson8_hdmi_tx_driver); -+ -+MODULE_AUTHOR("Martin Blumenstingl "); -+MODULE_DESCRIPTION("Meson8, Meson8b and Meson8m2 HDMI TX PHY driver"); -+MODULE_LICENSE("GPL v2"); -diff --git a/include/drm/bridge/txccq_txc_48352.h b/include/drm/bridge/txccq_txc_48352.h -new file mode 100644 -index 000000000..1ba9f4f24 ---- /dev/null -+++ b/include/drm/bridge/txccq_txc_48352.h -@@ -0,0 +1,16 @@ -+/* SPDX-License-Identifier: GPL-2.0-or-later */ -+/* -+ * Copyright (C) 2020 Martin Blumenstingl -+ */ -+ -+#ifndef __DRM_BRIDGE_TXCCQ_TXC_48352__ -+#define __DRM_BRIDGE_TXCCQ_TXC_48352__ -+ -+struct txc_48352; -+struct drm_encoder; -+ -+struct txc_48352 *txc_48352_bind(struct drm_encoder *encoder, -+ struct device *dev); -+void txc_48352_unbind(struct txc_48352 *priv); -+ -+#endif /* __DRM_BRIDGE_TXCCQ_TXC_48352__ */ -diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h -index 4c5965ae1..d273e41dc 100644 ---- a/include/dt-bindings/clock/meson8b-clkc.h -+++ b/include/dt-bindings/clock/meson8b-clkc.h -@@ -107,6 +107,13 @@ - #define CLKID_PERIPH 126 - #define CLKID_AXI 128 - #define CLKID_L2_DRAM 130 -+#define CLKID_HDMI_PLL_HDMI_OUT 132 -+#define CLKID_CTS_ENCT 161 -+#define CLKID_CTS_ENCP 163 -+#define CLKID_CTS_ENCI 165 -+#define CLKID_HDMI_TX_PIXEL 167 -+#define CLKID_CTS_ENCL 169 -+#define CLKID_CTS_VDAC0 171 - #define CLKID_HDMI_SYS 174 - #define CLKID_VPU 190 - #define CLKID_VDEC_1 196 --- -2.25.1 - diff --git a/patch/kernel/meson-legacy b/patch/kernel/meson-legacy deleted file mode 120000 index 8544fc49576c..000000000000 --- a/patch/kernel/meson-legacy +++ /dev/null @@ -1 +0,0 @@ -archive/meson-5.10 \ No newline at end of file