From 1cde2898a2314d9218ddcb6febcb481d6aae333b Mon Sep 17 00:00:00 2001 From: KristianHahn Date: Thu, 9 Feb 2023 17:30:19 +0100 Subject: [PATCH 1/7] config for second rev2 fpga --- .../config.yaml | 103 ++++ .../files_emp.dep | 46 ++ .../settings.tcl | 19 + .../src/sub_module.vhd | 454 ++++++++++++++++++ 4 files changed, 622 insertions(+) create mode 100644 configs/EMP_Cornell_rev2_p2_VU13p-1-SM_USP/config.yaml create mode 100644 configs/EMP_Cornell_rev2_p2_VU13p-1-SM_USP/files_emp.dep create mode 100644 configs/EMP_Cornell_rev2_p2_VU13p-1-SM_USP/settings.tcl create mode 100644 configs/EMP_Cornell_rev2_p2_VU13p-1-SM_USP/src/sub_module.vhd diff --git a/configs/EMP_Cornell_rev2_p2_VU13p-1-SM_USP/config.yaml b/configs/EMP_Cornell_rev2_p2_VU13p-1-SM_USP/config.yaml new file mode 100644 index 0000000..7bff794 --- /dev/null +++ b/configs/EMP_Cornell_rev2_p2_VU13p-1-SM_USP/config.yaml @@ -0,0 +1,103 @@ +AXI_CONTROL_SETS: + AXI_MASTER_CTRL: + axi_interconnect: "${::AXI_INTERCONNECT_NAME}" + axi_clk: "${::AXI_MASTER_CLK}" + axi_rstn: "${::AXI_MASTER_RSTN}" + axi_freq: "${::AXI_MASTER_CLK_FREQ}" + + +AXI_SLAVES: + F2_IO: + TCL_CALL: + command: AXI_PL_DEV_CONNECT + axi_control: "${::AXI_MASTER_CTRL}" + addr: + offset: "0xB3002000" + range: "4K" + remote_slave: "1" + XML: "address_table/modules/CM_IO.xml" + UHAL_BASE: 0xc1000000 + HDL: + out_name: "IO" + map_template: "axi_generic/template_map_withbram.vhd" + + # KH Feb'23 + # F2_SYS_MGMT: + # TCL_CALL: + # command: AXI_IP_SYS_MGMT + # enable_i2c_pins: 1 + # axi_control: "${::AXI_MASTER_CTRL}" + # addr: + # offset: "0xB3001000" + # range: "4K" + # remote_slave: "1" + # XML: "address_table/modules/VIRTEX_SYS_MGMT.xml" + # UHAL_BASE: 0xc0000000 + + F2_CM_FW_INFO: + TCL_CALL: + command: AXI_PL_DEV_CONNECT + axi_control: "${::AXI_MASTER_CTRL}" + addr: + offset: "0xB3003000" + range: "4K" + remote_slave: "1" + XML: "address_table/modules/FW_INFO.xml" + UHAL_BASE: 0xc2000000 + HDL: + out_name: "CM_FW_INFO" + map_template: "axi_generic/template_map.vhd" + + + F2_IPBUS: + TCL_CALL: + command: AXI_PL_DEV_CONNECT + axi_control: "${::AXI_MASTER_CTRL}" + type: "AXI4" + addr: + offset: "0xB2000000" + range: "16M" + data_width: "64" + remote_slave: "1" + XML: "address_table/modules/IPBUS.xml" + UHAL_BASE: 0xc5000000 + + F2_C2C_INTF: + TCL_CALL: + command: AXI_PL_DEV_CONNECT + axi_control: "${::AXI_MASTER_CTRL}" + addr: + offset: "0xB3010000" + range: "64K" + remote_slave: "1" + XML: "address_table/modules/C2C_INTFS.xml" + UHAL_BASE: 0xc6000000 + HDL: + out_name: "C2C_INTF" + map_template: "axi_generic/template_map_withbram.vhd" + SUB_SLAVES: + CM1_PB_UART: + TCL_CALL: + command: "AXI_IP_UART" + addr: + offset: "0xB3008000" + range: "4K" + irq_port: "F2_C2CB/axi_c2c_s2m_intr_in" + baud_rate: "115200" + axi_control: "${::AXI_MASTER_CTRL}" + manual_load_dtsi: "1" + remote_slave: "1" + dt_data: "compatible = \"xlnx,axi-uartlite-2.0\", \"xlnx,xps-uartlite-1.00.a\";current-speed = <115200>;device_type = \"serial\";interrupt-names = \"interrupt\";interrupt-parent = <&IRQ0_INTR_CTRL>;interrupts = <4 0>;port-number = <101>;xlnx,baudrate = <0x1c200>;xlnx,data-bits = <0x8>;xlnx,odd-parity = <0x0>;xlnx,s-axi-aclk-freq-hz-d = \"49.9995\";xlnx,use-parity = <0x0>; + " + +CORES: + onboardclk: + TCL_CALL: + command: BuildClockWizard + in_clk_type: Differential_clock_capable_pin + in_clk_freq_MHZ: 200 + out_clks: + 1: 200 + 2: 50 + + diff --git a/configs/EMP_Cornell_rev2_p2_VU13p-1-SM_USP/files_emp.dep b/configs/EMP_Cornell_rev2_p2_VU13p-1-SM_USP/files_emp.dep new file mode 100644 index 0000000..905514d --- /dev/null +++ b/configs/EMP_Cornell_rev2_p2_VU13p-1-SM_USP/files_emp.dep @@ -0,0 +1,46 @@ +setup ../../../../src/c2cBD/createC2CSlaveInterconnect.tcl +setup -c emp-fwk:boards/apollo/common ../cfg/apollo_set_paths.tcl + + + +src ../../src/sub_module.vhd + + +src ../../../../src/misc/pacd.vhd +src ../../../../src/misc/types.vhd +src ../../../../src/misc/capture_CDC.vhd +src ../../../../src/misc/rate_counter.vhd +src ../../../../src/misc/counter.vhd +src ../../../../src/misc/capture_CDC.vhd +src ../../../../src/misc/uart.vhd + +src ../../../../src/RGB_PWM.vhd +src ../../../../src/LED_PWM.vhd + +src ../../../../regmap_helper/axiReg/axiRegWidthPkg_32.vhd +src ../../../../regmap_helper/axiReg/axiRegPkg_d64.vhd +src ../../../../regmap_helper/axiReg/axiRegPkg.vhd +src ../../../../regmap_helper/axiReg/axiReg.vhd +src ../../../../regmap_helper/axiReg/axiRegBlocking.vhd +src ../../../../regmap_helper/axiReg/bramPortPkg.vhd + +src ../../../../src/C2C_INTF/CM_phy_lane_control.vhd +src ../../../../src/C2C_INTF/picoblaze/uC.vhd +src ../../../../src/C2C_INTF/picoblaze/kcpsm6.vhd +src ../../../../src/C2C_INTF/picoblaze/uart_tx6.vhd +src ../../../../src/C2C_INTF/picoblaze/uart_rx6.vhd +src ../../../../src/C2C_INTF/picoblaze/picoblaze/cli.vhd +src ../../../../src/C2C_INTF/C2C_Intf.vhd + +src ../../../../src/CM_FW_info/CM_FW_info.vhd + +src ../../autogen/CM_FW_INFO/CM_FW_INFO_PKG.vhd +src ../../autogen/CM_FW_INFO/CM_FW_INFO_map.vhd +src ../../autogen/C2C_INTF/C2C_INTF_map.vhd +src ../../autogen/C2C_INTF/C2C_INTF_PKG.vhd +src ../../autogen/IO/IO_map.vhd +src ../../autogen/IO/IO_PKG.vhd + + + + diff --git a/configs/EMP_Cornell_rev2_p2_VU13p-1-SM_USP/settings.tcl b/configs/EMP_Cornell_rev2_p2_VU13p-1-SM_USP/settings.tcl new file mode 100644 index 0000000..472058a --- /dev/null +++ b/configs/EMP_Cornell_rev2_p2_VU13p-1-SM_USP/settings.tcl @@ -0,0 +1,19 @@ + +#set the FPGA part number +set FPGA_part xcvu13p-flga2577-1-e + +##for c2c +set C2C F2_C2C +set C2C_PHY ${C2C}_PHY +set C2CB F2_C2CB +set C2CB_PHY ${C2CB}_PHY + +#create remote device tree entries, set them to 64 bit +global REMOTE_C2C_64 +set REMOTE_C2C_64 1 + + +set top top + +set outputDir ./ + diff --git a/configs/EMP_Cornell_rev2_p2_VU13p-1-SM_USP/src/sub_module.vhd b/configs/EMP_Cornell_rev2_p2_VU13p-1-SM_USP/src/sub_module.vhd new file mode 100644 index 0000000..86a6d46 --- /dev/null +++ b/configs/EMP_Cornell_rev2_p2_VU13p-1-SM_USP/src/sub_module.vhd @@ -0,0 +1,454 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.std_logic_misc.all; + +use work.axiRegPkg.all; +use work.axiRegPkg_d64.all; +use work.types.all; +use work.IO_Ctrl.all; +use work.C2C_INTF_CTRL.all; +use work.AXISlaveAddrPkg.all; + +Library UNISIM; +use UNISIM.vcomponents.all; + +entity sub_module is + port ( + -- clocks + clk_200 : in std_logic; -- 200 MHz system clock + locked_clk200 : in std_logic; + clk_50 : in std_logic; + + + -- Zynq AXI Chip2Chip + -- kh aug'22 drop _chan0 from refclk name, expand c2c links + n_util_clk : in std_logic; + p_util_clk : in std_logic; + n_mgt_z2FPGA : in std_logic_vector(2 downto 1); + p_mgt_z2FPGA : in std_logic_vector(2 downto 1); + n_mgt_FPGA2z : out std_logic_vector(2 downto 1); + p_mgt_FPGA2z : out std_logic_vector(2 downto 1); + + fpga_i2c_scl : inout std_logic; + fpga_i2c_sda : inout std_logic; + + clk_axi : out std_logic; + rst_n_axi : out std_logic; + ext_AXI_ReadMOSI : out AXIReadMOSI_d64 := DefaultAXIReadMOSI_d64; + ext_AXI_ReadMISO : in AXIReadMISO_d64 := DefaultAXIReadMISO_d64; + ext_AXI_WriteMOSI : out AXIWriteMOSI_d64 := DefaultAXIWriteMOSI_d64; + ext_AXI_WriteMISO : in AXIWriteMISO_d64 := DefaultAXIWriteMISO_d64; + + -- tri-color LED + led_red : out std_logic; + led_green : out std_logic; + led_blue : out std_logic; -- assert to turn on + + --kh aug'22 + c2c_ok : out std_logic + ); +end entity sub_module; + +architecture structure of sub_module is + + signal reset : std_logic; + + signal led_blue_local : slv_8_t; + signal led_red_local : slv_8_t; + signal led_green_local : slv_8_t; + + -- kh aug'22 + constant localAXISlaves : integer := 4; + --constant localAXISlaves : integer := 2; + signal local_AXI_ReadMOSI : AXIReadMOSI_array_t(0 to localAXISlaves-1) := ( others => DefaultAXIReadMOSI); + signal local_AXI_ReadMISO : AXIReadMISO_array_t(0 to localAXISlaves-1) := ( others => DefaultAXIReadMISO); + signal local_AXI_WriteMOSI : AXIWriteMOSI_array_t(0 to localAXISlaves-1) := ( others => DefaultAXIWriteMOSI); + signal local_AXI_WriteMISO : AXIWriteMISO_array_t(0 to localAXISlaves-1) := ( others => DefaultAXIWriteMISO); + signal AXI_CLK : std_logic; + signal AXI_RST_N : std_logic; + signal AXI_RESET : std_logic; + + -- kh aug'22 + signal C2C_Mon : C2C_INTF_MON_t; + signal C2C_Ctrl : C2C_INTF_Ctrl_t; + signal clk_F1_C2C_PHY_user : STD_logic_vector(1 downto 1); + signal pB_UART_tx : std_logic; + signal pB_UART_rx : std_logic; + + signal C2CLink_aurora_do_cc : STD_LOGIC; + signal C2CLink_axi_c2c_config_error_out : STD_LOGIC; + signal C2CLink_axi_c2c_link_status_out : STD_LOGIC; + signal C2CLink_axi_c2c_multi_bit_error_out : STD_LOGIC; + signal C2CLink_phy_gt_pll_lock : STD_LOGIC; + signal C2CLink_phy_hard_err : STD_LOGIC; + signal C2CLink_phy_lane_up : STD_LOGIC_VECTOR ( 0 to 0 ); + signal C2CLink_phy_link_reset_out : STD_LOGIC; + signal C2CLink_phy_mmcm_not_locked_out : STD_LOGIC; + signal C2CLink_phy_soft_err : STD_LOGIC; + + + constant std_logic1 : std_logic := '1'; + constant std_logic0 : std_logic := '0'; + + -- KH sep'22 register rate + signal rate_o : std_logic_vector(31 downto 0) := (others => '0'); + +begin -- architecture structure + + + + AXI_CLK <= clk_50; -- for now we just use the 50 MHz from emp for axi + + --export the axi clock and reset to emp + clk_axi <= AXI_CLK; + rst_n_axi <= AXI_RST_N; + + -- kh aug'22 : add uart. c2cb. V->F1 + -- kh feb'23 : F1->F2 + c2csslave_wrapper_1: entity work.c2cSlave_wrapper + port map ( + AXI_CLK => AXI_CLK, + AXI_RST_N(0) => AXI_RST_N, + CM1_PB_UART_rxd => pB_UART_tx, + CM1_PB_UART_txd => pB_UART_rx, + F2_C2C_phy_Rx_rxn => n_mgt_z2FPGA(1 downto 1), + F2_C2C_phy_Rx_rxp => p_mgt_z2FPGA(1 downto 1), + F2_C2C_phy_Tx_txn => n_mgt_FPGA2z(1 downto 1), + F2_C2C_phy_Tx_txp => p_mgt_FPGA2z(1 downto 1), + F2_C2CB_phy_Rx_rxn => n_mgt_z2FPGA(2 downto 2), + F2_C2CB_phy_Rx_rxp => p_mgt_z2FPGA(2 downto 2), + F2_C2CB_phy_Tx_txn => n_mgt_FPGA2z(2 downto 2), + F2_C2CB_phy_Tx_txp => p_mgt_FPGA2z(2 downto 2), + F2_C2C_phy_refclk_clk_n => n_util_clk, + F2_C2C_phy_refclk_clk_p => p_util_clk, + clk50Mhz => clk_50, + + F2_IO_araddr => local_AXI_ReadMOSI(0).address, + F2_IO_arprot => local_AXI_ReadMOSI(0).protection_type, + F2_IO_arready(0) => local_AXI_ReadMISO(0).ready_for_address, + F2_IO_arvalid(0) => local_AXI_ReadMOSI(0).address_valid, + F2_IO_awaddr => local_AXI_WriteMOSI(0).address, + F2_IO_awprot => local_AXI_WriteMOSI(0).protection_type, + F2_IO_awready(0) => local_AXI_WriteMISO(0).ready_for_address, + F2_IO_awvalid(0) => local_AXI_WriteMOSI(0).address_valid, + F2_IO_bready(0) => local_AXI_WriteMOSI(0).ready_for_response, + F2_IO_bresp => local_AXI_WriteMISO(0).response, + F2_IO_bvalid(0) => local_AXI_WriteMISO(0).response_valid, + F2_IO_rdata => local_AXI_ReadMISO(0).data, + F2_IO_rready(0) => local_AXI_ReadMOSI(0).ready_for_data, + F2_IO_rresp => local_AXI_ReadMISO(0).response, + F2_IO_rvalid(0) => local_AXI_ReadMISO(0).data_valid, + F2_IO_wdata => local_AXI_WriteMOSI(0).data, + F2_IO_wready(0) => local_AXI_WriteMISO(0).ready_for_data, + F2_IO_wstrb => local_AXI_WriteMOSI(0).data_write_strobe, + F2_IO_wvalid(0) => local_AXI_WriteMOSI(0).data_valid, + + -- kh aug'22 + F2_C2C_INTF_araddr => local_AXI_ReadMOSI(2).address, + F2_C2C_INTF_arprot => local_AXI_ReadMOSI(2).protection_type, + F2_C2C_INTF_arready => local_AXI_ReadMISO(2).ready_for_address, + F2_C2C_INTF_arvalid => local_AXI_ReadMOSI(2).address_valid, + F2_C2C_INTF_awaddr => local_AXI_WriteMOSI(2).address, + F2_C2C_INTF_awprot => local_AXI_WriteMOSI(2).protection_type, + F2_C2C_INTF_awready => local_AXI_WriteMISO(2).ready_for_address, + F2_C2C_INTF_awvalid => local_AXI_WriteMOSI(2).address_valid, + F2_C2C_INTF_bready => local_AXI_WriteMOSI(2).ready_for_response, + F2_C2C_INTF_bresp => local_AXI_WriteMISO(2).response, + F2_C2C_INTF_bvalid => local_AXI_WriteMISO(2).response_valid, + F2_C2C_INTF_rdata => local_AXI_ReadMISO(2).data, + F2_C2C_INTF_rready => local_AXI_ReadMOSI(2).ready_for_data, + F2_C2C_INTF_rresp => local_AXI_ReadMISO(2).response, + F2_C2C_INTF_rvalid => local_AXI_ReadMISO(2).data_valid, + F2_C2C_INTF_wdata => local_AXI_WriteMOSI(2).data, + F2_C2C_INTF_wready => local_AXI_WriteMISO(2).ready_for_data, + F2_C2C_INTF_wstrb => local_AXI_WriteMOSI(2).data_write_strobe, + F2_C2C_INTF_wvalid => local_AXI_WriteMOSI(2).data_valid, + -- kh aug'22 + + F2_CM_FW_INFO_araddr => local_AXI_ReadMOSI(1).address, + F2_CM_FW_INFO_arprot => local_AXI_ReadMOSI(1).protection_type, + F2_CM_FW_INFO_arready(0) => local_AXI_ReadMISO(1).ready_for_address, + F2_CM_FW_INFO_arvalid(0) => local_AXI_ReadMOSI(1).address_valid, + F2_CM_FW_INFO_awaddr => local_AXI_WriteMOSI(1).address, + F2_CM_FW_INFO_awprot => local_AXI_WriteMOSI(1).protection_type, + F2_CM_FW_INFO_awready(0) => local_AXI_WriteMISO(1).ready_for_address, + F2_CM_FW_INFO_awvalid(0) => local_AXI_WriteMOSI(1).address_valid, + F2_CM_FW_INFO_bready(0) => local_AXI_WriteMOSI(1).ready_for_response, + F2_CM_FW_INFO_bresp => local_AXI_WriteMISO(1).response, + F2_CM_FW_INFO_bvalid(0) => local_AXI_WriteMISO(1).response_valid, + F2_CM_FW_INFO_rdata => local_AXI_ReadMISO(1).data, + F2_CM_FW_INFO_rready(0) => local_AXI_ReadMOSI(1).ready_for_data, + F2_CM_FW_INFO_rresp => local_AXI_ReadMISO(1).response, + F2_CM_FW_INFO_rvalid(0) => local_AXI_ReadMISO(1).data_valid, + F2_CM_FW_INFO_wdata => local_AXI_WriteMOSI(1).data, + F2_CM_FW_INFO_wready(0) => local_AXI_WriteMISO(1).ready_for_data, + F2_CM_FW_INFO_wstrb => local_AXI_WriteMOSI(1).data_write_strobe, + F2_CM_FW_INFO_wvalid(0) => local_AXI_WriteMOSI(1).data_valid, + + F2_IPBUS_araddr => ext_AXI_ReadMOSI.address, + F2_IPBUS_arburst => ext_AXI_ReadMOSI.burst_type, + F2_IPBUS_arcache => ext_AXI_ReadMOSI.cache_type, + F2_IPBUS_arlen => ext_AXI_ReadMOSI.burst_length, + F2_IPBUS_arlock(0) => ext_AXI_ReadMOSI.lock_type, + F2_IPBUS_arprot => ext_AXI_ReadMOSI.protection_type, + F2_IPBUS_arqos => ext_AXI_ReadMOSI.qos, + F2_IPBUS_arready(0) => ext_AXI_ReadMISO.ready_for_address, + F2_IPBUS_arregion => ext_AXI_ReadMOSI.region, + F2_IPBUS_arsize => ext_AXI_ReadMOSI.burst_size, + F2_IPBUS_arvalid(0) => ext_AXI_ReadMOSI.address_valid, + F2_IPBUS_awaddr => ext_AXI_WriteMOSI.address, + F2_IPBUS_awburst => ext_AXI_WriteMOSI.burst_type, + F2_IPBUS_awcache => ext_AXI_WriteMOSI.cache_type, + F2_IPBUS_awlen => ext_AXI_WriteMOSI.burst_length, + F2_IPBUS_awlock(0) => ext_AXI_WriteMOSI.lock_type, + F2_IPBUS_awprot => ext_AXI_WriteMOSI.protection_type, + F2_IPBUS_awqos => ext_AXI_WriteMOSI.qos, + F2_IPBUS_awready(0) => ext_AXI_WriteMISO.ready_for_address, + F2_IPBUS_awregion => ext_AXI_WriteMOSI.region, + F2_IPBUS_awsize => ext_AXI_WriteMOSI.burst_size, + F2_IPBUS_awvalid(0) => ext_AXI_WriteMOSI.address_valid, + F2_IPBUS_bready(0) => ext_AXI_WriteMOSI.ready_for_response, + F2_IPBUS_bresp => ext_AXI_WriteMISO.response, + F2_IPBUS_bvalid(0) => ext_AXI_WriteMISO.response_valid, + F2_IPBUS_rdata => ext_AXI_ReadMISO.data, + F2_IPBUS_rlast(0) => ext_AXI_ReadMISO.last, + F2_IPBUS_rready(0) => ext_AXI_ReadMOSI.ready_for_data, + F2_IPBUS_rresp => ext_AXI_ReadMISO.response, + F2_IPBUS_rvalid(0) => ext_AXI_ReadMISO.data_valid, + F2_IPBUS_wdata => ext_AXI_WriteMOSI.data, + F2_IPBUS_wlast(0) => ext_AXI_WriteMOSI.last, + F2_IPBUS_wready(0) => ext_AXI_WriteMISO.ready_for_data, + F2_IPBUS_wstrb => ext_AXI_WriteMOSI.data_write_strobe, + F2_IPBUS_wvalid(0) => ext_AXI_WriteMOSI.data_valid, + + reset_n => locked_clk200,--reset, + + -- kh aug'22 + F2_C2C_PHY_DEBUG_cplllock(0) => C2C_Mon.C2C(1).DEBUG.CPLL_LOCK, + F2_C2C_PHY_DEBUG_dmonitorout => C2C_Mon.C2C(1).DEBUG.DMONITOR, + F2_C2C_PHY_DEBUG_eyescandataerror(0) => C2C_Mon.C2C(1).DEBUG.EYESCAN_DATA_ERROR, + + F2_C2C_PHY_DEBUG_eyescanreset(0) => C2C_Ctrl.C2C(1).DEBUG.EYESCAN_RESET, + F2_C2C_PHY_DEBUG_eyescantrigger(0) => C2C_Ctrl.C2C(1).DEBUG.EYESCAN_TRIGGER, + F2_C2C_PHY_DEBUG_pcsrsvdin => C2C_Ctrl.C2C(1).DEBUG.PCS_RSV_DIN, + F2_C2C_PHY_DEBUG_qplllock(0) => C2C_Mon.C2C(1).DEBUG.QPLL_LOCK, + F2_C2C_PHY_DEBUG_rxbufreset(0) => C2C_Ctrl.C2C(1).DEBUG.RX.BUF_RESET, + F2_C2C_PHY_DEBUG_rxbufstatus => C2C_Mon.C2C(1).DEBUG.RX.BUF_STATUS, + F2_C2C_PHY_DEBUG_rxcdrhold(0) => C2C_Ctrl.C2C(1).DEBUG.RX.CDR_HOLD, + F2_C2C_PHY_DEBUG_rxdfelpmreset(0) => C2C_Ctrl.C2C(1).DEBUG.RX.DFE_LPM_RESET, + F2_C2C_PHY_DEBUG_rxlpmen(0) => C2C_Ctrl.C2C(1).DEBUG.RX.LPM_EN, + F2_C2C_PHY_DEBUG_rxpcsreset(0) => C2C_Ctrl.C2C(1).DEBUG.RX.PCS_RESET, + F2_C2C_PHY_DEBUG_rxpmareset(0) => C2C_Ctrl.C2C(1).DEBUG.RX.PMA_RESET, + F2_C2C_PHY_DEBUG_rxpmaresetdone(0) => C2C_Mon.C2C(1).DEBUG.RX.PMA_RESET_DONE, + F2_C2C_PHY_DEBUG_rxprbscntreset(0) => C2C_Ctrl.C2C(1).DEBUG.RX.PRBS_CNT_RST, + F2_C2C_PHY_DEBUG_rxprbserr(0) => C2C_Mon.C2C(1).DEBUG.RX.PRBS_ERR, + F2_C2C_PHY_DEBUG_rxprbssel => C2C_Ctrl.C2C(1).DEBUG.RX.PRBS_SEL, + F2_C2C_PHY_DEBUG_rxrate => C2C_Ctrl.C2C(1).DEBUG.RX.RATE, + F2_C2C_PHY_DEBUG_rxresetdone(0) => C2C_Mon.C2C(1).DEBUG.RX.RESET_DONE, + F2_C2C_PHY_DEBUG_txbufstatus => C2C_Mon.C2C(1).DEBUG.TX.BUF_STATUS, + F2_C2C_PHY_DEBUG_txdiffctrl => C2C_Ctrl.C2C(1).DEBUG.TX.DIFF_CTRL, + F2_C2C_PHY_DEBUG_txinhibit(0) => C2C_Ctrl.C2C(1).DEBUG.TX.INHIBIT, + F2_C2C_PHY_DEBUG_txpcsreset(0) => C2C_Ctrl.C2C(1).DEBUG.TX.PCS_RESET, + F2_C2C_PHY_DEBUG_txpmareset(0) => C2C_Ctrl.C2C(1).DEBUG.TX.PMA_RESET, + F2_C2C_PHY_DEBUG_txpolarity(0) => C2C_Ctrl.C2C(1).DEBUG.TX.POLARITY, + F2_C2C_PHY_DEBUG_txpostcursor => C2C_Ctrl.C2C(1).DEBUG.TX.POST_CURSOR, + F2_C2C_PHY_DEBUG_txprbsforceerr(0) => C2C_Ctrl.C2C(1).DEBUG.TX.PRBS_FORCE_ERR, + F2_C2C_PHY_DEBUG_txprbssel => C2C_Ctrl.C2C(1).DEBUG.TX.PRBS_SEL, + F2_C2C_PHY_DEBUG_txprecursor => C2C_Ctrl.C2C(1).DEBUG.TX.PRE_CURSOR, + F2_C2C_PHY_DEBUG_txresetdone(0) => C2C_MON.C2C(1).DEBUG.TX.RESET_DONE, + + F2_C2C_PHY_channel_up => C2C_Mon.C2C(1).STATUS.CHANNEL_UP, + F2_C2C_PHY_gt_pll_lock => C2C_MON.C2C(1).STATUS.PHY_GT_PLL_LOCK, + F2_C2C_PHY_hard_err => C2C_Mon.C2C(1).STATUS.PHY_HARD_ERR, + F2_C2C_PHY_lane_up => C2C_Mon.C2C(1).STATUS.PHY_LANE_UP(0 downto 0), + F2_C2C_PHY_mmcm_not_locked_out => C2C_Mon.C2C(1).STATUS.PHY_MMCM_LOL, + F2_C2C_PHY_soft_err => C2C_Mon.C2C(1).STATUS.PHY_SOFT_ERR, + + F2_C2C_aurora_do_cc => C2C_Mon.C2C(1).STATUS.DO_CC, + F2_C2C_aurora_pma_init_in => C2C_Ctrl.C2C(1).STATUS.INITIALIZE, + F2_C2C_axi_c2c_config_error_out => C2C_Mon.C2C(1).STATUS.CONFIG_ERROR, + F2_C2C_axi_c2c_link_status_out => C2C_MON.C2C(1).STATUS.LINK_GOOD, + F2_C2C_axi_c2c_multi_bit_error_out => C2C_MON.C2C(1).STATUS.MB_ERROR, + --F2_C2C_phy_power_down => '0', + F2_C2C_phy_power_down => std_logic0, + F2_C2C_PHY_clk => clk_F2_C2C_PHY_user(1), + F2_C2C_PHY_DRP_daddr => C2C_Ctrl.C2C(1).DRP.address, + F2_C2C_PHY_DRP_den => C2C_Ctrl.C2C(1).DRP.enable, + F2_C2C_PHY_DRP_di => C2C_Ctrl.C2C(1).DRP.wr_data, + F2_C2C_PHY_DRP_do => C2C_MON.C2C(1).DRP.rd_data, + F2_C2C_PHY_DRP_drdy => C2C_MON.C2C(1).DRP.rd_data_valid, + F2_C2C_PHY_DRP_dwe => C2C_Ctrl.C2C(1).DRP.wr_enable, + + F2_C2CB_PHY_DEBUG_cplllock(0) => C2C_Mon.C2C(2).DEBUG.CPLL_LOCK, + F2_C2CB_PHY_DEBUG_dmonitorout => C2C_Mon.C2C(2).DEBUG.DMONITOR, + F2_C2CB_PHY_DEBUG_eyescandataerror(0) => C2C_Mon.C2C(2).DEBUG.EYESCAN_DATA_ERROR, + + F2_C2CB_PHY_DEBUG_eyescanreset(0) => C2C_Ctrl.C2C(2).DEBUG.EYESCAN_RESET, + F2_C2CB_PHY_DEBUG_eyescantrigger(0) => C2C_Ctrl.C2C(2).DEBUG.EYESCAN_TRIGGER, + F2_C2CB_PHY_DEBUG_pcsrsvdin => C2C_Ctrl.C2C(2).DEBUG.PCS_RSV_DIN, + F2_C2CB_PHY_DEBUG_qplllock(0) => C2C_Mon.C2C(2).DEBUG.QPLL_LOCK, + F2_C2CB_PHY_DEBUG_rxbufreset(0) => C2C_Ctrl.C2C(2).DEBUG.RX.BUF_RESET, + F2_C2CB_PHY_DEBUG_rxbufstatus => C2C_Mon.C2C(2).DEBUG.RX.BUF_STATUS, + F2_C2CB_PHY_DEBUG_rxcdrhold(0) => C2C_Ctrl.C2C(2).DEBUG.RX.CDR_HOLD, + F2_C2CB_PHY_DEBUG_rxdfelpmreset(0) => C2C_Ctrl.C2C(2).DEBUG.RX.DFE_LPM_RESET, + F2_C2CB_PHY_DEBUG_rxlpmen(0) => C2C_Ctrl.C2C(2).DEBUG.RX.LPM_EN, + F2_C2CB_PHY_DEBUG_rxpcsreset(0) => C2C_Ctrl.C2C(2).DEBUG.RX.PCS_RESET, + F2_C2CB_PHY_DEBUG_rxpmareset(0) => C2C_Ctrl.C2C(2).DEBUG.RX.PMA_RESET, + F2_C2CB_PHY_DEBUG_rxpmaresetdone(0) => C2C_Mon.C2C(2).DEBUG.RX.PMA_RESET_DONE, + F2_C2CB_PHY_DEBUG_rxprbscntreset(0) => C2C_Ctrl.C2C(2).DEBUG.RX.PRBS_CNT_RST, + F2_C2CB_PHY_DEBUG_rxprbserr(0) => C2C_Mon.C2C(2).DEBUG.RX.PRBS_ERR, + F2_C2CB_PHY_DEBUG_rxprbssel => C2C_Ctrl.C2C(2).DEBUG.RX.PRBS_SEL, + F2_C2CB_PHY_DEBUG_rxrate => C2C_Ctrl.C2C(2).DEBUG.RX.RATE, + F2_C2CB_PHY_DEBUG_rxresetdone(0) => C2C_Mon.C2C(2).DEBUG.RX.RESET_DONE, + F2_C2CB_PHY_DEBUG_txbufstatus => C2C_Mon.C2C(2).DEBUG.TX.BUF_STATUS, + F2_C2CB_PHY_DEBUG_txdiffctrl => C2C_Ctrl.C2C(2).DEBUG.TX.DIFF_CTRL, + F2_C2CB_PHY_DEBUG_txinhibit(0) => C2C_Ctrl.C2C(2).DEBUG.TX.INHIBIT, + F2_C2CB_PHY_DEBUG_txpcsreset(0) => C2C_Ctrl.C2C(2).DEBUG.TX.PCS_RESET, + F2_C2CB_PHY_DEBUG_txpmareset(0) => C2C_Ctrl.C2C(2).DEBUG.TX.PMA_RESET, + F2_C2CB_PHY_DEBUG_txpolarity(0) => C2C_Ctrl.C2C(2).DEBUG.TX.POLARITY, + F2_C2CB_PHY_DEBUG_txpostcursor => C2C_Ctrl.C2C(2).DEBUG.TX.POST_CURSOR, + F2_C2CB_PHY_DEBUG_txprbsforceerr(0) => C2C_Ctrl.C2C(2).DEBUG.TX.PRBS_FORCE_ERR, + F2_C2CB_PHY_DEBUG_txprbssel => C2C_Ctrl.C2C(2).DEBUG.TX.PRBS_SEL, + F2_C2CB_PHY_DEBUG_txprecursor => C2C_Ctrl.C2C(2).DEBUG.TX.PRE_CURSOR, + F2_C2CB_PHY_DEBUG_txresetdone(0) => C2C_MON.C2C(2).DEBUG.TX.RESET_DONE, + + F2_C2CB_PHY_channel_up => C2C_Mon.C2C(2).STATUS.CHANNEL_UP, + F2_C2CB_PHY_gt_pll_lock => C2C_MON.C2C(2).STATUS.PHY_GT_PLL_LOCK, + F2_C2CB_PHY_hard_err => C2C_Mon.C2C(2).STATUS.PHY_HARD_ERR, + F2_C2CB_PHY_lane_up => C2C_Mon.C2C(2).STATUS.PHY_LANE_UP(0 downto 0), +-- F2_C2CB_PHY_mmcm_not_locked => C2C_Mon.C2C(2).STATUS.PHY_MMCM_LOL, + F2_C2CB_PHY_soft_err => C2C_Mon.C2C(2).STATUS.PHY_SOFT_ERR, + + F2_C2CB_aurora_do_cc => C2C_Mon.C2C(2).STATUS.DO_CC, + F2_C2CB_aurora_pma_init_in => C2C_Ctrl.C2C(2).STATUS.INITIALIZE, + F2_C2CB_axi_c2c_config_error_out => C2C_Mon.C2C(2).STATUS.CONFIG_ERROR, + F2_C2CB_axi_c2c_link_status_out => C2C_MON.C2C(2).STATUS.LINK_GOOD, + F2_C2CB_axi_c2c_multi_bit_error_out => C2C_MON.C2C(2).STATUS.MB_ERROR, +-- F2_C2CB_phy_power_down => '0', + F2_C2CB_phy_power_down => std_logic0, +-- F2_C2CB_PHY_user_clk_out => clk_F2_C2CB_PHY_user, + F2_C2CB_PHY_DRP_daddr => C2C_Ctrl.C2C(2).DRP.address, + F2_C2CB_PHY_DRP_den => C2C_Ctrl.C2C(2).DRP.enable, + F2_C2CB_PHY_DRP_di => C2C_Ctrl.C2C(2).DRP.wr_data, + F2_C2CB_PHY_DRP_do => C2C_MON.C2C(2).DRP.rd_data, + F2_C2CB_PHY_DRP_drdy => C2C_MON.C2C(2).DRP.rd_data_valid, + F2_C2CB_PHY_DRP_dwe => C2C_Ctrl.C2C(2).DRP.wr_enable + -- kh aug'22 + + -- kh spe18'22 no sysmon for emp + --F2_SYS_MGMT_sda => fpga_i2c_sda, + --F2_SYS_MGMT_scl => fpga_i2c_scl +); + + -- kh aug'22 + c2c_ok <= C2C_Mon.C2C(1).STATUS.LINK_GOOD; + + + RGB_pwm_1: entity work.RGB_pwm + generic map ( + CLKFREQ => 200000000, + RGBFREQ => 1000) + port map ( + clk => clk_200, + redcount => led_red_local, + greencount => led_green_local, + bluecount => led_blue_local, + LEDred => led_red, + LEDgreen => led_green, + LEDblue => led_blue); + + + -- kh aug'22 + rate_counter_1: entity work.rate_counter + generic map ( + CLK_A_1_SECOND => 2000000) + port map ( + clk_A => clk_200, + clk_B => clk_F2_C2C_PHY_user(1), + reset_A_async => AXI_RESET, + event_b => '1', +-- KH register for timing +-- rate => C2C_Mon.C2C(1).USER_FREQ); + rate => rate_o); + rate_register : process ( clk_F2_C2C_PHY_user(1), rate_o ) + variable rate_reg : std_logic_vector(31 downto 0) := (others => '0'); + begin + if( rising_edge( clk_F2_C2C_PHY_user(1) ) ) then + C2C_Mon.C2C(1).USER_FREQ <= rate_reg; + rate_reg := rate_o; + end if; + end process; + C2C_Mon.C2C(2).USER_FREQ <= C2C_Mon.C2C(1).USER_FREQ; + + + +-- V_IO_interface_1: entity work.V_IO_interface + F2_IO_interface_1: entity work.IO_map + generic map( + ALLOCATED_MEMORY_RANGE => to_integer(AXI_RANGE_F2_IO) + ) + port map ( + clk_axi => AXI_CLK, + reset_axi_n => AXI_RST_N, + slave_readMOSI => local_AXI_readMOSI(0), + slave_readMISO => local_AXI_readMISO(0), + slave_writeMOSI => local_AXI_writeMOSI(0), + slave_writeMISO => local_AXI_writeMISO(0), + -- kh aug'22 : now move out to c2c slave + --Mon.C2C.CONFIG_ERR => C2CLink_axi_c2c_config_error_out, + --Mon.C2C.DO_CC => C2CLink_aurora_do_cc, + --Mon.C2C.GT_PLL_LOCK => C2CLink_phy_gt_pll_lock, + --Mon.C2C.HARD_ERR => C2CLink_phy_hard_err, + --Mon.C2C.LANE_UP => C2CLink_phy_lane_up(0), + --Mon.C2C.LINK_RESET => C2CLink_phy_link_reset_out, + --Mon.C2C.LINK_STATUS => C2CLink_axi_c2c_link_status_out, + --Mon.C2C.MMCM_NOT_LOCKED => C2CLink_phy_mmcm_not_locked_out, + --Mon.C2C.MULTIBIT_ERR => C2CLink_axi_c2c_multi_bit_error_out, + --Mon.C2C.SOFT_ERR => C2CLink_phy_soft_err, + Mon.CLK_200_LOCKED => locked_clk200, + Mon.BRAM.RD_DATA => (others => '0'), + Ctrl.RGB.R => led_red_local, + Ctrl.RGB.G => led_green_local, + Ctrl.RGB.B => led_blue_local, + Ctrl.BRAM => open + ); + +-- CM_V_info_1: entity work.CM_V_info + CM_F2_info_1: entity work.CM_FW_info + generic map ( + ALLOCATED_MEMORY_RANGE => to_integer(AXI_RANGE_F2_CM_FW_INFO) + ) + port map ( + clk_axi => AXI_CLK, + reset_axi_n => AXI_RST_N, + readMOSI => local_AXI_ReadMOSI(1), + readMISO => local_AXI_ReadMISO(1), + writeMOSI => local_AXI_WriteMOSI(1), + writeMISO => local_AXI_WriteMISO(1)); + + -- kh aug'22 + C2C_INTF_1: entity work.C2C_INTF + generic map ( + ERROR_WAIT_TIME => 90000000, + ALLOCATED_MEMORY_RANGE => to_integer(AXI_RANGE_F2_C2C_INTF) + ) + port map ( + clk_axi => AXI_CLK, + reset_axi_n => AXI_RST_N, + readMOSI => local_AXI_readMOSI(2), + readMISO => local_AXI_readMISO(2), + writeMOSI => local_AXI_writeMOSI(2), + writeMISO => local_AXI_writeMISO(2), + clk_C2C(1) => clk_F2_C2C_PHY_user(1), + clk_C2C(2) => clk_F2_C2C_PHY_user(1), + UART_Rx => pb_UART_Rx, + UART_Tx => pb_UART_Tx, + Mon => C2C_Mon, + Ctrl => C2C_Ctrl); + + + AXI_RESET <= not AXI_RST_N; + + +end architecture structure; From f239bc79aa3d087bb67d5c9545e372362096147f Mon Sep 17 00:00:00 2001 From: KristianHahn Date: Thu, 9 Feb 2023 17:35:25 +0100 Subject: [PATCH 2/7] add prebuild for 2nd fpga --- .ipbb_setup.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.ipbb_setup.yml b/.ipbb_setup.yml index 03a1c26..ee83ca4 100644 --- a/.ipbb_setup.yml +++ b/.ipbb_setup.yml @@ -3,6 +3,7 @@ init: - make list - make prebuild_EMP_Cornell_rev1_p2_VU7p-1-SM_7s - make prebuild_EMP_Cornell_rev2_p1_VU13p-1-SM_USP + - make prebuild_EMP_Cornell_rev2_p2_VU13p-1-SM_USP reset: From 21d52f505e77d6b79d498c2c768edaf52eace9b9 Mon Sep 17 00:00:00 2001 From: KristianHahn Date: Fri, 24 Feb 2023 11:48:36 +0100 Subject: [PATCH 3/7] f1->f2 for c2c phy --- configs/EMP_Cornell_rev2_p2_VU13p-1-SM_USP/src/sub_module.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/EMP_Cornell_rev2_p2_VU13p-1-SM_USP/src/sub_module.vhd b/configs/EMP_Cornell_rev2_p2_VU13p-1-SM_USP/src/sub_module.vhd index 86a6d46..fcb1af7 100644 --- a/configs/EMP_Cornell_rev2_p2_VU13p-1-SM_USP/src/sub_module.vhd +++ b/configs/EMP_Cornell_rev2_p2_VU13p-1-SM_USP/src/sub_module.vhd @@ -72,7 +72,7 @@ architecture structure of sub_module is -- kh aug'22 signal C2C_Mon : C2C_INTF_MON_t; signal C2C_Ctrl : C2C_INTF_Ctrl_t; - signal clk_F1_C2C_PHY_user : STD_logic_vector(1 downto 1); + signal clk_F2_C2C_PHY_user : STD_logic_vector(1 downto 1); signal pB_UART_tx : std_logic; signal pB_UART_rx : std_logic; From a10d9887161aabc8240cd9f6f96eecb0eb1dacd5 Mon Sep 17 00:00:00 2001 From: Dan Date: Mon, 27 Feb 2023 09:59:10 -0500 Subject: [PATCH 4/7] Update Makefile --- Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Makefile b/Makefile index d629eb3..cfaeaf2 100644 --- a/Makefile +++ b/Makefile @@ -166,6 +166,8 @@ $(BIT_BASE)%.bit : $(ADDRESS_TABLE_CREATION_PATH)config_%.yaml cd proj &&\ vivado $(VIVADO_FLAGS) -source $(SETUP_BUILD_TCL) -tclargs ${MAKE_PATH} ${BUILD_SCRIPTS_PATH} $(subst .bit,,$(subst ${BIT_BASE},,$@)) $(OUTPUT_MARKUP) $(MAKE) NOTIFY_DAN_GOOD $(OUTPUT_MARKUP) + @echo ${MAKE} $(ADDRESS_TABLE_CREATION_PATH)address_tables/address_table_$*/address_apollo.xml + ${MAKE} $(ADDRESS_TABLE_CREATION_PATH)address_tables/address_table_$*/address_apollo.xml $(MAKE) overlays $(OUTPUT_MARKUP) @rm -f $*.tar.gz $(MAKE) $*.tar.gz $(OUTPUT_MARKUP) From 80a55665ed6c87b11a206fa10f2a246d6fbf0067 Mon Sep 17 00:00:00 2001 From: Dan Gastler Date: Mon, 27 Feb 2023 15:56:10 -0500 Subject: [PATCH 5/7] Some fixes for build --- Makefile | 5 +- configs/MPI_rev1_p1_KU15p-2-SM_7s/autogen | 1 - configs/MPI_rev1_p1_KU15p-2-SM_7s/cores | 1 - .../MPI_rev1_p1_KU15p-2-SM_USP/src/top.vhd | 160 ++++-------------- 4 files changed, 35 insertions(+), 132 deletions(-) delete mode 120000 configs/MPI_rev1_p1_KU15p-2-SM_7s/autogen delete mode 120000 configs/MPI_rev1_p1_KU15p-2-SM_7s/cores diff --git a/Makefile b/Makefile index d629eb3..0022c9c 100644 --- a/Makefile +++ b/Makefile @@ -25,7 +25,8 @@ PL_PATH=${MAKE_PATH}/src BD_PATH=${MAKE_PATH}/bd CORES_PATH=${MAKE_PATH}/cores #ADDRESS_TABLE = ${MAKE_PATH}/os/address_table/address_apollo.xml -$(BIT_BASE)%.bit $(BIT_BASE)%.svf : ADDRESS_TABLE=${MAKE_PATH}/os/address_table_%/address_%.xml +#$(BIT_BASE)%.bit $(BIT_BASE)%.svf : ADDRESS_TABLE=${MAKE_PATH}/os/address_table_%/address_%.xml +$(BIT_BASE)%.bit $(BIT_BASE)%.svf : ADDRESS_TABLE=${MAKE_PATH}/kernel/address_table_%/address_%.xml ################################################################################ # Configs ################################################################################# @@ -166,6 +167,8 @@ $(BIT_BASE)%.bit : $(ADDRESS_TABLE_CREATION_PATH)config_%.yaml cd proj &&\ vivado $(VIVADO_FLAGS) -source $(SETUP_BUILD_TCL) -tclargs ${MAKE_PATH} ${BUILD_SCRIPTS_PATH} $(subst .bit,,$(subst ${BIT_BASE},,$@)) $(OUTPUT_MARKUP) $(MAKE) NOTIFY_DAN_GOOD $(OUTPUT_MARKUP) + @echo ${MAKE} $(ADDRESS_TABLE_CREATION_PATH)address_tables/address_table_$*/address_apollo.xml + ${MAKE} $(ADDRESS_TABLE_CREATION_PATH)address_tables/address_table_$*/address_apollo.xml $(MAKE) overlays $(OUTPUT_MARKUP) @rm -f $*.tar.gz $(MAKE) $*.tar.gz $(OUTPUT_MARKUP) diff --git a/configs/MPI_rev1_p1_KU15p-2-SM_7s/autogen b/configs/MPI_rev1_p1_KU15p-2-SM_7s/autogen deleted file mode 120000 index 5a634a9..0000000 --- a/configs/MPI_rev1_p1_KU15p-2-SM_7s/autogen +++ /dev/null @@ -1 +0,0 @@ -../MPI_rev1_p1_KU15p-2-SM_USP/autogen \ No newline at end of file diff --git a/configs/MPI_rev1_p1_KU15p-2-SM_7s/cores b/configs/MPI_rev1_p1_KU15p-2-SM_7s/cores deleted file mode 120000 index 8db0946..0000000 --- a/configs/MPI_rev1_p1_KU15p-2-SM_7s/cores +++ /dev/null @@ -1 +0,0 @@ -../MPI_rev1_p1_KU15p-2-SM_USP/cores \ No newline at end of file diff --git a/configs/MPI_rev1_p1_KU15p-2-SM_USP/src/top.vhd b/configs/MPI_rev1_p1_KU15p-2-SM_USP/src/top.vhd index 5558b89..172c26f 100644 --- a/configs/MPI_rev1_p1_KU15p-2-SM_USP/src/top.vhd +++ b/configs/MPI_rev1_p1_KU15p-2-SM_USP/src/top.vhd @@ -149,81 +149,44 @@ begin -- architecture structure clk50Mhz => clk_50, K_IO_araddr => local_AXI_ReadMOSI(0).address, K_IO_arprot => local_AXI_ReadMOSI(0).protection_type, - K_IO_arready => local_AXI_ReadMISO(0).ready_for_address, - K_IO_arvalid => local_AXI_ReadMOSI(0).address_valid, + K_IO_arready(0) => local_AXI_ReadMISO(0).ready_for_address, + K_IO_arvalid(0) => local_AXI_ReadMOSI(0).address_valid, K_IO_awaddr => local_AXI_WriteMOSI(0).address, K_IO_awprot => local_AXI_WriteMOSI(0).protection_type, - K_IO_awready => local_AXI_WriteMISO(0).ready_for_address, - K_IO_awvalid => local_AXI_WriteMOSI(0).address_valid, - K_IO_bready => local_AXI_WriteMOSI(0).ready_for_response, + K_IO_awready(0) => local_AXI_WriteMISO(0).ready_for_address, + K_IO_awvalid(0) => local_AXI_WriteMOSI(0).address_valid, + K_IO_bready(0) => local_AXI_WriteMOSI(0).ready_for_response, K_IO_bresp => local_AXI_WriteMISO(0).response, - K_IO_bvalid => local_AXI_WriteMISO(0).response_valid, + K_IO_bvalid(0) => local_AXI_WriteMISO(0).response_valid, K_IO_rdata => local_AXI_ReadMISO(0).data, - K_IO_rready => local_AXI_ReadMOSI(0).ready_for_data, + K_IO_rready(0) => local_AXI_ReadMOSI(0).ready_for_data, K_IO_rresp => local_AXI_ReadMISO(0).response, - K_IO_rvalid => local_AXI_ReadMISO(0).data_valid, + K_IO_rvalid(0) => local_AXI_ReadMISO(0).data_valid, K_IO_wdata => local_AXI_WriteMOSI(0).data, - K_IO_wready => local_AXI_WriteMISO(0).ready_for_data, + K_IO_wready(0) => local_AXI_WriteMISO(0).ready_for_data, K_IO_wstrb => local_AXI_WriteMOSI(0).data_write_strobe, - K_IO_wvalid => local_AXI_WriteMOSI(0).data_valid, + K_IO_wvalid(0) => local_AXI_WriteMOSI(0).data_valid, K_CM_FW_INFO_araddr => local_AXI_ReadMOSI(1).address, K_CM_FW_INFO_arprot => local_AXI_ReadMOSI(1).protection_type, - K_CM_FW_INFO_arready => local_AXI_ReadMISO(1).ready_for_address, - K_CM_FW_INFO_arvalid => local_AXI_ReadMOSI(1).address_valid, + K_CM_FW_INFO_arready(0) => local_AXI_ReadMISO(1).ready_for_address, + K_CM_FW_INFO_arvalid(0) => local_AXI_ReadMOSI(1).address_valid, K_CM_FW_INFO_awaddr => local_AXI_WriteMOSI(1).address, K_CM_FW_INFO_awprot => local_AXI_WriteMOSI(1).protection_type, - K_CM_FW_INFO_awready => local_AXI_WriteMISO(1).ready_for_address, - K_CM_FW_INFO_awvalid => local_AXI_WriteMOSI(1).address_valid, - K_CM_FW_INFO_bready => local_AXI_WriteMOSI(1).ready_for_response, + K_CM_FW_INFO_awready(0) => local_AXI_WriteMISO(1).ready_for_address, + K_CM_FW_INFO_awvalid(0) => local_AXI_WriteMOSI(1).address_valid, + K_CM_FW_INFO_bready(0) => local_AXI_WriteMOSI(1).ready_for_response, K_CM_FW_INFO_bresp => local_AXI_WriteMISO(1).response, - K_CM_FW_INFO_bvalid => local_AXI_WriteMISO(1).response_valid, + K_CM_FW_INFO_bvalid(0) => local_AXI_WriteMISO(1).response_valid, K_CM_FW_INFO_rdata => local_AXI_ReadMISO(1).data, - K_CM_FW_INFO_rready => local_AXI_ReadMOSI(1).ready_for_data, + K_CM_FW_INFO_rready(0) => local_AXI_ReadMOSI(1).ready_for_data, K_CM_FW_INFO_rresp => local_AXI_ReadMISO(1).response, - K_CM_FW_INFO_rvalid => local_AXI_ReadMISO(1).data_valid, + K_CM_FW_INFO_rvalid(0) => local_AXI_ReadMISO(1).data_valid, K_CM_FW_INFO_wdata => local_AXI_WriteMOSI(1).data, - K_CM_FW_INFO_wready => local_AXI_WriteMISO(1).ready_for_data, + K_CM_FW_INFO_wready(0) => local_AXI_WriteMISO(1).ready_for_data, K_CM_FW_INFO_wstrb => local_AXI_WriteMOSI(1).data_write_strobe, - K_CM_FW_INFO_wvalid => local_AXI_WriteMOSI(1).data_valid, - - KINTEX_BRAM_araddr => ext_AXI_ReadMOSI.address, - KINTEX_BRAM_arburst => ext_AXI_ReadMOSI.burst_type, - KINTEX_BRAM_arcache => ext_AXI_ReadMOSI.cache_type, - KINTEX_BRAM_arlen => ext_AXI_ReadMOSI.burst_length, - KINTEX_BRAM_arlock(0) => ext_AXI_ReadMOSI.lock_type, - KINTEX_BRAM_arprot => ext_AXI_ReadMOSI.protection_type, - KINTEX_BRAM_arqos => ext_AXI_ReadMOSI.qos, - KINTEX_BRAM_arready(0) => ext_AXI_ReadMISO.ready_for_address, - KINTEX_BRAM_arregion => ext_AXI_ReadMOSI.region, - KINTEX_BRAM_arsize => ext_AXI_ReadMOSI.burst_size, - KINTEX_BRAM_arvalid(0) => ext_AXI_ReadMOSI.address_valid, - KINTEX_BRAM_awaddr => ext_AXI_WriteMOSI.address, - KINTEX_BRAM_awburst => ext_AXI_WriteMOSI.burst_type, - KINTEX_BRAM_awcache => ext_AXI_WriteMOSI.cache_type, - KINTEX_BRAM_awlen => ext_AXI_WriteMOSI.burst_length, - KINTEX_BRAM_awlock(0) => ext_AXI_WriteMOSI.lock_type, - KINTEX_BRAM_awprot => ext_AXI_WriteMOSI.protection_type, - KINTEX_BRAM_awqos => ext_AXI_WriteMOSI.qos, - KINTEX_BRAM_awready(0) => ext_AXI_WriteMISO.ready_for_address, - KINTEX_BRAM_awregion => ext_AXI_WriteMOSI.region, - KINTEX_BRAM_awsize => ext_AXI_WriteMOSI.burst_size, - KINTEX_BRAM_awvalid(0) => ext_AXI_WriteMOSI.address_valid, - KINTEX_BRAM_bready(0) => ext_AXI_WriteMOSI.ready_for_response, - KINTEX_BRAM_bresp => ext_AXI_WriteMISO.response, - KINTEX_BRAM_bvalid(0) => ext_AXI_WriteMISO.response_valid, - KINTEX_BRAM_rdata => ext_AXI_ReadMISO.data, - KINTEX_BRAM_rlast(0) => ext_AXI_ReadMISO.last, - KINTEX_BRAM_rready(0) => ext_AXI_ReadMOSI.ready_for_data, - KINTEX_BRAM_rresp => ext_AXI_ReadMISO.response, - KINTEX_BRAM_rvalid(0) => ext_AXI_ReadMISO.data_valid, - KINTEX_BRAM_wdata => ext_AXI_WriteMOSI.data, - KINTEX_BRAM_wlast(0) => ext_AXI_WriteMOSI.last, - KINTEX_BRAM_wready(0) => ext_AXI_WriteMISO.ready_for_data, - KINTEX_BRAM_wstrb => ext_AXI_WriteMOSI.data_write_strobe, - KINTEX_BRAM_wvalid(0) => ext_AXI_WriteMOSI.data_valid, + K_CM_FW_INFO_wvalid(0) => local_AXI_WriteMOSI(1).data_valid, - - + reset_n => locked_clk200,--reset, K_C2C_PHY_DEBUG_cplllock(0) => C2C_Mon.C2C(1).DEBUG.CPLL_LOCK, K_C2C_PHY_DEBUG_dmonitorout => C2C_Mon.C2C(1).DEBUG.DMONITOR, @@ -334,23 +297,23 @@ begin -- architecture structure K_C2C_INTF_araddr => local_AXI_ReadMOSI(2).address, K_C2C_INTF_arprot => local_AXI_ReadMOSI(2).protection_type, - K_C2C_INTF_arready => local_AXI_ReadMISO(2).ready_for_address, - K_C2C_INTF_arvalid => local_AXI_ReadMOSI(2).address_valid, + K_C2C_INTF_arready(0) => local_AXI_ReadMISO(2).ready_for_address, + K_C2C_INTF_arvalid(0) => local_AXI_ReadMOSI(2).address_valid, K_C2C_INTF_awaddr => local_AXI_WriteMOSI(2).address, K_C2C_INTF_awprot => local_AXI_WriteMOSI(2).protection_type, - K_C2C_INTF_awready => local_AXI_WriteMISO(2).ready_for_address, - K_C2C_INTF_awvalid => local_AXI_WriteMOSI(2).address_valid, - K_C2C_INTF_bready => local_AXI_WriteMOSI(2).ready_for_response, + K_C2C_INTF_awready(0) => local_AXI_WriteMISO(2).ready_for_address, + K_C2C_INTF_awvalid(0) => local_AXI_WriteMOSI(2).address_valid, + K_C2C_INTF_bready(0) => local_AXI_WriteMOSI(2).ready_for_response, K_C2C_INTF_bresp => local_AXI_WriteMISO(2).response, - K_C2C_INTF_bvalid => local_AXI_WriteMISO(2).response_valid, + K_C2C_INTF_bvalid(0) => local_AXI_WriteMISO(2).response_valid, K_C2C_INTF_rdata => local_AXI_ReadMISO(2).data, - K_C2C_INTF_rready => local_AXI_ReadMOSI(2).ready_for_data, + K_C2C_INTF_rready(0) => local_AXI_ReadMOSI(2).ready_for_data, K_C2C_INTF_rresp => local_AXI_ReadMISO(2).response, - K_C2C_INTF_rvalid => local_AXI_ReadMISO(2).data_valid, + K_C2C_INTF_rvalid(0) => local_AXI_ReadMISO(2).data_valid, K_C2C_INTF_wdata => local_AXI_WriteMOSI(2).data, - K_C2C_INTF_wready => local_AXI_WriteMISO(2).ready_for_data, + K_C2C_INTF_wready(0) => local_AXI_WriteMISO(2).ready_for_data, K_C2C_INTF_wstrb => local_AXI_WriteMOSI(2).data_write_strobe, - K_C2C_INTF_wvalid => local_AXI_WriteMOSI(2).data_valid + K_C2C_INTF_wvalid(0) => local_AXI_WriteMOSI(2).data_valid ); @@ -424,67 +387,6 @@ begin -- architecture structure Ctrl => C2C_Ctrl); - AXI_BRAM_1: entity work.AXI_BRAM - port map ( - s_axi_aclk => AXI_CLK, - s_axi_aresetn => AXI_RST_N, - s_axi_araddr => ext_AXI_ReadMOSI.address(12 downto 0), - s_axi_arburst => ext_AXI_ReadMOSI.burst_type, - s_axi_arcache => ext_AXI_ReadMOSI.cache_type, - s_axi_arlen => ext_AXI_ReadMOSI.burst_length, - s_axi_arlock => ext_AXI_ReadMOSI.lock_type, - s_axi_arprot => ext_AXI_ReadMOSI.protection_type, --- s_axi_arqos => ext_AXI_ReadMOSI.qos, - s_axi_arready => ext_AXI_ReadMISO.ready_for_address, --- s_axi_arregion => ext_AXI_ReadMOSI.region, - s_axi_arsize => ext_AXI_ReadMOSI.burst_size, - s_axi_arvalid => ext_AXI_ReadMOSI.address_valid, - s_axi_awaddr => ext_AXI_WriteMOSI.address(12 downto 0), - s_axi_awburst => ext_AXI_WriteMOSI.burst_type, - s_axi_awcache => ext_AXI_WriteMOSI.cache_type, - s_axi_awlen => ext_AXI_WriteMOSI.burst_length, - s_axi_awlock => ext_AXI_WriteMOSI.lock_type, - s_axi_awprot => ext_AXI_WriteMOSI.protection_type, --- s_axi_awqos => ext_AXI_WriteMOSI.qos, - s_axi_awready => ext_AXI_WriteMISO.ready_for_address, --- s_axi_awregion => ext_AXI_WriteMOSI.region, - s_axi_awsize => ext_AXI_WriteMOSI.burst_size, - s_axi_awvalid => ext_AXI_WriteMOSI.address_valid, - s_axi_bready => ext_AXI_WriteMOSI.ready_for_response, - s_axi_bresp => ext_AXI_WriteMISO.response, - s_axi_bvalid => ext_AXI_WriteMISO.response_valid, - s_axi_rdata => ext_AXI_ReadMISO.data, - s_axi_rlast => ext_AXI_ReadMISO.last, - s_axi_rready => ext_AXI_ReadMOSI.ready_for_data, - s_axi_rresp => ext_AXI_ReadMISO.response, - s_axi_rvalid => ext_AXI_ReadMISO.data_valid, - s_axi_wdata => ext_AXI_WriteMOSI.data, - s_axi_wlast => ext_AXI_WriteMOSI.last, - s_axi_wready => ext_AXI_WriteMISO.ready_for_data, - s_axi_wstrb => ext_AXI_WriteMOSI.data_write_strobe, - s_axi_wvalid => ext_AXI_WriteMOSI.data_valid, - bram_rst_a => open, - bram_clk_a => AXI_CLK, - bram_en_a => AXI_BRAM_en, - bram_we_a => AXI_BRAM_we, - bram_addr_a => AXI_BRAM_addr, - bram_wrdata_a => AXI_BRAM_DATA_IN, - bram_rddata_a => AXI_BRAM_DATA_OUT); - - DP_BRAM_1: entity work.DP_BRAM - port map ( - clka => AXI_CLK, - ena => AXI_BRAM_EN, - wea => AXI_BRAM_we, - addra => AXI_BRAM_addr(11 downto 2), - dina => AXI_BRAM_DATA_IN, - douta => AXI_BRAM_DATA_OUT, - clkb => AXI_CLK, - enb => '1', - web => (others => BRAM_WRITE), - addrb => BRAM_ADDR, - dinb => BRAM_WR_DATA, - doutb => BRAM_RD_DATA); end architecture structure; From 2aac1ee24896611cd63d65858d6ea7397d1fddcc Mon Sep 17 00:00:00 2001 From: Dan Gastler Date: Tue, 28 Feb 2023 13:43:47 -0500 Subject: [PATCH 6/7] Some fixes for address table generation in prebuild only setups --- Makefile | 2 +- build-scripts | 2 +- cores/AXI_BRAM/AXI_BRAM.xci | 10 +++++----- cores/DP_BRAM/DP_BRAM.xci | 12 ++++++------ 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/Makefile b/Makefile index 0022c9c..8584003 100644 --- a/Makefile +++ b/Makefile @@ -35,7 +35,7 @@ CONFIGS_BASE_PATH=configs/ CONFIGS=$(patsubst ${CONFIGS_BASE_PATH}%/,%,$(dir $(wildcard ${CONFIGS_BASE_PATH}*/))) define CONFIGS_template = - $(1): clean autogen_clean_$(1) + $(1): clean autogen_clean_$(1) clean_overlays time $(MAKE) $(BIT_BASE)$$(@).bit || $(MAKE) NOTIFY_DAN_BAD endef define CONFIGS_autoclean_template = diff --git a/build-scripts b/build-scripts index 42f41c8..75a6388 160000 --- a/build-scripts +++ b/build-scripts @@ -1 +1 @@ -Subproject commit 42f41c8b6ca374ad90128c3df4d1c7855ff33b3e +Subproject commit 75a63880e2e42d062fe3840a591049b2c7f27fc5 diff --git a/cores/AXI_BRAM/AXI_BRAM.xci b/cores/AXI_BRAM/AXI_BRAM.xci index 890b918..583748d 100644 --- a/cores/AXI_BRAM/AXI_BRAM.xci +++ b/cores/AXI_BRAM/AXI_BRAM.xci @@ -93,7 +93,7 @@ 0 0 0 - virtexuplus + kintexuplus 0 1024 0 @@ -120,15 +120,15 @@ 1 1 0 - virtexuplus + kintexuplus - xcvu13p - flga2577 + xcku15p + ffva1760 VHDL MIXED - -1 + -2 E TRUE diff --git a/cores/DP_BRAM/DP_BRAM.xci b/cores/DP_BRAM/DP_BRAM.xci index 8238f59..7a481d8 100644 --- a/cores/DP_BRAM/DP_BRAM.xci +++ b/cores/DP_BRAM/DP_BRAM.xci @@ -114,7 +114,7 @@ 0 0 Estimated Power for IP : 7.496465 mW - virtexuplus + kintexuplus 0 1 1 @@ -164,7 +164,7 @@ WRITE_FIRST 64 32 - virtexuplus + kintexuplus 4 Memory_Slave AXI4_Full @@ -237,15 +237,15 @@ false false Stand_Alone - virtexuplus + kintexuplus - xcvu13p - flga2577 + xcku15p + ffva1760 VHDL MIXED - -1 + -2 E TRUE From d7d9c09d97000ee66c8ab25279ba9a47966b4cd9 Mon Sep 17 00:00:00 2001 From: Mark Pesaresi Date: Tue, 7 Mar 2023 19:10:14 +0100 Subject: [PATCH 7/7] add make address tables --- .ipbb_setup.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.ipbb_setup.yml b/.ipbb_setup.yml index ee83ca4..ba6538b 100644 --- a/.ipbb_setup.yml +++ b/.ipbb_setup.yml @@ -2,8 +2,11 @@ init: - make init - make list - make prebuild_EMP_Cornell_rev1_p2_VU7p-1-SM_7s + - make address_table_EMP_Cornell_rev1_p2_VU7p-1-SM_7s - make prebuild_EMP_Cornell_rev2_p1_VU13p-1-SM_USP + - make address_table_EMP_Cornell_rev2_p1_VU13p-1-SM_USP - make prebuild_EMP_Cornell_rev2_p2_VU13p-1-SM_USP + - make address_table_EMP_Cornell_rev2_p2_VU13p-1-SM_USP reset: