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info.yaml
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# Tiny Tapeout project information
project:
title: "Decimation Filter for Incremental and Regular Delta-Sigma Modulators" # Project title
author: "Andrea Murillo Martinez & Jaeden Chang" # Your name
discord: ".andreamu" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "Decimation filter that efficiently reduces oversampled data from incremental and regular delta-sigma modulators, while preserving signal accuaracy." # One line description of what your project does
language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
clock_hz: 50000000 # Clock frequency in Hz (or 0 if not applicable)
# How many tiles your design occupies? A single tile is about 167x108 uM.
tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
# Your top module name must start with "tt_um_". Make it unique by including your github username:
top_module: "tt_um_murmann_group"
# List your project's source files here.
# Source files must be in ./src and you must list each source file separately, one per line.
# Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
source_files:
- "decimation_filter.v"
# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
pinout:
# Inputs
ui[0]: X
ui[1]: type_dec
ui[2]: global_reset
ui[3]: ""
ui[4]: ""
ui[5]: ""
ui[6]: ""
ui[7]: ""
# Outputs
uo[0]: decimation_output[8]
uo[1]: decimation_output[9]
uo[2]: decimation_output[10]
uo[3]: decimation_output[11]
uo[4]: decimation_output[12]
uo[5]: decimation_output[13]
uo[6]: decimation_output[14]
uo[7]: decimation_output[15]
# Bidirectional pins
uio[0]: decimation_output[0]
uio[1]: decimation_output[1]
uio[2]: decimation_output[2]
uio[3]: decimation_output[3]
uio[4]: decimation_output[4]
uio[5]: decimation_output[5]
uio[6]: decimation_output[6]
uio[7]: decimation_output[7]
# Do not change!
yaml_version: 6