From d052830982d4a262aca9c4fa544245a3246d3cd7 Mon Sep 17 00:00:00 2001 From: Guilherme Heck Date: Fri, 9 Oct 2020 17:45:24 -0300 Subject: [PATCH] Updated NI version. Now NI set the header based on memory mapped registers. --- .../orca-ni/orca-ni-recv-Nflit.vhd | 8 +- .../orca-ni/orca-ni-send-Nflit.vhd | 15 +- .../orca-ni/orca-ni-top.vhd | 2 + rtl/orca-minimal-soc.vhd | 13 +- rtl/orca-tile-proc.vhd | 5 +- sim/mpsoc/app/app.txt | 248 +++++++++--------- sim/mpsoc/app/packet.txt | 13 +- sim/mpsoc/tb/SC_InputModule_2x2.h | 2 +- 8 files changed, 167 insertions(+), 139 deletions(-) diff --git a/rtl/network-interfaces/orca-ni/orca-ni-recv-Nflit.vhd b/rtl/network-interfaces/orca-ni/orca-ni-recv-Nflit.vhd index 9dbbdac..1828512 100644 --- a/rtl/network-interfaces/orca-ni/orca-ni-recv-Nflit.vhd +++ b/rtl/network-interfaces/orca-ni/orca-ni-recv-Nflit.vhd @@ -232,14 +232,14 @@ begin recv_copy_size <= (others => '1'); stall <= '0'; --enable cpu to use memory until next packet arrival recv_copy_addr <= (others => '0'); - if r_rx = '1' then - recv_copy_addr <= recv_copy_addr + 1; --advance mem. to 2nd position - end if; +-- if r_rx = '1' then +-- recv_copy_addr <= recv_copy_addr + 1; --advance mem. to 2nd position +-- end if; -- wait for the size flit to arrive when R_WAIT_FLIT_SIZE => if r_rx = '1' then - recv_copy_addr <= recv_copy_addr + 1; --advances mem ptr. +-- recv_copy_addr <= recv_copy_addr + 1; --advances mem ptr. recv_copy_size <= size(TAM_FLIT-1 downto 0) - 1; recv_status <= size(RAM_WIDTH/2 - 1 downto 0); -- notify recv flits to cpu end if; diff --git a/rtl/network-interfaces/orca-ni/orca-ni-send-Nflit.vhd b/rtl/network-interfaces/orca-ni/orca-ni-send-Nflit.vhd index 42aeebd..d73a345 100644 --- a/rtl/network-interfaces/orca-ni/orca-ni-send-Nflit.vhd +++ b/rtl/network-interfaces/orca-ni/orca-ni-send-Nflit.vhd @@ -28,6 +28,7 @@ entity orca_ni_send is -- dma programming (must be mapped into memory space) send_start : in std_logic; prog_address : in std_logic_vector((RAM_WIDTH - 1) downto 0); + prog_dest : in std_logic_vector((RAM_WIDTH - 1) downto 0); prog_size : in std_logic_vector((RAM_WIDTH - 1) downto 0); send_status : out std_logic ); @@ -152,16 +153,16 @@ end process; when S_SEND_DESTINY => if r_credit_i = '1' then r_tx <= '1'; - send_copy_size <= send_copy_size - 1; - send_copy_addr <= send_copy_addr + 4; - send_copy_addr_dly <= send_copy_addr; +-- send_copy_size <= send_copy_size - 1; +-- send_copy_addr <= send_copy_addr + 4; +-- send_copy_addr_dly <= send_copy_addr; end if; when S_SEND_SIZE => if r_credit_i = '1' then - send_copy_size <= send_copy_size - 1; - send_copy_addr <= send_copy_addr + 4; - send_copy_addr_dly <= send_copy_addr; +-- send_copy_size <= send_copy_size - 1; +-- send_copy_addr <= send_copy_addr + 4; +-- send_copy_addr_dly <= send_copy_addr; end if; when S_PAYLOAD => --copy from memory to the output buffer @@ -206,7 +207,7 @@ end process; mux(i) <= m_data_i((TAM_FLIT*(i+1)) - 1 downto (TAM_FLIT*i)) when send_state = S_PAYLOAD else (others => '0'); end generate; - r_data_o <= half_flit_complement & m_data_i(RAM_WIDTH/4+TAM_FLIT/4-1 downto RAM_WIDTH/4) & m_data_i(TAM_FLIT/4-1 downto 0) when previous_state = S_SEND_DESTINY else m_data_i(TAM_FLIT-INTEGER(CEIL(LOG2(REAL(RAM_WIDTH/TAM_FLIT))))-1 downto 0) & shift when previous_state = S_SEND_SIZE else mux(to_integer(unsigned(shift))) when previous_state = S_PAYLOAD else (others => '0'); + r_data_o <= half_flit_complement & prog_dest(RAM_WIDTH/4+TAM_FLIT/4-1 downto RAM_WIDTH/4) & prog_dest(TAM_FLIT/4-1 downto 0) when previous_state = S_SEND_DESTINY else prog_size(TAM_FLIT-INTEGER(CEIL(LOG2(REAL(RAM_WIDTH/TAM_FLIT))))-1 downto 0) & shift when previous_state = S_SEND_SIZE else mux(to_integer(unsigned(shift))) when previous_state = S_PAYLOAD else (others => '0'); stall <= r_stall; diff --git a/rtl/network-interfaces/orca-ni/orca-ni-top.vhd b/rtl/network-interfaces/orca-ni/orca-ni-top.vhd index 8f6120f..33e6da5 100644 --- a/rtl/network-interfaces/orca-ni/orca-ni-top.vhd +++ b/rtl/network-interfaces/orca-ni/orca-ni-top.vhd @@ -38,6 +38,7 @@ entity orca_ni_top is recv_start : in std_logic; send_status : out std_logic; recv_status : out std_logic_vector((RAM_WIDTH/2 - 1) downto 0); + prog_dest : in std_logic_vector((RAM_WIDTH - 1) downto 0); prog_address : in std_logic_vector((RAM_WIDTH - 1) downto 0); prog_size : in std_logic_vector((RAM_WIDTH - 1) downto 0) @@ -80,6 +81,7 @@ begin send_status => send_status_s, prog_address => prog_address, + prog_dest => prog_dest, prog_size => prog_size ); diff --git a/rtl/orca-minimal-soc.vhd b/rtl/orca-minimal-soc.vhd index 5d78599..d13aba7 100644 --- a/rtl/orca-minimal-soc.vhd +++ b/rtl/orca-minimal-soc.vhd @@ -6,7 +6,7 @@ -- -- Very simple configuration for a minimal SoC. Only a single GPIO port -- a counter and timer are included in this version. --- NI: registradores: NI_ADDRESS (0xe0ff8000), NI_STATUS (0xe0ff8010), NI_MEM_ADDR (0xe0ff8020), NI_PCT_SIZE (0xe0ff8030) +-- NI: registradores: NI_ADDRESS (0xe0ff8000), NI_STATUS (0xe0ff8010), NI_MEM_ADDR (0xe0ff8020), NI_PCT_SIZE (0xe0ff8030), NI_PCT_DEST (0xe0ff8040) @@ -38,7 +38,8 @@ entity peripherals is ni_intr : in std_logic; ni_recv_size : in std_logic_vector((RAM_WIDTH/2 - 1) downto 0); ni_mem_addr : out std_logic_vector((RAM_WIDTH - 1) downto 0); - ni_pct_size : out std_logic_vector((RAM_WIDTH - 1) downto 0) + ni_pct_size : out std_logic_vector((RAM_WIDTH - 1) downto 0); + ni_pct_dest : out std_logic_vector((RAM_WIDTH - 1) downto 0) ); end peripherals; @@ -50,7 +51,7 @@ architecture peripherals_arch of peripherals is signal paaltcfg0, s0cause, gpiocause, gpiocause_inv, gpiomask, timercause, timercause_inv, timermask: std_logic_vector(3 downto 0); signal paddr, paout, pain, pain_inv, pain_mask: std_logic_vector(7 downto 0); - signal timer0, ni_addr, ni_size : std_logic_vector(31 downto 0); + signal timer0, ni_addr, ni_size, ni_dest : std_logic_vector(31 downto 0); signal timer1, timer1_ctc, timer1_ocr: std_logic_vector(15 downto 0); signal timer1_pre: std_logic_vector(2 downto 0); signal timer1_set: std_logic; @@ -91,6 +92,7 @@ begin ni_reload <= ni_reld; ni_mem_addr <= ni_addr; ni_pct_size <= ni_size; + ni_pct_dest <= ni_dest; -- address decoder, read from peripheral registers process(clk_i, rst_i, segment, class, device, funct) @@ -114,6 +116,8 @@ begin data_o <= ni_addr; -- NI_MEM_ADDR (RW) when "0011" => data_o <= ni_size; -- NI_PCT_SIZE (RW) + when "0100" => + data_o <= ni_dest; -- NI_PCT_DEST (RW) when others => data_o <= (others => '0'); end case; @@ -221,6 +225,7 @@ begin ni_recv_strt <= '0'; ni_addr <= (others => '0'); ni_size <= (others => '0'); + ni_dest <= (others => '0'); elsif clk_i'event and clk_i = '1' then if sel_i = '1' and wr_i = '1' then case segment is @@ -238,6 +243,8 @@ begin ni_addr <= data_i; -- NI_MEM_ADDR (RW) when "0011" => ni_size <= data_i; -- NI_PCT_SIZE (RW) + when "0100" => + ni_dest <= data_i; -- NI_PCT_DEST (RW) when others => end case; when others => diff --git a/rtl/orca-tile-proc.vhd b/rtl/orca-tile-proc.vhd index edccbfc..785e99c 100644 --- a/rtl/orca-tile-proc.vhd +++ b/rtl/orca-tile-proc.vhd @@ -67,6 +67,7 @@ architecture orca_processing_tile of orca_processing_tile is signal recv_status : std_logic_vector(((RAM_WIDTH/2) - 1) downto 0); signal prog_address : std_logic_vector((RAM_WIDTH - 1) downto 0); signal prog_size : std_logic_vector((RAM_WIDTH - 1) downto 0); + signal prog_dest : std_logic_vector((RAM_WIDTH - 1) downto 0); signal n_addr_o : std_logic_vector((RAM_WIDTH - 1) downto 0); signal n_data_o : std_logic_vector((RAM_WIDTH - 1) downto 0); @@ -204,7 +205,8 @@ begin ni_intr => ni_intr, ni_recv_size => recv_status, ni_mem_addr => prog_address, - ni_pct_size => prog_size + ni_pct_size => prog_size, + ni_pct_dest => prog_dest ); @@ -279,6 +281,7 @@ begin send_status => send_status, recv_status => recv_status, prog_address => prog_address, + prog_dest => prog_dest, prog_size => prog_size ); diff --git a/sim/mpsoc/app/app.txt b/sim/mpsoc/app/app.txt index c60cbc4..16f1416 100644 --- a/sim/mpsoc/app/app.txt +++ b/sim/mpsoc/app/app.txt @@ -1,13 +1,13 @@ 97060000 -83a68639 +83a6863b 17060000 -03264639 +0326463b 97010000 -83a14138 +83a1413a 17010000 -03218138 +0321813a 17020000 -0322c237 +0322c239 137202fc ef004009 370d00e0 @@ -48,72 +48,96 @@ ef004009 67800000 b7070040 37070040 -9387c73a -1307c73a +9387c73c +1307c73c 63e4e700 6f000001 93874700 23ae07fe 6ff01fff -130101f1 -2326110e -ef00000c +1301019b +23261164 +ef000012 9307a000 +2322f132 +2322f100 +2324f100 +9307b000 +2326f100 +9307c000 +2328f100 +9307d000 232af100 -b7170c0d -9387a7b0 +9307e000 232cf100 -b7171011 -9387e7f0 +9307f000 232ef100 -b7170000 -93872731 -9306a000 -13068101 -93050000 -13050000 -23260100 -23280100 -2310f102 -ef00400f -ef00c005 +93070001 +2320f102 +93071001 +2322f102 +93072001 +2324f102 +13050100 +93073001 +23200132 +23200100 +2326f102 +ef000016 +ef00c009 +e30e05fe +ef004005 e30e05fe -93068101 -13064101 -93050101 -1305c100 -ef008018 -93078101 -93062102 -03c70700 -93871700 +13050132 +ef00401a +93070132 +93068134 +03a78700 +93874700 13071700 -a38fe7fe +23a2e700 e398d7fe -0325c100 -83264101 -83250101 -13068101 -ef00800a -8320c10e +ef00c003 +2324a132 +ef00c004 +2326a132 +13050132 +ef004011 +8320c164 13050000 -1301010f +13010165 67800000 b7070040 -83a7c738 +83a74739 +03c50700 +13751500 +67800000 +b7070040 +83a7073a +03a50700 +13558500 +1375f50f +67800000 +b7070040 +83a7073a +03a50700 +1375f50f +67800000 +b7070040 +83a7c739 03a50700 13150501 13550501 67800000 b7070040 -83a7c738 +83a7c739 03a50700 13151500 13551500 23a0a700 67800000 b7070040 -03a7c738 +03a7c739 83270700 630a0500 b7060020 @@ -125,7 +149,7 @@ b70600e0 b3f7d700 6ff0dffe b7070040 -03a7c738 +03a7c739 83270700 630a0500 b7060040 @@ -136,100 +160,84 @@ b70600c0 9386f6ff b3f7d700 6ff0dffe -93f73600 -b337f000 -93d62600 -b386d700 -13882600 -93172800 -130101ff -1387f700 -23248100 -23261100 -13040101 -137707ff +b7070040 +83a70739 13158500 -3301e140 93f5f50f -13070100 3365b500 -2322d700 -2320a700 -938687ff -93070000 -6392d704 +23a0a700 +03a70700 +13170701 +13570701 +23a0e700 +67800000 +130101ff +23248100 +83552500 +13040500 +03550500 +23261100 +13048400 +eff09ffb b7070040 -83a78738 +0327c4ff +83a78739 13051000 -23a00701 -b7070040 -83a74738 23a0e700 -eff0dff5 +b7070040 +83a7c738 +23a08700 +eff05ff6 13000000 -13050000 -eff01ff5 -130104ff -8320c100 03248100 +8320c100 +13050000 13010101 -67800000 -3305f600 -03250500 -b305f700 -93874700 -23a4a500 -6ff09ffa -130101fe -232c8100 -232a9100 -23282101 -23263101 -232e1100 -13090500 -93890500 -93040600 -13840600 -eff05fe9 -630c0506 -eff0dfe8 +6ff0dff4 +130101ff +23229100 +23261100 +23248100 +93040500 +eff01fed +630e0504 b7070040 -83a78738 -23a0a700 +03a74400 +83a78739 +23a0e700 b7070040 -83a74738 -23a08700 -eff01fe7 -23a0a400 +83a7c738 +13878400 +23a0e700 +eff09fea +13040500 13051000 -eff09fe9 +eff01fed 13000000 13050000 -eff0dfe8 -83470400 -23a0f900 -83471400 -2320f900 -83474400 -03a50400 -3305f540 -3335a000 -8320c101 -03248101 -83244101 -03290101 -8329c100 -13010102 +eff05fec +03a54400 +3305a440 +8320c100 +03248100 +83244100 +13010101 67800000 1305f0ff -6ff01ffe +6ff09ffe 2080ffe0 +4080ffe0 +1004f0e1 3080ffe0 1080ffe0 +0080ffe0 +00000000 +00000000 +00000000 00000000 -840b0040 -ac030040 -ac030040 +8c0b0040 +cc030040 +cc030040 00000140 ffffffff 00000000 diff --git a/sim/mpsoc/app/packet.txt b/sim/mpsoc/app/packet.txt index b518ded..479c09d 100644 --- a/sim/mpsoc/app/packet.txt +++ b/sim/mpsoc/app/packet.txt @@ -1,3 +1,10 @@ -0D0C0B0A -11100F0E -FFFF1312 +0000000A +0000000B +0000000C +0000000D +0000000E +0000000F +00000010 +00000011 +00000012 +00000013 diff --git a/sim/mpsoc/tb/SC_InputModule_2x2.h b/sim/mpsoc/tb/SC_InputModule_2x2.h index c48fc61..73c9d1f 100644 --- a/sim/mpsoc/tb/SC_InputModule_2x2.h +++ b/sim/mpsoc/tb/SC_InputModule_2x2.h @@ -188,7 +188,7 @@ void inline inputmodule::TrafficGenerator(){ outData = 0; // printf("\n\n\n\t\t\t******** Wait to send packet ****************\n\n\n\n"); wait(3,SC_US); - sprintf(temp,"./mpsoc/app/packet_endianness.txt"); + sprintf(temp,"./mpsoc/app/packet.txt"); numlines=numberoflines(temp); printf("\n\n\n\t\t\t******** Number of lines in PACKET.TXT: %d ****************\n\n\n\n",numlines); Input = fopen(temp,"r");