From 3bcebcc8678e769afcbb029a8901c80654e98ee8 Mon Sep 17 00:00:00 2001 From: Alincak Date: Wed, 10 Jan 2024 19:16:42 +0300 Subject: [PATCH] Update SystemCoreClock calculation with the inclusion of the OVR --- .../Maxim/MAX32662/Source/system_max32662.c | 21 +++++++++++++++++++ .../Maxim/MAX32672/Source/system_max32672.c | 16 ++++++++++++++ .../Maxim/MAX32675/Source/system_max32675.c | 16 ++++++++++++++ 3 files changed, 53 insertions(+) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Source/system_max32662.c b/Libraries/CMSIS/Device/Maxim/MAX32662/Source/system_max32662.c index 5d4053ebaad..6dd86512bd7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Source/system_max32662.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Source/system_max32662.c @@ -28,6 +28,7 @@ #include #include "max32662.h" #include "gcr_regs.h" +#include "pwrseq_regs.h" #include "mxc_sys.h" extern void (*const __isr_vector[])(void); @@ -82,6 +83,26 @@ __weak void SystemCoreClockUpdate(void) break; } + if (clk_src == MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO) { + uint32_t ovr = (MXC_PWRSEQ->lpctrl & MXC_F_PWRSEQ_LPCTRL_OVR); + switch (ovr) { + case MXC_S_PWRSEQ_LPCTRL_OVR_0_9V: + base_freq = base_freq >> 3; + break; + case MXC_S_PWRSEQ_LPCTRL_OVR_1_0V: + base_freq = base_freq >> 1; + break; + case MXC_S_PWRSEQ_LPCTRL_OVR_1_1V: + default: + /* Nothing to do here. + OVR = 1.1V means the clock runs full speed. */ + break; + } + // Get the clock divider + base_freq = base_freq >> ((MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_IPO_DIV) >> + MXC_F_GCR_CLKCTRL_IPO_DIV_POS); + } + div = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_DIV) >> MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS; SystemCoreClock = base_freq >> div; diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Source/system_max32672.c b/Libraries/CMSIS/Device/Maxim/MAX32672/Source/system_max32672.c index 4a2026a279f..f2ba016cf07 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Source/system_max32672.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Source/system_max32672.c @@ -25,6 +25,7 @@ #include "max32672.h" #include "gcr_regs.h" #include "mxc_sys.h" +#include "pwrseq_regs.h" extern void (*const __isr_vector[])(void); @@ -78,6 +79,21 @@ __weak void SystemCoreClockUpdate(void) } // Get the clock divider if (clk_src == MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO) { + uint32_t ovr = (MXC_PWRSEQ->lpcn & MXC_F_PWRSEQ_LPCN_OVR); + switch (ovr) { + case MXC_S_PWRSEQ_LPCN_OVR_0_9V: + base_freq = base_freq >> 3; + break; + case MXC_S_PWRSEQ_LPCN_OVR_1_0V: + base_freq = base_freq >> 1; + break; + case MXC_S_PWRSEQ_LPCN_OVR_1_1V: + default: + /* Nothing to do here. + OVR = 1.1V means the clock runs full speed. */ + break; + } + base_freq = base_freq >> ((MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_IPO_DIV) >> MXC_F_GCR_CLKCTRL_IPO_DIV_POS); } diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Source/system_max32675.c b/Libraries/CMSIS/Device/Maxim/MAX32675/Source/system_max32675.c index 0bc99185c6d..25afbb35b0f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Source/system_max32675.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Source/system_max32675.c @@ -25,6 +25,7 @@ #include "max32675.h" #include "gcr_regs.h" #include "mxc_sys.h" +#include "pwrseq_regs.h" extern void (*const __vector_table[])(void); @@ -80,6 +81,21 @@ __weak void SystemCoreClockUpdate(void) } // Get the clock divider if (clk_src == MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO) { + uint32_t ovr = (MXC_PWRSEQ->lpcn & MXC_F_PWRSEQ_LPCN_OVR); + switch (ovr) { + case MXC_S_PWRSEQ_LPCN_OVR_0_9V: + base_freq = base_freq >> 3; + break; + case MXC_S_PWRSEQ_LPCN_OVR_1_0V: + base_freq = base_freq >> 1; + break; + case MXC_S_PWRSEQ_LPCN_OVR_1_1V: + default: + /* Nothing to do here. + OVR = 1.1V means the clock runs full speed. */ + break; + } + base_freq = base_freq >> ((MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_IPO_DIV) >> MXC_F_GCR_CLKCTRL_IPO_DIV_POS); }