diff --git a/docs/projects/index.rst b/docs/projects/index.rst index 2889d50e5d..e4ee318233 100644 --- a/docs/projects/index.rst +++ b/docs/projects/index.rst @@ -60,5 +60,6 @@ Contents CN0579 CN0585 MAX96724 + QUAD_ADAQ7768-1 PULSAR-ADC PULSAR-LVDS diff --git a/docs/projects/quad_adaq77681/index.rst b/docs/projects/quad_adaq77681/index.rst new file mode 100644 index 0000000000..1a20472fbb --- /dev/null +++ b/docs/projects/quad_adaq77681/index.rst @@ -0,0 +1,268 @@ +.. _quad_adaq77681: + +QUAD_ADAQ77681 HDL project +================================================================================= + +Overview +--------------------------------------------------------------------------------- + +The :adi:`ADAQ7768-1` is a 24-bit precision data acquisition (DAQ) μModule system +that encapsulates signal conditioning, conversion, and processing blocks into one +system-in-package (SiP) design for the rapid development of highly compact, +high-performance precision DAQ systems. + +The :adi:`ADAQ7768-1` consists of a low-noise, low-bias current, high-bandwidth +programmable gain instrumentation amplifier (PGIA) also capable of signal +amplification and signal attenuation while maintaining high input impedance, a +fourth-order, low-noise, linear phase anti-aliasing filter, a low-noise, +low-distortion, high-bandwidth ADC driver plus an optional linearity boost +buffer. Also, contains a high-performance medium bandwidth 24-bit Σ-Δ ADC with +programmable digital filter,a low-noise, low-dropout linear regulator, reference +buffers and critical passive components required for the signal chain. + +The :adi:`ADAQ7768-1` supports fully differential input signal with a maximum +range of ±12.6 V. It has an input common-mode voltage range of ±12 V with +excellent common-mode rejection ratio (CMRR). The input signal is fully buffered +with very low input bias current of 2 pA typical. This allows easy input +impedance matching and enables the :adi:`ADAQ7768-1` to directly interface to +sensors with high output impedance. + +The analog-to-digital converter (ADC) inside the :adi:`ADAQ7768-1` is a +high-performance, 24-bit precision, single-channel sigma-delta converter with +excellent AC performance and DC precision, and the throughput rate of 256 kSPS +from a 16.384 MHz MCLK. + +The :adi:`ADAQ7768-1` device has an operating temperature range of −40°C to +85°C +and is available in a 12.00 mm × 6.00 mm 84-ball CSP_BGA package with an 0.80 mm +ball pitch, which makes it ideal for multiple channel applications. + +Supported boards +------------------------------------------------------------------------------- + +- QUAD_AD77681 PMB0004 EvalPlus Signal Chain Board + +Supported devices +------------------------------------------------------------------------------- + +- :adi:`ADAQ7768-1` + +Supported carriers +------------------------------------------------------------------------------- + +- :xilinx:`ZedBoard ` on FMC slot + +Block design +------------------------------------------------------------------------------- + +Block diagram +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The data path and clock domains are depicted in the below diagram: + +QUAD_ADAQ77681 +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. image:: quad_adaq77681_hdl.svg + :width: 800 + :align: center + :alt: QUAD_ADAQ77681 HDL block diagram + +CPU/Memory interconnects addresses +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The addresses are dependent on the architecture of the FPGA, having an offset +added to the base address from HDL (see more at :ref:`architecture`). + + +========================= =============== +Instance Zynq +========================= =============== +quad_adaq77681_axi_regmap 0x44A0_0000 +axi_qadc_dma 0x44A3_0000 +spi_clkgen 0x44A7_0000 +mclk_clkgen 0x44B0_0000 +========================= =============== + +I2C connections +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. list-table:: + :widths: 20 20 20 20 20 + :header-rows: 1 + + * - I2C type + - I2C manager instance + - Alias + - Address + - I2C subordinate + * - PL + - iic_fmc + - axi_iic_fmc + - 0x4162_0000 + - --- + * - PL + - iic_main + - axi_iic_main + - 0x4160_0000 + - --- + +SPI connections +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. list-table:: + :widths: 25 25 25 25 + :header-rows: 1 + + * - SPI type + - SPI manager instance + - SPI subordinate + - CS + * - PL + - axi_spi_engine + - quad_adaq77681 + - 0 + +GPIOs +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The Software GPIO number is calculated as follows: + +- Zynq-7000: if PS7 is used, then offset is 54 + +.. list-table:: + :widths: 25 25 25 25 + :header-rows: 2 + + * - GPIO signal + - Direction + - HDL GPIO EMIO + - Software GPIO + * - + - (from FPGA view) + - + - Zynq-7000 + * - qadc_pgood[3:0] + - INOUT + - 44:41 + - 98:95 + * - qadc_muxa[1:0] + - INOUT + - 40:39 + - 94:93 + * - qadc_muxb[1:0] + - INOUT + - 38:37 + - 92:91 + * - qadc_muxc[1:0] + - INOUT + - 36:35 + - 90:89 + * - qadc_muxd[1:0] + - INOUT + - 34:33 + - 88:87 + * - qadc_sync + - INOUT + - 32 + - 86 + +Interrupts +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Below are the Programmable Logic interrupts used in this project. + +=================== === ========== =========== +Instance name HDL Linux Zynq Actual Zynq +=================== === ========== =========== +axi_qadc_dma 13 57 89 +quad_adaq77681 12 56 88 +=================== === ========== =========== + +Building the HDL project +------------------------------------------------------------------------------- + +The design is built upon ADI's generic HDL reference design framework. +ADI distributes the bit/elf files of these projects as part of the +:dokuwiki:`ADI Kuiper Linux `. +If you want to build the sources, ADI makes them available on the +:git-hdl:`HDL repository `. To get the source you must +`clone `__ +the HDL repository, and then build the project as follows: + +**Linux/Cygwin/WSL** + +.. code-block:: + :linenos: + + user@analog:~$ cd hdl/projects/quad_adaq77681/zed + user@analog:~/hdl/projects/quad_adaq77681/zed$ make + +A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. + +Hardware related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Product datasheets: + + - :adi:`ADAQ7768-1` + +HDL related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :git-hdl:`quad_adaq77681 HDL project source code ` + +.. list-table:: + :widths: 30 40 30 + :header-rows: 1 + + * - IP name + - Source code link + - Documentation link + * - AXI_CLKGEN + - :git-hdl:`library/axi_clkgen ` + - :ref:`here ` + * - AXI_DMAC + - :git-hdl:`library/axi_dmac ` + - :ref:`here ` + * - AXI_HDMI_TX + - :git-hdl:`library/axi_hdmi_tx ` + - :ref:`here ` + * - AXI_I2S_ADI + - :git-hdl:`library/axi_i2s_adi ` + - --- + * - AXI_SPDIF_TX + - :git-hdl:`library/axi_spdif_tx ` + - --- + * - AXI_SYSID + - :git-hdl:`library/axi_sysid ` + - :ref:`here ` + * - AXI_SPI_ENGINE + - :git-hdl:`library/spi_engine/axi_spi_engine ` + - :ref:`here ` + * - SPI_ENGINE_EXECUTION + - :git-hdl:`library/spi_engine/spi_engine_execution ` + - :ref:`here ` + * - SPI_ENGINE_INTERCONNECT + - :git-hdl:`library/spi_engine/spi_engine_interconnect ` + - :ref:`here ` + * - SPI_ENGINE_OFFLOAD + - :git-hdl:`library/spi_engine/spi_engine_offload` + - :ref:`here ` + * - SYSID_ROM + - :git-hdl:`library/sysid_rom ` + - :ref:`here ` + * - UTIL_I2C_MIXER + - :git-hdl:`library/util_i2c_mixer ` + - --- + +- :ref:`SPI Engine Framework documentation ` + +Software related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :git-linux:`QUAD_ADAQ7768-1 Linux driver source code ` +- ADAQ7768-1 Linux device tree :git-linux:`zynq-zed-adv7511-quad-adaq7768-1-evb.dts ` + +.. include:: ../common/more_information.rst + +.. include:: ../common/support.rst diff --git a/docs/projects/quad_adaq77681/quad_adaq77681_hdl.svg b/docs/projects/quad_adaq77681/quad_adaq77681_hdl.svg new file mode 100644 index 0000000000..505c79dcc5 --- /dev/null +++ b/docs/projects/quad_adaq77681/quad_adaq77681_hdl.svg @@ -0,0 +1,2154 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + + + Ethernet + UART + DDRx + SPI + I2C + Interrupts + + Timer + + + MEMORY INTERCONNECT + ZedBoard + + + FMC CONNECTOR + + + QUAD_AD7768-1_DMA + 20MHz + + + + ARM (Zynq) + Zynq SoC + + + + + + MISO/SDI[3:0] + SPI ENGINE FRAMEWORK + CS[3:0] + MOSI/SDO + SCLK + + + + + + OFFLOAD + + INTER-CONNECT + + + EXECUTION + + AXI REGMAP + + + + + AXI CLKGEN + + AND GATE + spi_clk = 120 MHz + sys_clk = 100MHz + + + + + + + + + READY[3:0] + + + + AXI CLKGEN + + 50MHz + 32.768MHz + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 64b + + + 128b + trigger + + + + diff --git a/docs/regmap/adi_regmap_spi_engine.txt b/docs/regmap/adi_regmap_spi_engine.txt index 681c37d45d..74ce6ce614 100644 --- a/docs/regmap/adi_regmap_spi_engine.txt +++ b/docs/regmap/adi_regmap_spi_engine.txt @@ -354,16 +354,14 @@ ENDFIELD REG 0x3a -SDI_FIFO +SDI_FIFO_0 ENDREG FIELD [31:0] 0xXXXXXXXX -SDI_FIFO +SDI_FIFO_0 RO -SDI FIFO register. Reading from this register removes the first entry from the SDI FIFO. -Reading this register when the SDI FIFO is empty will return undefined data. -Writing to it has no effect. +Store SDI's 32 bits MSB, if exists. ENDFIELD ############################################################################################ @@ -371,12 +369,12 @@ ENDFIELD REG 0x3b -SDI_FIFO_MSB +SDI_FIFO_1 ENDREG FIELD [31:0] 0xXXXXXXXX -SDI_FIFO_MSB +SDI_FIFO_1 RO Store SDI's 32 bits MSB, if exists. ENDFIELD @@ -386,17 +384,59 @@ ENDFIELD REG 0x3c -SDI_FIFO_PEEK +SDI_FIFO_2 ENDREG FIELD [31:0] 0xXXXXXXXX -SDI_FIFO_PEEK +SDI_FIFO_2 RO -SDI FIFO peek register. -Reading from this register returns the first entry from the SDI FIFO, but without removing -it from the FIFO. Reading this register when the SDI FIFO is empty will return undefined -data. Writing to it has no effect. +Store SDI's 32 bits MSB, if exists. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x3d +SDI_FIFO_3 +ENDREG + +FIELD +[31:0] 0xXXXXXXXX +SDI_FIFO_3 +RO +Store SDI's 32 bits MSB, if exists. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x3e +SDI_FIFO_4 +ENDREG + +FIELD +[31:0] 0xXXXXXXXX +SDI_FIFO_4 +RO +Store SDI's 32 bits MSB, if exists. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x3f +SDI_FIFO_5 +ENDREG + +FIELD +[31:0] 0xXXXXXXXX +SDI_FIFO_5 +RO +Store SDI's 32 bits MSB, if exists. ENDFIELD ############################################################################################ @@ -404,14 +444,14 @@ ENDFIELD REG 0x40 -OFFLOAD0_EN +SDI_FIFO_6 ENDREG FIELD -[31:0] 0x00000000 -OFFLOAD0_EN -RW -Set this bit to enable the offload module. +[31:0] 0xXXXXXXXX +SDI_FIFO_6 +RO +Store SDI's 32 bits MSB, if exists. ENDFIELD ############################################################################################ @@ -419,14 +459,14 @@ ENDFIELD REG 0x41 -OFFLOAD0_STATUS +SDI_FIFO_7 ENDREG FIELD -[31:0] 0x00000000 -OFFLOAD0_STATUS +[31:0] 0xXXXXXXXX +SDI_FIFO_7 RO -Offload status register. +Store SDI's 32 bits MSB, if exists. ENDFIELD ############################################################################################ @@ -481,6 +521,180 @@ ENDFIELD ############################################################################################ ############################################################################################ +REG +0x46 +OFFLOAD0_EN +ENDREG + +FIELD +[31:0] 0x00000000 +OFFLOAD0_EN +RW +Set this bit to enable the offload module. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x47 +OFFLOAD0_STATUS +ENDREG + +FIELD +[31:0] 0x00000000 +OFFLOAD0_STATUS +RO +Offload status register. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x48 +SDI_FIFO_PEEK_0 +ENDREG + +FIELD +[31:0] 0xXXXXXXXX +SDI_FIFO_PEEK_0 +RO +SDI FIFO peek register. +Reading from this register returns the first entry from the SDI FIFO, but without removing +it from the FIFO. Reading this register when the SDI FIFO is empty will return undefined +data. Writing to it has no effect. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x49 +SDI_FIFO_PEEK_1 +ENDREG + +FIELD +[31:0] 0xXXXXXXXX +SDI_FIFO_PEEK_1 +RO +SDI FIFO peek register. +Reading from this register returns the first entry from the SDI FIFO, but without removing +it from the FIFO. Reading this register when the SDI FIFO is empty will return undefined +data. Writing to it has no effect. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x4A +SDI_FIFO_PEEK_2 +ENDREG + +FIELD +[31:0] 0xXXXXXXXX +SDI_FIFO_PEEK_2 +RO +SDI FIFO peek register. +Reading from this register returns the first entry from the SDI FIFO, but without removing +it from the FIFO. Reading this register when the SDI FIFO is empty will return undefined +data. Writing to it has no effect. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x4B +SDI_FIFO_PEEK_3 +ENDREG + +FIELD +[31:0] 0xXXXXXXXX +SDI_FIFO_PEEK_3 +RO +SDI FIFO peek register. +Reading from this register returns the first entry from the SDI FIFO, but without removing +it from the FIFO. Reading this register when the SDI FIFO is empty will return undefined +data. Writing to it has no effect. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x4C +SDI_FIFO_PEEK_4 +ENDREG + +FIELD +[31:0] 0xXXXXXXXX +SDI_FIFO_PEEK_4 +RO +SDI FIFO peek register. +Reading from this register returns the first entry from the SDI FIFO, but without removing +it from the FIFO. Reading this register when the SDI FIFO is empty will return undefined +data. Writing to it has no effect. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x4D +SDI_FIFO_PEEK_5 +ENDREG + +FIELD +[31:0] 0xXXXXXXXX +SDI_FIFO_PEEK_5 +RO +SDI FIFO peek register. +Reading from this register returns the first entry from the SDI FIFO, but without removing +it from the FIFO. Reading this register when the SDI FIFO is empty will return undefined +data. Writing to it has no effect. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x4E +SDI_FIFO_PEEK_6 +ENDREG + +FIELD +[31:0] 0xXXXXXXXX +SDI_FIFO_PEEK_6 +RO +SDI FIFO peek register. +Reading from this register returns the first entry from the SDI FIFO, but without removing +it from the FIFO. Reading this register when the SDI FIFO is empty will return undefined +data. Writing to it has no effect. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x4F +SDI_FIFO_PEEK_7 +ENDREG + +FIELD +[31:0] 0xXXXXXXXX +SDI_FIFO_PEEK_7 +RO +SDI FIFO peek register. +Reading from this register returns the first entry from the SDI FIFO, but without removing +it from the FIFO. Reading this register when the SDI FIFO is empty will return undefined +data. Writing to it has no effect. +ENDFIELD + +############################################################################################ +############################################################################################ + REG 0x80 CFG_INFO_0 diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine.v b/library/spi_engine/axi_spi_engine/axi_spi_engine.v index f91e00eb26..8bcbd6bcab 100644 --- a/library/spi_engine/axi_spi_engine/axi_spi_engine.v +++ b/library/spi_engine/axi_spi_engine/axi_spi_engine.v @@ -156,12 +156,15 @@ module axi_spi_engine #( wire sdo_fifo_in_ready; wire sdo_fifo_in_valid; - wire sdi_fifo_out_data_msb_s; wire [SDI_FIFO_ADDRESS_WIDTH-1:0] sdi_fifo_level; wire sdi_fifo_almost_full; wire up_sdi_fifo_almost_full; wire [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_fifo_out_data; + + wire [255:0] sdi_fifo_out_data_int; + assign sdi_fifo_out_data_int = sdi_fifo_out_data; + wire sdi_fifo_out_ready; wire sdi_fifo_out_valid; @@ -325,15 +328,6 @@ module axi_spi_engine #( end end - generate - if (NUM_OF_SDI > 1) begin - // Only the first two SDI data can be recovered through AXI regmap - assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data[DATA_WIDTH+:DATA_WIDTH]; - end else begin - assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data; - end - endgenerate - reg [7:0] offload_sdo_mem_address_width = OFFLOAD0_SDO_MEM_ADDRESS_WIDTH; reg [7:0] offload_cmd_mem_address_width = OFFLOAD0_CMD_MEM_ADDRESS_WIDTH; reg [7:0] sdi_fifo_address_width = SDI_FIFO_ADDRESS_WIDTH; @@ -357,11 +351,29 @@ module axi_spi_engine #( 8'h34: up_rdata_ff <= cmd_fifo_room; 8'h35: up_rdata_ff <= sdo_fifo_room; 8'h36: up_rdata_ff <= (sdi_fifo_out_valid == 1) ? sdi_fifo_level + 1 : sdi_fifo_level; /* beacuse of first-word-fall-through */ - 8'h3a: up_rdata_ff <= sdi_fifo_out_data[DATA_WIDTH-1:0]; - 8'h3b: up_rdata_ff <= sdi_fifo_out_data_msb_s; /* store SDI's 32 bits MSB, if exists */ - 8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */ - 8'h40: up_rdata_ff <= {offload0_enable_reg}; - 8'h41: up_rdata_ff <= {offload0_enabled_s}; + + 8'h3a: up_rdata_ff <= sdi_fifo_out_data_int[DATA_WIDTH-1:0]; + 8'h3b: up_rdata_ff <= sdi_fifo_out_data_int[(2*DATA_WIDTH)-1:DATA_WIDTH]; + 8'h3c: up_rdata_ff <= sdi_fifo_out_data_int[(3*DATA_WIDTH)-1:2*DATA_WIDTH]; + 8'h3d: up_rdata_ff <= sdi_fifo_out_data_int[(4*DATA_WIDTH)-1:3*DATA_WIDTH]; + 8'h3e: up_rdata_ff <= sdi_fifo_out_data_int[(5*DATA_WIDTH)-1:4*DATA_WIDTH]; + 8'h3f: up_rdata_ff <= sdi_fifo_out_data_int[(6*DATA_WIDTH)-1:5*DATA_WIDTH]; + 8'h40: up_rdata_ff <= sdi_fifo_out_data_int[(7*DATA_WIDTH)-1:6*DATA_WIDTH]; + 8'h41: up_rdata_ff <= sdi_fifo_out_data_int[(8*DATA_WIDTH)-1:7*DATA_WIDTH]; + + /* PEEK registers */ + + 8'h48: up_rdata_ff <= sdi_fifo_out_data_int[DATA_WIDTH-1:0]; + 8'h49: up_rdata_ff <= sdi_fifo_out_data_int[(2*DATA_WIDTH)-1:DATA_WIDTH]; + 8'h4A: up_rdata_ff <= sdi_fifo_out_data_int[(3*DATA_WIDTH)-1:2*DATA_WIDTH]; + 8'h4B: up_rdata_ff <= sdi_fifo_out_data_int[(4*DATA_WIDTH)-1:3*DATA_WIDTH]; + 8'h4C: up_rdata_ff <= sdi_fifo_out_data_int[(5*DATA_WIDTH)-1:4*DATA_WIDTH]; + 8'h4D: up_rdata_ff <= sdi_fifo_out_data_int[(6*DATA_WIDTH)-1:5*DATA_WIDTH]; + 8'h4E: up_rdata_ff <= sdi_fifo_out_data_int[(7*DATA_WIDTH)-1:6*DATA_WIDTH]; + 8'h4F: up_rdata_ff <= sdi_fifo_out_data_int[(8*DATA_WIDTH)-1:7*DATA_WIDTH]; + + 8'h46: up_rdata_ff <= {offload0_enable_reg}; + 8'h47: up_rdata_ff <= {offload0_enabled_s}; 8'h80: up_rdata_ff <= CFG_INFO_0; 8'h81: up_rdata_ff <= CFG_INFO_1; 8'h82: up_rdata_ff <= CFG_INFO_2; @@ -472,7 +484,8 @@ module axi_spi_engine #( .m_axis_empty(), .m_axis_almost_empty(sdo_fifo_almost_empty)); - assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a; + assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && (up_raddr_s == 8'h3a || up_raddr_s == 8'h3b || up_raddr_s == 8'h3c || up_raddr_s == 8'h3d || + up_raddr_s == 8'h3e || up_raddr_s == 8'h3f || up_raddr_s == 8'h40 || up_raddr_s == 8'h41); util_axis_fifo #( .DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH), diff --git a/projects/quad_adaq77681/Makefile b/projects/quad_adaq77681/Makefile new file mode 100644 index 0000000000..2458d9876a --- /dev/null +++ b/projects/quad_adaq77681/Makefile @@ -0,0 +1,7 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/quad_adaq77681/Readme.md b/projects/quad_adaq77681/Readme.md new file mode 100644 index 0000000000..6dbb206526 --- /dev/null +++ b/projects/quad_adaq77681/Readme.md @@ -0,0 +1,7 @@ +# QUAD-ADAQ7768-1 HDL Project + +Here are some pointers to help you: + * [Board Product Page](https://www.analog.com/EVP-PH0004) + * Parts : [ADAQ7768-1: 24-Bit, 250 kSPS Single Channel Precision μModule Data Acquisition System](https://www.analog.com/adaq7768-1) + * Project Doc: https://analogdevicesinc.github.io/hdl/projects/quad_adaq77681/index.html + * HDL Doc: https://analogdevicesinc.github.io/hdl/projects/quad_adaq77681/index.html diff --git a/projects/quad_adaq77681/common/quad_adaq77681_bd.tcl b/projects/quad_adaq77681/common/quad_adaq77681_bd.tcl new file mode 100644 index 0000000000..21c7d75ffd --- /dev/null +++ b/projects/quad_adaq77681/common/quad_adaq77681_bd.tcl @@ -0,0 +1,87 @@ +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl + +# system level parameters +set NUM_OF_SDI $ad_project_params(NUM_OF_SDI) + +puts "build parameters: NUM_OF_SDI: $NUM_OF_SDI" + +create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 quad_adaq77681_spi + +create_bd_port -dir I -from 3 -to 0 quad_adaq77681_drdy +create_bd_port -dir I quad_adaq77681_mclk_refclk +create_bd_port -dir O quad_adaq77681_xtal2_mclk + +set data_width 32 +set async_spi_clk 1 +set num_cs 4 +set num_sdi $NUM_OF_SDI +set num_sdo 1 +set sdi_delay 1 +set echo_sclk 0 + +set hier_spi_engine quad_adaq77681 + +spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk + +ad_ip_instance axi_clkgen spi_clkgen +ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 10 +ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1 +ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 12 + +ad_connect $sys_cpu_clk spi_clkgen/clk +ad_connect spi_clk spi_clkgen/clk_0 + +ad_ip_instance axi_clkgen mclk_clkgen +ad_ip_parameter mclk_clkgen CONFIG.CLK0_DIV 60 +ad_ip_parameter mclk_clkgen CONFIG.VCO_DIV 1 +ad_ip_parameter mclk_clkgen CONFIG.VCO_MUL 30 + +# dma to receive data stream +ad_ip_instance axi_dmac axi_qadc_dma +ad_ip_parameter axi_qadc_dma CONFIG.DMA_TYPE_SRC 1 +ad_ip_parameter axi_qadc_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_qadc_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_qadc_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_qadc_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_qadc_dma CONFIG.AXI_SLICE_DEST 1 +ad_ip_parameter axi_qadc_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_qadc_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $NUM_OF_SDI * $data_width] +ad_ip_parameter axi_qadc_dma CONFIG.DMA_DATA_WIDTH_DEST 64 + +ad_connect quad_adaq77681_mclk_refclk mclk_clkgen/clk +ad_connect quad_adaq77681_xtal2_mclk mclk_clkgen/clk_0 + +ad_connect spi_clk $hier_spi_engine/spi_clk +ad_connect spi_clk axi_qadc_dma/s_axis_aclk + +ad_connect axi_qadc_dma/s_axis $hier_spi_engine/M_AXIS_SAMPLE +ad_connect $hier_spi_engine/m_spi quad_adaq77681_spi + +ad_connect $sys_cpu_clk $hier_spi_engine/clk +#ad_connect mclk_clkgen/clk_0 $hier_spi_engine/spi_clk +#ad_connect mclk_clkgen/clk_0 axi_qadc_dma/s_axis_aclk +ad_connect sys_cpu_resetn $hier_spi_engine/resetn +ad_connect sys_cpu_resetn axi_qadc_dma/m_dest_axi_aresetn + +ad_ip_instance util_reduced_logic drdy_buf +ad_ip_parameter drdy_buf CONFIG.C_OPERATION {and} +ad_ip_parameter drdy_buf CONFIG.C_SIZE 4 + +ad_connect quad_adaq77681_drdy drdy_buf/Op1 +ad_connect drdy_buf/Res $hier_spi_engine/trigger + +ad_ip_instance util_reduced_logic drdy_chk +ad_ip_parameter drdy_chk CONFIG.C_OPERATION {xor} +ad_ip_parameter drdy_chk CONFIG.C_SIZE 4 + +ad_connect quad_adaq77681_drdy drdy_chk/Op1 + +ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap +ad_cpu_interconnect 0x44a30000 axi_qadc_dma +ad_cpu_interconnect 0x44a70000 spi_clkgen +ad_cpu_interconnect 0x44b00000 mclk_clkgen + +ad_cpu_interrupt "ps-13" "mb-13" axi_qadc_dma/irq +ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq + +ad_mem_hp0_interconnect sys_cpu_clk axi_qadc_dma/m_dest_axi diff --git a/projects/quad_adaq77681/zed/Makefile b/projects/quad_adaq77681/zed/Makefile new file mode 100644 index 0000000000..ca1109e2a1 --- /dev/null +++ b/projects/quad_adaq77681/zed/Makefile @@ -0,0 +1,30 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := quad_adaq77681_zed + +M_DEPS += system_constr.xdc +M_DEPS += ../common/quad_adaq77681_bd.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/zed/zed_system_constr.xdc +M_DEPS += ../../common/zed/zed_system_bd.tcl +M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl +M_DEPS += ../../../library/common/ad_iobuf.v + +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hdmi_tx +LIB_DEPS += axi_i2s_adi +LIB_DEPS += axi_spdif_tx +LIB_DEPS += axi_sysid +LIB_DEPS += spi_engine/axi_spi_engine +LIB_DEPS += spi_engine/spi_engine_execution +LIB_DEPS += spi_engine/spi_engine_interconnect +LIB_DEPS += spi_engine/spi_engine_offload +LIB_DEPS += sysid_rom +LIB_DEPS += util_i2c_mixer + +include ../../scripts/project-xilinx.mk diff --git a/projects/quad_adaq77681/zed/system_bd.tcl b/projects/quad_adaq77681/zed/system_bd.tcl new file mode 100644 index 0000000000..2101e22adf --- /dev/null +++ b/projects/quad_adaq77681/zed/system_bd.tcl @@ -0,0 +1,12 @@ + +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl +source ../common/quad_adaq77681_bd.tcl + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +sysid_gen_sys_init_file + diff --git a/projects/quad_adaq77681/zed/system_constr.xdc b/projects/quad_adaq77681/zed/system_constr.xdc new file mode 100644 index 0000000000..865da60c1d --- /dev/null +++ b/projects/quad_adaq77681/zed/system_constr.xdc @@ -0,0 +1,58 @@ + +# SPI interface + +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports se_spi_sdo] ; ## FMC_LA02_P +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports se_spi_sclk] ; ## FMC_LA01_CC_P + +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports se_spi_sdi[0]] ; ## FMC_LA03_P +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports se_spi_sdi[1]] ; ## FMC_LA04_P +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports se_spi_sdi[2]] ; ## FMC_LA05_P +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports se_spi_sdi[3]] ; ## FMC_LA06_P + +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports se_spi_cs[0]] ; ## FMC_LA08_P +set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports se_spi_cs[1]] ; ## FMC_LA09_P +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports se_spi_cs[2]] ; ## FMC_LA10_P +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25 IOB TRUE} [get_ports se_spi_cs[3]] ; ## FMC_LA11_P + +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports qadc_drdy[0]] ; ## FMC_LA13_P +set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25} [get_ports qadc_drdy[1]] ; ## FMC_LA14_P +set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports qadc_drdy[2]] ; ## FMC_LA15_P +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports qadc_drdy[3]] ; ## FMC_LA16_P + +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports qadc_mclk_refclk] ; ## FMC_CLK0_M2C_P +set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports qadc_xtal2_mclk] ; ## FMC_LA17_CC_P +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports qadc_sync] ; ## FMC_LA12_P + +set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS25} [get_ports qadc_muxa[0]] ; ## FMC_LA22_P +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports qadc_muxa[1]] ; ## FMC_LA23_P +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports qadc_muxb[0]] ; ## FMC_LA24_P +set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports qadc_muxb[1]] ; ## FMC_LA25_P +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports qadc_muxc[0]] ; ## FMC_LA26_P +set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports qadc_muxc[1]] ; ## FMC_LA27_P +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports qadc_muxd[0]] ; ## FMC_LA28_P +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25} [get_ports qadc_muxd[1]] ; ## FMC_LA29_P + +set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS25} [get_ports qadc_pgood[0]] ; ## FMC_LA30_P +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS25} [get_ports qadc_pgood[1]] ; ## FMC_LA30_P +set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports qadc_pgood[2]] ; ## FMC_LA30_P +set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS25} [get_ports qadc_pgood[3]] ; ## FMC_LA30_P + +#create_clock -period 30.5175781 -name qadc_mclk_refclk [get_ports qadc_mclk_refclk] +create_clock -period 32.768 -name qadc_mclk_refclk [get_ports qadc_mclk_refclk] + +## There is a multi-cycle path between the axi_spi_engine's SDO_FIFO and the +# execution's shift register, because we load new data into the shift register +# in every DATA_WIDTH's x 8 cycle. (worst case scenario) +# Set a multi-cycle delay of 8 spi_clk cycle, slightly over constraining the path. + +# rename auto-generated clock for SPIEngine to spi_clk - 16.384MHz +# NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk + +create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*mclk_clkgen*i_mmcm]] -master_clock qadc_mclk_refclk [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*mclk_clkgen*i_mmcm]] + +# relax the SDO path to help closing timing at high frequencies + +set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk] +set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]}] -from [get_clocks spi_clk] +set_multicycle_path -setup 8 -to [get_cells -hierarchical -filter {NAME=~*/left_aligned_reg*}] -from [get_clocks spi_clk] +set_multicycle_path -hold 7 -to [get_cells -hierarchical -filter {NAME=~*/left_aligned_reg*}] -from [get_clocks spi_clk] diff --git a/projects/quad_adaq77681/zed/system_project.tcl b/projects/quad_adaq77681/zed/system_project.tcl new file mode 100644 index 0000000000..9904b65a2b --- /dev/null +++ b/projects/quad_adaq77681/zed/system_project.tcl @@ -0,0 +1,16 @@ + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +adi_project quad_adaq77681_zed 0 [list \ + NUM_OF_SDI [get_env_param NUM_OF_SDI 4]] + +adi_project_files quad_adaq77681_zed [list \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] + +adi_project_run quad_adaq77681_zed + diff --git a/projects/quad_adaq77681/zed/system_top.v b/projects/quad_adaq77681/zed/system_top.v new file mode 100644 index 0000000000..0360972989 --- /dev/null +++ b/projects/quad_adaq77681/zed/system_top.v @@ -0,0 +1,239 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [31:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + + output spdif, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, + + input otg_vbusoc, + + // SPI configuration interface + + output se_spi_sdo, + output se_spi_sclk, + input [ 3:0] se_spi_sdi, + output [ 3:0] se_spi_cs, + + input [ 3:0] qadc_drdy, + + input qadc_mclk_refclk, + output qadc_xtal2_mclk, + inout qadc_sync, + + inout [ 3:0] qadc_pgood, + + inout [ 1:0] qadc_muxa, + inout [ 1:0] qadc_muxb, + inout [ 1:0] qadc_muxc, + inout [ 1:0] qadc_muxd +); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + + // instantiations + + assign gpio_i[63:45] = gpio_o[63:45]; + + ad_iobuf #( + .DATA_WIDTH(13) + ) qadc_gpio ( + .dio_t(gpio_t[44:32]), + .dio_i(gpio_o[44:32]), + .dio_o(gpio_i[44:32]), + .dio_p({qadc_pgood[3], + qadc_pgood[2], + qadc_pgood[1], + qadc_pgood[0], + qadc_muxa[1], + qadc_muxa[0], + qadc_muxb[1], + qadc_muxb[0], + qadc_muxc[1], + qadc_muxc[0], + qadc_muxd[1], + qadc_muxd[0], + qadc_sync + })); + + ad_iobuf #( + .DATA_WIDTH(32) + ) i_iobuf ( + .dio_t(gpio_t[31:0]), + .dio_i(gpio_o[31:0]), + .dio_o(gpio_i[31:0]), + .dio_p(gpio_bd)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_scl ( + .dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .dio_i(iic_mux_scl_o_s), + .dio_o(iic_mux_scl_i_s), + .dio_p(iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_sda ( + .dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .dio_i(iic_mux_sda_o_s), + .dio_o(iic_mux_sda_i_s), + .dio_p(iic_mux_sda)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + .spi0_clk_i (1'b0), + .spi0_clk_o (), + .spi0_csn_0_o (), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (1'b0), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .quad_adaq77681_spi_cs(se_spi_cs), + .quad_adaq77681_spi_sclk(se_spi_sclk), + .quad_adaq77681_spi_sdi(se_spi_sdi), + .quad_adaq77681_spi_sdo(se_spi_sdo), + .quad_adaq77681_spi_sdo_t(), + .quad_adaq77681_drdy(qadc_drdy), + .quad_adaq77681_mclk_refclk(qadc_mclk_refclk), + .quad_adaq77681_xtal2_mclk(qadc_xtal2_mclk), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif)); + +endmodule