diff --git a/library/common/tb/tb_base.v b/library/common/tb/tb_base.v
index 561c60ec3c..0b0000a39c 100644
--- a/library/common/tb/tb_base.v
+++ b/library/common/tb/tb_base.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2020-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
   reg clk = 1'b0;
   reg [3:0] reset_shift = 4'b1111;
diff --git a/library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl b/library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl
index 963f71d6e0..50f0402f13 100644
--- a/library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl
+++ b/library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl
diff --git a/library/intel/adi_jesd204/adi_jesd204_hw.tcl b/library/intel/adi_jesd204/adi_jesd204_hw.tcl
index 4d4fa5e110..0b8b187a5f 100644
--- a/library/intel/adi_jesd204/adi_jesd204_hw.tcl
+++ b/library/intel/adi_jesd204/adi_jesd204_hw.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl
diff --git a/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl b/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl
index fcf72717e3..187a7bce0b 100644
--- a/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl
+++ b/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl
diff --git a/library/intel/jesd204_phy/jesd204_phy_hw.tcl b/library/intel/jesd204_phy/jesd204_phy_hw.tcl
index 919f53acda..f9a6254d45 100644
--- a/library/intel/jesd204_phy/jesd204_phy_hw.tcl
+++ b/library/intel/jesd204_phy/jesd204_phy_hw.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 package require qsys 14.0
 
diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl
index ce4aa54f41..f274d3b031 100644
--- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl
+++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl
diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl
index 95e27ab735..3948f965d1 100644
--- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl
+++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl
index 105b13ab9e..be7f23eb9b 100644
--- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl
+++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 package require qsys 14.0
 source ../../../scripts/adi_env.tcl
diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl
index 2c5f3e23dc..173c375377 100644
--- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl
+++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/scripts/generate_presets.py b/library/jesd204/ad_ip_jesd204_tpl_dac/scripts/generate_presets.py
index 47699754ea..46696f67ae 100755
--- a/library/jesd204/ad_ip_jesd204_tpl_dac/scripts/generate_presets.py
+++ b/library/jesd204/ad_ip_jesd204_tpl_dac/scripts/generate_presets.py
@@ -43,7 +43,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 ###############################################################################
 
 import math
diff --git a/library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.tcl b/library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.tcl
index 71595d3600..1d2e244366 100644
--- a/library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.tcl
+++ b/library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/axi_jesd204_common/jesd204_up_common.v b/library/jesd204/axi_jesd204_common/jesd204_up_common.v
index 90b88f5a40..5122426650 100755
--- a/library/jesd204/axi_jesd204_common/jesd204_up_common.v
+++ b/library/jesd204/axi_jesd204_common/jesd204_up_common.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v b/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v
index fb72040be3..743110eb42 100755
--- a/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v
+++ b/library/jesd204/axi_jesd204_common/jesd204_up_sysref.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v
index d249eb6dc8..c78141f608 100755
--- a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v
+++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.sdc b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.sdc
index f31812bbb0..c5f250d6ac 100644
--- a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.sdc
+++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.sdc
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 set script_dir [file dirname [info script]]
 
diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc
index a6c6d4c644..98a17c0000 100755
--- a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc
+++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2017-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 set axi_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
 set core_clk [get_clocks -of_objects [get_ports core_clk]]
diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl
index 7fe1d3ec6f..75713b0122 100755
--- a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl
+++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 package require qsys 14.0
 
diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl
index 3b57c7508d..4a7586ed10 100755
--- a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl
+++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ooc.ttcl b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ooc.ttcl
index 7445af1d07..34414a83d6 100644
--- a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ooc.ttcl
+++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ooc.ttcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2019-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 <: setFileUsedIn { out_of_context synthesis implementation } :>
 <: ;#Component and file information :>
diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v b/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v
index 21efd38eb2..7f0c5748c4 100755
--- a/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v
+++ b/library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v b/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v
index b47c25729c..d7d65ada92 100755
--- a/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v
+++ b/library/jesd204/axi_jesd204_rx/jesd204_up_rx.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v b/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v
index a9598ca2f1..275c3a14b9 100755
--- a/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v
+++ b/library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v
index 63bcd7a21a..7b58da318b 100755
--- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v
+++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.sdc b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.sdc
index 8953bcdf9a..e9895702b4 100644
--- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.sdc
+++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.sdc
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 set script_dir [file dirname [info script]]
 
diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc
index 57ec0447f9..4c73db0369 100644
--- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc
+++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2017-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 set axi_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
 set core_clk [get_clocks -of_objects [get_ports core_clk]]
diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl
index ccf881cd52..1a8918957b 100644
--- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl
+++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 package require qsys 14.0
 
diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl
index a3a5405e02..dcb5deae76 100644
--- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl
+++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl
index 7445af1d07..34414a83d6 100644
--- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl
+++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2019-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 <: setFileUsedIn { out_of_context synthesis implementation } :>
 <: ;#Component and file information :>
diff --git a/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v b/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v
index 09a28db683..1500b3cfc2 100755
--- a/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v
+++ b/library/jesd204/axi_jesd204_tx/jesd204_up_tx.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/interfaces/interfaces_ip.tcl b/library/jesd204/interfaces/interfaces_ip.tcl
index b2fda4b8a8..840c2dbebf 100755
--- a/library/jesd204/interfaces/interfaces_ip.tcl
+++ b/library/jesd204/interfaces/interfaces_ip.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/jesd204_common/jesd204_common_ip.tcl b/library/jesd204/jesd204_common/jesd204_common_ip.tcl
index 4ec3ed9121..1153730990 100755
--- a/library/jesd204/jesd204_common/jesd204_common_ip.tcl
+++ b/library/jesd204/jesd204_common/jesd204_common_ip.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/jesd204_common/jesd204_crc12.v b/library/jesd204/jesd204_common/jesd204_crc12.v
index 22315dba37..d4f8b32214 100644
--- a/library/jesd204/jesd204_common/jesd204_crc12.v
+++ b/library/jesd204/jesd204_common/jesd204_crc12.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_common/jesd204_eof_generator.v b/library/jesd204/jesd204_common/jesd204_eof_generator.v
index fff361a529..88fc5b173f 100644
--- a/library/jesd204/jesd204_common/jesd204_eof_generator.v
+++ b/library/jesd204/jesd204_common/jesd204_eof_generator.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_common/jesd204_frame_align_replace.v b/library/jesd204/jesd204_common/jesd204_frame_align_replace.v
index 9b2b9ec5ea..5961b6f6a7 100755
--- a/library/jesd204/jesd204_common/jesd204_frame_align_replace.v
+++ b/library/jesd204/jesd204_common/jesd204_frame_align_replace.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 // Limitations:
 //   DATA_PATH_WIDTH = 4, 8
diff --git a/library/jesd204/jesd204_common/jesd204_frame_mark.v b/library/jesd204/jesd204_common/jesd204_frame_mark.v
index 8bf5c8665c..62f76056ca 100755
--- a/library/jesd204/jesd204_common/jesd204_frame_mark.v
+++ b/library/jesd204/jesd204_common/jesd204_frame_mark.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 // Limitations:
 //  for DATA_PATH_WIDTH = 4, 8
diff --git a/library/jesd204/jesd204_common/jesd204_lmfc.v b/library/jesd204/jesd204_common/jesd204_lmfc.v
index 4a44ac82ef..1a6f295961 100755
--- a/library/jesd204/jesd204_common/jesd204_lmfc.v
+++ b/library/jesd204/jesd204_common/jesd204_lmfc.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_common/jesd204_scrambler.v b/library/jesd204/jesd204_common/jesd204_scrambler.v
index 798e6b4b48..7471dd56a0 100644
--- a/library/jesd204/jesd204_common/jesd204_scrambler.v
+++ b/library/jesd204/jesd204_common/jesd204_scrambler.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_common/jesd204_scrambler_64b.v b/library/jesd204/jesd204_common/jesd204_scrambler_64b.v
index 991515e12a..c5befa606d 100644
--- a/library/jesd204/jesd204_common/jesd204_scrambler_64b.v
+++ b/library/jesd204/jesd204_common/jesd204_scrambler_64b.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_common/pipeline_stage.v b/library/jesd204/jesd204_common/pipeline_stage.v
index 50dc92ec63..47b89e80c0 100644
--- a/library/jesd204/jesd204_common/pipeline_stage.v
+++ b/library/jesd204/jesd204_common/pipeline_stage.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_common/sync_header_align.v b/library/jesd204/jesd204_common/sync_header_align.v
index b15b1f7de9..34bc544df5 100644
--- a/library/jesd204/jesd204_common/sync_header_align.v
+++ b/library/jesd204/jesd204_common/sync_header_align.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2021-2023, Analog Devices, Inc.
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/align_mux.v b/library/jesd204/jesd204_rx/align_mux.v
index 0c7f0aa910..70d4a696a2 100755
--- a/library/jesd204/jesd204_rx/align_mux.v
+++ b/library/jesd204/jesd204_rx/align_mux.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/bd/bd.tcl b/library/jesd204/jesd204_rx/bd/bd.tcl
index 16eace9531..8a962e85b9 100644
--- a/library/jesd204/jesd204_rx/bd/bd.tcl
+++ b/library/jesd204/jesd204_rx/bd/bd.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 proc init {cellpath otherInfo} {
   set ip [get_bd_cells $cellpath]
diff --git a/library/jesd204/jesd204_rx/elastic_buffer.v b/library/jesd204/jesd204_rx/elastic_buffer.v
index c6b336d712..74dc8852fd 100644
--- a/library/jesd204/jesd204_rx/elastic_buffer.v
+++ b/library/jesd204/jesd204_rx/elastic_buffer.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/error_monitor.v b/library/jesd204/jesd204_rx/error_monitor.v
index 091542b81e..6d94fd2ad2 100644
--- a/library/jesd204/jesd204_rx/error_monitor.v
+++ b/library/jesd204/jesd204_rx/error_monitor.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_ilas_monitor.v b/library/jesd204/jesd204_rx/jesd204_ilas_monitor.v
index e11cc4c803..5331286de2 100755
--- a/library/jesd204/jesd204_rx/jesd204_ilas_monitor.v
+++ b/library/jesd204/jesd204_rx/jesd204_ilas_monitor.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v b/library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v
index 16c2f093de..481e2175b2 100755
--- a/library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v
+++ b/library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_rx.v b/library/jesd204/jesd204_rx/jesd204_rx.v
index 32057bbd1c..c70954b870 100755
--- a/library/jesd204/jesd204_rx/jesd204_rx.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_cgs.v b/library/jesd204/jesd204_rx/jesd204_rx_cgs.v
index b8fea3dd9b..9b1ad6fe10 100644
--- a/library/jesd204/jesd204_rx/jesd204_rx_cgs.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx_cgs.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_constr.sdc b/library/jesd204/jesd204_rx/jesd204_rx_constr.sdc
index 0f9c4f67b3..d2594922dd 100644
--- a/library/jesd204/jesd204_rx/jesd204_rx_constr.sdc
+++ b/library/jesd204/jesd204_rx/jesd204_rx_constr.sdc
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 #
 
 set script_dir [file dirname [info script]]
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl b/library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl
index 9ca5bbd048..f8061e72e1 100644
--- a/library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl
+++ b/library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 <: set ComponentName [getComponentNameString] :>
 <: setOutputDirectory "./" :>
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_ctrl.v b/library/jesd204/jesd204_rx/jesd204_rx_ctrl.v
index 2b4710ec78..c30eef1059 100755
--- a/library/jesd204/jesd204_rx/jesd204_rx_ctrl.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx_ctrl.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_ctrl_64b.v b/library/jesd204/jesd204_rx/jesd204_rx_ctrl_64b.v
index 0e828c745e..ff97de2c74 100644
--- a/library/jesd204/jesd204_rx/jesd204_rx_ctrl_64b.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx_ctrl_64b.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2020-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_frame_align.v b/library/jesd204/jesd204_rx/jesd204_rx_frame_align.v
index 13f05612fd..c1608780d8 100755
--- a/library/jesd204/jesd204_rx/jesd204_rx_frame_align.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx_frame_align.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_header.v b/library/jesd204/jesd204_rx/jesd204_rx_header.v
index d1677df44d..e7b103b115 100644
--- a/library/jesd204/jesd204_rx/jesd204_rx_header.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx_header.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_hw.tcl b/library/jesd204/jesd204_rx/jesd204_rx_hw.tcl
index c8f6e829ab..74fbb4afa7 100755
--- a/library/jesd204/jesd204_rx/jesd204_rx_hw.tcl
+++ b/library/jesd204/jesd204_rx/jesd204_rx_hw.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 package require qsys 14.0
 
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_ip.tcl b/library/jesd204/jesd204_rx/jesd204_rx_ip.tcl
index 96072c6098..ae9cf820f9 100755
--- a/library/jesd204/jesd204_rx/jesd204_rx_ip.tcl
+++ b/library/jesd204/jesd204_rx/jesd204_rx_ip.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_lane.v b/library/jesd204/jesd204_rx/jesd204_rx_lane.v
index 8b153a7666..403676c15f 100755
--- a/library/jesd204/jesd204_rx/jesd204_rx_lane.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx_lane.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_lane_64b.v b/library/jesd204/jesd204_rx/jesd204_rx_lane_64b.v
index 3ff21c626d..ca6d088a93 100644
--- a/library/jesd204/jesd204_rx/jesd204_rx_lane_64b.v
+++ b/library/jesd204/jesd204_rx/jesd204_rx_lane_64b.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2020-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx/jesd204_rx_ooc.ttcl b/library/jesd204/jesd204_rx/jesd204_rx_ooc.ttcl
index 53b59522bc..4f70ed96a4 100644
--- a/library/jesd204/jesd204_rx/jesd204_rx_ooc.ttcl
+++ b/library/jesd204/jesd204_rx/jesd204_rx_ooc.ttcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2021-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 <: setFileUsedIn { out_of_context synthesis implementation } :>
 <: ;#Component and file information :>
diff --git a/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.v b/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.v
index 62bd45c580..05e07ade24 100755
--- a/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.v
+++ b/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config_ip.tcl b/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config_ip.tcl
index b40a620070..097c27cae6 100755
--- a/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config_ip.tcl
+++ b/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config_ip.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v b/library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v
index b8fe842ca5..f07d5f70c3 100644
--- a/library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v
+++ b/library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v b/library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v
index aae6e2b6d1..dc1ae69380 100644
--- a/library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v
+++ b/library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v b/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v
index 121cee060e..e53035b1b9 100644
--- a/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v
+++ b/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl b/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl
index 805e3c35fe..65468e5edd 100644
--- a/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl
+++ b/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 package require qsys 14.0
 
diff --git a/library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v b/library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v
index 572f30f285..f48375889f 100644
--- a/library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v
+++ b/library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v b/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v
index 6652bf85e9..a54aa3200f 100644
--- a/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v
+++ b/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl b/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl
index 6a22d4fc19..e9b9a5f417 100644
--- a/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl
+++ b/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 package require qsys 14.0
 
diff --git a/library/jesd204/jesd204_tx/bd/bd.tcl b/library/jesd204/jesd204_tx/bd/bd.tcl
index 16eace9531..8a962e85b9 100644
--- a/library/jesd204/jesd204_tx/bd/bd.tcl
+++ b/library/jesd204/jesd204_tx/bd/bd.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 proc init {cellpath otherInfo} {
   set ip [get_bd_cells $cellpath]
diff --git a/library/jesd204/jesd204_tx/jesd204_tx.v b/library/jesd204/jesd204_tx/jesd204_tx.v
index 3de0cc9baa..fbe6c28435 100755
--- a/library/jesd204/jesd204_tx/jesd204_tx.v
+++ b/library/jesd204/jesd204_tx/jesd204_tx.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_constr.sdc b/library/jesd204/jesd204_tx/jesd204_tx_constr.sdc
index 14cec65a21..17280a00cd 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx_constr.sdc
+++ b/library/jesd204/jesd204_tx/jesd204_tx_constr.sdc
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 set script_dir [file dirname [info script]]
 
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_constr.ttcl b/library/jesd204/jesd204_tx/jesd204_tx_constr.ttcl
index 60d8deb3ed..1ea7605223 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx_constr.ttcl
+++ b/library/jesd204/jesd204_tx/jesd204_tx_constr.ttcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 <: set ComponentName [getComponentNameString] :>
 <: setOutputDirectory "./" :>
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_ctrl.v b/library/jesd204/jesd204_tx/jesd204_tx_ctrl.v
index 59981a0c40..c6fd78f174 100755
--- a/library/jesd204/jesd204_tx/jesd204_tx_ctrl.v
+++ b/library/jesd204/jesd204_tx/jesd204_tx_ctrl.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_gearbox.v b/library/jesd204/jesd204_tx/jesd204_tx_gearbox.v
index 733b74d2de..5701aacb5a 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx_gearbox.v
+++ b/library/jesd204/jesd204_tx/jesd204_tx_gearbox.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2021-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_header.v b/library/jesd204/jesd204_tx/jesd204_tx_header.v
index f5f215dd93..868a082b14 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx_header.v
+++ b/library/jesd204/jesd204_tx/jesd204_tx_header.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_hw.tcl b/library/jesd204/jesd204_tx/jesd204_tx_hw.tcl
index e7d06e46aa..f6b97b2773 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx_hw.tcl
+++ b/library/jesd204/jesd204_tx/jesd204_tx_hw.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 package require qsys 14.0
 
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_ip.tcl b/library/jesd204/jesd204_tx/jesd204_tx_ip.tcl
index 045ab5fba7..fc73468f59 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx_ip.tcl
+++ b/library/jesd204/jesd204_tx/jesd204_tx_ip.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_lane.v b/library/jesd204/jesd204_tx/jesd204_tx_lane.v
index 2ea10179dc..2787fbb795 100755
--- a/library/jesd204/jesd204_tx/jesd204_tx_lane.v
+++ b/library/jesd204/jesd204_tx/jesd204_tx_lane.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_lane_64b.v b/library/jesd204/jesd204_tx/jesd204_tx_lane_64b.v
index 5c68465f14..13de3a49bc 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx_lane_64b.v
+++ b/library/jesd204/jesd204_tx/jesd204_tx_lane_64b.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2020-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_tx/jesd204_tx_ooc.ttcl b/library/jesd204/jesd204_tx/jesd204_tx_ooc.ttcl
index b2b50c1e5a..7fd0649b58 100644
--- a/library/jesd204/jesd204_tx/jesd204_tx_ooc.ttcl
+++ b/library/jesd204/jesd204_tx/jesd204_tx_ooc.ttcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2021-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 <: setFileUsedIn { out_of_context synthesis implementation } :>
 <: ;#Component and file information :>
diff --git a/library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v b/library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v
index e0c8c34ff2..ccbed4cf21 100755
--- a/library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v
+++ b/library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v b/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v
index cb87ceb95a..45d177eebc 100755
--- a/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v
+++ b/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config_ip.tcl b/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config_ip.tcl
index 0e19c8d981..d9072c9c2b 100644
--- a/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config_ip.tcl
+++ b/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config_ip.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v
index 776cb05ea4..28bdfef9d0 100644
--- a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v
+++ b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2021-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl
index 0b42c05364..8c91ac8be4 100644
--- a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl
+++ b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v
index 12000a38de..3a3a14c350 100644
--- a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v
+++ b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2021-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl
index ec482599ad..d88b804ad7 100644
--- a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl
+++ b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
diff --git a/library/jesd204/scripts/jesd204.tcl b/library/jesd204/scripts/jesd204.tcl
index ca9a679250..704d5e5453 100644
--- a/library/jesd204/scripts/jesd204.tcl
+++ b/library/jesd204/scripts/jesd204.tcl
@@ -41,7 +41,7 @@
 # to do so; it is up to your common sense to decide whether you want to comply
 # with this request or not.) For general publications, we suggest referencing :
 # “The design and implementation of the JESD204 HDL Core used in this project
-# is copyright © 2016-2023, Analog Devices, Inc.”
+# is copyright © 2016-2017, Analog Devices, Inc.”
 
 proc adi_axi_jesd204_tx_create {ip_name num_lanes {num_links 1} {link_mode 1}} {
 
diff --git a/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v b/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v
index f5f1881ca6..3f00b924d1 100644
--- a/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v
+++ b/library/jesd204/tb/axi_jesd204_rx_regmap_tb.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/axi_jesd204_tx_regmap_tb.v b/library/jesd204/tb/axi_jesd204_tx_regmap_tb.v
index 3b8f9e637c..dff7f89be7 100644
--- a/library/jesd204/tb/axi_jesd204_tx_regmap_tb.v
+++ b/library/jesd204/tb/axi_jesd204_tx_regmap_tb.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/crc12_tb.v b/library/jesd204/tb/crc12_tb.v
index 84234fc1e7..c6784ceccd 100644
--- a/library/jesd204/tb/crc12_tb.v
+++ b/library/jesd204/tb/crc12_tb.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2020-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/frame_align_tb.v b/library/jesd204/tb/frame_align_tb.v
index 73e8ddfb39..2ab47cb7cb 100755
--- a/library/jesd204/tb/frame_align_tb.v
+++ b/library/jesd204/tb/frame_align_tb.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // The design and implementation of the JESD204 HDL Core used in this project
-// is copyright � 2020-2023, Analog Devices, Inc.
+// is copyright � 2016-2017, Analog Devices, Inc.�
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/jesd204_frame_align_replace_tb.v b/library/jesd204/tb/jesd204_frame_align_replace_tb.v
index 9f76f68c93..1a8fd39b99 100755
--- a/library/jesd204/tb/jesd204_frame_align_replace_tb.v
+++ b/library/jesd204/tb/jesd204_frame_align_replace_tb.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2021-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/jesd204_frame_mark_tb.v b/library/jesd204/tb/jesd204_frame_mark_tb.v
index 90a0c9ac6b..4aaaf70e07 100755
--- a/library/jesd204/tb/jesd204_frame_mark_tb.v
+++ b/library/jesd204/tb/jesd204_frame_mark_tb.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2021-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/loopback_64b_tb.v b/library/jesd204/tb/loopback_64b_tb.v
index 721d56b2bc..c354b23081 100644
--- a/library/jesd204/tb/loopback_64b_tb.v
+++ b/library/jesd204/tb/loopback_64b_tb.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2020-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/loopback_tb.v b/library/jesd204/tb/loopback_tb.v
index 9cf5e588b0..6460896a0f 100755
--- a/library/jesd204/tb/loopback_tb.v
+++ b/library/jesd204/tb/loopback_tb.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/rx_cgs_tb.v b/library/jesd204/tb/rx_cgs_tb.v
index feb40368dc..44c2c783a3 100644
--- a/library/jesd204/tb/rx_cgs_tb.v
+++ b/library/jesd204/tb/rx_cgs_tb.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/rx_ctrl_tb.v b/library/jesd204/tb/rx_ctrl_tb.v
index 32bc95b5d8..324cd35358 100644
--- a/library/jesd204/tb/rx_ctrl_tb.v
+++ b/library/jesd204/tb/rx_ctrl_tb.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/rx_lane_tb.v b/library/jesd204/tb/rx_lane_tb.v
index a81920bfb3..ddeaa44944 100644
--- a/library/jesd204/tb/rx_lane_tb.v
+++ b/library/jesd204/tb/rx_lane_tb.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/rx_tb.v b/library/jesd204/tb/rx_tb.v
index e43bef085a..232a692056 100644
--- a/library/jesd204/tb/rx_tb.v
+++ b/library/jesd204/tb/rx_tb.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/scrambler_64b_tb.v b/library/jesd204/tb/scrambler_64b_tb.v
index c401a50459..c7c9745fb4 100644
--- a/library/jesd204/tb/scrambler_64b_tb.v
+++ b/library/jesd204/tb/scrambler_64b_tb.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2020-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/scrambler_tb.v b/library/jesd204/tb/scrambler_tb.v
index eba7cab6b9..0bc96e17dc 100644
--- a/library/jesd204/tb/scrambler_tb.v
+++ b/library/jesd204/tb/scrambler_tb.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v b/library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v
index e4b4d21dc5..1793fc9192 100644
--- a/library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v
+++ b/library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/soft_pcs_8b10b_table_tb.v b/library/jesd204/tb/soft_pcs_8b10b_table_tb.v
index 37cd66d182..12944f9045 100644
--- a/library/jesd204/tb/soft_pcs_8b10b_table_tb.v
+++ b/library/jesd204/tb/soft_pcs_8b10b_table_tb.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/soft_pcs_loopback_tb.v b/library/jesd204/tb/soft_pcs_loopback_tb.v
index 193d1848c2..5f924f0456 100644
--- a/library/jesd204/tb/soft_pcs_loopback_tb.v
+++ b/library/jesd204/tb/soft_pcs_loopback_tb.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/soft_pcs_pattern_align_tb.v b/library/jesd204/tb/soft_pcs_pattern_align_tb.v
index 361aec8580..d79e17bdf1 100644
--- a/library/jesd204/tb/soft_pcs_pattern_align_tb.v
+++ b/library/jesd204/tb/soft_pcs_pattern_align_tb.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/tb_base.v b/library/jesd204/tb/tb_base.v
index 921e016211..18db5e67a0 100755
--- a/library/jesd204/tb/tb_base.v
+++ b/library/jesd204/tb/tb_base.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
   reg clk = 1'b0;
   reg [3:0] reset_shift = 4'b1111;
diff --git a/library/jesd204/tb/tx_64b_tb.v b/library/jesd204/tb/tx_64b_tb.v
index 6272043a7b..4232251585 100644
--- a/library/jesd204/tb/tx_64b_tb.v
+++ b/library/jesd204/tb/tx_64b_tb.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps
 
diff --git a/library/jesd204/tb/tx_ctrl_phase_tb.v b/library/jesd204/tb/tx_ctrl_phase_tb.v
index d42e02ca89..b940da08b1 100644
--- a/library/jesd204/tb/tx_ctrl_phase_tb.v
+++ b/library/jesd204/tb/tx_ctrl_phase_tb.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 /*
  * Regardless of the phase relationship between LMFC and sync the output of the
diff --git a/library/jesd204/tb/tx_tb.v b/library/jesd204/tb/tx_tb.v
index 0a54fbeeb1..b7cad56363 100644
--- a/library/jesd204/tb/tx_tb.v
+++ b/library/jesd204/tb/tx_tb.v
@@ -42,7 +42,7 @@
 // to do so; it is up to your common sense to decide whether you want to comply
 // with this request or not.) For general publications, we suggest referencing :
 // “The design and implementation of the JESD204 HDL Core used in this project
-// is copyright © 2016-2023, Analog Devices, Inc.”
+// is copyright © 2016-2017, Analog Devices, Inc.”
 
 `timescale 1ns/100ps