diff --git a/docs/library/axi_adc_trigger/block_diagram.svg b/docs/library/axi_adc_trigger/block_diagram.svg new file mode 100644 index 0000000000..f792f38eb2 --- /dev/null +++ b/docs/library/axi_adc_trigger/block_diagram.svg @@ -0,0 +1,4333 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + +   +   +       +   +   + + + REGMAP + + + + AXI ADC TRIGGER + ADC ch A [15:0] +   + + + + + + + + + + + + + ADC ch B [15:0] + + + + + + + + +   +   + + Externaltrigger control + trigger_i[1:0] + trigger_o[1:0] + trigger_t[1:0] + I[1] + I[0] +   +   + +   + + + + + + Ch AMUX + + OutMUX + + + trigger_out +   +    + trigger_in(LA) + up_triggerd_o[1:0] + + +  32 bitdelaycounter + + + ADC data +embeddedtriger(bit 15) +   +   ADC ch A + ADC ch B + + + + Ch BMUX + ChannelTrigger + + + CH A + + + CH B + Pin 0(Ti)triggerdetect + Pin 1(To)triggerdetect + + trigger_out_la + + + + + + 2 FFsync + + + +   32 bitholdoffcounter + + + State hold + + + diff --git a/docs/library/axi_adc_trigger/index.rst b/docs/library/axi_adc_trigger/index.rst new file mode 100644 index 0000000000..bcbb67a131 --- /dev/null +++ b/docs/library/axi_adc_trigger/index.rst @@ -0,0 +1,205 @@ +.. _axi_adc_trigger: + +AXI ADC Trigger +================================================================================ + +.. hdl-component-diagram:: + +The :git-hdl:`AXI ADC Trigger ` IP core implements +triggering for the ADC path and also controls two I/O triggering pins. + +More about the generic framework interfacing ADCs can be read here at :ref:`axi_adc`. + +Features +-------------------------------------------------------------------------------- + +- AXI Lite control/status interface +- Analog triggers, two channels + + - Greater than a limit + - Lower than a limit + - Passing through the limit, high + - Passing through the limit, low + +- Digital triggers, two trigger pins + + - Low + - High + - Any edge + - Rising edge + - Falling edge + +- Mixing analog and digital triggers +- Instrument trigger (from Logic Analyzer) +- Controls two IO trigger pins + +Files +-------------------------------------------------------------------------------- + +.. list-table:: + :header-rows: 1 + + * - Name + - Description + * - :git-hdl:`library/axi_adc_trigger/axi_adc_trigger.v` + - Verilog source for the peripheral. + +Block Diagram +-------------------------------------------------------------------------------- + +.. image:: block_diagram.svg + :alt: AXI ADC Trigger block diagram + :align: center + +Submodules +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- **Channel trigger** + + - Channel A + + - Amplitude limit - LIMIT_A (0x0014) - Defines the threshold level for + the ADC trigger + - Function - TRIGGER_FUNCTION_A (0x0018) - Lower, higher than limit; + pass-through limit + - Hysteresis - TRIGGER_FUNCTION_A (0x001c) - "+-" value. Used for the + pass-through functions + + - Channel B + + - Amplitude limit - LIMIT_A (0x0024) - Defines the threshold level for + the ADC trigger + - Function - TRIGGER_FUNCTION_A (0x0028) - Lower, higher than limit; + pass-through limit + - Hysteresis - TRIGGER_FUNCTION_A (0x002c) - "+-" value. Used for the + pass-through functions + +- **External trigger** + + - Pin 0 (Ti) + Configurations - CONFIG_TRIGGER_I (0x004) allows for: + + - falling edge (bit 8) + - rising edge (bit 6) + - any edge (bit 4) + - high level (bit 2) + - low level (bit 0) + + - Pin 1 (To) + Configurations - CONFIG_TRIGGER_I (0x004) allows for: + + - falling edge (bit 9) + - rising edge (bit 7) + - any edge (bit 5) + - high level (bit 3) + - low level (bit 1) + +.. important:: + + In the case of :adi:`M2K `, the trigger pins (Ti and To) are + chosen one for input and one for output. This is for the ease of + configuring a daisy-chain of :adi:`M2Ks `. + Both pins can be configured as input or output using the IO_SELECTION + register (0x000c). + +- **Channel A MUX** - TRIGGER_MUX_A(0x0020) - Selects between a combination + of ADC trigger and the external trigger +- **Channel B MUX** - TRIGGER_MUX_B(0x0030) - Selects between a combination + of ADC trigger and the external trigger + +- **Output MUX** - TRIGGER_OUT_CONTROL(0x0034) - Selects a combination + between the channel A and/or B MUX's and the input of the instrument trigger +- **Holdoff counter** (32 bit) - TRIGGER_HOLDOFF(0x0048) - Controls the + trigger out silent period after an event. +- **Delay counter** (32 bit) - TRIGGER_DELAY(0x0040) - Controls the trigger + delay + +- **External trigger control** + + * IO_SELECTION(0x000c) - Controls the direction of the external trigger pins, + and the source (for each pin configured as output) + * TRIGGER_OUT_HOLD_PINS(0x004c) - Controls the hold period after a + transition to a new logic level. + +Configuration Parameters +-------------------------------------------------------------------------------- + +.. hdl-parameters:: + +Interface +-------------------------------------------------------------------------------- + +.. hdl-interfaces:: + + * - clk + - Clock input + * - trigger_in + - Instrument trigger input + * - trigger_i + - External trigger input + * - trigger_o + - Trigger output + * - trigger_t + - Trigger T signal, controlling if pin is input or output + * - data_a + - Analog data for channel A + * - data_b + - Analog data for channel B + * - data_valid_a + - Data valid signal for channel A + * - data_valid_b + - Data valid signal for channel B + * - data_a_trig + - Data with trigger embedded as most significant bit, channel A + * - data_b_trig + - Data with trigger embedded as most significant bit, channel B + * - data_valid_a_trig + - Data valid for channel A + * - data_valid_b_trig + - Data valid for channel B + * - trigger_out + - Trigger out of the adc_trigger delayed by 4 clock cycles plus the + trigger delay mechanism used with the variable FIFO for history (data + before trigger) + * - trigger_out_la + - Trigger out of the adc_trigger delayed by 2 clock cycles, minimum + delay possible for instrument trigger + * - fifo_depth + - Controls the dynamic depth of the history FIFO + * - s_axi + - Standard AXI Slave Memory Map interface + +Detailed Description +-------------------------------------------------------------------------------- + +The AXI ADC Trigger core implements triggering for the ADC path. The trigger is +generated based on two external trigger pins, a triggering signal from the logic +analyzer and the ADC channels. + +The external trigger pins are controlled by the core and can be both input or +output. For external triggering, they must be set to inputs (independently). + +The analog triggering is based on comparison with a limit. The data format must +be in 2's complement and the maximum number of bits of the analog channel is 15. +The trigger can be transmitted independent or embedded in the output word, at +bit 15. When embedded, the triggers must be extracted and data must be +reconstructed, before forwarding the data to the DMA. +The :ref:`util_extract` IP core can be used for this purpose. Embedding the +trigger in the data allows for additional IPs with unknown pipeline length +to be introduced in the path. + +If a history for data before the trigger is needed, a :ref:`util_var_fifo` +should be used. +The FIFO depth is controlled using the trigger_offset bus of this IP. + +Register Map +-------------------------------------------------------------------------------- + +.. hdl-regmap:: + :name: AXI_ADC_TRIGGER + +References +-------------------------------------------------------------------------------- + +* :git-hdl:`library/axi_adc_trigger` +* :git-linux:`/` diff --git a/docs/regmap/adi_regmap_axi_adc_trigger.txt b/docs/regmap/adi_regmap_axi_adc_trigger.txt new file mode 100644 index 0000000000..64ca8fb0ac --- /dev/null +++ b/docs/regmap/adi_regmap_axi_adc_trigger.txt @@ -0,0 +1,455 @@ +TITLE +AXI ADC Trigger (axi_adc_trigger) +AXI_ADC_TRIGGER +ENDTITLE + +############################################################################################ +############################################################################################ + +REG +0x0000 +VERSION +Version Register +ENDREG + +FIELD +[31:0] 0x00030000 +VERSION +RO +Version number +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0001 +SCRATCH +Scratch Register +ENDREG + +FIELD +[31:0] 0x00000000 +SCRATCH +RW +Scratch register +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0002 +TRIGGER_O +Control TRIGGER_O Value +ENDREG + +FIELD +[1] 0x00000000 +TRIGGER_O_1 +RW +Set TRIGGER_O_1 value +ENDFIELD + +FIELD +[0] 0x00000000 +TRIGGER_O_0 +RW +Set TRIGGER_O_0 value +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0003 +IO_SELECTION +Control Trigger Pins Direction +ENDREG + +FIELD +[7:5] 0x00000000 +TRIGGER_O_1 +RW +Select output trigger pin 1 (To PIN): + +0: SOFTWARE TRIGGER - TRRIGER_O_1(0x0004) +1: TRIGGER_I_1 (PIN) +2: TRIGGER_I_0 (PIN) +3: TRIGGER_OUT (axi_adc_trigger) 4: TRIGGER_IN (Logic analyzer) +ENDFIELD + +FIELD +[4:2] 0x00000000 +TRIGGER_O_0 +RW +Select output trigger pin 0 (Ti PIN): + +0: SOFTWARE TRIGGER - TRRIGER_O_0(0x0004) +1: TRIGGER_I_0 (PIN) +2: TRIGGER_I_1 (PIN) +3: TRIGGER_OUT (axi_adc_trigger) 4: TRIGGER_IN (Logic analyzer) +ENDFIELD + +FIELD +[1] 0x00000000 +IO_SELECTION_1 +RW +Drives the TRIGGER_T[1](To) pin. +ENDFIELD + +FIELD +[0] 0x00000000 +IO_SELECTION_0 +RW +Drives the TRIGGER_T[0](Ti) pin. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0004 +CONFIG_TRIGGER_I +Configure Digital Triggering +ENDREG + +FIELD +[9:8] 0x00000000 +FALL_EDGE +RW +Enable falling edge triggering for TRIGGER[0] or TRIGGER[1] pin. +ENDFIELD + +FIELD +[7:6] 0x00000000 +RISE_EDGE +RW +Enable rising edge triggering for TRIGGER[0] or TRIGGER[1] pin. +ENDFIELD + +FIELD +[5:4] 0x00000000 +ANY_EDGE +RW +Enable any edge triggering for TRIGGER[0] or TRIGGER[1] pin. +ENDFIELD + +FIELD +[3:2] 0x00000000 +HIGH_LEVEL +RW +Enable high level triggering for TRIGGER[0] or TRIGGER[1] pin. +ENDFIELD + +FIELD +[1:0] 0x00000000 +LOW_LEVEL +RW +Enable low level triggering for TRIGGER[0] or TRIGGER[1] pin. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0005 +LIMIT_A +Analog Trigger Level for Channel +ENDREG + +FIELD +[15:0] 0x00000000 +LIMIT_A +RW +Analog trigger level for channel A. 2's complement. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0006 +FUNCTION_A +Analog Triggering Function +ENDREG + +FIELD +[1:0] 0x00000000 +TRIGGER_FUNCTION_A +RW +Analog triggering function for channel A: + +0: Lower than limit +1: higher than limit +2: pass through high limit +3: passthrough low limit +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0007 +HYSTERESIS_A +Analog Trigger Hysteresis for Channel +ENDREG + +FIELD +[31:0] 0x00000000 +HYSTERESIS_A +RW +Used for the passthrough functions. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0008 +TRIGGER_MUX_A +Trigger Selection for Path +ENDREG + +FIELD +[3:0] 0x00000000 +TRIGGER_MUX_A +RW +Selects trigger a mode: + +0: Always on +1: Digital triggering, based on trigger[0] +2: ADC triggering, based on channel A +3: Reserved +4: Digital triggering OR ADC triggering +5: Digital triggering AND ADC triggering +6: Digital triggering XOR ADC triggering +7: Option 4 negated +8: Option 5 negated +9: Option 6 negated +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0009 +LIMIT_B +Analog Trigger Level for Channel +ENDREG + +FIELD +[15:0] 0x00000000 +LIMIT_B +RW +Analog trigger level for channel B. 2's complement. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x000A +FUNCTION_B +Analog Triggering Function +ENDREG + +FIELD +[1:0] 0x00000000 +TRIGGER_FUNCTION_B +RW +Analog triggering function for channel B: + +0: Lower than limit +1: higher than limit +2: pass through high limit +3: passthrough low limit +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x000B +HYSTERESIS_B +Analog Trigger Hysteresis for Channel +ENDREG + +FIELD +[31:0] 0x00000000 +HYSTERESIS_B +RW +Used for the passthrough functions. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x000C +TRIGGER_MUX_B +Trigger Selection for Path +ENDREG + +FIELD +[3:0] 0x00000000 +TRIGGER_MUX_B +RW +Selects trigger a mode: + +0: Always on +1: Digital triggering, based on trigger[0] +2: ADC triggering, based on channel B +3: Reserved +4: Digital triggering OR ADC triggering +5: Digital triggering AND ADC triggering +6: Digital triggering XOR ADC triggering +7: Option 4 negated +8: Option 5 negated +9: Option 6 negated +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x000D +TRIGGER_OUT_CONTROL +Selection Multiplexer and embedded trigger selection +ENDREG + +FIELD +[16] 0x00000000 +EMBEDDED_TRIGGER +RW +When set the bit 15 of the out channel data will be the trigger. +This allows to keep the data in sync with the trigger in future data processing, +before feeding the data to the DMA. +When set a util_extract module is required in the system. +ENDFIELD + +FIELD +[3:0] 0x00000000 +TRIGGER_MUX_OUT +RW +Final Trigger Selection Multiplexer. +Selects trigger a mode: + +0: Trigger A +1: Trigger B +2: Trigger A OR Trigger B +3: Trigger A AND Trigger B +4: Trigger A XOR Trigger B +5: Trigger LA +6: Trigger A OR Trigger LA +7: Trigger B OR Trigger LA +8: Trigger A OR Trigger B OR Trigger LA +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x000E +FIFO_DEPTH +Controls the Dynamic Depth of the History FIFO +ENDREG + +FIELD +[31:0] 0x00000000 +FIFO_DEPTH +RW +Controls the depth of the history FIFO. Should be less than the maximum FIFO depth. +If set to 0, the FIFO is bypassed. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x000F +TRIGGERED +Indicates Triggering Status +ENDREG + +FIELD +[1] 0x00000000 +TRIGGERED +RW1C +Indicates if the trigger has been triggered since the last time this register has been +reset. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0010 +TRIGGER_DELAY +Control the Trigger Delay +ENDREG + +FIELD +[31:0] 0x00000000 +TRIGGER_DELAY +RW +Delays the start of data capture with TRIGGER_DELAY number of samples after the trigger. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0011 +STREAMING +Controls Streaming Mode +ENDREG + +FIELD +[0] 0x00000000 +STREAMING +RW +If the streaming bit is set, after the trigger condition is met data will be continuously +captured by the DMA. The streaming bit must be set to 0 to reset triggering. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0012 +TRIGGER_HOLDOFF +Controls hold off time +ENDREG + +FIELD +[31:0] 0x00000000 +TRIGGER_HOLDOFF +RW +Defines the time interval, after a trigger event, where the next trigger events will be +ignored, until the end of the interval. The time interval is set by counter. Down-counting +on the ADC clock(100MHz). The value written in the register is loaded in the counter at a +trigger event. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0013 +TRIGGER_OUT_HOLD_PINS +Controls external trigger hold time +ENDREG + +FIELD +[1] 0x00000000 +TRIGGER_OUT_HOLD_PINS +RW +Defines a time period, in which the external trigger pins, configured as outputs, will hold +the new logic level after a transition. The down-counter, counting on ADC clock, is loaded +with the value written in the register after a new transition of the source trigger signal, +if the counter is inactive. +ENDFIELD + +############################################################################################ +############################################################################################