From 24135b7d47fc9c1dfa22bdbd56b6d80fc1d5f58a Mon Sep 17 00:00:00 2001 From: Jorge Marques Date: Tue, 7 May 2024 10:33:19 -0300 Subject: [PATCH] docs: Add axi_dac_interpolate IP core and regmap Signed-off-by: Jorge Marques --- .../axi_dac_interpolate/block_diagram.svg | 1362 +++++++++++++++++ docs/library/axi_dac_interpolate/index.rst | 150 ++ .../axi_dac_interpolate/transfer_sm.svg | 4 + docs/regmap/adi_regmap_interpolate.txt | 279 ++++ 4 files changed, 1795 insertions(+) create mode 100644 docs/library/axi_dac_interpolate/block_diagram.svg create mode 100644 docs/library/axi_dac_interpolate/index.rst create mode 100644 docs/library/axi_dac_interpolate/transfer_sm.svg create mode 100644 docs/regmap/adi_regmap_interpolate.txt diff --git a/docs/library/axi_dac_interpolate/block_diagram.svg b/docs/library/axi_dac_interpolate/block_diagram.svg new file mode 100644 index 0000000000..4384f9d685 --- /dev/null +++ b/docs/library/axi_dac_interpolate/block_diagram.svg @@ -0,0 +1,1362 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + CHANNEL_A + + + + ProgrammableCIC + Interpolation by5/50/500/5000/50000 + + + + ProgrammableCIC + Interpolation by5/50/500/5000/50000 + + + + CompensationFIR + Interpolation by2 + + + + Arbitrary Interpolation + + + + + CompensationFIR + Interpolation by2 + + + + Arbitrary Interpolation + + + + + + CHANNEL_B + + + + + + CHANNEL_A + + + + + + CHANNEL_B + + + + + + ScaleCompensation + + + + + ScaleCompensation + + + + diff --git a/docs/library/axi_dac_interpolate/index.rst b/docs/library/axi_dac_interpolate/index.rst new file mode 100644 index 0000000000..0427c58902 --- /dev/null +++ b/docs/library/axi_dac_interpolate/index.rst @@ -0,0 +1,150 @@ +.. _axi_dac_interpolate: + +AXI DAC Interpolate +================================================================================ + +.. hdl-component-diagram:: + +The :git-hdl:`AXI DAC Interpolate ` IP core +allows interpolation of the input data by 10/100/1000/10000/100000, with filtering +and arbitrary zero-hold interpolation. + +More about the generic framework interfacing DACs can be read here at :ref:`axi_dac`. + +Features +-------------------------------------------------------------------------------- + +* AXI Lite control/status interface +* Allows interpolation by 10/100/1000/10000/100000 with filtering +* Allows arbitrary zero-hold interpolation +* Filtering is implemented by a 6-section CIC programmable rate filter and a + compensation FIR filter. + +Files +-------------------------------------------------------------------------------- + +.. list-table:: + :header-rows: 1 + + * - Name + - Description + * - :git-hdl:`library/axi_dac_interpolate/axi_dac_interpolate.v` + - Verilog source for the peripheral. + +Block Diagram +-------------------------------------------------------------------------------- + +.. image:: block_diagram.svg + :alt: AXI DAC Interpolate block diagram + :align: center + +Configuration Parameters +-------------------------------------------------------------------------------- + +.. hdl-parameters:: + + * - CORRECTION_DISABLE + - Disable scale correction of the CIC output. + +Interface +-------------------------------------------------------------------------------- + +.. hdl-interfaces:: + + * - dac_clk + - Clock input. + * - dac_rst + - Reset, synchronous on the dac_clk clock domain. + * - dac_data_a + - Analog data for channel A. + * - dac_data_b + - Analog data for channel B. + * - dac_valid_a + - Data valid signal for channel A. + * - dac_valid_b + - Data valid signal for channel B. + * - dac_int_data_a + - Decimated data for channel A. + * - dac_int_data_b + - Decimated data for channel B. + * - dac_valid_out_a + - Data valid for channel A. + * - dac_valid_out_b + - Data valid for channel B. + * - trigger_i + - External trigger pins. + * - trigger_adc + - ADC trigger. + * - trigger_la + - Logic analyzer trigger. + * - s_axi + - Standard AXI Slave Memory Map interface. + +Detailed Description +-------------------------------------------------------------------------------- + +For some applications, the maximum sampling rate of the DAC is too high and +leads to bad utilization of the memory or USB bandwidth. To avoid it, the +interpolation IP can be used. + +The interpolation block allows interpolation by 10, 100, 1000, 10000,100000 with +filtering. The filtering is implemented using an FIR compensation filter +(interpolation by 2) for the CIC and a 6-stage CIC interpolation filter allowing +interpolation by 5/50/500/5000/50000. + +At the end of the filter blocks, there is an arbitrary interpolation zero-order +hold block which holds the value for a configurable number of samples. + +The axi_dac_interpolate also controls the data flow, being the middle man +between :ref:`axi_ad9963`: as the main data flow controller (consumer) and the DMA, +a subordinate in the path. This control is done through registers: + +- 0x50 FLAGS - Control flags +- 0x60 TRIGGER_CONFIG - Trigger configuration +- 0x64 RAW_CHANNEL_DATA - Raw data to transmit + +The actual control consists in fetching data from the DMA: + +#. at a desired rate +#. at a new transfer, waiting until the other channel DMA has valid DATA or + waiting for an external trigger +#. pausing/stopping the transfer at user request through remap or external + trigger + +If the DMA is stopped through the axi_dac_interpolate (dma_transfer_suspend or +external trigger) and not by disabling the DMA from it's register map, the DAC +data path will keep a few residual samples in the DMA's pipes. These samples +will be the first samples to be transferred when a new buffer is pushed. +To avoid it, one can use the DMA flush feature which clears the DMA when +stopped by the consumer. + +By default, the flush flag is active. It should be disabled only if the user +wants a "pause" functionality. Meaning, the transfer is stopped on an event and +then on another event, the transfer will continue from the same point without +having to create a new buffer. The event can be setting/clearing the +dma_transfer_suspend or an external trigger. + +Another feature is the stop_sync. There is only one use case for it. Stopping the +other channel (configured at a different rate and/or in cyclic mode) when the +first channel (DMA) finishes the transfer of a non-cyclic buffer. + +The RAW transfer feature enables the user to transfer data (written into a +register inside the axi_dac_interpolate) without needing DMA (buffer) +config (delays). + +For more info, check the state machine below. + +.. image:: transfer_sm.svg + +Register Map +-------------------------------------------------------------------------------- + +.. hdl-regmap:: + :name: axi_dac_interpolate + +References +-------------------------------------------------------------------------------- + +* :git-hdl:`library/axi_dac_interpolate` +* :git-linux:`/` +* :xilinx:`7 Series libraries ` diff --git a/docs/library/axi_dac_interpolate/transfer_sm.svg b/docs/library/axi_dac_interpolate/transfer_sm.svg new file mode 100644 index 0000000000..2d64ef57b4 --- /dev/null +++ b/docs/library/axi_dac_interpolate/transfer_sm.svg @@ -0,0 +1,4 @@ + + + +
push buffer
push buffer
Yes
Yes
dma_start_sync
dma_start_sync
adjacent DMA
is ready
adjacent DMA...
Yes
Yes
No
No
Yes
Yes
No
No
dma_transfer_suspend
stop trigger
dma_transfer_suspend...
No
No
flush
flush
wait for last sample
wait for last sample
start transfer
start transfer
raw enable
raw enable
raw data
raw data
DMA data
DMA data
Yes
Yes
No
No
raw active
raw active
The DMA outputs the last sample
from a buffer or DMA is stopped by software
for a cyclic transfer 
The DMA outputs the last sample...
Yes
YesText is not SVG - cannot display \ No newline at end of file diff --git a/docs/regmap/adi_regmap_interpolate.txt b/docs/regmap/adi_regmap_interpolate.txt new file mode 100644 index 0000000000..53f2c4dc42 --- /dev/null +++ b/docs/regmap/adi_regmap_interpolate.txt @@ -0,0 +1,279 @@ +TITLE +Analog Interpolation (axi_dac_interpolate) +axi_dac_interpolate +ENDTITLE + +############################################################################################ +############################################################################################ + +REG +0x000 +VERSION +Version of the peripheral. Follows semantic versioning. Current version 2.3.0. +ENDREG + +FIELD +[31:16] 0x00000002 +VERSION_MAJOR +RO +ENDFIELD + +FIELD +[15:8] 0x00000003 +VERSION_MINOR +RO +ENDFIELD + +FIELD +[7:0] 0x00000000 +VERSION_PATCH +RO +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0001 +SCRATCH +Scratch Register +ENDREG + +FIELD +[31:0] +SCRATCH +RW +Scratch register useful for debug. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0010 +ARBITRARY_INTERPOLATION_RATIO_A +Control Arbitrary Interpolation Ratio for Channel A +ENDREG + +FIELD +[31:0] +FILTERED_INTERPOLATION +RW +Set the arbitrary zero-order hold interpolation ratio at the end of the interpolation chain +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0011 +INTERPOLATION_RATIO_A +Control Filtered Interpolation for Channel A +ENDREG + +FIELD +[2:0] +FILTERED_INTERPOLATION +RW +Enables the filtered interpolation: + 0: No filtered interpolation + 1: Interpolation by 10. Result should be corrected by a 1.531 factor + 2: Interpolation by 100. Result should be corrected by a 1.168 factor + 3: Interpolation by 1000. Result should be corrected by a 1.783 factor + 6: Interpolation by 10000. Result should be corrected by a 1.360 factor + 7: Interpolation by 100000. Result should be corrected by a 1.038 factor + default: No filtered interpolation +ENDFIELD + + +############################################################################################ +############################################################################################ + +REG +0x0012 +ARBITRARY_INTERPOLATION_RATIO_B +Control Arbitrary Interpolation Ratio for Channel B +ENDREG + +FIELD +[31:0] +FILTERED_INTERPOLATION +RW +Set the arbitrary zero-order hold interpolation ratio at the end of the interpolation chain +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0013 +INTERPOLATION_RATIO_B +Control Filtered Interpolation for Channel B +ENDREG + +FIELD +[2:0] +FILTERED_INTERPOLATION +RW +Enables the filtered interpolation: + +0: No filtered interpolation +1: Interpolation by 10. Result should be corrected by a 1.531 factor +2: Interpolation by 100. Result should be corrected by a 1.168 factor +3: Interpolation by 1000. Result should be corrected by a 1.783 factor +6: Interpolation by 10000. Result should be corrected by a 1.360 factor +7: Interpolation by 100000. Result should be corrected by a 1.038 factor +default: No filtered interpolation +ENDFIELD + + +############################################################################################ +############################################################################################ + +REG +0x0014 +FLAGS +Control Flags +ENDREG + +FIELD +[0] +SUSPEND_TRANSFER +RW +If set to 1, the interpolation filters are in reset and no data is requested from the DMA. +Can be used to synchronize data transfer from two different DMAs. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0015 +CONFIG +Configuration Register +ENDREG + +FIELD +[1] +CORRECTION_ENABLE_B +RW +If set to 1, correction is enabled on channel B. The input data will be multiplied with the +value from the CORRECTION_COEFFICIENT_B register. +ENDFIELD + +FIELD +[0] +CORRECTION_ENABLE_A +RW +If set to 1, correction is enabled on channel A. The input data will be multiplied with the +value from the CORRECTION_COEFFICIENT_A register. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0016 +CORRECTION_COEFFICIENT_A +Correction Coefficient A +ENDREG + +FIELD +[15:0] +CORRECTION_COEFFICIENT +RW +Scale correction (if equipped) coefficient for channel A. The format is 1.1.14 (sign, +integer and fractional bits). Allows for correction of the CIC filter amplification. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0017 +CORRECTION_COEFFICIENT_B +Correction Coefficient B +ENDREG + +FIELD +[15:0] +CORRECTION_COEFFICIENT +RW +Scale correction (if equipped) coefficient for channel B. The format is 1.1.14 (sign, +integer and fractional bits). Allows for correction of the CIC filter amplification. +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x0018 +TRIGGER_CONFIG +Trigger configuration +ENDREG + +FIELD +[19] +EN_TRIGGER_LA +RW +Enable trigger from Logic Analyzer +ENDFIELD + +FIELD +[18] +EN_TRIGGER_ADC +RW +Enable trigger from ADC +ENDFIELD + +FIELD +[17] +EN_TRIGGER_TO +RW +Enable trigger from To +ENDFIELD + +FIELD +[16] +EN_TRIGGER_TI +RW +Enable trigger from Ti +ENDFIELD + +FIELD +[9:8] +FALL_EDGE +RW +Falling edge triggering for TRIGGER[0](Ti) or TRIGGER[1](To) pin +ENDFIELD + +FIELD +[7:6] +RISE_EDGE +RW +Rising edge triggering for TRIGGER[0](Ti) or TRIGGER[1](To) pin +ENDFIELD + +FIELD +[5:4] +ANY_EDGE +RW +Any edge triggering for TRIGGER[0](Ti) or TRIGGER[1](To) pin +ENDFIELD + +FIELD +[3:2] +HIGH_LEVEL +RW +High level triggering for TRIGGER[0](Ti) or TRIGGER[1](To) pin +ENDFIELD + +FIELD +[1:0] +LOW_LEVEL +RW +Low level triggering for TRIGGER[0](Ti) or TRIGGER[1](To) pin +ENDFIELD + +############################################################################################ +############################################################################################