[RISCV] Implement intrinsics for XAndesVPackFPH (llvm#140007)

This patch implements clang intrinsic support for XAndesVPackFPH.

The document for the intrinsics can be found at:

https://github.com/andestech/andes-vector-intrinsic-doc/blob/ast-v5_4_0-release-v5/auto-generated/andes-v5/intrinsic_funcs.adoc#andes-vector-packed-fp16-extensionxandesvpackfph
and with policy variants

https://github.com/andestech/andes-vector-intrinsic-doc/blob/ast-v5_4_0-release-v5/auto-generated/andes-v5/policy_funcs/intrinsic_funcs.adoc#andes-vector-packed-fp16-extensionxandesvpackfph

Co-authored-by: Tony Chuan-Yue Yuan <yuan593@andestech.com>

Author: tclin914

clang/include/clang/Basic/CMakeLists.txt

@@ -201,3 +201,12 @@ clang_tablegen(riscv_sifive_vector_builtin_cg.inc -gen-riscv-sifive-vector-built
 clang_tablegen(riscv_sifive_vector_builtin_sema.inc -gen-riscv-sifive-vector-builtin-sema
   SOURCE riscv_sifive_vector.td
   TARGET ClangRISCVSiFiveVectorBuiltinSema)
+clang_tablegen(riscv_andes_vector_builtins.inc -gen-riscv-andes-vector-builtins
+  SOURCE riscv_andes_vector.td
+  TARGET ClangRISCVAndesVectorBuiltins)
+clang_tablegen(riscv_andes_vector_builtin_cg.inc -gen-riscv-andes-vector-builtin-codegen
+  SOURCE riscv_andes_vector.td
+  TARGET ClangRISCVAndesVectorBuiltinCG)
+clang_tablegen(riscv_andes_vector_builtin_sema.inc -gen-riscv-andes-vector-builtin-sema
+  SOURCE riscv_andes_vector.td
+  TARGET ClangRISCVAndesVectorBuiltinSema)

clang/include/clang/Basic/TargetBuiltins.h

@@ -197,6 +197,9 @@ namespace clang {
     FirstSiFiveBuiltin,
     LastRVVBuiltin = FirstSiFiveBuiltin - 1,
 #include "clang/Basic/riscv_sifive_vector_builtins.inc"
+    FirstAndesBuiltin,
+    LastSiFiveBuiltin = FirstAndesBuiltin - 1,
+#include "clang/Basic/riscv_andes_vector_builtins.inc"
 #undef GET_RISCVV_BUILTIN_ENUMERATORS
     FirstTSBuiltin,
   };

clang/include/clang/Basic/riscv_andes_vector.td

@@ -0,0 +1,83 @@
+//==--- riscv_andes_vector.td - RISC-V Andes Builtin function list --------===//
+//
+//  Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+//  See https://llvm.org/LICENSE.txt for license information.
+//  SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the builtins for RISC-V Andes Vector Extension. See:
+//
+//     https://github.com/andestech/andes-vector-intrinsic-doc
+//
+//===----------------------------------------------------------------------===//
+
+include "riscv_vector_common.td"
+
+//===----------------------------------------------------------------------===//
+// Instruction definitions
+//===----------------------------------------------------------------------===//
+
+// Andes Vector Packed FP16 Extension (XAndesVPackFPH)
+
+multiclass RVVFPMAD {
+  let Log2LMUL = [-2, -1, 0, 1, 2, 3],
+      OverloadedName = NAME in {
+    defm NAME : RVVOutOp1BuiltinSet<NAME, "x", [["vf", "v", "vvf"]]>;
+
+    let HasFRMRoundModeOp = true in
+      defm NAME : RVVOutOp1BuiltinSet<NAME, "x", [["vf", "v", "vvfu"]]>;
+  }
+}
+
+let RequiredFeatures = ["Xandesvpackfph"],
+    UnMaskedPolicyScheme = HasPassthruOperand in {
+let ManualCodegen = [{
+  {
+    // LLVM intrinsic
+    // Unmasked: (passthru, op0, op1, round_mode, vl)
+    // Masked:   (passthru, vector_in, vector_in/scalar_in, mask, frm, vl, policy)
+
+    SmallVector<llvm::Value*, 7> Operands;
+    bool HasMaskedOff = !(
+        (IsMasked && (PolicyAttrs & RVV_VTA) && (PolicyAttrs & RVV_VMA)) ||
+        (!IsMasked && PolicyAttrs & RVV_VTA));
+    bool HasRoundModeOp = IsMasked ?
+      (HasMaskedOff ? Ops.size() == 6 : Ops.size() == 5) :
+      (HasMaskedOff ? Ops.size() == 5 : Ops.size() == 4);
+
+    unsigned Offset = IsMasked ?
+        (HasMaskedOff ? 2 : 1) : (HasMaskedOff ? 1 : 0);
+
+    if (!HasMaskedOff)
+      Operands.push_back(llvm::PoisonValue::get(ResultType));
+    else
+      Operands.push_back(Ops[IsMasked ? 1 : 0]);
+
+    Operands.push_back(Ops[Offset]); // op0
+    Operands.push_back(Ops[Offset + 1]); // op1
+
+    if (IsMasked)
+      Operands.push_back(Ops[0]); // mask
+
+    if (HasRoundModeOp) {
+      Operands.push_back(Ops[Offset + 2]); // frm
+      Operands.push_back(Ops[Offset + 3]); // vl
+    } else {
+      Operands.push_back(ConstantInt::get(Ops[Offset + 2]->getType(), 7)); // frm
+      Operands.push_back(Ops[Offset + 2]); // vl
+    }
+
+    if (IsMasked)
+      Operands.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
+
+    IntrinsicTypes = {ResultType, Ops[Offset + 1]->getType(),
+                      Operands.back()->getType()};
+    llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
+    return Builder.CreateCall(F, Operands, "");
+  }
+}] in {
+    defm nds_vfpmadt : RVVFPMAD;
+    defm nds_vfpmadb : RVVFPMAD;
+  }
+}

clang/include/clang/Sema/RISCVIntrinsicManager.h

@@ -24,7 +24,7 @@ class Preprocessor;
 namespace sema {
 class RISCVIntrinsicManager {
 public:
-  enum class IntrinsicKind : uint8_t { RVV, SIFIVE_VECTOR };
+  enum class IntrinsicKind : uint8_t { RVV, SIFIVE_VECTOR, ANDES_VECTOR };
 
   virtual ~RISCVIntrinsicManager() = default;
 

clang/include/clang/Sema/SemaRISCV.h

@@ -51,6 +51,9 @@ class SemaRISCV : public SemaBase {
   /// Indicate RISC-V SiFive vector builtin functions enabled or not.
   bool DeclareSiFiveVectorBuiltins = false;
 
+  /// Indicate RISC-V Andes vector builtin functions enabled or not.
+  bool DeclareAndesVectorBuiltins = false;
+
   std::unique_ptr<sema::RISCVIntrinsicManager> IntrinsicManager;
 };
 

clang/include/clang/Support/RISCVVIntrinsicUtils.h

@@ -489,6 +489,7 @@ class RVVIntrinsic {
 enum RVVRequire {
   RVV_REQ_RV64,
   RVV_REQ_Zvfhmin,
+  RVV_REQ_Xandesvpackfph,
   RVV_REQ_Xsfvcp,
   RVV_REQ_Xsfvfnrclipxfqf,
   RVV_REQ_Xsfvfwmaccqqq,

clang/lib/Basic/Targets/RISCV.cpp

@@ -265,13 +265,15 @@ void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
 static constexpr int NumRVVBuiltins =
     RISCVVector::FirstSiFiveBuiltin - Builtin::FirstTSBuiltin;
 static constexpr int NumRVVSiFiveBuiltins =
-    RISCVVector::FirstTSBuiltin - RISCVVector::FirstSiFiveBuiltin;
+    RISCVVector::FirstAndesBuiltin - RISCVVector::FirstSiFiveBuiltin;
+static constexpr int NumRVVAndesBuiltins =
+    RISCVVector::FirstTSBuiltin - RISCVVector::FirstAndesBuiltin;
 static constexpr int NumRISCVBuiltins =
     RISCV::LastTSBuiltin - RISCVVector::FirstTSBuiltin;
 static constexpr int NumBuiltins =
     RISCV::LastTSBuiltin - Builtin::FirstTSBuiltin;
-static_assert(NumBuiltins ==
-              (NumRVVBuiltins + NumRVVSiFiveBuiltins + NumRISCVBuiltins));
+static_assert(NumBuiltins == (NumRVVBuiltins + NumRVVSiFiveBuiltins +
+                              NumRVVAndesBuiltins + NumRISCVBuiltins));
 
 namespace RVV {
 #define GET_RISCVV_BUILTIN_STR_TABLE
@@ -299,6 +301,19 @@ static constexpr std::array<Builtin::Info, NumRVVSiFiveBuiltins> BuiltinInfos =
 };
 } // namespace RVVSiFive
 
+namespace RVVAndes {
+#define GET_RISCVV_BUILTIN_STR_TABLE
+#include "clang/Basic/riscv_andes_vector_builtins.inc"
+#undef GET_RISCVV_BUILTIN_STR_TABLE
+
+static constexpr std::array<Builtin::Info, NumRVVAndesBuiltins> BuiltinInfos =
+    {
+#define GET_RISCVV_BUILTIN_INFOS
+#include "clang/Basic/riscv_andes_vector_builtins.inc"
+#undef GET_RISCVV_BUILTIN_INFOS
+};
+} // namespace RVVAndes
+
 #define GET_BUILTIN_STR_TABLE
 #include "clang/Basic/BuiltinsRISCV.inc"
 #undef GET_BUILTIN_STR_TABLE
@@ -315,6 +330,7 @@ RISCVTargetInfo::getTargetBuiltins() const {
   return {
       {&RVV::BuiltinStrings, RVV::BuiltinInfos, "__builtin_rvv_"},
       {&RVVSiFive::BuiltinStrings, RVVSiFive::BuiltinInfos, "__builtin_rvv_"},
+      {&RVVAndes::BuiltinStrings, RVVAndes::BuiltinInfos, "__builtin_rvv_"},
       {&BuiltinStrings, BuiltinInfos},
   };
 }

clang/lib/CodeGen/TargetBuiltins/RISCV.cpp

@@ -418,6 +418,9 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
 
     // SiFive Vector builtins are handled from here.
 #include "clang/Basic/riscv_sifive_vector_builtin_cg.inc"
+
+    // Andes Vector builtins are handled from here.
+#include "clang/Basic/riscv_andes_vector_builtin_cg.inc"
   }
 
   assert(ID != Intrinsic::not_intrinsic);

clang/lib/Headers/CMakeLists.txt

@@ -127,6 +127,7 @@ set(riscv_files
   riscv_crypto.h
   riscv_ntlh.h
   sifive_vector.h
+  andes_vector.h
   )
 
 set(systemz_files

clang/lib/Headers/andes_vector.h

@@ -0,0 +1,16 @@
+//===----- andes_vector.h - Andes Vector definitions ----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _ANDES_VECTOR_H_
+#define _ANDES_VECTOR_H_
+
+#include "riscv_vector.h"
+
+#pragma clang riscv intrinsic andes_vector
+
+#endif //_ANDES_VECTOR_H_