From 494e56bc8921534ad7949aab298aedeafd51090a Mon Sep 17 00:00:00 2001 From: Afonso Bordado Date: Fri, 16 Aug 2024 18:37:17 +0100 Subject: [PATCH] riscv64: Restrict bitcasts to 16bit floating point values from/to vectors --- cranelift/codegen/src/isa/riscv64/inst.isle | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/cranelift/codegen/src/isa/riscv64/inst.isle b/cranelift/codegen/src/isa/riscv64/inst.isle index ebe6f1834b4a..d345cd064915 100644 --- a/cranelift/codegen/src/isa/riscv64/inst.isle +++ b/cranelift/codegen/src/isa/riscv64/inst.isle @@ -2924,9 +2924,13 @@ ;; Generates a bitcast instruction. ;; Args are: src, src_ty, dst_ty (decl gen_bitcast (Reg Type Type) Reg) -(rule 5 (gen_bitcast r (ty_supported_float src_ty) (ty_supported_vec _)) (rv_vfmv_sf r src_ty)) -(rule 4 (gen_bitcast r (ty_int_ref_scalar_64 src_ty) (ty_supported_vec _)) (rv_vmv_sx r src_ty)) -(rule 3 (gen_bitcast r (ty_supported_vec _) (ty_supported_float dst_ty)) (rv_vfmv_fs r dst_ty)) + +;; To support FP16 vfmv.* we need to check for the `zvfh` isa flag, which we currently don't +;; support, so restrict the floating point types to 32/64 bits. +(rule 5 (gen_bitcast r (ty_supported_float (ty_32_or_64 src_ty)) (ty_supported_vec _)) (rv_vfmv_sf r src_ty)) +(rule 4 (gen_bitcast r (ty_supported_vec _) (ty_supported_float (ty_32_or_64 dst_ty))) (rv_vfmv_fs r dst_ty)) + +(rule 3 (gen_bitcast r (ty_int_ref_scalar_64 src_ty) (ty_supported_vec _)) (rv_vmv_sx r src_ty)) (rule 2 (gen_bitcast r (ty_supported_vec _) (ty_int_ref_scalar_64 dst_ty)) (rv_vmv_xs r dst_ty)) (rule 1 (gen_bitcast r $F16 $I16) (rv_fmvxh r)) (rule 1 (gen_bitcast r $F32 $I32) (rv_fmvxw r))