Support for UDP?

[maliberty]

In asap7 the cells description in Verilog come from Liberate which uses UDP like:

primitive altos_latch (q, v, clk, d);
	output q;
	reg q;
	input v, clk, d;

	table
		* ? ? : ? : x;
		? 1 0 : ? : 0;
		? 1 1 : ? : 1;
		? x 0 : 0 : -;
		? x 1 : 1 : -;
		? 0 ? : ? : -;
	endtable
endprimitive

but I get errors when reading as soon as it sees this:

platforms/asap7/work_around_yosys/asap7sc7p5t_SEQ_RVT_TT_220101.v:37: ERROR: syntax error, unexpected TOK_ID

Are UDP supported in eqy? This is a common characterization tool so I expect this will be a common issue.

[maliberty]

This arises when trying to use the suggested script in #57. Without UDP (which were commented out, presumably because they don't parse) I get lots of errors about undriven signals.

[jix]

The lack of UDP support in EQY is entirely due to the lack of UDP support in yosys and there are currently no plans to add UDP support to yosys.

[maliberty]

That's unfortunate. So I would have to manually write Verilog models for all the registers? Will always @(posedge clock) style work ok in eqy?

[jix]

Everything that our FV flows support is supported in EQY, which includes almost all of what yosys can synthesize so always @ (en or d) if (en) q <= d; would describe a dlatch and always @(posedge clk) ... a dff, etc. following the patterns described in IEEE 1364.1.

For designs that use multiple clocks (which includes posedge and negedge of the same clock signal) or any async logic besides async resets (that includes latches) it may be necessary to use the clk2fflogic pass at the end of the gate and gold scripts. Such a design may work without that pass, but in that case would correspond to an implicit assumption that all clocks are the same global clock and that any async logic is an async reset for FFs using that clock. In the context of EQY this would then mean that any differences that are hidden by that assumption would not be detected.

This is described here https://yosyshq.readthedocs.io/projects/ap011/en/latest/faq_sby.html#clock-signals although as that was written for SBY it mentions the multiclock on option which corresponds to adding clk2fflogic in EQY.

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Instead of using the verilog simulation models, which usually aren't written using synthesizable verilog and thus require manual edits, it might also be possible to use read_liberty if there is a corresponding liberty file that defines the cell behavior and which yosys can read.

I'm not too familiar with the liberty file format, and even less familiar with the organization of the asap7 PDK, but this seems to mostly work with the latches and FFs when running this to convert some of the asap7 liberty files into synthesizable verilog that should work with EQY:

yosys -p 'read_liberty -ignore_miss_func asap7sc7p5t_SEQ_RVT_TT_ccs_201020.lib; write_verilog'

I had to add -ignore_miss_func as read_liberty as the liberty files are missing the function node on the internal IQ pins of the clock gating cells, but fixing this in the liberty files might be easier or at least easier to maintain than manually writing synthesizable verilog cell definitions. If not, converting the cells where this is not an issue from liberty might still reduce the amount of cells that require writing verilog manually.

[jix]

After using the following awk script to add a function definition to the IQ pins the example liberty file I picked loads completely:

gawk '{print};/ pin \(IQ\)/ {print "function : \"ENA + SE\";"}' asap7sc7p5t_SEQ_RVT_TT_ccs_201020.lib > fixed.lib

[maliberty]

If we can use Liberty instead of Verilog to describe the cells that would be great! Can you give an example script for that?

[maliberty]

nvm I see you mean you can do a one-time conversion, not use it directly in eqy

[jix]

You can also directly use read_liberty from EQY. The gate and gold scripts in EQY support all yosys commands. The read_liberty command creates a yosys RTLIL module for each defined cell (given that function definitions are present in the liberty file), the same way that read_verilog would create a yosys RTLIL module for each verilog module. I merely illustrated it using a stand alone yosys invocation as I don't have any structural verilog netlist with matching liberty files at hand to create a complete EQY example.