diff --git a/vunit/parsing/tokenizer.py b/vunit/parsing/tokenizer.py
index e30250aef..e6e79c25f 100644
--- a/vunit/parsing/tokenizer.py
+++ b/vunit/parsing/tokenizer.py
@@ -60,7 +60,7 @@ def add(self, kind, regex, func=None):
 
     def finalize(self):
         self._regex = re.compile(
-            "|".join("(?P<%s>%s)" % spec for spec in self._regexs),
+            "|".join(f"(?P<{spec[0]!s}>{spec[1]!s})" for spec in self._regexs),
             re.VERBOSE | re.MULTILINE,
         )
 
@@ -159,11 +159,8 @@ def expect(self, *kinds):
         """
         token = self.pop()
         if token.kind not in kinds:
-            if len(kinds) == 1:
-                expected = str(kinds[0])
-            else:
-                expected = "any of [%s]" % ", ".join(str(kind) for kind in kinds)
-            raise LocationException.error("Expected %s got %s" % (expected, token.kind), token.location)
+            expected = str(kinds[0]) if len(kinds) == 1 else f"any of [{', '.join(str(kind) for kind in kinds)}]"
+            raise LocationException.error(f"Expected {expected!s} got {token.kind!s}", token.location)
         return token
 
     def slice(self, start, end):
@@ -188,7 +185,7 @@ def describe_location(location, first=True):
         return retval
 
     if not file_exists(file_name):
-        retval += "Unknown location in %s" % file_name
+        retval += f"Unknown location in {file_name!s}"
         return retval
 
     contents = read_file(file_name)
@@ -203,11 +200,7 @@ def describe_location(location, first=True):
         lstart = count
         lend = lstart + len(line)
         if lstart <= start <= lend:
-            retval += "%s %s line %i:\n" % (
-                prefix,
-                simplify_path(file_name),
-                lineno + 1,
-            )
+            retval += f"{prefix!s} {simplify_path(file_name)!s} line {lineno + 1:d}:\n"
             retval += line + "\n"
             retval += (" " * (start - lstart)) + ("~" * (min(lend - 1, end) - start + 1))
             return retval
diff --git a/vunit/sim_if/activehdl.py b/vunit/sim_if/activehdl.py
index 9e973d8ae..c496a350d 100644
--- a/vunit/sim_if/activehdl.py
+++ b/vunit/sim_if/activehdl.py
@@ -110,9 +110,9 @@ def _std_str(vhdl_standard):
         Convert standard to format of Active-HDL command line flag
         """
         if vhdl_standard <= VHDL.STD_2008:
-            return "-%s" % vhdl_standard
+            return f"-{vhdl_standard!s}"
 
-        raise ValueError("Invalid VHDL standard %s" % vhdl_standard)
+        raise ValueError(f"Invalid VHDL standard {vhdl_standard!s}")
 
     def compile_vhdl_file_command(self, source_file):
         """
@@ -144,9 +144,9 @@ def compile_verilog_file_command(self, source_file):
         for library in self._libraries:
             args += ["-l", library.name]
         for include_dir in source_file.include_dirs:
-            args += ["+incdir+%s" % include_dir]
+            args += [f"+incdir+{include_dir!s}"]
         for key, value in source_file.defines.items():
-            args += ["+define+%s=%s" % (key, value)]
+            args += [f"+define+{key!s}={value!s}"]
         return args
 
     def create_library(self, library_name, path, mapped_libraries=None):
@@ -186,7 +186,7 @@ def _create_library_cfg(self):
             return
 
         with Path(self._library_cfg).open("w", encoding="utf-8") as ofile:
-            ofile.write('$INCLUDE = "%s"\n' % str(Path(self._prefix).parent / "vlib" / "library.cfg"))
+            ofile.write(f'$INCLUDE = "{str(Path(self._prefix).parent / "vlib" / "library.cfg")}"\n')
 
     _library_re = re.compile(r'([a-zA-Z_]+)\s=\s"(.*)"')
 
@@ -224,12 +224,12 @@ def _create_load_function(self, config, output_path):
         Create the vunit_load TCL function that runs the vsim command and loads the design
         """
         set_generic_str = "\n    ".join(
-            ("set vunit_generic_%s {%s}" % (name, value) for name, value in config.generics.items())
+            (f"set vunit_generic_{name!s} {{{value!s}}}" for name, value in config.generics.items())
         )
         set_generic_name_str = " ".join(
-            ("-g/%s/%s=${vunit_generic_%s}" % (config.entity_name, name, name) for name in config.generics)
+            (f"-g/{config.entity_name!s}/{name!s}=${{vunit_generic_{name!s}}}" for name in config.generics)
         )
-        pli_str = " ".join('-pli "%s"' % fix_path(name) for name in config.sim_options.get("pli", []))
+        pli_str = " ".join(f'-pli "{fix_path(name)}"' for name in config.sim_options.get("pli", []))
 
         vsim_flags = [
             pli_str,
@@ -245,7 +245,7 @@ def _create_load_function(self, config, output_path):
         if config.sim_options.get("enable_coverage", False):
             coverage_file_path = str(Path(output_path) / "coverage.acdb")
             self._coverage_files.add(coverage_file_path)
-            vsim_flags += ["-acdb_file {%s}" % fix_path(coverage_file_path)]
+            vsim_flags += [f"-acdb_file {{{fix_path(coverage_file_path)!s}}}"]
 
         vsim_flags += [self._vsim_extra_args(config)]
 
@@ -257,29 +257,25 @@ def _create_load_function(self, config, output_path):
 
         vhdl_assert_stop_level_mapping = dict(warning=1, error=2, failure=3)
 
-        tcl = """
+        tcl = f"""
 proc vunit_load {{}} {{
     {set_generic_str}
     set vsim_failed [catch {{
-        vsim {vsim_flags}
+        vsim {' '.join(vsim_flags)}
     }}]
     if {{${{vsim_failed}}}} {{
         return true
     }}
 
     global breakassertlevel
-    set breakassertlevel {breaklevel}
+    set breakassertlevel {{{vhdl_assert_stop_level_mapping[config.vhdl_assert_stop_level]}}}
 
     global builtinbreakassertlevel
     set builtinbreakassertlevel $breakassertlevel
 
     return false
 }}
-""".format(
-            set_generic_str=set_generic_str,
-            vsim_flags=" ".join(vsim_flags),
-            breaklevel=vhdl_assert_stop_level_mapping[config.vhdl_assert_stop_level],
-        )
+"""
 
         return tcl
 
@@ -314,14 +310,14 @@ def merge_coverage(self, file_name, args=None):
 
         for coverage_file in self._coverage_files:
             if file_exists(coverage_file):
-                merge_command += " -i {%s}" % fix_path(coverage_file)
+                merge_command += f" -i {{{fix_path(coverage_file)!s}}}"
             else:
                 LOGGER.warning("Missing coverage file: %s", coverage_file)
 
         if args is not None:
-            merge_command += " " + " ".join("{%s}" % arg for arg in args)
+            merge_command += " " + " ".join(f"{{{arg!s}}}" for arg in args)
 
-        merge_command += " -o {%s}" % fix_path(file_name) + "\n"
+        merge_command += f" -o {{{fix_path(file_name)!s}}}\n"
 
         merge_script_name = str(Path(self._output_path) / "acdb_merge.tcl")
         with Path(merge_script_name).open("w", encoding="utf-8") as fptr:
@@ -330,10 +326,10 @@ def merge_coverage(self, file_name, args=None):
         vcover_cmd = [
             str(Path(self._prefix) / "vsimsa"),
             "-tcl",
-            "%s" % fix_path(merge_script_name),
+            str(fix_path(merge_script_name)),
         ]
 
-        print("Merging coverage files into %s..." % file_name)
+        print(f"Merging coverage files into {file_name!s}...")
         vcover_merge_process = Process(vcover_cmd, env=self.get_env())
         vcover_merge_process.consume_output()
         print("Done merging coverage files")
@@ -354,7 +350,7 @@ def _create_batch_script(common_file_name, load_only=False):
         Create tcl script to run in batch mode
         """
         batch_do = ""
-        batch_do += 'source "%s"\n' % fix_path(common_file_name)
+        batch_do += f'source "{fix_path(common_file_name)!s}"\n'
         batch_do += "set failed [vunit_load]\n"
         batch_do += "if {$failed} {quit -code 1}\n"
         if not load_only:
@@ -369,18 +365,18 @@ def _create_gui_script(self, common_file_name, config):
         """
 
         tcl = ""
-        tcl += 'source "%s"\n' % fix_path(common_file_name)
+        tcl += f'source "{fix_path(common_file_name)!s}"\n'
         tcl += "workspace create workspace\n"
         tcl += "design create -a design .\n"
 
         for library in self._libraries:
-            tcl += "vmap %s %s\n" % (library.name, fix_path(library.directory))
+            tcl += f"vmap {library.name!s} {fix_path(library.directory)!s}\n"
 
         tcl += "vunit_load\n"
 
         init_file = config.sim_options.get(self.name + ".init_file.gui", None)
         if init_file is not None:
-            tcl += 'source "%s"\n' % fix_path(str(Path(init_file).resolve()))
+            tcl += f'source "{fix_path(str(Path(init_file).resolve()))!s}"\n'
 
         tcl += 'puts "VUnit help: Design already loaded. Use run -all to run the test."\n'
 
@@ -391,7 +387,7 @@ def _run_batch_file(self, batch_file_name, gui, cwd):
         Run a test bench in batch by invoking a new vsim process from the command line
         """
 
-        todo = '@do -tcl ""%s""' % fix_path(batch_file_name)
+        todo = f'@do -tcl ""{fix_path(batch_file_name)!s}""'
         if not gui:
             todo = "@onerror {quit -code 1};" + todo
 
diff --git a/vunit/sim_if/cds_file.py b/vunit/sim_if/cds_file.py
index c1f8f57ca..f1c703491 100644
--- a/vunit/sim_if/cds_file.py
+++ b/vunit/sim_if/cds_file.py
@@ -49,5 +49,7 @@ def write(self, file_name):
         """
         Write cds file to file named 'file_name'
         """
-        contents = "\n".join(self._other_lines + ['define %s "%s"' % item for item in sorted(self.items())]) + "\n"
+        contents = (
+            "\n".join(self._other_lines + [f'define {item[0]!s} "{item[1]!s}"' for item in sorted(self.items())]) + "\n"
+        )
         write_file(file_name, contents)
diff --git a/vunit/sim_if/factory.py b/vunit/sim_if/factory.py
index 523ef79fa..a1ff1dd14 100644
--- a/vunit/sim_if/factory.py
+++ b/vunit/sim_if/factory.py
@@ -80,7 +80,7 @@ def check_sim_option(self, name, value):
         known_options = sorted(list(self._sim_options.keys()))
 
         if name not in self._sim_options:
-            raise ValueError("Unknown sim_option %r, expected one of %r" % (name, known_options))
+            raise ValueError(f"Unknown sim_option {name!r}, expected one of {known_options!r}")
 
         self._sim_options[name].validate(value)
 
@@ -90,7 +90,7 @@ def check_compile_option_name(self, name):
         """
         known_options = sorted(list(self._compile_options.keys()))
         if name not in known_options:
-            raise ValueError("Unknown compile_option %r, expected one of %r" % (name, known_options))
+            raise ValueError(f"Unknown compile_option {name!r}, expected one of {known_options!r}")
 
     def check_compile_option(self, name, value):
         """
diff --git a/vunit/sim_if/incisive.py b/vunit/sim_if/incisive.py
index 0140c14d1..c1f465504 100644
--- a/vunit/sim_if/incisive.py
+++ b/vunit/sim_if/incisive.py
@@ -119,27 +119,24 @@ def _create_cdslib(self):
         """
         cds_root_virtuoso = self.find_cds_root_virtuoso()
 
-        if cds_root_virtuoso is None:
-            contents = """\
+        contents = (
+            f"""\
 ## cds.lib: Defines the locations of compiled libraries.
-softinclude {0}/tools/inca/files/cds.lib
+softinclude {self._cds_root_irun}/tools/inca/files/cds.lib
 # needed for referencing the library 'basic' for cells 'cds_alias', 'cds_thru' etc. in analog models:
 # NOTE: 'virtuoso' executable not found!
 # define basic ".../tools/dfII/etc/cdslib/basic"
-define work "{1}/libraries/work"
-""".format(
-                self._cds_root_irun, self._output_path
-            )
-        else:
-            contents = """\
+define work "{self._output_path}/libraries/work"
+"""
+            if cds_root_virtuoso is None
+            else f"""\
 ## cds.lib: Defines the locations of compiled libraries.
-softinclude {0}/tools/inca/files/cds.lib
+softinclude {self._cds_root_irun}/tools/inca/files/cds.lib
 # needed for referencing the library 'basic' for cells 'cds_alias', 'cds_thru' etc. in analog models:
-define basic "{1}/tools/dfII/etc/cdslib/basic"
-define work "{2}/libraries/work"
-""".format(
-                self._cds_root_irun, cds_root_virtuoso, self._output_path
-            )
+define basic "{cds_root_virtuoso}/tools/dfII/etc/cdslib/basic"
+define work "{self._output_path}/libraries/work"
+"""
+        )
 
         write_file(self._cdslib, contents)
 
@@ -179,7 +176,7 @@ def _vhdl_std_opt(vhdl_standard):
         if vhdl_standard == VHDL.STD_1993:
             return "-v93"
 
-        raise ValueError("Invalid VHDL standard %s" % vhdl_standard)
+        raise ValueError(f"Invalid VHDL standard {vhdl_standard!s}")
 
     def compile_vhdl_file_command(self, source_file):
         """
@@ -192,24 +189,22 @@ def compile_vhdl_file_command(self, source_file):
         args += ["-licqueue"]
         args += ["-nowarn DLCPTH"]  # "cds.lib Invalid path"
         args += ["-nowarn DLCVAR"]  # "cds.lib Invalid environment variable ''."
-        args += ["%s" % self._vhdl_std_opt(source_file.get_vhdl_standard())]
+        args += [str(self._vhdl_std_opt(source_file.get_vhdl_standard()))]
         args += ["-work work"]
-        args += ['-cdslib "%s"' % self._cdslib]
+        args += [f'-cdslib "{self._cdslib!s}"']
         args += self._hdlvar_args()
-        args += [
-            '-log "%s"' % str(Path(self._output_path) / ("irun_compile_vhdl_file_%s.log" % source_file.library.name))
-        ]
+        args += [f'-log "{(Path(self._output_path) / f"irun_compile_vhdl_file_{source_file.library.name!s}.log")!s}"']
         if not self._log_level == "debug":
             args += ["-quiet"]
         else:
             args += ["-messages"]
             args += ["-libverbose"]
         args += source_file.compile_options.get("incisive.irun_vhdl_flags", [])
-        args += ['-nclibdirname "%s"' % str(Path(source_file.library.directory).parent)]
-        args += ["-makelib %s" % source_file.library.directory]
-        args += ['"%s"' % source_file.name]
+        args += [f'-nclibdirname "{Path(source_file.library.directory).parent!s}"']
+        args += [f"-makelib {source_file.library.directory!s}"]
+        args += [f'"{source_file.name!s}"']
         args += ["-endlib"]
-        argsfile = str(Path(self._output_path) / ("irun_compile_vhdl_file_%s.args" % source_file.library.name))
+        argsfile = str(Path(self._output_path) / f"irun_compile_vhdl_file_{source_file.library.name!s}.args")
         write_file(argsfile, "\n".join(args))
         return [cmd, "-f", argsfile]
 
@@ -230,10 +225,10 @@ def compile_verilog_file_command(self, source_file):
         args += ["-nowarn DLCVAR"]
         args += ["-work work"]
         args += source_file.compile_options.get("incisive.irun_verilog_flags", [])
-        args += ['-cdslib "%s"' % self._cdslib]
+        args += [f'-cdslib "{self._cdslib!s}"']
         args += self._hdlvar_args()
         args += [
-            '-log "%s"' % str(Path(self._output_path) / ("irun_compile_verilog_file_%s.log" % source_file.library.name))
+            f'-log "{(Path(self._output_path) / f"irun_compile_verilog_file_{source_file.library.name!s}.log")!s}"'
         ]
         if not self._log_level == "debug":
             args += ["-quiet"]
@@ -241,18 +236,19 @@ def compile_verilog_file_command(self, source_file):
             args += ["-messages"]
             args += ["-libverbose"]
         for include_dir in source_file.include_dirs:
-            args += ['-incdir "%s"' % include_dir]
+            args += [f'-incdir "{include_dir!s}"']
 
         # for "disciplines.vams" etc.
-        args += ['-incdir "%s/tools/spectre/etc/ahdl/"' % self._cds_root_irun]
+        args += [f'-incdir "{self._cds_root_irun!s}/tools/spectre/etc/ahdl/"']
 
         for key, value in source_file.defines.items():
-            args += ["-define %s=%s" % (key, value.replace('"', '\\"'))]
-        args += ['-nclibdirname "%s"' % str(Path(source_file.library.directory).parent)]
-        args += ["-makelib %s" % source_file.library.name]
-        args += ['"%s"' % source_file.name]
+            val = value.replace('"', '\\"')
+            args += [f"-define {key!s}={val!s}"]
+        args += [f'-nclibdirname "{Path(source_file.library.directory).parent!s}"']
+        args += [f"-makelib {source_file.library.name!s}"]
+        args += [f'"{source_file.name!s}"']
         args += ["-endlib"]
-        argsfile = str(Path(self._output_path) / ("irun_compile_verilog_file_%s.args" % source_file.library.name))
+        argsfile = str(Path(self._output_path) / f"irun_compile_verilog_file_{source_file.library.name!s}.args")
         write_file(argsfile, "\n".join(args))
         return [cmd, "-f", argsfile]
 
@@ -314,11 +310,11 @@ def simulate(self, output_path, test_suite_name, config, elaborate_only=False):
             args += ["-ncerror EVBSTR"]  # promote to error: "bad string literal in generic association"
             args += ["-ncerror EVBNAT"]  # promote to error: "bad natural literal in generic association"
             args += ["-work work"]
-            args += ['-nclibdirname "%s"' % (str(Path(self._output_path) / "libraries"))]  # @TODO: ugly
+            args += [f'-nclibdirname "{Path(self._output_path) / "libraries"!s}"']  # @TODO: ugly
             args += config.sim_options.get("incisive.irun_sim_flags", [])
-            args += ['-cdslib "%s"' % self._cdslib]
+            args += [f'-cdslib "{self._cdslib!s}"']
             args += self._hdlvar_args()
-            args += ['-log "%s"' % str(Path(script_path) / ("irun_%s.log" % step))]
+            args += [f'-log "{(Path(script_path) / f"irun_{step!s}.log")!s}"']
             if not self._log_level == "debug":
                 args += ["-quiet"]
             else:
@@ -326,7 +322,7 @@ def simulate(self, output_path, test_suite_name, config, elaborate_only=False):
                 # args += ['-libverbose']
             args += self._generic_args(config.entity_name, config.generics)
             for library in self._libraries:
-                args += ['-reflib "%s"' % library.directory]
+                args += [f'-reflib "{library.directory!s}"']
             if launch_gui:
                 args += ["-access +rwc"]
                 # args += ['-linedebug']
@@ -337,18 +333,11 @@ def simulate(self, output_path, test_suite_name, config, elaborate_only=False):
 
             if config.architecture_name is None:
                 # we have a SystemVerilog toplevel:
-                args += ["-top %s.%s:sv" % (config.library_name, config.entity_name)]
+                args += [f"-top {config.library_name!s}.{config.entity_name!s}:sv"]
             else:
                 # we have a VHDL toplevel:
-                args += [
-                    "-top %s.%s:%s"
-                    % (
-                        config.library_name,
-                        config.entity_name,
-                        config.architecture_name,
-                    )
-                ]
-            argsfile = "%s/irun_%s.args" % (script_path, step)
+                args += [f"-top {config.library_name!s}.{config.entity_name!s}:{config.architecture_name!s}"]
+            argsfile = f"{script_path!s}/irun_{step!s}.args"
             write_file(argsfile, "\n".join(args))
             if not run_command(
                 [cmd, "-f", relpath(argsfile, script_path)],
@@ -364,7 +353,7 @@ def _hdlvar_args(self):
         """
         if self._hdlvar is None:
             return []
-        return ['-hdlvar "%s"' % self._hdlvar]
+        return [f'-hdlvar "{self._hdlvar!s}"']
 
     @staticmethod
     def _generic_args(entity_name, generics):
@@ -373,10 +362,11 @@ def _generic_args(entity_name, generics):
         """
         args = []
         for name, value in generics.items():
-            if _generic_needs_quoting(value):
-                args += ['''-gpg "%s.%s => \\"%s\\""''' % (entity_name, name, value)]
-            else:
-                args += ['''-gpg "%s.%s => %s"''' % (entity_name, name, value)]
+            args += (
+                [f'''-gpg "{entity_name!s}.{name!s} => \\"{value!s}\\""''']
+                if _generic_needs_quoting(value)
+                else [f'''-gpg "{entity_name!s}.{name!s} => {value!s}"''']
+            )
         return args
 
 
diff --git a/vunit/sim_if/modelsim.py b/vunit/sim_if/modelsim.py
index 2e3045699..eef039d91 100644
--- a/vunit/sim_if/modelsim.py
+++ b/vunit/sim_if/modelsim.py
@@ -149,9 +149,9 @@ def _std_str(vhdl_standard):
         Convert standard to format of Modelsim command line flag
         """
         if vhdl_standard <= VHDL.STD_2008:
-            return "-%s" % vhdl_standard
+            return f"-{vhdl_standard!s}"
 
-        raise ValueError("Invalid VHDL standard %s" % vhdl_standard)
+        raise ValueError(f"Invalid VHDL standard {vhdl_standard!s}")
 
     def compile_vhdl_file_command(self, source_file):
         """
@@ -191,9 +191,9 @@ def compile_verilog_file_command(self, source_file):
         for library in self._libraries:
             args += ["-L", library.name]
         for include_dir in source_file.include_dirs:
-            args += ["+incdir+%s" % include_dir]
+            args += [f"+incdir+{include_dir!s}"]
         for key, value in source_file.defines.items():
-            args += ["+define+%s=%s" % (key, value)]
+            args += [f"+define+{key!s}={value!s}"]
         return args
 
     def create_library(self, library_name, path, mapped_libraries=None):
@@ -235,23 +235,23 @@ def _create_load_function(self, test_suite_name, config, output_path):
 
         set_generic_str = " ".join(
             (
-                "-g/%s/%s=%s" % (config.entity_name, name, encode_generic_value(value))
+                f"-g/{config.entity_name!s}/{name!s}={encode_generic_value(value)!s}"
                 for name, value in config.generics.items()
             )
         )
-        pli_str = " ".join("-pli {%s}" % fix_path(name) for name in config.sim_options.get("pli", []))
+        pli_str = " ".join(f"-pli {{{fix_path(name)!s}}}" for name in config.sim_options.get("pli", []))
 
         if config.architecture_name is None:
             architecture_suffix = ""
         else:
-            architecture_suffix = "(%s)" % config.architecture_name
+            architecture_suffix = f"({config.architecture_name!s})"
 
         if config.sim_options.get("enable_coverage", False):
             coverage_file = str(Path(output_path) / "coverage.ucdb")
             self._coverage_files.add(coverage_file)
-            coverage_save_cmd = "coverage save -onexit -testname {%s} -assert -directive -cvg -codeAll {%s}" % (
-                test_suite_name,
-                fix_path(coverage_file),
+            coverage_save_cmd = (
+                f"coverage save -onexit -testname {{{test_suite_name!s}}} -assert -directive "
+                f"-cvg -codeAll {{{fix_path(coverage_file)!s}}}"
             )
             coverage_args = "-coverage"
         else:
@@ -259,7 +259,7 @@ def _create_load_function(self, test_suite_name, config, output_path):
             coverage_args = ""
 
         vsim_flags = [
-            "-wlf {%s}" % fix_path(str(Path(output_path) / "vsim.wlf")),
+            f"-wlf {{{fix_path(str(Path(output_path) / 'vsim.wlf'))!s}}}",
             "-quiet",
             "-t ps",
             # for correct handling of verilog fatal/finish
@@ -274,7 +274,7 @@ def _create_load_function(self, test_suite_name, config, output_path):
         # There is a known bug in modelsim that prevents the -modelsimini flag from accepting
         # a space in the path even with escaping, see issue #36
         if " " not in self._sim_cfg_file_name:
-            vsim_flags.insert(0, "-modelsimini %s" % fix_path(self._sim_cfg_file_name))
+            vsim_flags.insert(0, f"-modelsimini {fix_path(self._sim_cfg_file_name)!s}")
 
         for library in self._libraries:
             vsim_flags += ["-L", library.name]
@@ -386,7 +386,7 @@ def merge_coverage(self, file_name, args=None):
                 else:
                     LOGGER.warning("Missing coverage file: %s", coverage_file)
 
-        print("Merging coverage files into %s..." % file_name)
+        print(f"Merging coverage files into {file_name!s}...")
         vcover_merge_process = Process(vcover_cmd, env=self.get_env())
         vcover_merge_process.consume_output()
         print("Done merging coverage files")
@@ -410,9 +410,9 @@ def encode_generic_value(value):
     """
     s_value = str(value)
     if " " in s_value:
-        return '{"%s"}' % s_value
+        return f'{{"{s_value!s}"}}'
     if "," in s_value:
-        return '"%s"' % s_value
+        return f'"{s_value!s}"'
     return s_value
 
 
diff --git a/vunit/sim_if/rivierapro.py b/vunit/sim_if/rivierapro.py
index c90c9ebb5..b263975a5 100644
--- a/vunit/sim_if/rivierapro.py
+++ b/vunit/sim_if/rivierapro.py
@@ -164,7 +164,7 @@ def _std_str(self, vhdl_standard):
 
             return "-2019"
 
-        return "-%s" % vhdl_standard
+        return f"-{vhdl_standard!s}"
 
     def compile_vhdl_file_command(self, source_file):
         """
@@ -204,11 +204,11 @@ def compile_verilog_file_command(self, source_file):
         for library in self._libraries:
             args += ["-l", library.name]
         for include_dir in source_file.include_dirs:
-            args += ["+incdir+%s" % include_dir]
+            args += [f"+incdir+{include_dir!s}"]
         for key, value in source_file.defines.items():
-            args += ["+define+%s" % key]
+            args += [f"+define+{key!s}"]
             if value:
-                args[-1] += "=%s" % value
+                args[-1] += f"={value!s}"
         return args
 
     def create_library(self, library_name, path, mapped_libraries=None):
@@ -248,7 +248,7 @@ def _create_library_cfg(self):
             return
 
         with Path(self._sim_cfg_file_name).open("w", encoding="utf-8") as ofile:
-            ofile.write('$INCLUDE = "%s"\n' % self._builtin_library_cfg)
+            ofile.write(f'$INCLUDE = "{self._builtin_library_cfg!s}"\n')
 
     @property
     def _builtin_library_cfg(self):
@@ -279,15 +279,12 @@ def _create_load_function(self, test_suite_name, config, output_path):  # pylint
         Create the vunit_load TCL function that runs the vsim command and loads the design
         """
         set_generic_str = " ".join(
-            (
-                "-g/%s/%s=%s" % (config.entity_name, name, format_generic(value))
-                for name, value in config.generics.items()
-            )
+            (f"-g/{config.entity_name!s}/{name!s}={format_generic(value)!s}" for name, value in config.generics.items())
         )
-        pli_str = " ".join('-pli "%s"' % fix_path(name) for name in config.sim_options.get("pli", []))
+        pli_str = " ".join(f'-pli "{fix_path(name)}"' for name in config.sim_options.get("pli", []))
 
         vsim_flags = [
-            "-dataset {%s}" % fix_path(str(Path(output_path) / "dataset.asdb")),
+            f"-dataset {{{fix_path(str(Path(output_path) / 'dataset.asdb'))!s}}}",
             pli_str,
             set_generic_str,
         ]
@@ -295,7 +292,7 @@ def _create_load_function(self, test_suite_name, config, output_path):  # pylint
         if config.sim_options.get("enable_coverage", False):
             coverage_file_path = str(Path(output_path) / "coverage.acdb")
             self._coverage_files.add(coverage_file_path)
-            vsim_flags += ["-acdb_file {%s}" % coverage_file_path]
+            vsim_flags += [f"-acdb_file {{{coverage_file_path!s}}}"]
 
         vsim_flags += [self._vsim_extra_args(config)]
 
@@ -398,27 +395,30 @@ def merge_coverage(self, file_name, args=None):
 
         for coverage_file in self._coverage_files:
             if file_exists(coverage_file):
-                merge_command += " -i {%s}" % coverage_file.replace("\\", "/")
+                cfile = coverage_file.replace("\\", "/")
+                merge_command += f" -i {{{cfile}}}"
             else:
                 LOGGER.warning("Missing coverage file: %s", coverage_file)
 
         if args is not None:
-            merge_command += " " + " ".join("{%s}" % arg for arg in args)
+            merge_command += " " + " ".join(f"{{{arg!s}}}" for arg in args)
 
-        merge_command += " -o {%s}" % file_name.replace("\\", "/")
+        fname = file_name.replace("\\", "/")
+        merge_command += f" -o {{{fname}}}"
 
         merge_script_name = Path(self._output_path) / "acdb_merge.tcl"
         with merge_script_name.open("w", encoding="utf-8") as fptr:
             fptr.write(merge_command + "\n")
 
+        mscript = str(merge_script_name).replace("\\", "/")
         vcover_cmd = [
             str(Path(self._prefix) / "vsim"),
             "-c",
             "-do",
-            "source {%s}; quit;" % str(merge_script_name).replace("\\", "/"),
+            f"source {{{mscript}}}; quit;",
         ]
 
-        print("Merging coverage files into %s..." % file_name)
+        print(f"Merging coverage files into {file_name!s}...")
         vcover_merge_process = Process(vcover_cmd, env=self.get_env())
         vcover_merge_process.consume_output()
         print("Done merging coverage files")
@@ -429,9 +429,7 @@ def format_generic(value):
     Generic values with space in them need to be quoted
     """
     value_str = str(value)
-    if " " in value_str:
-        return '"%s"' % value_str
-    return value_str
+    return f'"{value_str!s}"' if " " in value_str else value_str
 
 
 class VersionConsumer(object):
diff --git a/vunit/sim_if/vsim_simulator_mixin.py b/vunit/sim_if/vsim_simulator_mixin.py
index 9c5b1cdad..8d89e066e 100644
--- a/vunit/sim_if/vsim_simulator_mixin.py
+++ b/vunit/sim_if/vsim_simulator_mixin.py
@@ -37,7 +37,7 @@ def create_process(ident):
                     str(Path(prefix) / "vsim"),
                     "-c",
                     "-l",
-                    str(Path(sim_cfg_file_name).parent / ("transcript%i" % ident)),
+                    str(Path(sim_cfg_file_name).parent / f"transcript{ident}"),
                     "-do",
                     str((Path(__file__).parent / "tcl_read_eval_loop.tcl").resolve()),
                 ],
@@ -76,55 +76,50 @@ def _create_restart_function():
         # relies on the return code from the python process rather than being
         # tricked by output going to stderr.  See issue #228.
         recompile_command_eval = [
-            "%s" % sys.executable,
+            str(sys.executable),
             "-u",
             "-c",
             (
                 "import sys;"
                 "import subprocess;"
-                "exit(subprocess.call(%r, "
-                "cwd=%r, "
+                f"exit(subprocess.call({recompile_command!r}, "
+                f"cwd={str(Path(os.getcwd()).resolve())!r}, "
                 "bufsize=0, "
                 "universal_newlines=True, "
                 "stdout=sys.stdout, "
                 "stderr=sys.stdout))"
-            )
-            % (recompile_command, str(Path(os.getcwd()).resolve())),
+            ),
         ]
-        recompile_command_eval_tcl = " ".join(["{%s}" % part for part in recompile_command_eval])
+        recompile_command_eval_tcl = " ".join([f"{{{part}}}" for part in recompile_command_eval])
 
-        tcl = """
-proc vunit_compile {} {
-    set cmd_show {%s}
-    puts "Re-compiling using command ${cmd_show}"
+        return f"""
+proc vunit_compile {{}} {{
+    set cmd_show {{{recompile_command_visual!s}}}
+    puts "Re-compiling using command ${{cmd_show}}"
 
-    set chan [open |[list %s] r]
+    set chan [open |[list {recompile_command_eval_tcl!s}] r]
 
-    while {[gets $chan line] >= 0} {
+    while {{[gets $chan line] >= 0}} {{
         puts $line
-    }
+    }}
 
-    if {[catch {close $chan} error_msg]} {
+    if {{[catch {{close $chan}} error_msg]}} {{
         puts "Re-compile failed"
-        puts ${error_msg}
+        puts ${{error_msg}}
         return true
-    } else {
+    }} else {{
         puts "Re-compile finished"
         return false
-    }
-}
+    }}
+}}
 
-proc vunit_restart {} {
-    if {![vunit_compile]} {
+proc vunit_restart {{}} {{
+    if {{![vunit_compile]}} {{
         _vunit_sim_restart
         vunit_run
-    }
-}
-""" % (
-            recompile_command_visual,
-            recompile_command_eval_tcl,
-        )
-        return tcl
+    }}
+}}
+"""
 
     def _create_common_script(self, test_suite_name, config, script_path, output_path):
         """
@@ -182,7 +177,7 @@ def _create_batch_script(common_file_name, load_only=False):
         """
         batch_do = ""
         batch_do += "onerror {quit -code 1}\n"
-        batch_do += 'source "%s"\n' % fix_path(common_file_name)
+        batch_do += f'source "{fix_path(common_file_name)!s}"\n'
         batch_do += "set failed [vunit_load]\n"
         batch_do += "if {$failed} {quit -code 1}\n"
         if not load_only:
@@ -260,7 +255,7 @@ def _create_gui_script(self, common_file_name, config):
         """
         Create the user facing script which loads common functions and prints a help message
         """
-        tcl = 'source "%s"\n' % fix_path(common_file_name)
+        tcl = f'source "{fix_path(common_file_name)!s}"\n'
         tcl += self._create_user_init_function(config)
         tcl += "if {![vunit_load]} {\n"
         tcl += "  vunit_user_init\n"
@@ -280,7 +275,7 @@ def _run_batch_file(self, batch_file_name, gui=False):
                 "-l",
                 str(Path(batch_file_name).parent / "transcript"),
                 "-do",
-                'source "%s"' % fix_path(batch_file_name),
+                f'source "{fix_path(batch_file_name)!s}"',
             ]
 
             proc = Process(args, cwd=str(Path(self._sim_cfg_file_name).parent))
@@ -294,7 +289,7 @@ def _run_persistent(self, common_file_name, load_only=False):
         Run a test bench using the persistent vsim process
         """
         try:
-            self._persistent_shell.execute('source "%s"' % fix_path(common_file_name))
+            self._persistent_shell.execute(f'source "{fix_path(common_file_name)!s}"')
             self._persistent_shell.execute("set failed [vunit_load]")
             if self._persistent_shell.read_bool("failed"):
                 return False
@@ -349,22 +344,18 @@ def get_is_test_suite_done_tcl(vunit_result_file):
     Returns tcl procedure to detect if simulation was successful or not
     Simulation is considered successful if the test_suite_done was reached in the results file
     """
-
-    tcl = """
-proc is_test_suite_done {} {
-    set fd [open "%s" "r"]
+    return f"""
+proc is_test_suite_done {{}} {{
+    set fd [open "{fix_path(vunit_result_file)!s}" "r"]
     set contents [read $fd]
     close $fd
     set lines [split $contents "\n"]
-    foreach line $lines {
-        if {$line=="test_suite_done"} {
+    foreach line $lines {{
+        if {{$line=="test_suite_done"}} {{
            return true;
-        }
-    }
+        }}
+    }}
 
     return false;
-}
-""" % (
-        fix_path(vunit_result_file)
-    )
-    return tcl
+}}
+"""