From 2c8b50a8ecb0b0e05edbb210ed061d800309e159 Mon Sep 17 00:00:00 2001 From: Sleigh-InSPECtor Date: Tue, 30 Jul 2024 20:37:32 +0930 Subject: [PATCH] [msp430] fixed ordering of SP decrementing for CALLA --- .../TI_MSP430/data/languages/TI430X.sinc | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/Ghidra/Processors/TI_MSP430/data/languages/TI430X.sinc b/Ghidra/Processors/TI_MSP430/data/languages/TI430X.sinc index b809311c71c..231864d5e42 100644 --- a/Ghidra/Processors/TI_MSP430/data/languages/TI430X.sinc +++ b/Ghidra/Processors/TI_MSP430/data/languages/TI430X.sinc @@ -1106,34 +1106,34 @@ macro suba(dst, src) { # # Other 20 bit address instructions :CALLA DST20_0_4 is ctx_haveext=0 & op16_8_8=0x13 & op16_4_4=0x4 & DST20_0_4 { + PC = DST20_0_4 & ~1; SP = SP - 0x4; *:4 SP = inst_next; - PC = DST20_0_4 & ~1; call [PC]; } :CALLA imms_0_16^"("^DST20_0_4^")" is ctx_haveext=0 & op16_8_8=0x13 & op16_4_4=0x5 & DST20_0_4 ; imms_0_16 { - SP = SP - 0x4; - *:4 SP = inst_next; tmp:$(REG_SIZE) = DST20_0_4 + sext(imms_0_16:2); PC = *[RAM]:$(REG_SIZE) tmp; PC = PC & 0xffffe; + SP = SP - 0x4; + *:4 SP = inst_next; call [PC]; } :CALLA "@"^DST20_0_4 is ctx_haveext=0 & op16_8_8=0x13 & op16_4_4=0x6 & DST20_0_4 { - SP = SP - 0x4; - *:4 SP = inst_next; PC = *[RAM]:$(REG_SIZE) DST20_0_4; PC = PC & 0xffffe; + SP = SP - 0x4; + *:4 SP = inst_next; call [PC]; } :CALLA "@"^DST20_0_4^"+" is ctx_haveext=0 & op16_8_8=0x13 & op16_4_4=0x7 & DST20_0_4 { - SP = SP - 0x4; - *:4 SP = inst_next; PC = *[RAM]:$(REG_SIZE) DST20_0_4; PC = PC & 0xffffe; + SP = SP - 0x4; + *:4 SP = inst_next; DST20_0_4 = DST20_0_4 + 4; call [PC]; } @@ -1148,11 +1148,11 @@ macro suba(dst, src) { } :CALLA imms_0_16^"(PC)" is ctx_haveext=0 & op16_8_8=0x13 & op16_4_4=0x9 ; imms_0_16 { - SP = SP - 0x4; - *:4 SP = inst_next; tmp:$(REG_SIZE) = inst_start + sext(imms_0_16:2); PC = *[RAM]:$(REG_SIZE) tmp; PC = PC & 0xffffe; + SP = SP - 0x4; + *:4 SP = inst_next; call [PC]; }