diff --git a/basil/utils/sim/utils.py b/basil/utils/sim/utils.py
index c95d13faa..f131aa9ee 100644
--- a/basil/utils/sim/utils.py
+++ b/basil/utils/sim/utils.py
@@ -43,6 +43,13 @@ def cocotb_makefile(sim_files, top_level='tb', test_module='basil.utils.sim.Test
     mkfile += extra
     mkfile += "\n"
 
+    try:
+        if os.environ['SIM'] == 'verilator':
+            mkfile += "EXTRA_ARGS += -DVERILATOR_SIM\n"
+            mkfile += "EXTRA_ARGS += -Wno-WIDTH -Wno-TIMESCALEMOD\n"
+    except KeyError:
+        pass
+
     mkfile += """
 export SIMULATION_HOST
 export SIMULATION_PORT
diff --git a/tests/test_SimFifo8to32.py b/tests/test_SimFifo8to32.py
index 65c2efa18..cccfeea4a 100644
--- a/tests/test_SimFifo8to32.py
+++ b/tests/test_SimFifo8to32.py
@@ -29,9 +29,20 @@
 """
 
 
-class TestSimM26(unittest.TestCase):
+class TestSimFifo8to32(unittest.TestCase):
+    def __init__(self, testname, tb='test_SimFifo8to32.v', bus_drv='basil.utils.sim.BasilBusDriver', bus_split=False):
+        super(TestSimFifo8to32, self).__init__(testname)
+        self._test_tb = tb
+        self._sim_bus = bus_drv
+        self._bus_split_def = ()
+        if bus_split is not False:
+            if bus_split == 'sbus':
+                self._bus_split_def = ("BASIL_SBUS",)
+            elif bus_split == 'top':
+                self._bus_split_def = ("BASIL_TOPSBUS",)
+
     def setUp(self):
-        cocotb_compile_and_run([os.path.join(os.path.dirname(__file__), 'test_SimFifo8to32.v')])
+        cocotb_compile_and_run(sim_files=[os.path.join(os.path.dirname(__file__), self._test_tb)], sim_bus=self._sim_bus, extra_defines=self._bus_split_def)
 
         self.chip = Dut(cnfg_yaml)
         self.chip.init()
diff --git a/tests/test_SimFifo8to32.v b/tests/test_SimFifo8to32.v
index 403110703..015160450 100644
--- a/tests/test_SimFifo8to32.v
+++ b/tests/test_SimFifo8to32.v
@@ -7,6 +7,13 @@
 
 `timescale 1ps / 1ps
 
+`ifdef BASIL_SBUS
+    `define SPLIT_BUS
+`elsif BASIL_TOPSBUS
+    `define SPLIT_BUS
+`endif
+
+`ifndef BASIL_SBUS
 `include "utils/bus_to_ip.v"
 
 `include "utils/cdc_syncfifo.v"
@@ -15,12 +22,20 @@
 
 `include "bram_fifo/bram_fifo_core.v"
 `include "bram_fifo/bram_fifo.v"
+`else
+    $fatal("Sbus modules not implemented yet");
+`endif
 
 module tb (
     input wire          BUS_CLK,
     input wire          BUS_RST,
     input wire  [31:0]  BUS_ADD,
-    inout wire  [31:0]  BUS_DATA,
+`ifndef SPLIT_BUS
+    inout wire  [31:0]   BUS_DATA,
+`else
+    input wire  [31:0]   BUS_DATA_IN,
+    output wire [31:0]   BUS_DATA_OUT,
+`endif
     input wire          BUS_RD,
     input wire          BUS_WR,
     output wire         BUS_BYTE_ACCESS
@@ -35,6 +50,16 @@ localparam FIFO_HIGHADDR_DATA = 32'h9000_0000-1;
 localparam ABUSWIDTH = 32;
 assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
 
+// Connect tb internal bus to external split bus
+`ifdef BASIL_TOPSBUS
+    wire [31:0] BUS_DATA;
+    assign BUS_DATA = BUS_DATA_IN;
+    assign BUS_DATA_OUT = BUS_DATA;
+`elsif BASIL_SBUS
+    wire [31:0] BUS_DATA_OUT_1;
+    assign BUS_DATA_OUT = BUS_DATA_OUT_1;
+`endif
+
 wire FIFO_READ_RX;
 wire FIFO_EMPTY_RX;
 wire [31:0] FIFO_DATA_RX;
@@ -43,19 +68,32 @@ assign cdc_fifo_write = (BUS_ADD >= 32'h1000 && BUS_ADD < 32'h8000) & BUS_WR;
 
 wire fifo_full, cdc_fifo_empty;
 wire [7:0] cdc_data_out;
+
+`ifndef BASIL_SBUS
 cdc_syncfifo #(
+`else
+cdc_syncfifo_sbus #(
+`endif
     .DSIZE(8),
     .ASIZE(3)
 ) cdc_syncfifo_i (
     .rdata(cdc_data_out),
     .wfull(),
     .rempty(cdc_fifo_empty),
+`ifndef BASIL_SBUS
     .wdata(BUS_DATA),
+`else
+    .wdata(BUS_DATA_IN),
+`endif
     .winc(cdc_fifo_write), .wclk(BUS_CLK), .wrst(BUS_RST),
     .rinc(!fifo_full), .rclk(BUS_CLK), .rrst(BUS_RST)
 );
 
+`ifndef BASIL_SBUS
 fifo_8_to_32 #(
+`else
+fifo_8_to_32_sbus #(
+`endif
     .DEPTH(1024)
 ) fifo_8_to_32_i (
     .RST(BUS_RST),
@@ -68,10 +106,14 @@ fifo_8_to_32 #(
     .DATA_OUT(FIFO_DATA)
 );
 
-
 wire FIFO_READ, FIFO_EMPTY;
 wire [31:0] FIFO_DATA;
+
+`ifndef BASIL_SBUS
 bram_fifo #(
+`else
+bram_fifo_sbus #(
+`endif
     .BASEADDR(FIFO_BASEADDR),
     .HIGHADDR(FIFO_HIGHADDR),
     .BASEADDR_DATA(FIFO_BASEADDR_DATA),
@@ -81,7 +123,12 @@ bram_fifo #(
     .BUS_CLK(BUS_CLK),
     .BUS_RST(BUS_RST),
     .BUS_ADD(BUS_ADD),
+`ifndef BASIL_SBUS
     .BUS_DATA(BUS_DATA),
+`else
+    .BUS_DATA_IN(BUS_DATA_IN),
+    .BUS_DATA_OUT(BUS_DATA_OUT_1),
+`endif
     .BUS_RD(BUS_RD),
     .BUS_WR(BUS_WR),
 
@@ -95,9 +142,11 @@ bram_fifo #(
     .FIFO_READ_ERROR()
 );
 
+`ifndef VERILATOR_SIM
 initial begin
     $dumpfile("test_SimFifo8to32.vcd");
     $dumpvars(0);
 end
+`endif
 
 endmodule
diff --git a/tests/test_SimFifo8to32_sbus.py b/tests/test_SimFifo8to32_sbus.py
new file mode 100644
index 000000000..260bcacfe
--- /dev/null
+++ b/tests/test_SimFifo8to32_sbus.py
@@ -0,0 +1,28 @@
+#
+# ------------------------------------------------------------
+# Copyright (c) All rights reserved
+# SiLab, Institute of Physics, University of Bonn
+# ------------------------------------------------------------
+#
+
+import unittest
+import sys
+
+from tests.test_SimFifo8to32 import TestSimFifo8to32
+
+
+if __name__ == '__main__':
+    # https://stackoverflow.com/a/2081750
+    test_loader = unittest.TestLoader()
+    test_names = test_loader.getTestCaseNames(TestSimFifo8to32)
+
+    suite = unittest.TestSuite()
+
+# TODO: add sbus versions of used modules
+#    for test_name in test_names:
+#        suite.addTest(TestSimFifo8to32(testname=test_name, tb='test_SimFifo8to32.v', bus_drv='basil.utils.sim.BasilSbusDriver', bus_split='sbus'))
+    for test_name in test_names:
+        suite.addTest(TestSimFifo8to32(testname=test_name, tb='test_SimFifo8to32.v', bus_drv='basil.utils.sim.BasilSbusDriver', bus_split='top'))
+
+    result = unittest.TextTestRunner().run(suite)
+    sys.exit(not result.wasSuccessful())
diff --git a/tests/test_SimGpio.py b/tests/test_SimGpio.py
index 1e9294358..577d02713 100644
--- a/tests/test_SimGpio.py
+++ b/tests/test_SimGpio.py
@@ -55,13 +55,19 @@
 
 
 class TestSimGpio(unittest.TestCase):
-    def __init__(self, testname, tb='test_SimGpio.v', bus='basil.utils.sim.BasilBusDriver'):
+    def __init__(self, testname, tb='test_SimGpio.v', bus_drv='basil.utils.sim.BasilBusDriver', bus_split=False):
         super(TestSimGpio, self).__init__(testname)
         self._test_tb = tb
-        self._sim_bus = bus
+        self._sim_bus = bus_drv
+        self._bus_split_def = ()
+        if bus_split is not False:
+            if bus_split == 'sbus':
+                self._bus_split_def = ("BASIL_SBUS",)
+            elif bus_split == 'top':
+                self._bus_split_def = ("BASIL_TOPSBUS",)
 
     def setUp(self):
-        cocotb_compile_and_run(sim_files=[os.path.join(os.path.dirname(__file__), self._test_tb)], sim_bus=self._sim_bus)
+        cocotb_compile_and_run(sim_files=[os.path.join(os.path.dirname(__file__), self._test_tb)], sim_bus=self._sim_bus, extra_defines=self._bus_split_def)
 
         self.chip = Dut(cnfg_yaml)
         self.chip.init()
diff --git a/tests/test_SimGpio.v b/tests/test_SimGpio.v
index 5a84d187b..4f76ee541 100644
--- a/tests/test_SimGpio.v
+++ b/tests/test_SimGpio.v
@@ -7,15 +7,31 @@
 
 `timescale 1ps / 1ps
 
-`include "utils/bus_to_ip.v"
+`ifdef BASIL_SBUS
+    `define SPLIT_BUS
+`elsif BASIL_TOPSBUS
+    `define SPLIT_BUS
+`endif
+
 `include "gpio/gpio_core.v"
-`include "gpio/gpio.v"
+`ifndef BASIL_SBUS
+    `include "utils/bus_to_ip.v"
+    `include "gpio/gpio.v"
+`else
+    `include "utils/sbus_to_ip.v"
+    `include "gpio/gpio_sbus.v"
+`endif
 
 module tb (
     input wire          BUS_CLK,
     input wire          BUS_RST,
     input wire  [15:0]  BUS_ADD,
+`ifndef SPLIT_BUS
     inout wire  [7:0]   BUS_DATA,
+`else
+    input wire  [7:0]   BUS_DATA_IN,
+    output wire [7:0]   BUS_DATA_OUT,
+`endif
     input wire          BUS_RD,
     input wire          BUS_WR
 );
@@ -26,9 +42,29 @@ localparam GPIO_HIGHADDR = 16'h000f;
 localparam GPIO2_BASEADDR = 16'h0010;
 localparam GPIO2_HIGHADDR = 16'h001f;
 
+// Connect tb internal bus to external split bus
+`ifdef BASIL_TOPSBUS
+    wire [7:0] BUS_DATA;
+    assign BUS_DATA = BUS_DATA_IN;
+    assign BUS_DATA_OUT = BUS_DATA;
+`elsif BASIL_SBUS
+    wire [7:0] BUS_DATA_OUT_1;
+    wire [7:0] BUS_DATA_OUT_2;
+    assign BUS_DATA_OUT = BUS_DATA_OUT_1 | BUS_DATA_OUT_2;
+`endif
+
+/* verilator lint_off UNOPT */
 wire [23:0] IO;
 
+assign IO[15:8] = IO[7:0];
+assign IO[23:20] = IO[19:16];
+/* verilator lint_on UNOPT */
+
+`ifndef BASIL_SBUS
 gpio #(
+`else
+gpio_sbus #(
+`endif
     .BASEADDR(GPIO_BASEADDR),
     .HIGHADDR(GPIO_HIGHADDR),
     .IO_WIDTH(24),
@@ -38,17 +74,25 @@ gpio #(
     .BUS_CLK(BUS_CLK),
     .BUS_RST(BUS_RST),
     .BUS_ADD(BUS_ADD),
+`ifndef BASIL_SBUS
     .BUS_DATA(BUS_DATA),
+`else
+    .BUS_DATA_IN(BUS_DATA_IN),
+    .BUS_DATA_OUT(BUS_DATA_OUT_1),
+`endif
     .BUS_RD(BUS_RD),
     .BUS_WR(BUS_WR),
     .IO(IO)
 );
 
-assign IO[15:8] = IO[7:0];
-assign IO[23:20] = IO[19:16];
-
 wire [15:0] IO_2;
+assign IO_2 = 16'ha5cd;
+
+`ifndef BASIL_SBUS
 gpio #(
+`else
+gpio_sbus #(
+`endif
     .BASEADDR(GPIO2_BASEADDR),
     .HIGHADDR(GPIO2_HIGHADDR),
     .IO_WIDTH(16),
@@ -57,16 +101,22 @@ gpio #(
     .BUS_CLK(BUS_CLK),
     .BUS_RST(BUS_RST),
     .BUS_ADD(BUS_ADD),
+`ifndef BASIL_SBUS
     .BUS_DATA(BUS_DATA),
+`else
+    .BUS_DATA_IN(BUS_DATA_IN),
+    .BUS_DATA_OUT(BUS_DATA_OUT_2),
+`endif
     .BUS_RD(BUS_RD),
     .BUS_WR(BUS_WR),
     .IO(IO_2)
 );
-assign IO_2 = 16'ha5cd;
 
+`ifndef VERILATOR_SIM
 initial begin
     $dumpfile("gpio.vcd");
     $dumpvars(0);
 end
+`endif
 
 endmodule
diff --git a/tests/test_SimGpio_sbus.py b/tests/test_SimGpio_sbus.py
index b159f4e2c..704be73b3 100644
--- a/tests/test_SimGpio_sbus.py
+++ b/tests/test_SimGpio_sbus.py
@@ -19,9 +19,9 @@
     suite = unittest.TestSuite()
 
     for test_name in test_names:
-        suite.addTest(TestSimGpio(test_name, 'test_SimGpio_sbus.v', 'basil.utils.sim.BasilSbusDriver'))
+        suite.addTest(TestSimGpio(testname=test_name, tb='test_SimGpio.v', bus_drv='basil.utils.sim.BasilSbusDriver', bus_split='sbus'))
     for test_name in test_names:
-        suite.addTest(TestSimGpio(test_name, 'test_SimGpio_sbus_top.v', 'basil.utils.sim.BasilSbusDriver'))
+        suite.addTest(TestSimGpio(testname=test_name, tb='test_SimGpio.v', bus_drv='basil.utils.sim.BasilSbusDriver', bus_split='top'))
 
     result = unittest.TextTestRunner().run(suite)
     sys.exit(not result.wasSuccessful())
diff --git a/tests/test_SimGpio_sbus.v b/tests/test_SimGpio_sbus.v
deleted file mode 100644
index 2c7971e83..000000000
--- a/tests/test_SimGpio_sbus.v
+++ /dev/null
@@ -1,84 +0,0 @@
-/**
- * ------------------------------------------------------------
- * Copyright (c) All rights reserved
- * SiLab, Institute of Physics, University of Bonn
- * ------------------------------------------------------------
- */
-
-`timescale 1ps / 1ps
-
-`include "utils/sbus_to_ip.v"
-`include "gpio/gpio_core.v"
-`include "gpio/gpio_sbus.v"
-
-module tb (
-    input wire          BUS_CLK,
-    input wire          BUS_RST,
-    input wire  [15:0]  BUS_ADD,
-    input wire  [7:0]   BUS_DATA_IN,
-    output wire [7:0]   BUS_DATA_OUT,
-    input wire          BUS_RD,
-    input wire          BUS_WR
-);
-
-localparam GPIO_BASEADDR = 16'h0000;
-localparam GPIO_HIGHADDR = 16'h000f;
-
-localparam GPIO2_BASEADDR = 16'h0010;
-localparam GPIO2_HIGHADDR = 16'h001f;
-
-wire [7:0] BUS_DATA_OUT_1;
-wire [7:0] BUS_DATA_OUT_2;
-
-assign BUS_DATA_OUT = BUS_DATA_OUT_1 | BUS_DATA_OUT_2;
-
-// FIXME: hack for Verilator optimization error
-/* verilator lint_off UNOPT */
-wire [23:0] IO;
-
-assign IO[15:8] = IO[7:0];
-assign IO[23:20] = IO[19:16];
-/* verilator lint_on UNOPT */
-
-gpio_sbus #(
-    .BASEADDR(GPIO_BASEADDR),
-    .HIGHADDR(GPIO_HIGHADDR),
-    .IO_WIDTH(24),
-    .IO_DIRECTION(24'h0000ff),
-    .IO_TRI(24'hff0000)
-) i_gpio (
-    .BUS_CLK(BUS_CLK),
-    .BUS_RST(BUS_RST),
-    .BUS_ADD(BUS_ADD),
-    .BUS_DATA_IN(BUS_DATA_IN),
-    .BUS_DATA_OUT(BUS_DATA_OUT_1),
-    .BUS_RD(BUS_RD),
-    .BUS_WR(BUS_WR),
-    .IO(IO)
-);
-
-wire [15:0] IO_2;
-assign IO_2 = 16'ha5cd;
-
-gpio_sbus #(
-    .BASEADDR(GPIO2_BASEADDR),
-    .HIGHADDR(GPIO2_HIGHADDR),
-    .IO_WIDTH(16),
-    .IO_DIRECTION(16'h0000)
-) i_gpio2 (
-    .BUS_CLK(BUS_CLK),
-    .BUS_RST(BUS_RST),
-    .BUS_ADD(BUS_ADD),
-    .BUS_DATA_IN(BUS_DATA_IN),
-    .BUS_DATA_OUT(BUS_DATA_OUT_2),
-    .BUS_RD(BUS_RD),
-    .BUS_WR(BUS_WR),
-    .IO(IO_2)
-);
-
-initial begin
-    $dumpfile("gpio_sbus1.vcd");
-    $dumpvars(0);
-end
-
-endmodule
diff --git a/tests/test_SimGpio_sbus_top.v b/tests/test_SimGpio_sbus_top.v
deleted file mode 100644
index 16779c860..000000000
--- a/tests/test_SimGpio_sbus_top.v
+++ /dev/null
@@ -1,82 +0,0 @@
-/**
- * ------------------------------------------------------------
- * Copyright (c) All rights reserved
- * SiLab, Institute of Physics, University of Bonn
- * ------------------------------------------------------------
- */
-
-`timescale 1ps / 1ps
-
-`include "utils/bus_to_ip.v"
-`include "gpio/gpio_core.v"
-`include "gpio/gpio.v"
-
-module tb (
-    input wire          BUS_CLK,
-    input wire          BUS_RST,
-    input wire  [15:0]  BUS_ADD,
-    input wire  [7:0]   BUS_DATA_IN,
-    output wire [7:0]   BUS_DATA_OUT,
-    input wire          BUS_RD,
-    input wire          BUS_WR
-);
-
-localparam GPIO_BASEADDR = 16'h0000;
-localparam GPIO_HIGHADDR = 16'h000f;
-
-localparam GPIO2_BASEADDR = 16'h0010;
-localparam GPIO2_HIGHADDR = 16'h001f;
-
-// Connect tb internal bus to external split bus
-wire [7:0] BUS_DATA;
-assign BUS_DATA = BUS_DATA_IN;
-assign BUS_DATA_OUT = BUS_DATA;
-
-// FIXME: hack for Verilator optimization error
-/* verilator lint_off UNOPT */
-wire [23:0] IO;
-
-assign IO[15:8] = IO[7:0];
-assign IO[23:20] = IO[19:16];
-/* verilator lint_on UNOPT */
-
-gpio #(
-    .BASEADDR(GPIO_BASEADDR),
-    .HIGHADDR(GPIO_HIGHADDR),
-    .IO_WIDTH(24),
-    .IO_DIRECTION(24'h0000ff),
-    .IO_TRI(24'hff0000)
-) i_gpio (
-    .BUS_CLK(BUS_CLK),
-    .BUS_RST(BUS_RST),
-    .BUS_ADD(BUS_ADD),
-    .BUS_DATA(BUS_DATA),
-    .BUS_RD(BUS_RD),
-    .BUS_WR(BUS_WR),
-    .IO(IO)
-);
-
-wire [15:0] IO_2;
-assign IO_2 = 16'ha5cd;
-
-gpio #(
-    .BASEADDR(GPIO2_BASEADDR),
-    .HIGHADDR(GPIO2_HIGHADDR),
-    .IO_WIDTH(16),
-    .IO_DIRECTION(16'h0000)
-) i_gpio2 (
-    .BUS_CLK(BUS_CLK),
-    .BUS_RST(BUS_RST),
-    .BUS_ADD(BUS_ADD),
-    .BUS_DATA(BUS_DATA),
-    .BUS_RD(BUS_RD),
-    .BUS_WR(BUS_WR),
-    .IO(IO_2)
-);
-
-initial begin
-    $dumpfile("gpio_sbus2.vcd");
-    $dumpvars(0);
-end
-
-endmodule
diff --git a/tests/test_SimSpi.py b/tests/test_SimSpi.py
index 4fb634687..6e41073d3 100644
--- a/tests/test_SimSpi.py
+++ b/tests/test_SimSpi.py
@@ -64,8 +64,19 @@
 
 
 class TestSimSpi(unittest.TestCase):
+    def __init__(self, testname, tb='test_SimSpi.v', bus_drv='basil.utils.sim.BasilBusDriver', bus_split=False):
+        super(TestSimSpi, self).__init__(testname)
+        self._test_tb = tb
+        self._sim_bus = bus_drv
+        self._bus_split_def = ()
+        if bus_split is not False:
+            if bus_split == 'sbus':
+                self._bus_split_def = ("BASIL_SBUS",)
+            elif bus_split == 'top':
+                self._bus_split_def = ("BASIL_TOPSBUS",)
+
     def setUp(self):
-        cocotb_compile_and_run([os.path.join(os.path.dirname(__file__), 'test_SimSpi.v')])
+        cocotb_compile_and_run(sim_files=[os.path.join(os.path.dirname(__file__), self._test_tb)], sim_bus=self._sim_bus, extra_defines=self._bus_split_def)
 
         self.chip = Dut(cnfg_yaml)
         self.chip.init()
diff --git a/tests/test_SimSpi.v b/tests/test_SimSpi.v
index faedb949f..a21bbeff6 100644
--- a/tests/test_SimSpi.v
+++ b/tests/test_SimSpi.v
@@ -7,37 +7,51 @@
 
 `timescale 1ps / 1ps
 
-
-`include "utils/bus_to_ip.v"
-`include "gpio/gpio_core.v"
-`include "gpio/gpio.v"
-
-`include "spi/spi.v"
-`include "spi/spi_core.v"
-`include "spi/blk_mem_gen_8_to_1_2k.v"
-
-`include "pulse_gen/pulse_gen.v"
-`include "pulse_gen/pulse_gen_core.v"
-
-`include "bram_fifo/bram_fifo_core.v"
-`include "bram_fifo/bram_fifo.v"
-
-`include "fast_spi_rx/fast_spi_rx.v"
-`include "fast_spi_rx/fast_spi_rx_core.v"
-
-`include "utils/cdc_syncfifo.v"
-`include "utils/generic_fifo.v"
-`include "utils/cdc_pulse_sync.v"
-`include "utils/CG_MOD_pos.v"
-`include "utils/clock_divider.v"
-`include "utils/3_stage_synchronizer.v"
-`include "utils/RAMB16_S1_S9_sim.v"
+`ifdef BASIL_SBUS
+    `define SPLIT_BUS
+`elsif BASIL_TOPSBUS
+    `define SPLIT_BUS
+`endif
+
+`ifndef BASIL_SBUS
+    `include "utils/bus_to_ip.v"
+    `include "gpio/gpio_core.v"
+    `include "gpio/gpio.v"
+
+    `include "spi/spi.v"
+    `include "spi/spi_core.v"
+    `include "spi/blk_mem_gen_8_to_1_2k.v"
+
+    `include "pulse_gen/pulse_gen.v"
+    `include "pulse_gen/pulse_gen_core.v"
+
+    `include "bram_fifo/bram_fifo_core.v"
+    `include "bram_fifo/bram_fifo.v"
+
+    `include "fast_spi_rx/fast_spi_rx.v"
+    `include "fast_spi_rx/fast_spi_rx_core.v"
+
+    `include "utils/cdc_syncfifo.v"
+    `include "utils/generic_fifo.v"
+    `include "utils/cdc_pulse_sync.v"
+    `include "utils/CG_MOD_pos.v"
+    `include "utils/clock_divider.v"
+    `include "utils/3_stage_synchronizer.v"
+    `include "utils/RAMB16_S1_S9_sim.v"
+`else
+    $fatal("Sbus modules not implemented yet");
+`endif
 
 module tb (
     input wire          BUS_CLK,
     input wire          BUS_RST,
     input wire  [31:0]  BUS_ADD,
-    inout wire  [31:0]  BUS_DATA,
+`ifndef SPLIT_BUS
+    inout wire  [31:0]   BUS_DATA,
+`else
+    input wire  [31:0]   BUS_DATA_IN,
+    output wire [31:0]   BUS_DATA_OUT,
+`endif
     input wire          BUS_RD,
     input wire          BUS_WR,
     output wire         BUS_BYTE_ACCESS
@@ -65,8 +79,28 @@ localparam FIFO_HIGHADDR_DATA = 32'h9000_0000;
 localparam ABUSWIDTH = 32;
 assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
 
+// BUS/SBUS //
+
+// Connect tb internal bus to external split bus
+`ifdef BASIL_TOPSBUS
+    wire [31:0] BUS_DATA;
+    assign BUS_DATA = BUS_DATA_IN;
+    assign BUS_DATA_OUT = BUS_DATA;
+`elsif BASIL_SBUS
+    wire [31:0] BUS_DATA_OUT_1;
+    wire [31:0] BUS_DATA_OUT_2;
+    wire [31:0] BUS_DATA_OUT_3;
+    wire [31:0] BUS_DATA_OUT_4;
+    wire [31:0] BUS_DATA_OUT_5;
+    assign BUS_DATA_OUT = BUS_DATA_OUT_1 | BUS_DATA_OUT_2 | BUS_DATA_OUT_3 | BUS_DATA_OUT_4 | BUS_DATA_OUT_5;
+`endif
+
 // MODULES //
+`ifndef BASIL_SBUS
 gpio #(
+`else
+gpio_sbus #(
+`endif
     .BASEADDR(GPIO_BASEADDR),
     .HIGHADDR(GPIO_HIGHADDR),
     .ABUSWIDTH(ABUSWIDTH),
@@ -76,7 +110,12 @@ gpio #(
     .BUS_CLK(BUS_CLK),
     .BUS_RST(BUS_RST),
     .BUS_ADD(BUS_ADD),
+`ifndef BASIL_SBUS
     .BUS_DATA(BUS_DATA[7:0]),
+`else
+    .BUS_DATA_IN(BUS_DATA_IN[7:0]),
+    .BUS_DATA_OUT(BUS_DATA_OUT_1[7:0]),
+`endif
     .BUS_RD(BUS_RD),
     .BUS_WR(BUS_WR),
     .IO()
@@ -84,7 +123,11 @@ gpio #(
 
 wire SPI_CLK;
 wire EX_START_PULSE;
+`ifndef BASIL_SBUS
 pulse_gen #(
+`else
+pulse_gen_sbus #(
+`endif
     .BASEADDR(PULSE_BASEADDR),
     .HIGHADDR(PULSE_HIGHADDR),
     .ABUSWIDTH(ABUSWIDTH)
@@ -92,7 +135,12 @@ pulse_gen #(
     .BUS_CLK(BUS_CLK),
     .BUS_RST(BUS_RST),
     .BUS_ADD(BUS_ADD),
+`ifndef BASIL_SBUS
     .BUS_DATA(BUS_DATA[7:0]),
+`else
+    .BUS_DATA_IN(BUS_DATA_IN[7:0]),
+    .BUS_DATA_OUT(BUS_DATA_OUT_2[7:0]),
+`endif
     .BUS_RD(BUS_RD),
     .BUS_WR(BUS_WR),
 
@@ -112,7 +160,11 @@ clock_divider #(
 
 wire SCLK, SDI, SDO, SEN, SLD;
 
+`ifndef BASIL_SBUS
 spi #(
+`else
+spi_sbus #(
+`endif
     .BASEADDR(SPI_BASEADDR),
     .HIGHADDR(SPI_HIGHADDR),
     .ABUSWIDTH(ABUSWIDTH),
@@ -121,7 +173,12 @@ spi #(
     .BUS_CLK(BUS_CLK),
     .BUS_RST(BUS_RST),
     .BUS_ADD(BUS_ADD),
+`ifndef BASIL_SBUS
     .BUS_DATA(BUS_DATA[7:0]),
+`else
+    .BUS_DATA_IN(BUS_DATA_IN[7:0]),
+    .BUS_DATA_OUT(BUS_DATA_OUT_3[7:0]),
+`endif
     .BUS_RD(BUS_RD),
     .BUS_WR(BUS_WR),
 
@@ -141,7 +198,11 @@ wire FIFO_READ_SPI_RX;
 wire FIFO_EMPTY_SPI_RX;
 wire [31:0] FIFO_DATA_SPI_RX;
 
+`ifndef BASIL_SBUS
 fast_spi_rx #(
+`else
+fast_spi_rx_sbus #(
+`endif
     .BASEADDR(FAST_SR_AQ_BASEADDR),
     .HIGHADDR(FAST_SR_AQ_HIGHADDR),
     .ABUSWIDTH(ABUSWIDTH)
@@ -149,7 +210,12 @@ fast_spi_rx #(
     .BUS_CLK(BUS_CLK),
     .BUS_RST(BUS_RST),
     .BUS_ADD(BUS_ADD),
+`ifndef BASIL_SBUS
     .BUS_DATA(BUS_DATA[7:0]),
+`else
+    .BUS_DATA_IN(BUS_DATA_IN[7:0]),
+    .BUS_DATA_OUT(BUS_DATA_OUT_4[7:0]),
+`endif
     .BUS_RD(BUS_RD),
     .BUS_WR(BUS_WR),
 
@@ -168,7 +234,11 @@ assign FIFO_DATA = FIFO_DATA_SPI_RX;
 assign FIFO_EMPTY = FIFO_EMPTY_SPI_RX;
 assign FIFO_READ_SPI_RX = FIFO_READ;
 
+`ifndef BASIL_SBUS
 bram_fifo #(
+`else
+bram_fifo_sbus #(
+`endif
     .BASEADDR(FIFO_BASEADDR),
     .HIGHADDR(FIFO_HIGHADDR),
     .BASEADDR_DATA(FIFO_BASEADDR_DATA),
@@ -178,7 +248,12 @@ bram_fifo #(
     .BUS_CLK(BUS_CLK),
     .BUS_RST(BUS_RST),
     .BUS_ADD(BUS_ADD),
+`ifndef BASIL_SBUS
     .BUS_DATA(BUS_DATA),
+`else
+    .BUS_DATA_IN(BUS_DATA_IN),
+    .BUS_DATA_OUT(BUS_DATA_OUT_5),
+`endif
     .BUS_RD(BUS_RD),
     .BUS_WR(BUS_WR),
 
@@ -192,9 +267,11 @@ bram_fifo #(
     .FIFO_READ_ERROR()
 );
 
+`ifndef VERILATOR_SIM
 initial begin
     $dumpfile("spi.vcd");
     $dumpvars(0);
 end
+`endif
 
 endmodule
diff --git a/tests/test_SimSpi_sbus.py b/tests/test_SimSpi_sbus.py
new file mode 100644
index 000000000..b6cd9a220
--- /dev/null
+++ b/tests/test_SimSpi_sbus.py
@@ -0,0 +1,28 @@
+#
+# ------------------------------------------------------------
+# Copyright (c) All rights reserved
+# SiLab, Institute of Physics, University of Bonn
+# ------------------------------------------------------------
+#
+
+import unittest
+import sys
+
+from tests.test_SimSpi import TestSimSpi
+
+
+if __name__ == '__main__':
+    # https://stackoverflow.com/a/2081750
+    test_loader = unittest.TestLoader()
+    test_names = test_loader.getTestCaseNames(TestSimSpi)
+
+    suite = unittest.TestSuite()
+
+# TODO: add sbus versions of used modules
+#    for test_name in test_names:
+#        suite.addTest(TestSimSpi(testname=test_name, tb='test_SimSpi.v', bus_drv='basil.utils.sim.BasilSbusDriver', bus_split='sbus'))
+    for test_name in test_names:
+        suite.addTest(TestSimSpi(testname=test_name, tb='test_SimSpi.v', bus_drv='basil.utils.sim.BasilSbusDriver', bus_split='top'))
+
+    result = unittest.TextTestRunner().run(suite)
+    sys.exit(not result.wasSuccessful())